/**********************************************************************
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* Copyright: (C)2024 LingYun IoT System Studio
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* Author: GuoWenxue<guowenxue@gmail.com>
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*
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* Description: Winbond W25Q32 SPI norflash compatible driver on ISKBoard
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* Reference datasheet: <<W25Q256JV.pdf>>
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*
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* ChangeLog:
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* Version Date Author Description
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* V1.0.0 2024.08.29 GuoWenxue Release initial version
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*
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***********************************************************************/
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#include <stdio.h>
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#include <string.h>
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#include "main.h"
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#include "w25q.h"
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#include "spi.h"
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#define CONFIG_DEBUG_W25Q /* Enable W25Q norflash debug */
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#ifdef CONFIG_DEBUG_W25Q
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#define spinor_print(format,args...) printf(format, ##args)
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#else
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#define spinor_print(format,args...) do{} while(0)
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#endif
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__attribute__((unused)) static void dump_buf(const char *prompt, uint8_t *buf, uint32_t size)
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{
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int i;
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if(!buf)
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return ;
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if(prompt)
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printf("%s\r\n", prompt);
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for(i=0; i<size; i++)
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printf("%02x ", buf[i]);
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printf("\r\n");
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}
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#ifdef USE_FREERTOS
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#include "cmsis_os.h"
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#define mdelay(ms) osDelay(ms)
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#else
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#define mdelay(ms) HAL_Delay(ms)
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#endif
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/*+-----------------------+
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*| SPI API Functions |
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*+-----------------------+*/
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#define W25Q_SPI &hspi1
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#define W25Q_CS_PORT GPIOA
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#define W25Q_CS_PIN GPIO_PIN_4
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#define SPI_DUMMY_BYTE 0xA5
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void spinor_gpio_init(struct spi_info *spi)
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{
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GPIO_InitTypeDef GPIO_InitStruct = {0};
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/* Initial W25Q Norflash SPI CS pin */
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HAL_GPIO_WritePin(spi->cs_gpio, spi->cs_pin, GPIO_PIN_SET);
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GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
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GPIO_InitStruct.Pin = spi->cs_pin;
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HAL_GPIO_Init(spi->cs_gpio, &GPIO_InitStruct);
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}
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void spi_cs_enable(struct spi_info *spi)
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{
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HAL_GPIO_WritePin(spi->cs_gpio, spi->cs_pin, GPIO_PIN_RESET);
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}
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void spi_cs_disable(struct spi_info *spi)
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{
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HAL_GPIO_WritePin(spi->cs_gpio, spi->cs_pin, GPIO_PIN_SET);
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}
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uint8_t spi_xfer(struct spi_info *spi, uint8_t data)
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{
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uint8_t rxbyte;
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HAL_SPI_TransmitReceive(spi->hspi, &data, &rxbyte, 1, 100);
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return rxbyte;
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}
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void spi_send(struct spi_info *spi, uint8_t *data, uint32_t bytes)
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{
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HAL_SPI_Transmit(spi->hspi, data, bytes, 100);
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}
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void spi_recv(struct spi_info *spi, uint8_t *buf, uint32_t size)
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{
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HAL_SPI_Receive(spi->hspi, buf, size, 100);
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}
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#define SPI_INFO(_hspi, _cs_gpio, _cs_pin) {\
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.hspi = _hspi, \
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.cs_gpio = _cs_gpio, \
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.cs_pin = _cs_pin, \
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.select = spi_cs_enable, \
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.deselect = spi_cs_disable, \
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.xfer = spi_xfer, \
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.send = spi_send, \
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.recv = spi_recv, \
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}
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static struct spi_info spinor_spi = SPI_INFO(W25Q_SPI, W25Q_CS_PORT, W25Q_CS_PIN);
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/*+-----------------------+
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*| W25Q SPI Norflash ID |
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*+-----------------------+*/
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#define W25Q_PAGSIZE 256 /* 1Page=256B */
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#define W25Q_SECSIZE 4096 /* 1Sector=16Pages=4KB */
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#define W25Q_BLKSIZE 65536 /* 1Block=16Sector=64KB */
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#define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0]))
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/* JEDEC ID the 3rd bytes is the storage capacity */
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#pragma GCC diagnostic ignored "-Wshift-count-overflow"
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#define CAPCITY_ID(id) (1UL<<(id&0xFF))
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#define NOR_INFO(_name, _jedec_id) \
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.name = _name, \
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.jedec_id = _jedec_id, \
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.block_size = W25Q_BLKSIZE, \
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.sector_size= W25Q_SECSIZE, \
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.page_size = W25Q_PAGSIZE, \
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.capacity = CAPCITY_ID(_jedec_id), \
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.n_blocks = CAPCITY_ID(_jedec_id)/W25Q_BLKSIZE, \
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.n_sectors = CAPCITY_ID(_jedec_id)/W25Q_SECSIZE, \
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.n_pages = CAPCITY_ID(_jedec_id)/W25Q_PAGSIZE, \
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static struct flash_info spinor_ids[] = {
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{ NOR_INFO("W25Q512", 0xef4020) },
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{ NOR_INFO("W25Q256", 0xef4019) },
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{ NOR_INFO("W25Q128", 0xef4018) },
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{ NOR_INFO("W25Q64", 0xef4017) },
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{ NOR_INFO("W25Q32", 0xef4016) },
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{ NOR_INFO("W25Q16", 0xef4015) },
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{ NOR_INFO("W25Q80", 0xef4014) },
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{ NOR_INFO("W25Q40", 0xef4013) },
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{ NOR_INFO("W25Q20", 0xef4012) },
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{ NOR_INFO("W25Q10", 0xef4011) },
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};
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/*+-------------------------------+
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*| SPI Norflash HighLevel API |
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*+-------------------------------+*/
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/* SPI Norflash API test function */
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void spinor_test(void)
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{
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spinor_info_t spinor;
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int i;
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uint8_t buf[W25Q_PAGSIZE*2];
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if( spinor_init(&spinor) < 0 )
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return ;
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//spinor_erase_chip(&spinor);
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//spinor_erase_block(&spinor, 1, W25Q_BLKSIZE);
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spinor_erase_sector(&spinor, 1, W25Q_SECSIZE);
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memset(buf, 0, sizeof(buf));
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spinor_read(&spinor, 0, buf, sizeof(buf));
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dump_buf("<<<Read data after erase:\n", buf, sizeof(buf));
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/* Read/Write data test on address not page align */
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for(i=0; i<sizeof(buf); i++)
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buf[i] = i;
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spinor_write(&spinor, 8, buf, W25Q_PAGSIZE);
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memset(buf, 0, sizeof(buf));
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spinor_read(&spinor, 0, buf, sizeof(buf));
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dump_buf("<<<Read data after write:\n", buf, sizeof(buf));
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return ;
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}
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/* Initial SPI and detect the flash chip. */
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int spinor_init(struct spinor_info *spinor)
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{
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spinor->spi = &spinor_spi;
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spinor_gpio_init(spinor->spi);
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if( !spinor_detect_by_jedec(spinor) )
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return -1;
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printf("Norflash %s detected, capacity %lu KB, %lu blocks, %lu sectors, %lu pages.\r\n",
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spinor->flash->name, spinor->flash->capacity>>10,
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spinor->flash->n_blocks, spinor->flash->n_sectors, spinor->flash->n_pages);
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return 0;
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}
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/* Description: Erase whole flash chip.
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* Reference : P60, 8.2.32 Chip Erase (C7h / 60h)
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*/
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int spinor_erase_chip(struct spinor_info *spinor)
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{
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struct spi_info *spi = spinor->spi;
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while (spinor->lock == 1)
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mdelay(1);
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spinor->lock = 1;
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#ifdef CONFIG_DEBUG_W25Q
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uint32_t StartTime = HAL_GetTick();
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printf("Norflash EraseChip Begin...\r\n");
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#endif
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spinor_write_enable(spi);
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spi->select(spi);
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spi->xfer(spi, SPINOR_OP_CHIP_ERASE);
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spi->deselect(spi);
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spinor_WaitForWriteEnd(spi);
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#ifdef CONFIG_DEBUG_W25Q
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printf("Norflash EraseChip done after %ld ms!\r\n", HAL_GetTick() - StartTime);
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#endif
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mdelay(10);
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spinor->lock = 0;
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return 0;
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}
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/* Description: Erase blocks by 64KiB,
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* Reference : P59, 8.2.31 64KB Block Erase with 4-Byte Address (DCh)
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* @address is the erase start physical address, which can be not block alignment such as 0x10001.
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* @size is the erase size, which can be larger than a block such as 4097, and it will erase 2 blocks;
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*/
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int spinor_erase_block(struct spinor_info *spinor, uint32_t address, uint32_t size)
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{
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struct spi_info *spi = spinor->spi;
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struct flash_info *flash = spinor->flash;
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uint32_t block, first, last;
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uint32_t addr;
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while (spinor->lock == 1)
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mdelay(1);
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spinor->lock = 1;
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/* find first and last erase block */
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first = address / flash->block_size;
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last = (address+size-1) / flash->block_size;
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#ifdef CONFIG_DEBUG_W25Q
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printf("Norflash Erase %ld Bytes Block@0x%lx Begin...\r\n", size, address);
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uint32_t StartTime = HAL_GetTick();
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#endif
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/* start erase all the blocks */
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for( block=first; block<=last; block++)
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{
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addr = block * flash->sector_size;
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#ifdef CONFIG_DEBUG_W25Q
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printf("Norflash Erase Block@%lx ...\r\n", addr);
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#endif
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spinor_WaitForWriteEnd(spi);
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spinor_write_enable(spi);
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spi->select(spi);
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if (spinor->flash->n_blocks >= 512 ) /* larger than W25Q256 */
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{
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spi->xfer(spi, SPINOR_OP_BE_4K_4B);
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spi->xfer(spi, (addr & 0xFF000000) >> 24);
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}
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else
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{
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spi->xfer(spi, SPINOR_OP_BE_4K);
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}
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spi->xfer(spi, (addr & 0xFF0000) >> 16);
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spi->xfer(spi, (addr & 0xFF00) >> 8);
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spi->xfer(spi, addr & 0xFF);
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spi->deselect(spi);
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spinor_WaitForWriteEnd(spi);
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}
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#ifdef CONFIG_DEBUG_W25Q
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printf("Norflash EraseBlock@0x%lx done after %ld ms\r\n", address, HAL_GetTick() - StartTime);
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mdelay(100);
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#endif
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mdelay(1);
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spinor->lock = 0;
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return 0;
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}
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/* Description: Erase sectors by 4KiB
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* Reference : P56, 8.2.28 Sector Erase with 4-Byte Address (21h)
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* @address is the erase start physical address, which can be not sector alignment such as 0x1001.
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* @size is the erase size, which can be larger than a sector such as 4097, and it will erase 2 sectors;
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*/
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int spinor_erase_sector(struct spinor_info *spinor, uint32_t address, uint32_t size)
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{
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struct spi_info *spi = spinor->spi;
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struct flash_info *flash = spinor->flash;
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uint32_t sector, first, last;
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uint32_t addr;
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while (spinor->lock == 1)
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mdelay(1);
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spinor->lock = 1;
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/* find first and last erase sector */
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first = address / flash->sector_size;
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last = (address+size-1) / flash->sector_size;
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#ifdef CONFIG_DEBUG_W25Q
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uint32_t StartTime = HAL_GetTick();
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printf("Norflash Erase %ld Bytes Sector@0x%lx Begin...\r\n", size, address);
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#endif
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/* start erase all the sectors */
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for( sector=first; sector<=last; sector++)
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{
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addr = sector * flash->sector_size;
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#ifdef CONFIG_DEBUG_W25Q
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printf("Norflash Erase Sector@%lx ...\r\n", addr);
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#endif
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spinor_WaitForWriteEnd(spi);
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spinor_write_enable(spi);
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spi->select(spi);
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if (spinor->flash->n_blocks >= 512 ) /* larger than W25Q256 */
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{
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spi->xfer(spi, SPINOR_OP_SE_4B);
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spi->xfer(spi, (addr & 0xFF000000) >> 24);
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}
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else
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{
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spi->xfer(spi, SPINOR_OP_SE);
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}
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spi->xfer(spi, (addr & 0xFF0000) >> 16);
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spi->xfer(spi, (addr & 0xFF00) >> 8);
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spi->xfer(spi, addr & 0xFF);
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spi->deselect(spi);
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spinor_WaitForWriteEnd(spi);
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}
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#ifdef CONFIG_DEBUG_W25Q
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printf("Norflash EraseSector@0x%lx done after %ld ms\r\n", address, HAL_GetTick() - StartTime);
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#endif
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mdelay(1);
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spinor->lock = 0;
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return 0;
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}
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/* P32: 10.2.14 Page Program (02h) */
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int spinor_write(struct spinor_info *spinor, uint32_t address, uint8_t *data, uint32_t bytes)
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{
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struct spi_info *spi = spinor->spi;
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struct flash_info *flash = spinor->flash;
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uint32_t page, first, last;
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uint32_t addr, ofset, len;
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while (spinor->lock == 1)
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mdelay(1);
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spinor->lock = 1;
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/* find first and last write page */
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first = address / flash->page_size;
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last = (address+bytes-1) / flash->page_size;
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#ifdef CONFIG_DEBUG_W25Q
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uint32_t StartTime = HAL_GetTick();
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printf("Norflash Write %ld Bytes to addr@0x%lx Begin...\r\n", bytes, address);
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#endif
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/* address in page and offset in buffer */
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addr = address;
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ofset = 0;
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/* start write all the pages */
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for( page=first; page<=last; page++)
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{
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len = flash->page_size - (addr%flash->page_size);
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len = len > bytes ? bytes : len;
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#ifdef CONFIG_DEBUG_W25Q
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printf("Norflash write addr@0x%lx, %lu bytes\r\n", addr, len);
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#endif
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spinor_WaitForWriteEnd(spi);
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spinor_write_enable(spi);
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spi->select(spi);
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if (spinor->flash->n_blocks >= 512 )
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{
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spi->xfer(spi, SPINOR_OP_PP_4B);
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spi->xfer(spi, (addr & 0xFF000000) >> 24);
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}
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else
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{
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spi->xfer(spi, SPINOR_OP_PP);
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}
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spi->xfer(spi, (addr & 0xFF0000) >> 16);
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spi->xfer(spi, (addr & 0xFF00) >> 8);
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spi->xfer(spi, addr & 0xFF);
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/* send data */
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spi->send(spi, data+ofset, len);
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spi->deselect(spi);
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spinor_WaitForWriteEnd(spi);
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addr += len;
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ofset += len;
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bytes -= len;
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}
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#ifdef CONFIG_DEBUG_W25Q
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printf("Norflash WriteByte@0x%lx done after %ld ms\r\n", address, HAL_GetTick() - StartTime);
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#endif
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mdelay(1);
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spinor->lock = 0;
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return 0;
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}
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/* Description: The Fast Read instruction can read the entire memory chip.
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* Reference : P41, 8.2.13 Fast Read with 4-Byte Address (0Ch)
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* @address is the read start physical address, which can be not page alignment such as 0x101.
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* @size is the read size, which can be larger than a page such as 257, and it will read 2 pages;
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*/
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int spinor_read(struct spinor_info *spinor, uint32_t address, uint8_t *buf, uint32_t bytes)
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{
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struct spi_info *spi = spinor->spi;
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while (spinor->lock == 1)
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mdelay(1);
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spinor->lock = 1;
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#ifdef CONFIG_DEBUG_W25Q
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uint32_t StartTime = HAL_GetTick();
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printf("Norflash Read %ld Bytes from addr@0x%lx Begin...\r\n", bytes, address);
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#endif
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spi->select(spi);
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/* send instruction and address */
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if (spinor->flash->n_blocks >= 512 )
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{
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spi->xfer(spi, SPINOR_OP_READ_FAST_4B);
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spi->xfer(spi, (address & 0xFF000000) >> 24);
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}
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else
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{
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spi->xfer(spi, SPINOR_OP_READ_FAST);
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}
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spi->xfer(spi, (address & 0xFF0000) >> 16);
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spi->xfer(spi, (address & 0xFF00) >> 8);
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spi->xfer(spi, address & 0xFF);
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/* read data */
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spi->xfer(spi, SPI_DUMMY_BYTE);
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spi->recv(spi, buf, bytes);
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spi->deselect(spi);
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#ifdef CONFIG_DEBUG_W25Q
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printf("Norflash ReadBytes@0x%lx done after %ld ms\r\n", address, HAL_GetTick() - StartTime);
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#endif
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spinor->lock = 0;
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return 0;
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}
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/*+-------------------------------+
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*| SPI Norflash LowLevel API |
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*+-------------------------------+*/
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/* Detect the norflash by JEDEC ID */
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int spinor_detect_by_jedec(struct spinor_info *spinor)
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{
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uint32_t jedec_id;
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int i, found = 0;
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jedec_id = spinor_read_jedecid(spinor->spi);
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for(i=0; i<ARRAY_SIZE(spinor_ids); i++)
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{
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if(spinor_ids[i].jedec_id == jedec_id)
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{
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found = 1;
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spinor->flash = &spinor_ids[i];
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break;
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}
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}
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printf("Detect JEDEC ID[0x%lx], Norflash %s found\r\n", jedec_id, found?spinor->flash->name:"not");
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return found;
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}
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/* Description: Read the chipset UNIQUE ID.
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* Reference : P68, 8.2.40 Read Unique ID Number (4Bh)
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*/
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int spinor_read_uniqid(struct spi_info *spi, uint8_t *uniq_id)
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{
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uint8_t i;
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uint8_t id;
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if( !uniq_id )
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return -1;
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spi->select(spi);
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spi->xfer(spi, SPINOR_OP_RDUID);
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/* Skip 4 bytes dummy bytes */
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for (i=0; i<4; i++)
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spi->xfer(spi, SPI_DUMMY_BYTE);
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for (i=0; i<8; i++)
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{
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id = spi->xfer(spi, SPI_DUMMY_BYTE);
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uniq_id[i] = id;
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}
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spi->deselect(spi);
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return 0;
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}
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/* Description: Read the chipset JEDEC ID.
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* Reference : P69, 8.2.41 Read JEDEC ID (9Fh)
|
*/
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uint32_t spinor_read_jedecid(struct spi_info *spi)
|
{
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uint32_t jedec_id = 0x0;
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uint8_t id[3];
|
|
spi->select(spi);
|
spi->xfer(spi, SPINOR_OP_RDID);
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id[0] = spi->xfer(spi, SPI_DUMMY_BYTE); /* Vendor ID */
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id[1] = spi->xfer(spi, SPI_DUMMY_BYTE); /* Memory Type */
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id[2] = spi->xfer(spi, SPI_DUMMY_BYTE); /* Storage Capacity */
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spi->deselect(spi);
|
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jedec_id = (id[0] << 16) | (id[1] << 8) | id[2];
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return jedec_id;
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}
|
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/* Description: Write Enable
|
* Reference : P31, 8.2.1 Write Enable (06h)
|
*/
|
void spinor_write_enable(struct spi_info *spi)
|
{
|
spi->select(spi);
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spi->xfer(spi, SPINOR_OP_WREN);
|
spi->deselect(spi);
|
|
mdelay(1);
|
}
|
|
/* Description: Write Disable
|
* Reference : P32, 8.2.3 Write Disable (04h)
|
*/
|
void spinor_write_disable(struct spi_info *spi)
|
{
|
spi->select(spi);
|
spi->xfer(spi, SPINOR_OP_WRDI);
|
spi->deselect(spi);
|
|
mdelay(1);
|
}
|
|
/* Description: Read Status Register
|
* Reference : P32, 8.2.4 Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h)
|
*/
|
uint8_t spinor_read_status_reg(struct spi_info *spi, uint8_t reg)
|
{
|
uint8_t value = 0;
|
uint8_t cmd[REG_STATUS_MAX] = { SPINOR_OP_RDSR1 , SPINOR_OP_RDSR2, SPINOR_OP_RDSR3 }; /* Status Register 1~3 */
|
|
if( reg>= REG_STATUS_MAX )
|
return 0xFF;
|
|
spi->select(spi);
|
spi->xfer(spi, cmd[reg]);
|
value = spi->xfer(spi, SPI_DUMMY_BYTE);
|
spi->deselect(spi);
|
|
return value;
|
}
|
|
/* Description: Write Status Register
|
* Reference : P33, 8.2.5 Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h)
|
*/
|
void spinor_write_status_reg(struct spi_info *spi, uint8_t reg, uint8_t value)
|
{
|
uint8_t cmd[REG_STATUS_MAX] = { SPINOR_OP_WRSR1 , SPINOR_OP_WRSR2, SPINOR_OP_WRSR3 }; /* Status Register 1~3 */
|
|
if( reg>= REG_STATUS_MAX )
|
return ;
|
|
spi->select(spi);
|
spi->xfer(spi, cmd[reg]);
|
value = spi->xfer(spi, value);
|
spi->deselect(spi);
|
}
|
|
/* Description: Wait flash program/erase finished by read Status Register for BUSY bit
|
* Reference : P15, 7.1 Status Registers
|
*/
|
void spinor_WaitForWriteEnd(struct spi_info *spi)
|
{
|
uint8_t value = 0;
|
mdelay(1);
|
|
spi->select(spi);
|
spi->xfer(spi, SPINOR_OP_RDSR1);
|
|
do
|
{
|
value = spi->xfer(spi, SPI_DUMMY_BYTE);
|
mdelay(1);
|
} while ((value & 0x01) == 0x01);
|
|
spi->deselect(spi);
|
}
|
