/*
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* Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/* ----------------------------------------------------------------------
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* Project: CMSIS NN Library
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* Title: arm_q7_to_q15_reordered_no_shift.c
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* Description: Converts the elements of the Q7 vector to reordered Q15 vector without left-shift
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*
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* $Date: 17. January 2018
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* $Revision: V.1.0.0
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*
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* Target Processor: Cortex-M cores
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*
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* -------------------------------------------------------------------- */
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#include "arm_nnsupportfunctions.h"
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/**
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* @ingroup groupSupport
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*/
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/**
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* @addtogroup nndata_convert
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* @{
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*/
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/**
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* @brief Converts the elements of the Q7 vector to reordered Q15 vector without left-shift
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* @param[in] *pSrc points to the Q7 input vector
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* @param[out] *pDst points to the Q15 output vector
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* @param[in] blockSize length of the input vector
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* @return none.
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*
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* @details
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*
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* This function does the q7 to q15 expansion with re-ordering
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*
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* <pre>
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* | A1 | A2 | A3 | A4 |
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*
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* 0 7 8 15 16 23 24 31
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* </pre>
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*
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* is converted into:
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*
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* <pre>
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* | A1 | A3 | and | A2 | A4 |
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*
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* 0 15 16 31 0 15 16 31
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* </pre>
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*
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*
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* This looks strange but is natural considering how sign-extension is done at
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* assembly level.
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*
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* The expansion of other other oprand will follow the same rule so that the end
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* results are the same.
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*
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* The tail (i.e., last (N % 4) elements) will still be in original order.
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*
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*/
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void arm_q7_to_q15_reordered_no_shift(const q7_t * pSrc, q15_t * pDst, uint32_t blockSize)
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{
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const q7_t *pIn = pSrc; /* Src pointer */
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uint32_t blkCnt; /* loop counter */
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#ifndef ARM_MATH_CM0_FAMILY
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q31_t in;
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q31_t in1, in2;
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/* Run the below code for Cortex-M4 and Cortex-M3 */
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/*loop Unrolling */
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blkCnt = blockSize >> 2u;
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/* First part of the processing with loop unrolling. Compute 4 outputs at a time.
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** a second loop below computes the remaining 1 to 3 samples. */
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while (blkCnt > 0u)
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{
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/* C = (q15_t) A << 8 */
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/* convert from q7 to q15 and then store the results in the destination buffer */
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in = *__SIMD32(pIn)++;
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/* rotatate in by 8 and extend two q7_t values to q15_t values */
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in1 = __SXTB16(__ROR(in, 8));
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/* extend remainig two q7_t values to q15_t values */
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in2 = __SXTB16(in);
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#ifndef ARM_MATH_BIG_ENDIAN
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*__SIMD32(pDst)++ = in2;
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*__SIMD32(pDst)++ = in1;
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#else
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*__SIMD32(pDst)++ = in1;
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*__SIMD32(pDst)++ = in2;
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#endif
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/* Decrement the loop counter */
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blkCnt--;
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}
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/* If the blockSize is not a multiple of 4, compute any remaining output samples here.
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** No loop unrolling is used. */
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blkCnt = blockSize % 0x4u;
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#else
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/* Run the below code for Cortex-M0 */
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/* Loop over blockSize number of values */
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blkCnt = blockSize;
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#endif /* #ifndef ARM_MATH_CM0_FAMILY */
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while (blkCnt > 0u)
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{
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/* C = (q15_t) A << 8 */
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/* convert from q7 to q15 and then store the results in the destination buffer */
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*pDst++ = (q15_t) * pIn++;
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/* Decrement the loop counter */
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blkCnt--;
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}
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}
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/**
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* @} end of q7_to_x group
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*/
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