/*
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* Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/* ----------------------------------------------------------------------
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* Project: CMSIS NN Library
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* Title: arm_convolve_HWC_q15_basic.c
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* Description: Q15 version of convolution
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*
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* $Date: 17. January 2018
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* $Revision: V.1.0.0
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*
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* Target Processor: Cortex-M cores
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*
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* -------------------------------------------------------------------- */
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#include "arm_math.h"
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#include "arm_nnfunctions.h"
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/**
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* @ingroup groupNN
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*/
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/**
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* @addtogroup NNConv
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* @{
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*/
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/**
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* @brief Basic Q15 convolution function
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* @param[in] Im_in pointer to input tensor
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* @param[in] dim_im_in input tensor dimention
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* @param[in] ch_im_in number of input tensor channels
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* @param[in] wt pointer to kernel weights
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* @param[in] ch_im_out number of filters, i.e., output tensor channels
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* @param[in] dim_kernel filter kernel size
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* @param[in] padding padding sizes
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* @param[in] stride convolution stride
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* @param[in] bias pointer to bias
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* @param[in] bias_shift amount of left-shift for bias
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* @param[in] out_shift amount of right-shift for output
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* @param[in,out] Im_out pointer to output tensor
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* @param[in] dim_im_out output tensor dimension
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* @param[in,out] bufferA pointer to buffer space for input
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* @param[in,out] bufferB pointer to buffer space for output
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* @return The function returns <code>ARM_MATH_SUCCESS</code>
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*
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* @details
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*
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* <b>Buffer size:</b>
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*
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* bufferA size: ch_im_in*dim_kernel*dim_kernel
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*
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* bufferB size: 0
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*
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* This basic version is designed to work for any input tensor and weight
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* dimension.
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*/
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arm_status
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arm_convolve_HWC_q15_basic(const q15_t * Im_in,
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const uint16_t dim_im_in,
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const uint16_t ch_im_in,
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const q15_t * wt,
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const uint16_t ch_im_out,
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const uint16_t dim_kernel,
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const uint16_t padding,
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const uint16_t stride,
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const q15_t * bias,
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const uint16_t bias_shift,
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const uint16_t out_shift,
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q15_t * Im_out,
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const uint16_t dim_im_out,
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q15_t * bufferA,
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q7_t * bufferB)
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{
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#if defined (ARM_MATH_DSP)
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/* Run the following code for Cortex-M4 and Cortex-M7 */
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int16_t i_out_y, i_out_x, i_ker_y, i_ker_x;
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uint16_t im2col_out_pixel_index = 0;
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q15_t *pBuffer = bufferA;
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q15_t *pOut = Im_out;
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q15_t *im_buffer = bufferA;
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const q15_t *pA;
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int i;
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/* This part implements the im2col function */
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for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++)
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{
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for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++)
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{
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for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++)
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{
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for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++)
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{
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if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in)
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{
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/* Filling 0 for out-of-bound paddings */
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/* arm_fill_q15(0, pBuffer, ch_im_in); */
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memset(pBuffer, 0, sizeof(q15_t)*ch_im_in);
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} else
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{
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/* arm_copy_q15((q15_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); */
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memcpy(pBuffer, (q15_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, sizeof(q15_t)*ch_im_in);
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}
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pBuffer += ch_im_in;
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}
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}
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pA = wt;
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for (i = 0; i < ch_im_out; i++)
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{
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q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
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q15_t *pB = im_buffer;
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uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 2;
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while (colCnt)
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{
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q31_t inA1 = *__SIMD32(pA)++;
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q31_t inB1 = *__SIMD32(pB)++;
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q31_t inA2 = *__SIMD32(pA)++;
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q31_t inB2 = *__SIMD32(pB)++;
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sum = __SMLAD(inA1, inB1, sum);
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sum = __SMLAD(inA2, inB2, sum);
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colCnt--;
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}
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colCnt = ch_im_in * dim_kernel * dim_kernel & 0x3;
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while (colCnt)
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{
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q15_t inA1 = *pA++;
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q15_t inB1 = *pB++;
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sum += inA1 * inB1;
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colCnt--;
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}
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*pOut = (q15_t) __SSAT((sum >> out_shift), 16);
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pOut++;
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}
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/* counter reset */
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pBuffer = im_buffer;
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im2col_out_pixel_index++;
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}
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}
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#else
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/* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
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uint16_t i, j, k, l, m, n;
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int conv_out;
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signed char in_row, in_col;
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for (i = 0; i < ch_im_out; i++)
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{
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for (j = 0; j < dim_im_out; j++)
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{
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for (k = 0; k < dim_im_out; k++)
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{
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conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
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for (m = 0; m < dim_kernel; m++)
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{
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for (n = 0; n < dim_kernel; n++)
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{
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in_row = stride * j + m - padding;
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in_col = stride * k + n - padding;
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if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in)
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{
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for (l = 0; l < ch_im_in; l++)
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{
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conv_out +=
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Im_in[(in_row * dim_im_in + in_col) * ch_im_in +
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l] * wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel +
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n) * ch_im_in + l];
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}
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}
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}
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}
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Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q15_t) __SSAT((conv_out >> out_shift), 16);
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}
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}
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}
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#endif /* ARM_MATH_DSP */
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/* Return to application */
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return ARM_MATH_SUCCESS;
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}
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/**
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* @} end of NNConv group
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*/
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