/*
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* Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/* ----------------------------------------------------------------------
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* Project: CMSIS NN Library
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* Title: arm_depthwise_separable_conv_HWC_q7_nonsquare.c
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* Description: Q7 depthwise separable convolution function (non-square shape)
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*
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* $Date: 17. January 2018
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* $Revision: V.1.0.0
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*
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* Target Processor: Cortex-M cores
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*
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* -------------------------------------------------------------------- */
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#include "arm_math.h"
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#include "arm_nnfunctions.h"
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/**
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* @ingroup groupNN
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*/
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/**
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* @addtogroup NNConv
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* @{
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*/
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/**
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* @brief Q7 depthwise separable convolution function (non-square shape)
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* @param[in] Im_in pointer to input tensor
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* @param[in] dim_im_in_x input tensor dimention x
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* @param[in] dim_im_in_y input tensor dimention y
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* @param[in] ch_im_in number of input tensor channels
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* @param[in] wt pointer to kernel weights
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* @param[in] ch_im_out number of filters, i.e., output tensor channels
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* @param[in] dim_kernel_x filter kernel size x
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* @param[in] dim_kernel_y filter kernel size y
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* @param[in] padding_x padding sizes x
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* @param[in] padding_y padding sizes y
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* @param[in] stride_x convolution stride x
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* @param[in] stride_y convolution stride y
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* @param[in] bias pointer to bias
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* @param[in] bias_shift amount of left-shift for bias
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* @param[in] out_shift amount of right-shift for output
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* @param[in,out] Im_out pointer to output tensor
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* @param[in] dim_im_out_x output tensor dimension x
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* @param[in] dim_im_out_y output tensor dimension y
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* @param[in,out] bufferA pointer to buffer space for input
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* @param[in,out] bufferB pointer to buffer space for output
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* @return The function returns either
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* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
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*
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* This function is the version with full list of optimization tricks, but with
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* some contraints:
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* ch_im_in is multiple of 2
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* ch_im_out is multiple of 2
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*/
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arm_status arm_depthwise_separable_conv_HWC_q7_nonsquare(const q7_t * Im_in,
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const uint16_t dim_im_in_x,
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const uint16_t dim_im_in_y,
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const uint16_t ch_im_in,
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const q7_t * wt,
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const uint16_t ch_im_out,
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const uint16_t dim_kernel_x,
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const uint16_t dim_kernel_y,
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const uint16_t padding_x,
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const uint16_t padding_y,
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const uint16_t stride_x,
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const uint16_t stride_y,
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const q7_t * bias,
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const uint16_t bias_shift,
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const uint16_t out_shift,
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q7_t * Im_out,
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const uint16_t dim_im_out_x,
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const uint16_t dim_im_out_y,
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q15_t * bufferA,
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q7_t * bufferB)
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{
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#if defined (ARM_MATH_DSP)
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/* Run the following code for Cortex-M4 and Cortex-M7 */
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/*
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* Implementation:
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* There are 3 nested loop here:
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* Inner loop: calculate each output value with MAC instruction over an accumulator
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* Mid loop: loop over different output channel
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* Outer loop: loop over different output (x, y)
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*
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*/
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int16_t i_out_y, i_out_x;
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int16_t i_ker_y, i_ker_x;
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q7_t *colBuffer = (q7_t *) bufferA;
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q7_t *pBuffer = colBuffer;
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const q7_t *pBias = bias;
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q7_t *pOut = Im_out;
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uint16_t rowCnt;
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uint16_t row_shift;
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/* do some checking here, basically ch_im_in == ch_im_out */
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if (ch_im_in != ch_im_out)
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{
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return ARM_MATH_SIZE_MISMATCH;
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}
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for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++)
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{
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for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++)
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{
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/* we first do im2col here */
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for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y;
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i_ker_y++)
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{
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for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x;
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i_ker_x++)
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{
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if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x)
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{
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/* arm_fill_q7(0, pBuffer, ch_im_in); */
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memset(pBuffer, 0, ch_im_in);
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} else
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{
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/* arm_copy_q7((q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, ch_im_in); */
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memcpy(pBuffer, (q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, ch_im_in);
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}
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pBuffer += ch_im_in;
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}
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}
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/* we will do the computation here for each channel */
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rowCnt = ch_im_out >> 2;
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row_shift = 0;
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pBias = bias;
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while (rowCnt)
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{
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q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
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q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
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q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
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q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
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uint16_t colCnt = (dim_kernel_x * dim_kernel_y) >> 1;
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q7_t *pB = colBuffer + row_shift;
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const q7_t *pA = wt + row_shift;
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row_shift += 4;
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#ifdef USE_INTRINSIC
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#ifndef ARM_MATH_BIG_ENDIAN
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while (colCnt)
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{
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q31_t inA1, inA2, inB1, inB2, opA, opB;
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inB1 = *__SIMD32(pB);
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pB += ch_im_in;
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opB = *__SIMD32(pB);
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pB += ch_im_in;
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inB2 = __PKHTB(opB, inB1, 16);
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inB1 = __PKHBT(inB1, opB, 16);
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inA1 = *__SIMD32(pA);
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pA += ch_im_in;
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opB = *__SIMD32(pA);
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pA += ch_im_in;
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inA2 = __PKHTB(opB, inA1, 16);
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inA1 = __PKHBT(inA1, opB, 16);
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opA = __SXTB16(inA1);
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opB = __SXTB16(inB1);
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sum = __SMLAD(opA, opB, sum);
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opA = __SXTB16(__ROR(inA1, 8));
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opB = __SXTB16(__ROR(inB1, 8));
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sum2 = __SMLAD(opA, opB, sum2);
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opA = __SXTB16(inA2);
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opB = __SXTB16(inB2);
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sum3 = __SMLAD(opA, opB, sum3);
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opA = __SXTB16(__ROR(inA2, 8));
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opB = __SXTB16(__ROR(inB2, 8));
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sum4 = __SMLAD(opA, opB, sum4);
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colCnt--;
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}
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#else
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while (colCnt)
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{
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q31_t inA1, inA2, inB1, inB2, opA, opB;
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inB1 = *__SIMD32(pB);
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pB += ch_im_in;
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opB = *__SIMD32(pB);
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pB += ch_im_in;
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inB2 = __PKHBT(opB, inB1, 16);
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inB1 = __PKHTB(inB1, opB, 16);
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inA1 = *__SIMD32(pA);
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pA += ch_im_in;
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opB = *__SIMD32(pA);
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pA += ch_im_in;
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inA2 = __PKHBT(opB, inA1, 16);
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inA1 = __PKHTB(inA1, opB, 16);
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opA = __SXTB16(inA1);
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opB = __SXTB16(inB1);
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sum2 = __SMLAD(opA, opB, sum2);
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opA = __SXTB16(__ROR(inA1, 8));
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opB = __SXTB16(__ROR(inB1, 8));
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sum = __SMLAD(opA, opB, sum);
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opA = __SXTB16(inA2);
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opB = __SXTB16(inB2);
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sum4 = __SMLAD(opA, opB, sum4);
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opA = __SXTB16(__ROR(inA2, 8));
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opB = __SXTB16(__ROR(inB2, 8));
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sum3 = __SMLAD(opA, opB, sum3);
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colCnt--;
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}
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#endif /* ARM_MATH_BIG_ENDIAN */
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#else
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#ifndef ARM_MATH_BIG_ENDIAN
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// r0 r1 r2 r3 r4 r5
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// inA1, inA2, inB1, inB2, opA, opB
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asm volatile ("COL_LOOP:\n"
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"ldr.w r2, [%[pB], #0]\n"
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"add.w %[pB], %[pB], %[ch_im_in]\n"
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"ldr.w r5, [%[pB], #0]\n"
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"add.w %[pB], %[pB], %[ch_im_in]\n"
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"pkhtb r3, r5, r2, ASR #16\n"
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"pkhbt r2, r2, r5, LSL #16\n"
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"ldr.w r0, [%[pA], #0]\n"
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"add.w %[pA], %[pA], %[ch_im_in]\n"
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"ldr.w r5, [%[pA], #0]\n"
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"add.w %[pA], %[pA], %[ch_im_in]\n"
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"pkhtb r1, r5, r0, ASR #16\n"
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"pkhbt r0, r0, r5, LSL #16\n"
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"sxtb16 r4, r0\n"
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"sxtb16 r5, r2\n"
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"smlad %[sum], r4, r5, %[sum]\n"
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"mov.w r4, r0, ror #8\n"
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"mov.w r5, r2, ror #8\n"
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"sxtb16 r4, r4\n"
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"sxtb16 r5, r5\n"
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"smlad %[sum2], r4, r5, %[sum2]\n"
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"sxtb16 r4, r1\n"
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"sxtb16 r5, r3\n"
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"smlad %[sum3], r4, r5, %[sum3]\n"
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"mov.w r4, r1, ror #8\n"
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"mov.w r5, r3, ror #8\n"
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"sxtb16 r4, r4\n"
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"sxtb16 r5, r5\n"
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"smlad %[sum4], r4, r5, %[sum4]\n"
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"subs %[colCnt], #1\n"
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"bne COL_LOOP\n":[sum] "+r"(sum),[sum2] "+r"(sum2),[sum3] "+r"(sum3),
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[sum4] "+r"(sum4),[pB] "+r"(pB),[pA] "+r"(pA):[colCnt] "r"(colCnt),
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[ch_im_in] "r"(ch_im_in):"r0", "r1", "r2", "r3", "r4", "r5");
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#else
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// r0 r1 r2 r3 r4 r5
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// inA1, inA2, inB1, inB2, opA, opB
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asm volatile ("COL_LOOP:\n"
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"ldr.w r2, [%[pB], #0]\n"
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"add.w %[pB], %[pB], %[ch_im_in]\n"
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"ldr.w r5, [%[pB], #0]\n"
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"add.w %[pB], %[pB], %[ch_im_in]\n"
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"pkhbt r3, r5, r2, LSL #16\n"
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"pkhtb r2, r2, r5, ASR #16\n"
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"ldr.w r0, [%[pA], #0]\n"
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"add.w %[pA], %[pA], %[ch_im_in]\n"
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"ldr.w r5, [%[pA], #0]\n"
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"add.w %[pA], %[pA], %[ch_im_in]\n"
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"pkhbt r1, r5, r0, LSL #16\n"
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"pkhtb r0, r0, r5, ASR #16\n"
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"sxtb16 r4, r0\n"
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"sxtb16 r5, r2\n"
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"smlad %[sum2], r4, r5, %[sum2]\n"
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"mov.w r4, r0, ror #8\n"
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"mov.w r5, r2, ror #8\n"
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"sxtb16 r4, r4\n"
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"sxtb16 r5, r5\n"
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"smlad %[sum], r4, r5, %[sum]\n"
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"sxtb16 r4, r1\n"
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"sxtb16 r5, r3\n"
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"smlad %[sum4], r4, r5, %[sum4]\n"
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"mov.w r4, r1, ror #8\n"
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"mov.w r5, r3, ror #8\n"
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"sxtb16 r4, r4\n"
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"sxtb16 r5, r5\n"
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"smlad %[sum3], r4, r5, %[sum3]\n"
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"subs %[colCnt], #1\n"
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"bne COL_LOOP\n":[sum] "+r"(sum),[sum2] "+r"(sum2),[sum3] "+r"(sum3),
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[sum4] "+r"(sum4),[pB] "+r"(pB),[pA] "+r"(pA):[colCnt] "r"(colCnt),
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[ch_im_in] "r"(ch_im_in):"r0", "r1", "r2", "r3", "r4", "r5");
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#endif /*ARM_MATH_BIG_ENDIAN */
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#endif /* USE_INTRINSIC */
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colCnt = (dim_kernel_x * dim_kernel_y) & 0x1;
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while (colCnt)
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{
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union arm_nnword inA, inB;
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inA.word = *__SIMD32(pA);
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pA += ch_im_in;
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inB.word = *__SIMD32(pB);
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pB += ch_im_in;
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sum += inA.bytes[0] * inB.bytes[0];
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sum2 += inA.bytes[1] * inB.bytes[1];
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sum3 += inA.bytes[2] * inB.bytes[2];
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sum4 += inA.bytes[3] * inB.bytes[3];
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colCnt--;
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}
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*pOut++ = (q7_t) __SSAT((sum >> out_shift), 8);
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*pOut++ = (q7_t) __SSAT((sum2 >> out_shift), 8);
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*pOut++ = (q7_t) __SSAT((sum3 >> out_shift), 8);
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*pOut++ = (q7_t) __SSAT((sum4 >> out_shift), 8);
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rowCnt--;
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}
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rowCnt = ch_im_out & 0x3;
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while (rowCnt)
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{
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q7_t *pB = colBuffer + row_shift;
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const q7_t *pA = wt + row_shift;
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q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
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uint16_t colCnt = (dim_kernel_x * dim_kernel_y);
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row_shift += 1;
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while (colCnt)
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{
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q7_t A1 = *pA;
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q7_t B1 = *pB;
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pA += ch_im_in;
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pB += ch_im_in;
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sum += A1 * B1;
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colCnt--;
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}
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*pOut++ = (q7_t) __SSAT((sum >> out_shift), 8);
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rowCnt--;
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}
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// clear counter and pointers
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pBuffer = colBuffer;
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}
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}
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#else
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/* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
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int i_out_y, i_out_x, i_ch_out;
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int i_ker_y, i_ker_x;
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/* do some checking here, basically ch_im_in == ch_im_out */
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if (ch_im_in != ch_im_out)
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{
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return ARM_MATH_SIZE_MISMATCH;
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}
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for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++)
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{
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for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++)
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{
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for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++)
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{
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// for each output
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int conv_out = ((q31_t)(bias[i_ch_out]) << bias_shift) + NN_ROUND(out_shift);
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for (i_ker_y = 0; i_ker_y < dim_kernel_y; i_ker_y++)
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{
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for (i_ker_x = 0; i_ker_x < dim_kernel_x; i_ker_x++)
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{
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int in_row = stride_y * i_out_y + i_ker_y - padding_y;
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int in_col = stride_x * i_out_x + i_ker_x - padding_x;
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if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x)
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{
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conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + i_ch_out] *
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wt[(i_ker_y * dim_kernel_x + i_ker_x) * ch_im_out + i_ch_out];
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}
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}
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}
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Im_out[(i_out_y * dim_im_out_x + i_out_x) * ch_im_out + i_ch_out] =
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(q7_t) __SSAT((conv_out >> out_shift), 8);
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}
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}
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}
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#endif /* ARM_MATH_DSP */
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/* Return to application */
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return ARM_MATH_SUCCESS;
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}
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/**
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* @} end of NNConv group
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*/
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