/*
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* Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/* ----------------------------------------------------------------------
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* Project: CMSIS NN Library
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* Title: arm_nn_mult_q15.c
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* Description: Q15 vector multiplication with variable output shifts
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*
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* $Date: 13. July 2018
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* $Revision: V.1.0.0
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*
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* Target Processor: Cortex-M cores
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*
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* -------------------------------------------------------------------- */
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#include "arm_nnfunctions.h"
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/**
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* @ingroup groupSupport
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*/
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/**
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* @addtogroup NNBasicMath
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* @{
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*/
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/**
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* @brief Q7 vector multiplication with variable output shifts
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* @param[in] *pSrcA pointer to the first input vector
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* @param[in] *pSrcB pointer to the second input vector
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* @param[out] *pDst pointer to the output vector
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* @param[in] out_shift amount of right-shift for output
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* @param[in] blockSize number of samples in each vector
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* @return none.
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*
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* <b>Scaling and Overflow Behavior:</b>
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* \par
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* The function uses saturating arithmetic.
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* Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
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*/
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void arm_nn_mult_q15(
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q15_t * pSrcA,
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q15_t * pSrcB,
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q15_t * pDst,
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const uint16_t out_shift,
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uint32_t blockSize)
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{
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uint32_t blkCnt; /* loop counters */
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#if defined (ARM_MATH_DSP)
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/* Run the below code for Cortex-M4 and Cortex-M3 */
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q31_t inA1, inA2, inB1, inB2; /* temporary input variables */
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q15_t out1, out2, out3, out4; /* temporary output variables */
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q31_t mul1, mul2, mul3, mul4; /* temporary variables */
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/* loop Unrolling */
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blkCnt = blockSize >> 2U;
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/* First part of the processing with loop unrolling. Compute 4 outputs at a time.
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** a second loop below computes the remaining 1 to 3 samples. */
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while (blkCnt > 0U)
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{
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/* read two samples at a time from sourceA */
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inA1 = *__SIMD32(pSrcA)++;
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/* read two samples at a time from sourceB */
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inB1 = *__SIMD32(pSrcB)++;
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/* read two samples at a time from sourceA */
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inA2 = *__SIMD32(pSrcA)++;
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/* read two samples at a time from sourceB */
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inB2 = *__SIMD32(pSrcB)++;
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/* multiply mul = sourceA * sourceB */
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mul1 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
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mul2 = (q31_t) ((q15_t) inA1 * (q15_t) inB1);
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mul3 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB2 >> 16));
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mul4 = (q31_t) ((q15_t) inA2 * (q15_t) inB2);
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/* saturate result to 16 bit */
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out1 = (q15_t) __SSAT((mul1 + NN_ROUND(out_shift)) >> out_shift, 16);
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out2 = (q15_t) __SSAT((mul2 + NN_ROUND(out_shift)) >> out_shift, 16);
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out3 = (q15_t) __SSAT((mul3 + NN_ROUND(out_shift)) >> out_shift, 16);
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out4 = (q15_t) __SSAT((mul4 + NN_ROUND(out_shift)) >> out_shift, 16);
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/* store the result */
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#ifndef ARM_MATH_BIG_ENDIAN
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*__SIMD32(pDst)++ = __PKHBT(out2, out1, 16);
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*__SIMD32(pDst)++ = __PKHBT(out4, out3, 16);
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#else
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*__SIMD32(pDst)++ = __PKHBT(out2, out1, 16);
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*__SIMD32(pDst)++ = __PKHBT(out4, out3, 16);
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#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
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/* Decrement the blockSize loop counter */
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blkCnt--;
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}
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/* If the blockSize is not a multiple of 4, compute any remaining output samples here.
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** No loop unrolling is used. */
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blkCnt = blockSize % 0x4U;
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#else
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/* Run the below code for Cortex-M0 */
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/* Initialize blkCnt with number of samples */
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blkCnt = blockSize;
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#endif /* #if defined (ARM_MATH_DSP) */
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while (blkCnt > 0U)
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{
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/* C = A * B */
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/* Multiply the inputs and store the result in the destination buffer */
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*pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 16);
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/* Decrement the blockSize loop counter */
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blkCnt--;
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}
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}
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/**
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* @} end of NNBasicMath group
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*/
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