/*
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* linux/include/linux/mtd/nand.h
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*
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* Copyright (c) 2000 David Woodhouse <dwmw2@infradead.org>
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* Steven J. Hill <sjhill@realitydiluted.com>
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* Thomas Gleixner <tglx@linutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Info:
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* Contains standard defines and IDs for NAND flash devices
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*
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* Changelog:
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* See git changelog.
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*/
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#ifndef __LINUX_MTD_NAND_H
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#define __LINUX_MTD_NAND_H
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#include <common.h>
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#include <linux/bitops.h>
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#define NAND_K9F2G08 0xecda
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/* This constant declares the max. oobsize / page, which
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* is supported now. If you add a chip with bigger oobsize/page
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* adjust this accordingly.
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*/
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#define NAND_MAX_OOBSIZE 218
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#define NAND_MAX_PAGESIZE 4096
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/*
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* Constants for hardware specific CLE/ALE/NCE function
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*
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* These are bits which can be or'ed to set/clear multiple
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* bits in one go.
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*/
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/* Select the chip by setting nCE to low */
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#define NAND_NCE 0x01
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/* Select the command latch by setting CLE to high */
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#define NAND_CLE 0x02
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/* Select the address latch by setting ALE to high */
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#define NAND_ALE 0x04
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#define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
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#define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
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#define NAND_CTRL_CHANGE 0x80
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/*
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* Standard NAND flash commands
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*/
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#define NAND_CMD_READ0 0x00 /*Page read period 1*/
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#define NAND_CMD_READSTART 0x30 /*Page read period 2, for large page*/
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#define NAND_CMD_READID 0x90 /*Read production ID*/
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#define NAND_CMD_SEQIN 0x80 /*Page write period 1*/
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#define NAND_CMD_PAGEPROG 0x10 /*Page write period 2*/
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#define NAND_CMD_ERASE1 0x60 /*Block erase period 1*/
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#define NAND_CMD_ERASE2 0xd0 /*Block erase period 2*/
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#define NAND_CMD_STATUS 0x70 /*Read status command*/
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#define NAND_CMD_RESET 0xff /*Nandflash reset command*/
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#define NAND_CMD_READ1 1
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#define NAND_CMD_RNDOUT 0x05 /*Page random read period 1*/
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#define NAND_CMD_RNDOUTSTART 0xE0 /*Page random read period 2*/
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#define NAND_CMD_RNDIN 0x85 /*Page random write*/
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#define NAND_CMD_READOOB 0x50
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#define NAND_CMD_STATUS_MULTI 0x71
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/* Extended commands for large page devices */
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#define NAND_CMD_CACHEDPROG 0x15
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/* Extended commands for AG-AND device */
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/*
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* Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
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* there is no way to distinguish that from NAND_CMD_READ0
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* until the remaining sequence of commands has been completed
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* so add a high order bit and mask it off in the command.
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*/
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#define NAND_CMD_DEPLETE1 0x100
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#define NAND_CMD_DEPLETE2 0x38
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#define NAND_CMD_STATUS_MULTI 0x71
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#define NAND_CMD_STATUS_ERROR 0x72
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/* multi-bank error status (banks 0-3) */
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#define NAND_CMD_STATUS_ERROR0 0x73
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#define NAND_CMD_STATUS_ERROR1 0x74
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#define NAND_CMD_STATUS_ERROR2 0x75
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#define NAND_CMD_STATUS_ERROR3 0x76
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#define NAND_CMD_STATUS_RESET 0x7f
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#define NAND_CMD_STATUS_CLEAR 0xff
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#define NAND_CMD_NONE -1
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/* Status bits */
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#define NAND_STATUS_FAIL 0x01
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#define NAND_STATUS_FAIL_N1 0x02
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#define NAND_STATUS_TRUE_READY 0x20
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#define NAND_STATUS_READY 0x40
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#define NAND_STATUS_WP 0x80
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/*
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* Constants for ECC_MODES
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*/
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typedef enum
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{
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NAND_ECC_NONE,
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NAND_ECC_SOFT,
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NAND_ECC_HW,
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NAND_ECC_HW_SYNDROME,
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NAND_ECC_HW_OOB_FIRST,
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} nand_ecc_modes_t;
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/*
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* Constants for Hardware ECC
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*/
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/* Reset Hardware ECC for read */
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#define NAND_ECC_READ 0
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/* Reset Hardware ECC for write */
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#define NAND_ECC_WRITE 1
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/* Enable Hardware ECC before syndrom is read back from flash */
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#define NAND_ECC_READSYN 2
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/* Bit mask for flags passed to do_nand_read_ecc */
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#define NAND_GET_DEVICE 0x80
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/* Option constants for bizarre disfunctionality and real
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* features
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*/
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/* Chip can not auto increment pages */
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#define NAND_NO_AUTOINCR 0x00000001
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/* Buswitdh is 16 bit */
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#define NAND_BUSWIDTH_16 0x00000002
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/* Device supports partial programming without padding */
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#define NAND_NO_PADDING 0x00000004
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/* Chip has cache program function */
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#define NAND_CACHEPRG 0x00000008
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/* Chip has copy back function */
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#define NAND_COPYBACK 0x00000010
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/* AND Chip which has 4 banks and a confusing page / block
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* assignment. See Renesas datasheet for further information */
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#define NAND_IS_AND 0x00000020
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/* Chip has a array of 4 pages which can be read without
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* additional ready /busy waits */
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#define NAND_4PAGE_ARRAY 0x00000040
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/* Chip requires that BBT is periodically rewritten to prevent
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* bits from adjacent blocks from 'leaking' in altering data.
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* This happens with the Renesas AG-AND chips, possibly others. */
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#define BBT_AUTO_REFRESH 0x00000080
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/* Chip does not require ready check on read. True
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* for all large page devices, as they do not support
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* autoincrement.*/
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#define NAND_NO_READRDY 0x00000100
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/* Chip does not allow subpage writes */
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#define NAND_NO_SUBPAGE_WRITE 0x00000200
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/* Options valid for Samsung large page devices */
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#define NAND_SAMSUNG_LP_OPTIONS \
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(NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
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/* Macros to identify the above */
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#define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
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#define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
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#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
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#define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
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/* Large page NAND with SOFT_ECC should support subpage reads */
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#define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \
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&& (chip->page_shift > 9))
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/* Mask to zero out the chip options, which come from the id table */
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#define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
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/* Non chip related options */
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/* Use a flash based bad block table. This option is passed to the
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* default bad block table function. */
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#define NAND_USE_FLASH_BBT 0x00010000
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/* This option skips the bbt scan during initialization. */
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#define NAND_SKIP_BBTSCAN 0x00020000
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/* This option is defined if the board driver allocates its own buffers
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(e.g. because it needs them DMA-coherent */
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#define NAND_OWN_BUFFERS 0x00040000
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/* Options set by nand scan */
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/* bbt has already been read */
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#define NAND_BBT_SCANNED 0x40000000
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/* Nand scan has allocated controller struct */
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#define NAND_CONTROLLER_ALLOC 0x80000000
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/* Cell info constants */
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#define NAND_CI_CHIPNR_MSK 0x03
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#define NAND_CI_CELLTYPE_MSK 0x0C
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/*
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* NAND Flash Manufacturer ID Codes
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*/
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#define NAND_MFR_TOSHIBA 0x98
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#define NAND_MFR_SAMSUNG 0xec
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#define NAND_MFR_FUJITSU 0x04
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#define NAND_MFR_NATIONAL 0x8f
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#define NAND_MFR_RENESAS 0x07
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#define NAND_MFR_STMICRO 0x20
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#define NAND_MFR_HYNIX 0xad
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#define NAND_MFR_MICRON 0x2c
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#define NAND_MFR_AMD 0x01
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/*
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* Constants for oob configuration
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*/
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#define NAND_SMALL_BADBLOCK_POS 5
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#define NAND_LARGE_BADBLOCK_POS 0
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#if defined(CONFIG_S3C2410)
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#define REG_NFCONF __REGi(ELFIN_NAND_BASE + 0x0)
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#define REG_NFCMD __REGb(ELFIN_NAND_BASE + 0x4)
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#define REG_NFADDR __REGb(ELFIN_NAND_BASE + 0x8)
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#define REG_NFDATA __REGb(ELFIN_NAND_BASE + 0xc)
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#define REG_NFSTAT __REGb(ELFIN_NAND_BASE + 0x10)
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#define NFSTAT_BUSY 1
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#define nand_select() (REG_NFCONF &= ~0x800) /*Clear bit 11*/
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#define nand_deselect() (REG_NFCONF |= 0x800)
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#define nand_clear_RnB() do {} while (0)
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#define nand_detect_RnB() do {} while (0)
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#define nand_wait_RnB() do {} while (0)
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#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
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#define REG_NFCONF __REGi(ELFIN_NAND_BASE + 0x0)
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#define REG_NFCONT __REGi(ELFIN_NAND_BASE + 0x4)
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#define REG_NFCMD __REGb(ELFIN_NAND_BASE + 0x8)
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#define REG_NFADDR __REGb(ELFIN_NAND_BASE + 0xc)
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#define REG_NFDATA __REGb(ELFIN_NAND_BASE + 0x10)
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#define REG_NFDATA16 __REGw(ELFIN_NAND_BASE + 0x10)
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#define REG_NFSTAT __REGb(ELFIN_NAND_BASE + 0x20)
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#define NFSTAT_BUSY 1
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#define nand_select() (REG_NFCONT &= ~(1 << 1))
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#define nand_deselect() (REG_NFCONT |= (1 << 1))
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#define nand_clear_RnB() (REG_NFSTAT |= (1 << 2))
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#define nand_detect_RnB() {while(!(REG_NFSTAT&(1<<2)));} /*Wait Read & Busy signal goto high(not busy)*/
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#define nand_wait_RnB() {while(!(REG_NFSTAT&(1<<0)));} /*Wait nand flash not busy, wait bit[0] goes to 1*/
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#endif
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#define SKIP_BAD_BLOCK 1
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#define NOT_SKIP_BAD_BLOCK 0
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struct boot_nand_t
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{
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int page_size;
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int spare_size;
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int block_size;
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int block_num;
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int bad_block_offset;
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int id;
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// unsigned long size;
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};
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int nand_init(struct boot_nand_t *nand);
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int nand_read_page(struct boot_nand_t *nand, ulong page_num, ulong offset, char *data, ulong size);
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int nand_write_page(struct boot_nand_t *nand, ulong page_num, ulong offset, char *data, ulong size);
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int is_bad_block(struct boot_nand_t *nand, ulong addr);
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int mark_bad_block(struct boot_nand_t *nand, ulong addr);
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int nand_erase_block(struct boot_nand_t *nand, ulong block_num);
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int nand_erase(struct boot_nand_t *nand, ulong start_addr, ulong size, int skip_bad);
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void nand_scrub(struct boot_nand_t *nand);
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int nand_read_spare(struct boot_nand_t *nand, ulong page_addr, int size, char *buf);
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int nand_write_spare(struct boot_nand_t *nand, ulong page_addr, int size, char *buf);
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int nand_read(struct boot_nand_t *nand, ulong start_addr, ulong size, char *buf);
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int nand_write(struct boot_nand_t *nand, ulong start_addr, ulong size, char *buf);
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#endif /* __LINUX_MTD_NAND_H */
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