/*
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* =====================================================================================
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*
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* Filename: bootstrap.h
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* Version: 1.0.0
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* Author: Guo Wenxue<Email: guowenxue@ghlsystems.com QQ:281143292>
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* CopyRight: 2011 (C) Guo Wenxue
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* Description: Some Reigster address definition for bootstrap.S
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* =====================================================================================
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*/
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#define S3C_WATCHDOG_BASE 0x53000000
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#define S3C_INTERRUPT_BASE 0x4a000000
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#define SRCPND_OFFSET 0x00
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#define INTMOD_OFFSET 0x04
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#define INTMSK_OFFSET 0x08
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#define PRIORITY_OFFSET 0x0c
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#define INTPND_OFFSET 0x10
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#define INTOFFSET_OFFSET 0x14
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#define SUBSRCPND_OFFSET 0x18
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#define INTSUBMSK_OFFSET 0x1c
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#define S3C_CLOCK_POWER_BASE 0x4c000000
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#define LOCKTIME_OFFSET 0x00
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#define MPLLCON_OFFSET 0x04
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#define UPLLCON_OFFSET 0x08
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#define CLKCON_OFFSET 0x0c
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#define CLKSLOW_OFFSET 0x10
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#define CLKDIVN_OFFSET 0x14
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#define CAMDIVN_OFFSET 0x18
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#define BWSCON 0x48000000
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#define MDIV_405 0x7f << 12
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#define PSDIV_405 0x21
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#define GPBCON 0x56000010
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#define GPBDAT 0x56000014
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#define GPBUP 0x56000018
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#define OUTPUT 0x01 /* Set GPIO port as output mode*/
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#define INPUT 0x00 /* Set GPIO port as input mode*/
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#define BEEP 0 /* On FL2440 board, LED0 use GPB0*/
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#define LED0 5 /* On FL2440 board, LED0 use GPB5*/
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#define LED1 6 /* On FL2440 board, LED0 use GPB6*/
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#define LED2 8 /* On FL2440 board, LED0 use GPB8*/
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#define LED3 10 /* On FL2440 board, LED0 use GPB10*/
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/* BWSCON */
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#define DW8 (0x0)
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#define DW16 (0x1)
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#define DW32 (0x2)
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#define WAIT (0x1<<2)
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#define UBLB (0x1<<3)
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#define B1_BWSCON (DW16)
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#define B2_BWSCON (DW16)
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#define B3_BWSCON (DW16 + WAIT + UBLB)
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#define B4_BWSCON (DW16)
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#define B5_BWSCON (DW16)
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#define B6_BWSCON (DW32)
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#define B7_BWSCON (DW32)
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#define B0_Tacs 0x0
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#define B0_Tcos 0x0
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#define B0_Tacc 0x7
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#define B0_Tcoh 0x0
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#define B0_Tah 0x0
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#define B0_Tacp 0x0
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#define B0_PMC 0x0
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#define B1_Tacs 0x0
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#define B1_Tcos 0x0
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#define B1_Tacc 0x7
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#define B1_Tcoh 0x0
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#define B1_Tah 0x0
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#define B1_Tacp 0x0
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#define B1_PMC 0x0
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#define B2_Tacs 0x0
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#define B2_Tcos 0x0
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#define B2_Tacc 0x7
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#define B2_Tcoh 0x0
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#define B2_Tah 0x0
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#define B2_Tacp 0x0
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#define B2_PMC 0x0
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#define B3_Tacs 0xc
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#define B3_Tcos 0x7
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#define B3_Tacc 0xf
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#define B3_Tcoh 0x1
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#define B3_Tah 0x0
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#define B3_Tacp 0x0
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#define B3_PMC 0x0
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#define B4_Tacs 0x0
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#define B4_Tcos 0x0
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#define B4_Tacc 0x7
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#define B4_Tcoh 0x0
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#define B4_Tah 0x0
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#define B4_Tacp 0x0
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#define B4_PMC 0x0
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#define B5_Tacs 0xc
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#define B5_Tcos 0x7
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#define B5_Tacc 0xf
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#define B5_Tcoh 0x1
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#define B5_Tah 0x0
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#define B5_Tacp 0x0
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#define B5_PMC 0x0
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/* SDRAM is on HSB bus, so its clock is from HCLK, FCLK=400, HCLK=100; so SDRAM 1clk=10ns */
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#define B6_MT 0x3 /* SDRAM */
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// K4S561632 datasheet: RAS to CAS delay(Trcd) Min value should be 18/20ns, HCLK is 100MHz, so 1clk=10ns
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// EM63A165 datasheet: RAS# to CAS# delay(Trcd) Min value should be 15/20ns, HCLK is 100MHz, so 1clk=10ns
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#define B6_Trcd 0x2 /* 4clk */
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#define B6_SCAN 0x1 /* 9bit */
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#define B7_MT 0x3 /* SDRAM */
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#define B7_Trcd 0x1 /* 3clk */
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#define B7_SCAN 0x1 /* 9bit */
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/* REFRESH register<0x48000024> parameter */
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#define REFEN 0x1 /* Refresh enable */
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#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
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// Trp: Row precharge time
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// K4S561632 datasheet: Min(Trp) value should be 18/20ns;
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// EM63A165 datasheet: Min value should be 15/20ns;
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#define Trp 0x2 /* 4clk */
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// Trc: Row cycle time
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// K4S561632 datasheet: Min value should be 60/65ns;
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// EM63A165 datasheet: Min value should be 60/63ns;
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// S3C2440 datasheet: REFRESH register describe: SDRAM Row cycle time: Trc=Tsrc+Trp
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#define Tsrc 0x2 /* 6clk, so Trc=Tsrc+Trp=6+3=9clk */
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// K4S561632 datasheet: 64ms refresh period (8K Cycle): 64000/8192=7.81us
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// EM63A165 datasheet: 8192 refresh cycles/64ms: 64000/8192=7.81us
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// S3C2440 datasheet: REFRESH Register Refresh period = (2^11-refresh_count+1)/HCLK
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// So Refresh count = 2^11 + 1 - 100x7.81 = 1268
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#define REFCNT 1268
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//#define REFCNT 489 /* HCLK=100Mhz, (2048+1-15.6*100) */
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