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/********************************************************************************************
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* File: bootstrap.S
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* Version: 1.0.0
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* Copyright: 2011 (c) Guo Wenxue <Email: guowenxue@gmail.com QQ:281143292>
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* Description: If we wanna debug u-boot by J-Link in external SDRAM, we must download this
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* bootstrap.bin file into s3c24x0 8K internal SRAM(Stepping Stone) and excute
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* first, which used to initialize the CPU and external SDRAM. Only after init
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* the SDRAM then we can debug u-boot in it.
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* ChangeLog: 1, Release initial version on "Tue Jul 12 16:43:18 CST 2011"
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*
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*******************************************************************************************/
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#include "bootstrap.h"
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.text
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.align 2
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.global _start
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_start:
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/* set cpu to SVC32 mode */
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mrs r0, cpsr
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bic r0, r0, #0x1f
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orr r0, r0, #0xd3
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msr cpsr, r0
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/* Disable watchdog */
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ldr r0, =S3C_WATCHDOG_BASE
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mov r1, #0
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str r1, [r0]
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/* Disable Interrupt */
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ldr r0, =S3C_INTERRUPT_BASE
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mov r1, #0xffffffff
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str r1, [r0, #INTMSK_OFFSET]
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ldr r1, =0x000007ff
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str r1, [r0, #INTSUBMSK_OFFSET]
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/* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0290g/Babjcgjg.html */
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache, Invalidate ICache and DCache */
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mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
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/* disable MMU stuff and caches */
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
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bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
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orr r0, r0, #0x00000002 @ set bit 2 (A) Align
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orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
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mcr p15, 0, r0, c1, c0, 0
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/*******************************************************************************************
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* Init system clock and power, FCLK:HCLK:PCLK = 1:4:8
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* Reference to S3C2440 datasheet: Chap 7 Clock&Power Management
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*
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* Initialize System Clock FCLK=400MHz HCLK=100MHz PCLK=50MHz
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* FCLK is used by ARM920T
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* HCLK is used for AHB bus, which is used by the ARM920T, the memory controller,
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* the interrupt controller, the LCD controller, the DMA and USB host block.
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* PCLK is is used for APB bus,which is used by the peripherals such as WDT,IIS,I2C,
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* PWM timer,MMC interface,ADC,UART,GPIO,RTC and SPI.
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******************************************************************************************/
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/*Set LOCKTIME as default value 0x00ffffff*/
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ldr r0, =S3C_CLOCK_POWER_BASE
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ldr r1, =0x00ffffff
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str r1, [r0, #LOCKTIME_OFFSET]
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/*******************************************************************************************
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* Reference to S3C2440 datasheet: Chap 7-8 ~ Page 242
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*
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* Set the selection of Dividing Ratio between FCLK,HCLK and PCLK as FCLK:HCLK:PCLK = 1:4:8.
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* This ratio is determined by HDIVN(here is 2) and PDIVN(here is 1) control register.
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* Refer to the s3c2440 datasheet
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*******************************************************************************************/
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ldr r0, =S3C_CLOCK_POWER_BASE
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mov r1, #5
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str r1, [r0, #CLKDIVN_OFFSET] /*Set Clock Divider*/
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mrc p15, 0, r1, c1, c0, 0
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orr r1, r1, #0xc0000000
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mcr p15, 0, r1, c1, c0, 0
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/***************************************************************************************
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* Reference to S3C2440 datasheet: Chap 7-20 ~ Page 254
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*
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* Set MPLLCON(0x4C000004) register as:
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* [19:12]: MDIV(Main Divider control)=0x7F (value set in MDIV_405)
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* [9:4]: PDIV(Pre-devider control)=0x02 (value set in PSDIV_405)
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* [1:0]: SDIV(Post divider control)=0x01 (value set in PSDIV_405)
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*
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* MPLL(FCLK) = (2 * m * Fin)/(p * 2^s)
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* m=(MDIV+8), p=(PDIV+2), s=SDIV
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*
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* So FCLK=((2*(127+8)*Fin)) / ((2+2)*2^1)
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* = (2*135*12MHz)/8
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* = 405MHz
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* For FCLK:HCLK:PCLK=1:4:8, so HCLK=100MHz, PCLK=50MHz
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***************************************************************************************/
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mov r1, #S3C_CLOCK_POWER_BASE
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mov r2, #MDIV_405
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add r2, r2, #PSDIV_405
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str r2, [r1, #MPLLCON_OFFSET]
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mem_init:
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/* memory control configuration */
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/* make r0 relative the current location so that it */
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/* reads SMRDATA out of FLASH rather than memory ! */
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ldr r0, =SMRDATA
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ldr r1, =mem_init
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sub r0, r0, r1
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adr r3, mem_init /* r3 <- current position of code */
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add r0, r0, r3 /*r0 =SMRDATA-mem_init+mem_init =SMRDATA*/
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ldr r1, =BWSCON /* Bus Width Status Controller */
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add r2, r0, #13*4
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0:
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ldr r3, [r0], #4
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str r3, [r1], #4
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cmp r2, r0
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bne 0b
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/*Set GPIO5, GPIO6, GPIO8, GPIO10 as GPIO OUTPUT mode*/
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ldr r0, =GPBCON
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ldr r1, [r0]
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bic r1, r1, #0xC00 /*Set GPBCON for GPIO5 as 0x00 */
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orr r1, r1, #0x0400 /*Set GPBCON for GPIO5 as GPIOOUT, 0x01*/
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str r1, [r0]
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ldr r3, [r2]
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bic r3, r3, #(1<<LED0) /*Clear bit 5, set GPB5 as low level*/
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str r3, [r2]
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/* everything is fine now */
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dead_loop:
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b dead_loop
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.ltorg
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/* the literal pools origin */
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SMRDATA:
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.word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
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.word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
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.word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
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.word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
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.word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
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.word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
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.word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
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.word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
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.word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
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.word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Tsrc<<18)+REFCNT)
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.word 0xb2
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.word 0x30
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.word 0x30
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