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/********************************************************************************************
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* File: start.S - Startup Code for ARM920 CPU-core
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* Version: 1.0.0
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* Copyright: 2011 (c) Guo Wenxue <guowenxue@gmail.com>
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* Description: When system power up, the CPU will comes here to excute the first code here.
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* ChangeLog: 1, Release initial version on "Tue Jul 12 16:43:18 CST 2011"
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*
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*******************************************************************************************/
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/*
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*************************************************************************
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*
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* Jump vector table as in table 3.1 in [1]
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*
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*************************************************************************
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*/
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#include <config.h>
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.globl _start
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_start: b start_code
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ldr pc, _undefined_instruction
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ldr pc, _software_interrupt
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ldr pc, _prefetch_abort
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ldr pc, _data_abort
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ldr pc, _not_used
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ldr pc, _irq
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ldr pc, _fiq
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_undefined_instruction: .word undefined_instruction
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_software_interrupt: .word software_interrupt
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_prefetch_abort: .word prefetch_abort
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_data_abort: .word data_abort
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_not_used: .word not_used
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_irq: .word irq
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_fiq: .word fiq
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.balignl 16,0xdeadbeef
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/*
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*************************************************************************
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*
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* Startup Code (called from the ARM reset exception vector)
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*
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* do important init only if we don't start from memory!
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* relocate armboot to ram
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* setup stack
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* jump to second stage
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*
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*************************************************************************
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*/
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_TEXT_BASE:
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.word TEXT_BASE
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.globl _armboot_start
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_armboot_start:
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.word _start
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/*
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* These are defined in the board-specific linker script.
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*/
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.globl _bss_start
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_bss_start:
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.word __bss_start
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.globl _bss_end
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_bss_end:
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.word _end
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/*
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* the actual start code
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*/
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start_code:
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/*
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* set the cpu to SVC32 mode
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*/
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mrs r0, cpsr
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bic r0, r0, #0x1f
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orr r0, r0, #0xd3
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msr cpsr, r0
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/* Disable watchdog */
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ldr r0, =ELFIN_WATCHDOG_BASE
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mov r1, #0
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str r1, [r0]
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/* Disable Interrupt */
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ldr r0, =ELFIN_INTERRUPT_BASE
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mov r1, #0xffffffff
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str r1, [r0, #INTMSK_OFFSET]
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ldr r1, =0x000007ff
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str r1, [r0, #INTSUBMSK_OFFSET]
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/* flush v4 I/D caches */
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
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mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
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/* disable MMU stuff and caches */
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
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bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
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orr r0, r0, #0x00000002 @ set bit 2 (A) Align
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orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
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mcr p15, 0, r0, c1, c0, 0
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/*******************************************************************************************
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* Init system clock and power, FCLK:HCLK:PCLK = 1:4:8
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* Reference to S3C2440 datasheet: Chap 7 Clock&Power Management
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*
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* Initialize System Clock FCLK=400MHz HCLK=100MHz PCLK=50MHz
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* FCLK is used by ARM920T
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* HCLK is used for AHB bus, which is used by the ARM920T, the memory controller,
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* the interrupt controller, the LCD controller, the DMA and USB host block.
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* PCLK is is used for APB bus,which is used by the peripherals such as WDT,IIS,I2C,
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* PWM timer,MMC interface,ADC,UART,GPIO,RTC and SPI.
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******************************************************************************************/
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/*Set LOCKTIME as default value 0x00ffffff*/
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ldr r0, =ELFIN_CLOCK_POWER_BASE
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ldr r1, =0x00ffffff
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str r1, [r0, #LOCKTIME_OFFSET]
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/*******************************************************************************************
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* Reference to S3C2440 datasheet: Chap 7-8 ~ Page 242
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*
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* Set the selection of Dividing Ratio between FCLK,HCLK and PCLK as FCLK:HCLK:PCLK = 1:4:8.
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* This ratio is determined by HDIVN(here is 2) and PDIVN(here is 1) control register.
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* Refer to the s3c2440 datasheet
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*******************************************************************************************/
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ldr r0, =ELFIN_CLOCK_POWER_BASE
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mov r1, #5
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str r1, [r0, #CLKDIVN_OFFSET] /*Set Clock Divider*/
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mrc p15, 0, r1, c1, c0, 0
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orr r1, r1, #0xc0000000
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mcr p15, 0, r1, c1, c0, 0
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/***************************************************************************************
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* Reference to S3C2440 datasheet: Chap 7-20 ~ Page 254
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*
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* Set MPLLCON(0x4C000004) register as:
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* [19:12]: MDIV(Main Divider control)=0x7F (value set in MDIV_405)
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* [9:4]: PDIV(Pre-devider control)=0x02 (value set in PSDIV_405)
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* [1:0]: SDIV(Post divider control)=0x01 (value set in PSDIV_405)
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*
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* MPLL(FCLK) = (2 * m * Fin)/(p * 2^s)
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* m=(MDIV+8), p=(PDIV+2), s=SDIV
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*
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* So FCLK=((2*(127+8)*Fin)) / ((2+2)*2^1)
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* = (2*135*12MHz)/8
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* = 405MHz
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* For FCLK:HCLK:PCLK=1:4:8, so HCLK=100MHz, PCLK=50MHz
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***************************************************************************************/
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mov r1, #ELFIN_CLOCK_POWER_BASE
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mov r2, #MDIV_405
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add r2, r2, #PSDIV_405
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str r2, [r1, #MPLLCON_OFFSET]
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/* Go to mem_init.S to Init memory controller register */
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bl mem_init
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/* Set up the stack */
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stack_setup:
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ldr r0, =STACK_BASE /* upper 128 KiB: relocated uboot */
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sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
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sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
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sub sp, r0, #12 /* leave 3 words for abort-stack */
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bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
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clear_bss:
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ldr r0, _bss_start /* find start of bss segment */
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ldr r1, _bss_end /* stop here */
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mov r2, #0x00000000 /* clear */
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clbss_l:str r2, [r0] /* clear loop... */
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add r0, r0, #4
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cmp r0, r1
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ble clbss_l
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#if 0 /*Don't wanna init BEEP & LED here*/
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bl init_led_beep
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/*
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* R0,R1,R2 are the 1st,2nd, 3rd argument passed to C function
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* If need pass more than 3 arguments, then we need use stack.
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*/
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mov r0,#LED1
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bl turn_led_on
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#endif
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bl bootstrap_main
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/*
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*************************************************************************
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*
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* Interrupt handling
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*
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*************************************************************************
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*/
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@
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@ IRQ stack frame.
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@
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#define S_FRAME_SIZE 72
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#define S_OLD_R0 68
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#define S_PSR 64
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#define S_PC 60
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#define S_LR 56
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#define S_SP 52
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#define S_IP 48
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#define S_FP 44
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#define S_R10 40
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#define S_R9 36
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#define S_R8 32
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#define S_R7 28
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#define S_R6 24
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#define S_R5 20
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#define S_R4 16
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#define S_R3 12
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#define S_R2 8
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#define S_R1 4
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#define S_R0 0
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#define MODE_SVC 0x13
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#define I_BIT 0x80
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/*
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* use bad_save_user_regs for abort/prefetch/undef/swi ...
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* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
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*/
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.macro bad_save_user_regs
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sub sp, sp, #S_FRAME_SIZE
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stmia sp, {r0 - r12} @ Calling r0-r12
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ldr r2, _armboot_start
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sub r2, r2, #(CONFIG_STACKSIZE)
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sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
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/* set base 2 words into abort stack */
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sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)
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ldmia r2, {r2 - r3} @ get pc, cpsr
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add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
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add r5, sp, #S_SP
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mov r1, lr
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stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
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mov r0, sp
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.endm
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.macro irq_save_user_regs
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sub sp, sp, #S_FRAME_SIZE
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stmia sp, {r0 - r12} @ Calling r0-r12
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add r7, sp, #S_PC
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stmdb r7, {sp, lr}^ @ Calling SP, LR
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str lr, [r7, #0] @ Save calling PC
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mrs r6, spsr
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str r6, [r7, #4] @ Save CPSR
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str r0, [r7, #8] @ Save OLD_R0
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mov r0, sp
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.endm
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.macro irq_restore_user_regs
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ldmia sp, {r0 - lr}^ @ Calling r0 - lr
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mov r0, r0
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ldr lr, [sp, #S_PC] @ Get PC
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add sp, sp, #S_FRAME_SIZE
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/* return & move spsr_svc into cpsr */
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subs pc, lr, #4
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.endm
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.macro get_bad_stack
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ldr r13, _armboot_start @ setup our mode stack
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sub r13, r13, #(CONFIG_STACKSIZE)
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sub r13, r13, #(CONFIG_SYS_MALLOC_LEN)
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/* reserve a couple spots in abort stack */
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sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8)
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str lr, [r13] @ save caller lr / spsr
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mrs lr, spsr
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str lr, [r13, #4]
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mov r13, #MODE_SVC @ prepare SVC-Mode
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@ msr spsr_c, r13
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msr spsr, r13
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mov lr, pc
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movs pc, lr
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.endm
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.macro get_irq_stack @ setup IRQ stack
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ldr sp, IRQ_STACK_START
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.endm
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.macro get_fiq_stack @ setup FIQ stack
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ldr sp, FIQ_STACK_START
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.endm
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/*
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* exception handlers
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*/
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.align 5
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undefined_instruction:
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get_bad_stack
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bad_save_user_regs
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bl do_undefined_instruction
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.align 5
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software_interrupt:
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get_bad_stack
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bad_save_user_regs
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bl do_software_interrupt
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.align 5
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prefetch_abort:
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get_bad_stack
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bad_save_user_regs
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bl do_prefetch_abort
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.align 5
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data_abort:
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get_bad_stack
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bad_save_user_regs
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bl do_data_abort
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.align 5
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not_used:
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get_bad_stack
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bad_save_user_regs
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bl do_not_used
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.align 5
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irq:
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get_bad_stack
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bad_save_user_regs
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bl do_irq
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.align 5
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fiq:
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get_bad_stack
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bad_save_user_regs
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bl do_fiq
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