/***********************************************************************
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* File: led.S
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* Version: 1.0.0
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* Copyright: 2013 (c) Guo Wenxue <guowenxue@gmail.com>
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* Description: This ASM used to disable watch dog and interrupt, then call C code to
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* turn the four LEDs on/off on OK6410 board.
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* ChangeLog: 1, Release initial version on "Sun Feb 24 15:06:12 CST 2013"
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*
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***********************************************************************/
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#define SROM_BW 0x70000000
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#define WTCON 0x7E004000
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/* Interrupt definition */
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#define ELFIN_VIC0_BASE_ADDR (0x71200000)
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#define ELFIN_VIC1_BASE_ADDR (0x71300000)
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#define oIRQSTATUS 0x000
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#define oFIQSTATUS 0x004
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#define oRAWINTR 0x008
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#define oINTSELECT 0x00c
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#define oINTENABLE 0x010
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#define oINTENCLEAR 0x014
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#define oSOFTINT 0x018
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#define oSOFTINTCLEAR 0x01c
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#define oPROTECTION 0x020
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#define oSWPRIORITYMASK 0x024
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#define oPRIORITYDAISY 0x028
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#define oVECTADDR(X) (0x100+(X)*4)
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#define oVECPRIORITY(X) (0x200+(X)*4)
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#define oVECTADDRESS 0xF00
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#define VIC0IRQSTATUS (ELFIN_VIC0_BASE_ADDR + oIRQSTATUS)
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#define VIC0FIQSTATUS (ELFIN_VIC0_BASE_ADDR + oFIQSTATUS)
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#define VIC0RAWINTR (ELFIN_VIC0_BASE_ADDR + oRAWINTR)
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#define VIC0INTSELECT (ELFIN_VIC0_BASE_ADDR + oINTSELECT)
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#define VIC0INTENABLE (ELFIN_VIC0_BASE_ADDR + oINTENABLE)
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#define VIC0INTENCLEAR (ELFIN_VIC0_BASE_ADDR + oINTENCLEAR)
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#define VIC0SOFTINT (ELFIN_VIC0_BASE_ADDR + oSOFTINT)
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#define VIC0SOFTINTCLEAR (ELFIN_VIC0_BASE_ADDR + oSOFTINTCLEAR)
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#define VIC0PROTECTION (ELFIN_VIC0_BASE_ADDR + oPROTECTION)
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#define VIC0SWPRIORITYMASK (ELFIN_VIC0_BASE_ADDR + oSWPRIORITYMASK)
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#define VIC0PRIORITYDAISY (ELFIN_VIC0_BASE_ADDR + oPRIORITYDAISY)
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#define VIC0VECTADDR(X) (ELFIN_VIC0_BASE_ADDR + oVECTADDR(X))
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#define VIC0VECPRIORITY(X) (ELFIN_VIC0_BASE_ADDR + oVECPRIORITY(X))
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#define VIC0VECTADDRESS (ELFIN_VIC0_BASE_ADDR + oVECTADDRESS)
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#define VIC1IRQSTATUS (ELFIN_VIC1_BASE_ADDR + oIRQSTATUS)
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#define VIC1FIQSTATUS (ELFIN_VIC1_BASE_ADDR + oFIQSTATUS)
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#define VIC1RAWINTR (ELFIN_VIC1_BASE_ADDR + oRAWINTR)
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#define VIC1INTSELECT (ELFIN_VIC1_BASE_ADDR + oINTSELECT)
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#define VIC1INTENABLE (ELFIN_VIC1_BASE_ADDR + oINTENABLE)
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#define VIC1INTENCLEAR (ELFIN_VIC1_BASE_ADDR + oINTENCLEAR)
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#define VIC1SOFTINT (ELFIN_VIC1_BASE_ADDR + oSOFTINT)
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#define VIC1SOFTINTCLEAR (ELFIN_VIC1_BASE_ADDR + oSOFTINTCLEAR)
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#define VIC1PROTECTION (ELFIN_VIC1_BASE_ADDR + oPROTECTION)
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#define VIC1SWPRIORITYMASK (ELFIN_VIC1_BASE_ADDR + oSWPRIORITYMASK)
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#define VIC1PRIORITYDAISY (ELFIN_VIC1_BASE_ADDR + oPRIORITYDAISY)
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#define VIC1VECTADDR(X) (ELFIN_VIC1_BASE_ADDR + oVECTADDR(X))
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#define VIC1VECPRIORITY(X) (ELFIN_VIC1_BASE_ADDR + oVECPRIORITY(X))
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#define VIC1VECTADDRESS (ELFIN_VIC1_BASE_ADDR + oVECTADDRESS)
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/*****************************/
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/* CP15 Mode Bit Definition */
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/*****************************/
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#define R1_iA (1<<31)
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#define R1_nF (1<<30)
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#define R1_VE (1<<24)
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#define R1_I (1<<12)
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#define R1_BP (1<<11) /* Z bit */
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#define R1_C (1<<2)
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#define R1_A (1<<1)
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#define R1_M (1<<0)
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.global _start
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_start:
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/* Enable Instruction Cache */
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 /* Invalidate Entire I&D Cache */
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mrc p15, 0, r0, c1, c0, 0 /* Enable I Cache */
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orr r0, r0, #R1_I
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mcr p15, 0, r0, c1, c0, 0
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/* disable vector interrupt */
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #(1<<24)
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mcr p15, 0, r0, c1, c0, 0
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/* Peri port setup */
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ldr r0, =SROM_BW
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orr r0, r0, #0x13
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mcr p15,0,r0,c15,c2,4 @ 256M(0x70000000-0x7fffffff)
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/* Disable watchdog */
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ldr r0, =WTCON
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mov r1, #0
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str r1, [r0]
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/* disable all interrupt */
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ldr r4, =VIC0INTENCLEAR
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ldr r5, =0xFFFFFFFF;
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str r5, [r4]
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ldr r4, =VIC1INTENCLEAR
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str r5, [r4]
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/* Setup Stack */
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ldr sp, =8*1024
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bl main
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halt:
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b halt
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