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| /***********************************************************************
| * File: start.S
| * Version: 1.0.0
| * Copyright: 2013 (c) Guo Wenxue <guowenxue@gmail.com>
| * Description: This ASM used to disable watch dog and interrupt, and initialise
| * the system clock and DDR SDRAM.
| * ChangeLog: 1, Release initial version on "Sun Feb 24 15:06:12 CST 2013"
| *
| ***********************************************************************/
|
| #include "s3c6410.h"
|
| .section .init, "ax"
| .global _start
|
| _start:
| /* Enable Instruction Cache */
| mov r0, #0
| mcr p15, 0, r0, c7, c7, 0 /* Invalidate Entire I&D Cache */
| mrc p15, 0, r0, c1, c0, 0 /* Enable I Cache */
| orr r0, r0, #R1_I
| mcr p15, 0, r0, c1, c0, 0
|
| /* disable vector interrupt */
| mrc p15, 0, r0, c1, c0, 0
| bic r0, r0, #(1<<24)
| mcr p15, 0, r0, c1, c0, 0
|
| /* Peri port setup */
| ldr r0, =ELFIN_SROM_BASE
| orr r0, r0, #0x13
| mcr p15,0,r0,c15,c2,4 @ 256M(0x70000000-0x7fffffff)
|
| /* Disable watchdog */
| ldr r0, =WTCON
| mov r1, #0
| str r1, [r0]
|
| /* disable all interrupt */
| ldr r0, =VIC0INTENCLEAR
| ldr r1, =0xFFFFFFFF;
| str r1, [r0]
| ldr r1, =VIC1INTENCLEAR
| str r1, [r0]
|
| bl system_clock_init /* setup clock */
| bl mem_ctrl_asm_init /* initialize DDR RAM */
|
| /* clear BSS */
| mov r0, #0
| ldr r1, =__bss_start
| ldr r2, =__bss_end
| _bss_loop:
| cmp r1, r2
| strlo r0, [r1], #4
| blo _bss_loop
|
| /* Setup Stack */
| ldr sp, =8*1024
| bl main
|
| halt:
| b halt
|
|
