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| /***********************************************************************
| * File: start.S
| * Version: 1.0.0
| * Copyright: 2013 (c) Guo Wenxue <guowenxue@gmail.com>
| * Description: This ASM used to disable watch dog and interrupt, and initialise
| * the system clock and DDR SDRAM.
| * ChangeLog: 1, Release initial version on "Sun Feb 24 15:06:12 CST 2013"
| *
| ***********************************************************************/
|
| #include "s3c6410.h"
|
| .section .init, "ax"
| .global _start
|
| _start:
| /* Enable Instruction Cache */
| mov r0, #0
| mcr p15, 0, r0, c7, c7, 0 /* Invalidate Entire I&D Cache */
| mrc p15, 0, r0, c1, c0, 0 /* Enable I Cache */
| orr r0, r0, #R1_I
| mcr p15, 0, r0, c1, c0, 0
|
| /* disable vector interrupt */
| mrc p15, 0, r0, c1, c0, 0
| bic r0, r0, #(1<<24)
| mcr p15, 0, r0, c1, c0, 0
|
| /* Peri port setup */
| ldr r0, =ELFIN_SROM_BASE
| orr r0, r0, #0x13
| mcr p15,0,r0,c15,c2,4 @ 256M(0x70000000-0x7fffffff)
|
| /* Disable watchdog */
| ldr r0, =WTCON
| mov r1, #0
| str r1, [r0]
|
| /* disable all interrupt */
| ldr r0, =VIC0INTENCLEAR
| ldr r1, =0xFFFFFFFF;
| str r1, [r0]
| ldr r1, =VIC1INTENCLEAR
| str r1, [r0]
|
| bl system_clock_init /* setup clock */
| bl mem_ctrl_asm_init /* initialize DDR RAM */
| bl setup_led
|
| halt:
| b halt
|
|
|
| /************************************************************
| * system_clock_init: Initialize core clock and bus clock. *
| ************************************************************/
| .globl system_clock_init
| system_clock_init:
| ldr r0, =ELFIN_CLOCK_POWER_BASE /* 0x7e00f000 */
|
| #ifdef CONFIG_SYNC_MODE /* Set to Synchronous Mode, HCLK and PCLK from APLL */
| ldr r1, [r0, #oOTHERS]
| mov r2, #0x40 /* SyncMUXSEL = DOUT_APLL */
| orr r1, r1, r2
| str r1, [r0, #oOTHERS]
| nop
| nop
| nop
| nop
| nop
| ldr r2, =0x80 /* SyncReq = request Sync */
| orr r1, r1, r2
| str r1, [r0, #oOTHERS]
|
| check_syncack:
| ldr r1, [r0, #oOTHERS]
| ldr r2, =0xF00
| and r1, r1, r2 /* Wait SYNCMODEACK = 0xF */
| cmp r1, #0xF00
| bne check_syncack
|
| #else /* CONFIG_ASYNC_MODE: Set to Asynchronous Mode, HCLK and PCLK from MPLL */
| ldr r1, [r0, #oOTHERS]
| bic r1, r1, #0xC0
| orr r1, r1, #0x40
| str r1, [r0, #oOTHERS]
|
| wait_for_async:
| ldr r1, [r0, #oOTHERS]
| and r1, r1, #0xf00 /* Wait SYNCMODEACK = 0x0 */
| cmp r1, #0x0
| bne wait_for_async
|
| ldr r1, [r0, #oOTHERS]
| bic r1, r1, #0x40 /* SyncMUX = Async */
| str r1, [r0, #oOTHERS]
|
| #endif /* CONFIG_SYNC_MODE end */
|
| /* Set lock time*/
| mov r1, #0xff00
| orr r1, r1, #0xff
| str r1, [r0, #oAPLL_LOCK]
| str r1, [r0, #oMPLL_LOCK]
| str r1, [r0, #oEPLL_LOCK]
|
| /* Set Clock Divider */
| ldr r1, [r0, #oCLK_DIV0]
| bic r1, r1, #0x30000
| bic r1, r1, #0xff00
| bic r1, r1, #0xff
| ldr r2, =CLK_DIV_VAL
| orr r1, r1, r2
| str r1, [r0, #oCLK_DIV0]
|
| /* Set System Clock Divider */
| ldr r1, =APLL_VAL
| str r1, [r0, #oAPLL_CON]
|
| ldr r1, =MPLL_VAL
| str r1, [r0, #oMPLL_CON]
|
| ldr r1, =EPLL_VAL
| str r1, [r0, #oEPLL_CON0]
| ldr r1, =EPLL_KVAL
| str r1, [r0, #oEPLL_CON1]
|
| /* APLL, MPLL, EPLL select to Fout */
| ldr r1, [r0, #oCLK_SRC]
| orr r1, r1, #0x7 /* PLL Clockout */
| str r1, [r0, #oCLK_SRC]
|
| /* wait at least 200us to stablize all clock */
| mov r1, #0x10000
| 1: subs r1, r1, #1
| bne 1b
|
| mov pc, lr
|
|
| /***************************
| * DDR SDRAM initialisze *
| ***************************/
| .globl mem_ctrl_asm_init
| mem_ctrl_asm_init:
| ldr r0, =ELFIN_MEM_SYS_CFG /* Memory sussystem address 0x7e00f120 */
| @mov r1, #0xd /* Xm0CSn2 = NFCON CS0, Xm0CSn3 = NFCON CS1 */
| mov r1, #S3C64XX_MEM_SYS_CFG_NAND /* Xm0CSn2 = NFCON CS0, Xm0CSn3 = NFCON CS1 */
| str r1, [r0]
|
| ldr r0, =ELFIN_DMC1_BASE /* DMC1 base address 0x7e001000 */
|
| @Enter Config State
| ldr r1, =0x04
| str r1, [r0, #INDEX_DMC_MEMC_CMD]
|
| ldr r1, =DMC_DDR_REFRESH_PRD
| str r1, [r0, #INDEX_DMC_REFRESH_PRD]
|
| ldr r1, =DMC_DDR_CAS_LATENCY
| str r1, [r0, #INDEX_DMC_CAS_LATENCY]
|
| ldr r1, =DMC_DDR_t_DQSS
| str r1, [r0, #INDEX_DMC_T_DQSS]
|
| ldr r1, =DMC_DDR_t_MRD
| str r1, [r0, #INDEX_DMC_T_MRD]
|
| ldr r1, =DMC_DDR_t_RAS
| str r1, [r0, #INDEX_DMC_T_RAS]
|
| ldr r1, =DMC_DDR_t_RC
| str r1, [r0, #INDEX_DMC_T_RC]
|
| ldr r1, =DMC_DDR_t_RCD
| ldr r2, =DMC_DDR_schedule_RCD
| orr r1, r1, r2
| str r1, [r0, #INDEX_DMC_T_RCD]
|
|
| ldr r1, =DMC_DDR_t_RFC
| ldr r2, =DMC_DDR_schedule_RFC
| orr r1, r1, r2
| str r1, [r0, #INDEX_DMC_T_RFC]
|
| ldr r1, =DMC_DDR_t_RP
| ldr r2, =DMC_DDR_schedule_RP
| orr r1, r1, r2
| str r1, [r0, #INDEX_DMC_T_RP]
|
| ldr r1, =DMC_DDR_t_RRD
| str r1, [r0, #INDEX_DMC_T_RRD]
|
| ldr r1, =DMC_DDR_t_WR
| str r1, [r0, #INDEX_DMC_T_WR]
|
| ldr r1, =DMC_DDR_t_WTR
| str r1, [r0, #INDEX_DMC_T_WTR]
|
| ldr r1, =DMC_DDR_t_XP
| str r1, [r0, #INDEX_DMC_T_XP]
|
| ldr r1, =DMC_DDR_t_XSR
| str r1, [r0, #INDEX_DMC_T_XSR]
|
| ldr r1, =DMC_DDR_t_ESR
| str r1, [r0, #INDEX_DMC_T_ESR]
|
| ldr r1, =DMC1_MEM_CFG
| str r1, [r0, #INDEX_DMC_MEMORY_CFG]
|
| ldr r1, =DMC1_MEM_CFG2
| str r1, [r0, #INDEX_DMC_MEMORY_CFG2]
|
| ldr r1, =DMC1_CHIP0_CFG
| str r1, [r0, #INDEX_DMC_CHIP_0_CFG]
|
| ldr r1, =DMC_DDR_32_CFG
| str r1, [r0, #INDEX_DMC_USER_CONFIG]
|
| @DMC0 DDR Chip 0 configuration direct command reg
| ldr r1, =DMC_NOP0
| str r1, [r0, #INDEX_DMC_DIRECT_CMD]
|
| @Precharge All
| ldr r1, =DMC_PA0
| str r1, [r0, #INDEX_DMC_DIRECT_CMD]
|
| @Auto Refresh 2 time
| ldr r1, =DMC_AR0
| str r1, [r0, #INDEX_DMC_DIRECT_CMD]
| str r1, [r0, #INDEX_DMC_DIRECT_CMD]
|
| @MRS
| ldr r1, =DMC_mDDR_EMR0
| str r1, [r0, #INDEX_DMC_DIRECT_CMD]
|
| @Mode Reg
| ldr r1, =DMC_mDDR_MR0
| str r1, [r0, #INDEX_DMC_DIRECT_CMD]
|
| @Enable DMC1, Enter Ready State
| mov r1, #0x0
| str r1, [r0, #INDEX_DMC_MEMC_CMD]
|
| @Wait for Ready
| _check_dmc1_ready:
| ldr r1, [r0, #INDEX_DMC_MEMC_STATUS]
| mov r2, #0x3
| and r1, r1, r2
| cmp r1, #0x1
| bne _check_dmc1_ready
| nop
|
| mov pc, lr
|
| setup_led:
| /*Set GPM0, GPM1, GPM2, GPM3 as GPIO OUTPUT mode*/
| ldr r0, =ELFIN_GPIO_BASE
| ldr r1, [r0, #oGPMCON]
| bic r1, r1, #0x00FF /*Set GPMCON for GPM0,GPM1 as 0x00 */
| orr r1, r1, #0x0011 /*Set GPMCON for GPM0,GPM1 as GPIOOUT, 0x01*/
| bic r1, r1, #0xFF00 /*Set GPMCON for GPM2,GPM3 as 0x00*/
| orr r1, r1, #0x1100 /*Set GPMCON for GPM2,GPM3 as GPIOOUT, 0x01*/
| str r1, [r0, #oGPMCON]
|
| /* Turn on LED1, LED2, LED3, LED4 */
| ldr r1, [r0, #oGPMDAT]
| bic r1, r1, #0xF /*Set bit[0:3] as low level*/
| str r1, [r0, #oGPMDAT]
|
| mov pc, lr
|
|
|
