/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#ifndef __HALHWOUTSRC_H__
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#define __HALHWOUTSRC_H__
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/*--------------------------Define -------------------------------------------*/
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#define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0)
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#define AGC_DIFF_CONFIG_MP(ic, band) (ODM_ReadAndConfig_MP_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_MP_##ic##_AGC_TAB_DIFF_##band, \
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sizeof(Array_MP_##ic##_AGC_TAB_DIFF_##band)/sizeof(u4Byte)))
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#define AGC_DIFF_CONFIG_TC(ic, band) (ODM_ReadAndConfig_TC_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_TC_##ic##_AGC_TAB_DIFF_##band, \
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sizeof(Array_TC_##ic##_AGC_TAB_DIFF_##band)/sizeof(u4Byte)))
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#define AGC_DIFF_CONFIG(ic, band) do {\
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if (pDM_Odm->bIsMPChip)\
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AGC_DIFF_CONFIG_MP(ic,band);\
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else\
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AGC_DIFF_CONFIG_TC(ic,band);\
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} while(0)
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//============================================================
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// structure and define
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//============================================================
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typedef struct _Phy_Rx_AGC_Info
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{
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#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
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u1Byte gain:7,trsw:1;
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#else
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u1Byte trsw:1,gain:7;
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#endif
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} PHY_RX_AGC_INFO_T,*pPHY_RX_AGC_INFO_T;
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typedef struct _Phy_Status_Rpt_8192cd
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{
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PHY_RX_AGC_INFO_T path_agc[2];
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u1Byte ch_corr[2];
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u1Byte cck_sig_qual_ofdm_pwdb_all;
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u1Byte cck_agc_rpt_ofdm_cfosho_a;
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u1Byte cck_rpt_b_ofdm_cfosho_b;
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u1Byte rsvd_1;//ch_corr_msb;
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u1Byte noise_power_db_msb;
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s1Byte path_cfotail[2];
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u1Byte pcts_mask[2];
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s1Byte stream_rxevm[2];
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u1Byte path_rxsnr[2];
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u1Byte noise_power_db_lsb;
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u1Byte rsvd_2[3];
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u1Byte stream_csi[2];
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u1Byte stream_target_csi[2];
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s1Byte sig_evm;
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u1Byte rsvd_3;
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#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
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u1Byte antsel_rx_keep_2:1; //ex_intf_flg:1;
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u1Byte sgi_en:1;
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u1Byte rxsc:2;
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u1Byte idle_long:1;
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u1Byte r_ant_train_en:1;
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u1Byte ant_sel_b:1;
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u1Byte ant_sel:1;
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#else // _BIG_ENDIAN_
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u1Byte ant_sel:1;
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u1Byte ant_sel_b:1;
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u1Byte r_ant_train_en:1;
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u1Byte idle_long:1;
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u1Byte rxsc:2;
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u1Byte sgi_en:1;
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u1Byte antsel_rx_keep_2:1; //ex_intf_flg:1;
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#endif
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} PHY_STATUS_RPT_8192CD_T,*PPHY_STATUS_RPT_8192CD_T;
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typedef struct _Phy_Status_Rpt_8812
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{
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#if 0
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PHY_RX_AGC_INFO_T path_agc[2];
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u1Byte ch_num[2];
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u1Byte cck_sig_qual_ofdm_pwdb_all;
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u1Byte cck_agc_rpt_ofdm_cfosho_a;
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u1Byte cck_bb_pwr_ofdm_cfosho_b;
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u1Byte cck_rx_path; //CCK_RX_PATH [3:0] (with regA07[3:0] definition)
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u1Byte rsvd_1;
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u1Byte path_cfotail[2];
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u1Byte pcts_mask[2];
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s1Byte stream_rxevm[2];
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u1Byte path_rxsnr[2];
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u1Byte rsvd_2[2];
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u1Byte stream_snr[2];
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u1Byte stream_csi[2];
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u1Byte rsvd_3[2];
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s1Byte sig_evm;
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u1Byte rsvd_4;
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#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
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u1Byte antidx_anta:3;
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u1Byte antidx_antb:3;
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u1Byte rsvd_5:2;
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#else // _BIG_ENDIAN_
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u1Byte rsvd_5:2;
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u1Byte antidx_antb:3;
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u1Byte antidx_anta:3;
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#endif
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#endif
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//2012.05.24 LukeLee: This structure should take big/little endian in consideration later.....
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//DWORD 0
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u1Byte gain_trsw[2];
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#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
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u2Byte chl_num:10;
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u2Byte sub_chnl:4;
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u2Byte r_RFMOD:2;
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#else // _BIG_ENDIAN_
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u2Byte r_RFMOD:2;
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u2Byte sub_chnl:4;
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u2Byte chl_num:10;
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#endif
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//DWORD 1
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u1Byte pwdb_all;
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u1Byte cfosho[4]; // DW 1 byte 1 DW 2 byte 0
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//DWORD 2
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s1Byte cfotail[4]; // DW 2 byte 1 DW 3 byte 0
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//DWORD 3
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s1Byte rxevm[2]; // DW 3 byte 1 DW 3 byte 2
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s1Byte rxsnr[2]; // DW 3 byte 3 DW 4 byte 0
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//DWORD 4
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u1Byte PCTS_MSK_RPT[2];
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u1Byte pdsnr[2]; // DW 4 byte 3 DW 5 Byte 0
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//DWORD 5
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u1Byte csi_current[2];
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u1Byte rx_gain_c;
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//DWORD 6
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u1Byte rx_gain_d;
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s1Byte sigevm;
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u1Byte resvd_0;
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u1Byte antidx_anta:3;
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u1Byte antidx_antb:3;
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u1Byte resvd_1:2;
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} PHY_STATUS_RPT_8812_T,*PPHY_STATUS_RPT_8812_T;
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VOID
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odm_Init_RSSIForDM(
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IN OUT PDM_ODM_T pDM_Odm
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);
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VOID
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ODM_PhyStatusQuery(
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IN OUT PDM_ODM_T pDM_Odm,
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OUT PODM_PHY_INFO_T pPhyInfo,
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IN pu1Byte pPhyStatus,
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IN PODM_PACKET_INFO_T pPktinfo
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);
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VOID
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ODM_MacStatusQuery(
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IN OUT PDM_ODM_T pDM_Odm,
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IN pu1Byte pMacStatus,
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IN u1Byte MacID,
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IN BOOLEAN bPacketMatchBSSID,
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IN BOOLEAN bPacketToSelf,
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IN BOOLEAN bPacketBeacon
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);
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#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE|ODM_AP))
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HAL_STATUS
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ODM_ConfigRFWithTxPwrTrackHeaderFile(
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IN PDM_ODM_T pDM_Odm
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);
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HAL_STATUS
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ODM_ConfigRFWithHeaderFile(
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IN PDM_ODM_T pDM_Odm,
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IN ODM_RF_Config_Type ConfigType,
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IN ODM_RF_RADIO_PATH_E eRFPath
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);
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HAL_STATUS
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ODM_ConfigBBWithHeaderFile(
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IN PDM_ODM_T pDM_Odm,
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IN ODM_BB_Config_Type ConfigType
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);
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HAL_STATUS
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ODM_ConfigMACWithHeaderFile(
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IN PDM_ODM_T pDM_Odm
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);
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HAL_STATUS
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ODM_ConfigFWWithHeaderFile(
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IN PDM_ODM_T pDM_Odm,
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IN ODM_FW_Config_Type ConfigType,
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OUT u1Byte *pFirmware,
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OUT u4Byte *pSize
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);
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u4Byte
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ODM_GetHWImgVersion(
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IN PDM_ODM_T pDM_Odm
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);
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s4Byte
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odm_SignalScaleMapping(
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IN OUT PDM_ODM_T pDM_Odm,
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IN s4Byte CurrSig
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);
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#endif
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#endif
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