/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#ifndef __HALDMOUTSRC_H__
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#define __HALDMOUTSRC_H__
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/*============================================================*/
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/*include files*/
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/*============================================================*/
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#include "phydm_pre_define.h"
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#include "phydm_dig.h"
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#if PHYDM_SUPPORT_EDCA
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#include "phydm_edcaturbocheck.h"
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#endif
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#include "phydm_pathdiv.h"
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#include "phydm_antdiv.h"
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#include "phydm_antdect.h"
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#include "phydm_dynamicbbpowersaving.h"
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#include "phydm_rainfo.h"
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#include "phydm_dynamictxpower.h"
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#include "phydm_cfotracking.h"
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#include "phydm_acs.h"
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#include "phydm_adaptivity.h"
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#include "phydm_iqk.h"
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#include "phydm_dfs.h"
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#include "phydm_ccx.h"
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#include "txbf/phydm_hal_txbf_api.h"
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#include "phydm_adc_sampling.h"
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#include "phydm_dynamic_rx_path.h"
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#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN))
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#include "phydm_beamforming.h"
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#endif
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#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
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#include "halphyrf_ap.h"
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#endif
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#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
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#include "phydm_noisemonitor.h"
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#include "halphyrf_ce.h"
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#endif
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#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
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#include "halphyrf_win.h"
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#include "phydm_noisemonitor.h"
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#endif
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/*============================================================*/
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/*Definition */
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/*============================================================*/
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/* Traffic load decision */
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#define TRAFFIC_ULTRA_LOW 1
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#define TRAFFIC_LOW 2
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#define TRAFFIC_MID 3
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#define TRAFFIC_HIGH 4
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#define NONE 0
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/*NBI API------------------------------------*/
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#define NBI_ENABLE 1
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#define NBI_DISABLE 2
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#define NBI_TABLE_SIZE_128 27
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#define NBI_TABLE_SIZE_256 59
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#define NUM_START_CH_80M 7
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#define NUM_START_CH_40M 14
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#define CH_OFFSET_40M 2
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#define CH_OFFSET_80M 6
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/*CSI MASK API------------------------------------*/
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#define CSI_MASK_ENABLE 1
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#define CSI_MASK_DISABLE 2
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/*------------------------------------------------*/
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#define FFT_128_TYPE 1
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#define FFT_256_TYPE 2
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#define SET_SUCCESS 1
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#define SET_ERROR 2
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#define SET_NO_NEED 3
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#define FREQ_POSITIVE 1
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#define FREQ_NEGATIVE 2
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#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
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#define PHYDM_WATCH_DOG_PERIOD 1
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#else
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#define PHYDM_WATCH_DOG_PERIOD 2
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#endif
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/*============================================================*/
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/*structure and define*/
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/*============================================================*/
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/*2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement.*/
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/*We need to remove to other position???*/
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#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN))
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struct rtl8192cd_priv {
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u8 temp;
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};
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#endif
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#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
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struct _ADAPTER {
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u8 temp;
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#ifdef AP_BUILD_WORKAROUND
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HAL_DATA_TYPE *temp2;
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struct rtl8192cd_priv *priv;
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#endif
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};
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#endif
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#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
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struct _WLAN_STA {
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u8 temp;
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};
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#endif
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struct _dynamic_primary_cca {
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u8 pri_cca_flag;
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u8 intf_flag;
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u8 intf_type;
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u8 dup_rts_flag;
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u8 monitor_flag;
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u8 CH_offset;
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u8 MF_state;
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};
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#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
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#ifdef ADSL_AP_BUILD_WORKAROUND
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#define MAX_TOLERANCE 5
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#define IQK_DELAY_TIME 1 /*ms*/
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#endif
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#endif /*#if(DM_ODM_SUPPORT_TYPE & (ODM_AP))*/
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#define dm_type_by_fw 0
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#define dm_type_by_driver 1
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/*Declare for common info*/
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#define IQK_THRESHOLD 8
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#define DPK_THRESHOLD 4
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#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
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__PACK struct _odm_phy_status_info_ {
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u8 rx_pwdb_all;
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u8 signal_quality; /* in 0-100 index. */
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u8 rx_mimo_signal_strength[4]; /* in 0~100 index */
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s8 rx_mimo_signal_quality[4]; /* EVM */
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s8 rx_snr[4]; /* per-path's SNR */
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#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
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u8 rx_count:2; /* RX path counter---*/
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u8 band_width:2;
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u8 rxsc:4; /* sub-channel---*/
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#else
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u8 band_width;
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#endif
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#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
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u8 channel; /* channel number---*/
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bool is_mu_packet; /* is MU packet or not---*/
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bool is_beamformed; /* BF packet---*/
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#endif
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};
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struct _odm_phy_status_info_append_ {
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u8 MAC_CRC32;
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};
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#else
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struct _odm_phy_status_info_ {
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/* */
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/* Be care, if you want to add any element please insert between */
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/* rx_pwdb_all & signal_strength. */
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/* */
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#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
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u32 rx_pwdb_all;
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#else
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u8 rx_pwdb_all;
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#endif
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u8 signal_quality; /* in 0-100 index. */
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s8 rx_mimo_signal_quality[4]; /* per-path's EVM translate to 0~100% */
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u8 rx_mimo_evm_dbm[4]; /* per-path's original EVM (dbm) */
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u8 rx_mimo_signal_strength[4]; /* in 0~100 index */
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s16 cfo_short[4]; /* per-path's cfo_short */
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s16 cfo_tail[4]; /* per-path's cfo_tail */
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s8 rx_power; /* in dBm Translate from PWdB */
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s8 recv_signal_power; /* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */
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u8 bt_rx_rssi_percentage;
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u8 signal_strength; /* in 0-100 index. */
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s8 rx_pwr[4]; /* per-path's pwdb */
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s8 rx_snr[4]; /* per-path's SNR */
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/* s8 BB_Backup[13]; backup reg. */
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#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
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u8 rx_count:2; /* RX path counter---*/
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u8 band_width:2;
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u8 rxsc:4; /* sub-channel---*/
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#else
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u8 band_width;
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#endif
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#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
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u8 bt_coex_pwr_adjust;
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#endif
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#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
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u8 channel; /* channel number---*/
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bool is_mu_packet; /* is MU packet or not---*/
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bool is_beamformed; /* BF packet---*/
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#endif
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};
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#endif
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struct _odm_per_pkt_info_ {
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u8 data_rate;
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u8 station_id;
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bool is_packet_match_bssid;
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bool is_packet_to_self;
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bool is_packet_beacon;
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bool is_to_self;
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u8 ppdu_cnt;
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};
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struct _odm_phy_dbg_info_ {
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/*ODM Write,debug info*/
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s8 rx_snr_db[4];
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u32 num_qry_phy_status;
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u32 num_qry_phy_status_cck;
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u32 num_qry_phy_status_ofdm;
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#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
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u32 num_qry_mu_pkt;
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u32 num_qry_bf_pkt;
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u32 num_qry_mu_vht_pkt[40];
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u32 num_qry_vht_pkt[40];
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bool is_ldpc_pkt;
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bool is_stbc_pkt;
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u8 num_of_ppdu[4];
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u8 gid_num[4];
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#endif
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u8 num_qry_beacon_pkt;
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/* Others */
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s32 rx_evm[4];
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};
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/*2011/20/20 MH For MP driver RT_WLAN_STA = struct sta_info*/
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/*Please declare below ODM relative info in your STA info structure.*/
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#if 1
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struct _ODM_STA_INFO {
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/*Driver Write*/
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bool is_used; /*record the sta status link or not?*/
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u8 iot_peer; /*Enum value. HT_IOT_PEER_E*/
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/*ODM Write*/
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/*PHY_STATUS_INFO*/
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u8 rssi_path[4];
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u8 rssi_ave;
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u8 RXEVM[4];
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u8 RXSNR[4];
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};
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#endif
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enum odm_cmninfo_e {
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/*Fixed value*/
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/*-----------HOOK BEFORE REG INIT-----------*/
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ODM_CMNINFO_PLATFORM = 0,
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ODM_CMNINFO_ABILITY,
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ODM_CMNINFO_INTERFACE,
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ODM_CMNINFO_MP_TEST_CHIP,
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ODM_CMNINFO_IC_TYPE,
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ODM_CMNINFO_CUT_VER,
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ODM_CMNINFO_FAB_VER,
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ODM_CMNINFO_RF_TYPE,
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ODM_CMNINFO_RFE_TYPE,
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ODM_CMNINFO_BOARD_TYPE,
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ODM_CMNINFO_PACKAGE_TYPE,
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ODM_CMNINFO_EXT_LNA,
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ODM_CMNINFO_5G_EXT_LNA,
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ODM_CMNINFO_EXT_PA,
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ODM_CMNINFO_5G_EXT_PA,
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ODM_CMNINFO_GPA,
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ODM_CMNINFO_APA,
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ODM_CMNINFO_GLNA,
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ODM_CMNINFO_ALNA,
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ODM_CMNINFO_EXT_TRSW,
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ODM_CMNINFO_EXT_LNA_GAIN,
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ODM_CMNINFO_PATCH_ID,
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ODM_CMNINFO_BINHCT_TEST,
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ODM_CMNINFO_BWIFI_TEST,
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ODM_CMNINFO_SMART_CONCURRENT,
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ODM_CMNINFO_CONFIG_BB_RF,
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ODM_CMNINFO_DOMAIN_CODE_2G,
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ODM_CMNINFO_DOMAIN_CODE_5G,
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ODM_CMNINFO_IQKFWOFFLOAD,
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ODM_CMNINFO_IQKPAOFF,
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ODM_CMNINFO_HUBUSBMODE,
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ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS,
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ODM_CMNINFO_TX_TP,
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ODM_CMNINFO_RX_TP,
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ODM_CMNINFO_SOUNDING_SEQ,
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ODM_CMNINFO_REGRFKFREEENABLE,
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ODM_CMNINFO_RFKFREEENABLE,
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ODM_CMNINFO_NORMAL_RX_PATH_CHANGE,
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ODM_CMNINFO_EFUSE0X3D8,
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ODM_CMNINFO_EFUSE0X3D7,
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/*-----------HOOK BEFORE REG INIT-----------*/
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/*Dynamic value:*/
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/*--------- POINTER REFERENCE-----------*/
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ODM_CMNINFO_MAC_PHY_MODE,
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ODM_CMNINFO_TX_UNI,
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ODM_CMNINFO_RX_UNI,
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ODM_CMNINFO_WM_MODE,
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ODM_CMNINFO_BAND,
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ODM_CMNINFO_SEC_CHNL_OFFSET,
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ODM_CMNINFO_SEC_MODE,
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ODM_CMNINFO_BW,
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ODM_CMNINFO_CHNL,
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ODM_CMNINFO_FORCED_RATE,
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ODM_CMNINFO_ANT_DIV,
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ODM_CMNINFO_ADAPTIVITY,
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ODM_CMNINFO_DMSP_GET_VALUE,
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ODM_CMNINFO_BUDDY_ADAPTOR,
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ODM_CMNINFO_DMSP_IS_MASTER,
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ODM_CMNINFO_SCAN,
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ODM_CMNINFO_POWER_SAVING,
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ODM_CMNINFO_ONE_PATH_CCA,
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ODM_CMNINFO_DRV_STOP,
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ODM_CMNINFO_PNP_IN,
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ODM_CMNINFO_INIT_ON,
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ODM_CMNINFO_ANT_TEST,
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ODM_CMNINFO_NET_CLOSED,
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ODM_CMNINFO_FORCED_IGI_LB,
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ODM_CMNINFO_P2P_LINK,
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ODM_CMNINFO_FCS_MODE,
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ODM_CMNINFO_IS1ANTENNA,
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ODM_CMNINFO_RFDEFAULTPATH,
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ODM_CMNINFO_DFS_MASTER_ENABLE,
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ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC,
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ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA,
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/*--------- POINTER REFERENCE-----------*/
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/*------------CALL BY VALUE-------------*/
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ODM_CMNINFO_WIFI_DIRECT,
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ODM_CMNINFO_WIFI_DISPLAY,
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ODM_CMNINFO_LINK_IN_PROGRESS,
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ODM_CMNINFO_LINK,
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ODM_CMNINFO_STATION_STATE,
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ODM_CMNINFO_RSSI_MIN,
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ODM_CMNINFO_DBG_COMP,
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ODM_CMNINFO_DBG_LEVEL,
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ODM_CMNINFO_RA_THRESHOLD_HIGH,
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ODM_CMNINFO_RA_THRESHOLD_LOW,
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ODM_CMNINFO_RF_ANTENNA_TYPE,
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ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH,
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ODM_CMNINFO_BE_FIX_TX_ANT,
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ODM_CMNINFO_BT_ENABLED,
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ODM_CMNINFO_BT_HS_CONNECT_PROCESS,
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ODM_CMNINFO_BT_HS_RSSI,
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ODM_CMNINFO_BT_OPERATION,
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ODM_CMNINFO_BT_LIMITED_DIG,
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ODM_CMNINFO_BT_DIG,
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ODM_CMNINFO_BT_BUSY,
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ODM_CMNINFO_BT_DISABLE_EDCA,
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#if (DM_ODM_SUPPORT_TYPE & ODM_AP) /*for repeater mode add by YuChen 2014.06.23*/
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#ifdef UNIVERSAL_REPEATER
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ODM_CMNINFO_VXD_LINK,
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#endif
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#endif
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ODM_CMNINFO_AP_TOTAL_NUM,
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ODM_CMNINFO_POWER_TRAINING,
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ODM_CMNINFO_DFS_REGION_DOMAIN,
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/*------------CALL BY VALUE-------------*/
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/*Dynamic ptr array hook itms.*/
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ODM_CMNINFO_STA_STATUS,
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ODM_CMNINFO_MAX,
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};
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enum phydm_info_query_e {
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PHYDM_INFO_FA_OFDM,
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PHYDM_INFO_FA_CCK,
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PHYDM_INFO_FA_TOTAL,
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PHYDM_INFO_CCA_OFDM,
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PHYDM_INFO_CCA_CCK,
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PHYDM_INFO_CCA_ALL,
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PHYDM_INFO_CRC32_OK_VHT,
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PHYDM_INFO_CRC32_OK_HT,
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PHYDM_INFO_CRC32_OK_LEGACY,
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PHYDM_INFO_CRC32_OK_CCK,
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PHYDM_INFO_CRC32_ERROR_VHT,
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PHYDM_INFO_CRC32_ERROR_HT,
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PHYDM_INFO_CRC32_ERROR_LEGACY,
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PHYDM_INFO_CRC32_ERROR_CCK,
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PHYDM_INFO_EDCCA_FLAG,
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PHYDM_INFO_OFDM_ENABLE,
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PHYDM_INFO_CCK_ENABLE,
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PHYDM_INFO_DBG_PORT_0
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};
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enum phydm_api_e {
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PHYDM_API_NBI = 1,
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PHYDM_API_CSI_MASK,
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};
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/*2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY*/
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enum odm_ability_e {
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/*BB ODM section BIT 0-19*/
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ODM_BB_DIG = BIT(0),
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ODM_BB_RA_MASK = BIT(1),
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ODM_BB_DYNAMIC_TXPWR = BIT(2),
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ODM_BB_FA_CNT = BIT(3),
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ODM_BB_RSSI_MONITOR = BIT(4),
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ODM_BB_CCK_PD = BIT(5),
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ODM_BB_ANT_DIV = BIT(6),
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ODM_BB_PWR_TRAIN = BIT(8),
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ODM_BB_RATE_ADAPTIVE = BIT(9),
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ODM_BB_PATH_DIV = BIT(10),
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ODM_BB_ADAPTIVITY = BIT(13),
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ODM_BB_CFO_TRACKING = BIT(14),
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ODM_BB_NHM_CNT = BIT(15),
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ODM_BB_PRIMARY_CCA = BIT(16),
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ODM_BB_TXBF = BIT(17),
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ODM_BB_DYNAMIC_ARFR = BIT(18),
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ODM_MAC_EDCA_TURBO = BIT(20),
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ODM_BB_DYNAMIC_RX_PATH = BIT(21),
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/*RF ODM section BIT 24-31*/
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ODM_RF_TX_PWR_TRACK = BIT(24),
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ODM_RF_RX_GAIN_TRACK = BIT(25),
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ODM_RF_CALIBRATION = BIT(26),
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};
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/*ODM_CMNINFO_ONE_PATH_CCA*/
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enum odm_cca_path_e {
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ODM_CCA_2R = 0,
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ODM_CCA_1R_A = 1,
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ODM_CCA_1R_B = 2,
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};
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enum cca_pathdiv_en_e {
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CCA_PATHDIV_DISABLE = 0,
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CCA_PATHDIV_ENABLE = 1,
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};
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enum phy_reg_pg_type {
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PHY_REG_PG_RELATIVE_VALUE = 0,
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PHY_REG_PG_EXACT_VALUE = 1
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};
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/*2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration.*/
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#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
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#if (RT_PLATFORM != PLATFORM_LINUX)
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typedef
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#endif
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struct PHY_DM_STRUCT
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#else/*for AP,ADSL,CE Team*/
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struct PHY_DM_STRUCT
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#endif
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{
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/*Add for different team use temporarily*/
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struct _ADAPTER *adapter; /*For CE/NIC team*/
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struct rtl8192cd_priv *priv; /*For AP/ADSL team*/
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/*WHen you use adapter or priv pointer, you must make sure the pointer is ready.*/
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bool odm_ready;
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#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN))
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struct rtl8192cd_priv fake_priv;
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#endif
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#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
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/* ADSL_AP_BUILD_WORKAROUND */
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struct _ADAPTER fake_adapter;
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#endif
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enum phy_reg_pg_type phy_reg_pg_value_type;
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u8 phy_reg_pg_version;
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u32 debug_components;
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u32 fw_debug_components;
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u32 debug_level;
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u32 num_qry_phy_status_all; /*CCK + OFDM*/
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u32 last_num_qry_phy_status_all;
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u32 rx_pwdb_ave;
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bool MPDIG_2G; /*off MPDIG*/
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u8 times_2g;
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bool is_init_hw_info_by_rfe;
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/*------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/
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bool is_cck_high_power;
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u8 rf_path_rx_enable;
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u8 control_channel;
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/*------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/
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/* 1 COMMON INFORMATION */
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/*Init value*/
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/*-----------HOOK BEFORE REG INIT-----------*/
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/*ODM Platform info AP/ADSL/CE/MP = 1/2/3/4*/
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u8 support_platform;
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/* ODM Platform info WIN/AP/CE = 1/2/3 */
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u8 normal_rx_path;
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/*ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K*/
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u32 support_ability;
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/*ODM PCIE/USB/SDIO = 1/2/3*/
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u8 support_interface;
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/*ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/...*/
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u32 support_ic_type;
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/*cut version TestChip/A-cut/B-cut... = 0/1/2/3/...*/
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u8 cut_version;
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/*Fab version TSMC/UMC = 0/1*/
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u8 fab_version;
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/*RF type 4T4R/3T3R/2T2R/1T2R/1T1R/...*/
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u8 rf_type;
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u8 rfe_type;
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/*Board type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/...*/
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u8 board_type;
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u8 package_type;
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u16 type_glna;
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u16 type_gpa;
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u16 type_alna;
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u16 type_apa;
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/*with external LNA NO/Yes = 0/1*/
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u8 ext_lna; /*2G*/
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u8 ext_lna_5g; /*5G*/
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/*with external PA NO/Yes = 0/1*/
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u8 ext_pa; /*2G*/
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u8 ext_pa_5g; /*5G*/
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/*with Efuse number*/
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u8 efuse0x3d7;
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u8 efuse0x3d8;
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/*with external TRSW NO/Yes = 0/1*/
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u8 ext_trsw;
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u8 ext_lna_gain; /*2G*/
|
u8 patch_id; /*Customer ID*/
|
bool is_in_hct_test;
|
u8 wifi_test;
|
|
bool is_dual_mac_smart_concurrent;
|
u32 bk_support_ability;
|
u8 ant_div_type;
|
u8 with_extenal_ant_switch;
|
bool config_bbrf;
|
u8 odm_regulation_2_4g;
|
u8 odm_regulation_5g;
|
u8 iqk_fw_offload;
|
bool cck_new_agc;
|
u8 phydm_period;
|
u32 phydm_sys_up_time;
|
u8 num_rf_path;
|
u8 is_receiver_blocking_en;
|
/*-----------HOOK BEFORE REG INIT-----------*/
|
|
/*Dynamic value*/
|
|
/*--------- POINTER REFERENCE-----------*/
|
|
u8 u1_byte_temp;
|
bool BOOLEAN_temp;
|
struct _ADAPTER *PADAPTER_temp;
|
|
/*MAC PHY mode SMSP/DMSP/DMDP = 0/1/2*/
|
u8 *p_mac_phy_mode;
|
/*TX Unicast byte count*/
|
u64 *p_num_tx_bytes_unicast;
|
/*RX Unicast byte count*/
|
u64 *p_num_rx_bytes_unicast;
|
/*Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3*/
|
u8 *p_wireless_mode;
|
/*Frequence band 2.4G/5G = 0/1*/
|
u8 *p_band_type;
|
/*Secondary channel offset don't_care/below/above = 0/1/2*/
|
u8 *p_sec_ch_offset;
|
/*security mode Open/WEP/AES/TKIP = 0/1/2/3*/
|
u8 *p_security;
|
/*BW info 20M/40M/80M = 0/1/2*/
|
u8 *p_band_width;
|
/*Central channel location Ch1/Ch2/....*/
|
u8 *p_channel; /*central channel number*/
|
bool dpk_done;
|
/*Common info for 92D DMSP*/
|
|
bool *p_is_get_value_from_other_mac;
|
struct _ADAPTER **p_buddy_adapter;
|
bool *p_is_master_of_dmsp; /* MAC0: master, MAC1: slave */
|
/*Common info for status*/
|
bool *p_is_scan_in_process;
|
bool *p_is_power_saving;
|
/*CCA path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path_e.*/
|
u8 *p_one_path_cca;
|
u8 *p_antenna_test;
|
bool *p_is_net_closed;
|
u8 *pu1_forced_igi_lb;
|
bool *p_is_fcs_mode_enable;
|
/*--------- For 8723B IQK-----------*/
|
bool *p_is_1_antenna;
|
u8 *p_rf_default_path;
|
/* 0:S1, 1:S0 */
|
|
/*--------- POINTER REFERENCE-----------*/
|
u16 *p_forced_data_rate;
|
u8 *p_enable_antdiv;
|
u8 *p_enable_adaptivity;
|
u8 *hub_usb_mode;
|
bool *p_is_fw_dw_rsvd_page_in_progress;
|
u32 *p_current_tx_tp;
|
u32 *p_current_rx_tp;
|
u8 *p_sounding_seq;
|
/*------------CALL BY VALUE-------------*/
|
bool is_link_in_process;
|
bool is_wifi_direct;
|
bool is_wifi_display;
|
bool is_linked;
|
bool bsta_state;
|
#if (DM_ODM_SUPPORT_TYPE & ODM_AP) /*for repeater mode add by YuChen 2014.06.23*/
|
#ifdef UNIVERSAL_REPEATER
|
bool vxd_linked;
|
#endif
|
#endif
|
u8 rssi_min;
|
u8 interface_index; /*Add for 92D dual MAC: 0--Mac0 1--Mac1*/
|
bool is_mp_chip;
|
bool is_one_entry_only;
|
bool mp_mode;
|
u32 one_entry_macid;
|
u8 pre_number_linked_client;
|
u8 number_linked_client;
|
u8 pre_number_active_client;
|
u8 number_active_client;
|
/*Common info for BTDM*/
|
bool is_bt_enabled; /*BT is enabled*/
|
bool is_bt_connect_process; /*BT HS is under connection progress.*/
|
u8 bt_hs_rssi; /*BT HS mode wifi rssi value.*/
|
bool is_bt_hs_operation; /*BT HS mode is under progress*/
|
u8 bt_hs_dig_val; /*use BT rssi to decide the DIG value*/
|
bool is_bt_disable_edca_turbo; /*Under some condition, don't enable the EDCA Turbo*/
|
bool is_bt_busy; /*BT is busy.*/
|
bool is_bt_limited_dig; /*BT is busy.*/
|
bool is_disable_phy_api;
|
/*------------CALL BY VALUE-------------*/
|
u8 RSSI_A;
|
u8 RSSI_B;
|
u8 RSSI_C;
|
u8 RSSI_D;
|
u64 RSSI_TRSW;
|
u64 RSSI_TRSW_H;
|
u64 RSSI_TRSW_L;
|
u64 RSSI_TRSW_iso;
|
u8 tx_ant_status;
|
u8 rx_ant_status;
|
u8 cck_lna_idx;
|
u8 cck_vga_idx;
|
u8 curr_station_id;
|
u8 ofdm_agc_idx[4];
|
|
u8 rx_rate;
|
bool is_noisy_state;
|
u8 tx_rate;
|
u8 linked_interval;
|
u8 pre_channel;
|
u32 txagc_offset_value_a;
|
bool is_txagc_offset_positive_a;
|
u32 txagc_offset_value_b;
|
bool is_txagc_offset_positive_b;
|
u32 tx_tp;
|
u32 rx_tp;
|
u32 total_tp;
|
u64 cur_tx_ok_cnt;
|
u64 cur_rx_ok_cnt;
|
u64 last_tx_ok_cnt;
|
u64 last_rx_ok_cnt;
|
u16 consecutive_idlel_time; /*unit: second*/
|
u32 bb_swing_offset_a;
|
bool is_bb_swing_offset_positive_a;
|
u32 bb_swing_offset_b;
|
bool is_bb_swing_offset_positive_b;
|
u8 igi_lower_bound;
|
u8 igi_upper_bound;
|
u8 antdiv_rssi;
|
u8 fat_comb_a;
|
u8 fat_comb_b;
|
u8 antdiv_intvl;
|
u8 ant_type;
|
u8 pre_ant_type;
|
u8 antdiv_period;
|
u8 evm_antdiv_period;
|
u8 antdiv_select;
|
u8 path_select;
|
u8 antdiv_evm_en;
|
u8 bdc_holdstate;
|
u8 ndpa_period;
|
bool h2c_rarpt_connect;
|
bool cck_agc_report_type;
|
|
u8 dm_dig_max_TH;
|
u8 dm_dig_min_TH;
|
u8 print_agc;
|
u8 traffic_load;
|
u8 pre_traffic_load;
|
/*8821C Antenna BTG/WLG/WLA Select*/
|
u8 current_rf_set_8821c;
|
u8 default_rf_set_8821c;
|
/*For Adaptivtiy*/
|
u16 nhm_cnt_0;
|
u16 nhm_cnt_1;
|
s8 TH_L2H_default;
|
s8 th_edcca_hl_diff_default;
|
s8 th_l2h_ini;
|
s8 th_edcca_hl_diff;
|
s8 th_l2h_ini_mode2;
|
s8 th_edcca_hl_diff_mode2;
|
bool carrier_sense_enable;
|
u8 adaptivity_igi_upper;
|
bool adaptivity_flag;
|
u8 dc_backoff;
|
bool adaptivity_enable;
|
u8 ap_total_num;
|
bool edcca_enable;
|
struct _ADAPTIVITY_STATISTICS adaptivity;
|
/*For Adaptivtiy*/
|
u8 last_usb_hub;
|
u8 tx_bf_data_rate;
|
|
u8 nbi_set_result;
|
|
u8 c2h_cmd_start;
|
u8 fw_debug_trace[60];
|
u8 pre_c2h_seq;
|
bool fw_buff_is_enpty;
|
u32 data_frame_num;
|
|
/*for noise detection*/
|
bool noisy_decision; /*b_noisy*/
|
bool pre_b_noisy;
|
u32 noisy_decision_smooth;
|
bool is_disable_dym_ecs;
|
|
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN))
|
struct _ODM_NOISE_MONITOR_ noise_level;
|
#endif
|
/*Define STA info.*/
|
/*_ODM_STA_INFO*/
|
/*2012/01/12 MH For MP, we need to reduce one array pointer for default port.??*/
|
struct sta_info *p_odm_sta_info[ODM_ASSOCIATE_ENTRY_NUM];
|
u16 platform2phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM];
|
/* platform_macid_table[platform_macid] = phydm_macid */
|
#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
|
s32 accumulate_pwdb[ODM_ASSOCIATE_ENTRY_NUM];
|
#endif
|
|
#if (RATE_ADAPTIVE_SUPPORT == 1)
|
u16 currmin_rpt_time;
|
struct _odm_ra_info_ ra_info[ODM_ASSOCIATE_ENTRY_NUM];
|
/*Use mac_id as array index. STA mac_id=0, VWiFi Client mac_id={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119*/
|
#endif
|
|
/*2012/02/14 MH Add to share 88E ra with other SW team.*/
|
/*We need to colelct all support abilit to a proper area.*/
|
|
bool ra_support88e;
|
|
struct _odm_phy_dbg_info_ phy_dbg_info;
|
|
/*ODM Structure*/
|
#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
|
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
struct _BF_DIV_COEX_ dm_bdc_table;
|
#endif
|
|
#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
|
struct _SMART_ANTENNA_TRAINNING_ dm_sat_table;
|
#endif
|
|
#endif
|
struct _FAST_ANTENNA_TRAINNING_ dm_fat_table;
|
struct _dynamic_initial_gain_threshold_ dm_dig_table;
|
#if (defined(CONFIG_BB_POWER_SAVING))
|
struct _dynamic_power_saving dm_ps_table;
|
#endif
|
struct _dynamic_primary_cca dm_pri_cca;
|
struct _rate_adaptive_table_ dm_ra_table;
|
struct _FALSE_ALARM_STATISTICS false_alm_cnt;
|
struct _FALSE_ALARM_STATISTICS flase_alm_cnt_buddy_adapter;
|
struct _sw_antenna_switch_ dm_swat_table;
|
struct _CFO_TRACKING_ dm_cfo_track;
|
struct _ACS_ dm_acs;
|
struct _CCX_INFO dm_ccx_info;
|
#if (PHYDM_LA_MODE_SUPPORT == 1)
|
struct _RT_ADCSMP adcsmp;
|
#endif
|
#if (CONFIG_DYNAMIC_RX_PATH == 1)
|
struct _DYNAMIC_RX_PATH_ dm_drp_table;
|
#endif
|
|
#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
|
struct _IQK_INFORMATION IQK_info;
|
#endif
|
|
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
/*path Div Struct*/
|
struct _path_div_parameter_define_ path_iqk;
|
#endif
|
#if (defined(CONFIG_PATH_DIVERSITY))
|
struct _ODM_PATH_DIVERSITY_ dm_path_div;
|
#endif
|
|
#if PHYDM_SUPPORT_EDCA
|
struct _EDCA_TURBO_ dm_edca_table;
|
u32 WMMEDCA_BE;
|
#endif
|
|
bool *p_is_driver_stopped;
|
bool *p_is_driver_is_going_to_pnp_set_power_sleep;
|
bool *pinit_adpt_in_progress;
|
|
/*PSD*/
|
bool is_user_assign_level;
|
u8 RSSI_BT; /*come from BT*/
|
bool is_psd_in_process;
|
bool is_psd_active;
|
bool is_dm_initial_gain_enable;
|
|
/*MPT DIG*/
|
struct timer_list mpt_dig_timer;
|
|
/*for rate adaptive, in fact, 88c/92c fw will handle this*/
|
u8 is_use_ra_mask;
|
|
struct _ODM_RATE_ADAPTIVE rate_adaptive;
|
#if (defined(CONFIG_ANT_DETECTION))
|
struct _ANT_DETECTED_INFO ant_detected_info; /* Antenna detected information for RSSI tool*/
|
#endif
|
struct odm_rf_calibration_structure rf_calibrate_info;
|
u32 n_iqk_cnt;
|
u32 n_iqk_ok_cnt;
|
u32 n_iqk_fail_cnt;
|
|
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
/*Power Training*/
|
u8 force_power_training_state;
|
bool is_change_state;
|
u32 PT_score;
|
u64 ofdm_rx_cnt;
|
u64 cck_rx_cnt;
|
#endif
|
bool is_disable_power_training;
|
u8 dynamic_tx_high_power_lvl;
|
u8 last_dtp_lvl;
|
u32 tx_agc_ofdm_18_6;
|
u8 rx_pkt_type;
|
|
/*ODM relative time.*/
|
struct timer_list path_div_switch_timer;
|
/*2011.09.27 add for path Diversity*/
|
struct timer_list cck_path_diversity_timer;
|
struct timer_list fast_ant_training_timer;
|
#ifdef ODM_EVM_ENHANCE_ANTDIV
|
struct timer_list evm_fast_ant_training_timer;
|
#endif
|
struct timer_list sbdcnt_timer;
|
|
/*ODM relative workitem.*/
|
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
#if USE_WORKITEM
|
RT_WORK_ITEM path_div_switch_workitem;
|
RT_WORK_ITEM cck_path_diversity_workitem;
|
RT_WORK_ITEM fast_ant_training_workitem;
|
RT_WORK_ITEM mpt_dig_workitem;
|
RT_WORK_ITEM ra_rpt_workitem;
|
RT_WORK_ITEM sbdcnt_workitem;
|
#endif
|
#endif
|
|
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
#if (BEAMFORMING_SUPPORT == 1)
|
struct _RT_BEAMFORMING_INFO beamforming_info;
|
#endif
|
#endif
|
|
#ifdef CONFIG_PHYDM_DFS_MASTER
|
u8 dfs_region_domain;
|
u8 *dfs_master_enabled;
|
|
/*====== phydm_radar_detect_with_dbg_parm start ======*/
|
u8 radar_detect_dbg_parm_en;
|
u32 radar_detect_reg_918;
|
u32 radar_detect_reg_91c;
|
u32 radar_detect_reg_920;
|
u32 radar_detect_reg_924;
|
/*====== phydm_radar_detect_with_dbg_parm end ======*/
|
#endif
|
|
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
|
#if (RT_PLATFORM != PLATFORM_LINUX)
|
}; /*DM_Dynamic_Mechanism_Structure*/
|
#else
|
};
|
#endif
|
|
#else /*for AP,ADSL,CE Team*/
|
};
|
#endif
|
|
|
enum phydm_structure_type {
|
PHYDM_FALSEALMCNT,
|
PHYDM_CFOTRACK,
|
PHYDM_ADAPTIVITY,
|
PHYDM_ROMINFO,
|
|
};
|
|
|
|
enum odm_rf_content {
|
odm_radioa_txt = 0x1000,
|
odm_radiob_txt = 0x1001,
|
odm_radioc_txt = 0x1002,
|
odm_radiod_txt = 0x1003
|
};
|
|
enum odm_bb_config_type {
|
CONFIG_BB_PHY_REG,
|
CONFIG_BB_AGC_TAB,
|
CONFIG_BB_AGC_TAB_2G,
|
CONFIG_BB_AGC_TAB_5G,
|
CONFIG_BB_PHY_REG_PG,
|
CONFIG_BB_PHY_REG_MP,
|
CONFIG_BB_AGC_TAB_DIFF,
|
};
|
|
enum odm_rf_config_type {
|
CONFIG_RF_RADIO,
|
CONFIG_RF_TXPWR_LMT,
|
};
|
|
enum odm_fw_config_type {
|
CONFIG_FW_NIC,
|
CONFIG_FW_NIC_2,
|
CONFIG_FW_AP,
|
CONFIG_FW_AP_2,
|
CONFIG_FW_MP,
|
CONFIG_FW_WOWLAN,
|
CONFIG_FW_WOWLAN_2,
|
CONFIG_FW_AP_WOWLAN,
|
CONFIG_FW_BT,
|
};
|
|
/*status code*/
|
#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
|
enum rt_status {
|
RT_STATUS_SUCCESS,
|
RT_STATUS_FAILURE,
|
RT_STATUS_PENDING,
|
RT_STATUS_RESOURCE,
|
RT_STATUS_INVALID_CONTEXT,
|
RT_STATUS_INVALID_PARAMETER,
|
RT_STATUS_NOT_SUPPORT,
|
RT_STATUS_OS_API_FAILED,
|
};
|
#endif /*end of enum rt_status definition*/
|
|
#ifdef REMOVE_PACK
|
#pragma pack()
|
#endif
|
|
/*===========================================================*/
|
/*AGC RX High Power mode*/
|
/*===========================================================*/
|
#define lna_low_gain_1 0x64
|
#define lna_low_gain_2 0x5A
|
#define lna_low_gain_3 0x58
|
|
#define FA_RXHP_TH1 5000
|
#define FA_RXHP_TH2 1500
|
#define FA_RXHP_TH3 800
|
#define FA_RXHP_TH4 600
|
#define FA_RXHP_TH5 500
|
|
enum dm_1r_cca_e {
|
CCA_1R = 0,
|
CCA_2R = 1,
|
CCA_MAX = 2,
|
};
|
|
enum dm_rf_e {
|
rf_save = 0,
|
rf_normal = 1,
|
RF_MAX = 2,
|
};
|
|
/*check Sta pointer valid or not*/
|
|
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
#define IS_STA_VALID(p_sta) (p_sta && p_sta->expire_to)
|
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
#define IS_STA_VALID(p_sta) (p_sta && p_sta->bUsed)
|
#else
|
#define IS_STA_VALID(p_sta) (p_sta)
|
#endif
|
|
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_AP))
|
|
bool
|
odm_check_power_status(
|
struct _ADAPTER *adapter
|
);
|
|
#endif
|
|
u32 odm_convert_to_db(u32 value);
|
|
u32 odm_convert_to_linear(u32 value);
|
|
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
|
u32
|
get_psd_data(
|
struct PHY_DM_STRUCT *p_dm_odm,
|
unsigned int point,
|
u8 initial_gain_psd);
|
|
#endif
|
|
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
void
|
odm_dm_watchdog_lps(
|
struct PHY_DM_STRUCT *p_dm_odm
|
);
|
#endif
|
|
|
s32
|
odm_pwdb_conversion(
|
s32 X,
|
u32 total_bit,
|
u32 decimal_bit
|
);
|
|
s32
|
odm_sign_conversion(
|
s32 value,
|
u32 total_bit
|
);
|
|
void
|
odm_init_mp_driver_status(
|
struct PHY_DM_STRUCT *p_dm_odm
|
);
|
|
void
|
phydm_txcurrentcalibration(
|
struct PHY_DM_STRUCT *p_dm_odm
|
);
|
|
|
void
|
phydm_seq_sorting(
|
void *p_dm_void,
|
u32 *p_value,
|
u32 *rank_idx,
|
u32 *p_idx_out,
|
u8 seq_length
|
);
|
|
void
|
odm_dm_init(
|
struct PHY_DM_STRUCT *p_dm_odm
|
);
|
|
void
|
odm_dm_reset(
|
struct PHY_DM_STRUCT *p_dm_odm
|
);
|
|
void
|
phydm_support_ability_debug(
|
void *p_dm_void,
|
u32 *const dm_value,
|
u32 *_used,
|
char *output,
|
u32 *_out_len
|
);
|
|
void
|
phydm_config_ofdm_rx_path(
|
struct PHY_DM_STRUCT *p_dm_odm,
|
u32 path
|
);
|
|
void
|
phydm_config_trx_path(
|
void *p_dm_void,
|
u32 *const dm_value,
|
u32 *_used,
|
char *output,
|
u32 *_out_len
|
);
|
|
void
|
odm_dm_watchdog(
|
struct PHY_DM_STRUCT *p_dm_odm
|
);
|
|
void
|
phydm_watchdog_mp(
|
struct PHY_DM_STRUCT *p_dm_odm
|
);
|
|
void
|
odm_cmn_info_init(
|
struct PHY_DM_STRUCT *p_dm_odm,
|
enum odm_cmninfo_e cmn_info,
|
u32 value
|
);
|
|
void
|
odm_cmn_info_hook(
|
struct PHY_DM_STRUCT *p_dm_odm,
|
enum odm_cmninfo_e cmn_info,
|
void *p_value
|
);
|
|
void
|
odm_cmn_info_ptr_array_hook(
|
struct PHY_DM_STRUCT *p_dm_odm,
|
enum odm_cmninfo_e cmn_info,
|
u16 index,
|
void *p_value
|
);
|
|
void
|
odm_cmn_info_update(
|
struct PHY_DM_STRUCT *p_dm_odm,
|
u32 cmn_info,
|
u64 value
|
);
|
|
u32
|
phydm_cmn_info_query(
|
struct PHY_DM_STRUCT *p_dm_odm,
|
enum phydm_info_query_e info_type
|
);
|
|
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
void
|
odm_init_all_threads(
|
struct PHY_DM_STRUCT *p_dm_odm
|
);
|
|
void
|
odm_stop_all_threads(
|
struct PHY_DM_STRUCT *p_dm_odm
|
);
|
#endif
|
|
void
|
odm_init_all_timers(
|
struct PHY_DM_STRUCT *p_dm_odm
|
);
|
|
void
|
odm_cancel_all_timers(
|
struct PHY_DM_STRUCT *p_dm_odm
|
);
|
|
void
|
odm_release_all_timers(
|
struct PHY_DM_STRUCT *p_dm_odm
|
);
|
|
|
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
void odm_init_all_work_items(struct PHY_DM_STRUCT *p_dm_odm);
|
void odm_free_all_work_items(struct PHY_DM_STRUCT *p_dm_odm);
|
|
u64
|
platform_division64(
|
u64 x,
|
u64 y
|
);
|
|
#define dm_change_dynamic_init_gain_thresh odm_change_dynamic_init_gain_thresh
|
|
enum dm_dig_connect_e {
|
DIG_STA_DISCONNECT = 0,
|
DIG_STA_CONNECT = 1,
|
DIG_STA_BEFORE_CONNECT = 2,
|
DIG_MULTI_STA_DISCONNECT = 3,
|
DIG_MULTI_STA_CONNECT = 4,
|
DIG_CONNECT_MAX
|
};
|
|
/*2012/01/12 MH Check afapter status. Temp fix BSOD.*/
|
|
#define HAL_ADAPTER_STS_CHK(p_dm_odm) do {\
|
if (p_dm_odm->adapter == NULL) { \
|
\
|
return;\
|
} \
|
} while (0)
|
|
#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
|
|
void
|
odm_asoc_entry_init(
|
struct PHY_DM_STRUCT *p_dm_odm
|
);
|
|
|
void *
|
phydm_get_structure(
|
struct PHY_DM_STRUCT *p_dm_odm,
|
u8 structure_type
|
);
|
|
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) || (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
/*===========================================================*/
|
/* The following is for compile only*/
|
/*===========================================================*/
|
|
#define IS_HARDWARE_TYPE_8723A(_adapter) false
|
#define IS_HARDWARE_TYPE_8723AE(_adapter) false
|
#define IS_HARDWARE_TYPE_8192C(_adapter) false
|
#define IS_HARDWARE_TYPE_8192D(_adapter) false
|
#define RF_T_METER_92D 0x42
|
|
|
#define GET_RX_STATUS_DESC_RX_MCS(__prx_status_desc) LE_BITS_TO_1BYTE(__prx_status_desc+12, 0, 6)
|
|
#define REG_CONFIG_RAM64X16 0xb2c
|
|
#define TARGET_CHNL_NUM_2G_5G 59
|
|
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
u8 get_right_chnl_place_for_iqk(u8 chnl);
|
#endif
|
|
/* *********************************************************** */
|
#endif
|
|
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
void odm_dtc(struct PHY_DM_STRUCT *p_dm_odm);
|
#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */
|
|
|
void phydm_noisy_detection(struct PHY_DM_STRUCT *p_dm_odm);
|
|
|
#endif
|
|
void
|
phydm_set_ext_switch(
|
void *p_dm_void,
|
u32 *const dm_value,
|
u32 *_used,
|
char *output,
|
u32 *_out_len
|
);
|
|
void
|
phydm_api_debug(
|
void *p_dm_void,
|
u32 function_map,
|
u32 *const dm_value,
|
u32 *_used,
|
char *output,
|
u32 *_out_len
|
);
|
|
u8
|
phydm_nbi_setting(
|
void *p_dm_void,
|
u32 enable,
|
u32 channel,
|
u32 bw,
|
u32 f_interference,
|
u32 second_ch
|
);
|
|
void
|
phydm_receiver_blocking(
|
void *p_dm_void
|
);
|
