#ifndef __INC_PHYDM_BEAMFORMING_H
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#define __INC_PHYDM_BEAMFORMING_H
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#ifndef BEAMFORMING_SUPPORT
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#define BEAMFORMING_SUPPORT 0
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#endif
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/*Beamforming Related*/
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#include "txbf/halcomtxbf.h"
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#include "txbf/haltxbfjaguar.h"
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#include "txbf/haltxbf8192e.h"
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#include "txbf/haltxbf8814a.h"
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#include "txbf/haltxbf8822b.h"
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#include "txbf/haltxbfinterface.h"
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#if (BEAMFORMING_SUPPORT == 1)
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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#define eq_mac_addr(a,b) ( ((a)[0]==(b)[0] && (a)[1]==(b)[1] && (a)[2]==(b)[2] && (a)[3]==(b)[3] && (a)[4]==(b)[4] && (a)[5]==(b)[5]) ? 1:0 )
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#define cp_mac_addr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3],(des)[4]=(src)[4],(des)[5]=(src)[5])
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#endif
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#define MAX_BEAMFORMEE_SU 2
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#define MAX_BEAMFORMER_SU 2
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#if (RTL8822B_SUPPORT == 1)
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#define MAX_BEAMFORMEE_MU 6
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#define MAX_BEAMFORMER_MU 1
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#else
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#define MAX_BEAMFORMEE_MU 0
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#define MAX_BEAMFORMER_MU 0
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#endif
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#define BEAMFORMEE_ENTRY_NUM (MAX_BEAMFORMEE_SU + MAX_BEAMFORMEE_MU)
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#define BEAMFORMER_ENTRY_NUM (MAX_BEAMFORMER_SU + MAX_BEAMFORMER_MU)
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#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
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/*for different naming between WIN and CE*/
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#define BEACON_QUEUE BCN_QUEUE_INX
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#define NORMAL_QUEUE MGT_QUEUE_INX
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#define RT_DISABLE_FUNC RTW_DISABLE_FUNC
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#define RT_ENABLE_FUNC RTW_ENABLE_FUNC
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#endif
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enum beamforming_entry_state {
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BEAMFORMING_ENTRY_STATE_UNINITIALIZE,
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BEAMFORMING_ENTRY_STATE_INITIALIZEING,
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BEAMFORMING_ENTRY_STATE_INITIALIZED,
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BEAMFORMING_ENTRY_STATE_PROGRESSING,
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BEAMFORMING_ENTRY_STATE_PROGRESSED
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};
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enum beamforming_notify_state {
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BEAMFORMING_NOTIFY_NONE,
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BEAMFORMING_NOTIFY_ADD,
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BEAMFORMING_NOTIFY_DELETE,
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BEAMFORMEE_NOTIFY_ADD_SU,
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BEAMFORMEE_NOTIFY_DELETE_SU,
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BEAMFORMEE_NOTIFY_ADD_MU,
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BEAMFORMEE_NOTIFY_DELETE_MU,
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BEAMFORMING_NOTIFY_RESET
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};
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enum beamforming_cap {
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BEAMFORMING_CAP_NONE = 0x0,
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BEAMFORMER_CAP_HT_EXPLICIT = BIT(1),
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BEAMFORMEE_CAP_HT_EXPLICIT = BIT(2),
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BEAMFORMER_CAP_VHT_SU = BIT(5), /* Self has er Cap, because Reg er & peer ee */
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BEAMFORMEE_CAP_VHT_SU = BIT(6), /* Self has ee Cap, because Reg ee & peer er */
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BEAMFORMER_CAP_VHT_MU = BIT(7), /* Self has er Cap, because Reg er & peer ee */
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BEAMFORMEE_CAP_VHT_MU = BIT(8), /* Self has ee Cap, because Reg ee & peer er */
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BEAMFORMER_CAP = BIT(9),
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BEAMFORMEE_CAP = BIT(10),
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};
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enum sounding_mode {
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SOUNDING_SW_VHT_TIMER = 0x0,
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SOUNDING_SW_HT_TIMER = 0x1,
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sounding_stop_all_timer = 0x2,
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SOUNDING_HW_VHT_TIMER = 0x3,
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SOUNDING_HW_HT_TIMER = 0x4,
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SOUNDING_STOP_OID_TIMER = 0x5,
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SOUNDING_AUTO_VHT_TIMER = 0x6,
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SOUNDING_AUTO_HT_TIMER = 0x7,
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SOUNDING_FW_VHT_TIMER = 0x8,
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SOUNDING_FW_HT_TIMER = 0x9,
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};
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struct _RT_BEAMFORM_STAINFO {
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u8 *ra;
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u16 aid;
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u16 mac_id;
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u8 my_mac_addr[6];
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WIRELESS_MODE wireless_mode;
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CHANNEL_WIDTH bw;
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enum beamforming_cap beamform_cap;
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u8 ht_beamform_cap;
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u16 vht_beamform_cap;
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u8 cur_beamform;
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u16 cur_beamform_vht;
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};
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struct _RT_BEAMFORMEE_ENTRY {
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bool is_used;
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bool is_txbf;
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bool is_sound;
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u16 aid; /*Used to construct AID field of NDPA packet.*/
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u16 mac_id; /*Used to Set Reg42C in IBSS mode. */
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u16 p_aid; /*Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */
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u16 g_id; /*Used to fill Tx DESC*/
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u8 my_mac_addr[6];
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u8 mac_addr[6]; /*Used to fill Reg6E4 to fill Mac address of CSI report frame.*/
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CHANNEL_WIDTH sound_bw; /*Sounding band_width*/
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u16 sound_period;
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enum beamforming_cap beamform_entry_cap;
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enum beamforming_entry_state beamform_entry_state;
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bool is_beamforming_in_progress;
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/*u8 log_seq; // Move to _RT_BEAMFORMER_ENTRY*/
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/*u16 log_retry_cnt:3; // 0~4 // Move to _RT_BEAMFORMER_ENTRY*/
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/*u16 LogSuccessCnt:2; // 0~2 // Move to _RT_BEAMFORMER_ENTRY*/
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u16 log_status_fail_cnt:5; /* 0~21 */
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u16 default_csi_cnt:5; /* 0~21 */
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u8 csi_matrix[327];
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u16 csi_matrix_len;
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u8 num_of_sounding_dim;
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u8 comp_steering_num_of_bfer;
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u8 su_reg_index;
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/*For MU-MIMO*/
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bool is_mu_sta;
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u8 mu_reg_index;
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u8 gid_valid[8];
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u8 user_position[16];
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};
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struct _RT_BEAMFORMER_ENTRY {
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bool is_used;
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/*P_AID of BFer entry is probably not used*/
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u16 p_aid; /*Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */
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u16 g_id;
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u8 my_mac_addr[6];
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u8 mac_addr[6];
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enum beamforming_cap beamform_entry_cap;
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u8 num_of_sounding_dim;
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u8 clock_reset_times; /*Modified by Jeffery @2015-04-10*/
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u8 pre_log_seq; /*Modified by Jeffery @2015-03-30*/
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u8 log_seq; /*Modified by Jeffery @2014-10-29*/
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u16 log_retry_cnt:3; /*Modified by Jeffery @2014-10-29*/
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u16 log_success:2; /*Modified by Jeffery @2014-10-29*/
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u8 su_reg_index;
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/*For MU-MIMO*/
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bool is_mu_ap;
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u8 gid_valid[8];
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u8 user_position[16];
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u16 aid;
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};
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struct _RT_SOUNDING_INFO {
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u8 sound_idx;
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CHANNEL_WIDTH sound_bw;
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enum sounding_mode sound_mode;
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u16 sound_period;
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};
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struct _RT_BEAMFORMING_OID_INFO {
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u8 sound_oid_idx;
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CHANNEL_WIDTH sound_oid_bw;
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enum sounding_mode sound_oid_mode;
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u16 sound_oid_period;
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};
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struct _RT_BEAMFORMING_INFO {
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enum beamforming_cap beamform_cap;
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struct _RT_BEAMFORMEE_ENTRY beamformee_entry[BEAMFORMEE_ENTRY_NUM];
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struct _RT_BEAMFORMER_ENTRY beamformer_entry[BEAMFORMER_ENTRY_NUM];
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struct _RT_BEAMFORM_STAINFO beamform_sta_info;
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u8 beamformee_cur_idx;
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struct timer_list beamforming_timer;
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struct timer_list mu_timer;
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struct _RT_SOUNDING_INFO sounding_info;
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struct _RT_BEAMFORMING_OID_INFO beamforming_oid_info;
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struct _HAL_TXBF_INFO txbf_info;
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u8 sounding_sequence;
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u8 beamformee_su_cnt;
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u8 beamformer_su_cnt;
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u32 beamformee_su_reg_maping;
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u32 beamformer_su_reg_maping;
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/*For MU-MINO*/
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u8 beamformee_mu_cnt;
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u8 beamformer_mu_cnt;
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u32 beamformee_mu_reg_maping;
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u8 mu_ap_index;
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bool is_mu_sounding;
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u8 first_mu_bfee_index;
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bool is_mu_sounding_in_progress;
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bool dbg_disable_mu_tx;
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bool apply_v_matrix;
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bool snding3ss;
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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struct _ADAPTER *source_adapter;
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#endif
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/* Control register */
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u32 reg_mu_tx_ctrl; /* For USB/SDIO interfaces aync I/O */
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};
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struct _RT_NDPA_STA_INFO {
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u16 aid:12;
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u16 feedback_type:1;
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u16 nc_index:3;
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};
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enum phydm_acting_type {
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phydm_acting_as_ibss = 0,
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phydm_acting_as_ap = 1
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};
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enum beamforming_cap
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phydm_beamforming_get_entry_beam_cap_by_mac_id(
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void *p_dm_void,
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u8 mac_id
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);
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struct _RT_BEAMFORMEE_ENTRY *
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phydm_beamforming_get_bfee_entry_by_addr(
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void *p_dm_void,
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u8 *RA,
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u8 *idx
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);
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struct _RT_BEAMFORMER_ENTRY *
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phydm_beamforming_get_bfer_entry_by_addr(
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void *p_dm_void,
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u8 *TA,
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u8 *idx
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);
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void
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phydm_beamforming_notify(
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void *p_dm_void
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);
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bool
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phydm_acting_determine(
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void *p_dm_void,
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enum phydm_acting_type type
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);
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void
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beamforming_enter(
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void *p_dm_void,
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u16 sta_idx
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);
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void
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beamforming_leave(
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void *p_dm_void,
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u8 *RA
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);
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bool
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beamforming_start_fw(
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void *p_dm_void,
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u8 idx
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);
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void
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beamforming_check_sounding_success(
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void *p_dm_void,
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bool status
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);
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void
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phydm_beamforming_end_sw(
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void *p_dm_void,
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bool status
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);
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void
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beamforming_timer_callback(
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void *p_dm_void
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);
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void
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phydm_beamforming_init(
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void *p_dm_void
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);
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enum beamforming_cap
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phydm_beamforming_get_beam_cap(
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void *p_dm_void,
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struct _RT_BEAMFORMING_INFO *p_beam_info
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);
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bool
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beamforming_control_v1(
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void *p_dm_void,
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u8 *RA,
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u8 AID,
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u8 mode,
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CHANNEL_WIDTH BW,
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u8 rate
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);
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bool
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phydm_beamforming_control_v2(
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void *p_dm_void,
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u8 idx,
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u8 mode,
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CHANNEL_WIDTH BW,
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u16 period
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);
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void
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phydm_beamforming_watchdog(
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void *p_dm_void
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);
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void
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beamforming_sw_timer_callback(
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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struct timer_list *p_timer
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#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
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void *function_context
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#endif
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);
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bool
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beamforming_send_ht_ndpa_packet(
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void *p_dm_void,
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u8 *RA,
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CHANNEL_WIDTH BW,
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u8 q_idx
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);
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bool
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beamforming_send_vht_ndpa_packet(
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void *p_dm_void,
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u8 *RA,
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u16 AID,
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CHANNEL_WIDTH BW,
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u8 q_idx
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);
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#else
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#define beamforming_gid_paid(adapter, p_tcb)
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#define phydm_acting_determine(p_dm_odm, type) false
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#define beamforming_enter(p_dm_odm, sta_idx)
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#define beamforming_leave(p_dm_odm, RA)
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#define beamforming_end_fw(p_dm_odm)
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#define beamforming_control_v1(p_dm_odm, RA, AID, mode, BW, rate) true
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#define beamforming_control_v2(p_dm_odm, idx, mode, BW, period) true
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#define phydm_beamforming_end_sw(p_dm_odm, _status)
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#define beamforming_timer_callback(p_dm_odm)
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#define phydm_beamforming_init(p_dm_odm)
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#define phydm_beamforming_control_v2(p_dm_odm, _idx, _mode, _BW, _period) false
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#define beamforming_watchdog(p_dm_odm)
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#define phydm_beamforming_watchdog(p_dm_odm)
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#endif
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#endif
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