/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#ifndef __PHYDMRAINFO_H__
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#define __PHYDMRAINFO_H__
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/*#define RAINFO_VERSION "2.0" //2014.11.04*/
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/*#define RAINFO_VERSION "3.0" //2015.01.13 Dino*/
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/*#define RAINFO_VERSION "3.1" //2015.01.14 Dino*/
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/*#define RAINFO_VERSION "3.3" 2015.07.29 YuChen*/
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/*#define RAINFO_VERSION "3.4"*/ /*2015.12.15 Stanley*/
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/*#define RAINFO_VERSION "4.0"*/ /*2016.03.24 Dino, Add more RA mask state and Phydm-lize partial ra mask function */
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/*#define RAINFO_VERSION "4.1"*/ /*2016.04.20 Dino, Add new function to adjust PCR RA threshold */
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/*#define RAINFO_VERSION "4.2"*/ /*2016.05.17 Dino, Add H2C debug cmd */
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#define RAINFO_VERSION "4.3" /*2016.07.11 Dino, Fix RA hang in CCK 1M problem */
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#define FORCED_UPDATE_RAMASK_PERIOD 5
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#define H2C_0X42_LENGTH 5
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#define H2C_MAX_LENGTH 7
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#define RA_FLOOR_UP_GAP 3
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#define RA_FLOOR_TABLE_SIZE 7
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#define ACTIVE_TP_THRESHOLD 150
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#define RA_RETRY_DESCEND_NUM 2
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#define RA_RETRY_LIMIT_LOW 4
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#define RA_RETRY_LIMIT_HIGH 32
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#define RAINFO_BE_RX_STATE BIT(0) /* 1:RX */ /* ULDL */
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#define RAINFO_STBC_STATE BIT(1)
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/* #define RAINFO_LDPC_STATE BIT2 */
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#define RAINFO_NOISY_STATE BIT(2) /* set by Noisy_Detection */
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#define RAINFO_SHURTCUT_STATE BIT(3)
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#define RAINFO_SHURTCUT_FLAG BIT(4)
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#define RAINFO_INIT_RSSI_RATE_STATE BIT(5)
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#define RAINFO_BF_STATE BIT(6)
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#define RAINFO_BE_TX_STATE BIT(7) /* 1:TX */
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#define RA_MASK_CCK 0xf
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#define RA_MASK_OFDM 0xff0
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#define RA_MASK_HT1SS 0xff000
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#define RA_MASK_HT2SS 0xff00000
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/*#define RA_MASK_MCS3SS */
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#define RA_MASK_HT4SS 0xff0
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#define RA_MASK_VHT1SS 0x3ff000
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#define RA_MASK_VHT2SS 0xffc00000
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#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
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#define RA_FIRST_MACID 1
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#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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#define RA_FIRST_MACID 0
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#define WIN_DEFAULT_PORT_MACID 0
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#define WIN_BT_PORT_MACID 2
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#else /*if (DM_ODM_SUPPORT_TYPE == ODM_CE)*/
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#define RA_FIRST_MACID 0
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#endif
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#define ap_init_rate_adaptive_state odm_rate_adaptive_state_ap_init
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#if (RA_MASK_PHYDMLIZE_CE || RA_MASK_PHYDMLIZE_AP || RA_MASK_PHYDMLIZE_WIN)
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#define DM_RATR_STA_INIT 0
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#define DM_RATR_STA_HIGH 1
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#define DM_RATR_STA_MIDDLE 2
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#define DM_RATR_STA_LOW 3
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#define DM_RATR_STA_ULTRA_LOW 4
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#endif
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enum phydm_ra_arfr_num_e {
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ARFR_0_RATE_ID = 0x9,
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ARFR_1_RATE_ID = 0xa,
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ARFR_2_RATE_ID = 0xb,
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ARFR_3_RATE_ID = 0xc,
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ARFR_4_RATE_ID = 0xd,
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ARFR_5_RATE_ID = 0xe
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};
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enum phydm_ra_dbg_para_e {
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RADBG_PCR_TH_OFFSET = 0,
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RADBG_RTY_PENALTY = 1,
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RADBG_N_HIGH = 2,
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RADBG_N_LOW = 3,
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RADBG_TRATE_UP_TABLE = 4,
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RADBG_TRATE_DOWN_TABLE = 5,
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RADBG_TRYING_NECESSARY = 6,
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RADBG_TDROPING_NECESSARY = 7,
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RADBG_RATE_UP_RTY_RATIO = 8,
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RADBG_RATE_DOWN_RTY_RATIO = 9, /* u8 */
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RADBG_DEBUG_MONITOR1 = 0xc,
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RADBG_DEBUG_MONITOR2 = 0xd,
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RADBG_DEBUG_MONITOR3 = 0xe,
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RADBG_DEBUG_MONITOR4 = 0xf,
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RADBG_DEBUG_MONITOR5 = 0x10,
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NUM_RA_PARA
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};
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enum phydm_wireless_mode_e {
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PHYDM_WIRELESS_MODE_UNKNOWN = 0x00,
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PHYDM_WIRELESS_MODE_A = 0x01,
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PHYDM_WIRELESS_MODE_B = 0x02,
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PHYDM_WIRELESS_MODE_G = 0x04,
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PHYDM_WIRELESS_MODE_AUTO = 0x08,
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PHYDM_WIRELESS_MODE_N_24G = 0x10,
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PHYDM_WIRELESS_MODE_N_5G = 0x20,
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PHYDM_WIRELESS_MODE_AC_5G = 0x40,
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PHYDM_WIRELESS_MODE_AC_24G = 0x80,
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PHYDM_WIRELESS_MODE_AC_ONLY = 0x100,
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PHYDM_WIRELESS_MODE_MAX = 0x800,
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PHYDM_WIRELESS_MODE_ALL = 0xFFFF
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};
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enum phydm_rateid_idx_e {
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PHYDM_BGN_40M_2SS = 0,
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PHYDM_BGN_40M_1SS = 1,
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PHYDM_BGN_20M_2SS = 2,
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PHYDM_BGN_20M_1SS = 3,
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PHYDM_GN_N2SS = 4,
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PHYDM_GN_N1SS = 5,
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PHYDM_BG = 6,
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PHYDM_G = 7,
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PHYDM_B_20M = 8,
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PHYDM_ARFR0_AC_2SS = 9,
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PHYDM_ARFR1_AC_1SS = 10,
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PHYDM_ARFR2_AC_2G_1SS = 11,
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PHYDM_ARFR3_AC_2G_2SS = 12,
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PHYDM_ARFR4_AC_3SS = 13,
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PHYDM_ARFR5_N_3SS = 14
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};
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enum phydm_rf_type_def_e {
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PHYDM_RF_1T1R = 0,
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PHYDM_RF_1T2R,
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PHYDM_RF_2T2R,
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PHYDM_RF_2T2R_GREEN,
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PHYDM_RF_2T3R,
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PHYDM_RF_2T4R,
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PHYDM_RF_3T3R,
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PHYDM_RF_3T4R,
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PHYDM_RF_4T4R,
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PHYDM_RF_MAX_TYPE
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};
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enum phydm_bw_e {
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PHYDM_BW_20 = 0,
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PHYDM_BW_40,
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PHYDM_BW_80,
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PHYDM_BW_80_80,
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PHYDM_BW_160,
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PHYDM_BW_10,
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PHYDM_BW_5
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};
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#if (RATE_ADAPTIVE_SUPPORT == 1)/* 88E RA */
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struct _odm_ra_info_ {
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u8 rate_id;
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u32 rate_mask;
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u32 ra_use_rate;
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u8 rate_sgi;
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u8 rssi_sta_ra;
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u8 pre_rssi_sta_ra;
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u8 sgi_enable;
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u8 decision_rate;
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u8 pre_rate;
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u8 highest_rate;
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u8 lowest_rate;
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u32 nsc_up;
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u32 nsc_down;
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u16 RTY[5];
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u32 TOTAL;
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u16 DROP;
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u8 active;
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u16 rpt_time;
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u8 ra_waiting_counter;
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u8 ra_pending_counter;
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u8 ra_drop_after_down;
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#if 1 /* POWER_TRAINING_ACTIVE == 1 */ /* For compile pass only~! */
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u8 pt_active; /* on or off */
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u8 pt_try_state; /* 0 trying state, 1 for decision state */
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u8 pt_stage; /* 0~6 */
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u8 pt_stop_count; /* Stop PT counter */
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u8 pt_pre_rate; /* if rate change do PT */
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u8 pt_pre_rssi; /* if RSSI change 5% do PT */
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u8 pt_mode_ss; /* decide whitch rate should do PT */
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u8 ra_stage; /* StageRA, decide how many times RA will be done between PT */
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u8 pt_smooth_factor;
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#endif
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#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
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u8 rate_down_counter;
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u8 rate_up_counter;
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u8 rate_direction;
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u8 bounding_type;
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u8 bounding_counter;
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u8 bounding_learning_time;
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u8 rate_down_start_time;
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#endif
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};
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#endif
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struct _rate_adaptive_table_ {
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u8 firstconnect;
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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bool PT_collision_pre;
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#endif
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#if (defined(CONFIG_RA_DBG_CMD))
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bool is_ra_dbg_init;
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u8 RTY_P[ODM_NUM_RATE_IDX];
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u8 RTY_P_default[ODM_NUM_RATE_IDX];
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bool RTY_P_modify_note[ODM_NUM_RATE_IDX];
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u8 RATE_UP_RTY_RATIO[ODM_NUM_RATE_IDX];
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u8 RATE_UP_RTY_RATIO_default[ODM_NUM_RATE_IDX];
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bool RATE_UP_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX];
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u8 RATE_DOWN_RTY_RATIO[ODM_NUM_RATE_IDX];
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u8 RATE_DOWN_RTY_RATIO_default[ODM_NUM_RATE_IDX];
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bool RATE_DOWN_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX];
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bool ra_para_feedback_req;
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u8 para_idx;
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u8 rate_idx;
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u8 value;
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u16 value_16;
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u8 rate_length;
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#endif
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u8 link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM];
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u8 highest_client_tx_order;
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u16 highest_client_tx_rate_order;
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u8 power_tracking_flag;
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u8 RA_threshold_offset;
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u8 RA_offset_direction;
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u8 force_update_ra_mask_count;
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#if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT))
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u8 per_rate_retrylimit_20M[ODM_NUM_RATE_IDX];
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u8 per_rate_retrylimit_40M[ODM_NUM_RATE_IDX];
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u8 retry_descend_num;
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u8 retrylimit_low;
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u8 retrylimit_high;
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#endif
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};
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struct _ODM_RATE_ADAPTIVE {
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u8 type; /* dm_type_by_fw/dm_type_by_driver */
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u8 high_rssi_thresh; /* if RSSI > high_rssi_thresh => ratr_state is DM_RATR_STA_HIGH */
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u8 low_rssi_thresh; /* if RSSI <= low_rssi_thresh => ratr_state is DM_RATR_STA_LOW */
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u8 ratr_state; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */
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#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
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u8 ldpc_thres; /* if RSSI > ldpc_thres => switch from LPDC to BCC */
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bool is_lower_rts_rate;
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#endif
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#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
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u8 rts_thres;
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#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
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bool is_use_ldpc;
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#else
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u8 ultra_low_rssi_thresh;
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u32 last_ratr; /* RATR Register Content */
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#endif
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};
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void
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phydm_h2C_debug(
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void *p_dm_void,
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u32 *const dm_value,
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u32 *_used,
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char *output,
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u32 *_out_len
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);
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#if (defined(CONFIG_RA_DBG_CMD))
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void
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odm_RA_debug(
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void *p_dm_void,
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u32 *const dm_value
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);
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void
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odm_ra_para_adjust_init(
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void *p_dm_void
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);
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#else
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void
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phydm_RA_debug_PCR(
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void *p_dm_void,
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u32 *const dm_value,
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u32 *_used,
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char *output,
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u32 *_out_len
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);
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#endif
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void
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odm_c2h_ra_para_report_handler(
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void *p_dm_void,
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u8 *cmd_buf,
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u8 cmd_len
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);
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void
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odm_ra_para_adjust(
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void *p_dm_void
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);
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void
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phydm_ra_dynamic_retry_count(
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void *p_dm_void
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);
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void
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phydm_ra_dynamic_retry_limit(
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void *p_dm_void
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);
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void
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phydm_ra_dynamic_rate_id_on_assoc(
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void *p_dm_void,
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u8 wireless_mode,
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u8 init_rate_id
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);
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void
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phydm_print_rate(
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void *p_dm_void,
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u8 rate,
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u32 dbg_component
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);
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void
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phydm_c2h_ra_report_handler(
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void *p_dm_void,
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u8 *cmd_buf,
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u8 cmd_len
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);
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u8
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phydm_rate_order_compute(
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void *p_dm_void,
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u8 rate_idx
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);
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void
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phydm_ra_info_watchdog(
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void *p_dm_void
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);
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void
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phydm_ra_info_init(
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void *p_dm_void
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);
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void
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odm_rssi_monitor_init(
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void *p_dm_void
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);
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void
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phydm_modify_RA_PCR_threshold(
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void *p_dm_void,
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u8 RA_offset_direction,
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u8 RA_threshold_offset
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);
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void
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odm_rssi_monitor_check(
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void *p_dm_void
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);
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void
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phydm_init_ra_info(
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void *p_dm_void
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);
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u8
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phydm_vht_en_mapping(
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void *p_dm_void,
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u32 wireless_mode
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);
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u8
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phydm_rate_id_mapping(
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void *p_dm_void,
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u32 wireless_mode,
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u8 rf_type,
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u8 bw
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);
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void
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phydm_update_hal_ra_mask(
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void *p_dm_void,
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u32 wireless_mode,
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u8 rf_type,
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u8 BW,
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u8 mimo_ps_enable,
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u8 disable_cck_rate,
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u32 *ratr_bitmap_msb_in,
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u32 *ratr_bitmap_in,
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u8 tx_rate_level
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);
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void
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odm_rate_adaptive_mask_init(
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void *p_dm_void
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);
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void
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odm_refresh_rate_adaptive_mask(
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void *p_dm_void
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);
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void
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odm_refresh_rate_adaptive_mask_mp(
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void *p_dm_void
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);
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void
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odm_refresh_rate_adaptive_mask_ce(
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void *p_dm_void
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);
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void
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odm_refresh_rate_adaptive_mask_apadsl(
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void *p_dm_void
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);
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u8
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phydm_RA_level_decision(
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void *p_dm_void,
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u32 rssi,
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u8 ratr_state
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);
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bool
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odm_ra_state_check(
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void *p_dm_void,
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s32 RSSI,
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bool is_force_update,
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u8 *p_ra_tr_state
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);
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void
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odm_refresh_basic_rate_mask(
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void *p_dm_void
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);
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void
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odm_ra_post_action_on_assoc(
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void *p_dm_odm
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);
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#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
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u8
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odm_find_rts_rate(
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void *p_dm_void,
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u8 tx_rate,
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bool is_erp_protect
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);
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void
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odm_update_noisy_state(
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void *p_dm_void,
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bool is_noisy_state_from_c2h
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);
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void
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phydm_update_pwr_track(
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void *p_dm_void,
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u8 rate
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);
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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s32
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phydm_find_minimum_rssi(
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struct PHY_DM_STRUCT *p_dm_odm,
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struct _ADAPTER *p_adapter,
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OUT bool *p_is_link_temp
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);
|
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void
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odm_update_init_rate_work_item_callback(
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void *p_context
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);
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void
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odm_rssi_dump_to_register(
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void *p_dm_void
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);
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void
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odm_refresh_ldpc_rts_mp(
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struct _ADAPTER *p_adapter,
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struct PHY_DM_STRUCT *p_dm_odm,
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u8 m_mac_id,
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u8 iot_peer,
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s32 undecorated_smoothed_pwdb
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);
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#if 0
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void
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odm_dynamic_arfb_select(
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void *p_dm_void,
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u8 rate,
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bool collision_state
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);
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#endif
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|
void
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odm_rate_adaptive_state_ap_init(
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void *PADAPTER_VOID,
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struct sta_info *p_entry
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);
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#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
|
static void
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find_minimum_rssi(
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struct _ADAPTER *p_adapter
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);
|
|
u64
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phydm_get_rate_bitmap_ex(
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void *p_dm_void,
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u32 macid,
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u64 ra_mask,
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u8 rssi_level,
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u64 *dm_ra_mask,
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u8 *dm_rte_id
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);
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u32
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odm_get_rate_bitmap(
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void *p_dm_void,
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u32 macid,
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u32 ra_mask,
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u8 rssi_level
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);
|
|
void phydm_ra_rssi_rpt_wk(void *p_context);
|
#endif/*#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)*/
|
|
#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
/*
|
void
|
phydm_gen_ramask_h2c_AP(
|
void *p_dm_void,
|
struct rtl8192cd_priv *priv,
|
struct sta_info *p_entry,
|
u8 rssi_level
|
);
|
*/
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#endif/*#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN| ODM_CE))*/
|
|
#endif /*#ifndef __ODMRAINFO_H__*/
|
