/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#ifndef __DRV_TYPES_PCI_H__
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#define __DRV_TYPES_PCI_H__
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#ifdef PLATFORM_LINUX
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#include <linux/pci.h>
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#endif
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#define INTEL_VENDOR_ID 0x8086
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#define SIS_VENDOR_ID 0x1039
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#define ATI_VENDOR_ID 0x1002
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#define ATI_DEVICE_ID 0x7914
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#define AMD_VENDOR_ID 0x1022
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#define PCI_MAX_BRIDGE_NUMBER 255
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#define PCI_MAX_DEVICES 32
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#define PCI_MAX_FUNCTION 8
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#define PCI_CONF_ADDRESS 0x0CF8 /* PCI Configuration Space Address */
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#define PCI_CONF_DATA 0x0CFC /* PCI Configuration Space Data */
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#define PCI_CLASS_BRIDGE_DEV 0x06
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#define PCI_SUBCLASS_BR_PCI_TO_PCI 0x04
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#define PCI_CAPABILITY_ID_PCI_EXPRESS 0x10
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#define U1DONTCARE 0xFF
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#define U2DONTCARE 0xFFFF
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#define U4DONTCARE 0xFFFFFFFF
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#define PCI_VENDER_ID_REALTEK 0x10ec
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#define HAL_HW_PCI_8180_DEVICE_ID 0x8180
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#define HAL_HW_PCI_8185_DEVICE_ID 0x8185 /* 8185 or 8185b */
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#define HAL_HW_PCI_8188_DEVICE_ID 0x8188 /* 8185b */
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#define HAL_HW_PCI_8198_DEVICE_ID 0x8198 /* 8185b */
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#define HAL_HW_PCI_8190_DEVICE_ID 0x8190 /* 8190 */
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#define HAL_HW_PCI_8723E_DEVICE_ID 0x8723 /* 8723E */
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#define HAL_HW_PCI_8192_DEVICE_ID 0x8192 /* 8192 PCI-E */
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#define HAL_HW_PCI_8192SE_DEVICE_ID 0x8192 /* 8192 SE */
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#define HAL_HW_PCI_8174_DEVICE_ID 0x8174 /* 8192 SE */
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#define HAL_HW_PCI_8173_DEVICE_ID 0x8173 /* 8191 SE Crab */
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#define HAL_HW_PCI_8172_DEVICE_ID 0x8172 /* 8191 SE RE */
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#define HAL_HW_PCI_8171_DEVICE_ID 0x8171 /* 8191 SE Unicron */
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#define HAL_HW_PCI_0045_DEVICE_ID 0x0045 /* 8190 PCI for Ceraga */
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#define HAL_HW_PCI_0046_DEVICE_ID 0x0046 /* 8190 Cardbus for Ceraga */
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#define HAL_HW_PCI_0044_DEVICE_ID 0x0044 /* 8192e PCIE for Ceraga */
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#define HAL_HW_PCI_0047_DEVICE_ID 0x0047 /* 8192e Express Card for Ceraga */
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#define HAL_HW_PCI_700F_DEVICE_ID 0x700F
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#define HAL_HW_PCI_701F_DEVICE_ID 0x701F
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#define HAL_HW_PCI_DLINK_DEVICE_ID 0x3304
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#define HAL_HW_PCI_8188EE_DEVICE_ID 0x8179
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#define HAL_MEMORY_MAPPED_IO_RANGE_8190PCI 0x1000 /* 8190 support 16 pages of IO registers */
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#define HAL_HW_PCI_REVISION_ID_8190PCI 0x00
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#define HAL_MEMORY_MAPPED_IO_RANGE_8192PCIE 0x4000 /* 8192 support 16 pages of IO registers */
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#define HAL_HW_PCI_REVISION_ID_8192PCIE 0x01
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#define HAL_MEMORY_MAPPED_IO_RANGE_8192SE 0x4000 /* 8192 support 16 pages of IO registers */
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#define HAL_HW_PCI_REVISION_ID_8192SE 0x10
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#define HAL_HW_PCI_REVISION_ID_8192CE 0x1
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#define HAL_MEMORY_MAPPED_IO_RANGE_8192CE 0x4000 /* 8192 support 16 pages of IO registers */
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#define HAL_HW_PCI_REVISION_ID_8192DE 0x0
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#define HAL_MEMORY_MAPPED_IO_RANGE_8192DE 0x4000 /* 8192 support 16 pages of IO registers */
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enum pci_bridge_vendor {
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PCI_BRIDGE_VENDOR_INTEL = 0x0,/* 0b'0000,0001 */
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PCI_BRIDGE_VENDOR_ATI, /* = 0x02, */ /* 0b'0000,0010 */
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PCI_BRIDGE_VENDOR_AMD, /* = 0x04, */ /* 0b'0000,0100 */
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PCI_BRIDGE_VENDOR_SIS ,/* = 0x08, */ /* 0b'0000,1000 */
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PCI_BRIDGE_VENDOR_UNKNOWN, /* = 0x40, */ /* 0b'0100,0000 */
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PCI_BRIDGE_VENDOR_MAX ,/* = 0x80 */
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} ;
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/* copy this data structor defination from MSDN SDK */
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typedef struct _PCI_COMMON_CONFIG {
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u16 VendorID;
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u16 DeviceID;
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u16 Command;
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u16 Status;
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u8 RevisionID;
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u8 ProgIf;
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u8 SubClass;
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u8 BaseClass;
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u8 CacheLineSize;
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u8 LatencyTimer;
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u8 HeaderType;
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u8 BIST;
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union {
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struct _PCI_HEADER_TYPE_0 {
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u32 BaseAddresses[6];
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u32 CIS;
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u16 SubVendorID;
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u16 SubSystemID;
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u32 ROMBaseAddress;
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u8 CapabilitiesPtr;
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u8 Reserved1[3];
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u32 Reserved2;
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u8 InterruptLine;
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u8 InterruptPin;
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u8 MinimumGrant;
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u8 MaximumLatency;
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} type0;
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#if 0
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struct _PCI_HEADER_TYPE_1 {
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ULONG BaseAddresses[PCI_TYPE1_ADDRESSES];
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UCHAR PrimaryBusNumber;
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UCHAR SecondaryBusNumber;
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UCHAR SubordinateBusNumber;
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UCHAR SecondaryLatencyTimer;
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UCHAR IOBase;
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UCHAR IOLimit;
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USHORT SecondaryStatus;
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USHORT MemoryBase;
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USHORT MemoryLimit;
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USHORT PrefetchableMemoryBase;
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USHORT PrefetchableMemoryLimit;
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ULONG PrefetchableMemoryBaseUpper32;
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ULONG PrefetchableMemoryLimitUpper32;
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USHORT IOBaseUpper;
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USHORT IOLimitUpper;
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ULONG Reserved2;
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ULONG ExpansionROMBase;
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UCHAR InterruptLine;
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UCHAR InterruptPin;
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USHORT BridgeControl;
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} type1;
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struct _PCI_HEADER_TYPE_2 {
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ULONG BaseAddress;
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UCHAR CapabilitiesPtr;
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UCHAR Reserved2;
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USHORT SecondaryStatus;
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UCHAR PrimaryBusNumber;
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UCHAR CardbusBusNumber;
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UCHAR SubordinateBusNumber;
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UCHAR CardbusLatencyTimer;
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ULONG MemoryBase0;
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ULONG MemoryLimit0;
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ULONG MemoryBase1;
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ULONG MemoryLimit1;
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USHORT IOBase0_LO;
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USHORT IOBase0_HI;
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USHORT IOLimit0_LO;
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USHORT IOLimit0_HI;
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USHORT IOBase1_LO;
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USHORT IOBase1_HI;
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USHORT IOLimit1_LO;
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USHORT IOLimit1_HI;
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UCHAR InterruptLine;
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UCHAR InterruptPin;
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USHORT BridgeControl;
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USHORT SubVendorID;
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USHORT SubSystemID;
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ULONG LegacyBaseAddress;
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UCHAR Reserved3[56];
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ULONG SystemControl;
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UCHAR MultiMediaControl;
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UCHAR GeneralStatus;
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UCHAR Reserved4[2];
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UCHAR GPIO0Control;
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UCHAR GPIO1Control;
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UCHAR GPIO2Control;
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UCHAR GPIO3Control;
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ULONG IRQMuxRouting;
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UCHAR RetryStatus;
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UCHAR CardControl;
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UCHAR DeviceControl;
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UCHAR Diagnostic;
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} type2;
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#endif
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} u;
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u8 DeviceSpecific[108];
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} PCI_COMMON_CONFIG , *PPCI_COMMON_CONFIG;
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typedef struct _RT_PCI_CAPABILITIES_HEADER {
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u8 CapabilityID;
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u8 Next;
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} RT_PCI_CAPABILITIES_HEADER, *PRT_PCI_CAPABILITIES_HEADER;
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struct pci_priv {
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BOOLEAN pci_clk_req;
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u8 pciehdr_offset;
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/* PCIeCap is only differece between B-cut and C-cut. */
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/* Configuration Space offset 72[7:4] */
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/* 0: A/B cut */
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/* 1: C cut and later. */
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u8 pcie_cap;
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u8 linkctrl_reg;
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u8 busnumber;
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u8 devnumber;
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u8 funcnumber;
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u8 pcibridge_busnum;
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u8 pcibridge_devnum;
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u8 pcibridge_funcnum;
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u8 pcibridge_vendor;
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u16 pcibridge_vendorid;
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u16 pcibridge_deviceid;
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u8 pcibridge_pciehdr_offset;
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u8 pcibridge_linkctrlreg;
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u8 amd_l1_patch;
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};
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typedef struct _RT_ISR_CONTENT {
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union {
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u32 IntArray[2];
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u32 IntReg4Byte;
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u16 IntReg2Byte;
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};
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} RT_ISR_CONTENT, *PRT_ISR_CONTENT;
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/* #define RegAddr(addr) (addr + 0xB2000000UL) */
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/* some platform macros will def here */
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static inline void NdisRawWritePortUlong(u32 port, u32 val)
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{
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outl(val, port);
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/* writel(val, (u8 *)RegAddr(port)); */
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}
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static inline void NdisRawWritePortUchar(u32 port, u8 val)
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{
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outb(val, port);
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/* writeb(val, (u8 *)RegAddr(port)); */
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}
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static inline void NdisRawReadPortUchar(u32 port, u8 *pval)
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{
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*pval = inb(port);
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/* *pval = readb((u8 *)RegAddr(port)); */
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}
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static inline void NdisRawReadPortUshort(u32 port, u16 *pval)
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{
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*pval = inw(port);
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/* *pval = readw((u8 *)RegAddr(port)); */
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}
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static inline void NdisRawReadPortUlong(u32 port, u32 *pval)
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{
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*pval = inl(port);
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/* *pval = readl((u8 *)RegAddr(port)); */
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}
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#endif
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