/**
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******************************************************************************
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* @file stm32l1xx_fsmc.h
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* @author MCD Application Team
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* @version V1.3.1
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* @date 20-April-2015
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* @brief This file contains all the functions prototypes for the FSMC firmware
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* library.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
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*
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32L1xx_FSMC_H
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#define __STM32L1xx_FSMC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32l1xx.h"
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/** @addtogroup STM32L1xx_StdPeriph_Driver
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* @{
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*/
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/** @addtogroup FSMC
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/**
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* @brief Timing parameters For NOR/SRAM Banks
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*/
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typedef struct
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{
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uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
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the duration of the address setup time.
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This parameter can be a value between 0 and 0xF.
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@note It is not used with synchronous NOR Flash memories. */
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uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
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the duration of the address hold time.
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This parameter can be a value between 0 and 0xF.
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@note It is not used with synchronous NOR Flash memories.*/
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uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
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the duration of the data setup time.
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This parameter can be a value between 0 and 0xFF.
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@note It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
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uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
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the duration of the bus turnaround.
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This parameter can be a value between 0 and 0xF.
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@note It is only used for multiplexed NOR Flash memories. */
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uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
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This parameter can be a value between 1 and 0xF.
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@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
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uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
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to the memory before getting the first data.
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The parameter value depends on the memory type as shown below:
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- It must be set to 0 in case of a CRAM
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- It is don't care in asynchronous NOR, SRAM or ROM accesses
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- It may assume a value between 0 and 0xF in NOR Flash memories
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with synchronous burst mode enable */
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uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode.
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This parameter can be a value of @ref FSMC_Access_Mode */
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}FSMC_NORSRAMTimingInitTypeDef;
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/**
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* @brief FSMC NOR/SRAM Init structure definition
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*/
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typedef struct
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{
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uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
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This parameter can be a value of @ref FSMC_NORSRAM_Bank */
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uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are
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multiplexed on the databus or not.
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This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
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uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to
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the corresponding memory bank.
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This parameter can be a value of @ref FSMC_Memory_Type */
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uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
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This parameter can be a value of @ref FSMC_Data_Width */
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uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
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valid only with synchronous burst Flash memories.
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This parameter can be a value of @ref FSMC_Burst_Access_Mode */
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uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
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valid only with asynchronous Flash memories.
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This parameter can be a value of @ref FSMC_AsynchronousWait */
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uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
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the Flash memory in burst mode.
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This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
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uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
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memory, valid only when accessing Flash memories in burst mode.
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This parameter can be a value of @ref FSMC_Wrap_Mode */
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uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
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clock cycle before the wait state or during the wait state,
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valid only when accessing memories in burst mode.
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This parameter can be a value of @ref FSMC_Wait_Timing */
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uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC.
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This parameter can be a value of @ref FSMC_Write_Operation */
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uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait
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signal, valid for Flash memory access in burst mode.
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This parameter can be a value of @ref FSMC_Wait_Signal */
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uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.
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This parameter can be a value of @ref FSMC_Extended_Mode */
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uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.
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This parameter can be a value of @ref FSMC_Write_Burst */
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FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/
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FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/
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}FSMC_NORSRAMInitTypeDef;
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup FSMC_Exported_Constants
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* @{
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*/
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/** @defgroup FSMC_NORSRAM_Bank
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* @{
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*/
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#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
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#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
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#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
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#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
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#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
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((BANK) == FSMC_Bank1_NORSRAM2) || \
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((BANK) == FSMC_Bank1_NORSRAM3) || \
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((BANK) == FSMC_Bank1_NORSRAM4))
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/**
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* @}
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*/
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/** @defgroup NOR_SRAM_Controller
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* @{
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*/
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/** @defgroup FSMC_Data_Address_Bus_Multiplexing
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* @{
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*/
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#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
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#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
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#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
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((MUX) == FSMC_DataAddressMux_Enable))
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/**
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* @}
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*/
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/** @defgroup FSMC_Memory_Type
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* @{
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*/
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#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
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#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
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#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
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#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
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((MEMORY) == FSMC_MemoryType_PSRAM)|| \
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((MEMORY) == FSMC_MemoryType_NOR))
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/**
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* @}
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*/
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/** @defgroup FSMC_Data_Width
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* @{
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*/
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#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
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#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
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#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
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((WIDTH) == FSMC_MemoryDataWidth_16b))
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/**
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* @}
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*/
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/** @defgroup FSMC_Burst_Access_Mode
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* @{
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*/
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#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
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#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
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#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
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((STATE) == FSMC_BurstAccessMode_Enable))
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/**
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* @}
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*/
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/** @defgroup FSMC_AsynchronousWait
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* @{
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*/
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#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
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#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
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#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
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((STATE) == FSMC_AsynchronousWait_Enable))
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/**
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* @}
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*/
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/** @defgroup FSMC_Wait_Signal_Polarity
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* @{
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*/
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#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
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#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
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#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
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((POLARITY) == FSMC_WaitSignalPolarity_High))
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/**
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* @}
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*/
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/** @defgroup FSMC_Wrap_Mode
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* @{
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*/
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#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
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#define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
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#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
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((MODE) == FSMC_WrapMode_Enable))
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/**
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* @}
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*/
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/** @defgroup FSMC_Wait_Timing
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* @{
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*/
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#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
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#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
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#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
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((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
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/**
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* @}
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*/
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/** @defgroup FSMC_Write_Operation
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* @{
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*/
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#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
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#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
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#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
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((OPERATION) == FSMC_WriteOperation_Enable))
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/**
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* @}
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*/
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/** @defgroup FSMC_Wait_Signal
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* @{
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*/
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#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
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#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
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#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
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((SIGNAL) == FSMC_WaitSignal_Enable))
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/**
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* @}
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*/
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/** @defgroup FSMC_Extended_Mode
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* @{
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*/
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#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
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#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
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#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
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((MODE) == FSMC_ExtendedMode_Enable))
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/**
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* @}
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*/
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/** @defgroup FSMC_Write_Burst
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* @{
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*/
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#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
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#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
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#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
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((BURST) == FSMC_WriteBurst_Enable))
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/**
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* @}
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*/
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/** @defgroup FSMC_Address_Setup_Time
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* @{
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*/
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#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
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/**
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* @}
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*/
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/** @defgroup FSMC_Address_Hold_Time
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* @{
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*/
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#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
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/**
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* @}
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*/
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/** @defgroup FSMC_Data_Setup_Time
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* @{
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*/
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#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
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/**
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* @}
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*/
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/** @defgroup FSMC_Bus_Turn_around_Duration
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* @{
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*/
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#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
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/**
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* @}
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*/
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/** @defgroup FSMC_CLK_Division
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* @{
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*/
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#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
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/**
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* @}
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*/
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/** @defgroup FSMC_Data_Latency
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* @{
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*/
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#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
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/**
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* @}
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*/
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/** @defgroup FSMC_Access_Mode
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* @{
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*/
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#define FSMC_AccessMode_A ((uint32_t)0x00000000)
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#define FSMC_AccessMode_B ((uint32_t)0x10000000)
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#define FSMC_AccessMode_C ((uint32_t)0x20000000)
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#define FSMC_AccessMode_D ((uint32_t)0x30000000)
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#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
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((MODE) == FSMC_AccessMode_B) || \
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((MODE) == FSMC_AccessMode_C) || \
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((MODE) == FSMC_AccessMode_D))
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/* Exported functions ------------------------------------------------------- */
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/* NOR/SRAM Controller functions **********************************************/
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void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
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void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
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void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
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void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
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#ifdef __cplusplus
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}
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#endif
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#endif /*__STM32L1xx_FSMC_H */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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