#ifndef __OV7670_REG_H
|
#define __OV7670_REG_H
|
|
#define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
|
#define REG_BLUE 0x01 /* blue gain */
|
#define REG_RED 0x02 /* red gain */
|
#define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */
|
#define REG_COM1 0x04 /* Control 1 */
|
#define COM1_CCIR656 0x40 /* CCIR656 enable */
|
|
#define REG_BAVE 0x05 /* U/B Average level */
|
#define REG_GbAVE 0x06 /* Y/Gb Average level */
|
#define REG_AECHH 0x07 /* AEC MS 5 bits */
|
#define REG_RAVE 0x08 /* V/R Average level */
|
#define REG_COM2 0x09 /* Control 2 */
|
#define COM2_SSLEEP 0x10 /* Soft sleep mode */
|
|
#define REG_PID 0x0a /* Product ID MSB */
|
#define REG_VER 0x0b /* Product ID LSB */
|
#define REG_COM3 0x0c /* Control 3 */
|
#define COM3_SWAP 0x40 /* Byte swap */
|
#define COM3_SCALEEN 0x08 /* Enable scaling */
|
#define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */
|
|
#define REG_COM4 0x0d /* Control 4 */
|
#define REG_COM5 0x0e /* All "reserved" */
|
#define REG_COM6 0x0f /* Control 6 */
|
#define REG_AECH 0x10 /* More bits of AEC value */
|
#define REG_CLKRC 0x11 /* Clocl control */
|
#define CLK_EXT 0x40 /* Use external clock directly */
|
#define CLK_SCALE 0x3f /* Mask for internal clock scale */
|
|
#define REG_COM7 0x12 /* Control 7 */
|
#define COM7_RESET 0x80 /* Register reset */
|
#define COM7_FMT_MASK 0x38
|
#define COM7_FMT_VGA 0x00
|
#define COM7_FMT_CIF 0x20 /* CIF format */
|
#define COM7_FMT_QVGA 0x10 /* QVGA format */
|
#define COM7_FMT_QCIF 0x08 /* QCIF format */
|
#define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */
|
#define COM7_YUV 0x00 /* YUV */
|
#define COM7_BAYER 0x01 /* Bayer format */
|
#define COM7_PBAYER 0x05 /* "Processed bayer" */
|
|
#define REG_COM8 0x13 /* Control 8 */
|
#define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
|
#define COM8_AECSTEP 0x40 /* Unlimited AEC step size */
|
#define COM8_BFILT 0x20 /* Band filter enable */
|
#define COM8_AGC 0x04 /* Auto gain enable */
|
#define COM8_AWB 0x02 /* White balance enable */
|
#define COM8_AEC 0x01 /* Auto exposure enable */
|
|
#define REG_COM9 0x14 /* Control 9 - gain ceiling */
|
#define REG_COM10 0x15 /* Control 10 */
|
#define COM10_HSYNC 0x40 /* HSYNC instead of HREF */
|
#define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */
|
#define COM10_HREF_REV 0x08 /* Reverse HREF */
|
#define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */
|
#define COM10_VS_NEG 0x02 /* VSYNC negative */
|
#define COM10_HS_NEG 0x01 /* HSYNC negative */
|
|
#define REG_HSTART 0x17 /* Horiz start high bits */
|
#define REG_HSTOP 0x18 /* Horiz stop high bits */
|
#define REG_VSTART 0x19 /* Vert start high bits */
|
#define REG_VSTOP 0x1a /* Vert stop high bits */
|
#define REG_PSHFT 0x1b /* Pixel delay after HREF */
|
#define REG_MIDH 0x1c /* Manuf. ID high */
|
#define REG_MIDL 0x1d /* Manuf. ID low */
|
#define REG_MVFP 0x1e /* Mirror / vflip */
|
#define MVFP_MIRROR 0x20 /* Mirror image */
|
#define MVFP_FLIP 0x10 /* Vertical flip */
|
#define REG_ADCCTR0 0x20
|
#define REG_ADCCTR1 0x21
|
#define REG_ADCCTR2 0x22
|
#define REG_AEW 0x24 /* AGC upper limit */
|
#define REG_AEB 0x25 /* AGC lower limit */
|
#define REG_VPT 0x26 /* AGC/AEC fast mode op region */
|
#define REG_HSYST 0x30 /* HSYNC rising edge delay */
|
#define REG_HSYEN 0x31 /* HSYNC falling edge delay */
|
#define REG_HREF 0x32 /* HREF pieces */
|
#define REG_CHLF 0x33
|
#define REG_ARBLM 0x34
|
/* 0x35~0x36 reserved */
|
#define REG_ADC 0x37
|
#define REG_ACOM 0x38
|
#define REG_OFON 0x39
|
#define REG_TSLB 0x3a /* lots of stuff */
|
#define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */
|
|
#define REG_COM11 0x3b /* Control 11 */
|
#define COM11_NIGHT 0x80 /* NIght mode enable */
|
#define COM11_NMFR 0x60 /* Two bit NM frame rate */
|
#define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */
|
#define COM11_50HZ 0x08 /* Manual 50Hz select */
|
#define COM11_EXP 0x02
|
|
#define REG_COM12 0x3c /* Control 12 */
|
#define COM12_HREF 0x80 /* HREF always */
|
|
#define REG_COM13 0x3d /* Control 13 */
|
#define REG_COM14 0x3e /* Control 14 */
|
#define COM13_GAMMA 0x80 /* Gamma enable */
|
#define COM13_UVSAT 0x40 /* UV saturation auto adjustment */
|
#define COM13_UVSWAP 0x01 /* V before U - w/TSLB */
|
#define REG_COM14 0x3e /* Control 14 */
|
#define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */
|
#define REG_EDGE 0x3f /* Edge enhancement factor */
|
|
#define REG_COM15 0x40 /* Control 15 */
|
#define COM15_R10F0 0x00 /* Data range 10 to F0 */
|
#define COM15_R01FE 0x80 /* 01 to FE */
|
#define COM15_R00FF 0xc0 /* 00 to FF */
|
#define COM15_RGB565 0x10 /* RGB565 output */
|
#define COM15_RGB555 0x30 /* RGB555 output */
|
|
#define REG_COM16 0x41 /* Control 16 */
|
#define COM16_AWBGAIN 0x08 /* AWB gain enable */
|
#define REG_COM17 0x42 /* Control 17 */
|
#define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */
|
#define COM17_CBAR 0x08 /* DSP Color bar */
|
|
#define REG_AWBC1 0x43
|
#define REG_AWBC2 0x44
|
#define REG_AWBC3 0x45
|
#define REG_AWBC4 0x46
|
#define REG_AWBC5 0x47
|
#define REG_AWBC6 0x48
|
|
/* 0x49~0x4A reserved */
|
|
#define REG_CMATRIX_BASE 0x4f
|
#define CMATRIX_LEN 6
|
#define REG_MTX1 0x4f
|
#define REG_MTX2 0x50
|
#define REG_MTX3 0x51
|
#define REG_MTX4 0x52
|
#define REG_MTX5 0x53
|
#define REG_MTX6 0x54
|
#define REG_BRIGHT 0x55
|
#define REG_CONTRAS 0X56
|
#define REG_CONTRAS_CENTER 0x57
|
#define REG_CMATRIX_SIGN 0x58
|
|
#define REG_GFIX 0x69 /* Fix gain control */
|
#define REG_LLC1 0x62
|
#define REG_LLC2 0x63
|
#define REG_LLC3 0x64
|
#define REG_LLC4 0x65
|
#define REG_LLC5 0x66
|
#define REG_LLC6 0x94
|
#define REG_LLC7 0x95
|
#define REG_GGAIN 0x6a
|
#define REG_DBLV 0x6b
|
#define REG_AWBCTR3 0x6c
|
#define REG_AWBCTR2 0x6d
|
#define REG_AWBCTR1 0x6e
|
#define REG_AWBCTR0 0x6f
|
#define REG_SCALING_XSC 0x70
|
#define REG_SCALING_YSC 0x71
|
#define REG_SCALING_DCWCTR 0x72
|
#define REG_SCALING_PC 0x73
|
|
#define REG_REG74 0x74
|
#define REG_REG75 0x75
|
#define REG_REG76 0x76 /* OV's name */
|
#define R76_WHTPCOR 0x40 /* White pixel correction enable */
|
#define R76_BLKPCOR 0x80 /* Black pixel correction enable */
|
#define REG_REG77 0x77
|
/* 0x78~0x79 reserved */
|
#define REG_SLOP 0x7a
|
#define REG_GAM1 0x7b
|
#define REG_GAM2 0x7c
|
#define REG_GAM3 0x7d
|
#define REG_GAM4 0x7e
|
#define REG_GAM5 0x7f
|
#define REG_GAM6 0x80
|
#define REG_GAM7 0x81
|
#define REG_GAM8 0x82
|
#define REG_GAM9 0x83
|
#define REG_GAM10 0x84
|
#define REG_GAM11 0x85
|
#define REG_GAM12 0x86
|
#define REG_GAM13 0x87
|
#define REG_GAM14 0x88
|
#define REG_GAM15 0x89
|
|
#define REG_RGB444 0x8c /* RGB 444 control */
|
#define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */
|
#define R444_RGBX 0x01 /* Empty nibble at end */
|
#define REG_DM_LNL 0x92
|
#define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */
|
#define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */
|
#define REG_SCALING_PCLK_DELAY 0xa2
|
#define REG_BD50MAX 0xa5 /* 50hz banding step limit */
|
#define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */
|
#define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */
|
#define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */
|
#define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */
|
#define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */
|
#define REG_BD60MAX 0xab /* 60hz banding step limit */
|
|
#define REG_ABLC1 0xb1
|
#define REG_THL_DLT 0xb3
|
|
/** terminating list entry for register in configuration file */
|
#define OV_REG_TERM 0xff
|
/** terminating list entry for value in configuration file */
|
#define OV_VAL_TERM 0xff
|
|
/** define a structure for omnivision register initialization values */
|
typedef struct ov_regval_s
|
{
|
/** Register to be written */
|
uint8_t reg ;
|
/** Value to be written in the register */
|
uint8_t val ;
|
} ov_regval_t ;
|
|
|
|
const ov_regval_t ov7670_default_regs[] =
|
{
|
{REG_TSLB, 0x04},
|
{REG_HREF, 0x80},
|
{REG_HSTART, 0x16},
|
|
{REG_HSTOP, 0x04},//5
|
{REG_VSTART, 0x02},
|
{REG_VSTOP, 0x7b},//0x7a,
|
{REG_VREF, 0x06},//0x0a,
|
{REG_COM3, 0x0c},
|
{REG_COM10, 0x02},
|
{REG_COM14, 0x00},//10
|
{REG_SCALING_XSC, 0x00},
|
{REG_SCALING_YSC, 0x01},
|
{REG_SCALING_DCWCTR, 0x11},
|
{REG_SCALING_PC, 0x09},//
|
|
{REG_SCALING_PCLK_DELAY, 0x02},//Ëõ·ÅÊä³öÑÓʱ
|
{REG_CLKRC, 0x00},
|
|
{REG_SLOP, 0x20},
|
{REG_GAM1, 0x1c},
|
{REG_GAM2, 0x28},
|
{REG_GAM3, 0x3c},//20
|
{REG_GAM4, 0x55},
|
{REG_GAM5, 0x68},
|
{REG_GAM6, 0x76},
|
{REG_GAM7, 0x80},
|
{REG_GAM8, 0x88},
|
{REG_GAM9, 0x8f},
|
{REG_GAM10, 0x96},
|
{REG_GAM11, 0xa3},
|
{REG_GAM12, 0xaf},
|
{REG_GAM13, 0xc4},//30
|
{REG_GAM14, 0xd7},
|
{REG_GAM15, 0xe8},
|
|
{REG_COM8, 0xe0},
|
{REG_GAIN, 0x00},//AGC
|
|
{REG_AECH, 0x00},
|
{REG_COM4, 0x00},
|
{REG_BD50MAX, 0x05},
|
{REG_BD60MAX, 0x07},
|
|
{REG_AEW, 0x75},//40
|
{REG_AEB, 0x63},
|
{REG_VPT, 0xA5},
|
|
{REG_HAECC1, 0x78},
|
{REG_HAECC2, 0x68},
|
{REG_HAECC3, 0xdf},//0xd8,
|
{REG_HAECC4, 0xdf},//0xd8,
|
{REG_HAECC5, 0xf0},
|
{REG_HAECC6, 0x90},
|
{REG_HAECC7, 0x94},//50
|
|
{REG_COM8, 0xe5},
|
{REG_COM5, 0x61},
|
{REG_COM6, 0x4b},
|
|
{REG_MVFP, 0x37},//0x07,
|
{REG_ADCCTR1, 0x02},
|
{REG_ADCCTR2, 0x91},
|
{REG_CHLF, 0x0b},
|
|
{REG_ADC, 0x1d},
|
{REG_ACOM, 0x71},
|
{REG_OFON, 0x2a},
|
{REG_COM12, 0x78},
|
|
{REG_GFIX, 0x5d},
|
{REG_DBLV, 0x40},//PLL
|
{REG_REG74, 0x19},
|
|
{REG_DM_LNL, 0x00},//0x19,//0x66
|
|
{REG_ABLC1, 0x0c},
|
{REG_THL_DLT, 0x82},//80
|
|
/* AWBC1~AWBC6 */
|
{REG_AWBC1, 0x14},
|
{REG_AWBC2, 0xf0},
|
{REG_AWBC3, 0x34},
|
{REG_AWBC4, 0x58},
|
{REG_AWBC5, 0x28},
|
{REG_AWBC6, 0x3a},
|
|
/* LCCx */
|
{REG_LLC3, 0x04},
|
{REG_LLC4, 0x20},
|
{REG_LLC5, 0x05},
|
{REG_LLC6, 0x04},
|
{REG_LLC7, 0x08},
|
|
{REG_AWBCTR3, 0x0a},
|
{REG_AWBCTR2, 0x55},
|
{REG_AWBCTR1, 0x11},//100
|
{REG_AWBCTR0, 0x9f},//0x9e for advance AWB
|
|
{REG_BRIGHT, 0x00},//ÁÁ¶È
|
{REG_CONTRAS, 0x45},//¶Ô±È¶È
|
{REG_CONTRAS_CENTER, 0x80},
|
{OV_REG_TERM,OV_VAL_TERM},
|
};
|
|
const ov_regval_t ov7670_fmt_qvga_yuv422[] =
|
{
|
{ REG_COM7, COM7_FMT_QVGA }, /* Selects YUV mode */
|
{ REG_RGB444, 0 }, /* No RGB444 please */
|
{ REG_COM1, 0 }, /* CCIR601 */
|
{ REG_COM15, COM15_R00FF },
|
{ REG_COM9, 0x18 }, /* 4x gain ceiling; 0x8 is reserved bit */
|
{ REG_MTX1, 0x80 }, /* "matrix coefficient 1" */
|
{ REG_MTX2, 0x80 }, /* "matrix coefficient 2" */
|
{ REG_MTX3, 0 }, /* vb */
|
{ REG_MTX4, 0x22 }, /* "matrix coefficient 4" */
|
{ REG_MTX5, 0x5e }, /* "matrix coefficient 5" */
|
{ REG_MTX6, 0x80 }, /* "matrix coefficient 6" */
|
{ REG_COM13, COM13_GAMMA|COM13_UVSAT },
|
{OV_REG_TERM,OV_VAL_TERM},
|
};
|
|
const ov_regval_t ov7670_fmt_qvga_rgb565[] =
|
{
|
{ REG_COM7, COM7_FMT_QVGA|COM7_RGB }, /* Selects RGB mode */
|
{ REG_RGB444, 0 }, /* No RGB444 please */
|
{ REG_COM1, 0x0 }, /* CCIR601 */
|
{ REG_COM15, COM15_RGB565 },
|
{ REG_COM9, 0x0 }, /* ×Ô¶¯ÔöÒæÏÞ¶È-×î´óAGCÖµ 2X */
|
{ REG_MTX1, 0xb3 }, /* "matrix coefficient 1" */
|
{ REG_MTX2, 0xb3 }, /* "matrix coefficient 2" */
|
{ REG_MTX3, 0 }, /* vb */
|
{ REG_MTX4, 0x3d }, /* "matrix coefficient 4" */
|
{ REG_MTX5, 0xa7 }, /* "matrix coefficient 5" */
|
{ REG_MTX6, 0xe4 }, /* "matrix coefficient 6" */
|
{ REG_COM13, COM13_GAMMA|COM13_UVSAT },
|
{OV_REG_TERM,OV_VAL_TERM},
|
};
|
|
const ov_regval_t ov7670_fmt_qvga_rgb444[] =
|
{
|
{ REG_COM7, COM7_FMT_QVGA|COM7_RGB }, /* Selects RGB mode */
|
{ REG_RGB444, R444_ENABLE }, /* Enable xxxxrrrr ggggbbbb */
|
{ REG_COM1, 0x0 }, /* CCIR601 */
|
{ REG_COM15, COM15_R01FE|COM15_RGB565 }, /* Data range needed? */
|
{ REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */
|
{ REG_MTX1, 0xb3 }, /* "matrix coefficient 1" */
|
{ REG_MTX2, 0xb3 }, /* "matrix coefficient 2" */
|
{ REG_MTX3, 0 }, /* vb */
|
{ REG_MTX4, 0x3d }, /* "matrix coefficient 4" */
|
{ REG_MTX5, 0xa7 }, /* "matrix coefficient 5" */
|
{ REG_MTX6, 0xe4 }, /* "matrix coefficient 6" */
|
{ REG_COM13, COM13_GAMMA|COM13_UVSAT|0x2 }, /* Magic rsvd bit */
|
{OV_REG_TERM,OV_VAL_TERM},
|
};
|
|
const ov_regval_t ov7670_fmt_qvga_raw[] =
|
{
|
{ REG_COM7, COM7_FMT_QVGA|COM7_BAYER },
|
{ REG_COM13, 0x08 }, /* No gamma, magic rsvd bit */
|
{ REG_COM16, 0x3d }, /* Edge enhancement, denoise */
|
{ REG_REG76, 0xe1 }, /* Pix correction, magic rsvd */
|
{OV_REG_TERM,OV_VAL_TERM},
|
};
|
|
#endif /* End of __OV7670_REG_H */
|
