/**
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******************************************************************************
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* @file system_stm32f10x.c
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
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* @author STMicroelectronics - MCD Application Team
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* @version V3.0.0
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* @date 04/06/2009
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******************************************************************************
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
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******************************************************************************
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*/
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/** @addtogroup Private_Includes
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* @{
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*/
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#include "stm32f10x.h"
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/**
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* @}
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*/
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/** @addtogroup Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup Private_Defines
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* @{
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*/
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/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
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frequency (after reset the HSI is used as SYSCLK source) */
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//#define SYSCLK_FREQ_HSE HSE_Value
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//#define SYSCLK_FREQ_20MHz 20000000
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//#define SYSCLK_FREQ_36MHz 36000000
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//#define SYSCLK_FREQ_48MHz 48000000
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//#define SYSCLK_FREQ_56MHz 56000000
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#define SYSCLK_FREQ_72MHz 72000000
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/*!< Uncomment the following line if you need to use external SRAM mounted
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on STM3210E-EVAL board (STM32 High density devices) as data memory */
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#ifdef STM32F10X_HD
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/* #define DATA_IN_ExtSRAM */
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#endif /* STM32F10X_HD */
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/**
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* @}
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*/
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/** @addtogroup Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup Private_Variables
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* @{
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*/
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/*******************************************************************************
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* Clock Definitions
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*******************************************************************************/
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#ifdef SYSCLK_FREQ_HSE
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const uint32_t SystemFrequency = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
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const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_HSE; /*!< System clock */
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const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_HSE; /*!< AHB System bus speed */
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const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_HSE; /*!< APB Peripheral bus 1 (low) speed */
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const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_HSE; /*!< APB Peripheral bus 2 (high) speed */
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#elif defined SYSCLK_FREQ_20MHz
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const uint32_t SystemFrequency = SYSCLK_FREQ_20MHz; /*!< System Clock Frequency (Core Clock) */
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const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_20MHz; /*!< System clock */
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const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_20MHz; /*!< AHB System bus speed */
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const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_20MHz; /*!< APB Peripheral bus 1 (low) speed */
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const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_20MHz; /*!< APB Peripheral bus 2 (high) speed */
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#elif defined SYSCLK_FREQ_36MHz
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const uint32_t SystemFrequency = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */
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const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_36MHz; /*!< System clock */
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const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_36MHz; /*!< AHB System bus speed */
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const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_36MHz; /*!< APB Peripheral bus 1 (low) speed */
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const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_36MHz; /*!< APB Peripheral bus 2 (high) speed */
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#elif defined SYSCLK_FREQ_48MHz
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const uint32_t SystemFrequency = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */
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const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_48MHz; /*!< System clock */
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const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_48MHz; /*!< AHB System bus speed */
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const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_48MHz/2); /*!< APB Peripheral bus 1 (low) speed */
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const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_48MHz; /*!< APB Peripheral bus 2 (high) speed */
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#elif defined SYSCLK_FREQ_56MHz
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const uint32_t SystemFrequency = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */
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const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_56MHz; /*!< System clock */
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const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_56MHz; /*!< AHB System bus speed */
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const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_56MHz/2); /*!< APB Peripheral bus 1 (low) speed */
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const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_56MHz; /*!< APB Peripheral bus 2 (high) speed */
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#elif defined SYSCLK_FREQ_72MHz
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const uint32_t SystemFrequency = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */
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const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_72MHz; /*!< System clock */
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const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_72MHz; /*!< AHB System bus speed */
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const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_72MHz/2); /*!< APB Peripheral bus 1 (low) speed */
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const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_72MHz; /*!< APB Peripheral bus 2 (high) speed */
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#else /*!< HSI Selected as System Clock source */
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const uint32_t SystemFrequency = HSI_Value; /*!< System Clock Frequency (Core Clock) */
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const uint32_t SystemFrequency_SysClk = HSI_Value; /*!< System clock */
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const uint32_t SystemFrequency_AHBClk = HSI_Value; /*!< AHB System bus speed */
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const uint32_t SystemFrequency_APB1Clk = HSI_Value; /*!< APB Peripheral bus 1 (low) speed */
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const uint32_t SystemFrequency_APB2Clk = HSI_Value; /*!< APB Peripheral bus 2 (high) speed */
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#endif
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/**
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* @}
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*/
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/** @addtogroup Private_FunctionPrototypes
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* @{
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*/
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static void SetSysClock(void);
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#ifdef SYSCLK_FREQ_HSE
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static void SetSysClockToHSE(void);
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#elif defined SYSCLK_FREQ_20MHz
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static void SetSysClockTo20(void);
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#elif defined SYSCLK_FREQ_36MHz
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static void SetSysClockTo36(void);
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#elif defined SYSCLK_FREQ_48MHz
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static void SetSysClockTo48(void);
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#elif defined SYSCLK_FREQ_56MHz
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static void SetSysClockTo56(void);
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#elif defined SYSCLK_FREQ_72MHz
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static void SetSysClockTo72(void);
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#endif
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/**
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* @}
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*/
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/** @addtogroup Private_Functions
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* @{
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*/
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/**
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* @brief Setup the microcontroller system
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* Initialize the Embedded Flash Interface, initialize the PLL and update th SystemFrequency variable
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* @param None.
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* @arg None.
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* @note : This function should be used only after reset.
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* @retval value: None.
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*/
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void SystemInit (void)
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{
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/*!< RCC system reset(for debug purpose) */
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/*!< Set HSION bit */
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RCC->CR |= (uint32_t)0x00000001;
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/*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits */
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RCC->CFGR &= (uint32_t)0xF8FF0000;
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/*!< Reset HSEON, CSSON and PLLON bits */
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RCC->CR &= (uint32_t)0xFEF6FFFF;
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/*!< Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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/*!< Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */
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RCC->CFGR &= (uint32_t)0xFF80FFFF;
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/*!< Disable all interrupts */
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RCC->CIR = 0x00000000;
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/*!< Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
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/*!< Configure the Flash Latency cycles and enable prefetch buffer */
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SetSysClock();
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}
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/**
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* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1
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* prescalers.
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* @param None.
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* @arg None.
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* @note : None.
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* @retval value: None.
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*/
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static void SetSysClock(void)
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{
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#ifdef SYSCLK_FREQ_HSE
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SetSysClockToHSE();
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#elif defined SYSCLK_FREQ_20MHz
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SetSysClockTo20();
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#elif defined SYSCLK_FREQ_36MHz
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SetSysClockTo36();
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#elif defined SYSCLK_FREQ_48MHz
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SetSysClockTo48();
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#elif defined SYSCLK_FREQ_56MHz
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SetSysClockTo56();
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#elif defined SYSCLK_FREQ_72MHz
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SetSysClockTo72();
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#endif
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/*!< If none of the define above is enabled, the HSI is used as System clock
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source (default after reset) */
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}
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/**
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* @brief Setup the external memory controller. Called in startup_stm32f10x.s
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* before jump to __main
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* @param None.
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* @arg None.
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* @note : None.
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* @retval value: None.
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*/
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#ifdef DATA_IN_ExtSRAM
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/**
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* @brief Setup the external memory controller.
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* Called in startup_stm32f10x_xx.s/.c before jump to main.
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* This function configures the external SRAM mounted on STM3210E-EVAL
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* board (STM32 High density devices). This SRAM will be used as program
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* data memory (including heap and stack).
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* @param None.
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* @arg None.
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* @note : None.
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* @retval value: None.
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*/
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void SystemInit_ExtMemCtl(void)
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{
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/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
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required, then adjust the Register Addresses */
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/*!< Enable FSMC clock */
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RCC->AHBENR = 0x00000114;
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/*!< Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
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RCC->APB2ENR = 0x000001E0;
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/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
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/*---------------- SRAM Address lines configuration -------------------------*/
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/*---------------- NOE and NWE configuration --------------------------------*/
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/*---------------- NE3 configuration ----------------------------------------*/
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/*---------------- NBL0, NBL1 configuration ---------------------------------*/
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GPIOD->CRL = 0x44BB44BB;
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GPIOD->CRH = 0xBBBBBBBB;
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GPIOE->CRL = 0xB44444BB;
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GPIOE->CRH = 0xBBBBBBBB;
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GPIOF->CRL = 0x44BBBBBB;
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GPIOF->CRH = 0xBBBB4444;
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GPIOG->CRL = 0x44BBBBBB;
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GPIOG->CRH = 0x44444B44;
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/*---------------- FSMC Configuration ---------------------------------------*/
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/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
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FSMC_Bank1->BTCR[4] = 0x00001011;
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FSMC_Bank1->BTCR[5] = 0x00000200;
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}
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#endif /* DATA_IN_ExtSRAM */
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#ifdef SYSCLK_FREQ_HSE
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/**
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* @brief Selects HSE as System clock source and configure HCLK, PCLK2
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* and PCLK1 prescalers.
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* @param None.
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* @arg None.
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* @note : This function should be used only after reset.
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* @retval value: None.
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*/
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static void SetSysClockToHSE(void)
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{
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__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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/*!< SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
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/*!< Enable HSE */
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RCC->CR |= ((uint32_t)RCC_CR_HSEON);
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/*!< Wait till HSE is ready and if Time out is reached exit */
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do
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{
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HSEStatus = RCC->CR & RCC_CR_HSERDY;
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StartUpCounter++;
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} while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
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if ((RCC->CR & RCC_CR_HSERDY) != RESET)
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{
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HSEStatus = (uint32_t)0x01;
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}
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else
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{
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HSEStatus = (uint32_t)0x00;
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}
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if (HSEStatus == (uint32_t)0x01)
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{
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/*!< Enable Prefetch Buffer */
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FLASH->ACR |= FLASH_ACR_PRFTBE;
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/*!< Flash 0 wait state */
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FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
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FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
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/*!< HCLK = SYSCLK */
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RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
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/*!< PCLK2 = HCLK */
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RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
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/*!< PCLK1 = HCLK */
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RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
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/*!< Select HSE as system clock source */
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RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
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RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
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/*!< Wait till HSE is used as system clock source */
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while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
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{
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}
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}
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else
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{ /*!< If HSE fails to start-up, the application will have wrong clock
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configuration. User can add here some code to deal with this error */
|
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/*!< Go to infinite loop */
|
while (1)
|
{
|
}
|
}
|
}
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#elif defined SYSCLK_FREQ_20MHz
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/**
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* @brief Sets System clock frequency to 20MHz and configure HCLK, PCLK2
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* and PCLK1 prescalers.
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* @param None.
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* @arg None.
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* @note : This function should be used only after reset.
|
* @retval value: None.
|
*/
|
static void SetSysClockTo20(void)
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{
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__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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/*!< SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
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/*!< Enable HSE */
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RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
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/*!< Wait till HSE is ready and if Time out is reached exit */
|
do
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{
|
HSEStatus = RCC->CR & RCC_CR_HSERDY;
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StartUpCounter++;
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} while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
|
|
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
{
|
HSEStatus = (uint32_t)0x01;
|
}
|
else
|
{
|
HSEStatus = (uint32_t)0x00;
|
}
|
|
if (HSEStatus == (uint32_t)0x01)
|
{
|
/*!< Enable Prefetch Buffer */
|
FLASH->ACR |= FLASH_ACR_PRFTBE;
|
|
/*!< Flash 0 wait state */
|
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
|
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
|
|
/*!< HCLK = SYSCLK */
|
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
|
|
/*!< PCLK2 = HCLK */
|
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
|
|
/*!< PCLK1 = HCLK */
|
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
|
|
/*!< PLLCLK = (8MHz / 2) * 5 = 20 MHz */
|
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
|
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL5);
|
|
/*!< Enable PLL */
|
RCC->CR |= RCC_CR_PLLON;
|
|
/*!< Wait till PLL is ready */
|
while((RCC->CR & RCC_CR_PLLRDY) == 0)
|
{
|
}
|
|
/*!< Select PLL as system clock source */
|
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
|
|
/*!< Wait till PLL is used as system clock source */
|
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
|
{
|
}
|
}
|
else
|
{ /*!< If HSE fails to start-up, the application will have wrong clock
|
configuration. User can add here some code to deal with this error */
|
|
/*!< Go to infinite loop */
|
while (1)
|
{
|
}
|
}
|
}
|
#elif defined SYSCLK_FREQ_36MHz
|
/**
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* @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
|
* and PCLK1 prescalers.
|
* @param None.
|
* @arg None.
|
* @note : This function should be used only after reset.
|
* @retval value: None.
|
*/
|
static void SetSysClockTo36(void)
|
{
|
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
|
/*!< SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
|
/*!< Enable HSE */
|
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
|
/*!< Wait till HSE is ready and if Time out is reached exit */
|
do
|
{
|
HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
StartUpCounter++;
|
} while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
|
|
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
{
|
HSEStatus = (uint32_t)0x01;
|
}
|
else
|
{
|
HSEStatus = (uint32_t)0x00;
|
}
|
|
if (HSEStatus == (uint32_t)0x01)
|
{
|
/*!< Enable Prefetch Buffer */
|
FLASH->ACR |= FLASH_ACR_PRFTBE;
|
|
/*!< Flash 1 wait state */
|
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
|
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
|
|
/*!< HCLK = SYSCLK */
|
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
|
|
/*!< PCLK2 = HCLK */
|
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
|
|
/*!< PCLK1 = HCLK */
|
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
|
|
/*!< PLLCLK = (8MHz / 2) * 9 = 36 MHz */
|
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
|
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL9);
|
|
/*!< Enable PLL */
|
RCC->CR |= RCC_CR_PLLON;
|
|
/*!< Wait till PLL is ready */
|
while((RCC->CR & RCC_CR_PLLRDY) == 0)
|
{
|
}
|
|
/*!< Select PLL as system clock source */
|
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
|
|
/*!< Wait till PLL is used as system clock source */
|
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
|
{
|
}
|
}
|
else
|
{ /*!< If HSE fails to start-up, the application will have wrong clock
|
configuration. User can add here some code to deal with this error */
|
|
/*!< Go to infinite loop */
|
while (1)
|
{
|
}
|
}
|
}
|
#elif defined SYSCLK_FREQ_48MHz
|
/**
|
* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
|
* and PCLK1 prescalers.
|
* @param None.
|
* @arg None.
|
* @note : This function should be used only after reset.
|
* @retval value: None.
|
*/
|
static void SetSysClockTo48(void)
|
{
|
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
|
/*!< SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
|
/*!< Enable HSE */
|
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
|
/*!< Wait till HSE is ready and if Time out is reached exit */
|
do
|
{
|
HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
StartUpCounter++;
|
} while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
|
|
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
{
|
HSEStatus = (uint32_t)0x01;
|
}
|
else
|
{
|
HSEStatus = (uint32_t)0x00;
|
}
|
|
if (HSEStatus == (uint32_t)0x01)
|
{
|
/*!< Enable Prefetch Buffer */
|
FLASH->ACR |= FLASH_ACR_PRFTBE;
|
|
/*!< Flash 1 wait state */
|
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
|
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
|
|
/*!< HCLK = SYSCLK */
|
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
|
|
/*!< PCLK2 = HCLK */
|
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
|
|
/*!< PCLK1 = HCLK */
|
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
|
|
/*!< PLLCLK = 8MHz * 6 = 48 MHz */
|
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
|
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL6);
|
|
/*!< Enable PLL */
|
RCC->CR |= RCC_CR_PLLON;
|
|
/*!< Wait till PLL is ready */
|
while((RCC->CR & RCC_CR_PLLRDY) == 0)
|
{
|
}
|
|
/*!< Select PLL as system clock source */
|
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
|
|
/*!< Wait till PLL is used as system clock source */
|
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
|
{
|
}
|
}
|
else
|
{ /*!< If HSE fails to start-up, the application will have wrong clock
|
configuration. User can add here some code to deal with this error */
|
|
/*!< Go to infinite loop */
|
while (1)
|
{
|
}
|
}
|
}
|
|
#elif defined SYSCLK_FREQ_56MHz
|
/**
|
* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2
|
* and PCLK1 prescalers.
|
* @param None.
|
* @arg None.
|
* @note : This function should be used only after reset.
|
* @retval value: None.
|
*/
|
static void SetSysClockTo56(void)
|
{
|
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
|
/*!< SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
|
/*!< Enable HSE */
|
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
|
/*!< Wait till HSE is ready and if Time out is reached exit */
|
do
|
{
|
HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
StartUpCounter++;
|
} while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
|
|
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
{
|
HSEStatus = (uint32_t)0x01;
|
}
|
else
|
{
|
HSEStatus = (uint32_t)0x00;
|
}
|
|
if (HSEStatus == (uint32_t)0x01)
|
{
|
/*!< Enable Prefetch Buffer */
|
FLASH->ACR |= FLASH_ACR_PRFTBE;
|
|
/*!< Flash 1 wait state */
|
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
|
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
|
|
/*!< HCLK = SYSCLK */
|
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
|
|
/*!< PCLK2 = HCLK */
|
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
|
|
/*!< PCLK1 = HCLK */
|
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
|
|
/*!< PLLCLK = 8MHz * 7 = 56 MHz */
|
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
|
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL7);
|
|
/*!< Enable PLL */
|
RCC->CR |= RCC_CR_PLLON;
|
|
/*!< Wait till PLL is ready */
|
while((RCC->CR & RCC_CR_PLLRDY) == 0)
|
{
|
}
|
|
/*!< Select PLL as system clock source */
|
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
|
|
/*!< Wait till PLL is used as system clock source */
|
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
|
{
|
}
|
}
|
else
|
{ /*!< If HSE fails to start-up, the application will have wrong clock
|
configuration. User can add here some code to deal with this error */
|
|
/*!< Go to infinite loop */
|
while (1)
|
{
|
}
|
}
|
}
|
|
#elif defined SYSCLK_FREQ_72MHz
|
/**
|
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
|
* and PCLK1 prescalers.
|
* @param None.
|
* @arg None.
|
* @note : This function should be used only after reset.
|
* @retval value: None.
|
*/
|
static void SetSysClockTo72(void)
|
{
|
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
|
/*!< SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
|
/*!< Enable HSE */
|
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
|
/*!< Wait till HSE is ready and if Time out is reached exit */
|
do
|
{
|
HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
StartUpCounter++;
|
} while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
|
|
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
{
|
HSEStatus = (uint32_t)0x01;
|
}
|
else
|
{
|
HSEStatus = (uint32_t)0x00;
|
}
|
|
if (HSEStatus == (uint32_t)0x01)
|
{
|
/*!< Enable Prefetch Buffer */
|
FLASH->ACR |= FLASH_ACR_PRFTBE;
|
|
/*!< Flash 2 wait state */
|
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
|
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
|
|
/*!< HCLK = SYSCLK */
|
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
|
|
/*!< PCLK2 = HCLK */
|
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
|
|
/*!< PCLK1 = HCLK */
|
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
|
|
/*!< PLLCLK = 8MHz * 9 = 72 MHz */
|
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
|
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL9);
|
|
/*!< Enable PLL */
|
RCC->CR |= RCC_CR_PLLON;
|
|
/*!< Wait till PLL is ready */
|
while((RCC->CR & RCC_CR_PLLRDY) == 0)
|
{
|
}
|
|
/*!< Select PLL as system clock source */
|
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
|
|
/*!< Wait till PLL is used as system clock source */
|
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
|
{
|
}
|
}
|
else
|
{ /*!< If HSE fails to start-up, the application will have wrong clock
|
configuration. User can add here some code to deal with this error */
|
|
/*!< Go to infinite loop */
|
while (1)
|
{
|
}
|
}
|
}
|
#endif
|
|
/**
|
* @}
|
*/
|
|
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
|
