update linux patch, add 4G/NB-IoT and overlays support

guowenxue

2022-06-30 472531a0e14cf3d83d241cf26dbc2ef47a4108d9

 bsp/kernel/patch/linux-imx-igkboard.patch

@@ -1,7 +1,7 @@
diff -Nuar -x include-prefixes -x logo_linux_clut224.ppm linux-imx/arch/arm/boot/dts/igkboard.dts linux-imx-igkboard/arch/arm/boot/dts/igkboard.dts
--- linux-imx/arch/arm/boot/dts/igkboard.dts   1970-01-01 08:00:00.000000000 +0800
+++ linux-imx-igkboard/arch/arm/boot/dts/igkboard.dts   2022-04-14 19:53:27.986034399 +0800
@@ -0,0 +1,801 @@
+++ linux-imx-igkboard/arch/arm/boot/dts/igkboard.dts   2022-03-27 22:09:19.799996369 +0800
@@ -0,0 +1,782 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for LingYun IGKBoard(IoT Gateway Kit Board)
@@ -121,6 +121,7 @@
+      regulator-name = "can-3v3";
+      regulator-min-microvolt = <3300000>;
+      regulator-max-microvolt = <3300000>;
+      gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
+   };
+
+   reg_3p3v: 3p3v {
@@ -152,87 +153,36 @@
+   };
+*/
+
+   spi4 {
+      compatible = "spi-gpio";
+      pinctrl-names = "default";
+      pinctrl-0 = <&pinctrl_spi4>;
+      status = "disabled"; /* MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 conflict with fec1 reset pin */
+      pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
+      gpio-sck = <&gpio5 11 0>;
+      gpio-mosi = <&gpio5 10 0>;
+      cs-gpios = <&gpio5 7 0>;
+      num-chipselects = <1>;
+      #address-cells = <1>;
+      #size-cells = <0>;
+
+      gpio_spi: gpio@0 {
+         compatible = "fairchild,74hc595";
+         gpio-controller;
+         #gpio-cells = <2>;
+         reg = <0>;
+         registers-number = <1>;
+         registers-default = /bits/ 8 <0x57>;
+         spi-max-frequency = <100000>;
+      };
+   };
+};
+
+
+&clks {
+   assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+   assigned-clock-rates = <786432000>;
+};
+
+/* 40Pin Header start */
+&i2c1 {
+   clock-frequency = <100000>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c1>;
+   status = "okay";
+};
+
+&uart2 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_uart2>;
+   status = "okay";
+};
+
+&uart3 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_uart3>;
+   status = "okay";
+};
+
+&uart4 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_uart4>;
+   status = "okay";
+};
+
+&uart7 { /* conflict with lcdif */
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_uart7>;
+   status = "okay";
+};
+
+&ecspi1 { /* conflict with lcdif */
+   cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_ecspi1>;
+   status = "okay";
+
+   spidev@0 {
+      compatible = "semtech,sx1301";
+      reg = <0>;
+      spi-max-frequency = <2000000>;
+   };
+};
+
+&pwm7 {
+   #pwm-cells = <2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_pwm7>;
+   status = "okay";
+};
+
+&pwm8 {
+   #pwm-cells = <2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_pwm8>;
+   status = "okay";
+};
+
+&can1 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_flexcan1>;
+    xceiver-supply = <&reg_can_3v3>;
+    status = "okay";
+};
+
+/* CAN2 is multiplexed with UART2 RTS/CTS */
+&can2 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_flexcan2>;
+    xceiver-supply = <&reg_can_3v3>;
+    status = "okay";
+};
+/* 40Pin Header end */
+
+&snvs_poweroff {
+   status = "okay";
@@ -245,6 +195,16 @@
+&uart1 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_uart1>;
+   status = "okay";
+};
+
+&uart2 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_uart2>;
+   uart-has-rtscts;
+   /* for DTE mode, add below change */
+   /* fsl,dte-mode; */
+   /* pinctrl-0 = <&pinctrl_uart2dte>; */
+   status = "okay";
+};
+
@@ -417,6 +377,40 @@
+};
+*/
+
+&sai1 {
+   assigned-clocks = <&clks IMX6UL_CLK_SAI1_SEL>,
+           <&clks IMX6UL_CLK_SAI1>;
+   assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+   assigned-clock-rates = <0>, <24576000>;
+   fsl,sai-mclk-direction-output;
+   status = "okay";
+};
+
+&sim2 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_sim2>;
+   assigned-clocks = <&clks IMX6UL_CLK_SIM_SEL>;
+   assigned-clock-parents = <&clks IMX6UL_CLK_SIM_PODF>;
+   assigned-clock-rates = <240000000>;
+   /* GPIO_ACTIVE_HIGH/LOW:sim card voltage control
+    * NCN8025:Vcc = ACTIVE_HIGH?5V:3V
+    * TDA8035:Vcc = ACTIVE_HIGH?5V:1.8V
+    */
+   pinctrl-assert-gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>;
+   port = <1>;
+   sven_low_active;
+   status = "disabled";
+};
+
+&tsc {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_tsc>;
+   xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+   measure-delay-time = <0xffff>;
+   pre-charge-time = <0xfff>;
+   status = "okay";
+};
+
+&usbotg1 {
+   dr_mode = "otg";
+   pinctrl-names = "default";
@@ -465,97 +459,6 @@
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_wdog>;
+   fsl,ext-reset-output;
+};
+
+/* 40Pin Header pinctrl */
+&iomuxc {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_extgpio>;
+
+   igkboard_extpin {
+      pinctrl_extgpio: extgpiogrp{
+         fsl,pins = <
+            MX6UL_PAD_UART1_CTS_B__GPIO1_IO18   0x17059 /*  7#  GPIO    */
+            MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01  0x17059 /* 35#  GPIO    */
+            MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08  0x17059 /* 37#  GPIO    */
+            MX6UL_PAD_LCD_DATA18__GPIO3_IO23    0x17059 /* 22# GPIO     */
+            MX6UL_PAD_LCD_DATA19__GPIO3_IO24    0x17059 /* 26# GPIO     */
+            MX6UL_PAD_JTAG_TMS__GPIO1_IO11      0x17059 /* 36# GPIO */
+            MX6UL_PAD_JTAG_MOD__GPIO1_IO10      0x17059 /* 38# GPIO */
+            MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09  0x17059 /* 40# GPIO */
+         >;
+      };
+
+      pinctrl_i2c1: i2c1grp {
+         fsl,pins = <
+            MX6UL_PAD_GPIO1_IO03__I2C1_SDA      0x4001b8b0
+            MX6UL_PAD_GPIO1_IO02__I2C1_SCL      0x4001b8b0
+         >;
+      };
+
+      pinctrl_uart2: uart2grp {
+         fsl,pins = <
+            MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x1b0b1
+            MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x1b0b1
+         >;
+      };
+
+      pinctrl_uart3: uart3grp {
+         fsl,pins = <
+            MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX   0x1b0b1
+            MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX   0x1b0b1
+         >;
+      };
+
+      pinctrl_uart4: uart4grp {
+         fsl,pins = <
+            MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX   0x1b0b1
+            MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX   0x1b0b1
+         >;
+      };
+
+      pinctrl_uart7: uart7grp {
+         fsl,pins = <
+            MX6UL_PAD_LCD_DATA16__UART7_DCE_TX      0x1b0b1
+            MX6UL_PAD_LCD_DATA17__UART7_DCE_RX      0x1b0b1
+         >;
+      };
+
+      pinctrl_ecspi1: ecspi1-grp {
+         fsl,pins = <
+            MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK   0x10b0
+            MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI   0x10b0
+            MX6UL_PAD_LCD_DATA23__ECSPI1_MISO   0x10b0
+            MX6UL_PAD_LCD_DATA21__GPIO3_IO26    0x10b0
+         >;
+      };
+
+      pinctrl_pwm7: pwm7grp {
+         fsl,pins = <
+            MX6UL_PAD_JTAG_TCK__PWM7_OUT      0x110b0
+         >;
+      };
+
+      pinctrl_pwm8: pwm8grp {
+         fsl,pins = <
+            MX6UL_PAD_JTAG_TRST_B__PWM8_OUT      0x110b0
+         >;
+      };
+
+      pinctrl_flexcan1: flexcan1grp{
+         fsl,pins = <
+            MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX   0x1b020
+            MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX   0x1b020
+         >;
+      };
+
+      pinctrl_flexcan2: flexcan2grp{
+         fsl,pins = <
+            MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX   0x1b020
+            MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX   0x1b020
+         >;
+      };
+   };
+};
+
+&iomuxc {
@@ -634,6 +537,27 @@
+      >;
+   };
+
+   pinctrl_flexcan1: flexcan1grp{
+      fsl,pins = <
+         MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX   0x1b020
+         MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX   0x1b020
+      >;
+   };
+
+   pinctrl_flexcan2: flexcan2grp{
+      fsl,pins = <
+         MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX   0x1b020
+         MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX   0x1b020
+      >;
+   };
+
+   pinctrl_i2c1: i2c1grp {
+      fsl,pins = <
+         MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
+         MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+      >;
+   };
+
+   pinctrl_i2c2: i2c2grp {
+      fsl,pins = <
+         MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
@@ -681,6 +605,16 @@
+      >;
+   };
+
+   pinctrl_sai2: sai2grp {
+      fsl,pins = <
+         MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK   0x17088
+         MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC   0x17088
+         MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
+         MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA   0x11088
+         MX6UL_PAD_JTAG_TMS__SAI2_MCLK      0x17088
+      >;
+   };
+
+   pinctrl_pwm1: pwm1grp {
+      fsl,pins = <
+         MX6UL_PAD_GPIO1_IO08__PWM1_OUT    0x110b0
@@ -693,10 +627,56 @@
+      >;
+   };
+
+   pinctrl_sim2: sim2grp {
+      fsl,pins = <
+         MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD      0xb808
+         MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK      0x31
+         MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B      0xb808
+         MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN      0xb808
+         MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD      0xb809
+         MX6UL_PAD_CSI_DATA02__GPIO4_IO23      0x3008
+      >;
+   };
+
+   pinctrl_spi4: spi4grp {
+      fsl,pins = <
+         MX6UL_PAD_BOOT_MODE0__GPIO5_IO10   0x70a1
+         MX6UL_PAD_BOOT_MODE1__GPIO5_IO11   0x70a1
+         MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08   0x80000000
+      >;
+   };
+
+   pinctrl_tsc: tscgrp {
+      fsl,pins = <
+         MX6UL_PAD_GPIO1_IO01__GPIO1_IO01      0xb0
+         MX6UL_PAD_GPIO1_IO02__GPIO1_IO02      0xb0
+         MX6UL_PAD_GPIO1_IO03__GPIO1_IO03      0xb0
+         MX6UL_PAD_GPIO1_IO04__GPIO1_IO04      0xb0
+      >;
+   };
+
+   pinctrl_uart1: uart1grp {
+      fsl,pins = <
+         MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+         MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+      >;
+   };
+
+   pinctrl_uart2: uart2grp {
+      fsl,pins = <
+         MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x1b0b1
+         MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x1b0b1
+         MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS   0x1b0b1
+         MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS   0x1b0b1
+      >;
+   };
+
+   pinctrl_uart2dte: uart2dtegrp {
+      fsl,pins = <
+         MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX   0x1b0b1
+         MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX   0x1b0b1
+         MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS   0x1b0b1
+         MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS   0x1b0b1
+      >;
+   };
+
@@ -726,6 +706,7 @@
+         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
+         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
+         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
+
+      >;
+   };
+
@@ -805,7 +786,7 @@
+
diff -Nuar -x include-prefixes -x logo_linux_clut224.ppm linux-imx/arch/arm/boot/dts/Makefile linux-imx-igkboard/arch/arm/boot/dts/Makefile
--- linux-imx/arch/arm/boot/dts/Makefile   2021-09-08 18:41:11.000000000 +0800
+++ linux-imx-igkboard/arch/arm/boot/dts/Makefile   2022-04-13 23:15:49.155016887 +0800
+++ linux-imx-igkboard/arch/arm/boot/dts/Makefile   2022-03-27 22:09:19.799996369 +0800
@@ -678,6 +678,7 @@
    imx6ul-tx6ul-0010.dtb \
    imx6ul-tx6ul-0011.dtb \
@@ -816,7 +797,7 @@
    imx6ull-14x14-evk-btwifi.dtb \
diff -Nuar -x include-prefixes -x logo_linux_clut224.ppm linux-imx/arch/arm/configs/igkboard_defconfig linux-imx-igkboard/arch/arm/configs/igkboard_defconfig
--- linux-imx/arch/arm/configs/igkboard_defconfig   1970-01-01 08:00:00.000000000 +0800
+++ linux-imx-igkboard/arch/arm/configs/igkboard_defconfig   2022-04-14 20:08:27.465008910 +0800
+++ linux-imx-igkboard/arch/arm/configs/igkboard_defconfig   2022-03-27 22:20:23.534446767 +0800
@@ -0,0 +1,722 @@
+CONFIG_KERNEL_LZO=y
+CONFIG_SYSVIPC=y
@@ -1540,35 +1521,9 @@
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_FTRACE is not set
diff -Nuar -x include-prefixes -x logo_linux_clut224.ppm linux-imx/do.sh linux-imx-igkboard/do.sh
--- linux-imx/do.sh   1970-01-01 08:00:00.000000000 +0800
+++ linux-imx-igkboard/do.sh   2022-04-14 19:56:04.963080600 +0800
@@ -0,0 +1,22 @@
+#!/bin/bash
+
+INST_PATH=/srv/ftp/pub/
+
+JOBS=`cat /proc/cpuinfo | grep processor | wc -l`
+
+function do_build()
+{
+   make igkboard_defconfig
+   make -j ${JOBS}
+}
+
+function do_install()
+{
+   set -x
+   cp arch/arm/boot/zImage $INST_PATH
+   cp arch/arm/boot/dts/igkboard.dtb $INST_PATH
+}
+
+do_build
+
+#do_install
diff -Nuar -x include-prefixes -x logo_linux_clut224.ppm linux-imx/Makefile linux-imx-igkboard/Makefile
--- linux-imx/Makefile   2021-09-08 18:41:11.000000000 +0800
+++ linux-imx-igkboard/Makefile   2022-04-14 20:05:02.060376092 +0800
+++ linux-imx-igkboard/Makefile   2022-03-27 22:09:19.803996342 +0800
@@ -367,7 +367,8 @@
 # Alternatively CROSS_COMPILE can be set in the environment.
 # Default value for CROSS_COMPILE is not to prefix executables