update uboot,linux kernel patch to remove space

guowenxue

2022-10-06 e77618540841b570ae6688e5f9469c77c0619112

 bsp/bootloader/patch/uboot-imx-lf-5.10.52-2.1.0.patch

@@ -1,6 +1,6 @@
diff -Nuar -x lingyun.bmp uboot-imx/arch/arm/dts/igkboard.dts uboot-imx-lf-5.10.52-2.1.0/arch/arm/dts/igkboard.dts
--- uboot-imx/arch/arm/dts/igkboard.dts   1970-01-01 08:00:00.000000000 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/arch/arm/dts/igkboard.dts   2022-06-05 20:35:49.127986610 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/arch/arm/dts/igkboard.dts   2022-06-30 20:28:15.839187950 +0800
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
@@ -23,7 +23,7 @@
+};
diff -Nuar -x lingyun.bmp uboot-imx/arch/arm/dts/imx6ul-14x14-evk.dtsi uboot-imx-lf-5.10.52-2.1.0/arch/arm/dts/imx6ul-14x14-evk.dtsi
--- uboot-imx/arch/arm/dts/imx6ul-14x14-evk.dtsi   2021-09-06 16:48:23.000000000 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/arch/arm/dts/imx6ul-14x14-evk.dtsi   2022-06-05 20:35:49.127986610 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/arch/arm/dts/imx6ul-14x14-evk.dtsi   2022-06-30 20:28:15.839187950 +0800
@@ -21,7 +21,6 @@
       regulator-name = "VSD_3V3";
       regulator-min-microvolt = <3300000>;
@@ -36,25 +36,25 @@
    pinctrl-0 = <&pinctrl_enet1>;
    phy-mode = "rmii";
    phy-handle = <&ethphy0>;
+    phy-reset-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>;
+    phy-reset-duration = <50>;
+    phy-reset-post-delay = <15>;
+   phy-reset-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>;
+   phy-reset-duration = <50>;
+   phy-reset-post-delay = <15>;
    status = "okay";
 };
 

@@ -91,14 +93,17 @@
    pinctrl-0 = <&pinctrl_enet2>;
    phy-mode = "rmii";
    phy-handle = <&ethphy1>;
+    phy-reset-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
+    phy-reset-duration = <50>;
+    phy-reset-post-delay = <15>;
+   phy-reset-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
+   phy-reset-duration = <50>;
+   phy-reset-post-delay = <15>;
    status = "okay";
 

    mdio {
       #address-cells = <1>;
       #size-cells = <0>;
 

-      ethphy0: ethernet-phy@2 {
-         reg = <2>;
+      ethphy0: ethernet-phy@0 {
@@ -62,15 +62,22 @@
          micrel,led-mode = <1>;
          clocks = <&clks IMX6UL_CLK_ENET_REF>;
          clock-names = "rmii-ref";
@@ -151,21 +156,21 @@
@@ -145,27 +150,27 @@
 &lcdif {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_lcdif_dat
-           &pinctrl_lcdif_ctrl>;
+          &pinctrl_lcdif_ctrl>;

    display = <&display0>;
    status = "okay";
 

    display0: display@0 {
-      bits-per-pixel = <24>;
-      bus-width = <24>;
+      bits-per-pixel = <16>;
+      bus-width = <16>;
 

       display-timings {
          native-mode = <&timing0>;
          timing0: timing0 {
@@ -92,34 +99,180 @@
+         vback-porch = <32>;
+         vfront-porch = <13>;
+         vsync-len = <3>;
 

          hsync-active = <0>;
          vsync-active = <0>;
@@ -312,6 +317,7 @@
          MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00   0x1b0b0
          MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01   0x1b0b0
@@ -284,6 +289,40 @@

 &iomuxc {
    pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_extgpio>;
+
+   pinctrl_extgpio: extgpiogrp {
+      fsl,pins = <
+         MX6UL_PAD_GPIO1_IO03__GPIO1_IO03   0x17059 /*   3# I2C1_SDA */
+         MX6UL_PAD_GPIO1_IO02__GPIO1_IO02   0x17059 /*   5# I2C1_SCL */
+         MX6UL_PAD_UART1_CTS_B__GPIO1_IO18   0x17059 /*   7#   GPIO   */
+         MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x17059 /* 11# UART3_TX */
+         MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x17059 /* 13# UART4_TX */
+         MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x17059 /* 15# UART4_RX */
+         MX6UL_PAD_LCD_DATA22__GPIO3_IO27   0x17059 /* 19# SPI1_MOSI*/
+         MX6UL_PAD_LCD_DATA23__GPIO3_IO28   0x17059 /* 21# SPI1_MISO*/
+         MX6UL_PAD_LCD_DATA20__GPIO3_IO25   0x17059 /* 23# SPI1_SCLK*/
+         MX6UL_PAD_UART3_CTS_B__GPIO1_IO26   0x17059 /* 27# CAN1_TX   */
+         MX6UL_PAD_UART3_RTS_B__GPIO1_IO27   0x17059 /* 29# CAN1_RX   */
+         MX6UL_PAD_UART2_CTS_B__GPIO1_IO22   0x17059 /* 31# CAN2_TX   */
+         MX6UL_PAD_UART2_RTS_B__GPIO1_IO23   0x17059 /* 33# CAN2_RX   */
+         MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01   0x17059 /* 35#   GPIO   */
+         MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08   0x17059 /* 37#   GPIO   */
+         MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x17059 /* 8# UART2_TX */
+         MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x17059 /* 10# UART2_RX */
+         MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x17059 /* 12# UART3_RX */
+         MX6UL_PAD_LCD_DATA16__GPIO3_IO21   0x17059 /* 16# UART7_TX */
+         MX6UL_PAD_LCD_DATA17__GPIO3_IO22   0x17059 /* 18# UART7_RX */
+         MX6UL_PAD_LCD_DATA18__GPIO3_IO23   0x17059 /* 22# GPIO      */
+         MX6UL_PAD_LCD_DATA21__GPIO3_IO26   0x17059 /* 24# SPI1_SS0 */
+         MX6UL_PAD_LCD_DATA19__GPIO3_IO24   0x17059 /* 26# GPIO      */
+         MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15   0x17059 /* 28# PWM8      */
+         MX6UL_PAD_JTAG_TCK__GPIO1_IO14      0x17059 /* 32# PWM7      */
+         MX6UL_PAD_JTAG_TMS__GPIO1_IO11      0x17059 /* 36# GPIO */
+         MX6UL_PAD_JTAG_MOD__GPIO1_IO10      0x17059 /* 38# GPIO */
+         MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09   0x17059 /* 40# GPIO */
+      >;
+   };

    pinctrl_csi1: csi1grp {
       fsl,pins = <
@@ -306,12 +345,13 @@
       fsl,pins = <
          MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN   0x1b0b0
          MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER   0x1b0b0
-         MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00   0x1b0b0
-         MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01   0x1b0b0
+         MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+         MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
          MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN   0x1b0b0
-         MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00   0x1b0b0
-         MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01   0x1b0b0
+         MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+         MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
          MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1   0x4001b031
+            MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x10B0 /* ENET1 RESET */
+         MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x10B0 /* ENET1 RESET */
       >;
    };
 
@@ -327,6 +333,7 @@
          MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00   0x1b0b0
          MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01   0x1b0b0

@@ -321,12 +361,13 @@
          MX6UL_PAD_GPIO1_IO06__ENET2_MDIO   0x1b0b0
          MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN   0x1b0b0
          MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER   0x1b0b0
-         MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00   0x1b0b0
-         MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01   0x1b0b0
+         MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
+         MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
          MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN   0x1b0b0
-         MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00   0x1b0b0
-         MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01   0x1b0b0
+         MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
+         MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
          MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2   0x4001b031
+            MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04  0x10B0 /* ENET2 RESET */
+         MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04   0x10B0 /* ENET2 RESET */
       >;
    };
 
@@ -423,7 +430,6 @@
          MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA   0x11088

@@ -367,41 +408,33 @@

    pinctrl_lcdif_dat: lcdifdatgrp {
       fsl,pins = <
-         MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
-         MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
-         MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
-         MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
-         MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
-         MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
-         MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
-         MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
-         MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
-         MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
-         MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
-         MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
-         MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
-         MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
-         MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
-         MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
-         MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
-         MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
-         MX6UL_PAD_LCD_DATA18__LCDIF_DATA18  0x79
-         MX6UL_PAD_LCD_DATA19__LCDIF_DATA19  0x79
-         MX6UL_PAD_LCD_DATA20__LCDIF_DATA20  0x79
-         MX6UL_PAD_LCD_DATA21__LCDIF_DATA21  0x79
-         MX6UL_PAD_LCD_DATA22__LCDIF_DATA22  0x79
-         MX6UL_PAD_LCD_DATA23__LCDIF_DATA23  0x79
+         MX6UL_PAD_LCD_DATA00__LCDIF_DATA00   0x79
+         MX6UL_PAD_LCD_DATA01__LCDIF_DATA01   0x79
+         MX6UL_PAD_LCD_DATA02__LCDIF_DATA02   0x79
+         MX6UL_PAD_LCD_DATA03__LCDIF_DATA03   0x79
+         MX6UL_PAD_LCD_DATA04__LCDIF_DATA04   0x79
+         MX6UL_PAD_LCD_DATA05__LCDIF_DATA05   0x79
+         MX6UL_PAD_LCD_DATA06__LCDIF_DATA06   0x79
+         MX6UL_PAD_LCD_DATA07__LCDIF_DATA07   0x79
+         MX6UL_PAD_LCD_DATA08__LCDIF_DATA08   0x79
+         MX6UL_PAD_LCD_DATA09__LCDIF_DATA09   0x79
+         MX6UL_PAD_LCD_DATA10__LCDIF_DATA10   0x79
+         MX6UL_PAD_LCD_DATA11__LCDIF_DATA11   0x79
+         MX6UL_PAD_LCD_DATA12__LCDIF_DATA12   0x79
+         MX6UL_PAD_LCD_DATA13__LCDIF_DATA13   0x79
+         MX6UL_PAD_LCD_DATA14__LCDIF_DATA14   0x79
+         MX6UL_PAD_LCD_DATA15__LCDIF_DATA15   0x79
       >;
    };

    pinctrl_lcdif_ctrl: lcdifctrlgrp {
       fsl,pins = <
-         MX6UL_PAD_LCD_CLK__LCDIF_CLK       0x79
-         MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
-         MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
-         MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
+         MX6UL_PAD_LCD_CLK__LCDIF_CLK      0x79
+         MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE   0x79
+         MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC   0x79
+         MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC   0x79
          /* used for lcd reset */
-         MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09  0x79
+         MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09   0x79
       >;
    };

@@ -409,8 +442,8 @@
       fsl,pins = <
          MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK   0x70a1
          MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00   0x70a1
-         MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01   0x70a1
-         MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02   0x70a1
+         MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
+         MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
          MX6UL_PAD_NAND_CLE__QSPI_A_DATA03   0x70a1
          MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B   0x70a1
       >;
@@ -420,16 +453,15 @@
       fsl,pins = <
          MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK   0x17088
          MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC   0x17088
-         MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA   0x11088
+         MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
          MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA   0x11088
          MX6UL_PAD_JTAG_TMS__SAI2_MCLK      0x17088
-         MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04   0x17059
       >;
    };
 
@@ -448,7 +454,6 @@

    pinctrl_pwm1: pwm1grp {
       fsl,pins = <
-         MX6UL_PAD_GPIO1_IO08__PWM1_OUT   0x110b0
+         MX6UL_PAD_GPIO1_IO08__PWM1_OUT    0x110b0
       >;
    };

@@ -448,7 +480,6 @@
       fsl,pins = <
          MX6UL_PAD_BOOT_MODE0__GPIO5_IO10   0x70a1
          MX6UL_PAD_BOOT_MODE1__GPIO5_IO11   0x70a1
@@ -127,23 +280,98 @@
          MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08   0x80000000
       >;
    };
@@ -492,9 +497,7 @@
          MX6UL_PAD_SD1_DATA1__USDHC1_DATA1    0x17059
          MX6UL_PAD_SD1_DATA2__USDHC1_DATA2    0x17059
          MX6UL_PAD_SD1_DATA3__USDHC1_DATA3    0x17059
@@ -486,22 +517,20 @@

    pinctrl_usdhc1: usdhc1grp {
       fsl,pins = <
-         MX6UL_PAD_SD1_CMD__USDHC1_CMD        0x17059
+         MX6UL_PAD_SD1_CMD__USDHC1_CMD      0x17059
          MX6UL_PAD_SD1_CLK__USDHC1_CLK      0x10071
-         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0    0x17059
-         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1    0x17059
-         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2    0x17059
-         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3    0x17059
-         MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059 /* SD1 CD */
-         MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT    0x17059 /* SD1 VSELECT */
-         MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
+         MX6UL_PAD_UART1_RTS_B__GPIO1_IO19   0x17059 /* SD1 CD */
+         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0   0x17059
+         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1   0x17059
+         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2   0x17059
+         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3   0x17059
+         MX6UL_PAD_UART1_RTS_B__GPIO1_IO19   0x17059 /* SD1 CD */
       >;
    };
 

    pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
       fsl,pins = <
-         MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
-         MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
+         MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
+         MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
          MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
          MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
          MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
@@ -512,8 +541,8 @@

    pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
       fsl,pins = <
-         MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
-         MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
+         MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
+         MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
          MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
          MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
          MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
@@ -523,8 +552,8 @@

    pinctrl_usdhc2: usdhc2grp {
       fsl,pins = <
-         MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x17059
-         MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
+         MX6UL_PAD_NAND_RE_B__USDHC2_CLK      0x17059
+         MX6UL_PAD_NAND_WE_B__USDHC2_CMD      0x17059
          MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
          MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
          MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
@@ -534,8 +563,8 @@

    pinctrl_usdhc2_8bit: usdhc2grp_8bit {
       fsl,pins = <
-         MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x10069
-         MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
+         MX6UL_PAD_NAND_RE_B__USDHC2_CLK      0x10069
+         MX6UL_PAD_NAND_WE_B__USDHC2_CMD      0x17059
          MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
          MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
          MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
@@ -549,8 +578,8 @@

    pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz {
       fsl,pins = <
-         MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x100b9
-         MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x170b9
+         MX6UL_PAD_NAND_RE_B__USDHC2_CLK      0x100b9
+         MX6UL_PAD_NAND_WE_B__USDHC2_CMD      0x170b9
          MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
          MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
          MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
@@ -564,8 +593,8 @@

    pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz {
       fsl,pins = <
-         MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x100f9
-         MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x170f9
+         MX6UL_PAD_NAND_RE_B__USDHC2_CLK      0x100f9
+         MX6UL_PAD_NAND_WE_B__USDHC2_CMD      0x170f9
          MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
          MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
          MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
diff -Nuar -x lingyun.bmp uboot-imx/arch/arm/dts/Makefile uboot-imx-lf-5.10.52-2.1.0/arch/arm/dts/Makefile
--- uboot-imx/arch/arm/dts/Makefile   2021-09-06 16:48:23.000000000 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/arch/arm/dts/Makefile   2022-06-05 20:35:49.127986610 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/arch/arm/dts/Makefile   2022-06-30 20:28:15.839187950 +0800
@@ -779,6 +779,7 @@
    imx6ul-pico-pi.dtb
 

 dtb-$(CONFIG_MX6ULL) += \
+   igkboard.dtb \
    imx6ull-14x14-ddr3-val.dtb \
@@ -151,11 +379,11 @@
    imx6ull-14x14-ddr3-val-emmc.dtb \
diff -Nuar -x lingyun.bmp uboot-imx/arch/arm/mach-imx/mx6/Kconfig uboot-imx-lf-5.10.52-2.1.0/arch/arm/mach-imx/mx6/Kconfig
--- uboot-imx/arch/arm/mach-imx/mx6/Kconfig   2021-09-06 16:48:23.000000000 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/arch/arm/mach-imx/mx6/Kconfig   2022-06-05 20:35:49.131986487 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/arch/arm/mach-imx/mx6/Kconfig   2022-06-30 20:28:15.839187950 +0800
@@ -158,6 +158,16 @@
    prompt "MX6 board select"
    optional
 

+config TARGET_LINGYUN_IGKBOARD
+   bool "LingYun IoT Gateway Kits Board(IGKBoard)"
+   depends on MX6ULL
@@ -173,12 +401,12 @@
 source "board/wandboard/Kconfig"
 source "board/warp/Kconfig"
 source "board/BuR/brppt2/Kconfig"
+source "board/lingyun/igkboard/Kconfig"  
 
+source "board/lingyun/igkboard/Kconfig"

 endif
diff -Nuar -x lingyun.bmp uboot-imx/board/lingyun/igkboard/igkboard.c uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/igkboard.c
--- uboot-imx/board/lingyun/igkboard/igkboard.c   1970-01-01 08:00:00.000000000 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/igkboard.c   2022-06-05 20:35:49.131986487 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/igkboard.c   2022-06-30 20:28:15.839187950 +0800
@@ -0,0 +1,369 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
@@ -551,7 +779,7 @@
+}
diff -Nuar -x lingyun.bmp uboot-imx/board/lingyun/igkboard/imximage.cfg uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/imximage.cfg
--- uboot-imx/board/lingyun/igkboard/imximage.cfg   1970-01-01 08:00:00.000000000 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/imximage.cfg   2022-06-05 20:35:49.131986487 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/imximage.cfg   2022-06-30 20:28:15.839187950 +0800
@@ -0,0 +1,121 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
@@ -676,7 +904,7 @@
+#endif
diff -Nuar -x lingyun.bmp uboot-imx/board/lingyun/igkboard/imximage_lpddr2.cfg uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/imximage_lpddr2.cfg
--- uboot-imx/board/lingyun/igkboard/imximage_lpddr2.cfg   1970-01-01 08:00:00.000000000 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/imximage_lpddr2.cfg   2022-06-05 20:35:49.131986487 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/imximage_lpddr2.cfg   2022-06-30 20:28:15.839187950 +0800
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
@@ -806,7 +1034,7 @@
+#endif
diff -Nuar -x lingyun.bmp uboot-imx/board/lingyun/igkboard/Kconfig uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/Kconfig
--- uboot-imx/board/lingyun/igkboard/Kconfig   1970-01-01 08:00:00.000000000 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/Kconfig   2022-06-05 20:35:49.131986487 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/Kconfig   2022-06-30 20:28:15.839187950 +0800
@@ -0,0 +1,14 @@
+if TARGET_LINGYUN_IGKBOARD
+
@@ -824,7 +1052,7 @@
+endif
diff -Nuar -x lingyun.bmp uboot-imx/board/lingyun/igkboard/MAINTAINERS uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/MAINTAINERS
--- uboot-imx/board/lingyun/igkboard/MAINTAINERS   1970-01-01 08:00:00.000000000 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/MAINTAINERS   2022-06-05 20:35:49.131986487 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/MAINTAINERS   2022-06-30 20:28:15.839187950 +0800
@@ -0,0 +1,6 @@
+LingYun IoT Gateway Board(IGKBoard)
+M:   Guo Wenxue <guowenxue@gmail.com>
@@ -834,7 +1062,7 @@
+F:   configs/igkboard_defconfig
diff -Nuar -x lingyun.bmp uboot-imx/board/lingyun/igkboard/Makefile uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/Makefile
--- uboot-imx/board/lingyun/igkboard/Makefile   1970-01-01 08:00:00.000000000 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/Makefile   2022-06-05 20:35:49.131986487 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/Makefile   2022-06-30 20:28:15.839187950 +0800
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2016 Freescale Semiconductor, Inc.
@@ -843,7 +1071,7 @@
+obj-y  += ../../freescale/common/mmc.o
diff -Nuar -x lingyun.bmp uboot-imx/board/lingyun/igkboard/plugin.S uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/plugin.S
--- uboot-imx/board/lingyun/igkboard/plugin.S   1970-01-01 08:00:00.000000000 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/plugin.S   2022-06-05 20:35:49.131986487 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/plugin.S   2022-06-30 20:28:15.839187950 +0800
@@ -0,0 +1,263 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
@@ -1110,7 +1338,7 @@
+#include <asm/arch/mx6_plugin.S>
diff -Nuar -x lingyun.bmp uboot-imx/configs/igkboard_defconfig uboot-imx-lf-5.10.52-2.1.0/configs/igkboard_defconfig
--- uboot-imx/configs/igkboard_defconfig   1970-01-01 08:00:00.000000000 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/configs/igkboard_defconfig   2022-06-12 00:41:52.657550517 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/configs/igkboard_defconfig   2022-06-30 20:28:15.839187950 +0800
@@ -0,0 +1,97 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
@@ -1211,7 +1439,7 @@
+CONFIG_OF_LIBFDT_OVERLAY=y
diff -Nuar -x lingyun.bmp uboot-imx/drivers/fastboot/fb_fsl/fb_fsl_partitions.c uboot-imx-lf-5.10.52-2.1.0/drivers/fastboot/fb_fsl/fb_fsl_partitions.c
--- uboot-imx/drivers/fastboot/fb_fsl/fb_fsl_partitions.c   2021-09-06 16:48:23.000000000 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/drivers/fastboot/fb_fsl/fb_fsl_partitions.c   2022-06-05 20:35:49.131986487 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/drivers/fastboot/fb_fsl/fb_fsl_partitions.c   2022-06-30 20:28:15.839187950 +0800
@@ -185,6 +185,12 @@
          boot_partition = FASTBOOT_MMC_BOOT_PARTITION_ID;
          user_partition = FASTBOOT_MMC_USER_PARTITION_ID;
@@ -1227,20 +1455,20 @@
          fastboot_devinfo.type);
diff -Nuar -x lingyun.bmp uboot-imx/drivers/net/phy/phy.c uboot-imx-lf-5.10.52-2.1.0/drivers/net/phy/phy.c
--- uboot-imx/drivers/net/phy/phy.c   2021-09-06 16:48:23.000000000 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/drivers/net/phy/phy.c   2022-06-05 20:35:49.131986487 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/drivers/net/phy/phy.c   2022-06-30 20:28:15.839187950 +0800
@@ -182,6 +182,9 @@
 {
    int result;
 

+    /*  add Soft Reset the PHY by guowenxue, 2021.11.14 */
+    phy_reset(phydev);
+
    if (phydev->autoneg != AUTONEG_ENABLE)
       return genphy_setup_forced(phydev);
 

diff -Nuar -x lingyun.bmp uboot-imx/include/configs/igkboard.h uboot-imx-lf-5.10.52-2.1.0/include/configs/igkboard.h
--- uboot-imx/include/configs/igkboard.h   1970-01-01 08:00:00.000000000 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/include/configs/igkboard.h   2022-06-05 20:35:49.131986487 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/include/configs/igkboard.h   2022-06-30 20:28:15.839187950 +0800
@@ -0,0 +1,200 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
@@ -1444,7 +1672,7 @@
+#endif
diff -Nuar -x lingyun.bmp uboot-imx/include/configs/igkboard_overlay.h uboot-imx-lf-5.10.52-2.1.0/include/configs/igkboard_overlay.h
--- uboot-imx/include/configs/igkboard_overlay.h   1970-01-01 08:00:00.000000000 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/include/configs/igkboard_overlay.h   2022-06-12 00:29:53.640427137 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/include/configs/igkboard_overlay.h   2022-06-30 20:28:15.843187892 +0800
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
@@ -1536,14 +1764,14 @@
+#endif
diff -Nuar -x lingyun.bmp uboot-imx/Makefile uboot-imx-lf-5.10.52-2.1.0/Makefile
--- uboot-imx/Makefile   2021-09-06 16:48:23.000000000 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/Makefile   2022-06-12 00:28:21.925275284 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/Makefile   2022-06-30 20:28:15.855187718 +0800
@@ -263,6 +263,9 @@
 CROSS_COMPILE ?=
 endif
 

+ARCH=arm
+CROSS_COMPILE?=/opt/buildroot/cortexA7/bin/arm-linux-
+
 KCONFIG_CONFIG   ?= .config
 export KCONFIG_CONFIG