.cproject
@@ -58,6 +58,9 @@ </tool> <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.1449997475" name="MCU/MPU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker"> <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script.1098456646" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script" value="${workspace_loc:/${ProjName}/STM32L431RCTX_FLASH.ld}" valueType="string"/> <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.otherflags.290509561" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.otherflags" valueType="stringList"> <listOptionValue builtIn="false" value="-u _printf_float"/> </option> <inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input.1988127802" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input"> <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/> <additionalInput kind="additionalinput" paths="$(LIBS)"/> Core/Inc/stm32l4xx_hal_conf.h
@@ -79,7 +79,7 @@ /*#define HAL_SWPMI_MODULE_ENABLED */ /*#define HAL_TIM_MODULE_ENABLED */ /*#define HAL_TSC_MODULE_ENABLED */ /*#define HAL_UART_MODULE_ENABLED */ #define HAL_UART_MODULE_ENABLED /*#define HAL_USART_MODULE_ENABLED */ /*#define HAL_WWDG_MODULE_ENABLED */ /*#define HAL_EXTI_MODULE_ENABLED */ Core/Inc/usart.h
New file @@ -0,0 +1,52 @@ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file usart.h * @brief This file contains all the function prototypes for * the usart.c file ****************************************************************************** * @attention * * Copyright (c) 2025 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __USART_H__ #define __USART_H__ #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "main.h" /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ extern UART_HandleTypeDef huart1; /* USER CODE BEGIN Private defines */ /* USER CODE END Private defines */ void MX_USART1_UART_Init(void); /* USER CODE BEGIN Prototypes */ /* USER CODE END Prototypes */ #ifdef __cplusplus } #endif #endif /* __USART_H__ */
@@ -153,3 +153,30 @@ } } /* *+----------------------+ *| printf API | *+----------------------+ */ #include "usart.h" /* 全局变量huart1定义在 usart.c中，并在sart.h头文件中声明 */ /* gcc 编译器中的 printf 函数将会调用 __io_putchar() 函数，实现最终的字符打印 * keil编译器中的 printf 函数将会调用 fputc() 函数，实现最终的字符打印 * 这里我们定义一个宏 PUTCHAR_PROTOTYPE 来兼容这两个编译器所需要的函数原型； */ #ifdef __GNUC__ #define PUTCHAR_PROTOTYPE int __io_putchar(int ch) #else #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) #endif /* * STM32CubeIDE使用的是 gcc 编译器，它会内建 __GNUC__ 宏定义，所以下面PUTCHAR_PROTOTYPE将会扩展为: * int __io_putchar(int ch) */ PUTCHAR_PROTOTYPE { /* 调用STM32 HAL库的串口发送函数，将printf要打印的这个字符通过串口发送出去 */ HAL_UART_Transmit(&huart1, (uint8_t *)&ch, 1, 0xFFFF); return ch; } Core/Src/board/miscdev.h
@@ -13,6 +13,8 @@ #ifndef __MISCDEV_H #define __MISCDEV_H #include <stdio.h> /* 定义ON/OFF两个宏，这样在代码中使用比 1/0 更具有可读性 */ #define OFF 0 #define ON 1 Core/Src/gpio.c
@@ -48,6 +48,7 @@ __HAL_RCC_GPIOH_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); /*Configure GPIO pin Output Level */ Core/Src/main.c
@@ -18,6 +18,7 @@ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "main.h" #include "usart.h" #include "gpio.h" /* Private includes ----------------------------------------------------------*/ @@ -86,7 +87,15 @@ /* Initialize all configured peripherals */ MX_GPIO_Init(); MX_USART1_UART_Init(); /* USER CODE BEGIN 2 */ printf("Welcome to ISKBoard!\r\n"); { float temp=30.0; printf("Temperature: %.3f\r\n", temp); } init_relay(); init_led();
New file @@ -0,0 +1,127 @@ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file usart.c * @brief This file provides code for the configuration * of the USART instances. ****************************************************************************** * @attention * * Copyright (c) 2025 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "usart.h" /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ UART_HandleTypeDef huart1; /* USART1 init function */ void MX_USART1_UART_Init(void) { /* USER CODE BEGIN USART1_Init 0 */ /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; huart1.Init.BaudRate = 115200; huart1.Init.WordLength = UART_WORDLENGTH_8B; huart1.Init.StopBits = UART_STOPBITS_1; huart1.Init.Parity = UART_PARITY_NONE; huart1.Init.Mode = UART_MODE_TX_RX; huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; huart1.Init.OverSampling = UART_OVERSAMPLING_16; huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; if (HAL_UART_Init(&huart1) != HAL_OK) { Error_Handler(); } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { GPIO_InitTypeDef GPIO_InitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; if(uartHandle->Instance==USART1) { /* USER CODE BEGIN USART1_MspInit 0 */ /* USER CODE END USART1_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1; PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { Error_Handler(); } /* USART1 clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); /**USART1 GPIO Configuration PA9 ------> USART1_TX PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF7_USART1; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); /* USER CODE BEGIN USART1_MspInit 1 */ /* USER CODE END USART1_MspInit 1 */ } } void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) { if(uartHandle->Instance==USART1) { /* USER CODE BEGIN USART1_MspDeInit 0 */ /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); /**USART1 GPIO Configuration PA9 ------> USART1_TX PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); /* USER CODE BEGIN USART1_MspDeInit 1 */ /* USER CODE END USART1_MspDeInit 1 */ } } /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h
New file @@ -0,0 +1,1810 @@ /** ****************************************************************************** * @file stm32l4xx_hal_uart.h * @author MCD Application Team * @brief Header file of UART HAL module. ****************************************************************************** * @attention * * Copyright (c) 2017 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32L4xx_HAL_UART_H #define STM32L4xx_HAL_UART_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" /** @addtogroup STM32L4xx_HAL_Driver * @{ */ /** @addtogroup UART * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup UART_Exported_Types UART Exported Types * @{ */ /** * @brief UART Init Structure definition */ typedef struct { uint32_t BaudRate; /*!< This member configures the UART communication baud rate. The baud rate register is computed using the following formula: LPUART: ======= Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) where lpuart_ker_ck_pres is the UART input clock (divided by a prescaler if applicable) UART: ===== - If oversampling is 16 or in LIN mode, Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) - If oversampling is 8, Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[15:4] Baud Rate Register[3] = 0 Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[3:0]) >> 1 where uart_ker_ck_pres is the UART input clock (divided by a prescaler if applicable) */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of @ref UARTEx_Word_Length. */ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. This parameter can be a value of @ref UART_Stop_Bits. */ uint32_t Parity; /*!< Specifies the parity mode. This parameter can be a value of @ref UART_Parity @note When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits). */ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of @ref UART_Mode. */ uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of @ref UART_Hardware_Flow_Control. */ uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8). This parameter can be a value of @ref UART_Over_Sampling. */ uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. Selecting the single sample method increases the receiver tolerance to clock deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ #if defined(USART_PRESC_PRESCALER) uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source. This parameter can be a value of @ref UART_ClockPrescaler. */ #endif /* USART_PRESC_PRESCALER */ } UART_InitTypeDef; /** * @brief UART Advanced Features initialization structure definition */ typedef struct { uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several Advanced Features may be initialized at the same time . This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */ uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. This parameter can be a value of @ref UART_Tx_Inv. */ uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted. This parameter can be a value of @ref UART_Rx_Inv. */ uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic vs negative/inverted logic). This parameter can be a value of @ref UART_Data_Inv. */ uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped. This parameter can be a value of @ref UART_Rx_Tx_Swap. */ uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. This parameter can be a value of @ref UART_Overrun_Disable. */ uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */ uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled. This parameter can be a value of @ref UART_AutoBaudRate_Enable. */ uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate detection is carried out. This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */ uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. This parameter can be a value of @ref UART_MSB_First. */ } UART_AdvFeatureInitTypeDef; /** * @brief HAL UART State definition * @note HAL UART State value is a combination of 2 different substates: * gState and RxState (see @ref UART_State_Definition). * - gState contains UART state information related to global Handle management * and also information related to Tx operations. * gState value coding follow below described bitmap : * b7-b6 Error information * 00 : No Error * 01 : (Not Used) * 10 : Timeout * 11 : Error * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) * 1 : Init done (Peripheral initialized. HAL UART Init function already called) * b4-b3 (not used) * xx : Should be set to 00 * b2 Intrinsic process state * 0 : Ready * 1 : Busy (Peripheral busy with some configuration or internal operations) * b1 (not used) * x : Should be set to 0 * b0 Tx state * 0 : Ready (no Tx operation ongoing) * 1 : Busy (Tx operation ongoing) * - RxState contains information related to Rx operations. * RxState value coding follow below described bitmap : * b7-b6 (not used) * xx : Should be set to 00 * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) * 1 : Init done (Peripheral initialized) * b4-b2 (not used) * xxx : Should be set to 000 * b1 Rx state * 0 : Ready (no Rx operation ongoing) * 1 : Busy (Rx operation ongoing) * b0 (not used) * x : Should be set to 0. */ typedef uint32_t HAL_UART_StateTypeDef; /** * @brief UART clock sources definition */ typedef enum { UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ UART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ UART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ UART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ UART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ } UART_ClockSourceTypeDef; /** * @brief HAL UART Reception type definition * @note HAL UART Reception type value aims to identify which type of Reception is ongoing. * This parameter can be a value of @ref UART_Reception_Type_Values : * HAL_UART_RECEPTION_STANDARD = 0x00U, * HAL_UART_RECEPTION_TOIDLE = 0x01U, * HAL_UART_RECEPTION_TORTO = 0x02U, * HAL_UART_RECEPTION_TOCHARMATCH = 0x03U, */ typedef uint32_t HAL_UART_RxTypeTypeDef; /** * @brief HAL UART Rx Event type definition * @note HAL UART Rx Event type value aims to identify which type of Event has occurred * leading to call of the RxEvent callback. * This parameter can be a value of @ref UART_RxEvent_Type_Values : * HAL_UART_RXEVENT_TC = 0x00U, * HAL_UART_RXEVENT_HT = 0x01U, * HAL_UART_RXEVENT_IDLE = 0x02U, */ typedef uint32_t HAL_UART_RxEventTypeTypeDef; /** * @brief UART handle Structure definition */ typedef struct __UART_HandleTypeDef { USART_TypeDef *Instance; /*!< UART registers base address */ UART_InitTypeDef Init; /*!< UART communication parameters */ UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */ const uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ uint16_t TxXferSize; /*!< UART Tx Transfer size */ __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ uint16_t RxXferSize; /*!< UART Rx Transfer size */ __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ uint16_t Mask; /*!< UART Rx RDR register mask */ #if defined(USART_CR1_FIFOEN) uint32_t FifoMode; /*!< Specifies if the FIFO mode is being used. This parameter can be a value of @ref UARTEx_FIFO_mode. */ uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ #endif /*USART_CR1_FIFOEN */ __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ __IO HAL_UART_RxEventTypeTypeDef RxEventType; /*!< Type of Rx Event */ void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management and also related to Tx operations. This parameter can be a value of @ref HAL_UART_StateTypeDef */ __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. This parameter can be a value of @ref HAL_UART_StateTypeDef */ __IO uint32_t ErrorCode; /*!< UART Error code */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */ void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */ void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */ void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */ void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */ void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */ void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */ void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */ void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */ #if defined(USART_CR1_FIFOEN) void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Fifo Full Callback */ void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Fifo Empty Callback */ #endif /* USART_CR1_FIFOEN */ void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */ void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } UART_HandleTypeDef; #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /** * @brief HAL UART Callback ID enumeration definition */ typedef enum { HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */ HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */ HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */ HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */ HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */ HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ #if defined(USART_CR1_FIFOEN) HAL_UART_RX_FIFO_FULL_CB_ID = 0x09U, /*!< UART Rx Fifo Full Callback ID */ HAL_UART_TX_FIFO_EMPTY_CB_ID = 0x0AU, /*!< UART Tx Fifo Empty Callback ID */ #endif /* USART_CR1_FIFOEN */ HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */ HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */ } HAL_UART_CallbackIDTypeDef; /** * @brief HAL UART Callback pointer definition */ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ typedef void (*pUART_RxEventCallbackTypeDef) (struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */ #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup UART_Exported_Constants UART Exported Constants * @{ */ /** @defgroup UART_State_Definition UART State Code Definition * @{ */ #define HAL_UART_STATE_RESET 0x00000000U /*!< Peripheral is not initialized Value is allowed for gState and RxState */ #define HAL_UART_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use Value is allowed for gState and RxState */ #define HAL_UART_STATE_BUSY 0x00000024U /*!< an internal process is ongoing Value is allowed for gState only */ #define HAL_UART_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing Value is allowed for gState only */ #define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing Value is allowed for RxState only */ #define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState.Value is result of combination (Or) between gState and RxState values */ #define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state Value is allowed for gState only */ #define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error Value is allowed for gState only */ /** * @} */ /** @defgroup UART_Error_Definition UART Error Definition * @{ */ #define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */ #define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */ #define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */ #define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */ #define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */ #define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ #define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) #define HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ /** * @} */ /** @defgroup UART_Stop_Bits UART Number of Stop Bits * @{ */ #define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */ #define UART_STOPBITS_1 0x00000000U /*!< UART frame with 1 stop bit */ #define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */ #define UART_STOPBITS_2 USART_CR2_STOP_1 /*!< UART frame with 2 stop bits */ /** * @} */ /** @defgroup UART_Parity UART Parity * @{ */ #define UART_PARITY_NONE 0x00000000U /*!< No parity */ #define UART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */ #define UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */ /** * @} */ /** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control * @{ */ #define UART_HWCONTROL_NONE 0x00000000U /*!< No hardware control */ #define UART_HWCONTROL_RTS USART_CR3_RTSE /*!< Request To Send */ #define UART_HWCONTROL_CTS USART_CR3_CTSE /*!< Clear To Send */ #define UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< Request and Clear To Send */ /** * @} */ /** @defgroup UART_Mode UART Transfer Mode * @{ */ #define UART_MODE_RX USART_CR1_RE /*!< RX mode */ #define UART_MODE_TX USART_CR1_TE /*!< TX mode */ #define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ /** * @} */ /** @defgroup UART_State UART State * @{ */ #define UART_STATE_DISABLE 0x00000000U /*!< UART disabled */ #define UART_STATE_ENABLE USART_CR1_UE /*!< UART enabled */ /** * @} */ /** @defgroup UART_Over_Sampling UART Over Sampling * @{ */ #define UART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ #define UART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ /** * @} */ /** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method * @{ */ #define UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disable */ #define UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enable */ /** * @} */ #if defined(USART_PRESC_PRESCALER) /** @defgroup UART_ClockPrescaler UART Clock Prescaler * @{ */ #define UART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ #define UART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ #define UART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ #define UART_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */ #define UART_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */ #define UART_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */ #define UART_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */ #define UART_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */ #define UART_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */ #define UART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ #define UART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ #define UART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ /** * @} */ #endif /* USART_PRESC_PRESCALER */ /** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode * @{ */ #define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection on start bit */ #define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection on falling edge */ #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection on 0x7F frame detection */ #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection on 0x55 frame detection */ /** * @} */ /** @defgroup UART_Receiver_Timeout UART Receiver Timeout * @{ */ #define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART Receiver Timeout disable */ #define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART Receiver Timeout enable */ /** * @} */ /** @defgroup UART_LIN UART Local Interconnection Network mode * @{ */ #define UART_LIN_DISABLE 0x00000000U /*!< Local Interconnect Network disable */ #define UART_LIN_ENABLE USART_CR2_LINEN /*!< Local Interconnect Network enable */ /** * @} */ /** @defgroup UART_LIN_Break_Detection UART LIN Break Detection * @{ */ #define UART_LINBREAKDETECTLENGTH_10B 0x00000000U /*!< LIN 10-bit break detection length */ #define UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL /*!< LIN 11-bit break detection length */ /** * @} */ /** @defgroup UART_DMA_Tx UART DMA Tx * @{ */ #define UART_DMA_TX_DISABLE 0x00000000U /*!< UART DMA TX disabled */ #define UART_DMA_TX_ENABLE USART_CR3_DMAT /*!< UART DMA TX enabled */ /** * @} */ /** @defgroup UART_DMA_Rx UART DMA Rx * @{ */ #define UART_DMA_RX_DISABLE 0x00000000U /*!< UART DMA RX disabled */ #define UART_DMA_RX_ENABLE USART_CR3_DMAR /*!< UART DMA RX enabled */ /** * @} */ /** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection * @{ */ #define UART_HALF_DUPLEX_DISABLE 0x00000000U /*!< UART half-duplex disabled */ #define UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL /*!< UART half-duplex enabled */ /** * @} */ /** @defgroup UART_WakeUp_Methods UART WakeUp Methods * @{ */ #define UART_WAKEUPMETHOD_IDLELINE 0x00000000U /*!< UART wake-up on idle line */ #define UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE /*!< UART wake-up on address mark */ /** * @} */ /** @defgroup UART_Request_Parameters UART Request Parameters * @{ */ #define UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */ #define UART_SENDBREAK_REQUEST USART_RQR_SBKRQ /*!< Send Break Request */ #define UART_MUTE_MODE_REQUEST USART_RQR_MMRQ /*!< Mute Mode Request */ #define UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */ #define UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */ /** * @} */ /** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type * @{ */ #define UART_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */ #define UART_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */ #define UART_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */ #define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */ #define UART_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */ #define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */ #define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */ #define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U /*!< Auto Baud rate detection initialization */ #define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */ /** * @} */ /** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion * @{ */ #define UART_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */ #define UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */ /** * @} */ /** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion * @{ */ #define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */ #define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */ /** * @} */ /** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion * @{ */ #define UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */ #define UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */ /** * @} */ /** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap * @{ */ #define UART_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */ #define UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */ /** * @} */ /** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable * @{ */ #define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */ #define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */ /** * @} */ /** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable * @{ */ #define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U /*!< RX Auto Baud rate detection enable */ #define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN /*!< RX Auto Baud rate detection disable */ /** * @} */ /** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error * @{ */ #define UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */ #define UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */ /** * @} */ /** @defgroup UART_MSB_First UART Advanced Feature MSB First * @{ */ #define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received first disable */ #define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received first enable */ /** * @} */ /** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable * @{ */ #define UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U /*!< UART stop mode disable */ #define UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM /*!< UART stop mode enable */ /** * @} */ /** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable * @{ */ #define UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U /*!< UART mute mode disable */ #define UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME /*!< UART mute mode enable */ /** * @} */ /** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register * @{ */ #define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */ /** * @} */ /** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection * @{ */ #define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ #define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */ #define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register not empty or RXFIFO is not empty */ /** * @} */ /** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity * @{ */ #define UART_DE_POLARITY_HIGH 0x00000000U /*!< Driver enable signal is active high */ #define UART_DE_POLARITY_LOW USART_CR3_DEP /*!< Driver enable signal is active low */ /** * @} */ /** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register * @{ */ #define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB position in CR1 register */ /** * @} */ /** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register * @{ */ #define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB position in CR1 register */ /** * @} */ /** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask * @{ */ #define UART_IT_MASK 0x001FU /*!< UART interruptions flags mask */ /** * @} */ /** @defgroup UART_TimeOut_Value UART polling-based communications time-out value * @{ */ #define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU /*!< UART polling-based communications time-out value */ /** * @} */ /** @defgroup UART_Flags UART Status Flags * Elements values convention: 0xXXXX * - 0xXXXX : Flag mask in the ISR register * @{ */ #if defined(USART_CR1_FIFOEN) #define UART_FLAG_TXFT USART_ISR_TXFT /*!< UART TXFIFO threshold flag */ #define UART_FLAG_RXFT USART_ISR_RXFT /*!< UART RXFIFO threshold flag */ #define UART_FLAG_RXFF USART_ISR_RXFF /*!< UART RXFIFO Full flag */ #define UART_FLAG_TXFE USART_ISR_TXFE /*!< UART TXFIFO Empty flag */ #endif /* USART_CR1_FIFOEN */ #define UART_FLAG_REACK USART_ISR_REACK /*!< UART receive enable acknowledge flag */ #define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */ #define UART_FLAG_WUF USART_ISR_WUF /*!< UART wake-up from stop mode flag */ #define UART_FLAG_RWU USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */ #define UART_FLAG_SBKF USART_ISR_SBKF /*!< UART send break flag */ #define UART_FLAG_CMF USART_ISR_CMF /*!< UART character match flag */ #define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */ #define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */ #define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */ #define UART_FLAG_RTOF USART_ISR_RTOF /*!< UART receiver timeout flag */ #define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */ #define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */ #define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */ #if defined(USART_CR1_FIFOEN) #define UART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< UART transmit data register empty */ #define UART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< UART TXFIFO not full */ #else #define UART_FLAG_TXE USART_ISR_TXE /*!< UART transmit data register empty */ #endif /* USART_CR1_FIFOEN */ #define UART_FLAG_TC USART_ISR_TC /*!< UART transmission complete */ #if defined(USART_CR1_FIFOEN) #define UART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< UART read data register not empty */ #define UART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< UART RXFIFO not empty */ #else #define UART_FLAG_RXNE USART_ISR_RXNE /*!< UART read data register not empty */ #endif /* USART_CR1_FIFOEN */ #define UART_FLAG_IDLE USART_ISR_IDLE /*!< UART idle flag */ #define UART_FLAG_ORE USART_ISR_ORE /*!< UART overrun error */ #define UART_FLAG_NE USART_ISR_NE /*!< UART noise error */ #define UART_FLAG_FE USART_ISR_FE /*!< UART frame error */ #define UART_FLAG_PE USART_ISR_PE /*!< UART parity error */ /** * @} */ /** @defgroup UART_Interrupt_definition UART Interrupts Definition * Elements values convention: 000ZZZZZ0XXYYYYYb * - YYYYY : Interrupt source position in the XX register (5bits) * - XX : Interrupt source register (2bits) * - 01: CR1 register * - 10: CR2 register * - 11: CR3 register * - ZZZZZ : Flag position in the ISR register(5bits) * Elements values convention: 000000000XXYYYYYb * - YYYYY : Interrupt source position in the XX register (5bits) * - XX : Interrupt source register (2bits) * - 01: CR1 register * - 10: CR2 register * - 11: CR3 register * Elements values convention: 0000ZZZZ00000000b * - ZZZZ : Flag position in the ISR register(4bits) * @{ */ #define UART_IT_PE 0x0028U /*!< UART parity error interruption */ #define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ #if defined(USART_CR1_FIFOEN) #define UART_IT_TXFNF 0x0727U /*!< UART TX FIFO not full interruption */ #endif /* USART_CR1_FIFOEN */ #define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ #define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ #if defined(USART_CR1_FIFOEN) #define UART_IT_RXFNE 0x0525U /*!< UART RXFIFO not empty interruption */ #endif /* USART_CR1_FIFOEN */ #define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ #define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ #define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ #define UART_IT_CM 0x112EU /*!< UART character match interruption */ #define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */ #if defined(USART_CR1_FIFOEN) #define UART_IT_RXFF 0x183FU /*!< UART RXFIFO full interruption */ #define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */ #define UART_IT_RXFT 0x1A7CU /*!< UART RXFIFO threshold reached interruption */ #define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */ #endif /* USART_CR1_FIFOEN */ #define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */ #define UART_IT_ERR 0x0060U /*!< UART error interruption */ #define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ #define UART_IT_NE 0x0200U /*!< UART noise error interruption */ #define UART_IT_FE 0x0100U /*!< UART frame error interruption */ /** * @} */ /** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags * @{ */ #define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ #define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ #define UART_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */ #define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */ #define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ #if defined(USART_CR1_FIFOEN) #define UART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO empty clear flag */ #endif /* USART_CR1_FIFOEN */ #define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ #define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */ #define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ #define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ #define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */ #define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< UART receiver timeout clear flag */ /** * @} */ /** @defgroup UART_Reception_Type_Values UART Reception type values * @{ */ #define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ #define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */ #define HAL_UART_RECEPTION_TORTO (0x00000002U) /*!< Reception till completion or RTO event */ #define HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U) /*!< Reception till completion or CM event */ /** * @} */ /** @defgroup UART_RxEvent_Type_Values UART RxEvent type values * @{ */ #define HAL_UART_RXEVENT_TC (0x00000000U) /*!< RxEvent linked to Transfer Complete event */ #define HAL_UART_RXEVENT_HT (0x00000001U) /*!< RxEvent linked to Half Transfer event */ #define HAL_UART_RXEVENT_IDLE (0x00000002U) /*!< RxEvent linked to IDLE event */ /** * @} */ /** * @} */ /* Exported macros -----------------------------------------------------------*/ /** @defgroup UART_Exported_Macros UART Exported Macros * @{ */ /** @brief Reset UART handle states. * @param __HANDLE__ UART handle. * @retval None */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ (__HANDLE__)->MspInitCallback = NULL; \ (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0U) #else #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ } while(0U) #endif /*USE_HAL_UART_REGISTER_CALLBACKS */ /** @brief Flush the UART Data registers. * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ do{ \ SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ } while(0U) /** @brief Clear the specified UART pending flag. * @param __HANDLE__ specifies the UART Handle. * @param __FLAG__ specifies the flag to check. * This parameter can be any combination of the following values: * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag * @arg @ref UART_CLEAR_TXFECF TXFIFO empty clear Flag * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag * @arg @ref UART_CLEAR_RTOF Receiver Timeout clear flag * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag * @arg @ref UART_CLEAR_CMF Character Match Clear Flag * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag * @retval None */ #define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) /** @brief Clear the UART PE pending flag. * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF) /** @brief Clear the UART FE pending flag. * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF) /** @brief Clear the UART NE pending flag. * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF) /** @brief Clear the UART ORE pending flag. * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF) /** @brief Clear the UART IDLE pending flag. * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF) #if defined(USART_CR1_FIFOEN) /** @brief Clear the UART TX FIFO empty clear flag. * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_CLEAR_TXFECF(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF) #endif /* USART_CR1_FIFOEN */ /** @brief Check whether the specified UART flag is set or not. * @param __HANDLE__ specifies the UART Handle. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg @ref UART_FLAG_TXFT TXFIFO threshold flag * @arg @ref UART_FLAG_RXFT RXFIFO threshold flag * @arg @ref UART_FLAG_RXFF RXFIFO Full flag * @arg @ref UART_FLAG_TXFE TXFIFO Empty flag * @arg @ref UART_FLAG_REACK Receive enable acknowledge flag * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag * @arg @ref UART_FLAG_WUF Wake up from stop mode flag * @arg @ref UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode) * @arg @ref UART_FLAG_SBKF Send Break flag * @arg @ref UART_FLAG_CMF Character match flag * @arg @ref UART_FLAG_BUSY Busy flag * @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag * @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag * @arg @ref UART_FLAG_CTS CTS Change flag * @arg @ref UART_FLAG_LBDF LIN Break detection flag * @arg @ref UART_FLAG_TXE Transmit data register empty flag * @arg @ref UART_FLAG_TXFNF UART TXFIFO not full flag * @arg @ref UART_FLAG_TC Transmission Complete flag * @arg @ref UART_FLAG_RXNE Receive data register not empty flag * @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag * @arg @ref UART_FLAG_RTOF Receiver Timeout flag * @arg @ref UART_FLAG_IDLE Idle Line detection flag * @arg @ref UART_FLAG_ORE Overrun Error flag * @arg @ref UART_FLAG_NE Noise Error flag * @arg @ref UART_FLAG_FE Framing Error flag * @arg @ref UART_FLAG_PE Parity Error flag * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) /** @brief Enable the specified UART interrupt. * @param __HANDLE__ specifies the UART Handle. * @param __INTERRUPT__ specifies the UART interrupt source to enable. * This parameter can be one of the following values: * @arg @ref UART_IT_RXFF RXFIFO Full interrupt * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt * @arg @ref UART_IT_CM Character match interrupt * @arg @ref UART_IT_CTS CTS change interrupt * @arg @ref UART_IT_LBD LIN Break detection interrupt * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt * @arg @ref UART_IT_TC Transmission complete interrupt * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt * @arg @ref UART_IT_RTO Receive Timeout interrupt * @arg @ref UART_IT_IDLE Idle line detection interrupt * @arg @ref UART_IT_PE Parity Error interrupt * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error) * @retval None */ #define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (\ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ ((__HANDLE__)->Instance->CR1 |= (1U <<\ ((__INTERRUPT__) & UART_IT_MASK))): \ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ ((__HANDLE__)->Instance->CR2 |= (1U <<\ ((__INTERRUPT__) & UART_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 |= (1U <<\ ((__INTERRUPT__) & UART_IT_MASK)))) /** @brief Disable the specified UART interrupt. * @param __HANDLE__ specifies the UART Handle. * @param __INTERRUPT__ specifies the UART interrupt source to disable. * This parameter can be one of the following values: * @arg @ref UART_IT_RXFF RXFIFO Full interrupt * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt * @arg @ref UART_IT_CM Character match interrupt * @arg @ref UART_IT_CTS CTS change interrupt * @arg @ref UART_IT_LBD LIN Break detection interrupt * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt * @arg @ref UART_IT_TC Transmission complete interrupt * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt * @arg @ref UART_IT_RTO Receive Timeout interrupt * @arg @ref UART_IT_IDLE Idle line detection interrupt * @arg @ref UART_IT_PE Parity Error interrupt * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) * @retval None */ #define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (\ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ ((__INTERRUPT__) & UART_IT_MASK))): \ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ ((__INTERRUPT__) & UART_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ ((__INTERRUPT__) & UART_IT_MASK)))) /** @brief Check whether the specified UART interrupt has occurred or not. * @param __HANDLE__ specifies the UART Handle. * @param __INTERRUPT__ specifies the UART interrupt to check. * This parameter can be one of the following values: * @arg @ref UART_IT_RXFF RXFIFO Full interrupt * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt * @arg @ref UART_IT_CM Character match interrupt * @arg @ref UART_IT_CTS CTS change interrupt * @arg @ref UART_IT_LBD LIN Break detection interrupt * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt * @arg @ref UART_IT_TC Transmission complete interrupt * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt * @arg @ref UART_IT_RTO Receive Timeout interrupt * @arg @ref UART_IT_IDLE Idle line detection interrupt * @arg @ref UART_IT_PE Parity Error interrupt * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) * @retval The new state of __INTERRUPT__ (SET or RESET). */ #define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) /** @brief Check whether the specified UART interrupt source is enabled or not. * @param __HANDLE__ specifies the UART Handle. * @param __INTERRUPT__ specifies the UART interrupt source to check. * This parameter can be one of the following values: * @arg @ref UART_IT_RXFF RXFIFO Full interrupt * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt * @arg @ref UART_IT_CM Character match interrupt * @arg @ref UART_IT_CTS CTS change interrupt * @arg @ref UART_IT_LBD LIN Break detection interrupt * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt * @arg @ref UART_IT_TC Transmission complete interrupt * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt * @arg @ref UART_IT_RTO Receive Timeout interrupt * @arg @ref UART_IT_IDLE Idle line detection interrupt * @arg @ref UART_IT_PE Parity Error interrupt * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) * @retval The new state of __INTERRUPT__ (SET or RESET). */ #define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\ (__HANDLE__)->Instance->CR1 : \ (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\ (__HANDLE__)->Instance->CR2 : \ (__HANDLE__)->Instance->CR3)) & (1U <<\ (((uint16_t)(__INTERRUPT__)) &\ UART_IT_MASK))) != RESET) ? SET : RESET) /** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the UART Handle. * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set * to clear the corresponding interrupt * This parameter can be one of the following values: * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag * @arg @ref UART_CLEAR_RTOF Receiver timeout clear flag * @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag * @arg @ref UART_CLEAR_CMF Character Match Clear Flag * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag * @retval None */ #define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) /** @brief Set a specific UART request flag. * @param __HANDLE__ specifies the UART Handle. * @param __REQ__ specifies the request flag to set * This parameter can be one of the following values: * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request * @arg @ref UART_SENDBREAK_REQUEST Send Break Request * @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request * @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request * @retval None */ #define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) /** @brief Enable the UART one bit sample method. * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) /** @brief Disable the UART one bit sample method. * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) /** @brief Enable UART. * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) /** @brief Disable UART. * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) /** @brief Enable CTS flow control. * @note This macro allows to enable CTS hardware flow control for a given UART instance, * without need to call HAL_UART_Init() function. * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ do{ \ ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ } while(0U) /** @brief Disable CTS flow control. * @note This macro allows to disable CTS hardware flow control for a given UART instance, * without need to call HAL_UART_Init() function. * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ do{ \ ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ } while(0U) /** @brief Enable RTS flow control. * @note This macro allows to enable RTS hardware flow control for a given UART instance, * without need to call HAL_UART_Init() function. * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ do{ \ ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ } while(0U) /** @brief Disable RTS flow control. * @note This macro allows to disable RTS hardware flow control for a given UART instance, * without need to call HAL_UART_Init() function. * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ do{ \ ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ } while(0U) /** * @} */ /* Private macros --------------------------------------------------------*/ /** @defgroup UART_Private_Macros UART Private Macros * @{ */ #if defined(USART_PRESC_PRESCALER) /** @brief Get UART clock division factor from clock prescaler value. * @param __CLOCKPRESCALER__ UART prescaler value. * @retval UART clock division factor */ #define UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \ (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) ? 1U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) ? 2U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) ? 4U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) ? 6U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) ? 8U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) ? 10U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) ? 12U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : 256U) /** @brief BRR division operation to set BRR register with LPUART. * @param __PCLK__ LPUART clock. * @param __BAUD__ Baud rate set by the user. * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ #define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ ((uint32_t)((((((uint64_t)(__PCLK__))/(UARTPrescTable[(__CLOCKPRESCALER__)]))*256U)+ \ (uint32_t)((__BAUD__)/2U)) / (__BAUD__)) \ ) /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ UART clock. * @param __BAUD__ Baud rate set by the user. * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ #define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U) + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief BRR division operation to set BRR register in 16-bit oversampling mode. * @param __PCLK__ UART clock. * @param __BAUD__ Baud rate set by the user. * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ #define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__)) #else /** @brief BRR division operation to set BRR register with LPUART. * @param __PCLK__ LPUART clock. * @param __BAUD__ Baud rate set by the user. * @retval Division result */ #define UART_DIV_LPUART(__PCLK__, __BAUD__) (((((uint64_t)(__PCLK__)*256U)) + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ UART clock. * @param __BAUD__ Baud rate set by the user. * @retval Division result */ #define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief BRR division operation to set BRR register in 16-bit oversampling mode. * @param __PCLK__ UART clock. * @param __BAUD__ Baud rate set by the user. * @retval Division result */ #define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__)) #endif /* USART_PRESC_PRESCALER */ /** @brief Check whether or not UART instance is Low Power UART. * @param __HANDLE__ specifies the UART Handle. * @retval SET (instance is LPUART) or RESET (instance isn't LPUART) */ #define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance)) /** @brief Check UART Baud rate. * @param __BAUDRATE__ Baudrate specified by the user. * The maximum Baud Rate is derived from the maximum clock on L4 * divided by the smallest oversampling used on the USART (i.e. 8) * (i.e. 120 MHz on STM32L4Rx/L4Sx, 80 Mhz otherwise) * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) */ #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 15000001U) #else #define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 10000001U) #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** @brief Check UART assertion time. * @param __TIME__ 5-bit value assertion time. * @retval Test result (TRUE or FALSE). */ #define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) /** @brief Check UART deassertion time. * @param __TIME__ 5-bit value deassertion time. * @retval Test result (TRUE or FALSE). */ #define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) /** * @brief Ensure that UART frame number of stop bits is valid. * @param __STOPBITS__ UART frame number of stop bits. * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) */ #define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \ ((__STOPBITS__) == UART_STOPBITS_1) || \ ((__STOPBITS__) == UART_STOPBITS_1_5) || \ ((__STOPBITS__) == UART_STOPBITS_2)) /** * @brief Ensure that LPUART frame number of stop bits is valid. * @param __STOPBITS__ LPUART frame number of stop bits. * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) */ #define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \ ((__STOPBITS__) == UART_STOPBITS_2)) /** * @brief Ensure that UART frame parity is valid. * @param __PARITY__ UART frame parity. * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) */ #define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \ ((__PARITY__) == UART_PARITY_EVEN) || \ ((__PARITY__) == UART_PARITY_ODD)) /** * @brief Ensure that UART hardware flow control is valid. * @param __CONTROL__ UART hardware flow control. * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid) */ #define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\ (((__CONTROL__) == UART_HWCONTROL_NONE) || \ ((__CONTROL__) == UART_HWCONTROL_RTS) || \ ((__CONTROL__) == UART_HWCONTROL_CTS) || \ ((__CONTROL__) == UART_HWCONTROL_RTS_CTS)) /** * @brief Ensure that UART communication mode is valid. * @param __MODE__ UART communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) /** * @brief Ensure that UART state is valid. * @param __STATE__ UART state. * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) */ #define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \ ((__STATE__) == UART_STATE_ENABLE)) /** * @brief Ensure that UART oversampling is valid. * @param __SAMPLING__ UART oversampling. * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) */ #define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \ ((__SAMPLING__) == UART_OVERSAMPLING_8)) /** * @brief Ensure that UART frame sampling is valid. * @param __ONEBIT__ UART frame sampling. * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) */ #define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \ ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE)) /** * @brief Ensure that UART auto Baud rate detection mode is valid. * @param __MODE__ UART auto Baud rate detection mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME)) /** * @brief Ensure that UART receiver timeout setting is valid. * @param __TIMEOUT__ UART receiver timeout setting. * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) */ #define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE)) /** @brief Check the receiver timeout value. * @note The maximum UART receiver timeout value is 0xFFFFFF. * @param __TIMEOUTVALUE__ receiver timeout value. * @retval Test result (TRUE or FALSE) */ #define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) /** * @brief Ensure that UART LIN state is valid. * @param __LIN__ UART LIN state. * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid) */ #define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \ ((__LIN__) == UART_LIN_ENABLE)) /** * @brief Ensure that UART LIN break detection length is valid. * @param __LENGTH__ UART LIN break detection length. * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) */ #define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \ ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B)) /** * @brief Ensure that UART DMA TX state is valid. * @param __DMATX__ UART DMA TX state. * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) */ #define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \ ((__DMATX__) == UART_DMA_TX_ENABLE)) /** * @brief Ensure that UART DMA RX state is valid. * @param __DMARX__ UART DMA RX state. * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) */ #define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \ ((__DMARX__) == UART_DMA_RX_ENABLE)) /** * @brief Ensure that UART half-duplex state is valid. * @param __HDSEL__ UART half-duplex state. * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid) */ #define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \ ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE)) /** * @brief Ensure that UART wake-up method is valid. * @param __WAKEUP__ UART wake-up method . * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid) */ #define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \ ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK)) /** * @brief Ensure that UART request parameter is valid. * @param __PARAM__ UART request parameter. * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) */ #define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \ ((__PARAM__) == UART_SENDBREAK_REQUEST) || \ ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \ ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \ ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST)) /** * @brief Ensure that UART advanced features initialization is valid. * @param __INIT__ UART advanced features initialization. * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) */ #define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ UART_ADVFEATURE_TXINVERT_INIT | \ UART_ADVFEATURE_RXINVERT_INIT | \ UART_ADVFEATURE_DATAINVERT_INIT | \ UART_ADVFEATURE_SWAP_INIT | \ UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ UART_ADVFEATURE_DMADISABLEONERROR_INIT | \ UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ UART_ADVFEATURE_MSBFIRST_INIT)) /** * @brief Ensure that UART frame TX inversion setting is valid. * @param __TXINV__ UART frame TX inversion setting. * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) */ #define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \ ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE)) /** * @brief Ensure that UART frame RX inversion setting is valid. * @param __RXINV__ UART frame RX inversion setting. * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) */ #define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \ ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE)) /** * @brief Ensure that UART frame data inversion setting is valid. * @param __DATAINV__ UART frame data inversion setting. * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) */ #define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \ ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE)) /** * @brief Ensure that UART frame RX/TX pins swap setting is valid. * @param __SWAP__ UART frame RX/TX pins swap setting. * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) */ #define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \ ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE)) /** * @brief Ensure that UART frame overrun setting is valid. * @param __OVERRUN__ UART frame overrun setting. * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) */ #define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \ ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE)) /** * @brief Ensure that UART auto Baud rate state is valid. * @param __AUTOBAUDRATE__ UART auto Baud rate state. * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid) */ #define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == \ UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) /** * @brief Ensure that UART DMA enabling or disabling on error setting is valid. * @param __DMA__ UART DMA enabling or disabling on error setting. * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) */ #define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \ ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR)) /** * @brief Ensure that UART frame MSB first setting is valid. * @param __MSBFIRST__ UART frame MSB first setting. * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) */ #define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \ ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE)) /** * @brief Ensure that UART stop mode state is valid. * @param __STOPMODE__ UART stop mode state. * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid) */ #define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \ ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE)) /** * @brief Ensure that UART mute mode state is valid. * @param __MUTE__ UART mute mode state. * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid) */ #define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \ ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE)) /** * @brief Ensure that UART wake-up selection is valid. * @param __WAKE__ UART wake-up selection. * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid) */ #define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \ ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY)) /** * @brief Ensure that UART driver enable polarity is valid. * @param __POLARITY__ UART driver enable polarity. * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid) */ #define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \ ((__POLARITY__) == UART_DE_POLARITY_LOW)) #if defined(USART_PRESC_PRESCALER) /** * @brief Ensure that UART Prescaler is valid. * @param __CLOCKPRESCALER__ UART Prescaler value. * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) */ #define IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) || \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) || \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) || \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) || \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) || \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) || \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) || \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) || \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) || \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) || \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256)) #endif /* USART_PRESC_PRESCALER */ /** * @} */ /* Include UART HAL Extended module */ #include "stm32l4xx_hal_uart_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup UART_Exported_Functions UART Exported Functions * @{ */ /** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ /* Initialization and de-initialization functions ****************************/ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart); void HAL_UART_MspInit(UART_HandleTypeDef *huart); void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ /** * @} */ /** @addtogroup UART_Exported_Functions_Group2 IO operation functions * @{ */ /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); /* Transfer Abort functions */ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart); void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size); /** * @} */ /** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions * @{ */ /* Peripheral Control functions ************************************************/ void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue); HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart); void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); /** * @} */ /** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions * @{ */ /* Peripheral State and Errors functions **************************************************/ HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart); uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart); /** * @} */ /** * @} */ /* Private functions -----------------------------------------------------------*/ /** @addtogroup UART_Private_Functions UART Private Functions * @{ */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); /** * @} */ /* Private variables -----------------------------------------------------------*/ #if defined(USART_PRESC_PRESCALER) /** @defgroup UART_Private_variables UART Private variables * @{ */ /* Prescaler Table used in BRR computation macros. Declared as extern here to allow use of private UART macros, outside of HAL UART functions */ extern const uint16_t UARTPrescTable[12]; /** * @} */ #endif /* USART_PRESC_PRESCALER */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32L4xx_HAL_UART_H */
New file @@ -0,0 +1,748 @@ /** ****************************************************************************** * @file stm32l4xx_hal_uart_ex.h * @author MCD Application Team * @brief Header file of UART HAL Extended module. ****************************************************************************** * @attention * * Copyright (c) 2017 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32L4xx_HAL_UART_EX_H #define STM32L4xx_HAL_UART_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" /** @addtogroup STM32L4xx_HAL_Driver * @{ */ /** @addtogroup UARTEx * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup UARTEx_Exported_Types UARTEx Exported Types * @{ */ /** * @brief UART wake up from stop mode parameters */ typedef struct { uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF). This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection. If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must be filled up. */ uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long. This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */ uint8_t Address; /*!< UART/USART node address (7-bit long max). */ } UART_WakeUpTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants * @{ */ /** @defgroup UARTEx_Word_Length UARTEx Word Length * @{ */ #define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ #define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ #define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ /** * @} */ /** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length * @{ */ #define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ #define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ /** * @} */ #if defined(USART_CR1_FIFOEN) /** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode * @brief UART FIFO mode * @{ */ #define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ #define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ /** * @} */ /** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level * @brief UART TXFIFO threshold level * @{ */ #define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TX FIFO reaches 1/8 of its depth */ #define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TX FIFO reaches 1/4 of its depth */ #define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TX FIFO reaches 1/2 of its depth */ #define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */ #define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TX FIFO reaches 7/8 of its depth */ #define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty */ /** * @} */ /** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level * @brief UART RXFIFO threshold level * @{ */ #define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RX FIFO reaches 1/8 of its depth */ #define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RX FIFO reaches 1/4 of its depth */ #define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RX FIFO reaches 1/2 of its depth */ #define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */ #define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RX FIFO reaches 7/8 of its depth */ #define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full */ /** * @} */ #endif /* USART_CR1_FIFOEN */ /** * @} */ /* Exported macros -----------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup UARTEx_Exported_Functions * @{ */ /** @addtogroup UARTEx_Exported_Functions_Group1 * @{ */ /* Initialization and de-initialization functions ****************************/ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime); /** * @} */ /** @addtogroup UARTEx_Exported_Functions_Group2 * @{ */ void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); #if defined(USART_CR1_FIFOEN) void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart); void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart); #endif /* USART_CR1_FIFOEN */ /** * @} */ /** @addtogroup UARTEx_Exported_Functions_Group3 * @{ */ /* Peripheral Control functions **********************************************/ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); #if defined(USART_CR3_UCESM) HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart); #endif /* USART_CR3_UCESM */ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); #if defined(USART_CR1_FIFOEN) HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); #endif /* USART_CR1_FIFOEN */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout); HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart); /** * @} */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @defgroup UARTEx_Private_Macros UARTEx Private Macros * @{ */ /** @brief Report the UART clock source. * @param __HANDLE__ specifies the UART Handle. * @param __CLOCKSOURCE__ output variable. * @retval UART clocking source, written in __CLOCKSOURCE__. */ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) \ || defined (STM32L485xx) || defined (STM32L486xx) \ || defined (STM32L496xx) || defined (STM32L4A6xx) \ || defined (STM32L4P5xx) || defined (STM32L4Q5xx) \ || defined (STM32L4R5xx) || defined (STM32L4R7xx) \ || defined (STM32L4R9xx) || defined (STM32L4S5xx) \ || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ switch(__HAL_RCC_GET_USART1_SOURCE()) \ { \ case RCC_USART1CLKSOURCE_PCLK2: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ break; \ case RCC_USART1CLKSOURCE_HSI: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ break; \ case RCC_USART1CLKSOURCE_SYSCLK: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ break; \ case RCC_USART1CLKSOURCE_LSE: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ break; \ default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ } \ } \ else if((__HANDLE__)->Instance == USART2) \ { \ switch(__HAL_RCC_GET_USART2_SOURCE()) \ { \ case RCC_USART2CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ case RCC_USART2CLKSOURCE_HSI: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ break; \ case RCC_USART2CLKSOURCE_SYSCLK: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ break; \ case RCC_USART2CLKSOURCE_LSE: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ break; \ default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ } \ } \ else if((__HANDLE__)->Instance == USART3) \ { \ switch(__HAL_RCC_GET_USART3_SOURCE()) \ { \ case RCC_USART3CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ case RCC_USART3CLKSOURCE_HSI: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ break; \ case RCC_USART3CLKSOURCE_SYSCLK: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ break; \ case RCC_USART3CLKSOURCE_LSE: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ break; \ default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ } \ } \ else if((__HANDLE__)->Instance == UART4) \ { \ switch(__HAL_RCC_GET_UART4_SOURCE()) \ { \ case RCC_UART4CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ case RCC_UART4CLKSOURCE_HSI: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ break; \ case RCC_UART4CLKSOURCE_SYSCLK: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ break; \ case RCC_UART4CLKSOURCE_LSE: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ break; \ default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ } \ } \ else if((__HANDLE__)->Instance == UART5) \ { \ switch(__HAL_RCC_GET_UART5_SOURCE()) \ { \ case RCC_UART5CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ case RCC_UART5CLKSOURCE_HSI: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ break; \ case RCC_UART5CLKSOURCE_SYSCLK: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ break; \ case RCC_UART5CLKSOURCE_LSE: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ break; \ default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ } \ } \ else if((__HANDLE__)->Instance == LPUART1) \ { \ switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ { \ case RCC_LPUART1CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ case RCC_LPUART1CLKSOURCE_HSI: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ break; \ case RCC_LPUART1CLKSOURCE_SYSCLK: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ break; \ case RCC_LPUART1CLKSOURCE_LSE: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ break; \ default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ } \ } \ else \ { \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ } \ } while(0U) #elif defined (STM32L412xx) || defined (STM32L422xx) \ || defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ switch(__HAL_RCC_GET_USART1_SOURCE()) \ { \ case RCC_USART1CLKSOURCE_PCLK2: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ break; \ case RCC_USART1CLKSOURCE_HSI: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ break; \ case RCC_USART1CLKSOURCE_SYSCLK: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ break; \ case RCC_USART1CLKSOURCE_LSE: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ break; \ default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ } \ } \ else if((__HANDLE__)->Instance == USART2) \ { \ switch(__HAL_RCC_GET_USART2_SOURCE()) \ { \ case RCC_USART2CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ case RCC_USART2CLKSOURCE_HSI: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ break; \ case RCC_USART2CLKSOURCE_SYSCLK: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ break; \ case RCC_USART2CLKSOURCE_LSE: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ break; \ default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ } \ } \ else if((__HANDLE__)->Instance == USART3) \ { \ switch(__HAL_RCC_GET_USART3_SOURCE()) \ { \ case RCC_USART3CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ case RCC_USART3CLKSOURCE_HSI: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ break; \ case RCC_USART3CLKSOURCE_SYSCLK: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ break; \ case RCC_USART3CLKSOURCE_LSE: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ break; \ default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ } \ } \ else if((__HANDLE__)->Instance == LPUART1) \ { \ switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ { \ case RCC_LPUART1CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ case RCC_LPUART1CLKSOURCE_HSI: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ break; \ case RCC_LPUART1CLKSOURCE_SYSCLK: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ break; \ case RCC_LPUART1CLKSOURCE_LSE: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ break; \ default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ } \ } \ else \ { \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ } \ } while(0U) #elif defined (STM32L432xx) || defined (STM32L442xx) #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ switch(__HAL_RCC_GET_USART1_SOURCE()) \ { \ case RCC_USART1CLKSOURCE_PCLK2: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ break; \ case RCC_USART1CLKSOURCE_HSI: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ break; \ case RCC_USART1CLKSOURCE_SYSCLK: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ break; \ case RCC_USART1CLKSOURCE_LSE: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ break; \ default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ } \ } \ else if((__HANDLE__)->Instance == USART2) \ { \ switch(__HAL_RCC_GET_USART2_SOURCE()) \ { \ case RCC_USART2CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ case RCC_USART2CLKSOURCE_HSI: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ break; \ case RCC_USART2CLKSOURCE_SYSCLK: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ break; \ case RCC_USART2CLKSOURCE_LSE: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ break; \ default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ } \ } \ else if((__HANDLE__)->Instance == LPUART1) \ { \ switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ { \ case RCC_LPUART1CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ case RCC_LPUART1CLKSOURCE_HSI: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ break; \ case RCC_LPUART1CLKSOURCE_SYSCLK: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ break; \ case RCC_LPUART1CLKSOURCE_LSE: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ break; \ default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ } \ } \ else \ { \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ } \ } while(0U) #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ switch(__HAL_RCC_GET_USART1_SOURCE()) \ { \ case RCC_USART1CLKSOURCE_PCLK2: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ break; \ case RCC_USART1CLKSOURCE_HSI: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ break; \ case RCC_USART1CLKSOURCE_SYSCLK: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ break; \ case RCC_USART1CLKSOURCE_LSE: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ break; \ default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ } \ } \ else if((__HANDLE__)->Instance == USART2) \ { \ switch(__HAL_RCC_GET_USART2_SOURCE()) \ { \ case RCC_USART2CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ case RCC_USART2CLKSOURCE_HSI: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ break; \ case RCC_USART2CLKSOURCE_SYSCLK: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ break; \ case RCC_USART2CLKSOURCE_LSE: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ break; \ default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ } \ } \ else if((__HANDLE__)->Instance == USART3) \ { \ switch(__HAL_RCC_GET_USART3_SOURCE()) \ { \ case RCC_USART3CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ case RCC_USART3CLKSOURCE_HSI: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ break; \ case RCC_USART3CLKSOURCE_SYSCLK: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ break; \ case RCC_USART3CLKSOURCE_LSE: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ break; \ default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ } \ } \ else if((__HANDLE__)->Instance == UART4) \ { \ switch(__HAL_RCC_GET_UART4_SOURCE()) \ { \ case RCC_UART4CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ case RCC_UART4CLKSOURCE_HSI: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ break; \ case RCC_UART4CLKSOURCE_SYSCLK: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ break; \ case RCC_UART4CLKSOURCE_LSE: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ break; \ default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ } \ } \ else if((__HANDLE__)->Instance == LPUART1) \ { \ switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ { \ case RCC_LPUART1CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ case RCC_LPUART1CLKSOURCE_HSI: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ break; \ case RCC_LPUART1CLKSOURCE_SYSCLK: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ break; \ case RCC_LPUART1CLKSOURCE_LSE: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ break; \ default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ } \ } \ else \ { \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ } \ } while(0U) #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || * STM32L496xx || STM32L4A6xx || * STM32L4P5xx || STM32L4Q5xx || * STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** @brief Report the UART mask to apply to retrieve the received data * according to the word length and to the parity bits activation. * @note If PCE = 1, the parity bit is not included in the data extracted * by the reception API(). * This masking operation is not carried out in the case of * DMA transfers. * @param __HANDLE__ specifies the UART Handle. * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field. */ #define UART_MASK_COMPUTATION(__HANDLE__) \ do { \ if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ { \ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ { \ (__HANDLE__)->Mask = 0x01FFU ; \ } \ else \ { \ (__HANDLE__)->Mask = 0x00FFU ; \ } \ } \ else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ { \ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ { \ (__HANDLE__)->Mask = 0x00FFU ; \ } \ else \ { \ (__HANDLE__)->Mask = 0x007FU ; \ } \ } \ else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ { \ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ { \ (__HANDLE__)->Mask = 0x007FU ; \ } \ else \ { \ (__HANDLE__)->Mask = 0x003FU ; \ } \ } \ else \ { \ (__HANDLE__)->Mask = 0x0000U; \ } \ } while(0U) /** * @brief Ensure that UART frame length is valid. * @param __LENGTH__ UART frame length. * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) */ #define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \ ((__LENGTH__) == UART_WORDLENGTH_8B) || \ ((__LENGTH__) == UART_WORDLENGTH_9B)) /** * @brief Ensure that UART wake-up address length is valid. * @param __ADDRESS__ UART wake-up address length. * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid) */ #define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \ ((__ADDRESS__) == UART_ADDRESS_DETECT_7B)) #if defined(USART_CR1_FIFOEN) /** * @brief Ensure that UART TXFIFO threshold level is valid. * @param __THRESHOLD__ UART TXFIFO threshold level. * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) */ #define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \ ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \ ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \ ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \ ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \ ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8)) /** * @brief Ensure that UART RXFIFO threshold level is valid. * @param __THRESHOLD__ UART RXFIFO threshold level. * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) */ #define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \ ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \ ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \ ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \ ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \ ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8)) #endif /* USART_CR1_FIFOEN */ /** * @} */ /* Private functions ---------------------------------------------------------*/ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32L4xx_HAL_UART_EX_H */
New file @@ -0,0 +1,2892 @@ /** ****************************************************************************** * @file stm32l4xx_ll_lpuart.h * @author MCD Application Team * @brief Header file of LPUART LL module. ****************************************************************************** * @attention * * Copyright (c) 2017 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32L4xx_LL_LPUART_H #define STM32L4xx_LL_LPUART_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx.h" /** @addtogroup STM32L4xx_LL_Driver * @{ */ #if defined (LPUART1) /** @defgroup LPUART_LL LPUART * @{ */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ #if defined(USART_PRESC_PRESCALER) /** @defgroup LPUART_LL_Private_Variables LPUART Private Variables * @{ */ /* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */ static const uint16_t LPUART_PRESCALER_TAB[] = { (uint16_t)1, (uint16_t)2, (uint16_t)4, (uint16_t)6, (uint16_t)8, (uint16_t)10, (uint16_t)12, (uint16_t)16, (uint16_t)32, (uint16_t)64, (uint16_t)128, (uint16_t)256 }; /** * @} */ #endif /* USART_PRESC_PRESCALER */ /* Private constants ---------------------------------------------------------*/ /** @defgroup LPUART_LL_Private_Constants LPUART Private Constants * @{ */ /* Defines used in Baud Rate related macros and corresponding register setting computation */ #define LPUART_LPUARTDIV_FREQ_MUL 256U #define LPUART_BRR_MASK 0x000FFFFFU #define LPUART_BRR_MIN_VALUE 0x00000300U /** * @} */ /* Private macros ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup LPUART_LL_Private_Macros LPUART Private Macros * @{ */ /** * @} */ #endif /*USE_FULL_LL_DRIVER*/ /* Exported types ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures * @{ */ /** * @brief LL LPUART Init Structure definition */ typedef struct { #if defined(USART_PRESC_PRESCALER) uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate. This parameter can be a value of @ref LPUART_LL_EC_PRESCALER. This feature can be modified afterwards using unitary function @ref LL_LPUART_SetPrescaler().*/ #endif /* USART_PRESC_PRESCALER */ uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate. This feature can be modified afterwards using unitary function @ref LL_LPUART_SetBaudRate().*/ uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH. This feature can be modified afterwards using unitary function @ref LL_LPUART_SetDataWidth().*/ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. This parameter can be a value of @ref LPUART_LL_EC_STOPBITS. This feature can be modified afterwards using unitary function @ref LL_LPUART_SetStopBitsLength().*/ uint32_t Parity; /*!< Specifies the parity mode. This parameter can be a value of @ref LPUART_LL_EC_PARITY. This feature can be modified afterwards using unitary function @ref LL_LPUART_SetParity().*/ uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. This parameter can be a value of @ref LPUART_LL_EC_DIRECTION. This feature can be modified afterwards using unitary function @ref LL_LPUART_SetTransferDirection().*/ uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL. This feature can be modified afterwards using unitary function @ref LL_LPUART_SetHWFlowCtrl().*/ } LL_LPUART_InitTypeDef; /** * @} */ #endif /* USE_FULL_LL_DRIVER */ /* Exported constants --------------------------------------------------------*/ /** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants * @{ */ /** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines * @brief Flags defines which can be used with LL_LPUART_WriteReg function * @{ */ #define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */ #define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */ #define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected clear flag */ #define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */ #define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */ #define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */ #define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */ #define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */ #define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */ /** * @} */ /** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines * @brief Flags defines which can be used with LL_LPUART_ReadReg function * @{ */ #define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */ #define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */ #define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ #define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ #define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ #if defined(USART_CR1_FIFOEN) #define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ #else #define LL_LPUART_ISR_RXNE USART_ISR_RXNE /*!< Read data register not empty flag */ #endif /* USART_CR1_FIFOEN */ #define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ #if defined(USART_CR1_FIFOEN) #define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/ #else #define LL_LPUART_ISR_TXE USART_ISR_TXE /*!< Transmit data register empty flag */ #endif /* USART_CR1_FIFOEN */ #define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ #define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ #define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ #define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ #define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ #define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ #define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */ #define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ #define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ #if defined(USART_CR1_FIFOEN) #define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */ #define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ #define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ #define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ #endif /* USART_CR1_FIFOEN */ /** * @} */ /** @defgroup LPUART_LL_EC_IT IT Defines * @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions * @{ */ #define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ #if defined(USART_CR1_FIFOEN) #define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty interrupt enable */ #else #define LL_LPUART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */ #endif /* USART_CR1_FIFOEN */ #define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ #if defined(USART_CR1_FIFOEN) #define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO not full interrupt enable */ #else #define LL_LPUART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */ #endif /* USART_CR1_FIFOEN */ #define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ #define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ #if defined(USART_CR1_FIFOEN) #define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ #define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ #endif /* USART_CR1_FIFOEN */ #define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ #define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ #define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */ #if defined(USART_CR1_FIFOEN) #define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ #define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ #endif /* USART_CR1_FIFOEN */ /** * @} */ #if defined(USART_CR1_FIFOEN) /** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold * @{ */ #define LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */ #define LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */ #define LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */ #define LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */ #define LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */ #define LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */ /** * @} */ #endif /* USART_CR1_FIFOEN */ /** @defgroup LPUART_LL_EC_DIRECTION Direction * @{ */ #define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ #define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ #define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ #define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ /** * @} */ /** @defgroup LPUART_LL_EC_PARITY Parity Control * @{ */ #define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ #define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ #define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ /** * @} */ /** @defgroup LPUART_LL_EC_WAKEUP Wakeup * @{ */ #define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */ #define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */ /** * @} */ /** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth * @{ */ #define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */ #define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ #define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ /** * @} */ #if defined(USART_PRESC_PRESCALER) /** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler * @{ */ #define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */ #define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */ #define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */ #define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 |\ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */ #define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */ #define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 |\ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */ #define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 |\ USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */ #define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 |\ USART_PRESC_PRESCALER_1 |\ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */ #define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */ #define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 |\ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */ #define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\ USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */ #define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\ USART_PRESC_PRESCALER_1 |\ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */ /** * @} */ #endif /* USART_PRESC_PRESCALER */ /** @defgroup LPUART_LL_EC_STOPBITS Stop Bits * @{ */ #define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ #define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ /** * @} */ /** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap * @{ */ #define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ #define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ /** * @} */ /** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion * @{ */ #define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ #define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ /** * @} */ /** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion * @{ */ #define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ #define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ /** * @} */ /** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion * @{ */ #define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */ #define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */ /** * @} */ /** @defgroup LPUART_LL_EC_BITORDER Bit Order * @{ */ #define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */ #define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */ /** * @} */ /** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection * @{ */ #define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */ #define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ /** * @} */ /** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control * @{ */ #define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ #define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */ #define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0)*/ #define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ /** * @} */ /** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation * @{ */ #define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */ #define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */ #define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */ /** * @} */ /** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity * @{ */ #define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ #define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ /** * @} */ /** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data * @{ */ #define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ #define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros * @{ */ /** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros * @{ */ /** * @brief Write a value in LPUART register * @param __INSTANCE__ LPUART Instance * @param __REG__ Register to be written * @param __VALUE__ Value to be written in the register * @retval None */ #define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) /** * @brief Read a value in LPUART register * @param __INSTANCE__ LPUART Instance * @param __REG__ Register to be read * @retval Register value */ #define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) /** * @} */ /** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros * @{ */ /** * @brief Compute LPUARTDIV value according to Peripheral Clock and * expected Baud Rate (20-bit value of LPUARTDIV is returned) * @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance @if USART_PRESC_PRESCALER * @param __PRESCALER__ This parameter can be one of the following values: * @arg @ref LL_LPUART_PRESCALER_DIV1 * @arg @ref LL_LPUART_PRESCALER_DIV2 * @arg @ref LL_LPUART_PRESCALER_DIV4 * @arg @ref LL_LPUART_PRESCALER_DIV6 * @arg @ref LL_LPUART_PRESCALER_DIV8 * @arg @ref LL_LPUART_PRESCALER_DIV10 * @arg @ref LL_LPUART_PRESCALER_DIV12 * @arg @ref LL_LPUART_PRESCALER_DIV16 * @arg @ref LL_LPUART_PRESCALER_DIV32 * @arg @ref LL_LPUART_PRESCALER_DIV64 * @arg @ref LL_LPUART_PRESCALER_DIV128 * @arg @ref LL_LPUART_PRESCALER_DIV256 @endif * @param __BAUDRATE__ Baud Rate value to achieve * @retval LPUARTDIV value to be used for BRR register filling */ #if defined(USART_PRESC_PRESCALER) #define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)\ ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\ * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK) #else #define __LL_LPUART_DIV(__PERIPHCLK__, __BAUDRATE__) (uint32_t)\ (((((uint64_t)(__PERIPHCLK__)*LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) \ & LPUART_BRR_MASK) #endif /* USART_PRESC_PRESCALER */ /** * @} */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions * @{ */ /** @defgroup LPUART_LL_EF_Configuration Configuration functions * @{ */ /** * @brief LPUART Enable * @rmtoll CR1 UE LL_LPUART_Enable * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx) { SET_BIT(LPUARTx->CR1, USART_CR1_UE); } /** * @brief LPUART Disable * @note When LPUART is disabled, LPUART prescalers and outputs are stopped immediately, * and current operations are discarded. The configuration of the LPUART is kept, but all the status * flags, in the LPUARTx_ISR are set to their default values. * @note In order to go into low-power mode without generating errors on the line, * the TE bit must be reset before and the software must wait * for the TC bit in the LPUART_ISR to be set before resetting the UE bit. * The DMA requests are also reset when UE = 0 so the DMA channel must * be disabled before resetting the UE bit. * @rmtoll CR1 UE LL_LPUART_Disable * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx) { CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE); } /** * @brief Indicate if LPUART is enabled * @rmtoll CR1 UE LL_LPUART_IsEnabled * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabled(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); } #if defined(USART_CR1_FIFOEN) /** * @brief FIFO Mode Enable * @rmtoll CR1 FIFOEN LL_LPUART_EnableFIFO * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx) { SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN); } /** * @brief FIFO Mode Disable * @rmtoll CR1 FIFOEN LL_LPUART_DisableFIFO * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx) { CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN); } /** * @brief Indicate if FIFO Mode is enabled * @rmtoll CR1 FIFOEN LL_LPUART_IsEnabledFIFO * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL); } /** * @brief Configure TX FIFO Threshold * @rmtoll CR3 TXFTCFG LL_LPUART_SetTXFIFOThreshold * @param LPUARTx LPUART Instance * @param Threshold This parameter can be one of the following values: * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 * @retval None */ __STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold) { ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); } /** * @brief Return TX FIFO Threshold Configuration * @rmtoll CR3 TXFTCFG LL_LPUART_GetTXFIFOThreshold * @param LPUARTx LPUART Instance * @retval Returned value can be one of the following values: * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 */ __STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); } /** * @brief Configure RX FIFO Threshold * @rmtoll CR3 RXFTCFG LL_LPUART_SetRXFIFOThreshold * @param LPUARTx LPUART Instance * @param Threshold This parameter can be one of the following values: * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 * @retval None */ __STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold) { ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); } /** * @brief Return RX FIFO Threshold Configuration * @rmtoll CR3 RXFTCFG LL_LPUART_GetRXFIFOThreshold * @param LPUARTx LPUART Instance * @retval Returned value can be one of the following values: * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 */ __STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); } /** * @brief Configure TX and RX FIFOs Threshold * @rmtoll CR3 TXFTCFG LL_LPUART_ConfigFIFOsThreshold\n * CR3 RXFTCFG LL_LPUART_ConfigFIFOsThreshold * @param LPUARTx LPUART Instance * @param TXThreshold This parameter can be one of the following values: * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 * @param RXThreshold This parameter can be one of the following values: * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 * @retval None */ __STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold) { ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \ (RXThreshold << USART_CR3_RXFTCFG_Pos)); } #endif /* USART_CR1_FIFOEN */ /** * @brief LPUART enabled in STOP Mode * @note When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that * LPUART clock selection is HSI or LSE in RCC. * @rmtoll CR1 UESM LL_LPUART_EnableInStopMode * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx) { ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM); } /** * @brief LPUART disabled in STOP Mode * @note When this function is disabled, LPUART is not able to wake up the MCU from Stop mode * @rmtoll CR1 UESM LL_LPUART_DisableInStopMode * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx) { ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM); } /** * @brief Indicate if LPUART is enabled in STOP Mode * (able to wake up MCU from Stop mode or not) * @rmtoll CR1 UESM LL_LPUART_IsEnabledInStopMode * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); } #if defined(USART_CR3_UCESM) /** * @brief LPUART Clock enabled in STOP Mode * @note When this function is called, LPUART Clock is enabled while in STOP mode * @rmtoll CR3 UCESM LL_LPUART_EnableClockInStopMode * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_EnableClockInStopMode(USART_TypeDef *LPUARTx) { ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_UCESM); } /** * @brief LPUART clock disabled in STOP Mode * @note When this function is called, LPUART Clock is disabled while in STOP mode * @rmtoll CR3 UCESM LL_LPUART_DisableClockInStopMode * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_DisableClockInStopMode(USART_TypeDef *LPUARTx) { ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_UCESM); } /** * @brief Indicate if LPUART clock is enabled in STOP Mode * @rmtoll CR3 UCESM LL_LPUART_IsClockEnabledInStopMode * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsClockEnabledInStopMode(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_UCESM) == (USART_CR3_UCESM)) ? 1UL : 0UL); } #endif /* USART_CR3_UCESM */ /** * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) * @rmtoll CR1 RE LL_LPUART_EnableDirectionRx * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx) { ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE); } /** * @brief Receiver Disable * @rmtoll CR1 RE LL_LPUART_DisableDirectionRx * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx) { ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE); } /** * @brief Transmitter Enable * @rmtoll CR1 TE LL_LPUART_EnableDirectionTx * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx) { ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE); } /** * @brief Transmitter Disable * @rmtoll CR1 TE LL_LPUART_DisableDirectionTx * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx) { ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE); } /** * @brief Configure simultaneously enabled/disabled states * of Transmitter and Receiver * @rmtoll CR1 RE LL_LPUART_SetTransferDirection\n * CR1 TE LL_LPUART_SetTransferDirection * @param LPUARTx LPUART Instance * @param TransferDirection This parameter can be one of the following values: * @arg @ref LL_LPUART_DIRECTION_NONE * @arg @ref LL_LPUART_DIRECTION_RX * @arg @ref LL_LPUART_DIRECTION_TX * @arg @ref LL_LPUART_DIRECTION_TX_RX * @retval None */ __STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection) { ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); } /** * @brief Return enabled/disabled states of Transmitter and Receiver * @rmtoll CR1 RE LL_LPUART_GetTransferDirection\n * CR1 TE LL_LPUART_GetTransferDirection * @param LPUARTx LPUART Instance * @retval Returned value can be one of the following values: * @arg @ref LL_LPUART_DIRECTION_NONE * @arg @ref LL_LPUART_DIRECTION_RX * @arg @ref LL_LPUART_DIRECTION_TX * @arg @ref LL_LPUART_DIRECTION_TX_RX */ __STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE)); } /** * @brief Configure Parity (enabled/disabled and parity mode if enabled) * @note This function selects if hardware parity control (generation and detection) is enabled or disabled. * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position * (depending on data width) and parity is checked on the received data. * @rmtoll CR1 PS LL_LPUART_SetParity\n * CR1 PCE LL_LPUART_SetParity * @param LPUARTx LPUART Instance * @param Parity This parameter can be one of the following values: * @arg @ref LL_LPUART_PARITY_NONE * @arg @ref LL_LPUART_PARITY_EVEN * @arg @ref LL_LPUART_PARITY_ODD * @retval None */ __STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity) { MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); } /** * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) * @rmtoll CR1 PS LL_LPUART_GetParity\n * CR1 PCE LL_LPUART_GetParity * @param LPUARTx LPUART Instance * @retval Returned value can be one of the following values: * @arg @ref LL_LPUART_PARITY_NONE * @arg @ref LL_LPUART_PARITY_EVEN * @arg @ref LL_LPUART_PARITY_ODD */ __STATIC_INLINE uint32_t LL_LPUART_GetParity(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); } /** * @brief Set Receiver Wake Up method from Mute mode. * @rmtoll CR1 WAKE LL_LPUART_SetWakeUpMethod * @param LPUARTx LPUART Instance * @param Method This parameter can be one of the following values: * @arg @ref LL_LPUART_WAKEUP_IDLELINE * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK * @retval None */ __STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method) { MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method); } /** * @brief Return Receiver Wake Up method from Mute mode * @rmtoll CR1 WAKE LL_LPUART_GetWakeUpMethod * @param LPUARTx LPUART Instance * @retval Returned value can be one of the following values: * @arg @ref LL_LPUART_WAKEUP_IDLELINE * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK */ __STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE)); } /** * @brief Set Word length (nb of data bits, excluding start and stop bits) * @rmtoll CR1 M LL_LPUART_SetDataWidth * @param LPUARTx LPUART Instance * @param DataWidth This parameter can be one of the following values: * @arg @ref LL_LPUART_DATAWIDTH_7B * @arg @ref LL_LPUART_DATAWIDTH_8B * @arg @ref LL_LPUART_DATAWIDTH_9B * @retval None */ __STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth) { MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth); } /** * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) * @rmtoll CR1 M LL_LPUART_GetDataWidth * @param LPUARTx LPUART Instance * @retval Returned value can be one of the following values: * @arg @ref LL_LPUART_DATAWIDTH_7B * @arg @ref LL_LPUART_DATAWIDTH_8B * @arg @ref LL_LPUART_DATAWIDTH_9B */ __STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M)); } /** * @brief Allow switch between Mute Mode and Active mode * @rmtoll CR1 MME LL_LPUART_EnableMuteMode * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx) { ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME); } /** * @brief Prevent Mute Mode use. Set Receiver in active mode permanently. * @rmtoll CR1 MME LL_LPUART_DisableMuteMode * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx) { ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME); } /** * @brief Indicate if switch between Mute Mode and Active mode is allowed * @rmtoll CR1 MME LL_LPUART_IsEnabledMuteMode * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); } #if defined(USART_PRESC_PRESCALER) /** * @brief Configure Clock source prescaler for baudrate generator and oversampling * @rmtoll PRESC PRESCALER LL_LPUART_SetPrescaler * @param LPUARTx LPUART Instance * @param PrescalerValue This parameter can be one of the following values: * @arg @ref LL_LPUART_PRESCALER_DIV1 * @arg @ref LL_LPUART_PRESCALER_DIV2 * @arg @ref LL_LPUART_PRESCALER_DIV4 * @arg @ref LL_LPUART_PRESCALER_DIV6 * @arg @ref LL_LPUART_PRESCALER_DIV8 * @arg @ref LL_LPUART_PRESCALER_DIV10 * @arg @ref LL_LPUART_PRESCALER_DIV12 * @arg @ref LL_LPUART_PRESCALER_DIV16 * @arg @ref LL_LPUART_PRESCALER_DIV32 * @arg @ref LL_LPUART_PRESCALER_DIV64 * @arg @ref LL_LPUART_PRESCALER_DIV128 * @arg @ref LL_LPUART_PRESCALER_DIV256 * @retval None */ __STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue) { MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue); } /** * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling * @rmtoll PRESC PRESCALER LL_LPUART_GetPrescaler * @param LPUARTx LPUART Instance * @retval Returned value can be one of the following values: * @arg @ref LL_LPUART_PRESCALER_DIV1 * @arg @ref LL_LPUART_PRESCALER_DIV2 * @arg @ref LL_LPUART_PRESCALER_DIV4 * @arg @ref LL_LPUART_PRESCALER_DIV6 * @arg @ref LL_LPUART_PRESCALER_DIV8 * @arg @ref LL_LPUART_PRESCALER_DIV10 * @arg @ref LL_LPUART_PRESCALER_DIV12 * @arg @ref LL_LPUART_PRESCALER_DIV16 * @arg @ref LL_LPUART_PRESCALER_DIV32 * @arg @ref LL_LPUART_PRESCALER_DIV64 * @arg @ref LL_LPUART_PRESCALER_DIV128 * @arg @ref LL_LPUART_PRESCALER_DIV256 */ __STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER)); } #endif /* USART_PRESC_PRESCALER */ /** * @brief Set the length of the stop bits * @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength * @param LPUARTx LPUART Instance * @param StopBits This parameter can be one of the following values: * @arg @ref LL_LPUART_STOPBITS_1 * @arg @ref LL_LPUART_STOPBITS_2 * @retval None */ __STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits) { MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits); } /** * @brief Retrieve the length of the stop bits * @rmtoll CR2 STOP LL_LPUART_GetStopBitsLength * @param LPUARTx LPUART Instance * @retval Returned value can be one of the following values: * @arg @ref LL_LPUART_STOPBITS_1 * @arg @ref LL_LPUART_STOPBITS_2 */ __STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP)); } /** * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) * @note Call of this function is equivalent to following function call sequence : * - Data Width configuration using @ref LL_LPUART_SetDataWidth() function * - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function * - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function * @rmtoll CR1 PS LL_LPUART_ConfigCharacter\n * CR1 PCE LL_LPUART_ConfigCharacter\n * CR1 M LL_LPUART_ConfigCharacter\n * CR2 STOP LL_LPUART_ConfigCharacter * @param LPUARTx LPUART Instance * @param DataWidth This parameter can be one of the following values: * @arg @ref LL_LPUART_DATAWIDTH_7B * @arg @ref LL_LPUART_DATAWIDTH_8B * @arg @ref LL_LPUART_DATAWIDTH_9B * @param Parity This parameter can be one of the following values: * @arg @ref LL_LPUART_PARITY_NONE * @arg @ref LL_LPUART_PARITY_EVEN * @arg @ref LL_LPUART_PARITY_ODD * @param StopBits This parameter can be one of the following values: * @arg @ref LL_LPUART_STOPBITS_1 * @arg @ref LL_LPUART_STOPBITS_2 * @retval None */ __STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity, uint32_t StopBits) { MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits); } /** * @brief Configure TX/RX pins swapping setting. * @rmtoll CR2 SWAP LL_LPUART_SetTXRXSwap * @param LPUARTx LPUART Instance * @param SwapConfig This parameter can be one of the following values: * @arg @ref LL_LPUART_TXRX_STANDARD * @arg @ref LL_LPUART_TXRX_SWAPPED * @retval None */ __STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig) { MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig); } /** * @brief Retrieve TX/RX pins swapping configuration. * @rmtoll CR2 SWAP LL_LPUART_GetTXRXSwap * @param LPUARTx LPUART Instance * @retval Returned value can be one of the following values: * @arg @ref LL_LPUART_TXRX_STANDARD * @arg @ref LL_LPUART_TXRX_SWAPPED */ __STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP)); } /** * @brief Configure RX pin active level logic * @rmtoll CR2 RXINV LL_LPUART_SetRXPinLevel * @param LPUARTx LPUART Instance * @param PinInvMethod This parameter can be one of the following values: * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED * @retval None */ __STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod) { MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod); } /** * @brief Retrieve RX pin active level logic configuration * @rmtoll CR2 RXINV LL_LPUART_GetRXPinLevel * @param LPUARTx LPUART Instance * @retval Returned value can be one of the following values: * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED */ __STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV)); } /** * @brief Configure TX pin active level logic * @rmtoll CR2 TXINV LL_LPUART_SetTXPinLevel * @param LPUARTx LPUART Instance * @param PinInvMethod This parameter can be one of the following values: * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED * @retval None */ __STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod) { MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod); } /** * @brief Retrieve TX pin active level logic configuration * @rmtoll CR2 TXINV LL_LPUART_GetTXPinLevel * @param LPUARTx LPUART Instance * @retval Returned value can be one of the following values: * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED */ __STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV)); } /** * @brief Configure Binary data logic. * * @note Allow to define how Logical data from the data register are send/received : * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) * @rmtoll CR2 DATAINV LL_LPUART_SetBinaryDataLogic * @param LPUARTx LPUART Instance * @param DataLogic This parameter can be one of the following values: * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE * @retval None */ __STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic) { MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic); } /** * @brief Retrieve Binary data configuration * @rmtoll CR2 DATAINV LL_LPUART_GetBinaryDataLogic * @param LPUARTx LPUART Instance * @retval Returned value can be one of the following values: * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE */ __STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV)); } /** * @brief Configure transfer bit order (either Less or Most Significant Bit First) * @note MSB First means data is transmitted/received with the MSB first, following the start bit. * LSB First means data is transmitted/received with data bit 0 first, following the start bit. * @rmtoll CR2 MSBFIRST LL_LPUART_SetTransferBitOrder * @param LPUARTx LPUART Instance * @param BitOrder This parameter can be one of the following values: * @arg @ref LL_LPUART_BITORDER_LSBFIRST * @arg @ref LL_LPUART_BITORDER_MSBFIRST * @retval None */ __STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder) { MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder); } /** * @brief Return transfer bit order (either Less or Most Significant Bit First) * @note MSB First means data is transmitted/received with the MSB first, following the start bit. * LSB First means data is transmitted/received with data bit 0 first, following the start bit. * @rmtoll CR2 MSBFIRST LL_LPUART_GetTransferBitOrder * @param LPUARTx LPUART Instance * @retval Returned value can be one of the following values: * @arg @ref LL_LPUART_BITORDER_LSBFIRST * @arg @ref LL_LPUART_BITORDER_MSBFIRST */ __STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST)); } /** * @brief Set Address of the LPUART node. * @note This is used in multiprocessor communication during Mute mode or Stop mode, * for wake up with address mark detection. * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7. * (b7-b4 should be set to 0) * 8bits address node is used when 7-bit Address Detection is selected in ADDM7. * (This is used in multiprocessor communication during Mute mode or Stop mode, * for wake up with 7-bit address mark detection. * The MSB of the character sent by the transmitter should be equal to 1. * It may also be used for character detection during normal reception, * Mute mode inactive (for example, end of block detection in ModBus protocol). * In this case, the whole received character (8-bit) is compared to the ADD[7:0] * value and CMF flag is set on match) * @rmtoll CR2 ADD LL_LPUART_ConfigNodeAddress\n * CR2 ADDM7 LL_LPUART_ConfigNodeAddress * @param LPUARTx LPUART Instance * @param AddressLen This parameter can be one of the following values: * @arg @ref LL_LPUART_ADDRESS_DETECT_4B * @arg @ref LL_LPUART_ADDRESS_DETECT_7B * @param NodeAddress 4 or 7 bit Address of the LPUART node. * @retval None */ __STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress) { MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos))); } /** * @brief Return 8 bit Address of the LPUART node as set in ADD field of CR2. * @note If 4-bit Address Detection is selected in ADDM7, * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) * If 7-bit Address Detection is selected in ADDM7, * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) * @rmtoll CR2 ADD LL_LPUART_GetNodeAddress * @param LPUARTx LPUART Instance * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255) */ __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); } /** * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit) * @rmtoll CR2 ADDM7 LL_LPUART_GetNodeAddressLen * @param LPUARTx LPUART Instance * @retval Returned value can be one of the following values: * @arg @ref LL_LPUART_ADDRESS_DETECT_4B * @arg @ref LL_LPUART_ADDRESS_DETECT_7B */ __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7)); } /** * @brief Enable RTS HW Flow Control * @rmtoll CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx) { SET_BIT(LPUARTx->CR3, USART_CR3_RTSE); } /** * @brief Disable RTS HW Flow Control * @rmtoll CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx) { CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE); } /** * @brief Enable CTS HW Flow Control * @rmtoll CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx) { SET_BIT(LPUARTx->CR3, USART_CR3_CTSE); } /** * @brief Disable CTS HW Flow Control * @rmtoll CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx) { CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE); } /** * @brief Configure HW Flow Control mode (both CTS and RTS) * @rmtoll CR3 RTSE LL_LPUART_SetHWFlowCtrl\n * CR3 CTSE LL_LPUART_SetHWFlowCtrl * @param LPUARTx LPUART Instance * @param HardwareFlowControl This parameter can be one of the following values: * @arg @ref LL_LPUART_HWCONTROL_NONE * @arg @ref LL_LPUART_HWCONTROL_RTS * @arg @ref LL_LPUART_HWCONTROL_CTS * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS * @retval None */ __STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl) { MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); } /** * @brief Return HW Flow Control configuration (both CTS and RTS) * @rmtoll CR3 RTSE LL_LPUART_GetHWFlowCtrl\n * CR3 CTSE LL_LPUART_GetHWFlowCtrl * @param LPUARTx LPUART Instance * @retval Returned value can be one of the following values: * @arg @ref LL_LPUART_HWCONTROL_NONE * @arg @ref LL_LPUART_HWCONTROL_RTS * @arg @ref LL_LPUART_HWCONTROL_CTS * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS */ __STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); } /** * @brief Enable Overrun detection * @rmtoll CR3 OVRDIS LL_LPUART_EnableOverrunDetect * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx) { CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS); } /** * @brief Disable Overrun detection * @rmtoll CR3 OVRDIS LL_LPUART_DisableOverrunDetect * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx) { SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS); } /** * @brief Indicate if Overrun detection is enabled * @rmtoll CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); } /** * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits) * @rmtoll CR3 WUS LL_LPUART_SetWKUPType * @param LPUARTx LPUART Instance * @param Type This parameter can be one of the following values: * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT * @arg @ref LL_LPUART_WAKEUP_ON_RXNE * @retval None */ __STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type) { MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type); } /** * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits) * @rmtoll CR3 WUS LL_LPUART_GetWKUPType * @param LPUARTx LPUART Instance * @retval Returned value can be one of the following values: * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT * @arg @ref LL_LPUART_WAKEUP_ON_RXNE */ __STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS)); } /** * @brief Configure LPUART BRR register for achieving expected Baud Rate value. * * @note Compute and set LPUARTDIV value in BRR Register (full BRR content) * according to used Peripheral Clock and expected Baud Rate values * @note Peripheral clock and Baud Rate values provided as function parameters should be valid * (Baud rate value != 0). * @note Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit, * a care should be taken when generating high baud rates using high PeriphClk * values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate]. * @rmtoll BRR BRR LL_LPUART_SetBaudRate * @param LPUARTx LPUART Instance * @param PeriphClk Peripheral Clock @if USART_PRESC_PRESCALER * @param PrescalerValue This parameter can be one of the following values: * @arg @ref LL_LPUART_PRESCALER_DIV1 * @arg @ref LL_LPUART_PRESCALER_DIV2 * @arg @ref LL_LPUART_PRESCALER_DIV4 * @arg @ref LL_LPUART_PRESCALER_DIV6 * @arg @ref LL_LPUART_PRESCALER_DIV8 * @arg @ref LL_LPUART_PRESCALER_DIV10 * @arg @ref LL_LPUART_PRESCALER_DIV12 * @arg @ref LL_LPUART_PRESCALER_DIV16 * @arg @ref LL_LPUART_PRESCALER_DIV32 * @arg @ref LL_LPUART_PRESCALER_DIV64 * @arg @ref LL_LPUART_PRESCALER_DIV128 * @arg @ref LL_LPUART_PRESCALER_DIV256 @endif * @param BaudRate Baud Rate * @retval None */ #if defined(USART_PRESC_PRESCALER) __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t BaudRate) #else __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t BaudRate) #endif /* USART_PRESC_PRESCALER */ { #if defined(USART_PRESC_PRESCALER) if (BaudRate != 0U) { LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate); } #else if (BaudRate != 0U) { LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, BaudRate); } #endif /* USART_PRESC_PRESCALER */ } /** * @brief Return current Baud Rate value, according to LPUARTDIV present in BRR register * (full BRR content), and to used Peripheral Clock values * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. * @rmtoll BRR BRR LL_LPUART_GetBaudRate * @param LPUARTx LPUART Instance * @param PeriphClk Peripheral Clock @if USART_PRESC_PRESCALER * @param PrescalerValue This parameter can be one of the following values: * @arg @ref LL_LPUART_PRESCALER_DIV1 * @arg @ref LL_LPUART_PRESCALER_DIV2 * @arg @ref LL_LPUART_PRESCALER_DIV4 * @arg @ref LL_LPUART_PRESCALER_DIV6 * @arg @ref LL_LPUART_PRESCALER_DIV8 * @arg @ref LL_LPUART_PRESCALER_DIV10 * @arg @ref LL_LPUART_PRESCALER_DIV12 * @arg @ref LL_LPUART_PRESCALER_DIV16 * @arg @ref LL_LPUART_PRESCALER_DIV32 * @arg @ref LL_LPUART_PRESCALER_DIV64 * @arg @ref LL_LPUART_PRESCALER_DIV128 * @arg @ref LL_LPUART_PRESCALER_DIV256 @endif * @retval Baud Rate */ #if defined(USART_PRESC_PRESCALER) __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue) #else __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk) #endif /* USART_PRESC_PRESCALER */ { uint32_t lpuartdiv; uint32_t brrresult; #if defined(USART_PRESC_PRESCALER) uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue])); #endif /* USART_PRESC_PRESCALER */ lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK; if (lpuartdiv >= LPUART_BRR_MIN_VALUE) { #if defined(USART_PRESC_PRESCALER) brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv); #else brrresult = (uint32_t)(((uint64_t)(PeriphClk) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv); #endif /* USART_PRESC_PRESCALER */ } else { brrresult = 0x0UL; } return (brrresult); } /** * @} */ /** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature * @{ */ /** * @brief Enable Single Wire Half-Duplex mode * @rmtoll CR3 HDSEL LL_LPUART_EnableHalfDuplex * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx) { SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL); } /** * @brief Disable Single Wire Half-Duplex mode * @rmtoll CR3 HDSEL LL_LPUART_DisableHalfDuplex * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx) { CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL); } /** * @brief Indicate if Single Wire Half-Duplex mode is enabled * @rmtoll CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); } /** * @} */ /** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature * @{ */ /** * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits). * @rmtoll CR1 DEDT LL_LPUART_SetDEDeassertionTime * @param LPUARTx LPUART Instance * @param Time Value between Min_Data=0 and Max_Data=31 * @retval None */ __STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time) { MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos); } /** * @brief Return DEDT (Driver Enable De-Assertion Time) * @rmtoll CR1 DEDT LL_LPUART_GetDEDeassertionTime * @param LPUARTx LPUART Instance * @retval Time value expressed on 5 bits ([4:0] bits) : c */ __STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); } /** * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). * @rmtoll CR1 DEAT LL_LPUART_SetDEAssertionTime * @param LPUARTx LPUART Instance * @param Time Value between Min_Data=0 and Max_Data=31 * @retval None */ __STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time) { MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); } /** * @brief Return DEAT (Driver Enable Assertion Time) * @rmtoll CR1 DEAT LL_LPUART_GetDEAssertionTime * @param LPUARTx LPUART Instance * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31 */ __STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); } /** * @brief Enable Driver Enable (DE) Mode * @rmtoll CR3 DEM LL_LPUART_EnableDEMode * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx) { SET_BIT(LPUARTx->CR3, USART_CR3_DEM); } /** * @brief Disable Driver Enable (DE) Mode * @rmtoll CR3 DEM LL_LPUART_DisableDEMode * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx) { CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM); } /** * @brief Indicate if Driver Enable (DE) Mode is enabled * @rmtoll CR3 DEM LL_LPUART_IsEnabledDEMode * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); } /** * @brief Select Driver Enable Polarity * @rmtoll CR3 DEP LL_LPUART_SetDESignalPolarity * @param LPUARTx LPUART Instance * @param Polarity This parameter can be one of the following values: * @arg @ref LL_LPUART_DE_POLARITY_HIGH * @arg @ref LL_LPUART_DE_POLARITY_LOW * @retval None */ __STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity) { MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity); } /** * @brief Return Driver Enable Polarity * @rmtoll CR3 DEP LL_LPUART_GetDESignalPolarity * @param LPUARTx LPUART Instance * @retval Returned value can be one of the following values: * @arg @ref LL_LPUART_DE_POLARITY_HIGH * @arg @ref LL_LPUART_DE_POLARITY_LOW */ __STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP)); } /** * @} */ /** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management * @{ */ /** * @brief Check if the LPUART Parity Error Flag is set or not * @rmtoll ISR PE LL_LPUART_IsActiveFlag_PE * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); } /** * @brief Check if the LPUART Framing Error Flag is set or not * @rmtoll ISR FE LL_LPUART_IsActiveFlag_FE * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); } /** * @brief Check if the LPUART Noise error detected Flag is set or not * @rmtoll ISR NE LL_LPUART_IsActiveFlag_NE * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); } /** * @brief Check if the LPUART OverRun Error Flag is set or not * @rmtoll ISR ORE LL_LPUART_IsActiveFlag_ORE * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); } /** * @brief Check if the LPUART IDLE line detected Flag is set or not * @rmtoll ISR IDLE LL_LPUART_IsActiveFlag_IDLE * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); } #if defined(USART_CR1_FIFOEN) #define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not * @rmtoll ISR RXNE_RXFNE LL_LPUART_IsActiveFlag_RXNE_RXFNE * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL); } #else /** * @brief Check if the LPUART Read Data Register Not Empty Flag is set or not * @rmtoll ISR RXNE LL_LPUART_IsActiveFlag_RXNE * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)) ? 1UL : 0UL); } #endif /* USART_CR1_FIFOEN */ /** * @brief Check if the LPUART Transmission Complete Flag is set or not * @rmtoll ISR TC LL_LPUART_IsActiveFlag_TC * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); } #if defined(USART_CR1_FIFOEN) #define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not * @rmtoll ISR TXE_TXFNF LL_LPUART_IsActiveFlag_TXE_TXFNF * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL); } #else /** * @brief Check if the LPUART Transmit Data Register Empty Flag is set or not * @rmtoll ISR TXE LL_LPUART_IsActiveFlag_TXE * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)) ? 1UL : 0UL); } #endif /* USART_CR1_FIFOEN */ /** * @brief Check if the LPUART CTS interrupt Flag is set or not * @rmtoll ISR CTSIF LL_LPUART_IsActiveFlag_nCTS * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); } /** * @brief Check if the LPUART CTS Flag is set or not * @rmtoll ISR CTS LL_LPUART_IsActiveFlag_CTS * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); } /** * @brief Check if the LPUART Busy Flag is set or not * @rmtoll ISR BUSY LL_LPUART_IsActiveFlag_BUSY * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); } /** * @brief Check if the LPUART Character Match Flag is set or not * @rmtoll ISR CMF LL_LPUART_IsActiveFlag_CM * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); } /** * @brief Check if the LPUART Send Break Flag is set or not * @rmtoll ISR SBKF LL_LPUART_IsActiveFlag_SBK * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); } /** * @brief Check if the LPUART Receive Wake Up from mute mode Flag is set or not * @rmtoll ISR RWU LL_LPUART_IsActiveFlag_RWU * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); } /** * @brief Check if the LPUART Wake Up from stop mode Flag is set or not * @rmtoll ISR WUF LL_LPUART_IsActiveFlag_WKUP * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL); } /** * @brief Check if the LPUART Transmit Enable Acknowledge Flag is set or not * @rmtoll ISR TEACK LL_LPUART_IsActiveFlag_TEACK * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); } /** * @brief Check if the LPUART Receive Enable Acknowledge Flag is set or not * @rmtoll ISR REACK LL_LPUART_IsActiveFlag_REACK * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); } #if defined(USART_CR1_FIFOEN) /** * @brief Check if the LPUART TX FIFO Empty Flag is set or not * @rmtoll ISR TXFE LL_LPUART_IsActiveFlag_TXFE * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL); } /** * @brief Check if the LPUART RX FIFO Full Flag is set or not * @rmtoll ISR RXFF LL_LPUART_IsActiveFlag_RXFF * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL); } /** * @brief Check if the LPUART TX FIFO Threshold Flag is set or not * @rmtoll ISR TXFT LL_LPUART_IsActiveFlag_TXFT * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL); } /** * @brief Check if the LPUART RX FIFO Threshold Flag is set or not * @rmtoll ISR RXFT LL_LPUART_IsActiveFlag_RXFT * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL); } #endif /* USART_CR1_FIFOEN */ /** * @brief Clear Parity Error Flag * @rmtoll ICR PECF LL_LPUART_ClearFlag_PE * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx) { WRITE_REG(LPUARTx->ICR, USART_ICR_PECF); } /** * @brief Clear Framing Error Flag * @rmtoll ICR FECF LL_LPUART_ClearFlag_FE * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx) { WRITE_REG(LPUARTx->ICR, USART_ICR_FECF); } /** * @brief Clear Noise detected Flag * @rmtoll ICR NECF LL_LPUART_ClearFlag_NE * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx) { WRITE_REG(LPUARTx->ICR, USART_ICR_NECF); } /** * @brief Clear OverRun Error Flag * @rmtoll ICR ORECF LL_LPUART_ClearFlag_ORE * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx) { WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF); } /** * @brief Clear IDLE line detected Flag * @rmtoll ICR IDLECF LL_LPUART_ClearFlag_IDLE * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx) { WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF); } /** * @brief Clear Transmission Complete Flag * @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx) { WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF); } /** * @brief Clear CTS Interrupt Flag * @rmtoll ICR CTSCF LL_LPUART_ClearFlag_nCTS * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx) { WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF); } /** * @brief Clear Character Match Flag * @rmtoll ICR CMCF LL_LPUART_ClearFlag_CM * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx) { WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF); } /** * @brief Clear Wake Up from stop mode Flag * @rmtoll ICR WUCF LL_LPUART_ClearFlag_WKUP * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx) { WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF); } /** * @} */ /** @defgroup LPUART_LL_EF_IT_Management IT_Management * @{ */ /** * @brief Enable IDLE Interrupt * @rmtoll CR1 IDLEIE LL_LPUART_EnableIT_IDLE * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx) { ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); } #if defined(USART_CR1_FIFOEN) #define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_EnableIT_RXNE_RXFNE * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) { ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); } #else /** * @brief Enable RX Not Empty Interrupt * @rmtoll CR1 RXNEIE LL_LPUART_EnableIT_RXNE * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_EnableIT_RXNE(USART_TypeDef *LPUARTx) { ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE); } #endif /* USART_CR1_FIFOEN */ /** * @brief Enable Transmission Complete Interrupt * @rmtoll CR1 TCIE LL_LPUART_EnableIT_TC * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx) { ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE); } #if defined(USART_CR1_FIFOEN) #define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Enable TX Empty and TX FIFO Not Full Interrupt * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_EnableIT_TXE_TXFNF * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) { ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); } #else /** * @brief Enable TX Empty Interrupt * @rmtoll CR1 TXEIE LL_LPUART_EnableIT_TXE * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_EnableIT_TXE(USART_TypeDef *LPUARTx) { ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE); } #endif /* USART_CR1_FIFOEN */ /** * @brief Enable Parity Error Interrupt * @rmtoll CR1 PEIE LL_LPUART_EnableIT_PE * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx) { ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE); } /** * @brief Enable Character Match Interrupt * @rmtoll CR1 CMIE LL_LPUART_EnableIT_CM * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx) { ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE); } #if defined(USART_CR1_FIFOEN) /** * @brief Enable TX FIFO Empty Interrupt * @rmtoll CR1 TXFEIE LL_LPUART_EnableIT_TXFE * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx) { ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); } /** * @brief Enable RX FIFO Full Interrupt * @rmtoll CR1 RXFFIE LL_LPUART_EnableIT_RXFF * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx) { ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); } #endif /* USART_CR1_FIFOEN */ /** * @brief Enable Error Interrupt * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register). * - 0: Interrupt is inhibited * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register. * @rmtoll CR3 EIE LL_LPUART_EnableIT_ERROR * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx) { ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE); } /** * @brief Enable CTS Interrupt * @rmtoll CR3 CTSIE LL_LPUART_EnableIT_CTS * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx) { ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE); } /** * @brief Enable Wake Up from Stop Mode Interrupt * @rmtoll CR3 WUFIE LL_LPUART_EnableIT_WKUP * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx) { ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE); } #if defined(USART_CR1_FIFOEN) /** * @brief Enable TX FIFO Threshold Interrupt * @rmtoll CR3 TXFTIE LL_LPUART_EnableIT_TXFT * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx) { ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); } /** * @brief Enable RX FIFO Threshold Interrupt * @rmtoll CR3 RXFTIE LL_LPUART_EnableIT_RXFT * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx) { ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); } #endif /* USART_CR1_FIFOEN */ /** * @brief Disable IDLE Interrupt * @rmtoll CR1 IDLEIE LL_LPUART_DisableIT_IDLE * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx) { ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); } #if defined(USART_CR1_FIFOEN) #define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_DisableIT_RXNE_RXFNE * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) { ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); } #else /** * @brief Disable RX Not Empty Interrupt * @rmtoll CR1 RXNEIE LL_LPUART_DisableIT_RXNE * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_DisableIT_RXNE(USART_TypeDef *LPUARTx) { ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE); } #endif /* USART_CR1_FIFOEN */ /** * @brief Disable Transmission Complete Interrupt * @rmtoll CR1 TCIE LL_LPUART_DisableIT_TC * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx) { ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE); } #if defined(USART_CR1_FIFOEN) #define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Disable TX Empty and TX FIFO Not Full Interrupt * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_DisableIT_TXE_TXFNF * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) { ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); } #else /** * @brief Disable TX Empty Interrupt * @rmtoll CR1 TXEIE LL_LPUART_DisableIT_TXE * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_DisableIT_TXE(USART_TypeDef *LPUARTx) { ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE); } #endif /* USART_CR1_FIFOEN */ /** * @brief Disable Parity Error Interrupt * @rmtoll CR1 PEIE LL_LPUART_DisableIT_PE * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx) { ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE); } /** * @brief Disable Character Match Interrupt * @rmtoll CR1 CMIE LL_LPUART_DisableIT_CM * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx) { ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE); } #if defined(USART_CR1_FIFOEN) /** * @brief Disable TX FIFO Empty Interrupt * @rmtoll CR1 TXFEIE LL_LPUART_DisableIT_TXFE * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx) { ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); } /** * @brief Disable RX FIFO Full Interrupt * @rmtoll CR1 RXFFIE LL_LPUART_DisableIT_RXFF * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx) { ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); } #endif /* USART_CR1_FIFOEN */ /** * @brief Disable Error Interrupt * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register). * - 0: Interrupt is inhibited * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register. * @rmtoll CR3 EIE LL_LPUART_DisableIT_ERROR * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx) { ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE); } /** * @brief Disable CTS Interrupt * @rmtoll CR3 CTSIE LL_LPUART_DisableIT_CTS * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx) { ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE); } /** * @brief Disable Wake Up from Stop Mode Interrupt * @rmtoll CR3 WUFIE LL_LPUART_DisableIT_WKUP * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx) { ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE); } #if defined(USART_CR1_FIFOEN) /** * @brief Disable TX FIFO Threshold Interrupt * @rmtoll CR3 TXFTIE LL_LPUART_DisableIT_TXFT * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx) { ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); } /** * @brief Disable RX FIFO Threshold Interrupt * @rmtoll CR3 RXFTIE LL_LPUART_DisableIT_RXFT * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx) { ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); } #endif /* USART_CR1_FIFOEN */ /** * @brief Check if the LPUART IDLE Interrupt source is enabled or disabled. * @rmtoll CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); } #if defined(USART_CR1_FIFOEN) #define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled. * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_IsEnabledIT_RXNE_RXFNE * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL); } #else /** * @brief Check if the LPUART RX Not Empty Interrupt is enabled or disabled. * @rmtoll CR1 RXNEIE LL_LPUART_IsEnabledIT_RXNE * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)) ? 1UL : 0UL); } #endif /* USART_CR1_FIFOEN */ /** * @brief Check if the LPUART Transmission Complete Interrupt is enabled or disabled. * @rmtoll CR1 TCIE LL_LPUART_IsEnabledIT_TC * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); } #if defined(USART_CR1_FIFOEN) #define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_IsEnabledIT_TXE_TXFNF * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL); } #else /** * @brief Check if the LPUART TX Empty Interrupt is enabled or disabled. * @rmtoll CR1 TXEIE LL_LPUART_IsEnabledIT_TXE * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)) ? 1UL : 0UL); } #endif /* USART_CR1_FIFOEN */ /** * @brief Check if the LPUART Parity Error Interrupt is enabled or disabled. * @rmtoll CR1 PEIE LL_LPUART_IsEnabledIT_PE * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); } /** * @brief Check if the LPUART Character Match Interrupt is enabled or disabled. * @rmtoll CR1 CMIE LL_LPUART_IsEnabledIT_CM * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); } #if defined(USART_CR1_FIFOEN) /** * @brief Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled * @rmtoll CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL); } /** * @brief Check if the LPUART RX FIFO Full Interrupt is enabled or disabled * @rmtoll CR1 RXFFIE LL_LPUART_IsEnabledIT_RXFF * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL); } #endif /* USART_CR1_FIFOEN */ /** * @brief Check if the LPUART Error Interrupt is enabled or disabled. * @rmtoll CR3 EIE LL_LPUART_IsEnabledIT_ERROR * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); } /** * @brief Check if the LPUART CTS Interrupt is enabled or disabled. * @rmtoll CR3 CTSIE LL_LPUART_IsEnabledIT_CTS * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); } /** * @brief Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled. * @rmtoll CR3 WUFIE LL_LPUART_IsEnabledIT_WKUP * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL); } #if defined(USART_CR1_FIFOEN) /** * @brief Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled * @rmtoll CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL); } /** * @brief Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled * @rmtoll CR3 RXFTIE LL_LPUART_IsEnabledIT_RXFT * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL); } #endif /* USART_CR1_FIFOEN */ /** * @} */ /** @defgroup LPUART_LL_EF_DMA_Management DMA_Management * @{ */ /** * @brief Enable DMA Mode for reception * @rmtoll CR3 DMAR LL_LPUART_EnableDMAReq_RX * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx) { ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR); } /** * @brief Disable DMA Mode for reception * @rmtoll CR3 DMAR LL_LPUART_DisableDMAReq_RX * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx) { ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR); } /** * @brief Check if DMA Mode is enabled for reception * @rmtoll CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); } /** * @brief Enable DMA Mode for transmission * @rmtoll CR3 DMAT LL_LPUART_EnableDMAReq_TX * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx) { ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT); } /** * @brief Disable DMA Mode for transmission * @rmtoll CR3 DMAT LL_LPUART_DisableDMAReq_TX * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx) { ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT); } /** * @brief Check if DMA Mode is enabled for transmission * @rmtoll CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); } /** * @brief Enable DMA Disabling on Reception Error * @rmtoll CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx) { SET_BIT(LPUARTx->CR3, USART_CR3_DDRE); } /** * @brief Disable DMA Disabling on Reception Error * @rmtoll CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx) { CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE); } /** * @brief Indicate if DMA Disabling on Reception Error is disabled * @rmtoll CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); } /** * @brief Get the LPUART data register address used for DMA transfer * @rmtoll RDR RDR LL_LPUART_DMA_GetRegAddr\n * @rmtoll TDR TDR LL_LPUART_DMA_GetRegAddr * @param LPUARTx LPUART Instance * @param Direction This parameter can be one of the following values: * @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT * @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE * @retval Address of data register */ __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(const USART_TypeDef *LPUARTx, uint32_t Direction) { uint32_t data_reg_addr; if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT) { /* return address of TDR register */ data_reg_addr = (uint32_t) &(LPUARTx->TDR); } else { /* return address of RDR register */ data_reg_addr = (uint32_t) &(LPUARTx->RDR); } return data_reg_addr; } /** * @} */ /** @defgroup LPUART_LL_EF_Data_Management Data_Management * @{ */ /** * @brief Read Receiver Data register (Receive Data value, 8 bits) * @rmtoll RDR RDR LL_LPUART_ReceiveData8 * @param LPUARTx LPUART Instance * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF */ __STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(const USART_TypeDef *LPUARTx) { return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU); } /** * @brief Read Receiver Data register (Receive Data value, 9 bits) * @rmtoll RDR RDR LL_LPUART_ReceiveData9 * @param LPUARTx LPUART Instance * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF */ __STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(const USART_TypeDef *LPUARTx) { return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR)); } /** * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) * @rmtoll TDR TDR LL_LPUART_TransmitData8 * @param LPUARTx LPUART Instance * @param Value between Min_Data=0x00 and Max_Data=0xFF * @retval None */ __STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value) { LPUARTx->TDR = Value; } /** * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits) * @rmtoll TDR TDR LL_LPUART_TransmitData9 * @param LPUARTx LPUART Instance * @param Value between Min_Data=0x00 and Max_Data=0x1FF * @retval None */ __STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value) { LPUARTx->TDR = Value & 0x1FFUL; } /** * @} */ /** @defgroup LPUART_LL_EF_Execution Execution * @{ */ /** * @brief Request Break sending * @rmtoll RQR SBKRQ LL_LPUART_RequestBreakSending * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx) { SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ); } /** * @brief Put LPUART in mute mode and set the RWU flag * @rmtoll RQR MMRQ LL_LPUART_RequestEnterMuteMode * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx) { SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ); } /** @if USART_CR1_FIFOEN * @brief Request a Receive Data and FIFO flush * @note Allows to discard the received data without reading them, and avoid an overrun * condition. @else * @brief Request a Receive Data flush @endif * @rmtoll RQR RXFRQ LL_LPUART_RequestRxDataFlush * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx) { SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ); } #if defined(USART_CR1_FIFOEN) /** * @brief Request a Transmit data FIFO flush * @note TXFRQ bit is set to flush the whole FIFO when FIFO mode is enabled. This * also sets the flag TXFE (TXFIFO empty bit in the LPUART_ISR register). * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll RQR TXFRQ LL_LPUART_RequestTxDataFlush * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_RequestTxDataFlush(USART_TypeDef *LPUARTx) { SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_TXFRQ); } #endif /* USART_CR1_FIFOEN */ /** * @} */ #if defined(USE_FULL_LL_DRIVER) /** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions * @{ */ ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx); ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct); void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct); /** * @} */ #endif /* USE_FULL_LL_DRIVER */ /** * @} */ /** * @} */ #endif /* LPUART1 */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32L4xx_LL_LPUART_H */
New file Diff too large Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c
New file Diff too large Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c
New file @@ -0,0 +1,1098 @@ /** ****************************************************************************** * @file stm32l4xx_hal_uart_ex.c * @author MCD Application Team * @brief Extended UART HAL module driver. * This file provides firmware functions to manage the following extended * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). * + Initialization and de-initialization functions * + Peripheral Control functions * * ****************************************************************************** * @attention * * Copyright (c) 2017 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** @verbatim ============================================================================== ##### UART peripheral extended features ##### ============================================================================== (#) Declare a UART_HandleTypeDef handle structure. (#) For the UART RS485 Driver Enable mode, initialize the UART registers by calling the HAL_RS485Ex_Init() API. (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming. -@- When UART operates in FIFO mode, FIFO mode must be enabled prior starting RX/TX transfers. Also RX/TX FIFO thresholds must be configured prior starting RX/TX transfers. @endverbatim ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" /** @addtogroup STM32L4xx_HAL_Driver * @{ */ /** @defgroup UARTEx UARTEx * @brief UART Extended HAL module driver * @{ */ #ifdef HAL_UART_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) /** @defgroup UARTEX_Private_Constants UARTEx Private Constants * @{ */ /* UART RX FIFO depth */ #define RX_FIFO_DEPTH 8U /* UART TX FIFO depth */ #define TX_FIFO_DEPTH 8U /** * @} */ #endif /* USART_CR1_FIFOEN */ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup UARTEx_Private_Functions UARTEx Private Functions * @{ */ static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); #if defined(USART_CR1_FIFOEN) static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart); #endif /* USART_CR1_FIFOEN */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions * @{ */ /** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Extended Initialization and Configuration Functions * @verbatim =============================================================================== ##### Initialization and Configuration functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to initialize the USARTx or the UARTy in asynchronous mode. (+) For the asynchronous mode the parameters below can be configured: (++) Baud Rate (++) Word Length (++) Stop Bit (++) Parity: If the parity is enabled, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit. (++) Hardware flow control (++) Receiver/transmitter modes (++) Over Sampling Method (++) One-Bit Sampling Method (+) For the asynchronous mode, the following advanced features can be configured as well: (++) TX and/or RX pin level inversion (++) data logical level inversion (++) RX and TX pins swap (++) RX overrun detection disabling (++) DMA disabling on RX error (++) MSB first on communication line (++) auto Baud rate detection [..] The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration procedures (details for the procedures are available in reference manual). @endverbatim Depending on the frame length defined by the M1 and M0 bits (7-bit, 8-bit or 9-bit), the possible UART formats are listed in the following table. Table 1. UART frame format. +-----------------------------------------------------------------------+ | M1 bit | M0 bit | PCE bit | UART frame | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 0 | | SB | 8 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 0 | | SB | 9 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 0 | | SB | 7 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | +-----------------------------------------------------------------------+ * @{ */ /** * @brief Initialize the RS485 Driver enable feature according to the specified * parameters in the UART_InitTypeDef and creates the associated handle. * @param huart UART handle. * @param Polarity Select the driver enable polarity. * This parameter can be one of the following values: * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high * @arg @ref UART_DE_POLARITY_LOW DE signal is active low * @param AssertionTime Driver Enable assertion time: * 5-bit value defining the time between the activation of the DE (Driver Enable) * signal and the beginning of the start bit. It is expressed in sample time * units (1/8 or 1/16 bit time, depending on the oversampling rate) * @param DeassertionTime Driver Enable deassertion time: * 5-bit value defining the time between the end of the last stop bit, in a * transmitted message, and the de-activation of the DE (Driver Enable) signal. * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the * oversampling rate). * @retval HAL status */ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime) { uint32_t temp; /* Check the UART handle allocation */ if (huart == NULL) { return HAL_ERROR; } /* Check the Driver Enable UART instance */ assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance)); /* Check the Driver Enable polarity */ assert_param(IS_UART_DE_POLARITY(Polarity)); /* Check the Driver Enable assertion time */ assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); /* Check the Driver Enable deassertion time */ assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); if (huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) UART_InitCallbacksToDefault(huart); if (huart->MspInitCallback == NULL) { huart->MspInitCallback = HAL_UART_MspInit; } /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK, CORTEX */ HAL_UART_MspInit(huart); #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); /* Perform advanced settings configuration */ /* For some items, configuration requires to be done prior TE and RE bits are set */ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { UART_AdvFeatureConfig(huart); } /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { return HAL_ERROR; } /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_DEM); /* Set the Driver Enable polarity */ MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); /* Set the Driver Enable assertion and deassertion times */ temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } /** * @} */ /** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions * @brief Extended functions * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== This subsection provides a set of Wakeup and FIFO mode related callback functions. (#) Wakeup from Stop mode Callback: (+) HAL_UARTEx_WakeupCallback() (#) TX/RX Fifos Callbacks: (+) HAL_UARTEx_RxFifoFullCallback() (+) HAL_UARTEx_TxFifoEmptyCallback() @endverbatim * @{ */ /** * @brief UART wakeup from Stop mode callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_WakeupCallback can be implemented in the user file. */ } #if defined(USART_CR1_FIFOEN) /** * @brief UART RX Fifo full callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. */ } /** * @brief UART TX Fifo empty callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. */ } #endif /* USART_CR1_FIFOEN */ /** * @} */ /** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions * @brief Extended Peripheral Control functions * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== [..] This section provides the following functions: (+) HAL_UARTEx_EnableClockStopMode() API enables the UART clock (HSI or LSE only) during stop mode (+) HAL_UARTEx_DisableClockStopMode() API disables the above functionality (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address detection length to more than 4 bits for multiprocessor address mark wake up. (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode trigger: address match, Start Bit detection or RXNE bit status. (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode (+) HAL_UARTEx_DisableStopMode() API disables the above functionality (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold [..] This subsection also provides a set of additional functions providing enhanced reception services to user. (For example, these functions allow application to handle use cases where number of data to be received is unknown). (#) Compared to standard reception services which only consider number of received data elements as reception completion criteria, these functions also consider additional events as triggers for updating reception status to caller : (+) Detection of inactivity period (RX line has not been active for a given period). (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) for 1 frame time, after last received byte. (++) RX inactivity detected by RTO, i.e. line has been in idle state for a programmable time, after last received byte. (+) Detection that a specific character has been received. (#) There are two mode of transfer: (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, or till IDLE event occurs. Reception is handled only during function execution. When function exits, no data reception could occur. HAL status and number of actually received data elements, are returned by function after finishing transfer. (+) Non-Blocking mode: The reception is performed using Interrupts or DMA. These API's return the HAL status. The end of the data processing will be indicated through the dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected. (#) Blocking mode API: (+) HAL_UARTEx_ReceiveToIdle() (#) Non-Blocking mode API with Interrupt: (+) HAL_UARTEx_ReceiveToIdle_IT() (#) Non-Blocking mode API with DMA: (+) HAL_UARTEx_ReceiveToIdle_DMA() @endverbatim * @{ */ #if defined(USART_CR3_UCESM) /** * @brief Keep UART Clock enabled when in Stop Mode. * @note When the USART clock source is configured to be LSE or HSI, it is possible to keep enabled * this clock during STOP mode by setting the UCESM bit in USART_CR3 control register. * @note When LPUART is used to wakeup from stop with LSE is selected as LPUART clock source, * and desired baud rate is 9600 baud, the bit UCESM bit in LPUART_CR3 control register must be set. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); /* Set UCESM bit */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_UCESM); /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; } /** * @brief Disable UART Clock when in Stop Mode. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); /* Clear UCESM bit */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_UCESM); /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; } #endif /* USART_CR3_UCESM */ /** * @brief By default in multiprocessor mode, when the wake up method is set * to address mark, the UART handles only 4-bit long addresses detection; * this API allows to enable longer addresses detection (6-, 7- or 8-bit * long). * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. * @param huart UART handle. * @param AddressLength This parameter can be one of the following values: * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address * @retval HAL status */ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength) { /* Check the UART handle allocation */ if (huart == NULL) { return HAL_ERROR; } /* Check the address length parameter */ assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); huart->gState = HAL_UART_STATE_BUSY; /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); /* Set the address length */ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); /* TEACK and/or REACK to check before moving huart->gState to Ready */ return (UART_CheckIdleState(huart)); } /** * @brief Set Wakeup from Stop mode interrupt flag selection. * @note It is the application responsibility to enable the interrupt used as * usart_wkup interrupt source before entering low-power mode. * @param huart UART handle. * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status. * This parameter can be one of the following values: * @arg @ref UART_WAKEUP_ON_ADDRESS * @arg @ref UART_WAKEUP_ON_STARTBIT * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) { HAL_StatusTypeDef status = HAL_OK; uint32_t tickstart; /* check the wake-up from stop mode UART instance */ assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); /* check the wake-up selection parameter */ assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); /* Set the wake-up selection scheme */ MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent); if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) { UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection); } /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) { status = HAL_TIMEOUT; } else { /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; } /* Process Unlocked */ __HAL_UNLOCK(huart); return status; } /** * @brief Enable UART Stop Mode. * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); /* Set UESM bit */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM); /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; } /** * @brief Disable UART Stop Mode. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); /* Clear UESM bit */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; } #if defined(USART_CR1_FIFOEN) /** * @brief Enable the FIFO mode. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart) { uint32_t tmpcr1; /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); /* Disable UART */ __HAL_UART_DISABLE(huart); /* Enable FIFO mode */ SET_BIT(tmpcr1, USART_CR1_FIFOEN); huart->FifoMode = UART_FIFOMODE_ENABLE; /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); huart->gState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; } /** * @brief Disable the FIFO mode. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) { uint32_t tmpcr1; /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); /* Disable UART */ __HAL_UART_DISABLE(huart); /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); huart->FifoMode = UART_FIFOMODE_DISABLE; /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); huart->gState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; } /** * @brief Set the TXFIFO threshold. * @param huart UART handle. * @param Threshold TX FIFO threshold value * This parameter can be one of the following values: * @arg @ref UART_TXFIFO_THRESHOLD_1_8 * @arg @ref UART_TXFIFO_THRESHOLD_1_4 * @arg @ref UART_TXFIFO_THRESHOLD_1_2 * @arg @ref UART_TXFIFO_THRESHOLD_3_4 * @arg @ref UART_TXFIFO_THRESHOLD_7_8 * @arg @ref UART_TXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { uint32_t tmpcr1; /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); /* Disable UART */ __HAL_UART_DISABLE(huart); /* Update TX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); huart->gState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; } /** * @brief Set the RXFIFO threshold. * @param huart UART handle. * @param Threshold RX FIFO threshold value * This parameter can be one of the following values: * @arg @ref UART_RXFIFO_THRESHOLD_1_8 * @arg @ref UART_RXFIFO_THRESHOLD_1_4 * @arg @ref UART_RXFIFO_THRESHOLD_1_2 * @arg @ref UART_RXFIFO_THRESHOLD_3_4 * @arg @ref UART_RXFIFO_THRESHOLD_7_8 * @arg @ref UART_RXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { uint32_t tmpcr1; /* Check the parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); /* Disable UART */ __HAL_UART_DISABLE(huart); /* Update RX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); huart->gState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; } #endif /* USART_CR1_FIFOEN */ /** * @brief Receive an amount of data in blocking mode till either the expected number of data * is received or an IDLE event occurs. * @note HAL_OK is returned if reception is completed (expected number of data has been received) * or if reception is stopped after IDLE event (less than the expected number of data has been received) * In this case, RxLen output parameter indicates number of data available in reception buffer. * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the received data is handled as a set of uint16_t. In this case, Size must indicate the number * of uint16_t available through pData. * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO * is not empty. Read operations from the RDR register are performed when * RXFNE flag is set. From hardware perspective, RXFNE flag and * RXNE are mapped on the same bit-field. * @param huart UART handle. * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. * @param RxLen Number of data elements finally received * (could be lower than Size, in case reception ends on IDLE event) * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence). * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout) { uint8_t *pdata8bits; uint16_t *pdata16bits; uint16_t uhMask; uint32_t tickstart; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) { if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; huart->RxEventType = HAL_UART_RXEVENT_TC; /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); huart->RxXferSize = Size; huart->RxXferCount = Size; /* Computation of UART mask to apply to RDR register */ UART_MASK_COMPUTATION(huart); uhMask = huart->Mask; /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { pdata8bits = NULL; pdata16bits = (uint16_t *) pData; } else { pdata8bits = pData; pdata16bits = NULL; } /* Initialize output number of received elements */ *RxLen = 0U; /* as long as data have to be received */ while (huart->RxXferCount > 0U) { /* Check if IDLE flag is set */ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) { /* Clear IDLE flag in ISR */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); /* If Set, but no data ever received, clear flag without exiting loop */ /* If Set, and data has already been received, this means Idle Event is valid : End reception */ if (*RxLen > 0U) { huart->RxEventType = HAL_UART_RXEVENT_IDLE; huart->RxState = HAL_UART_STATE_READY; return HAL_OK; } } /* Check if RXNE flag is set */ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE)) { if (pdata8bits == NULL) { *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); pdata16bits++; } else { *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); pdata8bits++; } /* Increment number of received elements */ *RxLen += 1U; huart->RxXferCount--; } /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { huart->RxState = HAL_UART_STATE_READY; return HAL_TIMEOUT; } } } /* Set number of received elements in output parameter : RxLen */ *RxLen = huart->RxXferSize - huart->RxXferCount; /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; return HAL_OK; } else { return HAL_BUSY; } } /** * @brief Receive an amount of data in interrupt mode till either the expected number of data * is received or an IDLE event occurs. * @note Reception is initiated by this function call. Further progress of reception is achieved thanks * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating * number of received data elements. * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the received data is handled as a set of uint16_t. In this case, Size must indicate the number * of uint16_t available through pData. * @param huart UART handle. * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef status = HAL_OK; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) { if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; huart->RxEventType = HAL_UART_RXEVENT_TC; (void)UART_Start_Receive_IT(huart, pData, Size); if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); } else { /* In case of errors already pending when reception is started, Interrupts may have already been raised and lead to reception abortion. (Overrun error for instance). In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ status = HAL_ERROR; } return status; } else { return HAL_BUSY; } } /** * @brief Receive an amount of data in DMA mode till either the expected number * of data is received or an IDLE event occurs. * @note Reception is initiated by this function call. Further progress of reception is achieved thanks * to DMA services, transferring automatically received data elements in user reception buffer and * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider * reception phase as ended. In all cases, callback execution will indicate number of received data elements. * @note When the UART parity is enabled (PCE = 1), the received data contain * the parity bit (MSB position). * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the received data is handled as a set of uint16_t. In this case, Size must indicate the number * of uint16_t available through pData. * @param huart UART handle. * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef status; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) { if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; huart->RxEventType = HAL_UART_RXEVENT_TC; status = UART_Start_Receive_DMA(huart, pData, Size); /* Check Rx process has been successfully started */ if (status == HAL_OK) { if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); } else { /* In case of errors already pending when reception is started, Interrupts may have already been raised and lead to reception abortion. (Overrun error for instance). In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ status = HAL_ERROR; } } return status; } else { return HAL_BUSY; } } /** * @brief Provide Rx Event type that has lead to RxEvent callback execution. * @note When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress * of reception process is provided to application through calls of Rx Event callback (either default one * HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event, * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead * to Rx Event callback execution. * @note This function is expected to be called within the user implementation of Rx Event Callback, * in order to provide the accurate value : * In Interrupt Mode : * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of * received data is lower than expected one) * In DMA Mode : * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of * received data is lower than expected one). * In DMA mode, RxEvent callback could be called several times; * When DMA is configured in Normal Mode, HT event does not stop Reception process; * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process; * @param huart UART handle. * @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values) */ HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart) { /* Return Rx Event type value, as stored in UART handle */ return (huart->RxEventType); } /** * @} */ /** * @} */ /** @addtogroup UARTEx_Private_Functions * @{ */ /** * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection. * @param huart UART handle. * @param WakeUpSelection UART wake up from stop mode parameters. * @retval None */ static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) { assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength)); /* Set the USART address length */ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); /* Set the USART address node */ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS)); } #if defined(USART_CR1_FIFOEN) /** * @brief Calculate the number of data to process in RX/TX ISR. * @note The RX FIFO depth and the TX FIFO depth is extracted from * the UART configuration registers. * @param huart UART handle. * @retval None */ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) { uint8_t rx_fifo_depth; uint8_t tx_fifo_depth; uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (huart->FifoMode == UART_FIFOMODE_DISABLE) { huart->NbTxDataToProcess = 1U; huart->NbRxDataToProcess = 1U; } else { rx_fifo_depth = RX_FIFO_DEPTH; tx_fifo_depth = TX_FIFO_DEPTH; rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; } } #endif /* USART_CR1_FIFOEN */ /** * @} */ #endif /* HAL_UART_MODULE_ENABLED */ /** * @} */ /** * @} */
@@ -10,20 +10,23 @@ Mcu.IP0=NVIC Mcu.IP1=RCC Mcu.IP2=SYS Mcu.IPNb=3 Mcu.IP3=USART1 Mcu.IPNb=4 Mcu.Name=STM32L431R(B-C)Tx Mcu.Package=LQFP64 Mcu.Pin0=PH0-OSC_IN (PH0) Mcu.Pin1=PH1-OSC_OUT (PH1) Mcu.Pin10=PD2 Mcu.Pin11=VP_SYS_VS_Systick Mcu.Pin2=PB2 Mcu.Pin3=PB12 Mcu.Pin4=PB13 Mcu.Pin5=PB14 Mcu.Pin6=PC6 Mcu.Pin7=PC9 Mcu.Pin8=PD2 Mcu.Pin9=VP_SYS_VS_Systick Mcu.PinsNb=10 Mcu.Pin8=PA9 Mcu.Pin9=PA10 Mcu.PinsNb=12 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32L431RCTx @@ -41,6 +44,10 @@ NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.SysTick_IRQn=true\:1\:0\:true\:false\:true\:false\:true\:false NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false PA10.Mode=Asynchronous PA10.Signal=USART1_RX PA9.Mode=Asynchronous PA9.Signal=USART1_TX PB12.GPIOParameters=GPIO_Label,GPIO_ModeDefaultEXTI PB12.GPIO_Label=Key1 PB12.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING @@ -106,7 +113,7 @@ ProjectManager.UAScriptAfterPath= ProjectManager.UAScriptBeforePath= ProjectManager.UnderRoot=true ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_USART1_UART_Init-USART1-false-HAL-true RCC.ADCFreq_Value=32000000 RCC.AHBFreq_Value=80000000 RCC.APB1Freq_Value=80000000 @@ -159,6 +166,8 @@ SH.GPXTI13.ConfNb=1 SH.GPXTI14.0=GPIO_EXTI14 SH.GPXTI14.ConfNb=1 USART1.IPParameters=VirtualMode-Asynchronous USART1.VirtualMode-Asynchronous=VM_ASYNC VP_SYS_VS_Systick.Mode=SysTick VP_SYS_VS_Systick.Signal=SYS_VS_Systick board=custom
