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src/ISKv1/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h
New file @@ -0,0 +1,1004 @@ /** ****************************************************************************** * @file stm32f1xx_hal_adc.h * @author MCD Application Team * @brief Header file containing functions prototypes of ADC HAL library. ****************************************************************************** * @attention * * * <h2><center>© Copyright (c) 2016 STMicroelectronics. * All rights reserved.</center></h2> * * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_ADC_H #define __STM32F1xx_HAL_ADC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @addtogroup ADC * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup ADC_Exported_Types ADC Exported Types * @{ */ /** * @brief Structure definition of ADC and regular group initialization * @note Parameters of this structure are shared within 2 scopes: * - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode. * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv. * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. * ADC can be either disabled or enabled without conversion on going on regular group. */ typedef struct { uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting) or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3). This parameter can be a value of @ref ADC_Data_align */ uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). Scan direction is upward: from rank1 to rank 'n'. This parameter can be a value of @ref ADC_Scan_mode Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1) or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the the last conversion of the sequence. All previous conversions would be overwritten by the last one. Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */ FunctionalState ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, after the selected trigger occurred (software start or external trigger). This parameter can be set to ENABLE or DISABLE. */ uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 16. */ FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE or DISABLE. */ uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. If set to ADC_SOFTWARE_START, external triggers are disabled. If set to external trigger source, triggering is on event rising edge. This parameter can be a value of @ref ADC_External_trigger_source_Regular */ }ADC_InitTypeDef; /** * @brief Structure definition of ADC channel for regular group * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. * ADC can be either disabled or enabled without conversion on going on regular group. */ typedef struct { uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. This parameter can be a value of @ref ADC_channels Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor) Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger. It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel. Refer to errata sheet of these devices for more details. */ uint32_t Rank; /*!< Specifies the rank in the regular group sequencer This parameter can be a value of @ref ADC_regular_rank Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits). This parameter can be a value of @ref ADC_sampling_times Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. Note: In case of usage of internal measurement channels (VrefInt/TempSensor), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */ }ADC_ChannelConfTypeDef; /** * @brief ADC Configuration analog watchdog definition * @note The setting of these parameters with function is conditioned to ADC state. * ADC state can be either disabled or enabled without conversion on going on regular and injected groups. */ typedef struct { uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group. This parameter can be a value of @ref ADC_analog_watchdog_mode. */ uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog. This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode) This parameter can be a value of @ref ADC_channels. */ FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode. This parameter can be set to ENABLE or DISABLE */ uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ }ADC_AnalogWDGConfTypeDef; /** * @brief HAL ADC state machine: ADC states definition (bitfields) */ /* States of ADC global scope */ #define HAL_ADC_STATE_RESET 0x00000000U /*!< ADC not yet initialized or disabled */ #define HAL_ADC_STATE_READY 0x00000001U /*!< ADC peripheral ready for use */ #define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /*!< ADC is busy to internal process (initialization, calibration) */ #define HAL_ADC_STATE_TIMEOUT 0x00000004U /*!< TimeOut occurrence */ /* States of ADC errors */ #define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /*!< Internal error occurrence */ #define HAL_ADC_STATE_ERROR_CONFIG 0x00000020U /*!< Configuration error occurrence */ #define HAL_ADC_STATE_ERROR_DMA 0x00000040U /*!< DMA error occurrence */ /* States of ADC group regular */ #define HAL_ADC_STATE_REG_BUSY 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, external trigger, low power auto power-on, multimode ADC master control) */ #define HAL_ADC_STATE_REG_EOC 0x00000200U /*!< Conversion data available on group regular */ #define HAL_ADC_STATE_REG_OVR 0x00000400U /*!< Not available on STM32F1 device: Overrun occurrence */ #define HAL_ADC_STATE_REG_EOSMP 0x00000800U /*!< Not available on STM32F1 device: End Of Sampling flag raised */ /* States of ADC group injected */ #define HAL_ADC_STATE_INJ_BUSY 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, external trigger, low power auto power-on, multimode ADC master control) */ #define HAL_ADC_STATE_INJ_EOC 0x00002000U /*!< Conversion data available on group injected */ #define HAL_ADC_STATE_INJ_JQOVF 0x00004000U /*!< Not available on STM32F1 device: Injected queue overflow occurrence */ /* States of ADC analog watchdogs */ #define HAL_ADC_STATE_AWD1 0x00010000U /*!< Out-of-window occurrence of analog watchdog 1 */ #define HAL_ADC_STATE_AWD2 0x00020000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 2 */ #define HAL_ADC_STATE_AWD3 0x00040000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 3 */ /* States of ADC multi-mode */ #define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< ADC in multimode slave state, controlled by another ADC master ( */ /** * @brief ADC handle Structure definition */ typedef struct __ADC_HandleTypeDef { ADC_TypeDef *Instance; /*!< Register base address */ ADC_InitTypeDef Init; /*!< ADC required parameters */ DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ HAL_LockTypeDef Lock; /*!< ADC locking object */ __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ __IO uint32_t ErrorCode; /*!< ADC Error code */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ /*!< ADC end of sampling callback */ void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ }ADC_HandleTypeDef; #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /** * @brief HAL ADC Callback ID enumeration definition */ typedef enum { HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ } HAL_ADC_CallbackIDTypeDef; /** * @brief HAL ADC Callback pointer definition */ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup ADC_Exported_Constants ADC Exported Constants * @{ */ /** @defgroup ADC_Error_Code ADC Error Code * @{ */ #define HAL_ADC_ERROR_NONE 0x00U /*!< No error */ #define HAL_ADC_ERROR_INTERNAL 0x01U /*!< ADC IP internal error: if problem of clocking, enable/disable, erroneous state */ #define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */ #define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /** * @} */ /** @defgroup ADC_Data_align ADC data alignment * @{ */ #define ADC_DATAALIGN_RIGHT 0x00000000U #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) /** * @} */ /** @defgroup ADC_Scan_mode ADC scan mode * @{ */ /* Note: Scan mode values are not among binary choices ENABLE/DISABLE for */ /* compatibility with other STM32 devices having a sequencer with */ /* additional options. */ #define ADC_SCAN_DISABLE 0x00000000U #define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN) /** * @} */ /** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group * @{ */ #define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG) /** * @} */ /** @defgroup ADC_channels ADC channels * @{ */ /* Note: Depending on devices, some channels may not be available on package */ /* pins. Refer to device datasheet for channels availability. */ #define ADC_CHANNEL_0 0x00000000U #define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR3_SQ1_1 )) #define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_4 ((uint32_t)( ADC_SQR3_SQ1_2 )) #define ADC_CHANNEL_5 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_6 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 )) #define ADC_CHANNEL_7 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_8 ((uint32_t)( ADC_SQR3_SQ1_3 )) #define ADC_CHANNEL_9 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_10 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 )) #define ADC_CHANNEL_11 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_12 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 )) #define ADC_CHANNEL_13 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_14 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 )) #define ADC_CHANNEL_15 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4 )) #define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin) */ #define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin) */ /** * @} */ /** @defgroup ADC_sampling_times ADC sampling times * @{ */ #define ADC_SAMPLETIME_1CYCLE_5 0x00000000U /*!< Sampling time 1.5 ADC clock cycle */ #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_0)) /*!< Sampling time 7.5 ADC clock cycles */ #define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 )) /*!< Sampling time 13.5 ADC clock cycles */ #define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 28.5 ADC clock cycles */ #define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 )) /*!< Sampling time 41.5 ADC clock cycles */ #define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 55.5 ADC clock cycles */ #define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 )) /*!< Sampling time 71.5 ADC clock cycles */ #define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 239.5 ADC clock cycles */ /** * @} */ /** @defgroup ADC_regular_rank ADC rank into regular group * @{ */ #define ADC_REGULAR_RANK_1 0x00000001U #define ADC_REGULAR_RANK_2 0x00000002U #define ADC_REGULAR_RANK_3 0x00000003U #define ADC_REGULAR_RANK_4 0x00000004U #define ADC_REGULAR_RANK_5 0x00000005U #define ADC_REGULAR_RANK_6 0x00000006U #define ADC_REGULAR_RANK_7 0x00000007U #define ADC_REGULAR_RANK_8 0x00000008U #define ADC_REGULAR_RANK_9 0x00000009U #define ADC_REGULAR_RANK_10 0x0000000AU #define ADC_REGULAR_RANK_11 0x0000000BU #define ADC_REGULAR_RANK_12 0x0000000CU #define ADC_REGULAR_RANK_13 0x0000000DU #define ADC_REGULAR_RANK_14 0x0000000EU #define ADC_REGULAR_RANK_15 0x0000000FU #define ADC_REGULAR_RANK_16 0x00000010U /** * @} */ /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode * @{ */ #define ADC_ANALOGWATCHDOG_NONE 0x00000000U #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN) #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN) #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) /** * @} */ /** @defgroup ADC_conversion_group ADC conversion group * @{ */ #define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC)) #define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC)) #define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC)) /** * @} */ /** @defgroup ADC_Event_type ADC Event type * @{ */ #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */ #define ADC_AWD1_EVENT ADC_AWD_EVENT /*!< ADC Analog watchdog 1 event: Alternate naming for compatibility with other STM32 devices having several analog watchdogs */ /** * @} */ /** @defgroup ADC_interrupts_definition ADC interrupts definition * @{ */ #define ADC_IT_EOC ADC_CR1_EOCIE /*!< ADC End of Regular Conversion interrupt source */ #define ADC_IT_JEOC ADC_CR1_JEOCIE /*!< ADC End of Injected Conversion interrupt source */ #define ADC_IT_AWD ADC_CR1_AWDIE /*!< ADC Analog watchdog interrupt source */ /** * @} */ /** @defgroup ADC_flags_definition ADC flags definition * @{ */ #define ADC_FLAG_STRT ADC_SR_STRT /*!< ADC Regular group start flag */ #define ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC Injected group start flag */ #define ADC_FLAG_EOC ADC_SR_EOC /*!< ADC End of Regular conversion flag */ #define ADC_FLAG_JEOC ADC_SR_JEOC /*!< ADC End of Injected conversion flag */ #define ADC_FLAG_AWD ADC_SR_AWD /*!< ADC Analog watchdog flag */ /** * @} */ /** * @} */ /* Private constants ---------------------------------------------------------*/ /** @addtogroup ADC_Private_Constants ADC Private Constants * @{ */ /** @defgroup ADC_conversion_cycles ADC conversion cycles * @{ */ /* ADC conversion cycles (unit: ADC clock cycles) */ /* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */ /* resolution 12 bits) */ #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 14U #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 20U #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 26U #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 41U #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 54U #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 68U #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 84U #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 252U /** * @} */ /** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels * @{ */ #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \ (ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 | \ ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 | \ ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2) #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \ (ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | \ ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2 ) #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \ (ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 | \ ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 | \ ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1) #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \ (ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | \ ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1 ) #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \ (ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 | \ ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 | \ ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0) #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \ (ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | \ ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0 ) #define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS 0x00000000U #define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) #define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) #define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) #define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) #define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) #define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) #define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) #define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS 0x00000000U #define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) #define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) #define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) #define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) #define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) #define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) #define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) /** * @} */ /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */ #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD ) /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup ADC_Exported_Macros ADC Exported Macros * @{ */ /* Macro for internal HAL driver usage, and possibly can be used into code of */ /* final user. */ /** * @brief Enable the ADC peripheral * @note ADC enable requires a delay for ADC stabilization time * (refer to device datasheet, parameter tSTAB) * @note On STM32F1, if ADC is already enabled this macro trigs a conversion * SW start on regular group. * @param __HANDLE__: ADC handle * @retval None */ #define __HAL_ADC_ENABLE(__HANDLE__) \ (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON))) /** * @brief Disable the ADC peripheral * @param __HANDLE__: ADC handle * @retval None */ #define __HAL_ADC_DISABLE(__HANDLE__) \ (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON))) /** @brief Enable the ADC end of conversion interrupt. * @param __HANDLE__: ADC handle * @param __INTERRUPT__: ADC Interrupt * This parameter can be any combination of the following values: * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source * @retval None */ #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) /** @brief Disable the ADC end of conversion interrupt. * @param __HANDLE__: ADC handle * @param __INTERRUPT__: ADC Interrupt * This parameter can be any combination of the following values: * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source * @retval None */ #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) /** @brief Checks if the specified ADC interrupt source is enabled or disabled. * @param __HANDLE__: ADC handle * @param __INTERRUPT__: ADC interrupt source to check * This parameter can be any combination of the following values: * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source * @retval None */ #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) /** @brief Get the selected ADC's flag status. * @param __HANDLE__: ADC handle * @param __FLAG__: ADC flag * This parameter can be any combination of the following values: * @arg ADC_FLAG_STRT: ADC Regular group start flag * @arg ADC_FLAG_JSTRT: ADC Injected group start flag * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag * @arg ADC_FLAG_AWD: ADC Analog watchdog flag * @retval None */ #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear the ADC's pending flags * @param __HANDLE__: ADC handle * @param __FLAG__: ADC flag * This parameter can be any combination of the following values: * @arg ADC_FLAG_STRT: ADC Regular group start flag * @arg ADC_FLAG_JSTRT: ADC Injected group start flag * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag * @arg ADC_FLAG_AWD: ADC Analog watchdog flag * @retval None */ #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__))) /** @brief Reset ADC handle state * @param __HANDLE__: ADC handle * @retval None */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ do{ \ (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ (__HANDLE__)->MspInitCallback = NULL; \ (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ ((__HANDLE__)->State = HAL_ADC_STATE_RESET) #endif /** * @} */ /* Private macro ------------------------------------------------------------*/ /** @defgroup ADC_Private_Macros ADC Private Macros * @{ */ /* Macro reserved for internal HAL driver usage, not intended to be used in */ /* code of final user. */ /** * @brief Verification of ADC state: enabled or disabled * @param __HANDLE__: ADC handle * @retval SET (ADC enabled) or RESET (ADC disabled) */ #define ADC_IS_ENABLE(__HANDLE__) \ ((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON ) \ ) ? SET : RESET) /** * @brief Test if conversion trigger of regular group is software start * or external trigger. * @param __HANDLE__: ADC handle * @retval SET (software start) or RESET (external trigger) */ #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START) /** * @brief Test if conversion trigger of injected group is software start * or external trigger. * @param __HANDLE__: ADC handle * @retval SET (software start) or RESET (external trigger) */ #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START) /** * @brief Simultaneously clears and sets specific bits of the handle State * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), * the first parameter is the ADC handle State, the second parameter is the * bit field to clear, the third and last parameter is the bit field to set. * @retval None */ #define ADC_STATE_CLR_SET MODIFY_REG /** * @brief Clear ADC error code (set it to error code: "no error") * @param __HANDLE__: ADC handle * @retval None */ #define ADC_CLEAR_ERRORCODE(__HANDLE__) \ ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) /** * @brief Set ADC number of conversions into regular channel sequence length. * @param _NbrOfConversion_: Regular channel sequence length * @retval None */ #define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \ (((_NbrOfConversion_) - (uint8_t)1) << ADC_SQR1_L_Pos) /** * @brief Set the ADC's sample time for channel numbers between 10 and 18. * @param _SAMPLETIME_: Sample time parameter. * @param _CHANNELNB_: Channel number. * @retval None */ #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \ ((_SAMPLETIME_) << (ADC_SMPR1_SMP11_Pos * ((_CHANNELNB_) - 10))) /** * @brief Set the ADC's sample time for channel numbers between 0 and 9. * @param _SAMPLETIME_: Sample time parameter. * @param _CHANNELNB_: Channel number. * @retval None */ #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \ ((_SAMPLETIME_) << (ADC_SMPR2_SMP1_Pos * (_CHANNELNB_))) /** * @brief Set the selected regular channel rank for rank between 1 and 6. * @param _CHANNELNB_: Channel number. * @param _RANKNB_: Rank number. * @retval None */ #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \ ((_CHANNELNB_) << (ADC_SQR3_SQ2_Pos * ((_RANKNB_) - 1))) /** * @brief Set the selected regular channel rank for rank between 7 and 12. * @param _CHANNELNB_: Channel number. * @param _RANKNB_: Rank number. * @retval None */ #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \ ((_CHANNELNB_) << (ADC_SQR2_SQ8_Pos * ((_RANKNB_) - 7))) /** * @brief Set the selected regular channel rank for rank between 13 and 16. * @param _CHANNELNB_: Channel number. * @param _RANKNB_: Rank number. * @retval None */ #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \ ((_CHANNELNB_) << (ADC_SQR1_SQ14_Pos * ((_RANKNB_) - 13))) /** * @brief Set the injected sequence length. * @param _JSQR_JL_: Sequence length. * @retval None */ #define ADC_JSQR_JL_SHIFT(_JSQR_JL_) \ (((_JSQR_JL_) -1) << ADC_JSQR_JL_Pos) /** * @brief Set the selected injected channel rank * Note: on STM32F1 devices, channel rank position in JSQR register * is depending on total number of ranks selected into * injected sequencer (ranks sequence starting from 4-JL) * @param _CHANNELNB_: Channel number. * @param _RANKNB_: Rank number. * @param _JSQR_JL_: Sequence length. * @retval None */ #define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \ ((_CHANNELNB_) << (ADC_JSQR_JSQ2_Pos * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1))) /** * @brief Enable ADC continuous conversion mode. * @param _CONTINUOUS_MODE_: Continuous mode. * @retval None */ #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \ ((_CONTINUOUS_MODE_) << ADC_CR2_CONT_Pos) /** * @brief Configures the number of discontinuous conversions for the regular group channels. * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions. * @retval None */ #define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \ (((_NBR_DISCONTINUOUS_CONV_) - 1) << ADC_CR1_DISCNUM_Pos) /** * @brief Enable ADC scan mode to convert multiple ranks with sequencer. * @param _SCAN_MODE_: Scan conversion mode. * @retval None */ /* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */ /* is equivalent to ADC_SCAN_ENABLE. */ #define ADC_CR1_SCAN_SET(_SCAN_MODE_) \ (( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE) \ )? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \ ) /** * @brief Get the maximum ADC conversion cycles on all channels. * Returns the selected sampling time + conversion time (12.5 ADC clock cycles) * Approximation of sampling time within 4 ranges, returns the highest value: * below 7.5 cycles {1.5 cycle; 7.5 cycles}, * between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles} * between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles} * equal to 239.5 cycles * Unit: ADC clock cycles * @param __HANDLE__: ADC handle * @retval ADC conversion cycles on all channels */ #define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \ (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \ (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \ \ (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \ (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ? \ ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5) \ : \ ((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \ (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) || \ ((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && \ (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ? \ ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \ ) #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ ((ALIGN) == ADC_DATAALIGN_LEFT) ) #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \ ((SCAN_MODE) == ADC_SCAN_ENABLE) ) #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) ) #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ ((CHANNEL) == ADC_CHANNEL_1) || \ ((CHANNEL) == ADC_CHANNEL_2) || \ ((CHANNEL) == ADC_CHANNEL_3) || \ ((CHANNEL) == ADC_CHANNEL_4) || \ ((CHANNEL) == ADC_CHANNEL_5) || \ ((CHANNEL) == ADC_CHANNEL_6) || \ ((CHANNEL) == ADC_CHANNEL_7) || \ ((CHANNEL) == ADC_CHANNEL_8) || \ ((CHANNEL) == ADC_CHANNEL_9) || \ ((CHANNEL) == ADC_CHANNEL_10) || \ ((CHANNEL) == ADC_CHANNEL_11) || \ ((CHANNEL) == ADC_CHANNEL_12) || \ ((CHANNEL) == ADC_CHANNEL_13) || \ ((CHANNEL) == ADC_CHANNEL_14) || \ ((CHANNEL) == ADC_CHANNEL_15) || \ ((CHANNEL) == ADC_CHANNEL_16) || \ ((CHANNEL) == ADC_CHANNEL_17) ) #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \ ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \ ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \ ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \ ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \ ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \ ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \ ((TIME) == ADC_SAMPLETIME_239CYCLES_5) ) #define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_10) || \ ((CHANNEL) == ADC_REGULAR_RANK_11) || \ ((CHANNEL) == ADC_REGULAR_RANK_12) || \ ((CHANNEL) == ADC_REGULAR_RANK_13) || \ ((CHANNEL) == ADC_REGULAR_RANK_14) || \ ((CHANNEL) == ADC_REGULAR_RANK_15) || \ ((CHANNEL) == ADC_REGULAR_RANK_16) ) #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) #define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || \ ((CONVERSION) == ADC_INJECTED_GROUP) || \ ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) ) #define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT) /** @defgroup ADC_range_verification ADC range verification * For a unique ADC resolution: 12 bits * @{ */ #define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= 0x0FFFU) /** * @} */ /** @defgroup ADC_regular_nb_conv_verification ADC regular nb conv verification * @{ */ #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U)) /** * @} */ /** @defgroup ADC_regular_discontinuous_mode_number_verification ADC regular discontinuous mode number verification * @{ */ #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U)) /** * @} */ /** * @} */ /* Include ADC HAL Extension module */ #include "stm32f1xx_hal_adc_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup ADC_Exported_Functions * @{ */ /** @addtogroup ADC_Exported_Functions_Group1 * @{ */ /* Initialization and de-initialization functions **********************************/ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /* Callbacks Register/UnRegister functions ***********************************/ HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /** * @} */ /* IO operation functions *****************************************************/ /** @addtogroup ADC_Exported_Functions_Group2 * @{ */ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); /* Non-blocking mode: Interruption */ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); /* Non-blocking mode: DMA */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); /* ADC retrieve conversion value intended to be used with polling or interruption */ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); /** * @} */ /* Peripheral Control functions ***********************************************/ /** @addtogroup ADC_Exported_Functions_Group3 * @{ */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); /** * @} */ /* Peripheral State functions *************************************************/ /** @addtogroup ADC_Exported_Functions_Group4 * @{ */ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** * @} */ /** * @} */ /* Internal HAL driver functions **********************************************/ /** @addtogroup ADC_Private_Functions * @{ */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc); void ADC_StabilizationTime(uint32_t DelayUs); void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); void ADC_DMAError(DMA_HandleTypeDef *hdma); /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F1xx_HAL_ADC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/ISKv1/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h
New file @@ -0,0 +1,710 @@ /** ****************************************************************************** * @file stm32f1xx_hal_adc_ex.h * @author MCD Application Team * @brief Header file of ADC HAL extension module. ****************************************************************************** * @attention * * <h2><center>© Copyright (c) 2016 STMicroelectronics. * All rights reserved.</center></h2> * * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_ADC_EX_H #define __STM32F1xx_HAL_ADC_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @addtogroup ADCEx * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup ADCEx_Exported_Types ADCEx Exported Types * @{ */ /** * @brief ADC Configuration injected Channel structure definition * @note Parameters of this structure are shared within 2 scopes: * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, * AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv. * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. * ADC state can be either: * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ExternalTrigInjecConv') * - For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group. */ typedef struct { uint32_t InjectedChannel; /*!< Selection of ADC channel to configure This parameter can be a value of @ref ADC_channels Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor) Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger. It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel. Refer to errata sheet of these devices for more details. */ uint32_t InjectedRank; /*!< Rank in the injected group sequencer This parameter must be a value of @ref ADCEx_injected_rank Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits). This parameter can be a value of @ref ADC_sampling_times Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. Note: In case of usage of internal measurement channels (VrefInt/TempSensor), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */ uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only). Offset value must be a positive number. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer. To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 4. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE or DISABLE. Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one This parameter can be set to ENABLE or DISABLE. Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START) Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. To maintain JAUTO always enabled, DMA must be configured in circular mode. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled. If set to external trigger source, triggering is on event rising edge. This parameter can be a value of @ref ADCEx_External_trigger_source_Injected Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ }ADC_InjectionConfTypeDef; #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) /** * @brief Structure definition of ADC multimode * @note The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group). * State of ADCs of the common group must be: disabled. */ typedef struct { uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode. This parameter can be a value of @ref ADCEx_Common_mode Note: In dual mode, a change of channel configuration generates a restart that can produce a loss of synchronization. It is recommended to disable dual mode before any configuration change. Note: In case of simultaneous mode used: Exactly the same sampling time should be configured for the 2 channels that will be sampled simultaneously by ACD1 and ADC2. Note: In case of interleaved mode used: To avoid overlap between conversions, maximum sampling time allowed is 7 ADC clock cycles for fast interleaved mode and 14 ADC clock cycles for slow interleaved mode. Note: Some multimode parameters are fixed on STM32F1 and can be configured on other STM32 devices with several ADC (multimode configuration structure can have additional parameters). The equivalences are: - Parameter 'DMAAccessMode': On STM32F1, this parameter is fixed to 1 DMA channel (one DMA channel for both ADC, DMA of ADC master). On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_DMAACCESSMODE_12_10_BITS'. - Parameter 'TwoSamplingDelay': On STM32F1, this parameter is fixed to 7 or 14 ADC clock cycles depending on fast or slow interleaved mode selected. On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_TWOSAMPLINGDELAY_7CYCLES' (for fast interleaved mode). */ }ADC_MultiModeTypeDef; #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants * @{ */ /** @defgroup ADCEx_injected_rank ADCEx rank into injected group * @{ */ #define ADC_INJECTED_RANK_1 0x00000001U #define ADC_INJECTED_RANK_2 0x00000002U #define ADC_INJECTED_RANK_3 0x00000003U #define ADC_INJECTED_RANK_4 0x00000004U /** * @} */ /** @defgroup ADCEx_External_trigger_edge_Injected ADCEx external trigger enable for injected group * @{ */ #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE 0x00000000U #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTTRIG) /** * @} */ /** @defgroup ADC_External_trigger_source_Regular ADC External trigger selection for regular group * @{ */ /*!< List of external triggers with generic trigger name, independently of */ /* ADC target, sorted by trigger name: */ /*!< External triggers of regular group for ADC1&ADC2 only */ #define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1 #define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2 #define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2 #define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO #define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4 #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11 #if defined (STM32F103xE) || defined (STM32F103xG) /*!< External triggers of regular group for ADC3 only */ #define ADC_EXTERNALTRIGCONV_T2_CC3 ADC3_EXTERNALTRIG_T2_CC3 #define ADC_EXTERNALTRIGCONV_T3_CC1 ADC3_EXTERNALTRIG_T3_CC1 #define ADC_EXTERNALTRIGCONV_T5_CC1 ADC3_EXTERNALTRIG_T5_CC1 #define ADC_EXTERNALTRIGCONV_T5_CC3 ADC3_EXTERNALTRIG_T5_CC3 #define ADC_EXTERNALTRIGCONV_T8_CC1 ADC3_EXTERNALTRIG_T8_CC1 #endif /* STM32F103xE || defined STM32F103xG */ /*!< External triggers of regular group for all ADC instances */ #define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_3_EXTERNALTRIG_T1_CC3 #if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) /*!< Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */ /* XL-density devices. */ /* To use it on ADC or ADC2, a remap of trigger must be done from */ /* EXTI line 11 to TIM8_TRGO with macro: */ /* __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() */ /* __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() */ /* Note for internal constant value management: If TIM8_TRGO is available, */ /* its definition is set to value for ADC1&ADC2 by default and changed to */ /* value for ADC3 by HAL ADC driver if ADC3 is selected. */ #define ADC_EXTERNALTRIGCONV_T8_TRGO ADC1_2_EXTERNALTRIG_T8_TRGO #endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ #define ADC_SOFTWARE_START ADC1_2_3_SWSTART /** * @} */ /** @defgroup ADCEx_External_trigger_source_Injected ADCEx External trigger selection for injected group * @{ */ /*!< List of external triggers with generic trigger name, independently of */ /* ADC target, sorted by trigger name: */ /*!< External triggers of injected group for ADC1&ADC2 only */ #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4 #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 #if defined (STM32F103xE) || defined (STM32F103xG) /*!< External triggers of injected group for ADC3 only */ #define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ADC3_EXTERNALTRIGINJEC_T4_CC3 #define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ADC3_EXTERNALTRIGINJEC_T8_CC2 #define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ADC3_EXTERNALTRIGINJEC_T5_TRGO #define ADC_EXTERNALTRIGINJECCONV_T5_CC4 ADC3_EXTERNALTRIGINJEC_T5_CC4 #endif /* STM32F103xE || defined STM32F103xG */ /*!< External triggers of injected group for all ADC instances */ #define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO #if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) /*!< Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and */ /* XL-density devices. */ /* To use it on ADC1 or ADC2, a remap of trigger must be done from */ /* EXTI line 11 to TIM8_CC4 with macro: */ /* __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() */ /* __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() */ /* Note for internal constant value management: If TIM8_CC4 is available, */ /* its definition is set to value for ADC1&ADC2 by default and changed to */ /* value for ADC3 by HAL ADC driver if ADC3 is selected. */ #define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T8_CC4 #endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ #define ADC_INJECTED_SOFTWARE_START ADC1_2_3_JSWSTART /** * @} */ #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) /** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode * @{ */ #define ADC_MODE_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */ #define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)( ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined regular simultaneous + injected simultaneous mode, on groups regular and injected */ #define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)( ADC_CR1_DUALMOD_1 )) /*!< ADC dual mode enabled: Combined regular simultaneous + alternate trigger mode, on groups regular and injected */ #define ADC_DUALMODE_INJECSIMULT_INTERLFAST ((uint32_t)( ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined injected simultaneous + fast interleaved mode, on groups regular and injected (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */ #define ADC_DUALMODE_INJECSIMULT_INTERLSLOW ((uint32_t)( ADC_CR1_DUALMOD_2 )) /*!< ADC dual mode enabled: Combined injected simultaneous + slow Interleaved mode, on groups regular and injected (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */ #define ADC_DUALMODE_INJECSIMULT ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Injected simultaneous mode, on group injected */ #define ADC_DUALMODE_REGSIMULT ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 )) /*!< ADC dual mode enabled: Regular simultaneous mode, on group regular */ #define ADC_DUALMODE_INTERLFAST ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Fast interleaved mode, on group regular (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */ #define ADC_DUALMODE_INTERLSLOW ((uint32_t)(ADC_CR1_DUALMOD_3 )) /*!< ADC dual mode enabled: Slow interleaved mode, on group regular (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */ #define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Alternate trigger mode, on group injected */ /** * @} */ #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @} */ /* Private constants ---------------------------------------------------------*/ /** @addtogroup ADCEx_Private_Constants ADCEx Private Constants * @{ */ /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended Internal HAL driver trigger selection for regular group * @{ */ /* List of external triggers of regular group for ADC1, ADC2, ADC3 (if ADC */ /* instance is available on the selected device). */ /* (used internally by HAL driver. To not use into HAL structure parameters) */ /* External triggers of regular group for ADC1&ADC2 (if ADCx available) */ #define ADC1_2_EXTERNALTRIG_T1_CC1 0x00000000U #define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)( ADC_CR2_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)( ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 )) #define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 )) #if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) /* Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */ /* XL-density devices. */ #define ADC1_2_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_EXT_IT11 #endif #if defined (STM32F103xE) || defined (STM32F103xG) /* External triggers of regular group for ADC3 */ #define ADC3_EXTERNALTRIG_T3_CC1 ADC1_2_EXTERNALTRIG_T1_CC1 #define ADC3_EXTERNALTRIG_T2_CC3 ADC1_2_EXTERNALTRIG_T1_CC2 #define ADC3_EXTERNALTRIG_T8_CC1 ADC1_2_EXTERNALTRIG_T2_CC2 #define ADC3_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO #define ADC3_EXTERNALTRIG_T5_CC1 ADC1_2_EXTERNALTRIG_T4_CC4 #define ADC3_EXTERNALTRIG_T5_CC3 ADC1_2_EXTERNALTRIG_EXT_IT11 #endif /* External triggers of regular group for ADC1&ADC2&ADC3 (if ADCx available) */ #define ADC1_2_3_EXTERNALTRIG_T1_CC3 ((uint32_t)( ADC_CR2_EXTSEL_1 )) #define ADC1_2_3_SWSTART ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) /** * @} */ /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADC Extended Internal HAL driver trigger selection for injected group * @{ */ /* List of external triggers of injected group for ADC1, ADC2, ADC3 (if ADC */ /* instance is available on the selected device). */ /* (used internally by HAL driver. To not use into HAL structure parameters) */ /* External triggers of injected group for ADC1&ADC2 (if ADCx available) */ #define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_1 )) #define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)( ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) #define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 )) #define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) #define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 )) #if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) /* Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and */ /* XL-density devices. */ #define ADC1_2_EXTERNALTRIGINJEC_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 #endif #if defined (STM32F103xE) || defined (STM32F103xG) /* External triggers of injected group for ADC3 */ #define ADC3_EXTERNALTRIGINJEC_T4_CC3 ADC1_2_EXTERNALTRIGINJEC_T2_TRGO #define ADC3_EXTERNALTRIGINJEC_T8_CC2 ADC1_2_EXTERNALTRIGINJEC_T2_CC1 #define ADC3_EXTERNALTRIGINJEC_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4 #define ADC3_EXTERNALTRIGINJEC_T5_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO #define ADC3_EXTERNALTRIGINJEC_T5_CC4 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 #endif /* STM32F103xE || defined STM32F103xG */ /* External triggers of injected group for ADC1&ADC2&ADC3 (if ADCx available) */ #define ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO 0x00000000U #define ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)( ADC_CR2_JEXTSEL_0)) #define ADC1_2_3_JSWSTART ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /** @defgroup ADCEx_Private_Macro ADCEx Private Macro * @{ */ /* Macro reserved for internal HAL driver usage, not intended to be used in */ /* code of final user. */ /** * @brief For devices with 3 ADCs: Defines the external trigger source * for regular group according to ADC into common group ADC1&ADC2 or * ADC3 (some triggers with same source have different value to * be programmed into ADC EXTSEL bits of CR2 register). * For devices with 2 ADCs or less: this macro makes no change. * @param __HANDLE__: ADC handle * @param __EXT_TRIG_CONV__: External trigger selected for regular group. * @retval External trigger to be programmed into EXTSEL bits of CR2 register */ #if defined (STM32F103xE) || defined (STM32F103xG) #define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \ (( (((__HANDLE__)->Instance) == ADC3) \ )? \ ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO \ )? \ (ADC3_EXTERNALTRIG_T8_TRGO) \ : \ (__EXT_TRIG_CONV__) \ ) \ : \ (__EXT_TRIG_CONV__) \ ) #else #define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \ (__EXT_TRIG_CONV__) #endif /* STM32F103xE || STM32F103xG */ /** * @brief For devices with 3 ADCs: Defines the external trigger source * for injected group according to ADC into common group ADC1&ADC2 or * ADC3 (some triggers with same source have different value to * be programmed into ADC JEXTSEL bits of CR2 register). * For devices with 2 ADCs or less: this macro makes no change. * @param __HANDLE__: ADC handle * @param __EXT_TRIG_INJECTCONV__: External trigger selected for injected group. * @retval External trigger to be programmed into JEXTSEL bits of CR2 register */ #if defined (STM32F103xE) || defined (STM32F103xG) #define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \ (( (((__HANDLE__)->Instance) == ADC3) \ )? \ ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4 \ )? \ (ADC3_EXTERNALTRIGINJEC_T8_CC4) \ : \ (__EXT_TRIG_INJECTCONV__) \ ) \ : \ (__EXT_TRIG_INJECTCONV__) \ ) #else #define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \ (__EXT_TRIG_INJECTCONV__) #endif /* STM32F103xE || STM32F103xG */ /** * @brief Verification if multimode is enabled for the selected ADC (multimode ADC master or ADC slave) (applicable for devices with several ADCs) * @param __HANDLE__: ADC handle * @retval Multimode state: RESET if multimode is disabled, other value if multimode is enabled */ #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) #define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) \ (( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \ )? \ (ADC1->CR1 & ADC_CR1_DUALMOD) \ : \ (RESET) \ ) #else #define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) \ (RESET) #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode, or multimode with handle of ADC master (applicable for devices with several ADCs) * @param __HANDLE__: ADC handle * @retval None */ #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ (( (((__HANDLE__)->Instance) == ADC2) \ )? \ ((ADC1->CR1 & ADC_CR1_DUALMOD) == RESET) \ : \ (!RESET) \ ) #else #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ (!RESET) #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @brief Check ADC multimode setting: In case of multimode, check whether ADC master of the selected ADC has feature auto-injection enabled (applicable for devices with several ADCs) * @param __HANDLE__: ADC handle * @retval None */ #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) #define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \ (( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \ )? \ (ADC1->CR1 & ADC_CR1_JAUTO) \ : \ (RESET) \ ) #else #define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \ (RESET) #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) /** * @brief Set handle of the other ADC sharing the common multimode settings * @param __HANDLE__: ADC handle * @param __HANDLE_OTHER_ADC__: other ADC handle * @retval None */ #define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) \ ((__HANDLE_OTHER_ADC__)->Instance = ADC2) /** * @brief Set handle of the ADC slave associated to the ADC master * On STM32F1 devices, ADC slave is always ADC2 (this can be different * on other STM32 devices) * @param __HANDLE_MASTER__: ADC master handle * @param __HANDLE_SLAVE__: ADC slave handle * @retval None */ #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ ((__HANDLE_SLAVE__)->Instance = ADC2) #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ #define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \ ((CHANNEL) == ADC_INJECTED_RANK_2) || \ ((CHANNEL) == ADC_INJECTED_RANK_3) || \ ((CHANNEL) == ADC_INJECTED_RANK_4)) #define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING)) /** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification * @{ */ #define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 4U)) /** * @} */ #if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ ((REGTRIG) == ADC_SOFTWARE_START)) #endif #if defined (STM32F101xE) #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \ ((REGTRIG) == ADC_SOFTWARE_START)) #endif #if defined (STM32F101xG) #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ ((REGTRIG) == ADC_SOFTWARE_START)) #endif #if defined (STM32F103xE) || defined (STM32F103xG) #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \ ((REGTRIG) == ADC_SOFTWARE_START)) #endif #if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) #define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ ((REGTRIG) == ADC_INJECTED_SOFTWARE_START)) #endif #if defined (STM32F101xE) #define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \ ((REGTRIG) == ADC_INJECTED_SOFTWARE_START)) #endif #if defined (STM32F101xG) #define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ ((REGTRIG) == ADC_INJECTED_SOFTWARE_START)) #endif #if defined (STM32F103xE) || defined (STM32F103xG) #define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \ ((REGTRIG) == ADC_INJECTED_SOFTWARE_START)) #endif #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) #define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \ ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLFAST) || \ ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLSLOW) || \ ((MODE) == ADC_DUALMODE_INJECSIMULT) || \ ((MODE) == ADC_DUALMODE_REGSIMULT) || \ ((MODE) == ADC_DUALMODE_INTERLFAST) || \ ((MODE) == ADC_DUALMODE_INTERLSLOW) || \ ((MODE) == ADC_DUALMODE_ALTERTRIG) ) #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup ADCEx_Exported_Functions * @{ */ /* IO operation functions *****************************************************/ /** @addtogroup ADCEx_Exported_Functions_Group1 * @{ */ /* ADC calibration */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); /* Non-blocking mode: Interruption */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc); #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) /* ADC multimode */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /* ADC retrieve conversion value intended to be used with polling or interruption */ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc); /** * @} */ /* Peripheral Control functions ***********************************************/ /** @addtogroup ADCEx_Exported_Functions_Group2 * @{ */ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F1xx_HAL_ADC_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/ISKv1/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c
New file @@ -0,0 +1,2437 @@ /** ****************************************************************************** * @file stm32f1xx_hal_adc.c * @author MCD Application Team * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: * + Initialization and de-initialization functions * ++ Initialization and Configuration of ADC * + Operation functions * ++ Start, stop, get result of conversions of regular * group, using 3 possible modes: polling, interruption or DMA. * + Control functions * ++ Channels configuration on regular group * ++ Channels configuration on injected group * ++ Analog Watchdog configuration * + State functions * ++ ADC state machine management * ++ Interrupts and flags management * Other functions (extended functions) are available in file * "stm32f1xx_hal_adc_ex.c". * @verbatim ============================================================================== ##### ADC peripheral features ##### ============================================================================== [..] (+) 12-bit resolution (+) Interrupt generation at the end of regular conversion, end of injected conversion, and in case of analog watchdog or overrun events. (+) Single and continuous conversion modes. (+) Scan mode for conversion of several channels sequentially. (+) Data alignment with in-built data coherency. (+) Programmable sampling time (channel wise) (+) ADC conversion of regular group and injected group. (+) External trigger (timer or EXTI) for both regular and injected groups. (+) DMA request generation for transfer of conversions data of regular group. (+) Multimode Dual mode (available on devices with 2 ADCs or more). (+) Configurable DMA data storage in Multimode Dual mode (available on devices with 2 DCs or more). (+) Configurable delay between conversions in Dual interleaved mode (available on devices with 2 DCs or more). (+) ADC calibration (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at slower speed. (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to Vdda or to an external voltage reference). ##### How to use this driver ##### ============================================================================== [..] *** Configuration of top level parameters related to ADC *** ============================================================ [..] (#) Enable the ADC interface (++) As prerequisite, ADC clock must be configured at RCC top level. Caution: On STM32F1, ADC clock frequency max is 14MHz (refer to device datasheet). Therefore, ADC clock prescaler must be configured in function of ADC clock source frequency to remain below this maximum frequency. (++) One clock setting is mandatory: ADC clock (core clock, also possibly conversion clock). (+++) Example: Into HAL_ADC_MspInit() (recommended code location) or with other device clock parameters configuration: (+++) RCC_PeriphCLKInitTypeDef PeriphClkInit; (+++) __ADC1_CLK_ENABLE(); (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV2; (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit); (#) ADC pins configuration (++) Enable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_ENABLE() (++) Configure these ADC pins in analog mode using function HAL_GPIO_Init() (#) Optionally, in case of usage of ADC with interruptions: (++) Configure the NVIC for ADC using function HAL_NVIC_EnableIRQ(ADCx_IRQn) (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() into the function of corresponding ADC interruption vector ADCx_IRQHandler(). (#) Optionally, in case of usage of DMA: (++) Configure the DMA (DMA channel, mode normal or circular, ...) using function HAL_DMA_Init(). (++) Configure the NVIC for DMA using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() into the function of corresponding DMA interruption vector DMAx_Channelx_IRQHandler(). *** Configuration of ADC, groups regular/injected, channels parameters *** ========================================================================== [..] (#) Configure the ADC parameters (resolution, data alignment, ...) and regular group parameters (conversion trigger, sequencer, ...) using function HAL_ADC_Init(). (#) Configure the channels for regular group parameters (channel number, channel rank into sequencer, ..., into regular group) using function HAL_ADC_ConfigChannel(). (#) Optionally, configure the injected group parameters (conversion trigger, sequencer, ..., of injected group) and the channels for injected group parameters (channel number, channel rank into sequencer, ..., into injected group) using function HAL_ADCEx_InjectedConfigChannel(). (#) Optionally, configure the analog watchdog parameters (channels monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig(). (#) Optionally, for devices with several ADC instances: configure the multimode parameters using function HAL_ADCEx_MultiModeConfigChannel(). *** Execution of ADC conversions *** ==================================== [..] (#) Optionally, perform an automatic ADC calibration to improve the conversion accuracy using function HAL_ADCEx_Calibration_Start(). (#) ADC driver can be used among three modes: polling, interruption, transfer by DMA. (++) ADC conversion by polling: (+++) Activate the ADC peripheral and start conversions using function HAL_ADC_Start() (+++) Wait for ADC conversion completion using function HAL_ADC_PollForConversion() (or for injected group: HAL_ADCEx_InjectedPollForConversion() ) (+++) Retrieve conversion results using function HAL_ADC_GetValue() (or for injected group: HAL_ADCEx_InjectedGetValue() ) (+++) Stop conversion and disable the ADC peripheral using function HAL_ADC_Stop() (++) ADC conversion by interruption: (+++) Activate the ADC peripheral and start conversions using function HAL_ADC_Start_IT() (+++) Wait for ADC conversion completion by call of function HAL_ADC_ConvCpltCallback() (this function must be implemented in user program) (or for injected group: HAL_ADCEx_InjectedConvCpltCallback() ) (+++) Retrieve conversion results using function HAL_ADC_GetValue() (or for injected group: HAL_ADCEx_InjectedGetValue() ) (+++) Stop conversion and disable the ADC peripheral using function HAL_ADC_Stop_IT() (++) ADC conversion with transfer by DMA: (+++) Activate the ADC peripheral and start conversions using function HAL_ADC_Start_DMA() (+++) Wait for ADC conversion completion by call of function HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() (these functions must be implemented in user program) (+++) Conversion results are automatically transferred by DMA into destination variable address. (+++) Stop conversion and disable the ADC peripheral using function HAL_ADC_Stop_DMA() (++) For devices with several ADCs: ADC multimode conversion with transfer by DMA: (+++) Activate the ADC peripheral (slave) and start conversions using function HAL_ADC_Start() (+++) Activate the ADC peripheral (master) and start conversions using function HAL_ADCEx_MultiModeStart_DMA() (+++) Wait for ADC conversion completion by call of function HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() (these functions must be implemented in user program) (+++) Conversion results are automatically transferred by DMA into destination variable address. (+++) Stop conversion and disable the ADC peripheral (master) using function HAL_ADCEx_MultiModeStop_DMA() (+++) Stop conversion and disable the ADC peripheral (slave) using function HAL_ADC_Stop_IT() [..] (@) Callback functions must be implemented in user program: (+@) HAL_ADC_ErrorCallback() (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) (+@) HAL_ADC_ConvCpltCallback() (+@) HAL_ADC_ConvHalfCpltCallback (+@) HAL_ADCEx_InjectedConvCpltCallback() *** Deinitialization of ADC *** ============================================================ [..] (#) Disable the ADC interface (++) ADC clock can be hard reset and disabled at RCC top level. (++) Hard reset of ADC peripherals using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET(). (++) ADC clock disable using the equivalent macro/functions as configuration step. (+++) Example: Into HAL_ADC_MspDeInit() (recommended code location) or with other device clock parameters configuration: (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPLLCLK2_OFF (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) (#) ADC pins configuration (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE() (#) Optionally, in case of usage of ADC with interruptions: (++) Disable the NVIC for ADC using function HAL_NVIC_EnableIRQ(ADCx_IRQn) (#) Optionally, in case of usage of DMA: (++) Deinitialize the DMA using function HAL_DMA_Init(). (++) Disable the NVIC for DMA using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) [..] *** Callback registration *** ============================================= [..] The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, allows the user to configure dynamically the driver callbacks. Use Functions @ref HAL_ADC_RegisterCallback() to register an interrupt callback. [..] Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks: (+) ConvCpltCallback : ADC conversion complete callback (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback (+) ErrorCallback : ADC error callback (+) InjectedConvCpltCallback : ADC group injected conversion complete callback (+) MspInitCallback : ADC Msp Init callback (+) MspDeInitCallback : ADC Msp DeInit callback This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default weak function. [..] @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) ConvCpltCallback : ADC conversion complete callback (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback (+) ErrorCallback : ADC error callback (+) InjectedConvCpltCallback : ADC group injected conversion complete callback (+) MspInitCallback : ADC Msp Init callback (+) MspDeInitCallback : ADC Msp DeInit callback [..] By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET all callbacks are set to the corresponding weak functions: examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when these callbacks are null (not registered beforehand). [..] If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. [..] Then, the user first registers the MspInit/MspDeInit user callbacks using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit() or @ref HAL_ADC_Init() function. [..] When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. @endverbatim ****************************************************************************** * @attention * * <h2><center>© Copyright (c) 2016 STMicroelectronics. * All rights reserved.</center></h2> * * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @defgroup ADC ADC * @brief ADC HAL module driver * @{ */ #ifdef HAL_ADC_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup ADC_Private_Constants ADC Private Constants * @{ */ /* Timeout values for ADC enable and disable settling time. */ /* Values defined to be higher than worst cases: low clocks freq, */ /* maximum prescaler. */ /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */ /* Unit: ms */ #define ADC_ENABLE_TIMEOUT 2U #define ADC_DISABLE_TIMEOUT 2U /* Delay for ADC stabilization time. */ /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ /* Unit: us */ #define ADC_STAB_DELAY_US 1U /* Delay for temperature sensor stabilization time. */ /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ /* Unit: us */ #define ADC_TEMPSENSOR_DELAY_US 10U /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup ADC_Private_Functions ADC Private Functions * @{ */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup ADC_Exported_Functions ADC Exported Functions * @{ */ /** @defgroup ADC_Exported_Functions_Group1 Initialization/de-initialization functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the ADC. (+) De-initialize the ADC. @endverbatim * @{ */ /** * @brief Initializes the ADC peripheral and regular group according to * parameters specified in structure "ADC_InitTypeDef". * @note As prerequisite, ADC clock must be configured at RCC top level * (clock source APB2). * See commented example code below that can be copied and uncommented * into HAL_ADC_MspInit(). * @note Possibility to update parameters on the fly: * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when * coming from ADC state reset. Following calls to this function can * be used to reconfigure some parameters of ADC_InitTypeDef * structure on the fly, without modifying MSP configuration. If ADC * MSP has to be modified again, HAL_ADC_DeInit() must be called * before HAL_ADC_Init(). * The setting of these parameters is conditioned to ADC state. * For parameters constraints, see comments of structure * "ADC_InitTypeDef". * @note This function configures the ADC within 2 scopes: scope of entire * ADC and scope of regular group. For parameters details, see comments * of structure "ADC_InitTypeDef". * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmp_cr1 = 0U; uint32_t tmp_cr2 = 0U; uint32_t tmp_sqr1 = 0U; /* Check ADC handle */ if(hadc == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) { assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); if(hadc->Init.DiscontinuousConvMode != DISABLE) { assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion)); } } /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */ /* at RCC top level. */ /* Refer to header of this file for more details on clock enabling */ /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /* Init the ADC Callback settings */ hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */ hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */ hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */ hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */ hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */ if (hadc->MspInitCallback == NULL) { hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ } /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ /* Note: In case of ADC already enabled, precaution to not launch an */ /* unwanted conversion while modifying register CR2 by writing 1 to */ /* bit ADON. */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); /* Set ADC parameters */ /* Configuration of ADC: */ /* - data alignment */ /* - external trigger to start conversion */ /* - external trigger polarity (always set to 1, because needed for all */ /* triggers: external trigger of SW start) */ /* - continuous conversion mode */ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ /* HAL_ADC_Start_xxx functions because if set in this function, */ /* a conversion on injected group would start a conversion also on */ /* regular group after ADC enabling. */ tmp_cr2 |= (hadc->Init.DataAlign | ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); /* Configuration of ADC: */ /* - scan mode */ /* - discontinuous mode disable/enable */ /* - discontinuous mode number of conversions */ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); /* Enable discontinuous mode only if continuous mode is disabled */ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ /* discontinuous is set anyway, but will have no effect on ADC HW. */ if (hadc->Init.DiscontinuousConvMode == ENABLE) { if (hadc->Init.ContinuousConvMode == DISABLE) { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmp_cr1, ADC_CR1_DISCEN | ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) ); } else { /* ADC regular group settings continuous and sequencer discontinuous*/ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); } } /* Update ADC configuration register CR1 with previous settings */ MODIFY_REG(hadc->Instance->CR1, ADC_CR1_SCAN | ADC_CR1_DISCEN | ADC_CR1_DISCNUM , tmp_cr1 ); /* Update ADC configuration register CR2 with previous settings */ MODIFY_REG(hadc->Instance->CR2, ADC_CR2_ALIGN | ADC_CR2_EXTSEL | ADC_CR2_EXTTRIG | ADC_CR2_CONT , tmp_cr2 ); /* Configuration of regular group sequencer: */ /* - if scan mode is disabled, regular channels sequence length is set to */ /* 0x00: 1 channel converted (channel on regular rank 1) */ /* Parameter "NbrOfConversion" is discarded. */ /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) { tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); } MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L , tmp_sqr1 ); /* Check back that ADC registers have effectively been configured to */ /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CR2 (excluding bits set in other functions: */ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ /* measurement path bit (TSVREFE). */ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | ADC_CR2_SWSTART | ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_TSVREFE )) == tmp_cr2) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); tmp_hal_status = HAL_ERROR; } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); tmp_hal_status = HAL_ERROR; } /* Return function status */ return tmp_hal_status; } /** * @brief Deinitialize the ADC peripheral registers to their default reset * values, with deinitialization of the ADC MSP. * If needed, the example code can be copied and uncommented into * function HAL_ADC_MspDeInit(). * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check ADC handle */ if(hadc == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (tmp_hal_status == HAL_OK) { /* ========== Reset ADC registers ========== */ /* Reset register SR */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_JEOC | ADC_FLAG_EOC | ADC_FLAG_JSTRT | ADC_FLAG_STRT)); /* Reset register CR1 */ CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_AWDCH )); /* Reset register CR2 */ CLEAR_BIT(hadc->Instance->CR2, (ADC_CR2_TSVREFE | ADC_CR2_SWSTART | ADC_CR2_JSWSTART | ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL | ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_ALIGN | ADC_CR2_DMA | ADC_CR2_RSTCAL | ADC_CR2_CAL | ADC_CR2_CONT | ADC_CR2_ADON )); /* Reset register SMPR1 */ CLEAR_BIT(hadc->Instance->SMPR1, (ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10 )); /* Reset register SMPR2 */ CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP9 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0 )); /* Reset register JOFR1 */ CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1); /* Reset register JOFR2 */ CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2); /* Reset register JOFR3 */ CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3); /* Reset register JOFR4 */ CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4); /* Reset register HTR */ CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT); /* Reset register LTR */ CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT); /* Reset register SQR1 */ CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L | ADC_SQR1_SQ16 | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13 ); /* Reset register SQR1 */ CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L | ADC_SQR1_SQ16 | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13 ); /* Reset register SQR2 */ CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 ); /* Reset register SQR3 */ CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 | ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1 ); /* Reset register JSQR */ CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ); /* Reset register JSQR */ CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ); /* Reset register DR */ /* bits in access mode read only, no direct reset applicable*/ /* Reset registers JDR1, JDR2, JDR3, JDR4 */ /* bits in access mode read only, no direct reset applicable*/ /* ========== Hard reset ADC peripheral ========== */ /* Performs a global reset of the entire ADC peripheral: ADC state is */ /* forced to a similar state after device power-on. */ /* If needed, copy-paste and uncomment the following reset code into */ /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */ /* */ /* __HAL_RCC_ADC1_FORCE_RESET() */ /* __HAL_RCC_ADC1_RELEASE_RESET() */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) if (hadc->MspDeInitCallback == NULL) { hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ } /* DeInit the low level hardware */ hadc->MspDeInitCallback(hadc); #else /* DeInit the low level hardware */ HAL_ADC_MspDeInit(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); /* Set ADC state */ hadc->State = HAL_ADC_STATE_RESET; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Initializes the ADC MSP. * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_MspInit must be implemented in the user file. */ } /** * @brief DeInitializes the ADC MSP. * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_MspDeInit must be implemented in the user file. */ } #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /** * @brief Register a User ADC Callback * To be used instead of the weak predefined callback * @param hadc Pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID * @param pCallback pointer to the Callback function * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; if (pCallback == NULL) { /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; return HAL_ERROR; } if ((hadc->State & HAL_ADC_STATE_READY) != 0) { switch (CallbackID) { case HAL_ADC_CONVERSION_COMPLETE_CB_ID : hadc->ConvCpltCallback = pCallback; break; case HAL_ADC_CONVERSION_HALF_CB_ID : hadc->ConvHalfCpltCallback = pCallback; break; case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : hadc->LevelOutOfWindowCallback = pCallback; break; case HAL_ADC_ERROR_CB_ID : hadc->ErrorCallback = pCallback; break; case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : hadc->InjectedConvCpltCallback = pCallback; break; case HAL_ADC_MSPINIT_CB_ID : hadc->MspInitCallback = pCallback; break; case HAL_ADC_MSPDEINIT_CB_ID : hadc->MspDeInitCallback = pCallback; break; default : /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; break; } } else if (HAL_ADC_STATE_RESET == hadc->State) { switch (CallbackID) { case HAL_ADC_MSPINIT_CB_ID : hadc->MspInitCallback = pCallback; break; case HAL_ADC_MSPDEINIT_CB_ID : hadc->MspDeInitCallback = pCallback; break; default : /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; break; } } else { /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; } return status; } /** * @brief Unregister a ADC Callback * ADC callback is redirected to the weak predefined callback * @param hadc Pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; if ((hadc->State & HAL_ADC_STATE_READY) != 0) { switch (CallbackID) { case HAL_ADC_CONVERSION_COMPLETE_CB_ID : hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; break; case HAL_ADC_CONVERSION_HALF_CB_ID : hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; break; case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; break; case HAL_ADC_ERROR_CB_ID : hadc->ErrorCallback = HAL_ADC_ErrorCallback; break; case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; break; case HAL_ADC_MSPINIT_CB_ID : hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ break; case HAL_ADC_MSPDEINIT_CB_ID : hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ break; default : /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; break; } } else if (HAL_ADC_STATE_RESET == hadc->State) { switch (CallbackID) { case HAL_ADC_MSPINIT_CB_ID : hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ break; case HAL_ADC_MSPDEINIT_CB_ID : hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ break; default : /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; break; } } else { /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; } return status; } #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /** * @} */ /** @defgroup ADC_Exported_Functions_Group2 IO operation functions * @brief Input and Output operation functions * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Start conversion of regular group. (+) Stop conversion of regular group. (+) Poll for conversion complete on regular group. (+) Poll for conversion event. (+) Get result of regular channel conversion. (+) Start conversion of regular group and enable interruptions. (+) Stop conversion of regular group and disable interruptions. (+) Handle ADC interrupt request (+) Start conversion of regular group and enable DMA transfer. (+) Stop conversion of regular group and disable ADC DMA transfer. @endverbatim * @{ */ /** * @brief Enables ADC, starts conversion of regular group. * Interruptions enabled in this function: None. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) and multimode state */ /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } } else { /* Set ADC state (ADC slave) */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Clear regular group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Case of multimode enabled: */ /* - if ADC is slave, ADC is enabled only (conversion is not started). */ /* - if ADC is master, ADC is enabled and conversion is started. */ /* If ADC is master, ADC is enabled and conversion is started. */ /* Note: Alternate trigger for single conversion could be to force an */ /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } /* Return function status */ return tmp_hal_status; } /** * @brief Stop ADC conversion of regular group (and injected channels in * case of auto_injection mode), disable ADC peripheral. * @note: ADC peripheral disable is forcing stop of potential * conversion on injected group. If injected group is under use, it * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Wait for regular group conversion to be completed. * @note This function cannot be used in a particular setup: ADC configured * in DMA mode. * In this case, DMA resets the flag EOC and polling cannot be * performed on each conversion. * @note On STM32F1 devices, limitation in case of sequencer enabled * (several ranks selected): polling cannot be done on each * conversion inside the sequence. In this case, polling is replaced by * wait for maximum conversion time. * @param hadc: ADC handle * @param Timeout: Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) { uint32_t tickstart = 0U; /* Variables for polling in case of scan mode enabled and polling for each */ /* conversion. */ __IO uint32_t Conversion_Timeout_CPU_cycles = 0U; uint32_t Conversion_Timeout_CPU_cycles_max = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Get tick count */ tickstart = HAL_GetTick(); /* Verification that ADC configuration is compliant with polling for */ /* each conversion: */ /* Particular case is ADC configured in DMA mode */ if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } /* Polling for end of conversion: differentiation if single/sequence */ /* conversion. */ /* - If single conversion for regular group (Scan mode disabled or enabled */ /* with NbrOfConversion =1), flag EOC is used to determine the */ /* conversion completion. */ /* - If sequence conversion for regular group (scan mode enabled and */ /* NbrOfConversion >=2), flag EOC is set only at the end of the */ /* sequence. */ /* To poll for each conversion, the maximum conversion time is computed */ /* from ADC conversion time (selected sampling time + conversion time of */ /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */ /* settings, conversion time range can be from 28 to 32256 CPU cycles). */ /* As flag EOC is not set after each conversion, no timeout status can */ /* be set. */ if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ) { /* Wait until End of Conversion flag is raised */ while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_TIMEOUT; } } } } } else { /* Replace polling by wait for maximum conversion time */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles */ /* and ADC maximum conversion cycles on all channels. */ /* - Wait for the expected ADC clock cycles delay */ Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) * ADC_CONVCYCLES_MAX_RANGE(hadc) ); while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* New check to avoid false timeout detection in case of preemption */ if(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_TIMEOUT; } } } Conversion_Timeout_CPU_cycles ++; } } /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && (hadc->Init.ContinuousConvMode == DISABLE) ) { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } /* Return ADC state */ return HAL_OK; } /** * @brief Poll for conversion event. * @param hadc: ADC handle * @param EventType: the ADC event type. * This parameter can be one of the following values: * @arg ADC_AWD_EVENT: ADC Analog watchdog event. * @param Timeout: Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) { uint32_t tickstart = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_EVENT_TYPE(EventType)); /* Get tick count */ tickstart = HAL_GetTick(); /* Check selected event flag */ while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) { /* New check to avoid false timeout detection in case of preemption */ if(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_TIMEOUT; } } } } /* Analog watchdog (level out of window) event */ /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); /* Return ADC state */ return HAL_OK; } /** * @brief Enables ADC, starts conversion of regular group with interruption. * Interruptions enabled in this function: * - EOC (end of conversion of regular group) * Each of these interruptions has its dedicated callback function. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) and multimode state */ /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } } else { /* Set ADC state (ADC slave) */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); /* Enable end of conversion interrupt for regular group */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC); /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Case of multimode enabled: */ /* - if ADC is slave, ADC is enabled only (conversion is not started). */ /* - if ADC is master, ADC is enabled and conversion is started. */ if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } /* Return function status */ return tmp_hal_status; } /** * @brief Stop ADC conversion of regular group (and injected group in * case of auto_injection mode), disable interrution of * end-of-conversion, disable ADC peripheral. * @param hadc: ADC handle * @retval None */ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Disable ADC end of conversion interrupt for regular group */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Enables ADC, starts conversion of regular group and transfers result * through DMA. * Interruptions enabled in this function: * - DMA transfer complete * - DMA half transfer * Each of these interruptions has its dedicated callback function. * @note For devices with several ADCs: This function is for single-ADC mode * only. For multimode, use the dedicated MultimodeStart function. * @note On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending * on devices) have DMA capability. * ADC2 converted data can be transferred in dual ADC mode using DMA * of ADC1 (ADC master in multimode). * In case of using ADC1 with DMA on a device featuring 2 ADC * instances: ADC1 conversion register DR contains ADC1 conversion * result (ADC1 register DR bits 0 to 11) and, additionally, ADC2 last * conversion result (ADC1 register DR bits 16 to 27). Therefore, to * have DMA transferring the conversion results of ADC1 only, DMA must * be configured to transfer size: half word. * @param hadc: ADC handle * @param pData: The destination Buffer address. * @param Length: The length of data to be transferred from ADC peripheral to memory. * @retval None */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance)); /* Verification if multimode is disabled (for devices with several ADC) */ /* If multimode is enabled, dedicated function multimode conversion */ /* start DMA must be used. */ if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET) { /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) and multimode state */ /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } } else { /* Set ADC state (ADC slave) */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ /* start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); /* Enable ADC DMA mode */ SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA); /* Start the DMA channel */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } } else { tmp_hal_status = HAL_ERROR; } /* Return function status */ return tmp_hal_status; } /** * @brief Stop ADC conversion of regular group (and injected group in * case of auto_injection mode), disable ADC DMA transfer, disable * ADC peripheral. * @note: ADC peripheral disable is forcing stop of potential * conversion on injected group. If injected group is under use, it * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. * @note For devices with several ADCs: This function is for single-ADC mode * only. For multimode, use the dedicated MultimodeStop function. * @note On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending * on devices) have DMA capability. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Disable ADC DMA mode */ CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA); /* Disable the DMA channel (in case of DMA in circular mode or stop while */ /* DMA transfer is on going) */ if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) { tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); /* Check if DMA channel effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); } } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Get ADC regular group conversion result. * @note Reading register DR automatically clears ADC flag EOC * (ADC group regular end of unitary conversion). * @note This function does not clear ADC flag EOS * (ADC group regular end of sequence conversion). * Occurrence of flag EOS rising: * - If sequencer is composed of 1 rank, flag EOS is equivalent * to flag EOC. * - If sequencer is composed of several ranks, during the scan * sequence flag EOC only is raised, at the end of the scan sequence * both flags EOC and EOS are raised. * To clear this flag, either use function: * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming * model polling: @ref HAL_ADC_PollForConversion() * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). * @param hadc: ADC handle * @retval ADC group regular conversion data */ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Note: EOC flag is not cleared here by software because automatically */ /* cleared by hardware when reading register DR. */ /* Return ADC converted value */ return hadc->Instance->DR; } /** * @brief Handles ADC interrupt request * @param hadc: ADC handle * @retval None */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); /* ========== Check End of Conversion flag for regular group ========== */ if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) { if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) ) { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); } /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && (hadc->Init.ContinuousConvMode == DISABLE) ) { /* Disable ADC end of conversion interrupt on group regular */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); } } /* ========== Check End of Conversion flag for injected group ========== */ if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC)) { if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)) { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); } /* Determine whether any further conversion upcoming on group injected */ /* by external trigger, scan sequence on going or by automatic injected */ /* conversion from group regular (same conditions as group regular */ /* interruption disabling above). */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && (ADC_IS_SOFTWARE_START_REGULAR(hadc) && (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) { /* Disable ADC end of conversion interrupt on group injected */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->InjectedConvCpltCallback(hadc); #else HAL_ADCEx_InjectedConvCpltCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear injected group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); } } /* ========== Check Analog watchdog flags ========== */ if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD)) { if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD)) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); /* Level out of window callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindowCallback(hadc); #else HAL_ADC_LevelOutOfWindowCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear the ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); } } } /** * @brief Conversion complete callback in non blocking mode * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvCpltCallback must be implemented in the user file. */ } /** * @brief Conversion DMA half-transfer callback in non blocking mode * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. */ } /** * @brief Analog watchdog callback in non blocking mode. * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. */ } /** * @brief ADC error callback in non blocking mode * (ADC conversion with interruption or transfer by DMA) * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ErrorCallback must be implemented in the user file. */ } /** * @} */ /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions * @brief Peripheral Control functions * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Configure channels on regular group (+) Configure the analog watchdog @endverbatim * @{ */ /** * @brief Configures the the selected channel to be linked to the regular * group. * @note In case of usage of internal measurement channels: * Vbat/VrefInt/TempSensor. * These internal paths can be be disabled using function * HAL_ADC_DeInit(). * @note Possibility to update parameters on the fly: * This function initializes channel into regular group, following * calls to this function can be used to reconfigure some parameters * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting * the ADC. * The setting of these parameters is conditioned to ADC state. * For parameters constraints, see comments of structure * "ADC_ChannelConfTypeDef". * @param hadc: ADC handle * @param sConfig: Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; __IO uint32_t wait_loop_index = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); /* Regular sequence configuration */ /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) { MODIFY_REG(hadc->Instance->SQR3 , ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13U) { MODIFY_REG(hadc->Instance->SQR2 , ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank) , ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 13 to 16 */ else { MODIFY_REG(hadc->Instance->SQR1 , ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank) , ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) ); } /* Channel sampling time configuration */ /* For channels 10 to 17 */ if (sConfig->Channel >= ADC_CHANNEL_10) { MODIFY_REG(hadc->Instance->SMPR1 , ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2 , ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel) , ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT) ) { /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ /* measurement channels (VrefInt/TempSensor). If these channels are */ /* intended to be set on other ADC instances, an error is reported. */ if (hadc->Instance == ADC1) { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); while(wait_loop_index != 0U) { wait_loop_index--; } } } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Configures the analog watchdog. * @note Analog watchdog thresholds can be modified while ADC conversion * is on going. * In this case, some constraints must be taken into account: * the programmed threshold values are effective from the next * ADC EOC (end of unitary conversion). * Considering that registers write delay may happen due to * bus activity, this might cause an uncertainty on the * effective timing of the new programmed threshold values. * @param hadc: ADC handle * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); assert_param(IS_ADC_RANGE(AnalogWDGConfig->HighThreshold)); assert_param(IS_ADC_RANGE(AnalogWDGConfig->LowThreshold)); if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) ) { assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); } /* Process locked */ __HAL_LOCK(hadc); /* Analog watchdog configuration */ /* Configure ADC Analog watchdog interrupt */ if(AnalogWDGConfig->ITMode == ENABLE) { /* Enable the ADC Analog watchdog interrupt */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); } else { /* Disable the ADC Analog watchdog interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD); } /* Configuration of analog watchdog: */ /* - Set the analog watchdog enable mode: regular and/or injected groups, */ /* one or all channels. */ /* - Set the Analog watchdog channel (is not used if watchdog */ /* mode "all channels": ADC_CFGR_AWD1SGL=0). */ MODIFY_REG(hadc->Instance->CR1 , ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDCH , AnalogWDGConfig->WatchdogMode | AnalogWDGConfig->Channel ); /* Set the high threshold */ WRITE_REG(hadc->Instance->HTR, AnalogWDGConfig->HighThreshold); /* Set the low threshold */ WRITE_REG(hadc->Instance->LTR, AnalogWDGConfig->LowThreshold); /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions * @brief Peripheral State functions * @verbatim =============================================================================== ##### Peripheral State and Errors functions ##### =============================================================================== [..] This subsection provides functions to get in run-time the status of the peripheral. (+) Check the ADC state (+) Check the ADC error code @endverbatim * @{ */ /** * @brief return the ADC state * @param hadc: ADC handle * @retval HAL state */ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) { /* Return ADC state */ return hadc->State; } /** * @brief Return the ADC error code * @param hadc: ADC handle * @retval ADC Error Code */ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) { return hadc->ErrorCode; } /** * @} */ /** * @} */ /** @defgroup ADC_Private_Functions ADC Private Functions * @{ */ /** * @brief Enable the selected ADC. * @note Prerequisite condition to use this function: ADC must be disabled * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { uint32_t tickstart = 0U; __IO uint32_t wait_loop_index = 0U; /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (ADC_IS_ENABLE(hadc) == RESET) { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); while(wait_loop_index != 0U) { wait_loop_index--; } /* Get tick count */ tickstart = HAL_GetTick(); /* Wait for ADC effectively enabled */ while(ADC_IS_ENABLE(hadc) == RESET) { if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) == RESET) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } } } } /* Return HAL status */ return HAL_OK; } /** * @brief Stop ADC conversion and disable the selected ADC * @note Prerequisite condition to use this function: ADC conversions must be * stopped to disable the ADC. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { uint32_t tickstart = 0U; /* Verification if ADC is not already disabled */ if (ADC_IS_ENABLE(hadc) != RESET) { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); /* Get tick count */ tickstart = HAL_GetTick(); /* Wait for ADC effectively disabled */ while(ADC_IS_ENABLE(hadc) != RESET) { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) != RESET) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); return HAL_ERROR; } } } } /* Return HAL status */ return HAL_OK; } /** * @brief DMA transfer complete callback. * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) { /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && (hadc->Init.ContinuousConvMode == DISABLE) ) { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } else { /* Call DMA error callback */ hadc->DMA_Handle->XferErrorCallback(hdma); } } /** * @brief DMA half transfer complete callback. * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else HAL_ADC_ConvHalfCpltCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } /** * @brief DMA error callback * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAError(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } /** * @} */ #endif /* HAL_ADC_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/ISKv1/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c
New file @@ -0,0 +1,1337 @@ /** ****************************************************************************** * @file stm32f1xx_hal_adc_ex.c * @author MCD Application Team * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: * + Operation functions * ++ Start, stop, get result of conversions of injected * group, using 2 possible modes: polling, interruption. * ++ Multimode feature (available on devices with 2 ADCs or more) * ++ Calibration (ADC automatic self-calibration) * + Control functions * ++ Channels configuration on injected group * Other functions (generic functions) are available in file * "stm32f1xx_hal_adc.c". * @verbatim [..] (@) Sections "ADC peripheral features" and "How to use this driver" are available in file of generic functions "stm32f1xx_hal_adc.c". [..] @endverbatim ****************************************************************************** * @attention * * <h2><center>© Copyright (c) 2016 STMicroelectronics. * All rights reserved.</center></h2> * * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @defgroup ADCEx ADCEx * @brief ADC Extension HAL module driver * @{ */ #ifdef HAL_ADC_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup ADCEx_Private_Constants ADCEx Private Constants * @{ */ /* Delay for ADC calibration: */ /* Hardware prerequisite before starting a calibration: the ADC must have */ /* been in power-on state for at least two ADC clock cycles. */ /* Unit: ADC clock cycles */ #define ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES 2U /* Timeout value for ADC calibration */ /* Value defined to be higher than worst cases: low clocks freq, */ /* maximum prescaler. */ /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */ /* Unit: ms */ #define ADC_CALIBRATION_TIMEOUT 10U /* Delay for temperature sensor stabilization time. */ /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ /* Unit: us */ #define ADC_TEMPSENSOR_DELAY_US 10U /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions * @{ */ /** @defgroup ADCEx_Exported_Functions_Group1 Extended Extended IO operation functions * @brief Extended Extended Input and Output operation functions * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Start conversion of injected group. (+) Stop conversion of injected group. (+) Poll for conversion complete on injected group. (+) Get result of injected channel conversion. (+) Start conversion of injected group and enable interruptions. (+) Stop conversion of injected group and disable interruptions. (+) Start multimode and enable DMA transfer. (+) Stop multimode and disable ADC DMA transfer. (+) Get result of multimode conversion. (+) Perform the ADC self-calibration for single or differential ending. (+) Get calibration factors for single or differential ending. (+) Set calibration factors for single or differential ending. @endverbatim * @{ */ /** * @brief Perform an ADC automatic self-calibration * Calibration prerequisite: ADC must be disabled (execute this * function before HAL_ADC_Start() or after HAL_ADC_Stop() ). * During calibration process, ADC is enabled. ADC is let enabled at * the completion of this function. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tickstart; __IO uint32_t wait_loop_index = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* 1. Calibration prerequisite: */ /* - ADC must be disabled for at least two ADC clock cycles in disable */ /* mode before ADC enable */ /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); /* Hardware prerequisite: delay before starting the calibration. */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles. */ /* - Wait for the expected ADC clock cycles delay */ wait_loop_index = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ); while(wait_loop_index != 0U) { wait_loop_index--; } /* 2. Enable the ADC peripheral */ ADC_Enable(hadc); /* 3. Resets ADC calibration registers */ SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL); tickstart = HAL_GetTick(); /* Wait for calibration reset completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } } } /* 4. Start ADC calibration */ SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL); tickstart = HAL_GetTick(); /* Wait for calibration completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Enables ADC, starts conversion of injected group. * Interruptions enabled in this function: None. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ /* - Clear state bitfield related to injected group conversion results */ /* - Set state bitfield related to injected operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); /* Case of independent mode or multimode (for devices with several ADCs): */ /* Set multimode state. */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } else { SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } /* Check if a regular conversion is ongoing */ /* Note: On this device, there is no ADC error code fields related to */ /* conversions on group injected only. In case of conversion on */ /* going on group regular, no error code is reset. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Clear injected group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); /* Enable conversion of injected group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* If automatic injected conversion is enabled, conversion will start */ /* after next regular group conversion. */ /* Case of multimode enabled (for devices with several ADCs): if ADC is */ /* slave, ADC is enabled only (conversion is not started). If ADC is */ /* master, ADC is enabled and conversion is started. */ if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)) { if (ADC_IS_SOFTWARE_START_INJECTED(hadc) && ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) { /* Start ADC conversion on injected group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG)); } else { /* Start ADC conversion on injected group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG); } } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } /* Return function status */ return tmp_hal_status; } /** * @brief Stop conversion of injected channels. Disable ADC peripheral if * no regular conversion is on going. * @note If ADC must be disabled and if conversion is on going on * regular group, function HAL_ADC_Stop must be used to stop both * injected and regular groups, and disable the ADC. * @note If injected group mode auto-injection is enabled, * function HAL_ADC_Stop must be used. * @note In case of auto-injection mode, HAL_ADC_Stop must be used. * @param hadc: ADC handle * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Stop potential conversion and disable ADC peripheral */ /* Conditioned to: */ /* - No conversion on the other group (regular group) is intended to */ /* continue (injected and regular groups stop conversion and ADC disable */ /* are common) */ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) { /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Wait for injected group conversion to be completed. * @param hadc: ADC handle * @param Timeout: Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) { uint32_t tickstart; /* Variables for polling in case of scan mode enabled and polling for each */ /* conversion. */ __IO uint32_t Conversion_Timeout_CPU_cycles = 0U; uint32_t Conversion_Timeout_CPU_cycles_max = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Get timeout */ tickstart = HAL_GetTick(); /* Polling for end of conversion: differentiation if single/sequence */ /* conversion. */ /* For injected group, flag JEOC is set only at the end of the sequence, */ /* not for each conversion within the sequence. */ /* - If single conversion for injected group (scan mode disabled or */ /* InjectedNbrOfConversion ==1), flag JEOC is used to determine the */ /* conversion completion. */ /* - If sequence conversion for injected group (scan mode enabled and */ /* InjectedNbrOfConversion >=2), flag JEOC is set only at the end of the */ /* sequence. */ /* To poll for each conversion, the maximum conversion time is computed */ /* from ADC conversion time (selected sampling time + conversion time of */ /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */ /* settings, conversion time range can be from 28 to 32256 CPU cycles). */ /* As flag JEOC is not set after each conversion, no timeout status can */ /* be set. */ if ((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET) { /* Wait until End of Conversion flag is raised */ while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC)) { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_TIMEOUT; } } } } } else { /* Replace polling by wait for maximum conversion time */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles */ /* and ADC maximum conversion cycles on all channels. */ /* - Wait for the expected ADC clock cycles delay */ Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) * ADC_CONVCYCLES_MAX_RANGE(hadc) ); while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* New check to avoid false timeout detection in case of preemption */ if(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_TIMEOUT; } } } Conversion_Timeout_CPU_cycles ++; } } /* Clear injected group conversion flag */ /* Note: On STM32F1 ADC, clear regular conversion flag raised */ /* simultaneously. */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC | ADC_FLAG_EOC); /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); /* Determine whether any further conversion upcoming on group injected */ /* by external trigger or by automatic injected conversion */ /* from group regular. */ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && (ADC_IS_SOFTWARE_START_REGULAR(hadc) && (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } /* Return ADC state */ return HAL_OK; } /** * @brief Enables ADC, starts conversion of injected group with interruption. * - JEOC (end of conversion of injected group) * Each of these interruptions has its dedicated callback function. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ /* - Clear state bitfield related to injected group conversion results */ /* - Set state bitfield related to injected operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); /* Case of independent mode or multimode (for devices with several ADCs): */ /* Set multimode state. */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } else { SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } /* Check if a regular conversion is ongoing */ /* Note: On this device, there is no ADC error code fields related to */ /* conversions on group injected only. In case of conversion on */ /* going on group regular, no error code is reset. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Clear injected group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); /* Enable end of conversion interrupt for injected channels */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); /* Start conversion of injected group if software start has been selected */ /* and if automatic injected conversion is disabled. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* If automatic injected conversion is enabled, conversion will start */ /* after next regular group conversion. */ if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)) { if (ADC_IS_SOFTWARE_START_INJECTED(hadc) && ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) { /* Start ADC conversion on injected group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG)); } else { /* Start ADC conversion on injected group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG); } } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } /* Return function status */ return tmp_hal_status; } /** * @brief Stop conversion of injected channels, disable interruption of * end-of-conversion. Disable ADC peripheral if no regular conversion * is on going. * @note If ADC must be disabled and if conversion is on going on * regular group, function HAL_ADC_Stop must be used to stop both * injected and regular groups, and disable the ADC. * @note If injected group mode auto-injection is enabled, * function HAL_ADC_Stop must be used. * @param hadc: ADC handle * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Stop potential conversion and disable ADC peripheral */ /* Conditioned to: */ /* - No conversion on the other group (regular group) is intended to */ /* continue (injected and regular groups stop conversion and ADC disable */ /* are common) */ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) { /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Disable ADC end of conversion interrupt for injected channels */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) /** * @brief Enables ADC, starts conversion of regular group and transfers result * through DMA. * Multimode must have been previously configured using * HAL_ADCEx_MultiModeConfigChannel() function. * Interruptions enabled in this function: * - DMA transfer complete * - DMA half transfer * Each of these interruptions has its dedicated callback function. * @note: On STM32F1 devices, ADC slave regular group must be configured * with conversion trigger ADC_SOFTWARE_START. * @note: ADC slave can be enabled preliminarily using single-mode * HAL_ADC_Start() function. * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used) * @param pData: The destination Buffer address. * @param Length: The length of data to be transferred from ADC peripheral to memory. * @retval None */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; ADC_HandleTypeDef tmphadcSlave={0}; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); /* Process locked */ __HAL_LOCK(hadc); /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); /* On STM32F1 devices, ADC slave regular group must be configured with */ /* conversion trigger ADC_SOFTWARE_START. */ /* Note: External trigger of ADC slave must be enabled, it is already done */ /* into function "HAL_ADC_Init()". */ if(!ADC_IS_SOFTWARE_START_REGULAR(&tmphadcSlave)) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } /* Enable the ADC peripherals: master and slave (in case if not already */ /* enabled previously) */ tmp_hal_status = ADC_Enable(hadc); if (tmp_hal_status == HAL_OK) { tmp_hal_status = ADC_Enable(&tmphadcSlave); } /* Start conversion if all ADCs of multimode are effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state (ADC master) */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_MULTIMODE_SLAVE, HAL_ADC_STATE_REG_BUSY); /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ /* start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); /* Enable ADC DMA mode of ADC master */ SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA); /* Start the DMA channel */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); /* Start conversion of regular group if software start has been selected. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Note: Alternate trigger for single conversion could be to force an */ /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } /* Return function status */ return tmp_hal_status; } /** * @brief Stop ADC conversion of regular group (and injected channels in * case of auto_injection mode), disable ADC DMA transfer, disable * ADC peripheral. * @note Multimode is kept enabled after this function. To disable multimode * (set with HAL_ADCEx_MultiModeConfigChannel(), ADC must be * reinitialized using HAL_ADC_Init() or HAL_ADC_ReInit(). * @note In case of DMA configured in circular mode, function * HAL_ADC_Stop_DMA must be called after this function with handle of * ADC slave, to properly disable the DMA channel. * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used) * @retval None */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; ADC_HandleTypeDef tmphadcSlave={0}; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC master peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ if(tmp_hal_status == HAL_OK) { /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); /* Disable ADC slave peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(&tmphadcSlave); /* Check if ADC is effectively disabled */ if(tmp_hal_status != HAL_OK) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } /* Disable ADC DMA mode */ CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA); /* Reset configuration of ADC DMA continuous request for dual mode */ CLEAR_BIT(hadc->Instance->CR1, ADC_CR1_DUALMOD); /* Disable the DMA channel (in case of DMA in circular mode or stop while */ /* while DMA transfer is on going) */ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); /* Change ADC state (ADC master) */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @brief Get ADC injected group conversion result. * @note Reading register JDRx automatically clears ADC flag JEOC * (ADC group injected end of unitary conversion). * @note This function does not clear ADC flag JEOS * (ADC group injected end of sequence conversion) * Occurrence of flag JEOS rising: * - If sequencer is composed of 1 rank, flag JEOS is equivalent * to flag JEOC. * - If sequencer is composed of several ranks, during the scan * sequence flag JEOC only is raised, at the end of the scan sequence * both flags JEOC and EOS are raised. * Flag JEOS must not be cleared by this function because * it would not be compliant with low power features * (feature low power auto-wait, not available on all STM32 families). * To clear this flag, either use function: * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming * model polling: @ref HAL_ADCEx_InjectedPollForConversion() * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS). * @param hadc: ADC handle * @param InjectedRank: the converted ADC injected rank. * This parameter can be one of the following values: * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected * @retval ADC group injected conversion data */ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank) { uint32_t tmp_jdr = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_INJECTED_RANK(InjectedRank)); /* Get ADC converted value */ switch(InjectedRank) { case ADC_INJECTED_RANK_4: tmp_jdr = hadc->Instance->JDR4; break; case ADC_INJECTED_RANK_3: tmp_jdr = hadc->Instance->JDR3; break; case ADC_INJECTED_RANK_2: tmp_jdr = hadc->Instance->JDR2; break; case ADC_INJECTED_RANK_1: default: tmp_jdr = hadc->Instance->JDR1; break; } /* Return ADC converted value */ return tmp_jdr; } #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) /** * @brief Returns the last ADC Master&Slave regular conversions results data * in the selected multi mode. * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used) * @retval The converted data value. */ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) { uint32_t tmpDR = 0U; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Note: EOC flag is not cleared here by software because automatically */ /* cleared by hardware when reading register DR. */ /* On STM32F1 devices, ADC1 data register DR contains ADC2 conversions */ /* only if ADC1 DMA mode is enabled. */ tmpDR = hadc->Instance->DR; if (HAL_IS_BIT_CLR(ADC1->CR2, ADC_CR2_DMA)) { tmpDR |= (ADC2->DR << 16U); } /* Return ADC converted value */ return tmpDR; } #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @brief Injected conversion complete callback in non blocking mode * @param hadc: ADC handle * @retval None */ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file */ } /** * @} */ /** @defgroup ADCEx_Exported_Functions_Group2 Extended Peripheral Control functions * @brief Extended Peripheral Control functions * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Configure channels on injected group (+) Configure multimode @endverbatim * @{ */ /** * @brief Configures the ADC injected group and the selected channel to be * linked to the injected group. * @note Possibility to update parameters on the fly: * This function initializes injected group, following calls to this * function can be used to reconfigure some parameters of structure * "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC. * The setting of these parameters is conditioned to ADC state: * this function must be called when ADC is not under conversion. * @param hadc: ADC handle * @param sConfigInjected: Structure of ADC injected group and ADC channel for * injected group. * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; __IO uint32_t wait_loop_index = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel)); assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv)); assert_param(IS_ADC_RANGE(sConfigInjected->InjectedOffset)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) { assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); } /* Process locked */ __HAL_LOCK(hadc); /* Configuration of injected group sequencer: */ /* - if scan mode is disabled, injected channels sequence length is set to */ /* 0x00: 1 channel converted (channel on regular rank 1) */ /* Parameter "InjectedNbrOfConversion" is discarded. */ /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, injected channels sequence length is set to */ /* parameter "InjectedNbrOfConversion". */ if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) { if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1) { /* Clear the old SQx bits for all injected ranks */ MODIFY_REG(hadc->Instance->JSQR , ADC_JSQR_JL | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 , ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1, 0x01U)); } /* If another injected rank than rank1 was intended to be set, and could */ /* not due to ScanConvMode disabled, error is reported. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } } else { /* Since injected channels rank conv. order depends on total number of */ /* injected conversions, selected rank must be below or equal to total */ /* number of injected conversions to be updated. */ if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion) { /* Clear the old SQx bits for the selected rank */ /* Set the SQx bits for the selected rank */ MODIFY_REG(hadc->Instance->JSQR , ADC_JSQR_JL | ADC_JSQR_RK_JL(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank, sConfigInjected->InjectedNbrOfConversion) , ADC_JSQR_JL_SHIFT(sConfigInjected->InjectedNbrOfConversion) | ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank, sConfigInjected->InjectedNbrOfConversion) ); } else { /* Clear the old SQx bits for the selected rank */ MODIFY_REG(hadc->Instance->JSQR , ADC_JSQR_JL | ADC_JSQR_RK_JL(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank, sConfigInjected->InjectedNbrOfConversion) , 0x00000000U); } } /* Configuration of injected group */ /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - external trigger to start conversion */ /* Parameters update not conditioned to ADC state: */ /* - Automatic injected conversion */ /* - Injected discontinuous mode */ /* Note: In case of ADC already enabled, caution to not launch an unwanted */ /* conversion while modifying register CR2 by writing 1 to bit ADON. */ if (ADC_IS_ENABLE(hadc) == RESET) { MODIFY_REG(hadc->Instance->CR2 , ADC_CR2_JEXTSEL | ADC_CR2_ADON , ADC_CFGR_JEXTSEL(hadc, sConfigInjected->ExternalTrigInjecConv) ); } /* Configuration of injected group */ /* - Automatic injected conversion */ /* - Injected discontinuous mode */ /* Automatic injected conversion can be enabled if injected group */ /* external triggers are disabled. */ if (sConfigInjected->AutoInjectedConv == ENABLE) { if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START) { SET_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO); } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } } /* Injected discontinuous can be enabled only if auto-injected mode is */ /* disabled. */ if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) { if (sConfigInjected->AutoInjectedConv == DISABLE) { SET_BIT(hadc->Instance->CR1, ADC_CR1_JDISCEN); } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } } /* InjectedChannel sampling time configuration */ /* For channels 10 to 17 */ if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10) { MODIFY_REG(hadc->Instance->SMPR1 , ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel) , ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) ); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2 , ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel) , ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) ); } /* If ADC1 InjectedChannel_16 or InjectedChannel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) ) { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); } /* Configure the offset: offset enable/disable, InjectedChannel, offset value */ switch(sConfigInjected->InjectedRank) { case 1: /* Set injected channel 1 offset */ MODIFY_REG(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1, sConfigInjected->InjectedOffset); break; case 2: /* Set injected channel 2 offset */ MODIFY_REG(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2, sConfigInjected->InjectedOffset); break; case 3: /* Set injected channel 3 offset */ MODIFY_REG(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3, sConfigInjected->InjectedOffset); break; case 4: default: MODIFY_REG(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4, sConfigInjected->InjectedOffset); break; } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) ) { /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ /* measurement channels (VrefInt/TempSensor). If these channels are */ /* intended to be set on other ADC instances, an error is reported. */ if (hadc->Instance == ADC1) { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR)) { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); while(wait_loop_index != 0U) { wait_loop_index--; } } } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) /** * @brief Enable ADC multimode and configure multimode parameters * @note Possibility to update parameters on the fly: * This function initializes multimode parameters, following * calls to this function can be used to reconfigure some parameters * of structure "ADC_MultiModeTypeDef" on the fly, without reseting * the ADCs (both ADCs of the common group). * The setting of these parameters is conditioned to ADC state. * For parameters constraints, see comments of structure * "ADC_MultiModeTypeDef". * @note To change back configuration from multimode to single mode, ADC must * be reset (using function HAL_ADC_Init() ). * @param hadc: ADC handle * @param multimode: Structure of ADC multimode configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; ADC_HandleTypeDef tmphadcSlave={0}; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); assert_param(IS_ADC_MODE(multimode->Mode)); /* Process locked */ __HAL_LOCK(hadc); /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - ADC master and ADC slave DMA configuration */ /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode mode selection */ /* To optimize code, all multimode settings can be set when both ADCs of */ /* the common group are in state: disabled. */ if ((ADC_IS_ENABLE(hadc) == RESET) && (ADC_IS_ENABLE(&tmphadcSlave) == RESET) && (IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)) ) { MODIFY_REG(hadc->Instance->CR1, ADC_CR1_DUALMOD , multimode->Mode ); } /* If one of the ADC sharing the same common group is enabled, no update */ /* could be done on neither of the multimode structure parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @} */ /** * @} */ #endif /* HAL_ADC_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
