Update u-boot patch, modify LPDDR4 size to 2GB and fix PMIC not work in SPL...

guowenxue

2023-12-20 7640c6f7327a1de96802076cd6fa652dfc3b7548

Update u-boot patch, modify LPDDR4 size to 2GB and fix PMIC not work in SPL stage

Signed-off-by: guowenxue <guowenxue@gmail.com>

 bootloader/patches/igkboard-imx8mp/uboot-imx-lf-6.1.36-2.1.0.patch

@@ -24,10 +24,10 @@
     imx8mm-ddr4-ab2.dtb \
diff --git a/arch/arm/dts/igkboard-imx8mp-u-boot.dtsi b/arch/arm/dts/igkboard-imx8mp-u-boot.dtsi
new file mode 100644
index 00000000..202e5307
index 00000000..b69049bb
--- /dev/null
+++ b/arch/arm/dts/igkboard-imx8mp-u-boot.dtsi
@@ -0,0 +1,74 @@
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copy from imx8mp-venice-u-boot.dtsi
@@ -102,9 +102,21 @@
+&pinctrl_wdog {
+    u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
+    u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
+    u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+    u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/igkboard-imx8mp.dts b/arch/arm/dts/igkboard-imx8mp.dts
new file mode 100644
index 00000000..a21acb92
index 00000000..523d5f32
--- /dev/null
+++ b/arch/arm/dts/igkboard-imx8mp.dts
@@ -0,0 +1,486 @@
@@ -131,7 +143,7 @@
+        stdout-path = &uart2;
+    };
+
+    /* MT53D512M32D2DS-053 WT:D, 8GB LPDDR4 */
+    /* MT53D512M32D2DS-053 WT:D, 2GB LPDDR4 */
+    memory@80000000 {
+        device_type = "memory";
+        reg = <0x0 0x80000000 0 0x80000000>;
@@ -3745,10 +3757,10 @@
++CONFIG_SYS_NAND_ONFI_DETECTION=y
diff --git a/include/configs/igkboard-imx8mp.h b/include/configs/igkboard-imx8mp.h
new file mode 100644
index 00000000..bc2686b2
index 00000000..16a4cb9b
--- /dev/null
+++ b/include/configs/igkboard-imx8mp.h
@@ -0,0 +1,189 @@
@@ -0,0 +1,183 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
@@ -3912,20 +3924,14 @@
+#define CFG_SYS_INIT_RAM_SIZE    0x80000
+
+
+/* Totally 6GB DDR */
+/* Totally 2GB DDR */
+#define CFG_SYS_SDRAM_BASE        0x40000000
+#define PHYS_SDRAM            0x40000000
+#define PHYS_SDRAM_SIZE            0xC0000000    /* 3 GB */
+#define PHYS_SDRAM_2            0x100000000
+#ifdef CONFIG_TARGET_IMX8MP_DDR4_EVK
+#define PHYS_SDRAM_2_SIZE        0x40000000    /* 1 GB */
+#else
+#define PHYS_SDRAM_2_SIZE        0xC0000000    /* 3 GB */
+#endif
+#define PHYS_SDRAM                0x40000000
+#define PHYS_SDRAM_SIZE            0x80000000    /* 2 GB */
+
+#define CFG_MXC_UART_BASE        UART2_BASE_ADDR
+
+#define CFG_SYS_NAND_BASE           0x20000000
+#define CFG_SYS_NAND_BASE       0x20000000
+
+#ifdef CONFIG_TARGET_IMX8MP_DDR4_EVK
+#define CFG_SYS_FSL_USDHC_NUM    1