| New file | 
 |  |  | 
 |  |  | diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile | 
 |  |  | index 7b1a129e6..1d5c6e770 100644 | 
 |  |  | --- a/arch/arm64/boot/dts/freescale/Makefile | 
 |  |  | +++ b/arch/arm64/boot/dts/freescale/Makefile | 
 |  |  | @@ -412,3 +412,5 @@ dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb \ | 
 |  |  |                s32v234-sbc.dtb | 
 |  |  |  dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek-sof-cs42888.dtb imx8qm-mek-sof-wm8960.dtb \ | 
 |  |  |                imx8qm-mek-revd-sof-wm8962.dtb imx8qm-mek-sof.dtb | 
 |  |  | + | 
 |  |  | +dtb-$(CONFIG_ARCH_MXC) += igkboard-imx8mp.dtb | 
 |  |  | diff --git a/arch/arm64/boot/dts/freescale/igkboard-imx8mp.dts b/arch/arm64/boot/dts/freescale/igkboard-imx8mp.dts | 
 |  |  | new file mode 100644 | 
 |  |  | index 000000000..cddc94704 | 
 |  |  | --- /dev/null | 
 |  |  | +++ b/arch/arm64/boot/dts/freescale/igkboard-imx8mp.dts | 
 |  |  | @@ -0,0 +1,475 @@ | 
 |  |  | +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) | 
 |  |  | +/* | 
 |  |  | + * Copyright 2023 LingYun IoT System Studio. | 
 |  |  | + */ | 
 |  |  | + | 
 |  |  | +/dts-v1/; | 
 |  |  | + | 
 |  |  | +#include <dt-bindings/usb/pd.h> | 
 |  |  | +#include "imx8mp.dtsi" | 
 |  |  | + | 
 |  |  | +/*+------------------------+ | 
 |  |  | +  |       root node        | | 
 |  |  | +  +------------------------+*/ | 
 |  |  | +/ { | 
 |  |  | +    model = "LingYun IoT Gateway Kits Board based on i.MX8MP"; | 
 |  |  | +    compatible = "lingyun,igkboard-imx8mp", "fsl,imx8mp"; | 
 |  |  | + | 
 |  |  | +    /* console and bootargs */ | 
 |  |  | +    chosen { | 
 |  |  | +        bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; | 
 |  |  | +        stdout-path = &uart2; | 
 |  |  | +    }; | 
 |  |  | + | 
 |  |  | +    /* MT53D512M32D2DS-053 WT:D, 2GB LPDDR4 */ | 
 |  |  | +    memory@80000000 { | 
 |  |  | +        device_type = "memory"; | 
 |  |  | +        reg = <0x0 0x80000000 0 0x80000000>; | 
 |  |  | +    }; | 
 |  |  | + | 
 |  |  | +    leds { | 
 |  |  | +        compatible = "gpio-leds"; | 
 |  |  | +        pinctrl-names = "default"; | 
 |  |  | +        pinctrl-0 = <&pinctrl_leds>; | 
 |  |  | +        status = "okay"; | 
 |  |  | + | 
 |  |  | +        sysled { | 
 |  |  | +            label = "sysled"; | 
 |  |  | +            gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; | 
 |  |  | +            default-state = "on"; | 
 |  |  | +        }; | 
 |  |  | +    }; | 
 |  |  | +}; | 
 |  |  | + | 
 |  |  | +/*+------------------------+ | 
 |  |  | +  |   power key & reset    | | 
 |  |  | +  +------------------------+*/ | 
 |  |  | + | 
 |  |  | +&snvs_pwrkey { | 
 |  |  | +    status = "okay"; | 
 |  |  | +}; | 
 |  |  | + | 
 |  |  | +&wdog1 { | 
 |  |  | +    pinctrl-names = "default"; | 
 |  |  | +    pinctrl-0 = <&pinctrl_wdog>; | 
 |  |  | +    fsl,ext-reset-output; | 
 |  |  | +    status = "okay"; | 
 |  |  | +}; | 
 |  |  | + | 
 |  |  | +/*+------------------------+ | 
 |  |  | +  |    console usart2      | | 
 |  |  | +  +------------------------+*/ | 
 |  |  | +&uart2 { | 
 |  |  | +    pinctrl-names = "default"; | 
 |  |  | +    pinctrl-0 = <&pinctrl_uart2>; | 
 |  |  | +    status = "okay"; | 
 |  |  | +}; | 
 |  |  | + | 
 |  |  | +/*+------------------------+ | 
 |  |  | +  |    8GB eMMC on SD3     | | 
 |  |  | +  +------------------------+*/ | 
 |  |  | + | 
 |  |  | +/* KLM8G1GETF-B041 8GB eMMC */ | 
 |  |  | +&usdhc3 { | 
 |  |  | +    pinctrl-names = "default", "state_100mhz", "state_200mhz"; | 
 |  |  | +    pinctrl-0 = <&pinctrl_usdhc3>; | 
 |  |  | +    pinctrl-1 = <&pinctrl_usdhc3_100mhz>; | 
 |  |  | +    pinctrl-2 = <&pinctrl_usdhc3_200mhz>; | 
 |  |  | +    bus-width = <8>; | 
 |  |  | +    non-removable; | 
 |  |  | +    status = "okay"; | 
 |  |  | +}; | 
 |  |  | + | 
 |  |  | +/*+------------------------+ | 
 |  |  | +  |     TF Card on SD2     | | 
 |  |  | +  +------------------------+*/ | 
 |  |  | + | 
 |  |  | +&usdhc2 { | 
 |  |  | +    pinctrl-names = "default", "state_100mhz", "state_200mhz"; | 
 |  |  | +    pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; | 
 |  |  | +    pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; | 
 |  |  | +    pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; | 
 |  |  | +    cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; | 
 |  |  | +    bus-width = <4>; | 
 |  |  | +    no-1-8-v; | 
 |  |  | +    status = "okay"; | 
 |  |  | +}; | 
 |  |  | + | 
 |  |  | +/*+------------------------+ | 
 |  |  | +  | Typec USB for download | | 
 |  |  | +  +------------------------+*/ | 
 |  |  | + | 
 |  |  | +&usb3_phy0 { | 
 |  |  | +    fsl,phy-tx-vref-tune = <6>; | 
 |  |  | +    fsl,phy-tx-rise-tune = <0>; | 
 |  |  | +    fsl,phy-tx-preemp-amp-tune = <3>; | 
 |  |  | +    fsl,phy-comp-dis-tune = <7>; | 
 |  |  | +    fsl,pcs-tx-deemph-3p5db = <0x21>; | 
 |  |  | +    fsl,phy-pcs-tx-swing-full = <0x7f>; | 
 |  |  | +    status = "okay"; | 
 |  |  | +}; | 
 |  |  | + | 
 |  |  | +&usb3_0 { | 
 |  |  | +    status = "okay"; | 
 |  |  | +}; | 
 |  |  | + | 
 |  |  | +&usb_dwc3_0 { | 
 |  |  | +    dr_mode = "peripheral"; | 
 |  |  | +    hnp-disable; | 
 |  |  | +    srp-disable; | 
 |  |  | +    adp-disable; | 
 |  |  | +    status = "okay"; | 
 |  |  | +}; | 
 |  |  | + | 
 |  |  | +/*+------------------------+ | 
 |  |  | +  | 2xUSB Host on USB Hub  | | 
 |  |  | +  +------------------------+*/ | 
 |  |  | + | 
 |  |  | +/* Renesas USB 3.0 Hub uPD720210 */ | 
 |  |  | +&usb3_phy1 { | 
 |  |  | +    fsl,phy-tx-preemp-amp-tune = <2>; | 
 |  |  | +    status = "okay"; | 
 |  |  | +}; | 
 |  |  | + | 
 |  |  | +&usb3_1 { | 
 |  |  | +    status = "okay"; | 
 |  |  | +}; | 
 |  |  | + | 
 |  |  | +&usb_dwc3_1 { | 
 |  |  | +    dr_mode = "host"; | 
 |  |  | +    status = "okay"; | 
 |  |  | +}; | 
 |  |  | + | 
 |  |  | +/*+------------------------+ | 
 |  |  | +  |        Ethernet        | | 
 |  |  | +  +------------------------+*/ | 
 |  |  | + | 
 |  |  | +/* First 1000Mbps Ethernet For TSN on ENET */ | 
 |  |  | +&eqos { | 
 |  |  | +    pinctrl-names = "default"; | 
 |  |  | +    pinctrl-0 = <&pinctrl_eqos>; | 
 |  |  | +    phy-mode = "rgmii-id"; | 
 |  |  | +    phy-handle = <ðphy0>; | 
 |  |  | +    snps,reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; | 
 |  |  | +    snps,reset-delays-us = <100000 200000 150000>; | 
 |  |  | +    status = "okay"; | 
 |  |  | + | 
 |  |  | +    mdio { | 
 |  |  | +        compatible = "snps,dwmac-mdio"; | 
 |  |  | +        #address-cells = <1>; | 
 |  |  | +        #size-cells = <0>; | 
 |  |  | + | 
 |  |  | +        ethphy0: ethernet-phy@0 { /* YT8521SH-CA */ | 
 |  |  | +            compatible = "ethernet-phy-ieee802.3-c22"; | 
 |  |  | +            reg = <0>; | 
 |  |  | +            eee-broken-1000t; | 
 |  |  | +        }; | 
 |  |  | +    }; | 
 |  |  | +}; | 
 |  |  | + | 
 |  |  | +/* Second 1000Mbps Ethernet on ENET1 */ | 
 |  |  | +&fec { | 
 |  |  | +    pinctrl-names = "default"; | 
 |  |  | +    pinctrl-0 = <&pinctrl_fec>; | 
 |  |  | +    phy-mode = "rgmii-id"; | 
 |  |  | +    phy-handle = <ðphy1>; | 
 |  |  | +    phy-reset-duration = <200>; | 
 |  |  | +    phy-reset-post-delay = <150>; | 
 |  |  | +    phy-reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; | 
 |  |  | + | 
 |  |  | +    fsl,magic-packet; | 
 |  |  | +    status = "okay"; | 
 |  |  | + | 
 |  |  | +    mdio { | 
 |  |  | +        #address-cells = <1>; | 
 |  |  | +        #size-cells = <0>; | 
 |  |  | + | 
 |  |  | +        ethphy1: ethernet-phy@0 { /* YT8521SH-CA */ | 
 |  |  | +            compatible = "ethernet-phy-ieee802.3-c22"; | 
 |  |  | +            reg = <0>; | 
 |  |  | +            eee-broken-1000t; | 
 |  |  | +        }; | 
 |  |  | +    }; | 
 |  |  | +}; | 
 |  |  | + | 
 |  |  | +/*+------------------------+ | 
 |  |  | +  |    PCA9450CHN PMIC     | | 
 |  |  | +  +------------------------+*/ | 
 |  |  | + | 
 |  |  | +&i2c1 { | 
 |  |  | +    clock-frequency = <400000>; | 
 |  |  | +    pinctrl-names = "default", "gpio"; | 
 |  |  | +    pinctrl-0 = <&pinctrl_i2c1>; | 
 |  |  | +    pinctrl-1 = <&pinctrl_i2c1_gpio>; | 
 |  |  | +    scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; | 
 |  |  | +    sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; | 
 |  |  | +    status = "okay"; | 
 |  |  | + | 
 |  |  | +    pmic@25 { | 
 |  |  | +        compatible = "nxp,pca9450c"; | 
 |  |  | +        reg = <0x25>; | 
 |  |  | +        pinctrl-names = "default"; | 
 |  |  | +        pinctrl-0 = <&pinctrl_pmic>; | 
 |  |  | +        interrupt-parent = <&gpio1>; | 
 |  |  | +        interrupts = <3 IRQ_TYPE_LEVEL_LOW>; | 
 |  |  | + | 
 |  |  | +        regulators { | 
 |  |  | +            buck1: BUCK1 { | 
 |  |  | +                regulator-name = "BUCK1"; | 
 |  |  | +                regulator-min-microvolt = <600000>; | 
 |  |  | +                regulator-max-microvolt = <2187500>; | 
 |  |  | +                regulator-boot-on; | 
 |  |  | +                regulator-always-on; | 
 |  |  | +                regulator-ramp-delay = <3125>; | 
 |  |  | +            }; | 
 |  |  | + | 
 |  |  | +            buck2: BUCK2 { | 
 |  |  | +                regulator-name = "BUCK2"; | 
 |  |  | +                regulator-min-microvolt = <600000>; | 
 |  |  | +                regulator-max-microvolt = <2187500>; | 
 |  |  | +                regulator-boot-on; | 
 |  |  | +                regulator-always-on; | 
 |  |  | +                regulator-ramp-delay = <3125>; | 
 |  |  | +                nxp,dvs-run-voltage = <950000>; | 
 |  |  | +                nxp,dvs-standby-voltage = <850000>; | 
 |  |  | +            }; | 
 |  |  | + | 
 |  |  | +            buck4: BUCK4{ | 
 |  |  | +                regulator-name = "BUCK4"; | 
 |  |  | +                regulator-min-microvolt = <600000>; | 
 |  |  | +                regulator-max-microvolt = <3400000>; | 
 |  |  | +                regulator-boot-on; | 
 |  |  | +                regulator-always-on; | 
 |  |  | +            }; | 
 |  |  | + | 
 |  |  | +            buck5: BUCK5{ | 
 |  |  | +                regulator-name = "BUCK5"; | 
 |  |  | +                regulator-min-microvolt = <600000>; | 
 |  |  | +                regulator-max-microvolt = <3400000>; | 
 |  |  | +                regulator-boot-on; | 
 |  |  | +                regulator-always-on; | 
 |  |  | +            }; | 
 |  |  | + | 
 |  |  | +            buck6: BUCK6 { | 
 |  |  | +                regulator-name = "BUCK6"; | 
 |  |  | +                regulator-min-microvolt = <600000>; | 
 |  |  | +                regulator-max-microvolt = <3400000>; | 
 |  |  | +                regulator-boot-on; | 
 |  |  | +                regulator-always-on; | 
 |  |  | +            }; | 
 |  |  | + | 
 |  |  | +            ldo1: LDO1 { | 
 |  |  | +                regulator-name = "LDO1"; | 
 |  |  | +                regulator-min-microvolt = <1600000>; | 
 |  |  | +                regulator-max-microvolt = <3300000>; | 
 |  |  | +                regulator-boot-on; | 
 |  |  | +                regulator-always-on; | 
 |  |  | +            }; | 
 |  |  | + | 
 |  |  | +            ldo2: LDO2 { | 
 |  |  | +                regulator-name = "LDO2"; | 
 |  |  | +                regulator-min-microvolt = <800000>; | 
 |  |  | +                regulator-max-microvolt = <1150000>; | 
 |  |  | +                regulator-boot-on; | 
 |  |  | +                regulator-always-on; | 
 |  |  | +            }; | 
 |  |  | + | 
 |  |  | +            ldo3: LDO3 { | 
 |  |  | +                regulator-name = "LDO3"; | 
 |  |  | +                regulator-min-microvolt = <800000>; | 
 |  |  | +                regulator-max-microvolt = <3300000>; | 
 |  |  | +                regulator-boot-on; | 
 |  |  | +                regulator-always-on; | 
 |  |  | +            }; | 
 |  |  | + | 
 |  |  | +            ldo4: LDO4 { | 
 |  |  | +                regulator-name = "LDO4"; | 
 |  |  | +                regulator-min-microvolt = <800000>; | 
 |  |  | +                regulator-max-microvolt = <3300000>; | 
 |  |  | +                regulator-boot-on; | 
 |  |  | +                regulator-always-on; | 
 |  |  | +            }; | 
 |  |  | + | 
 |  |  | +            ldo5: LDO5 { | 
 |  |  | +                regulator-name = "LDO5"; | 
 |  |  | +                regulator-min-microvolt = <1800000>; | 
 |  |  | +                regulator-max-microvolt = <3300000>; | 
 |  |  | +                regulator-boot-on; | 
 |  |  | +                regulator-always-on; | 
 |  |  | +            }; | 
 |  |  | +        }; | 
 |  |  | +    }; | 
 |  |  | +}; | 
 |  |  | + | 
 |  |  | +&iomuxc { | 
 |  |  | +    pinctrl-names = "default"; | 
 |  |  | + | 
 |  |  | +    pinctrl_leds: ledsgrp { | 
 |  |  | +        fsl,pins = < | 
 |  |  | +            MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16                       0x140 | 
 |  |  | +        >; | 
 |  |  | +    }; | 
 |  |  | + | 
 |  |  | +    pinctrl_wdog: wdoggrp { | 
 |  |  | +        fsl,pins = < | 
 |  |  | +            MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B                       0xc6 | 
 |  |  | +        >; | 
 |  |  | +    }; | 
 |  |  | + | 
 |  |  | +    pinctrl_uart2: uart2grp { | 
 |  |  | +        fsl,pins = < | 
 |  |  | +            MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX                        0x49 | 
 |  |  | +            MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX                        0x49 | 
 |  |  | +        >; | 
 |  |  | +    }; | 
 |  |  | + | 
 |  |  | +    pinctrl_i2c1: i2c1grp { | 
 |  |  | +        fsl,pins = < | 
 |  |  | +            MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL                             0x400001c3 | 
 |  |  | +            MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA                             0x400001c3 | 
 |  |  | +        >; | 
 |  |  | +    }; | 
 |  |  | + | 
 |  |  | +    pinctrl_i2c1_gpio: i2c1grp-gpio { | 
 |  |  | +        fsl,pins = < | 
 |  |  | +            MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14                           0x1c3 | 
 |  |  | +            MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15                           0x1c3 | 
 |  |  | +        >; | 
 |  |  | +    }; | 
 |  |  | + | 
 |  |  | +    pinctrl_pmic: pmicirq { | 
 |  |  | +        fsl,pins = < | 
 |  |  | +            MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03                         0x41 | 
 |  |  | +        >; | 
 |  |  | +    }; | 
 |  |  | + | 
 |  |  | +    pinctrl_usdhc2_gpio: usdhc2grp-gpio { | 
 |  |  | +        fsl,pins = < | 
 |  |  | +            MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12                           0x1c4 | 
 |  |  | +        >; | 
 |  |  | +    }; | 
 |  |  | + | 
 |  |  | +    pinctrl_usdhc2: usdhc2grp { | 
 |  |  | +        fsl,pins = < | 
 |  |  | +            MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK                            0x190 | 
 |  |  | +            MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD                            0x1d0 | 
 |  |  | +            MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0                        0x1d0 | 
 |  |  | +            MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1                        0x1d0 | 
 |  |  | +            MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2                        0x1d0 | 
 |  |  | +            MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3                        0x1d0 | 
 |  |  | +            MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT                     0xc1 | 
 |  |  | +        >; | 
 |  |  | +    }; | 
 |  |  | + | 
 |  |  | +    pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { | 
 |  |  | +        fsl,pins = < | 
 |  |  | +            MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK                            0x194 | 
 |  |  | +            MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD                            0x1d4 | 
 |  |  | +            MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0                        0x1d4 | 
 |  |  | +            MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1                        0x1d4 | 
 |  |  | +            MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2                        0x1d4 | 
 |  |  | +            MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3                        0x1d4 | 
 |  |  | +            MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT                     0xc1 | 
 |  |  | +        >; | 
 |  |  | +    }; | 
 |  |  | + | 
 |  |  | +    pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { | 
 |  |  | +        fsl,pins = < | 
 |  |  | +            MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK                            0x196 | 
 |  |  | +            MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD                            0x1d6 | 
 |  |  | +            MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0                        0x1d6 | 
 |  |  | +            MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1                        0x1d6 | 
 |  |  | +            MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2                        0x1d6 | 
 |  |  | +            MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3                        0x1d6 | 
 |  |  | +            MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT                     0xc1 | 
 |  |  | +        >; | 
 |  |  | +    }; | 
 |  |  | + | 
 |  |  | +    pinctrl_usdhc3: usdhc3grp { | 
 |  |  | +        fsl,pins = < | 
 |  |  | +            MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK                          0x190 | 
 |  |  | +            MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD                          0x1d0 | 
 |  |  | +            MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0                      0x1d0 | 
 |  |  | +            MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1                      0x1d0 | 
 |  |  | +            MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2                      0x1d0 | 
 |  |  | +            MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3                      0x1d0 | 
 |  |  | +            MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4                        0x1d0 | 
 |  |  | +            MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5                       0x1d0 | 
 |  |  | +            MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6                       0x1d0 | 
 |  |  | +            MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7                         0x1d0 | 
 |  |  | +            MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE                      0x190 | 
 |  |  | +        >; | 
 |  |  | +    }; | 
 |  |  | + | 
 |  |  | +    pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { | 
 |  |  | +        fsl,pins = < | 
 |  |  | +            MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK                          0x194 | 
 |  |  | +            MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD                          0x1d4 | 
 |  |  | +            MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0                      0x1d4 | 
 |  |  | +            MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1                      0x1d4 | 
 |  |  | +            MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2                      0x1d4 | 
 |  |  | +            MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3                      0x1d4 | 
 |  |  | +            MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4                        0x1d4 | 
 |  |  | +            MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5                       0x1d4 | 
 |  |  | +            MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6                       0x1d4 | 
 |  |  | +            MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7                         0x1d4 | 
 |  |  | +            MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE                      0x194 | 
 |  |  | +        >; | 
 |  |  | +    }; | 
 |  |  | + | 
 |  |  | +    pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { | 
 |  |  | +        fsl,pins = < | 
 |  |  | +            MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK                          0x196 | 
 |  |  | +            MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD                          0x1d6 | 
 |  |  | +            MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0                      0x1d6 | 
 |  |  | +            MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1                      0x1d6 | 
 |  |  | +            MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2                      0x1d6 | 
 |  |  | +            MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3                      0x1d6 | 
 |  |  | +            MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4                        0x1d6 | 
 |  |  | +            MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5                       0x1d6 | 
 |  |  | +            MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6                       0x1d6 | 
 |  |  | +            MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7                         0x1d6 | 
 |  |  | +            MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE                      0x196 | 
 |  |  | +        >; | 
 |  |  | +    }; | 
 |  |  | + | 
 |  |  | +    pinctrl_eqos: eqosgrp { | 
 |  |  | +        fsl,pins = < | 
 |  |  | +            MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC                         0x2 | 
 |  |  | +            MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO                       0x2 | 
 |  |  | +            MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0                   0x90 | 
 |  |  | +            MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1                   0x90 | 
 |  |  | +            MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2                   0x90 | 
 |  |  | +            MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3                   0x90 | 
 |  |  | +            MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK   0x90 | 
 |  |  | +            MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL             0x90 | 
 |  |  | +            MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0                   0x16 | 
 |  |  | +            MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1                   0x16 | 
 |  |  | +            MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2                   0x16 | 
 |  |  | +            MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3                   0x16 | 
 |  |  | +            MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL             0x16 | 
 |  |  | +            MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK   0x16 | 
 |  |  | +            MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06                         0x22 | 
 |  |  | +        >; | 
 |  |  | +    }; | 
 |  |  | + | 
 |  |  | +    pinctrl_fec: fecgrp { | 
 |  |  | +        fsl,pins = < | 
 |  |  | +            MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC                           0x2 | 
 |  |  | +            MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO                          0x2 | 
 |  |  | +            MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0                     0x90 | 
 |  |  | +            MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1                     0x90 | 
 |  |  | +            MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2                     0x90 | 
 |  |  | +            MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3                     0x90 | 
 |  |  | +            MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC                      0x90 | 
 |  |  | +            MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL                  0x90 | 
 |  |  | +            MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0                     0x16 | 
 |  |  | +            MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1                     0x16 | 
 |  |  | +            MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2                     0x16 | 
 |  |  | +            MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3                     0x16 | 
 |  |  | +            MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL                  0x16 | 
 |  |  | +            MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC                     0x16 | 
 |  |  | +            MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01                         0x11 | 
 |  |  | +        >; | 
 |  |  | +    }; | 
 |  |  | +}; | 
 |  |  | diff --git a/arch/arm64/configs/igkboard-imx8mp_defconfig b/arch/arm64/configs/igkboard-imx8mp_defconfig | 
 |  |  | new file mode 100644 | 
 |  |  | index 000000000..6b6fe01d9 | 
 |  |  | --- /dev/null | 
 |  |  | +++ b/arch/arm64/configs/igkboard-imx8mp_defconfig | 
 |  |  | @@ -0,0 +1,1118 @@ | 
 |  |  | +CONFIG_SYSVIPC=y | 
 |  |  | +CONFIG_POSIX_MQUEUE=y | 
 |  |  | +CONFIG_AUDIT=y | 
 |  |  | +CONFIG_NO_HZ_IDLE=y | 
 |  |  | +CONFIG_HIGH_RES_TIMERS=y | 
 |  |  | +CONFIG_BPF_SYSCALL=y | 
 |  |  | +CONFIG_BPF_JIT=y | 
 |  |  | +CONFIG_PREEMPT=y | 
 |  |  | +CONFIG_IRQ_TIME_ACCOUNTING=y | 
 |  |  | +CONFIG_BSD_PROCESS_ACCT=y | 
 |  |  | +CONFIG_BSD_PROCESS_ACCT_V3=y | 
 |  |  | +CONFIG_TASKSTATS=y | 
 |  |  | +CONFIG_TASK_XACCT=y | 
 |  |  | +CONFIG_TASK_IO_ACCOUNTING=y | 
 |  |  | +CONFIG_IKCONFIG=y | 
 |  |  | +CONFIG_IKCONFIG_PROC=y | 
 |  |  | +CONFIG_NUMA_BALANCING=y | 
 |  |  | +CONFIG_MEMCG=y | 
 |  |  | +CONFIG_BLK_CGROUP=y | 
 |  |  | +CONFIG_CGROUP_PIDS=y | 
 |  |  | +CONFIG_CGROUP_FREEZER=y | 
 |  |  | +CONFIG_CGROUP_HUGETLB=y | 
 |  |  | +CONFIG_CPUSETS=y | 
 |  |  | +CONFIG_CGROUP_DEVICE=y | 
 |  |  | +CONFIG_CGROUP_CPUACCT=y | 
 |  |  | +CONFIG_CGROUP_PERF=y | 
 |  |  | +CONFIG_CGROUP_BPF=y | 
 |  |  | +CONFIG_USER_NS=y | 
 |  |  | +CONFIG_SCHED_AUTOGROUP=y | 
 |  |  | +CONFIG_RELAY=y | 
 |  |  | +CONFIG_BLK_DEV_INITRD=y | 
 |  |  | +CONFIG_KALLSYMS_ALL=y | 
 |  |  | +CONFIG_PROFILING=y | 
 |  |  | +CONFIG_ARCH_KEEMBAY=y | 
 |  |  | +CONFIG_ARCH_NXP=y | 
 |  |  | +CONFIG_ARCH_LAYERSCAPE=y | 
 |  |  | +CONFIG_ARCH_MXC=y | 
 |  |  | +CONFIG_ARCH_S32=y | 
 |  |  | +CONFIG_SOC_S32V234=y | 
 |  |  | +CONFIG_ARM64_VA_BITS_48=y | 
 |  |  | +CONFIG_SCHED_MC=y | 
 |  |  | +CONFIG_SCHED_SMT=y | 
 |  |  | +CONFIG_NUMA=y | 
 |  |  | +CONFIG_KEXEC=y | 
 |  |  | +CONFIG_KEXEC_FILE=y | 
 |  |  | +CONFIG_CRASH_DUMP=y | 
 |  |  | +CONFIG_XEN=y | 
 |  |  | +CONFIG_ARCH_FORCE_MAX_ORDER=14 | 
 |  |  | +CONFIG_COMPAT=y | 
 |  |  | +CONFIG_RANDOMIZE_BASE=y | 
 |  |  | +CONFIG_PM_DEBUG=y | 
 |  |  | +CONFIG_PM_TEST_SUSPEND=y | 
 |  |  | +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y | 
 |  |  | +CONFIG_ENERGY_MODEL=y | 
 |  |  | +CONFIG_ARM_PSCI_CPUIDLE=y | 
 |  |  | +CONFIG_CPU_FREQ=y | 
 |  |  | +CONFIG_CPU_FREQ_STAT=y | 
 |  |  | +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y | 
 |  |  | +CONFIG_CPU_FREQ_GOV_POWERSAVE=y | 
 |  |  | +CONFIG_CPU_FREQ_GOV_USERSPACE=y | 
 |  |  | +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y | 
 |  |  | +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y | 
 |  |  | +CONFIG_CPUFREQ_DT=y | 
 |  |  | +CONFIG_ACPI_CPPC_CPUFREQ=m | 
 |  |  | +CONFIG_ARM_SCPI_CPUFREQ=y | 
 |  |  | +CONFIG_ARM_IMX_CPUFREQ_DT=y | 
 |  |  | +CONFIG_ARM_SCMI_CPUFREQ=y | 
 |  |  | +CONFIG_QORIQ_CPUFREQ=y | 
 |  |  | +CONFIG_ACPI=y | 
 |  |  | +CONFIG_ACPI_APEI=y | 
 |  |  | +CONFIG_ACPI_APEI_GHES=y | 
 |  |  | +CONFIG_ACPI_APEI_MEMORY_FAILURE=y | 
 |  |  | +CONFIG_ACPI_APEI_EINJ=y | 
 |  |  | +CONFIG_VIRTUALIZATION=y | 
 |  |  | +CONFIG_KVM=y | 
 |  |  | +CONFIG_JUMP_LABEL=y | 
 |  |  | +CONFIG_MODULES=y | 
 |  |  | +CONFIG_MODULE_UNLOAD=y | 
 |  |  | +CONFIG_MODVERSIONS=y | 
 |  |  | +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | 
 |  |  | +# CONFIG_COMPAT_BRK is not set | 
 |  |  | +CONFIG_KSM=y | 
 |  |  | +CONFIG_MEMORY_FAILURE=y | 
 |  |  | +CONFIG_TRANSPARENT_HUGEPAGE=y | 
 |  |  | +CONFIG_NET=y | 
 |  |  | +CONFIG_PACKET=y | 
 |  |  | +CONFIG_UNIX=y | 
 |  |  | +CONFIG_TLS=y | 
 |  |  | +CONFIG_TLS_DEVICE=y | 
 |  |  | +CONFIG_INET=y | 
 |  |  | +CONFIG_IP_MULTICAST=y | 
 |  |  | +CONFIG_IP_PNP=y | 
 |  |  | +CONFIG_IP_PNP_DHCP=y | 
 |  |  | +CONFIG_IP_PNP_BOOTP=y | 
 |  |  | +CONFIG_IPV6_SIT=m | 
 |  |  | +CONFIG_NETFILTER=y | 
 |  |  | +CONFIG_BRIDGE_NETFILTER=m | 
 |  |  | +CONFIG_NETFILTER_NETLINK_OSF=m | 
 |  |  | +CONFIG_NF_CONNTRACK=m | 
 |  |  | +CONFIG_NF_CONNTRACK_EVENTS=y | 
 |  |  | +CONFIG_NF_TABLES=y | 
 |  |  | +CONFIG_NF_TABLES_INET=y | 
 |  |  | +CONFIG_NF_TABLES_NETDEV=y | 
 |  |  | +CONFIG_NFT_CT=m | 
 |  |  | +CONFIG_NFT_MASQ=m | 
 |  |  | +CONFIG_NFT_NAT=m | 
 |  |  | +CONFIG_NFT_COMPAT=m | 
 |  |  | +CONFIG_NFT_DUP_NETDEV=m | 
 |  |  | +CONFIG_NFT_FWD_NETDEV=m | 
 |  |  | +CONFIG_NF_FLOW_TABLE=m | 
 |  |  | +CONFIG_NETFILTER_XT_MARK=m | 
 |  |  | +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m | 
 |  |  | +CONFIG_NETFILTER_XT_TARGET_LOG=m | 
 |  |  | +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m | 
 |  |  | +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m | 
 |  |  | +CONFIG_NETFILTER_XT_MATCH_IPVS=m | 
 |  |  | +CONFIG_IP_VS=m | 
 |  |  | +CONFIG_NF_SOCKET_IPV4=m | 
 |  |  | +CONFIG_NF_TPROXY_IPV4=m | 
 |  |  | +CONFIG_IP_NF_IPTABLES=m | 
 |  |  | +CONFIG_IP_NF_FILTER=m | 
 |  |  | +CONFIG_IP_NF_TARGET_REJECT=m | 
 |  |  | +CONFIG_IP_NF_NAT=m | 
 |  |  | +CONFIG_IP_NF_TARGET_MASQUERADE=m | 
 |  |  | +CONFIG_IP_NF_MANGLE=m | 
 |  |  | +CONFIG_NF_SOCKET_IPV6=m | 
 |  |  | +CONFIG_NF_TPROXY_IPV6=m | 
 |  |  | +CONFIG_IP6_NF_IPTABLES=m | 
 |  |  | +CONFIG_IP6_NF_FILTER=m | 
 |  |  | +CONFIG_IP6_NF_TARGET_REJECT=m | 
 |  |  | +CONFIG_IP6_NF_MANGLE=m | 
 |  |  | +CONFIG_IP6_NF_NAT=m | 
 |  |  | +CONFIG_IP6_NF_TARGET_MASQUERADE=m | 
 |  |  | +CONFIG_NF_TABLES_BRIDGE=m | 
 |  |  | +CONFIG_BRIDGE_NF_EBTABLES=m | 
 |  |  | +CONFIG_BRIDGE=y | 
 |  |  | +CONFIG_BRIDGE_VLAN_FILTERING=y | 
 |  |  | +CONFIG_NET_DSA=m | 
 |  |  | +CONFIG_VLAN_8021Q_GVRP=y | 
 |  |  | +CONFIG_VLAN_8021Q_MVRP=y | 
 |  |  | +CONFIG_LLC2=y | 
 |  |  | +CONFIG_NET_SCHED=y | 
 |  |  | +CONFIG_NET_SCH_MULTIQ=m | 
 |  |  | +CONFIG_NET_SCH_CBS=m | 
 |  |  | +CONFIG_NET_SCH_ETF=m | 
 |  |  | +CONFIG_NET_SCH_TAPRIO=m | 
 |  |  | +CONFIG_NET_SCH_MQPRIO=m | 
 |  |  | +CONFIG_NET_SCH_INGRESS=m | 
 |  |  | +CONFIG_NET_CLS_BASIC=m | 
 |  |  | +CONFIG_NET_CLS_U32=m | 
 |  |  | +CONFIG_NET_CLS_FLOWER=m | 
 |  |  | +CONFIG_NET_CLS_ACT=y | 
 |  |  | +CONFIG_NET_ACT_GACT=m | 
 |  |  | +CONFIG_NET_ACT_MIRRED=m | 
 |  |  | +CONFIG_NET_ACT_SKBEDIT=m | 
 |  |  | +CONFIG_NET_ACT_GATE=m | 
 |  |  | +CONFIG_TSN=y | 
 |  |  | +CONFIG_QRTR=m | 
 |  |  | +CONFIG_QRTR_SMD=m | 
 |  |  | +CONFIG_QRTR_TUN=m | 
 |  |  | +CONFIG_NET_PKTGEN=m | 
 |  |  | +CONFIG_CAN=m | 
 |  |  | +CONFIG_BT=y | 
 |  |  | +CONFIG_BT_RFCOMM=y | 
 |  |  | +CONFIG_BT_RFCOMM_TTY=y | 
 |  |  | +CONFIG_BT_BNEP=y | 
 |  |  | +CONFIG_BT_BNEP_MC_FILTER=y | 
 |  |  | +CONFIG_BT_BNEP_PROTO_FILTER=y | 
 |  |  | +CONFIG_BT_HIDP=y | 
 |  |  | +CONFIG_BT_LEDS=y | 
 |  |  | +# CONFIG_BT_DEBUGFS is not set | 
 |  |  | +CONFIG_BT_HCIBTUSB=m | 
 |  |  | +CONFIG_BT_HCIUART=y | 
 |  |  | +CONFIG_BT_HCIUART_BCSP=y | 
 |  |  | +CONFIG_BT_HCIUART_ATH3K=y | 
 |  |  | +CONFIG_BT_HCIUART_LL=y | 
 |  |  | +CONFIG_BT_HCIUART_3WIRE=y | 
 |  |  | +CONFIG_BT_HCIUART_BCM=y | 
 |  |  | +CONFIG_BT_HCIUART_QCA=y | 
 |  |  | +CONFIG_BT_HCIVHCI=y | 
 |  |  | +CONFIG_BT_NXPUART=m | 
 |  |  | +CONFIG_CFG80211=y | 
 |  |  | +CONFIG_NL80211_TESTMODE=y | 
 |  |  | +CONFIG_CFG80211_WEXT=y | 
 |  |  | +CONFIG_MAC80211=y | 
 |  |  | +CONFIG_MAC80211_LEDS=y | 
 |  |  | +CONFIG_NET_9P=y | 
 |  |  | +CONFIG_NET_9P_VIRTIO=y | 
 |  |  | +CONFIG_NFC=m | 
 |  |  | +CONFIG_NFC_NCI=m | 
 |  |  | +CONFIG_NFC_S3FWRN5_I2C=m | 
 |  |  | +CONFIG_PCI=y | 
 |  |  | +CONFIG_PCIEPORTBUS=y | 
 |  |  | +CONFIG_PCI_IOV=y | 
 |  |  | +CONFIG_PCI_PASID=y | 
 |  |  | +CONFIG_HOTPLUG_PCI=y | 
 |  |  | +CONFIG_HOTPLUG_PCI_ACPI=y | 
 |  |  | +CONFIG_PCI_HOST_GENERIC=y | 
 |  |  | +CONFIG_PCI_XGENE=y | 
 |  |  | +CONFIG_PCIE_ALTERA=y | 
 |  |  | +CONFIG_PCIE_ALTERA_MSI=y | 
 |  |  | +CONFIG_PCI_HOST_THUNDER_PEM=y | 
 |  |  | +CONFIG_PCI_HOST_THUNDER_ECAM=y | 
 |  |  | +CONFIG_PCI_IMX6_HOST=y | 
 |  |  | +CONFIG_PCI_IMX6_EP=y | 
 |  |  | +CONFIG_PCI_LAYERSCAPE=y | 
 |  |  | +CONFIG_PCI_HISI=y | 
 |  |  | +CONFIG_PCIE_KIRIN=y | 
 |  |  | +CONFIG_PCI_MESON=m | 
 |  |  | +CONFIG_PCIE_LAYERSCAPE_GEN4=y | 
 |  |  | +CONFIG_PCI_ENDPOINT=y | 
 |  |  | +CONFIG_PCI_ENDPOINT_CONFIGFS=y | 
 |  |  | +CONFIG_PCI_EPF_TEST=y | 
 |  |  | +CONFIG_DEVTMPFS=y | 
 |  |  | +CONFIG_DEVTMPFS_MOUNT=y | 
 |  |  | +CONFIG_FW_LOADER_USER_HELPER=y | 
 |  |  | +CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y | 
 |  |  | +CONFIG_BRCMSTB_GISB_ARB=y | 
 |  |  | +CONFIG_VEXPRESS_CONFIG=y | 
 |  |  | +CONFIG_FSL_MC_UAPI_SUPPORT=y | 
 |  |  | +CONFIG_ARM_SCMI_PROTOCOL=y | 
 |  |  | +CONFIG_ARM_SCPI_PROTOCOL=y | 
 |  |  | +CONFIG_EFI_CAPSULE_LOADER=y | 
 |  |  | +CONFIG_IMX_DSP=y | 
 |  |  | +CONFIG_IMX_SCU=y | 
 |  |  | +CONFIG_IMX_SCU_PD=y | 
 |  |  | +CONFIG_IMX_EL_ENCLAVE=y | 
 |  |  | +CONFIG_GNSS=m | 
 |  |  | +CONFIG_GNSS_MTK_SERIAL=m | 
 |  |  | +CONFIG_MTD=y | 
 |  |  | +CONFIG_MTD_CMDLINE_PARTS=y | 
 |  |  | +CONFIG_MTD_BLOCK=y | 
 |  |  | +CONFIG_MTD_CFI=y | 
 |  |  | +CONFIG_MTD_CFI_ADV_OPTIONS=y | 
 |  |  | +CONFIG_MTD_CFI_INTELEXT=y | 
 |  |  | +CONFIG_MTD_CFI_AMDSTD=y | 
 |  |  | +CONFIG_MTD_CFI_STAA=y | 
 |  |  | +CONFIG_MTD_PHYSMAP=y | 
 |  |  | +CONFIG_MTD_PHYSMAP_OF=y | 
 |  |  | +CONFIG_MTD_DATAFLASH=y | 
 |  |  | +CONFIG_MTD_SST25L=y | 
 |  |  | +CONFIG_MTD_RAW_NAND=y | 
 |  |  | +CONFIG_MTD_NAND_DENALI_DT=y | 
 |  |  | +CONFIG_MTD_NAND_GPMI_NAND=y | 
 |  |  | +CONFIG_MTD_NAND_FSL_IFC=y | 
 |  |  | +CONFIG_MTD_SPI_NAND=y | 
 |  |  | +CONFIG_MTD_SPI_NOR=y | 
 |  |  | +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set | 
 |  |  | +CONFIG_MTD_UBI=y | 
 |  |  | +CONFIG_BLK_DEV_LOOP=y | 
 |  |  | +CONFIG_BLK_DEV_NBD=m | 
 |  |  | +CONFIG_XEN_BLKDEV_BACKEND=m | 
 |  |  | +CONFIG_VIRTIO_BLK=y | 
 |  |  | +CONFIG_BLK_DEV_NVME=y | 
 |  |  | +CONFIG_SRAM=y | 
 |  |  | +CONFIG_PCI_ENDPOINT_TEST=y | 
 |  |  | +CONFIG_EEPROM_AT24=m | 
 |  |  | +CONFIG_EEPROM_AT25=m | 
 |  |  | +CONFIG_UACCE=m | 
 |  |  | +# CONFIG_SCSI_PROC_FS is not set | 
 |  |  | +CONFIG_BLK_DEV_SD=y | 
 |  |  | +CONFIG_SCSI_SAS_ATA=y | 
 |  |  | +CONFIG_SCSI_HISI_SAS=y | 
 |  |  | +CONFIG_SCSI_HISI_SAS_PCI=y | 
 |  |  | +CONFIG_MEGARAID_SAS=y | 
 |  |  | +CONFIG_SCSI_MPT3SAS=m | 
 |  |  | +CONFIG_ATA=y | 
 |  |  | +CONFIG_SATA_AHCI=y | 
 |  |  | +CONFIG_SATA_AHCI_PLATFORM=y | 
 |  |  | +CONFIG_AHCI_IMX=y | 
 |  |  | +CONFIG_AHCI_CEVA=y | 
 |  |  | +CONFIG_AHCI_XGENE=y | 
 |  |  | +CONFIG_AHCI_QORIQ=y | 
 |  |  | +CONFIG_SATA_SIL24=y | 
 |  |  | +CONFIG_PATA_OF_PLATFORM=y | 
 |  |  | +CONFIG_MD=y | 
 |  |  | +CONFIG_BLK_DEV_MD=m | 
 |  |  | +CONFIG_BLK_DEV_DM=m | 
 |  |  | +CONFIG_DM_CRYPT=m | 
 |  |  | +CONFIG_DM_MIRROR=m | 
 |  |  | +CONFIG_DM_ZERO=m | 
 |  |  | +CONFIG_NETDEVICES=y | 
 |  |  | +CONFIG_MACVLAN=m | 
 |  |  | +CONFIG_MACVTAP=m | 
 |  |  | +CONFIG_TUN=y | 
 |  |  | +CONFIG_VETH=m | 
 |  |  | +CONFIG_VIRTIO_NET=y | 
 |  |  | +CONFIG_NET_DSA_MSCC_FELIX=m | 
 |  |  | +CONFIG_NET_DSA_SJA1105=m | 
 |  |  | +CONFIG_NET_DSA_SJA1105_PTP=y | 
 |  |  | +CONFIG_NET_DSA_SJA1105_TAS=y | 
 |  |  | +CONFIG_NET_DSA_SJA1105_VL=y | 
 |  |  | +CONFIG_AMD_XGBE=y | 
 |  |  | +CONFIG_ATL1C=m | 
 |  |  | +CONFIG_BCMGENET=m | 
 |  |  | +CONFIG_BNX2X=m | 
 |  |  | +CONFIG_SYSTEMPORT=m | 
 |  |  | +CONFIG_MACB=y | 
 |  |  | +CONFIG_THUNDER_NIC_PF=y | 
 |  |  | +CONFIG_FEC=y | 
 |  |  | +CONFIG_FEC_UIO=y | 
 |  |  | +CONFIG_FSL_FMAN=y | 
 |  |  | +CONFIG_FSL_DPAA_ETH=y | 
 |  |  | +CONFIG_FSL_DPAA2_ETH=y | 
 |  |  | +CONFIG_FSL_DPAA2_MAC=y | 
 |  |  | +CONFIG_FSL_DPAA2_SWITCH=y | 
 |  |  | +CONFIG_FSL_ENETC=y | 
 |  |  | +CONFIG_FSL_ENETC_VF=y | 
 |  |  | +CONFIG_FSL_ENETC_QOS=y | 
 |  |  | +CONFIG_ENETC_TSN=y | 
 |  |  | +CONFIG_HIX5HD2_GMAC=y | 
 |  |  | +CONFIG_HNS_DSAF=y | 
 |  |  | +CONFIG_HNS_ENET=y | 
 |  |  | +CONFIG_HNS3=y | 
 |  |  | +CONFIG_HNS3_HCLGE=y | 
 |  |  | +CONFIG_HNS3_ENET=y | 
 |  |  | +CONFIG_E1000=y | 
 |  |  | +CONFIG_E1000E=y | 
 |  |  | +CONFIG_IGB=y | 
 |  |  | +CONFIG_IGBVF=y | 
 |  |  | +CONFIG_MVMDIO=y | 
 |  |  | +CONFIG_SKY2=y | 
 |  |  | +CONFIG_MLX4_EN=m | 
 |  |  | +CONFIG_MLX5_CORE=m | 
 |  |  | +CONFIG_MLX5_CORE_EN=y | 
 |  |  | +CONFIG_MSCC_OCELOT_SWITCH=y | 
 |  |  | +CONFIG_QCOM_EMAC=m | 
 |  |  | +CONFIG_RMNET=m | 
 |  |  | +CONFIG_SMC91X=y | 
 |  |  | +CONFIG_SMSC911X=y | 
 |  |  | +CONFIG_STMMAC_ETH=y | 
 |  |  | +CONFIG_DWMAC_GENERIC=m | 
 |  |  | +CONFIG_AQUANTIA_PHY=y | 
 |  |  | +CONFIG_BROADCOM_PHY=m | 
 |  |  | +CONFIG_BCM54140_PHY=m | 
 |  |  | +CONFIG_MARVELL_PHY=m | 
 |  |  | +CONFIG_MARVELL_10G_PHY=m | 
 |  |  | +CONFIG_MICREL_PHY=y | 
 |  |  | +CONFIG_MICROSEMI_PHY=y | 
 |  |  | +CONFIG_NXP_C45_TJA11XX_PHY=y | 
 |  |  | +CONFIG_NXP_TJA11XX_PHY=y | 
 |  |  | +CONFIG_AT803X_PHY=y | 
 |  |  | +CONFIG_REALTEK_PHY=y | 
 |  |  | +CONFIG_ROCKCHIP_PHY=y | 
 |  |  | +CONFIG_VITESSE_PHY=y | 
 |  |  | +CONFIG_CAN_FLEXCAN=m | 
 |  |  | +CONFIG_MDIO_BITBANG=y | 
 |  |  | +CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y | 
 |  |  | +CONFIG_MDIO_BUS_MUX_MMIOREG=y | 
 |  |  | +CONFIG_USB_PEGASUS=m | 
 |  |  | +CONFIG_USB_RTL8150=m | 
 |  |  | +CONFIG_USB_RTL8152=y | 
 |  |  | +CONFIG_USB_LAN78XX=m | 
 |  |  | +CONFIG_USB_USBNET=y | 
 |  |  | +CONFIG_USB_NET_AX8817X=m | 
 |  |  | +CONFIG_USB_NET_AX88179_178A=m | 
 |  |  | +CONFIG_USB_NET_CDCETHER=m | 
 |  |  | +CONFIG_USB_NET_CDC_NCM=m | 
 |  |  | +CONFIG_USB_NET_DM9601=m | 
 |  |  | +CONFIG_USB_NET_SR9800=m | 
 |  |  | +CONFIG_USB_NET_SMSC75XX=m | 
 |  |  | +CONFIG_USB_NET_SMSC95XX=m | 
 |  |  | +CONFIG_USB_NET_NET1080=m | 
 |  |  | +CONFIG_USB_NET_PLUSB=m | 
 |  |  | +CONFIG_USB_NET_MCS7830=m | 
 |  |  | +CONFIG_USB_NET_CDC_SUBSET=m | 
 |  |  | +CONFIG_USB_NET_ZAURUS=m | 
 |  |  | +CONFIG_HOSTAP=y | 
 |  |  | +CONFIG_WL18XX=m | 
 |  |  | +CONFIG_WLCORE_SDIO=m | 
 |  |  | +CONFIG_XEN_NETDEV_BACKEND=m | 
 |  |  | +CONFIG_IVSHMEM_NET=y | 
 |  |  | +CONFIG_INPUT_EVDEV=y | 
 |  |  | +CONFIG_KEYBOARD_ADC=m | 
 |  |  | +CONFIG_KEYBOARD_GPIO=y | 
 |  |  | +CONFIG_KEYBOARD_RPMSG=y | 
 |  |  | +CONFIG_KEYBOARD_SNVS_PWRKEY=y | 
 |  |  | +CONFIG_KEYBOARD_BBNSM_PWRKEY=y | 
 |  |  | +CONFIG_KEYBOARD_IMX_SC_KEY=y | 
 |  |  | +CONFIG_KEYBOARD_CROS_EC=y | 
 |  |  | +CONFIG_INPUT_TOUCHSCREEN=y | 
 |  |  | +CONFIG_TOUCHSCREEN_ATMEL_MXT=m | 
 |  |  | +CONFIG_TOUCHSCREEN_EXC3000=m | 
 |  |  | +CONFIG_TOUCHSCREEN_GOODIX=m | 
 |  |  | +CONFIG_TOUCHSCREEN_EDT_FT5X06=m | 
 |  |  | +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_I2C=m | 
 |  |  | +CONFIG_INPUT_MISC=y | 
 |  |  | +CONFIG_INPUT_PWM_BEEPER=m | 
 |  |  | +CONFIG_INPUT_PWM_VIBRA=m | 
 |  |  | +# CONFIG_SERIO_SERPORT is not set | 
 |  |  | +CONFIG_SERIO_AMBAKMI=y | 
 |  |  | +CONFIG_LEGACY_PTY_COUNT=16 | 
 |  |  | +CONFIG_SERIAL_8250=y | 
 |  |  | +CONFIG_SERIAL_8250_CONSOLE=y | 
 |  |  | +CONFIG_SERIAL_8250_EXTENDED=y | 
 |  |  | +CONFIG_SERIAL_8250_SHARE_IRQ=y | 
 |  |  | +CONFIG_SERIAL_8250_DW=y | 
 |  |  | +CONFIG_SERIAL_OF_PLATFORM=y | 
 |  |  | +CONFIG_SERIAL_AMBA_PL011=y | 
 |  |  | +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y | 
 |  |  | +CONFIG_SERIAL_IMX=y | 
 |  |  | +CONFIG_SERIAL_IMX_CONSOLE=y | 
 |  |  | +CONFIG_SERIAL_XILINX_PS_UART=y | 
 |  |  | +CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y | 
 |  |  | +CONFIG_SERIAL_FSL_LPUART=y | 
 |  |  | +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y | 
 |  |  | +CONFIG_SERIAL_FSL_LINFLEXUART=y | 
 |  |  | +CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y | 
 |  |  | +CONFIG_SERIAL_DEV_BUS=y | 
 |  |  | +CONFIG_VIRTIO_CONSOLE=y | 
 |  |  | +CONFIG_IPMI_HANDLER=m | 
 |  |  | +CONFIG_IPMI_DEVICE_INTERFACE=m | 
 |  |  | +CONFIG_IPMI_SI=m | 
 |  |  | +CONFIG_TCG_TPM=y | 
 |  |  | +CONFIG_TCG_TIS_I2C_INFINEON=y | 
 |  |  | +CONFIG_I2C_CHARDEV=y | 
 |  |  | +CONFIG_I2C_MUX=y | 
 |  |  | +CONFIG_I2C_MUX_GPIO=y | 
 |  |  | +CONFIG_I2C_MUX_PCA954x=y | 
 |  |  | +CONFIG_I2C_DESIGNWARE_PLATFORM=y | 
 |  |  | +CONFIG_I2C_GPIO=m | 
 |  |  | +CONFIG_I2C_IMX=y | 
 |  |  | +CONFIG_I2C_IMX_LPI2C=y | 
 |  |  | +CONFIG_I2C_RK3X=y | 
 |  |  | +CONFIG_I2C_RPBUS=y | 
 |  |  | +CONFIG_I2C_CROS_EC_TUNNEL=y | 
 |  |  | +CONFIG_I2C_SLAVE_EEPROM=y | 
 |  |  | +CONFIG_I3C=y | 
 |  |  | +CONFIG_SVC_I3C_MASTER=y | 
 |  |  | +CONFIG_SPI=y | 
 |  |  | +CONFIG_SPI_CADENCE_QUADSPI=y | 
 |  |  | +CONFIG_SPI_DESIGNWARE=m | 
 |  |  | +CONFIG_SPI_DW_DMA=y | 
 |  |  | +CONFIG_SPI_DW_MMIO=m | 
 |  |  | +CONFIG_SPI_FSL_LPSPI=y | 
 |  |  | +CONFIG_SPI_FSL_QUADSPI=y | 
 |  |  | +CONFIG_SPI_NXP_FLEXSPI=y | 
 |  |  | +CONFIG_SPI_IMX=y | 
 |  |  | +CONFIG_SPI_FSL_DSPI=y | 
 |  |  | +CONFIG_SPI_PL022=y | 
 |  |  | +CONFIG_SPI_ROCKCHIP=y | 
 |  |  | +CONFIG_SPI_SPIDEV=y | 
 |  |  | +CONFIG_SPI_SLAVE=y | 
 |  |  | +CONFIG_SPI_SLAVE_TIME=y | 
 |  |  | +CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y | 
 |  |  | +CONFIG_SPMI=y | 
 |  |  | +CONFIG_PPS_CLIENT_GPIO=y | 
 |  |  | +CONFIG_PINCTRL_MAX77620=y | 
 |  |  | +CONFIG_PINCTRL_SINGLE=y | 
 |  |  | +CONFIG_PINCTRL_IMX8MM=y | 
 |  |  | +CONFIG_PINCTRL_IMX8MN=y | 
 |  |  | +CONFIG_PINCTRL_IMX8MP=y | 
 |  |  | +CONFIG_PINCTRL_IMX8MQ=y | 
 |  |  | +CONFIG_PINCTRL_IMX8QM=y | 
 |  |  | +CONFIG_PINCTRL_IMX8QXP=y | 
 |  |  | +CONFIG_PINCTRL_IMX8DXL=y | 
 |  |  | +CONFIG_PINCTRL_IMX8ULP=y | 
 |  |  | +CONFIG_PINCTRL_IMX93=y | 
 |  |  | +CONFIG_PINCTRL_S32V234=y | 
 |  |  | +CONFIG_GPIO_ALTERA=m | 
 |  |  | +CONFIG_GPIO_DWAPB=y | 
 |  |  | +CONFIG_GPIO_IMX_RPMSG=y | 
 |  |  | +CONFIG_GPIO_MB86S7X=y | 
 |  |  | +CONFIG_GPIO_MPC8XXX=y | 
 |  |  | +CONFIG_GPIO_MXC=y | 
 |  |  | +CONFIG_GPIO_PL061=y | 
 |  |  | +CONFIG_GPIO_WCD934X=m | 
 |  |  | +CONFIG_GPIO_XGENE=y | 
 |  |  | +CONFIG_GPIO_MAX732X=y | 
 |  |  | +CONFIG_GPIO_PCA953X=y | 
 |  |  | +CONFIG_GPIO_PCA953X_IRQ=y | 
 |  |  | +CONFIG_GPIO_ADP5585=y | 
 |  |  | +CONFIG_GPIO_BD9571MWV=m | 
 |  |  | +CONFIG_GPIO_MAX77620=y | 
 |  |  | +CONFIG_GPIO_SL28CPLD=m | 
 |  |  | +CONFIG_POWER_RESET_BRCMSTB=y | 
 |  |  | +CONFIG_POWER_RESET_XGENE=y | 
 |  |  | +CONFIG_POWER_RESET_SYSCON=y | 
 |  |  | +CONFIG_SYSCON_REBOOT_MODE=y | 
 |  |  | +CONFIG_BATTERY_SBS=m | 
 |  |  | +CONFIG_BATTERY_BQ27XXX=y | 
 |  |  | +CONFIG_BATTERY_MAX17042=m | 
 |  |  | +CONFIG_CHARGER_BQ25890=m | 
 |  |  | +CONFIG_CHARGER_BQ25980=m | 
 |  |  | +CONFIG_SENSORS_ARM_SCMI=y | 
 |  |  | +CONFIG_SENSORS_ARM_SCPI=y | 
 |  |  | +CONFIG_SENSORS_FP9931=y | 
 |  |  | +CONFIG_SENSORS_LM90=m | 
 |  |  | +CONFIG_SENSORS_PWM_FAN=m | 
 |  |  | +CONFIG_SENSORS_SL28CPLD=m | 
 |  |  | +CONFIG_SENSORS_INA2XX=m | 
 |  |  | +CONFIG_SENSORS_INA3221=m | 
 |  |  | +CONFIG_THERMAL_WRITABLE_TRIPS=y | 
 |  |  | +CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y | 
 |  |  | +CONFIG_CPU_THERMAL=y | 
 |  |  | +CONFIG_THERMAL_EMULATION=y | 
 |  |  | +CONFIG_IMX_SC_THERMAL=y | 
 |  |  | +CONFIG_IMX8MM_THERMAL=y | 
 |  |  | +CONFIG_DEVICE_THERMAL=y | 
 |  |  | +CONFIG_QORIQ_THERMAL=y | 
 |  |  | +CONFIG_WATCHDOG=y | 
 |  |  | +CONFIG_SL28CPLD_WATCHDOG=m | 
 |  |  | +CONFIG_ARM_SP805_WATCHDOG=y | 
 |  |  | +CONFIG_ARM_SBSA_WATCHDOG=y | 
 |  |  | +CONFIG_DW_WATCHDOG=y | 
 |  |  | +CONFIG_IMX2_WDT=y | 
 |  |  | +CONFIG_IMX_SC_WDT=y | 
 |  |  | +CONFIG_IMX7ULP_WDT=y | 
 |  |  | +CONFIG_ARM_SMC_WATCHDOG=y | 
 |  |  | +CONFIG_XEN_WDT=y | 
 |  |  | +CONFIG_MFD_ADP5585=y | 
 |  |  | +CONFIG_MFD_BD9571MWV=y | 
 |  |  | +CONFIG_MFD_AXP20X_I2C=y | 
 |  |  | +CONFIG_MFD_IMX_FLEXIO=y | 
 |  |  | +CONFIG_MFD_HI6421_PMIC=y | 
 |  |  | +CONFIG_MFD_FP9931=y | 
 |  |  | +CONFIG_MFD_MAX77620=y | 
 |  |  | +CONFIG_MFD_MT6397=y | 
 |  |  | +CONFIG_MFD_RK808=y | 
 |  |  | +CONFIG_MFD_SEC_CORE=y | 
 |  |  | +CONFIG_MFD_SL28CPLD=y | 
 |  |  | +CONFIG_MFD_ROHM_BD718XX=y | 
 |  |  | +CONFIG_MFD_WCD934X=m | 
 |  |  | +CONFIG_REGULATOR_FIXED_VOLTAGE=y | 
 |  |  | +CONFIG_REGULATOR_AXP20X=y | 
 |  |  | +CONFIG_REGULATOR_BD718XX=y | 
 |  |  | +CONFIG_REGULATOR_BD9571MWV=y | 
 |  |  | +CONFIG_REGULATOR_FAN53555=y | 
 |  |  | +CONFIG_REGULATOR_GPIO=y | 
 |  |  | +CONFIG_REGULATOR_HI6421V530=y | 
 |  |  | +CONFIG_REGULATOR_MAX77620=y | 
 |  |  | +CONFIG_REGULATOR_MAX8973=y | 
 |  |  | +CONFIG_REGULATOR_FP9931=y | 
 |  |  | +CONFIG_REGULATOR_MP8859=y | 
 |  |  | +CONFIG_REGULATOR_MT6358=y | 
 |  |  | +CONFIG_REGULATOR_MT6397=y | 
 |  |  | +CONFIG_REGULATOR_PCA9450=y | 
 |  |  | +CONFIG_REGULATOR_PF8X00=y | 
 |  |  | +CONFIG_REGULATOR_PFUZE100=y | 
 |  |  | +CONFIG_REGULATOR_PWM=y | 
 |  |  | +CONFIG_REGULATOR_QCOM_SPMI=y | 
 |  |  | +CONFIG_REGULATOR_RK808=y | 
 |  |  | +CONFIG_REGULATOR_S2MPS11=y | 
 |  |  | +CONFIG_REGULATOR_TPS65132=m | 
 |  |  | +CONFIG_REGULATOR_VCTRL=m | 
 |  |  | +CONFIG_RC_CORE=m | 
 |  |  | +CONFIG_RC_DECODERS=y | 
 |  |  | +CONFIG_IR_IMON_DECODER=m | 
 |  |  | +CONFIG_IR_JVC_DECODER=m | 
 |  |  | +CONFIG_IR_MCE_KBD_DECODER=m | 
 |  |  | +CONFIG_IR_NEC_DECODER=m | 
 |  |  | +CONFIG_IR_RC5_DECODER=m | 
 |  |  | +CONFIG_IR_RC6_DECODER=m | 
 |  |  | +CONFIG_IR_RCMM_DECODER=m | 
 |  |  | +CONFIG_IR_SANYO_DECODER=m | 
 |  |  | +CONFIG_IR_SHARP_DECODER=m | 
 |  |  | +CONFIG_IR_SONY_DECODER=m | 
 |  |  | +CONFIG_IR_XMP_DECODER=m | 
 |  |  | +CONFIG_RC_DEVICES=y | 
 |  |  | +CONFIG_IR_GPIO_CIR=m | 
 |  |  | +CONFIG_MEDIA_SUPPORT=y | 
 |  |  | +CONFIG_MEDIA_CAMERA_SUPPORT=y | 
 |  |  | +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y | 
 |  |  | +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y | 
 |  |  | +CONFIG_MEDIA_SDR_SUPPORT=y | 
 |  |  | +CONFIG_MEDIA_PLATFORM_SUPPORT=y | 
 |  |  | +# CONFIG_DVB_NET is not set | 
 |  |  | +CONFIG_MEDIA_USB_SUPPORT=y | 
 |  |  | +CONFIG_USB_VIDEO_CLASS=m | 
 |  |  | +CONFIG_V4L_PLATFORM_DRIVERS=y | 
 |  |  | +CONFIG_SDR_PLATFORM_DRIVERS=y | 
 |  |  | +CONFIG_V4L_MEM2MEM_DRIVERS=y | 
 |  |  | +CONFIG_VIDEO_MX8_CAPTURE=y | 
 |  |  | +CONFIG_VIDEO_MXC_CAPTURE=y | 
 |  |  | +CONFIG_VIDEO_MXC_CSI_CAMERA=y | 
 |  |  | +CONFIG_MXC_MIPI_CSI=y | 
 |  |  | +CONFIG_MXC_CAMERA_OV5640_MIPI_V2=y | 
 |  |  | +CONFIG_VIDEO_AMPHION_VPU=y | 
 |  |  | +CONFIG_VIDEO_IMX8_JPEG=m | 
 |  |  | +CONFIG_VIDEO_HANTRO=m | 
 |  |  | +CONFIG_VIDEO_IMX219=m | 
 |  |  | +CONFIG_VIDEO_OV5640=y | 
 |  |  | +CONFIG_VIDEO_OV5645=m | 
 |  |  | +CONFIG_VIDEO_AP1302=y | 
 |  |  | +CONFIG_VIDEO_MT9M114=y | 
 |  |  | +CONFIG_IMX_DPU_CORE=y | 
 |  |  | +CONFIG_IMX8MM_LCDIF_CORE=y | 
 |  |  | +CONFIG_IMX_LCDIFV3_CORE=y | 
 |  |  | +CONFIG_DRM=y | 
 |  |  | +CONFIG_DRM_I2C_NXP_TDA998X=m | 
 |  |  | +CONFIG_DRM_MALI_DISPLAY=m | 
 |  |  | +CONFIG_DRM_NOUVEAU=m | 
 |  |  | +CONFIG_DRM_RCAR_DW_HDMI=m | 
 |  |  | +CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m | 
 |  |  | +CONFIG_DRM_PANEL_LVDS=m | 
 |  |  | +CONFIG_DRM_PANEL_SIMPLE=y | 
 |  |  | +CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m | 
 |  |  | +CONFIG_DRM_PANEL_RAYDIUM_RM67191=y | 
 |  |  | +CONFIG_DRM_PANEL_RAYDIUM_RM68200=y | 
 |  |  | +CONFIG_DRM_PANEL_ROCKTECK_HIMAX8394F=y | 
 |  |  | +CONFIG_DRM_PANEL_SEIKO_43WVF1G=y | 
 |  |  | +CONFIG_DRM_PANEL_SITRONIX_ST7703=m | 
 |  |  | +CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m | 
 |  |  | +CONFIG_DRM_PANEL_WKS_101WX001=y | 
 |  |  | +CONFIG_DRM_DISPLAY_CONNECTOR=m | 
 |  |  | +CONFIG_DRM_LONTIUM_LT8912B=m | 
 |  |  | +CONFIG_DRM_LONTIUM_LT9611=m | 
 |  |  | +CONFIG_DRM_LONTIUM_LT9611UXC=m | 
 |  |  | +CONFIG_DRM_FSL_IMX_LVDS_BRIDGE=y | 
 |  |  | +CONFIG_DRM_NWL_MIPI_DSI=y | 
 |  |  | +CONFIG_DRM_NXP_SEIKO_43WVFIG=y | 
 |  |  | +CONFIG_DRM_PARADE_PS8640=m | 
 |  |  | +CONFIG_DRM_SII902X=m | 
 |  |  | +CONFIG_DRM_SIMPLE_BRIDGE=m | 
 |  |  | +CONFIG_DRM_THINE_THC63LVD1024=m | 
 |  |  | +CONFIG_DRM_TI_SN65DSI86=m | 
 |  |  | +CONFIG_DRM_I2C_ADV7511=y | 
 |  |  | +CONFIG_DRM_I2C_ADV7511_AUDIO=y | 
 |  |  | +CONFIG_DRM_DW_HDMI_AHB_AUDIO=m | 
 |  |  | +CONFIG_DRM_DW_HDMI_I2S_AUDIO=m | 
 |  |  | +CONFIG_DRM_DW_HDMI_GP_AUDIO=y | 
 |  |  | +CONFIG_DRM_DW_HDMI_CEC=m | 
 |  |  | +CONFIG_DRM_ITE_IT6263=y | 
 |  |  | +CONFIG_DRM_ITE_IT6161=y | 
 |  |  | +CONFIG_DRM_IMX=y | 
 |  |  | +CONFIG_DRM_IMX_LCDIF_MUX_DISPLAY=y | 
 |  |  | +CONFIG_DRM_IMX_PARALLEL_DISPLAY=y | 
 |  |  | +CONFIG_DRM_IMX_TVE=y | 
 |  |  | +CONFIG_DRM_IMX_LDB=y | 
 |  |  | +CONFIG_DRM_IMX8QM_LDB=y | 
 |  |  | +CONFIG_DRM_IMX8QXP_LDB=y | 
 |  |  | +CONFIG_DRM_IMX8MP_LDB=y | 
 |  |  | +CONFIG_DRM_IMX93_LDB=y | 
 |  |  | +CONFIG_DRM_IMX_DW_MIPI_DSI=y | 
 |  |  | +CONFIG_DRM_IMX93_PARALLEL_DISPLAY_FORMAT=y | 
 |  |  | +CONFIG_DRM_IMX_HDMI=y | 
 |  |  | +CONFIG_DRM_IMX_SEC_DSIM=y | 
 |  |  | +CONFIG_DRM_IMX_DCNANO=y | 
 |  |  | +CONFIG_DRM_IMX_DCSS=y | 
 |  |  | +CONFIG_DRM_IMX_CDNS_MHDP=y | 
 |  |  | +CONFIG_DRM_ETNAVIV=m | 
 |  |  | +CONFIG_DRM_HISI_HIBMC=m | 
 |  |  | +CONFIG_DRM_HISI_KIRIN=m | 
 |  |  | +CONFIG_DRM_MXSFB=y | 
 |  |  | +CONFIG_DRM_PL111=m | 
 |  |  | +CONFIG_DRM_LIMA=m | 
 |  |  | +CONFIG_DRM_PANFROST=m | 
 |  |  | +CONFIG_FB=y | 
 |  |  | +CONFIG_FB_ARMCLCD=y | 
 |  |  | +CONFIG_FB_EFI=y | 
 |  |  | +CONFIG_FB_MXC_EINK_V2_PANEL=y | 
 |  |  | +CONFIG_BACKLIGHT_PWM=y | 
 |  |  | +CONFIG_BACKLIGHT_LP855X=m | 
 |  |  | +CONFIG_BACKLIGHT_GPIO=y | 
 |  |  | +CONFIG_LOGO=y | 
 |  |  | +# CONFIG_LOGO_LINUX_MONO is not set | 
 |  |  | +# CONFIG_LOGO_LINUX_VGA16 is not set | 
 |  |  | +CONFIG_SOUND=y | 
 |  |  | +CONFIG_SND=y | 
 |  |  | +CONFIG_SND_ALOOP=m | 
 |  |  | +CONFIG_SND_USB_AUDIO=m | 
 |  |  | +CONFIG_SND_SOC=y | 
 |  |  | +CONFIG_SND_SOC_FSL_ASRC=m | 
 |  |  | +CONFIG_SND_SOC_FSL_MQS=m | 
 |  |  | +CONFIG_SND_SOC_FSL_MICFIL=m | 
 |  |  | +CONFIG_SND_SOC_FSL_EASRC=m | 
 |  |  | +CONFIG_SND_SOC_FSL_XCVR=m | 
 |  |  | +CONFIG_SND_SOC_FSL_ESAI_CLIENT=y | 
 |  |  | +CONFIG_SND_SOC_FSL_RPMSG=m | 
 |  |  | +CONFIG_SND_IMX_SOC=m | 
 |  |  | +CONFIG_SND_SOC_IMX_SGTL5000=m | 
 |  |  | +CONFIG_SND_SOC_IMX_SPDIF=m | 
 |  |  | +CONFIG_SND_SOC_FSL_ASOC_CARD=m | 
 |  |  | +CONFIG_SND_SOC_IMX_AUDMIX=m | 
 |  |  | +CONFIG_SND_SOC_IMX_HDMI=m | 
 |  |  | +CONFIG_SND_SOC_IMX_CARD=m | 
 |  |  | +CONFIG_SND_SOC_IMX_PCM512X=m | 
 |  |  | +CONFIG_SND_SOC_SOF_TOPLEVEL=y | 
 |  |  | +CONFIG_SND_SOC_SOF_OF=m | 
 |  |  | +CONFIG_SND_SOC_SOF_IMX_TOPLEVEL=y | 
 |  |  | +CONFIG_SND_SOC_SOF_IMX8=m | 
 |  |  | +CONFIG_SND_SOC_SOF_IMX8M=m | 
 |  |  | +CONFIG_SND_SOC_SOF_IMX8ULP=m | 
 |  |  | +CONFIG_SND_SOC_AK4613=m | 
 |  |  | +CONFIG_SND_SOC_BT_SCO=y | 
 |  |  | +CONFIG_SND_SOC_CROS_EC_CODEC=m | 
 |  |  | +CONFIG_SND_SOC_CS42XX8_I2C=y | 
 |  |  | +CONFIG_SND_SOC_DMIC=m | 
 |  |  | +CONFIG_SND_SOC_ES7134=m | 
 |  |  | +CONFIG_SND_SOC_ES7241=m | 
 |  |  | +CONFIG_SND_SOC_GTM601=m | 
 |  |  | +CONFIG_SND_SOC_MAX98357A=m | 
 |  |  | +CONFIG_SND_SOC_MAX98927=m | 
 |  |  | +CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m | 
 |  |  | +CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m | 
 |  |  | +CONFIG_SND_SOC_PCM3168A_I2C=m | 
 |  |  | +CONFIG_SND_SOC_RT5659=m | 
 |  |  | +CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m | 
 |  |  | +CONFIG_SND_SOC_SIMPLE_MUX=m | 
 |  |  | +CONFIG_SND_SOC_SPDIF=m | 
 |  |  | +CONFIG_SND_SOC_TAS571X=m | 
 |  |  | +CONFIG_SND_SOC_WCD934X=m | 
 |  |  | +CONFIG_SND_SOC_WM8524=y | 
 |  |  | +CONFIG_SND_SOC_WM8904=m | 
 |  |  | +CONFIG_SND_SOC_WM8960=m | 
 |  |  | +CONFIG_SND_SOC_WM8962=m | 
 |  |  | +CONFIG_SND_SOC_WSA881X=m | 
 |  |  | +CONFIG_SND_SOC_RPMSG_WM8960=m | 
 |  |  | +CONFIG_SND_SOC_RPMSG_AK4497=m | 
 |  |  | +CONFIG_SND_SOC_LPASS_WSA_MACRO=m | 
 |  |  | +CONFIG_SND_SOC_LPASS_VA_MACRO=m | 
 |  |  | +CONFIG_SND_SIMPLE_CARD=y | 
 |  |  | +CONFIG_SND_AUDIO_GRAPH_CARD=y | 
 |  |  | +CONFIG_HID_MULTITOUCH=m | 
 |  |  | +CONFIG_I2C_HID_ACPI=m | 
 |  |  | +CONFIG_I2C_HID_OF=m | 
 |  |  | +CONFIG_USB_CONN_GPIO=y | 
 |  |  | +CONFIG_USB=y | 
 |  |  | +CONFIG_USB_OTG=y | 
 |  |  | +CONFIG_USB_XHCI_HCD=y | 
 |  |  | +CONFIG_USB_XHCI_PCI_RENESAS=m | 
 |  |  | +CONFIG_USB_EHCI_HCD=y | 
 |  |  | +CONFIG_USB_EHCI_HCD_PLATFORM=y | 
 |  |  | +CONFIG_USB_OHCI_HCD=y | 
 |  |  | +CONFIG_USB_OHCI_HCD_PLATFORM=y | 
 |  |  | +CONFIG_USB_HCD_TEST_MODE=y | 
 |  |  | +CONFIG_USB_ACM=m | 
 |  |  | +CONFIG_USB_STORAGE=y | 
 |  |  | +CONFIG_USB_UAS=y | 
 |  |  | +CONFIG_USB_CDNS_SUPPORT=y | 
 |  |  | +CONFIG_USB_CDNS3=y | 
 |  |  | +CONFIG_USB_CDNS3_GADGET=y | 
 |  |  | +CONFIG_USB_CDNS3_HOST=y | 
 |  |  | +CONFIG_USB_MUSB_HDRC=y | 
 |  |  | +CONFIG_USB_DWC3=y | 
 |  |  | +CONFIG_USB_DWC2=y | 
 |  |  | +CONFIG_USB_CHIPIDEA=y | 
 |  |  | +CONFIG_USB_CHIPIDEA_UDC=y | 
 |  |  | +CONFIG_USB_CHIPIDEA_HOST=y | 
 |  |  | +CONFIG_USB_ISP1760=y | 
 |  |  | +CONFIG_USB_SERIAL=y | 
 |  |  | +CONFIG_USB_SERIAL_CONSOLE=y | 
 |  |  | +CONFIG_USB_SERIAL_GENERIC=y | 
 |  |  | +CONFIG_USB_SERIAL_SIMPLE=y | 
 |  |  | +CONFIG_USB_SERIAL_CP210X=m | 
 |  |  | +CONFIG_USB_SERIAL_FTDI_SIO=y | 
 |  |  | +CONFIG_USB_SERIAL_OPTION=m | 
 |  |  | +CONFIG_USB_TEST=m | 
 |  |  | +CONFIG_USB_EHSET_TEST_FIXTURE=y | 
 |  |  | +CONFIG_USB_HSIC_USB3503=y | 
 |  |  | +CONFIG_NOP_USB_XCEIV=y | 
 |  |  | +CONFIG_USB_MXS_PHY=y | 
 |  |  | +CONFIG_USB_ULPI=y | 
 |  |  | +CONFIG_USB_GADGET=y | 
 |  |  | +CONFIG_USB_SNP_UDC_PLAT=y | 
 |  |  | +CONFIG_USB_BDC_UDC=y | 
 |  |  | +CONFIG_USB_CONFIGFS=y | 
 |  |  | +CONFIG_USB_CONFIGFS_SERIAL=y | 
 |  |  | +CONFIG_USB_CONFIGFS_ACM=y | 
 |  |  | +CONFIG_USB_CONFIGFS_OBEX=y | 
 |  |  | +CONFIG_USB_CONFIGFS_NCM=y | 
 |  |  | +CONFIG_USB_CONFIGFS_ECM=y | 
 |  |  | +CONFIG_USB_CONFIGFS_ECM_SUBSET=y | 
 |  |  | +CONFIG_USB_CONFIGFS_RNDIS=y | 
 |  |  | +CONFIG_USB_CONFIGFS_EEM=y | 
 |  |  | +CONFIG_USB_CONFIGFS_MASS_STORAGE=y | 
 |  |  | +CONFIG_USB_CONFIGFS_F_LB_SS=y | 
 |  |  | +CONFIG_USB_CONFIGFS_F_FS=y | 
 |  |  | +CONFIG_USB_CONFIGFS_F_UAC1=y | 
 |  |  | +CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y | 
 |  |  | +CONFIG_USB_CONFIGFS_F_UAC2=y | 
 |  |  | +CONFIG_USB_CONFIGFS_F_MIDI=y | 
 |  |  | +CONFIG_USB_CONFIGFS_F_HID=y | 
 |  |  | +CONFIG_USB_CONFIGFS_F_UVC=y | 
 |  |  | +CONFIG_USB_ZERO=m | 
 |  |  | +CONFIG_USB_AUDIO=m | 
 |  |  | +CONFIG_USB_ETH=m | 
 |  |  | +CONFIG_USB_MASS_STORAGE=m | 
 |  |  | +CONFIG_USB_G_SERIAL=m | 
 |  |  | +CONFIG_TYPEC=y | 
 |  |  | +CONFIG_TYPEC_TCPM=y | 
 |  |  | +CONFIG_TYPEC_TCPCI=y | 
 |  |  | +CONFIG_TYPEC_FUSB302=m | 
 |  |  | +CONFIG_TYPEC_TPS6598X=m | 
 |  |  | +CONFIG_TYPEC_HD3SS3220=m | 
 |  |  | +CONFIG_TYPEC_SWITCH_GPIO=y | 
 |  |  | +CONFIG_MMC=y | 
 |  |  | +CONFIG_MMC_BLOCK_MINORS=32 | 
 |  |  | +CONFIG_MMC_ARMMMCI=y | 
 |  |  | +CONFIG_MMC_SDHCI=y | 
 |  |  | +CONFIG_MMC_SDHCI_ACPI=y | 
 |  |  | +CONFIG_MMC_SDHCI_PLTFM=y | 
 |  |  | +CONFIG_MMC_SDHCI_OF_ARASAN=y | 
 |  |  | +CONFIG_MMC_SDHCI_OF_ESDHC=y | 
 |  |  | +CONFIG_MMC_SDHCI_CADENCE=y | 
 |  |  | +CONFIG_MMC_SDHCI_ESDHC_IMX=y | 
 |  |  | +CONFIG_MMC_SDHCI_F_SDH30=y | 
 |  |  | +CONFIG_MMC_SPI=y | 
 |  |  | +CONFIG_MMC_DW=y | 
 |  |  | +CONFIG_MMC_DW_EXYNOS=y | 
 |  |  | +CONFIG_MMC_DW_HI3798CV200=y | 
 |  |  | +CONFIG_MMC_DW_K3=y | 
 |  |  | +CONFIG_MMC_MTK=y | 
 |  |  | +CONFIG_MMC_SDHCI_XENON=y | 
 |  |  | +CONFIG_MMC_SDHCI_AM654=y | 
 |  |  | +CONFIG_SCSI_UFSHCD=y | 
 |  |  | +CONFIG_SCSI_UFSHCD_PLATFORM=y | 
 |  |  | +CONFIG_NEW_LEDS=y | 
 |  |  | +CONFIG_LEDS_CLASS=y | 
 |  |  | +CONFIG_LEDS_CLASS_MULTICOLOR=m | 
 |  |  | +CONFIG_LEDS_LM3692X=m | 
 |  |  | +CONFIG_LEDS_PCA9532=m | 
 |  |  | +CONFIG_LEDS_GPIO=y | 
 |  |  | +CONFIG_LEDS_PCA995X=m | 
 |  |  | +CONFIG_LEDS_PWM=y | 
 |  |  | +CONFIG_LEDS_SYSCON=y | 
 |  |  | +CONFIG_LEDS_TRIGGER_TIMER=y | 
 |  |  | +CONFIG_LEDS_TRIGGER_DISK=y | 
 |  |  | +CONFIG_LEDS_TRIGGER_HEARTBEAT=y | 
 |  |  | +CONFIG_LEDS_TRIGGER_CPU=y | 
 |  |  | +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y | 
 |  |  | +CONFIG_LEDS_TRIGGER_PANIC=y | 
 |  |  | +CONFIG_EDAC=y | 
 |  |  | +CONFIG_EDAC_GHES=y | 
 |  |  | +CONFIG_EDAC_LAYERSCAPE=m | 
 |  |  | +CONFIG_EDAC_SYNOPSYS=y | 
 |  |  | +CONFIG_RTC_CLASS=y | 
 |  |  | +CONFIG_RTC_DRV_DS1307=m | 
 |  |  | +CONFIG_RTC_DRV_HYM8563=m | 
 |  |  | +CONFIG_RTC_DRV_MAX77686=y | 
 |  |  | +CONFIG_RTC_DRV_RK808=m | 
 |  |  | +CONFIG_RTC_DRV_PCF85363=m | 
 |  |  | +CONFIG_RTC_DRV_M41T80=m | 
 |  |  | +CONFIG_RTC_DRV_RX8581=m | 
 |  |  | +CONFIG_RTC_DRV_RV3028=m | 
 |  |  | +CONFIG_RTC_DRV_RV8803=m | 
 |  |  | +CONFIG_RTC_DRV_S5M=y | 
 |  |  | +CONFIG_RTC_DRV_DS3232=y | 
 |  |  | +CONFIG_RTC_DRV_PCF2127=m | 
 |  |  | +CONFIG_RTC_DRV_PCF2131=m | 
 |  |  | +CONFIG_RTC_DRV_EFI=y | 
 |  |  | +CONFIG_RTC_DRV_CROS_EC=y | 
 |  |  | +CONFIG_RTC_DRV_FSL_FTM_ALARM=m | 
 |  |  | +CONFIG_RTC_DRV_PL031=y | 
 |  |  | +CONFIG_RTC_DRV_SNVS=y | 
 |  |  | +CONFIG_RTC_DRV_BBNSM=y | 
 |  |  | +CONFIG_RTC_DRV_IMX_SC=y | 
 |  |  | +CONFIG_RTC_DRV_IMX_RPMSG=y | 
 |  |  | +CONFIG_DMADEVICES=y | 
 |  |  | +CONFIG_BCM_SBA_RAID=m | 
 |  |  | +CONFIG_FSL_EDMA=y | 
 |  |  | +CONFIG_FSL_QDMA=m | 
 |  |  | +CONFIG_FSL_EDMA_V3=y | 
 |  |  | +CONFIG_IMX_SDMA=y | 
 |  |  | +CONFIG_MV_XOR_V2=y | 
 |  |  | +CONFIG_MXS_DMA=y | 
 |  |  | +CONFIG_MXC_PXP_V3=y | 
 |  |  | +CONFIG_PL330_DMA=y | 
 |  |  | +CONFIG_QCOM_HIDMA_MGMT=y | 
 |  |  | +CONFIG_QCOM_HIDMA=y | 
 |  |  | +CONFIG_DW_EDMA=y | 
 |  |  | +CONFIG_DW_EDMA_PCIE=y | 
 |  |  | +CONFIG_FSL_DPAA2_QDMA=m | 
 |  |  | +CONFIG_DMATEST=y | 
 |  |  | +CONFIG_DMABUF_HEAPS=y | 
 |  |  | +CONFIG_DMABUF_HEAPS_SYSTEM=y | 
 |  |  | +CONFIG_DMABUF_HEAPS_CMA=y | 
 |  |  | +CONFIG_DMABUF_HEAPS_DSP=y | 
 |  |  | +CONFIG_UIO_PCI_GENERIC=y | 
 |  |  | +CONFIG_UIO_IVSHMEM=y | 
 |  |  | +CONFIG_VFIO=y | 
 |  |  | +CONFIG_VFIO_PCI=y | 
 |  |  | +CONFIG_VFIO_FSL_MC=y | 
 |  |  | +CONFIG_VIRTIO_PCI=y | 
 |  |  | +CONFIG_VIRTIO_BALLOON=y | 
 |  |  | +CONFIG_VIRTIO_MMIO=y | 
 |  |  | +CONFIG_VIRTIO_IVSHMEM=y | 
 |  |  | +CONFIG_XEN_GNTDEV=y | 
 |  |  | +CONFIG_XEN_GRANT_DEV_ALLOC=y | 
 |  |  | +CONFIG_STAGING=y | 
 |  |  | +CONFIG_STAGING_MEDIA=y | 
 |  |  | +CONFIG_VIDEO_IMX_CAPTURE=y | 
 |  |  | +CONFIG_IMX8_MEDIA_DEVICE=m | 
 |  |  | +CONFIG_MHDP_HDMIRX=y | 
 |  |  | +CONFIG_MHDP_HDMIRX_CEC=y | 
 |  |  | +CONFIG_FSL_DPAA2=y | 
 |  |  | +CONFIG_FSL_PPFE=y | 
 |  |  | +CONFIG_FSL_PPFE_UTIL_DISABLED=y | 
 |  |  | +CONFIG_ETHOSU=y | 
 |  |  | +CONFIG_CHROME_PLATFORMS=y | 
 |  |  | +CONFIG_CROS_EC=y | 
 |  |  | +CONFIG_CROS_EC_I2C=y | 
 |  |  | +CONFIG_CROS_EC_SPI=y | 
 |  |  | +CONFIG_CROS_EC_CHARDEV=m | 
 |  |  | +CONFIG_CLK_VEXPRESS_OSC=y | 
 |  |  | +CONFIG_COMMON_CLK_RK808=y | 
 |  |  | +CONFIG_COMMON_CLK_SCMI=y | 
 |  |  | +CONFIG_COMMON_CLK_SCPI=y | 
 |  |  | +CONFIG_COMMON_CLK_CS2000_CP=y | 
 |  |  | +CONFIG_COMMON_CLK_FSL_SAI=y | 
 |  |  | +CONFIG_COMMON_CLK_S2MPS11=y | 
 |  |  | +CONFIG_COMMON_CLK_XGENE=y | 
 |  |  | +CONFIG_COMMON_CLK_PWM=y | 
 |  |  | +CONFIG_COMMON_CLK_VC5=y | 
 |  |  | +CONFIG_CLK_IMX8MM=y | 
 |  |  | +CONFIG_CLK_IMX8MN=y | 
 |  |  | +CONFIG_CLK_IMX8MP=y | 
 |  |  | +CONFIG_CLK_IMX8MQ=y | 
 |  |  | +CONFIG_CLK_IMX8QXP=y | 
 |  |  | +CONFIG_CLK_IMX8ULP=y | 
 |  |  | +CONFIG_CLK_IMX93=y | 
 |  |  | +CONFIG_HWSPINLOCK=y | 
 |  |  | +CONFIG_ARM_MHU=y | 
 |  |  | +CONFIG_IMX_MBOX=y | 
 |  |  | +CONFIG_PLATFORM_MHU=y | 
 |  |  | +CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y | 
 |  |  | +CONFIG_ARM_SMMU=y | 
 |  |  | +CONFIG_ARM_SMMU_V3=y | 
 |  |  | +CONFIG_REMOTEPROC=y | 
 |  |  | +CONFIG_IMX_REMOTEPROC=y | 
 |  |  | +CONFIG_IMX_DSP_REMOTEPROC=m | 
 |  |  | +CONFIG_RPMSG_CHAR=m | 
 |  |  | +CONFIG_RPMSG_CTRL=m | 
 |  |  | +CONFIG_RPMSG_QCOM_GLINK_RPM=y | 
 |  |  | +CONFIG_SOUNDWIRE=m | 
 |  |  | +CONFIG_SOUNDWIRE_QCOM=m | 
 |  |  | +CONFIG_SOC_BRCMSTB=y | 
 |  |  | +CONFIG_FSL_DPAA=y | 
 |  |  | +CONFIG_FSL_MC_DPIO=y | 
 |  |  | +CONFIG_FSL_RCPM=y | 
 |  |  | +CONFIG_FSL_QIXIS=y | 
 |  |  | +CONFIG_SOC_TI=y | 
 |  |  | +CONFIG_EXTCON_PTN5150=m | 
 |  |  | +CONFIG_EXTCON_USB_GPIO=y | 
 |  |  | +CONFIG_EXTCON_USBC_CROS_EC=y | 
 |  |  | +CONFIG_IIO=y | 
 |  |  | +CONFIG_FXLS8962AF_I2C=m | 
 |  |  | +CONFIG_IIO_ST_ACCEL_3AXIS=m | 
 |  |  | +CONFIG_IMX8QXP_ADC=y | 
 |  |  | +CONFIG_IMX93_ADC=y | 
 |  |  | +CONFIG_MAX9611=m | 
 |  |  | +CONFIG_QCOM_SPMI_VADC=m | 
 |  |  | +CONFIG_QCOM_SPMI_ADC5=m | 
 |  |  | +CONFIG_IIO_CROS_EC_SENSORS_CORE=m | 
 |  |  | +CONFIG_IIO_CROS_EC_SENSORS=m | 
 |  |  | +CONFIG_FXAS21002C=y | 
 |  |  | +CONFIG_IIO_ST_GYRO_3AXIS=m | 
 |  |  | +CONFIG_FXOS8700_I2C=y | 
 |  |  | +CONFIG_RPMSG_IIO_PEDOMETER=m | 
 |  |  | +CONFIG_INV_MPU6050_I2C=m | 
 |  |  | +CONFIG_IIO_ST_LSM6DSX=y | 
 |  |  | +CONFIG_IIO_CROS_EC_LIGHT_PROX=m | 
 |  |  | +CONFIG_SENSORS_ISL29018=y | 
 |  |  | +CONFIG_VCNL4000=m | 
 |  |  | +CONFIG_VCNL4035=m | 
 |  |  | +CONFIG_IIO_ST_MAGN_3AXIS=m | 
 |  |  | +CONFIG_IIO_CROS_EC_BARO=m | 
 |  |  | +CONFIG_MPL3115=y | 
 |  |  | +CONFIG_MS5611=m | 
 |  |  | +CONFIG_MS5611_I2C=m | 
 |  |  | +CONFIG_PWM=y | 
 |  |  | +CONFIG_PWM_ADP5585=y | 
 |  |  | +CONFIG_PWM_CROS_EC=m | 
 |  |  | +CONFIG_PWM_FSL_FTM=m | 
 |  |  | +CONFIG_PWM_IMX27=y | 
 |  |  | +CONFIG_PWM_RPCHIP=y | 
 |  |  | +CONFIG_PWM_SL28CPLD=m | 
 |  |  | +CONFIG_SL28CPLD_INTC=y | 
 |  |  | +CONFIG_RESET_IMX7=y | 
 |  |  | +CONFIG_RESET_IMX8ULP_SIM=y | 
 |  |  | +CONFIG_PHY_XGENE=y | 
 |  |  | +CONFIG_PHY_MIXEL_LVDS=y | 
 |  |  | +CONFIG_PHY_MIXEL_LVDS_COMBO=y | 
 |  |  | +CONFIG_PHY_CADENCE_SALVO=y | 
 |  |  | +CONFIG_PHY_FSL_IMX8MP_LVDS=y | 
 |  |  | +CONFIG_PHY_FSL_IMX93_MIPI_DPHY=y | 
 |  |  | +CONFIG_PHY_MIXEL_MIPI_DPHY=y | 
 |  |  | +CONFIG_PHY_FSL_IMX8M_PCIE=y | 
 |  |  | +CONFIG_PHY_FSL_IMX8Q_PCIE=y | 
 |  |  | +CONFIG_PHY_SAMSUNG_HDMI_PHY=y | 
 |  |  | +CONFIG_PHY_QCOM_USB_HS=y | 
 |  |  | +CONFIG_PHY_SAMSUNG_USB2=y | 
 |  |  | +CONFIG_ARM_CCI_PMU=m | 
 |  |  | +CONFIG_ARM_CCN=m | 
 |  |  | +CONFIG_ARM_CMN=m | 
 |  |  | +CONFIG_ARM_SMMU_V3_PMU=m | 
 |  |  | +CONFIG_ARM_DSU_PMU=m | 
 |  |  | +CONFIG_FSL_IMX8_DDR_PMU=y | 
 |  |  | +CONFIG_FSL_IMX9_DDR_PMU=y | 
 |  |  | +CONFIG_ARM_SPE_PMU=m | 
 |  |  | +CONFIG_ARM_DMC620_PMU=m | 
 |  |  | +CONFIG_HISI_PMU=y | 
 |  |  | +CONFIG_NVMEM_IMX_OCOTP=y | 
 |  |  | +CONFIG_NVMEM_IMX_OCOTP_SCU=y | 
 |  |  | +CONFIG_NVMEM_RMEM=m | 
 |  |  | +CONFIG_FPGA=y | 
 |  |  | +CONFIG_FPGA_BRIDGE=m | 
 |  |  | +CONFIG_ALTERA_FREEZE_BRIDGE=m | 
 |  |  | +CONFIG_FPGA_REGION=m | 
 |  |  | +CONFIG_OF_FPGA_REGION=m | 
 |  |  | +CONFIG_TEE=y | 
 |  |  | +CONFIG_OPTEE=y | 
 |  |  | +CONFIG_MUX_MMIO=y | 
 |  |  | +CONFIG_SLIM_QCOM_CTRL=m | 
 |  |  | +CONFIG_MXC_SIM=y | 
 |  |  | +CONFIG_MXC_GPU_VIV=y | 
 |  |  | +CONFIG_MXC_EMVSIM=y | 
 |  |  | +CONFIG_EXT2_FS=y | 
 |  |  | +CONFIG_EXT3_FS=y | 
 |  |  | +CONFIG_EXT4_FS_POSIX_ACL=y | 
 |  |  | +CONFIG_BTRFS_FS=m | 
 |  |  | +CONFIG_BTRFS_FS_POSIX_ACL=y | 
 |  |  | +CONFIG_FANOTIFY=y | 
 |  |  | +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y | 
 |  |  | +CONFIG_QUOTA=y | 
 |  |  | +CONFIG_AUTOFS4_FS=y | 
 |  |  | +CONFIG_FUSE_FS=m | 
 |  |  | +CONFIG_CUSE=m | 
 |  |  | +CONFIG_OVERLAY_FS=m | 
 |  |  | +CONFIG_VFAT_FS=y | 
 |  |  | +CONFIG_TMPFS_POSIX_ACL=y | 
 |  |  | +CONFIG_HUGETLBFS=y | 
 |  |  | +CONFIG_EFIVAR_FS=y | 
 |  |  | +CONFIG_JFFS2_FS=y | 
 |  |  | +CONFIG_UBIFS_FS=y | 
 |  |  | +CONFIG_SQUASHFS=y | 
 |  |  | +CONFIG_SQUASHFS_XZ=y | 
 |  |  | +CONFIG_NFS_FS=y | 
 |  |  | +CONFIG_NFS_V4=y | 
 |  |  | +CONFIG_NFS_V4_1=y | 
 |  |  | +CONFIG_NFS_V4_2=y | 
 |  |  | +CONFIG_ROOT_NFS=y | 
 |  |  | +CONFIG_9P_FS=y | 
 |  |  | +CONFIG_NLS_CODEPAGE_437=y | 
 |  |  | +CONFIG_NLS_ISO8859_1=y | 
 |  |  | +CONFIG_TRUSTED_KEYS=m | 
 |  |  | +# CONFIG_TRUSTED_KEYS_TPM is not set | 
 |  |  | +# CONFIG_TRUSTED_KEYS_TEE is not set | 
 |  |  | +CONFIG_SECURITY=y | 
 |  |  | +CONFIG_CRYPTO_USER=y | 
 |  |  | +CONFIG_CRYPTO_TEST=m | 
 |  |  | +CONFIG_CRYPTO_ANUBIS=m | 
 |  |  | +CONFIG_CRYPTO_ARIA=m | 
 |  |  | +CONFIG_CRYPTO_BLOWFISH=m | 
 |  |  | +CONFIG_CRYPTO_CAMELLIA=m | 
 |  |  | +CONFIG_CRYPTO_CAST5=m | 
 |  |  | +CONFIG_CRYPTO_CAST6=m | 
 |  |  | +CONFIG_CRYPTO_FCRYPT=m | 
 |  |  | +CONFIG_CRYPTO_KHAZAD=m | 
 |  |  | +CONFIG_CRYPTO_SEED=m | 
 |  |  | +CONFIG_CRYPTO_SERPENT=m | 
 |  |  | +CONFIG_CRYPTO_TEA=m | 
 |  |  | +CONFIG_CRYPTO_TWOFISH=m | 
 |  |  | +CONFIG_CRYPTO_ARC4=m | 
 |  |  | +CONFIG_CRYPTO_CFB=m | 
 |  |  | +CONFIG_CRYPTO_CTS=m | 
 |  |  | +CONFIG_CRYPTO_LRW=m | 
 |  |  | +CONFIG_CRYPTO_OFB=m | 
 |  |  | +CONFIG_CRYPTO_PCBC=m | 
 |  |  | +CONFIG_CRYPTO_CHACHA20POLY1305=m | 
 |  |  | +CONFIG_CRYPTO_ECHAINIV=y | 
 |  |  | +CONFIG_CRYPTO_TLS=m | 
 |  |  | +CONFIG_CRYPTO_MD4=m | 
 |  |  | +CONFIG_CRYPTO_RMD160=m | 
 |  |  | +CONFIG_CRYPTO_STREEBOG=m | 
 |  |  | +CONFIG_CRYPTO_VMAC=m | 
 |  |  | +CONFIG_CRYPTO_WP512=m | 
 |  |  | +CONFIG_CRYPTO_XCBC=m | 
 |  |  | +CONFIG_CRYPTO_ANSI_CPRNG=y | 
 |  |  | +CONFIG_CRYPTO_USER_API_HASH=m | 
 |  |  | +CONFIG_CRYPTO_USER_API_SKCIPHER=m | 
 |  |  | +CONFIG_CRYPTO_USER_API_RNG=m | 
 |  |  | +CONFIG_CRYPTO_USER_API_AEAD=m | 
 |  |  | +CONFIG_CRYPTO_CHACHA20_NEON=m | 
 |  |  | +CONFIG_CRYPTO_GHASH_ARM64_CE=y | 
 |  |  | +CONFIG_CRYPTO_SHA1_ARM64_CE=y | 
 |  |  | +CONFIG_CRYPTO_SHA2_ARM64_CE=y | 
 |  |  | +CONFIG_CRYPTO_SHA512_ARM64_CE=m | 
 |  |  | +CONFIG_CRYPTO_SHA3_ARM64=m | 
 |  |  | +CONFIG_CRYPTO_SM3_ARM64_CE=m | 
 |  |  | +CONFIG_CRYPTO_POLYVAL_ARM64_CE=m | 
 |  |  | +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y | 
 |  |  | +CONFIG_CRYPTO_AES_ARM64_BS=m | 
 |  |  | +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y | 
 |  |  | +CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m | 
 |  |  | +CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=m | 
 |  |  | +CONFIG_CRYPTO_DEV_FSL_CAAM=m | 
 |  |  | +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=m | 
 |  |  | +CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=m | 
 |  |  | +CONFIG_CRYPTO_DEV_CCREE=m | 
 |  |  | +CONFIG_CRYPTO_DEV_HISI_SEC2=m | 
 |  |  | +CONFIG_CRYPTO_DEV_HISI_ZIP=m | 
 |  |  | +CONFIG_CRYPTO_DEV_HISI_HPRE=m | 
 |  |  | +CONFIG_CRYPTO_DEV_HISI_TRNG=m | 
 |  |  | +CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m | 
 |  |  | +CONFIG_INDIRECT_PIO=y | 
 |  |  | +CONFIG_CRC_CCITT=m | 
 |  |  | +CONFIG_CRC8=y | 
 |  |  | +CONFIG_CMA_SIZE_MBYTES=32 | 
 |  |  | +CONFIG_PRINTK_TIME=y | 
 |  |  | +CONFIG_DEBUG_KERNEL=y | 
 |  |  | +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y | 
 |  |  | +CONFIG_DEBUG_INFO_REDUCED=y | 
 |  |  | +CONFIG_MAGIC_SYSRQ=y | 
 |  |  | +CONFIG_DEBUG_FS=y | 
 |  |  | +# CONFIG_SCHED_DEBUG is not set | 
 |  |  | +# CONFIG_DEBUG_PREEMPT is not set | 
 |  |  | +# CONFIG_FTRACE is not set | 
 |  |  | +CONFIG_CORESIGHT=y | 
 |  |  | +CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y | 
 |  |  | +CONFIG_CORESIGHT_CATU=m | 
 |  |  | +CONFIG_CORESIGHT_SINK_TPIU=m | 
 |  |  | +CONFIG_CORESIGHT_SINK_ETBV10=m | 
 |  |  | +CONFIG_CORESIGHT_SOURCE_ETM4X=y | 
 |  |  | +CONFIG_CORESIGHT_STM=m | 
 |  |  | +CONFIG_CORESIGHT_CPU_DEBUG=m | 
 |  |  | +CONFIG_CORESIGHT_CTI=m | 
 |  |  | +CONFIG_MEMTEST=y |