Update kernel build shell script to support igkboard-imx6ull

guowenxue

2023-12-22 d80f34b07dc4c64d19d1408e382a2dd41656b7c2

Update kernel build shell script to support igkboard-imx6ull

Signed-off-by: guowenxue <guowenxue@gmail.com>

 kernel/build.sh

@@ -42,12 +42,17 @@
    export GIT_URL=`jq -r ".bsp.giturl" $CONF_FILE | tr 'A-Z' 'a-z'`
    export CROSS_COMPILE=`jq -r ".bsp.cortexAtool" $CONF_FILE | tr 'A-Z' 'a-z'`

    export SRCS="linux-imx"
    export BRANCH=$BSP_VER
    export KER_PATH=$PRJ_PATH/linux-imx

    export JOBS=`cat /proc/cpuinfo | grep processor | wc -l`

    if [[ $BOARD =~ mx6ull ]] ; then
        export ARCH=arm
    else
    export ARCH=arm64
    export SRCS="linux-imx"
    fi
}

function build_kernel()
@@ -68,7 +73,7 @@

    cd $KER_PATH

    if [ ! -s arch/arm64/configs/$defconfig -a -s $patch_file ] ; then
    if [ ! -s arch/$ARCH/configs/$defconfig -a -s $patch_file ] ; then
        pr_warn "do patch for $KER_PATH now..."
        patch -p1 < $patch_file
    fi
@@ -88,13 +93,25 @@

    if [ -d $PRFX_PATH ] ; then
        rm -rf $PRFX_PATH/*
    else
        mkdir -p $PRFX_PATH
    fi

    # Install image
    cp arch/arm64/boot/Image $PRFX_PATH
    cp arch/arm64/boot/dts/freescale/${BOARD}.dtb $PRFX_PATH
    mkdir -p $PRFX_PATH/overlays

    # Install system image and device tree binaries

    if [[ $BOARD =~ 6ull ]] ; then
        set -x
        cp -f arch/${ARCH}/boot/zImage $PRFX_PATH
        cp -f arch/${ARCH}/boot/dts/${BOARD}.dtb $PRFX_PATH
        cp -f arch/${ARCH}/boot/dts/${BOARD}/*.dtbo $PRFX_PATH/overlays
        set +x
    else
        set -x
        cp -f arch/${ARCH}/boot/Image $PRFX_PATH
        cp -f arch/${ARCH}/boot/dts/freescale/${BOARD}.dtb $PRFX_PATH
        cp -f arch/${ARCH}/boot/dts/freescale/${BOARD}/*.dtbo $PRFX_PATH/overlays
        set +x
    fi

    # Install kernel modules
    make modules_install INSTALL_MOD_PATH=$PRFX_PATH INSTALL_MOD_STRIP=1
@@ -105,8 +122,8 @@

    if [[ -n "$INST_PATH" && -w $INST_PATH ]] ; then
        pr_info "install linux kernel to '$INST_PATH'"
        cp $PRFX_PATH/Image $INST_PATH
        cp $PRFX_PATH/${BOARD}.dtb $INST_PATH
        cp -f $PRFX_PATH/*Image $INST_PATH
        cp -f $PRFX_PATH/${BOARD}.dtb $INST_PATH
    fi
}


 kernel/patches/gen_patch.sh

@@ -58,7 +58,6 @@

if [ $# != 1 ] ; then
    pr_info "$0 usage example:"
    pr_info "$0 uboot-imx/"
    pr_info "$0 linux-imx/"
    exit
fi

 kernel/patches/igkboard-imx6ull/linux-imx-lf-6.1.36-2.1.0.patch

New file
@@ -0,0 +1,1958 @@
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 30408b4b2..80faa210e 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1749,3 +1749,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
     aspeed-bmc-vegman-n110.dtb \
     aspeed-bmc-vegman-rx20.dtb \
     aspeed-bmc-vegman-sx20.dtb
+
+DTC_FLAGS_igkboard-imx6ull := -@
+dtb-$(CONFIG_SOC_IMX6UL) += igkboard-imx6ull.dtb
+subdir-$(CONFIG_SOC_IMX6UL) += igkboard-imx6ull
diff --git a/arch/arm/boot/dts/igkboard-imx6ull.dts b/arch/arm/boot/dts/igkboard-imx6ull.dts
new file mode 100644
index 000000000..ef885fed2
--- /dev/null
+++ b/arch/arm/boot/dts/igkboard-imx6ull.dts
@@ -0,0 +1,604 @@
+/*
+ * Device Tree Source for LingYun IGKBoard-IMX6ULL(IoT Gateway Kit Board based on i.MX6ULL)
+ * Based on imx6ul-14x14-evk.dts/imx6ul-14x14-evk.dtsi
+ *
+ * Copyright (C) 2022 LingYun IoT System Studio.
+ * Author: Guo Wenxue<guowenxue@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "imx6ull.dtsi"
+
+/ {
+    model = "LingYun IoT System Studio IoT Gateway Kits Board Based on i.MX6ULL";
+    compatible = "lingyun,igkboard-imx6ull", "fsl,imx6ull";
+
+    chosen {
+        stdout-path = &uart1;
+    };
+
+    memory@80000000 {
+        device_type = "memory";
+        reg = <0x80000000 0x20000000>;
+    };
+
+    reserved-memory {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges;
+
+        linux,cma {
+            compatible = "shared-dma-pool";
+            reusable;
+            size = <0xa000000>;
+            linux,cma-default;
+        };
+    };
+
+    buzzer: pwm-buzzer {
+        compatible = "pwm-beeper";
+        pwms = <&pwm2 0 500000>;
+        status = "okay";
+    };
+
+    leds {
+        compatible = "gpio-leds";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_gpio_leds>;
+        status = "okay";
+
+        sysled {
+            lable = "sysled";
+            gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
+            linux,default-trigger = "heartbeat";
+            default-state = "off";
+        };
+    };
+
+    keys {
+        compatible = "gpio-keys";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_gpio_keys>;
+        autorepeat;
+        status = "okay";
+
+        key_user {
+            lable = "key_user";
+            gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
+            linux,code = <KEY_ENTER>;
+        };
+    };
+
+    pxp_v4l2 {
+        compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
+        status = "okay";
+    };
+
+    reg_sd1_vmmc: regulator-sd1-vmmc {
+        compatible = "regulator-fixed";
+        regulator-name = "VSD_3V3";
+        regulator-min-microvolt = <3300000>;
+        regulator-max-microvolt = <3300000>;
+        gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+        off-on-delay-us = <20000>;
+        enable-active-high;
+    };
+
+    reg_peri_3v3: regulator-peri-3v3 {
+        compatible = "regulator-fixed";
+        regulator-name = "VPERI_3V3";
+        regulator-min-microvolt = <3300000>;
+        regulator-max-microvolt = <3300000>;
+        /*
+         * If you want to want to make this dynamic please
+         * check schematics and test all affected peripherals:
+         *
+         * - sensors
+         * - ethernet phy
+         * - can
+         * - bluetooth
+         * - wm8960 audio codec
+         * - ov5640 camera
+         */
+        regulator-always-on;
+    };
+
+    reg_can_3v3: regulator@0 {
+        compatible = "regulator-fixed";
+        regulator-name = "can-3v3";
+        regulator-min-microvolt = <3300000>;
+        regulator-max-microvolt = <3300000>;
+        regulator-boot-on;
+        regulator-always-on;
+    };
+
+    reg_3p3v: 3p3v {
+        compatible = "regulator-fixed";
+        regulator-name = "3P3V";
+        regulator-min-microvolt = <3300000>;
+        regulator-max-microvolt = <3300000>;
+        regulator-boot-on;
+        regulator-always-on;
+    };
+
+    reg_1p8v: 1p8v {
+        compatible = "regulator-fixed";
+        regulator-name = "1P8V";
+        regulator-min-microvolt = <1800000>;
+        regulator-max-microvolt = <1800000>;
+        regulator-boot-on;
+        regulator-always-on;
+    };
+
+    backlight_lcd: backlight-lcd {
+        compatible = "pwm-backlight";
+        pwms = <&pwm1 0 5000000>;
+        brightness-levels = <0 4 8 16 32 64 128 255>;
+        default-brightness-level = <7>;
+        power-supply = <&reg_3p3v>;
+        status = "disabled";
+    };
+
+    /* 1-Wire sentinel for overlay */
+    w1: w1 {
+        compatible = "w1-gpio";
+        status = "disabled";
+    };
+
+    mqs: mqs {
+        #sound-dai-cells = <0>;
+        compatible = "fsl,imx6sx-mqs";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_mqs>;
+        clocks = <&clks IMX6UL_CLK_SAI1>;
+        clock-names = "mclk";
+        gpr = <&gpr>;
+        status = "okay";
+    };
+
+    sound-mqs {
+        compatible = "fsl,imx-audio-mqs";
+        model = "mqs-audio";
+        audio-cpu = <&sai1>;
+        audio-asrc = <&asrc>;
+        audio-codec = <&mqs>;
+        status = "okay";
+    };
+
+    /* LCD panel sentinel for overlay */
+    panel: panel {
+        status = "disabled";
+    };
+
+};
+
+/*+--------------+
+  | Misc Modules |
+  +--------------+*/
+
+&snvs_poweroff {
+    status = "okay";
+};
+
+&snvs_pwrkey {
+    status = "okay";
+};
+
+&uart1 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_uart1>;
+    status = "okay";
+};
+
+&pwm1 { /* backlight */
+    #pwm-cells = <2>;
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_pwm1>;
+    status = "okay";
+};
+
+&pwm2 {
+    #pwm-cells = <2>;
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_pwm2>;
+    status = "okay";
+};
+
+/*+---------------+
+  | Camera Module |
+  +---------------+*/
+
+&i2c2 {
+    clock-frequency = <100000>;
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_i2c2>;
+    status = "okay";
+
+    gt9xx@5d {
+        compatible = "goodix,gt9147";
+        reg = <0x5d>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ts_pins>;
+
+        irq-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+        reset-gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
+        interrupt-parent = <&gpio5>;
+        interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+
+        status = "disabled"; /* Enable in LCD overlay */
+    };
+
+    rtc@6f {
+        compatible = "isil,isl1208";
+        reg = <0x6f>;
+        status = "okay";
+    };
+
+    ov5640: ov5640@3c {
+        compatible = "ovti,ov5640";
+        reg = <0x3c>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_csi1>;
+        clocks = <&clks IMX6UL_CLK_CSI>;
+        clock-names = "csi_mclk";
+
+        DOVDD-supply = <&reg_3p3v>;
+        VDD-supply = <&reg_1p8v>;
+        AVDD-supply = <&reg_3p3v>;
+        DVDD-supply = <&reg_3p3v>;
+
+        pwn-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;
+        rst-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
+        csi_id = <0>;
+        mclk = <24000000>;
+        mclk_source = <0>;
+        /* rotation = <180>; */
+        status = "disabled"; /* Enable in CAM overlay */
+        port {
+            ov5640_ep: endpoint {
+                remote-endpoint = <&csi1_ep>;
+            };
+        };
+    };
+
+};
+
+&csi {
+    status = "disabled";
+    port {
+        csi1_ep: endpoint {
+            remote-endpoint = <&ov5640_ep>;
+        };
+    };
+};
+
+/*+--------------+
+  | Audio Module |
+  +--------------+*/
+
+&clks {
+    assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+    //assigned-clock-rates = <786432000>; // 16bit,2Ch,48KHz
+    assigned-clock-rates = <722534400>; // 16bit,2Ch,44.1KHz
+};
+
+&sai1 {
+    assigned-clocks = <&clks IMX6UL_CLK_SAI1_SEL>, <&clks IMX6UL_CLK_SAI1>;
+    assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+    //assigned-clock-rates = <0>, <24576000>; // 16bit,2Ch,48KHz
+    assigned-clock-rates = <0>, <22579200>; // 16bit,2Ch,44.1KHz
+    fsl,sai-mclk-direction-output;
+    status = "okay";
+};
+
+/*+------------------+
+  | Ethernet Modules |
+  +------------------+*/
+
+&fec1 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_enet1>;
+    phy-mode = "rmii";
+    phy-handle = <&ethphy0>;
+    phy-supply = <&reg_peri_3v3>;
+    phy-reset-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>;
+    phy-reset-duration = <50>;
+    phy-reset-post-delay = <15>;
+    status = "okay";
+};
+
+&fec2 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_enet2>;
+    phy-mode = "rmii";
+    phy-handle = <&ethphy1>;
+    phy-supply = <&reg_peri_3v3>;
+    phy-reset-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
+    phy-reset-duration = <50>;
+    phy-reset-post-delay = <15>;
+    status = "okay";
+
+    mdio {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        ethphy0: ethernet-phy@0 {
+            compatible = "ethernet-phy-id0022.1560";
+            reg = <0>;
+            micrel,led-mode = <1>;
+            clocks = <&clks IMX6UL_CLK_ENET_REF>;
+            clock-names = "rmii-ref";
+
+        };
+
+        ethphy1: ethernet-phy@1 {
+            compatible = "ethernet-phy-id0022.1560";
+            reg = <1>;
+            micrel,led-mode = <1>;
+            clocks = <&clks IMX6UL_CLK_ENET2_REF>;
+            clock-names = "rmii-ref";
+        };
+    };
+};
+
+/*+---------------+
+  | USB interface |
+  +---------------+*/
+
+&usbotg1 {
+    dr_mode = "otg";
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_usb_otg1>;
+    status = "okay";
+};
+
+&usbotg2 {
+    dr_mode = "host";
+    disable-over-current;
+    status = "okay";
+};
+
+&usbphy1 {
+    fsl,tx-d-cal = <106>;
+};
+
+&usbphy2 {
+    fsl,tx-d-cal = <106>;
+};
+
+/*+------------------+
+  | USDCHC interface |
+  +------------------+*/
+
+&usdhc1 {
+    pinctrl-names = "default", "state_100mhz", "state_200mhz";
+    pinctrl-0 = <&pinctrl_usdhc1>;
+    pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+    pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+    cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+    keep-power-in-suspend;
+    wakeup-source;
+    vmmc-supply = <&reg_sd1_vmmc>;
+    status = "okay";
+};
+
+&usdhc2 {
+    pinctrl-names = "default", "state_100mhz", "state_200mhz";
+    pinctrl-0 = <&pinctrl_usdhc2_8bit>;
+    pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>;
+    pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>;
+    non-removable;
+    bus-width = <8>;
+    keep-power-in-suspend;
+    wakeup-source;
+    status = "okay";
+};
+
+/*+----------------------+
+  | Basic pinctrl iomuxc |
+  +----------------------+*/
+
+&iomuxc {
+    pinctrl-names = "default";
+
+    pinctrl_gpio_leds: gpio-leds {
+        fsl,pins = <
+            MX6UL_PAD_NAND_DQS__GPIO4_IO16            0x17059 /* led run */
+        >;
+    };
+
+    pinctrl_gpio_keys: gpio-keys {
+        fsl,pins = <
+            MX6UL_PAD_NAND_CE1_B__GPIO4_IO14        0x17059 /* gpio key */
+        >;
+    };
+
+    pinctrl_mqs: pinctrl-mqs-pins {
+        fsl,pins = <
+            MX6UL_PAD_JTAG_TDI__MQS_LEFT            0x11088 /* MQS Left  */
+            MX6UL_PAD_JTAG_TDO__MQS_RIGHT            0x11088 /* MQS Right */
+        >;
+    };
+
+    pinctrl_ts_pins: pinctrl-ts-pins {
+        fsl,pins = <
+            MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02        0x17059 /* TouchScreen IRQ */
+            MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03        0x17059 /* TouchScreen RST */
+        >;
+    };
+
+    pinctrl_csi1: csi1grp {
+        fsl,pins = <
+            MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05        0x17059 /* CSI_RST */
+            MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06        0x17059 /* CSI_PWDN */
+            MX6UL_PAD_CSI_MCLK__CSI_MCLK        0x1b088
+            MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK    0x1b088
+            MX6UL_PAD_CSI_VSYNC__CSI_VSYNC        0x1b088
+            MX6UL_PAD_CSI_HSYNC__CSI_HSYNC        0x1b088
+            MX6UL_PAD_CSI_DATA00__CSI_DATA02    0x1b088
+            MX6UL_PAD_CSI_DATA01__CSI_DATA03    0x1b088
+            MX6UL_PAD_CSI_DATA02__CSI_DATA04    0x1b088
+            MX6UL_PAD_CSI_DATA03__CSI_DATA05    0x1b088
+            MX6UL_PAD_CSI_DATA04__CSI_DATA06    0x1b088
+            MX6UL_PAD_CSI_DATA05__CSI_DATA07    0x1b088
+            MX6UL_PAD_CSI_DATA06__CSI_DATA08    0x1b088
+            MX6UL_PAD_CSI_DATA07__CSI_DATA09    0x1b088
+        >;
+    };
+
+    pinctrl_enet1: enet1grp {
+        fsl,pins = <
+            MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN    0x1b0b0
+            MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER    0x1b0b0
+            MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00    0x1b0b0
+            MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01    0x1b0b0
+            MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN    0x1b0b0
+            MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00    0x1b0b0
+            MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01    0x1b0b0
+            MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1    0x4001b031
+            MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07        0x10B0
+        >;
+    };
+
+    pinctrl_enet2: enet2grp {
+        fsl,pins = <
+            MX6UL_PAD_GPIO1_IO07__ENET2_MDC        0x1b0b0
+            MX6UL_PAD_GPIO1_IO06__ENET2_MDIO    0x1b0b0
+            MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN    0x1b0b0
+            MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER    0x1b0b0
+            MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00    0x1b0b0
+            MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01    0x1b0b0
+            MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN    0x1b0b0
+            MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00    0x1b0b0
+            MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01    0x1b0b0
+            MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2    0x4001b031
+            MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04        0x10B0
+        >;
+    };
+
+    pinctrl_i2c2: i2c2grp {
+        fsl,pins = <
+            MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
+            MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
+        >;
+    };
+
+    pinctrl_pwm1: pwm1grp {
+        fsl,pins = <
+            MX6UL_PAD_GPIO1_IO08__PWM1_OUT            0x110b0
+        >;
+    };
+
+    pinctrl_pwm2: pwm2grp {
+        fsl,pins = <
+            MX6UL_PAD_GPIO1_IO09__PWM2_OUT            0x110b0
+        >;
+    };
+
+    pinctrl_uart1: uart1grp {
+        fsl,pins = <
+            MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+            MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+        >;
+    };
+
+    pinctrl_usb_otg1: usbotg1grp {
+        fsl,pins = <
+            MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID    0x17059
+        >;
+    };
+
+    pinctrl_usdhc1: usdhc1grp {
+        fsl,pins = <
+            MX6UL_PAD_SD1_CMD__USDHC1_CMD         0x17059
+            MX6UL_PAD_SD1_CLK__USDHC1_CLK        0x10071
+            MX6UL_PAD_SD1_DATA0__USDHC1_DATA0     0x17059
+            MX6UL_PAD_SD1_DATA1__USDHC1_DATA1     0x17059
+            MX6UL_PAD_SD1_DATA2__USDHC1_DATA2     0x17059
+            MX6UL_PAD_SD1_DATA3__USDHC1_DATA3     0x17059
+            MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059
+        >;
+    };
+
+    pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+        fsl,pins = <
+            MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
+            MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
+            MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
+            MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
+            MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
+            MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
+
+        >;
+    };
+
+    pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+        fsl,pins = <
+            MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
+            MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
+            MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
+            MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
+            MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
+            MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
+        >;
+    };
+
+    pinctrl_usdhc2: usdhc2grp {
+        fsl,pins = <
+            MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x17059
+            MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
+            MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+            MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+            MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+            MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+        >;
+    };
+
+    pinctrl_usdhc2_8bit: usdhc2grp_8bit {
+        fsl,pins = <
+            MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x10069
+            MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
+            MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+            MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+            MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+            MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+            MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
+            MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
+            MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
+            MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
+        >;
+    };
+
+    pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz {
+        fsl,pins = <
+            MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x100b9
+            MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x170b9
+            MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
+            MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
+            MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
+            MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
+            MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
+            MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
+            MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
+            MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
+        >;
+    };
+
+    pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz {
+        fsl,pins = <
+            MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x100f9
+            MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x170f9
+            MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
+            MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
+            MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
+            MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
+            MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
+            MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
+            MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
+            MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
+        >;
+    };	
+
+};
+
diff --git a/arch/arm/boot/dts/igkboard-imx6ull/Makefile b/arch/arm/boot/dts/igkboard-imx6ull/Makefile
new file mode 100644
index 000000000..563d3fe8d
--- /dev/null
+++ b/arch/arm/boot/dts/igkboard-imx6ull/Makefile
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0
+# required for overlay support
+
+DTC_FLAGS += -@
+dtb-y += can1.dtbo
+dtb-y += can2.dtbo
+dtb-y += i2c1.dtbo
+dtb-y += spi1.dtbo
+dtb-y += uart2.dtbo
+dtb-y += uart3.dtbo
+dtb-y += uart4.dtbo
+dtb-y += uart7.dtbo
+dtb-y += pwm7.dtbo
+dtb-y += pwm8.dtbo
+dtb-y += w1.dtbo
+dtb-y += lcd.dtbo
+dtb-y += cam.dtbo
+dtb-y += nbiot-4g.dtbo
+dtb-y += adc.dtbo
diff --git a/arch/arm/boot/dts/igkboard-imx6ull/adc.dts b/arch/arm/boot/dts/igkboard-imx6ull/adc.dts
new file mode 100644
index 000000000..e06d67907
--- /dev/null
+++ b/arch/arm/boot/dts/igkboard-imx6ull/adc.dts
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2022 LingYun IoT System Studio
+ * Author:  Guo Wenxue<guowenxue@gmail.com>
+ */
+/dts-v1/;
+/plugin/;
+
+#include "../imx6ul-pinfunc.h"
+
+/* 40-pin extended GPIO, ADC interfaces */
+
+&adc1 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_adc1>;
+    num-channels = <5>;
+    vref-supply = <&reg_peri_3v3>;
+    status = "okay";
+};
+
+&iomuxc {
+    pinctrl_adc1: adc1grp {
+        fsl,pins = <
+            MX6UL_PAD_GPIO1_IO01__GPIO1_IO01        0xb0 /* ADC1_1 --->TS_YN */
+            MX6UL_PAD_GPIO1_IO04__GPIO1_IO04        0xb0 /* ADC1_4 --->TS_XP */
+        >;
+    };
+};
diff --git a/arch/arm/boot/dts/igkboard-imx6ull/cam.dts b/arch/arm/boot/dts/igkboard-imx6ull/cam.dts
new file mode 100644
index 000000000..d4435f0d1
--- /dev/null
+++ b/arch/arm/boot/dts/igkboard-imx6ull/cam.dts
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2022 LingYun IoT System Studio
+ * Author:  Guo Wenxue<guowenxue@gmail.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/* MIPI-DSI2 camera overlay */
+
+&pxp { /* Pixel Pipeline (PXP) is a memory-to-memory graphics processing */
+    status = "okay";
+};
+
+&csi {
+    status = "okay";
+};
+
+&i2c2 {
+    ov5640@3c {
+        status = "okay";
+    };
+};
+
diff --git a/arch/arm/boot/dts/igkboard-imx6ull/can1.dts b/arch/arm/boot/dts/igkboard-imx6ull/can1.dts
new file mode 100644
index 000000000..fe57e00bb
--- /dev/null
+++ b/arch/arm/boot/dts/igkboard-imx6ull/can1.dts
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2022 LingYun IoT System Studio
+ * Author:  Guo Wenxue<guowenxue@gmail.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "../imx6ul-pinfunc.h"
+
+/* 40-pin extended GPIO, CAN1 interfaces */
+
+&can1 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_flexcan1>;
+    xceiver-supply = <&reg_can_3v3>;
+    status = "okay";
+};
+
+&iomuxc {
+    pinctrl_flexcan1: flexcan1grp{
+        fsl,pins = <
+            MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX    0x1b020
+            MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX    0x1b020
+        >;
+    };	
+};
+
diff --git a/arch/arm/boot/dts/igkboard-imx6ull/can2.dts b/arch/arm/boot/dts/igkboard-imx6ull/can2.dts
new file mode 100644
index 000000000..7eada165a
--- /dev/null
+++ b/arch/arm/boot/dts/igkboard-imx6ull/can2.dts
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2022 LingYun IoT System Studio
+ * Author:  Guo Wenxue<guowenxue@gmail.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "../imx6ul-pinfunc.h"
+
+/* 40-pin extended GPIO, CAN2 interfaces */
+
+&can2 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_flexcan2>;
+    xceiver-supply = <&reg_can_3v3>;
+    status = "okay";
+};
+
+&iomuxc {
+    pinctrl_flexcan2: flexcan2grp{
+        fsl,pins = <
+            MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX    0x1b020
+            MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX    0x1b020
+        >;
+    };
+};
+
diff --git a/arch/arm/boot/dts/igkboard-imx6ull/i2c1.dts b/arch/arm/boot/dts/igkboard-imx6ull/i2c1.dts
new file mode 100644
index 000000000..ce99b9a18
--- /dev/null
+++ b/arch/arm/boot/dts/igkboard-imx6ull/i2c1.dts
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2022 LingYun IoT System Studio
+ * Author:  Guo Wenxue<guowenxue@gmail.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "../imx6ul-pinfunc.h"
+
+/* 40-pin extended GPIO, I2C1 interfaces */
+
+&i2c1 {
+    clock-frequency = <100000>;
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_i2c1>;
+    status = "okay";
+};
+
+&iomuxc {
+    pinctrl_i2c1: i2c1grp {
+        fsl,pins = <
+            MX6UL_PAD_GPIO1_IO02__I2C1_SCL    0x4001b8b0
+            MX6UL_PAD_GPIO1_IO03__I2C1_SDA    0x4001b8b0
+        >;
+    };	
+};
+
diff --git a/arch/arm/boot/dts/igkboard-imx6ull/lcd.dts b/arch/arm/boot/dts/igkboard-imx6ull/lcd.dts
new file mode 100644
index 000000000..ef1c479bf
--- /dev/null
+++ b/arch/arm/boot/dts/igkboard-imx6ull/lcd.dts
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2022 LingYun IoT System Studio
+ * Author:  Guo Wenxue<guowenxue@gmail.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/imx6ul-clock.h>
+#include "../imx6ul-pinfunc.h"
+
+/* LCD DRM display overlay */
+
+&backlight_lcd {
+    status = "okay";
+};
+
+&i2c2 {
+    gt9xx@5d {
+        status = "okay";
+    };
+};
+
+&lcdif {
+    assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>;
+    assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>;
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>;
+    status = "okay";
+
+    port {
+        display_output: endpoint {
+            remote-endpoint = <&panel_input>;
+        };
+    };
+};
+
+&panel {
+    compatible = "lingyun,igkboard-imx6ull-panel", "panel-simple";
+    backlight = <&backlight_lcd>;
+    power-supply = <&reg_3p3v>;
+    status = "okay";
+
+    port {
+        panel_input: endpoint {
+            remote-endpoint = <&display_output>;
+        };
+    };
+};
+
+&iomuxc {
+    pinctrl_lcdif_dat: lcdifdatgrp {
+        fsl,pins = <
+            MX6UL_PAD_LCD_DATA00__LCDIF_DATA00    0x79
+            MX6UL_PAD_LCD_DATA01__LCDIF_DATA01    0x79
+            MX6UL_PAD_LCD_DATA02__LCDIF_DATA02    0x79
+            MX6UL_PAD_LCD_DATA03__LCDIF_DATA03    0x79
+            MX6UL_PAD_LCD_DATA04__LCDIF_DATA04    0x79
+            MX6UL_PAD_LCD_DATA05__LCDIF_DATA05    0x79
+            MX6UL_PAD_LCD_DATA06__LCDIF_DATA06    0x79
+            MX6UL_PAD_LCD_DATA07__LCDIF_DATA07    0x79
+            MX6UL_PAD_LCD_DATA08__LCDIF_DATA08    0x79
+            MX6UL_PAD_LCD_DATA09__LCDIF_DATA09    0x79
+            MX6UL_PAD_LCD_DATA10__LCDIF_DATA10    0x79
+            MX6UL_PAD_LCD_DATA11__LCDIF_DATA11    0x79
+            MX6UL_PAD_LCD_DATA12__LCDIF_DATA12    0x79
+            MX6UL_PAD_LCD_DATA13__LCDIF_DATA13    0x79
+            MX6UL_PAD_LCD_DATA14__LCDIF_DATA14    0x79
+            MX6UL_PAD_LCD_DATA15__LCDIF_DATA15    0x79
+        >;
+    };
+
+    pinctrl_lcdif_ctrl: lcdifctrlgrp {
+        fsl,pins = <
+            MX6UL_PAD_LCD_CLK__LCDIF_CLK        0x79
+            MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE    0x79
+            MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
+            MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
+            MX6UL_PAD_LCD_RESET__LCDIF_RESET    0x79
+        >;
+    };
+};
\ No newline at end of file
diff --git a/arch/arm/boot/dts/igkboard-imx6ull/nbiot-4g.dts b/arch/arm/boot/dts/igkboard-imx6ull/nbiot-4g.dts
new file mode 100644
index 000000000..07e278e7e
--- /dev/null
+++ b/arch/arm/boot/dts/igkboard-imx6ull/nbiot-4g.dts
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2022 LingYun IoT System Studio
+ * Author:  Guo Wenxue<guowenxue@gmail.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "../imx6ul-pinfunc.h"
+
+/* NB-IoT/4G module use UART8 interfaces, conflict with SPI interface */
+
+&uart8 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_spi_uart8 &pinctrl_nbiot_ctrl>;
+    status = "okay";
+};
+
+&iomuxc {
+    pinctrl_spi_uart8: spi_uart8_grp {
+        fsl,pins = <
+            MX6UL_PAD_LCD_DATA20__UART8_DCE_TX        0x1b0b1 /* MRXD */
+            MX6UL_PAD_LCD_DATA21__UART8_DCE_RX        0x1b0b1 /* MTXD */
+        >;
+    };
+
+    pinctrl_nbiot_ctrl: nbiot_ctrl_grp {
+        fsl,pins = <
+            MX6UL_PAD_LCD_DATA22__GPIO3_IO27        0x17059 /* NB_PWREN/4G_RESET */
+            MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15        0x17059 /* NB_MRST/4G_POWER_KEY */
+        >;
+    };
+};
+
diff --git a/arch/arm/boot/dts/igkboard-imx6ull/pwm7.dts b/arch/arm/boot/dts/igkboard-imx6ull/pwm7.dts
new file mode 100644
index 000000000..6467a21a6
--- /dev/null
+++ b/arch/arm/boot/dts/igkboard-imx6ull/pwm7.dts
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2022 LingYun IoT System Studio
+ * Author:  Guo Wenxue<guowenxue@gmail.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/imx6ul-clock.h>
+#include "../imx6ul-pinfunc.h"
+
+/* 40-pin extended GPIO, PWM7 interfaces */
+
+&pwm7 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_pwm7>;
+    clocks = <&clks IMX6UL_CLK_PWM7>, <&clks IMX6UL_CLK_PWM7>;
+    status = "okay";
+};
+
+&iomuxc {
+    pinctrl_pwm7: pwm7grp {
+        fsl,pins = <
+            MX6UL_PAD_JTAG_TCK__PWM7_OUT    0x110b0
+        >;
+    };
+};
+
diff --git a/arch/arm/boot/dts/igkboard-imx6ull/pwm8.dts b/arch/arm/boot/dts/igkboard-imx6ull/pwm8.dts
new file mode 100644
index 000000000..edfc3a7b6
--- /dev/null
+++ b/arch/arm/boot/dts/igkboard-imx6ull/pwm8.dts
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2022 LingYun IoT System Studio
+ * Author:  Guo Wenxue<guowenxue@gmail.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/imx6ul-clock.h>
+#include "../imx6ul-pinfunc.h"
+
+/* 40-pin extended GPIO, PWM8 interfaces, conflict with NB-IoT */
+
+&pwm8 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_pwm8_nbiot>;
+    clocks = <&clks IMX6UL_CLK_PWM8>, <&clks IMX6UL_CLK_PWM8>;
+    status = "okay";
+};
+
+&iomuxc {
+    pinctrl_pwm8_nbiot: pwm8nbiotgrp {
+        fsl,pins = <
+            MX6UL_PAD_JTAG_TRST_B__PWM8_OUT    0x110b0
+        >;
+    };
+};
+
diff --git a/arch/arm/boot/dts/igkboard-imx6ull/spi1.dts b/arch/arm/boot/dts/igkboard-imx6ull/spi1.dts
new file mode 100644
index 000000000..a32dc451b
--- /dev/null
+++ b/arch/arm/boot/dts/igkboard-imx6ull/spi1.dts
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2022 LingYun IoT System Studio
+ * Author:  Guo Wenxue<guowenxue@gmail.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "../imx6ul-pinfunc.h"
+
+/* 40-pin extended GPIO, SPI1 interfaces, conflict with UART8 */
+
+&ecspi1 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_spi_uart8>;
+    cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
+    status = "okay";
+
+    #address-cells = <1>;
+    #size-cells = <0>;
+
+    spidev0: spi@0 {
+        reg = <0>;
+        compatible = "semtech,sx1301";
+        spi-max-frequency = <1000000>;
+    };	
+};
+
+&iomuxc {
+    pinctrl_spi_uart8: spi_uart8_grp {
+        fsl,pins = <
+            MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK    0x10b0
+            MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI    0x10b0
+            MX6UL_PAD_LCD_DATA23__ECSPI1_MISO    0x10b0
+            MX6UL_PAD_LCD_DATA21__GPIO3_IO26    0x10b0
+        >;
+    };	
+};
diff --git a/arch/arm/boot/dts/igkboard-imx6ull/uart2.dts b/arch/arm/boot/dts/igkboard-imx6ull/uart2.dts
new file mode 100644
index 000000000..2b48a9cd7
--- /dev/null
+++ b/arch/arm/boot/dts/igkboard-imx6ull/uart2.dts
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2022 LingYun IoT System Studio
+ * Author:  Guo Wenxue<guowenxue@gmail.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "../imx6ul-pinfunc.h"
+
+/* 40-pin extended GPIO, UART2 interfaces */
+
+&uart2 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_uart2>;
+    status = "okay";
+};
+
+&iomuxc {
+    pinctrl_uart2: uart2grp {
+        fsl,pins = <
+            MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX    0x1b0b1
+            MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX    0x1b0b1
+        >;
+    };
+};
diff --git a/arch/arm/boot/dts/igkboard-imx6ull/uart3.dts b/arch/arm/boot/dts/igkboard-imx6ull/uart3.dts
new file mode 100644
index 000000000..7d9e8cdd1
--- /dev/null
+++ b/arch/arm/boot/dts/igkboard-imx6ull/uart3.dts
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2022 LingYun IoT System Studio
+ * Author:  Guo Wenxue<guowenxue@gmail.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "../imx6ul-pinfunc.h"
+
+/* 40-pin extended GPIO, UART3 interfaces */
+
+&uart3 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_uart3>;
+    status = "okay";
+};
+
+&iomuxc {
+    pinctrl_uart3: uart3grp {
+        fsl,pins = <
+            MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX    0x1b0b1
+            MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX    0x1b0b1
+        >;
+    };
+};
+
diff --git a/arch/arm/boot/dts/igkboard-imx6ull/uart4.dts b/arch/arm/boot/dts/igkboard-imx6ull/uart4.dts
new file mode 100644
index 000000000..aa81b91eb
--- /dev/null
+++ b/arch/arm/boot/dts/igkboard-imx6ull/uart4.dts
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2022 LingYun IoT System Studio
+ * Author:  Guo Wenxue<guowenxue@gmail.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "../imx6ul-pinfunc.h"
+
+/* 40-pin extended GPIO, UART4 interfaces */
+
+&uart4 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_uart4>;
+    status = "okay";
+};
+
+&iomuxc {
+    pinctrl_uart4: uart4grp {
+        fsl,pins = <
+            MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX    0x1b0b1
+            MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX    0x1b0b1
+        >;
+    };
+};
+
diff --git a/arch/arm/boot/dts/igkboard-imx6ull/uart7.dts b/arch/arm/boot/dts/igkboard-imx6ull/uart7.dts
new file mode 100644
index 000000000..0229b345e
--- /dev/null
+++ b/arch/arm/boot/dts/igkboard-imx6ull/uart7.dts
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2022 LingYun IoT System Studio
+ * Author:  Guo Wenxue<guowenxue@gmail.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "../imx6ul-pinfunc.h"
+
+/* 40-pin extended GPIO, UART7 interfaces, conflict with LCD display */
+
+&uart7 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_uart7>;
+    status = "okay";
+};
+
+&iomuxc {
+    pinctrl_uart7: uart7grp {
+        fsl,pins = <
+            MX6UL_PAD_LCD_DATA16__UART7_DCE_TX        0x1b0b1
+            MX6UL_PAD_LCD_DATA17__UART7_DCE_RX        0x1b0b1
+        >;
+    };
+};
+
diff --git a/arch/arm/boot/dts/igkboard-imx6ull/w1.dts b/arch/arm/boot/dts/igkboard-imx6ull/w1.dts
new file mode 100644
index 000000000..bc3945ecb
--- /dev/null
+++ b/arch/arm/boot/dts/igkboard-imx6ull/w1.dts
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2022 LingYun IoT System Studio
+ * Author:  Guo Wenxue<guowenxue@gmail.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "../imx6ul-pinfunc.h"
+
+/* W1(DS18B20) on 40Pin Header Pin#7 (GPIO1_IO18) */
+
+&w1 {
+    compatible = "w1-gpio";
+    status = "okay";
+
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_w1>;
+    gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
+};
+
+
+&iomuxc {
+    pinctrl_w1: w1grp {
+        fsl,pins = <
+            MX6UL_PAD_UART1_CTS_B__GPIO1_IO18    0x110b0
+        >;
+    };
+};
+
diff --git a/arch/arm/configs/igkboard-imx6ull_defconfig b/arch/arm/configs/igkboard-imx6ull_defconfig
new file mode 100644
index 000000000..84a721bc4
--- /dev/null
+++ b/arch/arm/configs/igkboard-imx6ull_defconfig
@@ -0,0 +1,604 @@
+CONFIG_KERNEL_LZO=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=18
+CONFIG_CGROUPS=y
+CONFIG_MEMCG=y
+CONFIG_CGROUP_PIDS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_NAMESPACES=y
+CONFIG_USER_NS=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EXPERT=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_PERF_EVENTS=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_ARCH_MXC=y
+CONFIG_SOC_IMX6Q=y
+CONFIG_SOC_IMX6SL=y
+CONFIG_SOC_IMX6SLL=y
+CONFIG_SOC_IMX6SX=y
+CONFIG_SOC_IMX6UL=y
+CONFIG_SOC_IMX7D=y
+CONFIG_SOC_IMX7ULP=y
+CONFIG_SMP=y
+CONFIG_VMSPLIT_2G=y
+CONFIG_ARM_PSCI=y
+CONFIG_HIGHMEM=y
+CONFIG_FORCE_MAX_ZONEORDER=14
+CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
+CONFIG_KEXEC=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_ARM_IMX6Q_CPUFREQ=y
+CONFIG_ARM_IMX_CPUFREQ_DT=y
+CONFIG_CPU_IDLE=y
+CONFIG_ARM_CPUIDLE=y
+CONFIG_ARM_PSCI_CPUIDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_PM_DEBUG=y
+CONFIG_PM_TEST_SUSPEND=y
+CONFIG_KPROBES=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_BINFMT_MISC=m
+CONFIG_CMA=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_NETFILTER=y
+CONFIG_VLAN_8021Q=m
+CONFIG_LLC2=y
+CONFIG_CAN=y
+CONFIG_CAN_FLEXCAN=y
+CONFIG_BT=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+CONFIG_BT_HCIBTUSB=y
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_BCSP=y
+CONFIG_BT_HCIUART_LL=y
+CONFIG_BT_HCIUART_3WIRE=y
+CONFIG_BT_HCIUART_MRVL=y
+CONFIG_BT_HCIVHCI=y
+CONFIG_BT_MRVL=y
+CONFIG_BT_MRVL_SDIO=y
+CONFIG_CFG80211=y
+CONFIG_NL80211_TESTMODE=y
+CONFIG_CFG80211_WEXT=y
+CONFIG_MAC80211=y
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_IMX6_HOST=y
+CONFIG_PCI_IMX6_EP=y
+CONFIG_PCI_ENDPOINT=y
+CONFIG_PCI_ENDPOINT_CONFIGFS=y
+CONFIG_PCI_EPF_TEST=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+CONFIG_FW_LOADER_USER_HELPER=y
+CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y
+CONFIG_IMX_WEIM=y
+CONFIG_CONNECTOR=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_DATAFLASH=y
+CONFIG_MTD_SST25L=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_NAND_GPMI_NAND=y
+CONFIG_MTD_NAND_MXC=y
+CONFIG_MTD_SPI_NOR=y
+# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_OF_OVERLAY=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=65536
+CONFIG_PCI_ENDPOINT_TEST=y
+CONFIG_EEPROM_AT24=y
+CONFIG_EEPROM_AT25=y
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_AHCI_IMX=y
+CONFIG_PATA_IMX=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_BLK_DEV_DM=m
+CONFIG_DM_CRYPT=m
+CONFIG_NETDEVICES=y
+CONFIG_TUN=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+CONFIG_CS89x0_PLATFORM=y
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+CONFIG_SMC91X=y
+CONFIG_SMC911X=y
+CONFIG_SMSC911X=y
+# CONFIG_NET_VENDOR_STMICRO is not set
+CONFIG_MICREL_PHY=y
+CONFIG_AT803X_PHY=y
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_RTL8152=y
+CONFIG_USB_LAN78XX=y
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_CDC_EEM=m
+CONFIG_USB_NET_SMSC95XX=y
+CONFIG_USB_NET_MCS7830=y
+CONFIG_ATH10K=m
+CONFIG_ATH10K_SDIO=m
+CONFIG_HOSTAP=y
+CONFIG_WL12XX=m
+CONFIG_WL18XX=m
+CONFIG_WLCORE_SDIO=m
+# CONFIG_WILINK_PLATFORM_DATA is not set
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_EVBUG=m
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_RPMSG=y
+CONFIG_KEYBOARD_IMX=y
+CONFIG_MOUSE_PS2=m
+CONFIG_MOUSE_PS2_ELANTECH=y
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ADS7846=y
+CONFIG_TOUCHSCREEN_AD7879=y
+CONFIG_TOUCHSCREEN_AD7879_I2C=y
+CONFIG_TOUCHSCREEN_ATMEL_MXT=y
+CONFIG_TOUCHSCREEN_DA9052=y
+CONFIG_TOUCHSCREEN_EGALAX=y
+CONFIG_TOUCHSCREEN_ELAN_TS=y
+CONFIG_TOUCHSCREEN_GOODIX=y
+CONFIG_TOUCHSCREEN_ILI210X=y
+CONFIG_TOUCHSCREEN_MAX11801=y
+CONFIG_TOUCHSCREEN_IMX6UL_TSC=y
+CONFIG_TOUCHSCREEN_EDT_FT5X06=y
+CONFIG_TOUCHSCREEN_MC13783=y
+CONFIG_TOUCHSCREEN_TSC2004=y
+CONFIG_TOUCHSCREEN_TSC2007=y
+CONFIG_TOUCHSCREEN_STMPE=y
+CONFIG_TOUCHSCREEN_SX8654=y
+CONFIG_TOUCHSCREEN_COLIBRI_VF50=y
+CONFIG_TOUCHSCREEN_FTS=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_MMA8450=y
+CONFIG_SERIO_SERPORT=m
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_SERIAL_FSL_LPUART=y
+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
+CONFIG_SERIAL_DEV_BUS=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_GPIO=y
+# CONFIG_I2C_HELPER_AUTO is not set
+CONFIG_I2C_ALGOPCF=m
+CONFIG_I2C_ALGOPCA=m
+CONFIG_I2C_GPIO=y
+CONFIG_I2C_IMX=y
+CONFIG_I2C_IMX_LPI2C=y
+CONFIG_SPI=y
+CONFIG_SPI_FSL_LPSPI=y
+CONFIG_SPI_FSL_QUADSPI=y
+CONFIG_SPI_GPIO=y
+CONFIG_SPI_IMX=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_SPI_SLAVE=y
+CONFIG_SPI_SLAVE_TIME=y
+CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_MXC=y
+CONFIG_GPIO_SIOX=m
+CONFIG_GPIO_IMX_RPMSG=y
+CONFIG_GPIO_MAX732X=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_PCF857X=y
+CONFIG_GPIO_STMPE=y
+CONFIG_GPIO_74X164=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_RESET_SYSCON_POWEROFF=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_SABRESD_MAX8903=y
+CONFIG_RN5T618_POWER=m
+CONFIG_SENSORS_MC13783_ADC=y
+CONFIG_SENSORS_GPIO_FAN=y
+CONFIG_SENSORS_IIO_HWMON=y
+CONFIG_SENSORS_MAX17135=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_STATISTICS=y
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+CONFIG_CPU_THERMAL=y
+CONFIG_IMX_THERMAL=y
+CONFIG_DEVICE_THERMAL=y
+CONFIG_WATCHDOG=y
+CONFIG_DA9063_WATCHDOG=m
+CONFIG_DA9062_WATCHDOG=y
+CONFIG_RN5T618_WATCHDOG=y
+CONFIG_IMX2_WDT=y
+CONFIG_IMX7ULP_WDT=y
+CONFIG_MFD_DA9052_I2C=y
+CONFIG_MFD_DA9062=y
+CONFIG_MFD_DA9063=y
+CONFIG_MFD_MC13XXX_SPI=y
+CONFIG_MFD_MC13XXX_I2C=y
+CONFIG_MFD_MAX17135=y
+CONFIG_MFD_RN5T618=y
+CONFIG_MFD_SI476X_CORE=y
+CONFIG_MFD_STMPE=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_ANATOP=y
+CONFIG_REGULATOR_DA9052=y
+CONFIG_REGULATOR_DA9062=y
+CONFIG_REGULATOR_DA9063=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_LTC3676=y
+CONFIG_REGULATOR_MAX17135=y
+CONFIG_REGULATOR_MC13783=y
+CONFIG_REGULATOR_MC13892=y
+CONFIG_REGULATOR_PF1550_RPMSG=y
+CONFIG_REGULATOR_PFUZE100=y
+CONFIG_REGULATOR_RN5T618=y
+CONFIG_RC_CORE=y
+CONFIG_RC_DEVICES=y
+CONFIG_IR_GPIO_CIR=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_RADIO_SI476X=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_VIDEO_MUX=y
+CONFIG_VIDEO_MXC_CAPTURE=m
+CONFIG_VIDEO_MXC_OUTPUT=y
+CONFIG_VIDEO_MXC_CSI_CAMERA=m
+CONFIG_MXC_VADC=m
+CONFIG_MXC_MIPI_CSI=m
+CONFIG_MXC_CAMERA_OV5640=m
+CONFIG_MXC_CAMERA_OV5640_V2=m
+CONFIG_MXC_CAMERA_OV5640_MIPI=m
+CONFIG_MXC_CAMERA_OV5640_MIPI_V2=m
+CONFIG_MXC_TVIN_ADV7180=m
+CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m
+CONFIG_VIDEO_MXC_IPU_OUTPUT=y
+CONFIG_VIDEO_MXC_PXP_V4L2=y
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_VIDEO_CODA=m
+CONFIG_VIDEO_IMX_PXP=y
+CONFIG_VIDEO_ADV7180=m
+CONFIG_VIDEO_OV2680=m
+CONFIG_VIDEO_OV5645=m
+CONFIG_DRM=y
+CONFIG_DRM_PANEL_LVDS=y
+CONFIG_DRM_PANEL_SIMPLE=y
+CONFIG_DRM_PANEL_SEIKO_43WVF1G=y
+CONFIG_DRM_TI_TFP410=y
+CONFIG_FB=y
+CONFIG_FB_MXS=y
+CONFIG_FB_MXC_SYNC_PANEL=y
+CONFIG_FB_MXC_OVERLAY=y
+CONFIG_FB_MXC_MIPI_DSI_NORTHWEST=y
+CONFIG_FB_MXC_ADV7535=y
+CONFIG_FB_MXC_TRULY_PANEL_TFT3P5581E=y
+CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y
+CONFIG_FB_MXC_RK_PANEL_RK055AHD042=y
+CONFIG_FB_MXC_RK_PANEL_RK055IQH042=y
+CONFIG_FB_MXC_MIPI_DSI_SAMSUNG=y
+CONFIG_FB_MXC_MIPI_DSI=y
+CONFIG_FB_MXC_LDB=y
+CONFIG_FB_MXC_EINK_PANEL=y
+CONFIG_FB_MXC_EINK_V2_PANEL=y
+CONFIG_FB_MXC_HDMI=y
+CONFIG_FB_MXS_SII902X=y
+CONFIG_FB_MXC_DCIC=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_LCD_L4F00242T03=y
+CONFIG_LCD_PLATFORM=y
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_LOGO=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_USB_AUDIO=m
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_FSL_ASRC=y
+CONFIG_SND_SOC_FSL_MQS=y
+CONFIG_SND_SOC_FSL_RPMSG=y
+CONFIG_SND_IMX_SOC=y
+CONFIG_SND_SOC_EUKREA_TLV320=y
+CONFIG_SND_SOC_IMX_ES8328=y
+CONFIG_SND_SOC_IMX_SGTL5000=y
+CONFIG_SND_SOC_IMX_SPDIF=y
+CONFIG_SND_SOC_FSL_ASOC_CARD=y
+CONFIG_SND_SOC_IMX_HDMI=y
+CONFIG_SND_SOC_IMX6QDL_HDMI=y
+CONFIG_SND_SOC_AC97_CODEC=y
+CONFIG_SND_SOC_CS42XX8_I2C=y
+CONFIG_SND_SOC_WM8960=y
+CONFIG_SND_SOC_WM8962=y
+CONFIG_SND_SOC_RPMSG_WM8960=y
+CONFIG_SND_SIMPLE_CARD=y
+CONFIG_HID_MULTITOUCH=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_HCD_TEST_MODE=y
+CONFIG_USB_ACM=m
+CONFIG_USB_STORAGE=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_SERIAL=m
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_USB_TEST=m
+CONFIG_USB_EHSET_TEST_FIXTURE=m
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_USB_MXS_PHY=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_CONFIGFS=y
+CONFIG_USB_CONFIGFS_SERIAL=y
+CONFIG_USB_CONFIGFS_ACM=y
+CONFIG_USB_CONFIGFS_OBEX=y
+CONFIG_USB_CONFIGFS_NCM=y
+CONFIG_USB_CONFIGFS_ECM=y
+CONFIG_USB_CONFIGFS_ECM_SUBSET=y
+CONFIG_USB_CONFIGFS_RNDIS=y
+CONFIG_USB_CONFIGFS_EEM=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_CONFIGFS_F_LB_SS=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_F_UAC1=y
+CONFIG_USB_CONFIGFS_F_UAC2=y
+CONFIG_USB_CONFIGFS_F_MIDI=y
+CONFIG_USB_CONFIGFS_F_HID=y
+CONFIG_USB_CONFIGFS_F_UVC=y
+CONFIG_USB_CONFIGFS_F_PRINTER=y
+CONFIG_USB_ZERO=m
+CONFIG_USB_AUDIO=m
+CONFIG_USB_ETH=m
+CONFIG_USB_G_NCM=m
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FUNCTIONFS=m
+CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_G_SERIAL=m
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_ESDHC_IMX=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+CONFIG_RTC_DRV_DS1307=y
+CONFIG_RTC_DRV_ISL1208=y
+CONFIG_RTC_DRV_PCF8523=y
+CONFIG_RTC_DRV_PCF8563=y
+CONFIG_RTC_DRV_M41T80=y
+CONFIG_RTC_DRV_RC5T619=y
+CONFIG_RTC_DRV_DA9063=y
+CONFIG_RTC_DRV_MC13XXX=y
+CONFIG_RTC_DRV_MXC=y
+CONFIG_RTC_DRV_MXC_V2=y
+CONFIG_RTC_DRV_SNVS=y
+CONFIG_RTC_DRV_IMX_RPMSG=y
+CONFIG_DMADEVICES=y
+CONFIG_FSL_EDMA=y
+CONFIG_IMX_SDMA=y
+CONFIG_MXS_DMA=y
+CONFIG_MXC_PXP_V2=y
+CONFIG_MXC_PXP_V3=y
+CONFIG_DMATEST=m
+CONFIG_STAGING=y
+CONFIG_STAGING_MEDIA=y
+CONFIG_COMMON_CLK_PWM=y
+CONFIG_REMOTEPROC=y
+CONFIG_IMX_REMOTEPROC=y
+CONFIG_EXTCON_USB_GPIO=y
+CONFIG_IIO=y
+CONFIG_MMA8452=y
+CONFIG_IMX7D_ADC=y
+CONFIG_RN5T618_ADC=y
+CONFIG_VF610_ADC=y
+CONFIG_FXAS21002C=y
+CONFIG_FXOS8700_I2C=y
+CONFIG_RPMSG_IIO_PEDOMETER=m
+CONFIG_SENSORS_ISL29018=y
+CONFIG_MAG3110=y
+CONFIG_MPL3115=y
+CONFIG_PWM=y
+CONFIG_PWM_FSL_FTM=y
+CONFIG_PWM_IMX27=y
+CONFIG_PWM_IMX_TPM=y
+CONFIG_PHY_MIXEL_LVDS=y
+CONFIG_PHY_MIXEL_LVDS_COMBO=y
+CONFIG_NVMEM_IMX_OCOTP=y
+CONFIG_NVMEM_SNVS_LPGPR=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_MUX_MMIO=y
+CONFIG_SIOX=m
+CONFIG_SIOX_BUS_GPIO=m
+CONFIG_MXC_SIM=y
+CONFIG_MXC_IPU=y
+CONFIG_MXC_SIMv2=y
+CONFIG_MXC_MLB150=y
+CONFIG_MXC_IPU_V3_PRE=y
+CONFIG_MXC_HDMI_CEC=y
+CONFIG_MXC_MIPI_CSI2=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_OVERLAY_FS=y
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_DEFAULT="cp437"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_UTF8=y
+CONFIG_SECURITYFS=y
+CONFIG_CRYPTO_USER=y
+CONFIG_CRYPTO_TEST=m
+CONFIG_CRYPTO_ECHAINIV=m
+CONFIG_CRYPTO_TLS=m
+CONFIG_CRYPTO_CFB=m
+CONFIG_CRYPTO_CTS=m
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_OFB=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_VMAC=m
+CONFIG_CRYPTO_XXHASH=m
+CONFIG_CRYPTO_BLAKE2B=m
+CONFIG_CRYPTO_BLAKE2S=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_SHA3=m
+CONFIG_CRYPTO_SM3=m
+CONFIG_CRYPTO_STREEBOG=m
+CONFIG_CRYPTO_WP512=m
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=m
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=m
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_SM4=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_ANSI_CPRNG=m
+CONFIG_CRYPTO_USER_API_RNG=m
+CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=m
+CONFIG_CRYPTO_DEV_FSL_CAAM=m
+CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=m
+CONFIG_CRYPTO_DEV_SAHARA=y
+CONFIG_CRYPTO_DEV_MXS_DCP=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC7=m
+CONFIG_LIBCRC32C=m
+CONFIG_DMA_CMA=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_PRINTK_TIME=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_FTRACE is not set
+
+# enable AF_ALG
+CONFIG_CRYPTO_USER_API_HASH=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
+CONFIG_CRYPTO_USER_API_AEAD=m
+
+# enable KTLS
+CONFIG_TLS=y
+CONFIG_TLS_DEVICE=y
+
+#enable trust based hardware key
+CONFIG_TRUSTED_KEYS=m
+CONFIG_TRUSTED_KEYS_TPM=n
+CONFIG_TRUSTED_KEYS_TEE=n
+CONFIG_TRUSTED_KEYS_CAAM=n
+CONFIG_TRUSTED_KEYS_DCP=y
+
+# Custom Addition of Linke
+# enable one wire device driver
+CONFIG_W1=y
+CONFIG_W1_MASTER_GPIO=y
+CONFIG_W1_SLAVE_THERM=y
+
+# enable drm to realize fb
+CONFIG_DRM_MXSFB=y
diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
index 582db321e..7444c06e4 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_drv.c
+++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
@@ -370,7 +370,7 @@ static int mxsfb_probe(struct platform_device *pdev)
     if (ret)
         goto err_unload;
 
-    drm_fbdev_generic_setup(drm, 32);
+    drm_fbdev_generic_setup(drm, 16); /* modify color depth to support RGB565 LCD by guowenxue */
 
     return 0;
 
@@ -426,7 +426,7 @@ static struct platform_driver mxsfb_platform_driver = {
     .remove        = mxsfb_remove,
     .shutdown    = mxsfb_shutdown,
     .driver    = {
-        .name        = "mxsfb",
+        .name        = "mxsfb-drm",
         .of_match_table    = mxsfb_dt_ids,
         .pm        = &mxsfb_pm_ops,
     },
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index 009e3e96c..3b158fd50 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -4024,8 +4024,33 @@ static const struct panel_desc arm_rtsm = {
     .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
 };
 
+static const struct drm_display_mode igkboard_6ull_panel_mode[] = {
+    {    
+        .clock = 30000,
+        .hdisplay = 800, 
+        .hsync_start = 800 + 40,
+        .hsync_end = 800 + 40 + 48,
+        .htotal = 800 + 40 + 48 + 88,
+        .vdisplay = 480, 
+        .vsync_start = 480 + 13,
+        .vsync_end = 480 + 13 + 3, 
+        .vtotal = 480 + 13 + 3 + 32,
+        .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
+    },   
+};
+
+static const struct panel_desc igkboard_6ull_panel = {
+    .modes = igkboard_6ull_panel_mode,
+    .num_modes = 1, 
+    .bpc = 8, 
+    .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
+};
+
 static const struct of_device_id platform_of_match[] = {
     {
+        .compatible = "lingyun,igkboard-imx6ull-panel",
+        .data = &igkboard_6ull_panel,
+    }, {
         .compatible = "ampire,am-1280800n3tzqw-t00h",
         .data = &ampire_am_1280800n3tzqw_t00h,
     }, {
diff --git a/drivers/video/backlight/pwm_bl.c b/drivers/video/backlight/pwm_bl.c
index b28ac814a..12143bbea 100644
--- a/drivers/video/backlight/pwm_bl.c
+++ b/drivers/video/backlight/pwm_bl.c
@@ -53,7 +53,7 @@ static void pwm_backlight_power_on(struct pwm_bl_data *pb)
     if (err < 0)
         dev_err(pb->dev, "failed to enable power supply\n");
 
-    state.enabled = true;
+    state.enabled = true; /* enalbe backlight as default */
     pwm_apply_state(pb->pwm, &state);
 
     if (pb->post_pwm_on_delay)
diff --git a/drivers/video/fbdev/core/fbcon.c b/drivers/video/fbdev/core/fbcon.c
index fa205be94..8bb25f64f 100644
--- a/drivers/video/fbdev/core/fbcon.c
+++ b/drivers/video/fbdev/core/fbcon.c
@@ -345,6 +345,7 @@ static int get_color(struct vc_data *vc, struct fb_info *info,
     return color;
 }
 
+#if 0 /* comment by guowenxue */
 static void fb_flashcursor(struct work_struct *work)
 {
     struct fbcon_ops *ops = container_of(work, struct fbcon_ops, cursor_work.work);
@@ -384,6 +385,9 @@ static void fb_flashcursor(struct work_struct *work)
     queue_delayed_work(system_power_efficient_wq, &ops->cursor_work,
                ops->cur_blink_jiffies);
 }
+#else
+static void fb_flashcursor(struct work_struct *work) {}
+#endif
 
 static void fbcon_add_cursor_work(struct fb_info *info)
 {
@@ -1301,6 +1305,7 @@ static void fbcon_clear_margins(struct vc_data *vc, int bottom_only)
         ops->clear_margins(vc, info, margin_color, bottom_only);
 }
 
+#if 0 /* comment by guowenxue */
 static void fbcon_cursor(struct vc_data *vc, int mode)
 {
     struct fb_info *info = fbcon_info_from_console(vc->vc_num);
@@ -1325,6 +1330,9 @@ static void fbcon_cursor(struct vc_data *vc, int mode)
     ops->cursor(vc, info, mode, get_color(vc, info, c, 1),
             get_color(vc, info, c, 0));
 }
+#else
+static void fbcon_cursor(struct vc_data *vc, int mode) {}
+#endif
 
 static int scrollback_phys_max = 0;
 static int scrollback_max = 0;
diff --git a/drivers/video/fbdev/mxsfb.c b/drivers/video/fbdev/mxsfb.c
index 862278022..ce647f570 100644
--- a/drivers/video/fbdev/mxsfb.c
+++ b/drivers/video/fbdev/mxsfb.c
@@ -1586,7 +1586,7 @@ MODULE_DEVICE_TABLE(platform, mxsfb_devtype);
 
 static const struct of_device_id mxsfb_dt_ids[] = {
     { .compatible = "fsl,imx23-lcdif", .data = &mxsfb_devtype[0], },
-    { .compatible = "fsl,imx28-lcdif", .data = &mxsfb_devtype[1], },
+    //{ .compatible = "fsl,imx28-lcdif", .data = &mxsfb_devtype[1], }, /* Use DRM driver as default */
     { .compatible = "fsl,imx7ulp-lcdif", .data = &mxsfb_devtype[2], },
     { /* sentinel */ }
 };