Add RK3568 mainboard schematic and eDP board documents

android

2024-06-25 14713472ff35323e73d5b09214e8f4b745afd094

Add RK3568 mainboard schematic and eDP board documents

Signed-off-by: android <android@lingyun.com>

 documents/edp/documents/LCD-TP/B8 Product Spec-NV156FHM-N22_P0_20230301-汇总更新(1).pdf

Binary files differ

 documents/edp/documents/LCD-TP/ICI2511.C3.P1.V1规格书.pdf

Binary files differ

 documents/edp/documents/LCD-TP/NV156FHM-N22(15.6寸屏) eDP线-30p-正边.pdf

Binary files differ

 documents/edp/documents/LCD-TP/TP-ILI2511.png

 documents/edp/documents/LCD-TP/TP板照片-I2C反向.jpg

 documents/edp/documents/LT8911EXB/LT8911EXB_Datasheet_R1.5.pdf

Binary files differ

 documents/edp/documents/LT8911EXB/LT8911EXB_MIPI2eDP_V2_XH_ST_N76_20220620.7z

Binary files differ

 documents/edp/documents/LT8911EXB/LT8911EXB_MIPI_to_eDP_Reg_Setting_20231124.c

New file
@@ -0,0 +1,1548 @@
/************************************************************

 * Copyright (C), 2009-2018, Lontium Tech. Co., Ltd.

 * FileName:

 * Author:

 * Date:

 * Description:

 * Version:

 * Function List:

 *

 * History:

 *     <author>  <time>   <version >   <desc>

 *

 ***********************************************************/





/*******************************************************



   1¡¢LT8911EXBµÄIICµØÖ·£º

   1. IIC address of lt8911exb:



   a)Èç¹ûLT8911EXBµÄµÚ31½Å£¨S_ADR£©ÎªµÍ£¬ÔòLT8911EXBµÄI2C µØַΪ0x52; // bit0 ÊǶÁд±ê־λ£»Èç¹ûÊÇLinuxϵͳ£¬IIC address µÄ bit7×÷Ϊ¶Áд±ê־룬ÔòI2CµØÖ· Ó¦¸ÃÊÇ 0x29

   A) if the 31st pin (s_adr) of lt8911exb is low, the I2C address of lt8911exb is 0x52; // bit0 is the read-write flag ; if it is Linux system, the bit7 of IIC address is the read-write flag, then the I2C address should be 0x29



   b)Èç¹ûLT8911EXBµÄµÚ31½Å£¨S_ADR£©Îª¸ß£¬ÔòLT8911EXBµÄI2C µØַΪ0x5a; // bit0 ÊǶÁд±ê־λ£»Èç¹ûÊÇLinuxϵͳ£¬IIC address µÄ bit7×÷Ϊ¶Áд±ê־룬ÔòI2CµØÖ· Ó¦¸ÃÊÇ 0x2d

   b) if the 31st pin (s_adr) of lt8911exb is high, the I2C address of lt8911exb is 0x5a; // bit0 is the read-write flag ; if it is a Linux system, the bit7 of IIC address is the read-write flag, then the I2C address should be 0x2d



   2¡¢IICËÙÂʲ»Òª³¬¹ý100KHz¡£

   2. IIC speed shall not exceed 100kHz.



   3¡¢ÒªÈ·¶¨MIPIÐźŸøµ½LT8911EXBÖ®ºó£¬ÔÙ³õʼ»¯LT8911EXB¡£

   3. Confirm that Mipi signal is sent to lt8911exb, and then initialize lt8911exb.



   4¡¢±ØÐëÓÉÇ°¶ËÖ÷¿ØGPIOÀ´¸´Î»LT8911EXB£»Ë¢¼Ä´æÆ÷֮ǰ£¬ÏÈReset LT8911EXB ,ÓÃGPIO ÏÈÀ­µÍLT8911EXBµÄ¸´Î»½Å 100ms×óÓÒ£¬ÔÙÀ­¸ß£¬±£³Ö100ms¡£

   4. The lt8911exb must be reset by the Master GPIO; before write the register, reset the lt8911exb first, pull down the reset pin by GPIO for about 100ms, and then pull up for 100ms.



   5¡¢LT8911EXB ¶ÔMIPIÊäÈëÐźŵÄÒªÇó£º

   5. LT8911EXB MIPI input signal requirements:

   a) MIPI DSI

   b) Video mode



   MIPI ÊäÈëÐèÒª¹Ø±ÕչƵ(SSC - Spread-Spectrum Clock)£¬´ò¿ªEOTP(End Of Transmite Packet)

   Mipi signal needs to turn off SSC(Spread-Spectrum Clock) and turn on eotp(End Of Transmite Packet)

 *********************************************************/



//#define _Test_Pattern_ // Output test pattern



//#define  _read_edid_ // read eDP panel EDID



//#define _Msa_Active_Only_



#define _eDP_2G7_

//#define _eDP_1G62_



#define _link_train_enable_



extern void LT8911EXB_IIC_Write_byte( u8 RegAddr, u8 data );    // IIC write operation, IIC rate do not exceed 100KHz





extern u8 LT8911EXB_IIC_Read_byte( u8 RegAddr );                
// IIC read operation, IIC rate do not exceed 100KHz





//********************************************************//



enum {

    hfp = 0,

    hs,

    hbp,

    hact,

    htotal,

    vfp,

    vs,

    vbp,

    vact,

    vtotal,

    pclk_10khz

};



u8        Read_DPCD010A = 0x00;



bool    ScrambleMode = 0;



bool    flag_mipi_on = 0;



#ifdef _read_edid_ // read eDP panel EDID



u8        EDID_DATA[128] = { 0 };

u16        EDID_Timing[11] = { 0 };



bool    EDID_Reply = 0;

#endif



//////////////////////LT8911EXB Config////////////////////////////////

//#define _1920x1200_eDP_Panel_

#define _1080P_eDP_Panel_

//#define _1366x768_eDP_Panel_

//#define _1280x800_eDP_Panel_

//#define _1280x720_eDP_Panel_



//#define _1600x900_eDP_Panel_

//#define _1920x1200_eDP_Panel_



//===========================================//



#define _MIPI_Lane_ 4   // 3 /2 / 1



#define _MIPI_data_PN_Swap_En    0xF0

#define _MIPI_data_PN_Swap_Dis    0x00



#define _MIPI_data_PN_ _MIPI_data_PN_Swap_Dis



//------------------------------------------//



#define _No_swap_            0x00    // 3210 default

#define _MIPI_data_3210_    0       // default

#define _MIPI_data_0123_    21

#define _MIPI_data_2103_    20



#define _MIPI_data_sequence_ _No_swap_





/*

   LT8911EXB pin        MIPI RX

   D3£¨37¡¢38£©        D3    2    3    2    1    1    3    2    3    2    0    0    3    0    3    0    1    1    2    0    2    0    1    1

   D2£¨40¡¢41£©        D2    3    1    1    2    3    2    3    0    0    2    3    0    3    1    1    0    3    0    2    1    1    0    2

   D1£¨44¡¢45£©        D1    1    2    3    3    2    0    1    2    3    3    2    1    1    0    3    3    0    1    1    0    2    2    0

   D0£¨47¡¢48£©        D0    0    0    0    0    0    1    0    1    1    1    1    2    2    2    2    2    2    3    3    3    3    3    3



   0xD003 Reg value    0    1    2    3    4    5    6    7    8    9    10    11    12    13    14    15    16    17    18    19    20    21    22    23

   //*/

//===========================================//



#define _eDP_data_PN_Swap_En    0xF0 // Please refer to the notes below

#define _eDP_data_PN_Swap_Dis    0x00



#define _eDP_data_PN_ _eDP_data_PN_Swap_Dis // defailt ; disable



/* eDP data P/N polarity swap 
bit7    RGD_MLCTRL_LANE3_RVSD_EN

        1 = data of lane3 polarity swap;

        0 = normal.



bit6    RGD_MLCTRL_LANE2_RVSD_EN

        1 = data of lane2 polarity swap;

        0 = normal.



bit5    RGD_MLCTRL_LANE1_RVSD_EN

        1 = data of lane1 polarity swap;

        0 = normal.



bit4    RGD_MLCTRL_LANE0_RVSD_EN

        1 = data of lane0 polarity swap;

        0 = normal.

//*/



//------------------------------------------//



#define _Lane0_data_    0

#define _Lane1_data_    1

#define _Lane2_data_    2

#define _Lane3_data_    3



#define _eDP_data3_select_    (_Lane3_data_ << 6) // default; _Lane3_data_select_ is lane3

#define _eDP_data2_select_    (_Lane2_data_ << 4) // default; _Lane2_data_select_ is lane2



#define _eDP_data1_select_    (_Lane1_data_ << 2)    // default; _Lane1_data_select_ is lane1

#define _eDP_data0_select_    (_Lane0_data_ << 0) // default; _Lane0_data_select_ is lane0



// example:lane1 and lane0 swap

//#define _eDP_data1_select_    (_Lane0_data_ << 2)    // default _Lane1_data_select_ is lane0

//#define _eDP_data0_select_    (_Lane1_data_ << 0) // default _Lane0_data_select_ is lane1



#define _eDP_data_No_swap_     0xe4 // default



#define _eDP_data_sequence_ _eDP_data_No_swap_ // default, no swap

// #define _eDP_data_sequence_ (_eDP_data3_select_ + _eDP_data2_select_ + _eDP_data1_select_ + _eDP_data0_select_) 




//===========================================//







//#define _eDP_scramble_ // eDP scramble mode



#define _Nvid 0         // 0: 0x0080,default

static int Nvid_Val[] = { 0x0080, 0x0800 };



#ifdef _1920x1200_eDP_Panel_



#define eDP_lane        2

#define PCR_PLL_PREDIV    0x40



#define _6bit_

//#define _8bit_



//const struct video_timing video[] =

static int MIPI_Timing[] =

// hfp, hs,    hbp,    hact,    htotal,    vfp,    vs,    vbp,    vact,    vtotal,    pixel_CLK/10000

//-----|---|------|-------|--------|-----|-----|-----|--------|--------|---------------

{ 48, 32, 80, 1920, 2080, 5, 5, 20, 1200, 1230, 15350 };                                //





/*******************************************************************

   È«Ö¾Æ½Ì¨µÄÆÁ²Î lcd_hbp ÊÇÆÁ²ÎÊý h_backporch + hs_width µÄºÍ£»

   The lcd_hbp of Allwinner platform is the sum of the above parameters hbp + hs;



   Í¬ÑùµÄ£¬È«Ö¾Æ½Ì¨µÄÆÁ²Î lcd_vbp ÊÇ ÆÁ²ÎÊý v_backporch + vs_width µÄºÍ£»ÕâµãҪעÒâ¡£

   In the same, lcd_vbp are the sum of the above parameters vbp + vs, which should be noted.

   //-------------------------------------------------------------------



   EOTP(End Of Transmite Packet£¬hs ´«ÍêÁË£¬»á·¢ÕâÑùÒ»¸ö°ü) Òª´ò¿ª£¬(֮ǰµÄLT8911B ÐèÒª¹Ø±ÕEOTP£¬ÕâÀïLT8911EXB ÐèÒª´ò¿ª)

   Eotp (end of transmit packet, HS will send such a packet) must be turn-on (lt8911b needs to turn-off eotp, here lt8911exb needs to turn-on)



   1¡¢MTKƽ̨ µÄ dis_eotp_en µÄÖµ£¬¸Ä³É false;   LKºÍkernel¶¼ÐèÒªÐÞ¸Ä,¸Ä³Éfalse¡£

   1. The value of dis_eotp_en of MTK platform should be changed to 'false'; LK and kernel need to be changed to 'false'.



   2¡¢Õ¹Ñ¶Æ½Ì¨µÄ tx_eotp µÄÖµÖà1 ¡£

   2. The value of tx_eotp of Spreadtrum platform is set to 1.



   3¡¢RKƽ̨ EN_EOTP_TX ÖÃ1.

   3. The value of EN_EOTP_TX of RK platform is set to 1.



   4¡¢¸ßͨƽ̨ ÕÒµ½ dsi_ctrl_hw_cmn.c -->void dsi_ctrl_hw_cmn_host_setup(struct dsi_ctrl_hw *ctrl,struct dsi_host_common_cfg *cfg)-->Ôö¼Ócfg->append_tx_eot = true;

   4¡¢Qualcomm: dsi_ctrl_hw_cmn.c -->void dsi_ctrl_hw_cmn_host_setup(struct dsi_ctrl_hw *ctrl,struct dsi_host_common_cfg *cfg)-->add cfg->append_tx_eot = true;

*******************************************************************/



#endif



#ifdef _1080P_eDP_Panel_



#define eDP_lane        2

#define PCR_PLL_PREDIV    0x40



// ¸ù¾ÝÇ°¶ËMIPIÐźŵÄTiming£¬ÐÞ¸ÄÒÔϲÎÊý£º

//According to the timing of the Mipi signal, modify the following parameters:

static int MIPI_Timing[] =

// hfp,    hs,    hbp,    hact,    htotal,    vfp,    vs,    vbp,    vact,    vtotal,    pixel_CLK/10000

//-----|---|------|-------|--------|-----|-----|-----|--------|--------|---------------

{ 88,     44, 148,     1920,     2200,     4,         5,     36,     1080,     1125,         14850 };   // VESA



//  { 48, 32, 80,   1920,   2080,   3,  5,  23,    1080,   1111,   13850 };    // SL156PP36





/*******************************************************************

   È«Ö¾Æ½Ì¨µÄÆÁ²Î lcd_hbp ÊÇ ÉÏÃæ²ÎÊý hbp + hs µÄºÍ£»

   The lcd_hbp of Allwiner platform is the sum of the above parameters hbp + hs;



   Í¬ÑùµÄ£¬È«Ö¾Æ½Ì¨µÄÆÁ²Î lcd_vbp ÊÇ ÉÏÃæ²ÎÊý vbp + vsµÄ ºÍ£¬ÕâµãҪעÒâ¡£

   In the same, lcd_vbp are the sum of the above parameters vbp + vs, which should be noted.

   //-------------------------------------------------------------------



   EOTP(End Of Transmite Packet£¬hs ´«ÍêÁË£¬»á·¢ÕâÑùÒ»¸ö°ü) Òª´ò¿ª£¬(֮ǰµÄLT8911B ÐèÒª¹Ø±ÕEOTP£¬ÕâÀïLT8911EXB ÐèÒª´ò¿ª)

   Eotp (end of transmit packet, HS will send such a packet) must be turn-on (lt8911b needs to turn-off eotp, here lt8911exb needs to turn-on)



   1¡¢MTKƽ̨ µÄ dis_eotp_en µÄÖµ£¬¸Ä³É false;   LKºÍkernel¶¼ÐèÒªÐÞ¸Ä,¸Ä³Éfalse¡£

   1. The value of dis_eotp_en of MTK platform should be changed to 'false'; LK and kernel need to be changed to 'false'.



   2¡¢Õ¹Ñ¶Æ½Ì¨µÄ tx_eotp µÄÖµÖà1 ¡£

   2. The value of tx_eotp of Spreadtrum platform is set to 1.



   3¡¢RKƽ̨ EN_EOTP_TX ÖÃ1.

   3. The value of EN_EOTP_TX of RK platform is set to 1.



   4¡¢¸ßͨƽ̨ ÕÒµ½ dsi_ctrl_hw_cmn.c -->void dsi_ctrl_hw_cmn_host_setup(struct dsi_ctrl_hw *ctrl,struct dsi_host_common_cfg *cfg)-->Ôö¼Ócfg->append_tx_eot = true;

   4¡¢Qualcomm: dsi_ctrl_hw_cmn.c -->void dsi_ctrl_hw_cmn_host_setup(struct dsi_ctrl_hw *ctrl,struct dsi_host_common_cfg *cfg)-->add cfg->append_tx_eot = true;



*******************************************************************/



//#define _6bit_ // eDP panel Color Depth£¬262K color

#define _8bit_                                              // eDP panel Color Depth£¬16.7M color



#endif



//-----------------------------------------



#ifdef _1366x768_eDP_Panel_



#define eDP_lane        1

#define PCR_PLL_PREDIV    0x40



// ¸ù¾ÝÇ°¶ËMIPIÐźŵÄTiming£¬ÐÞ¸ÄÒÔϲÎÊý£º

static int MIPI_Timing[] =

// hfp,    hs,    hbp,    hact,    htotal,    vfp,    vs,    vbp,    vact,    vtotal,    pixel_CLK/10000

//-----|---|------|-------|--------|-----|-----|-----|--------|--------|---------------

{ 14, 56, 64, 1366, 1500, 1, 3, 28, 768, 800, 7200 };





/*******************************************************************

   È«Ö¾Æ½Ì¨µÄÆÁ²Î lcd_hbp ÊÇ ÉÏÃæ²ÎÊý hbp + hs µÄºÍ£»

   The lcd_hbp of Allwiner platform is the sum of the above parameters hbp + hs;



   Í¬ÑùµÄ£¬È«Ö¾Æ½Ì¨µÄÆÁ²Î lcd_vbp ÊÇ ÉÏÃæ²ÎÊý vbp + vsµÄ ºÍ£¬ÕâµãҪעÒâ¡£

   In the same, lcd_vbp are the sum of the above parameters vbp + vs, which should be noted.

   //-------------------------------------------------------------------



   EOTP(End Of Transmite Packet£¬hs ´«ÍêÁË£¬»á·¢ÕâÑùÒ»¸ö°ü) Òª´ò¿ª£¬(֮ǰµÄLT8911B ÐèÒª¹Ø±ÕEOTP£¬ÕâÀïLT8911EXB ÐèÒª´ò¿ª)

   Eotp (end of transmit packet, HS will send such a packet) must be turn-on (lt8911b needs to turn-off eotp, here lt8911exb needs to turn-on)



   1¡¢MTKƽ̨ µÄ dis_eotp_en µÄÖµ£¬¸Ä³É false;     LKºÍkernel¶¼ÐèÒªÐÞ¸Ä,¸Ä³Éfalse¡£

   1. The value of dis_eotp_en of MTK platform should be changed to 'false'; LK and kernel need to be changed to 'false'.



   2¡¢Õ¹Ñ¶Æ½Ì¨µÄ tx_eotp µÄÖµÖà1 ¡£

   2. The value of tx_eotp of Spreadtrum platform is set to 1.



   3¡¢RKƽ̨ EN_EOTP_TX ÖÃ1.

   3. The value of EN_EOTP_TX of RK platform is set to 1.



   4¡¢¸ßͨƽ̨ ÕÒµ½ dsi_ctrl_hw_cmn.c -->void dsi_ctrl_hw_cmn_host_setup(struct dsi_ctrl_hw *ctrl,struct dsi_host_common_cfg *cfg)-->Ôö¼Ócfg->append_tx_eot = true;

   4¡¢Qualcomm: dsi_ctrl_hw_cmn.c -->void dsi_ctrl_hw_cmn_host_setup(struct dsi_ctrl_hw *ctrl,struct dsi_host_common_cfg *cfg)-->add cfg->append_tx_eot = true;



*******************************************************************/



#define _6bit_                                                              // eDP panel Color Depth£¬262K color



#endif



//*****************************************************//



void LT8911EX_ChipID( void )                                                // read Chip ID

{

//    Debug_Printf( "\r\n###################start#####################" );

    LT8911EXB_IIC_Write_byte( 0xff, 0x81 );                                 //register bank

    LT8911EXB_IIC_Write_byte( 0x08, 0x7f );



#ifdef _uart_debug_

    printf( "\r\nLT8911EXB chip ID:", LT8911EXB_IIC_Read_byte( 0x00 ) );    // 0x17

    printf( ", ", LT8911EXB_IIC_Read_byte( 0x01 ) );                        // 0x05

    printf( ", ", LT8911EXB_IIC_Read_byte( 0x02 ) );                        // 0xE0

#endif

}



/***********************************************************



***********************************************************/

void LT8911EXB_read_edid( void )

{

#ifdef _read_edid_

    u8 reg, i, j;

//    bool    aux_reply, aux_ack, aux_nack, aux_defer;

    LT8911EXB_IIC_Write_byte( 0xff, 0xac );

    LT8911EXB_IIC_Write_byte( 0x00, 0x20 ); //Soft Link train

    LT8911EXB_IIC_Write_byte( 0xff, 0xa6 );

    LT8911EXB_IIC_Write_byte( 0x2a, 0x01 );



    /*set edid offset addr*/

    LT8911EXB_IIC_Write_byte( 0x2b, 0x40 ); //CMD

    LT8911EXB_IIC_Write_byte( 0x2b, 0x00 ); //addr[15:8]

    LT8911EXB_IIC_Write_byte( 0x2b, 0x50 ); //addr[7:0]

    LT8911EXB_IIC_Write_byte( 0x2b, 0x00 ); //data lenth

    LT8911EXB_IIC_Write_byte( 0x2b, 0x00 ); //data lenth

    LT8911EXB_IIC_Write_byte( 0x2c, 0x00 ); //start Aux read edid



#ifdef _uart_debug_

    printf( "\r\n" );

    printf( "\r\nRead eDP EDID......" );

#endif



    Delay_ms( 20 );                         //more than 10ms

    reg = LT8911EXB_IIC_Read_byte( 0x25 );

    if( ( reg & 0x0f ) == 0x0c )

    {

        for( j = 0; j < 8; j++ )

        {

            if( j == 7 )

            {

                LT8911EXB_IIC_Write_byte( 0x2b, 0x10 ); //MOT

            }else

            {

                LT8911EXB_IIC_Write_byte( 0x2b, 0x50 );

            }



            LT8911EXB_IIC_Write_byte( 0x2b, 0x00 );

            LT8911EXB_IIC_Write_byte( 0x2b, 0x50 );

            LT8911EXB_IIC_Write_byte( 0x2b, 0x0f );

            LT8911EXB_IIC_Write_byte( 0x2c, 0x00 ); //start Aux read edid

            Delay_ms( 50 );                         //more than 50ms



            if( LT8911EXB_IIC_Read_byte( 0x39 ) == 0x31 )

            {

                LT8911EXB_IIC_Read_byte( 0x2b );

                for( i = 0; i < 16; i++ )

                {

                    EDID_DATA[j * 16 + i] = LT8911EXB_IIC_Read_byte( 0x2b );

                }



                EDID_Reply = 1;

            }else

            {

                EDID_Reply = 0;

#ifdef _uart_debug_

                printf( "\r\nno_reply" );

                printf( "\r\n" );

#endif

                //        print("\r\n*************End***************");

                return;

            }

        }



#ifdef _uart_debug_



        for( i = 0; i < 128; i++ ) //print edid data

        {

            if( ( i % 16 ) == 0 )

            {

                printf( "\r\n" );

            }

            printf( ", ", EDID_DATA[i] );

        }



        printf( "\r\n" );

        printf( "\r\neDP Timing = { H_FP / H_pluse / H_BP / H_act / H_tol / V_FP / V_pluse / V_BP / V_act / V_tol / D_CLK };" );

        printf( "\r\neDP Timing = { " );

        EDID_Timing[hfp] = ( ( EDID_DATA[0x41] & 0xC0 ) * 4 + EDID_DATA[0x3e] );

        printf( (u32)EDID_Timing[hfp] );        // HFB

        printf( ", " );



        EDID_Timing[hs] = ( ( EDID_DATA[0x41] & 0x30 ) * 16 + EDID_DATA[0x3f] );

        printf( (u32)EDID_Timing[hs] );         // Hsync Wid

        printf( ", " );



        EDID_Timing[hbp] = ( ( ( EDID_DATA[0x3a] & 0x0f ) * 0x100 + EDID_DATA[0x39] ) - ( ( EDID_DATA[0x41] & 0x30 ) * 16 + EDID_DATA[0x3f] ) - ( ( EDID_DATA[0x41] & 0xC0 ) * 4 + EDID_DATA[0x3e] ) );

        printf( (u32)EDID_Timing[hbp] );        // HBP

        printf( ", " );



        EDID_Timing[hact] = ( ( EDID_DATA[0x3a] & 0xf0 ) * 16 + EDID_DATA[0x38] );

        printf( (u32)EDID_Timing[hact] );       // H active

        printf( ", " );



        EDID_Timing[htotal] = ( ( EDID_DATA[0x3a] & 0xf0 ) * 16 + EDID_DATA[0x38] + ( ( EDID_DATA[0x3a] & 0x0f ) * 0x100 + EDID_DATA[0x39] ) );

        printf( (u32)EDID_Timing[htotal] );     // H total

        printf( ", " );



        EDID_Timing[vfp] = ( ( EDID_DATA[0x41] & 0x0c ) * 4 + ( EDID_DATA[0x40] & 0xf0 ) / 16 );

        printf( (u32)EDID_Timing[vfp] );        // VFB

        printf( ", " );



        EDID_Timing[vs] = ( ( EDID_DATA[0x41] & 0x03 ) * 16 + EDID_DATA[0x40] & 0x0f );

        printf( (u32)EDID_Timing[vs] );         // Vsync Wid

        printf( ", " );



        EDID_Timing[vbp] = ( ( ( EDID_DATA[0x3d] & 0x03 ) * 0x100 + EDID_DATA[0x3c] ) - ( ( EDID_DATA[0x41] & 0x03 ) * 16 + EDID_DATA[0x40] & 0x0f ) - ( ( EDID_DATA[0x41] & 0x0c ) * 4 + ( EDID_DATA[0x40] & 0xf0 ) / 16 ) );

        printf( (u32)EDID_Timing[vbp] );        // VBP

        printf( ", " );



        EDID_Timing[vact] = ( ( EDID_DATA[0x3d] & 0xf0 ) * 16 + EDID_DATA[0x3b] );

        printf( (u32)EDID_Timing[vact] );       // V active

        printf( ", " );



        EDID_Timing[vtotal] = ( ( EDID_DATA[0x3d] & 0xf0 ) * 16 + EDID_DATA[0x3b] + ( ( EDID_DATA[0x3d] & 0x03 ) * 0x100 + EDID_DATA[0x3c] ) );

        printf( (u32)EDID_Timing[vtotal] );     // V total

        printf( ", " );



        EDID_Timing[pclk_10khz] = ( EDID_DATA[0x37] * 0x100 + EDID_DATA[0x36] );

        printf( (u32)EDID_Timing[pclk_10khz] ); // CLK

        printf( " };" );

        printf( "\r\n" );

#endif

    }



    return;



#endif

}



/***********************************************************



***********************************************************/

void LT8911EXB_MIPI_Video_Timing( void )                                    // ( struct video_timing *video_format )

{

    LT8911EXB_IIC_Write_byte( 0xff, 0xd0 );

    LT8911EXB_IIC_Write_byte( 0x0d, (u8)( MIPI_Timing[vtotal] / 256 ) );

    LT8911EXB_IIC_Write_byte( 0x0e, (u8)( MIPI_Timing[vtotal] % 256 ) );    //vtotal

    LT8911EXB_IIC_Write_byte( 0x0f, (u8)( MIPI_Timing[vact] / 256 ) );

    LT8911EXB_IIC_Write_byte( 0x10, (u8)( MIPI_Timing[vact] % 256 ) );      //vactive



    LT8911EXB_IIC_Write_byte( 0x11, (u8)( MIPI_Timing[htotal] / 256 ) );

    LT8911EXB_IIC_Write_byte( 0x12, (u8)( MIPI_Timing[htotal] % 256 ) );    //htotal

    LT8911EXB_IIC_Write_byte( 0x13, (u8)( MIPI_Timing[hact] / 256 ) );

    LT8911EXB_IIC_Write_byte( 0x14, (u8)( MIPI_Timing[hact] % 256 ) );      //hactive



    LT8911EXB_IIC_Write_byte( 0x15, (u8)( MIPI_Timing[vs] % 256 ) );        //vsa

    LT8911EXB_IIC_Write_byte( 0x16, (u8)( MIPI_Timing[hs] % 256 ) );        //hsa

    LT8911EXB_IIC_Write_byte( 0x17, (u8)( MIPI_Timing[vfp] / 256 ) );

    LT8911EXB_IIC_Write_byte( 0x18, (u8)( MIPI_Timing[vfp] % 256 ) );       //vfp



    LT8911EXB_IIC_Write_byte( 0x19, (u8)( MIPI_Timing[hfp] / 256 ) );

    LT8911EXB_IIC_Write_byte( 0x1a, (u8)( MIPI_Timing[hfp] % 256 ) );       //hfp

}



//------------------------------------



void LT8911EXB_eDP_Video_cfg( void )                                        // ( struct video_timing *video_format )

{

    LT8911EXB_IIC_Write_byte( 0xff, 0xa8 );

    LT8911EXB_IIC_Write_byte( 0x2d, 0x88 );                                 // MSA from register



#ifdef _Msa_Active_Only_

    LT8911EXB_IIC_Write_byte( 0x05, 0x00 );

    LT8911EXB_IIC_Write_byte( 0x06, 0x00 );                                 //htotal

    LT8911EXB_IIC_Write_byte( 0x07, 0x00 );

    LT8911EXB_IIC_Write_byte( 0x08, 0x00 );                                 //h_start



    LT8911EXB_IIC_Write_byte( 0x09, 0x00 );

    LT8911EXB_IIC_Write_byte( 0x0a, 0x00 );                                 //hsa

    LT8911EXB_IIC_Write_byte( 0x0b, (u8)( MIPI_Timing[hact] / 256 ) );

    LT8911EXB_IIC_Write_byte( 0x0c, (u8)( MIPI_Timing[hact] % 256 ) );      //hactive



    LT8911EXB_IIC_Write_byte( 0x0d, 0x00 );

    LT8911EXB_IIC_Write_byte( 0x0e, 0x00 );                                 //vtotal



    LT8911EXB_IIC_Write_byte( 0x11, 0x00 );

    LT8911EXB_IIC_Write_byte( 0x12, 0x00 );

    LT8911EXB_IIC_Write_byte( 0x14, 0x00 );

    LT8911EXB_IIC_Write_byte( 0x15, (u8)( MIPI_Timing[vact] / 256 ) );

    LT8911EXB_IIC_Write_byte( 0x16, (u8)( MIPI_Timing[vact] % 256 ) );      //vactive



#else



    LT8911EXB_IIC_Write_byte( 0x05, (u8)( MIPI_Timing[htotal] / 256 ) );

    LT8911EXB_IIC_Write_byte( 0x06, (u8)( MIPI_Timing[htotal] % 256 ) );

    LT8911EXB_IIC_Write_byte( 0x07, (u8)( ( MIPI_Timing[hs] + MIPI_Timing[hbp] ) / 256 ) );

    LT8911EXB_IIC_Write_byte( 0x08, (u8)( ( MIPI_Timing[hs] + MIPI_Timing[hbp] ) % 256 ) );

    LT8911EXB_IIC_Write_byte( 0x09, (u8)( MIPI_Timing[hs] / 256 ) );

    LT8911EXB_IIC_Write_byte( 0x0a, (u8)( MIPI_Timing[hs] % 256 ) );

    LT8911EXB_IIC_Write_byte( 0x0b, (u8)( MIPI_Timing[hact] / 256 ) );

    LT8911EXB_IIC_Write_byte( 0x0c, (u8)( MIPI_Timing[hact] % 256 ) );

    LT8911EXB_IIC_Write_byte( 0x0d, (u8)( MIPI_Timing[vtotal] / 256 ) );

    LT8911EXB_IIC_Write_byte( 0x0e, (u8)( MIPI_Timing[vtotal] % 256 ) );

    LT8911EXB_IIC_Write_byte( 0x11, (u8)( ( MIPI_Timing[vs] + MIPI_Timing[vbp] ) / 256 ) );

    LT8911EXB_IIC_Write_byte( 0x12, (u8)( ( MIPI_Timing[vs] + MIPI_Timing[vbp] ) % 256 ) );

    LT8911EXB_IIC_Write_byte( 0x14, (u8)( MIPI_Timing[vs] % 256 ) );

    LT8911EXB_IIC_Write_byte( 0x15, (u8)( MIPI_Timing[vact] / 256 ) );

    LT8911EXB_IIC_Write_byte( 0x16, (u8)( MIPI_Timing[vact] % 256 ) );

#endif

}



/***********************************************************



***********************************************************/



//------------------------------------



void LT8911EXB_init( void )

{

    u8    i;

    u8    pcr_pll_postdiv;

    u8    pcr_m;

    u16 Temp16;



    /* init */

    LT8911EXB_IIC_Write_byte( 0xff, 0x81 ); // Change Reg bank

    LT8911EXB_IIC_Write_byte( 0x08, 0x7f ); // i2c over aux issue

    LT8911EXB_IIC_Write_byte( 0x49, 0xff ); // enable 0x87xx



    LT8911EXB_IIC_Write_byte( 0xff, 0x82 ); // Change Reg bank

    LT8911EXB_IIC_Write_byte( 0x5a, 0x0e ); // GPIO test output



    //for power consumption//

    LT8911EXB_IIC_Write_byte( 0xff, 0x81 );

    LT8911EXB_IIC_Write_byte( 0x05, 0x06 );

    LT8911EXB_IIC_Write_byte( 0x43, 0x00 );

    LT8911EXB_IIC_Write_byte( 0x44, 0x1f );

    #if( eDP_lane == 4) 
    LT8911EXB_IIC_Write_byte( 0x45, 0xff );

    LT8911EXB_IIC_Write_byte( 0x46, 0xfe );

    #else

    LT8911EXB_IIC_Write_byte( 0x45, 0xf7 );

    LT8911EXB_IIC_Write_byte( 0x46, 0xf6 );

    #endif

    LT8911EXB_IIC_Write_byte( 0x49, 0x7f );



    LT8911EXB_IIC_Write_byte( 0xff, 0x82 );

    #if( eDP_lane == 2) // 2 lane eDP

        {

        LT8911EXB_IIC_Write_byte( 0x12, 0x33 );

        }

    #elif( eDP_lane == 1) // 1 lane eDP

        {

        LT8911EXB_IIC_Write_byte( 0x12, 0x11 );

        }

    #elif( eDP_lane == 4) // 4 lane eDP

        {

        LT8911EXB_IIC_Write_byte( 0x12, 0xff );

    }



#endif



    /* mipi Rx analog */

    LT8911EXB_IIC_Write_byte( 0xff, 0x82 ); // Change Reg bank

    LT8911EXB_IIC_Write_byte( 0x32, 0x51 );

    LT8911EXB_IIC_Write_byte( 0x35, 0x22 ); //EQ current 0x22/0x42/0x62/0x82/0xA2/0xC2/0xe2

    LT8911EXB_IIC_Write_byte( 0x3a, 0x77 ); //EQ 12.5db

    LT8911EXB_IIC_Write_byte( 0x3b, 0x77 ); //EQ 12.5db



    LT8911EXB_IIC_Write_byte( 0x4c, 0x0c );

    LT8911EXB_IIC_Write_byte( 0x4d, 0x00 );



    /* dessc_pcr  pll analog */

    LT8911EXB_IIC_Write_byte( 0xff, 0x82 ); // Change Reg bank

    LT8911EXB_IIC_Write_byte( 0x6a, 0x40 );

    LT8911EXB_IIC_Write_byte( 0x6b, PCR_PLL_PREDIV );



    Temp16 = MIPI_Timing[pclk_10khz];



    if( MIPI_Timing[pclk_10khz] < 8800 )

    {

        LT8911EXB_IIC_Write_byte( 0x6e, 0x82 ); //0x44:pre-div = 2 ,pixel_clk=44~ 88MHz

        pcr_pll_postdiv = 0x08;

    }else

    if( MIPI_Timing[pclk_10khz] < 17600 )

    {

        LT8911EXB_IIC_Write_byte( 0x6e, 0x81 ); //0x40:pre-div = 1, pixel_clk =88~176MHz

        pcr_pll_postdiv = 0x04;

    }else

    {

        LT8911EXB_IIC_Write_byte( 0x6e, 0x80 ); //0x40:pre-div = 0, pixel_clk =176~200MHz

        pcr_pll_postdiv = 0x02;

    }



    pcr_m = (u8)( Temp16 * pcr_pll_postdiv / 25 / 100 );



    /* dessc pll digital */

    LT8911EXB_IIC_Write_byte( 0xff, 0x85 );     // Change Reg bank

    LT8911EXB_IIC_Write_byte( 0xa9, 0x31 );

    LT8911EXB_IIC_Write_byte( 0xaa, 0x17 );

    LT8911EXB_IIC_Write_byte( 0xab, 0xba );

    LT8911EXB_IIC_Write_byte( 0xac, 0xe1 );

    LT8911EXB_IIC_Write_byte( 0xad, 0x47 );

    LT8911EXB_IIC_Write_byte( 0xae, 0x01 );

    LT8911EXB_IIC_Write_byte( 0xae, 0x11 );



    /* Digital Top */

    LT8911EXB_IIC_Write_byte( 0xff, 0x85 );                             // Change Reg bank

    LT8911EXB_IIC_Write_byte( 0xc0, 0x01 );                             //select mipi Rx

#ifdef _6bit_

    LT8911EXB_IIC_Write_byte( 0xb0, 0xd0 );                             //enable dither

#else

    LT8911EXB_IIC_Write_byte( 0xb0, 0x00 );                             // disable dither

#endif



    /* mipi Rx Digital */

    LT8911EXB_IIC_Write_byte( 0xff, 0xd0 );                             // Change Reg bank

    LT8911EXB_IIC_Write_byte( 0x00, _MIPI_data_PN_ + _MIPI_Lane_ % 4 ); // 0: 4 Lane / 1: 1 Lane / 2 : 2 Lane / 3: 3 Lane

    LT8911EXB_IIC_Write_byte( 0x02, 0x08 );                             //settle

    LT8911EXB_IIC_Write_byte( 0x03, _MIPI_data_sequence_ );             // default is 0x00

    LT8911EXB_IIC_Write_byte( 0x08, 0x00 );

//    LT8911EXB_IIC_Write_byte( 0x0a, 0x12 );               //pcr mode



    LT8911EXB_IIC_Write_byte( 0x0c, 0x80 );                             //fifo position

    LT8911EXB_IIC_Write_byte( 0x1c, 0x80 );                             //fifo position



    //    hs mode:MIPIÐвÉÑù£»vs mode:MIPIÖ¡²ÉÑù

    LT8911EXB_IIC_Write_byte( 0x24, 0x70 );                             // 0x30  [3:0]  line limit      //pcr mode( de hs vs)



    LT8911EXB_IIC_Write_byte( 0x31, 0x0a );



    /*stage1 hs mode*/

    LT8911EXB_IIC_Write_byte( 0x25, 0x90 );                             // 0x80           // line limit

    LT8911EXB_IIC_Write_byte( 0x2a, 0x3a );                             // 0x04           // step in limit

    LT8911EXB_IIC_Write_byte( 0x21, 0x4f );                             // hs_step

    LT8911EXB_IIC_Write_byte( 0x22, 0xff );



    /*stage2 de mode*/

    LT8911EXB_IIC_Write_byte( 0x0a, 0x02 );                             //de adjust pre line

    LT8911EXB_IIC_Write_byte( 0x38, 0x02 );                             //de_threshold 1

    LT8911EXB_IIC_Write_byte( 0x39, 0x04 );                             //de_threshold 2

    LT8911EXB_IIC_Write_byte( 0x3a, 0x08 );                             //de_threshold 3

    LT8911EXB_IIC_Write_byte( 0x3b, 0x10 );                             //de_threshold 4



    LT8911EXB_IIC_Write_byte( 0x3f, 0x04 );                             //de_step 1

    LT8911EXB_IIC_Write_byte( 0x40, 0x08 );                             //de_step 2

    LT8911EXB_IIC_Write_byte( 0x41, 0x10 );                             //de_step 3

    LT8911EXB_IIC_Write_byte( 0x42, 0x60 );                             //de_step 4



    /*stage2 hs mode*/

    LT8911EXB_IIC_Write_byte( 0x1e, 0x01 );                             // 0x11

    LT8911EXB_IIC_Write_byte( 0x23, 0xf0 );                             // 0x80               //



    LT8911EXB_IIC_Write_byte( 0x2b, 0x80 );                             // 0xa0



#ifdef _Test_Pattern_

    LT8911EXB_IIC_Write_byte( 0x26, ( pcr_m | 0x80 ) );

#else



    LT8911EXB_IIC_Write_byte( 0x26, pcr_m );



//    LT8911EXB_IIC_Write_byte( 0x27, Read_0xD095 );

//    LT8911EXB_IIC_Write_byte( 0x28, Read_0xD096 );

#endif



    LT8911EXB_MIPI_Video_Timing( );         //defualt setting is 1080P



    LT8911EXB_IIC_Write_byte( 0xff, 0x81 ); // Change Reg bank

    LT8911EXB_IIC_Write_byte( 0x03, 0x7b ); //PCR reset

    LT8911EXB_IIC_Write_byte( 0x03, 0xff );



#ifdef _eDP_2G7_

    LT8911EXB_IIC_Write_byte( 0xff, 0x87 );

    LT8911EXB_IIC_Write_byte( 0x19, 0x31 );

//    LT8911EXB_IIC_Write_byte( 0x1a, 0x36 ); // sync m

    LT8911EXB_IIC_Write_byte(0x1a,0x1b);

    LT8911EXB_IIC_Write_byte( 0x1b, 0x00 ); // sync_k [7:0]

    LT8911EXB_IIC_Write_byte( 0x1c, 0x00 ); // sync_k [13:8]



    // txpll Analog

    LT8911EXB_IIC_Write_byte( 0xff, 0x82 );

    LT8911EXB_IIC_Write_byte( 0x09, 0x00 ); // div hardware mode, for ssc.



//    LT8911EXB_IIC_Write_byte( 0x01, 0x18 );// default : 0x18

    LT8911EXB_IIC_Write_byte( 0x02, 0x42 );

    LT8911EXB_IIC_Write_byte( 0x03, 0x00 ); // txpll en = 0

    LT8911EXB_IIC_Write_byte( 0x03, 0x01 ); // txpll en = 1

//    LT8911EXB_IIC_Write_byte( 0x04, 0x3a );// default : 0x3A

    LT8911EXB_IIC_Write_byte(0x0a,0x1b);

    LT8911EXB_IIC_Write_byte(0x04,0x2a);

		
    LT8911EXB_IIC_Write_byte( 0xff, 0x87 );

    LT8911EXB_IIC_Write_byte( 0x0c, 0x10 ); // cal en = 0



    LT8911EXB_IIC_Write_byte( 0xff, 0x81 );

    LT8911EXB_IIC_Write_byte( 0x09, 0xfc );

    LT8911EXB_IIC_Write_byte( 0x09, 0xfd );



    LT8911EXB_IIC_Write_byte( 0xff, 0x87 );

    LT8911EXB_IIC_Write_byte( 0x0c, 0x11 ); // cal en = 1



    // ssc

    LT8911EXB_IIC_Write_byte( 0xff, 0x87 );

    LT8911EXB_IIC_Write_byte( 0x13, 0x83 );

    LT8911EXB_IIC_Write_byte( 0x14, 0x41 );

    LT8911EXB_IIC_Write_byte( 0x16, 0x0a );

    LT8911EXB_IIC_Write_byte( 0x18, 0x0a );

    LT8911EXB_IIC_Write_byte( 0x19, 0x33 );

#endif



#ifdef _eDP_1G62_

    LT8911EXB_IIC_Write_byte( 0xff, 0x87 );

    LT8911EXB_IIC_Write_byte( 0x19, 0x31 );

    LT8911EXB_IIC_Write_byte( 0x1a, 0x20 ); // sync m

    LT8911EXB_IIC_Write_byte( 0x1b, 0x19 ); // sync_k [7:0]

    LT8911EXB_IIC_Write_byte( 0x1c, 0x99 ); // sync_k [13:8]



    // txpll Analog

    LT8911EXB_IIC_Write_byte( 0xff, 0x82 );

    LT8911EXB_IIC_Write_byte( 0x09, 0x00 ); // div hardware mode, for ssc.

    //    LT8911EXB_IIC_Write_byte( 0x01, 0x18 );// default : 0x18

    LT8911EXB_IIC_Write_byte( 0x02, 0x42 );

    LT8911EXB_IIC_Write_byte( 0x03, 0x00 ); // txpll en = 0

    LT8911EXB_IIC_Write_byte( 0x03, 0x01 ); // txpll en = 1

    //    LT8911EXB_IIC_Write_byte( 0x04, 0x3a );// default : 0x3A



    LT8911EXB_IIC_Write_byte( 0xff, 0x87 );

    LT8911EXB_IIC_Write_byte( 0x0c, 0x10 ); // cal en = 0



    LT8911EXB_IIC_Write_byte( 0xff, 0x81 );

    LT8911EXB_IIC_Write_byte( 0x09, 0xfc );

    LT8911EXB_IIC_Write_byte( 0x09, 0xfd );



    LT8911EXB_IIC_Write_byte( 0xff, 0x87 );

    LT8911EXB_IIC_Write_byte( 0x0c, 0x11 ); // cal en = 1



    //ssc

    LT8911EXB_IIC_Write_byte( 0xff, 0x87 );

    LT8911EXB_IIC_Write_byte( 0x13, 0x83 );

    LT8911EXB_IIC_Write_byte( 0x14, 0x41 );

    LT8911EXB_IIC_Write_byte( 0x16, 0x0a );

    LT8911EXB_IIC_Write_byte( 0x18, 0x0a );

    LT8911EXB_IIC_Write_byte( 0x19, 0x33 );

#endif



    LT8911EXB_IIC_Write_byte( 0xff, 0x87 );



    for( i = 0; i < 5; i++ ) //Check Tx PLL

    {

        Delay_ms( 5 );

        if( LT8911EXB_IIC_Read_byte( 0x37 ) & 0x02 )

        {

            printf( "\r\nLT8911 tx pll locked" );

            LT8911EXB_IIC_Write_byte(0xff,0x87);

            LT8911EXB_IIC_Write_byte(0x1a,0x36);

            LT8911EXB_IIC_Write_byte(0xff,0x82);

            LT8911EXB_IIC_Write_byte(0x0a,0x36);

            LT8911EXB_IIC_Write_byte(0x04,0x3a);

            break;

        }else

        {

            printf( "\r\nLT8911 tx pll unlocked" );

            LT8911EXB_IIC_Write_byte( 0xff, 0x81 );

            LT8911EXB_IIC_Write_byte( 0x09, 0xfc );

            LT8911EXB_IIC_Write_byte( 0x09, 0xfd );



            LT8911EXB_IIC_Write_byte( 0xff, 0x87 );

            LT8911EXB_IIC_Write_byte( 0x0c, 0x10 );

            LT8911EXB_IIC_Write_byte( 0x0c, 0x11 );

        }

    }



    LT8911EXB_IIC_Write_byte( 0xff, 0xac ); // Change Reg bank

    LT8911EXB_IIC_Write_byte( 0x15, _eDP_data_sequence_ ); // eDP data swap

    LT8911EXB_IIC_Write_byte( 0x16, _eDP_data_PN_); // eDP P / N swap



    // AUX reset

    LT8911EXB_IIC_Write_byte( 0xff, 0x81 ); // Change Reg bank

    LT8911EXB_IIC_Write_byte( 0x07, 0xfe );

    LT8911EXB_IIC_Write_byte( 0x07, 0xff );

    LT8911EXB_IIC_Write_byte( 0x0a, 0xfc );

    LT8911EXB_IIC_Write_byte( 0x0a, 0xfe );



    /* tx phy */

    LT8911EXB_IIC_Write_byte( 0xff, 0x82 ); // Change Reg bank

    LT8911EXB_IIC_Write_byte( 0x11, 0x00 );

    LT8911EXB_IIC_Write_byte( 0x13, 0x10 );

    LT8911EXB_IIC_Write_byte( 0x14, 0x0c );

    LT8911EXB_IIC_Write_byte( 0x14, 0x08 );

    LT8911EXB_IIC_Write_byte( 0x13, 0x20 );



    LT8911EXB_IIC_Write_byte( 0xff, 0x82 ); // Change Reg bank

    LT8911EXB_IIC_Write_byte( 0x0e, 0x35 );

//    LT8911EXB_IIC_Write_byte( 0x12, 0xff );

//    LT8911EXB_IIC_Write_byte( 0xff, 0x80 );

//    LT8911EXB_IIC_Write_byte( 0x40, 0x22 );



    /*eDP Tx Digital */

    LT8911EXB_IIC_Write_byte( 0xff, 0xa8 ); // Change Reg bank



#ifdef _Test_Pattern_



    LT8911EXB_IIC_Write_byte( 0x24, 0x50 ); // bit2 ~ bit 0 : test panttern image mode

    LT8911EXB_IIC_Write_byte( 0x25, 0x70 ); // bit6 ~ bit 4 : test Pattern color

    LT8911EXB_IIC_Write_byte( 0x27, 0x50 ); //0x50:Pattern; 0x10:mipi video



//    LT8911EXB_IIC_Write_byte( 0x2d, 0x00 ); //  pure color setting

//    LT8911EXB_IIC_Write_byte( 0x2d, 0x84 ); // black color

    LT8911EXB_IIC_Write_byte( 0x2d, 0x88 ); //  block



#else

    LT8911EXB_IIC_Write_byte( 0x27, 0x10 ); //0x50:Pattern; 0x10:mipi video

#endif



#ifdef _6bit_

    LT8911EXB_IIC_Write_byte( 0x17, 0x00 );

    LT8911EXB_IIC_Write_byte( 0x18, 0x00 );

#else

    // _8bit_

    LT8911EXB_IIC_Write_byte( 0x17, 0x10 );

    LT8911EXB_IIC_Write_byte( 0x18, 0x20 );

#endif



    /* nvid */

    LT8911EXB_IIC_Write_byte( 0xff, 0xa0 );                             // Change Reg bank

    LT8911EXB_IIC_Write_byte( 0x00, (u8)( Nvid_Val[_Nvid] / 256 ) );    // 0x08

    LT8911EXB_IIC_Write_byte( 0x01, (u8)( Nvid_Val[_Nvid] % 256 ) );    // 0x00

}



//-------------------------------------------------------------------

/* mipi should be ready before configuring below video check setting*/

void LT8911EXB_video_check( void )

{

    u8    temp;

    u32 reg = 0x00;

    /* mipi byte clk check*/

    LT8911EXB_IIC_Write_byte( 0xff, 0x85 );     // Change Reg bank

    LT8911EXB_IIC_Write_byte( 0x1d, 0x00 );     //FM select byte clk

    LT8911EXB_IIC_Write_byte( 0x40, 0xf7 );

    LT8911EXB_IIC_Write_byte( 0x41, 0x30 );



    //#ifdef _eDP_scramble_

    if( ScrambleMode )

    {

        LT8911EXB_IIC_Write_byte( 0xa1, 0x82 ); //eDP scramble mode;

    }

    //#else

    else

    {

        LT8911EXB_IIC_Write_byte( 0xa1, 0x02 ); // DP scramble mode;

    }

    //#endif



//    LT8911EXB_IIC_Write_byte( 0x17, 0xf0 ); // 0xf0:Close scramble; 0xD0 : Open scramble



    LT8911EXB_IIC_Write_byte( 0xff, 0x81 );

    LT8911EXB_IIC_Write_byte( 0x09, 0x7d );

    LT8911EXB_IIC_Write_byte( 0x09, 0xfd );



    LT8911EXB_IIC_Write_byte( 0xff, 0x85 );

    Delay_ms( 200 );

    if( LT8911EXB_IIC_Read_byte( 0x50 ) == 0x03 )

    {

        reg       = LT8911EXB_IIC_Read_byte( 0x4d );

        reg       = reg * 256 + LT8911EXB_IIC_Read_byte( 0x4e );

        reg       = reg * 256 + LT8911EXB_IIC_Read_byte( 0x4f );



        printf( "\r\nvideo check: mipi byteclk =  " ); // mipi byteclk = reg * 1000

        printf( reg );

    }else

    {

        printf( "\r\nvideo check: mipi clk unstable" );

    }



    /* mipi vtotal check*/

    reg       = LT8911EXB_IIC_Read_byte( 0x76 );

    reg       = reg * 256 + LT8911EXB_IIC_Read_byte( 0x77 );



    printf( "\r\nvideo check: Vtotal =  " );

    printf( reg );



    /* mipi word count check*/

    LT8911EXB_IIC_Write_byte( 0xff, 0xd0 );

    reg       = LT8911EXB_IIC_Read_byte( 0x82 );

    reg       = reg * 256 + LT8911EXB_IIC_Read_byte( 0x83 );

    reg       = reg / 3;



    printf( "\r\nvideo check: Hact(word counter) =  " );

    printf( reg );



    /* mipi Vact check*/

    reg       = LT8911EXB_IIC_Read_byte( 0x85 );

    reg       = reg * 256 + LT8911EXB_IIC_Read_byte( 0x86 );



    printf( "\r\nvideo check: Vact =  " );

    printf( reg );

}



//------------------------------------------------------------------

void DpcdWrite( u32 Address, u8 Data )

{

    /***************************

       ×¢Òâ´óС¶ËµÄÎÊÌâ!

       ÕâÀïĬÈÏÊÇ´ó¶Ëģʽ



       Pay attention to the Big-Endian and Little-Endian!

       The default mode is Big-Endian here.



     ****************************/

    u8    AddressH   = 0x0f & ( Address >> 16 );

    u8    AddressM   = 0xff & ( Address >> 8 );

    u8    AddressL   = 0xff & Address;



    u8    reg;



    LT8911EXB_IIC_Write_byte( 0xff, 0xa6 );

    LT8911EXB_IIC_Write_byte( 0x2b, ( 0x80 | AddressH ) );  //CMD

    LT8911EXB_IIC_Write_byte( 0x2b, AddressM );             //addr[15:8]

    LT8911EXB_IIC_Write_byte( 0x2b, AddressL );             //addr[7:0]

    LT8911EXB_IIC_Write_byte( 0x2b, 0x00 );                 //data lenth

    LT8911EXB_IIC_Write_byte( 0x2b, Data );                 //data

    LT8911EXB_IIC_Write_byte( 0x2c, 0x00 );                 //start Aux



    Delay_ms( 20 );                                         //more than 10ms

    reg = LT8911EXB_IIC_Read_byte( 0x25 );



    if( ( reg & 0x0f ) == 0x0c )

    {

        return;

    }

}



//------------------------------------------------------------------



u8 DpcdRead( u32 Address )

{

    /***************************

       ×¢Òâ´óС¶ËµÄÎÊÌâ!

       ÕâÀïĬÈÏÊÇ´ó¶Ëģʽ



       Pay attention to the Big-Endian and Little-Endian!

       The default mode is Big-Endian here.



     ****************************/



    u8    DpcdValue  = 0x00;

    u8    AddressH   = 0x0f & ( Address >> 16 );

    u8    AddressM   = 0xff & ( Address >> 8 );

    u8    AddressL   = 0xff & Address;

    u8    reg;



    LT8911EXB_IIC_Write_byte( 0xff, 0xac );

    LT8911EXB_IIC_Write_byte( 0x00, 0x20 );                 //Soft Link train

    LT8911EXB_IIC_Write_byte( 0xff, 0xa6 );

    LT8911EXB_IIC_Write_byte( 0x2a, 0x01 );



    LT8911EXB_IIC_Write_byte( 0xff, 0xa6 );

    LT8911EXB_IIC_Write_byte( 0x2b, ( 0x90 | AddressH ) );  //CMD

    LT8911EXB_IIC_Write_byte( 0x2b, AddressM );             //addr[15:8]

    LT8911EXB_IIC_Write_byte( 0x2b, AddressL );             //addr[7:0]

    LT8911EXB_IIC_Write_byte( 0x2b, 0x00 );                 //data lenth

    LT8911EXB_IIC_Write_byte( 0x2c, 0x00 );                 //start Aux read edid



    Delay_ms( 50 );                                         //more than 10ms

    reg = LT8911EXB_IIC_Read_byte( 0x25 );

    if( ( reg & 0x0f ) == 0x0c )

    {

        if( LT8911EXB_IIC_Read_byte( 0x39 ) == 0x22 )

        {

            LT8911EXB_IIC_Read_byte( 0x2b );

            DpcdValue = LT8911EXB_IIC_Read_byte( 0x2b );

        }





        /*

           else

           {

           //    goto no_reply;

           //    DpcdValue = 0xff;

           return DpcdValue;

           }//*/

    }else

    {

        LT8911EXB_IIC_Write_byte( 0xff, 0x81 ); // change bank

        LT8911EXB_IIC_Write_byte( 0x07, 0xfe );

        LT8911EXB_IIC_Write_byte( 0x07, 0xff );

        LT8911EXB_IIC_Write_byte( 0x0a, 0xfc );

        LT8911EXB_IIC_Write_byte( 0x0a, 0xfe );

    }



    return DpcdValue;

}



//------------------------------------------------------------------



void LT8911EX_link_train( void )

{

    LT8911EXB_IIC_Write_byte( 0xff, 0x81 );

    LT8911EXB_IIC_Write_byte( 0x06, 0xdf ); // rset VID TX

    LT8911EXB_IIC_Write_byte( 0x06, 0xff );



    LT8911EXB_IIC_Write_byte( 0xff, 0x85 );



//    LT8911EXB_IIC_Write_byte( 0x17, 0xf0 ); // turn off scramble



//#ifdef _eDP_scramble_

    if( ScrambleMode )

    {

        LT8911EXB_IIC_Write_byte( 0xa1, 0x82 ); // eDP scramble mode;



        /* Aux operater init */

        LT8911EXB_IIC_Write_byte( 0xff, 0xac );

        LT8911EXB_IIC_Write_byte( 0x00, 0x20 ); //Soft Link train

        LT8911EXB_IIC_Write_byte( 0xff, 0xa6 );

        LT8911EXB_IIC_Write_byte( 0x2a, 0x01 );



#if( eDP_lane == 4) 
        DpcdWrite( 0x0101, 0x84 );

        Delay_ms( 10 );

#endif

        DpcdWrite( 0x010a, 0x01 );

        Delay_ms( 10 );

        DpcdWrite( 0x0102, 0x00 );

        Delay_ms( 10 );

        DpcdWrite( 0x010a, 0x01 );



        Delay_ms( 200 );

        //*/

    }

//#else

    else

    {

        LT8911EXB_IIC_Write_byte( 0xa1, 0x02 ); // DP scramble mode;



        /* Aux operater init */

#if( eDP_lane == 4) 
        LT8911EXB_IIC_Write_byte( 0xff, 0xac );

        LT8911EXB_IIC_Write_byte( 0x00, 0x20 ); //Soft Link train

        LT8911EXB_IIC_Write_byte( 0xff, 0xa6 );

        LT8911EXB_IIC_Write_byte( 0x2a, 0x01 );



        DpcdWrite( 0x0101, 0x84 );

        Delay_ms( 10 );

#endif

    }

//#endif



    /* Aux setup */

    LT8911EXB_IIC_Write_byte( 0xff, 0xac );

    LT8911EXB_IIC_Write_byte( 0x00, 0x60 );     //Soft Link train

    LT8911EXB_IIC_Write_byte( 0xff, 0xa6 );

    LT8911EXB_IIC_Write_byte( 0x2a, 0x00 );



    LT8911EXB_IIC_Write_byte( 0xff, 0x81 );

    LT8911EXB_IIC_Write_byte( 0x07, 0xfe );

    LT8911EXB_IIC_Write_byte( 0x07, 0xff );

    LT8911EXB_IIC_Write_byte( 0x0a, 0xfc );

    LT8911EXB_IIC_Write_byte( 0x0a, 0xfe );



    /* link train */



    LT8911EXB_IIC_Write_byte( 0xff, 0x85 );

    LT8911EXB_IIC_Write_byte( 0x1a, eDP_lane );



#ifdef _link_train_enable_

    LT8911EXB_IIC_Write_byte( 0xff, 0xac );

    LT8911EXB_IIC_Write_byte( 0x00, 0x64 );

    LT8911EXB_IIC_Write_byte( 0x01, 0x0a );

    LT8911EXB_IIC_Write_byte( 0x0c, 0x85 );

    LT8911EXB_IIC_Write_byte( 0x0c, 0xc5 );

#else

    LT8911EXB_IIC_Write_byte( 0xff, 0xac );

    LT8911EXB_IIC_Write_byte( 0x00, 0x00 );

    LT8911EXB_IIC_Write_byte( 0x01, 0x0a );

    LT8911EXB_IIC_Write_byte( 0x14, 0x80 );

    LT8911EXB_IIC_Write_byte( 0x14, 0x81 );

    Delay_ms( 50 );

    LT8911EXB_IIC_Write_byte( 0x14, 0x84 );

    Delay_ms( 50 );

    LT8911EXB_IIC_Write_byte( 0x14, 0xc0 );

#endif

}



//-------------------------------------------



//*

void LT8911EX_link_train_result( void )

{

    u8 i, reg;

    LT8911EXB_IIC_Write_byte( 0xff, 0xac );

    for( i = 0; i < 10; i++ )

    {

        reg = LT8911EXB_IIC_Read_byte( 0x82 );

        //  Debug_DispStrNum( "\r\n0x82 = ", reg );

        if( reg & 0x20 )

        {

            if( ( reg & 0x1f ) == 0x1e )

            {

                printf( "\r\nLink train success, 0x82 = ", reg );

            } else

            {

                printf( "\r\nLink train fail, 0x82 = ", reg );

            }



            printf( "\r\npanel link rate: ", LT8911EXB_IIC_Read_byte( 0x83 ) );

            printf( "\r\npanel link count: ", LT8911EXB_IIC_Read_byte( 0x84 ) );

            return;

        }else

        {

            printf( "\r\nlink trian on going..." );

        }

        Delay_ms( 100 );

    }

}



//*/



void LT8911EXB_MainLoop( void )

{

#ifndef _Test_Pattern_

    u16 reg;



    LT8911EXB_IIC_Write_byte( 0xff, 0x85 );

    //LT8911EXB_IIC_Write_byte(0x1d,0x00); //FM select byte clk

    //LT8911EXB_IIC_Write_byte(0x40,0xf7);

    //LT8911EXB_IIC_Write_byte(0x41,0x30);



    if( ScrambleMode )

    {

        LT8911EXB_IIC_Write_byte( 0xa1, 0x82 ); //

    }else

    {

        LT8911EXB_IIC_Write_byte( 0xa1, 0x02 ); //

    }



    LT8911EXB_IIC_Write_byte( 0xff, 0x81 );     //video check rst

    LT8911EXB_IIC_Write_byte( 0x09, 0x7d );

    LT8911EXB_IIC_Write_byte( 0x09, 0xfd );

    Delay_ms( 50 );



    LT8911EXB_IIC_Write_byte( 0xff, 0x85 );

    reg       = LT8911EXB_IIC_Read_byte( 0x76 );

    reg       = reg * 256 + LT8911EXB_IIC_Read_byte( 0x77 );



//    if( reg == MIPI_Timing[vtotal] )

    if( ( reg > ( MIPI_Timing[vtotal] - 5 ) ) && ( reg < ( MIPI_Timing[vtotal] + 5 ) ) )

    {

        if( !flag_mipi_on )

        {

            LT8911EXB_IIC_Write_byte( 0xff, 0x81 ); //PCR reset

            LT8911EXB_IIC_Write_byte( 0x03, 0x7b );

            LT8911EXB_IIC_Write_byte( 0x03, 0xff );



            LT8911EXB_IIC_Write_byte( 0xff, 0xa8 );

            LT8911EXB_IIC_Write_byte( 0x2d, 0x88 );

            flag_mipi_on = 1;

            printf( "\r\nPCR reset" );

        }

    }else

    {

        LT8911EXB_IIC_Write_byte( 0xff, 0xa8 );

        LT8911EXB_IIC_Write_byte( 0x2d, 0x8c ); //edp output idle pattern;

        flag_mipi_on = 0;

    }



#ifdef _uart_debug_

    LT8911EXB_IIC_Write_byte( 0xff, 0xd0 );

    reg = LT8911EXB_IIC_Read_byte( 0x87 );

//    reg       = reg * 256 + HDMI_ReadI2C_Byte( 0x77 );



    printf( "\r\nReg0xD087 =  " );

    printf( " ", reg );

    printf( "\r\n " );

    if( reg & 0x10 )

    {

        printf( "\r\nPCR Clock stable" );

    }else

    {

        printf( "\r\nPCR Clock unstable" );

    }

    printf( "\r\n " );

#endif



#endif

}



/***********************************************************/





/*

   reg 0x822/0x8226 : bit1 bit0

   Da_edptx0_tap0_current_tune software output set value:



   2'b00 = None;

   2'b01 = 12.8mA;

   2'b10 = 15mA



   //--------------------------//



   reg 0x8223/ 0x8227 bit7 ~ bit0

   Da_edptx_tap0_current_tune software output set value:



   8'b00000000 = None;

   8'b00000001 = 50uA;

   8'b00000010 = 100uA;

   8'b00000100 = 200uA;

   8'b00001000 = 400uA;

   8'b00010000 = 800uA;

   8'b00100000 = 1.6mA;

   8'b01000000 = 3.2mA;

   8'b10000000 = 6.4mA



   //--------------------------//



 */

enum

{

    _Level0_ = 0,                                               // 27.8 mA  0x83/0x00

    _Level1_,                                                   // 26.2 mA  0x82/0xe0

    _Level2_,                                                   // 24.6 mA  0x82/0xc0

    _Level3_,                                                   // 23 mA    0x82/0xa0

    _Level4_,                                                   // 21.4 mA  0x82/0x80

    _Level5_,                                                   // 18.2 mA  0x82/0x40

    _Level6_,                                                   // 16.6 mA  0x82/0x20

    _Level7_,                                                   // 15mA     0x82/0x00  // level 1

    _Level8_,                                                   // 12.8mA   0x81/0x00  // level 2

    _Level9_,                                                   // 11.2mA   0x80/0xe0  // level 3

    _Level10_,                                                  // 9.6mA    0x80/0xc0  // level 4

    _Level11_,                                                  // 8mA      0x80/0xa0  // level 5

    _Level12_,                                                  // 6mA      0x80/0x80  // level 6

};



u8    Swing_Setting1[] = { 0x83, 0x82, 0x82, 0x82, 0x82, 0x82, 0x82, 0x82, 0x81, 0x80, 0x80, 0x80, 0x80 };

u8    Swing_Setting2[] = { 0x00, 0xe0, 0xc0, 0xa0, 0x80, 0x40, 0x20, 0x00, 0x00, 0xe0, 0xc0, 0xa0, 0x80 };



u8    Level = _Level7_;                                           // normal





/***********************************************************



***********************************************************/

void LT8911EX_TxSwingPreSet( void )

{

    LT8911EXB_IIC_Write_byte( 0xFF, 0x82 );

    LT8911EXB_IIC_Write_byte( 0x22, Swing_Setting1[Level] );    //lane 0 tap0

    LT8911EXB_IIC_Write_byte( 0x23, Swing_Setting2[Level] );

    LT8911EXB_IIC_Write_byte( 0x24, 0x80 );                     //lane 0 tap1

    LT8911EXB_IIC_Write_byte( 0x25, 0x00 );

	
    #if( eDP_lane >= 2)

    LT8911EXB_IIC_Write_byte( 0x26, Swing_Setting1[Level] );    //lane 1 tap0

    LT8911EXB_IIC_Write_byte( 0x27, Swing_Setting2[Level] );

    LT8911EXB_IIC_Write_byte( 0x28, 0x80 );                     //lane 1 tap1

    LT8911EXB_IIC_Write_byte( 0x29, 0x00 );



    #if( eDP_lane == 4)

    LT8911EXB_IIC_Write_byte( 0x2a, Swing_Setting1[Level] ); //lane 2 tap0

    LT8911EXB_IIC_Write_byte( 0x2b, Swing_Setting2[Level] );

    LT8911EXB_IIC_Write_byte( 0x2c, 0x80 );                  //lane 2 tap1

    LT8911EXB_IIC_Write_byte( 0x2d, 0x00 );

    LT8911EXB_IIC_Write_byte( 0x2e, Swing_Setting1[Level] ); //lane 3 tap0

    LT8911EXB_IIC_Write_byte( 0x2f, Swing_Setting2[Level] );

    LT8911EXB_IIC_Write_byte( 0x30, 0x80 );                  //lane 3 tap1

    LT8911EXB_IIC_Write_byte( 0x31, 0x00 );

    #endif

    #endif

}



/***********************************************************



***********************************************************/

void PCR_Status( void )                                         // for debug

{

#ifdef _uart_debug_

    u8 reg;



    LT8911EXB_IIC_Write_byte( 0xff, 0xd0 );

    reg = LT8911EXB_IIC_Read_byte( 0x87 );



    printf( "\r\nReg0xD087 =    ");

    printf( " ", reg );

    printf( "\r\n " );

    if( reg & 0x10 )

    {

        printf( "\r\nPCR Clock stable" );

    }else

    {

        printf( "\r\nPCR Clock unstable" );

    }

    printf( "\r\n " );

#endif

}



/***********************************************************



***********************************************************/

void Reset_LT8911EXB( void )

{

    _LT8911_RSTN_LOW;   // GPIO Low

    Delay_ms( 100 );

    _LT8911_RSTN_High;  // GPIO High

    Delay_ms( 100 );

}



/***********************************************************



***********************************************************/

void LT8911_MainLoop( void )

{

    u16 reg, H_act, V_act;

//    bool    flag_mipi_on = 0;



    LT8911EXB_IIC_Write_byte( 0xff, 0x85 );



    if( ScrambleMode )

    {

        LT8911EXB_IIC_Write_byte( 0xa1, 0x82 ); //video check from mipi

    }else

    {

        LT8911EXB_IIC_Write_byte( 0xa1, 0x02 );

    }



    LT8911EXB_IIC_Write_byte( 0xff, 0x81 );     //video check rst

    LT8911EXB_IIC_Write_byte( 0x09, 0x7d );

    LT8911EXB_IIC_Write_byte( 0x09, 0xfd );

    Delay_ms( 50 );



    /* mipi word count check*/

    LT8911EXB_IIC_Write_byte( 0xff, 0xd0 );

    reg       = LT8911EXB_IIC_Read_byte( 0x82 );

    reg       = reg * 256 + LT8911EXB_IIC_Read_byte( 0x83 );

    H_act  = reg / 3;



#ifdef _uart_debug_



    printf( "\r\nHact(word counter) =  " ); // H active = word counter / 3

    printf( H_act );

    printf( "\r\n " );



#endif



    /* mipi Vact check*/

    reg       = LT8911EXB_IIC_Read_byte( 0x85 );

    V_act  = reg * 256 + LT8911EXB_IIC_Read_byte( 0x86 );



#ifdef _uart_debug_



    printf( "\r\nVact =  " );

    printf( V_act );

    printf( "\r\n " );

#endif



    LT8911EXB_IIC_Write_byte( 0xff, 0x85 );

    reg       = LT8911EXB_IIC_Read_byte( 0x76 );

    reg       = reg * 256 + LT8911EXB_IIC_Read_byte( 0x77 );



#ifdef _uart_debug_

    printf( "\r\nvideo check: Vtotal =  " );

    printf( reg );

    printf( "\r\n " );

#endif



//    if( reg == MIPI_Timing[vtotal] )

    if( ( reg > ( MIPI_Timing[vtotal] - 5 ) ) && ( reg < ( MIPI_Timing[vtotal] + 5 ) ) )

    {

        if( !flag_mipi_on )

        {

            LT8911EXB_IIC_Write_byte( 0xff, 0x81 ); //PCR reset

            LT8911EXB_IIC_Write_byte( 0x03, 0x7b );

            LT8911EXB_IIC_Write_byte( 0x03, 0xff );



            LT8911EXB_IIC_Write_byte( 0xff, 0xa8 );

            LT8911EXB_IIC_Write_byte( 0x2d, 0x88 );

            flag_mipi_on = 1;

#ifdef _uart_debug_

            printf( "\r\nPCR reset" );

#endif

        }

    }else

    {

        LT8911EXB_IIC_Write_byte( 0xff, 0xa8 );

        LT8911EXB_IIC_Write_byte( 0x2d, 0x8c ); //edp output idle pattern;

        flag_mipi_on = 0;

    }



#ifdef _uart_debug_

    LT8911EXB_IIC_Write_byte( 0xff, 0xd0 );

    reg = LT8911EXB_IIC_Read_byte( 0x87 );



    printf( "\r\nReg0xD087 =  " );

    printf( " ", reg );

    printf( "\r\n " );

    if( reg & 0x10 )

    {

        printf( "\r\nPCR Clock stable" );

    }else

    {

        printf( "\r\nPCR Clock unstable" );

    }

    printf( "\r\n " );

#endif

}



/***********************************************************/



void LT8911EXB_LinkTrainResultCheck( void )

{

#ifdef _link_train_enable_

    u8    i;

    u8    val;

    //int ret;



    LT8911EXB_IIC_Write_byte( 0xff, 0xac );

    for( i = 0; i < 10; i++ )

    {

        val = LT8911EXB_IIC_Read_byte( 0x82 );

        if( val & 0x20 )

        {

            if( ( val & 0x1f ) == 0x1e )

            {

#ifdef _uart_debug_

                //   printf("\r\nLT8911_LinkTrainResultCheck: edp link train successed: 0x%bx", val);

                printf( "\r\nedp link train successed: ", val );

#endif

                return;

            }else

            {

#ifdef _uart_debug_

                //printf("\r\nLT8911_LinkTrainResultCheck: edp link train failed: 0x%bx", val);

                printf( "\r\nedp link train failed: ", val );

#endif

                LT8911EXB_IIC_Write_byte( 0xff, 0xac );

                LT8911EXB_IIC_Write_byte( 0x00, 0x00 );

                LT8911EXB_IIC_Write_byte( 0x01, 0x0a );

                LT8911EXB_IIC_Write_byte( 0x14, 0x80 );

                LT8911EXB_IIC_Write_byte( 0x14, 0x81 );

                Delay_ms( 50 );

                LT8911EXB_IIC_Write_byte( 0x14, 0x84 );

                Delay_ms( 50 );

                LT8911EXB_IIC_Write_byte( 0x14, 0xc0 );

                //printf("\r\nLT8911_LinkTrainResultCheck: Enable eDP video output while linktrian fail");

            }



#ifdef _uart_debug_



            val = LT8911EXB_IIC_Read_byte( 0x83 );

            //printf("\r\nLT8911_LinkTrainResultCheck: panel link rate: 0x%bx",val);

            printf( "\r\npanel link rate: ", val );

            val = LT8911EXB_IIC_Read_byte( 0x84 );

            //printf("\r\nLT8911_LinkTrainResultCheck: panel link count: 0x%bx",val);

            printf( "\r\npanel link count: ", val );

#endif

            Delay_ms( 100 ); // return;

        }else

        {

            //printf("\r\nLT8911_LinkTrainResultCheck: link trian on going...");

            Delay_ms( 100 );

        }

    }

#endif

}



//----------------------------------------



// void LT8911EXB_config( void )

void main( void )



{

    Reset_LT8911EXB( );     // ÏÈReset LT8911EXB ,ÓÃGPIO ÏÈÀ­µÍLT8911EXBµÄ¸´Î»½Å 100ms×óÓÒ£¬ÔÙÀ­¸ß£¬±£³Ö100ms¡£



    LT8911EX_ChipID( );     // read Chip ID



    LT8911EXB_eDP_Video_cfg( );

    LT8911EXB_init( );



    LT8911EXB_read_edid( ); // for debug





/*

   Read_DPCD010A = DpcdRead( 0x010A ) & 0x01;



   #ifdef _uart_debug_

   Debug_Printf( "\r\n" );

   Debug_DispStrNum( "\r\nDPCD010Ah:%x,", Read_DPCD010A );

   #endif



   if( Read_DPCD010A )

   {

   ScrambleMode = 1;

   }else

   {

   ScrambleMode = 0;

   }

   //*/

    ScrambleMode = 0;



    LT8911EX_TxSwingPreSet( );



    LT8911EX_link_train( );



    LT8911EXB_LinkTrainResultCheck( );

//======================================//

    LT8911EX_link_train_result( );  // for debug



    LT8911EXB_video_check( );       // just for Check MIPI Input



    PCR_Status( );                  // just for Check PCR CLK

//======================================//





/* If lt8911exb is controlled by MCU,LT8911_MainLoop( ) function is added in the main loop.

   while( 1 )

   {

   // Ñ­»·¼ì²âMIPIÐźţ¬Èç¹ûÓжÏÐø£¬ÐèÒªreset PCR

   //Loop detection of Mipi signal. If there is interruption, reset PCR will appear

   LT8911_MainLoop( );



   Delay_ms( 1000 );

   }

   //*/

}



/************************************** The End Of File **************************************/


 documents/edp/documents/LT8911EXB/LT8911EX_EXB_调试手册.pdf

Binary files differ

 documents/edp/documents/RK_AIC_eDP_V10/RK_AIC_eDP_pcb_top.pdf

Binary files differ

 documents/edp/documents/RK_AIC_eDP_V10/rk_aic_edp_v10_3d_bottom.png

 documents/edp/documents/RK_AIC_eDP_V10/rk_aic_edp_v10_3d_top.png

 documents/edp/documents/RK_AIC_eDP_V10/rk_aic_edp_v10_bom.xls

Binary files differ

 documents/edp/documents/RK_AIC_eDP_V10/rk_aic_edp_v10_sch.pdf

Binary files differ

 documents/edp/documents/eDP调试说明/01-20240529快递内容-1.jpg

 documents/edp/documents/eDP调试说明/02-20240529快递内容-2.jpg

 documents/edp/documents/eDP调试说明/03-eDP转接板接口说明.jpg

 documents/edp/documents/eDP调试说明/04-ILI2511 TPP转接口说明.jpg

 documents/edp/documents/eDP调试说明/05-LCD接柔性线-1.jpg

 documents/edp/documents/eDP调试说明/06-LCD接柔性线-2.jpg

 documents/edp/documents/eDP调试说明/07-LCD接FPC线-1.jpg

 documents/edp/documents/eDP调试说明/08-LCD接FPC线-2.jpg

 documents/edp/documents/eDP调试说明/09-eDP转接板完整接线.jpg

 documents/edp/documents/eDP调试说明/10-模拟输入4-20mA电流测试.png

 documents/edp/documents/eDP调试说明/11-模拟输入0-5V测试.png

 documents/schematic/rk_aic_v10_sch_20240220.pdf

Binary files differ