src/stm32L_bare/board/stm32_key.c
New file @@ -0,0 +1,83 @@ /**************************************************************************** * Copyright: (C)2018 Î人ÁèÔÆÎïÍøÖÇ¿ÆʵÑéÊÒ www.iot-yun.com * Author: GuoWenxue<guowenxue@gmail.com> QQ: 281143292 * Description: STM32L151C8T6 CubeMX ¿ª·¢°åÖ»ÓÐÒ»¸ö°´¼ü°´Å¥Á¬µ½PA0,ÁíÍâÒ»¸öÊǸ´Î»°´¼ü¡£ * * ChangeLog: * °æ±¾ºÅ ÈÕÆÚ ×÷Õß ËµÃ÷ * V1.0.0 2018.11.05 GuoWenxue ·¢²¼¸Ã°æ±¾ ****************************************************************************/ #include <stdio.h> #include "stm32l1xx.h" void init_key1_gpio_interrupt(void); /* º¯Êý˵Ã÷: ÅäÖÃËùÓеİ´¼üµÄ GPIO¿Ú¡¢Ê±ÖÓºÍÖÐ¶Ï */ void init_keys_interrupt(void) { /* STM32L151C8T6 CubeMX ¿ª·¢°åÖ»ÓÐÒ»¸ö°´¼ü°´Å¥Á¬µ½PA0ÉÏ */ init_key1_gpio_interrupt(); } void init_key1_gpio_interrupt(void) { GPIO_InitTypeDef GPIO_InitStructure; NVIC_InitTypeDef NVIC_InitStructure; EXTI_InitTypeDef EXTI_InitStructure; /* ʹÄÜGPIOAµÄʱÖÓ */ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE); /* ³õʼ»¯ÖжÏÓÅÏȼ¶ */ NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1); NVIC_InitStructure.NVIC_IRQChannel = EXTI0_IRQn; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 3; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); /* °´¼üÉ϶Ëͨ¹ýÉÏÀµç×èÁ¬µ½VCCÉÏ, ËùÒÔÉèÖÃÖжÏΪÉÏÉýÑØ´¥·¢ */ EXTI_DeInit(); EXTI_InitStructure.EXTI_Line = EXTI_Line0; EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; EXTI_InitStructure.EXTI_LineCmd = ENABLE; EXTI_Init(&EXTI_InitStructure); /* ĬÈϽ«GPIO¿ÚÅäÖóÉÏÂÀµÍµçƽģʽ, ÕâÑùµ±°´¼ü°´Ïº󽫻á±ä³ÉVCC²úÉúÉÏÉýÑØ */ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; GPIO_Init(GPIOA, &GPIO_InitStructure); } /* Ïû³ý°´¼ü¶¶¶¯ÑÓʱº¯Êý */ static __inline void key_dejitter_delay(void) { uint32_t times=6000; while( times--) ; } /* µ±°´¼ü°´ÏÂʱ»á²úÉúÖжϣ¬CPUÌøתµ½startup_stm32l1xx_md.sÖвéѯÖжÏÏòÁ¿±í,²¢µ÷ÓÃÏàÓ¦µÄÖжϷþÎñ´¦Àí³EXTI0_IRQHandler() */ void EXTI0_IRQHandler(void) { if(EXTI_GetITStatus(EXTI_Line0) != RESET) { /* È¥¶¶£º ÑÓʱһ¶Îʱ¼ä²é¿´GPIOµÄ״̬£¬Èç¹û»¹Êǵ͵çƽ˵Ã÷ÊÇÓÐЧ°´¼ü */ key_dejitter_delay(); if( Bit_SET == GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_0) ) { printf("Detect Key Pressed and turn LED ON/off.\n"); GPIO_WriteBit(GPIOB, GPIO_Pin_1, (BitAction)((1-GPIO_ReadOutputDataBit(GPIOB, GPIO_Pin_1)))); EXTI_ClearITPendingBit(EXTI_Line0); } } }
New file @@ -0,0 +1,19 @@ /**************************************************************************** * Copyright: (C)2018 Î人ÁèÔÆÎïÍøÖÇ¿ÆʵÑéÊÒ www.iot-yun.com * Author: GuoWenxue<guowenxue@gmail.com> QQ: 281143292 * Description: STM32L151C8T6 CubeMX ¿ª·¢°å °´¼ü ²Ù×÷º¯Êý * * ChangeLog: * °æ±¾ºÅ ÈÕÆÚ ×÷Õß ËµÃ÷ * V1.0.0 2018.11.05 GuoWenxue ·¢²¼¸Ã°æ±¾ ****************************************************************************/ #ifndef __STM32_KEY_H_ #define __STM32_KEY_H_ /* º¯Êý˵Ã÷: ÅäÖÃËùÓеİ´¼üµÄ GPIO¿Ú¡¢Ê±ÖÓºÍÖÐ¶Ï */ extern void init_keys_interrupt(void); #endif src/stm32L_bare/board/stm32_led.c
New file @@ -0,0 +1,60 @@ /**************************************************************************** * Copyright: (C)2018 Î人ÁèÔÆÎïÍøÖÇ¿ÆʵÑéÊÒ www.iot-yun.com * Author: GuoWenxue<guowenxue@gmail.com> QQ: 281143292 * Description: STM32L151C8T6 CubeMX ¿ª·¢°å LED²Ù×÷º¯Êý * * ChangeLog: * °æ±¾ºÅ ÈÕÆÚ ×÷Õß ËµÃ÷ * V1.0.0 2018.11.05 GuoWenxue ·¢²¼¸Ã°æ±¾ ****************************************************************************/ #include "stm32l1xx.h" #include "stm32_led.h" /* STM32L151C8T6 CubeMX ¿ª·¢°åÖ»ÓÐÒ»¸öGPIO¿ØÖÆµÄ Green LED£¬ ºìÉ«µÄLEDÊǵçԴָʾµÆ */ led_gpio_t leds_gpio[MAX_LED] = { {LED1, GPIOB, GPIO_Pin_1}, /* LED_Green ÓõÄGPB1 */ }; /* º¯Êý˵Ã÷: ÅäÖà LED GPIO¿ÚºÍʱÖÓ£» * ²ÎÊý˵Ã÷: ÎÞ * ·µ»ØÖµ: ÎÞ */ void init_led_gpio(void) { int i; GPIO_InitTypeDef GPIO_InitStructure; /* ʹÄÜPB×é GPIOµÄʱÖÓ */ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOB, ENABLE); /*ÉèÖà PB1(LED1) */ for(i=0; i<MAX_LED; i++) { GPIO_InitStructure.GPIO_Pin = leds_gpio[i].pin; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_Init(leds_gpio[i].group, &GPIO_InitStructure); } } /* º¯Êý˵Ã÷: µãÁÁ»òÃðµôÏàÓ¦LED * ²ÎÊý˵Ã÷: which: Òª²Ù×÷ÄĸöLED,ÆäÖµÓ¦¸ÃΪ LED1¡¢LED2 »ò LED3£ * cmd: ÒªÁÁ»¹ÊÇÃð, ÆäÖµ¶ÔӦΪ ON »ò OFF * ·µ»ØÖµ: ÎÞ */ void turn_led(int which, int cmd) { if(which<0 || which> MAX_LED ) return; if(OFF == cmd) GPIO_SetBits(leds_gpio[which].group, leds_gpio[which].pin); else GPIO_ResetBits(leds_gpio[which].group, leds_gpio[which].pin); } src/stm32L_bare/board/stm32_led.h
New file @@ -0,0 +1,49 @@ /**************************************************************************** * Copyright: (C)2018 Î人ÁèÔÆÎïÍøÖÇ¿ÆʵÑéÊÒ www.iot-yun.com * Author: GuoWenxue<guowenxue@gmail.com> QQ: 281143292 * Description: STM32L151C8T6 CubeMX ¿ª·¢°å LED²Ù×÷º¯Êý * * ChangeLog: * °æ±¾ºÅ ÈÕÆÚ ×÷Õß ËµÃ÷ * V1.0.0 2018.11.05 GuoWenxue ·¢²¼¸Ã°æ±¾ ****************************************************************************/ #ifndef __STM32_LED_H_ #define __STM32_LED_H_ #include "stm32l1xx.h" /* LED²Ù×÷µÄ ¿ª¹Øºê */ #define ON 1 #define OFF 0 /* 3¸öLEDµÄ±àºÅ¶¨Òå */ enum { LED1 = 0, MAX_LED, }; typedef struct led_gpio_s { int num; /* LED±àºÅ */ GPIO_TypeDef *group; /* LEDʹÓõÄGPIOÔÚÄÄÒ»×é: GPIOB or GPIOD */ uint16_t pin; /* LEDʹÓõÄGPIO×éÖеÄÄÇÒ»¸öpin: GPIO_Pin_x */ } led_gpio_t; /* º¯Êý˵Ã÷: ÅäÖà LED GPIO¿ÚºÍʱÖÓ£» * ²ÎÊý˵Ã÷: ÎÞ * ·µ»ØÖµ: ÎÞ */ extern void init_led_gpio(void); /* º¯Êý˵Ã÷: µãÁÁ»òÃðµôÏàÓ¦LED * ²ÎÊý˵Ã÷: which: Òª²Ù×÷ÄĸöLED,ÆäÖµÓ¦¸ÃΪ LED1¡¢LED2 »ò LED3? * cmd: ÒªÁÁ»¹ÊÇÃð, ÆäÖµ¶ÔӦΪ ON »ò OFF * ·µ»ØÖµ: ÎÞ */ extern void turn_led(int which, int cmd); #endif src/stm32L_bare/board/stm32_systick.c
New file @@ -0,0 +1,55 @@ /**************************************************************************** * Copyright: (C)2018 Î人ÁèÔÆÎïÍøÖÇ¿ÆʵÑéÊÒ www.iot-yun.com * Author: GuoWenxue<guowenxue@gmail.com> QQ: 281143292 * Description: STM32L151C8T6 CubeMX ¿ª·¢°å systick ÑÓʱº¯Êý¡¢jiffiesʵÏÖº¯Êý * * ChangeLog: * °æ±¾ºÅ ÈÕÆÚ ×÷Õß ËµÃ÷ * V1.0.0 2018.11.05 GuoWenxue ·¢²¼¸Ã°æ±¾ ****************************************************************************/ #include "stm32l1xx.h" #include "stm32_systick.h" static __IO uint32_t s_delay_ms; __IO uint32_t jiffies; /* ³õʼ»¯Systick, ÿ¸ô 1ms ²úÉúÒ»´ÎÖÐ¶Ï */ void init_systick(void) { /* Systick¶¨Ê±Æ÷»áÔÚÆäʱÖÓÊäÈëÿÀ´Ò»¸öʱÖÓÂö³åʱ×Ô¼õ1(¼´Ò»¸öϵͳµÎ´ð)£¬¶ø SystickÊǹÒÔÚAHB×ÜÏßÉϵģ¬ * Æä×ÜÏßƵÂÊÓëϵͳºËÐÄƵÂÊ(f=72MHz)Ò»ÖÂ. ÕâÑùSystickÉϵÄÒ»¸öµÎ´ðµÄʱ¼äÖÜÆÚ¾ÍÊÇ£º 1/f Ãë * * ÎÒÃÇ¿ÉÒÔͨ¹ý SysTick_Config()º¯ÊýÀ´ÅäÖÃsystickÿ¾¹ý¶àÉÙ¸öticks²úÉúÒ»´ÎÖжϣ¬ÖжϲúÉúºóÓ²¼þ½«×Ô¶¯ÖØмÓÔز¢ÖØпªÊ¼¼ÇÊý£» * ¼ÙÉèticks¸öʱÖÓÂö³åÊÇ 1ms : * 1Ãë = f ¸öticks => 1ms = f/1000 = SystemCoreClock/1000 * => 1us = f/1000000 = SystemCoreClock/1000000 */ if( SysTick_Config( SystemCoreClock/TICKS_PER_MSECOND ) ) { while(1); } } /* SystickÖжϴ¦Àíº¯Êý SysTick_Handler (stm32f10x_it.c) »áµ÷Óøú¯Êý */ void systick_handler_proc(void) { jiffies++; if (s_delay_ms != 0x00) { s_delay_ms--; } } /* sleep msºÁÃë */ void msleep(__IO uint32_t ms) { s_delay_ms = ms; while( s_delay_ms != 0); }
New file @@ -0,0 +1,57 @@ /**************************************************************************** * Copyright: (C)2018 Î人ÁèÔÆÎïÍøÖÇ¿ÆʵÑéÊÒ www.iot-yun.com * Author: GuoWenxue<guowenxue@gmail.com> QQ: 281143292 * Description: STM32L151C8T6 CubeMX ¿ª·¢°å systick ÑÓʱº¯Êý¡¢jiffiesʵÏÖº¯Êý * * ChangeLog: * °æ±¾ºÅ ÈÕÆÚ ×÷Õß ËµÃ÷ * V1.0.0 2018.11.05 GuoWenxue ·¢²¼¸Ã°æ±¾ ****************************************************************************/ #ifndef __STM32_SYSTICK_H_ #define __STM32_SYSTICK_H_ #define TICKS_PER_MSECOND 1000 /* ʱÖÓ½ÚÅÄÖжÏΪ1msÒ»´Î */ #define TICKS_PER_USECOND 1000000 /* ʱÖÓ½ÚÅÄÖжÏΪ1usÒ»´Î */ extern __IO uint32_t jiffies; /* * These inlines deal with timer wrapping correctly. You are strongly encouraged to use them * 1. Because people otherwise forget * 2. Because if the timer wrap changes in future you won't have to alter your driver code. * * time_after(a,b) returns true if the time a is after time b. * * Do this with "<0" and ">=0" to only test the sign of the result. A * good compiler would generate better code (and a really good compiler * wouldn't care). Gcc is currently neither. */ #define time_after(a,b) ((int32_t)(b) - (int32_t)(a) < 0) #define time_before(a,b) time_after(b,a) #define time_after_eq(a,b) ((int32_t)(a) - (int32_t)(b) >= 0) #define time_before_eq(a,b) time_after_eq(b,a) /* Timeout happened, x should be last jiffies+timeout value */ #define timeout_happened(x) (time_after_eq(jiffies, x)) /* ʹÓÃʵÀý´úÂë: ÔÚ100msÄÚ´òÓ¡"#" start_time = jiffies; while( time_before(jiffies, start_time+100) ) printf("#"); */ /* ³õʼ»¯Systick, ÿ¸ô 1ms ²úÉúÒ»´ÎÖÐ¶Ï */ extern void init_systick(void); /* SystickÖжϴ¦Àíº¯Êý: ÑÓʱʱ¼ä×Ô¼õ ºÍ jiffies ×Ô¼Ó */ extern void systick_handler_proc(void); /* sleep msºÁÃë */ extern void msleep(__IO uint32_t ms); #endif src/stm32L_bare/board/stm32_usart.c
New file @@ -0,0 +1,146 @@ /**************************************************************************** * Copyright: (C)2018 Î人ÁèÔÆÎïÍøÖÇ¿ÆʵÑéÊÒ www.iot-yun.com * Author: GuoWenxue<guowenxue@gmail.com> QQ: 281143292 * Description: STM32L151C8T6 CubeMX ¿ª·¢°å printfºÍ´®¿Ú³õʼ»¯º¯Êý * δʹÓÃÖжÏģʽ´¦Àí·¢ËͺͽÓÊÕ * * ChangeLog: * °æ±¾ºÅ ÈÕÆÚ ×÷Õß ËµÃ÷ * V1.0.0 2018.11.05 GuoWenxue ·¢²¼¸Ã°æ±¾ ****************************************************************************/ #include <stdio.h> #include "stm32_usart.h" static USART_TypeDef* debug_usart=USART1; /* ĬÈÏʹÓô®¿Ú1×÷Ϊµ÷ÊÔ´®¿Ú */ /* ¿ª·¢°åÉϵĸ÷¸ö´®¿ÚËùʹÓõĴ®¿Ú ¹Ü½Å¡¢Ê±ÖÓ¶¨Òå */ stm32_usart_pins_t usart_pins[USART_MAX] = { /* USARTx GPIOx Tx_Pin Rx_Pin Tx_Pin_source Rx_Pin_Source GPIO_AF_USARTx USART_Clock TxRx_GPIO_Clock */ {USART1, GPIOA, GPIO_Pin_9, GPIO_Pin_10, GPIO_PinSource9, GPIO_PinSource10, GPIO_AF_USART1, RCC_APB2Periph_USART1, RCC_AHBPeriph_GPIOA}, {USART2, GPIOA, GPIO_Pin_2, GPIO_Pin_3, GPIO_PinSource2, GPIO_PinSource3, GPIO_AF_USART2, RCC_APB1Periph_USART2, RCC_AHBPeriph_GPIOA}, {USART3, GPIOB, GPIO_Pin_10, GPIO_Pin_11, GPIO_PinSource10, GPIO_PinSource11, GPIO_AF_USART3, RCC_APB1Periph_USART3, RCC_AHBPeriph_GPIOB}, }; /* º¯Êý˵Ã÷: ÅäÖô®¿ÚGPIO¿ÚºÍʱÖÓ£» * ²ÎÊý˵Ã÷: whichÖ¸¶¨ÒªÅäÖõĴ®¿Ú,ÆäÖµÓ¦¸ÃΪ USART_PORT1¡¢USART_PORT2¡¢USART_PORT3£¬¶¨ÒåÔÚstm32_usart.hÖУ» * ·µ»ØÖµ: ÎÞ */ void init_usart_gpio(uint8_t which) { GPIO_InitTypeDef GPIO_InitStructure; if( which >= USART_MAX ) return ; /* Enable USART GPIO and USART clock */ RCC_AHBPeriphClockCmd(usart_pins[which].gpio_clk, ENABLE); if( USART_PORT1 == which ) RCC_APB2PeriphClockCmd(usart_pins[which].usart_clk, ENABLE); else RCC_APB1PeriphClockCmd(usart_pins[which].usart_clk, ENABLE); /* Connect PXx to USARTx_Tx, PXx to USARTx_Rx */ GPIO_PinAFConfig(usart_pins[which].group, usart_pins[which].txpin_src, usart_pins[which].gpio_af); GPIO_PinAFConfig(usart_pins[which].group, usart_pins[which].rxpin_src, usart_pins[which].gpio_af); GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz; /* Configure USART Tx as alternate function push-pull */ GPIO_InitStructure.GPIO_Pin = usart_pins[which].txpin; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_Init(usart_pins[which].group, &GPIO_InitStructure); /* Configure USART1 Rx as input floating */ GPIO_InitStructure.GPIO_Pin = usart_pins[which].rxpin; GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; GPIO_Init(usart_pins[which].group, &GPIO_InitStructure); } /* º¯Êý˵Ã÷: ÅäÖô®¿ÚµÄ²¨ÌØÂÊ¡¢Êý¾Ýλ¡¢ÆæżУÑéλ¡¢Í£Ö¹Î»¡¢Á÷¿ØµÈ£» * ²ÎÊý˵Ã÷: whichÖ¸¶¨ÒªÅäÖõĴ®¿Ú,ÆäÖµÓ¦¸ÃΪ USART_PORT1¡¢USART_PORT2¡¢USART_PORT3£¬¶¨ÒåÔÚstm32_usart.hÖУ» * baudrate: ²¨ÌØÂÊ,ÆäֵΪ: 115200,9600,4800,2400,1200.... * rxirq: ÊÇ·ñʹÄܽÓÊÕÖжϣ» 1->ʹÄÜ 0->²»Ê¹ÄÜ * txirq: ÊÇ·ñʹÄÜ·¢ËÍÖжϣ» 1->ʹÄÜ 0->²»Ê¹ÄÜ * ·µ»ØÖµ: ÎÞ */ void stm32_init_usart(uint8_t which, uint32_t baudrate, uint8_t txirq, uint8_t rxirq) { USART_InitTypeDef USART_InitStructure; if( which >= USART_MAX ) return ; init_usart_gpio(which); /* Configure USART1 */ USART_InitStructure.USART_BaudRate = baudrate; //²¨ÌØÂÊ USART_InitStructure.USART_WordLength = USART_WordLength_8b; //Êý¾Ýλ8λ USART_InitStructure.USART_StopBits = USART_StopBits_1; //ֹͣλ1λ USART_InitStructure.USART_Parity = USART_Parity_No; //ÎÞУÑéλ USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; //ÎÞÓ²¼þÁ÷¿Ø USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; //ÊÕ·¢Ä£Ê½ USART_Init(usart_pins[which].USARTx, &USART_InitStructure); //ÅäÖô®¿Ú²ÎÊýº¯Êý #if 0 /* Not implement yet */ if( rxirq ) //ʹÄܽÓÊÕÖÐ¶Ï USART_ITConfig(USARTx, USART_IT_RXNE, ENABLE); if( txirq ) //ʹÄÜ·¢ËÍ»º³å¿ÕÖÐ¶Ï USART_ITConfig(USARTx, USART_IT_TXE, ENABLE); #endif /* Enable the USARTx */ USART_Cmd(usart_pins[which].USARTx, ENABLE); } /* º¯Êý˵Ã÷: ³õʼ»¯µ÷ÊÔ´®¿Ú,²¢Ö¸¶¨ÏàÓ¦µÄ´®¿ÚΪprintfº¯ÊýµÄÊä³ö´®¿Ú * ²ÎÊý˵Ã÷: whichÖ¸¶¨ÒªÅäÖõĴ®¿Ú,ÆäÖµÓ¦¸ÃΪ USART_PORT1¡¢USART_PORT2¡¢USART_PORT3£¬¶¨ÒåÔÚstm32_usart.hÖУ» * baudrate: ²¨ÌØÂÊ,ÆäֵΪ: 115200,9600,4800,2400,1200.... * ·µ»ØÖµ£º ÎÞ */ void stm32_init_printf(uint8_t which, uint32_t baudrate) { if( which >= USART_MAX ) return ; debug_usart = usart_pins[which].USARTx; /* ³õʼ»¯ USART1µÄGPIO¿Ú */ stm32_init_usart(which, baudrate, TXIRQ_DISABLE, RXIRQ_DISABLE); /* Êä³öÒ»¸ö»Ø³µ, secureCRTÈí¼þ²Ù×÷´®¿ÚµÄʱºòÐèÒª */ USART_PUTCHR(debug_usart, '\n'); } /* º¯Êý˵Ã÷: printfº¯ÊýʵÏֵĹ³×Óº¯Êý * ²ÎÊý˵Ã÷: ch: Òª·¢Ë͵Ä×Ö·û FILE *f: δʹÓà * ·µ»ØÖµ£º ·¢Ë͵Ä×Ö·û */ int fputc(int ch, FILE *f) { /* windowsÏ»»ÐзûÊÇ\r\n,Èç¹ûÅöµ½\nÔòÔÚÇ°ÃæÌí¼Ó\r */ if('\n' == ch) { USART_PUTCHR(debug_usart, '\r'); } USART_PUTCHR(debug_usart, ch); return ch; }
New file @@ -0,0 +1,67 @@ /**************************************************************************** * Copyright: (C)2018 Î人ÁèÔÆÎïÍøÖÇ¿ÆʵÑéÊÒ www.iot-yun.com * Author: GuoWenxue<guowenxue@gmail.com> QQ: 281143292 * Description: STM32L151C8T6 CubeMX ¿ª·¢°å printfºÍ´®¿Ú³õʼ»¯º¯Êý * * ChangeLog: * °æ±¾ºÅ ÈÕÆÚ ×÷Õß ËµÃ÷ * V1.0.0 2018.11.05 GuoWenxue ·¢²¼¸Ã°æ±¾ ****************************************************************************/ #ifndef __STM32_USART_H_ #define __STM32_USART_H_ #include "stm32l1xx_usart.h" #define USART_PUTCHR(COM, ch) { USART_SendData(COM, ch); while (USART_GetFlagStatus(COM, USART_FLAG_TC) == RESET) ; } enum { USART_PORT1, USART_PORT2, USART_PORT3, USART_MAX, }; typedef struct stm32_usart_pins_s { USART_TypeDef *USARTx; /* USART1¡¢USART2¡¢USART3 */ GPIO_TypeDef *group; /* GPIOx: GPIOA¡¢GPIOB */ uint16_t txpin; /* GPIO_Pin: GPIO_Pin_2 */ uint16_t rxpin; /* GPIO_Pin: GPIO_Pin_3 */ uint16_t txpin_src; /* GPIO_PinSource: GPIO_PinSource2 */ uint16_t rxpin_src; /* GPIO_PinSource: GPIO_PinSource3 */ uint8_t gpio_af; /* GPIO_AF: GPIO_AF_USART1*/ uint32_t usart_clk; /* USART clock: RCC_APB1Periph_USART1 */ uint16_t gpio_clk; /* USART Tx/Rx Pin Clock: RCC_AHBPeriph_GPIOA */ } stm32_usart_pins_t; /* º¯Êý˵Ã÷: ÅäÖô®¿ÚµÄ²¨ÌØÂÊ¡¢Êý¾Ýλ¡¢ÆæżУÑéλ¡¢Í£Ö¹Î»¡¢Á÷¿ØµÈ£» * ²ÎÊý˵Ã÷: whichÖ¸¶¨ÒªÅäÖõĴ®¿Ú,ÆäÖµÓ¦¸ÃΪ USART_PORT1¡¢USART_PORT2¡¢USART_PORT3£¬¶¨ÒåÔÚstm32_usart.hÖУ» * baudrate: ²¨ÌØÂÊ,ÆäֵΪ: 115200,9600,4800,2400,1200.... * rxirq: ÊÇ·ñʹÄܽÓÊÕÖжϣ» 1->ʹÄÜ 0->²»Ê¹ÄÜ * txirq: ÊÇ·ñʹÄÜ·¢ËÍÖжϣ» 1->ʹÄÜ 0->²»Ê¹ÄÜ * ·µ»ØÖµ: ÎÞ */ #define RXIRQ_ENABLE 1 #define RXIRQ_DISABLE 0 #define TXIRQ_ENABLE 1 #define TXIRQ_DISABLE 0 extern void stm32_init_usart(uint8_t which, uint32_t baudrate, uint8_t txirq, uint8_t rxirq); /* º¯Êý˵Ã÷: ³õʼ»¯µ÷ÊÔ´®¿Ú,²¢Ö¸¶¨ÏàÓ¦µÄ´®¿ÚΪprintfº¯ÊýµÄÊä³ö´®¿Ú * ²ÎÊý˵Ã÷: whichÖ¸¶¨ÒªÅäÖõĴ®¿Ú,ÆäÖµÓ¦¸ÃΪ USART_PORT1¡¢USART_PORT2¡¢USART_PORT3£¬¶¨ÒåÔÚstm32_usart.hÖУ» * baudrate: ²¨ÌØÂÊ,ÆäֵΪ: 115200,9600,4800,2400,1200.... * ·µ»ØÖµ£º ÎÞ */ extern void stm32_init_printf(uint8_t which, uint32_t baudrate); /* º¯Êý˵Ã÷: Íùµ÷ÊÔ´®¿Ú·¢ËÍ×Ö·û´® * ²ÎÊý˵Ã÷: str Ö¸ÏòÒª·¢Ë͵Ä×Ö·û´®ÄÚÈÝ * ·µ»ØÖµ£º ÎÞ */ extern void usart_puts(const char *str); #endif src/stm32L_bare/board/stm32l1xx_it.c
New file @@ -0,0 +1,176 @@ /** ****************************************************************************** * @file SysTick/SysTick_Example/stm32l1xx_it.c * @author MCD Application Team * @version V1.2.1 * @date 20-April-2015 * @brief Main Interrupt Service Routines. * This file provides template for all exceptions handler and peripherals * interrupt service routine. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx_it.h" /** @addtogroup STM32L1xx_StdPeriph_Examples * @{ */ /** @addtogroup SysTick_Example * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /******************************************************************************/ /* Cortex-M3 Processor Exceptions Handlers */ /******************************************************************************/ /** * @brief This function handles NMI exception. * @param None * @retval None */ void NMI_Handler(void) { } /** * @brief This function handles Hard Fault exception. * @param None * @retval None */ void HardFault_Handler(void) { /* Go to infinite loop when Hard Fault exception occurs */ while (1) { } } /** * @brief This function handles Memory Manage exception. * @param None * @retval None */ void MemManage_Handler(void) { /* Go to infinite loop when Memory Manage exception occurs */ while (1) { } } /** * @brief This function handles Bus Fault exception. * @param None * @retval None */ void BusFault_Handler(void) { /* Go to infinite loop when Bus Fault exception occurs */ while (1) { } } /** * @brief This function handles Usage Fault exception. * @param None * @retval None */ void UsageFault_Handler(void) { /* Go to infinite loop when Usage Fault exception occurs */ while (1) { } } /** * @brief This function handles SVCall exception. * @param None * @retval None */ void SVC_Handler(void) { } /** * @brief This function handles Debug Monitor exception. * @param None * @retval None */ void DebugMon_Handler(void) { } /** * @brief This function handles PendSV_Handler exception. * @param None * @retval None */ void PendSV_Handler(void) { } /** * @brief This function handles SysTick Handler. * @param None * @retval None */ void systick_handler_proc(void); void SysTick_Handler(void) { systick_handler_proc(); } /******************************************************************************/ /* STM32L1xx Peripherals Interrupt Handlers */ /* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ /* available peripheral interrupt handler's name please refer to the startup */ /* file (startup_stm32l1xx_xx.s). */ /******************************************************************************/ /** * @brief This function handles PPP interrupt request. * @param None * @retval None */ /*void PPP_IRQHandler(void) { }*/ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/board/stm32l1xx_it.h
New file @@ -0,0 +1,60 @@ /** ****************************************************************************** * @file SysTick/SysTick_Example/stm32l1xx_it.h * @author MCD Application Team * @version V1.2.1 * @date 20-April-2015 * @brief This file contains the headers of the interrupt handlers. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L1xx_IT_H #define __STM32L1xx_IT_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx.h" /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ void NMI_Handler(void); void HardFault_Handler(void); void MemManage_Handler(void); void BusFault_Handler(void); void UsageFault_Handler(void); void SVC_Handler(void); void DebugMon_Handler(void); void PendSV_Handler(void); void SysTick_Handler(void); #ifdef __cplusplus } #endif #endif /* __STM32L1xx_IT_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/cmsis/startup_stm32l1xx_md.s
New file @@ -0,0 +1,319 @@ ;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** ;* File Name : startup_stm32l1xx_md.s ;* Author : MCD Application Team ;* Version : V1.3.3 ;* Date : 20-April-2015 ;* Description : STM32L1xx Ultra Low Power Medium-density Devices vector ;* table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == Reset_Handler ;* - Set the vector table entries with the exceptions ISR address ;* - Branches to __main in the C library (which eventually ;* calls main()). ;* After Reset the CortexM3 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;* <<< Use Configuration Wizard in Context Menu >>> ;******************************************************************************* ; ; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); ; You may not use this file except in compliance with the License. ; You may obtain a copy of the License at: ; ; http://www.st.com/software_license_agreement_liberty_v2 ; ; Unless required by applicable law or agreed to in writing, software ; distributed under the License is distributed on an "AS IS" BASIS, ; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ; See the License for the specific language governing permissions and ; limitations under the License. ; ;******************************************************************************* ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000200 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler DCD BusFault_Handler ; Bus Fault Handler DCD UsageFault_Handler ; Usage Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WWDG_IRQHandler ; Window Watchdog DCD PVD_IRQHandler ; PVD through EXTI Line detect DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp DCD RTC_WKUP_IRQHandler ; RTC Wakeup DCD FLASH_IRQHandler ; FLASH DCD RCC_IRQHandler ; RCC DCD EXTI0_IRQHandler ; EXTI Line 0 DCD EXTI1_IRQHandler ; EXTI Line 1 DCD EXTI2_IRQHandler ; EXTI Line 2 DCD EXTI3_IRQHandler ; EXTI Line 3 DCD EXTI4_IRQHandler ; EXTI Line 4 DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 DCD ADC1_IRQHandler ; ADC1 DCD USB_HP_IRQHandler ; USB High Priority DCD USB_LP_IRQHandler ; USB Low Priority DCD DAC_IRQHandler ; DAC DCD COMP_IRQHandler ; COMP through EXTI Line DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 DCD LCD_IRQHandler ; LCD DCD TIM9_IRQHandler ; TIM9 DCD TIM10_IRQHandler ; TIM10 DCD TIM11_IRQHandler ; TIM11 DCD TIM2_IRQHandler ; TIM2 DCD TIM3_IRQHandler ; TIM3 DCD TIM4_IRQHandler ; TIM4 DCD I2C1_EV_IRQHandler ; I2C1 Event DCD I2C1_ER_IRQHandler ; I2C1 Error DCD I2C2_EV_IRQHandler ; I2C2 Event DCD I2C2_ER_IRQHandler ; I2C2 Error DCD SPI1_IRQHandler ; SPI1 DCD SPI2_IRQHandler ; SPI2 DCD USART1_IRQHandler ; USART1 DCD USART2_IRQHandler ; USART2 DCD USART3_IRQHandler ; USART3 DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend DCD TIM6_IRQHandler ; TIM6 DCD TIM7_IRQHandler ; TIM7 __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset handler routine Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT __main IMPORT SystemInit LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP MemManage_Handler\ PROC EXPORT MemManage_Handler [WEAK] B . ENDP BusFault_Handler\ PROC EXPORT BusFault_Handler [WEAK] B . ENDP UsageFault_Handler\ PROC EXPORT UsageFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP DebugMon_Handler\ PROC EXPORT DebugMon_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WWDG_IRQHandler [WEAK] EXPORT PVD_IRQHandler [WEAK] EXPORT TAMPER_STAMP_IRQHandler [WEAK] EXPORT RTC_WKUP_IRQHandler [WEAK] EXPORT FLASH_IRQHandler [WEAK] EXPORT RCC_IRQHandler [WEAK] EXPORT EXTI0_IRQHandler [WEAK] EXPORT EXTI1_IRQHandler [WEAK] EXPORT EXTI2_IRQHandler [WEAK] EXPORT EXTI3_IRQHandler [WEAK] EXPORT EXTI4_IRQHandler [WEAK] EXPORT DMA1_Channel1_IRQHandler [WEAK] EXPORT DMA1_Channel2_IRQHandler [WEAK] EXPORT DMA1_Channel3_IRQHandler [WEAK] EXPORT DMA1_Channel4_IRQHandler [WEAK] EXPORT DMA1_Channel5_IRQHandler [WEAK] EXPORT DMA1_Channel6_IRQHandler [WEAK] EXPORT DMA1_Channel7_IRQHandler [WEAK] EXPORT ADC1_IRQHandler [WEAK] EXPORT USB_HP_IRQHandler [WEAK] EXPORT USB_LP_IRQHandler [WEAK] EXPORT DAC_IRQHandler [WEAK] EXPORT COMP_IRQHandler [WEAK] EXPORT EXTI9_5_IRQHandler [WEAK] EXPORT LCD_IRQHandler [WEAK] EXPORT TIM9_IRQHandler [WEAK] EXPORT TIM10_IRQHandler [WEAK] EXPORT TIM11_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT TIM3_IRQHandler [WEAK] EXPORT TIM4_IRQHandler [WEAK] EXPORT I2C1_EV_IRQHandler [WEAK] EXPORT I2C1_ER_IRQHandler [WEAK] EXPORT I2C2_EV_IRQHandler [WEAK] EXPORT I2C2_ER_IRQHandler [WEAK] EXPORT SPI1_IRQHandler [WEAK] EXPORT SPI2_IRQHandler [WEAK] EXPORT USART1_IRQHandler [WEAK] EXPORT USART2_IRQHandler [WEAK] EXPORT USART3_IRQHandler [WEAK] EXPORT EXTI15_10_IRQHandler [WEAK] EXPORT RTC_Alarm_IRQHandler [WEAK] EXPORT USB_FS_WKUP_IRQHandler [WEAK] EXPORT TIM6_IRQHandler [WEAK] EXPORT TIM7_IRQHandler [WEAK] WWDG_IRQHandler PVD_IRQHandler TAMPER_STAMP_IRQHandler RTC_WKUP_IRQHandler FLASH_IRQHandler RCC_IRQHandler EXTI0_IRQHandler EXTI1_IRQHandler EXTI2_IRQHandler EXTI3_IRQHandler EXTI4_IRQHandler DMA1_Channel1_IRQHandler DMA1_Channel2_IRQHandler DMA1_Channel3_IRQHandler DMA1_Channel4_IRQHandler DMA1_Channel5_IRQHandler DMA1_Channel6_IRQHandler DMA1_Channel7_IRQHandler ADC1_IRQHandler USB_HP_IRQHandler USB_LP_IRQHandler DAC_IRQHandler COMP_IRQHandler EXTI9_5_IRQHandler LCD_IRQHandler TIM9_IRQHandler TIM10_IRQHandler TIM11_IRQHandler TIM2_IRQHandler TIM3_IRQHandler TIM4_IRQHandler I2C1_EV_IRQHandler I2C1_ER_IRQHandler I2C2_EV_IRQHandler I2C2_ER_IRQHandler SPI1_IRQHandler SPI2_IRQHandler USART1_IRQHandler USART2_IRQHandler USART3_IRQHandler EXTI15_10_IRQHandler RTC_Alarm_IRQHandler USB_FS_WKUP_IRQHandler TIM6_IRQHandler TIM7_IRQHandler B . ENDP ALIGN ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ALIGN ENDIF END ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** src/stm32L_bare/cmsis/stm32l1xx.h
New file Diff too large src/stm32L_bare/cmsis/stm32l1xx_conf.h
New file @@ -0,0 +1,85 @@ /** ****************************************************************************** * @file Project/STM32L1xx_StdPeriph_Templates/stm32l1xx_conf.h * @author MCD Application Team * @version V1.2.0 * @date 16-May-2014 * @brief Library configuration file. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L1xx_CONF_H #define __STM32L1xx_CONF_H /* Includes ------------------------------------------------------------------*/ /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */ #include "stm32l1xx_adc.h" #include "stm32l1xx_aes.h" #include "stm32l1xx_comp.h" #include "stm32l1xx_crc.h" #include "stm32l1xx_dac.h" #include "stm32l1xx_dbgmcu.h" #include "stm32l1xx_dma.h" #include "stm32l1xx_exti.h" #include "stm32l1xx_flash.h" #include "stm32l1xx_fsmc.h" #include "stm32l1xx_gpio.h" #include "stm32l1xx_i2c.h" #include "stm32l1xx_iwdg.h" #include "stm32l1xx_lcd.h" #include "stm32l1xx_opamp.h" #include "stm32l1xx_pwr.h" #include "stm32l1xx_rcc.h" #include "stm32l1xx_rtc.h" #include "stm32l1xx_sdio.h" #include "stm32l1xx_spi.h" #include "stm32l1xx_syscfg.h" #include "stm32l1xx_tim.h" #include "stm32l1xx_usart.h" #include "stm32l1xx_wwdg.h" #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* Uncomment the line below to expanse the "assert_param" macro in the Standard Peripheral Library drivers code */ /* #define USE_FULL_ASSERT 1 */ /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT /** * @brief The assert_param macro is used for function's parameters check. * @param expr: If expr is false, it calls assert_failed function which reports * the name of the source file and the source line number of the call * that failed. If expr is true, it returns no value. * @retval None */ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ void assert_failed(uint8_t* file, uint32_t line); #else #define assert_param(expr) ((void)0) #endif /* USE_FULL_ASSERT */ #endif /* __STM32L1xx_CONF_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/cmsis/system_stm32l1xx.c
New file @@ -0,0 +1,533 @@ /** ****************************************************************************** * @file system_stm32l1xx.c * @author MCD Application Team * @version V1.3.3 * @date 20-April-2015 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. * This file contains the system clock configuration for STM32L1xx Ultra * Low Power devices, and is generated by the clock configuration * tool "STM32L1xx_Clock_Configuration_V1.1.0.xls". * * 1. This file provides two functions and one global variable to be called from * user application: * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier * and Divider factors, AHB/APBx prescalers and Flash settings), * depending on the configuration made in the clock xls tool. * This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32l1xx_xx.s" file. * * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used * by the user application to setup the SysTick * timer or configure other parameters. * * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must * be called whenever the core clock is changed * during program execution. * * 2. After each device reset the MSI (2.1 MHz Range) is used as system clock source. * Then SystemInit() function is called, in "startup_stm32l1xx_xx.s" file, to * configure the system clock before to branch to main program. * * 3. If the system clock source selected by user fails to startup, the SystemInit() * function will do nothing and MSI still used as system clock source. User can * add some code to deal with this issue inside the SetSysClock() function. * * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define * in "stm32l1xx.h" file. When HSE is used as system clock source, directly or * through PLL, and you are using different crystal you have to adapt the HSE * value to your own configuration. * * 5. This file configures the system clock as follows: *============================================================================= * System Clock Configuration *============================================================================= * System Clock source | PLL(HSE) *----------------------------------------------------------------------------- * SYSCLK | 32000000 Hz *----------------------------------------------------------------------------- * HCLK | 32000000 Hz *----------------------------------------------------------------------------- * AHB Prescaler | 1 *----------------------------------------------------------------------------- * APB1 Prescaler | 1 *----------------------------------------------------------------------------- * APB2 Prescaler | 1 *----------------------------------------------------------------------------- * HSE Frequency | 8000000 Hz *----------------------------------------------------------------------------- * PLL DIV | 3 *----------------------------------------------------------------------------- * PLL MUL | 12 *----------------------------------------------------------------------------- * VDD | 3.3 V *----------------------------------------------------------------------------- * Vcore | 1.8 V (Range 1) *----------------------------------------------------------------------------- * Flash Latency | 1 WS *----------------------------------------------------------------------------- * SDIO clock (SDIOCLK) | 48000000 Hz *----------------------------------------------------------------------------- * Require 48MHz for USB clock | Disabled *----------------------------------------------------------------------------- *============================================================================= ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /** @addtogroup CMSIS * @{ */ /** @addtogroup stm32l1xx_system * @{ */ /** @addtogroup STM32L1xx_System_Private_Includes * @{ */ #include "stm32l1xx.h" /** * @} */ /** @addtogroup STM32L1xx_System_Private_TypesDefinitions * @{ */ /** * @} */ /** @addtogroup STM32L1xx_System_Private_Defines * @{ */ /*!< Uncomment the following line if you need to use external SRAM mounted on STM32L152D_EVAL board as data memory */ /* #define DATA_IN_ExtSRAM */ /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ /* #define VECT_TAB_SRAM */ #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ /** * @} */ /** @addtogroup STM32L1xx_System_Private_Macros * @{ */ /** * @} */ /** @addtogroup STM32L1xx_System_Private_Variables * @{ */ uint32_t SystemCoreClock = 32000000; __I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} */ /** @addtogroup STM32L1xx_System_Private_FunctionPrototypes * @{ */ static void SetSysClock(void); #ifdef DATA_IN_ExtSRAM static void SystemInit_ExtMemCtl(void); #endif /* DATA_IN_ExtSRAM */ /** * @} */ /** @addtogroup STM32L1xx_System_Private_Functions * @{ */ /** * @brief Setup the microcontroller system. * Initialize the Embedded Flash Interface, the PLL and update the * SystemCoreClock variable. * @param None * @retval None */ void SystemInit (void) { /*!< Set MSION bit */ RCC->CR |= (uint32_t)0x00000100; /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ RCC->CFGR &= (uint32_t)0x88FFC00C; /*!< Reset HSION, HSEON, CSSON and PLLON bits */ RCC->CR &= (uint32_t)0xEEFEFFFE; /*!< Reset HSEBYP bit */ RCC->CR &= (uint32_t)0xFFFBFFFF; /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ RCC->CFGR &= (uint32_t)0xFF02FFFF; /*!< Disable all interrupts */ RCC->CIR = 0x00000000; #ifdef DATA_IN_ExtSRAM SystemInit_ExtMemCtl(); #endif /* DATA_IN_ExtSRAM */ /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */ SetSysClock(); #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ #endif } /** * @brief Update SystemCoreClock according to Clock Register Values * The SystemCoreClock variable contains the core clock (HCLK), it can * be used by the user application to setup the SysTick timer or configure * other parameters. * * @note Each time the core clock (HCLK) changes, this function must be called * to update SystemCoreClock variable value. Otherwise, any configuration * based on this variable will be incorrect. * * @note - The system frequency computed by this function is not the real * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: * * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI * value as defined by the MSI range. * * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) * * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) * * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) * or HSI_VALUE(*) multiplied/divided by the PLL factors. * * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value * 16 MHz) but the real value may vary depending on the variations * in voltage and temperature. * * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value * 8 MHz), user has to ensure that HSE_VALUE is same as the real * frequency of the crystal used. Otherwise, this function may * have wrong result. * * - The result of this function could be not correct when using fractional * value for HSE crystal. * @param None * @retval None */ void SystemCoreClockUpdate (void) { uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0; /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; switch (tmp) { case 0x00: /* MSI used as system clock */ msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; SystemCoreClock = (32768 * (1 << (msirange + 1))); break; case 0x04: /* HSI used as system clock */ SystemCoreClock = HSI_VALUE; break; case 0x08: /* HSE used as system clock */ SystemCoreClock = HSE_VALUE; break; case 0x0C: /* PLL used as system clock */ /* Get PLL clock source and multiplication factor ----------------------*/ pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; pllmul = PLLMulTable[(pllmul >> 18)]; plldiv = (plldiv >> 22) + 1; pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; if (pllsource == 0x00) { /* HSI oscillator clock selected as PLL clock entry */ SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); } else { /* HSE selected as PLL clock entry */ SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); } break; default: /* MSI used as system clock */ msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; SystemCoreClock = (32768 * (1 << (msirange + 1))); break; } /* Compute HCLK clock frequency --------------------------------------------*/ /* Get HCLK prescaler */ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; /* HCLK clock frequency */ SystemCoreClock >>= tmp; } /** * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash * settings. * @note This function should be called only once the RCC clock configuration * is reset to the default reset state (done in SystemInit() function). * @param None * @retval None */ static void SetSysClock(void) { __IO uint32_t StartUpCounter = 0, HSEStatus = 0; /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ /* Enable HSE */ RCC->CR |= ((uint32_t)RCC_CR_HSEON); /* Wait till HSE is ready and if Time out is reached exit */ do { HSEStatus = RCC->CR & RCC_CR_HSERDY; StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); if ((RCC->CR & RCC_CR_HSERDY) != RESET) { HSEStatus = (uint32_t)0x01; } else { HSEStatus = (uint32_t)0x00; } if (HSEStatus == (uint32_t)0x01) { /* Enable 64-bit access */ FLASH->ACR |= FLASH_ACR_ACC64; /* Enable Prefetch Buffer */ FLASH->ACR |= FLASH_ACR_PRFTEN; /* Flash 1 wait state */ FLASH->ACR |= FLASH_ACR_LATENCY; /* Power enable */ RCC->APB1ENR |= RCC_APB1ENR_PWREN; /* Select the Voltage Range 1 (1.8 V) */ PWR->CR = PWR_CR_VOS_0; /* Wait Until the Voltage Regulator is ready */ while((PWR->CSR & PWR_CSR_VOSF) != RESET) { } /* HCLK = SYSCLK /1*/ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; /* PCLK2 = HCLK /1*/ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; /* PCLK1 = HCLK /1*/ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; /* PLL configuration */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV)); RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3); /* Enable PLL */ RCC->CR |= RCC_CR_PLLON; /* Wait till PLL is ready */ while((RCC->CR & RCC_CR_PLLRDY) == 0) { } /* Select PLL as system clock source */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; /* Wait till PLL is used as system clock source */ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) { } } else { /* If HSE fails to start-up, the application will have wrong clock configuration. User can add here some code to deal with this error */ } } #ifdef DATA_IN_ExtSRAM /** * @brief Setup the external memory controller. * Called in SystemInit() function before jump to main. * This function configures the external SRAM mounted on STM32L152D_EVAL board * This SRAM will be used as program data memory (including heap and stack). * @param None * @retval None */ void SystemInit_ExtMemCtl(void) { /*-- GPIOs Configuration -----------------------------------------------------*/ /* +-------------------+--------------------+------------------+------------------+ + SRAM pins assignment + +-------------------+--------------------+------------------+------------------+ | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 | | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | | PD14 <-> FSMC_D0 | PE15 <-> FSMC_D12 |------------------+ | PD15 <-> FSMC_D1 |--------------------+ +-------------------+ */ /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ RCC->AHBENR = 0x000080D8; /* Connect PDx pins to FSMC Alternate function */ GPIOD->AFR[0] = 0x00CC00CC; GPIOD->AFR[1] = 0xCCCCCCCC; /* Configure PDx pins in Alternate function mode */ GPIOD->MODER = 0xAAAA0A0A; /* Configure PDx pins speed to 40 MHz */ GPIOD->OSPEEDR = 0xFFFF0F0F; /* Configure PDx pins Output type to push-pull */ GPIOD->OTYPER = 0x00000000; /* No pull-up, pull-down for PDx pins */ GPIOD->PUPDR = 0x00000000; /* Connect PEx pins to FSMC Alternate function */ GPIOE->AFR[0] = 0xC00000CC; GPIOE->AFR[1] = 0xCCCCCCCC; /* Configure PEx pins in Alternate function mode */ GPIOE->MODER = 0xAAAA800A; /* Configure PEx pins speed to 40 MHz */ GPIOE->OSPEEDR = 0xFFFFC00F; /* Configure PEx pins Output type to push-pull */ GPIOE->OTYPER = 0x00000000; /* No pull-up, pull-down for PEx pins */ GPIOE->PUPDR = 0x00000000; /* Connect PFx pins to FSMC Alternate function */ GPIOF->AFR[0] = 0x00CCCCCC; GPIOF->AFR[1] = 0xCCCC0000; /* Configure PFx pins in Alternate function mode */ GPIOF->MODER = 0xAA000AAA; /* Configure PFx pins speed to 40 MHz */ GPIOF->OSPEEDR = 0xFF000FFF; /* Configure PFx pins Output type to push-pull */ GPIOF->OTYPER = 0x00000000; /* No pull-up, pull-down for PFx pins */ GPIOF->PUPDR = 0x00000000; /* Connect PGx pins to FSMC Alternate function */ GPIOG->AFR[0] = 0x00CCCCCC; GPIOG->AFR[1] = 0x00000C00; /* Configure PGx pins in Alternate function mode */ GPIOG->MODER = 0x00200AAA; /* Configure PGx pins speed to 40 MHz */ GPIOG->OSPEEDR = 0x00300FFF; /* Configure PGx pins Output type to push-pull */ GPIOG->OTYPER = 0x00000000; /* No pull-up, pull-down for PGx pins */ GPIOG->PUPDR = 0x00000000; /*-- FSMC Configuration ------------------------------------------------------*/ /* Enable the FSMC interface clock */ RCC->AHBENR = 0x400080D8; /* Configure and enable Bank1_SRAM3 */ FSMC_Bank1->BTCR[4] = 0x00001011; FSMC_Bank1->BTCR[5] = 0x00000300; FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF; /* Bank1_SRAM3 is configured as follow: p.FSMC_AddressSetupTime = 0; p.FSMC_AddressHoldTime = 0; p.FSMC_DataSetupTime = 3; p.FSMC_BusTurnAroundDuration = 0; p.FSMC_CLKDivision = 0; p.FSMC_DataLatency = 0; p.FSMC_AccessMode = FSMC_AccessMode_A; FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3; FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM; FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE); */ } #endif /* DATA_IN_ExtSRAM */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/cmsis/system_stm32l1xx.h
New file @@ -0,0 +1,104 @@ /** ****************************************************************************** * @file system_stm32l1xx.h * @author MCD Application Team * @version V1.3.3 * @date 20-April-2015 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /** @addtogroup CMSIS * @{ */ /** @addtogroup stm32l1xx_system * @{ */ /** * @brief Define to prevent recursive inclusion */ #ifndef __SYSTEM_STM32L1XX_H #define __SYSTEM_STM32L1XX_H #ifdef __cplusplus extern "C" { #endif /** @addtogroup STM32L1xx_System_Includes * @{ */ /** * @} */ /** @addtogroup STM32L1xx_System_Exported_types * @{ */ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ /** * @} */ /** @addtogroup STM32L1xx_System_Exported_Constants * @{ */ /** * @} */ /** @addtogroup STM32L1xx_System_Exported_Macros * @{ */ /** * @} */ /** @addtogroup STM32L1xx_System_Exported_Functions * @{ */ extern void SystemInit(void); extern void SystemCoreClockUpdate(void); /** * @} */ #ifdef __cplusplus } #endif #endif /*__SYSTEM_STM32L1XX_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/keil_clean.bat
New file @@ -0,0 +1,19 @@ del *.d /s del *.o /s del *.bak /s del *.dep /s del *.htm /s del *.lnp /s del *.sct /s del *.map /s del *.crf /s del *.tra /s del *.axf /s del *.hex /s del *.plg /s del *.lst /s del *.__i /s del *.iex /s del *.txt /s del JLinkLog.txt /s
New file @@ -0,0 +1,57 @@ /**************************************************************************** * Copyright: (C)2018 Î人ÁèÔÆÎïÍøÖÇ¿ÆʵÑéÊÒ www.iot-yun.com * Author: GuoWenxue<guowenxue@gmail.com> QQ: 281143292 * Description: STM32L151C8T6 CubeMX ¿ª·¢°å LED¡¢´®¿Ú¡¢Systick µÈ²âÊÔ³ÌÐò ¿ª·¢°åÌÔ±¦¹ºÂòµØÖ·£º https://item.taobao.com/item.htm?spm=a1z09.2.0.0.6ff42e8dPmfuKR&id=551780894246&_u=41ifnbo379e * * ChangeLog: * °æ±¾ºÅ ÈÕÆÚ ×÷Õß ËµÃ÷ * V1.0.0 2018.11.04 GuoWenxue ·¢²¼¸Ã°æ±¾ ****************************************************************************/ #include <stdio.h> #include "stm32_led.h" #include "stm32_key.h" #include "stm32_usart.h" #include "stm32_systick.h" void blink_led(uint8_t which, uint32_t ms) { uint32_t start_time; start_time = jiffies; while( time_before(jiffies, start_time+ms) ) { turn_led(which, ON); msleep(100); turn_led(which, OFF); msleep(100); } } int main(void) { init_led_gpio(); init_systick(); init_keys_interrupt(); stm32_init_printf(USART_PORT1, 115200); printf("STM32L151C8T6A CubeMX Board Setup USART1 As Standard Output OK.\n"); printf("Blink test LED in 3000ms\n"); blink_led(LED1, 3000); printf("Wakeup Key Interrupt Detected start...\n"); while(1) { msleep(3000); turn_led(LED1, ON); msleep(150); turn_led(LED1, OFF); } } src/stm32L_bare/output/Empty.git
New file @@ -0,0 +1 @@ This empty file for git add this folder. src/stm32L_bare/stdlib/inc/misc.h
New file @@ -0,0 +1,202 @@ /** ****************************************************************************** * @file misc.h * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file contains all the functions prototypes for the miscellaneous * firmware library functions (add-on to CMSIS functions). ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __MISC_H #define __MISC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @addtogroup MISC * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief NVIC Init Structure definition */ typedef struct { uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. This parameter can be a value of @ref IRQn_Type (For the complete STM32 Devices IRQ Channels list, please refer to stm32l1xx.h file) */ uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel specified in NVIC_IRQChannel. This parameter can be a value between 0 and 15 as described in the table @ref NVIC_Priority_Table */ uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified in NVIC_IRQChannel. This parameter can be a value between 0 and 15 as described in the table @ref NVIC_Priority_Table */ FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel will be enabled or disabled. This parameter can be set either to ENABLE or DISABLE */ } NVIC_InitTypeDef; /** * @verbatim The table below gives the allowed values of the pre-emption priority and subpriority according to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function ============================================================================================================================ NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description ============================================================================================================================ NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority | | | 4 bits for subpriority ---------------------------------------------------------------------------------------------------------------------------- NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority | | | 3 bits for subpriority ---------------------------------------------------------------------------------------------------------------------------- NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority | | | 2 bits for subpriority ---------------------------------------------------------------------------------------------------------------------------- NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority | | | 1 bits for subpriority ---------------------------------------------------------------------------------------------------------------------------- NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority | | | 0 bits for subpriority ============================================================================================================================ @endverbatim */ /* Exported constants --------------------------------------------------------*/ /** @defgroup MISC_Exported_Constants * @{ */ /** @defgroup Vector_Table_Base * @{ */ #define NVIC_VectTab_RAM ((uint32_t)0x20000000) #define NVIC_VectTab_FLASH ((uint32_t)0x08000000) #define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ ((VECTTAB) == NVIC_VectTab_FLASH)) /** * @} */ /** @defgroup System_Low_Power * @{ */ #define NVIC_LP_SEVONPEND ((uint8_t)0x10) #define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) #define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) #define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ ((LP) == NVIC_LP_SLEEPDEEP) || \ ((LP) == NVIC_LP_SLEEPONEXIT)) /** * @} */ /** @defgroup Preemption_Priority_Group * @{ */ #define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */ #define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */ #define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */ #define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */ #define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */ #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ ((GROUP) == NVIC_PriorityGroup_1) || \ ((GROUP) == NVIC_PriorityGroup_2) || \ ((GROUP) == NVIC_PriorityGroup_3) || \ ((GROUP) == NVIC_PriorityGroup_4)) #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) #define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0005FFFF) /** * @} */ /** @defgroup SysTick_clock_source * @{ */ #define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) #define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); #ifdef __cplusplus } #endif #endif /* __MISC_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/inc/stm32l1xx_adc.h
New file @@ -0,0 +1,650 @@ /** ****************************************************************************** * @file stm32l1xx_adc.h * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file contains all the functions prototypes for the ADC firmware * library. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L1xx_ADC_H #define __STM32L1xx_ADC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @addtogroup ADC * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief ADC Init structure definition */ typedef struct { uint32_t ADC_Resolution; /*!< Selects the resolution of the conversion. This parameter can be a value of @ref ADC_Resolution */ FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in Scan (multichannel) or Single (one channel) mode. This parameter can be set to ENABLE or DISABLE */ FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in Continuous or Single mode. This parameter can be set to ENABLE or DISABLE. */ uint32_t ADC_ExternalTrigConvEdge; /*!< Selects the external trigger Edge and enables the trigger of a regular group. This parameter can be a value of @ref ADC_external_trigger_edge_for_regular_channels_conversion */ uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog to digital conversion of regular channels. This parameter can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right. This parameter can be a value of @ref ADC_data_align */ uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions that will be done using the sequencer for regular channel group. This parameter must range from 1 to 27. */ }ADC_InitTypeDef; typedef struct { uint32_t ADC_Prescaler; /*!< Selects the ADC prescaler. This parameter can be a value of @ref ADC_Prescaler */ }ADC_CommonInitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup ADC_Exported_Constants * @{ */ #define IS_ADC_ALL_PERIPH(PERIPH) ((PERIPH) == ADC1) #define IS_ADC_DMA_PERIPH(PERIPH) ((PERIPH) == ADC1) /** @defgroup ADC_Power_down_during_Idle_and_or_Delay_phase * @{ */ #define ADC_PowerDown_Delay ((uint32_t)0x00010000) #define ADC_PowerDown_Idle ((uint32_t)0x00020000) #define ADC_PowerDown_Idle_Delay ((uint32_t)0x00030000) #define IS_ADC_POWER_DOWN(DWON) (((DWON) == ADC_PowerDown_Delay) || \ ((DWON) == ADC_PowerDown_Idle) || \ ((DWON) == ADC_PowerDown_Idle_Delay)) /** * @} */ /** @defgroup ADC_Prescaler * @{ */ #define ADC_Prescaler_Div1 ((uint32_t)0x00000000) #define ADC_Prescaler_Div2 ((uint32_t)0x00010000) #define ADC_Prescaler_Div4 ((uint32_t)0x00020000) #define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div1) || \ ((PRESCALER) == ADC_Prescaler_Div2) || \ ((PRESCALER) == ADC_Prescaler_Div4)) /** * @} */ /** @defgroup ADC_Resolution * @{ */ #define ADC_Resolution_12b ((uint32_t)0x00000000) #define ADC_Resolution_10b ((uint32_t)0x01000000) #define ADC_Resolution_8b ((uint32_t)0x02000000) #define ADC_Resolution_6b ((uint32_t)0x03000000) #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \ ((RESOLUTION) == ADC_Resolution_10b) || \ ((RESOLUTION) == ADC_Resolution_8b) || \ ((RESOLUTION) == ADC_Resolution_6b)) /** * @} */ /** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion * @{ */ #define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000) #define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000) #define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000) #define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000) #define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \ ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \ ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \ ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling)) /** * @} */ /** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion * @{ */ /* TIM2 */ #define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x02000000) #define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000) #define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000) /* TIM3 */ #define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000) #define ADC_ExternalTrigConv_T3_CC3 ((uint32_t)0x08000000) #define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x04000000) /* TIM4 */ #define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x05000000) #define ADC_ExternalTrigConv_T4_TRGO ((uint32_t)0x09000000) /* TIM6 */ #define ADC_ExternalTrigConv_T6_TRGO ((uint32_t)0x0A000000) /* TIM9 */ #define ADC_ExternalTrigConv_T9_CC2 ((uint32_t)0x00000000) #define ADC_ExternalTrigConv_T9_TRGO ((uint32_t)0x01000000) /* EXTI */ #define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000) #define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T9_CC2) || \ ((REGTRIG) == ADC_ExternalTrigConv_T9_TRGO) || \ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \ ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ ((REGTRIG) == ADC_ExternalTrigConv_T3_CC3) || \ ((REGTRIG) == ADC_ExternalTrigConv_T4_TRGO) || \ ((REGTRIG) == ADC_ExternalTrigConv_T6_TRGO) || \ ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11)) /** * @} */ /** @defgroup ADC_data_align * @{ */ #define ADC_DataAlign_Right ((uint32_t)0x00000000) #define ADC_DataAlign_Left ((uint32_t)0x00000800) #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ ((ALIGN) == ADC_DataAlign_Left)) /** * @} */ /** @defgroup ADC_channels * @{ */ /* ADC Bank A Channels -------------------------------------------------------*/ #define ADC_Channel_0 ((uint8_t)0x00) #define ADC_Channel_1 ((uint8_t)0x01) #define ADC_Channel_2 ((uint8_t)0x02) #define ADC_Channel_3 ((uint8_t)0x03) #define ADC_Channel_6 ((uint8_t)0x06) #define ADC_Channel_7 ((uint8_t)0x07) #define ADC_Channel_8 ((uint8_t)0x08) #define ADC_Channel_9 ((uint8_t)0x09) #define ADC_Channel_10 ((uint8_t)0x0A) #define ADC_Channel_11 ((uint8_t)0x0B) #define ADC_Channel_12 ((uint8_t)0x0C) /* ADC Bank B Channels -------------------------------------------------------*/ #define ADC_Channel_0b ADC_Channel_0 #define ADC_Channel_1b ADC_Channel_1 #define ADC_Channel_2b ADC_Channel_2 #define ADC_Channel_3b ADC_Channel_3 #define ADC_Channel_6b ADC_Channel_6 #define ADC_Channel_7b ADC_Channel_7 #define ADC_Channel_8b ADC_Channel_8 #define ADC_Channel_9b ADC_Channel_9 #define ADC_Channel_10b ADC_Channel_10 #define ADC_Channel_11b ADC_Channel_11 #define ADC_Channel_12b ADC_Channel_12 /* ADC Common Channels (ADC Bank A and B) ------------------------------------*/ #define ADC_Channel_4 ((uint8_t)0x04) #define ADC_Channel_5 ((uint8_t)0x05) #define ADC_Channel_13 ((uint8_t)0x0D) #define ADC_Channel_14 ((uint8_t)0x0E) #define ADC_Channel_15 ((uint8_t)0x0F) #define ADC_Channel_16 ((uint8_t)0x10) #define ADC_Channel_17 ((uint8_t)0x11) #define ADC_Channel_18 ((uint8_t)0x12) #define ADC_Channel_19 ((uint8_t)0x13) #define ADC_Channel_20 ((uint8_t)0x14) #define ADC_Channel_21 ((uint8_t)0x15) #define ADC_Channel_22 ((uint8_t)0x16) #define ADC_Channel_23 ((uint8_t)0x17) #define ADC_Channel_24 ((uint8_t)0x18) #define ADC_Channel_25 ((uint8_t)0x19) #define ADC_Channel_27 ((uint8_t)0x1B) #define ADC_Channel_28 ((uint8_t)0x1C) #define ADC_Channel_29 ((uint8_t)0x1D) #define ADC_Channel_30 ((uint8_t)0x1E) #define ADC_Channel_31 ((uint8_t)0x1F) #define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) #define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \ ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \ ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \ ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \ ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \ ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \ ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \ ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \ ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17) || \ ((CHANNEL) == ADC_Channel_18) || ((CHANNEL) == ADC_Channel_19) || \ ((CHANNEL) == ADC_Channel_20) || ((CHANNEL) == ADC_Channel_21) || \ ((CHANNEL) == ADC_Channel_22) || ((CHANNEL) == ADC_Channel_23) || \ ((CHANNEL) == ADC_Channel_24) || ((CHANNEL) == ADC_Channel_25) || \ ((CHANNEL) == ADC_Channel_27) || ((CHANNEL) == ADC_Channel_28) || \ ((CHANNEL) == ADC_Channel_29) || ((CHANNEL) == ADC_Channel_30) || \ ((CHANNEL) == ADC_Channel_31)) /** * @} */ /** @defgroup ADC_sampling_times * @{ */ #define ADC_SampleTime_4Cycles ((uint8_t)0x00) #define ADC_SampleTime_9Cycles ((uint8_t)0x01) #define ADC_SampleTime_16Cycles ((uint8_t)0x02) #define ADC_SampleTime_24Cycles ((uint8_t)0x03) #define ADC_SampleTime_48Cycles ((uint8_t)0x04) #define ADC_SampleTime_96Cycles ((uint8_t)0x05) #define ADC_SampleTime_192Cycles ((uint8_t)0x06) #define ADC_SampleTime_384Cycles ((uint8_t)0x07) #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_4Cycles) || \ ((TIME) == ADC_SampleTime_9Cycles) || \ ((TIME) == ADC_SampleTime_16Cycles) || \ ((TIME) == ADC_SampleTime_24Cycles) || \ ((TIME) == ADC_SampleTime_48Cycles) || \ ((TIME) == ADC_SampleTime_96Cycles) || \ ((TIME) == ADC_SampleTime_192Cycles) || \ ((TIME) == ADC_SampleTime_384Cycles)) /** * @} */ /** @defgroup ADC_Delay_length * @{ */ #define ADC_DelayLength_None ((uint8_t)0x00) #define ADC_DelayLength_Freeze ((uint8_t)0x10) #define ADC_DelayLength_7Cycles ((uint8_t)0x20) #define ADC_DelayLength_15Cycles ((uint8_t)0x30) #define ADC_DelayLength_31Cycles ((uint8_t)0x40) #define ADC_DelayLength_63Cycles ((uint8_t)0x50) #define ADC_DelayLength_127Cycles ((uint8_t)0x60) #define ADC_DelayLength_255Cycles ((uint8_t)0x70) #define IS_ADC_DELAY_LENGTH(LENGTH) (((LENGTH) == ADC_DelayLength_None) || \ ((LENGTH) == ADC_DelayLength_Freeze) || \ ((LENGTH) == ADC_DelayLength_7Cycles) || \ ((LENGTH) == ADC_DelayLength_15Cycles) || \ ((LENGTH) == ADC_DelayLength_31Cycles) || \ ((LENGTH) == ADC_DelayLength_63Cycles) || \ ((LENGTH) == ADC_DelayLength_127Cycles) || \ ((LENGTH) == ADC_DelayLength_255Cycles)) /** * @} */ /** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion * @{ */ #define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000) #define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000) #define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000) #define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000) #define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \ ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \ ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \ ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling)) /** * @} */ /** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion * @{ */ /* TIM2 */ #define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00020000) #define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00030000) /* TIM3 */ #define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00040000) /* TIM4 */ #define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00050000) #define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000) #define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000) #define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000) /* TIM7 */ #define ADC_ExternalTrigInjecConv_T7_TRGO ((uint32_t)0x000A0000) /* TIM9 */ #define ADC_ExternalTrigInjecConv_T9_CC1 ((uint32_t)0x00000000) #define ADC_ExternalTrigInjecConv_T9_TRGO ((uint32_t)0x00010000) /* TIM10 */ #define ADC_ExternalTrigInjecConv_T10_CC1 ((uint32_t)0x00090000) /* EXTI */ #define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000) #define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T9_CC1) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T9_TRGO) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T10_CC1) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T7_TRGO) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15)) /** * @} */ /** @defgroup ADC_injected_channel_selection * @{ */ #define ADC_InjectedChannel_1 ((uint8_t)0x18) #define ADC_InjectedChannel_2 ((uint8_t)0x1C) #define ADC_InjectedChannel_3 ((uint8_t)0x20) #define ADC_InjectedChannel_4 ((uint8_t)0x24) #define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ ((CHANNEL) == ADC_InjectedChannel_2) || \ ((CHANNEL) == ADC_InjectedChannel_3) || \ ((CHANNEL) == ADC_InjectedChannel_4)) /** * @} */ /** @defgroup ADC_analog_watchdog_selection * @{ */ #define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) #define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) #define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) #define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) #define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) #define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) #define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) #define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ ((WATCHDOG) == ADC_AnalogWatchdog_None)) /** * @} */ /** @defgroup ADC_interrupts_definition * @{ */ #define ADC_IT_AWD ((uint16_t)0x0106) #define ADC_IT_EOC ((uint16_t)0x0205) #define ADC_IT_JEOC ((uint16_t)0x0407) #define ADC_IT_OVR ((uint16_t)0x201A) #define IS_ADC_IT(IT) (((IT) == ADC_IT_AWD) || ((IT) == ADC_IT_EOC) || \ ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) /** * @} */ /** @defgroup ADC_flags_definition * @{ */ #define ADC_FLAG_AWD ((uint16_t)0x0001) #define ADC_FLAG_EOC ((uint16_t)0x0002) #define ADC_FLAG_JEOC ((uint16_t)0x0004) #define ADC_FLAG_JSTRT ((uint16_t)0x0008) #define ADC_FLAG_STRT ((uint16_t)0x0010) #define ADC_FLAG_OVR ((uint16_t)0x0020) #define ADC_FLAG_ADONS ((uint16_t)0x0040) #define ADC_FLAG_RCNR ((uint16_t)0x0100) #define ADC_FLAG_JCNR ((uint16_t)0x0200) #define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFC0) == 0x00) && ((FLAG) != 0x00)) #define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \ ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \ ((FLAG) == ADC_FLAG_STRT) || ((FLAG)== ADC_FLAG_OVR) || \ ((FLAG) == ADC_FLAG_ADONS) || ((FLAG)== ADC_FLAG_RCNR) || \ ((FLAG) == ADC_FLAG_JCNR)) /** * @} */ /** @defgroup ADC_thresholds * @{ */ #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) /** * @} */ /** @defgroup ADC_injected_offset * @{ */ #define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) /** * @} */ /** @defgroup ADC_injected_length * @{ */ #define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) /** * @} */ /** @defgroup ADC_injected_rank * @{ */ #define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) /** * @} */ /** @defgroup ADC_regular_length * @{ */ #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 28)) /** * @} */ /** @defgroup ADC_regular_rank * @{ */ #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 1) && ((RANK) <= 28)) /** * @} */ /** @defgroup ADC_regular_discontinuous_mode_number * @{ */ #define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) /** * @} */ /** @defgroup ADC_Bank_Selection * @{ */ #define ADC_Bank_A ((uint8_t)0x00) #define ADC_Bank_B ((uint8_t)0x01) #define IS_ADC_BANK(BANK) (((BANK) == ADC_Bank_A) || ((BANK) == ADC_Bank_B)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ /* Function used to set the ADC configuration to the default reset state *****/ void ADC_DeInit(ADC_TypeDef* ADCx); /* Initialization and Configuration functions *********************************/ void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct); void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct); void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); void ADC_BankSelection(ADC_TypeDef* ADCx, uint8_t ADC_Bank); /* Power saving functions *****************************************************/ void ADC_PowerDownCmd(ADC_TypeDef* ADCx, uint32_t ADC_PowerDown, FunctionalState NewState); void ADC_DelaySelectionConfig(ADC_TypeDef* ADCx, uint8_t ADC_DelayLength); /* Analog Watchdog configuration functions ************************************/ void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold); void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); /* Temperature Sensor & Vrefint (Voltage Reference internal) management function */ void ADC_TempSensorVrefintCmd(FunctionalState NewState); /* Regular Channels Configuration functions ***********************************/ void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); void ADC_SoftwareStartConv(ADC_TypeDef* ADCx); FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState); void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); /* Regular Channels DMA Configuration functions *******************************/ void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState); /* Injected channels Configuration functions **********************************/ void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge); void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx); FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); /* Interrupts and flags management functions **********************************/ void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint16_t ADC_FLAG); void ADC_ClearFlag(ADC_TypeDef* ADCx, uint16_t ADC_FLAG); ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); #ifdef __cplusplus } #endif #endif /*__STM32L1xx_ADC_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/inc/stm32l1xx_aes.h
New file @@ -0,0 +1,236 @@ /** ****************************************************************************** * @file stm32l1xx_aes.h * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file contains all the functions prototypes for the AES firmware * library. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L1xx_AES_H #define __STM32L1xx_AES_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @addtogroup AES * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief AES Init structure definition */ typedef struct { uint32_t AES_Operation; /*!< Specifies the AES mode of operation. This parameter can be a value of @ref AES_possible_Operation_modes */ uint32_t AES_Chaining; /*!< Specifies the AES Chaining modes: ECB, CBC or CTR. This parameter can be a value of @ref AES_possible_chaining_modes */ uint32_t AES_DataType; /*!< Specifies the AES data swapping: 32-bit, 16-bit, 8-bit or 1-bit. This parameter can be a value of @ref AES_Data_Types */ }AES_InitTypeDef; /** * @brief AES Key(s) structure definition */ typedef struct { uint32_t AES_Key0; /*!< Key[31:0] */ uint32_t AES_Key1; /*!< Key[63:32] */ uint32_t AES_Key2; /*!< Key[95:64] */ uint32_t AES_Key3; /*!< Key[127:96] */ }AES_KeyInitTypeDef; /** * @brief AES Initialization Vectors (IV) structure definition */ typedef struct { uint32_t AES_IV0; /*!< Init Vector IV[31:0] */ uint32_t AES_IV1; /*!< Init Vector IV[63:32] */ uint32_t AES_IV2; /*!< Init Vector IV[95:64] */ uint32_t AES_IV3; /*!< Init Vector IV[127:96] */ }AES_IVInitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup AES_Exported_Constants * @{ */ /** @defgroup AES_possible_Operation_modes * @{ */ #define AES_Operation_Encryp ((uint32_t)0x00000000) /*!< AES in Encryption mode */ #define AES_Operation_KeyDeriv AES_CR_MODE_0 /*!< AES in Key Derivation mode */ #define AES_Operation_Decryp AES_CR_MODE_1 /*!< AES in Decryption mode */ #define AES_Operation_KeyDerivAndDecryp AES_CR_MODE /*!< AES in Key Derivation and Decryption mode */ #define IS_AES_MODE(OPERATION) (((OPERATION) == AES_Operation_Encryp) || \ ((OPERATION) == AES_Operation_KeyDeriv) || \ ((OPERATION) == AES_Operation_Decryp) || \ ((OPERATION) == AES_Operation_KeyDerivAndDecryp)) /** * @} */ /** @defgroup AES_possible_chaining_modes * @{ */ #define AES_Chaining_ECB ((uint32_t)0x00000000) /*!< AES in ECB chaining mode */ #define AES_Chaining_CBC AES_CR_CHMOD_0 /*!< AES in CBC chaining mode */ #define AES_Chaining_CTR AES_CR_CHMOD_1 /*!< AES in CTR chaining mode */ #define IS_AES_CHAINING(CHAINING) (((CHAINING) == AES_Chaining_ECB) || \ ((CHAINING) == AES_Chaining_CBC) || \ ((CHAINING) == AES_Chaining_CTR)) /** * @} */ /** @defgroup AES_Data_Types * @{ */ #define AES_DataType_32b ((uint32_t)0x00000000) /*!< 32-bit data. No swapping */ #define AES_DataType_16b AES_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */ #define AES_DataType_8b AES_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */ #define AES_DataType_1b AES_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */ #define IS_AES_DATATYPE(DATATYPE) (((DATATYPE) == AES_DataType_32b) || \ ((DATATYPE) == AES_DataType_16b)|| \ ((DATATYPE) == AES_DataType_8b) || \ ((DATATYPE) == AES_DataType_1b)) /** * @} */ /** @defgroup AES_Flags * @{ */ #define AES_FLAG_CCF AES_SR_CCF /*!< Computation Complete Flag */ #define AES_FLAG_RDERR AES_SR_RDERR /*!< Read Error Flag */ #define AES_FLAG_WRERR AES_SR_WRERR /*!< Write Error Flag */ #define IS_AES_FLAG(FLAG) (((FLAG) == AES_FLAG_CCF) || \ ((FLAG) == AES_FLAG_RDERR) || \ ((FLAG) == AES_FLAG_WRERR)) /** * @} */ /** @defgroup AES_Interrupts * @{ */ #define AES_IT_CC AES_CR_CCIE /*!< Computation Complete interrupt */ #define AES_IT_ERR AES_CR_ERRIE /*!< Error interrupt */ #define IS_AES_IT(IT) ((((IT) & (uint32_t)0xFFFFF9FF) == 0x00) && ((IT) != 0x00)) #define IS_AES_GET_IT(IT) (((IT) == AES_IT_CC) || ((IT) == AES_IT_ERR)) /** * @} */ /** @defgroup AES_DMA_Transfer_modes * @{ */ #define AES_DMATransfer_In AES_CR_DMAINEN /*!< DMA requests enabled for input transfer phase */ #define AES_DMATransfer_Out AES_CR_DMAOUTEN /*!< DMA requests enabled for input transfer phase */ #define AES_DMATransfer_InOut (AES_CR_DMAINEN | AES_CR_DMAOUTEN) /*!< DMA requests enabled for both input and output phases */ #define IS_AES_DMA_TRANSFER(TRANSFER) (((TRANSFER) == AES_DMATransfer_In) || \ ((TRANSFER) == AES_DMATransfer_Out) || \ ((TRANSFER) == AES_DMATransfer_InOut)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ /* Initialization and configuration functions *********************************/ void AES_DeInit(void); void AES_Init(AES_InitTypeDef* AES_InitStruct); void AES_KeyInit(AES_KeyInitTypeDef* AES_KeyInitStruct); void AES_IVInit(AES_IVInitTypeDef* AES_IVInitStruct); void AES_Cmd(FunctionalState NewState); /* Structures initialization functions ****************************************/ void AES_StructInit(AES_InitTypeDef* AES_InitStruct); void AES_KeyStructInit(AES_KeyInitTypeDef* AES_KeyInitStruct); void AES_IVStructInit(AES_IVInitTypeDef* AES_IVInitStruct); /* AES Read and Write functions **********************************************/ void AES_WriteSubData(uint32_t Data); uint32_t AES_ReadSubData(void); void AES_ReadKey(AES_KeyInitTypeDef* AES_KeyInitStruct); void AES_ReadIV(AES_IVInitTypeDef* AES_IVInitStruct); /* DMA transfers management function ******************************************/ void AES_DMAConfig(uint32_t AES_DMATransfer, FunctionalState NewState); /* Interrupts and flags management functions **********************************/ void AES_ITConfig(uint32_t AES_IT, FunctionalState NewState); FlagStatus AES_GetFlagStatus(uint32_t AES_FLAG); void AES_ClearFlag(uint32_t AES_FLAG); ITStatus AES_GetITStatus(uint32_t AES_IT); void AES_ClearITPendingBit(uint32_t AES_IT); /* High Level AES functions **************************************************/ ErrorStatus AES_ECB_Encrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output); ErrorStatus AES_ECB_Decrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output); ErrorStatus AES_CBC_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output); ErrorStatus AES_CBC_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output); ErrorStatus AES_CTR_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output); ErrorStatus AES_CTR_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output); #ifdef __cplusplus } #endif #endif /*__STM32L1xx_AES_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/inc/stm32l1xx_comp.h
New file @@ -0,0 +1,187 @@ /** ****************************************************************************** * @file stm32l1xx_comp.h * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file contains all the functions prototypes for the COMP firmware * library. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L1xx_COMP_H #define __STM32L1xx_COMP_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @addtogroup COMP * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief COMP Init structure definition */ typedef struct { uint32_t COMP_Speed; /*!< Defines the speed of comparator 2. This parameter can be a value of @ref COMP_Speed */ uint32_t COMP_InvertingInput; /*!< Selects the inverting input of the comparator 2. This parameter can be a value of @ref COMP_InvertingInput */ uint32_t COMP_OutputSelect; /*!< Selects the output redirection of the comparator 2. This parameter can be a value of @ref COMP_OutputSelect */ }COMP_InitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup COMP_Exported_Constants * @{ */ #define COMP_OutputLevel_High ((uint32_t)0x00000001) #define COMP_OutputLevel_Low ((uint32_t)0x00000000) /** @defgroup COMP_Selection * @{ */ #define COMP_Selection_COMP1 ((uint32_t)0x00000001) #define COMP_Selection_COMP2 ((uint32_t)0x00000002) #define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \ ((PERIPH) == COMP_Selection_COMP2)) /** * @} */ /** @defgroup COMP_InvertingInput * @{ */ #define COMP_InvertingInput_None ((uint32_t)0x00000000) /* COMP2 is disabled when this parameter is selected */ #define COMP_InvertingInput_IO ((uint32_t)0x00040000) #define COMP_InvertingInput_VREFINT ((uint32_t)0x00080000) #define COMP_InvertingInput_3_4VREFINT ((uint32_t)0x000C0000) #define COMP_InvertingInput_1_2VREFINT ((uint32_t)0x00100000) #define COMP_InvertingInput_1_4VREFINT ((uint32_t)0x00140000) #define COMP_InvertingInput_DAC1 ((uint32_t)0x00180000) #define COMP_InvertingInput_DAC2 ((uint32_t)0x001C0000) #define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_None) || \ ((INPUT) == COMP_InvertingInput_IO) || \ ((INPUT) == COMP_InvertingInput_VREFINT) || \ ((INPUT) == COMP_InvertingInput_3_4VREFINT) || \ ((INPUT) == COMP_InvertingInput_1_2VREFINT) || \ ((INPUT) == COMP_InvertingInput_1_4VREFINT) || \ ((INPUT) == COMP_InvertingInput_DAC1) || \ ((INPUT) == COMP_InvertingInput_DAC2)) /** * @} */ /** @defgroup COMP_OutputSelect * @{ */ #define COMP_OutputSelect_TIM2IC4 ((uint32_t)0x00000000) #define COMP_OutputSelect_TIM2OCREFCLR ((uint32_t)0x00200000) #define COMP_OutputSelect_TIM3IC4 ((uint32_t)0x00400000) #define COMP_OutputSelect_TIM3OCREFCLR ((uint32_t)0x00600000) #define COMP_OutputSelect_TIM4IC4 ((uint32_t)0x00800000) #define COMP_OutputSelect_TIM4OCREFCLR ((uint32_t)0x00A00000) #define COMP_OutputSelect_TIM10IC1 ((uint32_t)0x00C00000) #define COMP_OutputSelect_None ((uint32_t)0x00E00000) #define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OutputSelect_TIM2IC4) || \ ((OUTPUT) == COMP_OutputSelect_TIM2OCREFCLR) || \ ((OUTPUT) == COMP_OutputSelect_TIM3IC4) || \ ((OUTPUT) == COMP_OutputSelect_TIM3OCREFCLR) || \ ((OUTPUT) == COMP_OutputSelect_TIM4IC4) || \ ((OUTPUT) == COMP_OutputSelect_TIM4OCREFCLR) || \ ((OUTPUT) == COMP_OutputSelect_TIM10IC1) || \ ((OUTPUT) == COMP_OutputSelect_None)) /** * @} */ /** @defgroup COMP_Speed * @{ */ #define COMP_Speed_Slow ((uint32_t)0x00000000) #define COMP_Speed_Fast ((uint32_t)0x00001000) #define IS_COMP_SPEED(SPEED) (((SPEED) == COMP_Speed_Slow) || \ ((SPEED) == COMP_Speed_Fast)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ /* Function used to set the COMP configuration to the default reset state ****/ void COMP_DeInit(void); /* Initialization and Configuration functions *********************************/ void COMP_Init(COMP_InitTypeDef* COMP_InitStruct); void COMP_Cmd(FunctionalState NewState); uint8_t COMP_GetOutputLevel(uint32_t COMP_Selection); void COMP_SW1SwitchConfig(FunctionalState NewState); /* Window mode control function ***********************************************/ void COMP_WindowCmd(FunctionalState NewState); /* Internal Reference Voltage (VREFINT) output function ***********************/ void COMP_VrefintOutputCmd(FunctionalState NewState); #ifdef __cplusplus } #endif #endif /*__STM32L1xx_COMP_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/inc/stm32l1xx_crc.h
New file @@ -0,0 +1,83 @@ /** ****************************************************************************** * @file stm32l1xx_crc.h * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file contains all the functions prototypes for the CRC firmware * library. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L1xx_CRC_H #define __STM32L1xx_CRC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @addtogroup CRC * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup CRC_Exported_Constants * @{ */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ void CRC_ResetDR(void); uint32_t CRC_CalcCRC(uint32_t Data); uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); uint32_t CRC_GetCRC(void); void CRC_SetIDRegister(uint8_t IDValue); uint8_t CRC_GetIDRegister(void); #ifdef __cplusplus } #endif #endif /* __STM32L1xx_CRC_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/inc/stm32l1xx_dac.h
New file @@ -0,0 +1,305 @@ /** ****************************************************************************** * @file stm32l1xx_dac.h * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file contains all the functions prototypes for the DAC firmware * library. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L1xx_DAC_H #define __STM32L1xx_DAC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @addtogroup DAC * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief DAC Init structure definition */ typedef struct { uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. This parameter can be a value of @ref DAC_trigger_selection */ uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves are generated, or whether no wave is generated. This parameter can be a value of @ref DAC_wave_generation */ uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or the maximum amplitude triangle generation for the DAC channel. This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. This parameter can be a value of @ref DAC_output_buffer */ }DAC_InitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup DAC_Exported_Constants * @{ */ /** @defgroup DAC_trigger_selection * @{ */ #define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */ #define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ #define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ #define DAC_Trigger_T9_TRGO ((uint32_t)0x0000001C) /*!< TIM9 TRGO selected as external conversion trigger for DAC channel */ #define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ #define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ #define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ #define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ ((TRIGGER) == DAC_Trigger_T9_TRGO) || \ ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ ((TRIGGER) == DAC_Trigger_Software)) /** * @} */ /** @defgroup DAC_wave_generation * @{ */ #define DAC_WaveGeneration_None ((uint32_t)0x00000000) #define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) #define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) #define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ ((WAVE) == DAC_WaveGeneration_Noise) || \ ((WAVE) == DAC_WaveGeneration_Triangle)) /** * @} */ /** @defgroup DAC_lfsrunmask_triangleamplitude * @{ */ #define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ #define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ #define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ #define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ #define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ #define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ #define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ #define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ #define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ #define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ #define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ #define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ #define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ #define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ #define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ ((VALUE) == DAC_TriangleAmplitude_1) || \ ((VALUE) == DAC_TriangleAmplitude_3) || \ ((VALUE) == DAC_TriangleAmplitude_7) || \ ((VALUE) == DAC_TriangleAmplitude_15) || \ ((VALUE) == DAC_TriangleAmplitude_31) || \ ((VALUE) == DAC_TriangleAmplitude_63) || \ ((VALUE) == DAC_TriangleAmplitude_127) || \ ((VALUE) == DAC_TriangleAmplitude_255) || \ ((VALUE) == DAC_TriangleAmplitude_511) || \ ((VALUE) == DAC_TriangleAmplitude_1023) || \ ((VALUE) == DAC_TriangleAmplitude_2047) || \ ((VALUE) == DAC_TriangleAmplitude_4095)) /** * @} */ /** @defgroup DAC_output_buffer * @{ */ #define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) #define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ ((STATE) == DAC_OutputBuffer_Disable)) /** * @} */ /** @defgroup DAC_Channel_selection * @{ */ #define DAC_Channel_1 ((uint32_t)0x00000000) #define DAC_Channel_2 ((uint32_t)0x00000010) #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ ((CHANNEL) == DAC_Channel_2)) /** * @} */ /** @defgroup DAC_data_alignment * @{ */ #define DAC_Align_12b_R ((uint32_t)0x00000000) #define DAC_Align_12b_L ((uint32_t)0x00000004) #define DAC_Align_8b_R ((uint32_t)0x00000008) #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ ((ALIGN) == DAC_Align_12b_L) || \ ((ALIGN) == DAC_Align_8b_R)) /** * @} */ /** @defgroup DAC_wave_generation * @{ */ #define DAC_Wave_Noise ((uint32_t)0x00000040) #define DAC_Wave_Triangle ((uint32_t)0x00000080) #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ ((WAVE) == DAC_Wave_Triangle)) /** * @} */ /** @defgroup DAC_data * @{ */ #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) /** * @} */ /** @defgroup DAC_interrupts_definition * @{ */ #define DAC_IT_DMAUDR ((uint32_t)0x00002000) #define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) /** * @} */ /** @defgroup DAC_flags_definition * @{ */ #define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) #define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ /* Function used to set the DAC configuration to the default reset state *****/ void DAC_DeInit(void); /* DAC channels configuration: trigger, output buffer, data format functions */ void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); /* DMA management functions ***************************************************/ void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); /* Interrupts and flags management functions **********************************/ void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); #ifdef __cplusplus } #endif #endif /*__STM32L1xx_DAC_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/inc/stm32l1xx_dbgmcu.h
New file @@ -0,0 +1,105 @@ /** ****************************************************************************** * @file stm32l1xx_dbgmcu.h * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file contains all the functions prototypes for the DBGMCU * firmware library. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L1xx_DBGMCU_H #define __STM32L1xx_DBGMCU_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @addtogroup DBGMCU * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup DBGMCU_Exported_Constants * @{ */ #define DBGMCU_SLEEP ((uint32_t)0x00000001) #define DBGMCU_STOP ((uint32_t)0x00000002) #define DBGMCU_STANDBY ((uint32_t)0x00000004) #define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00)) #define DBGMCU_TIM2_STOP ((uint32_t)0x00000001) #define DBGMCU_TIM3_STOP ((uint32_t)0x00000002) #define DBGMCU_TIM4_STOP ((uint32_t)0x00000004) #define DBGMCU_TIM5_STOP ((uint32_t)0x00000008) #define DBGMCU_TIM6_STOP ((uint32_t)0x00000010) #define DBGMCU_TIM7_STOP ((uint32_t)0x00000020) #define DBGMCU_RTC_STOP ((uint32_t)0x00000400) #define DBGMCU_WWDG_STOP ((uint32_t)0x00000800) #define DBGMCU_IWDG_STOP ((uint32_t)0x00001000) #define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) #define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) #define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFF9FE3C0) == 0x00) && ((PERIPH) != 0x00)) #define DBGMCU_TIM9_STOP ((uint32_t)0x00000004) #define DBGMCU_TIM10_STOP ((uint32_t)0x00000008) #define DBGMCU_TIM11_STOP ((uint32_t)0x00000010) #define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFE3) == 0x00) && ((PERIPH) != 0x00)) /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ uint32_t DBGMCU_GetREVID(void); uint32_t DBGMCU_GetDEVID(void); void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); #ifdef __cplusplus } #endif #endif /* __STM32L1xx_DBGMCU_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/inc/stm32l1xx_dma.h
New file @@ -0,0 +1,435 @@ /** ****************************************************************************** * @file stm32l1xx_dma.h * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file contains all the functions prototypes for the DMA firmware * library. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L1xx_DMA_H #define __STM32L1xx_DMA_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @addtogroup DMA * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief DMA Init structure definition */ typedef struct { uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */ uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination. This parameter can be a value of @ref DMA_data_transfer_direction */ uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. The data unit is equal to the configuration set in DMA_PeripheralDataSize or DMA_MemoryDataSize members depending in the transfer direction. */ uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not. This parameter can be a value of @ref DMA_peripheral_incremented_mode */ uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. This parameter can be a value of @ref DMA_memory_incremented_mode */ uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. This parameter can be a value of @ref DMA_peripheral_data_size */ uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. This parameter can be a value of @ref DMA_memory_data_size */ uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx. This parameter can be a value of @ref DMA_circular_normal_mode @note: The circular buffer mode cannot be used if the memory-to-memory data transfer is configured on the selected Channel */ uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx. This parameter can be a value of @ref DMA_priority_level */ uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer. This parameter can be a value of @ref DMA_memory_to_memory */ }DMA_InitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup DMA_Exported_Constants * @{ */ #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \ ((PERIPH) == DMA1_Channel2) || \ ((PERIPH) == DMA1_Channel3) || \ ((PERIPH) == DMA1_Channel4) || \ ((PERIPH) == DMA1_Channel5) || \ ((PERIPH) == DMA1_Channel6) || \ ((PERIPH) == DMA1_Channel7) || \ ((PERIPH) == DMA2_Channel1) || \ ((PERIPH) == DMA2_Channel2) || \ ((PERIPH) == DMA2_Channel3) || \ ((PERIPH) == DMA2_Channel4) || \ ((PERIPH) == DMA2_Channel5)) /** @defgroup DMA_data_transfer_direction * @{ */ #define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) #define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) #define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \ ((DIR) == DMA_DIR_PeripheralSRC)) /** * @} */ /** @defgroup DMA_peripheral_incremented_mode * @{ */ #define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ ((STATE) == DMA_PeripheralInc_Disable)) /** * @} */ /** @defgroup DMA_memory_incremented_mode * @{ */ #define DMA_MemoryInc_Enable ((uint32_t)0x00000080) #define DMA_MemoryInc_Disable ((uint32_t)0x00000000) #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ ((STATE) == DMA_MemoryInc_Disable)) /** * @} */ /** @defgroup DMA_peripheral_data_size * @{ */ #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) #define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) #define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ ((SIZE) == DMA_PeripheralDataSize_Word)) /** * @} */ /** @defgroup DMA_memory_data_size * @{ */ #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) #define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) #define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ ((SIZE) == DMA_MemoryDataSize_Word)) /** * @} */ /** @defgroup DMA_circular_normal_mode * @{ */ #define DMA_Mode_Circular ((uint32_t)0x00000020) #define DMA_Mode_Normal ((uint32_t)0x00000000) #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal)) /** * @} */ /** @defgroup DMA_priority_level * @{ */ #define DMA_Priority_VeryHigh ((uint32_t)0x00003000) #define DMA_Priority_High ((uint32_t)0x00002000) #define DMA_Priority_Medium ((uint32_t)0x00001000) #define DMA_Priority_Low ((uint32_t)0x00000000) #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ ((PRIORITY) == DMA_Priority_High) || \ ((PRIORITY) == DMA_Priority_Medium) || \ ((PRIORITY) == DMA_Priority_Low)) /** * @} */ /** @defgroup DMA_memory_to_memory * @{ */ #define DMA_M2M_Enable ((uint32_t)0x00004000) #define DMA_M2M_Disable ((uint32_t)0x00000000) #define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable)) /** * @} */ /** @defgroup DMA_interrupts_definition * @{ */ #define DMA_IT_TC ((uint32_t)0x00000002) #define DMA_IT_HT ((uint32_t)0x00000004) #define DMA_IT_TE ((uint32_t)0x00000008) #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) #define DMA1_IT_GL1 ((uint32_t)0x00000001) #define DMA1_IT_TC1 ((uint32_t)0x00000002) #define DMA1_IT_HT1 ((uint32_t)0x00000004) #define DMA1_IT_TE1 ((uint32_t)0x00000008) #define DMA1_IT_GL2 ((uint32_t)0x00000010) #define DMA1_IT_TC2 ((uint32_t)0x00000020) #define DMA1_IT_HT2 ((uint32_t)0x00000040) #define DMA1_IT_TE2 ((uint32_t)0x00000080) #define DMA1_IT_GL3 ((uint32_t)0x00000100) #define DMA1_IT_TC3 ((uint32_t)0x00000200) #define DMA1_IT_HT3 ((uint32_t)0x00000400) #define DMA1_IT_TE3 ((uint32_t)0x00000800) #define DMA1_IT_GL4 ((uint32_t)0x00001000) #define DMA1_IT_TC4 ((uint32_t)0x00002000) #define DMA1_IT_HT4 ((uint32_t)0x00004000) #define DMA1_IT_TE4 ((uint32_t)0x00008000) #define DMA1_IT_GL5 ((uint32_t)0x00010000) #define DMA1_IT_TC5 ((uint32_t)0x00020000) #define DMA1_IT_HT5 ((uint32_t)0x00040000) #define DMA1_IT_TE5 ((uint32_t)0x00080000) #define DMA1_IT_GL6 ((uint32_t)0x00100000) #define DMA1_IT_TC6 ((uint32_t)0x00200000) #define DMA1_IT_HT6 ((uint32_t)0x00400000) #define DMA1_IT_TE6 ((uint32_t)0x00800000) #define DMA1_IT_GL7 ((uint32_t)0x01000000) #define DMA1_IT_TC7 ((uint32_t)0x02000000) #define DMA1_IT_HT7 ((uint32_t)0x04000000) #define DMA1_IT_TE7 ((uint32_t)0x08000000) #define DMA2_IT_GL1 ((uint32_t)0x10000001) #define DMA2_IT_TC1 ((uint32_t)0x10000002) #define DMA2_IT_HT1 ((uint32_t)0x10000004) #define DMA2_IT_TE1 ((uint32_t)0x10000008) #define DMA2_IT_GL2 ((uint32_t)0x10000010) #define DMA2_IT_TC2 ((uint32_t)0x10000020) #define DMA2_IT_HT2 ((uint32_t)0x10000040) #define DMA2_IT_TE2 ((uint32_t)0x10000080) #define DMA2_IT_GL3 ((uint32_t)0x10000100) #define DMA2_IT_TC3 ((uint32_t)0x10000200) #define DMA2_IT_HT3 ((uint32_t)0x10000400) #define DMA2_IT_TE3 ((uint32_t)0x10000800) #define DMA2_IT_GL4 ((uint32_t)0x10001000) #define DMA2_IT_TC4 ((uint32_t)0x10002000) #define DMA2_IT_HT4 ((uint32_t)0x10004000) #define DMA2_IT_TE4 ((uint32_t)0x10008000) #define DMA2_IT_GL5 ((uint32_t)0x10010000) #define DMA2_IT_TC5 ((uint32_t)0x10020000) #define DMA2_IT_HT5 ((uint32_t)0x10040000) #define DMA2_IT_TE5 ((uint32_t)0x10080000) #define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00)) #define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \ ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \ ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \ ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \ ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \ ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \ ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \ ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \ ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \ ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \ ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \ ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \ ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \ ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \ ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \ ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \ ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \ ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \ ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \ ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \ ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \ ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \ ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5)) /** * @} */ /** @defgroup DMA_flags_definition * @{ */ #define DMA1_FLAG_GL1 ((uint32_t)0x00000001) #define DMA1_FLAG_TC1 ((uint32_t)0x00000002) #define DMA1_FLAG_HT1 ((uint32_t)0x00000004) #define DMA1_FLAG_TE1 ((uint32_t)0x00000008) #define DMA1_FLAG_GL2 ((uint32_t)0x00000010) #define DMA1_FLAG_TC2 ((uint32_t)0x00000020) #define DMA1_FLAG_HT2 ((uint32_t)0x00000040) #define DMA1_FLAG_TE2 ((uint32_t)0x00000080) #define DMA1_FLAG_GL3 ((uint32_t)0x00000100) #define DMA1_FLAG_TC3 ((uint32_t)0x00000200) #define DMA1_FLAG_HT3 ((uint32_t)0x00000400) #define DMA1_FLAG_TE3 ((uint32_t)0x00000800) #define DMA1_FLAG_GL4 ((uint32_t)0x00001000) #define DMA1_FLAG_TC4 ((uint32_t)0x00002000) #define DMA1_FLAG_HT4 ((uint32_t)0x00004000) #define DMA1_FLAG_TE4 ((uint32_t)0x00008000) #define DMA1_FLAG_GL5 ((uint32_t)0x00010000) #define DMA1_FLAG_TC5 ((uint32_t)0x00020000) #define DMA1_FLAG_HT5 ((uint32_t)0x00040000) #define DMA1_FLAG_TE5 ((uint32_t)0x00080000) #define DMA1_FLAG_GL6 ((uint32_t)0x00100000) #define DMA1_FLAG_TC6 ((uint32_t)0x00200000) #define DMA1_FLAG_HT6 ((uint32_t)0x00400000) #define DMA1_FLAG_TE6 ((uint32_t)0x00800000) #define DMA1_FLAG_GL7 ((uint32_t)0x01000000) #define DMA1_FLAG_TC7 ((uint32_t)0x02000000) #define DMA1_FLAG_HT7 ((uint32_t)0x04000000) #define DMA1_FLAG_TE7 ((uint32_t)0x08000000) #define DMA2_FLAG_GL1 ((uint32_t)0x10000001) #define DMA2_FLAG_TC1 ((uint32_t)0x10000002) #define DMA2_FLAG_HT1 ((uint32_t)0x10000004) #define DMA2_FLAG_TE1 ((uint32_t)0x10000008) #define DMA2_FLAG_GL2 ((uint32_t)0x10000010) #define DMA2_FLAG_TC2 ((uint32_t)0x10000020) #define DMA2_FLAG_HT2 ((uint32_t)0x10000040) #define DMA2_FLAG_TE2 ((uint32_t)0x10000080) #define DMA2_FLAG_GL3 ((uint32_t)0x10000100) #define DMA2_FLAG_TC3 ((uint32_t)0x10000200) #define DMA2_FLAG_HT3 ((uint32_t)0x10000400) #define DMA2_FLAG_TE3 ((uint32_t)0x10000800) #define DMA2_FLAG_GL4 ((uint32_t)0x10001000) #define DMA2_FLAG_TC4 ((uint32_t)0x10002000) #define DMA2_FLAG_HT4 ((uint32_t)0x10004000) #define DMA2_FLAG_TE4 ((uint32_t)0x10008000) #define DMA2_FLAG_GL5 ((uint32_t)0x10010000) #define DMA2_FLAG_TC5 ((uint32_t)0x10020000) #define DMA2_FLAG_HT5 ((uint32_t)0x10040000) #define DMA2_FLAG_TE5 ((uint32_t)0x10080000) #define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00)) #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \ ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \ ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \ ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \ ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \ ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \ ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \ ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \ ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \ ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \ ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \ ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \ ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \ ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \ ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \ ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \ ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \ ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \ ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \ ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \ ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \ ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \ ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5)) /** * @} */ /** @defgroup DMA_Buffer_Size * @{ */ #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ /* Function used to set the DMA configuration to the default reset state *****/ void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); /* Initialization and Configuration functions *********************************/ void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); /* Data Counter functions *****************************************************/ void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); /* Interrupts and flags management functions **********************************/ void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); void DMA_ClearFlag(uint32_t DMAy_FLAG); ITStatus DMA_GetITStatus(uint32_t DMAy_IT); void DMA_ClearITPendingBit(uint32_t DMAy_IT); #ifdef __cplusplus } #endif #endif /*__STM32L1xx_DMA_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/inc/stm32l1xx_exti.h
New file @@ -0,0 +1,199 @@ /** ****************************************************************************** * @file stm32l1xx_exti.h * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file contains all the functions prototypes for the EXTI firmware * library. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L1xx_EXTI_H #define __STM32L1xx_EXTI_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @addtogroup EXTI * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief EXTI mode enumeration */ typedef enum { EXTI_Mode_Interrupt = 0x00, EXTI_Mode_Event = 0x04 }EXTIMode_TypeDef; #define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) /** * @brief EXTI Trigger enumeration */ typedef enum { EXTI_Trigger_Rising = 0x08, EXTI_Trigger_Falling = 0x0C, EXTI_Trigger_Rising_Falling = 0x10 }EXTITrigger_TypeDef; #define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ ((TRIGGER) == EXTI_Trigger_Falling) || \ ((TRIGGER) == EXTI_Trigger_Rising_Falling)) /** * @brief EXTI Init Structure definition */ typedef struct { uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. This parameter can be any combination of @ref EXTI_Lines */ EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. This parameter can be a value of @ref EXTIMode_TypeDef */ EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. This parameter can be a value of @ref EXTITrigger_TypeDef */ FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. This parameter can be set either to ENABLE or DISABLE */ }EXTI_InitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup EXTI_Exported_Constants * @{ */ /** @defgroup EXTI_Lines * @{ */ #define EXTI_Line0 ((uint32_t)0x00000001) /*!< External interrupt line 0 */ #define EXTI_Line1 ((uint32_t)0x00000002) /*!< External interrupt line 1 */ #define EXTI_Line2 ((uint32_t)0x00000004) /*!< External interrupt line 2 */ #define EXTI_Line3 ((uint32_t)0x00000008) /*!< External interrupt line 3 */ #define EXTI_Line4 ((uint32_t)0x00000010) /*!< External interrupt line 4 */ #define EXTI_Line5 ((uint32_t)0x00000020) /*!< External interrupt line 5 */ #define EXTI_Line6 ((uint32_t)0x00000040) /*!< External interrupt line 6 */ #define EXTI_Line7 ((uint32_t)0x00000080) /*!< External interrupt line 7 */ #define EXTI_Line8 ((uint32_t)0x00000100) /*!< External interrupt line 8 */ #define EXTI_Line9 ((uint32_t)0x00000200) /*!< External interrupt line 9 */ #define EXTI_Line10 ((uint32_t)0x00000400) /*!< External interrupt line 10 */ #define EXTI_Line11 ((uint32_t)0x00000800) /*!< External interrupt line 11 */ #define EXTI_Line12 ((uint32_t)0x00001000) /*!< External interrupt line 12 */ #define EXTI_Line13 ((uint32_t)0x00002000) /*!< External interrupt line 13 */ #define EXTI_Line14 ((uint32_t)0x00004000) /*!< External interrupt line 14 */ #define EXTI_Line15 ((uint32_t)0x00008000) /*!< External interrupt line 15 */ #define EXTI_Line16 ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD Output */ #define EXTI_Line17 ((uint32_t)0x00020000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ #define EXTI_Line18 ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB Device FS Wakeup from suspend event */ #define EXTI_Line19 ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */ #define EXTI_Line20 ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the RTC Wakeup event */ #define EXTI_Line21 ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to the Comparator 1 event */ #define EXTI_Line22 ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to the Comparator 2 event */ #define EXTI_Line23 ((uint32_t)0x00800000) /*!< External interrupt line 23 Comparator channel acquisition event */ #define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF000000) == 0x00) && ((LINE) != (uint16_t)0x00)) #define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \ ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \ ((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line23)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ /* Function used to set the EXTI configuration to the default reset state *****/ void EXTI_DeInit(void); /* Initialization and Configuration functions *********************************/ void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); /* Interrupts and flags management functions **********************************/ FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); void EXTI_ClearFlag(uint32_t EXTI_Line); ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); void EXTI_ClearITPendingBit(uint32_t EXTI_Line); #ifdef __cplusplus } #endif #endif /* __STM32L1xx_EXTI_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/inc/stm32l1xx_flash.h
New file @@ -0,0 +1,528 @@ /** ****************************************************************************** * @file stm32l1xx_flash.h * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file contains all the functions prototypes for the FLASH * firmware library. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L1xx_FLASH_H #define __STM32L1xx_FLASH_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @addtogroup FLASH * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief FLASH Status */ typedef enum { FLASH_BUSY = 1, FLASH_ERROR_WRP, FLASH_ERROR_PROGRAM, FLASH_COMPLETE, FLASH_TIMEOUT }FLASH_Status; /* Exported constants --------------------------------------------------------*/ /** @defgroup FLASH_Exported_Constants * @{ */ /** @defgroup FLASH_Latency * @{ */ #define FLASH_Latency_0 ((uint8_t)0x00) /*!< FLASH Zero Latency cycle */ #define FLASH_Latency_1 ((uint8_t)0x01) /*!< FLASH One Latency cycle */ #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ ((LATENCY) == FLASH_Latency_1)) /** * @} */ /** @defgroup FLASH_Interrupts * @{ */ #define FLASH_IT_EOP FLASH_PECR_EOPIE /*!< End of programming interrupt source */ #define FLASH_IT_ERR FLASH_PECR_ERRIE /*!< Error interrupt source */ #define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFCFFFF) == 0x00000000) && (((IT) != 0x00000000))) /** * @} */ /** @defgroup FLASH_Address * @{ */ #define IS_FLASH_DATA_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08080000) && ((ADDRESS) <= 0x08083FFF)) #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0807FFFF)) /** * @} */ /** @defgroup Option_Bytes_Write_Protection * @{ */ #define OB_WRP_Pages0to15 ((uint32_t)0x00000001) /* Write protection of Sector0 */ #define OB_WRP_Pages16to31 ((uint32_t)0x00000002) /* Write protection of Sector1 */ #define OB_WRP_Pages32to47 ((uint32_t)0x00000004) /* Write protection of Sector2 */ #define OB_WRP_Pages48to63 ((uint32_t)0x00000008) /* Write protection of Sector3 */ #define OB_WRP_Pages64to79 ((uint32_t)0x00000010) /* Write protection of Sector4 */ #define OB_WRP_Pages80to95 ((uint32_t)0x00000020) /* Write protection of Sector5 */ #define OB_WRP_Pages96to111 ((uint32_t)0x00000040) /* Write protection of Sector6 */ #define OB_WRP_Pages112to127 ((uint32_t)0x00000080) /* Write protection of Sector7 */ #define OB_WRP_Pages128to143 ((uint32_t)0x00000100) /* Write protection of Sector8 */ #define OB_WRP_Pages144to159 ((uint32_t)0x00000200) /* Write protection of Sector9 */ #define OB_WRP_Pages160to175 ((uint32_t)0x00000400) /* Write protection of Sector10 */ #define OB_WRP_Pages176to191 ((uint32_t)0x00000800) /* Write protection of Sector11 */ #define OB_WRP_Pages192to207 ((uint32_t)0x00001000) /* Write protection of Sector12 */ #define OB_WRP_Pages208to223 ((uint32_t)0x00002000) /* Write protection of Sector13 */ #define OB_WRP_Pages224to239 ((uint32_t)0x00004000) /* Write protection of Sector14 */ #define OB_WRP_Pages240to255 ((uint32_t)0x00008000) /* Write protection of Sector15 */ #define OB_WRP_Pages256to271 ((uint32_t)0x00010000) /* Write protection of Sector16 */ #define OB_WRP_Pages272to287 ((uint32_t)0x00020000) /* Write protection of Sector17 */ #define OB_WRP_Pages288to303 ((uint32_t)0x00040000) /* Write protection of Sector18 */ #define OB_WRP_Pages304to319 ((uint32_t)0x00080000) /* Write protection of Sector19 */ #define OB_WRP_Pages320to335 ((uint32_t)0x00100000) /* Write protection of Sector20 */ #define OB_WRP_Pages336to351 ((uint32_t)0x00200000) /* Write protection of Sector21 */ #define OB_WRP_Pages352to367 ((uint32_t)0x00400000) /* Write protection of Sector22 */ #define OB_WRP_Pages368to383 ((uint32_t)0x00800000) /* Write protection of Sector23 */ #define OB_WRP_Pages384to399 ((uint32_t)0x01000000) /* Write protection of Sector24 */ #define OB_WRP_Pages400to415 ((uint32_t)0x02000000) /* Write protection of Sector25 */ #define OB_WRP_Pages416to431 ((uint32_t)0x04000000) /* Write protection of Sector26 */ #define OB_WRP_Pages432to447 ((uint32_t)0x08000000) /* Write protection of Sector27 */ #define OB_WRP_Pages448to463 ((uint32_t)0x10000000) /* Write protection of Sector28 */ #define OB_WRP_Pages464to479 ((uint32_t)0x20000000) /* Write protection of Sector29 */ #define OB_WRP_Pages480to495 ((uint32_t)0x40000000) /* Write protection of Sector30 */ #define OB_WRP_Pages496to511 ((uint32_t)0x80000000) /* Write protection of Sector31 */ #define OB_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */ #define OB_WRP1_Pages512to527 ((uint32_t)0x00000001) /* Write protection of Sector32 */ #define OB_WRP1_Pages528to543 ((uint32_t)0x00000002) /* Write protection of Sector33 */ #define OB_WRP1_Pages544to559 ((uint32_t)0x00000004) /* Write protection of Sector34 */ #define OB_WRP1_Pages560to575 ((uint32_t)0x00000008) /* Write protection of Sector35 */ #define OB_WRP1_Pages576to591 ((uint32_t)0x00000010) /* Write protection of Sector36 */ #define OB_WRP1_Pages592to607 ((uint32_t)0x00000020) /* Write protection of Sector37 */ #define OB_WRP1_Pages608to623 ((uint32_t)0x00000040) /* Write protection of Sector38 */ #define OB_WRP1_Pages624to639 ((uint32_t)0x00000080) /* Write protection of Sector39 */ #define OB_WRP1_Pages640to655 ((uint32_t)0x00000100) /* Write protection of Sector40 */ #define OB_WRP1_Pages656to671 ((uint32_t)0x00000200) /* Write protection of Sector41 */ #define OB_WRP1_Pages672to687 ((uint32_t)0x00000400) /* Write protection of Sector42 */ #define OB_WRP1_Pages688to703 ((uint32_t)0x00000800) /* Write protection of Sector43 */ #define OB_WRP1_Pages704to719 ((uint32_t)0x00001000) /* Write protection of Sector44 */ #define OB_WRP1_Pages720to735 ((uint32_t)0x00002000) /* Write protection of Sector45 */ #define OB_WRP1_Pages736to751 ((uint32_t)0x00004000) /* Write protection of Sector46 */ #define OB_WRP1_Pages752to767 ((uint32_t)0x00008000) /* Write protection of Sector47 */ #define OB_WRP1_Pages768to783 ((uint32_t)0x00010000) /* Write protection of Sector48 */ #define OB_WRP1_Pages784to799 ((uint32_t)0x00020000) /* Write protection of Sector49 */ #define OB_WRP1_Pages800to815 ((uint32_t)0x00040000) /* Write protection of Sector50 */ #define OB_WRP1_Pages816to831 ((uint32_t)0x00080000) /* Write protection of Sector51 */ #define OB_WRP1_Pages832to847 ((uint32_t)0x00100000) /* Write protection of Sector52 */ #define OB_WRP1_Pages848to863 ((uint32_t)0x00200000) /* Write protection of Sector53 */ #define OB_WRP1_Pages864to879 ((uint32_t)0x00400000) /* Write protection of Sector54 */ #define OB_WRP1_Pages880to895 ((uint32_t)0x00800000) /* Write protection of Sector55 */ #define OB_WRP1_Pages896to911 ((uint32_t)0x01000000) /* Write protection of Sector56 */ #define OB_WRP1_Pages912to927 ((uint32_t)0x02000000) /* Write protection of Sector57 */ #define OB_WRP1_Pages928to943 ((uint32_t)0x04000000) /* Write protection of Sector58 */ #define OB_WRP1_Pages944to959 ((uint32_t)0x08000000) /* Write protection of Sector59 */ #define OB_WRP1_Pages960to975 ((uint32_t)0x10000000) /* Write protection of Sector60 */ #define OB_WRP1_Pages976to991 ((uint32_t)0x20000000) /* Write protection of Sector61 */ #define OB_WRP1_Pages992to1007 ((uint32_t)0x40000000) /* Write protection of Sector62 */ #define OB_WRP1_Pages1008to1023 ((uint32_t)0x80000000) /* Write protection of Sector63 */ #define OB_WRP1_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */ #define OB_WRP2_Pages1024to1039 ((uint32_t)0x00000001) /* Write protection of Sector64 */ #define OB_WRP2_Pages1040to1055 ((uint32_t)0x00000002) /* Write protection of Sector65 */ #define OB_WRP2_Pages1056to1071 ((uint32_t)0x00000004) /* Write protection of Sector66 */ #define OB_WRP2_Pages1072to1087 ((uint32_t)0x00000008) /* Write protection of Sector67 */ #define OB_WRP2_Pages1088to1103 ((uint32_t)0x00000010) /* Write protection of Sector68 */ #define OB_WRP2_Pages1104to1119 ((uint32_t)0x00000020) /* Write protection of Sector69 */ #define OB_WRP2_Pages1120to1135 ((uint32_t)0x00000040) /* Write protection of Sector70 */ #define OB_WRP2_Pages1136to1151 ((uint32_t)0x00000080) /* Write protection of Sector71 */ #define OB_WRP2_Pages1152to1167 ((uint32_t)0x00000100) /* Write protection of Sector72 */ #define OB_WRP2_Pages1168to1183 ((uint32_t)0x00000200) /* Write protection of Sector73 */ #define OB_WRP2_Pages1184to1199 ((uint32_t)0x00000400) /* Write protection of Sector74 */ #define OB_WRP2_Pages1200to1215 ((uint32_t)0x00000800) /* Write protection of Sector75 */ #define OB_WRP2_Pages1216to1231 ((uint32_t)0x00001000) /* Write protection of Sector76 */ #define OB_WRP2_Pages1232to1247 ((uint32_t)0x00002000) /* Write protection of Sector77 */ #define OB_WRP2_Pages1248to1263 ((uint32_t)0x00004000) /* Write protection of Sector78 */ #define OB_WRP2_Pages1264to1279 ((uint32_t)0x00008000) /* Write protection of Sector79 */ #define OB_WRP2_Pages1280to1295 ((uint32_t)0x00010000) /* Write protection of Sector80 */ #define OB_WRP2_Pages1296to1311 ((uint32_t)0x00020000) /* Write protection of Sector81 */ #define OB_WRP2_Pages1312to1327 ((uint32_t)0x00040000) /* Write protection of Sector82 */ #define OB_WRP2_Pages1328to1343 ((uint32_t)0x00080000) /* Write protection of Sector83 */ #define OB_WRP2_Pages1344to1359 ((uint32_t)0x00100000) /* Write protection of Sector84 */ #define OB_WRP2_Pages1360to1375 ((uint32_t)0x00200000) /* Write protection of Sector85 */ #define OB_WRP2_Pages1376to1391 ((uint32_t)0x00400000) /* Write protection of Sector86 */ #define OB_WRP2_Pages1392to1407 ((uint32_t)0x00800000) /* Write protection of Sector87 */ #define OB_WRP2_Pages1408to1423 ((uint32_t)0x01000000) /* Write protection of Sector88 */ #define OB_WRP2_Pages1424to1439 ((uint32_t)0x02000000) /* Write protection of Sector89 */ #define OB_WRP2_Pages1440to1455 ((uint32_t)0x04000000) /* Write protection of Sector90 */ #define OB_WRP2_Pages1456to1471 ((uint32_t)0x08000000) /* Write protection of Sector91 */ #define OB_WRP2_Pages1472to1487 ((uint32_t)0x10000000) /* Write protection of Sector92 */ #define OB_WRP2_Pages1488to1503 ((uint32_t)0x20000000) /* Write protection of Sector93 */ #define OB_WRP2_Pages1504to1519 ((uint32_t)0x40000000) /* Write protection of Sector94 */ #define OB_WRP2_Pages1520to1535 ((uint32_t)0x80000000) /* Write protection of Sector95 */ #define OB_WRP2_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */ #define OB_WRP3_Pages1536to1551 ((uint32_t)0x00000001) /* Write protection of Sector96 */ #define OB_WRP3_Pages1552to1567 ((uint32_t)0x00000002) /* Write protection of Sector97 */ #define OB_WRP3_Pages1568to1583 ((uint32_t)0x00000004) /* Write protection of Sector98 */ #define OB_WRP3_Pages1584to1599 ((uint32_t)0x00000008) /* Write protection of Sector99 */ #define OB_WRP3_Pages1600to1615 ((uint32_t)0x00000010) /* Write protection of Sector100 */ #define OB_WRP3_Pages1616to1631 ((uint32_t)0x00000020) /* Write protection of Sector101 */ #define OB_WRP3_Pages1632to1647 ((uint32_t)0x00000040) /* Write protection of Sector102 */ #define OB_WRP3_Pages1648to1663 ((uint32_t)0x00000080) /* Write protection of Sector103 */ #define OB_WRP3_Pages1664to1679 ((uint32_t)0x00000100) /* Write protection of Sector104 */ #define OB_WRP3_Pages1680to1695 ((uint32_t)0x00000200) /* Write protection of Sector105 */ #define OB_WRP3_Pages1696to1711 ((uint32_t)0x00000400) /* Write protection of Sector106 */ #define OB_WRP3_Pages1712to1727 ((uint32_t)0x00000800) /* Write protection of Sector107 */ #define OB_WRP3_Pages1728to1743 ((uint32_t)0x00001000) /* Write protection of Sector108 */ #define OB_WRP3_Pages1744to1759 ((uint32_t)0x00002000) /* Write protection of Sector109 */ #define OB_WRP3_Pages1760to1775 ((uint32_t)0x00004000) /* Write protection of Sector110 */ #define OB_WRP3_Pages1776to1791 ((uint32_t)0x00008000) /* Write protection of Sector111 */ #define OB_WRP3_Pages1792to1807 ((uint32_t)0x00010000) /* Write protection of Sector112 */ #define OB_WRP3_Pages1808to1823 ((uint32_t)0x00020000) /* Write protection of Sector113 */ #define OB_WRP3_Pages1824to1839 ((uint32_t)0x00040000) /* Write protection of Sector114 */ #define OB_WRP3_Pages1840to1855 ((uint32_t)0x00080000) /* Write protection of Sector115 */ #define OB_WRP3_Pages1856to1871 ((uint32_t)0x00100000) /* Write protection of Sector116 */ #define OB_WRP3_Pages1872to1887 ((uint32_t)0x00200000) /* Write protection of Sector117 */ #define OB_WRP3_Pages1888to1903 ((uint32_t)0x00400000) /* Write protection of Sector118 */ #define OB_WRP3_Pages1904to1919 ((uint32_t)0x00800000) /* Write protection of Sector119 */ #define OB_WRP3_Pages1920to1935 ((uint32_t)0x01000000) /* Write protection of Sector120 */ #define OB_WRP3_Pages1936to1951 ((uint32_t)0x02000000) /* Write protection of Sector121 */ #define OB_WRP3_Pages1952to1967 ((uint32_t)0x04000000) /* Write protection of Sector122 */ #define OB_WRP3_Pages1968to1983 ((uint32_t)0x08000000) /* Write protection of Sector123 */ #define OB_WRP3_Pages1984to1999 ((uint32_t)0x10000000) /* Write protection of Sector124 */ #define OB_WRP3_Pages2000to2015 ((uint32_t)0x20000000) /* Write protection of Sector125 */ #define OB_WRP3_Pages2016to2031 ((uint32_t)0x40000000) /* Write protection of Sector126 */ #define OB_WRP3_Pages2032to2047 ((uint32_t)0x80000000) /* Write protection of Sector127 */ #define OB_WRP3_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */ #define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000)) /* IMPORTANT NOTE ============== In the StdLib, the naming of WRP registers is shifted vs. the Reference Manual: - WRPR correspond to WRPR1 - WRPR1 correspond to WRPR2 - WRPR2 correspond to WRPR3 - WRPR3 correspond to WRPR4 */ /** * @} */ /** @defgroup Selection_Protection_Mode * @{ */ #define OB_PcROP_Enable ((uint16_t)0x0100) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */ #define OB_PcROP_Disable ((uint16_t)0x0000) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i */ #define IS_OB_PCROP_SELECT(OB_PcROP) (((OB_PcROP) == OB_PcROP_Enable) || ((OB_PcROP) == OB_PcROP_Disable)) /** * @} */ /** @defgroup Option_Bytes_Read_Protection * @{ */ /** * @brief Read Protection Level */ #define OB_RDP_Level_0 ((uint8_t)0xAA) #define OB_RDP_Level_1 ((uint8_t)0xBB) /*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2 it's no more possible to go back to level 1 or 0 */ #define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\ ((LEVEL) == OB_RDP_Level_1))/*||\ ((LEVEL) == OB_RDP_Level_2))*/ /** * @} */ /** @defgroup Option_Bytes_IWatchdog * @{ */ #define OB_IWDG_SW ((uint8_t)0x10) /*!< Software WDG selected */ #define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware WDG selected */ #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) /** * @} */ /** @defgroup Option_Bytes_nRST_STOP * @{ */ #define OB_STOP_NoRST ((uint8_t)0x20) /*!< No reset generated when entering in STOP */ #define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */ #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) /** * @} */ /** @defgroup Option_Bytes_nRST_STDBY * @{ */ #define OB_STDBY_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STANDBY */ #define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) /** * @} */ /** @defgroup Option_Bytes_BOOT * @{ */ #define OB_BOOT_BANK2 ((uint8_t)0x00) /*!< At startup, if boot pins are set in boot from user Flash position and this parameter is selected the device will boot from Bank 2 or Bank 1, depending on the activation of the bank */ #define OB_BOOT_BANK1 ((uint8_t)0x80) /*!< At startup, if boot pins are set in boot from user Flash position and this parameter is selected the device will boot from Bank1(Default) */ #define IS_OB_BOOT_BANK(BANK) (((BANK) == OB_BOOT_BANK2) || ((BANK) == OB_BOOT_BANK1)) /** * @} */ /** @defgroup Option_Bytes_BOR_Level * @{ */ #define OB_BOR_OFF ((uint8_t)0x00) /*!< BOR is disabled at power down, the reset is asserted when the VDD power supply reaches the PDR(Power Down Reset) threshold (1.5V) */ #define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply */ #define OB_BOR_LEVEL2 ((uint8_t)0x09) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply */ #define OB_BOR_LEVEL3 ((uint8_t)0x0A) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply */ #define OB_BOR_LEVEL4 ((uint8_t)0x0B) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply */ #define OB_BOR_LEVEL5 ((uint8_t)0x0C) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply */ #define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_OFF) || \ ((LEVEL) == OB_BOR_LEVEL1) || \ ((LEVEL) == OB_BOR_LEVEL2) || \ ((LEVEL) == OB_BOR_LEVEL3) || \ ((LEVEL) == OB_BOR_LEVEL4) || \ ((LEVEL) == OB_BOR_LEVEL5)) /** * @} */ /** @defgroup FLASH_Flags * @{ */ #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ #define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */ #define FLASH_FLAG_ENDHV FLASH_SR_ENHV /*!< FLASH End of High Voltage flag */ #define FLASH_FLAG_READY FLASH_SR_READY /*!< FLASH Ready flag after low power mode */ #define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */ #define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */ #define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */ #define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option Validity error flag */ #define FLASH_FLAG_OPTVERRUSR FLASH_SR_OPTVERRUSR /*!< FLASH Option User Validity error flag */ #define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH Read protected error flag (available only in STM32L1XX_MDP devices) */ #define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFC0FD) == 0x00000000) && ((FLAG) != 0x00000000)) #define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ ((FLAG) == FLASH_FLAG_ENDHV) || ((FLAG) == FLASH_FLAG_READY ) || \ ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR ) || \ ((FLAG) == FLASH_FLAG_SIZERR) || ((FLAG) == FLASH_FLAG_OPTVERR) || \ ((FLAG) == FLASH_FLAG_OPTVERRUSR) || ((FLAG) == FLASH_FLAG_RDERR)) /** * @} */ /** @defgroup FLASH_Keys * @{ */ #define FLASH_PDKEY1 ((uint32_t)0x04152637) /*!< Flash power down key1 */ #define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFD) /*!< Flash power down key2: used with FLASH_PDKEY1 to unlock the RUN_PD bit in FLASH_ACR */ #define FLASH_PEKEY1 ((uint32_t)0x89ABCDEF) /*!< Flash program erase key1 */ #define FLASH_PEKEY2 ((uint32_t)0x02030405) /*!< Flash program erase key: used with FLASH_PEKEY2 to unlock the write access to the FLASH_PECR register and data EEPROM */ #define FLASH_PRGKEY1 ((uint32_t)0x8C9DAEBF) /*!< Flash program memory key1 */ #define FLASH_PRGKEY2 ((uint32_t)0x13141516) /*!< Flash program memory key2: used with FLASH_PRGKEY2 to unlock the program memory */ #define FLASH_OPTKEY1 ((uint32_t)0xFBEAD9C8) /*!< Flash option key1 */ #define FLASH_OPTKEY2 ((uint32_t)0x24252627) /*!< Flash option key2: used with FLASH_OPTKEY1 to unlock the write access to the option byte block */ /** * @} */ /** @defgroup Timeout_definition * @{ */ #define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x8000) /** * @} */ /** @defgroup CMSIS_Legacy * @{ */ #if defined ( __ICCARM__ ) #define InterruptType_ACTLR_DISMCYCINT_Msk IntType_ACTLR_DISMCYCINT_Msk #endif /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ /** * @brief FLASH memory functions that can be executed from FLASH. */ /* FLASH Interface configuration functions ************************************/ void FLASH_SetLatency(uint32_t FLASH_Latency); void FLASH_PrefetchBufferCmd(FunctionalState NewState); void FLASH_ReadAccess64Cmd(FunctionalState NewState); void FLASH_SLEEPPowerDownCmd(FunctionalState NewState); /* FLASH Memory Programming functions *****************************************/ void FLASH_Unlock(void); void FLASH_Lock(void); FLASH_Status FLASH_ErasePage(uint32_t Page_Address); FLASH_Status FLASH_FastProgramWord(uint32_t Address, uint32_t Data); /* DATA EEPROM Programming functions ******************************************/ void DATA_EEPROM_Unlock(void); void DATA_EEPROM_Lock(void); void DATA_EEPROM_FixedTimeProgramCmd(FunctionalState NewState); FLASH_Status DATA_EEPROM_EraseByte(uint32_t Address); FLASH_Status DATA_EEPROM_EraseHalfWord(uint32_t Address); FLASH_Status DATA_EEPROM_EraseWord(uint32_t Address); FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data); FLASH_Status DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data); FLASH_Status DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data); FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data); FLASH_Status DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data); FLASH_Status DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data); /* Option Bytes Programming functions *****************************************/ void FLASH_OB_Unlock(void); void FLASH_OB_Lock(void); void FLASH_OB_Launch(void); FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState); FLASH_Status FLASH_OB_WRP1Config(uint32_t OB_WRP1, FunctionalState NewState); FLASH_Status FLASH_OB_WRP2Config(uint32_t OB_WRP2, FunctionalState NewState); FLASH_Status FLASH_OB_WRP3Config(uint32_t OB_WRP3, FunctionalState NewState); FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP); FLASH_Status FLASH_OB_PCROPConfig(uint32_t OB_WRP, FunctionalState NewState); FLASH_Status FLASH_OB_PCROP1Config(uint32_t OB_WRP1, FunctionalState NewState); FLASH_Status FLASH_OB_PCROPSelectionConfig(uint16_t OB_PcROP); FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); FLASH_Status FLASH_OB_BORConfig(uint8_t OB_BOR); FLASH_Status FLASH_OB_BootConfig(uint8_t OB_BOOT); uint8_t FLASH_OB_GetUser(void); uint32_t FLASH_OB_GetWRP(void); uint32_t FLASH_OB_GetWRP1(void); uint32_t FLASH_OB_GetWRP2(void); uint32_t FLASH_OB_GetWRP3(void); FlagStatus FLASH_OB_GetRDP(void); FlagStatus FLASH_OB_GetSPRMOD(void); uint8_t FLASH_OB_GetBOR(void); /* Interrupts and flags management functions **********************************/ void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); void FLASH_ClearFlag(uint32_t FLASH_FLAG); FLASH_Status FLASH_GetStatus(void); FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); /** * @brief FLASH memory functions that should be executed from internal SRAM. * These functions are defined inside the "stm32l1xx_flash_ramfunc.c" * file. */ __RAM_FUNC FLASH_RUNPowerDownCmd(FunctionalState NewState); __RAM_FUNC FLASH_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2); __RAM_FUNC FLASH_ProgramHalfPage(uint32_t Address, uint32_t* pBuffer); __RAM_FUNC FLASH_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2); __RAM_FUNC DATA_EEPROM_EraseDoubleWord(uint32_t Address); __RAM_FUNC DATA_EEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data); #ifdef __cplusplus } #endif #endif /* __STM32L1xx_FLASH_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/inc/stm32l1xx_fsmc.h
New file @@ -0,0 +1,438 @@ /** ****************************************************************************** * @file stm32l1xx_fsmc.h * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file contains all the functions prototypes for the FSMC firmware * library. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L1xx_FSMC_H #define __STM32L1xx_FSMC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @addtogroup FSMC * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief Timing parameters For NOR/SRAM Banks */ typedef struct { uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure the duration of the address setup time. This parameter can be a value between 0 and 0xF. @note It is not used with synchronous NOR Flash memories. */ uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure the duration of the address hold time. This parameter can be a value between 0 and 0xF. @note It is not used with synchronous NOR Flash memories.*/ uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure the duration of the data setup time. This parameter can be a value between 0 and 0xFF. @note It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure the duration of the bus turnaround. This parameter can be a value between 0 and 0xF. @note It is only used for multiplexed NOR Flash memories. */ uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. This parameter can be a value between 1 and 0xF. @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue to the memory before getting the first data. The parameter value depends on the memory type as shown below: - It must be set to 0 in case of a CRAM - It is don't care in asynchronous NOR, SRAM or ROM accesses - It may assume a value between 0 and 0xF in NOR Flash memories with synchronous burst mode enable */ uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. This parameter can be a value of @ref FSMC_Access_Mode */ }FSMC_NORSRAMTimingInitTypeDef; /** * @brief FSMC NOR/SRAM Init structure definition */ typedef struct { uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. This parameter can be a value of @ref FSMC_NORSRAM_Bank */ uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are multiplexed on the databus or not. This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to the corresponding memory bank. This parameter can be a value of @ref FSMC_Memory_Type */ uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. This parameter can be a value of @ref FSMC_Data_Width */ uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, valid only with synchronous burst Flash memories. This parameter can be a value of @ref FSMC_Burst_Access_Mode */ uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, valid only with asynchronous Flash memories. This parameter can be a value of @ref FSMC_AsynchronousWait */ uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing the Flash memory in burst mode. This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash memory, valid only when accessing Flash memories in burst mode. This parameter can be a value of @ref FSMC_Wrap_Mode */ uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one clock cycle before the wait state or during the wait state, valid only when accessing memories in burst mode. This parameter can be a value of @ref FSMC_Wait_Timing */ uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. This parameter can be a value of @ref FSMC_Write_Operation */ uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait signal, valid for Flash memory access in burst mode. This parameter can be a value of @ref FSMC_Wait_Signal */ uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode. This parameter can be a value of @ref FSMC_Extended_Mode */ uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation. This parameter can be a value of @ref FSMC_Write_Burst */ FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ }FSMC_NORSRAMInitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup FSMC_Exported_Constants * @{ */ /** @defgroup FSMC_NORSRAM_Bank * @{ */ #define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) #define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) #define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) #define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) #define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ ((BANK) == FSMC_Bank1_NORSRAM2) || \ ((BANK) == FSMC_Bank1_NORSRAM3) || \ ((BANK) == FSMC_Bank1_NORSRAM4)) /** * @} */ /** @defgroup NOR_SRAM_Controller * @{ */ /** @defgroup FSMC_Data_Address_Bus_Multiplexing * @{ */ #define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) #define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) #define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ ((MUX) == FSMC_DataAddressMux_Enable)) /** * @} */ /** @defgroup FSMC_Memory_Type * @{ */ #define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) #define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) #define FSMC_MemoryType_NOR ((uint32_t)0x00000008) #define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ ((MEMORY) == FSMC_MemoryType_NOR)) /** * @} */ /** @defgroup FSMC_Data_Width * @{ */ #define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) #define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) #define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ ((WIDTH) == FSMC_MemoryDataWidth_16b)) /** * @} */ /** @defgroup FSMC_Burst_Access_Mode * @{ */ #define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) #define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) #define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ ((STATE) == FSMC_BurstAccessMode_Enable)) /** * @} */ /** @defgroup FSMC_AsynchronousWait * @{ */ #define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000) #define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000) #define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \ ((STATE) == FSMC_AsynchronousWait_Enable)) /** * @} */ /** @defgroup FSMC_Wait_Signal_Polarity * @{ */ #define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) #define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) #define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ ((POLARITY) == FSMC_WaitSignalPolarity_High)) /** * @} */ /** @defgroup FSMC_Wrap_Mode * @{ */ #define FSMC_WrapMode_Disable ((uint32_t)0x00000000) #define FSMC_WrapMode_Enable ((uint32_t)0x00000400) #define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ ((MODE) == FSMC_WrapMode_Enable)) /** * @} */ /** @defgroup FSMC_Wait_Timing * @{ */ #define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) #define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) #define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) /** * @} */ /** @defgroup FSMC_Write_Operation * @{ */ #define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) #define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) #define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ ((OPERATION) == FSMC_WriteOperation_Enable)) /** * @} */ /** @defgroup FSMC_Wait_Signal * @{ */ #define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) #define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) #define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ ((SIGNAL) == FSMC_WaitSignal_Enable)) /** * @} */ /** @defgroup FSMC_Extended_Mode * @{ */ #define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) #define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) #define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ ((MODE) == FSMC_ExtendedMode_Enable)) /** * @} */ /** @defgroup FSMC_Write_Burst * @{ */ #define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) #define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) #define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ ((BURST) == FSMC_WriteBurst_Enable)) /** * @} */ /** @defgroup FSMC_Address_Setup_Time * @{ */ #define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) /** * @} */ /** @defgroup FSMC_Address_Hold_Time * @{ */ #define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) /** * @} */ /** @defgroup FSMC_Data_Setup_Time * @{ */ #define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) /** * @} */ /** @defgroup FSMC_Bus_Turn_around_Duration * @{ */ #define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) /** * @} */ /** @defgroup FSMC_CLK_Division * @{ */ #define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) /** * @} */ /** @defgroup FSMC_Data_Latency * @{ */ #define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) /** * @} */ /** @defgroup FSMC_Access_Mode * @{ */ #define FSMC_AccessMode_A ((uint32_t)0x00000000) #define FSMC_AccessMode_B ((uint32_t)0x10000000) #define FSMC_AccessMode_C ((uint32_t)0x20000000) #define FSMC_AccessMode_D ((uint32_t)0x30000000) #define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ ((MODE) == FSMC_AccessMode_B) || \ ((MODE) == FSMC_AccessMode_C) || \ ((MODE) == FSMC_AccessMode_D)) /** * @} */ /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ /* NOR/SRAM Controller functions **********************************************/ void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); #ifdef __cplusplus } #endif #endif /*__STM32L1xx_FSMC_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/inc/stm32l1xx_gpio.h
New file @@ -0,0 +1,391 @@ /** ****************************************************************************** * @file stm32l1xx_gpio.h * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file contains all the functions prototypes for the GPIO * firmware library. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L1xx_GPIO_H #define __STM32L1xx_GPIO_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @addtogroup GPIO * @{ */ /* Exported types ------------------------------------------------------------*/ #define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ ((PERIPH) == GPIOB) || \ ((PERIPH) == GPIOC) || \ ((PERIPH) == GPIOD) || \ ((PERIPH) == GPIOE) || \ ((PERIPH) == GPIOH) || \ ((PERIPH) == GPIOF) || \ ((PERIPH) == GPIOG)) /** @defgroup Configuration_Mode_enumeration * @{ */ typedef enum { GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */ GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */ GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */ GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */ }GPIOMode_TypeDef; #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \ ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN)) /** * @} */ /** @defgroup Output_type_enumeration * @{ */ typedef enum { GPIO_OType_PP = 0x00, GPIO_OType_OD = 0x01 }GPIOOType_TypeDef; #define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD)) /** * @} */ /** @defgroup Output_Maximum_frequency_enumeration * @{ */ typedef enum { GPIO_Speed_400KHz = 0x00, /*!< Very Low Speed */ GPIO_Speed_2MHz = 0x01, /*!< Low Speed */ GPIO_Speed_10MHz = 0x02, /*!< Medium Speed */ GPIO_Speed_40MHz = 0x03 /*!< High Speed */ }GPIOSpeed_TypeDef; #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_400KHz) || ((SPEED) == GPIO_Speed_2MHz) || \ ((SPEED) == GPIO_Speed_10MHz)|| ((SPEED) == GPIO_Speed_40MHz)) /** * @} */ /** @defgroup Configuration_Pull-Up_Pull-Down_enumeration * @{ */ typedef enum { GPIO_PuPd_NOPULL = 0x00, GPIO_PuPd_UP = 0x01, GPIO_PuPd_DOWN = 0x02 }GPIOPuPd_TypeDef; #define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \ ((PUPD) == GPIO_PuPd_DOWN)) /** * @} */ /** @defgroup Bit_SET_and_Bit_RESET_enumeration * @{ */ typedef enum { Bit_RESET = 0, Bit_SET }BitAction; #define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) /** * @} */ /** * @brief GPIO Init structure definition */ typedef struct { uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. This parameter can be any value of @ref GPIO_pins_define */ GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. This parameter can be a value of @ref GPIOMode_TypeDef */ GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. This parameter can be a value of @ref GPIOSpeed_TypeDef */ GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins. This parameter can be a value of @ref GPIOOType_TypeDef */ GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins. This parameter can be a value of @ref GPIOPuPd_TypeDef */ }GPIO_InitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup GPIO_Exported_Constants * @{ */ /** @defgroup GPIO_pins_define * @{ */ #define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ #define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ #define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ #define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ #define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ #define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ #define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ #define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ #define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ #define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ #define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ #define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ #define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ #define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ #define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ #define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ #define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */ #define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00) #define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ ((PIN) == GPIO_Pin_1) || \ ((PIN) == GPIO_Pin_2) || \ ((PIN) == GPIO_Pin_3) || \ ((PIN) == GPIO_Pin_4) || \ ((PIN) == GPIO_Pin_5) || \ ((PIN) == GPIO_Pin_6) || \ ((PIN) == GPIO_Pin_7) || \ ((PIN) == GPIO_Pin_8) || \ ((PIN) == GPIO_Pin_9) || \ ((PIN) == GPIO_Pin_10) || \ ((PIN) == GPIO_Pin_11) || \ ((PIN) == GPIO_Pin_12) || \ ((PIN) == GPIO_Pin_13) || \ ((PIN) == GPIO_Pin_14) || \ ((PIN) == GPIO_Pin_15)) /** * @} */ /** @defgroup GPIO_Pin_sources * @{ */ #define GPIO_PinSource0 ((uint8_t)0x00) #define GPIO_PinSource1 ((uint8_t)0x01) #define GPIO_PinSource2 ((uint8_t)0x02) #define GPIO_PinSource3 ((uint8_t)0x03) #define GPIO_PinSource4 ((uint8_t)0x04) #define GPIO_PinSource5 ((uint8_t)0x05) #define GPIO_PinSource6 ((uint8_t)0x06) #define GPIO_PinSource7 ((uint8_t)0x07) #define GPIO_PinSource8 ((uint8_t)0x08) #define GPIO_PinSource9 ((uint8_t)0x09) #define GPIO_PinSource10 ((uint8_t)0x0A) #define GPIO_PinSource11 ((uint8_t)0x0B) #define GPIO_PinSource12 ((uint8_t)0x0C) #define GPIO_PinSource13 ((uint8_t)0x0D) #define GPIO_PinSource14 ((uint8_t)0x0E) #define GPIO_PinSource15 ((uint8_t)0x0F) #define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ ((PINSOURCE) == GPIO_PinSource1) || \ ((PINSOURCE) == GPIO_PinSource2) || \ ((PINSOURCE) == GPIO_PinSource3) || \ ((PINSOURCE) == GPIO_PinSource4) || \ ((PINSOURCE) == GPIO_PinSource5) || \ ((PINSOURCE) == GPIO_PinSource6) || \ ((PINSOURCE) == GPIO_PinSource7) || \ ((PINSOURCE) == GPIO_PinSource8) || \ ((PINSOURCE) == GPIO_PinSource9) || \ ((PINSOURCE) == GPIO_PinSource10) || \ ((PINSOURCE) == GPIO_PinSource11) || \ ((PINSOURCE) == GPIO_PinSource12) || \ ((PINSOURCE) == GPIO_PinSource13) || \ ((PINSOURCE) == GPIO_PinSource14) || \ ((PINSOURCE) == GPIO_PinSource15)) /** * @} */ /** @defgroup GPIO_Alternat_function_selection_define * @{ */ /** * @brief AF 0 selection */ #define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /*!< RTC 50/60 Hz Alternate Function mapping */ #define GPIO_AF_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */ #define GPIO_AF_RTC_AF1 ((uint8_t)0x00) /*!< RTC_AF1 Alternate Function mapping */ #define GPIO_AF_WKUP ((uint8_t)0x00) /*!< Wakeup (WKUP1, WKUP2 and WKUP3) Alternate Function mapping */ #define GPIO_AF_SWJ ((uint8_t)0x00) /*!< SWJ (SW and JTAG) Alternate Function mapping */ #define GPIO_AF_TRACE ((uint8_t)0x00) /*!< TRACE Alternate Function mapping */ /** * @brief AF 1 selection */ #define GPIO_AF_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */ /** * @brief AF 2 selection */ #define GPIO_AF_TIM3 ((uint8_t)0x02) /*!< TIM3 Alternate Function mapping */ #define GPIO_AF_TIM4 ((uint8_t)0x02) /*!< TIM4 Alternate Function mapping */ #define GPIO_AF_TIM5 ((uint8_t)0x02) /*!< TIM5 Alternate Function mapping */ /** * @brief AF 3 selection */ #define GPIO_AF_TIM9 ((uint8_t)0x03) /*!< TIM9 Alternate Function mapping */ #define GPIO_AF_TIM10 ((uint8_t)0x03) /*!< TIM10 Alternate Function mapping */ #define GPIO_AF_TIM11 ((uint8_t)0x03) /*!< TIM11 Alternate Function mapping */ /** * @brief AF 4 selection */ #define GPIO_AF_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */ #define GPIO_AF_I2C2 ((uint8_t)0x04) /*!< I2C2 Alternate Function mapping */ /** * @brief AF 5 selection */ #define GPIO_AF_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */ #define GPIO_AF_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */ /** * @brief AF 6 selection */ #define GPIO_AF_SPI3 ((uint8_t)0x06) /*!< SPI3 Alternate Function mapping */ /** * @brief AF 7 selection */ #define GPIO_AF_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */ #define GPIO_AF_USART2 ((uint8_t)0x07) /*!< USART2 Alternate Function mapping */ #define GPIO_AF_USART3 ((uint8_t)0x07) /*!< USART3 Alternate Function mapping */ /** * @brief AF 8 selection */ #define GPIO_AF_UART4 ((uint8_t)0x08) /*!< UART4 Alternate Function mapping */ #define GPIO_AF_UART5 ((uint8_t)0x08) /*!< UART5 Alternate Function mapping */ /** * @brief AF 10 selection */ #define GPIO_AF_USB ((uint8_t)0xA) /*!< USB Full speed device Alternate Function mapping */ /** * @brief AF 11 selection */ #define GPIO_AF_LCD ((uint8_t)0x0B) /*!< LCD Alternate Function mapping */ /** * @brief AF 12 selection */ #define GPIO_AF_FSMC ((uint8_t)0x0C) /*!< FSMC Alternate Function mapping */ #define GPIO_AF_SDIO ((uint8_t)0x0C) /*!< SDIO Alternate Function mapping */ /** * @brief AF 14 selection */ #define GPIO_AF_RI ((uint8_t)0x0E) /*!< RI Alternate Function mapping */ /** * @brief AF 15 selection */ #define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */ #define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_MCO) || \ ((AF) == GPIO_AF_RTC_AF1) || ((AF) == GPIO_AF_WKUP) || \ ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ ((AF) == GPIO_AF_TIM2) || ((AF)== GPIO_AF_TIM3) || \ ((AF) == GPIO_AF_TIM4) || ((AF)== GPIO_AF_TIM9) || \ ((AF) == GPIO_AF_TIM10) || ((AF)== GPIO_AF_TIM11) || \ ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ ((AF) == GPIO_AF_SPI1) || ((AF) == GPIO_AF_SPI2) || \ ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_USB) || \ ((AF) == GPIO_AF_LCD) || ((AF) == GPIO_AF_RI) || \ ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_SPI3) || \ ((AF) == GPIO_AF_UART4) || ((AF) == GPIO_AF_UART5) || \ ((AF) == GPIO_AF_FSMC) || ((AF) == GPIO_AF_SDIO) || \ ((AF) == GPIO_AF_EVENTOUT)) /** * @} */ /** @defgroup GPIO_Legacy * @{ */ #define GPIO_Mode_AIN GPIO_Mode_AN /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ /* Function used to set the GPIO configuration to the default reset state ****/ void GPIO_DeInit(GPIO_TypeDef* GPIOx); /* Initialization and Configuration functions *********************************/ void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); /* GPIO Read and Write functions **********************************************/ uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); /* GPIO Alternate functions configuration functions ***************************/ void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF); #ifdef __cplusplus } #endif #endif /*__STM32L1xx_GPIO_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/inc/stm32l1xx_i2c.h
New file @@ -0,0 +1,703 @@ /** ****************************************************************************** * @file stm32l1xx_i2c.h * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file contains all the functions prototypes for the I2C firmware * library. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L1xx_I2C_H #define __STM32L1xx_I2C_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @addtogroup I2C * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief I2C Init structure definition */ typedef struct { uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency. This parameter must be set to a value lower than 400kHz */ uint16_t I2C_Mode; /*!< Specifies the I2C mode. This parameter can be a value of @ref I2C_mode */ uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle. This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address. This parameter can be a 7-bit or 10-bit address. */ uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement. This parameter can be a value of @ref I2C_acknowledgement */ uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. This parameter can be a value of @ref I2C_acknowledged_address */ }I2C_InitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup I2C_Exported_Constants * @{ */ #define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ ((PERIPH) == I2C2)) /** @defgroup I2C_mode * @{ */ #define I2C_Mode_I2C ((uint16_t)0x0000) #define I2C_Mode_SMBusDevice ((uint16_t)0x0002) #define I2C_Mode_SMBusHost ((uint16_t)0x000A) #define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ ((MODE) == I2C_Mode_SMBusDevice) || \ ((MODE) == I2C_Mode_SMBusHost)) /** * @} */ /** @defgroup I2C_duty_cycle_in_fast_mode * @{ */ #define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ #define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ #define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \ ((CYCLE) == I2C_DutyCycle_2)) /** * @} */ /** @defgroup I2C_acknowledgement * @{ */ #define I2C_Ack_Enable ((uint16_t)0x0400) #define I2C_Ack_Disable ((uint16_t)0x0000) #define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \ ((STATE) == I2C_Ack_Disable)) /** * @} */ /** @defgroup I2C_transfer_direction * @{ */ #define I2C_Direction_Transmitter ((uint8_t)0x00) #define I2C_Direction_Receiver ((uint8_t)0x01) #define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ ((DIRECTION) == I2C_Direction_Receiver)) /** * @} */ /** @defgroup I2C_acknowledged_address * @{ */ #define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) #define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) #define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) /** * @} */ /** @defgroup I2C_registers * @{ */ #define I2C_Register_CR1 ((uint8_t)0x00) #define I2C_Register_CR2 ((uint8_t)0x04) #define I2C_Register_OAR1 ((uint8_t)0x08) #define I2C_Register_OAR2 ((uint8_t)0x0C) #define I2C_Register_DR ((uint8_t)0x10) #define I2C_Register_SR1 ((uint8_t)0x14) #define I2C_Register_SR2 ((uint8_t)0x18) #define I2C_Register_CCR ((uint8_t)0x1C) #define I2C_Register_TRISE ((uint8_t)0x20) #define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ ((REGISTER) == I2C_Register_CR2) || \ ((REGISTER) == I2C_Register_OAR1) || \ ((REGISTER) == I2C_Register_OAR2) || \ ((REGISTER) == I2C_Register_DR) || \ ((REGISTER) == I2C_Register_SR1) || \ ((REGISTER) == I2C_Register_SR2) || \ ((REGISTER) == I2C_Register_CCR) || \ ((REGISTER) == I2C_Register_TRISE)) /** * @} */ /** @defgroup I2C_SMBus_alert_pin_level * @{ */ #define I2C_SMBusAlert_Low ((uint16_t)0x2000) #define I2C_SMBusAlert_High ((uint16_t)0xDFFF) #define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \ ((ALERT) == I2C_SMBusAlert_High)) /** * @} */ /** @defgroup I2C_PEC_position * @{ */ #define I2C_PECPosition_Next ((uint16_t)0x0800) #define I2C_PECPosition_Current ((uint16_t)0xF7FF) #define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \ ((POSITION) == I2C_PECPosition_Current)) /** * @} */ /** @defgroup I2C_NACK_position * @{ */ #define I2C_NACKPosition_Next ((uint16_t)0x0800) #define I2C_NACKPosition_Current ((uint16_t)0xF7FF) #define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \ ((POSITION) == I2C_NACKPosition_Current)) /** * @} */ /** @defgroup I2C_interrupts_definition * @{ */ #define I2C_IT_BUF ((uint16_t)0x0400) #define I2C_IT_EVT ((uint16_t)0x0200) #define I2C_IT_ERR ((uint16_t)0x0100) #define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) /** * @} */ /** @defgroup I2C_interrupts_definition * @{ */ #define I2C_IT_SMBALERT ((uint32_t)0x01008000) #define I2C_IT_TIMEOUT ((uint32_t)0x01004000) #define I2C_IT_PECERR ((uint32_t)0x01001000) #define I2C_IT_OVR ((uint32_t)0x01000800) #define I2C_IT_AF ((uint32_t)0x01000400) #define I2C_IT_ARLO ((uint32_t)0x01000200) #define I2C_IT_BERR ((uint32_t)0x01000100) #define I2C_IT_TXE ((uint32_t)0x06000080) #define I2C_IT_RXNE ((uint32_t)0x06000040) #define I2C_IT_STOPF ((uint32_t)0x02000010) #define I2C_IT_ADD10 ((uint32_t)0x02000008) #define I2C_IT_BTF ((uint32_t)0x02000004) #define I2C_IT_ADDR ((uint32_t)0x02000002) #define I2C_IT_SB ((uint32_t)0x02000001) #define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) #define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \ ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \ ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \ ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \ ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \ ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \ ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB)) /** * @} */ /** @defgroup I2C_flags_definition * @{ */ /** * @brief SR2 register flags */ #define I2C_FLAG_DUALF ((uint32_t)0x00800000) #define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) #define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) #define I2C_FLAG_GENCALL ((uint32_t)0x00100000) #define I2C_FLAG_TRA ((uint32_t)0x00040000) #define I2C_FLAG_BUSY ((uint32_t)0x00020000) #define I2C_FLAG_MSL ((uint32_t)0x00010000) /** * @brief SR1 register flags */ #define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) #define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) #define I2C_FLAG_PECERR ((uint32_t)0x10001000) #define I2C_FLAG_OVR ((uint32_t)0x10000800) #define I2C_FLAG_AF ((uint32_t)0x10000400) #define I2C_FLAG_ARLO ((uint32_t)0x10000200) #define I2C_FLAG_BERR ((uint32_t)0x10000100) #define I2C_FLAG_TXE ((uint32_t)0x10000080) #define I2C_FLAG_RXNE ((uint32_t)0x10000040) #define I2C_FLAG_STOPF ((uint32_t)0x10000010) #define I2C_FLAG_ADD10 ((uint32_t)0x10000008) #define I2C_FLAG_BTF ((uint32_t)0x10000004) #define I2C_FLAG_ADDR ((uint32_t)0x10000002) #define I2C_FLAG_SB ((uint32_t)0x10000001) #define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) #define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \ ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \ ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \ ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \ ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \ ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \ ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \ ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \ ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \ ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \ ((FLAG) == I2C_FLAG_SB)) /** * @} */ /** @defgroup I2C_Events * @{ */ /** =============================================================================== I2C Master Events (Events grouped in order of communication) =============================================================================== */ /** * @brief Communication start * * After sending the START condition (I2C_GenerateSTART() function) the master * has to wait for this event. It means that the Start condition has been correctly * released on the I2C bus (the bus is free, no other devices is communicating). * */ /* --EV5 */ #define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ /** * @brief Address Acknowledge * * After checking on EV5 (start condition correctly released on the bus), the * master sends the address of the slave(s) with which it will communicate * (I2C_Send7bitAddress() function, it also determines the direction of the communication: * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges * his address. If an acknowledge is sent on the bus, one of the following events will * be set: * * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED * event is set. * * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED * is set * * 3) In case of 10-Bit addressing mode, the master (just after generating the START * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() * function). Then master should wait on EV9. It means that the 10-bit addressing * header has been correctly sent on the bus. Then master should send the second part of * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master * should wait for event EV6. * */ /* --EV6 */ #define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ #define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ /* --EV9 */ #define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ /** * @brief Communication events * * If a communication is established (START condition generated and slave address * acknowledged) then the master has to check on one of the following events for * communication procedures: * * 1) Master Receiver mode: The master has to wait on the event EV7 then to read * the data received from the slave (I2C_ReceiveData() function). * * 2) Master Transmitter mode: The master has to send data (I2C_SendData() * function) then to wait on event EV8 or EV8_2. * These two events are similar: * - EV8 means that the data has been written in the data register and is * being shifted out. * - EV8_2 means that the data has been physically shifted out and output * on the bus. * In most cases, using EV8 is sufficient for the application. * Using EV8_2 leads to a slower communication but ensure more reliable test. * EV8_2 is also more suitable than EV8 for testing on the last data transmission * (before Stop condition generation). * * @note In case the user software does not guarantee that this event EV7 is * managed before the current byte end of transfer, then user may check on EV7 * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). * In this case the communication may be slower. * */ /* Master RECEIVER mode -----------------------------*/ /* --EV7 */ #define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ /* Master TRANSMITTER mode --------------------------*/ /* --EV8 */ #define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ /* --EV8_2 */ #define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ /** =============================================================================== I2C Slave Events (Events grouped in order of communication) =============================================================================== */ /** * @brief Communication start events * * Wait on one of these events at the start of the communication. It means that * the I2C peripheral detected a Start condition on the bus (generated by master * device) followed by the peripheral address. The peripheral generates an ACK * condition on the bus (if the acknowledge feature is enabled through function * I2C_AcknowledgeConfig()) and the events listed above are set : * * 1) In normal case (only one address managed by the slave), when the address * sent by the master matches the own address of the peripheral (configured by * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set * (where XXX could be TRANSMITTER or RECEIVER). * * 2) In case the address sent by the master matches the second address of the * peripheral (configured by the function I2C_OwnAddress2Config() and enabled * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED * (where XXX could be TRANSMITTER or RECEIVER) are set. * * 3) In case the address sent by the master is General Call (address 0x00) and * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. * */ /* --EV1 (all the events below are variants of EV1) */ /* 1) Case of One Single Address managed by the slave */ #define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ #define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ /* 2) Case of Dual address managed by the slave */ #define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ #define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ /* 3) Case of General Call enabled for the slave */ #define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ /** * @brief Communication events * * Wait on one of these events when EV1 has already been checked and: * * - Slave RECEIVER mode: * - EV2: When the application is expecting a data byte to be received. * - EV4: When the application is expecting the end of the communication: master * sends a stop condition and data transmission is stopped. * * - Slave Transmitter mode: * - EV3: When a byte has been transmitted by the slave and the application is expecting * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be * used when the user software doesn't guarantee the EV3 is managed before the * current byte end of transfer. * - EV3_2: When the master sends a NACK in order to tell slave that data transmission * shall end (before sending the STOP condition). In this case slave has to stop sending * data bytes and expect a Stop condition on the bus. * * @note In case the user software does not guarantee that the event EV2 is * managed before the current byte end of transfer, then user may check on EV2 * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). * In this case the communication may be slower. * */ /* Slave RECEIVER mode --------------------------*/ /* --EV2 */ #define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ /* --EV4 */ #define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ /* Slave TRANSMITTER mode -----------------------*/ /* --EV3 */ #define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ #define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ /* --EV3_2 */ #define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ /* =============================================================================== End of Events Description =============================================================================== */ #define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \ ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \ ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \ ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \ ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \ ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \ ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE)) /** * @} */ /** @defgroup I2C_own_address1 * @{ */ #define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) /** * @} */ /** @defgroup I2C_clock_speed * @{ */ #define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ /* Function used to set the I2C configuration to the default reset state *****/ void I2C_DeInit(I2C_TypeDef* I2Cx); /* Initialization and Configuration functions *********************************/ void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); /* Data transfers functions ***************************************************/ void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition); /* PEC management functions ***************************************************/ void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); /* DMA transfers management functions *****************************************/ void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); /* Interrupts, events and flags management functions **************************/ uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); /* =============================================================================== I2C State Monitoring Functions =============================================================================== This I2C driver provides three different ways for I2C state monitoring depending on the application requirements and constraints: 1. Basic state monitoring (Using I2C_CheckEvent() function) ----------------------------------------------------------- It compares the status registers (SR1 and SR2) content to a given event (can be the combination of one or more flags). It returns SUCCESS if the current status includes the given flags and returns ERROR if one or more flags are missing in the current status. - When to use - This function is suitable for most applications as well as for startup activity since the events are fully described in the product reference manual (RM0038). - It is also suitable for users who need to define their own events. - Limitations - If an error occurs (ie. error flags are set besides to the monitored flags), the I2C_CheckEvent() function may return SUCCESS despite the communication hold or corrupted real state. In this case, it is advised to use error interrupts to monitor the error events and handle them in the interrupt IRQ handler. Note For error management, it is advised to use the following functions: - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. Where x is the peripheral instance (I2C1, I2C2 ...) - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the I2Cx_ER_IRQHandler() function in order to determine which error occurred. - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() and/or I2C_GenerateStop() in order to clear the error flag and source and return to correct communciation status. 2. Advanced state monitoring (Using the function I2C_GetLastEvent()) -------------------------------------------------------------------- Using the function I2C_GetLastEvent() which returns the image of both status registers in a single word (uint32_t) (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1). - When to use - This function is suitable for the same applications above but it allows to overcome the mentioned limitation of I2C_GetFlagStatus() function. - The returned value could be compared to events already defined in the library (stm32l1xx_i2c.h) or to custom values defined by user. This function is suitable when multiple flags are monitored at the same time. - At the opposite of I2C_CheckEvent() function, this function allows user to choose when an event is accepted (when all events flags are set and no other flags are set or just when the needed flags are set like I2C_CheckEvent() function. - Limitations - User may need to define his own events. - Same remark concerning the error management is applicable for this function if user decides to check only regular communication flags (and ignores error flags). 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus()) ----------------------------------------------------------------------- Using the function I2C_GetFlagStatus() which simply returns the status of one single flag (ie. I2C_FLAG_RXNE ...). - When to use - This function could be used for specific applications or in debug phase. - It is suitable when only one flag checking is needed (most I2C events are monitored through multiple flags). - Limitations: - When calling this function, the Status register is accessed. Some flags are cleared when the status register is accessed. So checking the status of one Flag, may clear other ones. - Function may need to be called twice or more in order to monitor one single event. For detailed description of Events, please refer to section I2C_Events in stm32l1xx_i2c.h file. */ /* =============================================================================== 1. Basic state monitoring =============================================================================== */ ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); /* =============================================================================== 2. Advanced state monitoring =============================================================================== */ uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); /* =============================================================================== 3. Flag-based state monitoring =============================================================================== */ FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); #ifdef __cplusplus } #endif #endif /*__STM32L1xx_I2C_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/inc/stm32l1xx_iwdg.h
New file @@ -0,0 +1,134 @@ /** ****************************************************************************** * @file stm32l1xx_iwdg.h * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file contains all the functions prototypes for the IWDG * firmware library. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L1xx_IWDG_H #define __STM32L1xx_IWDG_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @addtogroup IWDG * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup IWDG_Exported_Constants * @{ */ /** @defgroup IWDG_WriteAccess * @{ */ #define IWDG_WriteAccess_Enable ((uint16_t)0x5555) #define IWDG_WriteAccess_Disable ((uint16_t)0x0000) #define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ ((ACCESS) == IWDG_WriteAccess_Disable)) /** * @} */ /** @defgroup IWDG_prescaler * @{ */ #define IWDG_Prescaler_4 ((uint8_t)0x00) #define IWDG_Prescaler_8 ((uint8_t)0x01) #define IWDG_Prescaler_16 ((uint8_t)0x02) #define IWDG_Prescaler_32 ((uint8_t)0x03) #define IWDG_Prescaler_64 ((uint8_t)0x04) #define IWDG_Prescaler_128 ((uint8_t)0x05) #define IWDG_Prescaler_256 ((uint8_t)0x06) #define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ ((PRESCALER) == IWDG_Prescaler_8) || \ ((PRESCALER) == IWDG_Prescaler_16) || \ ((PRESCALER) == IWDG_Prescaler_32) || \ ((PRESCALER) == IWDG_Prescaler_64) || \ ((PRESCALER) == IWDG_Prescaler_128)|| \ ((PRESCALER) == IWDG_Prescaler_256)) /** * @} */ /** @defgroup IWDG_Flag * @{ */ #define IWDG_FLAG_PVU ((uint16_t)0x0001) #define IWDG_FLAG_RVU ((uint16_t)0x0002) #define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) #define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ /* Prescaler and Counter configuration functions ******************************/ void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); void IWDG_SetReload(uint16_t Reload); void IWDG_ReloadCounter(void); /* IWDG activation function ***************************************************/ void IWDG_Enable(void); /* Flag management function ***************************************************/ FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); #ifdef __cplusplus } #endif #endif /* __STM32L1xx_IWDG_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/inc/stm32l1xx_lcd.h
New file @@ -0,0 +1,452 @@ /** ****************************************************************************** * @file stm32l1xx_lcd.h * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file contains all the functions prototypes for the LCD firmware * library. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L1xx_LCD_H #define __STM32L1xx_LCD_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @addtogroup LCD * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief LCD Init structure definition */ typedef struct { uint32_t LCD_Prescaler; /*!< Configures the LCD Prescaler. This parameter can be one value of @ref LCD_Prescaler */ uint32_t LCD_Divider; /*!< Configures the LCD Divider. This parameter can be one value of @ref LCD_Divider */ uint32_t LCD_Duty; /*!< Configures the LCD Duty. This parameter can be one value of @ref LCD_Duty */ uint32_t LCD_Bias; /*!< Configures the LCD Bias. This parameter can be one value of @ref LCD_Bias */ uint32_t LCD_VoltageSource; /*!< Selects the LCD Voltage source. This parameter can be one value of @ref LCD_Voltage_Source */ }LCD_InitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup LCD_Exported_Constants * @{ */ /** @defgroup LCD_Prescaler * @{ */ #define LCD_Prescaler_1 ((uint32_t)0x00000000) /*!< CLKPS = LCDCLK */ #define LCD_Prescaler_2 ((uint32_t)0x00400000) /*!< CLKPS = LCDCLK/2 */ #define LCD_Prescaler_4 ((uint32_t)0x00800000) /*!< CLKPS = LCDCLK/4 */ #define LCD_Prescaler_8 ((uint32_t)0x00C00000) /*!< CLKPS = LCDCLK/8 */ #define LCD_Prescaler_16 ((uint32_t)0x01000000) /*!< CLKPS = LCDCLK/16 */ #define LCD_Prescaler_32 ((uint32_t)0x01400000) /*!< CLKPS = LCDCLK/32 */ #define LCD_Prescaler_64 ((uint32_t)0x01800000) /*!< CLKPS = LCDCLK/64 */ #define LCD_Prescaler_128 ((uint32_t)0x01C00000) /*!< CLKPS = LCDCLK/128 */ #define LCD_Prescaler_256 ((uint32_t)0x02000000) /*!< CLKPS = LCDCLK/256 */ #define LCD_Prescaler_512 ((uint32_t)0x02400000) /*!< CLKPS = LCDCLK/512 */ #define LCD_Prescaler_1024 ((uint32_t)0x02800000) /*!< CLKPS = LCDCLK/1024 */ #define LCD_Prescaler_2048 ((uint32_t)0x02C00000) /*!< CLKPS = LCDCLK/2048 */ #define LCD_Prescaler_4096 ((uint32_t)0x03000000) /*!< CLKPS = LCDCLK/4096 */ #define LCD_Prescaler_8192 ((uint32_t)0x03400000) /*!< CLKPS = LCDCLK/8192 */ #define LCD_Prescaler_16384 ((uint32_t)0x03800000) /*!< CLKPS = LCDCLK/16384 */ #define LCD_Prescaler_32768 ((uint32_t)0x03C00000) /*!< CLKPS = LCDCLK/32768 */ #define IS_LCD_PRESCALER(PRESCALER) (((PRESCALER) == LCD_Prescaler_1) || \ ((PRESCALER) == LCD_Prescaler_2) || \ ((PRESCALER) == LCD_Prescaler_4) || \ ((PRESCALER) == LCD_Prescaler_8) || \ ((PRESCALER) == LCD_Prescaler_16) || \ ((PRESCALER) == LCD_Prescaler_32) || \ ((PRESCALER) == LCD_Prescaler_64) || \ ((PRESCALER) == LCD_Prescaler_128) || \ ((PRESCALER) == LCD_Prescaler_256) || \ ((PRESCALER) == LCD_Prescaler_512) || \ ((PRESCALER) == LCD_Prescaler_1024) || \ ((PRESCALER) == LCD_Prescaler_2048) || \ ((PRESCALER) == LCD_Prescaler_4096) || \ ((PRESCALER) == LCD_Prescaler_8192) || \ ((PRESCALER) == LCD_Prescaler_16384) || \ ((PRESCALER) == LCD_Prescaler_32768)) /** * @} */ /** @defgroup LCD_Divider * @{ */ #define LCD_Divider_16 ((uint32_t)0x00000000) /*!< LCD frequency = CLKPS/16 */ #define LCD_Divider_17 ((uint32_t)0x00040000) /*!< LCD frequency = CLKPS/17 */ #define LCD_Divider_18 ((uint32_t)0x00080000) /*!< LCD frequency = CLKPS/18 */ #define LCD_Divider_19 ((uint32_t)0x000C0000) /*!< LCD frequency = CLKPS/19 */ #define LCD_Divider_20 ((uint32_t)0x00100000) /*!< LCD frequency = CLKPS/20 */ #define LCD_Divider_21 ((uint32_t)0x00140000) /*!< LCD frequency = CLKPS/21 */ #define LCD_Divider_22 ((uint32_t)0x00180000) /*!< LCD frequency = CLKPS/22 */ #define LCD_Divider_23 ((uint32_t)0x001C0000) /*!< LCD frequency = CLKPS/23 */ #define LCD_Divider_24 ((uint32_t)0x00200000) /*!< LCD frequency = CLKPS/24 */ #define LCD_Divider_25 ((uint32_t)0x00240000) /*!< LCD frequency = CLKPS/25 */ #define LCD_Divider_26 ((uint32_t)0x00280000) /*!< LCD frequency = CLKPS/26 */ #define LCD_Divider_27 ((uint32_t)0x002C0000) /*!< LCD frequency = CLKPS/27 */ #define LCD_Divider_28 ((uint32_t)0x00300000) /*!< LCD frequency = CLKPS/28 */ #define LCD_Divider_29 ((uint32_t)0x00340000) /*!< LCD frequency = CLKPS/29 */ #define LCD_Divider_30 ((uint32_t)0x00380000) /*!< LCD frequency = CLKPS/30 */ #define LCD_Divider_31 ((uint32_t)0x003C0000) /*!< LCD frequency = CLKPS/31 */ #define IS_LCD_DIVIDER(DIVIDER) (((DIVIDER) == LCD_Divider_16) || \ ((DIVIDER) == LCD_Divider_17) || \ ((DIVIDER) == LCD_Divider_18) || \ ((DIVIDER) == LCD_Divider_19) || \ ((DIVIDER) == LCD_Divider_20) || \ ((DIVIDER) == LCD_Divider_21) || \ ((DIVIDER) == LCD_Divider_22) || \ ((DIVIDER) == LCD_Divider_23) || \ ((DIVIDER) == LCD_Divider_24) || \ ((DIVIDER) == LCD_Divider_25) || \ ((DIVIDER) == LCD_Divider_26) || \ ((DIVIDER) == LCD_Divider_27) || \ ((DIVIDER) == LCD_Divider_28) || \ ((DIVIDER) == LCD_Divider_29) || \ ((DIVIDER) == LCD_Divider_30) || \ ((DIVIDER) == LCD_Divider_31)) /** * @} */ /** @defgroup LCD_Duty * @{ */ #define LCD_Duty_Static ((uint32_t)0x00000000) /*!< Static duty */ #define LCD_Duty_1_2 ((uint32_t)0x00000004) /*!< 1/2 duty */ #define LCD_Duty_1_3 ((uint32_t)0x00000008) /*!< 1/3 duty */ #define LCD_Duty_1_4 ((uint32_t)0x0000000C) /*!< 1/4 duty */ #define LCD_Duty_1_8 ((uint32_t)0x00000010) /*!< 1/4 duty */ #define IS_LCD_DUTY(DUTY) (((DUTY) == LCD_Duty_Static) || \ ((DUTY) == LCD_Duty_1_2) || \ ((DUTY) == LCD_Duty_1_3) || \ ((DUTY) == LCD_Duty_1_4) || \ ((DUTY) == LCD_Duty_1_8)) /** * @} */ /** @defgroup LCD_Bias * @{ */ #define LCD_Bias_1_4 ((uint32_t)0x00000000) /*!< 1/4 Bias */ #define LCD_Bias_1_2 LCD_CR_BIAS_0 /*!< 1/2 Bias */ #define LCD_Bias_1_3 LCD_CR_BIAS_1 /*!< 1/3 Bias */ #define IS_LCD_BIAS(BIAS) (((BIAS) == LCD_Bias_1_4) || \ ((BIAS) == LCD_Bias_1_2) || \ ((BIAS) == LCD_Bias_1_3)) /** * @} */ /** @defgroup LCD_Voltage_Source * @{ */ #define LCD_VoltageSource_Internal ((uint32_t)0x00000000) /*!< Internal voltage source for the LCD */ #define LCD_VoltageSource_External LCD_CR_VSEL /*!< External voltage source for the LCD */ #define IS_LCD_VOLTAGE_SOURCE(SOURCE) (((SOURCE) == LCD_VoltageSource_Internal) || \ ((SOURCE) == LCD_VoltageSource_External)) /** * @} */ /** @defgroup LCD_Interrupts * @{ */ #define LCD_IT_SOF LCD_FCR_SOFIE #define LCD_IT_UDD LCD_FCR_UDDIE #define IS_LCD_IT(IT) ((((IT) & (uint32_t)0xFFFFFFF5) == 0x00) && ((IT) != 0x00)) #define IS_LCD_GET_IT(IT) (((IT) == LCD_IT_SOF) || ((IT) == LCD_IT_UDD)) /** * @} */ /** @defgroup LCD_PulseOnDuration * @{ */ #define LCD_PulseOnDuration_0 ((uint32_t)0x00000000) /*!< Pulse ON duration = 0 pulse */ #define LCD_PulseOnDuration_1 ((uint32_t)0x00000010) /*!< Pulse ON duration = 1/CK_PS */ #define LCD_PulseOnDuration_2 ((uint32_t)0x00000020) /*!< Pulse ON duration = 2/CK_PS */ #define LCD_PulseOnDuration_3 ((uint32_t)0x00000030) /*!< Pulse ON duration = 3/CK_PS */ #define LCD_PulseOnDuration_4 ((uint32_t)0x00000040) /*!< Pulse ON duration = 4/CK_PS */ #define LCD_PulseOnDuration_5 ((uint32_t)0x00000050) /*!< Pulse ON duration = 5/CK_PS */ #define LCD_PulseOnDuration_6 ((uint32_t)0x00000060) /*!< Pulse ON duration = 6/CK_PS */ #define LCD_PulseOnDuration_7 ((uint32_t)0x00000070) /*!< Pulse ON duration = 7/CK_PS */ #define IS_LCD_PULSE_ON_DURATION(DURATION) (((DURATION) == LCD_PulseOnDuration_0) || \ ((DURATION) == LCD_PulseOnDuration_1) || \ ((DURATION) == LCD_PulseOnDuration_2) || \ ((DURATION) == LCD_PulseOnDuration_3) || \ ((DURATION) == LCD_PulseOnDuration_4) || \ ((DURATION) == LCD_PulseOnDuration_5) || \ ((DURATION) == LCD_PulseOnDuration_6) || \ ((DURATION) == LCD_PulseOnDuration_7)) /** * @} */ /** @defgroup LCD_DeadTime * @{ */ #define LCD_DeadTime_0 ((uint32_t)0x00000000) /*!< No dead Time */ #define LCD_DeadTime_1 ((uint32_t)0x00000080) /*!< One Phase between different couple of Frame */ #define LCD_DeadTime_2 ((uint32_t)0x00000100) /*!< Two Phase between different couple of Frame */ #define LCD_DeadTime_3 ((uint32_t)0x00000180) /*!< Three Phase between different couple of Frame */ #define LCD_DeadTime_4 ((uint32_t)0x00000200) /*!< Four Phase between different couple of Frame */ #define LCD_DeadTime_5 ((uint32_t)0x00000280) /*!< Five Phase between different couple of Frame */ #define LCD_DeadTime_6 ((uint32_t)0x00000300) /*!< Six Phase between different couple of Frame */ #define LCD_DeadTime_7 ((uint32_t)0x00000380) /*!< Seven Phase between different couple of Frame */ #define IS_LCD_DEAD_TIME(TIME) (((TIME) == LCD_DeadTime_0) || \ ((TIME) == LCD_DeadTime_1) || \ ((TIME) == LCD_DeadTime_2) || \ ((TIME) == LCD_DeadTime_3) || \ ((TIME) == LCD_DeadTime_4) || \ ((TIME) == LCD_DeadTime_5) || \ ((TIME) == LCD_DeadTime_6) || \ ((TIME) == LCD_DeadTime_7)) /** * @} */ /** @defgroup LCD_BlinkMode * @{ */ #define LCD_BlinkMode_Off ((uint32_t)0x00000000) /*!< Blink disabled */ #define LCD_BlinkMode_SEG0_COM0 ((uint32_t)0x00010000) /*!< Blink enabled on SEG[0], COM[0] (1 pixel) */ #define LCD_BlinkMode_SEG0_AllCOM ((uint32_t)0x00020000) /*!< Blink enabled on SEG[0], all COM (up to 8 pixels according to the programmed duty) */ #define LCD_BlinkMode_AllSEG_AllCOM ((uint32_t)0x00030000) /*!< Blink enabled on all SEG and all COM (all pixels) */ #define IS_LCD_BLINK_MODE(MODE) (((MODE) == LCD_BlinkMode_Off) || \ ((MODE) == LCD_BlinkMode_SEG0_COM0) || \ ((MODE) == LCD_BlinkMode_SEG0_AllCOM) || \ ((MODE) == LCD_BlinkMode_AllSEG_AllCOM)) /** * @} */ /** @defgroup LCD_BlinkFrequency * @{ */ #define LCD_BlinkFrequency_Div8 ((uint32_t)0x00000000) /*!< The Blink frequency = fLCD/8 */ #define LCD_BlinkFrequency_Div16 ((uint32_t)0x00002000) /*!< The Blink frequency = fLCD/16 */ #define LCD_BlinkFrequency_Div32 ((uint32_t)0x00004000) /*!< The Blink frequency = fLCD/32 */ #define LCD_BlinkFrequency_Div64 ((uint32_t)0x00006000) /*!< The Blink frequency = fLCD/64 */ #define LCD_BlinkFrequency_Div128 ((uint32_t)0x00008000) /*!< The Blink frequency = fLCD/128 */ #define LCD_BlinkFrequency_Div256 ((uint32_t)0x0000A000) /*!< The Blink frequency = fLCD/256 */ #define LCD_BlinkFrequency_Div512 ((uint32_t)0x0000C000) /*!< The Blink frequency = fLCD/512 */ #define LCD_BlinkFrequency_Div1024 ((uint32_t)0x0000E000) /*!< The Blink frequency = fLCD/1024 */ #define IS_LCD_BLINK_FREQUENCY(FREQUENCY) (((FREQUENCY) == LCD_BlinkFrequency_Div8) || \ ((FREQUENCY) == LCD_BlinkFrequency_Div16) || \ ((FREQUENCY) == LCD_BlinkFrequency_Div32) || \ ((FREQUENCY) == LCD_BlinkFrequency_Div64) || \ ((FREQUENCY) == LCD_BlinkFrequency_Div128) || \ ((FREQUENCY) == LCD_BlinkFrequency_Div256) || \ ((FREQUENCY) == LCD_BlinkFrequency_Div512) || \ ((FREQUENCY) == LCD_BlinkFrequency_Div1024)) /** * @} */ /** @defgroup LCD_Contrast * @{ */ #define LCD_Contrast_Level_0 ((uint32_t)0x00000000) /*!< Maximum Voltage = 2.60V */ #define LCD_Contrast_Level_1 ((uint32_t)0x00000400) /*!< Maximum Voltage = 2.73V */ #define LCD_Contrast_Level_2 ((uint32_t)0x00000800) /*!< Maximum Voltage = 2.86V */ #define LCD_Contrast_Level_3 ((uint32_t)0x00000C00) /*!< Maximum Voltage = 2.99V */ #define LCD_Contrast_Level_4 ((uint32_t)0x00001000) /*!< Maximum Voltage = 3.12V */ #define LCD_Contrast_Level_5 ((uint32_t)0x00001400) /*!< Maximum Voltage = 3.25V */ #define LCD_Contrast_Level_6 ((uint32_t)0x00001800) /*!< Maximum Voltage = 3.38V */ #define LCD_Contrast_Level_7 ((uint32_t)0x00001C00) /*!< Maximum Voltage = 3.51V */ #define IS_LCD_CONTRAST(CONTRAST) (((CONTRAST) == LCD_Contrast_Level_0) || \ ((CONTRAST) == LCD_Contrast_Level_1) || \ ((CONTRAST) == LCD_Contrast_Level_2) || \ ((CONTRAST) == LCD_Contrast_Level_3) || \ ((CONTRAST) == LCD_Contrast_Level_4) || \ ((CONTRAST) == LCD_Contrast_Level_5) || \ ((CONTRAST) == LCD_Contrast_Level_6) || \ ((CONTRAST) == LCD_Contrast_Level_7)) /** * @} */ /** @defgroup LCD_Flag * @{ */ #define LCD_FLAG_ENS LCD_SR_ENS #define LCD_FLAG_SOF LCD_SR_SOF #define LCD_FLAG_UDR LCD_SR_UDR #define LCD_FLAG_UDD LCD_SR_UDD #define LCD_FLAG_RDY LCD_SR_RDY #define LCD_FLAG_FCRSF LCD_SR_FCRSR #define IS_LCD_GET_FLAG(FLAG) (((FLAG) == LCD_FLAG_ENS) || ((FLAG) == LCD_FLAG_SOF) || \ ((FLAG) == LCD_FLAG_UDR) || ((FLAG) == LCD_FLAG_UDD) || \ ((FLAG) == LCD_FLAG_RDY) || ((FLAG) == LCD_FLAG_FCRSF)) #define IS_LCD_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF5) == 0x00) && ((FLAG) != 0x00)) /** * @} */ /** @defgroup LCD_RAMRegister * @{ */ #define LCD_RAMRegister_0 ((uint32_t)0x00000000) /*!< LCD RAM Register 0 */ #define LCD_RAMRegister_1 ((uint32_t)0x00000001) /*!< LCD RAM Register 1 */ #define LCD_RAMRegister_2 ((uint32_t)0x00000002) /*!< LCD RAM Register 2 */ #define LCD_RAMRegister_3 ((uint32_t)0x00000003) /*!< LCD RAM Register 3 */ #define LCD_RAMRegister_4 ((uint32_t)0x00000004) /*!< LCD RAM Register 4 */ #define LCD_RAMRegister_5 ((uint32_t)0x00000005) /*!< LCD RAM Register 5 */ #define LCD_RAMRegister_6 ((uint32_t)0x00000006) /*!< LCD RAM Register 6 */ #define LCD_RAMRegister_7 ((uint32_t)0x00000007) /*!< LCD RAM Register 7 */ #define LCD_RAMRegister_8 ((uint32_t)0x00000008) /*!< LCD RAM Register 8 */ #define LCD_RAMRegister_9 ((uint32_t)0x00000009) /*!< LCD RAM Register 9 */ #define LCD_RAMRegister_10 ((uint32_t)0x0000000A) /*!< LCD RAM Register 10 */ #define LCD_RAMRegister_11 ((uint32_t)0x0000000B) /*!< LCD RAM Register 11 */ #define LCD_RAMRegister_12 ((uint32_t)0x0000000C) /*!< LCD RAM Register 12 */ #define LCD_RAMRegister_13 ((uint32_t)0x0000000D) /*!< LCD RAM Register 13 */ #define LCD_RAMRegister_14 ((uint32_t)0x0000000E) /*!< LCD RAM Register 14 */ #define LCD_RAMRegister_15 ((uint32_t)0x0000000F) /*!< LCD RAM Register 15 */ #define IS_LCD_RAM_REGISTER(REGISTER) (((REGISTER) == LCD_RAMRegister_0) || \ ((REGISTER) == LCD_RAMRegister_1) || \ ((REGISTER) == LCD_RAMRegister_2) || \ ((REGISTER) == LCD_RAMRegister_3) || \ ((REGISTER) == LCD_RAMRegister_4) || \ ((REGISTER) == LCD_RAMRegister_5) || \ ((REGISTER) == LCD_RAMRegister_6) || \ ((REGISTER) == LCD_RAMRegister_7) || \ ((REGISTER) == LCD_RAMRegister_8) || \ ((REGISTER) == LCD_RAMRegister_9) || \ ((REGISTER) == LCD_RAMRegister_10) || \ ((REGISTER) == LCD_RAMRegister_11) || \ ((REGISTER) == LCD_RAMRegister_12) || \ ((REGISTER) == LCD_RAMRegister_13) || \ ((REGISTER) == LCD_RAMRegister_14) || \ ((REGISTER) == LCD_RAMRegister_15)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ /* Function used to set the LCD configuration to the default reset state *****/ void LCD_DeInit(void); /* Initialization and Configuration functions *********************************/ void LCD_Init(LCD_InitTypeDef* LCD_InitStruct); void LCD_StructInit(LCD_InitTypeDef* LCD_InitStruct); void LCD_Cmd(FunctionalState NewState); void LCD_WaitForSynchro(void); void LCD_HighDriveCmd(FunctionalState NewState); void LCD_MuxSegmentCmd(FunctionalState NewState); void LCD_PulseOnDurationConfig(uint32_t LCD_PulseOnDuration); void LCD_DeadTimeConfig(uint32_t LCD_DeadTime); void LCD_BlinkConfig(uint32_t LCD_BlinkMode, uint32_t LCD_BlinkFrequency); void LCD_ContrastConfig(uint32_t LCD_Contrast); /* LCD RAM memory write functions *********************************************/ void LCD_Write(uint32_t LCD_RAMRegister, uint32_t LCD_Data); void LCD_UpdateDisplayRequest(void); /* Interrupts and flags management functions **********************************/ void LCD_ITConfig(uint32_t LCD_IT, FunctionalState NewState); FlagStatus LCD_GetFlagStatus(uint32_t LCD_FLAG); void LCD_ClearFlag(uint32_t LCD_FLAG); ITStatus LCD_GetITStatus(uint32_t LCD_IT); void LCD_ClearITPendingBit(uint32_t LCD_IT); #ifdef __cplusplus } #endif #endif /* __STM32L1xx_LCD_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/inc/stm32l1xx_opamp.h
New file @@ -0,0 +1,187 @@ /** ****************************************************************************** * @file stm32l1xx_opamp.h * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file contains all the functions prototypes for the operational * amplifiers (opamp) firmware library. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L1xx_OPAMP_H #define __STM32L1xx_OPAMP_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @addtogroup OPAMP * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup OPAMP_Exported_Constants * @{ */ /** @defgroup OPAMP_Selection * @{ */ #define OPAMP_Selection_OPAMP1 OPAMP_CSR_OPA1PD #define OPAMP_Selection_OPAMP2 OPAMP_CSR_OPA2PD #define OPAMP_Selection_OPAMP3 OPAMP_CSR_OPA3PD #define IS_OPAMP_ALL_PERIPH(PERIPH) (((PERIPH) == OPAMP_Selection_OPAMP1) || \ ((PERIPH) == OPAMP_Selection_OPAMP2) || \ ((PERIPH) == OPAMP_Selection_OPAMP3)) /** * @} */ /** @defgroup OPAMP_Switches * @{ */ /* OPAMP1 Switches */ #define OPAMP_OPAMP1Switch3 OPAMP_CSR_S3SEL1 /*!< OPAMP1 Switch 3 */ #define OPAMP_OPAMP1Switch4 OPAMP_CSR_S4SEL1 /*!< OPAMP1 Switch 4 */ #define OPAMP_OPAMP1Switch5 OPAMP_CSR_S5SEL1 /*!< OPAMP1 Switch 5 */ #define OPAMP_OPAMP1Switch6 OPAMP_CSR_S6SEL1 /*!< OPAMP1 Switch 6 */ #define OPAMP_OPAMP1SwitchANA OPAMP_CSR_ANAWSEL1 /*!< OPAMP1 Switch ANA */ /* OPAMP2 Switches */ #define OPAMP_OPAMP2Switch3 OPAMP_CSR_S3SEL2 /*!< OPAMP2 Switch 3 */ #define OPAMP_OPAMP2Switch4 OPAMP_CSR_S4SEL2 /*!< OPAMP2 Switch 4 */ #define OPAMP_OPAMP2Switch5 OPAMP_CSR_S5SEL2 /*!< OPAMP2 Switch 5 */ #define OPAMP_OPAMP2Switch6 OPAMP_CSR_S6SEL2 /*!< OPAMP2 Switch 6 */ #define OPAMP_OPAMP2Switch7 OPAMP_CSR_S7SEL2 /*!< OPAMP2 Switch 7 */ #define OPAMP_OPAMP2SwitchANA OPAMP_CSR_ANAWSEL2 /*!< OPAMP2 Switch ANA */ /* OPAMP3 Switches */ #define OPAMP_OPAMP3Switch3 OPAMP_CSR_S3SEL3 /*!< OPAMP3 Switch 3 */ #define OPAMP_OPAMP3Switch4 OPAMP_CSR_S4SEL3 /*!< OPAMP3 Switch 4 */ #define OPAMP_OPAMP3Switch5 OPAMP_CSR_S5SEL3 /*!< OPAMP3 Switch 5 */ #define OPAMP_OPAMP3Switch6 OPAMP_CSR_S6SEL3 /*!< OPAMP3 Switch 6 */ #define OPAMP_OPAMP3SwitchANA OPAMP_CSR_ANAWSEL3 /*!< OPAMP3 Switch ANA */ #define IS_OPAMP_SWITCH(SWITCH) ((((SWITCH) & (uint32_t)0xF0E1E1E1) == 0x00) && ((SWITCH) != 0x00)) /** * @} */ /** @defgroup OPAMP_Trimming * @{ */ #define OPAMP_Trimming_Factory ((uint32_t)0x00000000) /*!< Factory trimming */ #define OPAMP_Trimming_User OPAMP_OTR_OT_USER /*!< User trimming */ #define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_Trimming_Factory) || \ ((TRIMMING) == OPAMP_Trimming_User)) /** * @} */ /** @defgroup OPAMP_Input * @{ */ #define OPAMP_Input_NMOS OPAMP_CSR_OPA1CAL_H /*!< NMOS input */ #define OPAMP_Input_PMOS OPAMP_CSR_OPA1CAL_L /*!< PMOS input */ #define IS_OPAMP_INPUT(INPUT) (((INPUT) == OPAMP_Input_NMOS) || \ ((INPUT) == OPAMP_Input_PMOS)) /** * @} */ /** @defgroup OPAMP_TrimValue * @{ */ #define IS_OPAMP_TRIMMINGVALUE(VALUE) ((VALUE) <= 0x0000001F) /*!< Trimming value */ /** * @} */ /** @defgroup OPAMP_PowerRange * @{ */ #define OPAMP_PowerRange_Low ((uint32_t)0x00000000) /*!< Low power range is selected (VDDA is lower than 2.4V) */ #define OPAMP_PowerRange_High OPAMP_CSR_AOP_RANGE /*!< High power range is selected (VDDA is higher than 2.4V) */ #define IS_OPAMP_RANGE(RANGE) (((RANGE) == OPAMP_PowerRange_Low) || \ ((RANGE) == OPAMP_PowerRange_High)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ /* Initialization and Configuration functions *********************************/ void OPAMP_DeInit(void); void OPAMP_SwitchCmd(uint32_t OPAMP_OPAMPxSwitchy, FunctionalState NewState); void OPAMP_Cmd(uint32_t OPAMP_Selection, FunctionalState NewState); void OPAMP_LowPowerCmd(uint32_t OPAMP_Selection, FunctionalState NewState); void OPAMP_PowerRangeSelect(uint32_t OPAMP_PowerRange); /* Calibration functions ******************************************************/ void OPAMP_OffsetTrimmingModeSelect(uint32_t OPAMP_Trimming); void OPAMP_OffsetTrimConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue); void OPAMP_OffsetTrimLowPowerConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue); FlagStatus OPAMP_GetFlagStatus(uint32_t OPAMP_Selection); #ifdef __cplusplus } #endif #endif /*__STM32L1xx_OPAMP_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/inc/stm32l1xx_pwr.h
New file @@ -0,0 +1,213 @@ /** ****************************************************************************** * @file stm32l1xx_pwr.h * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file contains all the functions prototypes for the PWR firmware * library. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L1xx_PWR_H #define __STM32L1xx_PWR_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @addtogroup PWR * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup PWR_Exported_Constants * @{ */ /** @defgroup PWR_PVD_detection_level * @{ */ #define PWR_PVDLevel_0 PWR_CR_PLS_LEV0 #define PWR_PVDLevel_1 PWR_CR_PLS_LEV1 #define PWR_PVDLevel_2 PWR_CR_PLS_LEV2 #define PWR_PVDLevel_3 PWR_CR_PLS_LEV3 #define PWR_PVDLevel_4 PWR_CR_PLS_LEV4 #define PWR_PVDLevel_5 PWR_CR_PLS_LEV5 #define PWR_PVDLevel_6 PWR_CR_PLS_LEV6 #define PWR_PVDLevel_7 PWR_CR_PLS_LEV7 /* External input analog voltage (Compare internally to VREFINT) */ #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \ ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \ ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \ ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7)) /** * @} */ /** @defgroup PWR_WakeUp_Pins * @{ */ #define PWR_WakeUpPin_1 ((uint32_t)0x00000000) #define PWR_WakeUpPin_2 ((uint32_t)0x00000004) #define PWR_WakeUpPin_3 ((uint32_t)0x00000008) #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || \ ((PIN) == PWR_WakeUpPin_2) || \ ((PIN) == PWR_WakeUpPin_3)) /** * @} */ /** @defgroup PWR_Voltage_Scaling_Ranges * @{ */ #define PWR_VoltageScaling_Range1 PWR_CR_VOS_0 #define PWR_VoltageScaling_Range2 PWR_CR_VOS_1 #define PWR_VoltageScaling_Range3 PWR_CR_VOS #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_VoltageScaling_Range1) || \ ((RANGE) == PWR_VoltageScaling_Range2) || \ ((RANGE) == PWR_VoltageScaling_Range3)) /** * @} */ /** @defgroup PWR_Regulator_state_is_Sleep_STOP_mode * @{ */ #define PWR_Regulator_ON ((uint32_t)0x00000000) #define PWR_Regulator_LowPower PWR_CR_LPSDSR #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ ((REGULATOR) == PWR_Regulator_LowPower)) /** * @} */ /** @defgroup PWR_SLEEP_mode_entry * @{ */ #define PWR_SLEEPEntry_WFI ((uint8_t)0x01) #define PWR_SLEEPEntry_WFE ((uint8_t)0x02) #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE)) /** * @} */ /** @defgroup PWR_STOP_mode_entry * @{ */ #define PWR_STOPEntry_WFI ((uint8_t)0x01) #define PWR_STOPEntry_WFE ((uint8_t)0x02) #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) /** * @} */ /** @defgroup PWR_Flag * @{ */ #define PWR_FLAG_WU PWR_CSR_WUF #define PWR_FLAG_SB PWR_CSR_SBF #define PWR_FLAG_PVDO PWR_CSR_PVDO #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF #define PWR_FLAG_VOS PWR_CSR_VOSF #define PWR_FLAG_REGLP PWR_CSR_REGLPF #define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY) || \ ((FLAG) == PWR_FLAG_VOS) || ((FLAG) == PWR_FLAG_REGLP)) #define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ /* Function used to set the PWR configuration to the default reset state ******/ void PWR_DeInit(void); /* RTC Domain Access function *************************************************/ void PWR_RTCAccessCmd(FunctionalState NewState); /* PVD configuration functions ************************************************/ void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); void PWR_PVDCmd(FunctionalState NewState); /* WakeUp pins configuration functions ****************************************/ void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState); /* Ultra Low Power mode configuration functions *******************************/ void PWR_FastWakeUpCmd(FunctionalState NewState); void PWR_UltraLowPowerCmd(FunctionalState NewState); /* Voltage Scaling configuration functions ************************************/ void PWR_VoltageScalingConfig(uint32_t PWR_VoltageScaling); /* Low Power modes configuration functions ************************************/ void PWR_EnterLowPowerRunMode(FunctionalState NewState); void PWR_EnterSleepMode(uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry); void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); void PWR_EnterSTANDBYMode(void); /* Flags management functions *************************************************/ FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); void PWR_ClearFlag(uint32_t PWR_FLAG); #ifdef __cplusplus } #endif #endif /* __STM32L1xx_PWR_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/inc/stm32l1xx_rcc.h
New file @@ -0,0 +1,488 @@ /** ****************************************************************************** * @file stm32l1xx_rcc.h * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file contains all the functions prototypes for the RCC * firmware library. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L1xx_RCC_H #define __STM32L1xx_RCC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @addtogroup RCC * @{ */ /* Exported types ------------------------------------------------------------*/ typedef struct { uint32_t SYSCLK_Frequency; uint32_t HCLK_Frequency; uint32_t PCLK1_Frequency; uint32_t PCLK2_Frequency; }RCC_ClocksTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup RCC_Exported_Constants * @{ */ /** @defgroup RCC_HSE_configuration * @{ */ #define RCC_HSE_OFF ((uint8_t)0x00) #define RCC_HSE_ON ((uint8_t)0x01) #define RCC_HSE_Bypass ((uint8_t)0x05) #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ ((HSE) == RCC_HSE_Bypass)) /** * @} */ /** @defgroup RCC_MSI_Clock_Range * @{ */ #define RCC_MSIRange_0 RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz */ #define RCC_MSIRange_1 RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz */ #define RCC_MSIRange_2 RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */ #define RCC_MSIRange_3 RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */ #define RCC_MSIRange_4 RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz */ #define RCC_MSIRange_5 RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz */ #define RCC_MSIRange_6 RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz */ #define IS_RCC_MSI_CLOCK_RANGE(RANGE) (((RANGE) == RCC_MSIRange_0) || \ ((RANGE) == RCC_MSIRange_1) || \ ((RANGE) == RCC_MSIRange_2) || \ ((RANGE) == RCC_MSIRange_3) || \ ((RANGE) == RCC_MSIRange_4) || \ ((RANGE) == RCC_MSIRange_5) || \ ((RANGE) == RCC_MSIRange_6)) /** * @} */ /** @defgroup RCC_PLL_Clock_Source * @{ */ #define RCC_PLLSource_HSI ((uint8_t)0x00) #define RCC_PLLSource_HSE ((uint8_t)0x01) #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \ ((SOURCE) == RCC_PLLSource_HSE)) /** * @} */ /** @defgroup RCC_PLL_Multiplication_Factor * @{ */ #define RCC_PLLMul_3 ((uint8_t)0x00) #define RCC_PLLMul_4 ((uint8_t)0x04) #define RCC_PLLMul_6 ((uint8_t)0x08) #define RCC_PLLMul_8 ((uint8_t)0x0C) #define RCC_PLLMul_12 ((uint8_t)0x10) #define RCC_PLLMul_16 ((uint8_t)0x14) #define RCC_PLLMul_24 ((uint8_t)0x18) #define RCC_PLLMul_32 ((uint8_t)0x1C) #define RCC_PLLMul_48 ((uint8_t)0x20) #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_3) || ((MUL) == RCC_PLLMul_4) || \ ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_8) || \ ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_16) || \ ((MUL) == RCC_PLLMul_24) || ((MUL) == RCC_PLLMul_32) || \ ((MUL) == RCC_PLLMul_48)) /** * @} */ /** @defgroup RCC_PLL_Divider_Factor * @{ */ #define RCC_PLLDiv_2 ((uint8_t)0x40) #define RCC_PLLDiv_3 ((uint8_t)0x80) #define RCC_PLLDiv_4 ((uint8_t)0xC0) #define IS_RCC_PLL_DIV(DIV) (((DIV) == RCC_PLLDiv_2) || ((DIV) == RCC_PLLDiv_3) || \ ((DIV) == RCC_PLLDiv_4)) /** * @} */ /** @defgroup RCC_System_Clock_Source * @{ */ #define RCC_SYSCLKSource_MSI RCC_CFGR_SW_MSI #define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI #define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE #define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_MSI) || \ ((SOURCE) == RCC_SYSCLKSource_HSI) || \ ((SOURCE) == RCC_SYSCLKSource_HSE) || \ ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) /** * @} */ /** @defgroup RCC_AHB_Clock_Source * @{ */ #define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1 #define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2 #define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4 #define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8 #define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16 #define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64 #define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128 #define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256 #define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ ((HCLK) == RCC_SYSCLK_Div512)) /** * @} */ /** @defgroup RCC_APB1_APB2_Clock_Source * @{ */ #define RCC_HCLK_Div1 RCC_CFGR_PPRE1_DIV1 #define RCC_HCLK_Div2 RCC_CFGR_PPRE1_DIV2 #define RCC_HCLK_Div4 RCC_CFGR_PPRE1_DIV4 #define RCC_HCLK_Div8 RCC_CFGR_PPRE1_DIV8 #define RCC_HCLK_Div16 RCC_CFGR_PPRE1_DIV16 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ ((PCLK) == RCC_HCLK_Div16)) /** * @} */ /** @defgroup RCC_Interrupt_Source * @{ */ #define RCC_IT_LSIRDY ((uint8_t)0x01) #define RCC_IT_LSERDY ((uint8_t)0x02) #define RCC_IT_HSIRDY ((uint8_t)0x04) #define RCC_IT_HSERDY ((uint8_t)0x08) #define RCC_IT_PLLRDY ((uint8_t)0x10) #define RCC_IT_MSIRDY ((uint8_t)0x20) #define RCC_IT_LSECSS ((uint8_t)0x40) #define RCC_IT_CSS ((uint8_t)0x80) #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_MSIRDY) || \ ((IT) == RCC_IT_CSS) || ((IT) == RCC_IT_LSECSS)) #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x00) == 0x00) && ((IT) != 0x00)) /** * @} */ /** @defgroup RCC_LSE_Configuration * @{ */ #define RCC_LSE_OFF ((uint8_t)0x00) #define RCC_LSE_ON ((uint8_t)0x01) #define RCC_LSE_Bypass ((uint8_t)0x05) #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ ((LSE) == RCC_LSE_Bypass)) /** * @} */ /** @defgroup RCC_RTC_Clock_Source * @{ */ #define RCC_RTCCLKSource_LSE RCC_CSR_RTCSEL_LSE #define RCC_RTCCLKSource_LSI RCC_CSR_RTCSEL_LSI #define RCC_RTCCLKSource_HSE_Div2 RCC_CSR_RTCSEL_HSE #define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_0) #define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_1) #define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE) #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ ((SOURCE) == RCC_RTCCLKSource_LSI) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div16)) /** * @} */ /** @defgroup RCC_AHB_Peripherals * @{ */ #define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN #define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN #define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN #define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN #define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN #define RCC_AHBPeriph_GPIOH RCC_AHBENR_GPIOHEN #define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN #define RCC_AHBPeriph_GPIOG RCC_AHBENR_GPIOGEN #define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN #define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN #define RCC_AHBPeriph_SRAM RCC_AHBLPENR_SRAMLPEN #define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN #define RCC_AHBPeriph_DMA2 RCC_AHBENR_DMA2EN #define RCC_AHBPeriph_AES RCC_AHBENR_AESEN #define RCC_AHBPeriph_FSMC RCC_AHBENR_FSMCEN #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xB4FF6F00) == 0x00) && ((PERIPH) != 0x00)) #define IS_RCC_AHB_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0xB4FF6F00) == 0x00) && ((PERIPH) != 0x00)) /** * @} */ /** @defgroup RCC_APB2_Peripherals * @{ */ #define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN #define RCC_APB2Periph_TIM9 RCC_APB2ENR_TIM9EN #define RCC_APB2Periph_TIM10 RCC_APB2ENR_TIM10EN #define RCC_APB2Periph_TIM11 RCC_APB2ENR_TIM11EN #define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN #define RCC_APB2Periph_SDIO RCC_APB2ENR_SDIOEN #define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN #define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFA5E2) == 0x00) && ((PERIPH) != 0x00)) /** * @} */ /** @defgroup RCC_APB1_Peripherals * @{ */ #define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN #define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN #define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN #define RCC_APB1Periph_TIM5 RCC_APB1ENR_TIM5EN #define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN #define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN #define RCC_APB1Periph_LCD RCC_APB1ENR_LCDEN #define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN #define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN #define RCC_APB1Periph_SPI3 RCC_APB1ENR_SPI3EN #define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN #define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN #define RCC_APB1Periph_UART4 RCC_APB1ENR_UART4EN #define RCC_APB1Periph_UART5 RCC_APB1ENR_UART5EN #define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN #define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN #define RCC_APB1Periph_USB RCC_APB1ENR_USBEN #define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN #define RCC_APB1Periph_DAC RCC_APB1ENR_DACEN #define RCC_APB1Periph_COMP RCC_APB1ENR_COMPEN #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x4F0135C0) == 0x00) && ((PERIPH) != 0x00)) /** * @} */ /** @defgroup RCC_MCO_Clock_Source * @{ */ #define RCC_MCOSource_NoClock ((uint8_t)0x00) #define RCC_MCOSource_SYSCLK ((uint8_t)0x01) #define RCC_MCOSource_HSI ((uint8_t)0x02) #define RCC_MCOSource_MSI ((uint8_t)0x03) #define RCC_MCOSource_HSE ((uint8_t)0x04) #define RCC_MCOSource_PLLCLK ((uint8_t)0x05) #define RCC_MCOSource_LSI ((uint8_t)0x06) #define RCC_MCOSource_LSE ((uint8_t)0x07) #define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_SYSCLK) || \ ((SOURCE) == RCC_MCOSource_HSI) || ((SOURCE) == RCC_MCOSource_MSI) || \ ((SOURCE) == RCC_MCOSource_HSE) || ((SOURCE) == RCC_MCOSource_PLLCLK) || \ ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE)) /** * @} */ /** @defgroup RCC_MCO_Output_Divider * @{ */ #define RCC_MCODiv_1 ((uint8_t)0x00) #define RCC_MCODiv_2 ((uint8_t)0x10) #define RCC_MCODiv_4 ((uint8_t)0x20) #define RCC_MCODiv_8 ((uint8_t)0x30) #define RCC_MCODiv_16 ((uint8_t)0x40) #define IS_RCC_MCO_DIV(DIV) (((DIV) == RCC_MCODiv_1) || ((DIV) == RCC_MCODiv_2) || \ ((DIV) == RCC_MCODiv_4) || ((DIV) == RCC_MCODiv_8) || \ ((DIV) == RCC_MCODiv_16)) /** * @} */ /** @defgroup RCC_Flag * @{ */ #define RCC_FLAG_HSIRDY ((uint8_t)0x21) #define RCC_FLAG_MSIRDY ((uint8_t)0x29) #define RCC_FLAG_HSERDY ((uint8_t)0x31) #define RCC_FLAG_PLLRDY ((uint8_t)0x39) #define RCC_FLAG_LSERDY ((uint8_t)0x49) #define RCC_FLAG_LSECSS ((uint8_t)0x4A) #define RCC_FLAG_LSIRDY ((uint8_t)0x41) #define RCC_FLAG_OBLRST ((uint8_t)0x59) #define RCC_FLAG_PINRST ((uint8_t)0x5A) #define RCC_FLAG_PORRST ((uint8_t)0x5B) #define RCC_FLAG_SFTRST ((uint8_t)0x5C) #define RCC_FLAG_IWDGRST ((uint8_t)0x5D) #define RCC_FLAG_WWDGRST ((uint8_t)0x5E) #define RCC_FLAG_LPWRRST ((uint8_t)0x5F) #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ ((FLAG) == RCC_FLAG_MSIRDY) || ((FLAG) == RCC_FLAG_PLLRDY) || \ ((FLAG) == RCC_FLAG_LSERDY) || ((FLAG) == RCC_FLAG_LSIRDY) || \ ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \ ((FLAG) == RCC_FLAG_OBLRST)|| ((FLAG) == RCC_FLAG_LSECSS)) #define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) #define IS_RCC_MSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3F) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ /* Function used to set the RCC clock configuration to the default reset state */ void RCC_DeInit(void); /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ void RCC_HSEConfig(uint8_t RCC_HSE); ErrorStatus RCC_WaitForHSEStartUp(void); void RCC_MSIRangeConfig(uint32_t RCC_MSIRange); void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue); void RCC_MSICmd(FunctionalState NewState); void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); void RCC_HSICmd(FunctionalState NewState); void RCC_LSEConfig(uint8_t RCC_LSE); void RCC_LSICmd(FunctionalState NewState); void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv); void RCC_PLLCmd(FunctionalState NewState); void RCC_ClockSecuritySystemCmd(FunctionalState NewState); void RCC_LSEClockSecuritySystemCmd(FunctionalState NewState); void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv); /* System, AHB and APB busses clocks configuration functions ******************/ void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); uint8_t RCC_GetSYSCLKSource(void); void RCC_HCLKConfig(uint32_t RCC_SYSCLK); void RCC_PCLK1Config(uint32_t RCC_HCLK); void RCC_PCLK2Config(uint32_t RCC_HCLK); void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); /* Peripheral clocks configuration functions **********************************/ void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); void RCC_RTCCLKCmd(FunctionalState NewState); void RCC_RTCResetCmd(FunctionalState NewState); void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); /* Interrupts and flags management functions **********************************/ void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); void RCC_ClearFlag(void); ITStatus RCC_GetITStatus(uint8_t RCC_IT); void RCC_ClearITPendingBit(uint8_t RCC_IT); #ifdef __cplusplus } #endif #endif /* __STM32L1xx_RCC_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/inc/stm32l1xx_rtc.h
New file @@ -0,0 +1,896 @@ /** ****************************************************************************** * @file stm32l1xx_rtc.h * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file contains all the functions prototypes for the RTC firmware * library. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L1xx_RTC_H #define __STM32L1xx_RTC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @addtogroup RTC * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief RTC Init structures definition */ typedef struct { uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format. This parameter can be a value of @ref RTC_Hour_Formats */ uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. This parameter must be set to a value lower than 0x7F */ uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. This parameter must be set to a value lower than 0x7FFF */ }RTC_InitTypeDef; /** * @brief RTC Time structure definition */ typedef struct { uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour. This parameter must be set to a value in the 0-12 range if the RTC_HourFormat_12 is selected or 0-23 range if the RTC_HourFormat_24 is selected. */ uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes. This parameter must be set to a value in the 0-59 range. */ uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds. This parameter must be set to a value in the 0-59 range. */ uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time. This parameter can be a value of @ref RTC_AM_PM_Definitions */ }RTC_TimeTypeDef; /** * @brief RTC Date structure definition */ typedef struct { uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay. This parameter can be a value of @ref RTC_WeekDay_Definitions */ uint8_t RTC_Month; /*!< Specifies the RTC Date Month (in BCD format). This parameter can be a value of @ref RTC_Month_Date_Definitions */ uint8_t RTC_Date; /*!< Specifies the RTC Date. This parameter must be set to a value in the 1-31 range. */ uint8_t RTC_Year; /*!< Specifies the RTC Date Year. This parameter must be set to a value in the 0-99 range. */ }RTC_DateTypeDef; /** * @brief RTC Alarm structure definition */ typedef struct { RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */ uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks. This parameter can be a value of @ref RTC_AlarmMask_Definitions */ uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range. If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */ }RTC_AlarmTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup RTC_Exported_Constants * @{ */ /** @defgroup RTC_Hour_Formats * @{ */ #define RTC_HourFormat_24 ((uint32_t)0x00000000) #define RTC_HourFormat_12 ((uint32_t)0x00000040) #define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \ ((FORMAT) == RTC_HourFormat_24)) /** * @} */ /** @defgroup RTC_Asynchronous_Predivider * @{ */ #define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F) /** * @} */ /** @defgroup RTC_Synchronous_Predivider * @{ */ #define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF) /** * @} */ /** @defgroup RTC_Time_Definitions * @{ */ #define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12)) #define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23) #define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59) #define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59) /** * @} */ /** @defgroup RTC_AM_PM_Definitions * @{ */ #define RTC_H12_AM ((uint8_t)0x00) #define RTC_H12_PM ((uint8_t)0x40) #define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM)) /** * @} */ /** @defgroup RTC_Year_Date_Definitions * @{ */ #define IS_RTC_YEAR(YEAR) ((YEAR) <= 99) /** * @} */ /** @defgroup RTC_Month_Date_Definitions * @{ */ /* Coded in BCD format */ #define RTC_Month_January ((uint8_t)0x01) #define RTC_Month_February ((uint8_t)0x02) #define RTC_Month_March ((uint8_t)0x03) #define RTC_Month_April ((uint8_t)0x04) #define RTC_Month_May ((uint8_t)0x05) #define RTC_Month_June ((uint8_t)0x06) #define RTC_Month_July ((uint8_t)0x07) #define RTC_Month_August ((uint8_t)0x08) #define RTC_Month_September ((uint8_t)0x09) #define RTC_Month_October ((uint8_t)0x10) #define RTC_Month_November ((uint8_t)0x11) #define RTC_Month_December ((uint8_t)0x12) #define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12)) #define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31)) /** * @} */ /** @defgroup RTC_WeekDay_Definitions * @{ */ #define RTC_Weekday_Monday ((uint8_t)0x01) #define RTC_Weekday_Tuesday ((uint8_t)0x02) #define RTC_Weekday_Wednesday ((uint8_t)0x03) #define RTC_Weekday_Thursday ((uint8_t)0x04) #define RTC_Weekday_Friday ((uint8_t)0x05) #define RTC_Weekday_Saturday ((uint8_t)0x06) #define RTC_Weekday_Sunday ((uint8_t)0x07) #define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ ((WEEKDAY) == RTC_Weekday_Tuesday) || \ ((WEEKDAY) == RTC_Weekday_Wednesday) || \ ((WEEKDAY) == RTC_Weekday_Thursday) || \ ((WEEKDAY) == RTC_Weekday_Friday) || \ ((WEEKDAY) == RTC_Weekday_Saturday) || \ ((WEEKDAY) == RTC_Weekday_Sunday)) /** * @} */ /** @defgroup RTC_Alarm_Definitions * @{ */ #define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31)) #define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ ((WEEKDAY) == RTC_Weekday_Tuesday) || \ ((WEEKDAY) == RTC_Weekday_Wednesday) || \ ((WEEKDAY) == RTC_Weekday_Thursday) || \ ((WEEKDAY) == RTC_Weekday_Friday) || \ ((WEEKDAY) == RTC_Weekday_Saturday) || \ ((WEEKDAY) == RTC_Weekday_Sunday)) /** * @} */ /** @defgroup RTC_AlarmDateWeekDay_Definitions * @{ */ #define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000) #define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000) #define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \ ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay)) /** * @} */ /** @defgroup RTC_AlarmMask_Definitions * @{ */ #define RTC_AlarmMask_None ((uint32_t)0x00000000) #define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000) #define RTC_AlarmMask_Hours ((uint32_t)0x00800000) #define RTC_AlarmMask_Minutes ((uint32_t)0x00008000) #define RTC_AlarmMask_Seconds ((uint32_t)0x00000080) #define RTC_AlarmMask_All ((uint32_t)0x80808080) #define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) /** * @} */ /** @defgroup RTC_Alarms_Definitions * @{ */ #define RTC_Alarm_A ((uint32_t)0x00000100) #define RTC_Alarm_B ((uint32_t)0x00000200) #define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B)) #define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET) /** * @} */ /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions * @{ */ #define RTC_AlarmSubSecondMask_All ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm */ #define RTC_AlarmSubSecondMask_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm comparison. Only SS[0] is compared. */ #define RTC_AlarmSubSecondMask_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm comparison. Only SS[1:0] are compared */ #define RTC_AlarmSubSecondMask_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm comparison. Only SS[2:0] are compared */ #define RTC_AlarmSubSecondMask_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm comparison. Only SS[3:0] are compared */ #define RTC_AlarmSubSecondMask_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm comparison. Only SS[4:0] are compared */ #define RTC_AlarmSubSecondMask_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm comparison. Only SS[5:0] are compared */ #define RTC_AlarmSubSecondMask_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm comparison. Only SS[6:0] are compared */ #define RTC_AlarmSubSecondMask_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm comparison. Only SS[7:0] are compared */ #define RTC_AlarmSubSecondMask_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm comparison. Only SS[8:0] are compared */ #define RTC_AlarmSubSecondMask_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm comparison. Only SS[9:0] are compared */ #define RTC_AlarmSubSecondMask_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm comparison. Only SS[10:0] are compared */ #define RTC_AlarmSubSecondMask_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm comparison.Only SS[11:0] are compared */ #define RTC_AlarmSubSecondMask_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm comparison. Only SS[12:0] are compared */ #define RTC_AlarmSubSecondMask_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm comparison.Only SS[13:0] are compared */ #define RTC_AlarmSubSecondMask_None ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match to activate alarm. */ #define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14) || \ ((MASK) == RTC_AlarmSubSecondMask_None)) /** * @} */ /** @defgroup RTC_Alarm_Sub_Seconds_Value * @{ */ #define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF) /** * @} */ /** @defgroup RTC_Wakeup_Timer_Definitions * @{ */ #define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000) #define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001) #define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002) #define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003) #define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004) #define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006) #define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \ ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \ ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \ ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \ ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \ ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits)) #define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) /** * @} */ /** @defgroup RTC_Time_Stamp_Edges_definitions * @{ */ #define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000) #define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008) #define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \ ((EDGE) == RTC_TimeStampEdge_Falling)) /** * @} */ /** @defgroup RTC_Output_selection_Definitions * @{ */ #define RTC_Output_Disable ((uint32_t)0x00000000) #define RTC_Output_AlarmA ((uint32_t)0x00200000) #define RTC_Output_AlarmB ((uint32_t)0x00400000) #define RTC_Output_WakeUp ((uint32_t)0x00600000) #define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \ ((OUTPUT) == RTC_Output_AlarmA) || \ ((OUTPUT) == RTC_Output_AlarmB) || \ ((OUTPUT) == RTC_Output_WakeUp)) /** * @} */ /** @defgroup RTC_Output_Polarity_Definitions * @{ */ #define RTC_OutputPolarity_High ((uint32_t)0x00000000) #define RTC_OutputPolarity_Low ((uint32_t)0x00100000) #define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \ ((POL) == RTC_OutputPolarity_Low)) /** * @} */ /** @defgroup RTC_Coarse_Calibration_Definitions * @{ */ #define RTC_CalibSign_Positive ((uint32_t)0x00000000) #define RTC_CalibSign_Negative ((uint32_t)0x00000080) #define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \ ((SIGN) == RTC_CalibSign_Negative)) #define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20) /** * @} */ /** @defgroup RTC_Calib_Output_selection_Definitions * @{ */ #define RTC_CalibOutput_512Hz ((uint32_t)0x00000000) #define RTC_CalibOutput_1Hz ((uint32_t)0x00080000) #define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CalibOutput_512Hz) || \ ((OUTPUT) == RTC_CalibOutput_1Hz)) /** * @} */ /** @defgroup RTC_Smooth_calib_period_Definitions * @{ */ #define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation period is 32s, else 2exp20 RTCCLK seconds */ #define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation period is 16s, else 2exp19 RTCCLK seconds */ #define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation period is 8s, else 2exp18 RTCCLK seconds */ #define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \ ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \ ((PERIOD) == RTC_SmoothCalibPeriod_8sec)) /** * @} */ /** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions * @{ */ #define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added during a X -second window = Y - CALM[8:0]. with Y = 512, 256, 128 when X = 32, 16, 8 */ #define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited during a 32-second window = CALM[8:0]. */ #define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \ ((PLUS) == RTC_SmoothCalibPlusPulses_Reset)) /** * @} */ /** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions * @{ */ #define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF) /** * @} */ /** @defgroup RTC_DayLightSaving_Definitions * @{ */ #define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000) #define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000) #define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \ ((SAVE) == RTC_DayLightSaving_ADD1H)) #define RTC_StoreOperation_Reset ((uint32_t)0x00000000) #define RTC_StoreOperation_Set ((uint32_t)0x00040000) #define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \ ((OPERATION) == RTC_StoreOperation_Set)) /** * @} */ /** @defgroup RTC_Tamper_Trigger_Definitions * @{ */ #define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000) #define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001) #define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000) #define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001) #define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \ ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \ ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \ ((TRIGGER) == RTC_TamperTrigger_HighLevel)) /** * @} */ /** @defgroup RTC_Tamper_Filter_Definitions * @{ */ #define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */ #define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2 consecutive samples at the active level */ #define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4 consecutive samples at the active level */ #define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8 consecutive samples at the active leve. */ #define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \ ((FILTER) == RTC_TamperFilter_2Sample) || \ ((FILTER) == RTC_TamperFilter_4Sample) || \ ((FILTER) == RTC_TamperFilter_8Sample)) /** * @} */ /** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions * @{ */ #define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */ #define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */ #define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */ #define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */ #define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048 */ #define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024 */ #define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 512 */ #define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */ #define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256)) /** * @} */ /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions * @{ */ #define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ #define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */ #define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */ #define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */ #define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \ ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \ ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \ ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK)) /** * @} */ /** @defgroup RTC_Tamper_Pins_Definitions * @{ */ #define RTC_Tamper_1 RTC_TAFCR_TAMP1E /*!< Tamper detection enable for input tamper 1 */ #define RTC_Tamper_2 RTC_TAFCR_TAMP2E /*!< Tamper detection enable for input tamper 2 */ #define RTC_Tamper_3 RTC_TAFCR_TAMP3E /*!< Tamper detection enable for input tamper 3 */ #define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET)) /** * @} */ /** @defgroup RTC_Output_Type_ALARM_OUT * @{ */ #define RTC_OutputType_OpenDrain ((uint32_t)0x00000000) #define RTC_OutputType_PushPull ((uint32_t)0x00040000) #define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \ ((TYPE) == RTC_OutputType_PushPull)) /** * @} */ /** @defgroup RTC_Add_1_Second_Parameter_Definitions * @{ */ #define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000) #define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000) #define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \ ((SEL) == RTC_ShiftAdd1S_Set)) /** * @} */ /** @defgroup RTC_Substract_Fraction_Of_Second_Value * @{ */ #define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF) /** * @} */ /** @defgroup RTC_Backup_Registers_Definitions * @{ */ #define RTC_BKP_DR0 ((uint32_t)0x00000000) #define RTC_BKP_DR1 ((uint32_t)0x00000001) #define RTC_BKP_DR2 ((uint32_t)0x00000002) #define RTC_BKP_DR3 ((uint32_t)0x00000003) #define RTC_BKP_DR4 ((uint32_t)0x00000004) #define RTC_BKP_DR5 ((uint32_t)0x00000005) #define RTC_BKP_DR6 ((uint32_t)0x00000006) #define RTC_BKP_DR7 ((uint32_t)0x00000007) #define RTC_BKP_DR8 ((uint32_t)0x00000008) #define RTC_BKP_DR9 ((uint32_t)0x00000009) #define RTC_BKP_DR10 ((uint32_t)0x0000000A) #define RTC_BKP_DR11 ((uint32_t)0x0000000B) #define RTC_BKP_DR12 ((uint32_t)0x0000000C) #define RTC_BKP_DR13 ((uint32_t)0x0000000D) #define RTC_BKP_DR14 ((uint32_t)0x0000000E) #define RTC_BKP_DR15 ((uint32_t)0x0000000F) #define RTC_BKP_DR16 ((uint32_t)0x00000010) #define RTC_BKP_DR17 ((uint32_t)0x00000011) #define RTC_BKP_DR18 ((uint32_t)0x00000012) #define RTC_BKP_DR19 ((uint32_t)0x00000013) #define RTC_BKP_DR20 ((uint32_t)0x00000014) #define RTC_BKP_DR21 ((uint32_t)0x00000015) #define RTC_BKP_DR22 ((uint32_t)0x00000016) #define RTC_BKP_DR23 ((uint32_t)0x00000017) #define RTC_BKP_DR24 ((uint32_t)0x00000018) #define RTC_BKP_DR25 ((uint32_t)0x00000019) #define RTC_BKP_DR26 ((uint32_t)0x0000001A) #define RTC_BKP_DR27 ((uint32_t)0x0000001B) #define RTC_BKP_DR28 ((uint32_t)0x0000001C) #define RTC_BKP_DR29 ((uint32_t)0x0000001D) #define RTC_BKP_DR30 ((uint32_t)0x0000001E) #define RTC_BKP_DR31 ((uint32_t)0x0000001F) #define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \ ((BKP) == RTC_BKP_DR1) || \ ((BKP) == RTC_BKP_DR2) || \ ((BKP) == RTC_BKP_DR3) || \ ((BKP) == RTC_BKP_DR4) || \ ((BKP) == RTC_BKP_DR5) || \ ((BKP) == RTC_BKP_DR6) || \ ((BKP) == RTC_BKP_DR7) || \ ((BKP) == RTC_BKP_DR8) || \ ((BKP) == RTC_BKP_DR9) || \ ((BKP) == RTC_BKP_DR10) || \ ((BKP) == RTC_BKP_DR11) || \ ((BKP) == RTC_BKP_DR12) || \ ((BKP) == RTC_BKP_DR13) || \ ((BKP) == RTC_BKP_DR14) || \ ((BKP) == RTC_BKP_DR15) || \ ((BKP) == RTC_BKP_DR16) || \ ((BKP) == RTC_BKP_DR17) || \ ((BKP) == RTC_BKP_DR18) || \ ((BKP) == RTC_BKP_DR19) || \ ((BKP) == RTC_BKP_DR20) || \ ((BKP) == RTC_BKP_DR21) || \ ((BKP) == RTC_BKP_DR22) || \ ((BKP) == RTC_BKP_DR23) || \ ((BKP) == RTC_BKP_DR24) || \ ((BKP) == RTC_BKP_DR25) || \ ((BKP) == RTC_BKP_DR26) || \ ((BKP) == RTC_BKP_DR27) || \ ((BKP) == RTC_BKP_DR28) || \ ((BKP) == RTC_BKP_DR29) || \ ((BKP) == RTC_BKP_DR30) || \ ((BKP) == RTC_BKP_DR31)) /** * @} */ /** @defgroup RTC_Input_parameter_format_definitions * @{ */ #define RTC_Format_BIN ((uint32_t)0x000000000) #define RTC_Format_BCD ((uint32_t)0x000000001) #define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD)) /** * @} */ /** @defgroup RTC_Flags_Definitions * @{ */ #define RTC_FLAG_RECALPF ((uint32_t)0x00010000) #define RTC_FLAG_TAMP3F ((uint32_t)0x00008000) #define RTC_FLAG_TAMP2F ((uint32_t)0x00004000) #define RTC_FLAG_TAMP1F ((uint32_t)0x00002000) #define RTC_FLAG_TSOVF ((uint32_t)0x00001000) #define RTC_FLAG_TSF ((uint32_t)0x00000800) #define RTC_FLAG_WUTF ((uint32_t)0x00000400) #define RTC_FLAG_ALRBF ((uint32_t)0x00000200) #define RTC_FLAG_ALRAF ((uint32_t)0x00000100) #define RTC_FLAG_INITF ((uint32_t)0x00000040) #define RTC_FLAG_RSF ((uint32_t)0x00000020) #define RTC_FLAG_INITS ((uint32_t)0x00000010) #define RTC_FLAG_SHPF ((uint32_t)0x00000008) #define RTC_FLAG_WUTWF ((uint32_t)0x00000004) #define RTC_FLAG_ALRBWF ((uint32_t)0x00000002) #define RTC_FLAG_ALRAWF ((uint32_t)0x00000001) #define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \ ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \ ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \ ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \ ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \ ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_TAMP2F) || \ ((FLAG) == RTC_FLAG_TAMP3F) || ((FLAG) == RTC_FLAG_RECALPF) || \ ((FLAG) == RTC_FLAG_SHPF)|| ((FLAG) == RTC_FLAG_INITS)) #define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET)) /** * @} */ /** @defgroup RTC_Interrupts_Definitions * @{ */ #define RTC_IT_TS ((uint32_t)0x00008000) #define RTC_IT_WUT ((uint32_t)0x00004000) #define RTC_IT_ALRB ((uint32_t)0x00002000) #define RTC_IT_ALRA ((uint32_t)0x00001000) #define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */ #define RTC_IT_TAMP1 ((uint32_t)0x00020000) #define RTC_IT_TAMP2 ((uint32_t)0x00040000) #define RTC_IT_TAMP3 ((uint32_t)0x00080000) #define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET)) #define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \ ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \ ((IT) == RTC_IT_TAMP1) || ((IT) == RTC_IT_TAMP2) || \ ((IT) == RTC_IT_TAMP3)) #define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF10FFF) == (uint32_t)RESET)) /** * @} */ /** @defgroup RTC_Legacy * @{ */ #define RTC_DigitalCalibConfig RTC_CoarseCalibConfig #define RTC_DigitalCalibCmd RTC_CoarseCalibCmd /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ /* Function used to set the RTC configuration to the default reset state *****/ ErrorStatus RTC_DeInit(void); /* Initialization and Configuration functions *********************************/ ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct); void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct); void RTC_WriteProtectionCmd(FunctionalState NewState); ErrorStatus RTC_EnterInitMode(void); void RTC_ExitInitMode(void); ErrorStatus RTC_WaitForSynchro(void); ErrorStatus RTC_RefClockCmd(FunctionalState NewState); void RTC_BypassShadowCmd(FunctionalState NewState); /* Time and Date configuration functions **************************************/ ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct); void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); uint32_t RTC_GetSubSecond(void); ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct); void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); /* Alarms (Alarm A and Alarm B) configuration functions **********************/ void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct); void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState); void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask); uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm); /* WakeUp Timer configuration functions ***************************************/ void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock); void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter); uint32_t RTC_GetWakeUpCounter(void); ErrorStatus RTC_WakeUpCmd(FunctionalState NewState); /* Daylight Saving configuration functions ************************************/ void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation); uint32_t RTC_GetStoreOperation(void); /* Output pin Configuration function ******************************************/ void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity); /* Coarse and Smooth Calibration configuration functions **********************/ ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value); ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState); void RTC_CalibOutputCmd(FunctionalState NewState); void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput); ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, uint32_t RTC_SmoothCalibPlusPulses, uint32_t RTC_SmouthCalibMinusPulsesValue); /* TimeStamp configuration functions ******************************************/ void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState); void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, RTC_DateTypeDef* RTC_StampDateStruct); uint32_t RTC_GetTimeStampSubSecond(void); /* Tampers configuration functions ********************************************/ void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger); void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState); void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter); void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq); void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration); void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState); void RTC_TamperPullUpCmd(FunctionalState NewState); /* Backup Data Registers configuration functions ******************************/ void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data); uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR); /* Output Type Config configuration functions *********************************/ void RTC_OutputTypeConfig(uint32_t RTC_OutputType); /* RTC_Shift_control_synchonisation_functions *********************************/ ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS); /* Interrupts and flags management functions **********************************/ void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState); FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG); void RTC_ClearFlag(uint32_t RTC_FLAG); ITStatus RTC_GetITStatus(uint32_t RTC_IT); void RTC_ClearITPendingBit(uint32_t RTC_IT); #ifdef __cplusplus } #endif #endif /*__STM32L1xx_RTC_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/inc/stm32l1xx_sdio.h
New file @@ -0,0 +1,535 @@ /** ****************************************************************************** * @file stm32l1xx_sdio.h * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file contains all the functions prototypes for the SDIO firmware * library. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L1xx_SDIO_H #define __STM32L1xx_SDIO_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @addtogroup SDIO * @{ */ /* Exported types ------------------------------------------------------------*/ typedef struct { uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. This parameter can be a value of @ref SDIO_Clock_Edge */ uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is enabled or disabled. This parameter can be a value of @ref SDIO_Clock_Bypass */ uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or disabled when the bus is idle. This parameter can be a value of @ref SDIO_Clock_Power_Save */ uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width. This parameter can be a value of @ref SDIO_Bus_Wide */ uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. This parameter can be a value between 0x00 and 0xFF. */ } SDIO_InitTypeDef; typedef struct { uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing the command to the command register */ uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */ uint32_t SDIO_Response; /*!< Specifies the SDIO response type. This parameter can be a value of @ref SDIO_Response_Type */ uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled. This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) is enabled or disabled. This parameter can be a value of @ref SDIO_CPSM_State */ } SDIO_CmdInitTypeDef; typedef struct { uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */ uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer. This parameter can be a value of @ref SDIO_Data_Block_Size */ uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer is a read or write. This parameter can be a value of @ref SDIO_Transfer_Direction */ uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode. This parameter can be a value of @ref SDIO_Transfer_Type */ uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) is enabled or disabled. This parameter can be a value of @ref SDIO_DPSM_State */ } SDIO_DataInitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup SDIO_Exported_Constants * @{ */ /** @defgroup SDIO_Clock_Edge * @{ */ #define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) #define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \ ((EDGE) == SDIO_ClockEdge_Falling)) /** * @} */ /** @defgroup SDIO_Clock_Bypass * @{ */ #define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) #define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \ ((BYPASS) == SDIO_ClockBypass_Enable)) /** * @} */ /** @defgroup SDIO_Clock_Power_Save * @{ */ #define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) #define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \ ((SAVE) == SDIO_ClockPowerSave_Enable)) /** * @} */ /** @defgroup SDIO_Bus_Wide * @{ */ #define SDIO_BusWide_1b ((uint32_t)0x00000000) #define SDIO_BusWide_4b ((uint32_t)0x00000800) #define SDIO_BusWide_8b ((uint32_t)0x00001000) #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \ ((WIDE) == SDIO_BusWide_8b)) /** * @} */ /** @defgroup SDIO_Hardware_Flow_Control * @{ */ #define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) #define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \ ((CONTROL) == SDIO_HardwareFlowControl_Enable)) /** * @} */ /** @defgroup SDIO_Power_State * @{ */ #define SDIO_PowerState_OFF ((uint32_t)0x00000000) #define SDIO_PowerState_ON ((uint32_t)0x00000003) #define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) /** * @} */ /** @defgroup SDIO_Interrupt_soucres * @{ */ #define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) #define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) #define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) #define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) #define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) #define SDIO_IT_RXOVERR ((uint32_t)0x00000020) #define SDIO_IT_CMDREND ((uint32_t)0x00000040) #define SDIO_IT_CMDSENT ((uint32_t)0x00000080) #define SDIO_IT_DATAEND ((uint32_t)0x00000100) #define SDIO_IT_STBITERR ((uint32_t)0x00000200) #define SDIO_IT_DBCKEND ((uint32_t)0x00000400) #define SDIO_IT_CMDACT ((uint32_t)0x00000800) #define SDIO_IT_TXACT ((uint32_t)0x00001000) #define SDIO_IT_RXACT ((uint32_t)0x00002000) #define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) #define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) #define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) #define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) #define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) #define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) #define SDIO_IT_TXDAVL ((uint32_t)0x00100000) #define SDIO_IT_RXDAVL ((uint32_t)0x00200000) #define SDIO_IT_SDIOIT ((uint32_t)0x00400000) #define SDIO_IT_CEATAEND ((uint32_t)0x00800000) #define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00)) /** * @} */ /** @defgroup SDIO_Command_Index * @{ */ #define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) /** * @} */ /** @defgroup SDIO_Response_Type * @{ */ #define SDIO_Response_No ((uint32_t)0x00000000) #define SDIO_Response_Short ((uint32_t)0x00000040) #define SDIO_Response_Long ((uint32_t)0x000000C0) #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \ ((RESPONSE) == SDIO_Response_Short) || \ ((RESPONSE) == SDIO_Response_Long)) /** * @} */ /** @defgroup SDIO_Wait_Interrupt_State * @{ */ #define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */ #define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */ #define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */ #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \ ((WAIT) == SDIO_Wait_Pend)) /** * @} */ /** @defgroup SDIO_CPSM_State * @{ */ #define SDIO_CPSM_Disable ((uint32_t)0x00000000) #define SDIO_CPSM_Enable ((uint32_t)0x00000400) #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable)) /** * @} */ /** @defgroup SDIO_Response_Registers * @{ */ #define SDIO_RESP1 ((uint32_t)0x00000000) #define SDIO_RESP2 ((uint32_t)0x00000004) #define SDIO_RESP3 ((uint32_t)0x00000008) #define SDIO_RESP4 ((uint32_t)0x0000000C) #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \ ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4)) /** * @} */ /** @defgroup SDIO_Data_Length * @{ */ #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) /** * @} */ /** @defgroup SDIO_Data_Block_Size * @{ */ #define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) #define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) #define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) #define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) #define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) #define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) #define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) #define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) #define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) #define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) #define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) #define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) #define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) #define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) #define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \ ((SIZE) == SDIO_DataBlockSize_2b) || \ ((SIZE) == SDIO_DataBlockSize_4b) || \ ((SIZE) == SDIO_DataBlockSize_8b) || \ ((SIZE) == SDIO_DataBlockSize_16b) || \ ((SIZE) == SDIO_DataBlockSize_32b) || \ ((SIZE) == SDIO_DataBlockSize_64b) || \ ((SIZE) == SDIO_DataBlockSize_128b) || \ ((SIZE) == SDIO_DataBlockSize_256b) || \ ((SIZE) == SDIO_DataBlockSize_512b) || \ ((SIZE) == SDIO_DataBlockSize_1024b) || \ ((SIZE) == SDIO_DataBlockSize_2048b) || \ ((SIZE) == SDIO_DataBlockSize_4096b) || \ ((SIZE) == SDIO_DataBlockSize_8192b) || \ ((SIZE) == SDIO_DataBlockSize_16384b)) /** * @} */ /** @defgroup SDIO_Transfer_Direction * @{ */ #define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) #define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \ ((DIR) == SDIO_TransferDir_ToSDIO)) /** * @} */ /** @defgroup SDIO_Transfer_Type * @{ */ #define SDIO_TransferMode_Block ((uint32_t)0x00000000) #define SDIO_TransferMode_Stream ((uint32_t)0x00000004) #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \ ((MODE) == SDIO_TransferMode_Block)) /** * @} */ /** @defgroup SDIO_DPSM_State * @{ */ #define SDIO_DPSM_Disable ((uint32_t)0x00000000) #define SDIO_DPSM_Enable ((uint32_t)0x00000001) #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable)) /** * @} */ /** @defgroup SDIO_Flags * @{ */ #define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) #define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) #define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) #define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) #define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) #define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) #define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) #define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) #define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) #define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) #define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) #define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) #define SDIO_FLAG_TXACT ((uint32_t)0x00001000) #define SDIO_FLAG_RXACT ((uint32_t)0x00002000) #define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) #define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) #define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) #define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) #define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) #define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) #define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) #define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) #define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) #define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) #define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \ ((FLAG) == SDIO_FLAG_DCRCFAIL) || \ ((FLAG) == SDIO_FLAG_CTIMEOUT) || \ ((FLAG) == SDIO_FLAG_DTIMEOUT) || \ ((FLAG) == SDIO_FLAG_TXUNDERR) || \ ((FLAG) == SDIO_FLAG_RXOVERR) || \ ((FLAG) == SDIO_FLAG_CMDREND) || \ ((FLAG) == SDIO_FLAG_CMDSENT) || \ ((FLAG) == SDIO_FLAG_DATAEND) || \ ((FLAG) == SDIO_FLAG_STBITERR) || \ ((FLAG) == SDIO_FLAG_DBCKEND) || \ ((FLAG) == SDIO_FLAG_CMDACT) || \ ((FLAG) == SDIO_FLAG_TXACT) || \ ((FLAG) == SDIO_FLAG_RXACT) || \ ((FLAG) == SDIO_FLAG_TXFIFOHE) || \ ((FLAG) == SDIO_FLAG_RXFIFOHF) || \ ((FLAG) == SDIO_FLAG_TXFIFOF) || \ ((FLAG) == SDIO_FLAG_RXFIFOF) || \ ((FLAG) == SDIO_FLAG_TXFIFOE) || \ ((FLAG) == SDIO_FLAG_RXFIFOE) || \ ((FLAG) == SDIO_FLAG_TXDAVL) || \ ((FLAG) == SDIO_FLAG_RXDAVL) || \ ((FLAG) == SDIO_FLAG_SDIOIT) || \ ((FLAG) == SDIO_FLAG_CEATAEND)) #define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00)) #define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \ ((IT) == SDIO_IT_DCRCFAIL) || \ ((IT) == SDIO_IT_CTIMEOUT) || \ ((IT) == SDIO_IT_DTIMEOUT) || \ ((IT) == SDIO_IT_TXUNDERR) || \ ((IT) == SDIO_IT_RXOVERR) || \ ((IT) == SDIO_IT_CMDREND) || \ ((IT) == SDIO_IT_CMDSENT) || \ ((IT) == SDIO_IT_DATAEND) || \ ((IT) == SDIO_IT_STBITERR) || \ ((IT) == SDIO_IT_DBCKEND) || \ ((IT) == SDIO_IT_CMDACT) || \ ((IT) == SDIO_IT_TXACT) || \ ((IT) == SDIO_IT_RXACT) || \ ((IT) == SDIO_IT_TXFIFOHE) || \ ((IT) == SDIO_IT_RXFIFOHF) || \ ((IT) == SDIO_IT_TXFIFOF) || \ ((IT) == SDIO_IT_RXFIFOF) || \ ((IT) == SDIO_IT_TXFIFOE) || \ ((IT) == SDIO_IT_RXFIFOE) || \ ((IT) == SDIO_IT_TXDAVL) || \ ((IT) == SDIO_IT_RXDAVL) || \ ((IT) == SDIO_IT_SDIOIT) || \ ((IT) == SDIO_IT_CEATAEND)) #define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00)) /** * @} */ /** @defgroup SDIO_Read_Wait_Mode * @{ */ #define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001) #define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000) #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \ ((MODE) == SDIO_ReadWaitMode_DATA2)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ /* Function used to set the SDIO configuration to the default reset state ****/ void SDIO_DeInit(void); /* Initialization and Configuration functions *********************************/ void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); void SDIO_ClockCmd(FunctionalState NewState); void SDIO_SetPowerState(uint32_t SDIO_PowerState); uint32_t SDIO_GetPowerState(void); /* DMA transfers management functions *****************************************/ void SDIO_DMACmd(FunctionalState NewState); /* Command path state machine (CPSM) management functions *********************/ void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); uint8_t SDIO_GetCommandResponse(void); uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); /* Data path state machine (DPSM) management functions ************************/ void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); uint32_t SDIO_GetDataCounter(void); uint32_t SDIO_ReadData(void); void SDIO_WriteData(uint32_t Data); uint32_t SDIO_GetFIFOCount(void); /* SDIO IO Cards mode management functions ************************************/ void SDIO_StartSDIOReadWait(FunctionalState NewState); void SDIO_StopSDIOReadWait(FunctionalState NewState); void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); void SDIO_SetSDIOOperation(FunctionalState NewState); void SDIO_SendSDIOSuspendCmd(FunctionalState NewState); /* CE-ATA mode management functions *******************************************/ void SDIO_CommandCompletionCmd(FunctionalState NewState); void SDIO_CEATAITCmd(FunctionalState NewState); void SDIO_SendCEATACmd(FunctionalState NewState); /* Interrupts and flags management functions **********************************/ void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState); FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG); void SDIO_ClearFlag(uint32_t SDIO_FLAG); ITStatus SDIO_GetITStatus(uint32_t SDIO_IT); void SDIO_ClearITPendingBit(uint32_t SDIO_IT); #ifdef __cplusplus } #endif #endif /* __STM32L1xx_SDIO_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/inc/stm32l1xx_spi.h
New file @@ -0,0 +1,524 @@ /** ****************************************************************************** * @file stm32l1xx_spi.h * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file contains all the functions prototypes for the SPI * firmware library. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L1xx_SPI_H #define __STM32L1xx_SPI_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @addtogroup SPI * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief SPI Init structure definition */ typedef struct { uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. This parameter can be a value of @ref SPI_data_direction */ uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. This parameter can be a value of @ref SPI_mode */ uint16_t SPI_DataSize; /*!< Specifies the SPI data size. This parameter can be a value of @ref SPI_data_size */ uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. This parameter can be a value of @ref SPI_Clock_Polarity */ uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. This parameter can be a value of @ref SPI_Clock_Phase */ uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. This parameter can be a value of @ref SPI_Slave_Select_management */ uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be used to configure the transmit and receive SCK clock. This parameter can be a value of @ref SPI_BaudRate_Prescaler @note The communication clock is derived from the master clock. The slave clock does not need to be set. */ uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of @ref SPI_MSB_LSB_transmission */ uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ }SPI_InitTypeDef; /** * @brief I2S Init structure definition */ typedef struct { uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. This parameter can be a value of @ref SPI_I2S_Mode */ uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. This parameter can be a value of @ref SPI_I2S_Standard */ uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. This parameter can be a value of @ref SPI_I2S_Data_Format */ uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. This parameter can be a value of @ref SPI_I2S_MCLK_Output */ uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. This parameter can be a value of @ref SPI_I2S_Audio_Frequency */ uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. This parameter can be a value of @ref SPI_I2S_Clock_Polarity */ }I2S_InitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup SPI_Exported_Constants * @{ */ #define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ ((PERIPH) == SPI2) || \ ((PERIPH) == SPI3)) #define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ ((PERIPH) == SPI3)) /** @defgroup SPI_data_direction * @{ */ #define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) #define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) #define SPI_Direction_1Line_Rx ((uint16_t)0x8000) #define SPI_Direction_1Line_Tx ((uint16_t)0xC000) #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ ((MODE) == SPI_Direction_2Lines_RxOnly) || \ ((MODE) == SPI_Direction_1Line_Rx) || \ ((MODE) == SPI_Direction_1Line_Tx)) /** * @} */ /** @defgroup SPI_mode * @{ */ #define SPI_Mode_Master ((uint16_t)0x0104) #define SPI_Mode_Slave ((uint16_t)0x0000) #define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ ((MODE) == SPI_Mode_Slave)) /** * @} */ /** @defgroup SPI_data_size * @{ */ #define SPI_DataSize_16b ((uint16_t)0x0800) #define SPI_DataSize_8b ((uint16_t)0x0000) #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ ((DATASIZE) == SPI_DataSize_8b)) /** * @} */ /** @defgroup SPI_Clock_Polarity * @{ */ #define SPI_CPOL_Low ((uint16_t)0x0000) #define SPI_CPOL_High ((uint16_t)0x0002) #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ ((CPOL) == SPI_CPOL_High)) /** * @} */ /** @defgroup SPI_Clock_Phase * @{ */ #define SPI_CPHA_1Edge ((uint16_t)0x0000) #define SPI_CPHA_2Edge ((uint16_t)0x0001) #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ ((CPHA) == SPI_CPHA_2Edge)) /** * @} */ /** @defgroup SPI_Slave_Select_management * @{ */ #define SPI_NSS_Soft ((uint16_t)0x0200) #define SPI_NSS_Hard ((uint16_t)0x0000) #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ ((NSS) == SPI_NSS_Hard)) /** * @} */ /** @defgroup SPI_BaudRate_Prescaler * @{ */ #define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) #define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) #define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) #define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) #define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) #define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) #define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) #define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ ((PRESCALER) == SPI_BaudRatePrescaler_256)) /** * @} */ /** @defgroup SPI_MSB_LSB_transmission * @{ */ #define SPI_FirstBit_MSB ((uint16_t)0x0000) #define SPI_FirstBit_LSB ((uint16_t)0x0080) #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ ((BIT) == SPI_FirstBit_LSB)) /** * @} */ /** @defgroup SPI_I2S_Mode * @{ */ #define I2S_Mode_SlaveTx ((uint16_t)0x0000) #define I2S_Mode_SlaveRx ((uint16_t)0x0100) #define I2S_Mode_MasterTx ((uint16_t)0x0200) #define I2S_Mode_MasterRx ((uint16_t)0x0300) #define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ ((MODE) == I2S_Mode_SlaveRx) || \ ((MODE) == I2S_Mode_MasterTx)|| \ ((MODE) == I2S_Mode_MasterRx)) /** * @} */ /** @defgroup SPI_I2S_Standard * @{ */ #define I2S_Standard_Phillips ((uint16_t)0x0000) #define I2S_Standard_MSB ((uint16_t)0x0010) #define I2S_Standard_LSB ((uint16_t)0x0020) #define I2S_Standard_PCMShort ((uint16_t)0x0030) #define I2S_Standard_PCMLong ((uint16_t)0x00B0) #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ ((STANDARD) == I2S_Standard_MSB) || \ ((STANDARD) == I2S_Standard_LSB) || \ ((STANDARD) == I2S_Standard_PCMShort) || \ ((STANDARD) == I2S_Standard_PCMLong)) /** * @} */ /** @defgroup SPI_I2S_Data_Format * @{ */ #define I2S_DataFormat_16b ((uint16_t)0x0000) #define I2S_DataFormat_16bextended ((uint16_t)0x0001) #define I2S_DataFormat_24b ((uint16_t)0x0003) #define I2S_DataFormat_32b ((uint16_t)0x0005) #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ ((FORMAT) == I2S_DataFormat_16bextended) || \ ((FORMAT) == I2S_DataFormat_24b) || \ ((FORMAT) == I2S_DataFormat_32b)) /** * @} */ /** @defgroup SPI_I2S_MCLK_Output * @{ */ #define I2S_MCLKOutput_Enable ((uint16_t)0x0200) #define I2S_MCLKOutput_Disable ((uint16_t)0x0000) #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ ((OUTPUT) == I2S_MCLKOutput_Disable)) /** * @} */ /** @defgroup SPI_I2S_Audio_Frequency * @{ */ #define I2S_AudioFreq_192k ((uint32_t)192000) #define I2S_AudioFreq_96k ((uint32_t)96000) #define I2S_AudioFreq_48k ((uint32_t)48000) #define I2S_AudioFreq_44k ((uint32_t)44100) #define I2S_AudioFreq_32k ((uint32_t)32000) #define I2S_AudioFreq_22k ((uint32_t)22050) #define I2S_AudioFreq_16k ((uint32_t)16000) #define I2S_AudioFreq_11k ((uint32_t)11025) #define I2S_AudioFreq_8k ((uint32_t)8000) #define I2S_AudioFreq_Default ((uint32_t)2) #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ ((FREQ) <= I2S_AudioFreq_192k)) || \ ((FREQ) == I2S_AudioFreq_Default)) /** * @} */ /** @defgroup SPI_I2S_Clock_Polarity * @{ */ #define I2S_CPOL_Low ((uint16_t)0x0000) #define I2S_CPOL_High ((uint16_t)0x0008) #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ ((CPOL) == I2S_CPOL_High)) /** * @} */ /** @defgroup SPI_I2S_DMA_transfer_requests * @{ */ #define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) #define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) #define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) /** * @} */ /** @defgroup SPI_NSS_internal_software_management * @{ */ #define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) #define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) #define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ ((INTERNAL) == SPI_NSSInternalSoft_Reset)) /** * @} */ /** @defgroup SPI_CRC_Transmit_Receive * @{ */ #define SPI_CRC_Tx ((uint8_t)0x00) #define SPI_CRC_Rx ((uint8_t)0x01) #define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) /** * @} */ /** @defgroup SPI_direction_transmit_receive * @{ */ #define SPI_Direction_Rx ((uint16_t)0xBFFF) #define SPI_Direction_Tx ((uint16_t)0x4000) #define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ ((DIRECTION) == SPI_Direction_Tx)) /** * @} */ /** @defgroup SPI_I2S_interrupts_definition * @{ */ #define SPI_I2S_IT_TXE ((uint8_t)0x71) #define SPI_I2S_IT_RXNE ((uint8_t)0x60) #define SPI_I2S_IT_ERR ((uint8_t)0x50) #define I2S_IT_UDR ((uint8_t)0x53) #define SPI_I2S_IT_FRE ((uint8_t)0x58) #define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ ((IT) == SPI_I2S_IT_RXNE) || \ ((IT) == SPI_I2S_IT_ERR)) #define SPI_I2S_IT_OVR ((uint8_t)0x56) #define SPI_IT_MODF ((uint8_t)0x55) #define SPI_IT_CRCERR ((uint8_t)0x54) #define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) #define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \ ((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \ ((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\ ((IT) == SPI_I2S_IT_FRE)) /** * @} */ /** @defgroup SPI_I2S_flags_definition * @{ */ #define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) #define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) #define I2S_FLAG_CHSIDE ((uint16_t)0x0004) #define I2S_FLAG_UDR ((uint16_t)0x0008) #define SPI_FLAG_CRCERR ((uint16_t)0x0010) #define SPI_FLAG_MODF ((uint16_t)0x0020) #define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) #define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) #define SPI_I2S_FLAG_FRE ((uint16_t)0x0100) #define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) #define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \ ((FLAG) == SPI_I2S_FLAG_FRE)) /** * @} */ /** @defgroup SPI_CRC_polynomial * @{ */ #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) /** * @} */ /** @defgroup SPI_I2S_Legacy * @{ */ #define SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx #define SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx #define SPI_IT_TXE SPI_I2S_IT_TXE #define SPI_IT_RXNE SPI_I2S_IT_RXNE #define SPI_IT_ERR SPI_I2S_IT_ERR #define SPI_IT_OVR SPI_I2S_IT_OVR #define SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE #define SPI_FLAG_TXE SPI_I2S_FLAG_TXE #define SPI_FLAG_OVR SPI_I2S_FLAG_OVR #define SPI_FLAG_BSY SPI_I2S_FLAG_BSY #define SPI_DeInit SPI_I2S_DeInit #define SPI_ITConfig SPI_I2S_ITConfig #define SPI_DMACmd SPI_I2S_DMACmd #define SPI_SendData SPI_I2S_SendData #define SPI_ReceiveData SPI_I2S_ReceiveData #define SPI_GetFlagStatus SPI_I2S_GetFlagStatus #define SPI_ClearFlag SPI_I2S_ClearFlag #define SPI_GetITStatus SPI_I2S_GetITStatus #define SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ /* Function used to set the SPI configuration to the default reset state *****/ void SPI_I2S_DeInit(SPI_TypeDef* SPIx); /* Initialization and Configuration functions *********************************/ void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); /* Data transfers functions ***************************************************/ void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); /* Hardware CRC Calculation functions *****************************************/ void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); void SPI_TransmitCRC(SPI_TypeDef* SPIx); uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); /* DMA transfers management functions *****************************************/ void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); /* Interrupts and flags management functions **********************************/ void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); #ifdef __cplusplus } #endif #endif /*__STM32L1xx_SPI_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/inc/stm32l1xx_syscfg.h
New file @@ -0,0 +1,476 @@ /** ****************************************************************************** * @file stm32l1xx_syscfg.h * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file contains all the functions prototypes for the SYSCFG * firmware library. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /*!< Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L1xx_SYSCFG_H #define __STM32L1xx_SYSCFG_H #ifdef __cplusplus extern "C" { #endif /*!< Includes ------------------------------------------------------------------*/ #include "stm32l1xx.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @addtogroup SYSCFG * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup SYSCFG_Exported_Constants * @{ */ /** @defgroup EXTI_Port_Sources * @{ */ #define EXTI_PortSourceGPIOA ((uint8_t)0x00) #define EXTI_PortSourceGPIOB ((uint8_t)0x01) #define EXTI_PortSourceGPIOC ((uint8_t)0x02) #define EXTI_PortSourceGPIOD ((uint8_t)0x03) #define EXTI_PortSourceGPIOE ((uint8_t)0x04) #define EXTI_PortSourceGPIOH ((uint8_t)0x05) #define EXTI_PortSourceGPIOF ((uint8_t)0x06) #define EXTI_PortSourceGPIOG ((uint8_t)0x07) #define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \ ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \ ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \ ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \ ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \ ((PORTSOURCE) == EXTI_PortSourceGPIOF) || \ ((PORTSOURCE) == EXTI_PortSourceGPIOG) || \ ((PORTSOURCE) == EXTI_PortSourceGPIOH)) /** * @} */ /** @defgroup EXTI_Pin_sources * @{ */ #define EXTI_PinSource0 ((uint8_t)0x00) #define EXTI_PinSource1 ((uint8_t)0x01) #define EXTI_PinSource2 ((uint8_t)0x02) #define EXTI_PinSource3 ((uint8_t)0x03) #define EXTI_PinSource4 ((uint8_t)0x04) #define EXTI_PinSource5 ((uint8_t)0x05) #define EXTI_PinSource6 ((uint8_t)0x06) #define EXTI_PinSource7 ((uint8_t)0x07) #define EXTI_PinSource8 ((uint8_t)0x08) #define EXTI_PinSource9 ((uint8_t)0x09) #define EXTI_PinSource10 ((uint8_t)0x0A) #define EXTI_PinSource11 ((uint8_t)0x0B) #define EXTI_PinSource12 ((uint8_t)0x0C) #define EXTI_PinSource13 ((uint8_t)0x0D) #define EXTI_PinSource14 ((uint8_t)0x0E) #define EXTI_PinSource15 ((uint8_t)0x0F) #define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \ ((PINSOURCE) == EXTI_PinSource1) || \ ((PINSOURCE) == EXTI_PinSource2) || \ ((PINSOURCE) == EXTI_PinSource3) || \ ((PINSOURCE) == EXTI_PinSource4) || \ ((PINSOURCE) == EXTI_PinSource5) || \ ((PINSOURCE) == EXTI_PinSource6) || \ ((PINSOURCE) == EXTI_PinSource7) || \ ((PINSOURCE) == EXTI_PinSource8) || \ ((PINSOURCE) == EXTI_PinSource9) || \ ((PINSOURCE) == EXTI_PinSource10) || \ ((PINSOURCE) == EXTI_PinSource11) || \ ((PINSOURCE) == EXTI_PinSource12) || \ ((PINSOURCE) == EXTI_PinSource13) || \ ((PINSOURCE) == EXTI_PinSource14) || \ ((PINSOURCE) == EXTI_PinSource15)) /** * @} */ /** @defgroup SYSCFG_Memory_Remap_Config * @{ */ #define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00) #define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01) #define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02) #define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03) #define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \ ((REMAP) == SYSCFG_MemoryRemap_FSMC) || \ ((REMAP) == SYSCFG_MemoryRemap_SRAM)) /** * @} */ /** @defgroup RI_Resistor * @{ */ #define RI_Resistor_10KPU COMP_CSR_10KPU #define RI_Resistor_400KPU COMP_CSR_400KPU #define RI_Resistor_10KPD COMP_CSR_10KPD #define RI_Resistor_400KPD COMP_CSR_400KPD #define IS_RI_RESISTOR(RESISTOR) (((RESISTOR) == COMP_CSR_10KPU) || \ ((RESISTOR) == COMP_CSR_400KPU) || \ ((RESISTOR) == COMP_CSR_10KPD) || \ ((RESISTOR) == COMP_CSR_400KPD)) /** * @} */ /** @defgroup RI_Channel * @{ */ #define RI_Channel_3 ((uint32_t)0x04000000) #define RI_Channel_8 ((uint32_t)0x08000000) #define RI_Channel_13 ((uint32_t)0x10000000) #define IS_RI_CHANNEL(CHANNEL) (((CHANNEL) == RI_Channel_3) || \ ((CHANNEL) == RI_Channel_8) || \ ((CHANNEL) == RI_Channel_13)) /** * @} */ /** @defgroup RI_ChannelSpeed * @{ */ #define RI_ChannelSpeed_Fast ((uint32_t)0x00000000) #define RI_ChannelSpeed_Slow ((uint32_t)0x00000001) #define IS_RI_CHANNELSPEED(SPEED) (((SPEED) == RI_ChannelSpeed_Fast) || \ ((SPEED) == RI_ChannelSpeed_Slow)) /** * @} */ /** @defgroup RI_InputCapture * @{ */ #define RI_InputCapture_IC1 RI_ICR_IC1 /*!< Input Capture 1 */ #define RI_InputCapture_IC2 RI_ICR_IC2 /*!< Input Capture 2 */ #define RI_InputCapture_IC3 RI_ICR_IC3 /*!< Input Capture 3 */ #define RI_InputCapture_IC4 RI_ICR_IC4 /*!< Input Capture 4 */ #define IS_RI_INPUTCAPTURE(INPUTCAPTURE) ((((INPUTCAPTURE) & (uint32_t)0xFFC2FFFF) == 0x00) && ((INPUTCAPTURE) != (uint32_t)0x00)) /** * @} */ /** @defgroup TIM_Select * @{ */ #define TIM_Select_None ((uint32_t)0x00000000) /*!< None selected */ #define TIM_Select_TIM2 ((uint32_t)0x00010000) /*!< Timer 2 selected */ #define TIM_Select_TIM3 ((uint32_t)0x00020000) /*!< Timer 3 selected */ #define TIM_Select_TIM4 ((uint32_t)0x00030000) /*!< Timer 4 selected */ #define IS_RI_TIM(TIM) (((TIM) == TIM_Select_None) || \ ((TIM) == TIM_Select_TIM2) || \ ((TIM) == TIM_Select_TIM3) || \ ((TIM) == TIM_Select_TIM4)) /** * @} */ /** @defgroup RI_InputCaptureRouting * @{ */ /* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */ #define RI_InputCaptureRouting_0 ((uint32_t)0x00000000) /* PA0 PA1 PA2 PA3 */ #define RI_InputCaptureRouting_1 ((uint32_t)0x00000001) /* PA4 PA5 PA6 PA7 */ #define RI_InputCaptureRouting_2 ((uint32_t)0x00000002) /* PA8 PA9 PA10 PA11 */ #define RI_InputCaptureRouting_3 ((uint32_t)0x00000003) /* PA12 PA13 PA14 PA15 */ #define RI_InputCaptureRouting_4 ((uint32_t)0x00000004) /* PC0 PC1 PC2 PC3 */ #define RI_InputCaptureRouting_5 ((uint32_t)0x00000005) /* PC4 PC5 PC6 PC7 */ #define RI_InputCaptureRouting_6 ((uint32_t)0x00000006) /* PC8 PC9 PC10 PC11 */ #define RI_InputCaptureRouting_7 ((uint32_t)0x00000007) /* PC12 PC13 PC14 PC15 */ #define RI_InputCaptureRouting_8 ((uint32_t)0x00000008) /* PD0 PD1 PD2 PD3 */ #define RI_InputCaptureRouting_9 ((uint32_t)0x00000009) /* PD4 PD5 PD6 PD7 */ #define RI_InputCaptureRouting_10 ((uint32_t)0x0000000A) /* PD8 PD9 PD10 PD11 */ #define RI_InputCaptureRouting_11 ((uint32_t)0x0000000B) /* PD12 PD13 PD14 PD15 */ #define RI_InputCaptureRouting_12 ((uint32_t)0x0000000C) /* PE0 PE1 PE2 PE3 */ #define RI_InputCaptureRouting_13 ((uint32_t)0x0000000D) /* PE4 PE5 PE6 PE7 */ #define RI_InputCaptureRouting_14 ((uint32_t)0x0000000E) /* PE8 PE9 PE10 PE11 */ #define RI_InputCaptureRouting_15 ((uint32_t)0x0000000F) /* PE12 PE13 PE14 PE15 */ #define IS_RI_INPUTCAPTURE_ROUTING(ROUTING) (((ROUTING) == RI_InputCaptureRouting_0) || \ ((ROUTING) == RI_InputCaptureRouting_1) || \ ((ROUTING) == RI_InputCaptureRouting_2) || \ ((ROUTING) == RI_InputCaptureRouting_3) || \ ((ROUTING) == RI_InputCaptureRouting_4) || \ ((ROUTING) == RI_InputCaptureRouting_5) || \ ((ROUTING) == RI_InputCaptureRouting_6) || \ ((ROUTING) == RI_InputCaptureRouting_7) || \ ((ROUTING) == RI_InputCaptureRouting_8) || \ ((ROUTING) == RI_InputCaptureRouting_9) || \ ((ROUTING) == RI_InputCaptureRouting_10) || \ ((ROUTING) == RI_InputCaptureRouting_11) || \ ((ROUTING) == RI_InputCaptureRouting_12) || \ ((ROUTING) == RI_InputCaptureRouting_13) || \ ((ROUTING) == RI_InputCaptureRouting_14) || \ ((ROUTING) == RI_InputCaptureRouting_15)) /** * @} */ /** @defgroup RI_IOSwitch * @{ */ /* ASCR1 I/O switch: bit 31 is set to '1' to indicate that the mask is in ASCR1 register */ #define RI_IOSwitch_CH0 ((uint32_t)0x80000001) #define RI_IOSwitch_CH1 ((uint32_t)0x80000002) #define RI_IOSwitch_CH2 ((uint32_t)0x80000004) #define RI_IOSwitch_CH3 ((uint32_t)0x80000008) #define RI_IOSwitch_CH4 ((uint32_t)0x80000010) #define RI_IOSwitch_CH5 ((uint32_t)0x80000020) #define RI_IOSwitch_CH6 ((uint32_t)0x80000040) #define RI_IOSwitch_CH7 ((uint32_t)0x80000080) #define RI_IOSwitch_CH8 ((uint32_t)0x80000100) #define RI_IOSwitch_CH9 ((uint32_t)0x80000200) #define RI_IOSwitch_CH10 ((uint32_t)0x80000400) #define RI_IOSwitch_CH11 ((uint32_t)0x80000800) #define RI_IOSwitch_CH12 ((uint32_t)0x80001000) #define RI_IOSwitch_CH13 ((uint32_t)0x80002000) #define RI_IOSwitch_CH14 ((uint32_t)0x80004000) #define RI_IOSwitch_CH15 ((uint32_t)0x80008000) #define RI_IOSwitch_CH31 ((uint32_t)0x80010000) #define RI_IOSwitch_CH18 ((uint32_t)0x80040000) #define RI_IOSwitch_CH19 ((uint32_t)0x80080000) #define RI_IOSwitch_CH20 ((uint32_t)0x80100000) #define RI_IOSwitch_CH21 ((uint32_t)0x80200000) #define RI_IOSwitch_CH22 ((uint32_t)0x80400000) #define RI_IOSwitch_CH23 ((uint32_t)0x80800000) #define RI_IOSwitch_CH24 ((uint32_t)0x81000000) #define RI_IOSwitch_CH25 ((uint32_t)0x82000000) #define RI_IOSwitch_VCOMP ((uint32_t)0x84000000) /* VCOMP is an internal switch used to connect selected channel to COMP1 non inverting input */ #define RI_IOSwitch_CH27 ((uint32_t)0x88000000) #define RI_IOSwitch_CH28 ((uint32_t)0x90000000) #define RI_IOSwitch_CH29 ((uint32_t)0xA0000000) #define RI_IOSwitch_CH30 ((uint32_t)0xC0000000) /* ASCR2 IO switch: bit 31 is set to '0' to indicate that the mask is in ASCR2 register */ #define RI_IOSwitch_GR10_1 ((uint32_t)0x00000001) #define RI_IOSwitch_GR10_2 ((uint32_t)0x00000002) #define RI_IOSwitch_GR10_3 ((uint32_t)0x00000004) #define RI_IOSwitch_GR10_4 ((uint32_t)0x00000008) #define RI_IOSwitch_GR6_1 ((uint32_t)0x00000010) #define RI_IOSwitch_GR6_2 ((uint32_t)0x00000020) #define RI_IOSwitch_GR5_1 ((uint32_t)0x00000040) #define RI_IOSwitch_GR5_2 ((uint32_t)0x00000080) #define RI_IOSwitch_GR5_3 ((uint32_t)0x00000100) #define RI_IOSwitch_GR4_1 ((uint32_t)0x00000200) #define RI_IOSwitch_GR4_2 ((uint32_t)0x00000400) #define RI_IOSwitch_GR4_3 ((uint32_t)0x00000800) #define RI_IOSwitch_GR4_4 ((uint32_t)0x00008000) #define RI_IOSwitch_CH0b ((uint32_t)0x00010000) #define RI_IOSwitch_CH1b ((uint32_t)0x00020000) #define RI_IOSwitch_CH2b ((uint32_t)0x00040000) #define RI_IOSwitch_CH3b ((uint32_t)0x00080000) #define RI_IOSwitch_CH6b ((uint32_t)0x00100000) #define RI_IOSwitch_CH7b ((uint32_t)0x00200000) #define RI_IOSwitch_CH8b ((uint32_t)0x00400000) #define RI_IOSwitch_CH9b ((uint32_t)0x00800000) #define RI_IOSwitch_CH10b ((uint32_t)0x01000000) #define RI_IOSwitch_CH11b ((uint32_t)0x02000000) #define RI_IOSwitch_CH12b ((uint32_t)0x04000000) #define RI_IOSwitch_GR6_3 ((uint32_t)0x08000000) #define RI_IOSwitch_GR6_4 ((uint32_t)0x10000000) #define RI_IOSwitch_GR5_4 ((uint32_t)0x20000000) #define IS_RI_IOSWITCH(IOSWITCH) (((IOSWITCH) == RI_IOSwitch_CH0) || \ ((IOSWITCH) == RI_IOSwitch_CH1) || \ ((IOSWITCH) == RI_IOSwitch_CH2) || \ ((IOSWITCH) == RI_IOSwitch_CH3) || \ ((IOSWITCH) == RI_IOSwitch_CH4) || \ ((IOSWITCH) == RI_IOSwitch_CH5) || \ ((IOSWITCH) == RI_IOSwitch_CH6) || \ ((IOSWITCH) == RI_IOSwitch_CH7) || \ ((IOSWITCH) == RI_IOSwitch_CH8) || \ ((IOSWITCH) == RI_IOSwitch_CH9) || \ ((IOSWITCH) == RI_IOSwitch_CH10) || \ ((IOSWITCH) == RI_IOSwitch_CH11) || \ ((IOSWITCH) == RI_IOSwitch_CH12) || \ ((IOSWITCH) == RI_IOSwitch_CH13) || \ ((IOSWITCH) == RI_IOSwitch_CH14) || \ ((IOSWITCH) == RI_IOSwitch_CH15) || \ ((IOSWITCH) == RI_IOSwitch_CH18) || \ ((IOSWITCH) == RI_IOSwitch_CH19) || \ ((IOSWITCH) == RI_IOSwitch_CH20) || \ ((IOSWITCH) == RI_IOSwitch_CH21) || \ ((IOSWITCH) == RI_IOSwitch_CH22) || \ ((IOSWITCH) == RI_IOSwitch_CH23) || \ ((IOSWITCH) == RI_IOSwitch_CH24) || \ ((IOSWITCH) == RI_IOSwitch_CH25) || \ ((IOSWITCH) == RI_IOSwitch_VCOMP) || \ ((IOSWITCH) == RI_IOSwitch_CH27) || \ ((IOSWITCH) == RI_IOSwitch_CH28) || \ ((IOSWITCH) == RI_IOSwitch_CH29) || \ ((IOSWITCH) == RI_IOSwitch_CH30) || \ ((IOSWITCH) == RI_IOSwitch_CH31) || \ ((IOSWITCH) == RI_IOSwitch_GR10_1) || \ ((IOSWITCH) == RI_IOSwitch_GR10_2) || \ ((IOSWITCH) == RI_IOSwitch_GR10_3) || \ ((IOSWITCH) == RI_IOSwitch_GR10_4) || \ ((IOSWITCH) == RI_IOSwitch_GR6_1) || \ ((IOSWITCH) == RI_IOSwitch_GR6_2) || \ ((IOSWITCH) == RI_IOSwitch_GR6_3) || \ ((IOSWITCH) == RI_IOSwitch_GR6_4) || \ ((IOSWITCH) == RI_IOSwitch_GR5_1) || \ ((IOSWITCH) == RI_IOSwitch_GR5_2) || \ ((IOSWITCH) == RI_IOSwitch_GR5_3) || \ ((IOSWITCH) == RI_IOSwitch_GR5_4) || \ ((IOSWITCH) == RI_IOSwitch_GR4_1) || \ ((IOSWITCH) == RI_IOSwitch_GR4_2) || \ ((IOSWITCH) == RI_IOSwitch_GR4_3) || \ ((IOSWITCH) == RI_IOSwitch_GR4_4) || \ ((IOSWITCH) == RI_IOSwitch_CH0b) || \ ((IOSWITCH) == RI_IOSwitch_CH1b) || \ ((IOSWITCH) == RI_IOSwitch_CH2b) || \ ((IOSWITCH) == RI_IOSwitch_CH3b) || \ ((IOSWITCH) == RI_IOSwitch_CH6b) || \ ((IOSWITCH) == RI_IOSwitch_CH7b) || \ ((IOSWITCH) == RI_IOSwitch_CH8b) || \ ((IOSWITCH) == RI_IOSwitch_CH9b) || \ ((IOSWITCH) == RI_IOSwitch_CH10b) || \ ((IOSWITCH) == RI_IOSwitch_CH11b) || \ ((IOSWITCH) == RI_IOSwitch_CH12b)) /** * @} */ /** @defgroup RI_Port * @{ */ #define RI_PortA ((uint8_t)0x01) /*!< GPIOA selected */ #define RI_PortB ((uint8_t)0x02) /*!< GPIOB selected */ #define RI_PortC ((uint8_t)0x03) /*!< GPIOC selected */ #define RI_PortD ((uint8_t)0x04) /*!< GPIOD selected */ #define RI_PortE ((uint8_t)0x05) /*!< GPIOE selected */ #define RI_PortF ((uint8_t)0x06) /*!< GPIOF selected */ #define RI_PortG ((uint8_t)0x07) /*!< GPIOG selected */ #define IS_RI_PORT(PORT) (((PORT) == RI_PortA) || \ ((PORT) == RI_PortB) || \ ((PORT) == RI_PortC) || \ ((PORT) == RI_PortD) || \ ((PORT) == RI_PortE) || \ ((PORT) == RI_PortF) || \ ((PORT) == RI_PortG)) /** * @} */ /** @defgroup RI_Pin define * @{ */ #define RI_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ #define RI_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ #define RI_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ #define RI_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ #define RI_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ #define RI_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ #define RI_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ #define RI_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ #define RI_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ #define RI_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ #define RI_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ #define RI_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ #define RI_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ #define RI_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ #define RI_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ #define RI_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ #define RI_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */ #define IS_RI_PIN(PIN) ((PIN) != (uint16_t)0x00) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ /* Function used to set the SYSCFG and RI configuration to the default reset state **/ void SYSCFG_DeInit(void); void SYSCFG_RIDeInit(void); /* SYSCFG Initialization and Configuration functions **************************/ void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap); uint32_t SYSCFG_GetBootMode(void); void SYSCFG_USBPuCmd(FunctionalState NewState); void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex); /* RI Initialization and Configuration functions ******************************/ void SYSCFG_RITIMSelect(uint32_t TIM_Select); void SYSCFG_RITIMInputCaptureConfig(uint32_t RI_InputCapture, uint32_t RI_InputCaptureRouting); void SYSCFG_RIResistorConfig(uint32_t RI_Resistor, FunctionalState NewState); void SYSCFG_RIChannelSpeedConfig(uint32_t RI_Channel, uint32_t RI_ChannelSpeed); void SYSCFG_RISwitchControlModeCmd(FunctionalState NewState); void SYSCFG_RIIOSwitchConfig(uint32_t RI_IOSwitch, FunctionalState NewState); void SYSCFG_RIHysteresisConfig(uint8_t RI_Port, uint16_t RI_Pin, FunctionalState NewState); #ifdef __cplusplus } #endif #endif /*__STM32L1xx_SYSCFG_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/inc/stm32l1xx_tim.h
New file @@ -0,0 +1,982 @@ /** ****************************************************************************** * @file stm32l1xx_tim.h * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file contains all the functions prototypes for the TIM firmware * library. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L1xx_TIM_H #define __STM32L1xx_TIM_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @addtogroup TIM * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief TIM Time Base Init structure definition * @note This structure is used with all TIMx except for TIM6 and TIM7. */ typedef struct { uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between 0x0000 and 0xFFFF */ uint16_t TIM_CounterMode; /*!< Specifies the counter mode. This parameter can be a value of @ref TIM_Counter_Mode */ uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active Auto-Reload Register at the next update event. This parameter must be a number between 0x0000 and 0xFFFF. */ uint16_t TIM_ClockDivision; /*!< Specifies the clock division. This parameter can be a value of @ref TIM_Clock_Division_CKD */ } TIM_TimeBaseInitTypeDef; /** * @brief TIM Output Compare Init structure definition */ typedef struct { uint16_t TIM_OCMode; /*!< Specifies the TIM mode. This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. This parameter can be a value of @ref TIM_Output_Compare_state */ uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between 0x0000 and 0xFFFF */ uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. This parameter can be a value of @ref TIM_Output_Compare_Polarity */ } TIM_OCInitTypeDef; /** * @brief TIM Input Capture Init structure definition */ typedef struct { uint16_t TIM_Channel; /*!< Specifies the TIM channel. This parameter can be a value of @ref TIM_Channel */ uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ uint16_t TIM_ICSelection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. This parameter can be a number between 0x0 and 0xF */ } TIM_ICInitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup TIM_Exported_constants * @{ */ #define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM2) || \ ((PERIPH) == TIM3) || \ ((PERIPH) == TIM4) || \ ((PERIPH) == TIM5) || \ ((PERIPH) == TIM6) || \ ((PERIPH) == TIM7) || \ ((PERIPH) == TIM9) || \ ((PERIPH) == TIM10) || \ ((PERIPH) == TIM11)) /* LIST1: TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and TIM11 */ #define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM2) || \ ((PERIPH) == TIM3) || \ ((PERIPH) == TIM4) || \ ((PERIPH) == TIM5) || \ ((PERIPH) == TIM9) || \ ((PERIPH) == TIM10) || \ ((PERIPH) == TIM11)) /* LIST3: TIM2, TIM3, TIM4 and TIM5 */ #define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM2) || \ ((PERIPH) == TIM3) || \ ((PERIPH) == TIM4) || \ ((PERIPH) == TIM5)) /* LIST2: TIM2, TIM3, TIM4, TIM5 and TIM9 */ #define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM2) || \ ((PERIPH) == TIM3) || \ ((PERIPH) == TIM4) || \ ((PERIPH) == TIM5) || \ ((PERIPH) == TIM9)) /* LIST5: TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM9 */ #define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM2) || \ ((PERIPH) == TIM3) || \ ((PERIPH) == TIM4) || \ ((PERIPH) == TIM5) ||\ ((PERIPH) == TIM6) || \ ((PERIPH) == TIM7) ||\ ((PERIPH) == TIM9)) /* LIST4: TIM2, TIM3, TIM4, TIM5, TIM6 and TIM7 */ #define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM2) || \ ((PERIPH) == TIM3) || \ ((PERIPH) == TIM4) || \ ((PERIPH) == TIM5) ||\ ((PERIPH) == TIM6) || \ ((PERIPH) == TIM7)) /* LIST6: TIM2, TIM3, TIM9, TIM10 and TIM11 */ #define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM2) || \ ((PERIPH) == TIM3) || \ ((PERIPH) == TIM9) || \ ((PERIPH) == TIM10) || \ ((PERIPH) == TIM11)) /* LIST3: TIM2, TIM3, TIM4, TIM5 and TIM9 */ #define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM2) || \ ((PERIPH) == TIM3) || \ ((PERIPH) == TIM4) || \ ((PERIPH) == TIM5) || \ ((PERIPH) == TIM9)) /** @defgroup TIM_Output_Compare_and_PWM_modes * @{ */ #define TIM_OCMode_Timing ((uint16_t)0x0000) #define TIM_OCMode_Active ((uint16_t)0x0010) #define TIM_OCMode_Inactive ((uint16_t)0x0020) #define TIM_OCMode_Toggle ((uint16_t)0x0030) #define TIM_OCMode_PWM1 ((uint16_t)0x0060) #define TIM_OCMode_PWM2 ((uint16_t)0x0070) #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ ((MODE) == TIM_OCMode_Active) || \ ((MODE) == TIM_OCMode_Inactive) || \ ((MODE) == TIM_OCMode_Toggle)|| \ ((MODE) == TIM_OCMode_PWM1) || \ ((MODE) == TIM_OCMode_PWM2)) #define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ ((MODE) == TIM_OCMode_Active) || \ ((MODE) == TIM_OCMode_Inactive) || \ ((MODE) == TIM_OCMode_Toggle)|| \ ((MODE) == TIM_OCMode_PWM1) || \ ((MODE) == TIM_OCMode_PWM2) || \ ((MODE) == TIM_ForcedAction_Active) || \ ((MODE) == TIM_ForcedAction_InActive)) /** * @} */ /** @defgroup TIM_One_Pulse_Mode * @{ */ #define TIM_OPMode_Single ((uint16_t)0x0008) #define TIM_OPMode_Repetitive ((uint16_t)0x0000) #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ ((MODE) == TIM_OPMode_Repetitive)) /** * @} */ /** @defgroup TIM_Channel * @{ */ #define TIM_Channel_1 ((uint16_t)0x0000) #define TIM_Channel_2 ((uint16_t)0x0004) #define TIM_Channel_3 ((uint16_t)0x0008) #define TIM_Channel_4 ((uint16_t)0x000C) #define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ ((CHANNEL) == TIM_Channel_2) || \ ((CHANNEL) == TIM_Channel_3) || \ ((CHANNEL) == TIM_Channel_4)) #define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ ((CHANNEL) == TIM_Channel_2)) /** * @} */ /** @defgroup TIM_Clock_Division_CKD * @{ */ #define TIM_CKD_DIV1 ((uint16_t)0x0000) #define TIM_CKD_DIV2 ((uint16_t)0x0100) #define TIM_CKD_DIV4 ((uint16_t)0x0200) #define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ ((DIV) == TIM_CKD_DIV2) || \ ((DIV) == TIM_CKD_DIV4)) /** * @} */ /** @defgroup TIM_Counter_Mode * @{ */ #define TIM_CounterMode_Up ((uint16_t)0x0000) #define TIM_CounterMode_Down ((uint16_t)0x0010) #define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) #define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) #define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ ((MODE) == TIM_CounterMode_Down) || \ ((MODE) == TIM_CounterMode_CenterAligned1) || \ ((MODE) == TIM_CounterMode_CenterAligned2) || \ ((MODE) == TIM_CounterMode_CenterAligned3)) /** * @} */ /** @defgroup TIM_Output_Compare_Polarity * @{ */ #define TIM_OCPolarity_High ((uint16_t)0x0000) #define TIM_OCPolarity_Low ((uint16_t)0x0002) #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ ((POLARITY) == TIM_OCPolarity_Low)) /** * @} */ /** @defgroup TIM_Output_Compare_state * @{ */ #define TIM_OutputState_Disable ((uint16_t)0x0000) #define TIM_OutputState_Enable ((uint16_t)0x0001) #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ ((STATE) == TIM_OutputState_Enable)) /** * @} */ /** @defgroup TIM_Capture_Compare_state * @{ */ #define TIM_CCx_Enable ((uint16_t)0x0001) #define TIM_CCx_Disable ((uint16_t)0x0000) #define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ ((CCX) == TIM_CCx_Disable)) /** * @} */ /** @defgroup TIM_Input_Capture_Polarity * @{ */ #define TIM_ICPolarity_Rising ((uint16_t)0x0000) #define TIM_ICPolarity_Falling ((uint16_t)0x0002) #define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ ((POLARITY) == TIM_ICPolarity_Falling)|| \ ((POLARITY) == TIM_ICPolarity_BothEdge)) /** * @} */ /** @defgroup TIM_Input_Capture_Selection * @{ */ #define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ #define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively. */ #define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ ((SELECTION) == TIM_ICSelection_IndirectTI) || \ ((SELECTION) == TIM_ICSelection_TRC)) /** * @} */ /** @defgroup TIM_Input_Capture_Prescaler * @{ */ #define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ #define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ #define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ #define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ ((PRESCALER) == TIM_ICPSC_DIV2) || \ ((PRESCALER) == TIM_ICPSC_DIV4) || \ ((PRESCALER) == TIM_ICPSC_DIV8)) /** * @} */ /** @defgroup TIM_interrupt_sources * @{ */ #define TIM_IT_Update ((uint16_t)0x0001) #define TIM_IT_CC1 ((uint16_t)0x0002) #define TIM_IT_CC2 ((uint16_t)0x0004) #define TIM_IT_CC3 ((uint16_t)0x0008) #define TIM_IT_CC4 ((uint16_t)0x0010) #define TIM_IT_Trigger ((uint16_t)0x0040) #define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFFA0) == 0x0000) && ((IT) != 0x0000)) #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ ((IT) == TIM_IT_CC1) || \ ((IT) == TIM_IT_CC2) || \ ((IT) == TIM_IT_CC3) || \ ((IT) == TIM_IT_CC4) || \ ((IT) == TIM_IT_Trigger)) /** * @} */ /** @defgroup TIM_DMA_Base_address * @{ */ #define TIM_DMABase_CR1 ((uint16_t)0x0000) #define TIM_DMABase_CR2 ((uint16_t)0x0001) #define TIM_DMABase_SMCR ((uint16_t)0x0002) #define TIM_DMABase_DIER ((uint16_t)0x0003) #define TIM_DMABase_SR ((uint16_t)0x0004) #define TIM_DMABase_EGR ((uint16_t)0x0005) #define TIM_DMABase_CCMR1 ((uint16_t)0x0006) #define TIM_DMABase_CCMR2 ((uint16_t)0x0007) #define TIM_DMABase_CCER ((uint16_t)0x0008) #define TIM_DMABase_CNT ((uint16_t)0x0009) #define TIM_DMABase_PSC ((uint16_t)0x000A) #define TIM_DMABase_ARR ((uint16_t)0x000B) #define TIM_DMABase_CCR1 ((uint16_t)0x000D) #define TIM_DMABase_CCR2 ((uint16_t)0x000E) #define TIM_DMABase_CCR3 ((uint16_t)0x000F) #define TIM_DMABase_CCR4 ((uint16_t)0x0010) #define TIM_DMABase_DCR ((uint16_t)0x0012) #define TIM_DMABase_OR ((uint16_t)0x0013) #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ ((BASE) == TIM_DMABase_CR2) || \ ((BASE) == TIM_DMABase_SMCR) || \ ((BASE) == TIM_DMABase_DIER) || \ ((BASE) == TIM_DMABase_SR) || \ ((BASE) == TIM_DMABase_EGR) || \ ((BASE) == TIM_DMABase_CCMR1) || \ ((BASE) == TIM_DMABase_CCMR2) || \ ((BASE) == TIM_DMABase_CCER) || \ ((BASE) == TIM_DMABase_CNT) || \ ((BASE) == TIM_DMABase_PSC) || \ ((BASE) == TIM_DMABase_ARR) || \ ((BASE) == TIM_DMABase_CCR1) || \ ((BASE) == TIM_DMABase_CCR2) || \ ((BASE) == TIM_DMABase_CCR3) || \ ((BASE) == TIM_DMABase_CCR4) || \ ((BASE) == TIM_DMABase_DCR) || \ ((BASE) == TIM_DMABase_OR)) /** * @} */ /** @defgroup TIM_DMA_Burst_Length * @{ */ #define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) #define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) #define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) #define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) #define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) #define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) #define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) #define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) #define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) #define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) #define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) #define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) #define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) #define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) #define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) #define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) #define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) #define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ ((LENGTH) == TIM_DMABurstLength_18Transfers)) /** * @} */ /** @defgroup TIM_DMA_sources * @{ */ #define TIM_DMA_Update ((uint16_t)0x0100) #define TIM_DMA_CC1 ((uint16_t)0x0200) #define TIM_DMA_CC2 ((uint16_t)0x0400) #define TIM_DMA_CC3 ((uint16_t)0x0800) #define TIM_DMA_CC4 ((uint16_t)0x1000) #define TIM_DMA_Trigger ((uint16_t)0x4000) #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xA0FF) == 0x0000) && ((SOURCE) != 0x0000)) /** * @} */ /** @defgroup TIM_External_Trigger_Prescaler * @{ */ #define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) #define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) #define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) #define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) #define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) /** * @} */ /** @defgroup TIM_Internal_Trigger_Selection * @{ */ #define TIM_TS_ITR0 ((uint16_t)0x0000) #define TIM_TS_ITR1 ((uint16_t)0x0010) #define TIM_TS_ITR2 ((uint16_t)0x0020) #define TIM_TS_ITR3 ((uint16_t)0x0030) #define TIM_TS_TI1F_ED ((uint16_t)0x0040) #define TIM_TS_TI1FP1 ((uint16_t)0x0050) #define TIM_TS_TI2FP2 ((uint16_t)0x0060) #define TIM_TS_ETRF ((uint16_t)0x0070) #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ ((SELECTION) == TIM_TS_ITR1) || \ ((SELECTION) == TIM_TS_ITR2) || \ ((SELECTION) == TIM_TS_ITR3) || \ ((SELECTION) == TIM_TS_TI1F_ED) || \ ((SELECTION) == TIM_TS_TI1FP1) || \ ((SELECTION) == TIM_TS_TI2FP2) || \ ((SELECTION) == TIM_TS_ETRF)) #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ ((SELECTION) == TIM_TS_ITR1) || \ ((SELECTION) == TIM_TS_ITR2) || \ ((SELECTION) == TIM_TS_ITR3)) /** * @} */ /** @defgroup TIM_TIx_External_Clock_Source * @{ */ #define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) #define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) #define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) /** * @} */ /** @defgroup TIM_External_Trigger_Polarity * @{ */ #define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) #define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) #define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) /** * @} */ /** @defgroup TIM_Prescaler_Reload_Mode * @{ */ #define TIM_PSCReloadMode_Update ((uint16_t)0x0000) #define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) #define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ ((RELOAD) == TIM_PSCReloadMode_Immediate)) /** * @} */ /** @defgroup TIM_Forced_Action * @{ */ #define TIM_ForcedAction_Active ((uint16_t)0x0050) #define TIM_ForcedAction_InActive ((uint16_t)0x0040) #define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ ((ACTION) == TIM_ForcedAction_InActive)) /** * @} */ /** @defgroup TIM_Encoder_Mode * @{ */ #define TIM_EncoderMode_TI1 ((uint16_t)0x0001) #define TIM_EncoderMode_TI2 ((uint16_t)0x0002) #define TIM_EncoderMode_TI12 ((uint16_t)0x0003) #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ ((MODE) == TIM_EncoderMode_TI2) || \ ((MODE) == TIM_EncoderMode_TI12)) /** * @} */ /** @defgroup TIM_Event_Source * @{ */ #define TIM_EventSource_Update ((uint16_t)0x0001) #define TIM_EventSource_CC1 ((uint16_t)0x0002) #define TIM_EventSource_CC2 ((uint16_t)0x0004) #define TIM_EventSource_CC3 ((uint16_t)0x0008) #define TIM_EventSource_CC4 ((uint16_t)0x0010) #define TIM_EventSource_Trigger ((uint16_t)0x0040) #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFFA0) == 0x0000) && ((SOURCE) != 0x0000)) /** * @} */ /** @defgroup TIM_Update_Source * @{ */ #define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow or the setting of UG bit, or an update generation through the slave mode controller. */ #define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ ((SOURCE) == TIM_UpdateSource_Regular)) /** * @} */ /** @defgroup TIM_Output_Compare_Preload_State * @{ */ #define TIM_OCPreload_Enable ((uint16_t)0x0008) #define TIM_OCPreload_Disable ((uint16_t)0x0000) #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ ((STATE) == TIM_OCPreload_Disable)) /** * @} */ /** @defgroup TIM_Output_Compare_Fast_State * @{ */ #define TIM_OCFast_Enable ((uint16_t)0x0004) #define TIM_OCFast_Disable ((uint16_t)0x0000) #define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ ((STATE) == TIM_OCFast_Disable)) /** * @} */ /** @defgroup TIM_Output_Compare_Clear_State * @{ */ #define TIM_OCClear_Enable ((uint16_t)0x0080) #define TIM_OCClear_Disable ((uint16_t)0x0000) #define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ ((STATE) == TIM_OCClear_Disable)) /** * @} */ /** @defgroup TIM_Trigger_Output_Source * @{ */ #define TIM_TRGOSource_Reset ((uint16_t)0x0000) #define TIM_TRGOSource_Enable ((uint16_t)0x0010) #define TIM_TRGOSource_Update ((uint16_t)0x0020) #define TIM_TRGOSource_OC1 ((uint16_t)0x0030) #define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) #define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) #define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) #define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ ((SOURCE) == TIM_TRGOSource_Enable) || \ ((SOURCE) == TIM_TRGOSource_Update) || \ ((SOURCE) == TIM_TRGOSource_OC1) || \ ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ ((SOURCE) == TIM_TRGOSource_OC4Ref)) /** * @} */ /** @defgroup TIM_Slave_Mode * @{ */ #define TIM_SlaveMode_Reset ((uint16_t)0x0004) #define TIM_SlaveMode_Gated ((uint16_t)0x0005) #define TIM_SlaveMode_Trigger ((uint16_t)0x0006) #define TIM_SlaveMode_External1 ((uint16_t)0x0007) #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ ((MODE) == TIM_SlaveMode_Gated) || \ ((MODE) == TIM_SlaveMode_Trigger) || \ ((MODE) == TIM_SlaveMode_External1)) /** * @} */ /** @defgroup TIM_Master_Slave_Mode * @{ */ #define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) #define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ ((STATE) == TIM_MasterSlaveMode_Disable)) /** * @} */ /** @defgroup TIM_Flags * @{ */ #define TIM_FLAG_Update ((uint16_t)0x0001) #define TIM_FLAG_CC1 ((uint16_t)0x0002) #define TIM_FLAG_CC2 ((uint16_t)0x0004) #define TIM_FLAG_CC3 ((uint16_t)0x0008) #define TIM_FLAG_CC4 ((uint16_t)0x0010) #define TIM_FLAG_Trigger ((uint16_t)0x0040) #define TIM_FLAG_CC1OF ((uint16_t)0x0200) #define TIM_FLAG_CC2OF ((uint16_t)0x0400) #define TIM_FLAG_CC3OF ((uint16_t)0x0800) #define TIM_FLAG_CC4OF ((uint16_t)0x1000) #define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ ((FLAG) == TIM_FLAG_CC1) || \ ((FLAG) == TIM_FLAG_CC2) || \ ((FLAG) == TIM_FLAG_CC3) || \ ((FLAG) == TIM_FLAG_CC4) || \ ((FLAG) == TIM_FLAG_Trigger) || \ ((FLAG) == TIM_FLAG_CC1OF) || \ ((FLAG) == TIM_FLAG_CC2OF) || \ ((FLAG) == TIM_FLAG_CC3OF) || \ ((FLAG) == TIM_FLAG_CC4OF)) #define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE1A0) == 0x0000) && ((TIM_FLAG) != 0x0000)) /** * @} */ /** @defgroup TIM_Input_Capture_Filer_Value * @{ */ #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) /** * @} */ /** @defgroup TIM_External_Trigger_Filter * @{ */ #define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) /** * @} */ /** @defgroup TIM_OCReferenceClear * @{ */ #define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008) #define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000) #define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \ ((SOURCE) == TIM_OCReferenceClear_OCREFCLR)) /** * @} */ /** @defgroup TIM_Remap * @{ */ #define TIM2_TIM10_OC ((uint32_t)0xFFFE0000) #define TIM2_TIM5_TRGO ((uint32_t)0xFFFE0001) #define TIM3_TIM11_OC ((uint32_t)0xFFFE0000) #define TIM3_TIM5_TRGO ((uint32_t)0xFFFE0001) #define TIM9_GPIO ((uint32_t)0xFFFC0000) #define TIM9_LSE ((uint32_t)0xFFFC0001) #define TIM9_TIM3_TRGO ((uint32_t)0xFFFB0000) #define TIM9_TS_IO ((uint32_t)0xFFFB0004) #define TIM10_GPIO ((uint32_t)0xFFF40000) #define TIM10_LSI ((uint32_t)0xFFF40001) #define TIM10_LSE ((uint32_t)0xFFF40002) #define TIM10_RTC ((uint32_t)0xFFF40003) #define TIM10_RI ((uint32_t)0xFFF40008) #define TIM10_ETR_LSE ((uint32_t)0xFFFB0000) #define TIM10_ETR_TIM9_TRGO ((uint32_t)0xFFFB0004) #define TIM11_GPIO ((uint32_t)0xFFF40000) #define TIM11_MSI ((uint32_t)0xFFF40001) #define TIM11_HSE_RTC ((uint32_t)0xFFF40002) #define TIM11_RI ((uint32_t)0xFFF40008) #define TIM11_ETR_LSE ((uint32_t)0xFFFB0000) #define TIM11_ETR_TIM9_TRGO ((uint32_t)0xFFFB0004) #define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM2_TIM10_OC)|| \ ((TIM_REMAP) == TIM2_TIM5_TRGO)|| \ ((TIM_REMAP) == TIM3_TIM11_OC)|| \ ((TIM_REMAP) == TIM3_TIM5_TRGO)|| \ ((TIM_REMAP) == TIM9_GPIO)|| \ ((TIM_REMAP) == TIM9_LSE)|| \ ((TIM_REMAP) == TIM9_TIM3_TRGO)|| \ ((TIM_REMAP) == TIM9_TS_IO)|| \ ((TIM_REMAP) == TIM10_GPIO)|| \ ((TIM_REMAP) == TIM10_LSI)|| \ ((TIM_REMAP) == TIM10_LSE)|| \ ((TIM_REMAP) == TIM10_RTC)|| \ ((TIM_REMAP) == TIM10_RI)|| \ ((TIM_REMAP) == TIM10_ETR_LSE)|| \ ((TIM_REMAP) == TIM10_ETR_TIM9_TRGO)|| \ ((TIM_REMAP) == TIM11_GPIO)|| \ ((TIM_REMAP) == TIM11_MSI)|| \ ((TIM_REMAP) == TIM11_HSE_RTC)|| \ ((TIM_REMAP) == TIM11_RI)|| \ ((TIM_REMAP) == TIM11_ETR_LSE)|| \ ((TIM_REMAP) == TIM11_ETR_TIM9_TRGO)) /** * @} */ /** @defgroup TIM_Legacy * @{ */ #define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer #define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers #define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers #define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers #define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers #define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers #define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers #define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers #define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers #define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers #define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers #define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers #define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers #define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers #define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers #define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers #define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers #define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ /* TimeBase management ********************************************************/ void TIM_DeInit(TIM_TypeDef* TIMx); void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter); void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload); uint32_t TIM_GetCounter(TIM_TypeDef* TIMx); uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); /* Output Compare management **************************************************/ void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1); void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2); void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3); void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4); void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear); void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); /* Input Capture management ***************************************************/ void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx); uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx); uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx); uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx); void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); /* Interrupts, DMA and flags management ***************************************/ void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); /* Clocks management **********************************************************/ void TIM_InternalClockConfig(TIM_TypeDef* TIMx); void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t TIM_ICPolarity, uint16_t ICFilter); void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); /* Synchronization management *************************************************/ void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); /* Specific interface management **********************************************/ void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); /* Specific remapping management **********************************************/ void TIM_RemapConfig(TIM_TypeDef* TIMx, uint32_t TIM_Remap); #ifdef __cplusplus } #endif #endif /*__STM32L1xx_TIM_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/inc/stm32l1xx_usart.h
New file @@ -0,0 +1,427 @@ /** ****************************************************************************** * @file stm32l1xx_usart.h * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file contains all the functions prototypes for the USART * firmware library. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L1xx_USART_H #define __STM32L1xx_USART_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @addtogroup USART * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief USART Init Structure definition */ typedef struct { uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. The baud rate is computed using the following formula: - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate))) - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */ uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of @ref USART_Word_Length */ uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. This parameter can be a value of @ref USART_Stop_Bits */ uint16_t USART_Parity; /*!< Specifies the parity mode. This parameter can be a value of @ref USART_Parity @note When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits). */ uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of @ref USART_Mode */ uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled or disabled. This parameter can be a value of @ref USART_Hardware_Flow_Control */ } USART_InitTypeDef; /** * @brief USART Clock Init Structure definition */ typedef struct { uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. This parameter can be a value of @ref USART_Clock */ uint16_t USART_CPOL; /*!< Specifies the steady state of the serial clock. This parameter can be a value of @ref USART_Clock_Polarity */ uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. This parameter can be a value of @ref USART_Clock_Phase */ uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of @ref USART_Last_Bit */ } USART_ClockInitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup USART_Exported_Constants * @{ */ #define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ ((PERIPH) == USART2) || \ ((PERIPH) == USART3) || \ ((PERIPH) == UART4) || \ ((PERIPH) == UART5)) #define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \ ((PERIPH) == USART2) || \ ((PERIPH) == USART3)) /** @defgroup USART_Word_Length * @{ */ #define USART_WordLength_8b ((uint16_t)0x0000) #define USART_WordLength_9b ((uint16_t)0x1000) #define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ ((LENGTH) == USART_WordLength_9b)) /** * @} */ /** @defgroup USART_Stop_Bits * @{ */ #define USART_StopBits_1 ((uint16_t)0x0000) #define USART_StopBits_0_5 ((uint16_t)0x1000) #define USART_StopBits_2 ((uint16_t)0x2000) #define USART_StopBits_1_5 ((uint16_t)0x3000) #define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ ((STOPBITS) == USART_StopBits_0_5) || \ ((STOPBITS) == USART_StopBits_2) || \ ((STOPBITS) == USART_StopBits_1_5)) /** * @} */ /** @defgroup USART_Parity * @{ */ #define USART_Parity_No ((uint16_t)0x0000) #define USART_Parity_Even ((uint16_t)0x0400) #define USART_Parity_Odd ((uint16_t)0x0600) #define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ ((PARITY) == USART_Parity_Even) || \ ((PARITY) == USART_Parity_Odd)) /** * @} */ /** @defgroup USART_Mode * @{ */ #define USART_Mode_Rx ((uint16_t)0x0004) #define USART_Mode_Tx ((uint16_t)0x0008) #define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) /** * @} */ /** @defgroup USART_Hardware_Flow_Control * @{ */ #define USART_HardwareFlowControl_None ((uint16_t)0x0000) #define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) #define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) #define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) #define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ (((CONTROL) == USART_HardwareFlowControl_None) || \ ((CONTROL) == USART_HardwareFlowControl_RTS) || \ ((CONTROL) == USART_HardwareFlowControl_CTS) || \ ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) /** * @} */ /** @defgroup USART_Clock * @{ */ #define USART_Clock_Disable ((uint16_t)0x0000) #define USART_Clock_Enable ((uint16_t)0x0800) #define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ ((CLOCK) == USART_Clock_Enable)) /** * @} */ /** @defgroup USART_Clock_Polarity * @{ */ #define USART_CPOL_Low ((uint16_t)0x0000) #define USART_CPOL_High ((uint16_t)0x0400) #define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) /** * @} */ /** @defgroup USART_Clock_Phase * @{ */ #define USART_CPHA_1Edge ((uint16_t)0x0000) #define USART_CPHA_2Edge ((uint16_t)0x0200) #define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) /** * @} */ /** @defgroup USART_Last_Bit * @{ */ #define USART_LastBit_Disable ((uint16_t)0x0000) #define USART_LastBit_Enable ((uint16_t)0x0100) #define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ ((LASTBIT) == USART_LastBit_Enable)) /** * @} */ /** @defgroup USART_Interrupt_definition * @{ */ #define USART_IT_PE ((uint16_t)0x0028) #define USART_IT_TXE ((uint16_t)0x0727) #define USART_IT_TC ((uint16_t)0x0626) #define USART_IT_RXNE ((uint16_t)0x0525) #define USART_IT_IDLE ((uint16_t)0x0424) #define USART_IT_LBD ((uint16_t)0x0846) #define USART_IT_ORE_RX ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */ #define USART_IT_CTS ((uint16_t)0x096A) #define USART_IT_ERR ((uint16_t)0x0060) #define USART_IT_ORE_ER ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */ #define USART_IT_NE ((uint16_t)0x0260) #define USART_IT_FE ((uint16_t)0x0160) /** @defgroup USART_Legacy * @{ */ #define USART_IT_ORE USART_IT_ORE_ER /** * @} */ #define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) #define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE_RX) || \ ((IT) == USART_IT_ORE_ER) || ((IT) == USART_IT_NE) || \ ((IT) == USART_IT_FE)) #define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) /** * @} */ /** @defgroup USART_DMA_Requests * @{ */ #define USART_DMAReq_Tx ((uint16_t)0x0080) #define USART_DMAReq_Rx ((uint16_t)0x0040) #define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) /** * @} */ /** @defgroup USART_WakeUp_methods * @{ */ #define USART_WakeUp_IdleLine ((uint16_t)0x0000) #define USART_WakeUp_AddressMark ((uint16_t)0x0800) #define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ ((WAKEUP) == USART_WakeUp_AddressMark)) /** * @} */ /** @defgroup USART_LIN_Break_Detection_Length * @{ */ #define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) #define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) #define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ (((LENGTH) == USART_LINBreakDetectLength_10b) || \ ((LENGTH) == USART_LINBreakDetectLength_11b)) /** * @} */ /** @defgroup USART_IrDA_Low_Power * @{ */ #define USART_IrDAMode_LowPower ((uint16_t)0x0004) #define USART_IrDAMode_Normal ((uint16_t)0x0000) #define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ ((MODE) == USART_IrDAMode_Normal)) /** * @} */ /** @defgroup USART_Flags * @{ */ #define USART_FLAG_CTS ((uint16_t)0x0200) #define USART_FLAG_LBD ((uint16_t)0x0100) #define USART_FLAG_TXE ((uint16_t)0x0080) #define USART_FLAG_TC ((uint16_t)0x0040) #define USART_FLAG_RXNE ((uint16_t)0x0020) #define USART_FLAG_IDLE ((uint16_t)0x0010) #define USART_FLAG_ORE ((uint16_t)0x0008) #define USART_FLAG_NE ((uint16_t)0x0004) #define USART_FLAG_FE ((uint16_t)0x0002) #define USART_FLAG_PE ((uint16_t)0x0001) #define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) #define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) #define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x003D0901)) #define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) #define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ /* Function used to set the USART configuration to the default reset state ***/ void USART_DeInit(USART_TypeDef* USARTx); /* Initialization and Configuration functions *********************************/ void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); void USART_StructInit(USART_InitTypeDef* USART_InitStruct); void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); /* Data transfers functions ***************************************************/ void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); uint16_t USART_ReceiveData(USART_TypeDef* USARTx); /* Multi-Processor Communication functions ************************************/ void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); /* LIN mode functions *********************************************************/ void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); void USART_SendBreak(USART_TypeDef* USARTx); /* Half-duplex mode function **************************************************/ void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); /* Smartcard mode functions ***************************************************/ void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); /* IrDA mode functions ********************************************************/ void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); /* DMA transfers management functions *****************************************/ void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); /* Interrupts and flags management functions **********************************/ void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); #ifdef __cplusplus } #endif #endif /* __STM32L1xx_USART_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/inc/stm32l1xx_wwdg.h
New file @@ -0,0 +1,110 @@ /** ****************************************************************************** * @file stm32l1xx_wwdg.h * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file contains all the functions prototypes for the WWDG * firmware library. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L1xx_WWDG_H #define __STM32L1xx_WWDG_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @addtogroup WWDG * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup WWDG_Exported_Constants * @{ */ /** @defgroup WWDG_Prescaler * @{ */ #define WWDG_Prescaler_1 ((uint32_t)0x00000000) #define WWDG_Prescaler_2 ((uint32_t)0x00000080) #define WWDG_Prescaler_4 ((uint32_t)0x00000100) #define WWDG_Prescaler_8 ((uint32_t)0x00000180) #define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ ((PRESCALER) == WWDG_Prescaler_2) || \ ((PRESCALER) == WWDG_Prescaler_4) || \ ((PRESCALER) == WWDG_Prescaler_8)) #define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) #define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ /* Function used to set the WWDG configuration to the default reset state ****/ void WWDG_DeInit(void); /* Prescaler, Refresh window and Counter configuration functions **************/ void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); void WWDG_SetWindowValue(uint8_t WindowValue); void WWDG_EnableIT(void); void WWDG_SetCounter(uint8_t Counter); /* WWDG activation functions **************************************************/ void WWDG_Enable(uint8_t Counter); /* Interrupts and flags management functions **********************************/ FlagStatus WWDG_GetFlagStatus(void); void WWDG_ClearFlag(void); #ifdef __cplusplus } #endif #endif /* __STM32L1xx_WWDG_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/src/misc.c
New file @@ -0,0 +1,251 @@ /** ****************************************************************************** * @file misc.c * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file provides all the miscellaneous firmware functions (add-on * to CMSIS functions). ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "misc.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @defgroup MISC * @brief MISC driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup MISC_Private_Functions * @{ */ /** * @verbatim ******************************************************************************* ##### Interrupts configuration functions ##### ******************************************************************************* [..] This section provide functions allowing to configure the NVIC interrupts (IRQ).The Cortex-M3 exceptions are managed by CMSIS functions. (#) Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig() function according to the following table. The table below gives the allowed values of the preemption priority and subpriority according to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function. ============================================================================================================================ NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description ============================================================================================================================ NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for preemption priority | | | 4 bits for subpriority ---------------------------------------------------------------------------------------------------------------------------- NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for preemption priority | | | 3 bits for subpriority ---------------------------------------------------------------------------------------------------------------------------- NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for preemption priority | | | 2 bits for subpriority ---------------------------------------------------------------------------------------------------------------------------- NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for preemption priority | | | 1 bits for subpriority ---------------------------------------------------------------------------------------------------------------------------- NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for preemption priority | | | 0 bits for subpriority ============================================================================================================================ (#) Enable and Configure the priority of the selected IRQ Channels. -@- When the NVIC_PriorityGroup_0 is selected, it will no any nested interrupt, the IRQ priority will be managed only by subpriority. The sub-priority is only used to sort pending exception priorities, and does not affect active exceptions. -@- Lower priority values gives higher priority. -@- Priority Order: (#@) Lowest Preemption priority. (#@) Lowest Subpriority. (#@) Lowest hardware priority (IRQn position). @endverbatim */ /** * @brief Configures the priority grouping: preemption priority and subpriority. * @param NVIC_PriorityGroup: specifies the priority grouping bits length. * This parameter can be one of the following values: * @arg NVIC_PriorityGroup_0: 0 bits for preemption priority * 4 bits for subpriority. * @note When NVIC_PriorityGroup_0 is selected, it will no be any nested * interrupt. This interrupts priority is managed only with subpriority. * @arg NVIC_PriorityGroup_1: 1 bits for preemption priority. * 3 bits for subpriority. * @arg NVIC_PriorityGroup_2: 2 bits for preemption priority. * 2 bits for subpriority. * @arg NVIC_PriorityGroup_3: 3 bits for preemption priority. * 1 bits for subpriority. * @arg NVIC_PriorityGroup_4: 4 bits for preemption priority. * 0 bits for subpriority. * @retval None */ void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) { /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; } /** * @brief Initializes the NVIC peripheral according to the specified * parameters in the NVIC_InitStruct. * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() * function should be called before. * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains * the configuration information for the specified NVIC peripheral. * @retval None */ void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) { uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) { /* Compute the Corresponding IRQ Priority --------------------------------*/ tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; tmppre = (0x4 - tmppriority); tmpsub = tmpsub >> tmppriority; tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; tmppriority |= (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub); tmppriority = tmppriority << 0x04; NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; /* Enable the Selected IRQ Channels --------------------------------------*/ NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); } else { /* Disable the Selected IRQ Channels -------------------------------------*/ NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); } } /** * @brief Sets the vector table location and Offset. * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. * This parameter can be one of the following values: * @arg NVIC_VectTab_RAM: Vector Table in internal SRAM. * @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH. * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200. * @retval None */ void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) { /* Check the parameters */ assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); assert_param(IS_NVIC_OFFSET(Offset)); SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); } /** * @brief Selects the condition for the system to enter low power mode. * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. * This parameter can be one of the following values: * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend. * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request. * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit. * @param NewState: new state of LP condition. * This parameter can be: ENABLE or DISABLE. * @retval None */ void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_NVIC_LP(LowPowerMode)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { SCB->SCR |= LowPowerMode; } else { SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); } } /** * @brief Configures the SysTick clock source. * @param SysTick_CLKSource: specifies the SysTick clock source. * This parameter can be one of the following values: * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. * @retval None */ void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) { /* Check the parameters */ assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); if (SysTick_CLKSource == SysTick_CLKSource_HCLK) { SysTick->CTRL |= SysTick_CLKSource_HCLK; } else { SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; } } /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/src/stm32l1xx_adc.c
New file @@ -0,0 +1,1909 @@ /** ****************************************************************************** * @file stm32l1xx_adc.c * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) peripheral: * + Initialization and Configuration * + Power saving * + Analog Watchdog configuration * + Temperature Sensor & Vrefint (Voltage Reference internal) management * + Regular Channels Configuration * + Regular Channels DMA Configuration * + Injected channels Configuration * + Interrupts and flags management * * @verbatim ================================================================================ ##### How to use this driver ##### ================================================================================ [..] (#) Configure the ADC Prescaler, conversion resolution and data alignment using the ADC_Init() function. (#) Activate the ADC peripheral using ADC_Cmd() function. *** Regular channels group configuration *** ============================================ [..] (+) To configure the ADC regular channels group features, use ADC_Init() and ADC_RegularChannelConfig() functions. (+) To activate the continuous mode, use the ADC_continuousModeCmd() function. (+) To configurate and activate the Discontinuous mode, use the ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions. (+) To read the ADC converted values, use the ADC_GetConversionValue() function. *** DMA for Regular channels group features configuration *** ============================================================= [..] (+) To enable the DMA mode for regular channels group, use the ADC_DMACmd() function. (+) To enable the generation of DMA requests continuously at the end of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd() function. *** Injected channels group configuration *** ============================================= [..] (+) To configure the ADC Injected channels group features, use ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig() functions. (+) To activate the continuous mode, use the ADC_continuousModeCmd() function. (+) To activate the Injected Discontinuous mode, use the ADC_InjectedDiscModeCmd() function. (+) To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd() function. (+) To read the ADC converted values, use the ADC_GetInjectedConversionValue() function. @endverbatim * ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx_adc.h" #include "stm32l1xx_rcc.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @defgroup ADC * @brief ADC driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* ADC DISCNUM mask */ #define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF) /* ADC AWDCH mask */ #define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0) /* ADC Analog watchdog enable mode mask */ #define CR1_AWDMODE_RESET ((uint32_t)0xFF3FFDFF) /* CR1 register Mask */ #define CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF) /* ADC DELAY mask */ #define CR2_DELS_RESET ((uint32_t)0xFFFFFF0F) /* ADC JEXTEN mask */ #define CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF) /* ADC JEXTSEL mask */ #define CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF) /* CR2 register Mask */ #define CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD) /* ADC SQx mask */ #define SQR5_SQ_SET ((uint32_t)0x0000001F) #define SQR4_SQ_SET ((uint32_t)0x0000001F) #define SQR3_SQ_SET ((uint32_t)0x0000001F) #define SQR2_SQ_SET ((uint32_t)0x0000001F) #define SQR1_SQ_SET ((uint32_t)0x0000001F) /* ADC L Mask */ #define SQR1_L_RESET ((uint32_t)0xFE0FFFFF) /* ADC JSQx mask */ #define JSQR_JSQ_SET ((uint32_t)0x0000001F) /* ADC JL mask */ #define JSQR_JL_SET ((uint32_t)0x00300000) #define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF) /* ADC SMPx mask */ #define SMPR1_SMP_SET ((uint32_t)0x00000007) #define SMPR2_SMP_SET ((uint32_t)0x00000007) #define SMPR3_SMP_SET ((uint32_t)0x00000007) #define SMPR0_SMP_SET ((uint32_t)0x00000007) /* ADC JDRx registers offset */ #define JDR_OFFSET ((uint8_t)0x30) /* ADC CCR register Mask */ #define CR_CLEAR_MASK ((uint32_t)0xFFFCFFFF) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup ADC_Private_Functions * @{ */ /** @defgroup ADC_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions. * @verbatim =============================================================================== ##### Initialization and Configuration functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the ADC Prescaler. (+) ADC Conversion Resolution (12bit..6bit). (+) Scan Conversion Mode (multichannel or one channel) for regular group. (+) ADC Continuous Conversion Mode (Continuous or Single conversion) for regular group. (+) External trigger Edge and source of regular group. (+) Converted data alignment (left or right). (+) The number of ADC conversions that will be done using the sequencer for regular channel group. (+) Enable or disable the ADC peripheral. @endverbatim * @{ */ /** * @brief Deinitializes ADC1 peripheral registers to their default reset values. * @param None * @retval None */ void ADC_DeInit(ADC_TypeDef* ADCx) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); if(ADCx == ADC1) { /* Enable ADC1 reset state */ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); /* Release ADC1 from reset state */ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); } } /** * @brief Initializes the ADCx peripheral according to the specified parameters * in the ADC_InitStruct. * @note This function is used to configure the global features of the ADC ( * Resolution and Data Alignment), however, the rest of the configuration * parameters are specific to the regular channels group (scan mode * activation, continuous mode activation, External trigger source and * edge, number of conversion in the regular channels group sequencer). * @param ADCx: where x can be 1 to select the ADC peripheral. * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains * the configuration information for the specified ADC peripheral. * @retval None */ void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) { uint32_t tmpreg1 = 0; uint8_t tmpreg2 = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution)); assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge)); assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfConversion)); /*---------------------------- ADCx CR1 Configuration -----------------*/ /* Get the ADCx CR1 value */ tmpreg1 = ADCx->CR1; /* Clear RES and SCAN bits */ tmpreg1 &= CR1_CLEAR_MASK; /* Configure ADCx: scan conversion mode and resolution */ /* Set SCAN bit according to ADC_ScanConvMode value */ /* Set RES bit according to ADC_Resolution value */ tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | ADC_InitStruct->ADC_Resolution); /* Write to ADCx CR1 */ ADCx->CR1 = tmpreg1; /*---------------------------- ADCx CR2 Configuration -----------------*/ /* Get the ADCx CR2 value */ tmpreg1 = ADCx->CR2; /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */ tmpreg1 &= CR2_CLEAR_MASK; /* Configure ADCx: external trigger event and edge, data alignment and continuous conversion mode */ /* Set ALIGN bit according to ADC_DataAlign value */ /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */ /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ /* Set CONT bit according to ADC_ContinuousConvMode value */ tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | ADC_InitStruct->ADC_ExternalTrigConvEdge | ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); /* Write to ADCx CR2 */ ADCx->CR2 = tmpreg1; /*---------------------------- ADCx SQR1 Configuration -----------------*/ /* Get the ADCx SQR1 value */ tmpreg1 = ADCx->SQR1; /* Clear L bits */ tmpreg1 &= SQR1_L_RESET; /* Configure ADCx: regular channel sequence length */ /* Set L bits according to ADC_NbrOfConversion value */ tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1); tmpreg1 |= ((uint32_t)tmpreg2 << 20); /* Write to ADCx SQR1 */ ADCx->SQR1 = tmpreg1; } /** * @brief Fills each ADC_InitStruct member with its default value. * @note This function is used to initialize the global features of the ADC ( * Resolution and Data Alignment), however, the rest of the configuration * parameters are specific to the regular channels group (scan mode * activation, continuous mode activation, External trigger source and * edge, number of conversion in the regular channels group sequencer). * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will * be initialized. * @retval None */ void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) { /* Reset ADC init structure parameters values */ /* Initialize the ADC_Resolution member */ ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b; /* Initialize the ADC_ScanConvMode member */ ADC_InitStruct->ADC_ScanConvMode = DISABLE; /* Initialize the ADC_ContinuousConvMode member */ ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; /* Initialize the ADC_ExternalTrigConvEdge member */ ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; /* Initialize the ADC_ExternalTrigConv member */ ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T2_CC2; /* Initialize the ADC_DataAlign member */ ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; /* Initialize the ADC_NbrOfConversion member */ ADC_InitStruct->ADC_NbrOfConversion = 1; } /** * @brief Initializes the ADCs peripherals according to the specified parameters * in the ADC_CommonInitStruct. * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure * that contains the configuration information (Prescaler) for ADC1 peripheral. * @retval None */ void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler)); /*---------------------------- ADC CCR Configuration -----------------*/ /* Get the ADC CCR value */ tmpreg = ADC->CCR; /* Clear ADCPRE bit */ tmpreg &= CR_CLEAR_MASK; /* Configure ADCx: ADC prescaler according to ADC_Prescaler */ tmpreg |= (uint32_t)(ADC_CommonInitStruct->ADC_Prescaler); /* Write to ADC CCR */ ADC->CCR = tmpreg; } /** * @brief Fills each ADC_CommonInitStruct member with its default value. * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure * which will be initialized. * @retval None */ void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) { /* Reset ADC init structure parameters values */ /* Initialize the ADC_Prescaler member */ ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div1; } /** * @brief Enables or disables the specified ADC peripheral. * @param ADCx: where x can be 1 to select the ADC1 peripheral. * @param NewState: new state of the ADCx peripheral. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Set the ADON bit to wake up the ADC from power down mode */ ADCx->CR2 |= (uint32_t)ADC_CR2_ADON; } else { /* Disable the selected ADC peripheral */ ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON); } } /** * @brief Selects the specified ADC Channels Bank. * @param ADCx: where x can be 1 to select the ADC1 peripheral. * @param ADC_Bank: ADC Channels Bank. * @arg ADC_Bank_A: ADC Channels Bank A. * @arg ADC_Bank_B: ADC Channels Bank B. * @retval None */ void ADC_BankSelection(ADC_TypeDef* ADCx, uint8_t ADC_Bank) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_BANK(ADC_Bank)); if (ADC_Bank != ADC_Bank_A) { /* Set the ADC_CFG bit to select the ADC Bank B channels */ ADCx->CR2 |= (uint32_t)ADC_CR2_CFG; } else { /* Reset the ADC_CFG bit to select the ADC Bank A channels */ ADCx->CR2 &= (uint32_t)(~ADC_CR2_CFG); } } /** * @} */ /** @defgroup ADC_Group2 Power saving functions * @brief Power saving functions * @verbatim =============================================================================== ##### Power saving functions ##### =============================================================================== [..] This section provides functions allowing to reduce power consumption. [..] The two function must be combined to get the maximal benefits: When the ADC frequency is higher than the CPU one, it is recommended to: (#) Insert a freeze delay : ==> using ADC_DelaySelectionConfig(ADC1, ADC_DelayLength_Freeze). (#) Enable the power down in Idle and Delay phases : ==> using ADC_PowerDownCmd(ADC1, ADC_PowerDown_Idle_Delay, ENABLE). @endverbatim * @{ */ /** * @brief Enables or disables the ADC Power Down during Delay and/or Idle phase. * @note ADC power-on and power-off can be managed by hardware to cut the * consumption when the ADC is not converting. * @param ADCx: where x can be 1 to select the ADC1 peripheral. * @param ADC_PowerDown: The ADC power down configuration. * This parameter can be one of the following values: * @arg ADC_PowerDown_Delay: ADC is powered down during delay phase. * @arg ADC_PowerDown_Idle: ADC is powered down during Idle phase. * @arg ADC_PowerDown_Idle_Delay: ADC is powered down during Delay and Idle phases. * @note The ADC can be powered down: * @note During the hardware delay insertion (using the ADC_PowerDown_Delay * parameter). * => The ADC is powered up again at the end of the delay. * @note During the ADC is waiting for a trigger event ( using the * ADC_PowerDown_Idle parameter). * => The ADC is powered up at the next trigger event. * @note During the hardware delay insertion or the ADC is waiting for a * trigger event (using the ADC_PowerDown_Idle_Delay parameter). * => The ADC is powered up only at the end of the delay and at the * next trigger event. * @param NewState: new state of the ADCx power down. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_PowerDownCmd(ADC_TypeDef* ADCx, uint32_t ADC_PowerDown, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); assert_param(IS_ADC_POWER_DOWN(ADC_PowerDown)); if (NewState != DISABLE) { /* Enable the ADC power-down during Delay and/or Idle phase */ ADCx->CR1 |= ADC_PowerDown; } else { /* Disable The ADC power-down during Delay and/or Idle phase */ ADCx->CR1 &= (uint32_t)~ADC_PowerDown; } } /** * @brief Defines the length of the delay which is applied after a conversion * or a sequence of conversion. * @note When the CPU clock is not fast enough to manage the data rate, a * Hardware delay can be introduced between ADC conversions to reduce * this data rate. * @note The Hardware delay is inserted after : * - each regular conversion. * - after each sequence of injected conversions. * @note No Hardware delay is inserted between conversions of different groups. * @note When the hardware delay is not enough, the Freeze Delay Mode can be * selected and a new conversion can start only if all the previous data * of the same group have been treated: * - for a regular conversion: once the ADC conversion data register has * been read (using ADC_GetConversionValue() function) or if the EOC * Flag has been cleared (using ADC_ClearFlag() function). * - for an injected conversion: when the JEOC bit has been cleared * (using ADC_ClearFlag() function). * @param ADCx: where x can be 1 to select the ADC1 peripheral. * @param ADC_DelayLength: The length of delay which is applied after a * conversion or a sequence of conversion. * This parameter can be one of the following values: * @arg ADC_DelayLength_None: No delay. * @arg ADC_DelayLength_Freeze: Delay until the converted data has been read. * @arg ADC_DelayLength_7Cycles: Delay length equal to 7 APB clock cycles. * @arg ADC_DelayLength_15Cycles: Delay length equal to 15 APB clock cycles * @arg ADC_DelayLength_31Cycles: Delay length equal to 31 APB clock cycles * @arg ADC_DelayLength_63Cycles: Delay length equal to 63 APB clock cycles * @arg ADC_DelayLength_127Cycles: Delay length equal to 127 APB clock cycles * @arg ADC_DelayLength_255Cycles: Delay length equal to 255 APB clock cycles * @retval None */ void ADC_DelaySelectionConfig(ADC_TypeDef* ADCx, uint8_t ADC_DelayLength) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_DELAY_LENGTH(ADC_DelayLength)); /* Get the old register value */ tmpreg = ADCx->CR2; /* Clear the old delay length */ tmpreg &= CR2_DELS_RESET; /* Set the delay length */ tmpreg |= ADC_DelayLength; /* Store the new register value */ ADCx->CR2 = tmpreg; } /** * @} */ /** @defgroup ADC_Group3 Analog Watchdog configuration functions * @brief Analog Watchdog configuration functions. * @verbatim =============================================================================== ##### Analog Watchdog configuration functions ##### =============================================================================== [..] This section provides functions allowing to configure the Analog Watchdog (AWD) feature in the ADC. [..] A typical configuration Analog Watchdog is done following these steps : (#) the ADC guarded channel(s) is (are) selected using the ADC_AnalogWatchdogSingleChannelConfig() function. (#) The Analog watchdog lower and higher threshold are configured using the ADC_AnalogWatchdogThresholdsConfig() function. (#) The Analog watchdog is enabled and configured to enable the check, on one or more channels, using the ADC_AnalogWatchdogCmd() function. @endverbatim * @{ */ /** * @brief Enables or disables the analog watchdog on single/all regular * or injected channels. * @param ADCx: where x can be 1 to select the ADC1 peripheral. * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration. * This parameter can be one of the following values: * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single * regular channel. * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single * injected channel. * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a * single regular or injected channel. * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular * channel. * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected * channel. * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all * regular and injected channels. * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog. * @retval None */ void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); /* Get the old register value */ tmpreg = ADCx->CR1; /* Clear AWDEN, JAWDEN and AWDSGL bits */ tmpreg &= CR1_AWDMODE_RESET; /* Set the analog watchdog enable mode */ tmpreg |= ADC_AnalogWatchdog; /* Store the new register value */ ADCx->CR1 = tmpreg; } /** * @brief Configures the high and low thresholds of the analog watchdog. * @param ADCx: where x can be 1 to select the ADC1 peripheral. * @param HighThreshold: the ADC analog watchdog High threshold value. * This parameter must be a 12bit value. * @param LowThreshold: the ADC analog watchdog Low threshold value. * This parameter must be a 12bit value. * @retval None */ void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_THRESHOLD(HighThreshold)); assert_param(IS_ADC_THRESHOLD(LowThreshold)); /* Set the ADCx high threshold */ ADCx->HTR = HighThreshold; /* Set the ADCx low threshold */ ADCx->LTR = LowThreshold; } /** * @brief Configures the analog watchdog guarded single channel. * @param ADCx: where x can be 1 to select the ADC1 peripheral. * @param ADC_Channel: the ADC channel to configure for the analog watchdog. * This parameter can be one of the following values: * @arg ADC_Channel_0: ADC Channel0 selected * @arg ADC_Channel_1: ADC Channel1 selected * @arg ADC_Channel_2: ADC Channel2 selected * @arg ADC_Channel_3: ADC Channel3 selected * @arg ADC_Channel_4: ADC Channel4 selected * @arg ADC_Channel_5: ADC Channel5 selected * @arg ADC_Channel_6: ADC Channel6 selected * @arg ADC_Channel_7: ADC Channel7 selected * @arg ADC_Channel_8: ADC Channel8 selected * @arg ADC_Channel_9: ADC Channel9 selected * @arg ADC_Channel_10: ADC Channel10 selected * @arg ADC_Channel_11: ADC Channel11 selected * @arg ADC_Channel_12: ADC Channel12 selected * @arg ADC_Channel_13: ADC Channel13 selected * @arg ADC_Channel_14: ADC Channel14 selected * @arg ADC_Channel_15: ADC Channel15 selected * @arg ADC_Channel_16: ADC Channel16 selected * @arg ADC_Channel_17: ADC Channel17 selected * @arg ADC_Channel_18: ADC Channel18 selected * @arg ADC_Channel_19: ADC Channel19 selected * @arg ADC_Channel_20: ADC Channel20 selected * @arg ADC_Channel_21: ADC Channel21 selected * @arg ADC_Channel_22: ADC Channel22 selected * @arg ADC_Channel_23: ADC Channel23 selected * @arg ADC_Channel_24: ADC Channel24 selected * @arg ADC_Channel_25: ADC Channel25 selected * @arg ADC_Channel_27: ADC Channel27 selected * @arg ADC_Channel_28: ADC Channel28 selected * @arg ADC_Channel_29: ADC Channel29 selected * @arg ADC_Channel_30: ADC Channel30 selected * @arg ADC_Channel_31: ADC Channel31 selected * @arg ADC_Channel_0b: ADC Channel0b selected * @arg ADC_Channel_1b: ADC Channel1b selected * @arg ADC_Channel_2b: ADC Channel2b selected * @arg ADC_Channel_3b: ADC Channel3b selected * @arg ADC_Channel_6b: ADC Channel6b selected * @arg ADC_Channel_7b: ADC Channel7b selected * @arg ADC_Channel_8b: ADC Channel8b selected * @arg ADC_Channel_9b: ADC Channel9b selected * @arg ADC_Channel_10b: ADC Channel10b selected * @arg ADC_Channel_11b: ADC Channel11b selected * @arg ADC_Channel_12b: ADC Channel12b selected * @retval None */ void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_CHANNEL(ADC_Channel)); /* Get the old register value */ tmpreg = ADCx->CR1; /* Clear the Analog watchdog channel select bits */ tmpreg &= CR1_AWDCH_RESET; /* Set the Analog watchdog channel */ tmpreg |= ADC_Channel; /* Store the new register value */ ADCx->CR1 = tmpreg; } /** * @} */ /** @defgroup ADC_Group4 Temperature Sensor & Vrefint (Voltage Reference internal) management function * @brief Temperature Sensor & Vrefint (Voltage Reference internal) management function. * @verbatim ========================================================================================= ##### Temperature Sensor and Vrefint (Voltage Reference internal) management function ##### ========================================================================================= [..] This section provides a function allowing to enable/ disable the internal connections between the ADC and the Temperature Sensor and the Vrefint source. [..] A typical configuration to get the Temperature sensor and Vrefint channels voltages is done following these steps : (#) Enable the internal connection of Temperature sensor and Vrefint sources with the ADC channels using ADC_TempSensorVrefintCmd() function. (#) select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions. (#) Get the voltage values, using ADC_GetConversionValue() or ADC_GetInjectedConversionValue(). @endverbatim * @{ */ /** * @brief Enables or disables the temperature sensor and Vrefint channel. * @param NewState: new state of the temperature sensor and Vref int channels. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_TempSensorVrefintCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the temperature sensor and Vrefint channel*/ ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE; } else { /* Disable the temperature sensor and Vrefint channel*/ ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE); } } /** * @} */ /** @defgroup ADC_Group5 Regular Channels Configuration functions * @brief Regular Channels Configuration functions. * @verbatim =============================================================================== ##### Regular Channels Configuration functions ##### =============================================================================== [..] This section provides functions allowing to manage the ADC regular channels, it is composed of 2 sub sections : (#) Configuration and management functions for regular channels: This subsection provides functions allowing to configure the ADC regular channels : (++) Configure the rank in the regular group sequencer for each channel. (++) Configure the sampling time for each channel. (++) select the conversion Trigger for regular channels. (++) select the desired EOC event behavior configuration. (++) Activate the continuous Mode (*). (++) Activate the Discontinuous Mode. -@@- Please Note that the following features for regular channels are configurated using the ADC_Init() function : (+@@) scan mode activation. (+@@) continuous mode activation (**). (+@@) External trigger source. (+@@) External trigger edge. (+@@) number of conversion in the regular channels group sequencer. -@@- (*) and (**) are performing the same configuration. (#) Get the conversion data: This subsection provides an important function in the ADC peripheral since it returns the converted data of the current regular channel. When the Conversion value is read, the EOC Flag is automatically cleared. @endverbatim * @{ */ /** * @brief Configures for the selected ADC regular channel its corresponding * rank in the sequencer and its sampling time. * @param ADCx: where x can be 1 to select the ADC peripheral. * @param ADC_Channel: the ADC channel to configure. * This parameter can be one of the following values: * @arg ADC_Channel_0: ADC Channel0 selected * @arg ADC_Channel_1: ADC Channel1 selected * @arg ADC_Channel_2: ADC Channel2 selected * @arg ADC_Channel_3: ADC Channel3 selected * @arg ADC_Channel_4: ADC Channel4 selected * @arg ADC_Channel_5: ADC Channel5 selected * @arg ADC_Channel_6: ADC Channel6 selected * @arg ADC_Channel_7: ADC Channel7 selected * @arg ADC_Channel_8: ADC Channel8 selected * @arg ADC_Channel_9: ADC Channel9 selected * @arg ADC_Channel_10: ADC Channel10 selected * @arg ADC_Channel_11: ADC Channel11 selected * @arg ADC_Channel_12: ADC Channel12 selected * @arg ADC_Channel_13: ADC Channel13 selected * @arg ADC_Channel_14: ADC Channel14 selected * @arg ADC_Channel_15: ADC Channel15 selected * @arg ADC_Channel_16: ADC Channel16 selected * @arg ADC_Channel_17: ADC Channel17 selected * @arg ADC_Channel_18: ADC Channel18 selected * @arg ADC_Channel_19: ADC Channel19 selected * @arg ADC_Channel_20: ADC Channel20 selected * @arg ADC_Channel_21: ADC Channel21 selected * @arg ADC_Channel_22: ADC Channel22 selected * @arg ADC_Channel_23: ADC Channel23 selected * @arg ADC_Channel_24: ADC Channel24 selected * @arg ADC_Channel_25: ADC Channel25 selected * @arg ADC_Channel_27: ADC Channel27 selected * @arg ADC_Channel_28: ADC Channel28 selected * @arg ADC_Channel_29: ADC Channel29 selected * @arg ADC_Channel_30: ADC Channel30 selected * @arg ADC_Channel_31: ADC Channel31 selected * @arg ADC_Channel_0b: ADC Channel0b selected * @arg ADC_Channel_1b: ADC Channel1b selected * @arg ADC_Channel_2b: ADC Channel2b selected * @arg ADC_Channel_3b: ADC Channel3b selected * @arg ADC_Channel_6b: ADC Channel6b selected * @arg ADC_Channel_7b: ADC Channel7b selected * @arg ADC_Channel_8b: ADC Channel8b selected * @arg ADC_Channel_9b: ADC Channel9b selected * @arg ADC_Channel_10b: ADC Channel10b selected * @arg ADC_Channel_11b: ADC Channel11b selected * @arg ADC_Channel_12b: ADC Channel12b selected * @param Rank: The rank in the regular group sequencer. This parameter * must be between 1 to 28. * @param ADC_SampleTime: The sample time value to be set for the selected * channel. * This parameter can be one of the following values: * @arg ADC_SampleTime_4Cycles: Sample time equal to 4 cycles * @arg ADC_SampleTime_9Cycles: Sample time equal to 9 cycles * @arg ADC_SampleTime_16Cycles: Sample time equal to 16 cycles * @arg ADC_SampleTime_24Cycles: Sample time equal to 24 cycles * @arg ADC_SampleTime_48Cycles: Sample time equal to 48 cycles * @arg ADC_SampleTime_96Cycles: Sample time equal to 96 cycles * @arg ADC_SampleTime_192Cycles: Sample time equal to 192 cycles * @arg ADC_SampleTime_384Cycles: Sample time equal to 384 cycles * @retval None */ void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) { uint32_t tmpreg1 = 0, tmpreg2 = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_CHANNEL(ADC_Channel)); assert_param(IS_ADC_REGULAR_RANK(Rank)); assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); /* If ADC_Channel_30 or ADC_Channel_31 is selected */ if (ADC_Channel > ADC_Channel_29) { /* Get the old register value */ tmpreg1 = ADCx->SMPR0; /* Calculate the mask to clear */ tmpreg2 = SMPR0_SMP_SET << (3 * (ADC_Channel - 30)); /* Clear the old sample time */ tmpreg1 &= ~tmpreg2; /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 30)); /* Set the new sample time */ tmpreg1 |= tmpreg2; /* Store the new register value */ ADCx->SMPR0 = tmpreg1; } /* If ADC_Channel_20 ... ADC_Channel_29 is selected */ else if (ADC_Channel > ADC_Channel_19) { /* Get the old register value */ tmpreg1 = ADCx->SMPR1; /* Calculate the mask to clear */ tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 20)); /* Clear the old sample time */ tmpreg1 &= ~tmpreg2; /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 20)); /* Set the new sample time */ tmpreg1 |= tmpreg2; /* Store the new register value */ ADCx->SMPR1 = tmpreg1; } /* If ADC_Channel_10 ... ADC_Channel_19 is selected */ else if (ADC_Channel > ADC_Channel_9) { /* Get the old register value */ tmpreg1 = ADCx->SMPR2; /* Calculate the mask to clear */ tmpreg2 = SMPR2_SMP_SET << (3 * (ADC_Channel - 10)); /* Clear the old sample time */ tmpreg1 &= ~tmpreg2; /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); /* Set the new sample time */ tmpreg1 |= tmpreg2; /* Store the new register value */ ADCx->SMPR2 = tmpreg1; } else /* ADC_Channel include in ADC_Channel_[0..9] */ { /* Get the old register value */ tmpreg1 = ADCx->SMPR3; /* Calculate the mask to clear */ tmpreg2 = SMPR3_SMP_SET << (3 * ADC_Channel); /* Clear the old sample time */ tmpreg1 &= ~tmpreg2; /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); /* Set the new sample time */ tmpreg1 |= tmpreg2; /* Store the new register value */ ADCx->SMPR3 = tmpreg1; } /* For Rank 1 to 6 */ if (Rank < 7) { /* Get the old register value */ tmpreg1 = ADCx->SQR5; /* Calculate the mask to clear */ tmpreg2 = SQR5_SQ_SET << (5 * (Rank - 1)); /* Clear the old SQx bits for the selected rank */ tmpreg1 &= ~tmpreg2; /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); /* Set the SQx bits for the selected rank */ tmpreg1 |= tmpreg2; /* Store the new register value */ ADCx->SQR5 = tmpreg1; } /* For Rank 7 to 12 */ else if (Rank < 13) { /* Get the old register value */ tmpreg1 = ADCx->SQR4; /* Calculate the mask to clear */ tmpreg2 = SQR4_SQ_SET << (5 * (Rank - 7)); /* Clear the old SQx bits for the selected rank */ tmpreg1 &= ~tmpreg2; /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); /* Set the SQx bits for the selected rank */ tmpreg1 |= tmpreg2; /* Store the new register value */ ADCx->SQR4 = tmpreg1; } /* For Rank 13 to 18 */ else if (Rank < 19) { /* Get the old register value */ tmpreg1 = ADCx->SQR3; /* Calculate the mask to clear */ tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 13)); /* Clear the old SQx bits for the selected rank */ tmpreg1 &= ~tmpreg2; /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); /* Set the SQx bits for the selected rank */ tmpreg1 |= tmpreg2; /* Store the new register value */ ADCx->SQR3 = tmpreg1; } /* For Rank 19 to 24 */ else if (Rank < 25) { /* Get the old register value */ tmpreg1 = ADCx->SQR2; /* Calculate the mask to clear */ tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 19)); /* Clear the old SQx bits for the selected rank */ tmpreg1 &= ~tmpreg2; /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 19)); /* Set the SQx bits for the selected rank */ tmpreg1 |= tmpreg2; /* Store the new register value */ ADCx->SQR2 = tmpreg1; } /* For Rank 25 to 28 */ else { /* Get the old register value */ tmpreg1 = ADCx->SQR1; /* Calculate the mask to clear */ tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 25)); /* Clear the old SQx bits for the selected rank */ tmpreg1 &= ~tmpreg2; /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 25)); /* Set the SQx bits for the selected rank */ tmpreg1 |= tmpreg2; /* Store the new register value */ ADCx->SQR1 = tmpreg1; } } /** * @brief Enables the selected ADC software start conversion of the regular channels. * @param ADCx: where x can be 1 to select the ADC1 peripheral. * @retval None */ void ADC_SoftwareStartConv(ADC_TypeDef* ADCx) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Enable the selected ADC conversion for regular group */ ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART; } /** * @brief Gets the selected ADC Software start regular conversion Status. * @param ADCx: where x can be 1 to select the ADC1 peripheral. * @retval The new state of ADC software start conversion (SET or RESET). */ FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Check the status of SWSTART bit */ if ((ADCx->CR2 & ADC_CR2_SWSTART) != (uint32_t)RESET) { /* SWSTART bit is set */ bitstatus = SET; } else { /* SWSTART bit is reset */ bitstatus = RESET; } /* Return the SWSTART bit status */ return bitstatus; } /** * @brief Enables or disables the EOC on each regular channel conversion. * @param ADCx: where x can be 1 to select the ADC1 peripheral. * @param NewState: new state of the selected ADC EOC flag rising * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected ADC EOC rising on each regular channel conversion */ ADCx->CR2 |= ADC_CR2_EOCS; } else { /* Disable the selected ADC EOC rising on each regular channel conversion */ ADCx->CR2 &= (uint32_t)~ADC_CR2_EOCS; } } /** * @brief Enables or disables the ADC continuous conversion mode. * @param ADCx: where x can be 1 to select the ADC1 peripheral. * @param NewState: new state of the selected ADC continuous conversion mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected ADC continuous conversion mode */ ADCx->CR2 |= (uint32_t)ADC_CR2_CONT; } else { /* Disable the selected ADC continuous conversion mode */ ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT); } } /** * @brief Configures the discontinuous mode for the selected ADC regular * group channel. * @param ADCx: where x can be 1 to select the ADC1 peripheral. * @param Number: specifies the discontinuous mode regular channel count value. * This number must be between 1 and 8. * @retval None */ void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number) { uint32_t tmpreg1 = 0; uint32_t tmpreg2 = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number)); /* Get the old register value */ tmpreg1 = ADCx->CR1; /* Clear the old discontinuous mode channel count */ tmpreg1 &= CR1_DISCNUM_RESET; /* Set the discontinuous mode channel count */ tmpreg2 = Number - 1; tmpreg1 |= tmpreg2 << 13; /* Store the new register value */ ADCx->CR1 = tmpreg1; } /** * @brief Enables or disables the discontinuous mode on regular group * channel for the specified ADC. * @param ADCx: where x can be 1 to select the ADC1 peripheral. * @param NewState: new state of the selected ADC discontinuous mode on regular * group channel. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected ADC regular discontinuous mode */ ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN; } else { /* Disable the selected ADC regular discontinuous mode */ ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN); } } /** * @brief Returns the last ADCx conversion result data for regular channel. * @param ADCx: where x can be 1 to select the ADC1 peripheral. * @retval The Data conversion value. */ uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Return the selected ADC conversion value */ return (uint16_t) ADCx->DR; } /** * @} */ /** @defgroup ADC_Group6 Regular Channels DMA Configuration functions * @brief Regular Channels DMA Configuration functions. * @verbatim =============================================================================== ##### Regular Channels DMA Configuration functions ##### =============================================================================== [..] This section provides functions allowing to configure the DMA for ADC regular channels.Since converted regular channel values are stored into a unique data register, it is useful to use DMA for conversion of more than one regular channel. This avoids the loss of the data already stored in the ADC Data register. When the DMA mode is enabled (using the ADC_DMACmd() function), after each conversion of a regular channel, a DMA request is generated. [..] Depending on the "DMA disable selection" configuration (using the ADC_DMARequestAfterLastTransferCmd() function), at the end of the last DMA transfer, two possibilities are allowed: (+) No new DMA request is issued to the DMA controller (feature DISABLED). (+) Requests can continue to be generated (feature ENABLED). @endverbatim * @{ */ /** * @brief Enables or disables the specified ADC DMA request. * @param ADCx: where x can be 1 to select the ADC1 peripheral. * @param NewState: new state of the selected ADC DMA transfer. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_ADC_DMA_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected ADC DMA request */ ADCx->CR2 |= (uint32_t)ADC_CR2_DMA; } else { /* Disable the selected ADC DMA request */ ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA); } } /** * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode). * @param ADCx: where x can be 1 to select the ADC1 peripheral. * @param NewState: new state of the selected ADC EOC flag rising * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected ADC DMA request after last transfer */ ADCx->CR2 |= ADC_CR2_DDS; } else { /* Disable the selected ADC DMA request after last transfer */ ADCx->CR2 &= (uint32_t)~ADC_CR2_DDS; } } /** * @} */ /** @defgroup ADC_Group7 Injected channels Configuration functions * @brief Injected channels Configuration functions. * @verbatim =============================================================================== ##### Injected channels Configuration functions ##### =============================================================================== [..] This section provide functions allowing to configure the ADC Injected channels, it is composed of 2 sub sections : (#) Configuration functions for Injected channels: This subsection provides functions allowing to configure the ADC injected channels : (++) Configure the rank in the injected group sequencer for each channel. (++) Configure the sampling time for each channel. (++) Activate the Auto injected Mode. (++) Activate the Discontinuous Mode. (++) scan mode activation. (++) External/software trigger source. (++) External trigger edge. (++) injected channels sequencer. (#) Get the Specified Injected channel conversion data: This subsection provides an important function in the ADC peripheral since it returns the converted data of the specific injected channel. @endverbatim * @{ */ /** * @brief Configures for the selected ADC injected channel its corresponding * rank in the sequencer and its sample time. * @param ADCx: where x can be 1 to select the ADC1 peripheral. * @param ADC_Channel: the ADC channel to configure. * This parameter can be one of the following values: * @arg ADC_Channel_0: ADC Channel0 selected * @arg ADC_Channel_1: ADC Channel1 selected * @arg ADC_Channel_2: ADC Channel2 selected * @arg ADC_Channel_3: ADC Channel3 selected * @arg ADC_Channel_4: ADC Channel4 selected * @arg ADC_Channel_5: ADC Channel5 selected * @arg ADC_Channel_6: ADC Channel6 selected * @arg ADC_Channel_7: ADC Channel7 selected * @arg ADC_Channel_8: ADC Channel8 selected * @arg ADC_Channel_9: ADC Channel9 selected * @arg ADC_Channel_10: ADC Channel10 selected * @arg ADC_Channel_11: ADC Channel11 selected * @arg ADC_Channel_12: ADC Channel12 selected * @arg ADC_Channel_13: ADC Channel13 selected * @arg ADC_Channel_14: ADC Channel14 selected * @arg ADC_Channel_15: ADC Channel15 selected * @arg ADC_Channel_16: ADC Channel16 selected * @arg ADC_Channel_17: ADC Channel17 selected * @arg ADC_Channel_18: ADC Channel18 selected * @arg ADC_Channel_19: ADC Channel19 selected * @arg ADC_Channel_20: ADC Channel20 selected * @arg ADC_Channel_21: ADC Channel21 selected * @arg ADC_Channel_22: ADC Channel22 selected * @arg ADC_Channel_23: ADC Channel23 selected * @arg ADC_Channel_24: ADC Channel24 selected * @arg ADC_Channel_25: ADC Channel25 selected * @arg ADC_Channel_27: ADC Channel27 selected * @arg ADC_Channel_28: ADC Channel28 selected * @arg ADC_Channel_29: ADC Channel29 selected * @arg ADC_Channel_30: ADC Channel30 selected * @arg ADC_Channel_31: ADC Channel31 selected * @arg ADC_Channel_0b: ADC Channel0b selected * @arg ADC_Channel_1b: ADC Channel1b selected * @arg ADC_Channel_2b: ADC Channel2b selected * @arg ADC_Channel_3b: ADC Channel3b selected * @arg ADC_Channel_6b: ADC Channel6b selected * @arg ADC_Channel_7b: ADC Channel7b selected * @arg ADC_Channel_8b: ADC Channel8b selected * @arg ADC_Channel_9b: ADC Channel9b selected * @arg ADC_Channel_10b: ADC Channel10b selected * @arg ADC_Channel_11b: ADC Channel11b selected * @arg ADC_Channel_12b: ADC Channel12b selected * @param Rank: The rank in the injected group sequencer. This parameter * must be between 1 to 4. * @param ADC_SampleTime: The sample time value to be set for the selected * channel. This parameter can be one of the following values: * @arg ADC_SampleTime_4Cycles: Sample time equal to 4 cycles * @arg ADC_SampleTime_9Cycles: Sample time equal to 9 cycles * @arg ADC_SampleTime_16Cycles: Sample time equal to 16 cycles * @arg ADC_SampleTime_24Cycles: Sample time equal to 24 cycles * @arg ADC_SampleTime_48Cycles: Sample time equal to 48 cycles * @arg ADC_SampleTime_96Cycles: Sample time equal to 96 cycles * @arg ADC_SampleTime_192Cycles: Sample time equal to 192 cycles * @arg ADC_SampleTime_384Cycles: Sample time equal to 384 cycles * @retval None */ void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) { uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_CHANNEL(ADC_Channel)); assert_param(IS_ADC_INJECTED_RANK(Rank)); assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); /* If ADC_Channel_30 or ADC_Channel_31 is selected */ if (ADC_Channel > ADC_Channel_29) { /* Get the old register value */ tmpreg1 = ADCx->SMPR0; /* Calculate the mask to clear */ tmpreg2 = SMPR0_SMP_SET << (3 * (ADC_Channel - 30)); /* Clear the old sample time */ tmpreg1 &= ~tmpreg2; /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 30)); /* Set the new sample time */ tmpreg1 |= tmpreg2; /* Store the new register value */ ADCx->SMPR0 = tmpreg1; } /* If ADC_Channel_20 ... ADC_Channel_29 is selected */ else if (ADC_Channel > ADC_Channel_19) { /* Get the old register value */ tmpreg1 = ADCx->SMPR1; /* Calculate the mask to clear */ tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 20)); /* Clear the old sample time */ tmpreg1 &= ~tmpreg2; /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 20)); /* Set the new sample time */ tmpreg1 |= tmpreg2; /* Store the new register value */ ADCx->SMPR1 = tmpreg1; } /* If ADC_Channel_10 ... ADC_Channel_19 is selected */ else if (ADC_Channel > ADC_Channel_9) { /* Get the old register value */ tmpreg1 = ADCx->SMPR2; /* Calculate the mask to clear */ tmpreg2 = SMPR2_SMP_SET << (3 * (ADC_Channel - 10)); /* Clear the old sample time */ tmpreg1 &= ~tmpreg2; /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); /* Set the new sample time */ tmpreg1 |= tmpreg2; /* Store the new register value */ ADCx->SMPR2 = tmpreg1; } else /* ADC_Channel include in ADC_Channel_[0..9] */ { /* Get the old register value */ tmpreg1 = ADCx->SMPR3; /* Calculate the mask to clear */ tmpreg2 = SMPR3_SMP_SET << (3 * ADC_Channel); /* Clear the old sample time */ tmpreg1 &= ~tmpreg2; /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); /* Set the new sample time */ tmpreg1 |= tmpreg2; /* Store the new register value */ ADCx->SMPR3 = tmpreg1; } /* Rank configuration */ /* Get the old register value */ tmpreg1 = ADCx->JSQR; /* Get JL value: Number = JL+1 */ tmpreg3 = (tmpreg1 & JSQR_JL_SET)>> 20; /* Calculate the mask to clear: ((Rank-1)+(4- (JL+1))) */ tmpreg2 = (uint32_t)(JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)))); /* Clear the old JSQx bits for the selected rank */ tmpreg1 &= ~tmpreg2; /* Calculate the mask to set: ((Rank-1)+(4- (JL+1))) */ tmpreg2 = (uint32_t)(((uint32_t)(ADC_Channel)) << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)))); /* Set the JSQx bits for the selected rank */ tmpreg1 |= tmpreg2; /* Store the new register value */ ADCx->JSQR = tmpreg1; } /** * @brief Configures the sequencer length for injected channels. * @param ADCx: where x can be 1 to select the ADC1 peripheral. * @param Length: The sequencer length. * This parameter must be a number between 1 to 4. * @retval None */ void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length) { uint32_t tmpreg1 = 0; uint32_t tmpreg2 = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_INJECTED_LENGTH(Length)); /* Get the old register value */ tmpreg1 = ADCx->JSQR; /* Clear the old injected sequence length JL bits */ tmpreg1 &= JSQR_JL_RESET; /* Set the injected sequence length JL bits */ tmpreg2 = Length - 1; tmpreg1 |= tmpreg2 << 20; /* Store the new register value */ ADCx->JSQR = tmpreg1; } /** * @brief Set the injected channels conversion value offset. * @param ADCx: where x can be 1 to select the ADC1 peripheral. * @param ADC_InjectedChannel: the ADC injected channel to set its offset. * This parameter can be one of the following values: * @arg ADC_InjectedChannel_1: Injected Channel1 selected. * @arg ADC_InjectedChannel_2: Injected Channel2 selected. * @arg ADC_InjectedChannel_3: Injected Channel3 selected. * @arg ADC_InjectedChannel_4: Injected Channel4 selected. * @param Offset: the offset value for the selected ADC injected channel * This parameter must be a 12bit value. * @retval None */ void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) { __IO uint32_t tmp = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); assert_param(IS_ADC_OFFSET(Offset)); tmp = (uint32_t)ADCx; tmp += ADC_InjectedChannel; /* Set the selected injected channel data offset */ *(__IO uint32_t *) tmp = (uint32_t)Offset; } /** * @brief Configures the ADCx external trigger for injected channels conversion. * @param ADCx: where x can be 1 to select the ADC1 peripheral. * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected * conversion. This parameter can be one of the following values: * @arg ADC_ExternalTrigInjecConv_T9_CC1: Timer9 capture compare1 selected * @arg ADC_ExternalTrigInjecConv_T9_TRGO: Timer9 TRGO event selected * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected * @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected * @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected * @arg ADC_ExternalTrigInjecConv_T10_CC1: Timer10 capture compare1 selected * @arg ADC_ExternalTrigInjecConv_T7_TRGO: Timer7 TRGO event selected * @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected * @retval None */ void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv)); /* Get the old register value */ tmpreg = ADCx->CR2; /* Clear the old external event selection for injected group */ tmpreg &= CR2_JEXTSEL_RESET; /* Set the external event selection for injected group */ tmpreg |= ADC_ExternalTrigInjecConv; /* Store the new register value */ ADCx->CR2 = tmpreg; } /** * @brief Configures the ADCx external trigger edge for injected channels conversion. * @param ADCx: where x can be 1 to select the ADC1 peripheral. * @param ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger * edge to start injected conversion. * This parameter can be one of the following values: * @arg ADC_ExternalTrigConvEdge_None: external trigger disabled for * injected conversion. * @arg ADC_ExternalTrigConvEdge_Rising: detection on rising edge * @arg ADC_ExternalTrigConvEdge_Falling: detection on falling edge * @arg ADC_ExternalTrigConvEdge_RisingFalling: detection on * both rising and falling edge * @retval None */ void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(ADC_ExternalTrigInjecConvEdge)); /* Get the old register value */ tmpreg = ADCx->CR2; /* Clear the old external trigger edge for injected group */ tmpreg &= CR2_JEXTEN_RESET; /* Set the new external trigger edge for injected group */ tmpreg |= ADC_ExternalTrigInjecConvEdge; /* Store the new register value */ ADCx->CR2 = tmpreg; } /** * @brief Enables the selected ADC software start conversion of the injected * channels. * @param ADCx: where x can be 1 to select the ADC1 peripheral. * @retval None */ void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Enable the selected ADC conversion for injected group */ ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART; } /** * @brief Gets the selected ADC Software start injected conversion Status. * @param ADCx: where x can be 1 to select the ADC1 peripheral. * @retval The new state of ADC software start injected conversion (SET or RESET). */ FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Check the status of JSWSTART bit */ if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET) { /* JSWSTART bit is set */ bitstatus = SET; } else { /* JSWSTART bit is reset */ bitstatus = RESET; } /* Return the JSWSTART bit status */ return bitstatus; } /** * @brief Enables or disables the selected ADC automatic injected group * conversion after regular one. * @param ADCx: where x can be 1 to select the ADC1 peripheral. * @param NewState: new state of the selected ADC auto injected * conversion. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected ADC automatic injected group conversion */ ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO; } else { /* Disable the selected ADC automatic injected group conversion */ ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO); } } /** * @brief Enables or disables the discontinuous mode for injected group * channel for the specified ADC. * @param ADCx: where x can be 1 to select the ADC1 peripheral. * @param NewState: new state of the selected ADC discontinuous mode * on injected group channel. This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected ADC injected discontinuous mode */ ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN; } else { /* Disable the selected ADC injected discontinuous mode */ ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN); } } /** * @brief Returns the ADC injected channel conversion result. * @param ADCx: where x can be 1 to select the ADC1 peripheral. * @param ADC_InjectedChannel: the converted ADC injected channel. * This parameter can be one of the following values: * @arg ADC_InjectedChannel_1: Injected Channel1 selected * @arg ADC_InjectedChannel_2: Injected Channel2 selected * @arg ADC_InjectedChannel_3: Injected Channel3 selected * @arg ADC_InjectedChannel_4: Injected Channel4 selected * @retval The Data conversion value. */ uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel) { __IO uint32_t tmp = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); tmp = (uint32_t)ADCx; tmp += ADC_InjectedChannel + JDR_OFFSET; /* Returns the selected injected channel conversion data value */ return (uint16_t) (*(__IO uint32_t*) tmp); } /** * @} */ /** @defgroup ADC_Group8 Interrupts and flags management functions * @brief Interrupts and flags management functions. * @verbatim =============================================================================== ##### Interrupts and flags management functions ##### =============================================================================== [..] This section provides functions allowing to configure the ADC Interrupts and get the status and clear flags and Interrupts pending bits. [..] The ADC provide 4 Interrupts sources and 9 Flags which can be divided into 3 groups: *** Flags and Interrupts for ADC regular channels *** ===================================================== [..] (+)Flags : (##) ADC_FLAG_OVR : Overrun detection when regular converted data are lost. (##) ADC_FLAG_EOC : Regular channel end of conversion + to indicate (depending on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() ) the end of : (+++) a regular CHANNEL conversion. (+++) sequence of regular GROUP conversions. (##) ADC_FLAG_STRT: Regular channel start + to indicate when regular CHANNEL conversion starts. (##) ADC_FLAG_RCNR: Regular channel not ready + to indicate if a new regular conversion can be launched. (+)Interrupts : (##) ADC_IT_OVR : specifies the interrupt source for Overrun detection event. (##) ADC_IT_EOC : specifies the interrupt source for Regular channel end of conversion event. *** Flags and Interrupts for ADC Injected channels *** ====================================================== (+)Flags : (##) ADC_FLAG_JEOC : Injected channel end of conversion+ to indicate at the end of injected GROUP conversion. (##) ADC_FLAG_JSTRT: Injected channel start + to indicate hardware when injected GROUP conversion starts. (##) ADC_FLAG_JCNR: Injected channel not ready + to indicate if a new injected conversion can be launched. (+)Interrupts (##) ADC_IT_JEOC : specifies the interrupt source for Injected channel end of conversion event. *** General Flags and Interrupts for the ADC *** ================================================ (+)Flags : (##) ADC_FLAG_AWD: Analog watchdog + to indicate if the converted voltage crosses the programmed thresholds values. (##) ADC_FLAG_ADONS: ADC ON status + to indicate if the ADC is ready to convert. (+)Interrupts : (##) ADC_IT_AWD : specifies the interrupt source for Analog watchdog event. [..] The user should identify which mode will be used in his application to manage the ADC controller events: Polling mode or Interrupt mode. [..] In the Polling Mode it is advised to use the following functions: (+) ADC_GetFlagStatus() : to check if flags events occur. (+) ADC_ClearFlag() : to clear the flags events. [..] In the Interrupt Mode it is advised to use the following functions: (+) ADC_ITConfig() : to enable or disable the interrupt source. (+) ADC_GetITStatus() : to check if Interrupt occurs. (+) ADC_ClearITPendingBit() : to clear the Interrupt pending Bit (corresponding Flag). @endverbatim * @{ */ /** * @brief Enables or disables the specified ADC interrupts. * @param ADCx: where x can be 1 to select the ADC peripheral. * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. * This parameter can be one of the following values: * @arg ADC_IT_EOC: End of conversion interrupt * @arg ADC_IT_AWD: Analog watchdog interrupt * @arg ADC_IT_JEOC: End of injected conversion interrupt * @arg ADC_IT_OVR: overrun interrupt * @param NewState: new state of the specified ADC interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) { uint32_t itmask = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); assert_param(IS_ADC_IT(ADC_IT)); /* Get the ADC IT index */ itmask = (uint8_t)ADC_IT; itmask = (uint32_t)0x01 << itmask; if (NewState != DISABLE) { /* Enable the selected ADC interrupts */ ADCx->CR1 |= itmask; } else { /* Disable the selected ADC interrupts */ ADCx->CR1 &= (~(uint32_t)itmask); } } /** * @brief Checks whether the specified ADC flag is set or not. * @param ADCx: where x can be 1 to select the ADC1 peripheral. * @param ADC_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg ADC_FLAG_AWD: Analog watchdog flag * @arg ADC_FLAG_EOC: End of conversion flag * @arg ADC_FLAG_JEOC: End of injected group conversion flag * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag * @arg ADC_FLAG_STRT: Start of regular group conversion flag * @arg ADC_FLAG_OVR: Overrun flag * @arg ADC_FLAG_ADONS: ADC ON status * @arg ADC_FLAG_RCNR: Regular channel not ready * @arg ADC_FLAG_JCNR: Injected channel not ready * @retval The new state of ADC_FLAG (SET or RESET). */ FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint16_t ADC_FLAG) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); /* Check the status of the specified ADC flag */ if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET) { /* ADC_FLAG is set */ bitstatus = SET; } else { /* ADC_FLAG is reset */ bitstatus = RESET; } /* Return the ADC_FLAG status */ return bitstatus; } /** * @brief Clears the ADCx's pending flags. * @param ADCx: where x can be 1 to select the ADC1 peripheral. * @param ADC_FLAG: specifies the flag to clear. * This parameter can be any combination of the following values: * @arg ADC_FLAG_AWD: Analog watchdog flag * @arg ADC_FLAG_EOC: End of conversion flag * @arg ADC_FLAG_JEOC: End of injected group conversion flag * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag * @arg ADC_FLAG_STRT: Start of regular group conversion flag * @arg ADC_FLAG_OVR: overrun flag * @retval None */ void ADC_ClearFlag(ADC_TypeDef* ADCx, uint16_t ADC_FLAG) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); /* Clear the selected ADC flags */ ADCx->SR = ~(uint32_t)ADC_FLAG; } /** * @brief Checks whether the specified ADC interrupt has occurred or not. * @param ADCx: where x can be 1 to select the ADC1 peripheral. * @param ADC_IT: specifies the ADC interrupt source to check. * This parameter can be one of the following values: * @arg ADC_IT_EOC: End of conversion interrupt * @arg ADC_IT_AWD: Analog watchdog interrupt * @arg ADC_IT_JEOC: End of injected conversion interrupt * @arg ADC_IT_OVR: Overrun interrupt * @retval The new state of ADC_IT (SET or RESET). */ ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT) { ITStatus bitstatus = RESET; uint32_t itmask = 0, enablestatus = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_IT(ADC_IT)); /* Get the ADC IT index */ itmask = (uint32_t)((uint32_t)ADC_IT >> 8); /* Get the ADC_IT enable bit status */ enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT)); /* Check the status of the specified ADC interrupt */ if (((uint32_t)(ADCx->SR & (uint32_t)itmask) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) { /* ADC_IT is set */ bitstatus = SET; } else { /* ADC_IT is reset */ bitstatus = RESET; } /* Return the ADC_IT status */ return bitstatus; } /** * @brief Clears the ADCx's interrupt pending bits. * @param ADCx: where x can be 1 to select the ADC1 peripheral. * @param ADC_IT: specifies the ADC interrupt pending bit to clear. * This parameter can be one of the following values: * @arg ADC_IT_EOC: End of conversion interrupt * @arg ADC_IT_AWD: Analog watchdog interrupt * @arg ADC_IT_JEOC: End of injected conversion interrupt * @arg ADC_IT_OVR: Overrun interrupt * @retval None */ void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) { uint8_t itmask = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_IT(ADC_IT)); /* Get the ADC IT index */ itmask = (uint8_t)(ADC_IT >> 8); /* Clear the selected ADC interrupt pending bits */ ADCx->SR = ~(uint32_t)itmask; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/src/stm32l1xx_aes.c
New file @@ -0,0 +1,599 @@ /** ****************************************************************************** * @file stm32l1xx_aes.c * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file provides firmware functions to manage the following * functionalities of the AES peripheral: * + Configuration * + Read/Write operations * + DMA transfers management * + Interrupts and flags management * * @verbatim =============================================================================== ##### AES Peripheral features ##### =============================================================================== ....[..] (#) The Advanced Encryption Standard hardware accelerator (AES) can be used to both encipher and decipher data using AES algorithm. (#) The AES supports 4 operation modes: (++) Encryption: It consumes 214 clock cycle when processing one 128-bit block (++) Decryption: It consumes 214 clock cycle when processing one 128-bit block (++) Key derivation for decryption: It consumes 80 clock cycle when processing one 128-bit block (++) Key Derivation and decryption: It consumes 288 clock cycle when processing one 128-bit blobk (#) Moreover 3 chaining modes are supported: (++) Electronic codebook (ECB): Each plain text is encrypted/decrypted separately (++) Cipher block chaining (CBC): Each block is XORed with the previous block (++) Counter mode (CTR): A 128-bit counter is encrypted and then XORed with the plain text to give the cipher text (#) The AES peripheral supports data swapping: 1-bit, 8-bit, 16-bit and 32-bit. (#) The AES peripheral supports write/read error handling with interrupt capability. (#) Automatic data flow control with support of direct memory access (DMA) using 2 channels, one for incoming data (DMA2 Channel5), and one for outcoming data (DMA2 Channel3). ##### How to use this driver ##### =============================================================================== [..] (#) AES AHB clock must be enabled to get write access to AES registers using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_AES, ENABLE). (#) Initialize the key using AES_KeyInit(). (#) Configure the AES operation mode using AES_Init(). (#) If required, enable interrupt source using AES_ITConfig() and enable the AES interrupt vector using NVIC_Init(). (#) If required, when using the DMA mode. (##) Configure the DMA using DMA_Init(). (##) Enable DMA requests using AES_DMAConfig(). (#) Enable the AES peripheral using AES_Cmd(). @endverbatim ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx_aes.h" #include "stm32l1xx_rcc.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @defgroup AES * @brief AES driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #define CR_CLEAR_MASK ((uint32_t)0xFFFFFF81) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup AES_Private_Functions * @{ */ /** @defgroup AES_Group1 Initialization and configuration * @brief Initialization and configuration. * @verbatim =============================================================================== ##### Initialization and configuration ##### =============================================================================== @endverbatim * @{ */ /** * @brief Deinitializes AES peripheral registers to their default reset values. * @param None * @retval None */ void AES_DeInit(void) { /* Enable AES reset state */ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_AES, ENABLE); /* Release AES from reset state */ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_AES, DISABLE); } /** * @brief Initializes the AES peripheral according to the specified parameters * in the AES_InitStruct: * - AES_Operation: specifies the operation mode (encryption, decryption...). * - AES_Chaining: specifies the chaining mode (ECB, CBC or CTR). * - AES_DataType: specifies the data swapping type: 32-bit, 16-bit, 8-bit or 1-bit. * @note If AES is already enabled, use AES_Cmd(DISABLE) before setting the new * configuration (When AES is enabled, setting configuration is forbidden). * @param AES_InitStruct: pointer to an AES_InitTypeDef structure that contains * the configuration information for AES peripheral. * @retval None */ void AES_Init(AES_InitTypeDef* AES_InitStruct) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_AES_MODE(AES_InitStruct->AES_Operation)); assert_param(IS_AES_CHAINING(AES_InitStruct->AES_Chaining)); assert_param(IS_AES_DATATYPE(AES_InitStruct->AES_DataType)); /* Get AES CR register value */ tmpreg = AES->CR; /* Clear DATATYPE[1:0], MODE[1:0] and CHMOD[1:0] bits */ tmpreg &= (uint32_t)CR_CLEAR_MASK; tmpreg |= (AES_InitStruct->AES_Operation | AES_InitStruct->AES_Chaining | AES_InitStruct->AES_DataType); AES->CR = (uint32_t) tmpreg; } /** * @brief Initializes the AES Keys according to the specified parameters in the AES_KeyInitStruct. * @param AES_KeyInitStruct: pointer to an AES_KeyInitTypeDef structure that * contains the configuration information for the specified AES Keys. * @note This function must be called while the AES is disabled. * @note In encryption, key derivation and key derivation + decryption modes, * AES_KeyInitStruct must contain the encryption key. * In decryption mode, AES_KeyInitStruct must contain the decryption key. * @retval None */ void AES_KeyInit(AES_KeyInitTypeDef* AES_KeyInitStruct) { AES->KEYR0 = AES_KeyInitStruct->AES_Key0; AES->KEYR1 = AES_KeyInitStruct->AES_Key1; AES->KEYR2 = AES_KeyInitStruct->AES_Key2; AES->KEYR3 = AES_KeyInitStruct->AES_Key3; } /** * @brief Initializes the AES Initialization Vector IV according to * the specified parameters in the AES_IVInitStruct. * @param AES_KeyInitStruct: pointer to an AES_IVInitTypeDef structure that * contains the configuration information for the specified AES IV. * @note When ECB chaining mode is selected, Initialization Vector IV has no * meaning. * When CTR chaining mode is selected, AES_IV0 contains the CTR value. * AES_IV1, AES_IV2 and AES_IV3 contains nonce value. * @retval None */ void AES_IVInit(AES_IVInitTypeDef* AES_IVInitStruct) { AES->IVR0 = AES_IVInitStruct->AES_IV0; AES->IVR1 = AES_IVInitStruct->AES_IV1; AES->IVR2 = AES_IVInitStruct->AES_IV2; AES->IVR3 = AES_IVInitStruct->AES_IV3; } /** * @brief Enable or disable the AES peripheral. * @param NewState: new state of the AES peripheral. * This parameter can be: ENABLE or DISABLE. * @note The key must be written while AES is disabled. * @retval None */ void AES_Cmd(FunctionalState NewState) { /* Check the parameter */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the AES peripheral */ AES->CR |= (uint32_t) AES_CR_EN; /**< AES Enable */ } else { /* Disable the AES peripheral */ AES->CR &= (uint32_t)(~AES_CR_EN); /**< AES Disable */ } } /** * @} */ /** @defgroup AES_Group2 Structures initialization functions * @brief Structures initialization. * @verbatim =============================================================================== ##### Structures initialization functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Fills each AES_InitStruct member with its default value. * @param AES_InitStruct: pointer to an AES_InitTypeDef structure which will * be initialized. * @retval None */ void AES_StructInit(AES_InitTypeDef* AES_InitStruct) { AES_InitStruct->AES_Operation = AES_Operation_Encryp; AES_InitStruct->AES_Chaining = AES_Chaining_ECB; AES_InitStruct->AES_DataType = AES_DataType_32b; } /** * @brief Fills each AES_KeyInitStruct member with its default value. * @param AES_KeyInitStruct: pointer to an AES_KeyInitStruct structure which * will be initialized. * @retval None */ void AES_KeyStructInit(AES_KeyInitTypeDef* AES_KeyInitStruct) { AES_KeyInitStruct->AES_Key0 = 0x00000000; AES_KeyInitStruct->AES_Key1 = 0x00000000; AES_KeyInitStruct->AES_Key2 = 0x00000000; AES_KeyInitStruct->AES_Key3 = 0x00000000; } /** * @brief Fills each AES_IVInitStruct member with its default value. * @param AES_IVInitStruct: pointer to an AES_IVInitTypeDef structure which * will be initialized. * @retval None */ void AES_IVStructInit(AES_IVInitTypeDef* AES_IVInitStruct) { AES_IVInitStruct->AES_IV0 = 0x00000000; AES_IVInitStruct->AES_IV1 = 0x00000000; AES_IVInitStruct->AES_IV2 = 0x00000000; AES_IVInitStruct->AES_IV3 = 0x00000000; } /** * @} */ /** @defgroup AES_Group3 AES Read and Write * @brief AES Read and Write. * @verbatim =============================================================================== ##### AES Read and Write functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Write data in DINR register to be processed by AES peripheral. * @note To process 128-bit data (4 * 32-bit), this function must be called * four times to write the 128-bit data in the 32-bit register DINR. * @note When an unexpected write to DOUTR register is detected, WRERR flag is * set. * @param Data: The data to be processed. * @retval None */ void AES_WriteSubData(uint32_t Data) { /* Write Data */ AES->DINR = Data; } /** * @brief Returns the data in DOUTR register processed by AES peripheral. * @note This function must be called four times to get the 128-bit data. * @note When an unexpected read of DINR register is detected, RDERR flag is * set. * @retval The processed data. */ uint32_t AES_ReadSubData(void) { /* Read Data */ return AES->DOUTR; } /** * @brief Read the Key value. * @param AES_KeyInitStruct: pointer to an AES_KeyInitTypeDef structure which * will contain the key. * @note When the key derivation mode is selected, AES must be disabled * (AES_Cmd(DISABLE)) before reading the decryption key. * Reading the key while the AES is enabled will return unpredictable * value. * @retval None */ void AES_ReadKey(AES_KeyInitTypeDef* AES_KeyInitStruct) { AES_KeyInitStruct->AES_Key0 = AES->KEYR0; AES_KeyInitStruct->AES_Key1 = AES->KEYR1; AES_KeyInitStruct->AES_Key2 = AES->KEYR2; AES_KeyInitStruct->AES_Key3 = AES->KEYR3; } /** * @brief Read the Initialization Vector IV value. * @param AES_IVInitStruct: pointer to an AES_IVInitTypeDef structure which * will contain the Initialization Vector IV. * @note When the AES is enabled Reading the Initialization Vector IV value * will return 0. The AES must be disabled using AES_Cmd(DISABLE) * to get the right value. * @note When ECB chaining mode is selected, Initialization Vector IV has no * meaning. * When CTR chaining mode is selected, AES_IV0 contains 32-bit Counter value. * AES_IV1, AES_IV2 and AES_IV3 contains nonce value. * @retval None */ void AES_ReadIV(AES_IVInitTypeDef* AES_IVInitStruct) { AES_IVInitStruct->AES_IV0 = AES->IVR0; AES_IVInitStruct->AES_IV1 = AES->IVR1; AES_IVInitStruct->AES_IV2 = AES->IVR2; AES_IVInitStruct->AES_IV3 = AES->IVR3; } /** * @} */ /** @defgroup AES_Group4 DMA transfers management functions * @brief DMA transfers management function. * @verbatim =============================================================================== ##### DMA transfers management functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Configures the AES DMA interface. * @param AES_DMATransfer: Specifies the AES DMA transfer. * This parameter can be one of the following values: * @arg AES_DMATransfer_In: When selected, DMA manages the data input phase. * @arg AES_DMATransfer_Out: When selected, DMA manages the data output phase. * @arg AES_DMATransfer_InOut: When selected, DMA manages both the data input/output phases. * @param NewState Indicates the new state of the AES DMA interface. * This parameter can be: ENABLE or DISABLE. * @note The DMA has no action in key derivation mode. * @retval None */ void AES_DMAConfig(uint32_t AES_DMATransfer, FunctionalState NewState) { /* Check the parameter */ assert_param(IS_AES_DMA_TRANSFER(AES_DMATransfer)); if (NewState != DISABLE) { /* Enable the DMA transfer */ AES->CR |= (uint32_t) AES_DMATransfer; } else { /* Disable the DMA transfer */ AES->CR &= (uint32_t)(~AES_DMATransfer); } } /** * @} */ /** @defgroup AES_Group5 Interrupts and flags management functions * @brief Interrupts and flags management functions. * @verbatim =============================================================================== ##### Interrupts and flags management functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables the specified AES interrupt. * @param AES_IT: Specifies the AES interrupt source to enable/disable. * This parameter can be any combinations of the following values: * @arg AES_IT_CC: Computation Complete Interrupt. If enabled, once CCF * flag is set an interrupt is generated. * @arg AES_IT_ERR: Error Interrupt. If enabled, once a read error * flags (RDERR) or write error flag (WRERR) is set, * an interrupt is generated. * @param NewState: The new state of the AES interrupt source. * This parameter can be: ENABLE or DISABLE. * @retval None */ void AES_ITConfig(uint32_t AES_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); assert_param(IS_AES_IT(AES_IT)); if (NewState != DISABLE) { AES->CR |= (uint32_t) AES_IT; /**< AES_IT Enable */ } else { AES->CR &= (uint32_t)(~AES_IT); /**< AES_IT Disable */ } } /** * @brief Checks whether the specified AES flag is set or not. * @param AES_FLAG specifies the flag to check. * This parameter can be one of the following values: * @arg AES_FLAG_CCF: Computation Complete Flag is set by hardware when * he computation phase is completed. * @arg AES_FLAG_RDERR: Read Error Flag is set when an unexpected read * operation of DOUTR register is detected. * @arg AES_FLAG_WRERR: Write Error Flag is set when an unexpected write * operation in DINR is detected. * @retval FlagStatus (SET or RESET) */ FlagStatus AES_GetFlagStatus(uint32_t AES_FLAG) { FlagStatus bitstatus = RESET; /* Check parameters */ assert_param(IS_AES_FLAG(AES_FLAG)); if ((AES->SR & AES_FLAG) != (uint32_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } /* Return the AES_FLAG status */ return bitstatus; } /** * @brief Clears the AES flags. * @param AES_FLAG: specifies the flag to clear. * This parameter can be: * @arg AES_FLAG_CCF: Computation Complete Flag is cleared by setting CCFC * bit in CR register. * @arg AES_FLAG_RDERR: Read Error is cleared by setting ERRC bit in * CR register. * @arg AES_FLAG_WRERR: Write Error is cleared by setting ERRC bit in * CR register. * @retval None */ void AES_ClearFlag(uint32_t AES_FLAG) { /* Check the parameters */ assert_param(IS_AES_FLAG(AES_FLAG)); /* Check if AES_FLAG is AES_FLAG_CCF */ if (AES_FLAG == AES_FLAG_CCF) { /* Clear CCF flag by setting CCFC bit */ AES->CR |= (uint32_t) AES_CR_CCFC; } else /* AES_FLAG is AES_FLAG_RDERR or AES_FLAG_WRERR */ { /* Clear RDERR and WRERR flags by setting ERRC bit */ AES->CR |= (uint32_t) AES_CR_ERRC; } } /** * @brief Checks whether the specified AES interrupt has occurred or not. * @param AES_IT: Specifies the AES interrupt pending bit to check. * This parameter can be: * @arg AES_IT_CC: Computation Complete Interrupt. * @arg AES_IT_ERR: Error Interrupt. * @retval ITStatus The new state of AES_IT (SET or RESET). */ ITStatus AES_GetITStatus(uint32_t AES_IT) { ITStatus itstatus = RESET; uint32_t cciebitstatus = RESET, ccfbitstatus = RESET; /* Check parameters */ assert_param(IS_AES_GET_IT(AES_IT)); cciebitstatus = AES->CR & AES_CR_CCIE; ccfbitstatus = AES->SR & AES_SR_CCF; /* Check if AES_IT is AES_IT_CC */ if (AES_IT == AES_IT_CC) { /* Check the status of the specified AES interrupt */ if (((cciebitstatus) != (uint32_t)RESET) && ((ccfbitstatus) != (uint32_t)RESET)) { /* Interrupt occurred */ itstatus = SET; } else { /* Interrupt didn't occur */ itstatus = RESET; } } else /* AES_IT is AES_IT_ERR */ { /* Check the status of the specified AES interrupt */ if ((AES->CR & AES_CR_ERRIE) != RESET) { /* Check if WRERR or RDERR flags are set */ if ((AES->SR & (uint32_t)(AES_SR_WRERR | AES_SR_RDERR)) != (uint16_t)RESET) { /* Interrupt occurred */ itstatus = SET; } else { /* Interrupt didn't occur */ itstatus = RESET; } } else { /* Interrupt didn't occur */ itstatus = (ITStatus) RESET; } } /* Return the AES_IT status */ return itstatus; } /** * @brief Clears the AES's interrupt pending bits. * @param AES_IT: specifies the interrupt pending bit to clear. * This parameter can be any combinations of the following values: * @arg AES_IT_CC: Computation Complete Interrupt. * @arg AES_IT_ERR: Error Interrupt. * @retval None */ void AES_ClearITPendingBit(uint32_t AES_IT) { /* Check the parameters */ assert_param(IS_AES_IT(AES_IT)); /* Clear the interrupt pending bit */ AES->CR |= (uint32_t) (AES_IT >> (uint32_t) 0x00000002); } /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/src/stm32l1xx_aes_util.c
New file @@ -0,0 +1,679 @@ /** ****************************************************************************** * @file stm32l1xx_aes_util.c * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file provides high level functions to encrypt and decrypt an * input message using AES in ECB/CBC/CTR modes. * * @verbatim ================================================================================ ##### How to use this driver ##### ================================================================================ [..] (#) Enable The AES controller clock using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_AES, ENABLE); function. (#) Use AES_ECB_Encrypt() function to encrypt an input message in ECB mode. (#) Use AES_ECB_Decrypt() function to decrypt an input message in ECB mode. (#) Use AES_CBC_Encrypt() function to encrypt an input message in CBC mode. (#) Use AES_CBC_Decrypt() function to decrypt an input message in CBC mode. (#) Use AES_CTR_Encrypt() function to encrypt an input message in CTR mode. (#) Use AES_CTR_Decrypt() function to decrypt an input message in CTR mode. * @endverbatim * ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx_aes.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @addtogroup AES * @brief AES driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #define AES_CC_TIMEOUT ((uint32_t) 0x00010000) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup AES_Private_Functions * @{ */ /** @defgroup AES_Group6 High Level AES functions * @brief High Level AES functions * @verbatim ================================================================================ ##### High Level AES functions ##### ================================================================================ @endverbatim * @{ */ /** * @brief Encrypt using AES in ECB Mode * @param Key: Key used for AES algorithm. * @param Input: pointer to the Input buffer. * @param Ilength: length of the Input buffer, must be a multiple of 16 bytes. * @param Output: pointer to the returned buffer. * @retval An ErrorStatus enumeration value: * - SUCCESS: Operation done * - ERROR: Operation failed */ ErrorStatus AES_ECB_Encrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output) { AES_InitTypeDef AES_InitStructure; AES_KeyInitTypeDef AES_KeyInitStructure; ErrorStatus status = SUCCESS; uint32_t keyaddr = (uint32_t)Key; uint32_t inputaddr = (uint32_t)Input; uint32_t outputaddr = (uint32_t)Output; __IO uint32_t counter = 0; uint32_t ccstatus = 0; uint32_t i = 0; /* AES Key initialisation */ AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr)); keyaddr += 4; AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr)); keyaddr += 4; AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr)); keyaddr += 4; AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr)); AES_KeyInit(&AES_KeyInitStructure); /* AES configuration */ AES_InitStructure.AES_Operation = AES_Operation_Encryp; AES_InitStructure.AES_Chaining = AES_Chaining_ECB; AES_InitStructure.AES_DataType = AES_DataType_8b; AES_Init(&AES_InitStructure); /* Enable AES */ AES_Cmd(ENABLE); for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16) { AES_WriteSubData(*(uint32_t*)(inputaddr)); inputaddr += 4; AES_WriteSubData(*(uint32_t*)(inputaddr)); inputaddr += 4; AES_WriteSubData(*(uint32_t*)(inputaddr)); inputaddr += 4; AES_WriteSubData(*(uint32_t*)(inputaddr)); inputaddr += 4; /* Wait for CCF flag to be set */ counter = 0; do { ccstatus = AES_GetFlagStatus(AES_FLAG_CCF); counter++; }while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET)); if (ccstatus == RESET) { status = ERROR; } else { /* Clear CCF flag */ AES_ClearFlag(AES_FLAG_CCF); /* Read cipher text */ *(uint32_t*)(outputaddr) = AES_ReadSubData(); outputaddr += 4; *(uint32_t*)(outputaddr) = AES_ReadSubData(); outputaddr += 4; *(uint32_t*)(outputaddr) = AES_ReadSubData(); outputaddr += 4; *(uint32_t*)(outputaddr) = AES_ReadSubData(); outputaddr += 4; } } /* Disable AES before starting new processing */ AES_Cmd(DISABLE); return status; } /** * @brief Decrypt using AES in ECB Mode * @param Key: Key used for AES algorithm. * @param Input: pointer to the Input buffer. * @param Ilength: length of the Input buffer, must be a multiple of 16 bytes. * @param Output: pointer to the returned buffer. * @retval An ErrorStatus enumeration value: * - SUCCESS: Operation done * - ERROR: Operation failed */ ErrorStatus AES_ECB_Decrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output) { AES_InitTypeDef AES_InitStructure; AES_KeyInitTypeDef AES_KeyInitStructure; ErrorStatus status = SUCCESS; uint32_t keyaddr = (uint32_t)Key; uint32_t inputaddr = (uint32_t)Input; uint32_t outputaddr = (uint32_t)Output; __IO uint32_t counter = 0; uint32_t ccstatus = 0; uint32_t i = 0; /* AES Key initialisation */ AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr)); keyaddr += 4; AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr)); keyaddr += 4; AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr)); keyaddr += 4; AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr)); AES_KeyInit(&AES_KeyInitStructure); /* AES configuration */ AES_InitStructure.AES_Operation = AES_Operation_KeyDerivAndDecryp; AES_InitStructure.AES_Chaining = AES_Chaining_ECB; AES_InitStructure.AES_DataType = AES_DataType_8b; AES_Init(&AES_InitStructure); /* Enable AES */ AES_Cmd(ENABLE); for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16) { AES_WriteSubData(*(uint32_t*)(inputaddr)); inputaddr += 4; AES_WriteSubData(*(uint32_t*)(inputaddr)); inputaddr += 4; AES_WriteSubData(*(uint32_t*)(inputaddr)); inputaddr += 4; AES_WriteSubData(*(uint32_t*)(inputaddr)); inputaddr += 4; /* Wait for CCF flag to be set */ counter = 0; do { ccstatus = AES_GetFlagStatus(AES_FLAG_CCF); counter++; }while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET)); if (ccstatus == RESET) { status = ERROR; } else { /* Clear CCF flag */ AES_ClearFlag(AES_FLAG_CCF); /* Read cipher text */ *(uint32_t*)(outputaddr) = AES_ReadSubData(); outputaddr += 4; *(uint32_t*)(outputaddr) = AES_ReadSubData(); outputaddr += 4; *(uint32_t*)(outputaddr) = AES_ReadSubData(); outputaddr += 4; *(uint32_t*)(outputaddr) = AES_ReadSubData(); outputaddr += 4; } } /* Disable AES before starting new processing */ AES_Cmd(DISABLE); return status; } /** * @brief Encrypt using AES in CBC Mode * @param InitVectors: Initialisation Vectors used for AES algorithm. * @param Key: Key used for AES algorithm. * @param Input: pointer to the Input buffer. * @param Ilength: length of the Input buffer, must be a multiple of 16 bytes. * @param Output: pointer to the returned buffer. * @retval An ErrorStatus enumeration value: * - SUCCESS: Operation done * - ERROR: Operation failed */ ErrorStatus AES_CBC_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output) { AES_InitTypeDef AES_InitStructure; AES_KeyInitTypeDef AES_KeyInitStructure; AES_IVInitTypeDef AES_IVInitStructure; ErrorStatus status = SUCCESS; uint32_t keyaddr = (uint32_t)Key; uint32_t inputaddr = (uint32_t)Input; uint32_t outputaddr = (uint32_t)Output; uint32_t ivaddr = (uint32_t)InitVectors; __IO uint32_t counter = 0; uint32_t ccstatus = 0; uint32_t i = 0; /* AES Key initialisation*/ AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr)); keyaddr += 4; AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr)); keyaddr += 4; AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr)); keyaddr += 4; AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr)); AES_KeyInit(&AES_KeyInitStructure); /* AES Initialization Vectors */ AES_IVInitStructure.AES_IV3 = __REV(*(uint32_t*)(ivaddr)); ivaddr += 4; AES_IVInitStructure.AES_IV2 = __REV(*(uint32_t*)(ivaddr)); ivaddr += 4; AES_IVInitStructure.AES_IV1 = __REV(*(uint32_t*)(ivaddr)); ivaddr += 4; AES_IVInitStructure.AES_IV0 = __REV(*(uint32_t*)(ivaddr)); AES_IVInit(&AES_IVInitStructure); /* AES configuration */ AES_InitStructure.AES_Operation = AES_Operation_Encryp; AES_InitStructure.AES_Chaining = AES_Chaining_CBC; AES_InitStructure.AES_DataType = AES_DataType_8b; AES_Init(&AES_InitStructure); /* Enable AES */ AES_Cmd(ENABLE); for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16) { AES_WriteSubData(*(uint32_t*)(inputaddr)); inputaddr += 4; AES_WriteSubData(*(uint32_t*)(inputaddr)); inputaddr += 4; AES_WriteSubData(*(uint32_t*)(inputaddr)); inputaddr += 4; AES_WriteSubData(*(uint32_t*)(inputaddr)); inputaddr += 4; /* Wait for CCF flag to be set */ counter = 0; do { ccstatus = AES_GetFlagStatus(AES_FLAG_CCF); counter++; }while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET)); if (ccstatus == RESET) { status = ERROR; } else { /* Clear CCF flag */ AES_ClearFlag(AES_FLAG_CCF); /* Read cipher text */ *(uint32_t*)(outputaddr) = AES_ReadSubData(); outputaddr += 4; *(uint32_t*)(outputaddr) = AES_ReadSubData(); outputaddr += 4; *(uint32_t*)(outputaddr) = AES_ReadSubData(); outputaddr += 4; *(uint32_t*)(outputaddr) = AES_ReadSubData(); outputaddr += 4; } } /* Disable AES before starting new processing */ AES_Cmd(DISABLE); return status; } /** * @brief Decrypt using AES in CBC Mode * @param InitVectors: Initialisation Vectors used for AES algorithm. * @param Key: Key used for AES algorithm. * @param Input: pointer to the Input buffer. * @param Ilength: length of the Input buffer, must be a multiple of 16 bytes. * @param Output: pointer to the returned buffer. * @retval An ErrorStatus enumeration value: * - SUCCESS: Operation done * - ERROR: Operation failed */ ErrorStatus AES_CBC_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output) { AES_InitTypeDef AES_InitStructure; AES_KeyInitTypeDef AES_KeyInitStructure; AES_IVInitTypeDef AES_IVInitStructure; ErrorStatus status = SUCCESS; uint32_t keyaddr = (uint32_t)Key; uint32_t inputaddr = (uint32_t)Input; uint32_t outputaddr = (uint32_t)Output; uint32_t ivaddr = (uint32_t)InitVectors; __IO uint32_t counter = 0; uint32_t ccstatus = 0; uint32_t i = 0; /* AES Key initialisation*/ AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr)); keyaddr += 4; AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr)); keyaddr += 4; AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr)); keyaddr += 4; AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr)); AES_KeyInit(&AES_KeyInitStructure); /* AES Initialization Vectors */ AES_IVInitStructure.AES_IV3 = __REV(*(uint32_t*)(ivaddr)); ivaddr += 4; AES_IVInitStructure.AES_IV2 = __REV(*(uint32_t*)(ivaddr)); ivaddr += 4; AES_IVInitStructure.AES_IV1 = __REV(*(uint32_t*)(ivaddr)); ivaddr += 4; AES_IVInitStructure.AES_IV0 = __REV(*(uint32_t*)(ivaddr)); AES_IVInit(&AES_IVInitStructure); /* AES configuration */ AES_InitStructure.AES_Operation = AES_Operation_KeyDerivAndDecryp; AES_InitStructure.AES_Chaining = AES_Chaining_CBC; AES_InitStructure.AES_DataType = AES_DataType_8b; AES_Init(&AES_InitStructure); /* Enable AES */ AES_Cmd(ENABLE); for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16) { AES_WriteSubData(*(uint32_t*)(inputaddr)); inputaddr += 4; AES_WriteSubData(*(uint32_t*)(inputaddr)); inputaddr += 4; AES_WriteSubData(*(uint32_t*)(inputaddr)); inputaddr += 4; AES_WriteSubData(*(uint32_t*)(inputaddr)); inputaddr += 4; /* Wait for CCF flag to be set */ counter = 0; do { ccstatus = AES_GetFlagStatus(AES_FLAG_CCF); counter++; }while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET)); if (ccstatus == RESET) { status = ERROR; } else { /* Clear CCF flag */ AES_ClearFlag(AES_FLAG_CCF); /* Read cipher text */ *(uint32_t*)(outputaddr) = AES_ReadSubData(); outputaddr += 4; *(uint32_t*)(outputaddr) = AES_ReadSubData(); outputaddr += 4; *(uint32_t*)(outputaddr) = AES_ReadSubData(); outputaddr += 4; *(uint32_t*)(outputaddr) = AES_ReadSubData(); outputaddr += 4; } } /* Disable AES before starting new processing */ AES_Cmd(DISABLE); return status; } /** * @brief Encrypt using AES in CTR Mode * @param InitVectors: Initialisation Vectors used for AES algorithm. * @param Key: Key used for AES algorithm. * @param Input: pointer to the Input buffer. * @param Ilength: length of the Input buffer, must be a multiple of 16 bytes. * @param Output: pointer to the returned buffer. * @retval An ErrorStatus enumeration value: * - SUCCESS: Operation done * - ERROR: Operation failed */ ErrorStatus AES_CTR_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output) { AES_InitTypeDef AES_InitStructure; AES_KeyInitTypeDef AES_KeyInitStructure; AES_IVInitTypeDef AES_IVInitStructure; ErrorStatus status = SUCCESS; uint32_t keyaddr = (uint32_t)Key; uint32_t inputaddr = (uint32_t)Input; uint32_t outputaddr = (uint32_t)Output; uint32_t ivaddr = (uint32_t)InitVectors; __IO uint32_t counter = 0; uint32_t ccstatus = 0; uint32_t i = 0; /* AES key initialisation*/ AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr)); keyaddr += 4; AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr)); keyaddr += 4; AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr)); keyaddr += 4; AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr)); AES_KeyInit(&AES_KeyInitStructure); /* AES Initialization Vectors */ AES_IVInitStructure.AES_IV3 = __REV(*(uint32_t*)(ivaddr)); ivaddr += 4; AES_IVInitStructure.AES_IV2= __REV(*(uint32_t*)(ivaddr)); ivaddr += 4; AES_IVInitStructure.AES_IV1 = __REV(*(uint32_t*)(ivaddr)); ivaddr += 4; AES_IVInitStructure.AES_IV0= __REV(*(uint32_t*)(ivaddr)); AES_IVInit(&AES_IVInitStructure); /* AES configuration */ AES_InitStructure.AES_Operation = AES_Operation_Encryp; AES_InitStructure.AES_Chaining = AES_Chaining_CTR; AES_InitStructure.AES_DataType = AES_DataType_8b; AES_Init(&AES_InitStructure); /* Enable AES */ AES_Cmd(ENABLE); for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16) { AES_WriteSubData(*(uint32_t*)(inputaddr)); inputaddr += 4; AES_WriteSubData(*(uint32_t*)(inputaddr)); inputaddr += 4; AES_WriteSubData(*(uint32_t*)(inputaddr)); inputaddr += 4; AES_WriteSubData(*(uint32_t*)(inputaddr)); inputaddr += 4; /* Wait for CCF flag to be set */ counter = 0; do { ccstatus = AES_GetFlagStatus(AES_FLAG_CCF); counter++; }while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET)); if (ccstatus == RESET) { status = ERROR; } else { /* Clear CCF flag */ AES_ClearFlag(AES_FLAG_CCF); /* Read cipher text */ *(uint32_t*)(outputaddr) = AES_ReadSubData(); outputaddr += 4; *(uint32_t*)(outputaddr) = AES_ReadSubData(); outputaddr += 4; *(uint32_t*)(outputaddr) = AES_ReadSubData(); outputaddr += 4; *(uint32_t*)(outputaddr) = AES_ReadSubData(); outputaddr += 4; } } /* Disable AES before starting new processing */ AES_Cmd(DISABLE); return status; } /** * @brief Decrypt using AES in CTR Mode * @param InitVectors: Initialisation Vectors used for AES algorithm. * @param Key: Key used for AES algorithm. * @param Input: pointer to the Input buffer. * @param Ilength: length of the Input buffer, must be a multiple of 16 bytes. * @param Output: pointer to the returned buffer. * @retval An ErrorStatus enumeration value: * - SUCCESS: Operation done * - ERROR: Operation failed */ ErrorStatus AES_CTR_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output) { AES_InitTypeDef AES_InitStructure; AES_KeyInitTypeDef AES_KeyInitStructure; AES_IVInitTypeDef AES_IVInitStructure; ErrorStatus status = SUCCESS; uint32_t keyaddr = (uint32_t)Key; uint32_t inputaddr = (uint32_t)Input; uint32_t outputaddr = (uint32_t)Output; uint32_t ivaddr = (uint32_t)InitVectors; __IO uint32_t counter = 0; uint32_t ccstatus = 0; uint32_t i = 0; /* AES Key initialisation*/ AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr)); keyaddr += 4; AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr)); keyaddr += 4; AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr)); keyaddr += 4; AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr)); AES_KeyInit(&AES_KeyInitStructure); /* AES Initialization Vectors */ AES_IVInitStructure.AES_IV3 = __REV(*(uint32_t*)(ivaddr)); ivaddr += 4; AES_IVInitStructure.AES_IV2 = __REV(*(uint32_t*)(ivaddr)); ivaddr += 4; AES_IVInitStructure.AES_IV1 = __REV(*(uint32_t*)(ivaddr)); ivaddr += 4; AES_IVInitStructure.AES_IV0 = __REV(*(uint32_t*)(ivaddr)); AES_IVInit(&AES_IVInitStructure); /* AES configuration */ AES_InitStructure.AES_Operation = AES_Operation_KeyDerivAndDecryp; AES_InitStructure.AES_Chaining = AES_Chaining_CTR; AES_InitStructure.AES_DataType = AES_DataType_8b; AES_Init(&AES_InitStructure); /* Enable AES */ AES_Cmd(ENABLE); for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16) { AES_WriteSubData(*(uint32_t*)(inputaddr)); inputaddr += 4; AES_WriteSubData(*(uint32_t*)(inputaddr)); inputaddr += 4; AES_WriteSubData(*(uint32_t*)(inputaddr)); inputaddr += 4; AES_WriteSubData(*(uint32_t*)(inputaddr)); inputaddr += 4; /* Wait for CCF flag to be set */ counter = 0; do { ccstatus = AES_GetFlagStatus(AES_FLAG_CCF); counter++; }while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET)); if (ccstatus == RESET) { status = ERROR; } else { /* Clear CCF flag */ AES_ClearFlag(AES_FLAG_CCF); /* Read cipher text */ *(uint32_t*)(outputaddr) = AES_ReadSubData(); outputaddr += 4; *(uint32_t*)(outputaddr) = AES_ReadSubData(); outputaddr += 4; *(uint32_t*)(outputaddr) = AES_ReadSubData(); outputaddr += 4; *(uint32_t*)(outputaddr) = AES_ReadSubData(); outputaddr += 4; } } /* Disable AES before starting new processing */ AES_Cmd(DISABLE); return status; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
New file @@ -0,0 +1,378 @@ /** ****************************************************************************** * @file stm32l1xx_comp.c * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file provides firmware functions to manage the following * functionalities of the comparators (COMP1 and COMP2) peripheral: * + Comparators configuration * + Window mode control * + Internal Reference Voltage (VREFINT) output * * @verbatim =============================================================================== ##### How to use this driver ##### =============================================================================== [..] The device integrates two analog comparators COMP1 and COMP2: (+) COMP1 is a fixed threshold (VREFINT) that shares the non inverting input with the ADC channels. (+) COMP2 is a rail-to-rail comparator whose the inverting input can be selected among: DAC_OUT1, DAC_OUT2, 1/4 VREFINT, 1/2 VERFINT, 3/4 VREFINT, VREFINT, PB3 and whose the output can be redirected to embedded timers: TIM2, TIM3, TIM4, TIM10. (+) The two comparators COMP1 and COMP2 can be combined in window mode. -@- (#@) Comparator APB clock must be enabled to get write access to comparator register using RCC_APB1PeriphClockCmd(RCC_APB1Periph_COMP, ENABLE). (#@) COMP1 comparator and ADC can't be used at the same time since they share the same ADC switch matrix (analog switches). (#@) When an I/O is used as comparator input, the corresponding GPIO registers should be configured in analog mode. (#@) Comparators outputs (CMP1OUT and CMP2OUT) are not mapped on GPIO pin. They are only internal. To get the comparator output level, use COMP_GetOutputLevel(). (#@) COMP1 and COMP2 outputs are internally connected to EXTI Line 21 and EXTI Line 22 respectively. Interrupts can be used by configuring the EXTI Line using the EXTI peripheral driver. (#@) After enabling the comparator (COMP1 or COMP2), user should wait for start-up time (tSTART) to get right output levels. Please refer to product datasheet for more information on tSTART. (#@) Comparators cannot be used to exit the device from Sleep or Stop mode when the internal reference voltage is switched off using the PWR_UltraLowPowerCmd() function (ULP bit in the PWR_CR register). @endverbatim ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx_comp.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @defgroup COMP * @brief COMP driver modules. * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup COMP_Private_Functions * @{ */ /** @defgroup COMP_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions. * @verbatim =============================================================================== ##### Initialization and Configuration functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Deinitializes COMP peripheral registers to their default reset values. * @param None * @retval None */ void COMP_DeInit(void) { COMP->CSR = ((uint32_t)0x00000000); /*!< Set COMP->CSR to reset value */ } /** * @brief Initializes the COMP2 peripheral according to the specified parameters * in the COMP_InitStruct. * @note This function configures only COMP2. * @note COMP2 comparator is enabled as soon as the INSEL[2:0] bits are * different from "000". * @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure that contains * the configuration information for the specified COMP peripheral. * @retval None */ void COMP_Init(COMP_InitTypeDef* COMP_InitStruct) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_COMP_INVERTING_INPUT(COMP_InitStruct->COMP_InvertingInput)); assert_param(IS_COMP_OUTPUT(COMP_InitStruct->COMP_OutputSelect)); assert_param(IS_COMP_SPEED(COMP_InitStruct->COMP_Speed)); /*!< Get the COMP CSR value */ tmpreg = COMP->CSR; /*!< Clear the INSEL[2:0], OUTSEL[1:0] and SPEED bits */ tmpreg &= (uint32_t) (~(uint32_t) (COMP_CSR_OUTSEL | COMP_CSR_INSEL | COMP_CSR_SPEED)); /*!< Configure COMP: speed, inversion input selection and output redirection */ /*!< Set SPEED bit according to COMP_InitStruct->COMP_Speed value */ /*!< Set INSEL bits according to COMP_InitStruct->COMP_InvertingInput value */ /*!< Set OUTSEL bits according to COMP_InitStruct->COMP_OutputSelect value */ tmpreg |= (uint32_t)((COMP_InitStruct->COMP_Speed | COMP_InitStruct->COMP_InvertingInput | COMP_InitStruct->COMP_OutputSelect)); /*!< The COMP2 comparator is enabled as soon as the INSEL[2:0] bits value are different from "000" */ /*!< Write to COMP_CSR register */ COMP->CSR = tmpreg; } /** * @brief Enable or disable the COMP1 peripheral. * @note After enabling COMP1, the following functions should be called to * connect the selected GPIO input to COMP1 non inverting input: * @note Enable switch control mode using SYSCFG_RISwitchControlModeCmd() * @note Close VCOMP switch using SYSCFG_RIIOSwitchConfig() * @note Close the I/O switch number n corresponding to the I/O * using SYSCFG_RIIOSwitchConfig() * @param NewState: new state of the COMP1 peripheral. * This parameter can be: ENABLE or DISABLE. * @note This function enables/disables only the COMP1. * @retval None */ void COMP_Cmd(FunctionalState NewState) { /* Check the parameter */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the COMP1 */ COMP->CSR |= (uint32_t) COMP_CSR_CMP1EN; } else { /* Disable the COMP1 */ COMP->CSR &= (uint32_t)(~COMP_CSR_CMP1EN); } } /** * @brief Return the output level (high or low) of the selected comparator. * @note Comparator output is low when the noninverting input is at a lower * voltage than the inverting input. * @note Comparator output is high when the noninverting input is at a higher * voltage than the inverting input. * @note Comparators outputs aren't available on GPIO (outputs levels are * only internal). The COMP1 and COMP2 outputs are connected internally * to the EXTI Line 21 and Line 22 respectively. * @param COMP_Selection: the selected comparator. * This parameter can be one of the following values: * @arg COMP_Selection_COMP1: COMP1 selected * @arg COMP_Selection_COMP2: COMP2 selected * @retval Returns the selected comparator output level. */ uint8_t COMP_GetOutputLevel(uint32_t COMP_Selection) { uint8_t compout = 0x0; /* Check the parameters */ assert_param(IS_COMP_ALL_PERIPH(COMP_Selection)); /* Check if Comparator 1 is selected */ if(COMP_Selection == COMP_Selection_COMP1) { /* Check if comparator 1 output level is high */ if((COMP->CSR & COMP_CSR_CMP1OUT) != (uint8_t) RESET) { /* Get Comparator 1 output level */ compout = (uint8_t) COMP_OutputLevel_High; } /* comparator 1 output level is low */ else { /* Get Comparator 1 output level */ compout = (uint8_t) COMP_OutputLevel_Low; } } /* Comparator 2 is selected */ else { /* Check if comparator 2 output level is high */ if((COMP->CSR & COMP_CSR_CMP2OUT) != (uint8_t) RESET) { /* Get Comparator output level */ compout = (uint8_t) COMP_OutputLevel_High; } /* comparator 2 output level is low */ else { /* Get Comparator 2 output level */ compout = (uint8_t) COMP_OutputLevel_Low; } } /* Return the comparator output level */ return (uint8_t)(compout); } /** * @brief Close or Open the SW1 switch. * @param NewState: new state of the SW1 switch. * This parameter can be: ENABLE or DISABLE. * @note ENABLE to close the SW1 switch * @note DISABLE to open the SW1 switch * @retval None. */ void COMP_SW1SwitchConfig(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Close SW1 switch */ COMP->CSR |= (uint32_t) COMP_CSR_SW1; } else { /* Open SW1 switch */ COMP->CSR &= (uint32_t)(~COMP_CSR_SW1); } } /** * @} */ /** @defgroup COMP_Group2 Window mode control function * @brief Window mode control function. * @verbatim =============================================================================== ##### Window mode control function ##### =============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables the window mode. * In window mode: * @note COMP1 inverting input is fixed to VREFINT defining the first * threshold. * @note COMP2 inverting input is configurable (DAC_OUT1, DAC_OUT2, VREFINT * sub-multiples, PB3) defining the second threshold. * @note COMP1 and COMP2 non inverting inputs are connected together. * @note In window mode, only the Group 6 (PB4 or PB5) can be used as * noninverting inputs. * @param NewState: new state of the window mode. * This parameter can be ENABLE or DISABLE. * @retval None */ void COMP_WindowCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the window mode */ COMP->CSR |= (uint32_t) COMP_CSR_WNDWE; } else { /* Disable the window mode */ COMP->CSR &= (uint32_t)(~COMP_CSR_WNDWE); } } /** * @} */ /** @defgroup COMP_Group3 Internal Reference Voltage output function * @brief Internal Reference Voltage (VREFINT) output function. * @verbatim =============================================================================== ##### Internal Reference Voltage (VREFINT) output function ##### =============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables the output of internal reference voltage (VREFINT). * The VREFINT output can be routed to any I/O in group 3: CH8 (PB0) or * CH9 (PB1). * To correctly use this function, the SYSCFG_RIIOSwitchConfig() function * should be called after. * @param NewState: new state of the Vrefint output. * This parameter can be: ENABLE or DISABLE. * @retval None */ void COMP_VrefintOutputCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the output of internal reference voltage */ COMP->CSR |= (uint32_t) COMP_CSR_VREFOUTEN; } else { /* Disable the output of internal reference voltage */ COMP->CSR &= (uint32_t) (~COMP_CSR_VREFOUTEN); } } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/src/stm32l1xx_crc.c
New file @@ -0,0 +1,133 @@ /** ****************************************************************************** * @file stm32l1xx_crc.c * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file provides all the CRC firmware functions. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx_crc.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @defgroup CRC * @brief CRC driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup CRC_Private_Functions * @{ */ /** * @brief Resets the CRC Data register (DR). * @param None * @retval None */ void CRC_ResetDR(void) { /* Reset CRC generator */ CRC->CR = CRC_CR_RESET; } /** * @brief Computes the 32-bit CRC of a given data word(32-bit). * @param Data: data word(32-bit) to compute its CRC. * @retval 32-bit CRC */ uint32_t CRC_CalcCRC(uint32_t Data) { CRC->DR = Data; return (CRC->DR); } /** * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). * @param pBuffer: pointer to the buffer containing the data to be computed. * @param BufferLength: length of the buffer to be computed * @retval 32-bit CRC */ uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) { uint32_t index = 0; for(index = 0; index < BufferLength; index++) { CRC->DR = pBuffer[index]; } return (CRC->DR); } /** * @brief Returns the current CRC value. * @param None * @retval 32-bit CRC */ uint32_t CRC_GetCRC(void) { return (CRC->DR); } /** * @brief Stores a 8-bit data in the Independent Data(ID) register. * @param IDValue: 8-bit value to be stored in the ID register * @retval None */ void CRC_SetIDRegister(uint8_t IDValue) { CRC->IDR = IDValue; } /** * @brief Returns the 8-bit data stored in the Independent Data(ID) register. * @param None * @retval 8-bit value of the ID register */ uint8_t CRC_GetIDRegister(void) { return (CRC->IDR); } /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/src/stm32l1xx_dac.c
New file @@ -0,0 +1,687 @@ /** ****************************************************************************** * @file stm32l1xx_dac.c * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file provides firmware functions to manage the following * functionalities of the Digital-to-Analog Converter (DAC) peripheral: * + DAC channels configuration: trigger, output buffer, data format * + DMA management * + Interrupts and flags management * @verbatim * =============================================================================== ##### DAC Peripheral features ##### =============================================================================== [..] The device integrates two 12-bit Digital Analog Converters that can be used independently or simultaneously (dual mode): (#) DAC channel1 with DAC_OUT1 (PA4) as output. (#) DAC channel2 with DAC_OUT2 (PA5) as output. [..] Digital to Analog conversion can be non-triggered using DAC_Trigger_None and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register using DAC_SetChannel1Data()/DAC_SetChannel2Data. [..] Digital to Analog conversion can be triggered by: (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9. The used pin (GPIOx_Pin9) must be configured in input mode. (#) Timers TRGO: TIM2, TIM4, TIM6, TIM7 and TIM9 (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...). The timer TRGO event should be selected using TIM_SelectOutputTrigger() (#) Software using DAC_Trigger_Software. [..] Each DAC channel integrates an output buffer that can be used to reduce the output impedance, and to drive external loads directly without having to add an external operational amplifier. To enable, the output buffer use DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable; [..] Refer to the device datasheet for more details about output impedance value with and without output buffer. [..] Both DAC channels can be used to generate: (#) Noise wave using DAC_WaveGeneration_Noise (#) Triangle wave using DAC_WaveGeneration_Triangle [..] Wave generation can be disabled using DAC_WaveGeneration_None. [..] The DAC data format can be: (#) 8-bit right alignment using DAC_Align_8b_R (#) 12-bit left alignment using DAC_Align_12b_L (#) 12-bit right alignment using DAC_Align_12b_R [..] The analog output voltage on each DAC channel pin is determined by the following equation: DAC_OUTx = VREF+ * DOR / 4095 with DOR is the Data Output Register. VEF+ is the input voltage reference (refer to the device datasheet) e.g. To set DAC_OUT1 to 0.7V, use DAC_SetChannel1Data(DAC_Align_12b_R, 868); Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V. [..] A DMA1 request can be generated when an external trigger (but not a software trigger) occurs if DMA1 requests are enabled using DAC_DMACmd() [..] DMA1 requests are mapped as following: (#) DAC channel1 is mapped on DMA1 channel3 which must be already configured. (#) DAC channel2 is mapped on DMA1 channel4 which must be already configured. ##### How to use this driver ##### =============================================================================== [..] (+) DAC APB clock must be enabled to get write access to DAC registers using RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE) (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode. (+) Configure the DAC channel using DAC_Init() (+) Enable the DAC channel using DAC_Cmd() @endverbatim * ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx_dac.h" #include "stm32l1xx_rcc.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @defgroup DAC * @brief DAC driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* CR register Mask */ #define CR_CLEAR_MASK ((uint32_t)0x00000FFE) /* DAC Dual Channels SWTRIG masks */ #define DUAL_SWTRIG_SET ((uint32_t)0x00000003) #define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC) /* DHR registers offsets */ #define DHR12R1_OFFSET ((uint32_t)0x00000008) #define DHR12R2_OFFSET ((uint32_t)0x00000014) #define DHR12RD_OFFSET ((uint32_t)0x00000020) /* DOR register offset */ #define DOR_OFFSET ((uint32_t)0x0000002C) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup DAC_Private_Functions * @{ */ /** @defgroup DAC_Group1 DAC channels configuration * @brief DAC channels configuration: trigger, output buffer, data format. * @verbatim =============================================================================== ##### DAC channels configuration: trigger, output buffer, data format ##### =============================================================================== @endverbatim * @{ */ /** * @brief Deinitializes the DAC peripheral registers to their default reset values. * @param None * @retval None */ void DAC_DeInit(void) { /* Enable DAC reset state */ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); /* Release DAC from reset state */ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); } /** * @brief Initializes the DAC peripheral according to the specified * parameters in the DAC_InitStruct. * @param DAC_Channel: the selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected. * @arg DAC_Channel_2: DAC Channel2 selected. * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that * contains the configuration information for the specified DAC channel. * @retval None */ void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) { uint32_t tmpreg1 = 0, tmpreg2 = 0; /* Check the DAC parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); /*---------------------------- DAC CR Configuration --------------------------*/ /* Get the DAC CR value */ tmpreg1 = DAC->CR; /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel); /* Configure for the selected DAC channel: buffer output, trigger, wave generation, mask/amplitude for wave generation */ /* Set TSELx and TENx bits according to DAC_Trigger value */ /* Set WAVEx bits according to DAC_WaveGeneration value */ /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ /* Set BOFFx bit according to DAC_OutputBuffer value */ tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer); /* Calculate CR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << DAC_Channel; /* Write to DAC CR */ DAC->CR = tmpreg1; } /** * @brief Fills each DAC_InitStruct member with its default value. * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will * be initialized. * @retval None */ void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) { /*--------------- Reset DAC init structure parameters values -----------------*/ /* Initialize the DAC_Trigger member */ DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; /* Initialize the DAC_WaveGeneration member */ DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; /* Initialize the DAC_OutputBuffer member */ DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; } /** * @brief Enables or disables the specified DAC channel. * @param DAC_Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @param NewState: new state of the DAC channel. * This parameter can be: ENABLE or DISABLE. * @note When the DAC channel is enabled the trigger source can no more * be modified. * @retval None */ void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected DAC channel */ DAC->CR |= (DAC_CR_EN1 << DAC_Channel); } else { /* Disable the selected DAC channel */ DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel)); } } /** * @brief Enables or disables the selected DAC channel software trigger. * @param DAC_Channel: the selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @param NewState: new state of the selected DAC channel software trigger. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable software trigger for the selected DAC channel */ DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4); } else { /* Disable software trigger for the selected DAC channel */ DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4)); } } /** * @brief Enables or disables simultaneously the two DAC channels software * triggers. * @param NewState: new state of the DAC channels software triggers. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable software trigger for both DAC channels */ DAC->SWTRIGR |= DUAL_SWTRIG_SET; } else { /* Disable software trigger for both DAC channels */ DAC->SWTRIGR &= DUAL_SWTRIG_RESET; } } /** * @brief Enables or disables the selected DAC channel wave generation. * @param DAC_Channel: the selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @param DAC_Wave: Specifies the wave type to enable or disable. * This parameter can be one of the following values: * @arg DAC_Wave_Noise: noise wave generation * @arg DAC_Wave_Triangle: triangle wave generation * @param NewState: new state of the selected DAC channel wave generation. * This parameter can be: ENABLE or DISABLE. * @note * @retval None */ void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_DAC_WAVE(DAC_Wave)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected wave generation for the selected DAC channel */ DAC->CR |= DAC_Wave << DAC_Channel; } else { /* Disable the selected wave generation for the selected DAC channel */ DAC->CR &= ~(DAC_Wave << DAC_Channel); } } /** * @brief Set the specified data holding register value for DAC channel1. * @param DAC_Align: Specifies the data alignment for DAC channel1. * This parameter can be one of the following values: * @arg DAC_Align_8b_R: 8bit right data alignment selected * @arg DAC_Align_12b_L: 12bit left data alignment selected * @arg DAC_Align_12b_R: 12bit right data alignment selected * @param Data : Data to be loaded in the selected data holding register. * @retval None */ void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) { __IO uint32_t tmp = 0; /* Check the parameters */ assert_param(IS_DAC_ALIGN(DAC_Align)); assert_param(IS_DAC_DATA(Data)); tmp = (uint32_t)DAC_BASE; tmp += DHR12R1_OFFSET + DAC_Align; /* Set the DAC channel1 selected data holding register */ *(__IO uint32_t *) tmp = Data; } /** * @brief Set the specified data holding register value for DAC channel2. * @param DAC_Align: Specifies the data alignment for DAC channel2. * This parameter can be one of the following values: * @arg DAC_Align_8b_R: 8bit right data alignment selected * @arg DAC_Align_12b_L: 12bit left data alignment selected * @arg DAC_Align_12b_R: 12bit right data alignment selected * @param Data : Data to be loaded in the selected data holding register. * @retval None */ void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) { __IO uint32_t tmp = 0; /* Check the parameters */ assert_param(IS_DAC_ALIGN(DAC_Align)); assert_param(IS_DAC_DATA(Data)); tmp = (uint32_t)DAC_BASE; tmp += DHR12R2_OFFSET + DAC_Align; /* Set the DAC channel2 selected data holding register */ *(__IO uint32_t *)tmp = Data; } /** * @brief Set the specified data holding register value for dual channel DAC. * @param DAC_Align: Specifies the data alignment for dual channel DAC. * This parameter can be one of the following values: * @arg DAC_Align_8b_R: 8bit right data alignment selected * @arg DAC_Align_12b_L: 12bit left data alignment selected * @arg DAC_Align_12b_R: 12bit right data alignment selected * @param Data2: Data for DAC Channel2 to be loaded in the selected data * holding register. * @param Data1: Data for DAC Channel1 to be loaded in the selected data * holding register. * @note In dual mode, a unique register access is required to write in both * DAC channels at the same time. * @retval None */ void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) { uint32_t data = 0, tmp = 0; /* Check the parameters */ assert_param(IS_DAC_ALIGN(DAC_Align)); assert_param(IS_DAC_DATA(Data1)); assert_param(IS_DAC_DATA(Data2)); /* Calculate and set dual DAC data holding register value */ if (DAC_Align == DAC_Align_8b_R) { data = ((uint32_t)Data2 << 8) | Data1; } else { data = ((uint32_t)Data2 << 16) | Data1; } tmp = (uint32_t)DAC_BASE; tmp += DHR12RD_OFFSET + DAC_Align; /* Set the dual DAC selected data holding register */ *(__IO uint32_t *)tmp = data; } /** * @brief Returns the last data output value of the selected DAC channel. * @param DAC_Channel: the selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @retval The selected DAC channel data output value. */ uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) { __IO uint32_t tmp = 0; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); tmp = (uint32_t) DAC_BASE ; tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); /* Returns the DAC channel data output register value */ return (uint16_t) (*(__IO uint32_t*) tmp); } /** * @} */ /** @defgroup DAC_Group2 DMA management functions * @brief DMA management functions * @verbatim =============================================================================== ##### DMA management functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables the specified DAC channel DMA request. * When enabled DMA1 is generated when an external trigger (EXTI Line9, * TIM2, TIM4, TIM6, TIM7 or TIM9 but not a software trigger) occurs. * @param DAC_Channel: the selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @param NewState: new state of the selected DAC channel DMA request. * This parameter can be: ENABLE or DISABLE. * @note The DAC channel1 (channel2) is mapped on DMA1 channel3 (channel4) which * must be already configured. * @retval None */ void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected DAC channel DMA request */ DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel); } else { /* Disable the selected DAC channel DMA request */ DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel)); } } /** * @} */ /** @defgroup DAC_Group3 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== ##### Interrupts and flags management functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables the specified DAC interrupts. * @param DAC_Channel: the selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. * This parameter can be the following value: * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask * @note The DMA underrun occurs when a second external trigger arrives before * the acknowledgement for the first external trigger is received (first request). * @param NewState: new state of the specified DAC interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_FUNCTIONAL_STATE(NewState)); assert_param(IS_DAC_IT(DAC_IT)); if (NewState != DISABLE) { /* Enable the selected DAC interrupts */ DAC->CR |= (DAC_IT << DAC_Channel); } else { /* Disable the selected DAC interrupts */ DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel)); } } /** * @brief Checks whether the specified DAC flag is set or not. * @param DAC_Channel: thee selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @param DAC_FLAG: specifies the flag to check. * This parameter can be only of the following value: * @arg DAC_FLAG_DMAUDR: DMA underrun flag * @note The DMA underrun occurs when a second external trigger arrives before * the acknowledgement for the first external trigger is received (first request). * @retval The new state of DAC_FLAG (SET or RESET). */ FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_DAC_FLAG(DAC_FLAG)); /* Check the status of the specified DAC flag */ if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET) { /* DAC_FLAG is set */ bitstatus = SET; } else { /* DAC_FLAG is reset */ bitstatus = RESET; } /* Return the DAC_FLAG status */ return bitstatus; } /** * @brief Clears the DAC channel's pending flags. * @param DAC_Channel: the selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @param DAC_FLAG: specifies the flag to clear. * This parameter can be the following value: * @arg DAC_FLAG_DMAUDR: DMA underrun flag * @retval None */ void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_DAC_FLAG(DAC_FLAG)); /* Clear the selected DAC flags */ DAC->SR = (DAC_FLAG << DAC_Channel); } /** * @brief Checks whether the specified DAC interrupt has occurred or not. * @param DAC_Channel: the selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @param DAC_IT: specifies the DAC interrupt source to check. * This parameter can be the following values: * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask * @note The DMA underrun occurs when a second external trigger arrives before * the acknowledgement for the first external trigger is received (first request). * @retval The new state of DAC_IT (SET or RESET). */ ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT) { ITStatus bitstatus = RESET; uint32_t enablestatus = 0; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_DAC_IT(DAC_IT)); /* Get the DAC_IT enable bit status */ enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ; /* Check the status of the specified DAC interrupt */ if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus) { /* DAC_IT is set */ bitstatus = SET; } else { /* DAC_IT is reset */ bitstatus = RESET; } /* Return the DAC_IT status */ return bitstatus; } /** * @brief Clears the DAC channel's interrupt pending bits. * @param DAC_Channel: the selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @param DAC_IT: specifies the DAC interrupt pending bit to clear. * This parameter can be the following values: * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask * @retval None */ void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_DAC_IT(DAC_IT)); /* Clear the selected DAC interrupt pending bits */ DAC->SR = (DAC_IT << DAC_Channel); } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/src/stm32l1xx_dbgmcu.c
New file @@ -0,0 +1,181 @@ /** ****************************************************************************** * @file stm32l1xx_dbgmcu.c * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file provides all the DBGMCU firmware functions. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx_dbgmcu.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @defgroup DBGMCU * @brief DBGMCU driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup DBGMCU_Private_Functions * @{ */ /** * @brief Returns the device revision identifier. * @param None * @retval Device revision identifier */ uint32_t DBGMCU_GetREVID(void) { return(DBGMCU->IDCODE >> 16); } /** * @brief Returns the device identifier. * @param None * @retval Device identifier */ uint32_t DBGMCU_GetDEVID(void) { return(DBGMCU->IDCODE & IDCODE_DEVID_MASK); } /** * @brief Configures low power mode behavior when the MCU is in Debug mode. * @param DBGMCU_Periph: specifies the low power mode. * This parameter can be any combination of the following values: * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode * @arg DBGMCU_STOP: Keep debugger connection during STOP mode * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode * @param NewState: new state of the specified low power mode in Debug mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { DBGMCU->CR |= DBGMCU_Periph; } else { DBGMCU->CR &= ~DBGMCU_Periph; } } /** * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode. * @param DBGMCU_Periph: specifies the APB1 peripheral. * This parameter can be any combination of the following values: * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted * @arg DBGMCU_RTC_STOP: * + On STM32L1xx Medium-density devices: RTC Wakeup counter stopped when * Core is halted. * + On STM32L1xx High-density and Medium-density Plus devices: RTC Calendar * and Wakeup counter stopped when Core is halted. * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is * halted * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is * halted * @param NewState: new state of the specified APB1 peripheral in Debug mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { DBGMCU->APB1FZ |= DBGMCU_Periph; } else { DBGMCU->APB1FZ &= ~DBGMCU_Periph; } } /** * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode. * @param DBGMCU_Periph: specifies the APB2 peripheral. * This parameter can be any combination of the following values: * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted * @param NewState: new state of the specified APB2 peripheral in Debug mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { DBGMCU->APB2FZ |= DBGMCU_Periph; } else { DBGMCU->APB2FZ &= ~DBGMCU_Periph; } } /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/src/stm32l1xx_dma.c
New file @@ -0,0 +1,866 @@ /** ****************************************************************************** * @file stm32l1xx_dma.c * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file provides firmware functions to manage the following * functionalities of the Direct Memory Access controller (DMA): * + Initialization and Configuration * + Data Counter * + Interrupts and flags management * * @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] (#) Enable The DMA controller clock using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE) function for DMA1 or using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE) function for DMA2. (#) Enable and configure the peripheral to be connected to the DMA channel (except for internal SRAM / FLASH memories: no initialization is necessary). (#) For a given Channel, program the Source and Destination addresses, the transfer Direction, the Buffer Size, the Peripheral and Memory Incrementation mode and Data Size, the Circular or Normal mode, the channel transfer Priority and the Memory-to-Memory transfer mode (if needed) using the DMA_Init() function. (#) Enable the NVIC and the corresponding interrupt(s) using the function DMA_ITConfig() if you need to use DMA interrupts. (#) Enable the DMA channel using the DMA_Cmd() function. (#) Activate the needed channel Request using PPP_DMACmd() function for any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...) The function allowing this operation is provided in each PPP peripheral driver (ie. SPI_DMACmd for SPI peripheral). (#) Optionally, you can configure the number of data to be transferred when the channel is disabled (ie. after each Transfer Complete event or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter(). And you can get the number of remaining data to be transferred using the function DMA_GetCurrDataCounter() at run time (when the DMA channel is enabled and running). (#) To control DMA events you can use one of the following two methods: (##) Check on DMA channel flags using the function DMA_GetFlagStatus(). (##) Use DMA interrupts through the function DMA_ITConfig() at initialization phase and DMA_GetITStatus() function into interrupt routines in communication phase. After checking on a flag you should clear it using DMA_ClearFlag() function. And after checking on an interrupt event you should clear it using DMA_ClearITPendingBit() function. @endverbatim ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx_dma.h" #include "stm32l1xx_rcc.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @defgroup DMA * @brief DMA driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* DMA1 Channelx interrupt pending bit masks */ #define DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) #define DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) #define DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) #define DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) #define DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) #define DMA1_CHANNEL6_IT_MASK ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6)) #define DMA1_CHANNEL7_IT_MASK ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7)) /* DMA2 Channelx interrupt pending bit masks */ #define DMA2_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) #define DMA2_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) #define DMA2_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) #define DMA2_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) #define DMA2_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) /* DMA FLAG mask */ #define FLAG_MASK ((uint32_t)0x10000000) /* DMA registers Masks */ #define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup DMA_Private_Functions * @{ */ /** @defgroup DMA_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and Configuration functions ##### =============================================================================== [..] This subsection provides functions allowing to initialize the DMA channel source and destination addresses, incrementation and data sizes, transfer direction, buffer size, circular/normal mode selection, memory-to-memory mode selection and channel priority value. [..] The DMA_Init() function follows the DMA configuration procedures as described in reference manual (RM0038). @endverbatim * @{ */ /** * @brief Deinitializes the DMAy Channelx registers to their default reset * values. * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. * @retval None */ void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx) { /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); /* Disable the selected DMAy Channelx */ DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); /* Reset DMAy Channelx control register */ DMAy_Channelx->CCR = 0; /* Reset DMAy Channelx remaining bytes register */ DMAy_Channelx->CNDTR = 0; /* Reset DMAy Channelx peripheral address register */ DMAy_Channelx->CPAR = 0; /* Reset DMAy Channelx memory address register */ DMAy_Channelx->CMAR = 0; if (DMAy_Channelx == DMA1_Channel1) { /* Reset interrupt pending bits for DMA1 Channel1 */ DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK; } else if (DMAy_Channelx == DMA1_Channel2) { /* Reset interrupt pending bits for DMA1 Channel2 */ DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK; } else if (DMAy_Channelx == DMA1_Channel3) { /* Reset interrupt pending bits for DMA1 Channel3 */ DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK; } else if (DMAy_Channelx == DMA1_Channel4) { /* Reset interrupt pending bits for DMA1 Channel4 */ DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK; } else if (DMAy_Channelx == DMA1_Channel5) { /* Reset interrupt pending bits for DMA1 Channel5 */ DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK; } else if (DMAy_Channelx == DMA1_Channel6) { /* Reset interrupt pending bits for DMA1 Channel6 */ DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK; } else if (DMAy_Channelx == DMA1_Channel7) { /* Reset interrupt pending bits for DMA1 Channel7 */ DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK; } else if (DMAy_Channelx == DMA2_Channel1) { /* Reset interrupt pending bits for DMA2 Channel1 */ DMA2->IFCR |= DMA2_CHANNEL1_IT_MASK; } else if (DMAy_Channelx == DMA2_Channel2) { /* Reset interrupt pending bits for DMA2 Channel2 */ DMA2->IFCR |= DMA2_CHANNEL2_IT_MASK; } else if (DMAy_Channelx == DMA2_Channel3) { /* Reset interrupt pending bits for DMA2 Channel3 */ DMA2->IFCR |= DMA2_CHANNEL3_IT_MASK; } else if (DMAy_Channelx == DMA2_Channel4) { /* Reset interrupt pending bits for DMA2 Channel4 */ DMA2->IFCR |= DMA2_CHANNEL4_IT_MASK; } else { if (DMAy_Channelx == DMA2_Channel5) { /* Reset interrupt pending bits for DMA2 Channel5 */ DMA2->IFCR |= DMA2_CHANNEL5_IT_MASK; } } } /** * @brief Initializes the DMAy Channelx according to the specified * parameters in the DMA_InitStruct. * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that * contains the configuration information for the specified DMA Channel. * @retval None */ void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR)); assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); /*--------------------------- DMAy Channelx CCR Configuration -----------------*/ /* Get the DMAy_Channelx CCR value */ tmpreg = DMAy_Channelx->CCR; /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ tmpreg &= CCR_CLEAR_MASK; /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ /* Set DIR bit according to DMA_DIR value */ /* Set CIRC bit according to DMA_Mode value */ /* Set PINC bit according to DMA_PeripheralInc value */ /* Set MINC bit according to DMA_MemoryInc value */ /* Set PSIZE bits according to DMA_PeripheralDataSize value */ /* Set MSIZE bits according to DMA_MemoryDataSize value */ /* Set PL bits according to DMA_Priority value */ /* Set the MEM2MEM bit according to DMA_M2M value */ tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; /* Write to DMAy Channelx CCR */ DMAy_Channelx->CCR = tmpreg; /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ /* Write to DMAy Channelx CNDTR */ DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; /*--------------------------- DMAy Channelx CPAR Configuration ----------------*/ /* Write to DMAy Channelx CPAR */ DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; /*--------------------------- DMAy Channelx CMAR Configuration ----------------*/ /* Write to DMAy Channelx CMAR */ DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; } /** * @brief Fills each DMA_InitStruct member with its default value. * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will * be initialized. * @retval None */ void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) { /*-------------- Reset DMA init structure parameters values ------------------*/ /* Initialize the DMA_PeripheralBaseAddr member */ DMA_InitStruct->DMA_PeripheralBaseAddr = 0; /* Initialize the DMA_MemoryBaseAddr member */ DMA_InitStruct->DMA_MemoryBaseAddr = 0; /* Initialize the DMA_DIR member */ DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; /* Initialize the DMA_BufferSize member */ DMA_InitStruct->DMA_BufferSize = 0; /* Initialize the DMA_PeripheralInc member */ DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; /* Initialize the DMA_MemoryInc member */ DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; /* Initialize the DMA_PeripheralDataSize member */ DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; /* Initialize the DMA_MemoryDataSize member */ DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; /* Initialize the DMA_Mode member */ DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; /* Initialize the DMA_Priority member */ DMA_InitStruct->DMA_Priority = DMA_Priority_Low; /* Initialize the DMA_M2M member */ DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; } /** * @brief Enables or disables the specified DMAy Channelx. * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. * @param NewState: new state of the DMAy Channelx. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected DMAy Channelx */ DMAy_Channelx->CCR |= DMA_CCR1_EN; } else { /* Disable the selected DMAy Channelx */ DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); } } /** * @} */ /** @defgroup DMA_Group2 Data Counter functions * @brief Data Counter functions * @verbatim =============================================================================== ##### Data Counter functions ##### =============================================================================== [..] This subsection provides function allowing to configure and read the buffer size (number of data to be transferred).The DMA data counter can be written only when the DMA channel is disabled (ie. after transfer complete event). [..] The following function can be used to write the Channel data counter value: (+) void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber). -@- It is advised to use this function rather than DMA_Init() in situations where only the Data buffer needs to be reloaded. [..] The DMA data counter can be read to indicate the number of remaining transfers for the relative DMA channel. This counter is decremented at the end of each data transfer and when the transfer is complete: (+) If Normal mode is selected: the counter is set to 0. (+) If Circular mode is selected: the counter is reloaded with the initial value(configured before enabling the DMA channel). [..] The following function can be used to read the Channel data counter value: (+) uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx). @endverbatim * @{ */ /** * @brief Sets the number of data units in the current DMAy Channelx transfer. * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. * @param DataNumber: The number of data units in the current DMAy Channelx * transfer. * @note This function can only be used when the DMAy_Channelx is disabled. * @retval None. */ void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber) { /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ /* Write to DMAy Channelx CNDTR */ DMAy_Channelx->CNDTR = DataNumber; } /** * @brief Returns the number of remaining data units in the current * DMAy Channelx transfer. * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. * @retval The number of remaining data units in the current DMAy Channelx * transfer. */ uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) { /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); /* Return the number of remaining data units for DMAy Channelx */ return ((uint16_t)(DMAy_Channelx->CNDTR)); } /** * @} */ /** @defgroup DMA_Group3 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== ##### Interrupts and flags management functions ##### =============================================================================== [..] This subsection provides functions allowing to configure the DMA Interrupts sources and check or clear the flags or pending bits status. The user should identify which mode will be used in his application to manage the DMA controller events: Polling mode or Interrupt mode. *** Polling Mode *** ==================== [..] Each DMA channel can be managed through 4 event Flags:(y : DMA Controller number x : DMA channel number ). (#) DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred. (#) DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occurred. (#) DMAy_FLAG_TEx : to indicate that a Transfer Error occurred. (#) DMAy_FLAG_GLx : to indicate that at least one of the events described above occurred. -@- Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx). [..]In this Mode it is advised to use the following functions: (+) FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG); (+) void DMA_ClearFlag(uint32_t DMA_FLAG); *** Interrupt Mode *** ====================== [..] Each DMA channel can be managed through 4 Interrupts: (+) Interrupt Source (##) DMA_IT_TC: specifies the interrupt source for the Transfer Complete event. (##) DMA_IT_HT : specifies the interrupt source for the Half-transfer Complete event. (##) DMA_IT_TE : specifies the interrupt source for the transfer errors event. (##) DMA_IT_GL : to indicate that at least one of the interrupts described above occurred. -@@- Clearing DMA_IT_GL interrupt results in clearing all other interrupts of the same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE). [..]In this Mode it is advised to use the following functions: (+) void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); (+) ITStatus DMA_GetITStatus(uint32_t DMA_IT); (+) void DMA_ClearITPendingBit(uint32_t DMA_IT); @endverbatim * @{ */ /** * @brief Enables or disables the specified DMAy Channelx interrupts. * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. * @param DMA_IT: specifies the DMA interrupts sources to be enabled * or disabled. * This parameter can be any combination of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer interrupt mask * @arg DMA_IT_TE: Transfer error interrupt mask * @param NewState: new state of the specified DMA interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); assert_param(IS_DMA_CONFIG_IT(DMA_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected DMA interrupts */ DMAy_Channelx->CCR |= DMA_IT; } else { /* Disable the selected DMA interrupts */ DMAy_Channelx->CCR &= ~DMA_IT; } } /** * @brief Checks whether the specified DMAy Channelx flag is set or not. * @param DMAy_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. * * @note * The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags * relative to the same channel is set (Transfer Complete, Half-transfer * Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or * DMAy_FLAG_TEx). * * @retval The new state of DMAy_FLAG (SET or RESET). */ FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) { FlagStatus bitstatus = RESET; uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_DMA_GET_FLAG(DMAy_FLAG)); /* Calculate the used DMAy */ if ((DMAy_FLAG & FLAG_MASK) == (uint32_t)RESET) { /* Get DMA1 ISR register value */ tmpreg = DMA1->ISR; } else { /* Get DMA2 ISR register value */ tmpreg = DMA2->ISR; } /* Check the status of the specified DMAy flag */ if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET) { /* DMAy_FLAG is set */ bitstatus = SET; } else { /* DMAy_FLAG is reset */ bitstatus = RESET; } /* Return the DMAy_FLAG status */ return bitstatus; } /** * @brief Clears the DMAy Channelx's pending flags. * @param DMAy_FLAG: specifies the flag to clear. * This parameter can be any combination (for the same DMA) of the following values: * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. * * @note * Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags * relative to the same channel (Transfer Complete, Half-transfer Complete and * Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx). * * @retval None */ void DMA_ClearFlag(uint32_t DMAy_FLAG) { /* Check the parameters */ assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG)); if ((DMAy_FLAG & FLAG_MASK) == (uint32_t)RESET) { /* Clear the selected DMAy flags */ DMA1->IFCR = DMAy_FLAG; } else { /* Clear the selected DMAy flags */ DMA2->IFCR = DMAy_FLAG; } } /** * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not. * @param DMAy_IT: specifies the DMAy interrupt source to check. * This parameter can be one of the following values: * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. * * @note * The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other * interrupts relative to the same channel is set (Transfer Complete, * Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx, * DMAy_IT_HTx or DMAy_IT_TEx). * * @retval The new state of DMAy_IT (SET or RESET). */ ITStatus DMA_GetITStatus(uint32_t DMAy_IT) { ITStatus bitstatus = RESET; uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_DMA_GET_IT(DMAy_IT)); /* Calculate the used DMAy */ if ((DMAy_IT & FLAG_MASK) == (uint32_t)RESET) { /* Get DMA1 ISR register value */ tmpreg = DMA1->ISR; } else { /* Get DMA2 ISR register value */ tmpreg = DMA2->ISR; } /* Check the status of the specified DMAy interrupt */ if ((tmpreg & DMAy_IT) != (uint32_t)RESET) { /* DMAy_IT is set */ bitstatus = SET; } else { /* DMAy_IT is reset */ bitstatus = RESET; } /* Return the DMAy_IT status */ return bitstatus; } /** * @brief Clears the DMAy Channelx's interrupt pending bits. * @param DMAy_IT: specifies the DMAy interrupt pending bit to clear. * This parameter can be any combination (for the same DMA) of the following values: * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. * * @note * Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other * interrupts relative to the same channel (Transfer Complete, Half-transfer * Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and * DMAy_IT_TEx). * * @retval None */ void DMA_ClearITPendingBit(uint32_t DMAy_IT) { /* Check the parameters */ assert_param(IS_DMA_CLEAR_IT(DMAy_IT)); /* Calculate the used DMAy */ if ((DMAy_IT & FLAG_MASK) == (uint32_t)RESET) { /* Clear the selected DMAy interrupt pending bits */ DMA1->IFCR = DMAy_IT; } else { /* Clear the selected DMAy interrupt pending bits */ DMA2->IFCR = DMAy_IT; } } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/src/stm32l1xx_exti.c
New file @@ -0,0 +1,315 @@ /** ****************************************************************************** * @file stm32l1xx_exti.c * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file provides firmware functions to manage the following * functionalities of the EXTI peripheral: * + Initialization and Configuration * + Interrupts and flags management * * @verbatim ============================================================================== ##### EXTI features ##### ============================================================================== [..] External interrupt/event lines are mapped as following: (#) All available GPIO pins are connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. (#) EXTI line 16 is connected to the PVD output. (#) EXTI line 17 is connected to the RTC Alarm event. (#) EXTI line 18 is connected to the USB Device FS wakeup event. (#) EXTI line 19 is connected to the RTC Tamper and TimeStamp events. (#) EXTI line 20 is connected to the RTC Wakeup event. (#) EXTI line 21 is connected to the Comparator 1 wakeup event. (#) EXTI line 22 is connected to the Comparator 2 wakeup event. (#) EXTI line 23 is connected to the Comparator channel acquisition wakeup event. ##### How to use this driver ##### ============================================================================== [..] In order to use an I/O pin as an external interrupt source, follow steps below: (#) Configure the I/O in input mode using GPIO_Init() (#) Select the input source pin for the EXTI line using SYSCFG_EXTILineConfig() (#) Select the mode(interrupt, event) and configure the trigger selection (Rising, falling or both) using EXTI_Init() (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init() [..] (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); * @endverbatim * ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx_exti.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @defgroup EXTI * @brief EXTI driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup EXTI_Private_Functions * @{ */ /** @defgroup EXTI_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * @verbatim ============================================================================== ##### Initialization and Configuration functions ##### ============================================================================== @endverbatim * @{ */ /** * @brief Deinitializes the EXTI peripheral registers to their default reset values. * @param None * @retval None */ void EXTI_DeInit(void) { EXTI->IMR = 0x00000000; EXTI->EMR = 0x00000000; EXTI->RTSR = 0x00000000; EXTI->FTSR = 0x00000000; EXTI->PR = 0x00FFFFFF; } /** * @brief Initializes the EXTI peripheral according to the specified * parameters in the EXTI_InitStruct. * EXTI_Line specifies the EXTI line (EXTI0....EXTI23). * EXTI_Mode specifies which EXTI line is used as interrupt or an event. * EXTI_Trigger selects the trigger. When the trigger occurs, interrupt * pending bit will be set. * EXTI_LineCmd controls (Enable/Disable) the EXTI line. * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure * that contains the configuration information for the EXTI peripheral. * @retval None */ void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) { uint32_t tmp = 0; /* Check the parameters */ assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); tmp = (uint32_t)EXTI_BASE; if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) { /* Clear EXTI line configuration */ EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; tmp += EXTI_InitStruct->EXTI_Mode; *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; /* Clear Rising Falling edge configuration */ EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; /* Select the trigger for the selected external interrupts */ if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) { /* Rising Falling edge */ EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; } else { tmp = (uint32_t)EXTI_BASE; tmp += EXTI_InitStruct->EXTI_Trigger; *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; } } else { tmp += EXTI_InitStruct->EXTI_Mode; /* Disable the selected external lines */ *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; } } /** * @brief Fills each EXTI_InitStruct member with its reset value. * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will * be initialized. * @retval None */ void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) { EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; EXTI_InitStruct->EXTI_LineCmd = DISABLE; } /** * @brief Generates a Software interrupt on selected EXTI line. * @param EXTI_Line: specifies the EXTI line on which the software interrupt * will be generated. * This parameter can be any combination of EXTI_Linex where x can be (0..23). * @retval None */ void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) { /* Check the parameters */ assert_param(IS_EXTI_LINE(EXTI_Line)); EXTI->SWIER |= EXTI_Line; } /** * @} */ /** @defgroup EXTI_Group2 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim ============================================================================== ##### Interrupts and flags management functions ##### ============================================================================== @endverbatim * @{ */ /** * @brief Checks whether the specified EXTI line flag is set or not. * @param EXTI_Line: specifies the EXTI line flag to check. * This parameter can be: * EXTI_Linex: External interrupt line x where x(0..23). * @retval The new state of EXTI_Line (SET or RESET). */ FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_GET_EXTI_LINE(EXTI_Line)); if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Clears the EXTI's line pending flags. * @param EXTI_Line: specifies the EXTI lines flags to clear. * This parameter can be any combination of EXTI_Linex where x can be (0..23). * @retval None */ void EXTI_ClearFlag(uint32_t EXTI_Line) { /* Check the parameters */ assert_param(IS_EXTI_LINE(EXTI_Line)); EXTI->PR = EXTI_Line; } /** * @brief Checks whether the specified EXTI line is asserted or not. * @param EXTI_Line: specifies the EXTI line to check. * This parameter can be: * EXTI_Linex: External interrupt line x where x(0..23). * @retval The new state of EXTI_Line (SET or RESET). */ ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_GET_EXTI_LINE(EXTI_Line)); if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Clears the EXTI's line pending bits. * @param EXTI_Line: specifies the EXTI lines to clear. * This parameter can be any combination of EXTI_Linex where x can be (0..23). * @retval None */ void EXTI_ClearITPendingBit(uint32_t EXTI_Line) { /* Check the parameters */ assert_param(IS_EXTI_LINE(EXTI_Line)); EXTI->PR = EXTI_Line; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/src/stm32l1xx_flash.c
New file @@ -0,0 +1,1932 @@ /** ****************************************************************************** * @file stm32l1xx_flash.c * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file provides all the Flash firmware functions. These functions * can be executed from Internal FLASH or Internal SRAM memories. * The functions that should be called from SRAM are defined inside * the "stm32l1xx_flash_ramfunc.c" file. * This file provides firmware functions to manage the following * functionalities of the FLASH peripheral: * + FLASH Interface configuration * + FLASH Memory Programming * + DATA EEPROM Programming * + Option Bytes Programming * + Interrupts and flags management * * @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] This driver provides functions to configure and program the Flash memory of all STM32L1xx devices. [..] These functions are split in 5 groups: (#) FLASH Interface configuration functions: this group includes the management of following features: (++) Set the latency. (++) Enable/Disable the prefetch buffer. (++) Enable/Disable the 64 bit Read Access. (++) Enable/Disable the RUN PowerDown mode. (++) Enable/Disable the SLEEP PowerDown mode. (#) FLASH Memory Programming functions: this group includes all needed functions to erase and program the main memory: (++) Lock and Unlock the Flash interface. (++) Erase function: Erase Page. (++) Program functions: Fast Word and Half Page(should be executed from internal SRAM). (#) DATA EEPROM Programming functions: this group includes all needed functions to erase and program the DATA EEPROM memory: (++) Lock and Unlock the DATA EEPROM interface. (++) Erase function: Erase Byte, erase HalfWord, erase Word, erase (++) Double Word (should be executed from internal SRAM). (++) Program functions: Fast Program Byte, Fast Program Half-Word, FastProgramWord, Program Byte, Program Half-Word, Program Word and Program Double-Word (should be executed from internal SRAM). (#) FLASH Option Bytes Programming functions: this group includes all needed functions to: (++) Lock and Unlock the Flash Option bytes. (++) Set/Reset the write protection. (++) Set the Read protection Level. (++) Set the BOR level. (++) rogram the user option Bytes. (++) Launch the Option Bytes loader. (++) Get the Write protection. (++) Get the read protection status. (++) Get the BOR level. (++) Get the user option bytes. (#) FLASH Interrupts and flag management functions: this group includes all needed functions to: (++) Enable/Disable the flash interrupt sources. (++) Get flags status. (++) Clear flags. (++) Get Flash operation status. (++) Wait for last flash operation. * @endverbatim * ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx_flash.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @defgroup FLASH * @brief FLASH driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* FLASH Mask */ #define WRP01_MASK ((uint32_t)0x0000FFFF) #define WRP23_MASK ((uint32_t)0xFFFF0000) #define WRP45_MASK ((uint32_t)0x0000FFFF) #define WRP67_MASK ((uint32_t)0xFFFF0000) #define WRP89_MASK ((uint32_t)0x0000FFFF) #define WRP1011_MASK ((uint32_t)0xFFFF0000) #define WRP1213_MASK ((uint32_t)0x0000FFFF) #define WRP1415_MASK ((uint32_t)0xFFFF0000) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup FLASH_Private_Functions * @{ */ /** @defgroup FLASH_Group1 FLASH Interface configuration functions * @brief FLASH Interface configuration functions * @verbatim ============================================================================== ##### FLASH Interface configuration functions ##### ============================================================================== [..] FLASH_Interface configuration_Functions, includes the following functions: (+) void FLASH_SetLatency(uint32_t FLASH_Latency): [..] To correctly read data from Flash memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. [..] ---------------------------------------------------------------- | Wait states | HCLK clock frequency (MHz) | | |------------------------------------------------| | (Latency) | voltage range | voltage range | | | 1.65 V - 3.6 V | 2.0 V - 3.6 V | | |----------------|---------------|---------------| | | VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V | |-------------- |----------------|---------------|---------------| |0WS(1CPU cycle)|0 < HCLK <= 2 |0 < HCLK <= 8 |0 < HCLK <= 16 | |---------------|----------------|---------------|---------------| |1WS(2CPU cycle)|2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32| ---------------------------------------------------------------- [..] (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState); (+) void FLASH_ReadAccess64Cmd(FunctionalState NewState); (+) void FLASH_RUNPowerDownCmd(FunctionalState NewState); (+) void FLASH_SLEEPPowerDownCmd(FunctionalState NewState); (+) void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); [..] Here below the allowed configuration of Latency, 64Bit access and prefetch buffer [..] -------------------------------------------------------------------------------- | | ACC64 = 0 | ACC64 = 1 | | Latency |----------------|---------------|---------------|---------------| | | PRFTEN = 0 | PRFTEN = 1 | PRFTEN = 0 | PRFTEN = 1 | |---------------|----------------|---------------|---------------|---------------| |0WS(1CPU cycle)| YES | NO | YES | YES | |---------------|----------------|---------------|---------------|---------------| |1WS(2CPU cycle)| NO | NO | YES | YES | -------------------------------------------------------------------------------- [..] All these functions don't need the unlock sequence. @endverbatim * @{ */ /** * @brief Sets the code latency value. * @param FLASH_Latency: specifies the FLASH Latency value. * This parameter can be one of the following values: * @arg FLASH_Latency_0: FLASH Zero Latency cycle. * @arg FLASH_Latency_1: FLASH One Latency cycle. * @retval None */ void FLASH_SetLatency(uint32_t FLASH_Latency) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_FLASH_LATENCY(FLASH_Latency)); /* Read the ACR register */ tmpreg = FLASH->ACR; /* Sets the Latency value */ tmpreg &= (uint32_t) (~((uint32_t)FLASH_ACR_LATENCY)); tmpreg |= FLASH_Latency; /* Write the ACR register */ FLASH->ACR = tmpreg; } /** * @brief Enables or disables the Prefetch Buffer. * @param NewState: new state of the FLASH prefetch buffer. * This parameter can be: ENABLE or DISABLE. * @retval None */ void FLASH_PrefetchBufferCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if(NewState != DISABLE) { FLASH->ACR |= FLASH_ACR_PRFTEN; } else { FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_PRFTEN)); } } /** * @brief Enables or disables read access to flash by 64 bits. * @param NewState: new state of the FLASH read access mode. * This parameter can be: ENABLE or DISABLE. * @note If this bit is set, the Read access 64 bit is used. * If this bit is reset, the Read access 32 bit is used. * @note This bit cannot be written at the same time as the LATENCY and * PRFTEN bits. * To reset this bit, the LATENCY should be zero wait state and the * prefetch off. * @retval None */ void FLASH_ReadAccess64Cmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if(NewState != DISABLE) { FLASH->ACR |= FLASH_ACR_ACC64; } else { FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_ACC64)); } } /** * @brief Enable or disable the power down mode during Sleep mode. * @note This function is used to power down the FLASH when the system is in SLEEP LP mode. * @param NewState: new state of the power down mode during sleep mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void FLASH_SLEEPPowerDownCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Set the SLEEP_PD bit to put Flash in power down mode during sleep mode */ FLASH->ACR |= FLASH_ACR_SLEEP_PD; } else { /* Clear the SLEEP_PD bit in to put Flash in idle mode during sleep mode */ FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_SLEEP_PD)); } } /** * @} */ /** @defgroup FLASH_Group2 FLASH Memory Programming functions * @brief FLASH Memory Programming functions * @verbatim ============================================================================== ##### FLASH Memory Programming functions ##### ============================================================================== [..] The FLASH Memory Programming functions, includes the following functions: (+) void FLASH_Unlock(void); (+) void FLASH_Lock(void); (+) FLASH_Status FLASH_ErasePage(uint32_t Page_Address); (+) FLASH_Status FLASH_FastProgramWord(uint32_t Address, uint32_t Data); [..] Any operation of erase or program should follow these steps: (#) Call the FLASH_Unlock() function to enable the flash control register and program memory access. (#) Call the desired function to erase page or program data. (#) Call the FLASH_Lock() to disable the flash program memory access (recommended to protect the FLASH memory against possible unwanted operation). @endverbatim * @{ */ /** * @brief Unlocks the FLASH control register and program memory access. * @param None * @retval None */ void FLASH_Unlock(void) { if((FLASH->PECR & FLASH_PECR_PRGLOCK) != RESET) { /* Unlocking the data memory and FLASH_PECR register access */ DATA_EEPROM_Unlock(); /* Unlocking the program memory access */ FLASH->PRGKEYR = FLASH_PRGKEY1; FLASH->PRGKEYR = FLASH_PRGKEY2; } } /** * @brief Locks the Program memory access. * @param None * @retval None */ void FLASH_Lock(void) { /* Set the PRGLOCK Bit to lock the program memory access */ FLASH->PECR |= FLASH_PECR_PRGLOCK; } /** * @brief Erases a specified page in program memory. * @note To correctly run this function, the FLASH_Unlock() function * must be called before. * Call the FLASH_Lock() to disable the flash memory access * (recommended to protect the FLASH memory against possible unwanted operation) * @param Page_Address: The page address in program memory to be erased. * @note A Page is erased in the Program memory only if the address to load * is the start address of a page (multiple of 256 bytes). * @retval FLASH Status: The returned value can be: * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status FLASH_ErasePage(uint32_t Page_Address) { FLASH_Status status = FLASH_COMPLETE; /* Check the parameters */ assert_param(IS_FLASH_PROGRAM_ADDRESS(Page_Address)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); if(status == FLASH_COMPLETE) { /* If the previous operation is completed, proceed to erase the page */ /* Set the ERASE bit */ FLASH->PECR |= FLASH_PECR_ERASE; /* Set PROG bit */ FLASH->PECR |= FLASH_PECR_PROG; /* Write 00000000h to the first word of the program page to erase */ *(__IO uint32_t *)Page_Address = 0x00000000; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); /* If the erase operation is completed, disable the ERASE and PROG bits */ FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG); FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE); } /* Return the Erase Status */ return status; } /** * @brief Programs a word at a specified address in program memory. * @note To correctly run this function, the FLASH_Unlock() function * must be called before. * Call the FLASH_Lock() to disable the flash memory access * (recommended to protect the FLASH memory against possible unwanted operation). * @param Address: specifies the address to be written. * @param Data: specifies the data to be written. * @retval FLASH Status: The returned value can be: * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status FLASH_FastProgramWord(uint32_t Address, uint32_t Data) { FLASH_Status status = FLASH_COMPLETE; /* Check the parameters */ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); if(status == FLASH_COMPLETE) { /* If the previous operation is completed, proceed to program the new word */ *(__IO uint32_t *)Address = Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); } /* Return the Write Status */ return status; } /** * @} */ /** @defgroup FLASH_Group3 DATA EEPROM Programming functions * @brief DATA EEPROM Programming functions * @verbatim =============================================================================== ##### DATA EEPROM Programming functions ##### =============================================================================== [..] The DATA_EEPROM Programming_Functions, includes the following functions: (+) void DATA_EEPROM_Unlock(void); (+) void DATA_EEPROM_Lock(void); (+) FLASH_Status DATA_EEPROM_EraseByte(uint32_t Address); (+) FLASH_Status DATA_EEPROM_EraseHalfWord(uint32_t Address); (+) FLASH_Status DATA_EEPROM_EraseWord(uint32_t Address); (+) FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data); (+) FLASH_Status DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data); (+) FLASH_Status DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data); (+) FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data); (+) FLASH_Status DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data); (+) FLASH_Status DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data); [..] Any operation of erase or program should follow these steps: (#) Call the DATA_EEPROM_Unlock() function to enable the data EEPROM access and Flash program erase control register access. (#) Call the desired function to erase or program data. (#) Call the DATA_EEPROM_Lock() to disable the data EEPROM access and Flash program erase control register access(recommended to protect the DATA_EEPROM against possible unwanted operation). @endverbatim * @{ */ /** * @brief Unlocks the data memory and FLASH_PECR register access. * @param None * @retval None */ void DATA_EEPROM_Unlock(void) { if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET) { /* Unlocking the Data memory and FLASH_PECR register access*/ FLASH->PEKEYR = FLASH_PEKEY1; FLASH->PEKEYR = FLASH_PEKEY2; } } /** * @brief Locks the Data memory and FLASH_PECR register access. * @param None * @retval None */ void DATA_EEPROM_Lock(void) { /* Set the PELOCK Bit to lock the data memory and FLASH_PECR register access */ FLASH->PECR |= FLASH_PECR_PELOCK; } /** * @brief Enables or disables DATA EEPROM fixed Time programming (2*Tprog). * @param NewState: new state of the DATA EEPROM fixed Time programming mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DATA_EEPROM_FixedTimeProgramCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if(NewState != DISABLE) { FLASH->PECR |= (uint32_t)FLASH_PECR_FTDW; } else { FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW)); } } /** * @brief Erase a byte in data memory. * @param Address: specifies the address to be erased. * @note This function can be used only for STM32L1XX_HD, STM32L1XX_MDP and * STM32L1XX_XL devices. * @note To correctly run this function, the DATA_EEPROM_Unlock() function * must be called before. * Call the DATA_EEPROM_Lock() to disable the data EEPROM access * and Flash program erase control register access(recommended to protect * the DATA_EEPROM against possible unwanted operation). * @retval FLASH Status: The returned value can be: * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status DATA_EEPROM_EraseByte(uint32_t Address) { FLASH_Status status = FLASH_COMPLETE; /* Check the parameters */ assert_param(IS_FLASH_DATA_ADDRESS(Address)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); if(status == FLASH_COMPLETE) { /* Write "00h" to valid address in the data memory" */ *(__IO uint8_t *) Address = (uint8_t)0x00; } /* Return the erase status */ return status; } /** * @brief Erase a halfword in data memory. * @param Address: specifies the address to be erased. * @note This function can be used only for STM32L1XX_HD, STM32L1XX_MDP and * STM32L1XX_XL devices. * @note To correctly run this function, the DATA_EEPROM_Unlock() function * must be called before. * Call the DATA_EEPROM_Lock() to disable the data EEPROM access * and Flash program erase control register access(recommended to protect * the DATA_EEPROM against possible unwanted operation). * @retval FLASH Status: The returned value can be: * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status DATA_EEPROM_EraseHalfWord(uint32_t Address) { FLASH_Status status = FLASH_COMPLETE; /* Check the parameters */ assert_param(IS_FLASH_DATA_ADDRESS(Address)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); if(status == FLASH_COMPLETE) { /* Write "0000h" to valid address in the data memory" */ *(__IO uint16_t *) Address = (uint16_t)0x0000; } /* Return the erase status */ return status; } /** * @brief Erase a word in data memory. * @param Address: specifies the address to be erased. * @note For STM32L1XX_MD, A data memory word is erased in the data memory only * if the address to load is the start address of a word (multiple of a word). * @note To correctly run this function, the DATA_EEPROM_Unlock() function * must be called before. * Call the DATA_EEPROM_Lock() to disable the data EEPROM access * and Flash program erase control register access(recommended to protect * the DATA_EEPROM against possible unwanted operation). * @retval FLASH Status: The returned value can be: * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status DATA_EEPROM_EraseWord(uint32_t Address) { FLASH_Status status = FLASH_COMPLETE; /* Check the parameters */ assert_param(IS_FLASH_DATA_ADDRESS(Address)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); if(status == FLASH_COMPLETE) { /* Write "00000000h" to valid address in the data memory" */ *(__IO uint32_t *) Address = 0x00000000; } /* Return the erase status */ return status; } /** * @brief Write a Byte at a specified address in data memory. * @note To correctly run this function, the DATA_EEPROM_Unlock() function * must be called before. * Call the DATA_EEPROM_Lock() to disable the data EEPROM access * and Flash program erase control register access(recommended to protect * the DATA_EEPROM against possible unwanted operation). * @param Address: specifies the address to be written. * @param Data: specifies the data to be written. * @note This function assumes that the is data word is already erased. * @retval FLASH Status: The returned value can be: * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data) { FLASH_Status status = FLASH_COMPLETE; #if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_XL) uint32_t tmp = 0, tmpaddr = 0; #endif /* Check the parameters */ assert_param(IS_FLASH_DATA_ADDRESS(Address)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); if(status == FLASH_COMPLETE) { /* Clear the FTDW bit */ FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW)); #if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_XL) if(Data != (uint8_t)0x00) { /* If the previous operation is completed, proceed to write the new Data */ *(__IO uint8_t *)Address = Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); } else { tmpaddr = Address & 0xFFFFFFFC; tmp = * (__IO uint32_t *) tmpaddr; tmpaddr = 0xFF << ((uint32_t) (0x8 * (Address & 0x3))); tmp &= ~tmpaddr; status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC); status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp); } #elif defined (STM32L1XX_HD) || defined (STM32L1XX_MDP) || defined (STM32L1XX_XL) /* If the previous operation is completed, proceed to write the new Data */ *(__IO uint8_t *)Address = Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); #endif } /* Return the Write Status */ return status; } /** * @brief Writes a half word at a specified address in data memory. * @note To correctly run this function, the DATA_EEPROM_Unlock() function * must be called before. * Call the DATA_EEPROM_Lock() to disable the data EEPROM access * and Flash program erase control register access(recommended to protect * the DATA_EEPROM against possible unwanted operation). * @param Address: specifies the address to be written. * @param Data: specifies the data to be written. * @note This function assumes that the is data word is already erased. * @retval FLASH Status: The returned value can be: * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data) { FLASH_Status status = FLASH_COMPLETE; #if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_XL) uint32_t tmp = 0, tmpaddr = 0; #endif /* Check the parameters */ assert_param(IS_FLASH_DATA_ADDRESS(Address)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); if(status == FLASH_COMPLETE) { /* Clear the FTDW bit */ FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW)); #if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_XL) if(Data != (uint16_t)0x0000) { /* If the previous operation is completed, proceed to write the new data */ *(__IO uint16_t *)Address = Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); } else { if((Address & 0x3) != 0x3) { tmpaddr = Address & 0xFFFFFFFC; tmp = * (__IO uint32_t *) tmpaddr; tmpaddr = 0xFFFF << ((uint32_t) (0x8 * (Address & 0x3))); tmp &= ~tmpaddr; status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC); status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp); } else { DATA_EEPROM_FastProgramByte(Address, 0x00); DATA_EEPROM_FastProgramByte(Address + 1, 0x00); } } #elif defined (STM32L1XX_HD) || defined (STM32L1XX_MDP) || defined (STM32L1XX_XL) /* If the previous operation is completed, proceed to write the new data */ *(__IO uint16_t *)Address = Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); #endif } /* Return the Write Status */ return status; } /** * @brief Programs a word at a specified address in data memory. * @note To correctly run this function, the DATA_EEPROM_Unlock() function * must be called before. * Call the DATA_EEPROM_Lock() to disable the data EEPROM access * and Flash program erase control register access(recommended to protect * the DATA_EEPROM against possible unwanted operation). * @param Address: specifies the address to be written. * @param Data: specifies the data to be written. * @note This function assumes that the is data word is already erased. * @retval FLASH Status: The returned value can be: * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data) { FLASH_Status status = FLASH_COMPLETE; /* Check the parameters */ assert_param(IS_FLASH_DATA_ADDRESS(Address)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); if(status == FLASH_COMPLETE) { /* Clear the FTDW bit */ FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW)); /* If the previous operation is completed, proceed to program the new data */ *(__IO uint32_t *)Address = Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); } /* Return the Write Status */ return status; } /** * @brief Write a Byte at a specified address in data memory without erase. * @note To correctly run this function, the DATA_EEPROM_Unlock() function * must be called before. * Call the DATA_EEPROM_Lock() to disable the data EEPROM access * and Flash program erase control register access(recommended to protect * the DATA_EEPROM against possible unwanted operation). * @note The function DATA_EEPROM_FixedTimeProgramCmd() can be called before * this function to configure the Fixed Time Programming. * @param Address: specifies the address to be written. * @param Data: specifies the data to be written. * @retval FLASH Status: The returned value can be: * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data) { FLASH_Status status = FLASH_COMPLETE; #if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_XL) uint32_t tmp = 0, tmpaddr = 0; #endif /* Check the parameters */ assert_param(IS_FLASH_DATA_ADDRESS(Address)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); if(status == FLASH_COMPLETE) { #if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_XL) if(Data != (uint8_t) 0x00) { *(__IO uint8_t *)Address = Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); } else { tmpaddr = Address & 0xFFFFFFFC; tmp = * (__IO uint32_t *) tmpaddr; tmpaddr = 0xFF << ((uint32_t) (0x8 * (Address & 0x3))); tmp &= ~tmpaddr; status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC); status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp); } #elif defined (STM32L1XX_HD) || defined (STM32L1XX_MDP) || defined (STM32L1XX_XL) *(__IO uint8_t *)Address = Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); #endif } /* Return the Write Status */ return status; } /** * @brief Writes a half word at a specified address in data memory without erase. * @note To correctly run this function, the DATA_EEPROM_Unlock() function * must be called before. * Call the DATA_EEPROM_Lock() to disable the data EEPROM access * and Flash program erase control register access(recommended to protect * the DATA_EEPROM against possible unwanted operation). * @note The function DATA_EEPROM_FixedTimeProgramCmd() can be called before * this function to configure the Fixed Time Programming * @param Address: specifies the address to be written. * @param Data: specifies the data to be written. * @retval FLASH Status: The returned value can be: * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data) { FLASH_Status status = FLASH_COMPLETE; #if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_XL) uint32_t tmp = 0, tmpaddr = 0; #endif /* Check the parameters */ assert_param(IS_FLASH_DATA_ADDRESS(Address)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); if(status == FLASH_COMPLETE) { #if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_XL) if(Data != (uint16_t)0x0000) { *(__IO uint16_t *)Address = Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); } else { if((Address & 0x3) != 0x3) { tmpaddr = Address & 0xFFFFFFFC; tmp = * (__IO uint32_t *) tmpaddr; tmpaddr = 0xFFFF << ((uint32_t) (0x8 * (Address & 0x3))); tmp &= ~tmpaddr; status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC); status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp); } else { DATA_EEPROM_FastProgramByte(Address, 0x00); DATA_EEPROM_FastProgramByte(Address + 1, 0x00); } } #elif defined (STM32L1XX_HD) || defined (STM32L1XX_MDP) || defined (STM32L1XX_XL) *(__IO uint16_t *)Address = Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); #endif } /* Return the Write Status */ return status; } /** * @brief Programs a word at a specified address in data memory without erase. * @note To correctly run this function, the DATA_EEPROM_Unlock() function * must be called before. * Call the DATA_EEPROM_Lock() to disable the data EEPROM access * and Flash program erase control register access(recommended to protect * the DATA_EEPROM against possible unwanted operation). * @note The function DATA_EEPROM_FixedTimeProgramCmd() can be called before * this function to configure the Fixed Time Programming. * @param Address: specifies the address to be written. * @param Data: specifies the data to be written. * @retval FLASH Status: The returned value can be: * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data) { FLASH_Status status = FLASH_COMPLETE; /* Check the parameters */ assert_param(IS_FLASH_DATA_ADDRESS(Address)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); if(status == FLASH_COMPLETE) { *(__IO uint32_t *)Address = Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); } /* Return the Write Status */ return status; } /** * @} */ /** @defgroup FLASH_Group4 Option Bytes Programming functions * @brief Option Bytes Programming functions * @verbatim ============================================================================== ##### Option Bytes Programming functions ##### ============================================================================== [..] The FLASH_Option Bytes Programming_functions, includes the following functions: (+) void FLASH_OB_Unlock(void); (+) void FLASH_OB_Lock(void); (+) void FLASH_OB_Launch(void); (+) FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState); (+) FLASH_Status FLASH_OB_WRP1Config(uint32_t OB_WRP1, FunctionalState NewState); (+) FLASH_Status FLASH_OB_WRP2Config(uint32_t OB_WRP2, FunctionalState NewState); (+) FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP); (+) FLASH_Status FLASH_OB_PCROPConfig(uint32_t OB_WRP, FunctionalState NewState); (+) FLASH_Status FLASH_OB_PCROP1Config(uint32_t OB_WRP1, FunctionalState NewState); (+) FLASH_Status FLASH_OB_PCROPSelectionConfig(uint16_t OB_PcROP); (+) FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); (+) FLASH_Status FLASH_OB_BORConfig(uint8_t OB_BOR); (+) uint8_t FLASH_OB_GetUser(void); (+) uint32_t FLASH_OB_GetWRP(void); (+) uint32_t FLASH_OB_GetWRP1(void); (+) uint32_t FLASH_OB_GetWRP2(void); (+) FlagStatus FLASH_OB_GetRDP(void); (+) FlagStatus FLASH_OB_GetSPRMOD(void); (+) uint8_t FLASH_OB_GetBOR(void); (+) FLASH_Status FLASH_OB_BootConfig(uint16_t OB_BOOT); [..] Any operation of erase or program should follow these steps: (#) Call the FLASH_OB_Unlock() function to enable the Flash option control register access. (#) Call one or several functions to program the desired option bytes. (++) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) => to Enable/Disable the desired sector write protection. (++) void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read Protection Level. (++) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) => to configure the user option Bytes: IWDG, STOP and the Standby. (++) void FLASH_OB_BORConfig(uint8_t OB_BOR) => to Set the BOR level. (#) Once all needed option bytes to be programmed are correctly written, call the FLASH_OB_Launch(void) function to launch the Option Bytes programming process. (#) Call the FLASH_OB_Lock() to disable the Flash option control register access (recommended to protect the option Bytes against possible unwanted operations). [..] Proprietary code Read Out Protection (PcROP): (#) The PcROP sector is selected by using the same option bytes as the Write protection (nWRPi bits). As a result, these 2 options are exclusive each other. (#) In order to activate the PcROP (change the function of the nWRPi option bits), the SPRMOD option bit must be activated. (#) The active value of nWRPi bits is inverted when PCROP mode is active, this means: if SPRMOD = 1 and nWRPi = 1 (default value), then the user sector "i" is read/write protected. (#) To activate PCROP mode for Flash sector(s), you need to follow the sequence below: (++) For sector(s) within the first 128KB of the Flash, use this function FLASH_OB_PCROPConfig(OB_WRP_Pagesxxx, ENABLE) (++) For sector(s) within the second 128KB of the Flash, use this function FLASH_OB_PCROP1Config(OB_WRP_Pagesxxx, ENABLE) (++) Activate the PCROP mode using FLASH_OB_PCROPSelectionConfig(OB_PcROP_Enable) function (#) PcROP is available only in STM32L1XX_MDP devices @endverbatim * @{ */ /** * @brief Unlocks the option bytes block access. * @param None * @retval None */ void FLASH_OB_Unlock(void) { if((FLASH->PECR & FLASH_PECR_OPTLOCK) != RESET) { /* Unlocking the data memory and FLASH_PECR register access */ DATA_EEPROM_Unlock(); /* Unlocking the option bytes block access */ FLASH->OPTKEYR = FLASH_OPTKEY1; FLASH->OPTKEYR = FLASH_OPTKEY2; } } /** * @brief Locks the option bytes block access. * @param None * @retval None */ void FLASH_OB_Lock(void) { /* Set the OPTLOCK Bit to lock the option bytes block access */ FLASH->PECR |= FLASH_PECR_OPTLOCK; } /** * @brief Launch the option byte loading. * @param None * @retval None */ void FLASH_OB_Launch(void) { /* Set the OBL_Launch bit to lauch the option byte loading */ FLASH->PECR |= FLASH_PECR_OBL_LAUNCH; } /** * @brief Write protects the desired pages of the first 128KB of the Flash. * @param OB_WRP: specifies the address of the pages to be write protected. * This parameter can be: * @arg value between OB_WRP_Pages0to15 and OB_WRP_Pages496to511 * @arg OB_WRP_AllPages * @note In the StdLib, the naming of WRP registers is shifted vs. the Reference Manual: * - WRPR correspond to WRPR1 * @param NewState: new state of the specified FLASH Pages Wtite protection. * This parameter can be: ENABLE or DISABLE. * @retval FLASH Status: The returned value can be: * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) { uint32_t WRP01_Data = 0, WRP23_Data = 0; FLASH_Status status = FLASH_COMPLETE; uint32_t tmp1 = 0, tmp2 = 0; /* Check the parameters */ assert_param(IS_OB_WRP(OB_WRP)); assert_param(IS_FUNCTIONAL_STATE(NewState)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); if(status == FLASH_COMPLETE) { if (NewState != DISABLE) { WRP01_Data = (uint16_t)(((OB_WRP & WRP01_MASK) | OB->WRP01)); WRP23_Data = (uint16_t)((((OB_WRP & WRP23_MASK)>>16 | OB->WRP23))); tmp1 = (uint32_t)(~(WRP01_Data) << 16)|(WRP01_Data); OB->WRP01 = tmp1; tmp2 = (uint32_t)(~(WRP23_Data) << 16)|(WRP23_Data); OB->WRP23 = tmp2; } else { WRP01_Data = (uint16_t)(~OB_WRP & (WRP01_MASK & OB->WRP01)); WRP23_Data = (uint16_t)((((~OB_WRP & WRP23_MASK)>>16 & OB->WRP23))); tmp1 = (uint32_t)((~WRP01_Data) << 16)|(WRP01_Data); OB->WRP01 = tmp1; tmp2 = (uint32_t)((~WRP23_Data) << 16)|(WRP23_Data); OB->WRP23 = tmp2; } /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); } /* Return the write protection operation Status */ return status; } /** * @brief Write protects the desired pages of the second 128KB of the Flash. * @note This function can be used only for STM32L1XX_HD, STM32L1XX_MDP and * STM32L1XX_XL devices. * @param OB_WRP1: specifies the address of the pages to be write protected. * This parameter can be: * @arg value between OB_WRP_Pages512to527 and OB_WRP_Pages1008to1023 * @arg OB_WRP1_AllPages * @note In the StdLib, the naming of WRP registers is shifted vs. the Reference Manual: * - WRPR1 correspond to WRPR2 * @param NewState: new state of the specified FLASH Pages Wtite protection. * This parameter can be: ENABLE or DISABLE. * @retval FLASH Status: The returned value can be: * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status FLASH_OB_WRP1Config(uint32_t OB_WRP1, FunctionalState NewState) { uint32_t WRP45_Data = 0, WRP67_Data = 0; FLASH_Status status = FLASH_COMPLETE; uint32_t tmp1 = 0, tmp2 = 0; /* Check the parameters */ assert_param(IS_OB_WRP(OB_WRP1)); assert_param(IS_FUNCTIONAL_STATE(NewState)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); if(status == FLASH_COMPLETE) { if (NewState != DISABLE) { WRP45_Data = (uint16_t)(((OB_WRP1 & WRP45_MASK) | OB->WRP45)); WRP67_Data = (uint16_t)((((OB_WRP1 & WRP67_MASK)>>16 | OB->WRP67))); tmp1 = (uint32_t)(~(WRP45_Data) << 16)|(WRP45_Data); OB->WRP45 = tmp1; tmp2 = (uint32_t)(~(WRP67_Data) << 16)|(WRP67_Data); OB->WRP67 = tmp2; } else { WRP45_Data = (uint16_t)(~OB_WRP1 & (WRP45_MASK & OB->WRP45)); WRP67_Data = (uint16_t)((((~OB_WRP1 & WRP67_MASK)>>16 & OB->WRP67))); tmp1 = (uint32_t)((~WRP45_Data) << 16)|(WRP45_Data); OB->WRP45 = tmp1; tmp2 = (uint32_t)((~WRP67_Data) << 16)|(WRP67_Data); OB->WRP67 = tmp2; } /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); } /* Return the write protection operation Status */ return status; } /** * @brief Write protects the desired pages of the third 128KB of the Flash. * @note This function can be used only for STM32L1XX_HD and STM32L1XX_XL devices. * @param OB_WRP2: specifies the address of the pages to be write protected. * This parameter can be: * @arg value between OB_WRP_Pages1024to1039 and OB_WRP_Pages1520to1535 * @arg OB_WRP2_AllPages * @note In the StdLib, the naming of WRP registers is shifted vs. the Reference Manual: * - WRPR2 correspond to WRPR3 * @param NewState: new state of the specified FLASH Pages Wtite protection. * This parameter can be: ENABLE or DISABLE. * @retval FLASH Status: The returned value can be: * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status FLASH_OB_WRP2Config(uint32_t OB_WRP2, FunctionalState NewState) { uint32_t WRP89_Data = 0, WRP1011_Data = 0; FLASH_Status status = FLASH_COMPLETE; uint32_t tmp1 = 0, tmp2 = 0; /* Check the parameters */ assert_param(IS_OB_WRP(OB_WRP2)); assert_param(IS_FUNCTIONAL_STATE(NewState)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); if(status == FLASH_COMPLETE) { if (NewState != DISABLE) { WRP89_Data = (uint16_t)(((OB_WRP2 & WRP89_MASK) | OB->WRP89)); WRP1011_Data = (uint16_t)((((OB_WRP2 & WRP1011_MASK)>>16 | OB->WRP1011))); tmp1 = (uint32_t)(~(WRP89_Data) << 16)|(WRP89_Data); OB->WRP89 = tmp1; tmp2 = (uint32_t)(~(WRP1011_Data) << 16)|(WRP1011_Data); OB->WRP1011 = tmp2; } else { WRP89_Data = (uint16_t)(~OB_WRP2 & (WRP89_MASK & OB->WRP89)); WRP1011_Data = (uint16_t)((((~OB_WRP2 & WRP1011_MASK)>>16 & OB->WRP1011))); tmp1 = (uint32_t)((~WRP89_Data) << 16)|(WRP89_Data); OB->WRP89 = tmp1; tmp2 = (uint32_t)((~WRP1011_Data) << 16)|(WRP1011_Data); OB->WRP1011 = tmp2; } /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); } /* Return the write protection operation Status */ return status; } /** * @brief Write protects the desired pages of the fourth 128KB of the Flash. * @note This function can be used only for STM32L1XX_XL devices. * @param OB_WRP3: specifies the address of the pages to be write protected. * This parameter can be: * @arg value between OB_WRP3_Pages1536to1551 and OB_WRP3_Pages2032to2047 * @arg OB_WRP3_AllPages * @note In the StdLib, the naming of WRP registers is shifted vs. the Reference Manual: * - WRPR3 correspond to WRPR4 * @param NewState: new state of the specified FLASH Pages Wtite protection. * This parameter can be: ENABLE or DISABLE. * @retval FLASH Status: The returned value can be: * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status FLASH_OB_WRP3Config(uint32_t OB_WRP3, FunctionalState NewState) { uint32_t WRP1213_Data = 0, WRP1415_Data = 0; FLASH_Status status = FLASH_COMPLETE; uint32_t tmp1 = 0, tmp2 = 0; /* Check the parameters */ assert_param(IS_OB_WRP(OB_WRP3)); assert_param(IS_FUNCTIONAL_STATE(NewState)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); if(status == FLASH_COMPLETE) { if (NewState != DISABLE) { WRP1213_Data = (uint16_t)(((OB_WRP3 & WRP1213_MASK) | OB->WRP1213)); WRP1415_Data = (uint16_t)((((OB_WRP3 & WRP1415_MASK)>>16 | OB->WRP1415))); tmp1 = (uint32_t)(~(WRP1213_Data) << 16)|(WRP1213_Data); OB->WRP1213 = tmp1; tmp2 = (uint32_t)(~(WRP1415_Data) << 16)|(WRP1415_Data); OB->WRP1415 = tmp2; } else { WRP1213_Data = (uint16_t)(~OB_WRP3 & (WRP1213_MASK & OB->WRP1213)); WRP1415_Data = (uint16_t)((((~OB_WRP3 & WRP1415_MASK)>>16 & OB->WRP1415))); tmp1 = (uint32_t)((~WRP1213_Data) << 16)|(WRP1213_Data); OB->WRP1213 = tmp1; tmp2 = (uint32_t)((~WRP1415_Data) << 16)|(WRP1415_Data); OB->WRP1415 = tmp2; } /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); } /* Return the write protection operation Status */ return status; } /** * @brief Enables or disables the read out protection. * @note To correctly run this function, the FLASH_OB_Unlock() function * must be called before. * @param FLASH_ReadProtection_Level: specifies the read protection level. * This parameter can be: * @arg OB_RDP_Level_0: No protection * @arg OB_RDP_Level_1: Read protection of the memory * @arg OB_RDP_Level_2: Chip protection * * !!!Warning!!! When enabling OB_RDP_Level_2 it's no more possible to go back to level 1 or 0 * * @retval FLASH Status: The returned value can be: * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP) { FLASH_Status status = FLASH_COMPLETE; uint16_t tmp1 = 0; uint32_t tmp2 = 0; /* Check the parameters */ assert_param(IS_OB_RDP(OB_RDP)); status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); /* calculate the option byte to write */ tmp1 = ((uint16_t)(*(__IO uint16_t *)(OB_BASE)) & 0xFF00) | OB_RDP; tmp2 = (uint32_t)(((uint32_t)((uint32_t)(~tmp1) << 16)) | ((uint32_t)tmp1)); if(status == FLASH_COMPLETE) { /* program read protection level */ OB->RDP = tmp2; } /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); /* Return the Read protection operation Status */ return status; } /** * @brief Enables or disables the read/write protection (PCROP) of the desired * sectors, for the first 128KB of the Flash. * @note This function can be used only for STM32L1XX_MDP devices * @param OB_WRP: specifies the address of the pages to be write protected. * This parameter can be: * @arg value between OB_WRP_Pages0to15 and OB_WRP_Pages496to511 * @arg OB_WRP_AllPages * @param NewState: new state of the specified FLASH Pages Write protection. * This parameter can be: ENABLE or DISABLE. * @retval FLASH Status: The returned value can be: * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status FLASH_OB_PCROPConfig(uint32_t OB_WRP, FunctionalState NewState) { uint32_t WRP01_Data = 0, WRP23_Data = 0; FLASH_Status status = FLASH_COMPLETE; uint32_t tmp1 = 0, tmp2 = 0; /* Check the parameters */ assert_param(IS_OB_WRP(OB_WRP)); assert_param(IS_FUNCTIONAL_STATE(NewState)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); if(status == FLASH_COMPLETE) { if (NewState != DISABLE) { WRP01_Data = (uint16_t)(~OB_WRP & (WRP01_MASK & OB->WRP01)); WRP23_Data = (uint16_t)((((~OB_WRP & WRP23_MASK)>>16 & OB->WRP23))); tmp1 = (uint32_t)((~WRP01_Data) << 16)|(WRP01_Data); OB->WRP01 = tmp1; tmp2 = (uint32_t)((~WRP23_Data) << 16)|(WRP23_Data); OB->WRP23 = tmp2; } else { WRP01_Data = (uint16_t)((OB_WRP & WRP01_MASK) | OB->WRP01); WRP23_Data = (uint16_t)(((OB_WRP & WRP23_MASK) >> 16) | OB->WRP23); tmp1 = (uint32_t)(~(WRP01_Data) << 16)|(WRP01_Data); OB->WRP01 = tmp1; tmp2 = (uint32_t)(~(WRP23_Data) << 16)|(WRP23_Data); OB->WRP23 = tmp2; } /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); } /* Return the write protection operation Status */ return status; } /** * @brief Enables or disables the read/write protection (PCROP) of the desired * sectors, for the second 128KB of the Flash. * @note This function can be used only for STM32L1XX_MDP devices * @param OB_WRP1: specifies the address of the pages to be write protected. * This parameter can be: * @arg value between OB_WRP_Pages512to527 and OB_WRP_Pages1008to1023 * @arg OB_WRP_AllPages * @param NewState: new state of the specified FLASH Pages Write protection. * This parameter can be: ENABLE or DISABLE. * @retval FLASH Status: The returned value can be: * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status FLASH_OB_PCROP1Config(uint32_t OB_WRP1, FunctionalState NewState) { uint32_t WRP45_Data = 0, WRP67_Data = 0; FLASH_Status status = FLASH_COMPLETE; uint32_t tmp1 = 0, tmp2 = 0; /* Check the parameters */ assert_param(IS_OB_WRP(OB_WRP1)); assert_param(IS_FUNCTIONAL_STATE(NewState)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); if(status == FLASH_COMPLETE) { if (NewState != DISABLE) { WRP45_Data = (uint16_t)(~OB_WRP1 & (WRP45_MASK & OB->WRP45)); WRP67_Data = (uint16_t)((((~OB_WRP1 & WRP67_MASK)>>16 & OB->WRP67))); tmp1 = (uint32_t)((~WRP45_Data) << 16)|(WRP45_Data); OB->WRP45 = tmp1; tmp2 = (uint32_t)((~WRP67_Data) << 16)|(WRP67_Data); OB->WRP67 = tmp2; } else { WRP45_Data = (uint16_t)((OB_WRP1 & WRP45_MASK) | OB->WRP45); WRP67_Data = (uint16_t)(((OB_WRP1 & WRP67_MASK)>>16) | OB->WRP67); tmp1 = (uint32_t)(~(WRP45_Data) << 16)|(WRP45_Data); OB->WRP45 = tmp1; tmp2 = (uint32_t)(~(WRP67_Data) << 16)|(WRP67_Data); OB->WRP67 = tmp2; } /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); } /* Return the write protection operation Status */ return status; } /** * @brief Select the Protection Mode (SPRMOD). * @note This function can be used only for STM32L1XX_MDP devices * @note Once SPRMOD bit is active, unprotection of a protected sector is not possible * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag * @param OB_PcROP: Select the Protection Mode of nWPRi bits. * This parameter can be: * @arg OB_PcROP_Enable: nWRPi control the read&write protection (PcROP) of respective user sectors. * @arg OB_PcROP_Disable: nWRPi control the write protection of respective user sectors. * @retval FLASH Status: The returned value can be: * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status FLASH_OB_PCROPSelectionConfig(uint16_t OB_PcROP) { FLASH_Status status = FLASH_COMPLETE; uint16_t tmp1 = 0; uint32_t tmp2 = 0; uint8_t optiontmp = 0; uint16_t optiontmp2 = 0; /* Check the parameters */ assert_param(IS_OB_PCROP_SELECT(OB_PcROP)); status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); /* Mask RDP Byte */ optiontmp = (uint8_t)(*(__IO uint8_t *)(OB_BASE)); /* Update Option Byte */ optiontmp2 = (uint16_t)(OB_PcROP | optiontmp); /* calculate the option byte to write */ tmp1 = (uint16_t)(~(optiontmp2 )); tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16)) | ((uint32_t)optiontmp2)); if(status == FLASH_COMPLETE) { /* program PCRop */ OB->RDP = tmp2; } /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); /* Return the Read protection operation Status */ return status; } /** * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. * @param OB_IWDG: Selects the WDG mode. * This parameter can be one of the following values: * @arg OB_IWDG_SW: Software WDG selected * @arg OB_IWDG_HW: Hardware WDG selected * @param OB_STOP: Reset event when entering STOP mode. * This parameter can be one of the following values: * @arg OB_STOP_NoRST: No reset generated when entering in STOP * @arg OB_STOP_RST: Reset generated when entering in STOP * @param OB_STDBY: Reset event when entering Standby mode. * This parameter can be one of the following values: * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY * @arg OB_STDBY_RST: Reset generated when entering in STANDBY * @retval FLASH Status: The returned value can be: * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) { FLASH_Status status = FLASH_COMPLETE; uint32_t tmp = 0, tmp1 = 0; /* Check the parameters */ assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); assert_param(IS_OB_STOP_SOURCE(OB_STOP)); assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); /* Get the User Option byte register */ tmp1 = (FLASH->OBR & 0x000F0000) >> 16; /* Calculate the user option byte to write */ tmp = (uint32_t)(((uint32_t)~((uint32_t)((uint32_t)(OB_IWDG) | (uint32_t)(OB_STOP) | (uint32_t)(OB_STDBY) | tmp1))) << ((uint32_t)0x10)); tmp |= ((uint32_t)(OB_IWDG) | ((uint32_t)OB_STOP) | (uint32_t)(OB_STDBY) | tmp1); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); if(status == FLASH_COMPLETE) { /* Write the User Option Byte */ OB->USER = tmp; } /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); /* Return the Option Byte program Status */ return status; } /** * @brief Programs the FLASH brownout reset threshold level Option Byte. * @param OB_BOR: Selects the brownout reset threshold level. * This parameter can be one of the following values: * @arg OB_BOR_OFF: BOR is disabled at power down, the reset is asserted when the VDD * power supply reaches the PDR(Power Down Reset) threshold (1.5V) * @arg OB_BOR_LEVEL1: BOR Reset threshold levels for 1.7V - 1.8V VDD power supply * @arg OB_BOR_LEVEL2: BOR Reset threshold levels for 1.9V - 2.0V VDD power supply * @arg OB_BOR_LEVEL3: BOR Reset threshold levels for 2.3V - 2.4V VDD power supply * @arg OB_BOR_LEVEL4: BOR Reset threshold levels for 2.55V - 2.65V VDD power supply * @arg OB_BOR_LEVEL5: BOR Reset threshold levels for 2.8V - 2.9V VDD power supply * @retval FLASH Status: The returned value can be: * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status FLASH_OB_BORConfig(uint8_t OB_BOR) { FLASH_Status status = FLASH_COMPLETE; uint32_t tmp = 0, tmp1 = 0; /* Check the parameters */ assert_param(IS_OB_BOR_LEVEL(OB_BOR)); /* Get the User Option byte register */ tmp1 = (FLASH->OBR & 0x00F00000) >> 16; /* Calculate the option byte to write */ tmp = (uint32_t)~(OB_BOR | tmp1)<<16; tmp |= (OB_BOR | tmp1); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); if(status == FLASH_COMPLETE) { /* Write the BOR Option Byte */ OB->USER = tmp; } /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); /* Return the Option Byte program Status */ return status; } /** * @brief Configures to boot from Bank1 or Bank2. * @note This function can be used only for STM32L1XX_HD and STM32L1XX_XL devices. * @param OB_BOOT: select the FLASH Bank to boot from. * This parameter can be one of the following values: * @arg OB_BOOT_BANK2: At startup, if boot pins are set in boot from user Flash * position and this parameter is selected the device will boot from Bank2 or Bank1, * depending on the activation of the bank. The active banks are checked in * the following order: Bank2, followed by Bank1. * The active bank is recognized by the value programmed at the base address * of the respective bank (corresponding to the initial stack pointer value * in the interrupt vector table). * @arg OB_BOOT_BANK1: At startup, if boot pins are set in boot from user Flash * position and this parameter is selected the device will boot from Bank1(Default). * For more information, please refer to AN2606 from www.st.com. * @retval FLASH Status: The returned value can be: * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status FLASH_OB_BootConfig(uint8_t OB_BOOT) { FLASH_Status status = FLASH_COMPLETE; uint32_t tmp = 0, tmp1 = 0; /* Check the parameters */ assert_param(IS_OB_BOOT_BANK(OB_BOOT)); /* Get the User Option byte register */ tmp1 = (FLASH->OBR & 0x007F0000) >> 16; /* Calculate the option byte to write */ tmp = (uint32_t)~(OB_BOOT | tmp1)<<16; tmp |= (OB_BOOT | tmp1); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); if(status == FLASH_COMPLETE) { /* Write the BOOT Option Byte */ OB->USER = tmp; } /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); /* Return the Option Byte program Status */ return status; } /** * @brief Returns the FLASH User Option Bytes values. * @param None * @retval The FLASH User Option Bytes. */ uint8_t FLASH_OB_GetUser(void) { /* Return the User Option Byte */ return (uint8_t)(FLASH->OBR >> 20); } /** * @brief Returns the FLASH Write Protection Option Bytes value. * @note In the StdLib, the naming of WRP registers is shifted vs. the Reference Manual: * - WRPR correspond to WRPR1 * @param None * @retval The FLASH Write Protection Option Bytes value. */ uint32_t FLASH_OB_GetWRP(void) { /* Return the FLASH write protection Register value */ return (uint32_t)(FLASH->WRPR); } /** * @brief Returns the FLASH Write Protection Option Bytes value. * @note This function can be used only for STM32L1XX_HD, STM32L1XX_MDP and * STM32L1XX_XL devices. * @note In the StdLib, the naming of WRP registers is shifted vs. the Reference Manual: * - WRPR1 correspond to WRPR2 * @param None * @retval The FLASH Write Protection Option Bytes value. */ uint32_t FLASH_OB_GetWRP1(void) { /* Return the FLASH write protection Register value */ return (uint32_t)(FLASH->WRPR1); } /** * @brief Returns the FLASH Write Protection Option Bytes value. * @note This function can be used only for STM32L1XX_HD and STM32L1XX_XL devices. * @note In the StdLib, the naming of WRP registers is shifted vs. the Reference Manual: * - WRPR2 correspond to WRPR3 * @param None * @retval The FLASH Write Protection Option Bytes value. */ uint32_t FLASH_OB_GetWRP2(void) { /* Return the FLASH write protection Register value */ return (uint32_t)(FLASH->WRPR2); } /** * @brief Returns the FLASH Write Protection Option Bytes value. * @note This function can be used only for STM32L1XX_XL devices. * @note In the StdLib, the naming of WRP registers is shifted vs. the Reference Manual: * - WRPR3 correspond to WRPR4 * @param None * @retval The FLASH Write Protection Option Bytes value. */ uint32_t FLASH_OB_GetWRP3(void) { /* Return the FLASH write protection Register value */ return (uint32_t)(FLASH->WRPR3); } /** * @brief Checks whether the FLASH Read out Protection Status is set or not. * @param None * @retval FLASH ReadOut Protection Status(SET or RESET). */ FlagStatus FLASH_OB_GetRDP(void) { FlagStatus readstatus = RESET; if ((uint8_t)(FLASH->OBR) != (uint8_t)OB_RDP_Level_0) { readstatus = SET; } else { readstatus = RESET; } return readstatus; } /** * @brief Returns the SPRMOD Status. * @note This function can be used only for STM32L1XX_MDP devices * @param None * @retval The SPRMOD Status. */ FlagStatus FLASH_OB_GetSPRMOD(void) { FlagStatus readstatus = RESET; uint16_t tmp = 0; /* Return the SPRMOD value */ tmp = (uint16_t)(FLASH->OBR & (uint16_t)(0x0100)); if (tmp != (uint16_t)0x0000) { readstatus = SET; } else { readstatus = RESET; } return readstatus; } /** * @brief Returns the FLASH BOR level. * @param None * @retval The FLASH User Option Bytes. */ uint8_t FLASH_OB_GetBOR(void) { /* Return the BOR level */ return (uint8_t)((FLASH->OBR & (uint32_t)0x000F0000) >> 16); } /** * @} */ /** @defgroup FLASH_Group5 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim ============================================================================== ##### Interrupts and flags management functions ##### ============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables the specified FLASH interrupts. * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or * disabled. * This parameter can be any combination of the following values: * @arg FLASH_IT_EOP: FLASH end of programming Interrupt * @arg FLASH_IT_ERR: FLASH Error Interrupt * @retval None */ void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FLASH_IT(FLASH_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if(NewState != DISABLE) { /* Enable the interrupt sources */ FLASH->PECR |= FLASH_IT; } else { /* Disable the interrupt sources */ FLASH->PECR &= ~(uint32_t)FLASH_IT; } } /** * @brief Checks whether the specified FLASH flag is set or not. * @param FLASH_FLAG: specifies the FLASH flag to check. * This parameter can be one of the following values: * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag * @arg FLASH_FLAG_EOP: FLASH End of Operation flag * @arg FLASH_FLAG_READY: FLASH Ready flag after low power mode * @arg FLASH_FLAG_ENDHV: FLASH End of high voltage flag * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag * @arg FLASH_FLAG_SIZERR: FLASH size error flag * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag * @arg FLASH_FLAG_OPTVERRUSR: FLASH Option User validity error flag * @arg FLASH_FLAG_RDERR: FLASH Read protected error flag (available only in STM32L1XX_MDP devices) * @retval The new state of FLASH_FLAG (SET or RESET). */ FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)); if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } /* Return the new state of FLASH_FLAG (SET or RESET) */ return bitstatus; } /** * @brief Clears the FLASH's pending flags. * @param FLASH_FLAG: specifies the FLASH flags to clear. * This parameter can be any combination of the following values: * @arg FLASH_FLAG_EOP: FLASH End of Operation flag * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag * @arg FLASH_FLAG_SIZERR: FLASH size error flag * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag * @arg FLASH_FLAG_OPTVERRUSR: FLASH Option User validity error flag * @arg FLASH_FLAG_RDERR: FLASH Read protected error flag (available only in STM32L1XX_MDP devices) * @retval None */ void FLASH_ClearFlag(uint32_t FLASH_FLAG) { /* Check the parameters */ assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)); /* Clear the flags */ FLASH->SR = FLASH_FLAG; } /** * @brief Returns the FLASH Status. * @param None * @retval FLASH Status: The returned value can be: * FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE. */ FLASH_Status FLASH_GetStatus(void) { FLASH_Status FLASHstatus = FLASH_COMPLETE; if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) { FLASHstatus = FLASH_BUSY; } else { if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00) { FLASHstatus = FLASH_ERROR_WRP; } else { if((FLASH->SR & (uint32_t)0x1E00) != (uint32_t)0x00) { FLASHstatus = FLASH_ERROR_PROGRAM; } else { FLASHstatus = FLASH_COMPLETE; } } } /* Return the FLASH Status */ return FLASHstatus; } /** * @brief Waits for a FLASH operation to complete or a TIMEOUT to occur. * @param Timeout: FLASH programming Timeout. * @retval FLASH Status: The returned value can be: FLASH_BUSY, * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) { __IO FLASH_Status status = FLASH_COMPLETE; /* Check for the FLASH Status */ status = FLASH_GetStatus(); /* Wait for a FLASH operation to complete or a TIMEOUT to occur */ while((status == FLASH_BUSY) && (Timeout != 0x00)) { status = FLASH_GetStatus(); Timeout--; } if(Timeout == 0x00 ) { status = FLASH_TIMEOUT; } /* Return the operation status */ return status; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ src/stm32L_bare/stdlib/src/stm32l1xx_flash_ramfunc.c
New file @@ -0,0 +1,559 @@ /** ****************************************************************************** * @file stm32l1xx_flash_ramfunc.c * @author MCD Application Team * @version V1.3.1 * @date 20-April-2015 * @brief This file provides all the Flash firmware functions which should be * executed from the internal SRAM. This file should be placed in * internal SRAM. * Other FLASH memory functions that can be used from the FLASH are * defined in the "stm32l1xx_flash.c" file. @verbatim *** ARM Compiler *** -------------------- [..] RAM functions are defined using the toolchain options. Functions that are be executed in RAM should reside in a separate source module. Using the 'Options for File' dialog you can simply change the 'Code / Const' area of a module to a memory space in physical RAM. Available memory areas are declared in the 'Target' tab of the Options for Target' dialog. *** ICCARM Compiler *** ----------------------- [..] RAM functions are defined using a specific toolchain keyword "__ramfunc". *** GNU Compiler *** -------------------- [..] RAM functions are defined using a specific toolchain attribute "__attribute__((section(".data")))". *** TASKING Compiler *** ------------------------ [..] RAM functions are defined using a specific toolchain pragma. This pragma is defined inside this file. @endverbatim * ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx_flash.h" /** @addtogroup STM32L1xx_StdPeriph_Driver * @{ */ /** @defgroup FLASH * @brief FLASH driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ static __RAM_FUNC GetStatus(void); static __RAM_FUNC WaitForLastOperation(uint32_t Timeout); /* Private functions ---------------------------------------------------------*/ /** @defgroup FLASH_Private_Functions * @{ */ /** @addtogroup FLASH_Group1 * @verbatim @endverbatim * @{ */ #if defined ( __TASKING__ ) #pragma section_code_init on #endif /** * @brief Enable or disable the power down mode during RUN mode. * @note This function can be used only when the user code is running from Internal SRAM. * @param NewState: new state of the power down mode during RUN mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ __RAM_FUNC FLASH_RUNPowerDownCmd(FunctionalState NewState) { FLASH_Status status = FLASH_COMPLETE; if (NewState != DISABLE) { /* Unlock the RUN_PD bit */ FLASH->PDKEYR = FLASH_PDKEY1; FLASH->PDKEYR = FLASH_PDKEY2; /* Set the RUN_PD bit in FLASH_ACR register to put Flash in power down mode */ FLASH->ACR |= (uint32_t)FLASH_ACR_RUN_PD; if((FLASH->ACR & FLASH_ACR_RUN_PD) != FLASH_ACR_RUN_PD) { status = FLASH_ERROR_PROGRAM; } } else { /* Clear the RUN_PD bit in FLASH_ACR register to put Flash in idle mode */ FLASH->ACR &= (uint32_t)(~(uint32_t)FLASH_ACR_RUN_PD); } /* Return the Write Status */ return status; } /** * @} */ /** @addtogroup FLASH_Group2 * @verbatim @endverbatim * @{ */ /** * @brief Erases a specified 2 page in program memory in parallel. * @note This function can be used only for STM32L1XX_HD and STM32L1XX_XL devices. * To correctly run this function, the FLASH_Unlock() function * must be called before. * Call the FLASH_Lock() to disable the flash memory access * (recommended to protect the FLASH memory against possible unwanted operation). * @param Page_Address1: The page address in program memory to be erased in * the first Bank (BANK1). This parameter should be: * - between 0x08000000 and 0x0802FF00 for STM32L1XX_HD devices * - between 0x08000000 and 0x0803FF00 for STM32L1XX_XL devices * @param Page_Address2: The page address in program memory to be erased in * the second Bank (BANK2). This parameter should be: * - between 0x08030000 and 0x0805FF00 for STM32L1XX_HD devices * - between 0x08040000 and 0x0807FF00 for STM32L1XX_XL devices * @note A Page is erased in the Program memory only if the address to load * is the start address of a page (multiple of 256 bytes). * @retval FLASH Status: The returned value can be: * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status FLASH_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2) { FLASH_Status status = FLASH_COMPLETE; /* Wait for last operation to be completed */ status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); if(status == FLASH_COMPLETE) { /* If the previous operation is completed, proceed to erase the page */ /* Set the PARALLBANK bit */ FLASH->PECR |= FLASH_PECR_PARALLBANK; /* Set the ERASE bit */ FLASH->PECR |= FLASH_PECR_ERASE; /* Set PROG bit */ FLASH->PECR |= FLASH_PECR_PROG; /* Write 00000000h to the first word of the first program page to erase */ *(__IO uint32_t *)Page_Address1 = 0x00000000; /* Write 00000000h to the first word of the second program page to erase */ *(__IO uint32_t *)Page_Address2 = 0x00000000; /* Wait for last operation to be completed */ status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); /* If the erase operation is completed, disable the ERASE, PROG and PARALLBANK bits */ FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG); FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE); FLASH->PECR &= (uint32_t)(~FLASH_PECR_PARALLBANK); } /* Return the Erase Status */ return status; } /** * @brief Programs a half page in program memory. * @param Address: specifies the address to be written. * @param pBuffer: pointer to the buffer containing the data to be written to * the half page. * @note To correctly run this function, the FLASH_Unlock() function * must be called before. * Call the FLASH_Lock() to disable the flash memory access * (recommended to protect the FLASH memory against possible unwanted operation) * @note Half page write is possible only from SRAM. * @note If there are more than 32 words to write, after 32 words another * Half Page programming operation starts and has to be finished. * @note A half page is written to the program memory only if the first * address to load is the start address of a half page (multiple of 128 * bytes) and the 31 remaining words to load are in the same half page. * @note During the Program memory half page write all read operations are * forbidden (this includes DMA read operations and debugger read * operations such as breakpoints, periodic updates, etc.). * @note If a PGAERR is set during a Program memory half page write, the * complete write operation is aborted. Software should then reset the * FPRG and PROG/DATA bits and restart the write operation from the * beginning. * @retval FLASH Status: The returned value can be: * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ __RAM_FUNC FLASH_ProgramHalfPage(uint32_t Address, uint32_t* pBuffer) { uint32_t count = 0; FLASH_Status status = FLASH_COMPLETE; /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008) This bit prevents the interruption of multicycle instructions and therefore will increase the interrupt latency. of Cortex-M3. */ SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk; /* Wait for last operation to be completed */ status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); if(status == FLASH_COMPLETE) { /* if the previous operation is completed, proceed to program the new half page */ FLASH->PECR |= FLASH_PECR_FPRG; FLASH->PECR |= FLASH_PECR_PROG; /* Write one half page directly with 32 different words */ while(count < 32) { *(__IO uint32_t*) (Address + (4 * count)) = *(pBuffer++); count ++; } /* Wait for last operation to be completed */ status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); /* if the write operation is completed, disable the PROG and FPRG bits */ FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG); FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG); } SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk; /* Return the Write Status */ return status; } /** * @brief Programs 2 half page in program memory in parallel. * @param Address1: specifies the first address to be written in the first bank * (BANK1).This parameter should be: * - between 0x08000000 and 0x0802FF80 for STM32L1XX_HD devices * - between 0x08000000 and 0x0803FF80 for STM32L1XX_XL devices * @param pBuffer1: pointer to the buffer containing the data to be written * to the first half page in the first bank. * @param Address2: specifies the second address to be written in the second bank * (BANK2). This parameter should be: * - between 0x08030000 and 0x0805FF80 for STM32L1XX_HD devices * - between 0x08040000 and 0x0807FF80 for STM32L1XX_XL devices * @param pBuffer2: pointer to the buffer containing the data to be written * to the second half page in the second bank. * @note This function can be used only for STM32L1XX_HD and STM32L1XX_XL devices. * @note To correctly run this function, the FLASH_Unlock() function * must be called before. * Call the FLASH_Lock() to disable the flash memory access * (recommended to protect the FLASH memory against possible unwanted operation). * @note Half page write is possible only from SRAM. * @note If there are more than 32 words to write, after 32 words another * Half Page programming operation starts and has to be finished. * @note A half page is written to the program memory only if the first * address to load is the start address of a half page (multiple of 128 * bytes) and the 31 remaining words to load are in the same half page. * @note During the Program memory half page write all read operations are * forbidden (this includes DMA read operations and debugger read * operations such as breakpoints, periodic updates, etc.). * @note If a PGAERR is set during a Program memory half page write, the * complete write operation is aborted. Software should then reset the * FPRG and PROG/DATA bits and restart the write operation from the * beginning. * @retval FLASH Status: The returned value can be: * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ __RAM_FUNC FLASH_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2) { uint32_t count = 0; FLASH_Status status = FLASH_COMPLETE; /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008) This bit prevents the interruption of multicycle instructions and therefore will increase the interrupt latency. of Cortex-M3. */ SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk; /* Wait for last operation to be completed */ status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); if(status == FLASH_COMPLETE) { /* If the previous operation is completed, proceed to program the new half page */ FLASH->PECR |= FLASH_PECR_PARALLBANK; FLASH->PECR |= FLASH_PECR_FPRG; FLASH->PECR |= FLASH_PECR_PROG; /* Write the first half page directly with 32 different words */ while(count < 32) { *(__IO uint32_t*) (Address1 + (4 * count)) = *(pBuffer1++); count ++; } count = 0; /* Write the second half page directly with 32 different words */ while(count < 32) { *(__IO uint32_t*) (Address2 + (4 * count)) = *(pBuffer2++); count ++; } /* Wait for last operation to be completed */ status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); /* if the write operation is completed, disable the PROG, FPRG and PARALLBANK bits */ FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG); FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG); FLASH->PECR &= (uint32_t)(~FLASH_PECR_PARALLBANK); } SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk; /* Return the Write Status */ return status; } /** * @} */ /** @addtogroup FLASH_Group3 * @verbatim @endverbatim * @{ */ /** * @brief Erase a double word in data memory. * @param Address: specifies the address to be erased. * @note To correctly run this function, the DATA_EEPROM_Unlock() function * must be called before. * Call the DATA_EEPROM_Lock() to he data EEPROM access * and Flash program erase control register access(recommended to protect * the DATA_EEPROM against possible unwanted operation). * @note Data memory double word erase is possible only from SRAM. * @note A double word is erased to the data memory only if the first address * to load is the start address of a double word (multiple of 8 bytes). * @note During the Data memory double word erase, all read operations are * forbidden (this includes DMA read operations and debugger read * operations such as breakpoints, periodic updates, etc.). * @retval FLASH Status: The returned value can be: * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ __RAM_FUNC DATA_EEPROM_EraseDoubleWord(uint32_t Address) { FLASH_Status status = FLASH_COMPLETE; /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008) This bit prevents the interruption of multicycle instructions and therefore will increase the interrupt latency. of Cortex-M3. */ SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk; /* Wait for last operation to be completed */ status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); if(status == FLASH_COMPLETE) { /* If the previous operation is completed, proceed to erase the next double word */ /* Set the ERASE bit */ FLASH->PECR |= FLASH_PECR_ERASE; /* Set DATA bit */ FLASH->PECR |= FLASH_PECR_DATA; /* Write 00000000h to the 2 words to erase */ *(__IO uint32_t *)Address = 0x00000000; Address += 4; *(__IO uint32_t *)Address = 0x00000000; /* Wait for last operation to be completed */ status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); /* If the erase operation is completed, disable the ERASE and DATA bits */ FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE); FLASH->PECR &= (uint32_t)(~FLASH_PECR_DATA); } SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk; /* Return the erase status */ return status; } /** * @brief Write a double word in data memory without erase. * @param Address: specifies the address to be written. * @param Data: specifies the data to be written. * @note To correctly run this function, the DATA_EEPROM_Unlock() function * must be called before. * Call the DATA_EEPROM_Lock() to he data EEPROM access * and Flash program erase control register access(recommended to protect * the DATA_EEPROM against possible unwanted operation). * @note Data memory double word write is possible only from SRAM. * @note A data memory double word is written to the data memory only if the * first address to load is the start address of a double word (multiple * of double word). * @note During the Data memory double word write, all read operations are * forbidden (this includes DMA read operations and debugger read * operations such as breakpoints, periodic updates, etc.). * @retval FLASH Status: The returned value can be: * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ __RAM_FUNC DATA_EEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data) { FLASH_Status status = FLASH_COMPLETE; /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008) This bit prevents the interruption of multicycle instructions and therefore will increase the interrupt latency. of Cortex-M3. */ SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk; /* Wait for last operation to be completed */ status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); if(status == FLASH_COMPLETE) { /* If the previous operation is completed, proceed to program the new data*/ FLASH->PECR |= FLASH_PECR_FPRG; FLASH->PECR |= FLASH_PECR_DATA; /* Write the 2 words */ *(__IO uint32_t *)Address = (uint32_t) Data; Address += 4; *(__IO uint32_t *)Address = (uint32_t) (Data >> 32); /* Wait for last operation to be completed */ status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); /* If the write operation is completed, disable the FPRG and DATA bits */ FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG); FLASH->PECR &= (uint32_t)(~FLASH_PECR_DATA); } SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk; /* Return the Write Status */ return status; } /** * @} */ /** * @brief Returns the FLASH Status. * @param None * @retval FLASH Status: The returned value can be: FLASH_BUSY, * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE */ static __RAM_FUNC GetStatus(void) { FLASH_Status FLASHstatus = FLASH_COMPLETE; if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) { FLASHstatus = FLASH_BUSY; } else { if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00) { FLASHstatus = FLASH_ERROR_WRP; } else { if((FLASH->SR & (uint32_t)0x1E00) != (uint32_t)0x00) { FLASHstatus = FLASH_ERROR_PROGRAM; } else { FLASHstatus = FLASH_COMPLETE; } } } /* Return the FLASH Status */ return FLASHstatus; } /** * @brief Waits for a FLASH operation to complete or a TIMEOUT to occur. * @param Timeout: FLASH programming Timeout * @retval FLASH Status: The returned value can be: FLASH_BUSY, * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or * FLASH_TIMEOUT. */ static __RAM_FUNC WaitForLastOperation(uint32_t Timeout) { __IO FLASH_Status status = FLASH_COMPLETE; /* Check for the FLASH Status */ status = GetStatus(); /* Wait for a FLASH operation to complete or a TIMEOUT to occur */ while((status == FLASH_BUSY) && (Timeout != 0x00)) { status = GetStatus(); Timeout--; } if(Timeout == 0x00 ) { status = FLASH_TIMEOUT; } /* Return the operation status */ return status; } #if defined ( __TASKING__ ) #pragma section_code_init restore #endif /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Diff truncated after the above file
src/stm32L_bare/stdlib/src/stm32l1xx_fsmc.c src/stm32L_bare/stdlib/src/stm32l1xx_gpio.c src/stm32L_bare/stdlib/src/stm32l1xx_i2c.c src/stm32L_bare/stdlib/src/stm32l1xx_iwdg.c src/stm32L_bare/stdlib/src/stm32l1xx_lcd.c src/stm32L_bare/stdlib/src/stm32l1xx_opamp.c src/stm32L_bare/stdlib/src/stm32l1xx_pwr.c src/stm32L_bare/stdlib/src/stm32l1xx_rcc.c src/stm32L_bare/stdlib/src/stm32l1xx_rtc.c src/stm32L_bare/stdlib/src/stm32l1xx_sdio.c src/stm32L_bare/stdlib/src/stm32l1xx_spi.c src/stm32L_bare/stdlib/src/stm32l1xx_syscfg.c src/stm32L_bare/stdlib/src/stm32l1xx_tim.c src/stm32L_bare/stdlib/src/stm32l1xx_usart.c src/stm32L_bare/stdlib/src/stm32l1xx_wwdg.c src/stm32L_bare/stm32L_bare.uvgui.Think src/stm32L_bare/stm32L_bare.uvopt src/stm32L_bare/stm32L_bare.uvproj
