src/bare_test/1.Led/JLinkSettings.ini
File was renamed from src/bare_test/stm32_key/JLinkSettings.ini @@ -1,31 +1,31 @@ [BREAKPOINTS] ShowInfoWin = 1 EnableFlashBP = 2 BPDuringExecution = 0 [CFI] CFISize = 0x00 CFIAddr = 0x00 [CPU] OverrideMemMap = 0 AllowSimulation = 1 ScriptFile="" [FLASH] MinNumBytesFlashDL = 0 SkipProgOnCRCMatch = 1 VerifyDownload = 1 AllowCaching = 1 EnableFlashDL = 2 Override = 0 Device="AD7160" [GENERAL] WorkRAMSize = 0x00 WorkRAMAddr = 0x00 [SWO] SWOLogFile="" [MEM] RdOverrideOrMask = 0x00 RdOverrideAndMask = 0xFFFFFFFF RdOverrideAddr = 0xFFFFFFFF WrOverrideOrMask = 0x00 WrOverrideAndMask = 0xFFFFFFFF WrOverrideAddr = 0xFFFFFFFF [BREAKPOINTS] ShowInfoWin = 1 EnableFlashBP = 2 BPDuringExecution = 0 [CFI] CFISize = 0x00 CFIAddr = 0x00 [CPU] OverrideMemMap = 0 AllowSimulation = 1 ScriptFile="" [FLASH] MinNumBytesFlashDL = 0 SkipProgOnCRCMatch = 1 VerifyDownload = 1 AllowCaching = 1 EnableFlashDL = 2 Override = 0 Device="AD7160" [GENERAL] WorkRAMSize = 0x00 WorkRAMAddr = 0x00 [SWO] SWOLogFile="" [MEM] RdOverrideOrMask = 0x00 RdOverrideAndMask = 0xFFFFFFFF RdOverrideAddr = 0xFFFFFFFF WrOverrideOrMask = 0x00 WrOverrideAndMask = 0xFFFFFFFF WrOverrideAddr = 0xFFFFFFFF src/bare_test/1.Led/cmsis/core_cm3.c
File was renamed from src/bare_test/stm32_key/cmsis/core_cm3.c @@ -1,784 +1,784 @@ /**************************************************************************//** * @file core_cm3.c * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File * @version V1.30 * @date 30. October 2009 * * @note * Copyright (C) 2009 ARM Limited. All rights reserved. * * @par * ARM Limited (ARM) is supplying this software for use with Cortex-M * processor based microcontrollers. This file can be freely distributed * within development tools that are supporting such ARM based processors. * * @par * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. * ******************************************************************************/ #include <stdint.h> /* define compiler specific symbols */ #if defined ( __CC_ARM ) #define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #elif defined ( __ICCARM__ ) #define __ASM __asm /*!< asm keyword for IAR Compiler */ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ #elif defined ( __GNUC__ ) #define __ASM __asm /*!< asm keyword for GNU Compiler */ #define __INLINE inline /*!< inline keyword for GNU Compiler */ #elif defined ( __TASKING__ ) #define __ASM __asm /*!< asm keyword for TASKING Compiler */ #define __INLINE inline /*!< inline keyword for TASKING Compiler */ #endif /* ################### Compiler specific Intrinsics ########################### */ #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ /* ARM armcc specific functions */ /** * @brief Return the Process Stack Pointer * * @return ProcessStackPointer * * Return the actual process stack pointer */ __ASM uint32_t __get_PSP(void) { mrs r0, psp bx lr } /** * @brief Set the Process Stack Pointer * * @param topOfProcStack Process Stack Pointer * * Assign the value ProcessStackPointer to the MSP * (process stack pointer) Cortex processor register */ __ASM void __set_PSP(uint32_t topOfProcStack) { msr psp, r0 bx lr } /** * @brief Return the Main Stack Pointer * * @return Main Stack Pointer * * Return the current value of the MSP (main stack pointer) * Cortex processor register */ __ASM uint32_t __get_MSP(void) { mrs r0, msp bx lr } /** * @brief Set the Main Stack Pointer * * @param topOfMainStack Main Stack Pointer * * Assign the value mainStackPointer to the MSP * (main stack pointer) Cortex processor register */ __ASM void __set_MSP(uint32_t mainStackPointer) { msr msp, r0 bx lr } /** * @brief Reverse byte order in unsigned short value * * @param value value to reverse * @return reversed value * * Reverse byte order in unsigned short value */ __ASM uint32_t __REV16(uint16_t value) { rev16 r0, r0 bx lr } /** * @brief Reverse byte order in signed short value with sign extension to integer * * @param value value to reverse * @return reversed value * * Reverse byte order in signed short value with sign extension to integer */ __ASM int32_t __REVSH(int16_t value) { revsh r0, r0 bx lr } #if (__ARMCC_VERSION < 400000) /** * @brief Remove the exclusive lock created by ldrex * * Removes the exclusive lock which is created by ldrex. */ __ASM void __CLREX(void) { clrex } /** * @brief Return the Base Priority value * * @return BasePriority * * Return the content of the base priority register */ __ASM uint32_t __get_BASEPRI(void) { mrs r0, basepri bx lr } /** * @brief Set the Base Priority value * * @param basePri BasePriority * * Set the base priority register */ __ASM void __set_BASEPRI(uint32_t basePri) { msr basepri, r0 bx lr } /** * @brief Return the Priority Mask value * * @return PriMask * * Return state of the priority mask bit from the priority mask register */ __ASM uint32_t __get_PRIMASK(void) { mrs r0, primask bx lr } /** * @brief Set the Priority Mask value * * @param priMask PriMask * * Set the priority mask bit in the priority mask register */ __ASM void __set_PRIMASK(uint32_t priMask) { msr primask, r0 bx lr } /** * @brief Return the Fault Mask value * * @return FaultMask * * Return the content of the fault mask register */ __ASM uint32_t __get_FAULTMASK(void) { mrs r0, faultmask bx lr } /** * @brief Set the Fault Mask value * * @param faultMask faultMask value * * Set the fault mask register */ __ASM void __set_FAULTMASK(uint32_t faultMask) { msr faultmask, r0 bx lr } /** * @brief Return the Control Register value * * @return Control value * * Return the content of the control register */ __ASM uint32_t __get_CONTROL(void) { mrs r0, control bx lr } /** * @brief Set the Control Register value * * @param control Control value * * Set the control register */ __ASM void __set_CONTROL(uint32_t control) { msr control, r0 bx lr } #endif /* __ARMCC_VERSION */ #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ /* IAR iccarm specific functions */ #pragma diag_suppress=Pe940 /** * @brief Return the Process Stack Pointer * * @return ProcessStackPointer * * Return the actual process stack pointer */ uint32_t __get_PSP(void) { __ASM("mrs r0, psp"); __ASM("bx lr"); } /** * @brief Set the Process Stack Pointer * * @param topOfProcStack Process Stack Pointer * * Assign the value ProcessStackPointer to the MSP * (process stack pointer) Cortex processor register */ void __set_PSP(uint32_t topOfProcStack) { __ASM("msr psp, r0"); __ASM("bx lr"); } /** * @brief Return the Main Stack Pointer * * @return Main Stack Pointer * * Return the current value of the MSP (main stack pointer) * Cortex processor register */ uint32_t __get_MSP(void) { __ASM("mrs r0, msp"); __ASM("bx lr"); } /** * @brief Set the Main Stack Pointer * * @param topOfMainStack Main Stack Pointer * * Assign the value mainStackPointer to the MSP * (main stack pointer) Cortex processor register */ void __set_MSP(uint32_t topOfMainStack) { __ASM("msr msp, r0"); __ASM("bx lr"); } /** * @brief Reverse byte order in unsigned short value * * @param value value to reverse * @return reversed value * * Reverse byte order in unsigned short value */ uint32_t __REV16(uint16_t value) { __ASM("rev16 r0, r0"); __ASM("bx lr"); } /** * @brief Reverse bit order of value * * @param value value to reverse * @return reversed value * * Reverse bit order of value */ uint32_t __RBIT(uint32_t value) { __ASM("rbit r0, r0"); __ASM("bx lr"); } /** * @brief LDR Exclusive (8 bit) * * @param *addr address pointer * @return value of (*address) * * Exclusive LDR command for 8 bit values) */ uint8_t __LDREXB(uint8_t *addr) { __ASM("ldrexb r0, [r0]"); __ASM("bx lr"); } /** * @brief LDR Exclusive (16 bit) * * @param *addr address pointer * @return value of (*address) * * Exclusive LDR command for 16 bit values */ uint16_t __LDREXH(uint16_t *addr) { __ASM("ldrexh r0, [r0]"); __ASM("bx lr"); } /** * @brief LDR Exclusive (32 bit) * * @param *addr address pointer * @return value of (*address) * * Exclusive LDR command for 32 bit values */ uint32_t __LDREXW(uint32_t *addr) { __ASM("ldrex r0, [r0]"); __ASM("bx lr"); } /** * @brief STR Exclusive (8 bit) * * @param value value to store * @param *addr address pointer * @return successful / failed * * Exclusive STR command for 8 bit values */ uint32_t __STREXB(uint8_t value, uint8_t *addr) { __ASM("strexb r0, r0, [r1]"); __ASM("bx lr"); } /** * @brief STR Exclusive (16 bit) * * @param value value to store * @param *addr address pointer * @return successful / failed * * Exclusive STR command for 16 bit values */ uint32_t __STREXH(uint16_t value, uint16_t *addr) { __ASM("strexh r0, r0, [r1]"); __ASM("bx lr"); } /** * @brief STR Exclusive (32 bit) * * @param value value to store * @param *addr address pointer * @return successful / failed * * Exclusive STR command for 32 bit values */ uint32_t __STREXW(uint32_t value, uint32_t *addr) { __ASM("strex r0, r0, [r1]"); __ASM("bx lr"); } #pragma diag_default=Pe940 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ /* GNU gcc specific functions */ /** * @brief Return the Process Stack Pointer * * @return ProcessStackPointer * * Return the actual process stack pointer */ uint32_t __get_PSP(void) __attribute__( ( naked ) ); uint32_t __get_PSP(void) { uint32_t result=0; __ASM volatile ("MRS %0, psp\n\t" "MOV r0, %0 \n\t" "BX lr \n\t" : "=r" (result) ); return(result); } /** * @brief Set the Process Stack Pointer * * @param topOfProcStack Process Stack Pointer * * Assign the value ProcessStackPointer to the MSP * (process stack pointer) Cortex processor register */ void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); void __set_PSP(uint32_t topOfProcStack) { __ASM volatile ("MSR psp, %0\n\t" "BX lr \n\t" : : "r" (topOfProcStack) ); } /** * @brief Return the Main Stack Pointer * * @return Main Stack Pointer * * Return the current value of the MSP (main stack pointer) * Cortex processor register */ uint32_t __get_MSP(void) __attribute__( ( naked ) ); uint32_t __get_MSP(void) { uint32_t result=0; __ASM volatile ("MRS %0, msp\n\t" "MOV r0, %0 \n\t" "BX lr \n\t" : "=r" (result) ); return(result); } /** * @brief Set the Main Stack Pointer * * @param topOfMainStack Main Stack Pointer * * Assign the value mainStackPointer to the MSP * (main stack pointer) Cortex processor register */ void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); void __set_MSP(uint32_t topOfMainStack) { __ASM volatile ("MSR msp, %0\n\t" "BX lr \n\t" : : "r" (topOfMainStack) ); } /** * @brief Return the Base Priority value * * @return BasePriority * * Return the content of the base priority register */ uint32_t __get_BASEPRI(void) { uint32_t result=0; __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); return(result); } /** * @brief Set the Base Priority value * * @param basePri BasePriority * * Set the base priority register */ void __set_BASEPRI(uint32_t value) { __ASM volatile ("MSR basepri, %0" : : "r" (value) ); } /** * @brief Return the Priority Mask value * * @return PriMask * * Return state of the priority mask bit from the priority mask register */ uint32_t __get_PRIMASK(void) { uint32_t result=0; __ASM volatile ("MRS %0, primask" : "=r" (result) ); return(result); } /** * @brief Set the Priority Mask value * * @param priMask PriMask * * Set the priority mask bit in the priority mask register */ void __set_PRIMASK(uint32_t priMask) { __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); } /** * @brief Return the Fault Mask value * * @return FaultMask * * Return the content of the fault mask register */ uint32_t __get_FAULTMASK(void) { uint32_t result=0; __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); return(result); } /** * @brief Set the Fault Mask value * * @param faultMask faultMask value * * Set the fault mask register */ void __set_FAULTMASK(uint32_t faultMask) { __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); } /** * @brief Return the Control Register value * * @return Control value * * Return the content of the control register */ uint32_t __get_CONTROL(void) { uint32_t result=0; __ASM volatile ("MRS %0, control" : "=r" (result) ); return(result); } /** * @brief Set the Control Register value * * @param control Control value * * Set the control register */ void __set_CONTROL(uint32_t control) { __ASM volatile ("MSR control, %0" : : "r" (control) ); } /** * @brief Reverse byte order in integer value * * @param value value to reverse * @return reversed value * * Reverse byte order in integer value */ uint32_t __REV(uint32_t value) { uint32_t result=0; __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); return(result); } /** * @brief Reverse byte order in unsigned short value * * @param value value to reverse * @return reversed value * * Reverse byte order in unsigned short value */ uint32_t __REV16(uint16_t value) { uint32_t result=0; __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); return(result); } /** * @brief Reverse byte order in signed short value with sign extension to integer * * @param value value to reverse * @return reversed value * * Reverse byte order in signed short value with sign extension to integer */ int32_t __REVSH(int16_t value) { uint32_t result=0; __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); return(result); } /** * @brief Reverse bit order of value * * @param value value to reverse * @return reversed value * * Reverse bit order of value */ uint32_t __RBIT(uint32_t value) { uint32_t result=0; __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); return(result); } /** * @brief LDR Exclusive (8 bit) * * @param *addr address pointer * @return value of (*address) * * Exclusive LDR command for 8 bit value */ uint8_t __LDREXB(uint8_t *addr) { uint8_t result=0; __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); return(result); } /** * @brief LDR Exclusive (16 bit) * * @param *addr address pointer * @return value of (*address) * * Exclusive LDR command for 16 bit values */ uint16_t __LDREXH(uint16_t *addr) { uint16_t result=0; __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); return(result); } /** * @brief LDR Exclusive (32 bit) * * @param *addr address pointer * @return value of (*address) * * Exclusive LDR command for 32 bit values */ uint32_t __LDREXW(uint32_t *addr) { uint32_t result=0; __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); return(result); } /** * @brief STR Exclusive (8 bit) * * @param value value to store * @param *addr address pointer * @return successful / failed * * Exclusive STR command for 8 bit values */ uint32_t __STREXB(uint8_t value, uint8_t *addr) { uint32_t result=0; __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); return(result); } /** * @brief STR Exclusive (16 bit) * * @param value value to store * @param *addr address pointer * @return successful / failed * * Exclusive STR command for 16 bit values */ uint32_t __STREXH(uint16_t value, uint16_t *addr) { uint32_t result=0; __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); return(result); } /** * @brief STR Exclusive (32 bit) * * @param value value to store * @param *addr address pointer * @return successful / failed * * Exclusive STR command for 32 bit values */ uint32_t __STREXW(uint32_t value, uint32_t *addr) { uint32_t result=0; __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); return(result); } #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ /* TASKING carm specific functions */ /* * The CMSIS functions have been implemented as intrinsics in the compiler. * Please use "carm -?i" to get an up to date list of all instrinsics, * Including the CMSIS ones. */ #endif /**************************************************************************//** * @file core_cm3.c * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File * @version V1.30 * @date 30. October 2009 * * @note * Copyright (C) 2009 ARM Limited. All rights reserved. * * @par * ARM Limited (ARM) is supplying this software for use with Cortex-M * processor based microcontrollers. This file can be freely distributed * within development tools that are supporting such ARM based processors. * * @par * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. * ******************************************************************************/ #include <stdint.h> /* define compiler specific symbols */ #if defined ( __CC_ARM ) #define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #elif defined ( __ICCARM__ ) #define __ASM __asm /*!< asm keyword for IAR Compiler */ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ #elif defined ( __GNUC__ ) #define __ASM __asm /*!< asm keyword for GNU Compiler */ #define __INLINE inline /*!< inline keyword for GNU Compiler */ #elif defined ( __TASKING__ ) #define __ASM __asm /*!< asm keyword for TASKING Compiler */ #define __INLINE inline /*!< inline keyword for TASKING Compiler */ #endif /* ################### Compiler specific Intrinsics ########################### */ #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ /* ARM armcc specific functions */ /** * @brief Return the Process Stack Pointer * * @return ProcessStackPointer * * Return the actual process stack pointer */ __ASM uint32_t __get_PSP(void) { mrs r0, psp bx lr } /** * @brief Set the Process Stack Pointer * * @param topOfProcStack Process Stack Pointer * * Assign the value ProcessStackPointer to the MSP * (process stack pointer) Cortex processor register */ __ASM void __set_PSP(uint32_t topOfProcStack) { msr psp, r0 bx lr } /** * @brief Return the Main Stack Pointer * * @return Main Stack Pointer * * Return the current value of the MSP (main stack pointer) * Cortex processor register */ __ASM uint32_t __get_MSP(void) { mrs r0, msp bx lr } /** * @brief Set the Main Stack Pointer * * @param topOfMainStack Main Stack Pointer * * Assign the value mainStackPointer to the MSP * (main stack pointer) Cortex processor register */ __ASM void __set_MSP(uint32_t mainStackPointer) { msr msp, r0 bx lr } /** * @brief Reverse byte order in unsigned short value * * @param value value to reverse * @return reversed value * * Reverse byte order in unsigned short value */ __ASM uint32_t __REV16(uint16_t value) { rev16 r0, r0 bx lr } /** * @brief Reverse byte order in signed short value with sign extension to integer * * @param value value to reverse * @return reversed value * * Reverse byte order in signed short value with sign extension to integer */ __ASM int32_t __REVSH(int16_t value) { revsh r0, r0 bx lr } #if (__ARMCC_VERSION < 400000) /** * @brief Remove the exclusive lock created by ldrex * * Removes the exclusive lock which is created by ldrex. */ __ASM void __CLREX(void) { clrex } /** * @brief Return the Base Priority value * * @return BasePriority * * Return the content of the base priority register */ __ASM uint32_t __get_BASEPRI(void) { mrs r0, basepri bx lr } /** * @brief Set the Base Priority value * * @param basePri BasePriority * * Set the base priority register */ __ASM void __set_BASEPRI(uint32_t basePri) { msr basepri, r0 bx lr } /** * @brief Return the Priority Mask value * * @return PriMask * * Return state of the priority mask bit from the priority mask register */ __ASM uint32_t __get_PRIMASK(void) { mrs r0, primask bx lr } /** * @brief Set the Priority Mask value * * @param priMask PriMask * * Set the priority mask bit in the priority mask register */ __ASM void __set_PRIMASK(uint32_t priMask) { msr primask, r0 bx lr } /** * @brief Return the Fault Mask value * * @return FaultMask * * Return the content of the fault mask register */ __ASM uint32_t __get_FAULTMASK(void) { mrs r0, faultmask bx lr } /** * @brief Set the Fault Mask value * * @param faultMask faultMask value * * Set the fault mask register */ __ASM void __set_FAULTMASK(uint32_t faultMask) { msr faultmask, r0 bx lr } /** * @brief Return the Control Register value * * @return Control value * * Return the content of the control register */ __ASM uint32_t __get_CONTROL(void) { mrs r0, control bx lr } /** * @brief Set the Control Register value * * @param control Control value * * Set the control register */ __ASM void __set_CONTROL(uint32_t control) { msr control, r0 bx lr } #endif /* __ARMCC_VERSION */ #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ /* IAR iccarm specific functions */ #pragma diag_suppress=Pe940 /** * @brief Return the Process Stack Pointer * * @return ProcessStackPointer * * Return the actual process stack pointer */ uint32_t __get_PSP(void) { __ASM("mrs r0, psp"); __ASM("bx lr"); } /** * @brief Set the Process Stack Pointer * * @param topOfProcStack Process Stack Pointer * * Assign the value ProcessStackPointer to the MSP * (process stack pointer) Cortex processor register */ void __set_PSP(uint32_t topOfProcStack) { __ASM("msr psp, r0"); __ASM("bx lr"); } /** * @brief Return the Main Stack Pointer * * @return Main Stack Pointer * * Return the current value of the MSP (main stack pointer) * Cortex processor register */ uint32_t __get_MSP(void) { __ASM("mrs r0, msp"); __ASM("bx lr"); } /** * @brief Set the Main Stack Pointer * * @param topOfMainStack Main Stack Pointer * * Assign the value mainStackPointer to the MSP * (main stack pointer) Cortex processor register */ void __set_MSP(uint32_t topOfMainStack) { __ASM("msr msp, r0"); __ASM("bx lr"); } /** * @brief Reverse byte order in unsigned short value * * @param value value to reverse * @return reversed value * * Reverse byte order in unsigned short value */ uint32_t __REV16(uint16_t value) { __ASM("rev16 r0, r0"); __ASM("bx lr"); } /** * @brief Reverse bit order of value * * @param value value to reverse * @return reversed value * * Reverse bit order of value */ uint32_t __RBIT(uint32_t value) { __ASM("rbit r0, r0"); __ASM("bx lr"); } /** * @brief LDR Exclusive (8 bit) * * @param *addr address pointer * @return value of (*address) * * Exclusive LDR command for 8 bit values) */ uint8_t __LDREXB(uint8_t *addr) { __ASM("ldrexb r0, [r0]"); __ASM("bx lr"); } /** * @brief LDR Exclusive (16 bit) * * @param *addr address pointer * @return value of (*address) * * Exclusive LDR command for 16 bit values */ uint16_t __LDREXH(uint16_t *addr) { __ASM("ldrexh r0, [r0]"); __ASM("bx lr"); } /** * @brief LDR Exclusive (32 bit) * * @param *addr address pointer * @return value of (*address) * * Exclusive LDR command for 32 bit values */ uint32_t __LDREXW(uint32_t *addr) { __ASM("ldrex r0, [r0]"); __ASM("bx lr"); } /** * @brief STR Exclusive (8 bit) * * @param value value to store * @param *addr address pointer * @return successful / failed * * Exclusive STR command for 8 bit values */ uint32_t __STREXB(uint8_t value, uint8_t *addr) { __ASM("strexb r0, r0, [r1]"); __ASM("bx lr"); } /** * @brief STR Exclusive (16 bit) * * @param value value to store * @param *addr address pointer * @return successful / failed * * Exclusive STR command for 16 bit values */ uint32_t __STREXH(uint16_t value, uint16_t *addr) { __ASM("strexh r0, r0, [r1]"); __ASM("bx lr"); } /** * @brief STR Exclusive (32 bit) * * @param value value to store * @param *addr address pointer * @return successful / failed * * Exclusive STR command for 32 bit values */ uint32_t __STREXW(uint32_t value, uint32_t *addr) { __ASM("strex r0, r0, [r1]"); __ASM("bx lr"); } #pragma diag_default=Pe940 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ /* GNU gcc specific functions */ /** * @brief Return the Process Stack Pointer * * @return ProcessStackPointer * * Return the actual process stack pointer */ uint32_t __get_PSP(void) __attribute__( ( naked ) ); uint32_t __get_PSP(void) { uint32_t result=0; __ASM volatile ("MRS %0, psp\n\t" "MOV r0, %0 \n\t" "BX lr \n\t" : "=r" (result) ); return(result); } /** * @brief Set the Process Stack Pointer * * @param topOfProcStack Process Stack Pointer * * Assign the value ProcessStackPointer to the MSP * (process stack pointer) Cortex processor register */ void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); void __set_PSP(uint32_t topOfProcStack) { __ASM volatile ("MSR psp, %0\n\t" "BX lr \n\t" : : "r" (topOfProcStack) ); } /** * @brief Return the Main Stack Pointer * * @return Main Stack Pointer * * Return the current value of the MSP (main stack pointer) * Cortex processor register */ uint32_t __get_MSP(void) __attribute__( ( naked ) ); uint32_t __get_MSP(void) { uint32_t result=0; __ASM volatile ("MRS %0, msp\n\t" "MOV r0, %0 \n\t" "BX lr \n\t" : "=r" (result) ); return(result); } /** * @brief Set the Main Stack Pointer * * @param topOfMainStack Main Stack Pointer * * Assign the value mainStackPointer to the MSP * (main stack pointer) Cortex processor register */ void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); void __set_MSP(uint32_t topOfMainStack) { __ASM volatile ("MSR msp, %0\n\t" "BX lr \n\t" : : "r" (topOfMainStack) ); } /** * @brief Return the Base Priority value * * @return BasePriority * * Return the content of the base priority register */ uint32_t __get_BASEPRI(void) { uint32_t result=0; __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); return(result); } /** * @brief Set the Base Priority value * * @param basePri BasePriority * * Set the base priority register */ void __set_BASEPRI(uint32_t value) { __ASM volatile ("MSR basepri, %0" : : "r" (value) ); } /** * @brief Return the Priority Mask value * * @return PriMask * * Return state of the priority mask bit from the priority mask register */ uint32_t __get_PRIMASK(void) { uint32_t result=0; __ASM volatile ("MRS %0, primask" : "=r" (result) ); return(result); } /** * @brief Set the Priority Mask value * * @param priMask PriMask * * Set the priority mask bit in the priority mask register */ void __set_PRIMASK(uint32_t priMask) { __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); } /** * @brief Return the Fault Mask value * * @return FaultMask * * Return the content of the fault mask register */ uint32_t __get_FAULTMASK(void) { uint32_t result=0; __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); return(result); } /** * @brief Set the Fault Mask value * * @param faultMask faultMask value * * Set the fault mask register */ void __set_FAULTMASK(uint32_t faultMask) { __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); } /** * @brief Return the Control Register value * * @return Control value * * Return the content of the control register */ uint32_t __get_CONTROL(void) { uint32_t result=0; __ASM volatile ("MRS %0, control" : "=r" (result) ); return(result); } /** * @brief Set the Control Register value * * @param control Control value * * Set the control register */ void __set_CONTROL(uint32_t control) { __ASM volatile ("MSR control, %0" : : "r" (control) ); } /** * @brief Reverse byte order in integer value * * @param value value to reverse * @return reversed value * * Reverse byte order in integer value */ uint32_t __REV(uint32_t value) { uint32_t result=0; __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); return(result); } /** * @brief Reverse byte order in unsigned short value * * @param value value to reverse * @return reversed value * * Reverse byte order in unsigned short value */ uint32_t __REV16(uint16_t value) { uint32_t result=0; __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); return(result); } /** * @brief Reverse byte order in signed short value with sign extension to integer * * @param value value to reverse * @return reversed value * * Reverse byte order in signed short value with sign extension to integer */ int32_t __REVSH(int16_t value) { uint32_t result=0; __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); return(result); } /** * @brief Reverse bit order of value * * @param value value to reverse * @return reversed value * * Reverse bit order of value */ uint32_t __RBIT(uint32_t value) { uint32_t result=0; __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); return(result); } /** * @brief LDR Exclusive (8 bit) * * @param *addr address pointer * @return value of (*address) * * Exclusive LDR command for 8 bit value */ uint8_t __LDREXB(uint8_t *addr) { uint8_t result=0; __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); return(result); } /** * @brief LDR Exclusive (16 bit) * * @param *addr address pointer * @return value of (*address) * * Exclusive LDR command for 16 bit values */ uint16_t __LDREXH(uint16_t *addr) { uint16_t result=0; __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); return(result); } /** * @brief LDR Exclusive (32 bit) * * @param *addr address pointer * @return value of (*address) * * Exclusive LDR command for 32 bit values */ uint32_t __LDREXW(uint32_t *addr) { uint32_t result=0; __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); return(result); } /** * @brief STR Exclusive (8 bit) * * @param value value to store * @param *addr address pointer * @return successful / failed * * Exclusive STR command for 8 bit values */ uint32_t __STREXB(uint8_t value, uint8_t *addr) { uint32_t result=0; __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); return(result); } /** * @brief STR Exclusive (16 bit) * * @param value value to store * @param *addr address pointer * @return successful / failed * * Exclusive STR command for 16 bit values */ uint32_t __STREXH(uint16_t value, uint16_t *addr) { uint32_t result=0; __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); return(result); } /** * @brief STR Exclusive (32 bit) * * @param value value to store * @param *addr address pointer * @return successful / failed * * Exclusive STR command for 32 bit values */ uint32_t __STREXW(uint32_t value, uint32_t *addr) { uint32_t result=0; __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); return(result); } #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ /* TASKING carm specific functions */ /* * The CMSIS functions have been implemented as intrinsics in the compiler. * Please use "carm -?i" to get an up to date list of all instrinsics, * Including the CMSIS ones. */ #endif src/bare_test/1.Led/cmsis/core_cm3.h
File was renamed from src/bare_test/stm32_key/cmsis/core_cm3.h @@ -1,1818 +1,1818 @@ /**************************************************************************//** * @file core_cm3.h * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File * @version V1.30 * @date 30. October 2009 * * @note * Copyright (C) 2009 ARM Limited. All rights reserved. * * @par * ARM Limited (ARM) is supplying this software for use with Cortex-M * processor based microcontrollers. This file can be freely distributed * within development tools that are supporting such ARM based processors. * * @par * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. * ******************************************************************************/ #ifndef __CM3_CORE_H__ #define __CM3_CORE_H__ /** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration * * List of Lint messages which will be suppressed and not shown: * - Error 10: \n * register uint32_t __regBasePri __asm("basepri"); \n * Error 10: Expecting ';' * . * - Error 530: \n * return(__regBasePri); \n * Warning 530: Symbol '__regBasePri' (line 264) not initialized * . * - Error 550: \n * __regBasePri = (basePri & 0x1ff); \n * Warning 550: Symbol '__regBasePri' (line 271) not accessed * . * - Error 754: \n * uint32_t RESERVED0[24]; \n * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced * . * - Error 750: \n * #define __CM3_CORE_H__ \n * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced * . * - Error 528: \n * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced * . * - Error 751: \n * } InterruptType_Type; \n * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced * . * Note: To re-enable a Message, insert a space before 'lint' * * */ /*lint -save */ /*lint -e10 */ /*lint -e530 */ /*lint -e550 */ /*lint -e754 */ /*lint -e750 */ /*lint -e528 */ /*lint -e751 */ /** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions This file defines all structures and symbols for CMSIS core: - CMSIS version number - Cortex-M core registers and bitfields - Cortex-M core peripheral base address @{ */ #ifdef __cplusplus extern "C" { #endif #define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ #define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ #define __CORTEX_M (0x03) /*!< Cortex core */ #include <stdint.h> /* Include standard types */ #if defined (__ICCARM__) #include <intrinsics.h> /* IAR Intrinsics */ #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ #endif /** * IO definitions * * define access restrictions to peripheral registers */ #ifdef __cplusplus #define __I volatile /*!< defines 'read only' permissions */ #else #define __I volatile const /*!< defines 'read only' permissions */ #endif #define __O volatile /*!< defines 'write only' permissions */ #define __IO volatile /*!< defines 'read / write' permissions */ /******************************************************************************* * Register Abstraction ******************************************************************************/ /** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register @{ */ /** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC memory mapped structure for Nested Vectored Interrupt Controller (NVIC) @{ */ typedef struct { __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ uint32_t RESERVED0[24]; __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ uint32_t RSERVED1[24]; __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ uint32_t RESERVED2[24]; __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ uint32_t RESERVED3[24]; __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ uint32_t RESERVED4[56]; __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644]; __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ } NVIC_Type; /*@}*/ /* end of group CMSIS_CM3_NVIC */ /** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB memory mapped structure for System Control Block (SCB) @{ */ typedef struct { __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ #define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Registers Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* SCB Hard Fault Status Registers Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ /*@}*/ /* end of group CMSIS_CM3_SCB */ /** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick memory mapped structure for SysTick @{ */ typedef struct { __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ /*@}*/ /* end of group CMSIS_CM3_SysTick */ /** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM memory mapped structure for Instrumentation Trace Macrocell (ITM) @{ */ typedef struct { __O union { __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ uint32_t RESERVED0[864]; __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ uint32_t RESERVED1[15]; __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ uint32_t RESERVED2[15]; __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ uint32_t RESERVED3[29]; __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ uint32_t RESERVED4[43]; __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ uint32_t RESERVED5[6]; __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ #define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ #define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ #define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ #define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_CM3_ITM */ /** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type memory mapped structure for Interrupt Type @{ */ typedef struct { uint32_t RESERVED0; __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ #if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ #else uint32_t RESERVED1; #endif } InterruptType_Type; /* Interrupt Controller Type Register Definitions */ #define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ #define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ #define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ #define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ #define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ #define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ #define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ #define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ /*@}*/ /* end of group CMSIS_CM3_InterruptType */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) /** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU memory mapped structure for Memory Protection Unit (MPU) @{ */ typedef struct { __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; /* MPU Type Register */ #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register */ #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register */ #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register */ #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register */ #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ #define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ #define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ #define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ #define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ #define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ #define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ #define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ #define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ #define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ /*@}*/ /* end of group CMSIS_CM3_MPU */ #endif /** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug memory mapped structure for Core Debug Register @{ */ typedef struct { __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register */ #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register */ #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register */ #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@}*/ /* end of group CMSIS_CM3_CoreDebug */ /* Memory mapping of Cortex-M3 Hardware */ #define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000) /*!< ITM Base Address */ #define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ #define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ #define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ #endif /*@}*/ /* end of group CMSIS_CM3_core_register */ /******************************************************************************* * Hardware Abstraction Layer ******************************************************************************/ #if defined ( __CC_ARM ) #define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #elif defined ( __ICCARM__ ) #define __ASM __asm /*!< asm keyword for IAR Compiler */ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ #elif defined ( __GNUC__ ) #define __ASM __asm /*!< asm keyword for GNU Compiler */ #define __INLINE inline /*!< inline keyword for GNU Compiler */ #elif defined ( __TASKING__ ) #define __ASM __asm /*!< asm keyword for TASKING Compiler */ #define __INLINE inline /*!< inline keyword for TASKING Compiler */ #endif /* ################### Compiler specific Intrinsics ########################### */ #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ /* ARM armcc specific functions */ #define __enable_fault_irq __enable_fiq #define __disable_fault_irq __disable_fiq #define __NOP __nop #define __WFI __wfi #define __WFE __wfe #define __SEV __sev #define __ISB() __isb(0) #define __DSB() __dsb(0) #define __DMB() __dmb(0) #define __REV __rev #define __RBIT __rbit #define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) #define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) #define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) #define __STREXB(value, ptr) __strex(value, ptr) #define __STREXH(value, ptr) __strex(value, ptr) #define __STREXW(value, ptr) __strex(value, ptr) /* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ /* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ /* intrinsic void __enable_irq(); */ /* intrinsic void __disable_irq(); */ /** * @brief Return the Process Stack Pointer * * @return ProcessStackPointer * * Return the actual process stack pointer */ extern uint32_t __get_PSP(void); /** * @brief Set the Process Stack Pointer * * @param topOfProcStack Process Stack Pointer * * Assign the value ProcessStackPointer to the MSP * (process stack pointer) Cortex processor register */ extern void __set_PSP(uint32_t topOfProcStack); /** * @brief Return the Main Stack Pointer * * @return Main Stack Pointer * * Return the current value of the MSP (main stack pointer) * Cortex processor register */ extern uint32_t __get_MSP(void); /** * @brief Set the Main Stack Pointer * * @param topOfMainStack Main Stack Pointer * * Assign the value mainStackPointer to the MSP * (main stack pointer) Cortex processor register */ extern void __set_MSP(uint32_t topOfMainStack); /** * @brief Reverse byte order in unsigned short value * * @param value value to reverse * @return reversed value * * Reverse byte order in unsigned short value */ extern uint32_t __REV16(uint16_t value); /** * @brief Reverse byte order in signed short value with sign extension to integer * * @param value value to reverse * @return reversed value * * Reverse byte order in signed short value with sign extension to integer */ extern int32_t __REVSH(int16_t value); #if (__ARMCC_VERSION < 400000) /** * @brief Remove the exclusive lock created by ldrex * * Removes the exclusive lock which is created by ldrex. */ extern void __CLREX(void); /** * @brief Return the Base Priority value * * @return BasePriority * * Return the content of the base priority register */ extern uint32_t __get_BASEPRI(void); /** * @brief Set the Base Priority value * * @param basePri BasePriority * * Set the base priority register */ extern void __set_BASEPRI(uint32_t basePri); /** * @brief Return the Priority Mask value * * @return PriMask * * Return state of the priority mask bit from the priority mask register */ extern uint32_t __get_PRIMASK(void); /** * @brief Set the Priority Mask value * * @param priMask PriMask * * Set the priority mask bit in the priority mask register */ extern void __set_PRIMASK(uint32_t priMask); /** * @brief Return the Fault Mask value * * @return FaultMask * * Return the content of the fault mask register */ extern uint32_t __get_FAULTMASK(void); /** * @brief Set the Fault Mask value * * @param faultMask faultMask value * * Set the fault mask register */ extern void __set_FAULTMASK(uint32_t faultMask); /** * @brief Return the Control Register value * * @return Control value * * Return the content of the control register */ extern uint32_t __get_CONTROL(void); /** * @brief Set the Control Register value * * @param control Control value * * Set the control register */ extern void __set_CONTROL(uint32_t control); #else /* (__ARMCC_VERSION >= 400000) */ /** * @brief Remove the exclusive lock created by ldrex * * Removes the exclusive lock which is created by ldrex. */ #define __CLREX __clrex /** * @brief Return the Base Priority value * * @return BasePriority * * Return the content of the base priority register */ static __INLINE uint32_t __get_BASEPRI(void) { register uint32_t __regBasePri __ASM("basepri"); return(__regBasePri); } /** * @brief Set the Base Priority value * * @param basePri BasePriority * * Set the base priority register */ static __INLINE void __set_BASEPRI(uint32_t basePri) { register uint32_t __regBasePri __ASM("basepri"); __regBasePri = (basePri & 0xff); } /** * @brief Return the Priority Mask value * * @return PriMask * * Return state of the priority mask bit from the priority mask register */ static __INLINE uint32_t __get_PRIMASK(void) { register uint32_t __regPriMask __ASM("primask"); return(__regPriMask); } /** * @brief Set the Priority Mask value * * @param priMask PriMask * * Set the priority mask bit in the priority mask register */ static __INLINE void __set_PRIMASK(uint32_t priMask) { register uint32_t __regPriMask __ASM("primask"); __regPriMask = (priMask); } /** * @brief Return the Fault Mask value * * @return FaultMask * * Return the content of the fault mask register */ static __INLINE uint32_t __get_FAULTMASK(void) { register uint32_t __regFaultMask __ASM("faultmask"); return(__regFaultMask); } /** * @brief Set the Fault Mask value * * @param faultMask faultMask value * * Set the fault mask register */ static __INLINE void __set_FAULTMASK(uint32_t faultMask) { register uint32_t __regFaultMask __ASM("faultmask"); __regFaultMask = (faultMask & 1); } /** * @brief Return the Control Register value * * @return Control value * * Return the content of the control register */ static __INLINE uint32_t __get_CONTROL(void) { register uint32_t __regControl __ASM("control"); return(__regControl); } /** * @brief Set the Control Register value * * @param control Control value * * Set the control register */ static __INLINE void __set_CONTROL(uint32_t control) { register uint32_t __regControl __ASM("control"); __regControl = control; } #endif /* __ARMCC_VERSION */ #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ /* IAR iccarm specific functions */ #define __enable_irq __enable_interrupt /*!< global Interrupt enable */ #define __disable_irq __disable_interrupt /*!< global Interrupt disable */ static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } #define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ static __INLINE void __WFI() { __ASM ("wfi"); } static __INLINE void __WFE() { __ASM ("wfe"); } static __INLINE void __SEV() { __ASM ("sev"); } static __INLINE void __CLREX() { __ASM ("clrex"); } /* intrinsic void __ISB(void) */ /* intrinsic void __DSB(void) */ /* intrinsic void __DMB(void) */ /* intrinsic void __set_PRIMASK(); */ /* intrinsic void __get_PRIMASK(); */ /* intrinsic void __set_FAULTMASK(); */ /* intrinsic void __get_FAULTMASK(); */ /* intrinsic uint32_t __REV(uint32_t value); */ /* intrinsic uint32_t __REVSH(uint32_t value); */ /* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ /* intrinsic unsigned long __LDREX(unsigned long *); */ /** * @brief Return the Process Stack Pointer * * @return ProcessStackPointer * * Return the actual process stack pointer */ extern uint32_t __get_PSP(void); /** * @brief Set the Process Stack Pointer * * @param topOfProcStack Process Stack Pointer * * Assign the value ProcessStackPointer to the MSP * (process stack pointer) Cortex processor register */ extern void __set_PSP(uint32_t topOfProcStack); /** * @brief Return the Main Stack Pointer * * @return Main Stack Pointer * * Return the current value of the MSP (main stack pointer) * Cortex processor register */ extern uint32_t __get_MSP(void); /** * @brief Set the Main Stack Pointer * * @param topOfMainStack Main Stack Pointer * * Assign the value mainStackPointer to the MSP * (main stack pointer) Cortex processor register */ extern void __set_MSP(uint32_t topOfMainStack); /** * @brief Reverse byte order in unsigned short value * * @param value value to reverse * @return reversed value * * Reverse byte order in unsigned short value */ extern uint32_t __REV16(uint16_t value); /** * @brief Reverse bit order of value * * @param value value to reverse * @return reversed value * * Reverse bit order of value */ extern uint32_t __RBIT(uint32_t value); /** * @brief LDR Exclusive (8 bit) * * @param *addr address pointer * @return value of (*address) * * Exclusive LDR command for 8 bit values) */ extern uint8_t __LDREXB(uint8_t *addr); /** * @brief LDR Exclusive (16 bit) * * @param *addr address pointer * @return value of (*address) * * Exclusive LDR command for 16 bit values */ extern uint16_t __LDREXH(uint16_t *addr); /** * @brief LDR Exclusive (32 bit) * * @param *addr address pointer * @return value of (*address) * * Exclusive LDR command for 32 bit values */ extern uint32_t __LDREXW(uint32_t *addr); /** * @brief STR Exclusive (8 bit) * * @param value value to store * @param *addr address pointer * @return successful / failed * * Exclusive STR command for 8 bit values */ extern uint32_t __STREXB(uint8_t value, uint8_t *addr); /** * @brief STR Exclusive (16 bit) * * @param value value to store * @param *addr address pointer * @return successful / failed * * Exclusive STR command for 16 bit values */ extern uint32_t __STREXH(uint16_t value, uint16_t *addr); /** * @brief STR Exclusive (32 bit) * * @param value value to store * @param *addr address pointer * @return successful / failed * * Exclusive STR command for 32 bit values */ extern uint32_t __STREXW(uint32_t value, uint32_t *addr); #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ /* GNU gcc specific functions */ static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } static __INLINE void __NOP() { __ASM volatile ("nop"); } static __INLINE void __WFI() { __ASM volatile ("wfi"); } static __INLINE void __WFE() { __ASM volatile ("wfe"); } static __INLINE void __SEV() { __ASM volatile ("sev"); } static __INLINE void __ISB() { __ASM volatile ("isb"); } static __INLINE void __DSB() { __ASM volatile ("dsb"); } static __INLINE void __DMB() { __ASM volatile ("dmb"); } static __INLINE void __CLREX() { __ASM volatile ("clrex"); } /** * @brief Return the Process Stack Pointer * * @return ProcessStackPointer * * Return the actual process stack pointer */ extern uint32_t __get_PSP(void); /** * @brief Set the Process Stack Pointer * * @param topOfProcStack Process Stack Pointer * * Assign the value ProcessStackPointer to the MSP * (process stack pointer) Cortex processor register */ extern void __set_PSP(uint32_t topOfProcStack); /** * @brief Return the Main Stack Pointer * * @return Main Stack Pointer * * Return the current value of the MSP (main stack pointer) * Cortex processor register */ extern uint32_t __get_MSP(void); /** * @brief Set the Main Stack Pointer * * @param topOfMainStack Main Stack Pointer * * Assign the value mainStackPointer to the MSP * (main stack pointer) Cortex processor register */ extern void __set_MSP(uint32_t topOfMainStack); /** * @brief Return the Base Priority value * * @return BasePriority * * Return the content of the base priority register */ extern uint32_t __get_BASEPRI(void); /** * @brief Set the Base Priority value * * @param basePri BasePriority * * Set the base priority register */ extern void __set_BASEPRI(uint32_t basePri); /** * @brief Return the Priority Mask value * * @return PriMask * * Return state of the priority mask bit from the priority mask register */ extern uint32_t __get_PRIMASK(void); /** * @brief Set the Priority Mask value * * @param priMask PriMask * * Set the priority mask bit in the priority mask register */ extern void __set_PRIMASK(uint32_t priMask); /** * @brief Return the Fault Mask value * * @return FaultMask * * Return the content of the fault mask register */ extern uint32_t __get_FAULTMASK(void); /** * @brief Set the Fault Mask value * * @param faultMask faultMask value * * Set the fault mask register */ extern void __set_FAULTMASK(uint32_t faultMask); /** * @brief Return the Control Register value * * @return Control value * * Return the content of the control register */ extern uint32_t __get_CONTROL(void); /** * @brief Set the Control Register value * * @param control Control value * * Set the control register */ extern void __set_CONTROL(uint32_t control); /** * @brief Reverse byte order in integer value * * @param value value to reverse * @return reversed value * * Reverse byte order in integer value */ extern uint32_t __REV(uint32_t value); /** * @brief Reverse byte order in unsigned short value * * @param value value to reverse * @return reversed value * * Reverse byte order in unsigned short value */ extern uint32_t __REV16(uint16_t value); /** * @brief Reverse byte order in signed short value with sign extension to integer * * @param value value to reverse * @return reversed value * * Reverse byte order in signed short value with sign extension to integer */ extern int32_t __REVSH(int16_t value); /** * @brief Reverse bit order of value * * @param value value to reverse * @return reversed value * * Reverse bit order of value */ extern uint32_t __RBIT(uint32_t value); /** * @brief LDR Exclusive (8 bit) * * @param *addr address pointer * @return value of (*address) * * Exclusive LDR command for 8 bit value */ extern uint8_t __LDREXB(uint8_t *addr); /** * @brief LDR Exclusive (16 bit) * * @param *addr address pointer * @return value of (*address) * * Exclusive LDR command for 16 bit values */ extern uint16_t __LDREXH(uint16_t *addr); /** * @brief LDR Exclusive (32 bit) * * @param *addr address pointer * @return value of (*address) * * Exclusive LDR command for 32 bit values */ extern uint32_t __LDREXW(uint32_t *addr); /** * @brief STR Exclusive (8 bit) * * @param value value to store * @param *addr address pointer * @return successful / failed * * Exclusive STR command for 8 bit values */ extern uint32_t __STREXB(uint8_t value, uint8_t *addr); /** * @brief STR Exclusive (16 bit) * * @param value value to store * @param *addr address pointer * @return successful / failed * * Exclusive STR command for 16 bit values */ extern uint32_t __STREXH(uint16_t value, uint16_t *addr); /** * @brief STR Exclusive (32 bit) * * @param value value to store * @param *addr address pointer * @return successful / failed * * Exclusive STR command for 32 bit values */ extern uint32_t __STREXW(uint32_t value, uint32_t *addr); #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ /* TASKING carm specific functions */ /* * The CMSIS functions have been implemented as intrinsics in the compiler. * Please use "carm -?i" to get an up to date list of all instrinsics, * Including the CMSIS ones. */ #endif /** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface Core Function Interface containing: - Core NVIC Functions - Core SysTick Functions - Core Reset Functions */ /*@{*/ /* ########################## NVIC functions #################################### */ /** * @brief Set the Priority Grouping in NVIC Interrupt Controller * * @param PriorityGroup is priority grouping field * * Set the priority grouping field using the required unlock sequence. * The parameter priority_grouping is assigned to the field * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. * In case of a conflict between priority grouping and available * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. */ static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ reg_value = (reg_value | (0x5FA << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ SCB->AIRCR = reg_value; } /** * @brief Get the Priority Grouping from NVIC Interrupt Controller * * @return priority grouping field * * Get the priority grouping from NVIC Interrupt Controller. * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. */ static __INLINE uint32_t NVIC_GetPriorityGrouping(void) { return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ } /** * @brief Enable Interrupt in NVIC Interrupt Controller * * @param IRQn The positive number of the external interrupt to enable * * Enable a device specific interupt in the NVIC interrupt controller. * The interrupt number cannot be a negative value. */ static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ } /** * @brief Disable the interrupt line for external interrupt specified * * @param IRQn The positive number of the external interrupt to disable * * Disable a device specific interupt in the NVIC interrupt controller. * The interrupt number cannot be a negative value. */ static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ } /** * @brief Read the interrupt pending bit for a device specific interrupt source * * @param IRQn The number of the device specifc interrupt * @return 1 = interrupt pending, 0 = interrupt not pending * * Read the pending register in NVIC and return 1 if its status is pending, * otherwise it returns 0 */ static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ } /** * @brief Set the pending bit for an external interrupt * * @param IRQn The number of the interrupt for set pending * * Set the pending bit for the specified interrupt. * The interrupt number cannot be a negative value. */ static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ } /** * @brief Clear the pending bit for an external interrupt * * @param IRQn The number of the interrupt for clear pending * * Clear the pending bit for the specified interrupt. * The interrupt number cannot be a negative value. */ static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ } /** * @brief Read the active bit for an external interrupt * * @param IRQn The number of the interrupt for read active bit * @return 1 = interrupt active, 0 = interrupt not active * * Read the active register in NVIC and returns 1 if its status is active, * otherwise it returns 0. */ static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) { return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ } /** * @brief Set the priority for an interrupt * * @param IRQn The number of the interrupt for set priority * @param priority The priority to set * * Set the priority for the specified interrupt. The interrupt * number can be positive to specify an external (device specific) * interrupt, or negative to specify an internal (core) interrupt. * * Note: The priority cannot be set for every core interrupt. */ static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if(IRQn < 0) { SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ else { NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ } /** * @brief Read the priority for an interrupt * * @param IRQn The number of the interrupt for get priority * @return The priority for the interrupt * * Read the priority for the specified interrupt. The interrupt * number can be positive to specify an external (device specific) * interrupt, or negative to specify an internal (core) interrupt. * * The returned priority value is automatically aligned to the implemented * priority bits of the microcontroller. * * Note: The priority cannot be set for every core interrupt. */ static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) { if(IRQn < 0) { return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ else { return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ } /** * @brief Encode the priority for an interrupt * * @param PriorityGroup The used priority group * @param PreemptPriority The preemptive priority value (starting from 0) * @param SubPriority The sub priority value (starting from 0) * @return The encoded priority for the interrupt * * Encode the priority for an interrupt with the given priority group, * preemptive priority value and sub priority value. * In case of a conflict between priority grouping and available * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. * * The returned priority value can be used for NVIC_SetPriority(...) function */ static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; return ( ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | ((SubPriority & ((1 << (SubPriorityBits )) - 1))) ); } /** * @brief Decode the priority of an interrupt * * @param Priority The priority for the interrupt * @param PriorityGroup The used priority group * @param pPreemptPriority The preemptive priority value (starting from 0) * @param pSubPriority The sub priority value (starting from 0) * * Decode an interrupt priority value with the given priority group to * preemptive priority value and sub priority value. * In case of a conflict between priority grouping and available * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. * * The priority value can be retrieved with NVIC_GetPriority(...) function */ static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); } /* ################################## SysTick function ############################################ */ #if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) /** * @brief Initialize and start the SysTick counter and its interrupt. * * @param ticks number of ticks between two interrupts * @return 1 = failed, 0 = successful * * Initialise the system tick timer and its interrupt and start the * system tick timer / counter in free running mode to generate * periodical interrupts. */ static __INLINE uint32_t SysTick_Config(uint32_t ticks) { if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ SysTick->VAL = 0; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0); /* Function successful */ } #endif /* ################################## Reset function ############################################ */ /** * @brief Initiate a system reset request. * * Initiate a system reset request to reset the MCU */ static __INLINE void NVIC_SystemReset(void) { SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ while(1); /* wait until reset */ } /*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ /* ##################################### Debug In/Output function ########################################### */ /** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface Core Debug Interface containing: - Core Debug Receive / Transmit Functions - Core Debug Defines - Core Debug Variables */ /*@{*/ extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ /** * @brief Outputs a character via the ITM channel 0 * * @param ch character to output * @return character to output * * The function outputs a character via the ITM channel 0. * The function returns when no debugger is connected that has booked the output. * It is blocking when a debugger is connected, but the previous character send is not transmitted. */ static __INLINE uint32_t ITM_SendChar (uint32_t ch) { if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0].u32 == 0); ITM->PORT[0].u8 = (uint8_t) ch; } return (ch); } /** * @brief Inputs a character via variable ITM_RxBuffer * * @return received character, -1 = no character received * * The function inputs a character via variable ITM_RxBuffer. * The function returns when no debugger is connected that has booked the output. * It is blocking when a debugger is connected, but the previous character send is not transmitted. */ static __INLINE int ITM_ReceiveChar (void) { int ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** * @brief Check if a character via variable ITM_RxBuffer is available * * @return 1 = character available, 0 = no character available * * The function checks variable ITM_RxBuffer whether a character is available or not. * The function returns '1' if a character is available and '0' if no character is available. */ static __INLINE int ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ #ifdef __cplusplus } #endif /*@}*/ /* end of group CMSIS_CM3_core_definitions */ #endif /* __CM3_CORE_H__ */ /*lint -restore */ /**************************************************************************//** * @file core_cm3.h * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File * @version V1.30 * @date 30. October 2009 * * @note * Copyright (C) 2009 ARM Limited. All rights reserved. * * @par * ARM Limited (ARM) is supplying this software for use with Cortex-M * processor based microcontrollers. This file can be freely distributed * within development tools that are supporting such ARM based processors. * * @par * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. * ******************************************************************************/ #ifndef __CM3_CORE_H__ #define __CM3_CORE_H__ /** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration * * List of Lint messages which will be suppressed and not shown: * - Error 10: \n * register uint32_t __regBasePri __asm("basepri"); \n * Error 10: Expecting ';' * . * - Error 530: \n * return(__regBasePri); \n * Warning 530: Symbol '__regBasePri' (line 264) not initialized * . * - Error 550: \n * __regBasePri = (basePri & 0x1ff); \n * Warning 550: Symbol '__regBasePri' (line 271) not accessed * . * - Error 754: \n * uint32_t RESERVED0[24]; \n * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced * . * - Error 750: \n * #define __CM3_CORE_H__ \n * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced * . * - Error 528: \n * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced * . * - Error 751: \n * } InterruptType_Type; \n * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced * . * Note: To re-enable a Message, insert a space before 'lint' * * */ /*lint -save */ /*lint -e10 */ /*lint -e530 */ /*lint -e550 */ /*lint -e754 */ /*lint -e750 */ /*lint -e528 */ /*lint -e751 */ /** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions This file defines all structures and symbols for CMSIS core: - CMSIS version number - Cortex-M core registers and bitfields - Cortex-M core peripheral base address @{ */ #ifdef __cplusplus extern "C" { #endif #define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ #define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ #define __CORTEX_M (0x03) /*!< Cortex core */ #include <stdint.h> /* Include standard types */ #if defined (__ICCARM__) #include <intrinsics.h> /* IAR Intrinsics */ #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ #endif /** * IO definitions * * define access restrictions to peripheral registers */ #ifdef __cplusplus #define __I volatile /*!< defines 'read only' permissions */ #else #define __I volatile const /*!< defines 'read only' permissions */ #endif #define __O volatile /*!< defines 'write only' permissions */ #define __IO volatile /*!< defines 'read / write' permissions */ /******************************************************************************* * Register Abstraction ******************************************************************************/ /** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register @{ */ /** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC memory mapped structure for Nested Vectored Interrupt Controller (NVIC) @{ */ typedef struct { __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ uint32_t RESERVED0[24]; __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ uint32_t RSERVED1[24]; __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ uint32_t RESERVED2[24]; __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ uint32_t RESERVED3[24]; __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ uint32_t RESERVED4[56]; __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644]; __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ } NVIC_Type; /*@}*/ /* end of group CMSIS_CM3_NVIC */ /** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB memory mapped structure for System Control Block (SCB) @{ */ typedef struct { __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ #define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Registers Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* SCB Hard Fault Status Registers Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ /*@}*/ /* end of group CMSIS_CM3_SCB */ /** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick memory mapped structure for SysTick @{ */ typedef struct { __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ /*@}*/ /* end of group CMSIS_CM3_SysTick */ /** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM memory mapped structure for Instrumentation Trace Macrocell (ITM) @{ */ typedef struct { __O union { __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ uint32_t RESERVED0[864]; __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ uint32_t RESERVED1[15]; __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ uint32_t RESERVED2[15]; __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ uint32_t RESERVED3[29]; __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ uint32_t RESERVED4[43]; __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ uint32_t RESERVED5[6]; __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ #define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ #define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ #define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ #define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_CM3_ITM */ /** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type memory mapped structure for Interrupt Type @{ */ typedef struct { uint32_t RESERVED0; __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ #if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ #else uint32_t RESERVED1; #endif } InterruptType_Type; /* Interrupt Controller Type Register Definitions */ #define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ #define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ #define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ #define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ #define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ #define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ #define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ #define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ /*@}*/ /* end of group CMSIS_CM3_InterruptType */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) /** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU memory mapped structure for Memory Protection Unit (MPU) @{ */ typedef struct { __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; /* MPU Type Register */ #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register */ #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register */ #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register */ #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register */ #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ #define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ #define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ #define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ #define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ #define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ #define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ #define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ #define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ #define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ /*@}*/ /* end of group CMSIS_CM3_MPU */ #endif /** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug memory mapped structure for Core Debug Register @{ */ typedef struct { __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register */ #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register */ #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register */ #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@}*/ /* end of group CMSIS_CM3_CoreDebug */ /* Memory mapping of Cortex-M3 Hardware */ #define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000) /*!< ITM Base Address */ #define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ #define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ #define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ #endif /*@}*/ /* end of group CMSIS_CM3_core_register */ /******************************************************************************* * Hardware Abstraction Layer ******************************************************************************/ #if defined ( __CC_ARM ) #define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #elif defined ( __ICCARM__ ) #define __ASM __asm /*!< asm keyword for IAR Compiler */ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ #elif defined ( __GNUC__ ) #define __ASM __asm /*!< asm keyword for GNU Compiler */ #define __INLINE inline /*!< inline keyword for GNU Compiler */ #elif defined ( __TASKING__ ) #define __ASM __asm /*!< asm keyword for TASKING Compiler */ #define __INLINE inline /*!< inline keyword for TASKING Compiler */ #endif /* ################### Compiler specific Intrinsics ########################### */ #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ /* ARM armcc specific functions */ #define __enable_fault_irq __enable_fiq #define __disable_fault_irq __disable_fiq #define __NOP __nop #define __WFI __wfi #define __WFE __wfe #define __SEV __sev #define __ISB() __isb(0) #define __DSB() __dsb(0) #define __DMB() __dmb(0) #define __REV __rev #define __RBIT __rbit #define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) #define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) #define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) #define __STREXB(value, ptr) __strex(value, ptr) #define __STREXH(value, ptr) __strex(value, ptr) #define __STREXW(value, ptr) __strex(value, ptr) /* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ /* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ /* intrinsic void __enable_irq(); */ /* intrinsic void __disable_irq(); */ /** * @brief Return the Process Stack Pointer * * @return ProcessStackPointer * * Return the actual process stack pointer */ extern uint32_t __get_PSP(void); /** * @brief Set the Process Stack Pointer * * @param topOfProcStack Process Stack Pointer * * Assign the value ProcessStackPointer to the MSP * (process stack pointer) Cortex processor register */ extern void __set_PSP(uint32_t topOfProcStack); /** * @brief Return the Main Stack Pointer * * @return Main Stack Pointer * * Return the current value of the MSP (main stack pointer) * Cortex processor register */ extern uint32_t __get_MSP(void); /** * @brief Set the Main Stack Pointer * * @param topOfMainStack Main Stack Pointer * * Assign the value mainStackPointer to the MSP * (main stack pointer) Cortex processor register */ extern void __set_MSP(uint32_t topOfMainStack); /** * @brief Reverse byte order in unsigned short value * * @param value value to reverse * @return reversed value * * Reverse byte order in unsigned short value */ extern uint32_t __REV16(uint16_t value); /** * @brief Reverse byte order in signed short value with sign extension to integer * * @param value value to reverse * @return reversed value * * Reverse byte order in signed short value with sign extension to integer */ extern int32_t __REVSH(int16_t value); #if (__ARMCC_VERSION < 400000) /** * @brief Remove the exclusive lock created by ldrex * * Removes the exclusive lock which is created by ldrex. */ extern void __CLREX(void); /** * @brief Return the Base Priority value * * @return BasePriority * * Return the content of the base priority register */ extern uint32_t __get_BASEPRI(void); /** * @brief Set the Base Priority value * * @param basePri BasePriority * * Set the base priority register */ extern void __set_BASEPRI(uint32_t basePri); /** * @brief Return the Priority Mask value * * @return PriMask * * Return state of the priority mask bit from the priority mask register */ extern uint32_t __get_PRIMASK(void); /** * @brief Set the Priority Mask value * * @param priMask PriMask * * Set the priority mask bit in the priority mask register */ extern void __set_PRIMASK(uint32_t priMask); /** * @brief Return the Fault Mask value * * @return FaultMask * * Return the content of the fault mask register */ extern uint32_t __get_FAULTMASK(void); /** * @brief Set the Fault Mask value * * @param faultMask faultMask value * * Set the fault mask register */ extern void __set_FAULTMASK(uint32_t faultMask); /** * @brief Return the Control Register value * * @return Control value * * Return the content of the control register */ extern uint32_t __get_CONTROL(void); /** * @brief Set the Control Register value * * @param control Control value * * Set the control register */ extern void __set_CONTROL(uint32_t control); #else /* (__ARMCC_VERSION >= 400000) */ /** * @brief Remove the exclusive lock created by ldrex * * Removes the exclusive lock which is created by ldrex. */ #define __CLREX __clrex /** * @brief Return the Base Priority value * * @return BasePriority * * Return the content of the base priority register */ static __INLINE uint32_t __get_BASEPRI(void) { register uint32_t __regBasePri __ASM("basepri"); return(__regBasePri); } /** * @brief Set the Base Priority value * * @param basePri BasePriority * * Set the base priority register */ static __INLINE void __set_BASEPRI(uint32_t basePri) { register uint32_t __regBasePri __ASM("basepri"); __regBasePri = (basePri & 0xff); } /** * @brief Return the Priority Mask value * * @return PriMask * * Return state of the priority mask bit from the priority mask register */ static __INLINE uint32_t __get_PRIMASK(void) { register uint32_t __regPriMask __ASM("primask"); return(__regPriMask); } /** * @brief Set the Priority Mask value * * @param priMask PriMask * * Set the priority mask bit in the priority mask register */ static __INLINE void __set_PRIMASK(uint32_t priMask) { register uint32_t __regPriMask __ASM("primask"); __regPriMask = (priMask); } /** * @brief Return the Fault Mask value * * @return FaultMask * * Return the content of the fault mask register */ static __INLINE uint32_t __get_FAULTMASK(void) { register uint32_t __regFaultMask __ASM("faultmask"); return(__regFaultMask); } /** * @brief Set the Fault Mask value * * @param faultMask faultMask value * * Set the fault mask register */ static __INLINE void __set_FAULTMASK(uint32_t faultMask) { register uint32_t __regFaultMask __ASM("faultmask"); __regFaultMask = (faultMask & 1); } /** * @brief Return the Control Register value * * @return Control value * * Return the content of the control register */ static __INLINE uint32_t __get_CONTROL(void) { register uint32_t __regControl __ASM("control"); return(__regControl); } /** * @brief Set the Control Register value * * @param control Control value * * Set the control register */ static __INLINE void __set_CONTROL(uint32_t control) { register uint32_t __regControl __ASM("control"); __regControl = control; } #endif /* __ARMCC_VERSION */ #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ /* IAR iccarm specific functions */ #define __enable_irq __enable_interrupt /*!< global Interrupt enable */ #define __disable_irq __disable_interrupt /*!< global Interrupt disable */ static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } #define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ static __INLINE void __WFI() { __ASM ("wfi"); } static __INLINE void __WFE() { __ASM ("wfe"); } static __INLINE void __SEV() { __ASM ("sev"); } static __INLINE void __CLREX() { __ASM ("clrex"); } /* intrinsic void __ISB(void) */ /* intrinsic void __DSB(void) */ /* intrinsic void __DMB(void) */ /* intrinsic void __set_PRIMASK(); */ /* intrinsic void __get_PRIMASK(); */ /* intrinsic void __set_FAULTMASK(); */ /* intrinsic void __get_FAULTMASK(); */ /* intrinsic uint32_t __REV(uint32_t value); */ /* intrinsic uint32_t __REVSH(uint32_t value); */ /* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ /* intrinsic unsigned long __LDREX(unsigned long *); */ /** * @brief Return the Process Stack Pointer * * @return ProcessStackPointer * * Return the actual process stack pointer */ extern uint32_t __get_PSP(void); /** * @brief Set the Process Stack Pointer * * @param topOfProcStack Process Stack Pointer * * Assign the value ProcessStackPointer to the MSP * (process stack pointer) Cortex processor register */ extern void __set_PSP(uint32_t topOfProcStack); /** * @brief Return the Main Stack Pointer * * @return Main Stack Pointer * * Return the current value of the MSP (main stack pointer) * Cortex processor register */ extern uint32_t __get_MSP(void); /** * @brief Set the Main Stack Pointer * * @param topOfMainStack Main Stack Pointer * * Assign the value mainStackPointer to the MSP * (main stack pointer) Cortex processor register */ extern void __set_MSP(uint32_t topOfMainStack); /** * @brief Reverse byte order in unsigned short value * * @param value value to reverse * @return reversed value * * Reverse byte order in unsigned short value */ extern uint32_t __REV16(uint16_t value); /** * @brief Reverse bit order of value * * @param value value to reverse * @return reversed value * * Reverse bit order of value */ extern uint32_t __RBIT(uint32_t value); /** * @brief LDR Exclusive (8 bit) * * @param *addr address pointer * @return value of (*address) * * Exclusive LDR command for 8 bit values) */ extern uint8_t __LDREXB(uint8_t *addr); /** * @brief LDR Exclusive (16 bit) * * @param *addr address pointer * @return value of (*address) * * Exclusive LDR command for 16 bit values */ extern uint16_t __LDREXH(uint16_t *addr); /** * @brief LDR Exclusive (32 bit) * * @param *addr address pointer * @return value of (*address) * * Exclusive LDR command for 32 bit values */ extern uint32_t __LDREXW(uint32_t *addr); /** * @brief STR Exclusive (8 bit) * * @param value value to store * @param *addr address pointer * @return successful / failed * * Exclusive STR command for 8 bit values */ extern uint32_t __STREXB(uint8_t value, uint8_t *addr); /** * @brief STR Exclusive (16 bit) * * @param value value to store * @param *addr address pointer * @return successful / failed * * Exclusive STR command for 16 bit values */ extern uint32_t __STREXH(uint16_t value, uint16_t *addr); /** * @brief STR Exclusive (32 bit) * * @param value value to store * @param *addr address pointer * @return successful / failed * * Exclusive STR command for 32 bit values */ extern uint32_t __STREXW(uint32_t value, uint32_t *addr); #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ /* GNU gcc specific functions */ static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } static __INLINE void __NOP() { __ASM volatile ("nop"); } static __INLINE void __WFI() { __ASM volatile ("wfi"); } static __INLINE void __WFE() { __ASM volatile ("wfe"); } static __INLINE void __SEV() { __ASM volatile ("sev"); } static __INLINE void __ISB() { __ASM volatile ("isb"); } static __INLINE void __DSB() { __ASM volatile ("dsb"); } static __INLINE void __DMB() { __ASM volatile ("dmb"); } static __INLINE void __CLREX() { __ASM volatile ("clrex"); } /** * @brief Return the Process Stack Pointer * * @return ProcessStackPointer * * Return the actual process stack pointer */ extern uint32_t __get_PSP(void); /** * @brief Set the Process Stack Pointer * * @param topOfProcStack Process Stack Pointer * * Assign the value ProcessStackPointer to the MSP * (process stack pointer) Cortex processor register */ extern void __set_PSP(uint32_t topOfProcStack); /** * @brief Return the Main Stack Pointer * * @return Main Stack Pointer * * Return the current value of the MSP (main stack pointer) * Cortex processor register */ extern uint32_t __get_MSP(void); /** * @brief Set the Main Stack Pointer * * @param topOfMainStack Main Stack Pointer * * Assign the value mainStackPointer to the MSP * (main stack pointer) Cortex processor register */ extern void __set_MSP(uint32_t topOfMainStack); /** * @brief Return the Base Priority value * * @return BasePriority * * Return the content of the base priority register */ extern uint32_t __get_BASEPRI(void); /** * @brief Set the Base Priority value * * @param basePri BasePriority * * Set the base priority register */ extern void __set_BASEPRI(uint32_t basePri); /** * @brief Return the Priority Mask value * * @return PriMask * * Return state of the priority mask bit from the priority mask register */ extern uint32_t __get_PRIMASK(void); /** * @brief Set the Priority Mask value * * @param priMask PriMask * * Set the priority mask bit in the priority mask register */ extern void __set_PRIMASK(uint32_t priMask); /** * @brief Return the Fault Mask value * * @return FaultMask * * Return the content of the fault mask register */ extern uint32_t __get_FAULTMASK(void); /** * @brief Set the Fault Mask value * * @param faultMask faultMask value * * Set the fault mask register */ extern void __set_FAULTMASK(uint32_t faultMask); /** * @brief Return the Control Register value * * @return Control value * * Return the content of the control register */ extern uint32_t __get_CONTROL(void); /** * @brief Set the Control Register value * * @param control Control value * * Set the control register */ extern void __set_CONTROL(uint32_t control); /** * @brief Reverse byte order in integer value * * @param value value to reverse * @return reversed value * * Reverse byte order in integer value */ extern uint32_t __REV(uint32_t value); /** * @brief Reverse byte order in unsigned short value * * @param value value to reverse * @return reversed value * * Reverse byte order in unsigned short value */ extern uint32_t __REV16(uint16_t value); /** * @brief Reverse byte order in signed short value with sign extension to integer * * @param value value to reverse * @return reversed value * * Reverse byte order in signed short value with sign extension to integer */ extern int32_t __REVSH(int16_t value); /** * @brief Reverse bit order of value * * @param value value to reverse * @return reversed value * * Reverse bit order of value */ extern uint32_t __RBIT(uint32_t value); /** * @brief LDR Exclusive (8 bit) * * @param *addr address pointer * @return value of (*address) * * Exclusive LDR command for 8 bit value */ extern uint8_t __LDREXB(uint8_t *addr); /** * @brief LDR Exclusive (16 bit) * * @param *addr address pointer * @return value of (*address) * * Exclusive LDR command for 16 bit values */ extern uint16_t __LDREXH(uint16_t *addr); /** * @brief LDR Exclusive (32 bit) * * @param *addr address pointer * @return value of (*address) * * Exclusive LDR command for 32 bit values */ extern uint32_t __LDREXW(uint32_t *addr); /** * @brief STR Exclusive (8 bit) * * @param value value to store * @param *addr address pointer * @return successful / failed * * Exclusive STR command for 8 bit values */ extern uint32_t __STREXB(uint8_t value, uint8_t *addr); /** * @brief STR Exclusive (16 bit) * * @param value value to store * @param *addr address pointer * @return successful / failed * * Exclusive STR command for 16 bit values */ extern uint32_t __STREXH(uint16_t value, uint16_t *addr); /** * @brief STR Exclusive (32 bit) * * @param value value to store * @param *addr address pointer * @return successful / failed * * Exclusive STR command for 32 bit values */ extern uint32_t __STREXW(uint32_t value, uint32_t *addr); #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ /* TASKING carm specific functions */ /* * The CMSIS functions have been implemented as intrinsics in the compiler. * Please use "carm -?i" to get an up to date list of all instrinsics, * Including the CMSIS ones. */ #endif /** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface Core Function Interface containing: - Core NVIC Functions - Core SysTick Functions - Core Reset Functions */ /*@{*/ /* ########################## NVIC functions #################################### */ /** * @brief Set the Priority Grouping in NVIC Interrupt Controller * * @param PriorityGroup is priority grouping field * * Set the priority grouping field using the required unlock sequence. * The parameter priority_grouping is assigned to the field * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. * In case of a conflict between priority grouping and available * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. */ static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ reg_value = (reg_value | (0x5FA << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ SCB->AIRCR = reg_value; } /** * @brief Get the Priority Grouping from NVIC Interrupt Controller * * @return priority grouping field * * Get the priority grouping from NVIC Interrupt Controller. * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. */ static __INLINE uint32_t NVIC_GetPriorityGrouping(void) { return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ } /** * @brief Enable Interrupt in NVIC Interrupt Controller * * @param IRQn The positive number of the external interrupt to enable * * Enable a device specific interupt in the NVIC interrupt controller. * The interrupt number cannot be a negative value. */ static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ } /** * @brief Disable the interrupt line for external interrupt specified * * @param IRQn The positive number of the external interrupt to disable * * Disable a device specific interupt in the NVIC interrupt controller. * The interrupt number cannot be a negative value. */ static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ } /** * @brief Read the interrupt pending bit for a device specific interrupt source * * @param IRQn The number of the device specifc interrupt * @return 1 = interrupt pending, 0 = interrupt not pending * * Read the pending register in NVIC and return 1 if its status is pending, * otherwise it returns 0 */ static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ } /** * @brief Set the pending bit for an external interrupt * * @param IRQn The number of the interrupt for set pending * * Set the pending bit for the specified interrupt. * The interrupt number cannot be a negative value. */ static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ } /** * @brief Clear the pending bit for an external interrupt * * @param IRQn The number of the interrupt for clear pending * * Clear the pending bit for the specified interrupt. * The interrupt number cannot be a negative value. */ static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ } /** * @brief Read the active bit for an external interrupt * * @param IRQn The number of the interrupt for read active bit * @return 1 = interrupt active, 0 = interrupt not active * * Read the active register in NVIC and returns 1 if its status is active, * otherwise it returns 0. */ static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) { return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ } /** * @brief Set the priority for an interrupt * * @param IRQn The number of the interrupt for set priority * @param priority The priority to set * * Set the priority for the specified interrupt. The interrupt * number can be positive to specify an external (device specific) * interrupt, or negative to specify an internal (core) interrupt. * * Note: The priority cannot be set for every core interrupt. */ static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if(IRQn < 0) { SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ else { NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ } /** * @brief Read the priority for an interrupt * * @param IRQn The number of the interrupt for get priority * @return The priority for the interrupt * * Read the priority for the specified interrupt. The interrupt * number can be positive to specify an external (device specific) * interrupt, or negative to specify an internal (core) interrupt. * * The returned priority value is automatically aligned to the implemented * priority bits of the microcontroller. * * Note: The priority cannot be set for every core interrupt. */ static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) { if(IRQn < 0) { return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ else { return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ } /** * @brief Encode the priority for an interrupt * * @param PriorityGroup The used priority group * @param PreemptPriority The preemptive priority value (starting from 0) * @param SubPriority The sub priority value (starting from 0) * @return The encoded priority for the interrupt * * Encode the priority for an interrupt with the given priority group, * preemptive priority value and sub priority value. * In case of a conflict between priority grouping and available * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. * * The returned priority value can be used for NVIC_SetPriority(...) function */ static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; return ( ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | ((SubPriority & ((1 << (SubPriorityBits )) - 1))) ); } /** * @brief Decode the priority of an interrupt * * @param Priority The priority for the interrupt * @param PriorityGroup The used priority group * @param pPreemptPriority The preemptive priority value (starting from 0) * @param pSubPriority The sub priority value (starting from 0) * * Decode an interrupt priority value with the given priority group to * preemptive priority value and sub priority value. * In case of a conflict between priority grouping and available * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. * * The priority value can be retrieved with NVIC_GetPriority(...) function */ static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); } /* ################################## SysTick function ############################################ */ #if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) /** * @brief Initialize and start the SysTick counter and its interrupt. * * @param ticks number of ticks between two interrupts * @return 1 = failed, 0 = successful * * Initialise the system tick timer and its interrupt and start the * system tick timer / counter in free running mode to generate * periodical interrupts. */ static __INLINE uint32_t SysTick_Config(uint32_t ticks) { if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ SysTick->VAL = 0; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0); /* Function successful */ } #endif /* ################################## Reset function ############################################ */ /** * @brief Initiate a system reset request. * * Initiate a system reset request to reset the MCU */ static __INLINE void NVIC_SystemReset(void) { SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ while(1); /* wait until reset */ } /*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ /* ##################################### Debug In/Output function ########################################### */ /** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface Core Debug Interface containing: - Core Debug Receive / Transmit Functions - Core Debug Defines - Core Debug Variables */ /*@{*/ extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ /** * @brief Outputs a character via the ITM channel 0 * * @param ch character to output * @return character to output * * The function outputs a character via the ITM channel 0. * The function returns when no debugger is connected that has booked the output. * It is blocking when a debugger is connected, but the previous character send is not transmitted. */ static __INLINE uint32_t ITM_SendChar (uint32_t ch) { if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0].u32 == 0); ITM->PORT[0].u8 = (uint8_t) ch; } return (ch); } /** * @brief Inputs a character via variable ITM_RxBuffer * * @return received character, -1 = no character received * * The function inputs a character via variable ITM_RxBuffer. * The function returns when no debugger is connected that has booked the output. * It is blocking when a debugger is connected, but the previous character send is not transmitted. */ static __INLINE int ITM_ReceiveChar (void) { int ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** * @brief Check if a character via variable ITM_RxBuffer is available * * @return 1 = character available, 0 = no character available * * The function checks variable ITM_RxBuffer whether a character is available or not. * The function returns '1' if a character is available and '0' if no character is available. */ static __INLINE int ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ #ifdef __cplusplus } #endif /*@}*/ /* end of group CMSIS_CM3_core_definitions */ #endif /* __CM3_CORE_H__ */ /*lint -restore */ src/bare_test/1.Led/cmsis/startup_stm32f10x_hd.s
File was renamed from src/bare_test/stm32_key/board/startup_stm32f10x_hd.s @@ -1,358 +1,358 @@ ;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** ;* File Name : startup_stm32f10x_hd.s ;* Author : MCD Application Team ;* Version : V3.5.0 ;* Date : 11-March-2011 ;* Description : STM32F10x High Density Devices vector table for MDK-ARM ;* toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == Reset_Handler ;* - Set the vector table entries with the exceptions ISR address ;* - Configure the clock system and also configure the external ;* SRAM mounted on STM3210E-EVAL board to be used as data ;* memory (optional, to be enabled by user) ;* - Branches to __main in the C library (which eventually ;* calls main()). ;* After Reset the CortexM3 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;* <<< Use Configuration Wizard in Context Menu >>> ;******************************************************************************* ; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS ; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. ; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, ; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE ; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING ; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. ;******************************************************************************* ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000200 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler DCD BusFault_Handler ; Bus Fault Handler DCD UsageFault_Handler ; Usage Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WWDG_IRQHandler ; Window Watchdog DCD PVD_IRQHandler ; PVD through EXTI Line detect DCD TAMPER_IRQHandler ; Tamper DCD RTC_IRQHandler ; RTC DCD FLASH_IRQHandler ; Flash DCD RCC_IRQHandler ; RCC DCD EXTI0_IRQHandler ; EXTI Line 0 DCD EXTI1_IRQHandler ; EXTI Line 1 DCD EXTI2_IRQHandler ; EXTI Line 2 DCD EXTI3_IRQHandler ; EXTI Line 3 DCD EXTI4_IRQHandler ; EXTI Line 4 DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 DCD ADC1_2_IRQHandler ; ADC1 & ADC2 DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 DCD CAN1_RX1_IRQHandler ; CAN1 RX1 DCD CAN1_SCE_IRQHandler ; CAN1 SCE DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 DCD TIM1_BRK_IRQHandler ; TIM1 Break DCD TIM1_UP_IRQHandler ; TIM1 Update DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare DCD TIM2_IRQHandler ; TIM2 DCD TIM3_IRQHandler ; TIM3 DCD TIM4_IRQHandler ; TIM4 DCD I2C1_EV_IRQHandler ; I2C1 Event DCD I2C1_ER_IRQHandler ; I2C1 Error DCD I2C2_EV_IRQHandler ; I2C2 Event DCD I2C2_ER_IRQHandler ; I2C2 Error DCD SPI1_IRQHandler ; SPI1 DCD SPI2_IRQHandler ; SPI2 DCD USART1_IRQHandler ; USART1 DCD USART2_IRQHandler ; USART2 DCD USART3_IRQHandler ; USART3 DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend DCD TIM8_BRK_IRQHandler ; TIM8 Break DCD TIM8_UP_IRQHandler ; TIM8 Update DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare DCD ADC3_IRQHandler ; ADC3 DCD FSMC_IRQHandler ; FSMC DCD SDIO_IRQHandler ; SDIO DCD TIM5_IRQHandler ; TIM5 DCD SPI3_IRQHandler ; SPI3 DCD UART4_IRQHandler ; UART4 DCD UART5_IRQHandler ; UART5 DCD TIM6_IRQHandler ; TIM6 DCD TIM7_IRQHandler ; TIM7 DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT __main IMPORT SystemInit LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP MemManage_Handler\ PROC EXPORT MemManage_Handler [WEAK] B . ENDP BusFault_Handler\ PROC EXPORT BusFault_Handler [WEAK] B . ENDP UsageFault_Handler\ PROC EXPORT UsageFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP DebugMon_Handler\ PROC EXPORT DebugMon_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WWDG_IRQHandler [WEAK] EXPORT PVD_IRQHandler [WEAK] EXPORT TAMPER_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT FLASH_IRQHandler [WEAK] EXPORT RCC_IRQHandler [WEAK] EXPORT EXTI0_IRQHandler [WEAK] EXPORT EXTI1_IRQHandler [WEAK] EXPORT EXTI2_IRQHandler [WEAK] EXPORT EXTI3_IRQHandler [WEAK] EXPORT EXTI4_IRQHandler [WEAK] EXPORT DMA1_Channel1_IRQHandler [WEAK] EXPORT DMA1_Channel2_IRQHandler [WEAK] EXPORT DMA1_Channel3_IRQHandler [WEAK] EXPORT DMA1_Channel4_IRQHandler [WEAK] EXPORT DMA1_Channel5_IRQHandler [WEAK] EXPORT DMA1_Channel6_IRQHandler [WEAK] EXPORT DMA1_Channel7_IRQHandler [WEAK] EXPORT ADC1_2_IRQHandler [WEAK] EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] EXPORT CAN1_RX1_IRQHandler [WEAK] EXPORT CAN1_SCE_IRQHandler [WEAK] EXPORT EXTI9_5_IRQHandler [WEAK] EXPORT TIM1_BRK_IRQHandler [WEAK] EXPORT TIM1_UP_IRQHandler [WEAK] EXPORT TIM1_TRG_COM_IRQHandler [WEAK] EXPORT TIM1_CC_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT TIM3_IRQHandler [WEAK] EXPORT TIM4_IRQHandler [WEAK] EXPORT I2C1_EV_IRQHandler [WEAK] EXPORT I2C1_ER_IRQHandler [WEAK] EXPORT I2C2_EV_IRQHandler [WEAK] EXPORT I2C2_ER_IRQHandler [WEAK] EXPORT SPI1_IRQHandler [WEAK] EXPORT SPI2_IRQHandler [WEAK] EXPORT USART1_IRQHandler [WEAK] EXPORT USART2_IRQHandler [WEAK] EXPORT USART3_IRQHandler [WEAK] EXPORT EXTI15_10_IRQHandler [WEAK] EXPORT RTCAlarm_IRQHandler [WEAK] EXPORT USBWakeUp_IRQHandler [WEAK] EXPORT TIM8_BRK_IRQHandler [WEAK] EXPORT TIM8_UP_IRQHandler [WEAK] EXPORT TIM8_TRG_COM_IRQHandler [WEAK] EXPORT TIM8_CC_IRQHandler [WEAK] EXPORT ADC3_IRQHandler [WEAK] EXPORT FSMC_IRQHandler [WEAK] EXPORT SDIO_IRQHandler [WEAK] EXPORT TIM5_IRQHandler [WEAK] EXPORT SPI3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT UART5_IRQHandler [WEAK] EXPORT TIM6_IRQHandler [WEAK] EXPORT TIM7_IRQHandler [WEAK] EXPORT DMA2_Channel1_IRQHandler [WEAK] EXPORT DMA2_Channel2_IRQHandler [WEAK] EXPORT DMA2_Channel3_IRQHandler [WEAK] EXPORT DMA2_Channel4_5_IRQHandler [WEAK] WWDG_IRQHandler PVD_IRQHandler TAMPER_IRQHandler RTC_IRQHandler FLASH_IRQHandler RCC_IRQHandler EXTI0_IRQHandler EXTI1_IRQHandler EXTI2_IRQHandler EXTI3_IRQHandler EXTI4_IRQHandler DMA1_Channel1_IRQHandler DMA1_Channel2_IRQHandler DMA1_Channel3_IRQHandler DMA1_Channel4_IRQHandler DMA1_Channel5_IRQHandler DMA1_Channel6_IRQHandler DMA1_Channel7_IRQHandler ADC1_2_IRQHandler USB_HP_CAN1_TX_IRQHandler USB_LP_CAN1_RX0_IRQHandler CAN1_RX1_IRQHandler CAN1_SCE_IRQHandler EXTI9_5_IRQHandler TIM1_BRK_IRQHandler TIM1_UP_IRQHandler TIM1_TRG_COM_IRQHandler TIM1_CC_IRQHandler TIM2_IRQHandler TIM3_IRQHandler TIM4_IRQHandler I2C1_EV_IRQHandler I2C1_ER_IRQHandler I2C2_EV_IRQHandler I2C2_ER_IRQHandler SPI1_IRQHandler SPI2_IRQHandler USART1_IRQHandler USART2_IRQHandler USART3_IRQHandler EXTI15_10_IRQHandler RTCAlarm_IRQHandler USBWakeUp_IRQHandler TIM8_BRK_IRQHandler TIM8_UP_IRQHandler TIM8_TRG_COM_IRQHandler TIM8_CC_IRQHandler ADC3_IRQHandler FSMC_IRQHandler SDIO_IRQHandler TIM5_IRQHandler SPI3_IRQHandler UART4_IRQHandler UART5_IRQHandler TIM6_IRQHandler TIM7_IRQHandler DMA2_Channel1_IRQHandler DMA2_Channel2_IRQHandler DMA2_Channel3_IRQHandler DMA2_Channel4_5_IRQHandler B . ENDP ALIGN ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ALIGN ENDIF END ;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** ;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** ;* File Name : startup_stm32f10x_hd.s ;* Author : MCD Application Team ;* Version : V3.5.0 ;* Date : 11-March-2011 ;* Description : STM32F10x High Density Devices vector table for MDK-ARM ;* toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == Reset_Handler ;* - Set the vector table entries with the exceptions ISR address ;* - Configure the clock system and also configure the external ;* SRAM mounted on STM3210E-EVAL board to be used as data ;* memory (optional, to be enabled by user) ;* - Branches to __main in the C library (which eventually ;* calls main()). ;* After Reset the CortexM3 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;* <<< Use Configuration Wizard in Context Menu >>> ;******************************************************************************* ; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS ; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. ; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, ; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE ; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING ; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. ;******************************************************************************* ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> Heap_Size EQU 0x00000200 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler DCD BusFault_Handler ; Bus Fault Handler DCD UsageFault_Handler ; Usage Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WWDG_IRQHandler ; Window Watchdog DCD PVD_IRQHandler ; PVD through EXTI Line detect DCD TAMPER_IRQHandler ; Tamper DCD RTC_IRQHandler ; RTC DCD FLASH_IRQHandler ; Flash DCD RCC_IRQHandler ; RCC DCD EXTI0_IRQHandler ; EXTI Line 0 DCD EXTI1_IRQHandler ; EXTI Line 1 DCD EXTI2_IRQHandler ; EXTI Line 2 DCD EXTI3_IRQHandler ; EXTI Line 3 DCD EXTI4_IRQHandler ; EXTI Line 4 DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 DCD ADC1_2_IRQHandler ; ADC1 & ADC2 DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 DCD CAN1_RX1_IRQHandler ; CAN1 RX1 DCD CAN1_SCE_IRQHandler ; CAN1 SCE DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 DCD TIM1_BRK_IRQHandler ; TIM1 Break DCD TIM1_UP_IRQHandler ; TIM1 Update DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare DCD TIM2_IRQHandler ; TIM2 DCD TIM3_IRQHandler ; TIM3 DCD TIM4_IRQHandler ; TIM4 DCD I2C1_EV_IRQHandler ; I2C1 Event DCD I2C1_ER_IRQHandler ; I2C1 Error DCD I2C2_EV_IRQHandler ; I2C2 Event DCD I2C2_ER_IRQHandler ; I2C2 Error DCD SPI1_IRQHandler ; SPI1 DCD SPI2_IRQHandler ; SPI2 DCD USART1_IRQHandler ; USART1 DCD USART2_IRQHandler ; USART2 DCD USART3_IRQHandler ; USART3 DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend DCD TIM8_BRK_IRQHandler ; TIM8 Break DCD TIM8_UP_IRQHandler ; TIM8 Update DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare DCD ADC3_IRQHandler ; ADC3 DCD FSMC_IRQHandler ; FSMC DCD SDIO_IRQHandler ; SDIO DCD TIM5_IRQHandler ; TIM5 DCD SPI3_IRQHandler ; SPI3 DCD UART4_IRQHandler ; UART4 DCD UART5_IRQHandler ; UART5 DCD TIM6_IRQHandler ; TIM6 DCD TIM7_IRQHandler ; TIM7 DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT __main IMPORT SystemInit LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP MemManage_Handler\ PROC EXPORT MemManage_Handler [WEAK] B . ENDP BusFault_Handler\ PROC EXPORT BusFault_Handler [WEAK] B . ENDP UsageFault_Handler\ PROC EXPORT UsageFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP DebugMon_Handler\ PROC EXPORT DebugMon_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WWDG_IRQHandler [WEAK] EXPORT PVD_IRQHandler [WEAK] EXPORT TAMPER_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT FLASH_IRQHandler [WEAK] EXPORT RCC_IRQHandler [WEAK] EXPORT EXTI0_IRQHandler [WEAK] EXPORT EXTI1_IRQHandler [WEAK] EXPORT EXTI2_IRQHandler [WEAK] EXPORT EXTI3_IRQHandler [WEAK] EXPORT EXTI4_IRQHandler [WEAK] EXPORT DMA1_Channel1_IRQHandler [WEAK] EXPORT DMA1_Channel2_IRQHandler [WEAK] EXPORT DMA1_Channel3_IRQHandler [WEAK] EXPORT DMA1_Channel4_IRQHandler [WEAK] EXPORT DMA1_Channel5_IRQHandler [WEAK] EXPORT DMA1_Channel6_IRQHandler [WEAK] EXPORT DMA1_Channel7_IRQHandler [WEAK] EXPORT ADC1_2_IRQHandler [WEAK] EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] EXPORT CAN1_RX1_IRQHandler [WEAK] EXPORT CAN1_SCE_IRQHandler [WEAK] EXPORT EXTI9_5_IRQHandler [WEAK] EXPORT TIM1_BRK_IRQHandler [WEAK] EXPORT TIM1_UP_IRQHandler [WEAK] EXPORT TIM1_TRG_COM_IRQHandler [WEAK] EXPORT TIM1_CC_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT TIM3_IRQHandler [WEAK] EXPORT TIM4_IRQHandler [WEAK] EXPORT I2C1_EV_IRQHandler [WEAK] EXPORT I2C1_ER_IRQHandler [WEAK] EXPORT I2C2_EV_IRQHandler [WEAK] EXPORT I2C2_ER_IRQHandler [WEAK] EXPORT SPI1_IRQHandler [WEAK] EXPORT SPI2_IRQHandler [WEAK] EXPORT USART1_IRQHandler [WEAK] EXPORT USART2_IRQHandler [WEAK] EXPORT USART3_IRQHandler [WEAK] EXPORT EXTI15_10_IRQHandler [WEAK] EXPORT RTCAlarm_IRQHandler [WEAK] EXPORT USBWakeUp_IRQHandler [WEAK] EXPORT TIM8_BRK_IRQHandler [WEAK] EXPORT TIM8_UP_IRQHandler [WEAK] EXPORT TIM8_TRG_COM_IRQHandler [WEAK] EXPORT TIM8_CC_IRQHandler [WEAK] EXPORT ADC3_IRQHandler [WEAK] EXPORT FSMC_IRQHandler [WEAK] EXPORT SDIO_IRQHandler [WEAK] EXPORT TIM5_IRQHandler [WEAK] EXPORT SPI3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT UART5_IRQHandler [WEAK] EXPORT TIM6_IRQHandler [WEAK] EXPORT TIM7_IRQHandler [WEAK] EXPORT DMA2_Channel1_IRQHandler [WEAK] EXPORT DMA2_Channel2_IRQHandler [WEAK] EXPORT DMA2_Channel3_IRQHandler [WEAK] EXPORT DMA2_Channel4_5_IRQHandler [WEAK] WWDG_IRQHandler PVD_IRQHandler TAMPER_IRQHandler RTC_IRQHandler FLASH_IRQHandler RCC_IRQHandler EXTI0_IRQHandler EXTI1_IRQHandler EXTI2_IRQHandler EXTI3_IRQHandler EXTI4_IRQHandler DMA1_Channel1_IRQHandler DMA1_Channel2_IRQHandler DMA1_Channel3_IRQHandler DMA1_Channel4_IRQHandler DMA1_Channel5_IRQHandler DMA1_Channel6_IRQHandler DMA1_Channel7_IRQHandler ADC1_2_IRQHandler USB_HP_CAN1_TX_IRQHandler USB_LP_CAN1_RX0_IRQHandler CAN1_RX1_IRQHandler CAN1_SCE_IRQHandler EXTI9_5_IRQHandler TIM1_BRK_IRQHandler TIM1_UP_IRQHandler TIM1_TRG_COM_IRQHandler TIM1_CC_IRQHandler TIM2_IRQHandler TIM3_IRQHandler TIM4_IRQHandler I2C1_EV_IRQHandler I2C1_ER_IRQHandler I2C2_EV_IRQHandler I2C2_ER_IRQHandler SPI1_IRQHandler SPI2_IRQHandler USART1_IRQHandler USART2_IRQHandler USART3_IRQHandler EXTI15_10_IRQHandler RTCAlarm_IRQHandler USBWakeUp_IRQHandler TIM8_BRK_IRQHandler TIM8_UP_IRQHandler TIM8_TRG_COM_IRQHandler TIM8_CC_IRQHandler ADC3_IRQHandler FSMC_IRQHandler SDIO_IRQHandler TIM5_IRQHandler SPI3_IRQHandler UART4_IRQHandler UART5_IRQHandler TIM6_IRQHandler TIM7_IRQHandler DMA2_Channel1_IRQHandler DMA2_Channel2_IRQHandler DMA2_Channel3_IRQHandler DMA2_Channel4_5_IRQHandler B . ENDP ALIGN ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ALIGN ENDIF END ;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** src/bare_test/1.Led/cmsis/stm32f10x.h
File was renamed from src/bare_test/stm32_key/cmsis/stm32f10x.h Diff too large src/bare_test/1.Led/cmsis/stm32f10x_conf.h
File was renamed from src/bare_test/stm32_led/user/stm32f10x_conf.h @@ -1,77 +1,77 @@ /** ****************************************************************************** * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h * @author MCD Application Team * @version V3.5.0 * @date 08-April-2011 * @brief Library configuration file. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_CONF_H #define __STM32F10x_CONF_H /* Includes ------------------------------------------------------------------*/ /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */ #include "stm32f10x_adc.h" #include "stm32f10x_bkp.h" #include "stm32f10x_can.h" #include "stm32f10x_cec.h" #include "stm32f10x_crc.h" #include "stm32f10x_dac.h" #include "stm32f10x_dbgmcu.h" #include "stm32f10x_dma.h" #include "stm32f10x_exti.h" #include "stm32f10x_flash.h" #include "stm32f10x_fsmc.h" #include "stm32f10x_gpio.h" #include "stm32f10x_i2c.h" #include "stm32f10x_iwdg.h" #include "stm32f10x_pwr.h" #include "stm32f10x_rcc.h" #include "stm32f10x_rtc.h" #include "stm32f10x_sdio.h" #include "stm32f10x_spi.h" #include "stm32f10x_tim.h" #include "stm32f10x_usart.h" #include "stm32f10x_wwdg.h" #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* Uncomment the line below to expanse the "assert_param" macro in the Standard Peripheral Library drivers code */ /* #define USE_FULL_ASSERT 1 */ /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT /** * @brief The assert_param macro is used for function's parameters check. * @param expr: If expr is false, it calls assert_failed function which reports * the name of the source file and the source line number of the call * that failed. If expr is true, it returns no value. * @retval None */ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ void assert_failed(uint8_t* file, uint32_t line); #else #define assert_param(expr) ((void)0) #endif /* USE_FULL_ASSERT */ #endif /* __STM32F10x_CONF_H */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /** ****************************************************************************** * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h * @author MCD Application Team * @version V3.5.0 * @date 08-April-2011 * @brief Library configuration file. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_CONF_H #define __STM32F10x_CONF_H /* Includes ------------------------------------------------------------------*/ /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */ #include "stm32f10x_adc.h" #include "stm32f10x_bkp.h" #include "stm32f10x_can.h" #include "stm32f10x_cec.h" #include "stm32f10x_crc.h" #include "stm32f10x_dac.h" #include "stm32f10x_dbgmcu.h" #include "stm32f10x_dma.h" #include "stm32f10x_exti.h" #include "stm32f10x_flash.h" #include "stm32f10x_fsmc.h" #include "stm32f10x_gpio.h" #include "stm32f10x_i2c.h" #include "stm32f10x_iwdg.h" #include "stm32f10x_pwr.h" #include "stm32f10x_rcc.h" #include "stm32f10x_rtc.h" #include "stm32f10x_sdio.h" #include "stm32f10x_spi.h" #include "stm32f10x_tim.h" #include "stm32f10x_usart.h" #include "stm32f10x_wwdg.h" #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* Uncomment the line below to expanse the "assert_param" macro in the Standard Peripheral Library drivers code */ /* #define USE_FULL_ASSERT 1 */ /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT /** * @brief The assert_param macro is used for function's parameters check. * @param expr: If expr is false, it calls assert_failed function which reports * the name of the source file and the source line number of the call * that failed. If expr is true, it returns no value. * @retval None */ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ void assert_failed(uint8_t* file, uint32_t line); #else #define assert_param(expr) ((void)0) #endif /* USE_FULL_ASSERT */ #endif /* __STM32F10x_CONF_H */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ src/bare_test/1.Led/cmsis/system_stm32f10x.c
File was renamed from src/bare_test/stm32_key/cmsis/system_stm32f10x.c @@ -1,1094 +1,1094 @@ /** ****************************************************************************** * @file system_stm32f10x.c * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. * * 1. This file provides two functions and one global variable to be called from * user application: * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier * factors, AHB/APBx prescalers and Flash settings). * This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32f10x_xx.s" file. * * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used * by the user application to setup the SysTick * timer or configure other parameters. * * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must * be called whenever the core clock is changed * during program execution. * * 2. After each device reset the HSI (8 MHz) is used as system clock source. * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to * configure the system clock before to branch to main program. * * 3. If the system clock source selected by user fails to startup, the SystemInit() * function will do nothing and HSI still used as system clock source. User can * add some code to deal with this issue inside the SetSysClock() function. * * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. * When HSE is used as system clock source, directly or through PLL, and you * are using different crystal you have to adapt the HSE value to your own * configuration. * ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /** @addtogroup CMSIS * @{ */ /** @addtogroup stm32f10x_system * @{ */ /** @addtogroup STM32F10x_System_Private_Includes * @{ */ #include "stm32f10x.h" /** * @} */ /** @addtogroup STM32F10x_System_Private_TypesDefinitions * @{ */ /** * @} */ /** @addtogroup STM32F10x_System_Private_Defines * @{ */ /*!< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source) IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source. 2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency. 3. If none of the define below is enabled, the HSI is used as System clock source. 4. The System clock configuration functions provided within this file assume that: - For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock. - For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock. - For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. */ #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) /* #define SYSCLK_FREQ_HSE HSE_VALUE */ #define SYSCLK_FREQ_24MHz 24000000 #else /* #define SYSCLK_FREQ_HSE HSE_VALUE */ /* #define SYSCLK_FREQ_24MHz 24000000 */ /* #define SYSCLK_FREQ_36MHz 36000000 */ /* #define SYSCLK_FREQ_48MHz 48000000 */ /* #define SYSCLK_FREQ_56MHz 56000000 */ #define SYSCLK_FREQ_72MHz 72000000 #endif /*!< Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) /* #define DATA_IN_ExtSRAM */ #endif /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ /* #define VECT_TAB_SRAM */ #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ /** * @} */ /** @addtogroup STM32F10x_System_Private_Macros * @{ */ /** * @} */ /** @addtogroup STM32F10x_System_Private_Variables * @{ */ /******************************************************************************* * Clock Definitions *******************************************************************************/ #ifdef SYSCLK_FREQ_HSE uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ #elif defined SYSCLK_FREQ_24MHz uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ #elif defined SYSCLK_FREQ_36MHz uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ #elif defined SYSCLK_FREQ_48MHz uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ #elif defined SYSCLK_FREQ_56MHz uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ #elif defined SYSCLK_FREQ_72MHz uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ #else /*!< HSI Selected as System Clock source */ uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ #endif __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} */ /** @addtogroup STM32F10x_System_Private_FunctionPrototypes * @{ */ static void SetSysClock(void); #ifdef SYSCLK_FREQ_HSE static void SetSysClockToHSE(void); #elif defined SYSCLK_FREQ_24MHz static void SetSysClockTo24(void); #elif defined SYSCLK_FREQ_36MHz static void SetSysClockTo36(void); #elif defined SYSCLK_FREQ_48MHz static void SetSysClockTo48(void); #elif defined SYSCLK_FREQ_56MHz static void SetSysClockTo56(void); #elif defined SYSCLK_FREQ_72MHz static void SetSysClockTo72(void); #endif #ifdef DATA_IN_ExtSRAM static void SystemInit_ExtMemCtl(void); #endif /* DATA_IN_ExtSRAM */ /** * @} */ /** @addtogroup STM32F10x_System_Private_Functions * @{ */ /** * @brief Setup the microcontroller system * Initialize the Embedded Flash Interface, the PLL and update the * SystemCoreClock variable. * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ /* Set HSION bit */ RCC->CR |= (uint32_t)0x00000001; /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ #ifndef STM32F10X_CL RCC->CFGR &= (uint32_t)0xF8FF0000; #else RCC->CFGR &= (uint32_t)0xF0FF0000; #endif /* STM32F10X_CL */ /* Reset HSEON, CSSON and PLLON bits */ RCC->CR &= (uint32_t)0xFEF6FFFF; /* Reset HSEBYP bit */ RCC->CR &= (uint32_t)0xFFFBFFFF; /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ RCC->CFGR &= (uint32_t)0xFF80FFFF; #ifdef STM32F10X_CL /* Reset PLL2ON and PLL3ON bits */ RCC->CR &= (uint32_t)0xEBFFFFFF; /* Disable all interrupts and clear pending bits */ RCC->CIR = 0x00FF0000; /* Reset CFGR2 register */ RCC->CFGR2 = 0x00000000; #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) /* Disable all interrupts and clear pending bits */ RCC->CIR = 0x009F0000; /* Reset CFGR2 register */ RCC->CFGR2 = 0x00000000; #else /* Disable all interrupts and clear pending bits */ RCC->CIR = 0x009F0000; #endif /* STM32F10X_CL */ #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) #ifdef DATA_IN_ExtSRAM SystemInit_ExtMemCtl(); #endif /* DATA_IN_ExtSRAM */ #endif /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ /* Configure the Flash Latency cycles and enable prefetch buffer */ SetSysClock(); #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ #endif } /** * @brief Update SystemCoreClock variable according to Clock Register Values. * The SystemCoreClock variable contains the core clock (HCLK), it can * be used by the user application to setup the SysTick timer or configure * other parameters. * * @note Each time the core clock (HCLK) changes, this function must be called * to update SystemCoreClock variable value. Otherwise, any configuration * based on this variable will be incorrect. * * @note - The system frequency computed by this function is not the real * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: * * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) * * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) * * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) * or HSI_VALUE(*) multiplied by the PLL factors. * * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value * 8 MHz) but the real value may vary depending on the variations * in voltage and temperature. * * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value * 8 MHz or 25 MHz, depedning on the product used), user has to ensure * that HSE_VALUE is same as the real frequency of the crystal used. * Otherwise, this function may have wrong result. * * - The result of this function could be not correct when using fractional * value for HSE crystal. * @param None * @retval None */ void SystemCoreClockUpdate (void) { uint32_t tmp = 0, pllmull = 0, pllsource = 0; #ifdef STM32F10X_CL uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; #endif /* STM32F10X_CL */ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) uint32_t prediv1factor = 0; #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; switch (tmp) { case 0x00: /* HSI used as system clock */ SystemCoreClock = HSI_VALUE; break; case 0x04: /* HSE used as system clock */ SystemCoreClock = HSE_VALUE; break; case 0x08: /* PLL used as system clock */ /* Get PLL clock source and multiplication factor ----------------------*/ pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; #ifndef STM32F10X_CL pllmull = ( pllmull >> 18) + 2; if (pllsource == 0x00) { /* HSI oscillator clock divided by 2 selected as PLL clock entry */ SystemCoreClock = (HSI_VALUE >> 1) * pllmull; } else { #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; /* HSE oscillator clock selected as PREDIV1 clock entry */ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; #else /* HSE selected as PLL clock entry */ if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) {/* HSE oscillator clock divided by 2 */ SystemCoreClock = (HSE_VALUE >> 1) * pllmull; } else { SystemCoreClock = HSE_VALUE * pllmull; } #endif } #else pllmull = pllmull >> 18; if (pllmull != 0x0D) { pllmull += 2; } else { /* PLL multiplication factor = PLL input clock * 6.5 */ pllmull = 13 / 2; } if (pllsource == 0x00) { /* HSI oscillator clock divided by 2 selected as PLL clock entry */ SystemCoreClock = (HSI_VALUE >> 1) * pllmull; } else {/* PREDIV1 selected as PLL clock entry */ /* Get PREDIV1 clock source and division factor */ prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; if (prediv1source == 0) { /* HSE oscillator clock selected as PREDIV1 clock entry */ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; } else {/* PLL2 clock selected as PREDIV1 clock entry */ /* Get PREDIV2 division factor and PLL2 multiplication factor */ prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; } } #endif /* STM32F10X_CL */ break; default: SystemCoreClock = HSI_VALUE; break; } /* Compute HCLK clock frequency ----------------*/ /* Get HCLK prescaler */ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; /* HCLK clock frequency */ SystemCoreClock >>= tmp; } /** * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. * @param None * @retval None */ static void SetSysClock(void) { #ifdef SYSCLK_FREQ_HSE SetSysClockToHSE(); #elif defined SYSCLK_FREQ_24MHz SetSysClockTo24(); #elif defined SYSCLK_FREQ_36MHz SetSysClockTo36(); #elif defined SYSCLK_FREQ_48MHz SetSysClockTo48(); #elif defined SYSCLK_FREQ_56MHz SetSysClockTo56(); #elif defined SYSCLK_FREQ_72MHz SetSysClockTo72(); #endif /* If none of the define above is enabled, the HSI is used as System clock source (default after reset) */ } /** * @brief Setup the external memory controller. Called in startup_stm32f10x.s * before jump to __main * @param None * @retval None */ #ifdef DATA_IN_ExtSRAM /** * @brief Setup the external memory controller. * Called in startup_stm32f10x_xx.s/.c before jump to main. * This function configures the external SRAM mounted on STM3210E-EVAL * board (STM32 High density devices). This SRAM will be used as program * data memory (including heap and stack). * @param None * @retval None */ void SystemInit_ExtMemCtl(void) { /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is required, then adjust the Register Addresses */ /* Enable FSMC clock */ RCC->AHBENR = 0x00000114; /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ RCC->APB2ENR = 0x000001E0; /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ /*---------------- SRAM Address lines configuration -------------------------*/ /*---------------- NOE and NWE configuration --------------------------------*/ /*---------------- NE3 configuration ----------------------------------------*/ /*---------------- NBL0, NBL1 configuration ---------------------------------*/ GPIOD->CRL = 0x44BB44BB; GPIOD->CRH = 0xBBBBBBBB; GPIOE->CRL = 0xB44444BB; GPIOE->CRH = 0xBBBBBBBB; GPIOF->CRL = 0x44BBBBBB; GPIOF->CRH = 0xBBBB4444; GPIOG->CRL = 0x44BBBBBB; GPIOG->CRH = 0x44444B44; /*---------------- FSMC Configuration ---------------------------------------*/ /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ FSMC_Bank1->BTCR[4] = 0x00001011; FSMC_Bank1->BTCR[5] = 0x00000200; } #endif /* DATA_IN_ExtSRAM */ #ifdef SYSCLK_FREQ_HSE /** * @brief Selects HSE as System clock source and configure HCLK, PCLK2 * and PCLK1 prescalers. * @note This function should be used only after reset. * @param None * @retval None */ static void SetSysClockToHSE(void) { __IO uint32_t StartUpCounter = 0, HSEStatus = 0; /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ /* Enable HSE */ RCC->CR |= ((uint32_t)RCC_CR_HSEON); /* Wait till HSE is ready and if Time out is reached exit */ do { HSEStatus = RCC->CR & RCC_CR_HSERDY; StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); if ((RCC->CR & RCC_CR_HSERDY) != RESET) { HSEStatus = (uint32_t)0x01; } else { HSEStatus = (uint32_t)0x00; } if (HSEStatus == (uint32_t)0x01) { #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL /* Enable Prefetch Buffer */ FLASH->ACR |= FLASH_ACR_PRFTBE; /* Flash 0 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); #ifndef STM32F10X_CL FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; #else if (HSE_VALUE <= 24000000) { FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; } else { FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; } #endif /* STM32F10X_CL */ #endif /* HCLK = SYSCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; /* PCLK2 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; /* PCLK1 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; /* Select HSE as system clock source */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; /* Wait till HSE is used as system clock source */ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) { } } else { /* If HSE fails to start-up, the application will have wrong clock configuration. User can add here some code to deal with this error */ } } #elif defined SYSCLK_FREQ_24MHz /** * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 * and PCLK1 prescalers. * @note This function should be used only after reset. * @param None * @retval None */ static void SetSysClockTo24(void) { __IO uint32_t StartUpCounter = 0, HSEStatus = 0; /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ /* Enable HSE */ RCC->CR |= ((uint32_t)RCC_CR_HSEON); /* Wait till HSE is ready and if Time out is reached exit */ do { HSEStatus = RCC->CR & RCC_CR_HSERDY; StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); if ((RCC->CR & RCC_CR_HSERDY) != RESET) { HSEStatus = (uint32_t)0x01; } else { HSEStatus = (uint32_t)0x00; } if (HSEStatus == (uint32_t)0x01) { #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL /* Enable Prefetch Buffer */ FLASH->ACR |= FLASH_ACR_PRFTBE; /* Flash 0 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; #endif /* HCLK = SYSCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; /* PCLK2 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; /* PCLK1 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; #ifdef STM32F10X_CL /* Configure PLLs ------------------------------------------------------*/ /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLMULL6); /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); /* Enable PLL2 */ RCC->CR |= RCC_CR_PLL2ON; /* Wait till PLL2 is ready */ while((RCC->CR & RCC_CR_PLL2RDY) == 0) { } #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); #else /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); #endif /* STM32F10X_CL */ /* Enable PLL */ RCC->CR |= RCC_CR_PLLON; /* Wait till PLL is ready */ while((RCC->CR & RCC_CR_PLLRDY) == 0) { } /* Select PLL as system clock source */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; /* Wait till PLL is used as system clock source */ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) { } } else { /* If HSE fails to start-up, the application will have wrong clock configuration. User can add here some code to deal with this error */ } } #elif defined SYSCLK_FREQ_36MHz /** * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 * and PCLK1 prescalers. * @note This function should be used only after reset. * @param None * @retval None */ static void SetSysClockTo36(void) { __IO uint32_t StartUpCounter = 0, HSEStatus = 0; /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ /* Enable HSE */ RCC->CR |= ((uint32_t)RCC_CR_HSEON); /* Wait till HSE is ready and if Time out is reached exit */ do { HSEStatus = RCC->CR & RCC_CR_HSERDY; StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); if ((RCC->CR & RCC_CR_HSERDY) != RESET) { HSEStatus = (uint32_t)0x01; } else { HSEStatus = (uint32_t)0x00; } if (HSEStatus == (uint32_t)0x01) { /* Enable Prefetch Buffer */ FLASH->ACR |= FLASH_ACR_PRFTBE; /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; /* HCLK = SYSCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; /* PCLK2 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; /* PCLK1 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; #ifdef STM32F10X_CL /* Configure PLLs ------------------------------------------------------*/ /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLMULL9); /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); /* Enable PLL2 */ RCC->CR |= RCC_CR_PLL2ON; /* Wait till PLL2 is ready */ while((RCC->CR & RCC_CR_PLL2RDY) == 0) { } #else /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); #endif /* STM32F10X_CL */ /* Enable PLL */ RCC->CR |= RCC_CR_PLLON; /* Wait till PLL is ready */ while((RCC->CR & RCC_CR_PLLRDY) == 0) { } /* Select PLL as system clock source */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; /* Wait till PLL is used as system clock source */ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) { } } else { /* If HSE fails to start-up, the application will have wrong clock configuration. User can add here some code to deal with this error */ } } #elif defined SYSCLK_FREQ_48MHz /** * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 * and PCLK1 prescalers. * @note This function should be used only after reset. * @param None * @retval None */ static void SetSysClockTo48(void) { __IO uint32_t StartUpCounter = 0, HSEStatus = 0; /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ /* Enable HSE */ RCC->CR |= ((uint32_t)RCC_CR_HSEON); /* Wait till HSE is ready and if Time out is reached exit */ do { HSEStatus = RCC->CR & RCC_CR_HSERDY; StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); if ((RCC->CR & RCC_CR_HSERDY) != RESET) { HSEStatus = (uint32_t)0x01; } else { HSEStatus = (uint32_t)0x00; } if (HSEStatus == (uint32_t)0x01) { /* Enable Prefetch Buffer */ FLASH->ACR |= FLASH_ACR_PRFTBE; /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; /* HCLK = SYSCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; /* PCLK2 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; /* PCLK1 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; #ifdef STM32F10X_CL /* Configure PLLs ------------------------------------------------------*/ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); /* Enable PLL2 */ RCC->CR |= RCC_CR_PLL2ON; /* Wait till PLL2 is ready */ while((RCC->CR & RCC_CR_PLL2RDY) == 0) { } /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLMULL6); #else /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); #endif /* STM32F10X_CL */ /* Enable PLL */ RCC->CR |= RCC_CR_PLLON; /* Wait till PLL is ready */ while((RCC->CR & RCC_CR_PLLRDY) == 0) { } /* Select PLL as system clock source */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; /* Wait till PLL is used as system clock source */ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) { } } else { /* If HSE fails to start-up, the application will have wrong clock configuration. User can add here some code to deal with this error */ } } #elif defined SYSCLK_FREQ_56MHz /** * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 * and PCLK1 prescalers. * @note This function should be used only after reset. * @param None * @retval None */ static void SetSysClockTo56(void) { __IO uint32_t StartUpCounter = 0, HSEStatus = 0; /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ /* Enable HSE */ RCC->CR |= ((uint32_t)RCC_CR_HSEON); /* Wait till HSE is ready and if Time out is reached exit */ do { HSEStatus = RCC->CR & RCC_CR_HSERDY; StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); if ((RCC->CR & RCC_CR_HSERDY) != RESET) { HSEStatus = (uint32_t)0x01; } else { HSEStatus = (uint32_t)0x00; } if (HSEStatus == (uint32_t)0x01) { /* Enable Prefetch Buffer */ FLASH->ACR |= FLASH_ACR_PRFTBE; /* Flash 2 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; /* HCLK = SYSCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; /* PCLK2 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; /* PCLK1 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; #ifdef STM32F10X_CL /* Configure PLLs ------------------------------------------------------*/ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); /* Enable PLL2 */ RCC->CR |= RCC_CR_PLL2ON; /* Wait till PLL2 is ready */ while((RCC->CR & RCC_CR_PLL2RDY) == 0) { } /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLMULL7); #else /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); #endif /* STM32F10X_CL */ /* Enable PLL */ RCC->CR |= RCC_CR_PLLON; /* Wait till PLL is ready */ while((RCC->CR & RCC_CR_PLLRDY) == 0) { } /* Select PLL as system clock source */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; /* Wait till PLL is used as system clock source */ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) { } } else { /* If HSE fails to start-up, the application will have wrong clock configuration. User can add here some code to deal with this error */ } } #elif defined SYSCLK_FREQ_72MHz /** * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 * and PCLK1 prescalers. * @note This function should be used only after reset. * @param None * @retval None */ static void SetSysClockTo72(void) { __IO uint32_t StartUpCounter = 0, HSEStatus = 0; /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ /* Enable HSE */ RCC->CR |= ((uint32_t)RCC_CR_HSEON); /* Wait till HSE is ready and if Time out is reached exit */ do { HSEStatus = RCC->CR & RCC_CR_HSERDY; StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); if ((RCC->CR & RCC_CR_HSERDY) != RESET) { HSEStatus = (uint32_t)0x01; } else { HSEStatus = (uint32_t)0x00; } if (HSEStatus == (uint32_t)0x01) { /* Enable Prefetch Buffer */ FLASH->ACR |= FLASH_ACR_PRFTBE; /* Flash 2 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; /* HCLK = SYSCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; /* PCLK2 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; /* PCLK1 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; #ifdef STM32F10X_CL /* Configure PLLs ------------------------------------------------------*/ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); /* Enable PLL2 */ RCC->CR |= RCC_CR_PLL2ON; /* Wait till PLL2 is ready */ while((RCC->CR & RCC_CR_PLL2RDY) == 0) { } /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLMULL9); #else /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); #endif /* STM32F10X_CL */ /* Enable PLL */ RCC->CR |= RCC_CR_PLLON; /* Wait till PLL is ready */ while((RCC->CR & RCC_CR_PLLRDY) == 0) { } /* Select PLL as system clock source */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; /* Wait till PLL is used as system clock source */ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) { } } else { /* If HSE fails to start-up, the application will have wrong clock configuration. User can add here some code to deal with this error */ } } #endif /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /** ****************************************************************************** * @file system_stm32f10x.c * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. * * 1. This file provides two functions and one global variable to be called from * user application: * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier * factors, AHB/APBx prescalers and Flash settings). * This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32f10x_xx.s" file. * * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used * by the user application to setup the SysTick * timer or configure other parameters. * * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must * be called whenever the core clock is changed * during program execution. * * 2. After each device reset the HSI (8 MHz) is used as system clock source. * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to * configure the system clock before to branch to main program. * * 3. If the system clock source selected by user fails to startup, the SystemInit() * function will do nothing and HSI still used as system clock source. User can * add some code to deal with this issue inside the SetSysClock() function. * * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. * When HSE is used as system clock source, directly or through PLL, and you * are using different crystal you have to adapt the HSE value to your own * configuration. * ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /** @addtogroup CMSIS * @{ */ /** @addtogroup stm32f10x_system * @{ */ /** @addtogroup STM32F10x_System_Private_Includes * @{ */ #include "stm32f10x.h" /** * @} */ /** @addtogroup STM32F10x_System_Private_TypesDefinitions * @{ */ /** * @} */ /** @addtogroup STM32F10x_System_Private_Defines * @{ */ /*!< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source) IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source. 2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency. 3. If none of the define below is enabled, the HSI is used as System clock source. 4. The System clock configuration functions provided within this file assume that: - For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock. - For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock. - For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. */ #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) /* #define SYSCLK_FREQ_HSE HSE_VALUE */ #define SYSCLK_FREQ_24MHz 24000000 #else /* #define SYSCLK_FREQ_HSE HSE_VALUE */ /* #define SYSCLK_FREQ_24MHz 24000000 */ /* #define SYSCLK_FREQ_36MHz 36000000 */ /* #define SYSCLK_FREQ_48MHz 48000000 */ /* #define SYSCLK_FREQ_56MHz 56000000 */ #define SYSCLK_FREQ_72MHz 72000000 #endif /*!< Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) /* #define DATA_IN_ExtSRAM */ #endif /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ /* #define VECT_TAB_SRAM */ #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ /** * @} */ /** @addtogroup STM32F10x_System_Private_Macros * @{ */ /** * @} */ /** @addtogroup STM32F10x_System_Private_Variables * @{ */ /******************************************************************************* * Clock Definitions *******************************************************************************/ #ifdef SYSCLK_FREQ_HSE uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ #elif defined SYSCLK_FREQ_24MHz uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ #elif defined SYSCLK_FREQ_36MHz uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ #elif defined SYSCLK_FREQ_48MHz uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ #elif defined SYSCLK_FREQ_56MHz uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ #elif defined SYSCLK_FREQ_72MHz uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ #else /*!< HSI Selected as System Clock source */ uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ #endif __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} */ /** @addtogroup STM32F10x_System_Private_FunctionPrototypes * @{ */ static void SetSysClock(void); #ifdef SYSCLK_FREQ_HSE static void SetSysClockToHSE(void); #elif defined SYSCLK_FREQ_24MHz static void SetSysClockTo24(void); #elif defined SYSCLK_FREQ_36MHz static void SetSysClockTo36(void); #elif defined SYSCLK_FREQ_48MHz static void SetSysClockTo48(void); #elif defined SYSCLK_FREQ_56MHz static void SetSysClockTo56(void); #elif defined SYSCLK_FREQ_72MHz static void SetSysClockTo72(void); #endif #ifdef DATA_IN_ExtSRAM static void SystemInit_ExtMemCtl(void); #endif /* DATA_IN_ExtSRAM */ /** * @} */ /** @addtogroup STM32F10x_System_Private_Functions * @{ */ /** * @brief Setup the microcontroller system * Initialize the Embedded Flash Interface, the PLL and update the * SystemCoreClock variable. * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ /* Set HSION bit */ RCC->CR |= (uint32_t)0x00000001; /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ #ifndef STM32F10X_CL RCC->CFGR &= (uint32_t)0xF8FF0000; #else RCC->CFGR &= (uint32_t)0xF0FF0000; #endif /* STM32F10X_CL */ /* Reset HSEON, CSSON and PLLON bits */ RCC->CR &= (uint32_t)0xFEF6FFFF; /* Reset HSEBYP bit */ RCC->CR &= (uint32_t)0xFFFBFFFF; /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ RCC->CFGR &= (uint32_t)0xFF80FFFF; #ifdef STM32F10X_CL /* Reset PLL2ON and PLL3ON bits */ RCC->CR &= (uint32_t)0xEBFFFFFF; /* Disable all interrupts and clear pending bits */ RCC->CIR = 0x00FF0000; /* Reset CFGR2 register */ RCC->CFGR2 = 0x00000000; #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) /* Disable all interrupts and clear pending bits */ RCC->CIR = 0x009F0000; /* Reset CFGR2 register */ RCC->CFGR2 = 0x00000000; #else /* Disable all interrupts and clear pending bits */ RCC->CIR = 0x009F0000; #endif /* STM32F10X_CL */ #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) #ifdef DATA_IN_ExtSRAM SystemInit_ExtMemCtl(); #endif /* DATA_IN_ExtSRAM */ #endif /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ /* Configure the Flash Latency cycles and enable prefetch buffer */ SetSysClock(); #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ #endif } /** * @brief Update SystemCoreClock variable according to Clock Register Values. * The SystemCoreClock variable contains the core clock (HCLK), it can * be used by the user application to setup the SysTick timer or configure * other parameters. * * @note Each time the core clock (HCLK) changes, this function must be called * to update SystemCoreClock variable value. Otherwise, any configuration * based on this variable will be incorrect. * * @note - The system frequency computed by this function is not the real * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: * * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) * * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) * * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) * or HSI_VALUE(*) multiplied by the PLL factors. * * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value * 8 MHz) but the real value may vary depending on the variations * in voltage and temperature. * * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value * 8 MHz or 25 MHz, depedning on the product used), user has to ensure * that HSE_VALUE is same as the real frequency of the crystal used. * Otherwise, this function may have wrong result. * * - The result of this function could be not correct when using fractional * value for HSE crystal. * @param None * @retval None */ void SystemCoreClockUpdate (void) { uint32_t tmp = 0, pllmull = 0, pllsource = 0; #ifdef STM32F10X_CL uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; #endif /* STM32F10X_CL */ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) uint32_t prediv1factor = 0; #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; switch (tmp) { case 0x00: /* HSI used as system clock */ SystemCoreClock = HSI_VALUE; break; case 0x04: /* HSE used as system clock */ SystemCoreClock = HSE_VALUE; break; case 0x08: /* PLL used as system clock */ /* Get PLL clock source and multiplication factor ----------------------*/ pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; #ifndef STM32F10X_CL pllmull = ( pllmull >> 18) + 2; if (pllsource == 0x00) { /* HSI oscillator clock divided by 2 selected as PLL clock entry */ SystemCoreClock = (HSI_VALUE >> 1) * pllmull; } else { #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; /* HSE oscillator clock selected as PREDIV1 clock entry */ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; #else /* HSE selected as PLL clock entry */ if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) {/* HSE oscillator clock divided by 2 */ SystemCoreClock = (HSE_VALUE >> 1) * pllmull; } else { SystemCoreClock = HSE_VALUE * pllmull; } #endif } #else pllmull = pllmull >> 18; if (pllmull != 0x0D) { pllmull += 2; } else { /* PLL multiplication factor = PLL input clock * 6.5 */ pllmull = 13 / 2; } if (pllsource == 0x00) { /* HSI oscillator clock divided by 2 selected as PLL clock entry */ SystemCoreClock = (HSI_VALUE >> 1) * pllmull; } else {/* PREDIV1 selected as PLL clock entry */ /* Get PREDIV1 clock source and division factor */ prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; if (prediv1source == 0) { /* HSE oscillator clock selected as PREDIV1 clock entry */ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; } else {/* PLL2 clock selected as PREDIV1 clock entry */ /* Get PREDIV2 division factor and PLL2 multiplication factor */ prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; } } #endif /* STM32F10X_CL */ break; default: SystemCoreClock = HSI_VALUE; break; } /* Compute HCLK clock frequency ----------------*/ /* Get HCLK prescaler */ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; /* HCLK clock frequency */ SystemCoreClock >>= tmp; } /** * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. * @param None * @retval None */ static void SetSysClock(void) { #ifdef SYSCLK_FREQ_HSE SetSysClockToHSE(); #elif defined SYSCLK_FREQ_24MHz SetSysClockTo24(); #elif defined SYSCLK_FREQ_36MHz SetSysClockTo36(); #elif defined SYSCLK_FREQ_48MHz SetSysClockTo48(); #elif defined SYSCLK_FREQ_56MHz SetSysClockTo56(); #elif defined SYSCLK_FREQ_72MHz SetSysClockTo72(); #endif /* If none of the define above is enabled, the HSI is used as System clock source (default after reset) */ } /** * @brief Setup the external memory controller. Called in startup_stm32f10x.s * before jump to __main * @param None * @retval None */ #ifdef DATA_IN_ExtSRAM /** * @brief Setup the external memory controller. * Called in startup_stm32f10x_xx.s/.c before jump to main. * This function configures the external SRAM mounted on STM3210E-EVAL * board (STM32 High density devices). This SRAM will be used as program * data memory (including heap and stack). * @param None * @retval None */ void SystemInit_ExtMemCtl(void) { /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is required, then adjust the Register Addresses */ /* Enable FSMC clock */ RCC->AHBENR = 0x00000114; /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ RCC->APB2ENR = 0x000001E0; /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ /*---------------- SRAM Address lines configuration -------------------------*/ /*---------------- NOE and NWE configuration --------------------------------*/ /*---------------- NE3 configuration ----------------------------------------*/ /*---------------- NBL0, NBL1 configuration ---------------------------------*/ GPIOD->CRL = 0x44BB44BB; GPIOD->CRH = 0xBBBBBBBB; GPIOE->CRL = 0xB44444BB; GPIOE->CRH = 0xBBBBBBBB; GPIOF->CRL = 0x44BBBBBB; GPIOF->CRH = 0xBBBB4444; GPIOG->CRL = 0x44BBBBBB; GPIOG->CRH = 0x44444B44; /*---------------- FSMC Configuration ---------------------------------------*/ /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ FSMC_Bank1->BTCR[4] = 0x00001011; FSMC_Bank1->BTCR[5] = 0x00000200; } #endif /* DATA_IN_ExtSRAM */ #ifdef SYSCLK_FREQ_HSE /** * @brief Selects HSE as System clock source and configure HCLK, PCLK2 * and PCLK1 prescalers. * @note This function should be used only after reset. * @param None * @retval None */ static void SetSysClockToHSE(void) { __IO uint32_t StartUpCounter = 0, HSEStatus = 0; /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ /* Enable HSE */ RCC->CR |= ((uint32_t)RCC_CR_HSEON); /* Wait till HSE is ready and if Time out is reached exit */ do { HSEStatus = RCC->CR & RCC_CR_HSERDY; StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); if ((RCC->CR & RCC_CR_HSERDY) != RESET) { HSEStatus = (uint32_t)0x01; } else { HSEStatus = (uint32_t)0x00; } if (HSEStatus == (uint32_t)0x01) { #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL /* Enable Prefetch Buffer */ FLASH->ACR |= FLASH_ACR_PRFTBE; /* Flash 0 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); #ifndef STM32F10X_CL FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; #else if (HSE_VALUE <= 24000000) { FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; } else { FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; } #endif /* STM32F10X_CL */ #endif /* HCLK = SYSCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; /* PCLK2 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; /* PCLK1 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; /* Select HSE as system clock source */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; /* Wait till HSE is used as system clock source */ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) { } } else { /* If HSE fails to start-up, the application will have wrong clock configuration. User can add here some code to deal with this error */ } } #elif defined SYSCLK_FREQ_24MHz /** * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 * and PCLK1 prescalers. * @note This function should be used only after reset. * @param None * @retval None */ static void SetSysClockTo24(void) { __IO uint32_t StartUpCounter = 0, HSEStatus = 0; /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ /* Enable HSE */ RCC->CR |= ((uint32_t)RCC_CR_HSEON); /* Wait till HSE is ready and if Time out is reached exit */ do { HSEStatus = RCC->CR & RCC_CR_HSERDY; StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); if ((RCC->CR & RCC_CR_HSERDY) != RESET) { HSEStatus = (uint32_t)0x01; } else { HSEStatus = (uint32_t)0x00; } if (HSEStatus == (uint32_t)0x01) { #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL /* Enable Prefetch Buffer */ FLASH->ACR |= FLASH_ACR_PRFTBE; /* Flash 0 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; #endif /* HCLK = SYSCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; /* PCLK2 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; /* PCLK1 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; #ifdef STM32F10X_CL /* Configure PLLs ------------------------------------------------------*/ /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLMULL6); /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); /* Enable PLL2 */ RCC->CR |= RCC_CR_PLL2ON; /* Wait till PLL2 is ready */ while((RCC->CR & RCC_CR_PLL2RDY) == 0) { } #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); #else /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); #endif /* STM32F10X_CL */ /* Enable PLL */ RCC->CR |= RCC_CR_PLLON; /* Wait till PLL is ready */ while((RCC->CR & RCC_CR_PLLRDY) == 0) { } /* Select PLL as system clock source */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; /* Wait till PLL is used as system clock source */ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) { } } else { /* If HSE fails to start-up, the application will have wrong clock configuration. User can add here some code to deal with this error */ } } #elif defined SYSCLK_FREQ_36MHz /** * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 * and PCLK1 prescalers. * @note This function should be used only after reset. * @param None * @retval None */ static void SetSysClockTo36(void) { __IO uint32_t StartUpCounter = 0, HSEStatus = 0; /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ /* Enable HSE */ RCC->CR |= ((uint32_t)RCC_CR_HSEON); /* Wait till HSE is ready and if Time out is reached exit */ do { HSEStatus = RCC->CR & RCC_CR_HSERDY; StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); if ((RCC->CR & RCC_CR_HSERDY) != RESET) { HSEStatus = (uint32_t)0x01; } else { HSEStatus = (uint32_t)0x00; } if (HSEStatus == (uint32_t)0x01) { /* Enable Prefetch Buffer */ FLASH->ACR |= FLASH_ACR_PRFTBE; /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; /* HCLK = SYSCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; /* PCLK2 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; /* PCLK1 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; #ifdef STM32F10X_CL /* Configure PLLs ------------------------------------------------------*/ /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLMULL9); /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); /* Enable PLL2 */ RCC->CR |= RCC_CR_PLL2ON; /* Wait till PLL2 is ready */ while((RCC->CR & RCC_CR_PLL2RDY) == 0) { } #else /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); #endif /* STM32F10X_CL */ /* Enable PLL */ RCC->CR |= RCC_CR_PLLON; /* Wait till PLL is ready */ while((RCC->CR & RCC_CR_PLLRDY) == 0) { } /* Select PLL as system clock source */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; /* Wait till PLL is used as system clock source */ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) { } } else { /* If HSE fails to start-up, the application will have wrong clock configuration. User can add here some code to deal with this error */ } } #elif defined SYSCLK_FREQ_48MHz /** * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 * and PCLK1 prescalers. * @note This function should be used only after reset. * @param None * @retval None */ static void SetSysClockTo48(void) { __IO uint32_t StartUpCounter = 0, HSEStatus = 0; /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ /* Enable HSE */ RCC->CR |= ((uint32_t)RCC_CR_HSEON); /* Wait till HSE is ready and if Time out is reached exit */ do { HSEStatus = RCC->CR & RCC_CR_HSERDY; StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); if ((RCC->CR & RCC_CR_HSERDY) != RESET) { HSEStatus = (uint32_t)0x01; } else { HSEStatus = (uint32_t)0x00; } if (HSEStatus == (uint32_t)0x01) { /* Enable Prefetch Buffer */ FLASH->ACR |= FLASH_ACR_PRFTBE; /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; /* HCLK = SYSCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; /* PCLK2 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; /* PCLK1 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; #ifdef STM32F10X_CL /* Configure PLLs ------------------------------------------------------*/ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); /* Enable PLL2 */ RCC->CR |= RCC_CR_PLL2ON; /* Wait till PLL2 is ready */ while((RCC->CR & RCC_CR_PLL2RDY) == 0) { } /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLMULL6); #else /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); #endif /* STM32F10X_CL */ /* Enable PLL */ RCC->CR |= RCC_CR_PLLON; /* Wait till PLL is ready */ while((RCC->CR & RCC_CR_PLLRDY) == 0) { } /* Select PLL as system clock source */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; /* Wait till PLL is used as system clock source */ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) { } } else { /* If HSE fails to start-up, the application will have wrong clock configuration. User can add here some code to deal with this error */ } } #elif defined SYSCLK_FREQ_56MHz /** * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 * and PCLK1 prescalers. * @note This function should be used only after reset. * @param None * @retval None */ static void SetSysClockTo56(void) { __IO uint32_t StartUpCounter = 0, HSEStatus = 0; /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ /* Enable HSE */ RCC->CR |= ((uint32_t)RCC_CR_HSEON); /* Wait till HSE is ready and if Time out is reached exit */ do { HSEStatus = RCC->CR & RCC_CR_HSERDY; StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); if ((RCC->CR & RCC_CR_HSERDY) != RESET) { HSEStatus = (uint32_t)0x01; } else { HSEStatus = (uint32_t)0x00; } if (HSEStatus == (uint32_t)0x01) { /* Enable Prefetch Buffer */ FLASH->ACR |= FLASH_ACR_PRFTBE; /* Flash 2 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; /* HCLK = SYSCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; /* PCLK2 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; /* PCLK1 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; #ifdef STM32F10X_CL /* Configure PLLs ------------------------------------------------------*/ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); /* Enable PLL2 */ RCC->CR |= RCC_CR_PLL2ON; /* Wait till PLL2 is ready */ while((RCC->CR & RCC_CR_PLL2RDY) == 0) { } /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLMULL7); #else /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); #endif /* STM32F10X_CL */ /* Enable PLL */ RCC->CR |= RCC_CR_PLLON; /* Wait till PLL is ready */ while((RCC->CR & RCC_CR_PLLRDY) == 0) { } /* Select PLL as system clock source */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; /* Wait till PLL is used as system clock source */ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) { } } else { /* If HSE fails to start-up, the application will have wrong clock configuration. User can add here some code to deal with this error */ } } #elif defined SYSCLK_FREQ_72MHz /** * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 * and PCLK1 prescalers. * @note This function should be used only after reset. * @param None * @retval None */ static void SetSysClockTo72(void) { __IO uint32_t StartUpCounter = 0, HSEStatus = 0; /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ /* Enable HSE */ RCC->CR |= ((uint32_t)RCC_CR_HSEON); /* Wait till HSE is ready and if Time out is reached exit */ do { HSEStatus = RCC->CR & RCC_CR_HSERDY; StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); if ((RCC->CR & RCC_CR_HSERDY) != RESET) { HSEStatus = (uint32_t)0x01; } else { HSEStatus = (uint32_t)0x00; } if (HSEStatus == (uint32_t)0x01) { /* Enable Prefetch Buffer */ FLASH->ACR |= FLASH_ACR_PRFTBE; /* Flash 2 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; /* HCLK = SYSCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; /* PCLK2 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; /* PCLK1 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; #ifdef STM32F10X_CL /* Configure PLLs ------------------------------------------------------*/ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); /* Enable PLL2 */ RCC->CR |= RCC_CR_PLL2ON; /* Wait till PLL2 is ready */ while((RCC->CR & RCC_CR_PLL2RDY) == 0) { } /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLMULL9); #else /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); #endif /* STM32F10X_CL */ /* Enable PLL */ RCC->CR |= RCC_CR_PLLON; /* Wait till PLL is ready */ while((RCC->CR & RCC_CR_PLLRDY) == 0) { } /* Select PLL as system clock source */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; /* Wait till PLL is used as system clock source */ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) { } } else { /* If HSE fails to start-up, the application will have wrong clock configuration. User can add here some code to deal with this error */ } } #endif /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ src/bare_test/1.Led/cmsis/system_stm32f10x.h
File was renamed from src/bare_test/stm32_key/cmsis/system_stm32f10x.h @@ -1,98 +1,98 @@ /** ****************************************************************************** * @file system_stm32f10x.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /** @addtogroup CMSIS * @{ */ /** @addtogroup stm32f10x_system * @{ */ /** * @brief Define to prevent recursive inclusion */ #ifndef __SYSTEM_STM32F10X_H #define __SYSTEM_STM32F10X_H #ifdef __cplusplus extern "C" { #endif /** @addtogroup STM32F10x_System_Includes * @{ */ /** * @} */ /** @addtogroup STM32F10x_System_Exported_types * @{ */ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ /** * @} */ /** @addtogroup STM32F10x_System_Exported_Constants * @{ */ /** * @} */ /** @addtogroup STM32F10x_System_Exported_Macros * @{ */ /** * @} */ /** @addtogroup STM32F10x_System_Exported_Functions * @{ */ extern void SystemInit(void); extern void SystemCoreClockUpdate(void); /** * @} */ #ifdef __cplusplus } #endif #endif /*__SYSTEM_STM32F10X_H */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /** ****************************************************************************** * @file system_stm32f10x.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /** @addtogroup CMSIS * @{ */ /** @addtogroup stm32f10x_system * @{ */ /** * @brief Define to prevent recursive inclusion */ #ifndef __SYSTEM_STM32F10X_H #define __SYSTEM_STM32F10X_H #ifdef __cplusplus extern "C" { #endif /** @addtogroup STM32F10x_System_Includes * @{ */ /** * @} */ /** @addtogroup STM32F10x_System_Exported_types * @{ */ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ /** * @} */ /** @addtogroup STM32F10x_System_Exported_Constants * @{ */ /** * @} */ /** @addtogroup STM32F10x_System_Exported_Macros * @{ */ /** * @} */ /** @addtogroup STM32F10x_System_Exported_Functions * @{ */ extern void SystemInit(void); extern void SystemCoreClockUpdate(void); /** * @} */ #ifdef __cplusplus } #endif #endif /*__SYSTEM_STM32F10X_H */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ src/bare_test/1.Led/keil_clean.bat
File was renamed from src/bare_test/stm32_key/keil_clean.bat @@ -1,19 +1,19 @@ del *.d /s del *.o /s del *.bak /s del *.dep /s del *.htm /s del *.lnp /s del *.sct /s del *.map /s del *.crf /s del *.tra /s del *.axf /s del *.hex /s del *.plg /s del *.lst /s del *.__i /s del *.iex /s del *.txt /s del JLinkLog.txt /s del *.d /s del *.o /s del *.bak /s del *.dep /s del *.htm /s del *.lnp /s del *.sct /s del *.map /s del *.crf /s del *.tra /s del *.axf /s del *.hex /s del *.plg /s del *.lst /s del *.__i /s del *.iex /s del *.txt /s del JLinkLog.txt /s
File was renamed from src/bare_test/stm32_key/fwlib/inc/misc.h @@ -1,220 +1,220 @@ /** ****************************************************************************** * @file misc.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the miscellaneous * firmware library functions (add-on to CMSIS functions). ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __MISC_H #define __MISC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup MISC * @{ */ /** @defgroup MISC_Exported_Types * @{ */ /** * @brief NVIC Init Structure definition */ typedef struct { uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. This parameter can be a value of @ref IRQn_Type (For the complete STM32 Devices IRQ Channels list, please refer to stm32f10x.h file) */ uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel specified in NVIC_IRQChannel. This parameter can be a value between 0 and 15 as described in the table @ref NVIC_Priority_Table */ uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified in NVIC_IRQChannel. This parameter can be a value between 0 and 15 as described in the table @ref NVIC_Priority_Table */ FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel will be enabled or disabled. This parameter can be set either to ENABLE or DISABLE */ } NVIC_InitTypeDef; /** * @} */ /** @defgroup NVIC_Priority_Table * @{ */ /** @code The table below gives the allowed values of the pre-emption priority and subpriority according to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function ============================================================================================================================ NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description ============================================================================================================================ NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority | | | 4 bits for subpriority ---------------------------------------------------------------------------------------------------------------------------- NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority | | | 3 bits for subpriority ---------------------------------------------------------------------------------------------------------------------------- NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority | | | 2 bits for subpriority ---------------------------------------------------------------------------------------------------------------------------- NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority | | | 1 bits for subpriority ---------------------------------------------------------------------------------------------------------------------------- NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority | | | 0 bits for subpriority ============================================================================================================================ @endcode */ /** * @} */ /** @defgroup MISC_Exported_Constants * @{ */ /** @defgroup Vector_Table_Base * @{ */ #define NVIC_VectTab_RAM ((uint32_t)0x20000000) #define NVIC_VectTab_FLASH ((uint32_t)0x08000000) #define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ ((VECTTAB) == NVIC_VectTab_FLASH)) /** * @} */ /** @defgroup System_Low_Power * @{ */ #define NVIC_LP_SEVONPEND ((uint8_t)0x10) #define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) #define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) #define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ ((LP) == NVIC_LP_SLEEPDEEP) || \ ((LP) == NVIC_LP_SLEEPONEXIT)) /** * @} */ /** @defgroup Preemption_Priority_Group * @{ */ #define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */ #define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */ #define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */ #define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */ #define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */ #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ ((GROUP) == NVIC_PriorityGroup_1) || \ ((GROUP) == NVIC_PriorityGroup_2) || \ ((GROUP) == NVIC_PriorityGroup_3) || \ ((GROUP) == NVIC_PriorityGroup_4)) #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) #define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) /** * @} */ /** @defgroup SysTick_clock_source * @{ */ #define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) #define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) /** * @} */ /** * @} */ /** @defgroup MISC_Exported_Macros * @{ */ /** * @} */ /** @defgroup MISC_Exported_Functions * @{ */ void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); #ifdef __cplusplus } #endif #endif /* __MISC_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /** ****************************************************************************** * @file misc.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the miscellaneous * firmware library functions (add-on to CMSIS functions). ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __MISC_H #define __MISC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup MISC * @{ */ /** @defgroup MISC_Exported_Types * @{ */ /** * @brief NVIC Init Structure definition */ typedef struct { uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. This parameter can be a value of @ref IRQn_Type (For the complete STM32 Devices IRQ Channels list, please refer to stm32f10x.h file) */ uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel specified in NVIC_IRQChannel. This parameter can be a value between 0 and 15 as described in the table @ref NVIC_Priority_Table */ uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified in NVIC_IRQChannel. This parameter can be a value between 0 and 15 as described in the table @ref NVIC_Priority_Table */ FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel will be enabled or disabled. This parameter can be set either to ENABLE or DISABLE */ } NVIC_InitTypeDef; /** * @} */ /** @defgroup NVIC_Priority_Table * @{ */ /** @code The table below gives the allowed values of the pre-emption priority and subpriority according to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function ============================================================================================================================ NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description ============================================================================================================================ NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority | | | 4 bits for subpriority ---------------------------------------------------------------------------------------------------------------------------- NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority | | | 3 bits for subpriority ---------------------------------------------------------------------------------------------------------------------------- NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority | | | 2 bits for subpriority ---------------------------------------------------------------------------------------------------------------------------- NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority | | | 1 bits for subpriority ---------------------------------------------------------------------------------------------------------------------------- NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority | | | 0 bits for subpriority ============================================================================================================================ @endcode */ /** * @} */ /** @defgroup MISC_Exported_Constants * @{ */ /** @defgroup Vector_Table_Base * @{ */ #define NVIC_VectTab_RAM ((uint32_t)0x20000000) #define NVIC_VectTab_FLASH ((uint32_t)0x08000000) #define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ ((VECTTAB) == NVIC_VectTab_FLASH)) /** * @} */ /** @defgroup System_Low_Power * @{ */ #define NVIC_LP_SEVONPEND ((uint8_t)0x10) #define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) #define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) #define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ ((LP) == NVIC_LP_SLEEPDEEP) || \ ((LP) == NVIC_LP_SLEEPONEXIT)) /** * @} */ /** @defgroup Preemption_Priority_Group * @{ */ #define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */ #define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */ #define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */ #define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */ #define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */ #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ ((GROUP) == NVIC_PriorityGroup_1) || \ ((GROUP) == NVIC_PriorityGroup_2) || \ ((GROUP) == NVIC_PriorityGroup_3) || \ ((GROUP) == NVIC_PriorityGroup_4)) #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) #define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) /** * @} */ /** @defgroup SysTick_clock_source * @{ */ #define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) #define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) /** * @} */ /** * @} */ /** @defgroup MISC_Exported_Macros * @{ */ /** * @} */ /** @defgroup MISC_Exported_Functions * @{ */ void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); #ifdef __cplusplus } #endif #endif /* __MISC_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ src/bare_test/1.Led/stdlib/inc/stm32f10x_adc.h
File was renamed from src/bare_test/stm32_key/fwlib/inc/stm32f10x_adc.h @@ -1,483 +1,483 @@ /** ****************************************************************************** * @file stm32f10x_adc.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the ADC firmware * library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_ADC_H #define __STM32F10x_ADC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup ADC * @{ */ /** @defgroup ADC_Exported_Types * @{ */ /** * @brief ADC Init structure definition */ typedef struct { uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or dual mode. This parameter can be a value of @ref ADC_mode */ FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in Scan (multichannels) or Single (one channel) mode. This parameter can be set to ENABLE or DISABLE */ FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in Continuous or Single mode. This parameter can be set to ENABLE or DISABLE. */ uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog to digital conversion of regular channels. This parameter can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right. This parameter can be a value of @ref ADC_data_align */ uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted using the sequencer for regular channel group. This parameter must range from 1 to 16. */ }ADC_InitTypeDef; /** * @} */ /** @defgroup ADC_Exported_Constants * @{ */ #define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ ((PERIPH) == ADC2) || \ ((PERIPH) == ADC3)) #define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ ((PERIPH) == ADC3)) /** @defgroup ADC_mode * @{ */ #define ADC_Mode_Independent ((uint32_t)0x00000000) #define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) #define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) #define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) #define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) #define ADC_Mode_InjecSimult ((uint32_t)0x00050000) #define ADC_Mode_RegSimult ((uint32_t)0x00060000) #define ADC_Mode_FastInterl ((uint32_t)0x00070000) #define ADC_Mode_SlowInterl ((uint32_t)0x00080000) #define ADC_Mode_AlterTrig ((uint32_t)0x00090000) #define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ ((MODE) == ADC_Mode_RegInjecSimult) || \ ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \ ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \ ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \ ((MODE) == ADC_Mode_InjecSimult) || \ ((MODE) == ADC_Mode_RegSimult) || \ ((MODE) == ADC_Mode_FastInterl) || \ ((MODE) == ADC_Mode_SlowInterl) || \ ((MODE) == ADC_Mode_AlterTrig)) /** * @} */ /** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion * @{ */ #define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */ #define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */ #define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */ #define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */ #define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */ #define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */ #define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */ #define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */ #define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */ #define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */ #define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */ #define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */ #define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */ #define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */ #define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \ ((REGTRIG) == ADC_ExternalTrigConv_None) || \ ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3)) /** * @} */ /** @defgroup ADC_data_align * @{ */ #define ADC_DataAlign_Right ((uint32_t)0x00000000) #define ADC_DataAlign_Left ((uint32_t)0x00000800) #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ ((ALIGN) == ADC_DataAlign_Left)) /** * @} */ /** @defgroup ADC_channels * @{ */ #define ADC_Channel_0 ((uint8_t)0x00) #define ADC_Channel_1 ((uint8_t)0x01) #define ADC_Channel_2 ((uint8_t)0x02) #define ADC_Channel_3 ((uint8_t)0x03) #define ADC_Channel_4 ((uint8_t)0x04) #define ADC_Channel_5 ((uint8_t)0x05) #define ADC_Channel_6 ((uint8_t)0x06) #define ADC_Channel_7 ((uint8_t)0x07) #define ADC_Channel_8 ((uint8_t)0x08) #define ADC_Channel_9 ((uint8_t)0x09) #define ADC_Channel_10 ((uint8_t)0x0A) #define ADC_Channel_11 ((uint8_t)0x0B) #define ADC_Channel_12 ((uint8_t)0x0C) #define ADC_Channel_13 ((uint8_t)0x0D) #define ADC_Channel_14 ((uint8_t)0x0E) #define ADC_Channel_15 ((uint8_t)0x0F) #define ADC_Channel_16 ((uint8_t)0x10) #define ADC_Channel_17 ((uint8_t)0x11) #define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) #define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \ ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \ ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \ ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \ ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \ ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \ ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \ ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \ ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17)) /** * @} */ /** @defgroup ADC_sampling_time * @{ */ #define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) #define ADC_SampleTime_7Cycles5 ((uint8_t)0x01) #define ADC_SampleTime_13Cycles5 ((uint8_t)0x02) #define ADC_SampleTime_28Cycles5 ((uint8_t)0x03) #define ADC_SampleTime_41Cycles5 ((uint8_t)0x04) #define ADC_SampleTime_55Cycles5 ((uint8_t)0x05) #define ADC_SampleTime_71Cycles5 ((uint8_t)0x06) #define ADC_SampleTime_239Cycles5 ((uint8_t)0x07) #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \ ((TIME) == ADC_SampleTime_7Cycles5) || \ ((TIME) == ADC_SampleTime_13Cycles5) || \ ((TIME) == ADC_SampleTime_28Cycles5) || \ ((TIME) == ADC_SampleTime_41Cycles5) || \ ((TIME) == ADC_SampleTime_55Cycles5) || \ ((TIME) == ADC_SampleTime_71Cycles5) || \ ((TIME) == ADC_SampleTime_239Cycles5)) /** * @} */ /** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion * @{ */ #define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */ #define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */ #define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */ #define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */ #define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */ #define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */ #define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */ #define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */ #define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */ #define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */ #define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */ #define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */ #define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */ #define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4)) /** * @} */ /** @defgroup ADC_injected_channel_selection * @{ */ #define ADC_InjectedChannel_1 ((uint8_t)0x14) #define ADC_InjectedChannel_2 ((uint8_t)0x18) #define ADC_InjectedChannel_3 ((uint8_t)0x1C) #define ADC_InjectedChannel_4 ((uint8_t)0x20) #define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ ((CHANNEL) == ADC_InjectedChannel_2) || \ ((CHANNEL) == ADC_InjectedChannel_3) || \ ((CHANNEL) == ADC_InjectedChannel_4)) /** * @} */ /** @defgroup ADC_analog_watchdog_selection * @{ */ #define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) #define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) #define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) #define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) #define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) #define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) #define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) #define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ ((WATCHDOG) == ADC_AnalogWatchdog_None)) /** * @} */ /** @defgroup ADC_interrupts_definition * @{ */ #define ADC_IT_EOC ((uint16_t)0x0220) #define ADC_IT_AWD ((uint16_t)0x0140) #define ADC_IT_JEOC ((uint16_t)0x0480) #define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00)) #define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \ ((IT) == ADC_IT_JEOC)) /** * @} */ /** @defgroup ADC_flags_definition * @{ */ #define ADC_FLAG_AWD ((uint8_t)0x01) #define ADC_FLAG_EOC ((uint8_t)0x02) #define ADC_FLAG_JEOC ((uint8_t)0x04) #define ADC_FLAG_JSTRT ((uint8_t)0x08) #define ADC_FLAG_STRT ((uint8_t)0x10) #define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00)) #define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \ ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \ ((FLAG) == ADC_FLAG_STRT)) /** * @} */ /** @defgroup ADC_thresholds * @{ */ #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) /** * @} */ /** @defgroup ADC_injected_offset * @{ */ #define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) /** * @} */ /** @defgroup ADC_injected_length * @{ */ #define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) /** * @} */ /** @defgroup ADC_injected_rank * @{ */ #define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) /** * @} */ /** @defgroup ADC_regular_length * @{ */ #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) /** * @} */ /** @defgroup ADC_regular_rank * @{ */ #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) /** * @} */ /** @defgroup ADC_regular_discontinuous_mode_number * @{ */ #define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) /** * @} */ /** * @} */ /** @defgroup ADC_Exported_Macros * @{ */ /** * @} */ /** @defgroup ADC_Exported_Functions * @{ */ void ADC_DeInit(ADC_TypeDef* ADCx); void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); void ADC_ResetCalibration(ADC_TypeDef* ADCx); FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx); void ADC_StartCalibration(ADC_TypeDef* ADCx); FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx); void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); uint32_t ADC_GetDualModeConversionValue(void); void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold); void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); void ADC_TempSensorVrefintCmd(FunctionalState NewState); FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); #ifdef __cplusplus } #endif #endif /*__STM32F10x_ADC_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /** ****************************************************************************** * @file stm32f10x_adc.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the ADC firmware * library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_ADC_H #define __STM32F10x_ADC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup ADC * @{ */ /** @defgroup ADC_Exported_Types * @{ */ /** * @brief ADC Init structure definition */ typedef struct { uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or dual mode. This parameter can be a value of @ref ADC_mode */ FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in Scan (multichannels) or Single (one channel) mode. This parameter can be set to ENABLE or DISABLE */ FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in Continuous or Single mode. This parameter can be set to ENABLE or DISABLE. */ uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog to digital conversion of regular channels. This parameter can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right. This parameter can be a value of @ref ADC_data_align */ uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted using the sequencer for regular channel group. This parameter must range from 1 to 16. */ }ADC_InitTypeDef; /** * @} */ /** @defgroup ADC_Exported_Constants * @{ */ #define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ ((PERIPH) == ADC2) || \ ((PERIPH) == ADC3)) #define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ ((PERIPH) == ADC3)) /** @defgroup ADC_mode * @{ */ #define ADC_Mode_Independent ((uint32_t)0x00000000) #define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) #define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) #define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) #define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) #define ADC_Mode_InjecSimult ((uint32_t)0x00050000) #define ADC_Mode_RegSimult ((uint32_t)0x00060000) #define ADC_Mode_FastInterl ((uint32_t)0x00070000) #define ADC_Mode_SlowInterl ((uint32_t)0x00080000) #define ADC_Mode_AlterTrig ((uint32_t)0x00090000) #define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ ((MODE) == ADC_Mode_RegInjecSimult) || \ ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \ ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \ ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \ ((MODE) == ADC_Mode_InjecSimult) || \ ((MODE) == ADC_Mode_RegSimult) || \ ((MODE) == ADC_Mode_FastInterl) || \ ((MODE) == ADC_Mode_SlowInterl) || \ ((MODE) == ADC_Mode_AlterTrig)) /** * @} */ /** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion * @{ */ #define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */ #define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */ #define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */ #define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */ #define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */ #define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */ #define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */ #define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */ #define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */ #define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */ #define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */ #define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */ #define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */ #define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */ #define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \ ((REGTRIG) == ADC_ExternalTrigConv_None) || \ ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3)) /** * @} */ /** @defgroup ADC_data_align * @{ */ #define ADC_DataAlign_Right ((uint32_t)0x00000000) #define ADC_DataAlign_Left ((uint32_t)0x00000800) #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ ((ALIGN) == ADC_DataAlign_Left)) /** * @} */ /** @defgroup ADC_channels * @{ */ #define ADC_Channel_0 ((uint8_t)0x00) #define ADC_Channel_1 ((uint8_t)0x01) #define ADC_Channel_2 ((uint8_t)0x02) #define ADC_Channel_3 ((uint8_t)0x03) #define ADC_Channel_4 ((uint8_t)0x04) #define ADC_Channel_5 ((uint8_t)0x05) #define ADC_Channel_6 ((uint8_t)0x06) #define ADC_Channel_7 ((uint8_t)0x07) #define ADC_Channel_8 ((uint8_t)0x08) #define ADC_Channel_9 ((uint8_t)0x09) #define ADC_Channel_10 ((uint8_t)0x0A) #define ADC_Channel_11 ((uint8_t)0x0B) #define ADC_Channel_12 ((uint8_t)0x0C) #define ADC_Channel_13 ((uint8_t)0x0D) #define ADC_Channel_14 ((uint8_t)0x0E) #define ADC_Channel_15 ((uint8_t)0x0F) #define ADC_Channel_16 ((uint8_t)0x10) #define ADC_Channel_17 ((uint8_t)0x11) #define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) #define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \ ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \ ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \ ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \ ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \ ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \ ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \ ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \ ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17)) /** * @} */ /** @defgroup ADC_sampling_time * @{ */ #define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) #define ADC_SampleTime_7Cycles5 ((uint8_t)0x01) #define ADC_SampleTime_13Cycles5 ((uint8_t)0x02) #define ADC_SampleTime_28Cycles5 ((uint8_t)0x03) #define ADC_SampleTime_41Cycles5 ((uint8_t)0x04) #define ADC_SampleTime_55Cycles5 ((uint8_t)0x05) #define ADC_SampleTime_71Cycles5 ((uint8_t)0x06) #define ADC_SampleTime_239Cycles5 ((uint8_t)0x07) #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \ ((TIME) == ADC_SampleTime_7Cycles5) || \ ((TIME) == ADC_SampleTime_13Cycles5) || \ ((TIME) == ADC_SampleTime_28Cycles5) || \ ((TIME) == ADC_SampleTime_41Cycles5) || \ ((TIME) == ADC_SampleTime_55Cycles5) || \ ((TIME) == ADC_SampleTime_71Cycles5) || \ ((TIME) == ADC_SampleTime_239Cycles5)) /** * @} */ /** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion * @{ */ #define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */ #define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */ #define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */ #define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */ #define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */ #define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */ #define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */ #define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */ #define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */ #define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */ #define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */ #define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */ #define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */ #define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4)) /** * @} */ /** @defgroup ADC_injected_channel_selection * @{ */ #define ADC_InjectedChannel_1 ((uint8_t)0x14) #define ADC_InjectedChannel_2 ((uint8_t)0x18) #define ADC_InjectedChannel_3 ((uint8_t)0x1C) #define ADC_InjectedChannel_4 ((uint8_t)0x20) #define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ ((CHANNEL) == ADC_InjectedChannel_2) || \ ((CHANNEL) == ADC_InjectedChannel_3) || \ ((CHANNEL) == ADC_InjectedChannel_4)) /** * @} */ /** @defgroup ADC_analog_watchdog_selection * @{ */ #define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) #define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) #define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) #define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) #define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) #define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) #define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) #define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ ((WATCHDOG) == ADC_AnalogWatchdog_None)) /** * @} */ /** @defgroup ADC_interrupts_definition * @{ */ #define ADC_IT_EOC ((uint16_t)0x0220) #define ADC_IT_AWD ((uint16_t)0x0140) #define ADC_IT_JEOC ((uint16_t)0x0480) #define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00)) #define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \ ((IT) == ADC_IT_JEOC)) /** * @} */ /** @defgroup ADC_flags_definition * @{ */ #define ADC_FLAG_AWD ((uint8_t)0x01) #define ADC_FLAG_EOC ((uint8_t)0x02) #define ADC_FLAG_JEOC ((uint8_t)0x04) #define ADC_FLAG_JSTRT ((uint8_t)0x08) #define ADC_FLAG_STRT ((uint8_t)0x10) #define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00)) #define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \ ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \ ((FLAG) == ADC_FLAG_STRT)) /** * @} */ /** @defgroup ADC_thresholds * @{ */ #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) /** * @} */ /** @defgroup ADC_injected_offset * @{ */ #define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) /** * @} */ /** @defgroup ADC_injected_length * @{ */ #define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) /** * @} */ /** @defgroup ADC_injected_rank * @{ */ #define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) /** * @} */ /** @defgroup ADC_regular_length * @{ */ #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) /** * @} */ /** @defgroup ADC_regular_rank * @{ */ #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) /** * @} */ /** @defgroup ADC_regular_discontinuous_mode_number * @{ */ #define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) /** * @} */ /** * @} */ /** @defgroup ADC_Exported_Macros * @{ */ /** * @} */ /** @defgroup ADC_Exported_Functions * @{ */ void ADC_DeInit(ADC_TypeDef* ADCx); void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); void ADC_ResetCalibration(ADC_TypeDef* ADCx); FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx); void ADC_StartCalibration(ADC_TypeDef* ADCx); FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx); void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); uint32_t ADC_GetDualModeConversionValue(void); void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold); void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); void ADC_TempSensorVrefintCmd(FunctionalState NewState); FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); #ifdef __cplusplus } #endif #endif /*__STM32F10x_ADC_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ src/bare_test/1.Led/stdlib/inc/stm32f10x_bkp.h
File was renamed from src/bare_test/stm32_key/fwlib/inc/stm32f10x_bkp.h @@ -1,195 +1,195 @@ /** ****************************************************************************** * @file stm32f10x_bkp.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the BKP firmware * library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_BKP_H #define __STM32F10x_BKP_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup BKP * @{ */ /** @defgroup BKP_Exported_Types * @{ */ /** * @} */ /** @defgroup BKP_Exported_Constants * @{ */ /** @defgroup Tamper_Pin_active_level * @{ */ #define BKP_TamperPinLevel_High ((uint16_t)0x0000) #define BKP_TamperPinLevel_Low ((uint16_t)0x0001) #define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \ ((LEVEL) == BKP_TamperPinLevel_Low)) /** * @} */ /** @defgroup RTC_output_source_to_output_on_the_Tamper_pin * @{ */ #define BKP_RTCOutputSource_None ((uint16_t)0x0000) #define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) #define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) #define BKP_RTCOutputSource_Second ((uint16_t)0x0300) #define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \ ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \ ((SOURCE) == BKP_RTCOutputSource_Alarm) || \ ((SOURCE) == BKP_RTCOutputSource_Second)) /** * @} */ /** @defgroup Data_Backup_Register * @{ */ #define BKP_DR1 ((uint16_t)0x0004) #define BKP_DR2 ((uint16_t)0x0008) #define BKP_DR3 ((uint16_t)0x000C) #define BKP_DR4 ((uint16_t)0x0010) #define BKP_DR5 ((uint16_t)0x0014) #define BKP_DR6 ((uint16_t)0x0018) #define BKP_DR7 ((uint16_t)0x001C) #define BKP_DR8 ((uint16_t)0x0020) #define BKP_DR9 ((uint16_t)0x0024) #define BKP_DR10 ((uint16_t)0x0028) #define BKP_DR11 ((uint16_t)0x0040) #define BKP_DR12 ((uint16_t)0x0044) #define BKP_DR13 ((uint16_t)0x0048) #define BKP_DR14 ((uint16_t)0x004C) #define BKP_DR15 ((uint16_t)0x0050) #define BKP_DR16 ((uint16_t)0x0054) #define BKP_DR17 ((uint16_t)0x0058) #define BKP_DR18 ((uint16_t)0x005C) #define BKP_DR19 ((uint16_t)0x0060) #define BKP_DR20 ((uint16_t)0x0064) #define BKP_DR21 ((uint16_t)0x0068) #define BKP_DR22 ((uint16_t)0x006C) #define BKP_DR23 ((uint16_t)0x0070) #define BKP_DR24 ((uint16_t)0x0074) #define BKP_DR25 ((uint16_t)0x0078) #define BKP_DR26 ((uint16_t)0x007C) #define BKP_DR27 ((uint16_t)0x0080) #define BKP_DR28 ((uint16_t)0x0084) #define BKP_DR29 ((uint16_t)0x0088) #define BKP_DR30 ((uint16_t)0x008C) #define BKP_DR31 ((uint16_t)0x0090) #define BKP_DR32 ((uint16_t)0x0094) #define BKP_DR33 ((uint16_t)0x0098) #define BKP_DR34 ((uint16_t)0x009C) #define BKP_DR35 ((uint16_t)0x00A0) #define BKP_DR36 ((uint16_t)0x00A4) #define BKP_DR37 ((uint16_t)0x00A8) #define BKP_DR38 ((uint16_t)0x00AC) #define BKP_DR39 ((uint16_t)0x00B0) #define BKP_DR40 ((uint16_t)0x00B4) #define BKP_DR41 ((uint16_t)0x00B8) #define BKP_DR42 ((uint16_t)0x00BC) #define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \ ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \ ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \ ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \ ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \ ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \ ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \ ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \ ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \ ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \ ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \ ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \ ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \ ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42)) #define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F) /** * @} */ /** * @} */ /** @defgroup BKP_Exported_Macros * @{ */ /** * @} */ /** @defgroup BKP_Exported_Functions * @{ */ void BKP_DeInit(void); void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); void BKP_TamperPinCmd(FunctionalState NewState); void BKP_ITConfig(FunctionalState NewState); void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); FlagStatus BKP_GetFlagStatus(void); void BKP_ClearFlag(void); ITStatus BKP_GetITStatus(void); void BKP_ClearITPendingBit(void); #ifdef __cplusplus } #endif #endif /* __STM32F10x_BKP_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /** ****************************************************************************** * @file stm32f10x_bkp.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the BKP firmware * library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_BKP_H #define __STM32F10x_BKP_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup BKP * @{ */ /** @defgroup BKP_Exported_Types * @{ */ /** * @} */ /** @defgroup BKP_Exported_Constants * @{ */ /** @defgroup Tamper_Pin_active_level * @{ */ #define BKP_TamperPinLevel_High ((uint16_t)0x0000) #define BKP_TamperPinLevel_Low ((uint16_t)0x0001) #define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \ ((LEVEL) == BKP_TamperPinLevel_Low)) /** * @} */ /** @defgroup RTC_output_source_to_output_on_the_Tamper_pin * @{ */ #define BKP_RTCOutputSource_None ((uint16_t)0x0000) #define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) #define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) #define BKP_RTCOutputSource_Second ((uint16_t)0x0300) #define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \ ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \ ((SOURCE) == BKP_RTCOutputSource_Alarm) || \ ((SOURCE) == BKP_RTCOutputSource_Second)) /** * @} */ /** @defgroup Data_Backup_Register * @{ */ #define BKP_DR1 ((uint16_t)0x0004) #define BKP_DR2 ((uint16_t)0x0008) #define BKP_DR3 ((uint16_t)0x000C) #define BKP_DR4 ((uint16_t)0x0010) #define BKP_DR5 ((uint16_t)0x0014) #define BKP_DR6 ((uint16_t)0x0018) #define BKP_DR7 ((uint16_t)0x001C) #define BKP_DR8 ((uint16_t)0x0020) #define BKP_DR9 ((uint16_t)0x0024) #define BKP_DR10 ((uint16_t)0x0028) #define BKP_DR11 ((uint16_t)0x0040) #define BKP_DR12 ((uint16_t)0x0044) #define BKP_DR13 ((uint16_t)0x0048) #define BKP_DR14 ((uint16_t)0x004C) #define BKP_DR15 ((uint16_t)0x0050) #define BKP_DR16 ((uint16_t)0x0054) #define BKP_DR17 ((uint16_t)0x0058) #define BKP_DR18 ((uint16_t)0x005C) #define BKP_DR19 ((uint16_t)0x0060) #define BKP_DR20 ((uint16_t)0x0064) #define BKP_DR21 ((uint16_t)0x0068) #define BKP_DR22 ((uint16_t)0x006C) #define BKP_DR23 ((uint16_t)0x0070) #define BKP_DR24 ((uint16_t)0x0074) #define BKP_DR25 ((uint16_t)0x0078) #define BKP_DR26 ((uint16_t)0x007C) #define BKP_DR27 ((uint16_t)0x0080) #define BKP_DR28 ((uint16_t)0x0084) #define BKP_DR29 ((uint16_t)0x0088) #define BKP_DR30 ((uint16_t)0x008C) #define BKP_DR31 ((uint16_t)0x0090) #define BKP_DR32 ((uint16_t)0x0094) #define BKP_DR33 ((uint16_t)0x0098) #define BKP_DR34 ((uint16_t)0x009C) #define BKP_DR35 ((uint16_t)0x00A0) #define BKP_DR36 ((uint16_t)0x00A4) #define BKP_DR37 ((uint16_t)0x00A8) #define BKP_DR38 ((uint16_t)0x00AC) #define BKP_DR39 ((uint16_t)0x00B0) #define BKP_DR40 ((uint16_t)0x00B4) #define BKP_DR41 ((uint16_t)0x00B8) #define BKP_DR42 ((uint16_t)0x00BC) #define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \ ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \ ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \ ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \ ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \ ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \ ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \ ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \ ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \ ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \ ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \ ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \ ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \ ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42)) #define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F) /** * @} */ /** * @} */ /** @defgroup BKP_Exported_Macros * @{ */ /** * @} */ /** @defgroup BKP_Exported_Functions * @{ */ void BKP_DeInit(void); void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); void BKP_TamperPinCmd(FunctionalState NewState); void BKP_ITConfig(FunctionalState NewState); void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); FlagStatus BKP_GetFlagStatus(void); void BKP_ClearFlag(void); ITStatus BKP_GetITStatus(void); void BKP_ClearITPendingBit(void); #ifdef __cplusplus } #endif #endif /* __STM32F10x_BKP_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ src/bare_test/1.Led/stdlib/inc/stm32f10x_can.h
File was renamed from src/bare_test/stm32_key/fwlib/inc/stm32f10x_can.h @@ -1,697 +1,697 @@ /** ****************************************************************************** * @file stm32f10x_can.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the CAN firmware * library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_CAN_H #define __STM32F10x_CAN_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup CAN * @{ */ /** @defgroup CAN_Exported_Types * @{ */ #define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \ ((PERIPH) == CAN2)) /** * @brief CAN init structure definition */ typedef struct { uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. It ranges from 1 to 1024. */ uint8_t CAN_Mode; /*!< Specifies the CAN operating mode. This parameter can be a value of @ref CAN_operating_mode */ uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta the CAN hardware is allowed to lengthen or shorten a bit to perform resynchronization. This parameter can be a value of @ref CAN_synchronisation_jump_width */ uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit Segment 1. This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2. This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode. This parameter can be set either to ENABLE or DISABLE. */ FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management. This parameter can be set either to ENABLE or DISABLE. */ FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. This parameter can be set either to ENABLE or DISABLE. */ FunctionalState CAN_NART; /*!< Enable or disable the no-automatic retransmission mode. This parameter can be set either to ENABLE or DISABLE. */ FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode. This parameter can be set either to ENABLE or DISABLE. */ FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority. This parameter can be set either to ENABLE or DISABLE. */ } CAN_InitTypeDef; /** * @brief CAN filter init structure definition */ typedef struct { uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit configuration, first one for a 16-bit configuration). This parameter can be a value between 0x0000 and 0xFFFF */ uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit configuration, second one for a 16-bit configuration). This parameter can be a value between 0x0000 and 0xFFFF */ uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, according to the mode (MSBs for a 32-bit configuration, first one for a 16-bit configuration). This parameter can be a value between 0x0000 and 0xFFFF */ uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, according to the mode (LSBs for a 32-bit configuration, second one for a 16-bit configuration). This parameter can be a value between 0x0000 and 0xFFFF */ uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. This parameter can be a value of @ref CAN_filter_FIFO */ uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized. This parameter can be a value of @ref CAN_filter_mode */ uint8_t CAN_FilterScale; /*!< Specifies the filter scale. This parameter can be a value of @ref CAN_filter_scale */ FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter. This parameter can be set either to ENABLE or DISABLE. */ } CAN_FilterInitTypeDef; /** * @brief CAN Tx message structure definition */ typedef struct { uint32_t StdId; /*!< Specifies the standard identifier. This parameter can be a value between 0 to 0x7FF. */ uint32_t ExtId; /*!< Specifies the extended identifier. This parameter can be a value between 0 to 0x1FFFFFFF. */ uint8_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. This parameter can be a value of @ref CAN_identifier_type */ uint8_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. This parameter can be a value of @ref CAN_remote_transmission_request */ uint8_t DLC; /*!< Specifies the length of the frame that will be transmitted. This parameter can be a value between 0 to 8 */ uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 to 0xFF. */ } CanTxMsg; /** * @brief CAN Rx message structure definition */ typedef struct { uint32_t StdId; /*!< Specifies the standard identifier. This parameter can be a value between 0 to 0x7FF. */ uint32_t ExtId; /*!< Specifies the extended identifier. This parameter can be a value between 0 to 0x1FFFFFFF. */ uint8_t IDE; /*!< Specifies the type of identifier for the message that will be received. This parameter can be a value of @ref CAN_identifier_type */ uint8_t RTR; /*!< Specifies the type of frame for the received message. This parameter can be a value of @ref CAN_remote_transmission_request */ uint8_t DLC; /*!< Specifies the length of the frame that will be received. This parameter can be a value between 0 to 8 */ uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to 0xFF. */ uint8_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. This parameter can be a value between 0 to 0xFF */ } CanRxMsg; /** * @} */ /** @defgroup CAN_Exported_Constants * @{ */ /** @defgroup CAN_sleep_constants * @{ */ #define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */ #define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */ /** * @} */ /** @defgroup CAN_Mode * @{ */ #define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */ #define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */ #define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */ #define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */ #define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \ ((MODE) == CAN_Mode_LoopBack)|| \ ((MODE) == CAN_Mode_Silent) || \ ((MODE) == CAN_Mode_Silent_LoopBack)) /** * @} */ /** * @defgroup CAN_Operating_Mode * @{ */ #define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */ #define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */ #define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */ #define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\ ((MODE) == CAN_OperatingMode_Normal)|| \ ((MODE) == CAN_OperatingMode_Sleep)) /** * @} */ /** * @defgroup CAN_Mode_Status * @{ */ #define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */ #define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */ /** * @} */ /** @defgroup CAN_synchronisation_jump_width * @{ */ #define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ #define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ #define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ #define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ #define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \ ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq)) /** * @} */ /** @defgroup CAN_time_quantum_in_bit_segment_1 * @{ */ #define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ #define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ #define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ #define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ #define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ #define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ #define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ #define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ #define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ #define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ #define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ #define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ #define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ #define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ #define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ #define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ #define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq) /** * @} */ /** @defgroup CAN_time_quantum_in_bit_segment_2 * @{ */ #define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ #define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ #define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ #define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ #define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ #define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ #define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ #define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ #define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq) /** * @} */ /** @defgroup CAN_clock_prescaler * @{ */ #define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) /** * @} */ /** @defgroup CAN_filter_number * @{ */ #ifndef STM32F10X_CL #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13) #else #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) #endif /* STM32F10X_CL */ /** * @} */ /** @defgroup CAN_filter_mode * @{ */ #define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */ #define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */ #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \ ((MODE) == CAN_FilterMode_IdList)) /** * @} */ /** @defgroup CAN_filter_scale * @{ */ #define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */ #define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */ #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \ ((SCALE) == CAN_FilterScale_32bit)) /** * @} */ /** @defgroup CAN_filter_FIFO * @{ */ #define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ #define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \ ((FIFO) == CAN_FilterFIFO1)) /** * @} */ /** @defgroup Start_bank_filter_for_slave_CAN * @{ */ #define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27)) /** * @} */ /** @defgroup CAN_Tx * @{ */ #define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) #define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) #define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) #define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) /** * @} */ /** @defgroup CAN_identifier_type * @{ */ #define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */ #define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */ #define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \ ((IDTYPE) == CAN_Id_Extended)) /** * @} */ /** @defgroup CAN_remote_transmission_request * @{ */ #define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */ #define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */ #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote)) /** * @} */ /** @defgroup CAN_transmit_constants * @{ */ #define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */ #define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */ #define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */ #define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */ /** * @} */ /** @defgroup CAN_receive_FIFO_number_constants * @{ */ #define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ #define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ #define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) /** * @} */ /** @defgroup CAN_sleep_constants * @{ */ #define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ #define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */ /** * @} */ /** @defgroup CAN_wake_up_constants * @{ */ #define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ #define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ /** * @} */ /** * @defgroup CAN_Error_Code_constants * @{ */ #define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */ #define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */ #define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */ #define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */ #define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ #define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */ #define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */ #define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */ /** * @} */ /** @defgroup CAN_flags * @{ */ /* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() and CAN_ClearFlag() functions. */ /* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. */ /* Transmit Flags */ #define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */ #define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */ #define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */ /* Receive Flags */ #define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */ #define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */ #define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */ #define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */ #define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */ #define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */ /* Operating Mode Flags */ #define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */ #define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */ /* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible. In this case the SLAK bit can be polled.*/ /* Error Flags */ #define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */ #define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */ #define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */ #define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */ #define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \ ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \ ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \ ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \ ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \ ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \ ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \ ((FLAG) == CAN_FLAG_SLAK )) #define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \ ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \ ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\ ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \ ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK)) /** * @} */ /** @defgroup CAN_interrupts * @{ */ #define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/ /* Receive Interrupts */ #define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/ #define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/ #define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/ #define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/ #define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/ #define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/ /* Operating Mode Interrupts */ #define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/ #define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/ /* Error Interrupts */ #define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/ #define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/ #define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/ #define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/ #define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/ /* Flags named as Interrupts : kept only for FW compatibility */ #define CAN_IT_RQCP0 CAN_IT_TME #define CAN_IT_RQCP1 CAN_IT_TME #define CAN_IT_RQCP2 CAN_IT_TME #define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) #define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\ ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\ ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) /** * @} */ /** @defgroup CAN_Legacy * @{ */ #define CANINITFAILED CAN_InitStatus_Failed #define CANINITOK CAN_InitStatus_Success #define CAN_FilterFIFO0 CAN_Filter_FIFO0 #define CAN_FilterFIFO1 CAN_Filter_FIFO1 #define CAN_ID_STD CAN_Id_Standard #define CAN_ID_EXT CAN_Id_Extended #define CAN_RTR_DATA CAN_RTR_Data #define CAN_RTR_REMOTE CAN_RTR_Remote #define CANTXFAILE CAN_TxStatus_Failed #define CANTXOK CAN_TxStatus_Ok #define CANTXPENDING CAN_TxStatus_Pending #define CAN_NO_MB CAN_TxStatus_NoMailBox #define CANSLEEPFAILED CAN_Sleep_Failed #define CANSLEEPOK CAN_Sleep_Ok #define CANWAKEUPFAILED CAN_WakeUp_Failed #define CANWAKEUPOK CAN_WakeUp_Ok /** * @} */ /** * @} */ /** @defgroup CAN_Exported_Macros * @{ */ /** * @} */ /** @defgroup CAN_Exported_Functions * @{ */ /* Function used to set the CAN configuration to the default reset state *****/ void CAN_DeInit(CAN_TypeDef* CANx); /* Initialization and Configuration functions *********************************/ uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); void CAN_SlaveStartBank(uint8_t CAN_BankNumber); void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState); /* Transmit functions *********************************************************/ uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); /* Receive functions **********************************************************/ void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); /* Operation modes functions **************************************************/ uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode); uint8_t CAN_Sleep(CAN_TypeDef* CANx); uint8_t CAN_WakeUp(CAN_TypeDef* CANx); /* Error management functions *************************************************/ uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx); uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx); uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx); /* Interrupts and flags management functions **********************************/ void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); #ifdef __cplusplus } #endif #endif /* __STM32F10x_CAN_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /** ****************************************************************************** * @file stm32f10x_can.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the CAN firmware * library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_CAN_H #define __STM32F10x_CAN_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup CAN * @{ */ /** @defgroup CAN_Exported_Types * @{ */ #define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \ ((PERIPH) == CAN2)) /** * @brief CAN init structure definition */ typedef struct { uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. It ranges from 1 to 1024. */ uint8_t CAN_Mode; /*!< Specifies the CAN operating mode. This parameter can be a value of @ref CAN_operating_mode */ uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta the CAN hardware is allowed to lengthen or shorten a bit to perform resynchronization. This parameter can be a value of @ref CAN_synchronisation_jump_width */ uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit Segment 1. This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2. This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode. This parameter can be set either to ENABLE or DISABLE. */ FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management. This parameter can be set either to ENABLE or DISABLE. */ FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. This parameter can be set either to ENABLE or DISABLE. */ FunctionalState CAN_NART; /*!< Enable or disable the no-automatic retransmission mode. This parameter can be set either to ENABLE or DISABLE. */ FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode. This parameter can be set either to ENABLE or DISABLE. */ FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority. This parameter can be set either to ENABLE or DISABLE. */ } CAN_InitTypeDef; /** * @brief CAN filter init structure definition */ typedef struct { uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit configuration, first one for a 16-bit configuration). This parameter can be a value between 0x0000 and 0xFFFF */ uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit configuration, second one for a 16-bit configuration). This parameter can be a value between 0x0000 and 0xFFFF */ uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, according to the mode (MSBs for a 32-bit configuration, first one for a 16-bit configuration). This parameter can be a value between 0x0000 and 0xFFFF */ uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, according to the mode (LSBs for a 32-bit configuration, second one for a 16-bit configuration). This parameter can be a value between 0x0000 and 0xFFFF */ uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. This parameter can be a value of @ref CAN_filter_FIFO */ uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized. This parameter can be a value of @ref CAN_filter_mode */ uint8_t CAN_FilterScale; /*!< Specifies the filter scale. This parameter can be a value of @ref CAN_filter_scale */ FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter. This parameter can be set either to ENABLE or DISABLE. */ } CAN_FilterInitTypeDef; /** * @brief CAN Tx message structure definition */ typedef struct { uint32_t StdId; /*!< Specifies the standard identifier. This parameter can be a value between 0 to 0x7FF. */ uint32_t ExtId; /*!< Specifies the extended identifier. This parameter can be a value between 0 to 0x1FFFFFFF. */ uint8_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. This parameter can be a value of @ref CAN_identifier_type */ uint8_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. This parameter can be a value of @ref CAN_remote_transmission_request */ uint8_t DLC; /*!< Specifies the length of the frame that will be transmitted. This parameter can be a value between 0 to 8 */ uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 to 0xFF. */ } CanTxMsg; /** * @brief CAN Rx message structure definition */ typedef struct { uint32_t StdId; /*!< Specifies the standard identifier. This parameter can be a value between 0 to 0x7FF. */ uint32_t ExtId; /*!< Specifies the extended identifier. This parameter can be a value between 0 to 0x1FFFFFFF. */ uint8_t IDE; /*!< Specifies the type of identifier for the message that will be received. This parameter can be a value of @ref CAN_identifier_type */ uint8_t RTR; /*!< Specifies the type of frame for the received message. This parameter can be a value of @ref CAN_remote_transmission_request */ uint8_t DLC; /*!< Specifies the length of the frame that will be received. This parameter can be a value between 0 to 8 */ uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to 0xFF. */ uint8_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. This parameter can be a value between 0 to 0xFF */ } CanRxMsg; /** * @} */ /** @defgroup CAN_Exported_Constants * @{ */ /** @defgroup CAN_sleep_constants * @{ */ #define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */ #define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */ /** * @} */ /** @defgroup CAN_Mode * @{ */ #define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */ #define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */ #define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */ #define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */ #define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \ ((MODE) == CAN_Mode_LoopBack)|| \ ((MODE) == CAN_Mode_Silent) || \ ((MODE) == CAN_Mode_Silent_LoopBack)) /** * @} */ /** * @defgroup CAN_Operating_Mode * @{ */ #define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */ #define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */ #define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */ #define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\ ((MODE) == CAN_OperatingMode_Normal)|| \ ((MODE) == CAN_OperatingMode_Sleep)) /** * @} */ /** * @defgroup CAN_Mode_Status * @{ */ #define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */ #define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */ /** * @} */ /** @defgroup CAN_synchronisation_jump_width * @{ */ #define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ #define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ #define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ #define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ #define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \ ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq)) /** * @} */ /** @defgroup CAN_time_quantum_in_bit_segment_1 * @{ */ #define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ #define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ #define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ #define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ #define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ #define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ #define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ #define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ #define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ #define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ #define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ #define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ #define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ #define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ #define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ #define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ #define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq) /** * @} */ /** @defgroup CAN_time_quantum_in_bit_segment_2 * @{ */ #define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ #define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ #define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ #define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ #define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ #define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ #define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ #define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ #define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq) /** * @} */ /** @defgroup CAN_clock_prescaler * @{ */ #define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) /** * @} */ /** @defgroup CAN_filter_number * @{ */ #ifndef STM32F10X_CL #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13) #else #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) #endif /* STM32F10X_CL */ /** * @} */ /** @defgroup CAN_filter_mode * @{ */ #define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */ #define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */ #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \ ((MODE) == CAN_FilterMode_IdList)) /** * @} */ /** @defgroup CAN_filter_scale * @{ */ #define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */ #define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */ #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \ ((SCALE) == CAN_FilterScale_32bit)) /** * @} */ /** @defgroup CAN_filter_FIFO * @{ */ #define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ #define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \ ((FIFO) == CAN_FilterFIFO1)) /** * @} */ /** @defgroup Start_bank_filter_for_slave_CAN * @{ */ #define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27)) /** * @} */ /** @defgroup CAN_Tx * @{ */ #define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) #define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) #define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) #define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) /** * @} */ /** @defgroup CAN_identifier_type * @{ */ #define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */ #define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */ #define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \ ((IDTYPE) == CAN_Id_Extended)) /** * @} */ /** @defgroup CAN_remote_transmission_request * @{ */ #define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */ #define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */ #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote)) /** * @} */ /** @defgroup CAN_transmit_constants * @{ */ #define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */ #define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */ #define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */ #define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */ /** * @} */ /** @defgroup CAN_receive_FIFO_number_constants * @{ */ #define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ #define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ #define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) /** * @} */ /** @defgroup CAN_sleep_constants * @{ */ #define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ #define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */ /** * @} */ /** @defgroup CAN_wake_up_constants * @{ */ #define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ #define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ /** * @} */ /** * @defgroup CAN_Error_Code_constants * @{ */ #define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */ #define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */ #define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */ #define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */ #define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ #define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */ #define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */ #define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */ /** * @} */ /** @defgroup CAN_flags * @{ */ /* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() and CAN_ClearFlag() functions. */ /* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. */ /* Transmit Flags */ #define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */ #define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */ #define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */ /* Receive Flags */ #define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */ #define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */ #define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */ #define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */ #define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */ #define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */ /* Operating Mode Flags */ #define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */ #define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */ /* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible. In this case the SLAK bit can be polled.*/ /* Error Flags */ #define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */ #define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */ #define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */ #define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */ #define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \ ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \ ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \ ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \ ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \ ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \ ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \ ((FLAG) == CAN_FLAG_SLAK )) #define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \ ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \ ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\ ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \ ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK)) /** * @} */ /** @defgroup CAN_interrupts * @{ */ #define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/ /* Receive Interrupts */ #define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/ #define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/ #define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/ #define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/ #define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/ #define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/ /* Operating Mode Interrupts */ #define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/ #define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/ /* Error Interrupts */ #define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/ #define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/ #define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/ #define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/ #define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/ /* Flags named as Interrupts : kept only for FW compatibility */ #define CAN_IT_RQCP0 CAN_IT_TME #define CAN_IT_RQCP1 CAN_IT_TME #define CAN_IT_RQCP2 CAN_IT_TME #define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) #define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\ ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\ ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) /** * @} */ /** @defgroup CAN_Legacy * @{ */ #define CANINITFAILED CAN_InitStatus_Failed #define CANINITOK CAN_InitStatus_Success #define CAN_FilterFIFO0 CAN_Filter_FIFO0 #define CAN_FilterFIFO1 CAN_Filter_FIFO1 #define CAN_ID_STD CAN_Id_Standard #define CAN_ID_EXT CAN_Id_Extended #define CAN_RTR_DATA CAN_RTR_Data #define CAN_RTR_REMOTE CAN_RTR_Remote #define CANTXFAILE CAN_TxStatus_Failed #define CANTXOK CAN_TxStatus_Ok #define CANTXPENDING CAN_TxStatus_Pending #define CAN_NO_MB CAN_TxStatus_NoMailBox #define CANSLEEPFAILED CAN_Sleep_Failed #define CANSLEEPOK CAN_Sleep_Ok #define CANWAKEUPFAILED CAN_WakeUp_Failed #define CANWAKEUPOK CAN_WakeUp_Ok /** * @} */ /** * @} */ /** @defgroup CAN_Exported_Macros * @{ */ /** * @} */ /** @defgroup CAN_Exported_Functions * @{ */ /* Function used to set the CAN configuration to the default reset state *****/ void CAN_DeInit(CAN_TypeDef* CANx); /* Initialization and Configuration functions *********************************/ uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); void CAN_SlaveStartBank(uint8_t CAN_BankNumber); void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState); /* Transmit functions *********************************************************/ uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); /* Receive functions **********************************************************/ void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); /* Operation modes functions **************************************************/ uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode); uint8_t CAN_Sleep(CAN_TypeDef* CANx); uint8_t CAN_WakeUp(CAN_TypeDef* CANx); /* Error management functions *************************************************/ uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx); uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx); uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx); /* Interrupts and flags management functions **********************************/ void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); #ifdef __cplusplus } #endif #endif /* __STM32F10x_CAN_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ src/bare_test/1.Led/stdlib/inc/stm32f10x_cec.h
File was renamed from src/bare_test/stm32_key/fwlib/inc/stm32f10x_cec.h @@ -1,210 +1,210 @@ /** ****************************************************************************** * @file stm32f10x_cec.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the CEC firmware * library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_CEC_H #define __STM32F10x_CEC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup CEC * @{ */ /** @defgroup CEC_Exported_Types * @{ */ /** * @brief CEC Init structure definition */ typedef struct { uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode. This parameter can be a value of @ref CEC_BitTiming_Mode */ uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode. This parameter can be a value of @ref CEC_BitPeriod_Mode */ }CEC_InitTypeDef; /** * @} */ /** @defgroup CEC_Exported_Constants * @{ */ /** @defgroup CEC_BitTiming_Mode * @{ */ #define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */ #define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */ #define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \ ((MODE) == CEC_BitTimingErrFreeMode)) /** * @} */ /** @defgroup CEC_BitPeriod_Mode * @{ */ #define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */ #define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */ #define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \ ((MODE) == CEC_BitPeriodFlexibleMode)) /** * @} */ /** @defgroup CEC_interrupts_definition * @{ */ #define CEC_IT_TERR CEC_CSR_TERR #define CEC_IT_TBTRF CEC_CSR_TBTRF #define CEC_IT_RERR CEC_CSR_RERR #define CEC_IT_RBTF CEC_CSR_RBTF #define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \ ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF)) /** * @} */ /** @defgroup CEC_Own_Address * @{ */ #define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10) /** * @} */ /** @defgroup CEC_Prescaler * @{ */ #define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF) /** * @} */ /** @defgroup CEC_flags_definition * @{ */ /** * @brief ESR register flags */ #define CEC_FLAG_BTE ((uint32_t)0x10010000) #define CEC_FLAG_BPE ((uint32_t)0x10020000) #define CEC_FLAG_RBTFE ((uint32_t)0x10040000) #define CEC_FLAG_SBE ((uint32_t)0x10080000) #define CEC_FLAG_ACKE ((uint32_t)0x10100000) #define CEC_FLAG_LINE ((uint32_t)0x10200000) #define CEC_FLAG_TBTFE ((uint32_t)0x10400000) /** * @brief CSR register flags */ #define CEC_FLAG_TEOM ((uint32_t)0x00000002) #define CEC_FLAG_TERR ((uint32_t)0x00000004) #define CEC_FLAG_TBTRF ((uint32_t)0x00000008) #define CEC_FLAG_RSOM ((uint32_t)0x00000010) #define CEC_FLAG_REOM ((uint32_t)0x00000020) #define CEC_FLAG_RERR ((uint32_t)0x00000040) #define CEC_FLAG_RBTF ((uint32_t)0x00000080) #define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00)) #define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \ ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \ ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \ ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \ ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \ ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \ ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF)) /** * @} */ /** * @} */ /** @defgroup CEC_Exported_Macros * @{ */ /** * @} */ /** @defgroup CEC_Exported_Functions * @{ */ void CEC_DeInit(void); void CEC_Init(CEC_InitTypeDef* CEC_InitStruct); void CEC_Cmd(FunctionalState NewState); void CEC_ITConfig(FunctionalState NewState); void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress); void CEC_SetPrescaler(uint16_t CEC_Prescaler); void CEC_SendDataByte(uint8_t Data); uint8_t CEC_ReceiveDataByte(void); void CEC_StartOfMessage(void); void CEC_EndOfMessageCmd(FunctionalState NewState); FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG); void CEC_ClearFlag(uint32_t CEC_FLAG); ITStatus CEC_GetITStatus(uint8_t CEC_IT); void CEC_ClearITPendingBit(uint16_t CEC_IT); #ifdef __cplusplus } #endif #endif /* __STM32F10x_CEC_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /** ****************************************************************************** * @file stm32f10x_cec.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the CEC firmware * library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_CEC_H #define __STM32F10x_CEC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup CEC * @{ */ /** @defgroup CEC_Exported_Types * @{ */ /** * @brief CEC Init structure definition */ typedef struct { uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode. This parameter can be a value of @ref CEC_BitTiming_Mode */ uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode. This parameter can be a value of @ref CEC_BitPeriod_Mode */ }CEC_InitTypeDef; /** * @} */ /** @defgroup CEC_Exported_Constants * @{ */ /** @defgroup CEC_BitTiming_Mode * @{ */ #define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */ #define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */ #define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \ ((MODE) == CEC_BitTimingErrFreeMode)) /** * @} */ /** @defgroup CEC_BitPeriod_Mode * @{ */ #define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */ #define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */ #define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \ ((MODE) == CEC_BitPeriodFlexibleMode)) /** * @} */ /** @defgroup CEC_interrupts_definition * @{ */ #define CEC_IT_TERR CEC_CSR_TERR #define CEC_IT_TBTRF CEC_CSR_TBTRF #define CEC_IT_RERR CEC_CSR_RERR #define CEC_IT_RBTF CEC_CSR_RBTF #define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \ ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF)) /** * @} */ /** @defgroup CEC_Own_Address * @{ */ #define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10) /** * @} */ /** @defgroup CEC_Prescaler * @{ */ #define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF) /** * @} */ /** @defgroup CEC_flags_definition * @{ */ /** * @brief ESR register flags */ #define CEC_FLAG_BTE ((uint32_t)0x10010000) #define CEC_FLAG_BPE ((uint32_t)0x10020000) #define CEC_FLAG_RBTFE ((uint32_t)0x10040000) #define CEC_FLAG_SBE ((uint32_t)0x10080000) #define CEC_FLAG_ACKE ((uint32_t)0x10100000) #define CEC_FLAG_LINE ((uint32_t)0x10200000) #define CEC_FLAG_TBTFE ((uint32_t)0x10400000) /** * @brief CSR register flags */ #define CEC_FLAG_TEOM ((uint32_t)0x00000002) #define CEC_FLAG_TERR ((uint32_t)0x00000004) #define CEC_FLAG_TBTRF ((uint32_t)0x00000008) #define CEC_FLAG_RSOM ((uint32_t)0x00000010) #define CEC_FLAG_REOM ((uint32_t)0x00000020) #define CEC_FLAG_RERR ((uint32_t)0x00000040) #define CEC_FLAG_RBTF ((uint32_t)0x00000080) #define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00)) #define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \ ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \ ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \ ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \ ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \ ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \ ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF)) /** * @} */ /** * @} */ /** @defgroup CEC_Exported_Macros * @{ */ /** * @} */ /** @defgroup CEC_Exported_Functions * @{ */ void CEC_DeInit(void); void CEC_Init(CEC_InitTypeDef* CEC_InitStruct); void CEC_Cmd(FunctionalState NewState); void CEC_ITConfig(FunctionalState NewState); void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress); void CEC_SetPrescaler(uint16_t CEC_Prescaler); void CEC_SendDataByte(uint8_t Data); uint8_t CEC_ReceiveDataByte(void); void CEC_StartOfMessage(void); void CEC_EndOfMessageCmd(FunctionalState NewState); FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG); void CEC_ClearFlag(uint32_t CEC_FLAG); ITStatus CEC_GetITStatus(uint8_t CEC_IT); void CEC_ClearITPendingBit(uint16_t CEC_IT); #ifdef __cplusplus } #endif #endif /* __STM32F10x_CEC_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ src/bare_test/1.Led/stdlib/inc/stm32f10x_crc.h
File was renamed from src/bare_test/stm32_key/fwlib/inc/stm32f10x_crc.h @@ -1,94 +1,94 @@ /** ****************************************************************************** * @file stm32f10x_crc.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the CRC firmware * library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_CRC_H #define __STM32F10x_CRC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup CRC * @{ */ /** @defgroup CRC_Exported_Types * @{ */ /** * @} */ /** @defgroup CRC_Exported_Constants * @{ */ /** * @} */ /** @defgroup CRC_Exported_Macros * @{ */ /** * @} */ /** @defgroup CRC_Exported_Functions * @{ */ void CRC_ResetDR(void); uint32_t CRC_CalcCRC(uint32_t Data); uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); uint32_t CRC_GetCRC(void); void CRC_SetIDRegister(uint8_t IDValue); uint8_t CRC_GetIDRegister(void); #ifdef __cplusplus } #endif #endif /* __STM32F10x_CRC_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /** ****************************************************************************** * @file stm32f10x_crc.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the CRC firmware * library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_CRC_H #define __STM32F10x_CRC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup CRC * @{ */ /** @defgroup CRC_Exported_Types * @{ */ /** * @} */ /** @defgroup CRC_Exported_Constants * @{ */ /** * @} */ /** @defgroup CRC_Exported_Macros * @{ */ /** * @} */ /** @defgroup CRC_Exported_Functions * @{ */ void CRC_ResetDR(void); uint32_t CRC_CalcCRC(uint32_t Data); uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); uint32_t CRC_GetCRC(void); void CRC_SetIDRegister(uint8_t IDValue); uint8_t CRC_GetIDRegister(void); #ifdef __cplusplus } #endif #endif /* __STM32F10x_CRC_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ src/bare_test/1.Led/stdlib/inc/stm32f10x_dac.h
File was renamed from src/bare_test/stm32_key/fwlib/inc/stm32f10x_dac.h @@ -1,317 +1,317 @@ /** ****************************************************************************** * @file stm32f10x_dac.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the DAC firmware * library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_DAC_H #define __STM32F10x_DAC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup DAC * @{ */ /** @defgroup DAC_Exported_Types * @{ */ /** * @brief DAC Init structure definition */ typedef struct { uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. This parameter can be a value of @ref DAC_trigger_selection */ uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves are generated, or whether no wave is generated. This parameter can be a value of @ref DAC_wave_generation */ uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or the maximum amplitude triangle generation for the DAC channel. This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. This parameter can be a value of @ref DAC_output_buffer */ }DAC_InitTypeDef; /** * @} */ /** @defgroup DAC_Exported_Constants * @{ */ /** @defgroup DAC_trigger_selection * @{ */ #define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */ #define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ #define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel only in High-density devices*/ #define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel only in Connectivity line, Medium-density and Low-density Value Line devices */ #define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ #define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ #define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel only in Medium-density and Low-density Value Line devices*/ #define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ #define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ #define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ #define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ ((TRIGGER) == DAC_Trigger_Software)) /** * @} */ /** @defgroup DAC_wave_generation * @{ */ #define DAC_WaveGeneration_None ((uint32_t)0x00000000) #define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) #define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) #define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ ((WAVE) == DAC_WaveGeneration_Noise) || \ ((WAVE) == DAC_WaveGeneration_Triangle)) /** * @} */ /** @defgroup DAC_lfsrunmask_triangleamplitude * @{ */ #define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ #define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ #define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ #define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ #define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ #define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ #define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ #define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ #define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ #define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ #define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ #define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ #define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ #define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ #define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ ((VALUE) == DAC_TriangleAmplitude_1) || \ ((VALUE) == DAC_TriangleAmplitude_3) || \ ((VALUE) == DAC_TriangleAmplitude_7) || \ ((VALUE) == DAC_TriangleAmplitude_15) || \ ((VALUE) == DAC_TriangleAmplitude_31) || \ ((VALUE) == DAC_TriangleAmplitude_63) || \ ((VALUE) == DAC_TriangleAmplitude_127) || \ ((VALUE) == DAC_TriangleAmplitude_255) || \ ((VALUE) == DAC_TriangleAmplitude_511) || \ ((VALUE) == DAC_TriangleAmplitude_1023) || \ ((VALUE) == DAC_TriangleAmplitude_2047) || \ ((VALUE) == DAC_TriangleAmplitude_4095)) /** * @} */ /** @defgroup DAC_output_buffer * @{ */ #define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) #define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ ((STATE) == DAC_OutputBuffer_Disable)) /** * @} */ /** @defgroup DAC_Channel_selection * @{ */ #define DAC_Channel_1 ((uint32_t)0x00000000) #define DAC_Channel_2 ((uint32_t)0x00000010) #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ ((CHANNEL) == DAC_Channel_2)) /** * @} */ /** @defgroup DAC_data_alignment * @{ */ #define DAC_Align_12b_R ((uint32_t)0x00000000) #define DAC_Align_12b_L ((uint32_t)0x00000004) #define DAC_Align_8b_R ((uint32_t)0x00000008) #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ ((ALIGN) == DAC_Align_12b_L) || \ ((ALIGN) == DAC_Align_8b_R)) /** * @} */ /** @defgroup DAC_wave_generation * @{ */ #define DAC_Wave_Noise ((uint32_t)0x00000040) #define DAC_Wave_Triangle ((uint32_t)0x00000080) #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ ((WAVE) == DAC_Wave_Triangle)) /** * @} */ /** @defgroup DAC_data * @{ */ #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) /** * @} */ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) /** @defgroup DAC_interrupts_definition * @{ */ #define DAC_IT_DMAUDR ((uint32_t)0x00002000) #define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) /** * @} */ /** @defgroup DAC_flags_definition * @{ */ #define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) #define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) /** * @} */ #endif /** * @} */ /** @defgroup DAC_Exported_Macros * @{ */ /** * @} */ /** @defgroup DAC_Exported_Functions * @{ */ void DAC_DeInit(void); void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); #endif void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); #endif #ifdef __cplusplus } #endif #endif /*__STM32F10x_DAC_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /** ****************************************************************************** * @file stm32f10x_dac.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the DAC firmware * library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_DAC_H #define __STM32F10x_DAC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup DAC * @{ */ /** @defgroup DAC_Exported_Types * @{ */ /** * @brief DAC Init structure definition */ typedef struct { uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. This parameter can be a value of @ref DAC_trigger_selection */ uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves are generated, or whether no wave is generated. This parameter can be a value of @ref DAC_wave_generation */ uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or the maximum amplitude triangle generation for the DAC channel. This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. This parameter can be a value of @ref DAC_output_buffer */ }DAC_InitTypeDef; /** * @} */ /** @defgroup DAC_Exported_Constants * @{ */ /** @defgroup DAC_trigger_selection * @{ */ #define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */ #define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ #define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel only in High-density devices*/ #define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel only in Connectivity line, Medium-density and Low-density Value Line devices */ #define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ #define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ #define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel only in Medium-density and Low-density Value Line devices*/ #define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ #define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ #define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ #define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ ((TRIGGER) == DAC_Trigger_Software)) /** * @} */ /** @defgroup DAC_wave_generation * @{ */ #define DAC_WaveGeneration_None ((uint32_t)0x00000000) #define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) #define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) #define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ ((WAVE) == DAC_WaveGeneration_Noise) || \ ((WAVE) == DAC_WaveGeneration_Triangle)) /** * @} */ /** @defgroup DAC_lfsrunmask_triangleamplitude * @{ */ #define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ #define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ #define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ #define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ #define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ #define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ #define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ #define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ #define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ #define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ #define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ #define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ #define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ #define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ #define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ ((VALUE) == DAC_TriangleAmplitude_1) || \ ((VALUE) == DAC_TriangleAmplitude_3) || \ ((VALUE) == DAC_TriangleAmplitude_7) || \ ((VALUE) == DAC_TriangleAmplitude_15) || \ ((VALUE) == DAC_TriangleAmplitude_31) || \ ((VALUE) == DAC_TriangleAmplitude_63) || \ ((VALUE) == DAC_TriangleAmplitude_127) || \ ((VALUE) == DAC_TriangleAmplitude_255) || \ ((VALUE) == DAC_TriangleAmplitude_511) || \ ((VALUE) == DAC_TriangleAmplitude_1023) || \ ((VALUE) == DAC_TriangleAmplitude_2047) || \ ((VALUE) == DAC_TriangleAmplitude_4095)) /** * @} */ /** @defgroup DAC_output_buffer * @{ */ #define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) #define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ ((STATE) == DAC_OutputBuffer_Disable)) /** * @} */ /** @defgroup DAC_Channel_selection * @{ */ #define DAC_Channel_1 ((uint32_t)0x00000000) #define DAC_Channel_2 ((uint32_t)0x00000010) #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ ((CHANNEL) == DAC_Channel_2)) /** * @} */ /** @defgroup DAC_data_alignment * @{ */ #define DAC_Align_12b_R ((uint32_t)0x00000000) #define DAC_Align_12b_L ((uint32_t)0x00000004) #define DAC_Align_8b_R ((uint32_t)0x00000008) #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ ((ALIGN) == DAC_Align_12b_L) || \ ((ALIGN) == DAC_Align_8b_R)) /** * @} */ /** @defgroup DAC_wave_generation * @{ */ #define DAC_Wave_Noise ((uint32_t)0x00000040) #define DAC_Wave_Triangle ((uint32_t)0x00000080) #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ ((WAVE) == DAC_Wave_Triangle)) /** * @} */ /** @defgroup DAC_data * @{ */ #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) /** * @} */ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) /** @defgroup DAC_interrupts_definition * @{ */ #define DAC_IT_DMAUDR ((uint32_t)0x00002000) #define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) /** * @} */ /** @defgroup DAC_flags_definition * @{ */ #define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) #define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) /** * @} */ #endif /** * @} */ /** @defgroup DAC_Exported_Macros * @{ */ /** * @} */ /** @defgroup DAC_Exported_Functions * @{ */ void DAC_DeInit(void); void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); #endif void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); #endif #ifdef __cplusplus } #endif #endif /*__STM32F10x_DAC_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ src/bare_test/1.Led/stdlib/inc/stm32f10x_dbgmcu.h
File was renamed from src/bare_test/stm32_key/fwlib/inc/stm32f10x_dbgmcu.h @@ -1,119 +1,119 @@ /** ****************************************************************************** * @file stm32f10x_dbgmcu.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the DBGMCU * firmware library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_DBGMCU_H #define __STM32F10x_DBGMCU_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup DBGMCU * @{ */ /** @defgroup DBGMCU_Exported_Types * @{ */ /** * @} */ /** @defgroup DBGMCU_Exported_Constants * @{ */ #define DBGMCU_SLEEP ((uint32_t)0x00000001) #define DBGMCU_STOP ((uint32_t)0x00000002) #define DBGMCU_STANDBY ((uint32_t)0x00000004) #define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) #define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) #define DBGMCU_TIM1_STOP ((uint32_t)0x00000400) #define DBGMCU_TIM2_STOP ((uint32_t)0x00000800) #define DBGMCU_TIM3_STOP ((uint32_t)0x00001000) #define DBGMCU_TIM4_STOP ((uint32_t)0x00002000) #define DBGMCU_CAN1_STOP ((uint32_t)0x00004000) #define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) #define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) #define DBGMCU_TIM8_STOP ((uint32_t)0x00020000) #define DBGMCU_TIM5_STOP ((uint32_t)0x00040000) #define DBGMCU_TIM6_STOP ((uint32_t)0x00080000) #define DBGMCU_TIM7_STOP ((uint32_t)0x00100000) #define DBGMCU_CAN2_STOP ((uint32_t)0x00200000) #define DBGMCU_TIM15_STOP ((uint32_t)0x00400000) #define DBGMCU_TIM16_STOP ((uint32_t)0x00800000) #define DBGMCU_TIM17_STOP ((uint32_t)0x01000000) #define DBGMCU_TIM12_STOP ((uint32_t)0x02000000) #define DBGMCU_TIM13_STOP ((uint32_t)0x04000000) #define DBGMCU_TIM14_STOP ((uint32_t)0x08000000) #define DBGMCU_TIM9_STOP ((uint32_t)0x10000000) #define DBGMCU_TIM10_STOP ((uint32_t)0x20000000) #define DBGMCU_TIM11_STOP ((uint32_t)0x40000000) #define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00)) /** * @} */ /** @defgroup DBGMCU_Exported_Macros * @{ */ /** * @} */ /** @defgroup DBGMCU_Exported_Functions * @{ */ uint32_t DBGMCU_GetREVID(void); uint32_t DBGMCU_GetDEVID(void); void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); #ifdef __cplusplus } #endif #endif /* __STM32F10x_DBGMCU_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /** ****************************************************************************** * @file stm32f10x_dbgmcu.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the DBGMCU * firmware library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_DBGMCU_H #define __STM32F10x_DBGMCU_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup DBGMCU * @{ */ /** @defgroup DBGMCU_Exported_Types * @{ */ /** * @} */ /** @defgroup DBGMCU_Exported_Constants * @{ */ #define DBGMCU_SLEEP ((uint32_t)0x00000001) #define DBGMCU_STOP ((uint32_t)0x00000002) #define DBGMCU_STANDBY ((uint32_t)0x00000004) #define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) #define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) #define DBGMCU_TIM1_STOP ((uint32_t)0x00000400) #define DBGMCU_TIM2_STOP ((uint32_t)0x00000800) #define DBGMCU_TIM3_STOP ((uint32_t)0x00001000) #define DBGMCU_TIM4_STOP ((uint32_t)0x00002000) #define DBGMCU_CAN1_STOP ((uint32_t)0x00004000) #define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) #define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) #define DBGMCU_TIM8_STOP ((uint32_t)0x00020000) #define DBGMCU_TIM5_STOP ((uint32_t)0x00040000) #define DBGMCU_TIM6_STOP ((uint32_t)0x00080000) #define DBGMCU_TIM7_STOP ((uint32_t)0x00100000) #define DBGMCU_CAN2_STOP ((uint32_t)0x00200000) #define DBGMCU_TIM15_STOP ((uint32_t)0x00400000) #define DBGMCU_TIM16_STOP ((uint32_t)0x00800000) #define DBGMCU_TIM17_STOP ((uint32_t)0x01000000) #define DBGMCU_TIM12_STOP ((uint32_t)0x02000000) #define DBGMCU_TIM13_STOP ((uint32_t)0x04000000) #define DBGMCU_TIM14_STOP ((uint32_t)0x08000000) #define DBGMCU_TIM9_STOP ((uint32_t)0x10000000) #define DBGMCU_TIM10_STOP ((uint32_t)0x20000000) #define DBGMCU_TIM11_STOP ((uint32_t)0x40000000) #define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00)) /** * @} */ /** @defgroup DBGMCU_Exported_Macros * @{ */ /** * @} */ /** @defgroup DBGMCU_Exported_Functions * @{ */ uint32_t DBGMCU_GetREVID(void); uint32_t DBGMCU_GetDEVID(void); void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); #ifdef __cplusplus } #endif #endif /* __STM32F10x_DBGMCU_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ src/bare_test/1.Led/stdlib/inc/stm32f10x_dma.h
File was renamed from src/bare_test/stm32_key/fwlib/inc/stm32f10x_dma.h @@ -1,439 +1,439 @@ /** ****************************************************************************** * @file stm32f10x_dma.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the DMA firmware * library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_DMA_H #define __STM32F10x_DMA_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup DMA * @{ */ /** @defgroup DMA_Exported_Types * @{ */ /** * @brief DMA Init structure definition */ typedef struct { uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */ uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination. This parameter can be a value of @ref DMA_data_transfer_direction */ uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. The data unit is equal to the configuration set in DMA_PeripheralDataSize or DMA_MemoryDataSize members depending in the transfer direction. */ uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not. This parameter can be a value of @ref DMA_peripheral_incremented_mode */ uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. This parameter can be a value of @ref DMA_memory_incremented_mode */ uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. This parameter can be a value of @ref DMA_peripheral_data_size */ uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. This parameter can be a value of @ref DMA_memory_data_size */ uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx. This parameter can be a value of @ref DMA_circular_normal_mode. @note: The circular buffer mode cannot be used if the memory-to-memory data transfer is configured on the selected Channel */ uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx. This parameter can be a value of @ref DMA_priority_level */ uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer. This parameter can be a value of @ref DMA_memory_to_memory */ }DMA_InitTypeDef; /** * @} */ /** @defgroup DMA_Exported_Constants * @{ */ #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \ ((PERIPH) == DMA1_Channel2) || \ ((PERIPH) == DMA1_Channel3) || \ ((PERIPH) == DMA1_Channel4) || \ ((PERIPH) == DMA1_Channel5) || \ ((PERIPH) == DMA1_Channel6) || \ ((PERIPH) == DMA1_Channel7) || \ ((PERIPH) == DMA2_Channel1) || \ ((PERIPH) == DMA2_Channel2) || \ ((PERIPH) == DMA2_Channel3) || \ ((PERIPH) == DMA2_Channel4) || \ ((PERIPH) == DMA2_Channel5)) /** @defgroup DMA_data_transfer_direction * @{ */ #define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) #define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) #define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \ ((DIR) == DMA_DIR_PeripheralSRC)) /** * @} */ /** @defgroup DMA_peripheral_incremented_mode * @{ */ #define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ ((STATE) == DMA_PeripheralInc_Disable)) /** * @} */ /** @defgroup DMA_memory_incremented_mode * @{ */ #define DMA_MemoryInc_Enable ((uint32_t)0x00000080) #define DMA_MemoryInc_Disable ((uint32_t)0x00000000) #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ ((STATE) == DMA_MemoryInc_Disable)) /** * @} */ /** @defgroup DMA_peripheral_data_size * @{ */ #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) #define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) #define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ ((SIZE) == DMA_PeripheralDataSize_Word)) /** * @} */ /** @defgroup DMA_memory_data_size * @{ */ #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) #define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) #define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ ((SIZE) == DMA_MemoryDataSize_Word)) /** * @} */ /** @defgroup DMA_circular_normal_mode * @{ */ #define DMA_Mode_Circular ((uint32_t)0x00000020) #define DMA_Mode_Normal ((uint32_t)0x00000000) #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal)) /** * @} */ /** @defgroup DMA_priority_level * @{ */ #define DMA_Priority_VeryHigh ((uint32_t)0x00003000) #define DMA_Priority_High ((uint32_t)0x00002000) #define DMA_Priority_Medium ((uint32_t)0x00001000) #define DMA_Priority_Low ((uint32_t)0x00000000) #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ ((PRIORITY) == DMA_Priority_High) || \ ((PRIORITY) == DMA_Priority_Medium) || \ ((PRIORITY) == DMA_Priority_Low)) /** * @} */ /** @defgroup DMA_memory_to_memory * @{ */ #define DMA_M2M_Enable ((uint32_t)0x00004000) #define DMA_M2M_Disable ((uint32_t)0x00000000) #define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable)) /** * @} */ /** @defgroup DMA_interrupts_definition * @{ */ #define DMA_IT_TC ((uint32_t)0x00000002) #define DMA_IT_HT ((uint32_t)0x00000004) #define DMA_IT_TE ((uint32_t)0x00000008) #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) #define DMA1_IT_GL1 ((uint32_t)0x00000001) #define DMA1_IT_TC1 ((uint32_t)0x00000002) #define DMA1_IT_HT1 ((uint32_t)0x00000004) #define DMA1_IT_TE1 ((uint32_t)0x00000008) #define DMA1_IT_GL2 ((uint32_t)0x00000010) #define DMA1_IT_TC2 ((uint32_t)0x00000020) #define DMA1_IT_HT2 ((uint32_t)0x00000040) #define DMA1_IT_TE2 ((uint32_t)0x00000080) #define DMA1_IT_GL3 ((uint32_t)0x00000100) #define DMA1_IT_TC3 ((uint32_t)0x00000200) #define DMA1_IT_HT3 ((uint32_t)0x00000400) #define DMA1_IT_TE3 ((uint32_t)0x00000800) #define DMA1_IT_GL4 ((uint32_t)0x00001000) #define DMA1_IT_TC4 ((uint32_t)0x00002000) #define DMA1_IT_HT4 ((uint32_t)0x00004000) #define DMA1_IT_TE4 ((uint32_t)0x00008000) #define DMA1_IT_GL5 ((uint32_t)0x00010000) #define DMA1_IT_TC5 ((uint32_t)0x00020000) #define DMA1_IT_HT5 ((uint32_t)0x00040000) #define DMA1_IT_TE5 ((uint32_t)0x00080000) #define DMA1_IT_GL6 ((uint32_t)0x00100000) #define DMA1_IT_TC6 ((uint32_t)0x00200000) #define DMA1_IT_HT6 ((uint32_t)0x00400000) #define DMA1_IT_TE6 ((uint32_t)0x00800000) #define DMA1_IT_GL7 ((uint32_t)0x01000000) #define DMA1_IT_TC7 ((uint32_t)0x02000000) #define DMA1_IT_HT7 ((uint32_t)0x04000000) #define DMA1_IT_TE7 ((uint32_t)0x08000000) #define DMA2_IT_GL1 ((uint32_t)0x10000001) #define DMA2_IT_TC1 ((uint32_t)0x10000002) #define DMA2_IT_HT1 ((uint32_t)0x10000004) #define DMA2_IT_TE1 ((uint32_t)0x10000008) #define DMA2_IT_GL2 ((uint32_t)0x10000010) #define DMA2_IT_TC2 ((uint32_t)0x10000020) #define DMA2_IT_HT2 ((uint32_t)0x10000040) #define DMA2_IT_TE2 ((uint32_t)0x10000080) #define DMA2_IT_GL3 ((uint32_t)0x10000100) #define DMA2_IT_TC3 ((uint32_t)0x10000200) #define DMA2_IT_HT3 ((uint32_t)0x10000400) #define DMA2_IT_TE3 ((uint32_t)0x10000800) #define DMA2_IT_GL4 ((uint32_t)0x10001000) #define DMA2_IT_TC4 ((uint32_t)0x10002000) #define DMA2_IT_HT4 ((uint32_t)0x10004000) #define DMA2_IT_TE4 ((uint32_t)0x10008000) #define DMA2_IT_GL5 ((uint32_t)0x10010000) #define DMA2_IT_TC5 ((uint32_t)0x10020000) #define DMA2_IT_HT5 ((uint32_t)0x10040000) #define DMA2_IT_TE5 ((uint32_t)0x10080000) #define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00)) #define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \ ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \ ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \ ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \ ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \ ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \ ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \ ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \ ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \ ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \ ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \ ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \ ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \ ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \ ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \ ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \ ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \ ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \ ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \ ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \ ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \ ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \ ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5)) /** * @} */ /** @defgroup DMA_flags_definition * @{ */ #define DMA1_FLAG_GL1 ((uint32_t)0x00000001) #define DMA1_FLAG_TC1 ((uint32_t)0x00000002) #define DMA1_FLAG_HT1 ((uint32_t)0x00000004) #define DMA1_FLAG_TE1 ((uint32_t)0x00000008) #define DMA1_FLAG_GL2 ((uint32_t)0x00000010) #define DMA1_FLAG_TC2 ((uint32_t)0x00000020) #define DMA1_FLAG_HT2 ((uint32_t)0x00000040) #define DMA1_FLAG_TE2 ((uint32_t)0x00000080) #define DMA1_FLAG_GL3 ((uint32_t)0x00000100) #define DMA1_FLAG_TC3 ((uint32_t)0x00000200) #define DMA1_FLAG_HT3 ((uint32_t)0x00000400) #define DMA1_FLAG_TE3 ((uint32_t)0x00000800) #define DMA1_FLAG_GL4 ((uint32_t)0x00001000) #define DMA1_FLAG_TC4 ((uint32_t)0x00002000) #define DMA1_FLAG_HT4 ((uint32_t)0x00004000) #define DMA1_FLAG_TE4 ((uint32_t)0x00008000) #define DMA1_FLAG_GL5 ((uint32_t)0x00010000) #define DMA1_FLAG_TC5 ((uint32_t)0x00020000) #define DMA1_FLAG_HT5 ((uint32_t)0x00040000) #define DMA1_FLAG_TE5 ((uint32_t)0x00080000) #define DMA1_FLAG_GL6 ((uint32_t)0x00100000) #define DMA1_FLAG_TC6 ((uint32_t)0x00200000) #define DMA1_FLAG_HT6 ((uint32_t)0x00400000) #define DMA1_FLAG_TE6 ((uint32_t)0x00800000) #define DMA1_FLAG_GL7 ((uint32_t)0x01000000) #define DMA1_FLAG_TC7 ((uint32_t)0x02000000) #define DMA1_FLAG_HT7 ((uint32_t)0x04000000) #define DMA1_FLAG_TE7 ((uint32_t)0x08000000) #define DMA2_FLAG_GL1 ((uint32_t)0x10000001) #define DMA2_FLAG_TC1 ((uint32_t)0x10000002) #define DMA2_FLAG_HT1 ((uint32_t)0x10000004) #define DMA2_FLAG_TE1 ((uint32_t)0x10000008) #define DMA2_FLAG_GL2 ((uint32_t)0x10000010) #define DMA2_FLAG_TC2 ((uint32_t)0x10000020) #define DMA2_FLAG_HT2 ((uint32_t)0x10000040) #define DMA2_FLAG_TE2 ((uint32_t)0x10000080) #define DMA2_FLAG_GL3 ((uint32_t)0x10000100) #define DMA2_FLAG_TC3 ((uint32_t)0x10000200) #define DMA2_FLAG_HT3 ((uint32_t)0x10000400) #define DMA2_FLAG_TE3 ((uint32_t)0x10000800) #define DMA2_FLAG_GL4 ((uint32_t)0x10001000) #define DMA2_FLAG_TC4 ((uint32_t)0x10002000) #define DMA2_FLAG_HT4 ((uint32_t)0x10004000) #define DMA2_FLAG_TE4 ((uint32_t)0x10008000) #define DMA2_FLAG_GL5 ((uint32_t)0x10010000) #define DMA2_FLAG_TC5 ((uint32_t)0x10020000) #define DMA2_FLAG_HT5 ((uint32_t)0x10040000) #define DMA2_FLAG_TE5 ((uint32_t)0x10080000) #define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00)) #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \ ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \ ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \ ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \ ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \ ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \ ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \ ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \ ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \ ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \ ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \ ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \ ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \ ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \ ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \ ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \ ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \ ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \ ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \ ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \ ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \ ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \ ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5)) /** * @} */ /** @defgroup DMA_Buffer_Size * @{ */ #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) /** * @} */ /** * @} */ /** @defgroup DMA_Exported_Macros * @{ */ /** * @} */ /** @defgroup DMA_Exported_Functions * @{ */ void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); void DMA_ClearFlag(uint32_t DMAy_FLAG); ITStatus DMA_GetITStatus(uint32_t DMAy_IT); void DMA_ClearITPendingBit(uint32_t DMAy_IT); #ifdef __cplusplus } #endif #endif /*__STM32F10x_DMA_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /** ****************************************************************************** * @file stm32f10x_dma.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the DMA firmware * library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_DMA_H #define __STM32F10x_DMA_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup DMA * @{ */ /** @defgroup DMA_Exported_Types * @{ */ /** * @brief DMA Init structure definition */ typedef struct { uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */ uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination. This parameter can be a value of @ref DMA_data_transfer_direction */ uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. The data unit is equal to the configuration set in DMA_PeripheralDataSize or DMA_MemoryDataSize members depending in the transfer direction. */ uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not. This parameter can be a value of @ref DMA_peripheral_incremented_mode */ uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. This parameter can be a value of @ref DMA_memory_incremented_mode */ uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. This parameter can be a value of @ref DMA_peripheral_data_size */ uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. This parameter can be a value of @ref DMA_memory_data_size */ uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx. This parameter can be a value of @ref DMA_circular_normal_mode. @note: The circular buffer mode cannot be used if the memory-to-memory data transfer is configured on the selected Channel */ uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx. This parameter can be a value of @ref DMA_priority_level */ uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer. This parameter can be a value of @ref DMA_memory_to_memory */ }DMA_InitTypeDef; /** * @} */ /** @defgroup DMA_Exported_Constants * @{ */ #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \ ((PERIPH) == DMA1_Channel2) || \ ((PERIPH) == DMA1_Channel3) || \ ((PERIPH) == DMA1_Channel4) || \ ((PERIPH) == DMA1_Channel5) || \ ((PERIPH) == DMA1_Channel6) || \ ((PERIPH) == DMA1_Channel7) || \ ((PERIPH) == DMA2_Channel1) || \ ((PERIPH) == DMA2_Channel2) || \ ((PERIPH) == DMA2_Channel3) || \ ((PERIPH) == DMA2_Channel4) || \ ((PERIPH) == DMA2_Channel5)) /** @defgroup DMA_data_transfer_direction * @{ */ #define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) #define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) #define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \ ((DIR) == DMA_DIR_PeripheralSRC)) /** * @} */ /** @defgroup DMA_peripheral_incremented_mode * @{ */ #define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ ((STATE) == DMA_PeripheralInc_Disable)) /** * @} */ /** @defgroup DMA_memory_incremented_mode * @{ */ #define DMA_MemoryInc_Enable ((uint32_t)0x00000080) #define DMA_MemoryInc_Disable ((uint32_t)0x00000000) #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ ((STATE) == DMA_MemoryInc_Disable)) /** * @} */ /** @defgroup DMA_peripheral_data_size * @{ */ #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) #define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) #define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ ((SIZE) == DMA_PeripheralDataSize_Word)) /** * @} */ /** @defgroup DMA_memory_data_size * @{ */ #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) #define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) #define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ ((SIZE) == DMA_MemoryDataSize_Word)) /** * @} */ /** @defgroup DMA_circular_normal_mode * @{ */ #define DMA_Mode_Circular ((uint32_t)0x00000020) #define DMA_Mode_Normal ((uint32_t)0x00000000) #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal)) /** * @} */ /** @defgroup DMA_priority_level * @{ */ #define DMA_Priority_VeryHigh ((uint32_t)0x00003000) #define DMA_Priority_High ((uint32_t)0x00002000) #define DMA_Priority_Medium ((uint32_t)0x00001000) #define DMA_Priority_Low ((uint32_t)0x00000000) #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ ((PRIORITY) == DMA_Priority_High) || \ ((PRIORITY) == DMA_Priority_Medium) || \ ((PRIORITY) == DMA_Priority_Low)) /** * @} */ /** @defgroup DMA_memory_to_memory * @{ */ #define DMA_M2M_Enable ((uint32_t)0x00004000) #define DMA_M2M_Disable ((uint32_t)0x00000000) #define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable)) /** * @} */ /** @defgroup DMA_interrupts_definition * @{ */ #define DMA_IT_TC ((uint32_t)0x00000002) #define DMA_IT_HT ((uint32_t)0x00000004) #define DMA_IT_TE ((uint32_t)0x00000008) #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) #define DMA1_IT_GL1 ((uint32_t)0x00000001) #define DMA1_IT_TC1 ((uint32_t)0x00000002) #define DMA1_IT_HT1 ((uint32_t)0x00000004) #define DMA1_IT_TE1 ((uint32_t)0x00000008) #define DMA1_IT_GL2 ((uint32_t)0x00000010) #define DMA1_IT_TC2 ((uint32_t)0x00000020) #define DMA1_IT_HT2 ((uint32_t)0x00000040) #define DMA1_IT_TE2 ((uint32_t)0x00000080) #define DMA1_IT_GL3 ((uint32_t)0x00000100) #define DMA1_IT_TC3 ((uint32_t)0x00000200) #define DMA1_IT_HT3 ((uint32_t)0x00000400) #define DMA1_IT_TE3 ((uint32_t)0x00000800) #define DMA1_IT_GL4 ((uint32_t)0x00001000) #define DMA1_IT_TC4 ((uint32_t)0x00002000) #define DMA1_IT_HT4 ((uint32_t)0x00004000) #define DMA1_IT_TE4 ((uint32_t)0x00008000) #define DMA1_IT_GL5 ((uint32_t)0x00010000) #define DMA1_IT_TC5 ((uint32_t)0x00020000) #define DMA1_IT_HT5 ((uint32_t)0x00040000) #define DMA1_IT_TE5 ((uint32_t)0x00080000) #define DMA1_IT_GL6 ((uint32_t)0x00100000) #define DMA1_IT_TC6 ((uint32_t)0x00200000) #define DMA1_IT_HT6 ((uint32_t)0x00400000) #define DMA1_IT_TE6 ((uint32_t)0x00800000) #define DMA1_IT_GL7 ((uint32_t)0x01000000) #define DMA1_IT_TC7 ((uint32_t)0x02000000) #define DMA1_IT_HT7 ((uint32_t)0x04000000) #define DMA1_IT_TE7 ((uint32_t)0x08000000) #define DMA2_IT_GL1 ((uint32_t)0x10000001) #define DMA2_IT_TC1 ((uint32_t)0x10000002) #define DMA2_IT_HT1 ((uint32_t)0x10000004) #define DMA2_IT_TE1 ((uint32_t)0x10000008) #define DMA2_IT_GL2 ((uint32_t)0x10000010) #define DMA2_IT_TC2 ((uint32_t)0x10000020) #define DMA2_IT_HT2 ((uint32_t)0x10000040) #define DMA2_IT_TE2 ((uint32_t)0x10000080) #define DMA2_IT_GL3 ((uint32_t)0x10000100) #define DMA2_IT_TC3 ((uint32_t)0x10000200) #define DMA2_IT_HT3 ((uint32_t)0x10000400) #define DMA2_IT_TE3 ((uint32_t)0x10000800) #define DMA2_IT_GL4 ((uint32_t)0x10001000) #define DMA2_IT_TC4 ((uint32_t)0x10002000) #define DMA2_IT_HT4 ((uint32_t)0x10004000) #define DMA2_IT_TE4 ((uint32_t)0x10008000) #define DMA2_IT_GL5 ((uint32_t)0x10010000) #define DMA2_IT_TC5 ((uint32_t)0x10020000) #define DMA2_IT_HT5 ((uint32_t)0x10040000) #define DMA2_IT_TE5 ((uint32_t)0x10080000) #define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00)) #define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \ ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \ ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \ ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \ ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \ ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \ ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \ ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \ ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \ ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \ ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \ ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \ ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \ ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \ ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \ ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \ ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \ ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \ ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \ ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \ ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \ ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \ ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5)) /** * @} */ /** @defgroup DMA_flags_definition * @{ */ #define DMA1_FLAG_GL1 ((uint32_t)0x00000001) #define DMA1_FLAG_TC1 ((uint32_t)0x00000002) #define DMA1_FLAG_HT1 ((uint32_t)0x00000004) #define DMA1_FLAG_TE1 ((uint32_t)0x00000008) #define DMA1_FLAG_GL2 ((uint32_t)0x00000010) #define DMA1_FLAG_TC2 ((uint32_t)0x00000020) #define DMA1_FLAG_HT2 ((uint32_t)0x00000040) #define DMA1_FLAG_TE2 ((uint32_t)0x00000080) #define DMA1_FLAG_GL3 ((uint32_t)0x00000100) #define DMA1_FLAG_TC3 ((uint32_t)0x00000200) #define DMA1_FLAG_HT3 ((uint32_t)0x00000400) #define DMA1_FLAG_TE3 ((uint32_t)0x00000800) #define DMA1_FLAG_GL4 ((uint32_t)0x00001000) #define DMA1_FLAG_TC4 ((uint32_t)0x00002000) #define DMA1_FLAG_HT4 ((uint32_t)0x00004000) #define DMA1_FLAG_TE4 ((uint32_t)0x00008000) #define DMA1_FLAG_GL5 ((uint32_t)0x00010000) #define DMA1_FLAG_TC5 ((uint32_t)0x00020000) #define DMA1_FLAG_HT5 ((uint32_t)0x00040000) #define DMA1_FLAG_TE5 ((uint32_t)0x00080000) #define DMA1_FLAG_GL6 ((uint32_t)0x00100000) #define DMA1_FLAG_TC6 ((uint32_t)0x00200000) #define DMA1_FLAG_HT6 ((uint32_t)0x00400000) #define DMA1_FLAG_TE6 ((uint32_t)0x00800000) #define DMA1_FLAG_GL7 ((uint32_t)0x01000000) #define DMA1_FLAG_TC7 ((uint32_t)0x02000000) #define DMA1_FLAG_HT7 ((uint32_t)0x04000000) #define DMA1_FLAG_TE7 ((uint32_t)0x08000000) #define DMA2_FLAG_GL1 ((uint32_t)0x10000001) #define DMA2_FLAG_TC1 ((uint32_t)0x10000002) #define DMA2_FLAG_HT1 ((uint32_t)0x10000004) #define DMA2_FLAG_TE1 ((uint32_t)0x10000008) #define DMA2_FLAG_GL2 ((uint32_t)0x10000010) #define DMA2_FLAG_TC2 ((uint32_t)0x10000020) #define DMA2_FLAG_HT2 ((uint32_t)0x10000040) #define DMA2_FLAG_TE2 ((uint32_t)0x10000080) #define DMA2_FLAG_GL3 ((uint32_t)0x10000100) #define DMA2_FLAG_TC3 ((uint32_t)0x10000200) #define DMA2_FLAG_HT3 ((uint32_t)0x10000400) #define DMA2_FLAG_TE3 ((uint32_t)0x10000800) #define DMA2_FLAG_GL4 ((uint32_t)0x10001000) #define DMA2_FLAG_TC4 ((uint32_t)0x10002000) #define DMA2_FLAG_HT4 ((uint32_t)0x10004000) #define DMA2_FLAG_TE4 ((uint32_t)0x10008000) #define DMA2_FLAG_GL5 ((uint32_t)0x10010000) #define DMA2_FLAG_TC5 ((uint32_t)0x10020000) #define DMA2_FLAG_HT5 ((uint32_t)0x10040000) #define DMA2_FLAG_TE5 ((uint32_t)0x10080000) #define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00)) #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \ ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \ ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \ ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \ ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \ ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \ ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \ ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \ ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \ ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \ ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \ ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \ ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \ ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \ ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \ ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \ ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \ ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \ ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \ ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \ ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \ ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \ ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5)) /** * @} */ /** @defgroup DMA_Buffer_Size * @{ */ #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) /** * @} */ /** * @} */ /** @defgroup DMA_Exported_Macros * @{ */ /** * @} */ /** @defgroup DMA_Exported_Functions * @{ */ void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); void DMA_ClearFlag(uint32_t DMAy_FLAG); ITStatus DMA_GetITStatus(uint32_t DMAy_IT); void DMA_ClearITPendingBit(uint32_t DMAy_IT); #ifdef __cplusplus } #endif #endif /*__STM32F10x_DMA_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ src/bare_test/1.Led/stdlib/inc/stm32f10x_exti.h
File was renamed from src/bare_test/stm32_key/fwlib/inc/stm32f10x_exti.h @@ -1,184 +1,184 @@ /** ****************************************************************************** * @file stm32f10x_exti.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the EXTI firmware * library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_EXTI_H #define __STM32F10x_EXTI_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup EXTI * @{ */ /** @defgroup EXTI_Exported_Types * @{ */ /** * @brief EXTI mode enumeration */ typedef enum { EXTI_Mode_Interrupt = 0x00, EXTI_Mode_Event = 0x04 }EXTIMode_TypeDef; #define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) /** * @brief EXTI Trigger enumeration */ typedef enum { EXTI_Trigger_Rising = 0x08, EXTI_Trigger_Falling = 0x0C, EXTI_Trigger_Rising_Falling = 0x10 }EXTITrigger_TypeDef; #define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ ((TRIGGER) == EXTI_Trigger_Falling) || \ ((TRIGGER) == EXTI_Trigger_Rising_Falling)) /** * @brief EXTI Init Structure definition */ typedef struct { uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. This parameter can be any combination of @ref EXTI_Lines */ EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. This parameter can be a value of @ref EXTIMode_TypeDef */ EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. This parameter can be a value of @ref EXTIMode_TypeDef */ FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. This parameter can be set either to ENABLE or DISABLE */ }EXTI_InitTypeDef; /** * @} */ /** @defgroup EXTI_Exported_Constants * @{ */ /** @defgroup EXTI_Lines * @{ */ #define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ #define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ #define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ #define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ #define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ #define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ #define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ #define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ #define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ #define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ #define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ #define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ #define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ #define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ #define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ #define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ #define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ #define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ #define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS Wakeup from suspend event */ #define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ #define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00)) #define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19)) /** * @} */ /** * @} */ /** @defgroup EXTI_Exported_Macros * @{ */ /** * @} */ /** @defgroup EXTI_Exported_Functions * @{ */ void EXTI_DeInit(void); void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); void EXTI_ClearFlag(uint32_t EXTI_Line); ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); void EXTI_ClearITPendingBit(uint32_t EXTI_Line); #ifdef __cplusplus } #endif #endif /* __STM32F10x_EXTI_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /** ****************************************************************************** * @file stm32f10x_exti.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the EXTI firmware * library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_EXTI_H #define __STM32F10x_EXTI_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup EXTI * @{ */ /** @defgroup EXTI_Exported_Types * @{ */ /** * @brief EXTI mode enumeration */ typedef enum { EXTI_Mode_Interrupt = 0x00, EXTI_Mode_Event = 0x04 }EXTIMode_TypeDef; #define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) /** * @brief EXTI Trigger enumeration */ typedef enum { EXTI_Trigger_Rising = 0x08, EXTI_Trigger_Falling = 0x0C, EXTI_Trigger_Rising_Falling = 0x10 }EXTITrigger_TypeDef; #define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ ((TRIGGER) == EXTI_Trigger_Falling) || \ ((TRIGGER) == EXTI_Trigger_Rising_Falling)) /** * @brief EXTI Init Structure definition */ typedef struct { uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. This parameter can be any combination of @ref EXTI_Lines */ EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. This parameter can be a value of @ref EXTIMode_TypeDef */ EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. This parameter can be a value of @ref EXTIMode_TypeDef */ FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. This parameter can be set either to ENABLE or DISABLE */ }EXTI_InitTypeDef; /** * @} */ /** @defgroup EXTI_Exported_Constants * @{ */ /** @defgroup EXTI_Lines * @{ */ #define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ #define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ #define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ #define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ #define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ #define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ #define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ #define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ #define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ #define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ #define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ #define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ #define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ #define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ #define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ #define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ #define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ #define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ #define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS Wakeup from suspend event */ #define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ #define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00)) #define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19)) /** * @} */ /** * @} */ /** @defgroup EXTI_Exported_Macros * @{ */ /** * @} */ /** @defgroup EXTI_Exported_Functions * @{ */ void EXTI_DeInit(void); void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); void EXTI_ClearFlag(uint32_t EXTI_Line); ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); void EXTI_ClearITPendingBit(uint32_t EXTI_Line); #ifdef __cplusplus } #endif #endif /* __STM32F10x_EXTI_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ src/bare_test/1.Led/stdlib/inc/stm32f10x_flash.h
File was renamed from src/bare_test/stm32_key/fwlib/inc/stm32f10x_flash.h @@ -1,426 +1,426 @@ /** ****************************************************************************** * @file stm32f10x_flash.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the FLASH * firmware library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_FLASH_H #define __STM32F10x_FLASH_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup FLASH * @{ */ /** @defgroup FLASH_Exported_Types * @{ */ /** * @brief FLASH Status */ typedef enum { FLASH_BUSY = 1, FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE, FLASH_TIMEOUT }FLASH_Status; /** * @} */ /** @defgroup FLASH_Exported_Constants * @{ */ /** @defgroup Flash_Latency * @{ */ #define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */ #define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */ #define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */ #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ ((LATENCY) == FLASH_Latency_1) || \ ((LATENCY) == FLASH_Latency_2)) /** * @} */ /** @defgroup Half_Cycle_Enable_Disable * @{ */ #define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */ #define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */ #define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \ ((STATE) == FLASH_HalfCycleAccess_Disable)) /** * @} */ /** @defgroup Prefetch_Buffer_Enable_Disable * @{ */ #define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */ #define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */ #define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \ ((STATE) == FLASH_PrefetchBuffer_Disable)) /** * @} */ /** @defgroup Option_Bytes_Write_Protection * @{ */ /* Values to be used with STM32 Low and Medium density devices */ #define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */ #define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */ #define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */ #define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */ #define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */ #define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */ #define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */ #define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */ /* Values to be used with STM32 Medium-density devices */ #define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */ #define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */ #define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */ #define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */ #define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */ #define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */ #define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */ #define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */ #define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */ #define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */ #define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */ #define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */ #define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */ #define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */ #define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */ #define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */ #define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */ #define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */ #define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */ #define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */ #define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */ #define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */ #define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */ #define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */ /* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */ #define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 0 to 1 */ #define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 2 to 3 */ #define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 4 to 5 */ #define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 6 to 7 */ #define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 8 to 9 */ #define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 10 to 11 */ #define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 12 to 13 */ #define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 14 to 15 */ #define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 16 to 17 */ #define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 18 to 19 */ #define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 20 to 21 */ #define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 22 to 23 */ #define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 24 to 25 */ #define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 26 to 27 */ #define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 28 to 29 */ #define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 30 to 31 */ #define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 32 to 33 */ #define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 34 to 35 */ #define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 36 to 37 */ #define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 38 to 39 */ #define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 40 to 41 */ #define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 42 to 43 */ #define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 44 to 45 */ #define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 46 to 47 */ #define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 48 to 49 */ #define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 50 to 51 */ #define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 52 to 53 */ #define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 54 to 55 */ #define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 56 to 57 */ #define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 58 to 59 */ #define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 60 to 61 */ #define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */ #define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */ #define FLASH_WRProt_Pages62to511 ((uint32_t)0x80000000) /*!< STM32 XL-density devices: Write protection of page 62 to 511 */ #define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */ #define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000)) #define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) #define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806)) /** * @} */ /** @defgroup Option_Bytes_IWatchdog * @{ */ #define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */ #define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */ #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) /** * @} */ /** @defgroup Option_Bytes_nRST_STOP * @{ */ #define OB_STOP_NoRST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */ #define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */ #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) /** * @} */ /** @defgroup Option_Bytes_nRST_STDBY * @{ */ #define OB_STDBY_NoRST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */ #define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */ #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) #ifdef STM32F10X_XL /** * @} */ /** @defgroup FLASH_Boot * @{ */ #define FLASH_BOOT_Bank1 ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position and this parameter is selected the device will boot from Bank1(Default) */ #define FLASH_BOOT_Bank2 ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position and this parameter is selected the device will boot from Bank 2 or Bank 1, depending on the activation of the bank */ #define IS_FLASH_BOOT(BOOT) (((BOOT) == FLASH_BOOT_Bank1) || ((BOOT) == FLASH_BOOT_Bank2)) #endif /** * @} */ /** @defgroup FLASH_Interrupts * @{ */ #ifdef STM32F10X_XL #define FLASH_IT_BANK2_ERROR ((uint32_t)0x80000400) /*!< FPEC BANK2 error interrupt source */ #define FLASH_IT_BANK2_EOP ((uint32_t)0x80001000) /*!< End of FLASH BANK2 Operation Interrupt source */ #define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */ #define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */ #define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC BANK1 error interrupt source */ #define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH BANK1 Operation Interrupt source */ #define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0x7FFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) #else #define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */ #define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */ #define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */ #define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */ #define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) #endif /** * @} */ /** @defgroup FLASH_Flags * @{ */ #ifdef STM32F10X_XL #define FLASH_FLAG_BANK2_BSY ((uint32_t)0x80000001) /*!< FLASH BANK2 Busy flag */ #define FLASH_FLAG_BANK2_EOP ((uint32_t)0x80000020) /*!< FLASH BANK2 End of Operation flag */ #define FLASH_FLAG_BANK2_PGERR ((uint32_t)0x80000004) /*!< FLASH BANK2 Program error flag */ #define FLASH_FLAG_BANK2_WRPRTERR ((uint32_t)0x80000010) /*!< FLASH BANK2 Write protected error flag */ #define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/ #define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */ #define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */ #define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */ #define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ #define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ #define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ #define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ #define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ #define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x7FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) #define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ ((FLAG) == FLASH_FLAG_OPTERR)|| \ ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \ ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \ ((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || \ ((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR)) #else #define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ #define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ #define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ #define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ #define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ #define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/ #define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */ #define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */ #define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */ #define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) #define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \ ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \ ((FLAG) == FLASH_FLAG_OPTERR)) #endif /** * @} */ /** * @} */ /** @defgroup FLASH_Exported_Macros * @{ */ /** * @} */ /** @defgroup FLASH_Exported_Functions * @{ */ /*------------ Functions used for all STM32F10x devices -----*/ void FLASH_SetLatency(uint32_t FLASH_Latency); void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess); void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer); void FLASH_Unlock(void); void FLASH_Lock(void); FLASH_Status FLASH_ErasePage(uint32_t Page_Address); FLASH_Status FLASH_EraseAllPages(void); FLASH_Status FLASH_EraseOptionBytes(void); FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); uint32_t FLASH_GetUserOptionByte(void); uint32_t FLASH_GetWriteProtectionOptionByte(void); FlagStatus FLASH_GetReadOutProtectionStatus(void); FlagStatus FLASH_GetPrefetchBufferStatus(void); void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); void FLASH_ClearFlag(uint32_t FLASH_FLAG); FLASH_Status FLASH_GetStatus(void); FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); /*------------ New function used for all STM32F10x devices -----*/ void FLASH_UnlockBank1(void); void FLASH_LockBank1(void); FLASH_Status FLASH_EraseAllBank1Pages(void); FLASH_Status FLASH_GetBank1Status(void); FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout); #ifdef STM32F10X_XL /*---- New Functions used only with STM32F10x_XL density devices -----*/ void FLASH_UnlockBank2(void); void FLASH_LockBank2(void); FLASH_Status FLASH_EraseAllBank2Pages(void); FLASH_Status FLASH_GetBank2Status(void); FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout); FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT); #endif #ifdef __cplusplus } #endif #endif /* __STM32F10x_FLASH_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /** ****************************************************************************** * @file stm32f10x_flash.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the FLASH * firmware library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_FLASH_H #define __STM32F10x_FLASH_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup FLASH * @{ */ /** @defgroup FLASH_Exported_Types * @{ */ /** * @brief FLASH Status */ typedef enum { FLASH_BUSY = 1, FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE, FLASH_TIMEOUT }FLASH_Status; /** * @} */ /** @defgroup FLASH_Exported_Constants * @{ */ /** @defgroup Flash_Latency * @{ */ #define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */ #define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */ #define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */ #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ ((LATENCY) == FLASH_Latency_1) || \ ((LATENCY) == FLASH_Latency_2)) /** * @} */ /** @defgroup Half_Cycle_Enable_Disable * @{ */ #define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */ #define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */ #define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \ ((STATE) == FLASH_HalfCycleAccess_Disable)) /** * @} */ /** @defgroup Prefetch_Buffer_Enable_Disable * @{ */ #define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */ #define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */ #define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \ ((STATE) == FLASH_PrefetchBuffer_Disable)) /** * @} */ /** @defgroup Option_Bytes_Write_Protection * @{ */ /* Values to be used with STM32 Low and Medium density devices */ #define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */ #define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */ #define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */ #define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */ #define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */ #define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */ #define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */ #define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */ /* Values to be used with STM32 Medium-density devices */ #define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */ #define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */ #define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */ #define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */ #define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */ #define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */ #define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */ #define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */ #define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */ #define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */ #define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */ #define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */ #define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */ #define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */ #define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */ #define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */ #define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */ #define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */ #define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */ #define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */ #define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */ #define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */ #define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */ #define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */ /* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */ #define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 0 to 1 */ #define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 2 to 3 */ #define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 4 to 5 */ #define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 6 to 7 */ #define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 8 to 9 */ #define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 10 to 11 */ #define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 12 to 13 */ #define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 14 to 15 */ #define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 16 to 17 */ #define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 18 to 19 */ #define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 20 to 21 */ #define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 22 to 23 */ #define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 24 to 25 */ #define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 26 to 27 */ #define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 28 to 29 */ #define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 30 to 31 */ #define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 32 to 33 */ #define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 34 to 35 */ #define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 36 to 37 */ #define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 38 to 39 */ #define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 40 to 41 */ #define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 42 to 43 */ #define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 44 to 45 */ #define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 46 to 47 */ #define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 48 to 49 */ #define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 50 to 51 */ #define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 52 to 53 */ #define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 54 to 55 */ #define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 56 to 57 */ #define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 58 to 59 */ #define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 High-density, XL-density and Connectivity line devices: Write protection of page 60 to 61 */ #define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */ #define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */ #define FLASH_WRProt_Pages62to511 ((uint32_t)0x80000000) /*!< STM32 XL-density devices: Write protection of page 62 to 511 */ #define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */ #define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000)) #define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) #define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806)) /** * @} */ /** @defgroup Option_Bytes_IWatchdog * @{ */ #define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */ #define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */ #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) /** * @} */ /** @defgroup Option_Bytes_nRST_STOP * @{ */ #define OB_STOP_NoRST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */ #define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */ #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) /** * @} */ /** @defgroup Option_Bytes_nRST_STDBY * @{ */ #define OB_STDBY_NoRST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */ #define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */ #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) #ifdef STM32F10X_XL /** * @} */ /** @defgroup FLASH_Boot * @{ */ #define FLASH_BOOT_Bank1 ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position and this parameter is selected the device will boot from Bank1(Default) */ #define FLASH_BOOT_Bank2 ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position and this parameter is selected the device will boot from Bank 2 or Bank 1, depending on the activation of the bank */ #define IS_FLASH_BOOT(BOOT) (((BOOT) == FLASH_BOOT_Bank1) || ((BOOT) == FLASH_BOOT_Bank2)) #endif /** * @} */ /** @defgroup FLASH_Interrupts * @{ */ #ifdef STM32F10X_XL #define FLASH_IT_BANK2_ERROR ((uint32_t)0x80000400) /*!< FPEC BANK2 error interrupt source */ #define FLASH_IT_BANK2_EOP ((uint32_t)0x80001000) /*!< End of FLASH BANK2 Operation Interrupt source */ #define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */ #define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */ #define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC BANK1 error interrupt source */ #define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH BANK1 Operation Interrupt source */ #define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0x7FFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) #else #define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */ #define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */ #define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */ #define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */ #define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) #endif /** * @} */ /** @defgroup FLASH_Flags * @{ */ #ifdef STM32F10X_XL #define FLASH_FLAG_BANK2_BSY ((uint32_t)0x80000001) /*!< FLASH BANK2 Busy flag */ #define FLASH_FLAG_BANK2_EOP ((uint32_t)0x80000020) /*!< FLASH BANK2 End of Operation flag */ #define FLASH_FLAG_BANK2_PGERR ((uint32_t)0x80000004) /*!< FLASH BANK2 Program error flag */ #define FLASH_FLAG_BANK2_WRPRTERR ((uint32_t)0x80000010) /*!< FLASH BANK2 Write protected error flag */ #define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/ #define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */ #define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */ #define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */ #define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ #define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ #define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ #define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ #define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ #define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x7FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) #define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ ((FLAG) == FLASH_FLAG_OPTERR)|| \ ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \ ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \ ((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || \ ((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR)) #else #define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ #define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ #define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ #define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ #define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ #define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/ #define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */ #define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */ #define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */ #define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) #define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \ ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \ ((FLAG) == FLASH_FLAG_OPTERR)) #endif /** * @} */ /** * @} */ /** @defgroup FLASH_Exported_Macros * @{ */ /** * @} */ /** @defgroup FLASH_Exported_Functions * @{ */ /*------------ Functions used for all STM32F10x devices -----*/ void FLASH_SetLatency(uint32_t FLASH_Latency); void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess); void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer); void FLASH_Unlock(void); void FLASH_Lock(void); FLASH_Status FLASH_ErasePage(uint32_t Page_Address); FLASH_Status FLASH_EraseAllPages(void); FLASH_Status FLASH_EraseOptionBytes(void); FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); uint32_t FLASH_GetUserOptionByte(void); uint32_t FLASH_GetWriteProtectionOptionByte(void); FlagStatus FLASH_GetReadOutProtectionStatus(void); FlagStatus FLASH_GetPrefetchBufferStatus(void); void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); void FLASH_ClearFlag(uint32_t FLASH_FLAG); FLASH_Status FLASH_GetStatus(void); FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); /*------------ New function used for all STM32F10x devices -----*/ void FLASH_UnlockBank1(void); void FLASH_LockBank1(void); FLASH_Status FLASH_EraseAllBank1Pages(void); FLASH_Status FLASH_GetBank1Status(void); FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout); #ifdef STM32F10X_XL /*---- New Functions used only with STM32F10x_XL density devices -----*/ void FLASH_UnlockBank2(void); void FLASH_LockBank2(void); FLASH_Status FLASH_EraseAllBank2Pages(void); FLASH_Status FLASH_GetBank2Status(void); FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout); FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT); #endif #ifdef __cplusplus } #endif #endif /* __STM32F10x_FLASH_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ src/bare_test/1.Led/stdlib/inc/stm32f10x_fsmc.h
File was renamed from src/bare_test/stm32_key/fwlib/inc/stm32f10x_fsmc.h @@ -1,733 +1,733 @@ /** ****************************************************************************** * @file stm32f10x_fsmc.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the FSMC firmware * library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_FSMC_H #define __STM32F10x_FSMC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup FSMC * @{ */ /** @defgroup FSMC_Exported_Types * @{ */ /** * @brief Timing parameters For NOR/SRAM Banks */ typedef struct { uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure the duration of the address setup time. This parameter can be a value between 0 and 0xF. @note: It is not used with synchronous NOR Flash memories. */ uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure the duration of the address hold time. This parameter can be a value between 0 and 0xF. @note: It is not used with synchronous NOR Flash memories.*/ uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure the duration of the data setup time. This parameter can be a value between 0 and 0xFF. @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure the duration of the bus turnaround. This parameter can be a value between 0 and 0xF. @note: It is only used for multiplexed NOR Flash memories. */ uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. This parameter can be a value between 1 and 0xF. @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue to the memory before getting the first data. The value of this parameter depends on the memory type as shown below: - It must be set to 0 in case of a CRAM - It is don't care in asynchronous NOR, SRAM or ROM accesses - It may assume a value between 0 and 0xF in NOR Flash memories with synchronous burst mode enable */ uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. This parameter can be a value of @ref FSMC_Access_Mode */ }FSMC_NORSRAMTimingInitTypeDef; /** * @brief FSMC NOR/SRAM Init structure definition */ typedef struct { uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. This parameter can be a value of @ref FSMC_NORSRAM_Bank */ uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are multiplexed on the databus or not. This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to the corresponding memory bank. This parameter can be a value of @ref FSMC_Memory_Type */ uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. This parameter can be a value of @ref FSMC_Data_Width */ uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, valid only with synchronous burst Flash memories. This parameter can be a value of @ref FSMC_Burst_Access_Mode */ uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, valid only with asynchronous Flash memories. This parameter can be a value of @ref FSMC_AsynchronousWait */ uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing the Flash memory in burst mode. This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash memory, valid only when accessing Flash memories in burst mode. This parameter can be a value of @ref FSMC_Wrap_Mode */ uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one clock cycle before the wait state or during the wait state, valid only when accessing memories in burst mode. This parameter can be a value of @ref FSMC_Wait_Timing */ uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. This parameter can be a value of @ref FSMC_Write_Operation */ uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait signal, valid for Flash memory access in burst mode. This parameter can be a value of @ref FSMC_Wait_Signal */ uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode. This parameter can be a value of @ref FSMC_Extended_Mode */ uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation. This parameter can be a value of @ref FSMC_Write_Burst */ FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ }FSMC_NORSRAMInitTypeDef; /** * @brief Timing parameters For FSMC NAND and PCCARD Banks */ typedef struct { uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before the command assertion for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a value between 0 and 0xFF.*/ uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the command for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between 0x00 and 0xFF */ uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address (and data for write access) after the command deassertion for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between 0x00 and 0xFF */ uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the start of a NAND-Flash write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between 0x00 and 0xFF */ }FSMC_NAND_PCCARDTimingInitTypeDef; /** * @brief FSMC NAND Init structure definition */ typedef struct { uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used. This parameter can be a value of @ref FSMC_NAND_Bank */ uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. This parameter can be any value of @ref FSMC_Wait_feature */ uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. This parameter can be any value of @ref FSMC_Data_Width */ uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation. This parameter can be any value of @ref FSMC_ECC */ uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC. This parameter can be any value of @ref FSMC_ECC_Page_Size */ uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between CLE low and RE low. This parameter can be a value between 0 and 0xFF. */ uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between 0x0 and 0xFF */ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ }FSMC_NANDInitTypeDef; /** * @brief FSMC PCCARD Init structure definition */ typedef struct { uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. This parameter can be any value of @ref FSMC_Wait_feature */ uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between CLE low and RE low. This parameter can be a value between 0 and 0xFF. */ uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between 0x0 and 0xFF */ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ }FSMC_PCCARDInitTypeDef; /** * @} */ /** @defgroup FSMC_Exported_Constants * @{ */ /** @defgroup FSMC_NORSRAM_Bank * @{ */ #define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) #define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) #define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) #define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) /** * @} */ /** @defgroup FSMC_NAND_Bank * @{ */ #define FSMC_Bank2_NAND ((uint32_t)0x00000010) #define FSMC_Bank3_NAND ((uint32_t)0x00000100) /** * @} */ /** @defgroup FSMC_PCCARD_Bank * @{ */ #define FSMC_Bank4_PCCARD ((uint32_t)0x00001000) /** * @} */ #define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ ((BANK) == FSMC_Bank1_NORSRAM2) || \ ((BANK) == FSMC_Bank1_NORSRAM3) || \ ((BANK) == FSMC_Bank1_NORSRAM4)) #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ ((BANK) == FSMC_Bank3_NAND)) #define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ ((BANK) == FSMC_Bank3_NAND) || \ ((BANK) == FSMC_Bank4_PCCARD)) #define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ ((BANK) == FSMC_Bank3_NAND) || \ ((BANK) == FSMC_Bank4_PCCARD)) /** @defgroup NOR_SRAM_Controller * @{ */ /** @defgroup FSMC_Data_Address_Bus_Multiplexing * @{ */ #define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) #define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) #define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ ((MUX) == FSMC_DataAddressMux_Enable)) /** * @} */ /** @defgroup FSMC_Memory_Type * @{ */ #define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) #define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) #define FSMC_MemoryType_NOR ((uint32_t)0x00000008) #define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ ((MEMORY) == FSMC_MemoryType_NOR)) /** * @} */ /** @defgroup FSMC_Data_Width * @{ */ #define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) #define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) #define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ ((WIDTH) == FSMC_MemoryDataWidth_16b)) /** * @} */ /** @defgroup FSMC_Burst_Access_Mode * @{ */ #define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) #define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) #define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ ((STATE) == FSMC_BurstAccessMode_Enable)) /** * @} */ /** @defgroup FSMC_AsynchronousWait * @{ */ #define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000) #define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000) #define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \ ((STATE) == FSMC_AsynchronousWait_Enable)) /** * @} */ /** @defgroup FSMC_Wait_Signal_Polarity * @{ */ #define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) #define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) #define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ ((POLARITY) == FSMC_WaitSignalPolarity_High)) /** * @} */ /** @defgroup FSMC_Wrap_Mode * @{ */ #define FSMC_WrapMode_Disable ((uint32_t)0x00000000) #define FSMC_WrapMode_Enable ((uint32_t)0x00000400) #define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ ((MODE) == FSMC_WrapMode_Enable)) /** * @} */ /** @defgroup FSMC_Wait_Timing * @{ */ #define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) #define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) #define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) /** * @} */ /** @defgroup FSMC_Write_Operation * @{ */ #define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) #define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) #define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ ((OPERATION) == FSMC_WriteOperation_Enable)) /** * @} */ /** @defgroup FSMC_Wait_Signal * @{ */ #define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) #define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) #define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ ((SIGNAL) == FSMC_WaitSignal_Enable)) /** * @} */ /** @defgroup FSMC_Extended_Mode * @{ */ #define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) #define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) #define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ ((MODE) == FSMC_ExtendedMode_Enable)) /** * @} */ /** @defgroup FSMC_Write_Burst * @{ */ #define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) #define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) #define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ ((BURST) == FSMC_WriteBurst_Enable)) /** * @} */ /** @defgroup FSMC_Address_Setup_Time * @{ */ #define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) /** * @} */ /** @defgroup FSMC_Address_Hold_Time * @{ */ #define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) /** * @} */ /** @defgroup FSMC_Data_Setup_Time * @{ */ #define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) /** * @} */ /** @defgroup FSMC_Bus_Turn_around_Duration * @{ */ #define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) /** * @} */ /** @defgroup FSMC_CLK_Division * @{ */ #define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) /** * @} */ /** @defgroup FSMC_Data_Latency * @{ */ #define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) /** * @} */ /** @defgroup FSMC_Access_Mode * @{ */ #define FSMC_AccessMode_A ((uint32_t)0x00000000) #define FSMC_AccessMode_B ((uint32_t)0x10000000) #define FSMC_AccessMode_C ((uint32_t)0x20000000) #define FSMC_AccessMode_D ((uint32_t)0x30000000) #define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ ((MODE) == FSMC_AccessMode_B) || \ ((MODE) == FSMC_AccessMode_C) || \ ((MODE) == FSMC_AccessMode_D)) /** * @} */ /** * @} */ /** @defgroup NAND_PCCARD_Controller * @{ */ /** @defgroup FSMC_Wait_feature * @{ */ #define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) #define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ ((FEATURE) == FSMC_Waitfeature_Enable)) /** * @} */ /** @defgroup FSMC_ECC * @{ */ #define FSMC_ECC_Disable ((uint32_t)0x00000000) #define FSMC_ECC_Enable ((uint32_t)0x00000040) #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ ((STATE) == FSMC_ECC_Enable)) /** * @} */ /** @defgroup FSMC_ECC_Page_Size * @{ */ #define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) #define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) #define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) #define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) #define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) #define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ ((SIZE) == FSMC_ECCPageSize_512Bytes) || \ ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ ((SIZE) == FSMC_ECCPageSize_8192Bytes)) /** * @} */ /** @defgroup FSMC_TCLR_Setup_Time * @{ */ #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) /** * @} */ /** @defgroup FSMC_TAR_Setup_Time * @{ */ #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) /** * @} */ /** @defgroup FSMC_Setup_Time * @{ */ #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) /** * @} */ /** @defgroup FSMC_Wait_Setup_Time * @{ */ #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) /** * @} */ /** @defgroup FSMC_Hold_Setup_Time * @{ */ #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) /** * @} */ /** @defgroup FSMC_HiZ_Setup_Time * @{ */ #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) /** * @} */ /** @defgroup FSMC_Interrupt_sources * @{ */ #define FSMC_IT_RisingEdge ((uint32_t)0x00000008) #define FSMC_IT_Level ((uint32_t)0x00000010) #define FSMC_IT_FallingEdge ((uint32_t)0x00000020) #define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) #define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ ((IT) == FSMC_IT_Level) || \ ((IT) == FSMC_IT_FallingEdge)) /** * @} */ /** @defgroup FSMC_Flags * @{ */ #define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) #define FSMC_FLAG_Level ((uint32_t)0x00000002) #define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) #define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) #define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ ((FLAG) == FSMC_FLAG_Level) || \ ((FLAG) == FSMC_FLAG_FallingEdge) || \ ((FLAG) == FSMC_FLAG_FEMPT)) #define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) /** * @} */ /** * @} */ /** * @} */ /** @defgroup FSMC_Exported_Macros * @{ */ /** * @} */ /** @defgroup FSMC_Exported_Functions * @{ */ void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); void FSMC_NANDDeInit(uint32_t FSMC_Bank); void FSMC_PCCARDDeInit(void); void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); void FSMC_PCCARDCmd(FunctionalState NewState); void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); uint32_t FSMC_GetECC(uint32_t FSMC_Bank); void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); #ifdef __cplusplus } #endif #endif /*__STM32F10x_FSMC_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /** ****************************************************************************** * @file stm32f10x_fsmc.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the FSMC firmware * library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_FSMC_H #define __STM32F10x_FSMC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup FSMC * @{ */ /** @defgroup FSMC_Exported_Types * @{ */ /** * @brief Timing parameters For NOR/SRAM Banks */ typedef struct { uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure the duration of the address setup time. This parameter can be a value between 0 and 0xF. @note: It is not used with synchronous NOR Flash memories. */ uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure the duration of the address hold time. This parameter can be a value between 0 and 0xF. @note: It is not used with synchronous NOR Flash memories.*/ uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure the duration of the data setup time. This parameter can be a value between 0 and 0xFF. @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure the duration of the bus turnaround. This parameter can be a value between 0 and 0xF. @note: It is only used for multiplexed NOR Flash memories. */ uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. This parameter can be a value between 1 and 0xF. @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue to the memory before getting the first data. The value of this parameter depends on the memory type as shown below: - It must be set to 0 in case of a CRAM - It is don't care in asynchronous NOR, SRAM or ROM accesses - It may assume a value between 0 and 0xF in NOR Flash memories with synchronous burst mode enable */ uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. This parameter can be a value of @ref FSMC_Access_Mode */ }FSMC_NORSRAMTimingInitTypeDef; /** * @brief FSMC NOR/SRAM Init structure definition */ typedef struct { uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. This parameter can be a value of @ref FSMC_NORSRAM_Bank */ uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are multiplexed on the databus or not. This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to the corresponding memory bank. This parameter can be a value of @ref FSMC_Memory_Type */ uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. This parameter can be a value of @ref FSMC_Data_Width */ uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, valid only with synchronous burst Flash memories. This parameter can be a value of @ref FSMC_Burst_Access_Mode */ uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, valid only with asynchronous Flash memories. This parameter can be a value of @ref FSMC_AsynchronousWait */ uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing the Flash memory in burst mode. This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash memory, valid only when accessing Flash memories in burst mode. This parameter can be a value of @ref FSMC_Wrap_Mode */ uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one clock cycle before the wait state or during the wait state, valid only when accessing memories in burst mode. This parameter can be a value of @ref FSMC_Wait_Timing */ uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. This parameter can be a value of @ref FSMC_Write_Operation */ uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait signal, valid for Flash memory access in burst mode. This parameter can be a value of @ref FSMC_Wait_Signal */ uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode. This parameter can be a value of @ref FSMC_Extended_Mode */ uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation. This parameter can be a value of @ref FSMC_Write_Burst */ FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ }FSMC_NORSRAMInitTypeDef; /** * @brief Timing parameters For FSMC NAND and PCCARD Banks */ typedef struct { uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before the command assertion for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a value between 0 and 0xFF.*/ uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the command for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between 0x00 and 0xFF */ uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address (and data for write access) after the command deassertion for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between 0x00 and 0xFF */ uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the start of a NAND-Flash write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between 0x00 and 0xFF */ }FSMC_NAND_PCCARDTimingInitTypeDef; /** * @brief FSMC NAND Init structure definition */ typedef struct { uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used. This parameter can be a value of @ref FSMC_NAND_Bank */ uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. This parameter can be any value of @ref FSMC_Wait_feature */ uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. This parameter can be any value of @ref FSMC_Data_Width */ uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation. This parameter can be any value of @ref FSMC_ECC */ uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC. This parameter can be any value of @ref FSMC_ECC_Page_Size */ uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between CLE low and RE low. This parameter can be a value between 0 and 0xFF. */ uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between 0x0 and 0xFF */ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ }FSMC_NANDInitTypeDef; /** * @brief FSMC PCCARD Init structure definition */ typedef struct { uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. This parameter can be any value of @ref FSMC_Wait_feature */ uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between CLE low and RE low. This parameter can be a value between 0 and 0xFF. */ uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between 0x0 and 0xFF */ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ }FSMC_PCCARDInitTypeDef; /** * @} */ /** @defgroup FSMC_Exported_Constants * @{ */ /** @defgroup FSMC_NORSRAM_Bank * @{ */ #define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) #define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) #define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) #define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) /** * @} */ /** @defgroup FSMC_NAND_Bank * @{ */ #define FSMC_Bank2_NAND ((uint32_t)0x00000010) #define FSMC_Bank3_NAND ((uint32_t)0x00000100) /** * @} */ /** @defgroup FSMC_PCCARD_Bank * @{ */ #define FSMC_Bank4_PCCARD ((uint32_t)0x00001000) /** * @} */ #define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ ((BANK) == FSMC_Bank1_NORSRAM2) || \ ((BANK) == FSMC_Bank1_NORSRAM3) || \ ((BANK) == FSMC_Bank1_NORSRAM4)) #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ ((BANK) == FSMC_Bank3_NAND)) #define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ ((BANK) == FSMC_Bank3_NAND) || \ ((BANK) == FSMC_Bank4_PCCARD)) #define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ ((BANK) == FSMC_Bank3_NAND) || \ ((BANK) == FSMC_Bank4_PCCARD)) /** @defgroup NOR_SRAM_Controller * @{ */ /** @defgroup FSMC_Data_Address_Bus_Multiplexing * @{ */ #define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) #define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) #define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ ((MUX) == FSMC_DataAddressMux_Enable)) /** * @} */ /** @defgroup FSMC_Memory_Type * @{ */ #define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) #define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) #define FSMC_MemoryType_NOR ((uint32_t)0x00000008) #define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ ((MEMORY) == FSMC_MemoryType_NOR)) /** * @} */ /** @defgroup FSMC_Data_Width * @{ */ #define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) #define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) #define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ ((WIDTH) == FSMC_MemoryDataWidth_16b)) /** * @} */ /** @defgroup FSMC_Burst_Access_Mode * @{ */ #define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) #define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) #define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ ((STATE) == FSMC_BurstAccessMode_Enable)) /** * @} */ /** @defgroup FSMC_AsynchronousWait * @{ */ #define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000) #define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000) #define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \ ((STATE) == FSMC_AsynchronousWait_Enable)) /** * @} */ /** @defgroup FSMC_Wait_Signal_Polarity * @{ */ #define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) #define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) #define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ ((POLARITY) == FSMC_WaitSignalPolarity_High)) /** * @} */ /** @defgroup FSMC_Wrap_Mode * @{ */ #define FSMC_WrapMode_Disable ((uint32_t)0x00000000) #define FSMC_WrapMode_Enable ((uint32_t)0x00000400) #define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ ((MODE) == FSMC_WrapMode_Enable)) /** * @} */ /** @defgroup FSMC_Wait_Timing * @{ */ #define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) #define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) #define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) /** * @} */ /** @defgroup FSMC_Write_Operation * @{ */ #define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) #define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) #define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ ((OPERATION) == FSMC_WriteOperation_Enable)) /** * @} */ /** @defgroup FSMC_Wait_Signal * @{ */ #define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) #define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) #define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ ((SIGNAL) == FSMC_WaitSignal_Enable)) /** * @} */ /** @defgroup FSMC_Extended_Mode * @{ */ #define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) #define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) #define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ ((MODE) == FSMC_ExtendedMode_Enable)) /** * @} */ /** @defgroup FSMC_Write_Burst * @{ */ #define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) #define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) #define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ ((BURST) == FSMC_WriteBurst_Enable)) /** * @} */ /** @defgroup FSMC_Address_Setup_Time * @{ */ #define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) /** * @} */ /** @defgroup FSMC_Address_Hold_Time * @{ */ #define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) /** * @} */ /** @defgroup FSMC_Data_Setup_Time * @{ */ #define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) /** * @} */ /** @defgroup FSMC_Bus_Turn_around_Duration * @{ */ #define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) /** * @} */ /** @defgroup FSMC_CLK_Division * @{ */ #define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) /** * @} */ /** @defgroup FSMC_Data_Latency * @{ */ #define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) /** * @} */ /** @defgroup FSMC_Access_Mode * @{ */ #define FSMC_AccessMode_A ((uint32_t)0x00000000) #define FSMC_AccessMode_B ((uint32_t)0x10000000) #define FSMC_AccessMode_C ((uint32_t)0x20000000) #define FSMC_AccessMode_D ((uint32_t)0x30000000) #define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ ((MODE) == FSMC_AccessMode_B) || \ ((MODE) == FSMC_AccessMode_C) || \ ((MODE) == FSMC_AccessMode_D)) /** * @} */ /** * @} */ /** @defgroup NAND_PCCARD_Controller * @{ */ /** @defgroup FSMC_Wait_feature * @{ */ #define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) #define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ ((FEATURE) == FSMC_Waitfeature_Enable)) /** * @} */ /** @defgroup FSMC_ECC * @{ */ #define FSMC_ECC_Disable ((uint32_t)0x00000000) #define FSMC_ECC_Enable ((uint32_t)0x00000040) #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ ((STATE) == FSMC_ECC_Enable)) /** * @} */ /** @defgroup FSMC_ECC_Page_Size * @{ */ #define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) #define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) #define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) #define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) #define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) #define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ ((SIZE) == FSMC_ECCPageSize_512Bytes) || \ ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ ((SIZE) == FSMC_ECCPageSize_8192Bytes)) /** * @} */ /** @defgroup FSMC_TCLR_Setup_Time * @{ */ #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) /** * @} */ /** @defgroup FSMC_TAR_Setup_Time * @{ */ #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) /** * @} */ /** @defgroup FSMC_Setup_Time * @{ */ #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) /** * @} */ /** @defgroup FSMC_Wait_Setup_Time * @{ */ #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) /** * @} */ /** @defgroup FSMC_Hold_Setup_Time * @{ */ #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) /** * @} */ /** @defgroup FSMC_HiZ_Setup_Time * @{ */ #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) /** * @} */ /** @defgroup FSMC_Interrupt_sources * @{ */ #define FSMC_IT_RisingEdge ((uint32_t)0x00000008) #define FSMC_IT_Level ((uint32_t)0x00000010) #define FSMC_IT_FallingEdge ((uint32_t)0x00000020) #define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) #define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ ((IT) == FSMC_IT_Level) || \ ((IT) == FSMC_IT_FallingEdge)) /** * @} */ /** @defgroup FSMC_Flags * @{ */ #define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) #define FSMC_FLAG_Level ((uint32_t)0x00000002) #define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) #define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) #define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ ((FLAG) == FSMC_FLAG_Level) || \ ((FLAG) == FSMC_FLAG_FallingEdge) || \ ((FLAG) == FSMC_FLAG_FEMPT)) #define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) /** * @} */ /** * @} */ /** * @} */ /** @defgroup FSMC_Exported_Macros * @{ */ /** * @} */ /** @defgroup FSMC_Exported_Functions * @{ */ void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); void FSMC_NANDDeInit(uint32_t FSMC_Bank); void FSMC_PCCARDDeInit(void); void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); void FSMC_PCCARDCmd(FunctionalState NewState); void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); uint32_t FSMC_GetECC(uint32_t FSMC_Bank); void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); #ifdef __cplusplus } #endif #endif /*__STM32F10x_FSMC_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ src/bare_test/1.Led/stdlib/inc/stm32f10x_gpio.h
File was renamed from src/bare_test/stm32_key/fwlib/inc/stm32f10x_gpio.h @@ -1,385 +1,385 @@ /** ****************************************************************************** * @file stm32f10x_gpio.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the GPIO * firmware library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_GPIO_H #define __STM32F10x_GPIO_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup GPIO * @{ */ /** @defgroup GPIO_Exported_Types * @{ */ #define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ ((PERIPH) == GPIOB) || \ ((PERIPH) == GPIOC) || \ ((PERIPH) == GPIOD) || \ ((PERIPH) == GPIOE) || \ ((PERIPH) == GPIOF) || \ ((PERIPH) == GPIOG)) /** * @brief Output Maximum frequency selection */ typedef enum { GPIO_Speed_10MHz = 1, GPIO_Speed_2MHz, GPIO_Speed_50MHz }GPIOSpeed_TypeDef; #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \ ((SPEED) == GPIO_Speed_50MHz)) /** * @brief Configuration Mode enumeration */ typedef enum { GPIO_Mode_AIN = 0x0, GPIO_Mode_IN_FLOATING = 0x04, GPIO_Mode_IPD = 0x28, GPIO_Mode_IPU = 0x48, GPIO_Mode_Out_OD = 0x14, GPIO_Mode_Out_PP = 0x10, GPIO_Mode_AF_OD = 0x1C, GPIO_Mode_AF_PP = 0x18 }GPIOMode_TypeDef; #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \ ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \ ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \ ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP)) /** * @brief GPIO Init structure definition */ typedef struct { uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. This parameter can be any value of @ref GPIO_pins_define */ GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. This parameter can be a value of @ref GPIOSpeed_TypeDef */ GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. This parameter can be a value of @ref GPIOMode_TypeDef */ }GPIO_InitTypeDef; /** * @brief Bit_SET and Bit_RESET enumeration */ typedef enum { Bit_RESET = 0, Bit_SET }BitAction; #define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) /** * @} */ /** @defgroup GPIO_Exported_Constants * @{ */ /** @defgroup GPIO_pins_define * @{ */ #define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ #define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ #define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ #define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ #define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ #define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ #define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ #define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ #define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ #define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ #define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ #define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ #define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ #define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ #define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ #define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ #define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */ #define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) #define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ ((PIN) == GPIO_Pin_1) || \ ((PIN) == GPIO_Pin_2) || \ ((PIN) == GPIO_Pin_3) || \ ((PIN) == GPIO_Pin_4) || \ ((PIN) == GPIO_Pin_5) || \ ((PIN) == GPIO_Pin_6) || \ ((PIN) == GPIO_Pin_7) || \ ((PIN) == GPIO_Pin_8) || \ ((PIN) == GPIO_Pin_9) || \ ((PIN) == GPIO_Pin_10) || \ ((PIN) == GPIO_Pin_11) || \ ((PIN) == GPIO_Pin_12) || \ ((PIN) == GPIO_Pin_13) || \ ((PIN) == GPIO_Pin_14) || \ ((PIN) == GPIO_Pin_15)) /** * @} */ /** @defgroup GPIO_Remap_define * @{ */ #define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */ #define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */ #define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */ #define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */ #define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */ #define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */ #define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */ #define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */ #define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */ #define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */ #define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */ #define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */ #define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */ #define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */ #define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */ #define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */ #define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */ #define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */ #define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */ #define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */ #define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */ #define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */ #define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */ #define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */ #define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */ #define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */ #define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */ #define GPIO_Remap_SPI3 ((uint32_t)0x00201100) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */ #define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices) */ #define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */ #define GPIO_Remap_TIM15 ((uint32_t)0x80000001) /*!< TIM15 Alternate Function mapping (only for Value line devices) */ #define GPIO_Remap_TIM16 ((uint32_t)0x80000002) /*!< TIM16 Alternate Function mapping (only for Value line devices) */ #define GPIO_Remap_TIM17 ((uint32_t)0x80000004) /*!< TIM17 Alternate Function mapping (only for Value line devices) */ #define GPIO_Remap_CEC ((uint32_t)0x80000008) /*!< CEC Alternate Function mapping (only for Value line devices) */ #define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /*!< TIM1 DMA requests mapping (only for Value line devices) */ #define GPIO_Remap_TIM9 ((uint32_t)0x80000020) /*!< TIM9 Alternate Function mapping (only for XL-density devices) */ #define GPIO_Remap_TIM10 ((uint32_t)0x80000040) /*!< TIM10 Alternate Function mapping (only for XL-density devices) */ #define GPIO_Remap_TIM11 ((uint32_t)0x80000080) /*!< TIM11 Alternate Function mapping (only for XL-density devices) */ #define GPIO_Remap_TIM13 ((uint32_t)0x80000100) /*!< TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) */ #define GPIO_Remap_TIM14 ((uint32_t)0x80000200) /*!< TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) */ #define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /*!< FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) */ #define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) /*!< TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */ #define GPIO_Remap_TIM12 ((uint32_t)0x80001000) /*!< TIM12 Alternate Function mapping (only for High density Value line devices) */ #define GPIO_Remap_MISC ((uint32_t)0x80002000) /*!< Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, only for High density Value line devices) */ #define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \ ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \ ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \ ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \ ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \ ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \ ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \ ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \ ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \ ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \ ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \ ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \ ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \ ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \ ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \ ((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \ ((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \ ((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \ ((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \ ((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \ ((REMAP) == GPIO_Remap_FSMC_NADV) || ((REMAP) == GPIO_Remap_TIM67_DAC_DMA) || \ ((REMAP) == GPIO_Remap_TIM12) || ((REMAP) == GPIO_Remap_MISC)) /** * @} */ /** @defgroup GPIO_Port_Sources * @{ */ #define GPIO_PortSourceGPIOA ((uint8_t)0x00) #define GPIO_PortSourceGPIOB ((uint8_t)0x01) #define GPIO_PortSourceGPIOC ((uint8_t)0x02) #define GPIO_PortSourceGPIOD ((uint8_t)0x03) #define GPIO_PortSourceGPIOE ((uint8_t)0x04) #define GPIO_PortSourceGPIOF ((uint8_t)0x05) #define GPIO_PortSourceGPIOG ((uint8_t)0x06) #define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ ((PORTSOURCE) == GPIO_PortSourceGPIOE)) #define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \ ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \ ((PORTSOURCE) == GPIO_PortSourceGPIOG)) /** * @} */ /** @defgroup GPIO_Pin_sources * @{ */ #define GPIO_PinSource0 ((uint8_t)0x00) #define GPIO_PinSource1 ((uint8_t)0x01) #define GPIO_PinSource2 ((uint8_t)0x02) #define GPIO_PinSource3 ((uint8_t)0x03) #define GPIO_PinSource4 ((uint8_t)0x04) #define GPIO_PinSource5 ((uint8_t)0x05) #define GPIO_PinSource6 ((uint8_t)0x06) #define GPIO_PinSource7 ((uint8_t)0x07) #define GPIO_PinSource8 ((uint8_t)0x08) #define GPIO_PinSource9 ((uint8_t)0x09) #define GPIO_PinSource10 ((uint8_t)0x0A) #define GPIO_PinSource11 ((uint8_t)0x0B) #define GPIO_PinSource12 ((uint8_t)0x0C) #define GPIO_PinSource13 ((uint8_t)0x0D) #define GPIO_PinSource14 ((uint8_t)0x0E) #define GPIO_PinSource15 ((uint8_t)0x0F) #define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ ((PINSOURCE) == GPIO_PinSource1) || \ ((PINSOURCE) == GPIO_PinSource2) || \ ((PINSOURCE) == GPIO_PinSource3) || \ ((PINSOURCE) == GPIO_PinSource4) || \ ((PINSOURCE) == GPIO_PinSource5) || \ ((PINSOURCE) == GPIO_PinSource6) || \ ((PINSOURCE) == GPIO_PinSource7) || \ ((PINSOURCE) == GPIO_PinSource8) || \ ((PINSOURCE) == GPIO_PinSource9) || \ ((PINSOURCE) == GPIO_PinSource10) || \ ((PINSOURCE) == GPIO_PinSource11) || \ ((PINSOURCE) == GPIO_PinSource12) || \ ((PINSOURCE) == GPIO_PinSource13) || \ ((PINSOURCE) == GPIO_PinSource14) || \ ((PINSOURCE) == GPIO_PinSource15)) /** * @} */ /** @defgroup Ethernet_Media_Interface * @{ */ #define GPIO_ETH_MediaInterface_MII ((u32)0x00000000) #define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001) #define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \ ((INTERFACE) == GPIO_ETH_MediaInterface_RMII)) /** * @} */ /** * @} */ /** @defgroup GPIO_Exported_Macros * @{ */ /** * @} */ /** @defgroup GPIO_Exported_Functions * @{ */ void GPIO_DeInit(GPIO_TypeDef* GPIOx); void GPIO_AFIODeInit(void); void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); void GPIO_EventOutputCmd(FunctionalState NewState); void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface); #ifdef __cplusplus } #endif #endif /* __STM32F10x_GPIO_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /** ****************************************************************************** * @file stm32f10x_gpio.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the GPIO * firmware library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_GPIO_H #define __STM32F10x_GPIO_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup GPIO * @{ */ /** @defgroup GPIO_Exported_Types * @{ */ #define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ ((PERIPH) == GPIOB) || \ ((PERIPH) == GPIOC) || \ ((PERIPH) == GPIOD) || \ ((PERIPH) == GPIOE) || \ ((PERIPH) == GPIOF) || \ ((PERIPH) == GPIOG)) /** * @brief Output Maximum frequency selection */ typedef enum { GPIO_Speed_10MHz = 1, GPIO_Speed_2MHz, GPIO_Speed_50MHz }GPIOSpeed_TypeDef; #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \ ((SPEED) == GPIO_Speed_50MHz)) /** * @brief Configuration Mode enumeration */ typedef enum { GPIO_Mode_AIN = 0x0, GPIO_Mode_IN_FLOATING = 0x04, GPIO_Mode_IPD = 0x28, GPIO_Mode_IPU = 0x48, GPIO_Mode_Out_OD = 0x14, GPIO_Mode_Out_PP = 0x10, GPIO_Mode_AF_OD = 0x1C, GPIO_Mode_AF_PP = 0x18 }GPIOMode_TypeDef; #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \ ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \ ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \ ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP)) /** * @brief GPIO Init structure definition */ typedef struct { uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. This parameter can be any value of @ref GPIO_pins_define */ GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. This parameter can be a value of @ref GPIOSpeed_TypeDef */ GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. This parameter can be a value of @ref GPIOMode_TypeDef */ }GPIO_InitTypeDef; /** * @brief Bit_SET and Bit_RESET enumeration */ typedef enum { Bit_RESET = 0, Bit_SET }BitAction; #define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) /** * @} */ /** @defgroup GPIO_Exported_Constants * @{ */ /** @defgroup GPIO_pins_define * @{ */ #define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ #define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ #define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ #define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ #define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ #define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ #define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ #define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ #define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ #define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ #define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ #define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ #define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ #define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ #define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ #define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ #define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */ #define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) #define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ ((PIN) == GPIO_Pin_1) || \ ((PIN) == GPIO_Pin_2) || \ ((PIN) == GPIO_Pin_3) || \ ((PIN) == GPIO_Pin_4) || \ ((PIN) == GPIO_Pin_5) || \ ((PIN) == GPIO_Pin_6) || \ ((PIN) == GPIO_Pin_7) || \ ((PIN) == GPIO_Pin_8) || \ ((PIN) == GPIO_Pin_9) || \ ((PIN) == GPIO_Pin_10) || \ ((PIN) == GPIO_Pin_11) || \ ((PIN) == GPIO_Pin_12) || \ ((PIN) == GPIO_Pin_13) || \ ((PIN) == GPIO_Pin_14) || \ ((PIN) == GPIO_Pin_15)) /** * @} */ /** @defgroup GPIO_Remap_define * @{ */ #define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */ #define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */ #define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */ #define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */ #define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */ #define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */ #define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */ #define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */ #define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */ #define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */ #define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */ #define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */ #define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */ #define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */ #define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */ #define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */ #define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */ #define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */ #define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */ #define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */ #define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */ #define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */ #define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */ #define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */ #define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */ #define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */ #define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */ #define GPIO_Remap_SPI3 ((uint32_t)0x00201100) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */ #define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices) */ #define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */ #define GPIO_Remap_TIM15 ((uint32_t)0x80000001) /*!< TIM15 Alternate Function mapping (only for Value line devices) */ #define GPIO_Remap_TIM16 ((uint32_t)0x80000002) /*!< TIM16 Alternate Function mapping (only for Value line devices) */ #define GPIO_Remap_TIM17 ((uint32_t)0x80000004) /*!< TIM17 Alternate Function mapping (only for Value line devices) */ #define GPIO_Remap_CEC ((uint32_t)0x80000008) /*!< CEC Alternate Function mapping (only for Value line devices) */ #define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /*!< TIM1 DMA requests mapping (only for Value line devices) */ #define GPIO_Remap_TIM9 ((uint32_t)0x80000020) /*!< TIM9 Alternate Function mapping (only for XL-density devices) */ #define GPIO_Remap_TIM10 ((uint32_t)0x80000040) /*!< TIM10 Alternate Function mapping (only for XL-density devices) */ #define GPIO_Remap_TIM11 ((uint32_t)0x80000080) /*!< TIM11 Alternate Function mapping (only for XL-density devices) */ #define GPIO_Remap_TIM13 ((uint32_t)0x80000100) /*!< TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) */ #define GPIO_Remap_TIM14 ((uint32_t)0x80000200) /*!< TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) */ #define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /*!< FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) */ #define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) /*!< TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */ #define GPIO_Remap_TIM12 ((uint32_t)0x80001000) /*!< TIM12 Alternate Function mapping (only for High density Value line devices) */ #define GPIO_Remap_MISC ((uint32_t)0x80002000) /*!< Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, only for High density Value line devices) */ #define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \ ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \ ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \ ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \ ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \ ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \ ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \ ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \ ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \ ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \ ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \ ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \ ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \ ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \ ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \ ((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \ ((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \ ((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \ ((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \ ((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \ ((REMAP) == GPIO_Remap_FSMC_NADV) || ((REMAP) == GPIO_Remap_TIM67_DAC_DMA) || \ ((REMAP) == GPIO_Remap_TIM12) || ((REMAP) == GPIO_Remap_MISC)) /** * @} */ /** @defgroup GPIO_Port_Sources * @{ */ #define GPIO_PortSourceGPIOA ((uint8_t)0x00) #define GPIO_PortSourceGPIOB ((uint8_t)0x01) #define GPIO_PortSourceGPIOC ((uint8_t)0x02) #define GPIO_PortSourceGPIOD ((uint8_t)0x03) #define GPIO_PortSourceGPIOE ((uint8_t)0x04) #define GPIO_PortSourceGPIOF ((uint8_t)0x05) #define GPIO_PortSourceGPIOG ((uint8_t)0x06) #define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ ((PORTSOURCE) == GPIO_PortSourceGPIOE)) #define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \ ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \ ((PORTSOURCE) == GPIO_PortSourceGPIOG)) /** * @} */ /** @defgroup GPIO_Pin_sources * @{ */ #define GPIO_PinSource0 ((uint8_t)0x00) #define GPIO_PinSource1 ((uint8_t)0x01) #define GPIO_PinSource2 ((uint8_t)0x02) #define GPIO_PinSource3 ((uint8_t)0x03) #define GPIO_PinSource4 ((uint8_t)0x04) #define GPIO_PinSource5 ((uint8_t)0x05) #define GPIO_PinSource6 ((uint8_t)0x06) #define GPIO_PinSource7 ((uint8_t)0x07) #define GPIO_PinSource8 ((uint8_t)0x08) #define GPIO_PinSource9 ((uint8_t)0x09) #define GPIO_PinSource10 ((uint8_t)0x0A) #define GPIO_PinSource11 ((uint8_t)0x0B) #define GPIO_PinSource12 ((uint8_t)0x0C) #define GPIO_PinSource13 ((uint8_t)0x0D) #define GPIO_PinSource14 ((uint8_t)0x0E) #define GPIO_PinSource15 ((uint8_t)0x0F) #define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ ((PINSOURCE) == GPIO_PinSource1) || \ ((PINSOURCE) == GPIO_PinSource2) || \ ((PINSOURCE) == GPIO_PinSource3) || \ ((PINSOURCE) == GPIO_PinSource4) || \ ((PINSOURCE) == GPIO_PinSource5) || \ ((PINSOURCE) == GPIO_PinSource6) || \ ((PINSOURCE) == GPIO_PinSource7) || \ ((PINSOURCE) == GPIO_PinSource8) || \ ((PINSOURCE) == GPIO_PinSource9) || \ ((PINSOURCE) == GPIO_PinSource10) || \ ((PINSOURCE) == GPIO_PinSource11) || \ ((PINSOURCE) == GPIO_PinSource12) || \ ((PINSOURCE) == GPIO_PinSource13) || \ ((PINSOURCE) == GPIO_PinSource14) || \ ((PINSOURCE) == GPIO_PinSource15)) /** * @} */ /** @defgroup Ethernet_Media_Interface * @{ */ #define GPIO_ETH_MediaInterface_MII ((u32)0x00000000) #define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001) #define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \ ((INTERFACE) == GPIO_ETH_MediaInterface_RMII)) /** * @} */ /** * @} */ /** @defgroup GPIO_Exported_Macros * @{ */ /** * @} */ /** @defgroup GPIO_Exported_Functions * @{ */ void GPIO_DeInit(GPIO_TypeDef* GPIOx); void GPIO_AFIODeInit(void); void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); void GPIO_EventOutputCmd(FunctionalState NewState); void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface); #ifdef __cplusplus } #endif #endif /* __STM32F10x_GPIO_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ src/bare_test/1.Led/stdlib/inc/stm32f10x_i2c.h
File was renamed from src/bare_test/stm32_key/fwlib/inc/stm32f10x_i2c.h @@ -1,684 +1,684 @@ /** ****************************************************************************** * @file stm32f10x_i2c.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the I2C firmware * library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_I2C_H #define __STM32F10x_I2C_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup I2C * @{ */ /** @defgroup I2C_Exported_Types * @{ */ /** * @brief I2C Init structure definition */ typedef struct { uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency. This parameter must be set to a value lower than 400kHz */ uint16_t I2C_Mode; /*!< Specifies the I2C mode. This parameter can be a value of @ref I2C_mode */ uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle. This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address. This parameter can be a 7-bit or 10-bit address. */ uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement. This parameter can be a value of @ref I2C_acknowledgement */ uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. This parameter can be a value of @ref I2C_acknowledged_address */ }I2C_InitTypeDef; /** * @} */ /** @defgroup I2C_Exported_Constants * @{ */ #define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ ((PERIPH) == I2C2)) /** @defgroup I2C_mode * @{ */ #define I2C_Mode_I2C ((uint16_t)0x0000) #define I2C_Mode_SMBusDevice ((uint16_t)0x0002) #define I2C_Mode_SMBusHost ((uint16_t)0x000A) #define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ ((MODE) == I2C_Mode_SMBusDevice) || \ ((MODE) == I2C_Mode_SMBusHost)) /** * @} */ /** @defgroup I2C_duty_cycle_in_fast_mode * @{ */ #define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ #define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ #define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \ ((CYCLE) == I2C_DutyCycle_2)) /** * @} */ /** @defgroup I2C_acknowledgement * @{ */ #define I2C_Ack_Enable ((uint16_t)0x0400) #define I2C_Ack_Disable ((uint16_t)0x0000) #define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \ ((STATE) == I2C_Ack_Disable)) /** * @} */ /** @defgroup I2C_transfer_direction * @{ */ #define I2C_Direction_Transmitter ((uint8_t)0x00) #define I2C_Direction_Receiver ((uint8_t)0x01) #define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ ((DIRECTION) == I2C_Direction_Receiver)) /** * @} */ /** @defgroup I2C_acknowledged_address * @{ */ #define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) #define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) #define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) /** * @} */ /** @defgroup I2C_registers * @{ */ #define I2C_Register_CR1 ((uint8_t)0x00) #define I2C_Register_CR2 ((uint8_t)0x04) #define I2C_Register_OAR1 ((uint8_t)0x08) #define I2C_Register_OAR2 ((uint8_t)0x0C) #define I2C_Register_DR ((uint8_t)0x10) #define I2C_Register_SR1 ((uint8_t)0x14) #define I2C_Register_SR2 ((uint8_t)0x18) #define I2C_Register_CCR ((uint8_t)0x1C) #define I2C_Register_TRISE ((uint8_t)0x20) #define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ ((REGISTER) == I2C_Register_CR2) || \ ((REGISTER) == I2C_Register_OAR1) || \ ((REGISTER) == I2C_Register_OAR2) || \ ((REGISTER) == I2C_Register_DR) || \ ((REGISTER) == I2C_Register_SR1) || \ ((REGISTER) == I2C_Register_SR2) || \ ((REGISTER) == I2C_Register_CCR) || \ ((REGISTER) == I2C_Register_TRISE)) /** * @} */ /** @defgroup I2C_SMBus_alert_pin_level * @{ */ #define I2C_SMBusAlert_Low ((uint16_t)0x2000) #define I2C_SMBusAlert_High ((uint16_t)0xDFFF) #define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \ ((ALERT) == I2C_SMBusAlert_High)) /** * @} */ /** @defgroup I2C_PEC_position * @{ */ #define I2C_PECPosition_Next ((uint16_t)0x0800) #define I2C_PECPosition_Current ((uint16_t)0xF7FF) #define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \ ((POSITION) == I2C_PECPosition_Current)) /** * @} */ /** @defgroup I2C_NCAK_position * @{ */ #define I2C_NACKPosition_Next ((uint16_t)0x0800) #define I2C_NACKPosition_Current ((uint16_t)0xF7FF) #define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \ ((POSITION) == I2C_NACKPosition_Current)) /** * @} */ /** @defgroup I2C_interrupts_definition * @{ */ #define I2C_IT_BUF ((uint16_t)0x0400) #define I2C_IT_EVT ((uint16_t)0x0200) #define I2C_IT_ERR ((uint16_t)0x0100) #define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) /** * @} */ /** @defgroup I2C_interrupts_definition * @{ */ #define I2C_IT_SMBALERT ((uint32_t)0x01008000) #define I2C_IT_TIMEOUT ((uint32_t)0x01004000) #define I2C_IT_PECERR ((uint32_t)0x01001000) #define I2C_IT_OVR ((uint32_t)0x01000800) #define I2C_IT_AF ((uint32_t)0x01000400) #define I2C_IT_ARLO ((uint32_t)0x01000200) #define I2C_IT_BERR ((uint32_t)0x01000100) #define I2C_IT_TXE ((uint32_t)0x06000080) #define I2C_IT_RXNE ((uint32_t)0x06000040) #define I2C_IT_STOPF ((uint32_t)0x02000010) #define I2C_IT_ADD10 ((uint32_t)0x02000008) #define I2C_IT_BTF ((uint32_t)0x02000004) #define I2C_IT_ADDR ((uint32_t)0x02000002) #define I2C_IT_SB ((uint32_t)0x02000001) #define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) #define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \ ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \ ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \ ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \ ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \ ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \ ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB)) /** * @} */ /** @defgroup I2C_flags_definition * @{ */ /** * @brief SR2 register flags */ #define I2C_FLAG_DUALF ((uint32_t)0x00800000) #define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) #define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) #define I2C_FLAG_GENCALL ((uint32_t)0x00100000) #define I2C_FLAG_TRA ((uint32_t)0x00040000) #define I2C_FLAG_BUSY ((uint32_t)0x00020000) #define I2C_FLAG_MSL ((uint32_t)0x00010000) /** * @brief SR1 register flags */ #define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) #define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) #define I2C_FLAG_PECERR ((uint32_t)0x10001000) #define I2C_FLAG_OVR ((uint32_t)0x10000800) #define I2C_FLAG_AF ((uint32_t)0x10000400) #define I2C_FLAG_ARLO ((uint32_t)0x10000200) #define I2C_FLAG_BERR ((uint32_t)0x10000100) #define I2C_FLAG_TXE ((uint32_t)0x10000080) #define I2C_FLAG_RXNE ((uint32_t)0x10000040) #define I2C_FLAG_STOPF ((uint32_t)0x10000010) #define I2C_FLAG_ADD10 ((uint32_t)0x10000008) #define I2C_FLAG_BTF ((uint32_t)0x10000004) #define I2C_FLAG_ADDR ((uint32_t)0x10000002) #define I2C_FLAG_SB ((uint32_t)0x10000001) #define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) #define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \ ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \ ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \ ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \ ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \ ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \ ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \ ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \ ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \ ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \ ((FLAG) == I2C_FLAG_SB)) /** * @} */ /** @defgroup I2C_Events * @{ */ /*======================================== I2C Master Events (Events grouped in order of communication) ==========================================*/ /** * @brief Communication start * * After sending the START condition (I2C_GenerateSTART() function) the master * has to wait for this event. It means that the Start condition has been correctly * released on the I2C bus (the bus is free, no other devices is communicating). * */ /* --EV5 */ #define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ /** * @brief Address Acknowledge * * After checking on EV5 (start condition correctly released on the bus), the * master sends the address of the slave(s) with which it will communicate * (I2C_Send7bitAddress() function, it also determines the direction of the communication: * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges * his address. If an acknowledge is sent on the bus, one of the following events will * be set: * * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED * event is set. * * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED * is set * * 3) In case of 10-Bit addressing mode, the master (just after generating the START * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() * function). Then master should wait on EV9. It means that the 10-bit addressing * header has been correctly sent on the bus. Then master should send the second part of * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master * should wait for event EV6. * */ /* --EV6 */ #define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ #define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ /* --EV9 */ #define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ /** * @brief Communication events * * If a communication is established (START condition generated and slave address * acknowledged) then the master has to check on one of the following events for * communication procedures: * * 1) Master Receiver mode: The master has to wait on the event EV7 then to read * the data received from the slave (I2C_ReceiveData() function). * * 2) Master Transmitter mode: The master has to send data (I2C_SendData() * function) then to wait on event EV8 or EV8_2. * These two events are similar: * - EV8 means that the data has been written in the data register and is * being shifted out. * - EV8_2 means that the data has been physically shifted out and output * on the bus. * In most cases, using EV8 is sufficient for the application. * Using EV8_2 leads to a slower communication but ensure more reliable test. * EV8_2 is also more suitable than EV8 for testing on the last data transmission * (before Stop condition generation). * * @note In case the user software does not guarantee that this event EV7 is * managed before the current byte end of transfer, then user may check on EV7 * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). * In this case the communication may be slower. * */ /* Master RECEIVER mode -----------------------------*/ /* --EV7 */ #define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ /* Master TRANSMITTER mode --------------------------*/ /* --EV8 */ #define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ /* --EV8_2 */ #define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ /*======================================== I2C Slave Events (Events grouped in order of communication) ==========================================*/ /** * @brief Communication start events * * Wait on one of these events at the start of the communication. It means that * the I2C peripheral detected a Start condition on the bus (generated by master * device) followed by the peripheral address. The peripheral generates an ACK * condition on the bus (if the acknowledge feature is enabled through function * I2C_AcknowledgeConfig()) and the events listed above are set : * * 1) In normal case (only one address managed by the slave), when the address * sent by the master matches the own address of the peripheral (configured by * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set * (where XXX could be TRANSMITTER or RECEIVER). * * 2) In case the address sent by the master matches the second address of the * peripheral (configured by the function I2C_OwnAddress2Config() and enabled * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED * (where XXX could be TRANSMITTER or RECEIVER) are set. * * 3) In case the address sent by the master is General Call (address 0x00) and * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. * */ /* --EV1 (all the events below are variants of EV1) */ /* 1) Case of One Single Address managed by the slave */ #define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ #define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ /* 2) Case of Dual address managed by the slave */ #define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ #define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ /* 3) Case of General Call enabled for the slave */ #define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ /** * @brief Communication events * * Wait on one of these events when EV1 has already been checked and: * * - Slave RECEIVER mode: * - EV2: When the application is expecting a data byte to be received. * - EV4: When the application is expecting the end of the communication: master * sends a stop condition and data transmission is stopped. * * - Slave Transmitter mode: * - EV3: When a byte has been transmitted by the slave and the application is expecting * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be * used when the user software doesn't guarantee the EV3 is managed before the * current byte end of transfer. * - EV3_2: When the master sends a NACK in order to tell slave that data transmission * shall end (before sending the STOP condition). In this case slave has to stop sending * data bytes and expect a Stop condition on the bus. * * @note In case the user software does not guarantee that the event EV2 is * managed before the current byte end of transfer, then user may check on EV2 * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). * In this case the communication may be slower. * */ /* Slave RECEIVER mode --------------------------*/ /* --EV2 */ #define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ /* --EV4 */ #define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ /* Slave TRANSMITTER mode -----------------------*/ /* --EV3 */ #define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ #define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ /* --EV3_2 */ #define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ /*=========================== End of Events Description ==========================================*/ #define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \ ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \ ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \ ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \ ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \ ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \ ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE)) /** * @} */ /** @defgroup I2C_own_address1 * @{ */ #define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) /** * @} */ /** @defgroup I2C_clock_speed * @{ */ #define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) /** * @} */ /** * @} */ /** @defgroup I2C_Exported_Macros * @{ */ /** * @} */ /** @defgroup I2C_Exported_Functions * @{ */ void I2C_DeInit(I2C_TypeDef* I2Cx); void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition); void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); /** * @brief **************************************************************************************** * * I2C State Monitoring Functions * **************************************************************************************** * This I2C driver provides three different ways for I2C state monitoring * depending on the application requirements and constraints: * * * 1) Basic state monitoring: * Using I2C_CheckEvent() function: * It compares the status registers (SR1 and SR2) content to a given event * (can be the combination of one or more flags). * It returns SUCCESS if the current status includes the given flags * and returns ERROR if one or more flags are missing in the current status. * - When to use: * - This function is suitable for most applications as well as for startup * activity since the events are fully described in the product reference manual * (RM0008). * - It is also suitable for users who need to define their own events. * - Limitations: * - If an error occurs (ie. error flags are set besides to the monitored flags), * the I2C_CheckEvent() function may return SUCCESS despite the communication * hold or corrupted real state. * In this case, it is advised to use error interrupts to monitor the error * events and handle them in the interrupt IRQ handler. * * @note * For error management, it is advised to use the following functions: * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. * Where x is the peripheral instance (I2C1, I2C2 ...) * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() * in order to determine which error occurred. * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() * and/or I2C_GenerateStop() in order to clear the error flag and source, * and return to correct communication status. * * * 2) Advanced state monitoring: * Using the function I2C_GetLastEvent() which returns the image of both status * registers in a single word (uint32_t) (Status Register 2 value is shifted left * by 16 bits and concatenated to Status Register 1). * - When to use: * - This function is suitable for the same applications above but it allows to * overcome the limitations of I2C_GetFlagStatus() function (see below). * The returned value could be compared to events already defined in the * library (stm32f10x_i2c.h) or to custom values defined by user. * - This function is suitable when multiple flags are monitored at the same time. * - At the opposite of I2C_CheckEvent() function, this function allows user to * choose when an event is accepted (when all events flags are set and no * other flags are set or just when the needed flags are set like * I2C_CheckEvent() function). * - Limitations: * - User may need to define his own events. * - Same remark concerning the error management is applicable for this * function if user decides to check only regular communication flags (and * ignores error flags). * * * 3) Flag-based state monitoring: * Using the function I2C_GetFlagStatus() which simply returns the status of * one single flag (ie. I2C_FLAG_RXNE ...). * - When to use: * - This function could be used for specific applications or in debug phase. * - It is suitable when only one flag checking is needed (most I2C events * are monitored through multiple flags). * - Limitations: * - When calling this function, the Status register is accessed. Some flags are * cleared when the status register is accessed. So checking the status * of one Flag, may clear other ones. * - Function may need to be called twice or more in order to monitor one * single event. * */ /** * * 1) Basic state monitoring ******************************************************************************* */ ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); /** * * 2) Advanced state monitoring ******************************************************************************* */ uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); /** * * 3) Flag-based state monitoring ******************************************************************************* */ FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); /** * ******************************************************************************* */ void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); #ifdef __cplusplus } #endif #endif /*__STM32F10x_I2C_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /** ****************************************************************************** * @file stm32f10x_i2c.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the I2C firmware * library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_I2C_H #define __STM32F10x_I2C_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup I2C * @{ */ /** @defgroup I2C_Exported_Types * @{ */ /** * @brief I2C Init structure definition */ typedef struct { uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency. This parameter must be set to a value lower than 400kHz */ uint16_t I2C_Mode; /*!< Specifies the I2C mode. This parameter can be a value of @ref I2C_mode */ uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle. This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address. This parameter can be a 7-bit or 10-bit address. */ uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement. This parameter can be a value of @ref I2C_acknowledgement */ uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. This parameter can be a value of @ref I2C_acknowledged_address */ }I2C_InitTypeDef; /** * @} */ /** @defgroup I2C_Exported_Constants * @{ */ #define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ ((PERIPH) == I2C2)) /** @defgroup I2C_mode * @{ */ #define I2C_Mode_I2C ((uint16_t)0x0000) #define I2C_Mode_SMBusDevice ((uint16_t)0x0002) #define I2C_Mode_SMBusHost ((uint16_t)0x000A) #define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ ((MODE) == I2C_Mode_SMBusDevice) || \ ((MODE) == I2C_Mode_SMBusHost)) /** * @} */ /** @defgroup I2C_duty_cycle_in_fast_mode * @{ */ #define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ #define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ #define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \ ((CYCLE) == I2C_DutyCycle_2)) /** * @} */ /** @defgroup I2C_acknowledgement * @{ */ #define I2C_Ack_Enable ((uint16_t)0x0400) #define I2C_Ack_Disable ((uint16_t)0x0000) #define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \ ((STATE) == I2C_Ack_Disable)) /** * @} */ /** @defgroup I2C_transfer_direction * @{ */ #define I2C_Direction_Transmitter ((uint8_t)0x00) #define I2C_Direction_Receiver ((uint8_t)0x01) #define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ ((DIRECTION) == I2C_Direction_Receiver)) /** * @} */ /** @defgroup I2C_acknowledged_address * @{ */ #define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) #define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) #define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) /** * @} */ /** @defgroup I2C_registers * @{ */ #define I2C_Register_CR1 ((uint8_t)0x00) #define I2C_Register_CR2 ((uint8_t)0x04) #define I2C_Register_OAR1 ((uint8_t)0x08) #define I2C_Register_OAR2 ((uint8_t)0x0C) #define I2C_Register_DR ((uint8_t)0x10) #define I2C_Register_SR1 ((uint8_t)0x14) #define I2C_Register_SR2 ((uint8_t)0x18) #define I2C_Register_CCR ((uint8_t)0x1C) #define I2C_Register_TRISE ((uint8_t)0x20) #define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ ((REGISTER) == I2C_Register_CR2) || \ ((REGISTER) == I2C_Register_OAR1) || \ ((REGISTER) == I2C_Register_OAR2) || \ ((REGISTER) == I2C_Register_DR) || \ ((REGISTER) == I2C_Register_SR1) || \ ((REGISTER) == I2C_Register_SR2) || \ ((REGISTER) == I2C_Register_CCR) || \ ((REGISTER) == I2C_Register_TRISE)) /** * @} */ /** @defgroup I2C_SMBus_alert_pin_level * @{ */ #define I2C_SMBusAlert_Low ((uint16_t)0x2000) #define I2C_SMBusAlert_High ((uint16_t)0xDFFF) #define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \ ((ALERT) == I2C_SMBusAlert_High)) /** * @} */ /** @defgroup I2C_PEC_position * @{ */ #define I2C_PECPosition_Next ((uint16_t)0x0800) #define I2C_PECPosition_Current ((uint16_t)0xF7FF) #define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \ ((POSITION) == I2C_PECPosition_Current)) /** * @} */ /** @defgroup I2C_NCAK_position * @{ */ #define I2C_NACKPosition_Next ((uint16_t)0x0800) #define I2C_NACKPosition_Current ((uint16_t)0xF7FF) #define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \ ((POSITION) == I2C_NACKPosition_Current)) /** * @} */ /** @defgroup I2C_interrupts_definition * @{ */ #define I2C_IT_BUF ((uint16_t)0x0400) #define I2C_IT_EVT ((uint16_t)0x0200) #define I2C_IT_ERR ((uint16_t)0x0100) #define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) /** * @} */ /** @defgroup I2C_interrupts_definition * @{ */ #define I2C_IT_SMBALERT ((uint32_t)0x01008000) #define I2C_IT_TIMEOUT ((uint32_t)0x01004000) #define I2C_IT_PECERR ((uint32_t)0x01001000) #define I2C_IT_OVR ((uint32_t)0x01000800) #define I2C_IT_AF ((uint32_t)0x01000400) #define I2C_IT_ARLO ((uint32_t)0x01000200) #define I2C_IT_BERR ((uint32_t)0x01000100) #define I2C_IT_TXE ((uint32_t)0x06000080) #define I2C_IT_RXNE ((uint32_t)0x06000040) #define I2C_IT_STOPF ((uint32_t)0x02000010) #define I2C_IT_ADD10 ((uint32_t)0x02000008) #define I2C_IT_BTF ((uint32_t)0x02000004) #define I2C_IT_ADDR ((uint32_t)0x02000002) #define I2C_IT_SB ((uint32_t)0x02000001) #define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) #define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \ ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \ ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \ ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \ ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \ ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \ ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB)) /** * @} */ /** @defgroup I2C_flags_definition * @{ */ /** * @brief SR2 register flags */ #define I2C_FLAG_DUALF ((uint32_t)0x00800000) #define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) #define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) #define I2C_FLAG_GENCALL ((uint32_t)0x00100000) #define I2C_FLAG_TRA ((uint32_t)0x00040000) #define I2C_FLAG_BUSY ((uint32_t)0x00020000) #define I2C_FLAG_MSL ((uint32_t)0x00010000) /** * @brief SR1 register flags */ #define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) #define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) #define I2C_FLAG_PECERR ((uint32_t)0x10001000) #define I2C_FLAG_OVR ((uint32_t)0x10000800) #define I2C_FLAG_AF ((uint32_t)0x10000400) #define I2C_FLAG_ARLO ((uint32_t)0x10000200) #define I2C_FLAG_BERR ((uint32_t)0x10000100) #define I2C_FLAG_TXE ((uint32_t)0x10000080) #define I2C_FLAG_RXNE ((uint32_t)0x10000040) #define I2C_FLAG_STOPF ((uint32_t)0x10000010) #define I2C_FLAG_ADD10 ((uint32_t)0x10000008) #define I2C_FLAG_BTF ((uint32_t)0x10000004) #define I2C_FLAG_ADDR ((uint32_t)0x10000002) #define I2C_FLAG_SB ((uint32_t)0x10000001) #define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) #define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \ ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \ ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \ ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \ ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \ ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \ ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \ ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \ ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \ ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \ ((FLAG) == I2C_FLAG_SB)) /** * @} */ /** @defgroup I2C_Events * @{ */ /*======================================== I2C Master Events (Events grouped in order of communication) ==========================================*/ /** * @brief Communication start * * After sending the START condition (I2C_GenerateSTART() function) the master * has to wait for this event. It means that the Start condition has been correctly * released on the I2C bus (the bus is free, no other devices is communicating). * */ /* --EV5 */ #define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ /** * @brief Address Acknowledge * * After checking on EV5 (start condition correctly released on the bus), the * master sends the address of the slave(s) with which it will communicate * (I2C_Send7bitAddress() function, it also determines the direction of the communication: * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges * his address. If an acknowledge is sent on the bus, one of the following events will * be set: * * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED * event is set. * * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED * is set * * 3) In case of 10-Bit addressing mode, the master (just after generating the START * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() * function). Then master should wait on EV9. It means that the 10-bit addressing * header has been correctly sent on the bus. Then master should send the second part of * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master * should wait for event EV6. * */ /* --EV6 */ #define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ #define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ /* --EV9 */ #define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ /** * @brief Communication events * * If a communication is established (START condition generated and slave address * acknowledged) then the master has to check on one of the following events for * communication procedures: * * 1) Master Receiver mode: The master has to wait on the event EV7 then to read * the data received from the slave (I2C_ReceiveData() function). * * 2) Master Transmitter mode: The master has to send data (I2C_SendData() * function) then to wait on event EV8 or EV8_2. * These two events are similar: * - EV8 means that the data has been written in the data register and is * being shifted out. * - EV8_2 means that the data has been physically shifted out and output * on the bus. * In most cases, using EV8 is sufficient for the application. * Using EV8_2 leads to a slower communication but ensure more reliable test. * EV8_2 is also more suitable than EV8 for testing on the last data transmission * (before Stop condition generation). * * @note In case the user software does not guarantee that this event EV7 is * managed before the current byte end of transfer, then user may check on EV7 * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). * In this case the communication may be slower. * */ /* Master RECEIVER mode -----------------------------*/ /* --EV7 */ #define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ /* Master TRANSMITTER mode --------------------------*/ /* --EV8 */ #define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ /* --EV8_2 */ #define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ /*======================================== I2C Slave Events (Events grouped in order of communication) ==========================================*/ /** * @brief Communication start events * * Wait on one of these events at the start of the communication. It means that * the I2C peripheral detected a Start condition on the bus (generated by master * device) followed by the peripheral address. The peripheral generates an ACK * condition on the bus (if the acknowledge feature is enabled through function * I2C_AcknowledgeConfig()) and the events listed above are set : * * 1) In normal case (only one address managed by the slave), when the address * sent by the master matches the own address of the peripheral (configured by * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set * (where XXX could be TRANSMITTER or RECEIVER). * * 2) In case the address sent by the master matches the second address of the * peripheral (configured by the function I2C_OwnAddress2Config() and enabled * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED * (where XXX could be TRANSMITTER or RECEIVER) are set. * * 3) In case the address sent by the master is General Call (address 0x00) and * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. * */ /* --EV1 (all the events below are variants of EV1) */ /* 1) Case of One Single Address managed by the slave */ #define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ #define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ /* 2) Case of Dual address managed by the slave */ #define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ #define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ /* 3) Case of General Call enabled for the slave */ #define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ /** * @brief Communication events * * Wait on one of these events when EV1 has already been checked and: * * - Slave RECEIVER mode: * - EV2: When the application is expecting a data byte to be received. * - EV4: When the application is expecting the end of the communication: master * sends a stop condition and data transmission is stopped. * * - Slave Transmitter mode: * - EV3: When a byte has been transmitted by the slave and the application is expecting * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be * used when the user software doesn't guarantee the EV3 is managed before the * current byte end of transfer. * - EV3_2: When the master sends a NACK in order to tell slave that data transmission * shall end (before sending the STOP condition). In this case slave has to stop sending * data bytes and expect a Stop condition on the bus. * * @note In case the user software does not guarantee that the event EV2 is * managed before the current byte end of transfer, then user may check on EV2 * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). * In this case the communication may be slower. * */ /* Slave RECEIVER mode --------------------------*/ /* --EV2 */ #define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ /* --EV4 */ #define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ /* Slave TRANSMITTER mode -----------------------*/ /* --EV3 */ #define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ #define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ /* --EV3_2 */ #define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ /*=========================== End of Events Description ==========================================*/ #define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \ ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \ ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \ ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \ ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \ ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \ ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE)) /** * @} */ /** @defgroup I2C_own_address1 * @{ */ #define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) /** * @} */ /** @defgroup I2C_clock_speed * @{ */ #define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) /** * @} */ /** * @} */ /** @defgroup I2C_Exported_Macros * @{ */ /** * @} */ /** @defgroup I2C_Exported_Functions * @{ */ void I2C_DeInit(I2C_TypeDef* I2Cx); void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition); void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); /** * @brief **************************************************************************************** * * I2C State Monitoring Functions * **************************************************************************************** * This I2C driver provides three different ways for I2C state monitoring * depending on the application requirements and constraints: * * * 1) Basic state monitoring: * Using I2C_CheckEvent() function: * It compares the status registers (SR1 and SR2) content to a given event * (can be the combination of one or more flags). * It returns SUCCESS if the current status includes the given flags * and returns ERROR if one or more flags are missing in the current status. * - When to use: * - This function is suitable for most applications as well as for startup * activity since the events are fully described in the product reference manual * (RM0008). * - It is also suitable for users who need to define their own events. * - Limitations: * - If an error occurs (ie. error flags are set besides to the monitored flags), * the I2C_CheckEvent() function may return SUCCESS despite the communication * hold or corrupted real state. * In this case, it is advised to use error interrupts to monitor the error * events and handle them in the interrupt IRQ handler. * * @note * For error management, it is advised to use the following functions: * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. * Where x is the peripheral instance (I2C1, I2C2 ...) * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() * in order to determine which error occurred. * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() * and/or I2C_GenerateStop() in order to clear the error flag and source, * and return to correct communication status. * * * 2) Advanced state monitoring: * Using the function I2C_GetLastEvent() which returns the image of both status * registers in a single word (uint32_t) (Status Register 2 value is shifted left * by 16 bits and concatenated to Status Register 1). * - When to use: * - This function is suitable for the same applications above but it allows to * overcome the limitations of I2C_GetFlagStatus() function (see below). * The returned value could be compared to events already defined in the * library (stm32f10x_i2c.h) or to custom values defined by user. * - This function is suitable when multiple flags are monitored at the same time. * - At the opposite of I2C_CheckEvent() function, this function allows user to * choose when an event is accepted (when all events flags are set and no * other flags are set or just when the needed flags are set like * I2C_CheckEvent() function). * - Limitations: * - User may need to define his own events. * - Same remark concerning the error management is applicable for this * function if user decides to check only regular communication flags (and * ignores error flags). * * * 3) Flag-based state monitoring: * Using the function I2C_GetFlagStatus() which simply returns the status of * one single flag (ie. I2C_FLAG_RXNE ...). * - When to use: * - This function could be used for specific applications or in debug phase. * - It is suitable when only one flag checking is needed (most I2C events * are monitored through multiple flags). * - Limitations: * - When calling this function, the Status register is accessed. Some flags are * cleared when the status register is accessed. So checking the status * of one Flag, may clear other ones. * - Function may need to be called twice or more in order to monitor one * single event. * */ /** * * 1) Basic state monitoring ******************************************************************************* */ ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); /** * * 2) Advanced state monitoring ******************************************************************************* */ uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); /** * * 3) Flag-based state monitoring ******************************************************************************* */ FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); /** * ******************************************************************************* */ void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); #ifdef __cplusplus } #endif #endif /*__STM32F10x_I2C_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ src/bare_test/1.Led/stdlib/inc/stm32f10x_iwdg.h
File was renamed from src/bare_test/stm32_key/fwlib/inc/stm32f10x_iwdg.h @@ -1,140 +1,140 @@ /** ****************************************************************************** * @file stm32f10x_iwdg.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the IWDG * firmware library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_IWDG_H #define __STM32F10x_IWDG_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup IWDG * @{ */ /** @defgroup IWDG_Exported_Types * @{ */ /** * @} */ /** @defgroup IWDG_Exported_Constants * @{ */ /** @defgroup IWDG_WriteAccess * @{ */ #define IWDG_WriteAccess_Enable ((uint16_t)0x5555) #define IWDG_WriteAccess_Disable ((uint16_t)0x0000) #define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ ((ACCESS) == IWDG_WriteAccess_Disable)) /** * @} */ /** @defgroup IWDG_prescaler * @{ */ #define IWDG_Prescaler_4 ((uint8_t)0x00) #define IWDG_Prescaler_8 ((uint8_t)0x01) #define IWDG_Prescaler_16 ((uint8_t)0x02) #define IWDG_Prescaler_32 ((uint8_t)0x03) #define IWDG_Prescaler_64 ((uint8_t)0x04) #define IWDG_Prescaler_128 ((uint8_t)0x05) #define IWDG_Prescaler_256 ((uint8_t)0x06) #define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ ((PRESCALER) == IWDG_Prescaler_8) || \ ((PRESCALER) == IWDG_Prescaler_16) || \ ((PRESCALER) == IWDG_Prescaler_32) || \ ((PRESCALER) == IWDG_Prescaler_64) || \ ((PRESCALER) == IWDG_Prescaler_128)|| \ ((PRESCALER) == IWDG_Prescaler_256)) /** * @} */ /** @defgroup IWDG_Flag * @{ */ #define IWDG_FLAG_PVU ((uint16_t)0x0001) #define IWDG_FLAG_RVU ((uint16_t)0x0002) #define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) #define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) /** * @} */ /** * @} */ /** @defgroup IWDG_Exported_Macros * @{ */ /** * @} */ /** @defgroup IWDG_Exported_Functions * @{ */ void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); void IWDG_SetReload(uint16_t Reload); void IWDG_ReloadCounter(void); void IWDG_Enable(void); FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); #ifdef __cplusplus } #endif #endif /* __STM32F10x_IWDG_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /** ****************************************************************************** * @file stm32f10x_iwdg.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the IWDG * firmware library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_IWDG_H #define __STM32F10x_IWDG_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup IWDG * @{ */ /** @defgroup IWDG_Exported_Types * @{ */ /** * @} */ /** @defgroup IWDG_Exported_Constants * @{ */ /** @defgroup IWDG_WriteAccess * @{ */ #define IWDG_WriteAccess_Enable ((uint16_t)0x5555) #define IWDG_WriteAccess_Disable ((uint16_t)0x0000) #define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ ((ACCESS) == IWDG_WriteAccess_Disable)) /** * @} */ /** @defgroup IWDG_prescaler * @{ */ #define IWDG_Prescaler_4 ((uint8_t)0x00) #define IWDG_Prescaler_8 ((uint8_t)0x01) #define IWDG_Prescaler_16 ((uint8_t)0x02) #define IWDG_Prescaler_32 ((uint8_t)0x03) #define IWDG_Prescaler_64 ((uint8_t)0x04) #define IWDG_Prescaler_128 ((uint8_t)0x05) #define IWDG_Prescaler_256 ((uint8_t)0x06) #define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ ((PRESCALER) == IWDG_Prescaler_8) || \ ((PRESCALER) == IWDG_Prescaler_16) || \ ((PRESCALER) == IWDG_Prescaler_32) || \ ((PRESCALER) == IWDG_Prescaler_64) || \ ((PRESCALER) == IWDG_Prescaler_128)|| \ ((PRESCALER) == IWDG_Prescaler_256)) /** * @} */ /** @defgroup IWDG_Flag * @{ */ #define IWDG_FLAG_PVU ((uint16_t)0x0001) #define IWDG_FLAG_RVU ((uint16_t)0x0002) #define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) #define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) /** * @} */ /** * @} */ /** @defgroup IWDG_Exported_Macros * @{ */ /** * @} */ /** @defgroup IWDG_Exported_Functions * @{ */ void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); void IWDG_SetReload(uint16_t Reload); void IWDG_ReloadCounter(void); void IWDG_Enable(void); FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); #ifdef __cplusplus } #endif #endif /* __STM32F10x_IWDG_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ src/bare_test/1.Led/stdlib/inc/stm32f10x_pwr.h
File was renamed from src/bare_test/stm32_key/fwlib/inc/stm32f10x_pwr.h @@ -1,156 +1,156 @@ /** ****************************************************************************** * @file stm32f10x_pwr.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the PWR firmware * library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_PWR_H #define __STM32F10x_PWR_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup PWR * @{ */ /** @defgroup PWR_Exported_Types * @{ */ /** * @} */ /** @defgroup PWR_Exported_Constants * @{ */ /** @defgroup PVD_detection_level * @{ */ #define PWR_PVDLevel_2V2 ((uint32_t)0x00000000) #define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) #define PWR_PVDLevel_2V4 ((uint32_t)0x00000040) #define PWR_PVDLevel_2V5 ((uint32_t)0x00000060) #define PWR_PVDLevel_2V6 ((uint32_t)0x00000080) #define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0) #define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0) #define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0) #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \ ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \ ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \ ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9)) /** * @} */ /** @defgroup Regulator_state_is_STOP_mode * @{ */ #define PWR_Regulator_ON ((uint32_t)0x00000000) #define PWR_Regulator_LowPower ((uint32_t)0x00000001) #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ ((REGULATOR) == PWR_Regulator_LowPower)) /** * @} */ /** @defgroup STOP_mode_entry * @{ */ #define PWR_STOPEntry_WFI ((uint8_t)0x01) #define PWR_STOPEntry_WFE ((uint8_t)0x02) #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) /** * @} */ /** @defgroup PWR_Flag * @{ */ #define PWR_FLAG_WU ((uint32_t)0x00000001) #define PWR_FLAG_SB ((uint32_t)0x00000002) #define PWR_FLAG_PVDO ((uint32_t)0x00000004) #define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ ((FLAG) == PWR_FLAG_PVDO)) #define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) /** * @} */ /** * @} */ /** @defgroup PWR_Exported_Macros * @{ */ /** * @} */ /** @defgroup PWR_Exported_Functions * @{ */ void PWR_DeInit(void); void PWR_BackupAccessCmd(FunctionalState NewState); void PWR_PVDCmd(FunctionalState NewState); void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); void PWR_WakeUpPinCmd(FunctionalState NewState); void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); void PWR_EnterSTANDBYMode(void); FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); void PWR_ClearFlag(uint32_t PWR_FLAG); #ifdef __cplusplus } #endif #endif /* __STM32F10x_PWR_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /** ****************************************************************************** * @file stm32f10x_pwr.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the PWR firmware * library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_PWR_H #define __STM32F10x_PWR_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup PWR * @{ */ /** @defgroup PWR_Exported_Types * @{ */ /** * @} */ /** @defgroup PWR_Exported_Constants * @{ */ /** @defgroup PVD_detection_level * @{ */ #define PWR_PVDLevel_2V2 ((uint32_t)0x00000000) #define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) #define PWR_PVDLevel_2V4 ((uint32_t)0x00000040) #define PWR_PVDLevel_2V5 ((uint32_t)0x00000060) #define PWR_PVDLevel_2V6 ((uint32_t)0x00000080) #define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0) #define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0) #define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0) #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \ ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \ ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \ ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9)) /** * @} */ /** @defgroup Regulator_state_is_STOP_mode * @{ */ #define PWR_Regulator_ON ((uint32_t)0x00000000) #define PWR_Regulator_LowPower ((uint32_t)0x00000001) #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ ((REGULATOR) == PWR_Regulator_LowPower)) /** * @} */ /** @defgroup STOP_mode_entry * @{ */ #define PWR_STOPEntry_WFI ((uint8_t)0x01) #define PWR_STOPEntry_WFE ((uint8_t)0x02) #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) /** * @} */ /** @defgroup PWR_Flag * @{ */ #define PWR_FLAG_WU ((uint32_t)0x00000001) #define PWR_FLAG_SB ((uint32_t)0x00000002) #define PWR_FLAG_PVDO ((uint32_t)0x00000004) #define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ ((FLAG) == PWR_FLAG_PVDO)) #define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) /** * @} */ /** * @} */ /** @defgroup PWR_Exported_Macros * @{ */ /** * @} */ /** @defgroup PWR_Exported_Functions * @{ */ void PWR_DeInit(void); void PWR_BackupAccessCmd(FunctionalState NewState); void PWR_PVDCmd(FunctionalState NewState); void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); void PWR_WakeUpPinCmd(FunctionalState NewState); void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); void PWR_EnterSTANDBYMode(void); FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); void PWR_ClearFlag(uint32_t PWR_FLAG); #ifdef __cplusplus } #endif #endif /* __STM32F10x_PWR_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ src/bare_test/1.Led/stdlib/inc/stm32f10x_rcc.h
File was renamed from src/bare_test/stm32_key/fwlib/inc/stm32f10x_rcc.h @@ -1,727 +1,727 @@ /** ****************************************************************************** * @file stm32f10x_rcc.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the RCC firmware * library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_RCC_H #define __STM32F10x_RCC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup RCC * @{ */ /** @defgroup RCC_Exported_Types * @{ */ typedef struct { uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */ uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */ uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */ uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */ uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */ }RCC_ClocksTypeDef; /** * @} */ /** @defgroup RCC_Exported_Constants * @{ */ /** @defgroup HSE_configuration * @{ */ #define RCC_HSE_OFF ((uint32_t)0x00000000) #define RCC_HSE_ON ((uint32_t)0x00010000) #define RCC_HSE_Bypass ((uint32_t)0x00040000) #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ ((HSE) == RCC_HSE_Bypass)) /** * @} */ /** @defgroup PLL_entry_clock_source * @{ */ #define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_CL) #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ ((SOURCE) == RCC_PLLSource_HSE_Div1) || \ ((SOURCE) == RCC_PLLSource_HSE_Div2)) #else #define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000) #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ ((SOURCE) == RCC_PLLSource_PREDIV1)) #endif /* STM32F10X_CL */ /** * @} */ /** @defgroup PLL_multiplication_factor * @{ */ #ifndef STM32F10X_CL #define RCC_PLLMul_2 ((uint32_t)0x00000000) #define RCC_PLLMul_3 ((uint32_t)0x00040000) #define RCC_PLLMul_4 ((uint32_t)0x00080000) #define RCC_PLLMul_5 ((uint32_t)0x000C0000) #define RCC_PLLMul_6 ((uint32_t)0x00100000) #define RCC_PLLMul_7 ((uint32_t)0x00140000) #define RCC_PLLMul_8 ((uint32_t)0x00180000) #define RCC_PLLMul_9 ((uint32_t)0x001C0000) #define RCC_PLLMul_10 ((uint32_t)0x00200000) #define RCC_PLLMul_11 ((uint32_t)0x00240000) #define RCC_PLLMul_12 ((uint32_t)0x00280000) #define RCC_PLLMul_13 ((uint32_t)0x002C0000) #define RCC_PLLMul_14 ((uint32_t)0x00300000) #define RCC_PLLMul_15 ((uint32_t)0x00340000) #define RCC_PLLMul_16 ((uint32_t)0x00380000) #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ ((MUL) == RCC_PLLMul_16)) #else #define RCC_PLLMul_4 ((uint32_t)0x00080000) #define RCC_PLLMul_5 ((uint32_t)0x000C0000) #define RCC_PLLMul_6 ((uint32_t)0x00100000) #define RCC_PLLMul_7 ((uint32_t)0x00140000) #define RCC_PLLMul_8 ((uint32_t)0x00180000) #define RCC_PLLMul_9 ((uint32_t)0x001C0000) #define RCC_PLLMul_6_5 ((uint32_t)0x00340000) #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ ((MUL) == RCC_PLLMul_6_5)) #endif /* STM32F10X_CL */ /** * @} */ /** @defgroup PREDIV1_division_factor * @{ */ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) #define RCC_PREDIV1_Div1 ((uint32_t)0x00000000) #define RCC_PREDIV1_Div2 ((uint32_t)0x00000001) #define RCC_PREDIV1_Div3 ((uint32_t)0x00000002) #define RCC_PREDIV1_Div4 ((uint32_t)0x00000003) #define RCC_PREDIV1_Div5 ((uint32_t)0x00000004) #define RCC_PREDIV1_Div6 ((uint32_t)0x00000005) #define RCC_PREDIV1_Div7 ((uint32_t)0x00000006) #define RCC_PREDIV1_Div8 ((uint32_t)0x00000007) #define RCC_PREDIV1_Div9 ((uint32_t)0x00000008) #define RCC_PREDIV1_Div10 ((uint32_t)0x00000009) #define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A) #define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B) #define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C) #define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D) #define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E) #define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F) #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \ ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \ ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \ ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \ ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \ ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) #endif /** * @} */ /** @defgroup PREDIV1_clock_source * @{ */ #ifdef STM32F10X_CL /* PREDIV1 clock source (for STM32 connectivity line devices) */ #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) #define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000) #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \ ((SOURCE) == RCC_PREDIV1_Source_PLL2)) #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) /* PREDIV1 clock source (for STM32 Value line devices) */ #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE)) #endif /** * @} */ #ifdef STM32F10X_CL /** @defgroup PREDIV2_division_factor * @{ */ #define RCC_PREDIV2_Div1 ((uint32_t)0x00000000) #define RCC_PREDIV2_Div2 ((uint32_t)0x00000010) #define RCC_PREDIV2_Div3 ((uint32_t)0x00000020) #define RCC_PREDIV2_Div4 ((uint32_t)0x00000030) #define RCC_PREDIV2_Div5 ((uint32_t)0x00000040) #define RCC_PREDIV2_Div6 ((uint32_t)0x00000050) #define RCC_PREDIV2_Div7 ((uint32_t)0x00000060) #define RCC_PREDIV2_Div8 ((uint32_t)0x00000070) #define RCC_PREDIV2_Div9 ((uint32_t)0x00000080) #define RCC_PREDIV2_Div10 ((uint32_t)0x00000090) #define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0) #define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0) #define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0) #define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0) #define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0) #define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0) #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \ ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \ ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \ ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \ ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \ ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \ ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \ ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16)) /** * @} */ /** @defgroup PLL2_multiplication_factor * @{ */ #define RCC_PLL2Mul_8 ((uint32_t)0x00000600) #define RCC_PLL2Mul_9 ((uint32_t)0x00000700) #define RCC_PLL2Mul_10 ((uint32_t)0x00000800) #define RCC_PLL2Mul_11 ((uint32_t)0x00000900) #define RCC_PLL2Mul_12 ((uint32_t)0x00000A00) #define RCC_PLL2Mul_13 ((uint32_t)0x00000B00) #define RCC_PLL2Mul_14 ((uint32_t)0x00000C00) #define RCC_PLL2Mul_16 ((uint32_t)0x00000E00) #define RCC_PLL2Mul_20 ((uint32_t)0x00000F00) #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \ ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \ ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \ ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \ ((MUL) == RCC_PLL2Mul_20)) /** * @} */ /** @defgroup PLL3_multiplication_factor * @{ */ #define RCC_PLL3Mul_8 ((uint32_t)0x00006000) #define RCC_PLL3Mul_9 ((uint32_t)0x00007000) #define RCC_PLL3Mul_10 ((uint32_t)0x00008000) #define RCC_PLL3Mul_11 ((uint32_t)0x00009000) #define RCC_PLL3Mul_12 ((uint32_t)0x0000A000) #define RCC_PLL3Mul_13 ((uint32_t)0x0000B000) #define RCC_PLL3Mul_14 ((uint32_t)0x0000C000) #define RCC_PLL3Mul_16 ((uint32_t)0x0000E000) #define RCC_PLL3Mul_20 ((uint32_t)0x0000F000) #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \ ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \ ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \ ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \ ((MUL) == RCC_PLL3Mul_20)) /** * @} */ #endif /* STM32F10X_CL */ /** @defgroup System_clock_source * @{ */ #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ ((SOURCE) == RCC_SYSCLKSource_HSE) || \ ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) /** * @} */ /** @defgroup AHB_clock_source * @{ */ #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) #define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ ((HCLK) == RCC_SYSCLK_Div512)) /** * @} */ /** @defgroup APB1_APB2_clock_source * @{ */ #define RCC_HCLK_Div1 ((uint32_t)0x00000000) #define RCC_HCLK_Div2 ((uint32_t)0x00000400) #define RCC_HCLK_Div4 ((uint32_t)0x00000500) #define RCC_HCLK_Div8 ((uint32_t)0x00000600) #define RCC_HCLK_Div16 ((uint32_t)0x00000700) #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ ((PCLK) == RCC_HCLK_Div16)) /** * @} */ /** @defgroup RCC_Interrupt_source * @{ */ #define RCC_IT_LSIRDY ((uint8_t)0x01) #define RCC_IT_LSERDY ((uint8_t)0x02) #define RCC_IT_HSIRDY ((uint8_t)0x04) #define RCC_IT_HSERDY ((uint8_t)0x08) #define RCC_IT_PLLRDY ((uint8_t)0x10) #define RCC_IT_CSS ((uint8_t)0x80) #ifndef STM32F10X_CL #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00)) #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00)) #else #define RCC_IT_PLL2RDY ((uint8_t)0x20) #define RCC_IT_PLL3RDY ((uint8_t)0x40) #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY)) #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00) #endif /* STM32F10X_CL */ /** * @} */ #ifndef STM32F10X_CL /** @defgroup USB_Device_clock_source * @{ */ #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00) #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \ ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) /** * @} */ #else /** @defgroup USB_OTG_FS_clock_source * @{ */ #define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00) #define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01) #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \ ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2)) /** * @} */ #endif /* STM32F10X_CL */ #ifdef STM32F10X_CL /** @defgroup I2S2_clock_source * @{ */ #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00) #define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01) #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \ ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO)) /** * @} */ /** @defgroup I2S3_clock_source * @{ */ #define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00) #define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01) #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \ ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO)) /** * @} */ #endif /* STM32F10X_CL */ /** @defgroup ADC_clock_source * @{ */ #define RCC_PCLK2_Div2 ((uint32_t)0x00000000) #define RCC_PCLK2_Div4 ((uint32_t)0x00004000) #define RCC_PCLK2_Div6 ((uint32_t)0x00008000) #define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) #define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \ ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) /** * @} */ /** @defgroup LSE_configuration * @{ */ #define RCC_LSE_OFF ((uint8_t)0x00) #define RCC_LSE_ON ((uint8_t)0x01) #define RCC_LSE_Bypass ((uint8_t)0x04) #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ ((LSE) == RCC_LSE_Bypass)) /** * @} */ /** @defgroup RTC_clock_source * @{ */ #define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) #define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ ((SOURCE) == RCC_RTCCLKSource_LSI) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) /** * @} */ /** @defgroup AHB_peripheral * @{ */ #define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) #define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) #define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) #define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) #define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) #ifndef STM32F10X_CL #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) #else #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000) #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000) #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000) #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000) #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00)) #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00)) #endif /* STM32F10X_CL */ /** * @} */ /** @defgroup APB2_peripheral * @{ */ #define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) #define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) #define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) #define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) #define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) #define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) #define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080) #define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100) #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) #define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) #define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) #define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) #define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000) #define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000) #define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000) #define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000) #define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) #define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) #define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000) #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00)) /** * @} */ /** @defgroup APB1_peripheral * @{ */ #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) #define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) #define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) #define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) #define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) #define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) #define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) #define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) #define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) #define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) #define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) #define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) #define RCC_APB1Periph_USB ((uint32_t)0x00800000) #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) #define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) #define RCC_APB1Periph_BKP ((uint32_t)0x08000000) #define RCC_APB1Periph_PWR ((uint32_t)0x10000000) #define RCC_APB1Periph_DAC ((uint32_t)0x20000000) #define RCC_APB1Periph_CEC ((uint32_t)0x40000000) #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00)) /** * @} */ /** @defgroup Clock_source_to_output_on_MCO_pin * @{ */ #define RCC_MCO_NoClock ((uint8_t)0x00) #define RCC_MCO_SYSCLK ((uint8_t)0x04) #define RCC_MCO_HSI ((uint8_t)0x05) #define RCC_MCO_HSE ((uint8_t)0x06) #define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) #ifndef STM32F10X_CL #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ ((MCO) == RCC_MCO_PLLCLK_Div2)) #else #define RCC_MCO_PLL2CLK ((uint8_t)0x08) #define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09) #define RCC_MCO_XT1 ((uint8_t)0x0A) #define RCC_MCO_PLL3CLK ((uint8_t)0x0B) #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \ ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \ ((MCO) == RCC_MCO_PLL3CLK)) #endif /* STM32F10X_CL */ /** * @} */ /** @defgroup RCC_Flag * @{ */ #define RCC_FLAG_HSIRDY ((uint8_t)0x21) #define RCC_FLAG_HSERDY ((uint8_t)0x31) #define RCC_FLAG_PLLRDY ((uint8_t)0x39) #define RCC_FLAG_LSERDY ((uint8_t)0x41) #define RCC_FLAG_LSIRDY ((uint8_t)0x61) #define RCC_FLAG_PINRST ((uint8_t)0x7A) #define RCC_FLAG_PORRST ((uint8_t)0x7B) #define RCC_FLAG_SFTRST ((uint8_t)0x7C) #define RCC_FLAG_IWDGRST ((uint8_t)0x7D) #define RCC_FLAG_WWDGRST ((uint8_t)0x7E) #define RCC_FLAG_LPWRRST ((uint8_t)0x7F) #ifndef STM32F10X_CL #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ ((FLAG) == RCC_FLAG_LPWRRST)) #else #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \ ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ ((FLAG) == RCC_FLAG_LPWRRST)) #endif /* STM32F10X_CL */ #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) /** * @} */ /** * @} */ /** @defgroup RCC_Exported_Macros * @{ */ /** * @} */ /** @defgroup RCC_Exported_Functions * @{ */ void RCC_DeInit(void); void RCC_HSEConfig(uint32_t RCC_HSE); ErrorStatus RCC_WaitForHSEStartUp(void); void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); void RCC_HSICmd(FunctionalState NewState); void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); void RCC_PLLCmd(FunctionalState NewState); #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div); #endif #ifdef STM32F10X_CL void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div); void RCC_PLL2Config(uint32_t RCC_PLL2Mul); void RCC_PLL2Cmd(FunctionalState NewState); void RCC_PLL3Config(uint32_t RCC_PLL3Mul); void RCC_PLL3Cmd(FunctionalState NewState); #endif /* STM32F10X_CL */ void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); uint8_t RCC_GetSYSCLKSource(void); void RCC_HCLKConfig(uint32_t RCC_SYSCLK); void RCC_PCLK1Config(uint32_t RCC_HCLK); void RCC_PCLK2Config(uint32_t RCC_HCLK); void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); #ifndef STM32F10X_CL void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); #else void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource); #endif /* STM32F10X_CL */ void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); #ifdef STM32F10X_CL void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource); void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource); #endif /* STM32F10X_CL */ void RCC_LSEConfig(uint8_t RCC_LSE); void RCC_LSICmd(FunctionalState NewState); void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); void RCC_RTCCLKCmd(FunctionalState NewState); void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); #ifdef STM32F10X_CL void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); #endif /* STM32F10X_CL */ void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); void RCC_BackupResetCmd(FunctionalState NewState); void RCC_ClockSecuritySystemCmd(FunctionalState NewState); void RCC_MCOConfig(uint8_t RCC_MCO); FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); void RCC_ClearFlag(void); ITStatus RCC_GetITStatus(uint8_t RCC_IT); void RCC_ClearITPendingBit(uint8_t RCC_IT); #ifdef __cplusplus } #endif #endif /* __STM32F10x_RCC_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /** ****************************************************************************** * @file stm32f10x_rcc.h * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file contains all the functions prototypes for the RCC firmware * library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_RCC_H #define __STM32F10x_RCC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f10x.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @addtogroup RCC * @{ */ /** @defgroup RCC_Exported_Types * @{ */ typedef struct { uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */ uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */ uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */ uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */ uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */ }RCC_ClocksTypeDef; /** * @} */ /** @defgroup RCC_Exported_Constants * @{ */ /** @defgroup HSE_configuration * @{ */ #define RCC_HSE_OFF ((uint32_t)0x00000000) #define RCC_HSE_ON ((uint32_t)0x00010000) #define RCC_HSE_Bypass ((uint32_t)0x00040000) #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ ((HSE) == RCC_HSE_Bypass)) /** * @} */ /** @defgroup PLL_entry_clock_source * @{ */ #define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_CL) #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ ((SOURCE) == RCC_PLLSource_HSE_Div1) || \ ((SOURCE) == RCC_PLLSource_HSE_Div2)) #else #define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000) #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ ((SOURCE) == RCC_PLLSource_PREDIV1)) #endif /* STM32F10X_CL */ /** * @} */ /** @defgroup PLL_multiplication_factor * @{ */ #ifndef STM32F10X_CL #define RCC_PLLMul_2 ((uint32_t)0x00000000) #define RCC_PLLMul_3 ((uint32_t)0x00040000) #define RCC_PLLMul_4 ((uint32_t)0x00080000) #define RCC_PLLMul_5 ((uint32_t)0x000C0000) #define RCC_PLLMul_6 ((uint32_t)0x00100000) #define RCC_PLLMul_7 ((uint32_t)0x00140000) #define RCC_PLLMul_8 ((uint32_t)0x00180000) #define RCC_PLLMul_9 ((uint32_t)0x001C0000) #define RCC_PLLMul_10 ((uint32_t)0x00200000) #define RCC_PLLMul_11 ((uint32_t)0x00240000) #define RCC_PLLMul_12 ((uint32_t)0x00280000) #define RCC_PLLMul_13 ((uint32_t)0x002C0000) #define RCC_PLLMul_14 ((uint32_t)0x00300000) #define RCC_PLLMul_15 ((uint32_t)0x00340000) #define RCC_PLLMul_16 ((uint32_t)0x00380000) #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ ((MUL) == RCC_PLLMul_16)) #else #define RCC_PLLMul_4 ((uint32_t)0x00080000) #define RCC_PLLMul_5 ((uint32_t)0x000C0000) #define RCC_PLLMul_6 ((uint32_t)0x00100000) #define RCC_PLLMul_7 ((uint32_t)0x00140000) #define RCC_PLLMul_8 ((uint32_t)0x00180000) #define RCC_PLLMul_9 ((uint32_t)0x001C0000) #define RCC_PLLMul_6_5 ((uint32_t)0x00340000) #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ ((MUL) == RCC_PLLMul_6_5)) #endif /* STM32F10X_CL */ /** * @} */ /** @defgroup PREDIV1_division_factor * @{ */ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) #define RCC_PREDIV1_Div1 ((uint32_t)0x00000000) #define RCC_PREDIV1_Div2 ((uint32_t)0x00000001) #define RCC_PREDIV1_Div3 ((uint32_t)0x00000002) #define RCC_PREDIV1_Div4 ((uint32_t)0x00000003) #define RCC_PREDIV1_Div5 ((uint32_t)0x00000004) #define RCC_PREDIV1_Div6 ((uint32_t)0x00000005) #define RCC_PREDIV1_Div7 ((uint32_t)0x00000006) #define RCC_PREDIV1_Div8 ((uint32_t)0x00000007) #define RCC_PREDIV1_Div9 ((uint32_t)0x00000008) #define RCC_PREDIV1_Div10 ((uint32_t)0x00000009) #define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A) #define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B) #define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C) #define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D) #define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E) #define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F) #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \ ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \ ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \ ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \ ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \ ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) #endif /** * @} */ /** @defgroup PREDIV1_clock_source * @{ */ #ifdef STM32F10X_CL /* PREDIV1 clock source (for STM32 connectivity line devices) */ #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) #define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000) #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \ ((SOURCE) == RCC_PREDIV1_Source_PLL2)) #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) /* PREDIV1 clock source (for STM32 Value line devices) */ #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE)) #endif /** * @} */ #ifdef STM32F10X_CL /** @defgroup PREDIV2_division_factor * @{ */ #define RCC_PREDIV2_Div1 ((uint32_t)0x00000000) #define RCC_PREDIV2_Div2 ((uint32_t)0x00000010) #define RCC_PREDIV2_Div3 ((uint32_t)0x00000020) #define RCC_PREDIV2_Div4 ((uint32_t)0x00000030) #define RCC_PREDIV2_Div5 ((uint32_t)0x00000040) #define RCC_PREDIV2_Div6 ((uint32_t)0x00000050) #define RCC_PREDIV2_Div7 ((uint32_t)0x00000060) #define RCC_PREDIV2_Div8 ((uint32_t)0x00000070) #define RCC_PREDIV2_Div9 ((uint32_t)0x00000080) #define RCC_PREDIV2_Div10 ((uint32_t)0x00000090) #define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0) #define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0) #define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0) #define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0) #define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0) #define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0) #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \ ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \ ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \ ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \ ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \ ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \ ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \ ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16)) /** * @} */ /** @defgroup PLL2_multiplication_factor * @{ */ #define RCC_PLL2Mul_8 ((uint32_t)0x00000600) #define RCC_PLL2Mul_9 ((uint32_t)0x00000700) #define RCC_PLL2Mul_10 ((uint32_t)0x00000800) #define RCC_PLL2Mul_11 ((uint32_t)0x00000900) #define RCC_PLL2Mul_12 ((uint32_t)0x00000A00) #define RCC_PLL2Mul_13 ((uint32_t)0x00000B00) #define RCC_PLL2Mul_14 ((uint32_t)0x00000C00) #define RCC_PLL2Mul_16 ((uint32_t)0x00000E00) #define RCC_PLL2Mul_20 ((uint32_t)0x00000F00) #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \ ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \ ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \ ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \ ((MUL) == RCC_PLL2Mul_20)) /** * @} */ /** @defgroup PLL3_multiplication_factor * @{ */ #define RCC_PLL3Mul_8 ((uint32_t)0x00006000) #define RCC_PLL3Mul_9 ((uint32_t)0x00007000) #define RCC_PLL3Mul_10 ((uint32_t)0x00008000) #define RCC_PLL3Mul_11 ((uint32_t)0x00009000) #define RCC_PLL3Mul_12 ((uint32_t)0x0000A000) #define RCC_PLL3Mul_13 ((uint32_t)0x0000B000) #define RCC_PLL3Mul_14 ((uint32_t)0x0000C000) #define RCC_PLL3Mul_16 ((uint32_t)0x0000E000) #define RCC_PLL3Mul_20 ((uint32_t)0x0000F000) #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \ ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \ ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \ ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \ ((MUL) == RCC_PLL3Mul_20)) /** * @} */ #endif /* STM32F10X_CL */ /** @defgroup System_clock_source * @{ */ #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ ((SOURCE) == RCC_SYSCLKSource_HSE) || \ ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) /** * @} */ /** @defgroup AHB_clock_source * @{ */ #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) #define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ ((HCLK) == RCC_SYSCLK_Div512)) /** * @} */ /** @defgroup APB1_APB2_clock_source * @{ */ #define RCC_HCLK_Div1 ((uint32_t)0x00000000) #define RCC_HCLK_Div2 ((uint32_t)0x00000400) #define RCC_HCLK_Div4 ((uint32_t)0x00000500) #define RCC_HCLK_Div8 ((uint32_t)0x00000600) #define RCC_HCLK_Div16 ((uint32_t)0x00000700) #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ ((PCLK) == RCC_HCLK_Div16)) /** * @} */ /** @defgroup RCC_Interrupt_source * @{ */ #define RCC_IT_LSIRDY ((uint8_t)0x01) #define RCC_IT_LSERDY ((uint8_t)0x02) #define RCC_IT_HSIRDY ((uint8_t)0x04) #define RCC_IT_HSERDY ((uint8_t)0x08) #define RCC_IT_PLLRDY ((uint8_t)0x10) #define RCC_IT_CSS ((uint8_t)0x80) #ifndef STM32F10X_CL #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00)) #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00)) #else #define RCC_IT_PLL2RDY ((uint8_t)0x20) #define RCC_IT_PLL3RDY ((uint8_t)0x40) #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY)) #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00) #endif /* STM32F10X_CL */ /** * @} */ #ifndef STM32F10X_CL /** @defgroup USB_Device_clock_source * @{ */ #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00) #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \ ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) /** * @} */ #else /** @defgroup USB_OTG_FS_clock_source * @{ */ #define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00) #define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01) #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \ ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2)) /** * @} */ #endif /* STM32F10X_CL */ #ifdef STM32F10X_CL /** @defgroup I2S2_clock_source * @{ */ #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00) #define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01) #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \ ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO)) /** * @} */ /** @defgroup I2S3_clock_source * @{ */ #define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00) #define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01) #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \ ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO)) /** * @} */ #endif /* STM32F10X_CL */ /** @defgroup ADC_clock_source * @{ */ #define RCC_PCLK2_Div2 ((uint32_t)0x00000000) #define RCC_PCLK2_Div4 ((uint32_t)0x00004000) #define RCC_PCLK2_Div6 ((uint32_t)0x00008000) #define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) #define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \ ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) /** * @} */ /** @defgroup LSE_configuration * @{ */ #define RCC_LSE_OFF ((uint8_t)0x00) #define RCC_LSE_ON ((uint8_t)0x01) #define RCC_LSE_Bypass ((uint8_t)0x04) #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ ((LSE) == RCC_LSE_Bypass)) /** * @} */ /** @defgroup RTC_clock_source * @{ */ #define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) #define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ ((SOURCE) == RCC_RTCCLKSource_LSI) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) /** * @} */ /** @defgroup AHB_peripheral * @{ */ #define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) #define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) #define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) #define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) #define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) #ifndef STM32F10X_CL #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) #else #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000) #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000) #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000) #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000) #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00)) #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00)) #endif /* STM32F10X_CL */ /** * @} */ /** @defgroup APB2_peripheral * @{ */ #define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) #define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) #define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) #define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) #define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) #define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) #define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080) #define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100) #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) #define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) #define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) #define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) #define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000) #define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000) #define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000) #define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000) #define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) #define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) #define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000) #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00)) /** * @} */ /** @defgroup APB1_peripheral * @{ */ #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) #define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) #define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) #define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) #define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) #define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) #define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) #define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) #define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) #define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) #define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) #define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) #define RCC_APB1Periph_USB ((uint32_t)0x00800000) #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) #define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) #define RCC_APB1Periph_BKP ((uint32_t)0x08000000) #define RCC_APB1Periph_PWR ((uint32_t)0x10000000) #define RCC_APB1Periph_DAC ((uint32_t)0x20000000) #define RCC_APB1Periph_CEC ((uint32_t)0x40000000) #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00)) /** * @} */ /** @defgroup Clock_source_to_output_on_MCO_pin * @{ */ #define RCC_MCO_NoClock ((uint8_t)0x00) #define RCC_MCO_SYSCLK ((uint8_t)0x04) #define RCC_MCO_HSI ((uint8_t)0x05) #define RCC_MCO_HSE ((uint8_t)0x06) #define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) #ifndef STM32F10X_CL #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ ((MCO) == RCC_MCO_PLLCLK_Div2)) #else #define RCC_MCO_PLL2CLK ((uint8_t)0x08) #define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09) #define RCC_MCO_XT1 ((uint8_t)0x0A) #define RCC_MCO_PLL3CLK ((uint8_t)0x0B) #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \ ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \ ((MCO) == RCC_MCO_PLL3CLK)) #endif /* STM32F10X_CL */ /** * @} */ /** @defgroup RCC_Flag * @{ */ #define RCC_FLAG_HSIRDY ((uint8_t)0x21) #define RCC_FLAG_HSERDY ((uint8_t)0x31) #define RCC_FLAG_PLLRDY ((uint8_t)0x39) #define RCC_FLAG_LSERDY ((uint8_t)0x41) #define RCC_FLAG_LSIRDY ((uint8_t)0x61) #define RCC_FLAG_PINRST ((uint8_t)0x7A) #define RCC_FLAG_PORRST ((uint8_t)0x7B) #define RCC_FLAG_SFTRST ((uint8_t)0x7C) #define RCC_FLAG_IWDGRST ((uint8_t)0x7D) #define RCC_FLAG_WWDGRST ((uint8_t)0x7E) #define RCC_FLAG_LPWRRST ((uint8_t)0x7F) #ifndef STM32F10X_CL #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ ((FLAG) == RCC_FLAG_LPWRRST)) #else #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \ ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ ((FLAG) == RCC_FLAG_LPWRRST)) #endif /* STM32F10X_CL */ #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) /** * @} */ /** * @} */ /** @defgroup RCC_Exported_Macros * @{ */ /** * @} */ /** @defgroup RCC_Exported_Functions * @{ */ void RCC_DeInit(void); void RCC_HSEConfig(uint32_t RCC_HSE); ErrorStatus RCC_WaitForHSEStartUp(void); void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); void RCC_HSICmd(FunctionalState NewState); void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); void RCC_PLLCmd(FunctionalState NewState); #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div); #endif #ifdef STM32F10X_CL void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div); void RCC_PLL2Config(uint32_t RCC_PLL2Mul); void RCC_PLL2Cmd(FunctionalState NewState); void RCC_PLL3Config(uint32_t RCC_PLL3Mul); void RCC_PLL3Cmd(FunctionalState NewState); #endif /* STM32F10X_CL */ void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); uint8_t RCC_GetSYSCLKSource(void); void RCC_HCLKConfig(uint32_t RCC_SYSCLK); void RCC_PCLK1Config(uint32_t RCC_HCLK); void RCC_PCLK2Config(uint32_t RCC_HCLK); void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); #ifndef STM32F10X_CL void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); #else void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource); #endif /* STM32F10X_CL */ void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); #ifdef STM32F10X_CL void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource); void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource); #endif /* STM32F10X_CL */ void RCC_LSEConfig(uint8_t RCC_LSE); void RCC_LSICmd(FunctionalState NewState); void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); void RCC_RTCCLKCmd(FunctionalState NewState); void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); #ifdef STM32F10X_CL void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); #endif /* STM32F10X_CL */ void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); void RCC_BackupResetCmd(FunctionalState NewState); void RCC_ClockSecuritySystemCmd(FunctionalState NewState); void RCC_MCOConfig(uint8_t RCC_MCO); FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); void RCC_ClearFlag(void); ITStatus RCC_GetITStatus(uint8_t RCC_IT); void RCC_ClearITPendingBit(uint8_t RCC_IT); #ifdef __cplusplus } #endif #endif /* __STM32F10x_RCC_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ Diff truncated after the above file
src/bare_test/1.Led/stdlib/inc/stm32f10x_rtc.h src/bare_test/1.Led/stdlib/inc/stm32f10x_sdio.h src/bare_test/1.Led/stdlib/inc/stm32f10x_spi.h src/bare_test/1.Led/stdlib/inc/stm32f10x_tim.h src/bare_test/1.Led/stdlib/inc/stm32f10x_usart.h src/bare_test/1.Led/stdlib/inc/stm32f10x_wwdg.h src/bare_test/1.Led/stdlib/src/misc.c src/bare_test/1.Led/stdlib/src/stm32f10x_adc.c src/bare_test/1.Led/stdlib/src/stm32f10x_bkp.c src/bare_test/1.Led/stdlib/src/stm32f10x_can.c src/bare_test/1.Led/stdlib/src/stm32f10x_cec.c src/bare_test/1.Led/stdlib/src/stm32f10x_crc.c src/bare_test/1.Led/stdlib/src/stm32f10x_dac.c src/bare_test/1.Led/stdlib/src/stm32f10x_dbgmcu.c src/bare_test/1.Led/stdlib/src/stm32f10x_dma.c src/bare_test/1.Led/stdlib/src/stm32f10x_exti.c src/bare_test/1.Led/stdlib/src/stm32f10x_flash.c src/bare_test/1.Led/stdlib/src/stm32f10x_fsmc.c src/bare_test/1.Led/stdlib/src/stm32f10x_gpio.c src/bare_test/1.Led/stdlib/src/stm32f10x_i2c.c src/bare_test/1.Led/stdlib/src/stm32f10x_iwdg.c src/bare_test/1.Led/stdlib/src/stm32f10x_pwr.c src/bare_test/1.Led/stdlib/src/stm32f10x_rcc.c src/bare_test/1.Led/stdlib/src/stm32f10x_rtc.c src/bare_test/1.Led/stdlib/src/stm32f10x_sdio.c src/bare_test/1.Led/stdlib/src/stm32f10x_spi.c src/bare_test/1.Led/stdlib/src/stm32f10x_tim.c src/bare_test/1.Led/stdlib/src/stm32f10x_usart.c src/bare_test/1.Led/stdlib/src/stm32f10x_wwdg.c src/bare_test/1.Led/stm32v5_led.uvgui.Think src/bare_test/1.Led/stm32v5_led.uvopt src/bare_test/1.Led/stm32v5_led.uvproj src/bare_test/1.Led/user/main.c src/bare_test/1.Led/user/stm32v5_led.c src/bare_test/1.Led/user/stm32v5_led.h src/bare_test/2.Key/JLinkSettings.ini src/bare_test/2.Key/cmsis/core_cm3.c src/bare_test/2.Key/cmsis/core_cm3.h src/bare_test/2.Key/cmsis/startup_stm32f10x_hd.s src/bare_test/2.Key/cmsis/stm32f10x.h src/bare_test/2.Key/cmsis/stm32f10x_conf.h src/bare_test/2.Key/cmsis/system_stm32f10x.c src/bare_test/2.Key/cmsis/system_stm32f10x.h src/bare_test/2.Key/keil_clean.bat src/bare_test/2.Key/stdlib/inc/misc.h src/bare_test/2.Key/stdlib/inc/stm32f10x_adc.h src/bare_test/2.Key/stdlib/inc/stm32f10x_bkp.h src/bare_test/2.Key/stdlib/inc/stm32f10x_can.h src/bare_test/2.Key/stdlib/inc/stm32f10x_cec.h src/bare_test/2.Key/stdlib/inc/stm32f10x_crc.h src/bare_test/2.Key/stdlib/inc/stm32f10x_dac.h src/bare_test/2.Key/stdlib/inc/stm32f10x_dbgmcu.h src/bare_test/2.Key/stdlib/inc/stm32f10x_dma.h src/bare_test/2.Key/stdlib/inc/stm32f10x_exti.h src/bare_test/2.Key/stdlib/inc/stm32f10x_flash.h src/bare_test/2.Key/stdlib/inc/stm32f10x_fsmc.h src/bare_test/2.Key/stdlib/inc/stm32f10x_gpio.h src/bare_test/2.Key/stdlib/inc/stm32f10x_i2c.h src/bare_test/2.Key/stdlib/inc/stm32f10x_iwdg.h src/bare_test/2.Key/stdlib/inc/stm32f10x_pwr.h src/bare_test/2.Key/stdlib/inc/stm32f10x_rcc.h src/bare_test/2.Key/stdlib/inc/stm32f10x_rtc.h src/bare_test/2.Key/stdlib/inc/stm32f10x_sdio.h src/bare_test/2.Key/stdlib/inc/stm32f10x_spi.h src/bare_test/2.Key/stdlib/inc/stm32f10x_tim.h src/bare_test/2.Key/stdlib/inc/stm32f10x_usart.h src/bare_test/2.Key/stdlib/inc/stm32f10x_wwdg.h src/bare_test/2.Key/stdlib/src/misc.c src/bare_test/2.Key/stdlib/src/stm32f10x_adc.c src/bare_test/2.Key/stdlib/src/stm32f10x_bkp.c src/bare_test/2.Key/stdlib/src/stm32f10x_can.c src/bare_test/2.Key/stdlib/src/stm32f10x_cec.c src/bare_test/2.Key/stdlib/src/stm32f10x_crc.c src/bare_test/2.Key/stdlib/src/stm32f10x_dac.c src/bare_test/2.Key/stdlib/src/stm32f10x_dbgmcu.c src/bare_test/2.Key/stdlib/src/stm32f10x_dma.c src/bare_test/2.Key/stdlib/src/stm32f10x_exti.c src/bare_test/2.Key/stdlib/src/stm32f10x_flash.c src/bare_test/2.Key/stdlib/src/stm32f10x_fsmc.c src/bare_test/2.Key/stdlib/src/stm32f10x_gpio.c src/bare_test/2.Key/stdlib/src/stm32f10x_i2c.c src/bare_test/2.Key/stdlib/src/stm32f10x_iwdg.c src/bare_test/2.Key/stdlib/src/stm32f10x_pwr.c src/bare_test/2.Key/stdlib/src/stm32f10x_rcc.c src/bare_test/2.Key/stdlib/src/stm32f10x_rtc.c src/bare_test/2.Key/stdlib/src/stm32f10x_sdio.c src/bare_test/2.Key/stdlib/src/stm32f10x_spi.c src/bare_test/2.Key/stdlib/src/stm32f10x_tim.c src/bare_test/2.Key/stdlib/src/stm32f10x_usart.c src/bare_test/2.Key/stdlib/src/stm32f10x_wwdg.c src/bare_test/2.Key/stm32v5_key.uvgui.Think src/bare_test/2.Key/stm32v5_key.uvopt src/bare_test/2.Key/stm32v5_key.uvproj src/bare_test/2.Key/user/main.c src/bare_test/2.Key/user/stm32v5_key.c src/bare_test/2.Key/user/stm32v5_key.h src/bare_test/2.Key/user/stm32v5_led.c src/bare_test/2.Key/user/stm32v5_led.h src/bare_test/4.Systick/JLinkSettings.ini src/bare_test/4.Systick/cmsis/core_cm3.c src/bare_test/4.Systick/cmsis/core_cm3.h src/bare_test/4.Systick/cmsis/startup_stm32f10x_hd.s src/bare_test/4.Systick/cmsis/stm32f10x.h src/bare_test/4.Systick/cmsis/stm32f10x_conf.h src/bare_test/4.Systick/cmsis/stm32f10x_it.c src/bare_test/4.Systick/cmsis/stm32f10x_it.h src/bare_test/4.Systick/cmsis/system_stm32f10x.c src/bare_test/4.Systick/cmsis/system_stm32f10x.h src/bare_test/4.Systick/keil_clean.bat src/bare_test/4.Systick/stdlib/inc/misc.h src/bare_test/4.Systick/stdlib/inc/stm32f10x_adc.h src/bare_test/4.Systick/stdlib/inc/stm32f10x_bkp.h src/bare_test/4.Systick/stdlib/inc/stm32f10x_can.h src/bare_test/4.Systick/stdlib/inc/stm32f10x_cec.h src/bare_test/4.Systick/stdlib/inc/stm32f10x_crc.h src/bare_test/4.Systick/stdlib/inc/stm32f10x_dac.h src/bare_test/4.Systick/stdlib/inc/stm32f10x_dbgmcu.h src/bare_test/4.Systick/stdlib/inc/stm32f10x_dma.h src/bare_test/4.Systick/stdlib/inc/stm32f10x_exti.h src/bare_test/4.Systick/stdlib/inc/stm32f10x_flash.h src/bare_test/4.Systick/stdlib/inc/stm32f10x_fsmc.h src/bare_test/4.Systick/stdlib/inc/stm32f10x_gpio.h src/bare_test/4.Systick/stdlib/inc/stm32f10x_i2c.h src/bare_test/4.Systick/stdlib/inc/stm32f10x_iwdg.h src/bare_test/4.Systick/stdlib/inc/stm32f10x_pwr.h src/bare_test/4.Systick/stdlib/inc/stm32f10x_rcc.h src/bare_test/4.Systick/stdlib/inc/stm32f10x_rtc.h src/bare_test/4.Systick/stdlib/inc/stm32f10x_sdio.h src/bare_test/4.Systick/stdlib/inc/stm32f10x_spi.h src/bare_test/4.Systick/stdlib/inc/stm32f10x_tim.h src/bare_test/4.Systick/stdlib/inc/stm32f10x_usart.h src/bare_test/4.Systick/stdlib/inc/stm32f10x_wwdg.h src/bare_test/4.Systick/stdlib/src/misc.c src/bare_test/4.Systick/stdlib/src/stm32f10x_adc.c src/bare_test/4.Systick/stdlib/src/stm32f10x_bkp.c src/bare_test/4.Systick/stdlib/src/stm32f10x_can.c src/bare_test/4.Systick/stdlib/src/stm32f10x_cec.c src/bare_test/4.Systick/stdlib/src/stm32f10x_crc.c src/bare_test/4.Systick/stdlib/src/stm32f10x_dac.c src/bare_test/4.Systick/stdlib/src/stm32f10x_dbgmcu.c src/bare_test/4.Systick/stdlib/src/stm32f10x_dma.c src/bare_test/4.Systick/stdlib/src/stm32f10x_exti.c src/bare_test/4.Systick/stdlib/src/stm32f10x_flash.c src/bare_test/4.Systick/stdlib/src/stm32f10x_fsmc.c src/bare_test/4.Systick/stdlib/src/stm32f10x_gpio.c src/bare_test/4.Systick/stdlib/src/stm32f10x_i2c.c src/bare_test/4.Systick/stdlib/src/stm32f10x_iwdg.c src/bare_test/4.Systick/stdlib/src/stm32f10x_pwr.c src/bare_test/4.Systick/stdlib/src/stm32f10x_rcc.c src/bare_test/4.Systick/stdlib/src/stm32f10x_rtc.c src/bare_test/4.Systick/stdlib/src/stm32f10x_sdio.c src/bare_test/4.Systick/stdlib/src/stm32f10x_spi.c src/bare_test/4.Systick/stdlib/src/stm32f10x_tim.c src/bare_test/4.Systick/stdlib/src/stm32f10x_usart.c src/bare_test/4.Systick/stdlib/src/stm32f10x_wwdg.c src/bare_test/4.Systick/stm32v5_systick.uvgui.Think src/bare_test/4.Systick/stm32v5_systick.uvopt src/bare_test/4.Systick/stm32v5_systick.uvproj src/bare_test/4.Systick/user/main.c src/bare_test/4.Systick/user/stm32v5_led.c src/bare_test/4.Systick/user/stm32v5_led.h src/bare_test/4.Systick/user/stm32v5_systick.c src/bare_test/4.Systick/user/stm32v5_systick.h src/bare_test/4.Systick/user/stm32v5_usart.c src/bare_test/4.Systick/user/stm32v5_usart.h src/bare_test/stm32_key/board/stm32v5_key.c (deleted) src/bare_test/stm32_key/board/stm32v5_key.h (deleted) src/bare_test/stm32_key/board/stm32v5_led.h (deleted) src/bare_test/stm32_key/fwlib/inc/stm32f10x_conf.h (deleted) src/bare_test/stm32_key/fwlib/src/system_stm32f10x.c (deleted) src/bare_test/stm32_key/main/main.c (deleted) src/bare_test/stm32_key/stm32_interrupt.uvproj (deleted) src/bare_test/stm32_led/JLinkSettings.ini (deleted) src/bare_test/stm32_led/asm/startup_stm32f10x_hd.s (deleted) src/bare_test/stm32_led/cmsis/core_cm3.c (deleted) src/bare_test/stm32_led/cmsis/core_cm3.h (deleted) src/bare_test/stm32_led/cmsis/stm32f10x.h (deleted) src/bare_test/stm32_led/cmsis/system_stm32f10x.c (deleted) src/bare_test/stm32_led/cmsis/system_stm32f10x.h (deleted) src/bare_test/stm32_led/fwlib/inc/misc.h (deleted) src/bare_test/stm32_led/fwlib/inc/stm32f10x_adc.h (deleted) src/bare_test/stm32_led/fwlib/inc/stm32f10x_bkp.h (deleted) src/bare_test/stm32_led/fwlib/inc/stm32f10x_can.h (deleted) src/bare_test/stm32_led/fwlib/inc/stm32f10x_cec.h (deleted) src/bare_test/stm32_led/fwlib/inc/stm32f10x_conf.h (deleted) src/bare_test/stm32_led/fwlib/inc/stm32f10x_crc.h (deleted) src/bare_test/stm32_led/fwlib/inc/stm32f10x_dac.h (deleted) src/bare_test/stm32_led/fwlib/inc/stm32f10x_dbgmcu.h (deleted) src/bare_test/stm32_led/fwlib/inc/stm32f10x_dma.h (deleted) src/bare_test/stm32_led/fwlib/inc/stm32f10x_exti.h (deleted) src/bare_test/stm32_led/fwlib/inc/stm32f10x_flash.h (deleted) src/bare_test/stm32_led/fwlib/inc/stm32f10x_fsmc.h (deleted) src/bare_test/stm32_led/fwlib/inc/stm32f10x_gpio.h (deleted) src/bare_test/stm32_led/fwlib/inc/stm32f10x_i2c.h (deleted) src/bare_test/stm32_led/fwlib/inc/stm32f10x_iwdg.h (deleted) src/bare_test/stm32_led/fwlib/inc/stm32f10x_pwr.h (deleted) src/bare_test/stm32_led/fwlib/inc/stm32f10x_rcc.h (deleted) src/bare_test/stm32_led/fwlib/inc/stm32f10x_rtc.h (deleted) src/bare_test/stm32_led/fwlib/inc/stm32f10x_sdio.h (deleted) src/bare_test/stm32_led/fwlib/inc/stm32f10x_spi.h (deleted) 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