From 94101a2cd9baed60360f68096033dc75cbb1dcb3 Mon Sep 17 00:00:00 2001
From: android <android@lingyun.com>
Date: Wed, 10 Jul 2024 19:27:36 +0800
Subject: [PATCH] Add STM8S003F3 eDP LCD drvier
---
mcu_sdk/stm8s003f3_edp/Libraries/STM8S_StdPeriph_Driver/src/LT8911EXB.c | 860 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 860 insertions(+), 0 deletions(-)
diff --git a/mcu_sdk/stm8s003f3_edp/Libraries/STM8S_StdPeriph_Driver/src/LT8911EXB.c b/mcu_sdk/stm8s003f3_edp/Libraries/STM8S_StdPeriph_Driver/src/LT8911EXB.c
new file mode 100644
index 0000000..5fa200e
--- /dev/null
+++ b/mcu_sdk/stm8s003f3_edp/Libraries/STM8S_StdPeriph_Driver/src/LT8911EXB.c
@@ -0,0 +1,860 @@
+#include "LT8911EXB.h"
+
+u8 Swing_Setting1[] = { 0x83, 0x82, 0x82, 0x82, 0x82, 0x82, 0x82, 0x82, 0x81, 0x80, 0x80, 0x80, 0x80 };
+u8 Swing_Setting2[] = { 0x00, 0xe0, 0xc0, 0xa0, 0x80, 0x40, 0x20, 0x00, 0x00, 0xe0, 0xc0, 0xa0, 0x80 };
+u8 Level = _Level7_;
+bool ScrambleMode = 0;
+bool flag_mipi_on = 0;
+#ifdef _read_edid_
+u8 EDID_DATA[128] = { 0 };
+u16 EDID_Timing[11] = { 0 };
+bool EDID_Reply = 0;
+#endif
+
+
+void LT8911EXB_GPIO_Init(void)
+{
+ GPIO_Init(GPIOA,GPIO_PIN_1,GPIO_MODE_OUT_PP_LOW_FAST);
+ GPIO_Init(GPIOC,GPIO_PIN_7,GPIO_MODE_OUT_PP_LOW_FAST);
+ GPIO_Init(GPIOC,GPIO_PIN_6,GPIO_MODE_OUT_PP_LOW_FAST);
+}
+
+void Reset_LT8911EXB( void )
+{
+ _LT8911_RSTN_LOW; // GPIO Low
+ TIMDelay_Nms( 110 );
+ _LT8911_RSTN_High; // GPIO High
+ TIMDelay_Nms( 110 );
+}
+
+void LT8911EX_ChipID( void ) // read Chip ID
+{
+// Debug_Printf( "\r\n###################start#####################" );
+ gpio_i2c_write( 0x52,0xff,0x81); //register bank
+
+ gpio_i2c_write( 0x52,0x08,0x7f);
+
+#ifdef _uart_debug_
+ uart_send_hex(gpio_i2c_read(0x52,0x00));
+ uart_send_hex(gpio_i2c_read(0x52,0x01));
+ uart_send_hex(gpio_i2c_read(0x52,0x02));
+#endif
+}
+void LT8911EXB_MIPI_Video_Timing( void ) // ( struct video_timing *video_format )
+{
+ gpio_i2c_write(0x52, 0xff, 0xd0 );
+ gpio_i2c_write(0x52, 0x0d, (u8)( MIPI_Timing[vtotal] / 256 ) );
+ gpio_i2c_write(0x52, 0x0e, (u8)( MIPI_Timing[vtotal] % 256 ) ); //vtotal
+ gpio_i2c_write(0x52, 0x0f, (u8)( MIPI_Timing[vact] / 256 ) );
+ gpio_i2c_write(0x52, 0x10, (u8)( MIPI_Timing[vact] % 256 ) ); //vactive
+
+ gpio_i2c_write(0x52, 0x11, (u8)( MIPI_Timing[htotal] / 256 ) );
+ gpio_i2c_write(0x52, 0x12, (u8)( MIPI_Timing[htotal] % 256 ) ); //htotal
+ gpio_i2c_write(0x52, 0x13, (u8)( MIPI_Timing[hact] / 256 ) );
+ gpio_i2c_write(0x52, 0x14, (u8)( MIPI_Timing[hact] % 256 ) ); //hactive
+
+ gpio_i2c_write(0x52, 0x15, (u8)( MIPI_Timing[vs] % 256 ) ); //vsa
+ gpio_i2c_write(0x52, 0x16, (u8)( MIPI_Timing[hs] % 256 ) ); //hsa
+ gpio_i2c_write(0x52, 0x17, (u8)( MIPI_Timing[vfp] / 256 ) );
+ gpio_i2c_write(0x52, 0x18, (u8)( MIPI_Timing[vfp] % 256 ) ); //vfp
+
+ gpio_i2c_write(0x52, 0x19, (u8)( MIPI_Timing[hfp] / 256 ) );
+ gpio_i2c_write(0x52, 0x1a, (u8)( MIPI_Timing[hfp] % 256 ) ); //hfp
+}
+
+void LT8911EXB_eDP_Video_cfg( void ) // ( struct video_timing *video_format )
+{
+ gpio_i2c_write( 0x52,0xff, 0xa8 );
+ gpio_i2c_write( 0x52,0x2d, 0x88 ); // MSA from register
+
+ gpio_i2c_write( 0x52,0x05, (u8)( MIPI_Timing[htotal] / 256 ) );
+ gpio_i2c_write( 0x52,0x06, (u8)( MIPI_Timing[htotal] % 256 ) );
+ gpio_i2c_write( 0x52,0x07, (u8)( ( MIPI_Timing[hs] + MIPI_Timing[hbp] ) / 256 ) );
+ gpio_i2c_write( 0x52,0x08, (u8)( ( MIPI_Timing[hs] + MIPI_Timing[hbp] ) % 256 ) );
+ gpio_i2c_write( 0x52,0x09, (u8)( MIPI_Timing[hs] / 256 ) );
+ gpio_i2c_write( 0x52,0x0a, (u8)( MIPI_Timing[hs] % 256 ) );
+ gpio_i2c_write( 0x52,0x0b, (u8)( MIPI_Timing[hact] / 256 ) );
+ gpio_i2c_write( 0x52,0x0c, (u8)( MIPI_Timing[hact] % 256 ) );
+ gpio_i2c_write( 0x52,0x0d, (u8)( MIPI_Timing[vtotal] / 256 ) );
+ gpio_i2c_write( 0x52,0x0e, (u8)( MIPI_Timing[vtotal] % 256 ) );
+ gpio_i2c_write( 0x52,0x11, (u8)( ( MIPI_Timing[vs] + MIPI_Timing[vbp] ) / 256 ) );
+ gpio_i2c_write( 0x52,0x12, (u8)( ( MIPI_Timing[vs] + MIPI_Timing[vbp] ) % 256 ) );
+ gpio_i2c_write( 0x52,0x14, (u8)( MIPI_Timing[vs] % 256 ) );
+ gpio_i2c_write( 0x52,0x15, (u8)( MIPI_Timing[vact] / 256 ) );
+ gpio_i2c_write( 0x52,0x16, (u8)( MIPI_Timing[vact] % 256 ) );
+
+}
+
+void LT8911EXB_init( void )
+{
+ u8 i;
+ u8 pcr_pll_postdiv;
+ u8 pcr_m;
+ u16 Temp16;
+
+ /* init */
+ gpio_i2c_write(0x52, 0xff, 0x81 ); // Change Reg bank
+ gpio_i2c_write(0x52, 0x08, 0x7f ); // i2c over aux issue
+ gpio_i2c_write(0x52, 0x49, 0xff ); // enable 0x87xx
+
+ gpio_i2c_write(0x52, 0xff, 0x82 ); // Change Reg bank
+ gpio_i2c_write(0x52, 0x5a, 0x0e ); // GPIO test output
+
+ //for power consumption//
+ gpio_i2c_write(0x52, 0xff, 0x81 );
+ gpio_i2c_write(0x52, 0x05, 0x06 );
+ gpio_i2c_write(0x52, 0x43, 0x00 );
+ gpio_i2c_write(0x52, 0x44, 0x1f );
+ #if( eDP_lane == 4)
+ gpio_i2c_write(0x52, 0x45, 0xff );
+ gpio_i2c_write(0x52, 0x46, 0xfe );
+ #else
+ gpio_i2c_write(0x52, 0x45, 0xf7 );
+ gpio_i2c_write(0x52, 0x46, 0xf6 );
+ #endif
+ gpio_i2c_write(0x52, 0x49, 0x7f );
+
+ gpio_i2c_write(0x52, 0xff, 0x82 );
+ #if( eDP_lane == 2) // 2 lane eDP
+ {
+ gpio_i2c_write(0x52, 0x12, 0x33 );
+ }
+ #elif( eDP_lane == 1) // 1 lane eDP
+ {
+ gpio_i2c_write(0x52, 0x12, 0x11 );
+ }
+ #elif( eDP_lane == 4) // 4 lane eDP
+ {
+ gpio_i2c_write(0x52, 0x12, 0xff );
+ }
+
+#endif
+
+ /* mipi Rx analog */
+ gpio_i2c_write(0x52, 0xff, 0x82 ); // Change Reg bank
+ gpio_i2c_write(0x52, 0x32, 0x51 );
+ gpio_i2c_write(0x52, 0x35, 0x22 ); //EQ current 0x22/0x42/0x62/0x82/0xA2/0xC2/0xe2
+ gpio_i2c_write(0x52, 0x3a, 0x77 ); //EQ 12.5db
+ gpio_i2c_write(0x52, 0x3b, 0x77 ); //EQ 12.5db
+
+ gpio_i2c_write(0x52, 0x4c, 0x0c );
+ gpio_i2c_write(0x52, 0x4d, 0x00 );
+
+ /* dessc_pcr pll analog */
+ gpio_i2c_write(0x52, 0xff, 0x82 ); // Change Reg bank
+ gpio_i2c_write(0x52, 0x6a, 0x40 );
+ gpio_i2c_write(0x52, 0x6b, PCR_PLL_PREDIV );
+
+ Temp16 = MIPI_Timing[pclk_10khz];
+
+ if( MIPI_Timing[pclk_10khz] < 8800 )
+ {
+ gpio_i2c_write(0x52, 0x6e, 0x82 ); //0x44:pre-div = 2 ,pixel_clk=44~ 88MHz
+ pcr_pll_postdiv = 0x08;
+ }else
+ if( MIPI_Timing[pclk_10khz] < 17600 )
+ {
+ gpio_i2c_write(0x52, 0x6e, 0x81 ); //0x40:pre-div = 1, pixel_clk =88~176MHz
+ pcr_pll_postdiv = 0x04;
+ }else
+ {
+ gpio_i2c_write(0x52, 0x6e, 0x80 ); //0x40:pre-div = 0, pixel_clk =176~200MHz
+ pcr_pll_postdiv = 0x02;
+ }
+
+ pcr_m = (u8)( Temp16 * pcr_pll_postdiv / 25 / 100 );
+
+ /* dessc pll digital */
+ gpio_i2c_write(0x52, 0xff, 0x85 ); // Change Reg bank
+ gpio_i2c_write(0x52, 0xa9, 0x31 );
+ gpio_i2c_write(0x52, 0xaa, 0x17 );
+ gpio_i2c_write(0x52, 0xab, 0xba );
+ gpio_i2c_write(0x52, 0xac, 0xe1 );
+ gpio_i2c_write(0x52, 0xad, 0x47 );
+ gpio_i2c_write(0x52, 0xae, 0x01 );
+ gpio_i2c_write(0x52, 0xae, 0x11 );
+
+ /* Digital Top */
+ gpio_i2c_write(0x52, 0xff, 0x85 ); // Change Reg bank
+ gpio_i2c_write(0x52, 0xc0, 0x01 ); //select mipi Rx
+#ifdef _6bit_
+ gpio_i2c_write(0x52, 0xb0, 0xd0 ); //enable dither
+#else
+ gpio_i2c_write(0x52, 0xb0, 0x00 ); // disable dither
+#endif
+
+ /* mipi Rx Digital */
+ gpio_i2c_write(0x52, 0xff, 0xd0 ); // Change Reg bank
+ gpio_i2c_write(0x52, 0x00, _MIPI_data_PN_ + _MIPI_Lane_ % 4 ); // 0: 4 Lane / 1: 1 Lane / 2 : 2 Lane / 3: 3 Lane
+ gpio_i2c_write(0x52, 0x02, 0x08 ); //settle
+ gpio_i2c_write(0x52, 0x03, _MIPI_data_sequence_ ); // default is 0x00
+ gpio_i2c_write(0x52, 0x08, 0x00 );
+// gpio_i2c_write(0x52, 0x0a, 0x12 ); //pcr mode
+
+ gpio_i2c_write(0x52, 0x0c, 0x80 ); //fifo position
+ gpio_i2c_write(0x52, 0x1c, 0x80 ); //fifo position
+
+ // hs mode:MIPI�в�����vs mode:MIPI֡����
+ gpio_i2c_write(0x52, 0x24, 0x70 ); // 0x30 [3:0] line limit //pcr mode( de hs vs)
+
+ gpio_i2c_write(0x52, 0x31, 0x0a );
+
+ /*stage1 hs mode*/
+ gpio_i2c_write(0x52, 0x25, 0x90 ); // 0x80 // line limit
+ gpio_i2c_write(0x52, 0x2a, 0x3a ); // 0x04 // step in limit
+ gpio_i2c_write(0x52, 0x21, 0x4f ); // hs_step
+ gpio_i2c_write(0x52, 0x22, 0xff );
+
+ /*stage2 de mode*/
+ gpio_i2c_write(0x52, 0x0a, 0x02 ); //de adjust pre line
+ gpio_i2c_write(0x52, 0x38, 0x02 ); //de_threshold 1
+ gpio_i2c_write(0x52, 0x39, 0x04 ); //de_threshold 2
+ gpio_i2c_write(0x52, 0x3a, 0x08 ); //de_threshold 3
+ gpio_i2c_write(0x52, 0x3b, 0x10 ); //de_threshold 4
+
+ gpio_i2c_write(0x52, 0x3f, 0x04 ); //de_step 1
+ gpio_i2c_write(0x52, 0x40, 0x08 ); //de_step 2
+ gpio_i2c_write(0x52, 0x41, 0x10 ); //de_step 3
+ gpio_i2c_write(0x52, 0x42, 0x60 ); //de_step 4
+
+ /*stage2 hs mode*/
+ gpio_i2c_write(0x52, 0x1e, 0x01 ); // 0x11
+ gpio_i2c_write(0x52, 0x23, 0xf0 ); // 0x80 //
+
+ gpio_i2c_write(0x52, 0x2b, 0x80 ); // 0xa0
+
+#ifdef _Test_Pattern_
+ gpio_i2c_write(0x52, 0x26, ( pcr_m | 0x80 ) );
+#else
+
+ gpio_i2c_write(0x52, 0x26, pcr_m );
+
+// gpio_i2c_write(0x52, 0x27, Read_0xD095 );
+// gpio_i2c_write(0x52, 0x28, Read_0xD096 );
+#endif
+
+ LT8911EXB_MIPI_Video_Timing( ); //defualt setting is 1080P
+
+ gpio_i2c_write(0x52, 0xff, 0x81 ); // Change Reg bank
+ gpio_i2c_write(0x52, 0x03, 0x7b ); //PCR reset
+ gpio_i2c_write(0x52, 0x03, 0xff );
+
+#ifdef _eDP_2G7_
+ gpio_i2c_write(0x52, 0xff, 0x87 );
+ gpio_i2c_write(0x52, 0x19, 0x31 );
+// gpio_i2c_write(0x52, 0x1a, 0x36 ); // sync m
+ gpio_i2c_write(0x52,0x1a,0x1b);
+ gpio_i2c_write(0x52, 0x1b, 0x00 ); // sync_k [7:0]
+ gpio_i2c_write(0x52, 0x1c, 0x00 ); // sync_k [13:8]
+
+ // txpll Analog
+ gpio_i2c_write(0x52, 0xff, 0x82 );
+ gpio_i2c_write(0x52, 0x09, 0x00 ); // div hardware mode, for ssc.
+
+// gpio_i2c_write(0x52, 0x01, 0x18 );// default : 0x18
+ gpio_i2c_write(0x52, 0x02, 0x42 );
+ gpio_i2c_write(0x52, 0x03, 0x00 ); // txpll en = 0
+ gpio_i2c_write(0x52, 0x03, 0x01 ); // txpll en = 1
+// gpio_i2c_write(0x52, 0x04, 0x3a );// default : 0x3A
+ gpio_i2c_write(0x52,0x0a,0x1b);
+ gpio_i2c_write(0x52,0x04,0x2a);
+
+ gpio_i2c_write(0x52, 0xff, 0x87 );
+ gpio_i2c_write(0x52, 0x0c, 0x10 ); // cal en = 0
+
+ gpio_i2c_write(0x52, 0xff, 0x81 );
+ gpio_i2c_write(0x52, 0x09, 0xfc );
+ gpio_i2c_write(0x52, 0x09, 0xfd );
+
+ gpio_i2c_write(0x52, 0xff, 0x87 );
+ gpio_i2c_write(0x52, 0x0c, 0x11 ); // cal en = 1
+
+ // ssc
+ gpio_i2c_write(0x52, 0xff, 0x87 );
+ gpio_i2c_write(0x52, 0x13, 0x83 );
+ gpio_i2c_write(0x52, 0x14, 0x41 );
+ gpio_i2c_write(0x52, 0x16, 0x0a );
+ gpio_i2c_write(0x52, 0x18, 0x0a );
+ gpio_i2c_write(0x52, 0x19, 0x33 );
+#endif
+
+#ifdef _eDP_1G62_
+ gpio_i2c_write(0x52, 0xff, 0x87 );
+ gpio_i2c_write(0x52, 0x19, 0x31 );
+ gpio_i2c_write(0x52, 0x1a, 0x20 ); // sync m
+ gpio_i2c_write(0x52, 0x1b, 0x19 ); // sync_k [7:0]
+ gpio_i2c_write(0x52, 0x1c, 0x99 ); // sync_k [13:8]
+
+ // txpll Analog
+ gpio_i2c_write(0x52, 0xff, 0x82 );
+ gpio_i2c_write(0x52, 0x09, 0x00 ); // div hardware mode, for ssc.
+ // gpio_i2c_write(0x52, 0x01, 0x18 );// default : 0x18
+ gpio_i2c_write(0x52, 0x02, 0x42 );
+ gpio_i2c_write(0x52, 0x03, 0x00 ); // txpll en = 0
+ gpio_i2c_write(0x52, 0x03, 0x01 ); // txpll en = 1
+ // gpio_i2c_write(0x52, 0x04, 0x3a );// default : 0x3A
+
+ gpio_i2c_write(0x52, 0xff, 0x87 );
+ gpio_i2c_write(0x52, 0x0c, 0x10 ); // cal en = 0
+
+ gpio_i2c_write(0x52, 0xff, 0x81 );
+ gpio_i2c_write(0x52, 0x09, 0xfc );
+ gpio_i2c_write(0x52, 0x09, 0xfd );
+
+ gpio_i2c_write(0x52, 0xff, 0x87 );
+ gpio_i2c_write(0x52, 0x0c, 0x11 ); // cal en = 1
+
+ //ssc
+ gpio_i2c_write(0x52, 0xff, 0x87 );
+ gpio_i2c_write(0x52, 0x13, 0x83 );
+ gpio_i2c_write(0x52, 0x14, 0x41 );
+ gpio_i2c_write(0x52, 0x16, 0x0a );
+ gpio_i2c_write(0x52, 0x18, 0x0a );
+ gpio_i2c_write(0x52, 0x19, 0x33 );
+#endif
+
+ gpio_i2c_write(0x52, 0xff, 0x87 );
+
+ for( i = 0; i < 5; i++ ) //Check Tx PLL
+ {
+ TIMDelay_Nms( 6 );
+ if( gpio_i2c_read( 0X52,0x37 ) & 0x02 )
+ {
+ uart_send_string("LT8911 tx pll locked" );
+ uart_send_char('\r');
+ uart_send_char('\n');
+ gpio_i2c_write(0x52,0xff,0x87);
+ gpio_i2c_write(0x52,0x1a,0x36);
+ gpio_i2c_write(0x52,0xff,0x82);
+ gpio_i2c_write(0x52,0x0a,0x36);
+ gpio_i2c_write(0x52,0x04,0x3a);
+ break;
+ }else
+ {
+ uart_send_string( "LT8911 tx pll unlocked" );
+ uart_send_char('\r');
+ uart_send_char('\n');
+ gpio_i2c_write(0x52, 0xff, 0x81 );
+ gpio_i2c_write(0x52, 0x09, 0xfc );
+ gpio_i2c_write(0x52, 0x09, 0xfd );
+
+ gpio_i2c_write(0x52, 0xff, 0x87 );
+ gpio_i2c_write(0x52, 0x0c, 0x10 );
+ gpio_i2c_write(0x52, 0x0c, 0x11 );
+ }
+ }
+
+ gpio_i2c_write(0x52, 0xff, 0xac ); // Change Reg bank
+ gpio_i2c_write(0x52, 0x15, _eDP_data_sequence_ ); // eDP data swap
+ gpio_i2c_write(0x52, 0x16, _eDP_data_PN_); // eDP P / N swap
+
+ // AUX reset
+ gpio_i2c_write(0x52, 0xff, 0x81 ); // Change Reg bank
+ gpio_i2c_write(0x52, 0x07, 0xfe );
+ gpio_i2c_write(0x52, 0x07, 0xff );
+ gpio_i2c_write(0x52, 0x0a, 0xfc );
+ gpio_i2c_write(0x52, 0x0a, 0xfe );
+
+ /* tx phy */
+ gpio_i2c_write(0x52, 0xff, 0x82 ); // Change Reg bank
+ gpio_i2c_write(0x52, 0x11, 0x00 );
+ gpio_i2c_write(0x52, 0x13, 0x10 );
+ gpio_i2c_write(0x52, 0x14, 0x0c );
+ gpio_i2c_write(0x52, 0x14, 0x08 );
+ gpio_i2c_write(0x52, 0x13, 0x20 );
+
+ gpio_i2c_write(0x52, 0xff, 0x82 ); // Change Reg bank
+ gpio_i2c_write(0x52, 0x0e, 0x35 );
+// gpio_i2c_write(0x52, 0x12, 0xff );
+// gpio_i2c_write(0x52, 0xff, 0x80 );
+// gpio_i2c_write(0x52, 0x40, 0x22 );
+
+ /*eDP Tx Digital */
+ gpio_i2c_write(0x52, 0xff, 0xa8 ); // Change Reg bank
+
+#ifdef _Test_Pattern_
+
+ gpio_i2c_write(0x52, 0x24, 0x50 ); // bit2 ~ bit 0 : test panttern image mode
+ gpio_i2c_write(0x52, 0x25, 0x70 ); // bit6 ~ bit 4 : test Pattern color
+ gpio_i2c_write(0x52, 0x27, 0x50 ); //0x50:Pattern; 0x10:mipi video
+
+// gpio_i2c_write(0x52, 0x2d, 0x00 ); // pure color setting
+// gpio_i2c_write(0x52, 0x2d, 0x84 ); // black color
+ gpio_i2c_write(0x52, 0x2d, 0x88 ); // block
+
+#else
+ gpio_i2c_write(0x52, 0x27, 0x10 ); //0x50:Pattern; 0x10:mipi video
+#endif
+
+#ifdef _6bit_
+ gpio_i2c_write(0x52, 0x17, 0x00 );
+ gpio_i2c_write(0x52, 0x18, 0x00 );
+#else
+ // _8bit_
+ gpio_i2c_write(0x52, 0x17, 0x10 );
+ gpio_i2c_write(0x52, 0x18, 0x20 );
+#endif
+
+ /* nvid */
+ gpio_i2c_write(0x52, 0xff, 0xa0 ); // Change Reg bank
+ gpio_i2c_write(0x52, 0x00, (u8)( Nvid_Val[_Nvid] / 256 ) ); // 0x08
+ gpio_i2c_write(0x52, 0x01, (u8)( Nvid_Val[_Nvid] % 256 ) ); // 0x00
+}
+
+void LT8911EXB_read_edid( void )
+{
+#ifdef _read_edid_
+ u8 reg, i, j;
+// bool aux_reply, aux_ack, aux_nack, aux_defer;
+ gpio_i2c_write(0x52, 0xff, 0xac );
+ gpio_i2c_write(0x52, 0x00, 0x20 ); //Soft Link train
+ gpio_i2c_write(0x52, 0xff, 0xa6 );
+ gpio_i2c_write(0x52, 0x2a, 0x01 );
+
+ /*set edid offset addr*/
+ gpio_i2c_write(0x52, 0x2b, 0x40 ); //CMD
+ gpio_i2c_write(0x52, 0x2b, 0x00 ); //addr[15:8]
+ gpio_i2c_write(0x52, 0x2b, 0x50 ); //addr[7:0]
+ gpio_i2c_write(0x52, 0x2b, 0x00 ); //data lenth
+ gpio_i2c_write(0x52, 0x2b, 0x00 ); //data lenth
+ gpio_i2c_write(0x52, 0x2c, 0x00 ); //start Aux read edid
+
+#ifdef _uart_debug_
+ uart_send_string( "Read eDP EDID....");
+ uart_send_char('\r');
+ uart_send_char('\n');
+#endif
+
+ TIMDelay_Nms( 20 ); //more than 10ms
+ reg = gpio_i2c_read(0x52,0x25 );
+ if( ( reg & 0x0f ) == 0x0c )
+ {
+ for( j = 0; j < 8; j++ )
+ {
+ if( j == 7 )
+ {
+ gpio_i2c_write(0x52, 0x2b, 0x10 ); //MOT
+ }else
+ {
+ gpio_i2c_write(0x52, 0x2b, 0x50 );
+ }
+
+ gpio_i2c_write(0x52, 0x2b, 0x00 );
+ gpio_i2c_write(0x52, 0x2b, 0x50 );
+ gpio_i2c_write(0x52, 0x2b, 0x0f );
+ gpio_i2c_write(0x52, 0x2c, 0x00 ); //start Aux read edid
+ TIMDelay_Nms( 50 ); //more than 50ms
+
+ if( gpio_i2c_read(0x52, 0x39 ) == 0x31 )
+ {
+ gpio_i2c_read(0x52, 0x2b );
+ for( i = 0; i < 16; i++ )
+ {
+ EDID_DATA[j * 16 + i] = gpio_i2c_read(0x52, 0x2b );
+ }
+
+ EDID_Reply = 1;
+ }else
+ {
+ EDID_Reply = 0;
+#ifdef _uart_debug_
+ uart_send_string( "no_reply" );
+ uart_send_char('\r');
+ uart_send_char('\n');
+#endif
+ return;
+ }
+ }
+
+#ifdef _uart_debug_
+
+ for( i = 0; i < 128; i++ ) //print edid data
+ {
+ if( ( i % 16 ) == 0 )
+ {
+ uart_send_char('\r');
+ uart_send_char('\n');
+ }
+
+ uart_send_hex(EDID_DATA[i]);
+ }
+
+ EDID_Timing[hfp] = ( ( EDID_DATA[0x41] & 0xC0 ) * 4 + EDID_DATA[0x3e] );
+ uart_send_string("eDP Timing = ");
+ uart_send_hex((u32)EDID_Timing[hfp]); // HFB
+
+
+ EDID_Timing[hs] = ( ( EDID_DATA[0x41] & 0x30 ) * 16 + EDID_DATA[0x3f] );
+ uart_send_string("hs = ");
+ uart_send_hex((u32)EDID_Timing[hs]);// Hsync Wid
+
+
+ EDID_Timing[hbp] = ( ( ( EDID_DATA[0x3a] & 0x0f ) * 0x100 + EDID_DATA[0x39] ) - ( ( EDID_DATA[0x41] & 0x30 ) * 16 + EDID_DATA[0x3f] ) - ( ( EDID_DATA[0x41] & 0xC0 ) * 4 + EDID_DATA[0x3e] ) );
+
+ uart_send_string("hbp = ");
+ uart_send_hex((u32)EDID_Timing[hbp]); // HBP
+
+ EDID_Timing[hact] = ( ( EDID_DATA[0x3a] & 0xf0 ) * 16 + EDID_DATA[0x38] );
+ uart_send_string("hact = ");
+ uart_send_hex((u32)EDID_Timing[hact]);// H active
+
+ EDID_Timing[htotal] = ( ( EDID_DATA[0x3a] & 0xf0 ) * 16 + EDID_DATA[0x38] + ( ( EDID_DATA[0x3a] & 0x0f ) * 0x100 + EDID_DATA[0x39] ) );
+ uart_send_string("htotal = ");
+ uart_send_hex((u32)EDID_Timing[htotal]);// H total
+
+ EDID_Timing[vfp] = ( ( EDID_DATA[0x41] & 0x0c ) * 4 + ( EDID_DATA[0x40] & 0xf0 ) / 16 );
+ uart_send_string("vfp = ");
+ uart_send_hex((u32)EDID_Timing[vfp]); // VFB
+
+ EDID_Timing[vs] = ( ( EDID_DATA[0x41] & 0x03 ) * 16 + EDID_DATA[0x40] & 0x0f );
+ uart_send_string("vs = ");
+ uart_send_hex((u32)EDID_Timing[vs]);// Vsync Wid
+
+ EDID_Timing[vbp] = ( ( ( EDID_DATA[0x3d] & 0x03 ) * 0x100 + EDID_DATA[0x3c] ) - ( ( EDID_DATA[0x41] & 0x03 ) * 16 + EDID_DATA[0x40] & 0x0f ) - ( ( EDID_DATA[0x41] & 0x0c ) * 4 + ( EDID_DATA[0x40] & 0xf0 ) / 16 ) );
+ uart_send_string("vbp = ");
+ uart_send_hex((u32)EDID_Timing[vbp]);
+
+ EDID_Timing[vact] = ( ( EDID_DATA[0x3d] & 0xf0 ) * 16 + EDID_DATA[0x3b] );
+ uart_send_string("vact = ");
+ uart_send_hex((u32)EDID_Timing[vact]);// V active
+
+ EDID_Timing[vtotal] = ( ( EDID_DATA[0x3d] & 0xf0 ) * 16 + EDID_DATA[0x3b] + ( ( EDID_DATA[0x3d] & 0x03 ) * 0x100 + EDID_DATA[0x3c] ) );
+ uart_send_string("vtotal = ");
+ uart_send_hex((u32)EDID_Timing[vtotal]);// V total
+
+ EDID_Timing[pclk_10khz] = ( EDID_DATA[0x37] * 0x100 + EDID_DATA[0x36] );
+ uart_send_string("pclk_10khz = ");
+ uart_send_hex((u32)EDID_Timing[pclk_10khz]);// CLK
+#endif
+ }
+
+ return;
+
+#endif
+}
+
+void LT8911EX_TxSwingPreSet( void )
+{
+ gpio_i2c_write(0x52, 0xFF, 0x82 );
+ gpio_i2c_write(0x52, 0x22, Swing_Setting1[Level] ); //lane 0 tap0
+ gpio_i2c_write(0x52, 0x23, Swing_Setting2[Level] );
+ gpio_i2c_write(0x52, 0x24, 0x80 ); //lane 0 tap1
+ gpio_i2c_write(0x52, 0x25, 0x00 );
+
+ #if( eDP_lane >= 2)
+ gpio_i2c_write(0x52, 0x26, Swing_Setting1[Level] ); //lane 1 tap0
+ gpio_i2c_write(0x52, 0x27, Swing_Setting2[Level] );
+ gpio_i2c_write(0x52, 0x28, 0x80 ); //lane 1 tap1
+ gpio_i2c_write(0x52, 0x29, 0x00 );
+
+ #if( eDP_lane == 4)
+ gpio_i2c_write(0x52, 0x2a, Swing_Setting1[Level] ); //lane 2 tap0
+ gpio_i2c_write(0x52, 0x2b, Swing_Setting2[Level] );
+ gpio_i2c_write(0x52, 0x2c, 0x80 ); //lane 2 tap1
+ gpio_i2c_write(0x52, 0x2d, 0x00 );
+ gpio_i2c_write(0x52, 0x2e, Swing_Setting1[Level] ); //lane 3 tap0
+ gpio_i2c_write(0x52, 0x2f, Swing_Setting2[Level] );
+ gpio_i2c_write(0x52, 0x30, 0x80 ); //lane 3 tap1
+ gpio_i2c_write(0x52, 0x31, 0x00 );
+ #endif
+ #endif
+}
+
+void DpcdWrite( u32 Address, u8 Data )
+{
+ /***************************
+ ע���С�˵�����!
+ ����Ĭ���Ǵ��ģʽ
+
+ Pay attention to the Big-Endian and Little-Endian!
+ The default mode is Big-Endian here.
+
+ ****************************/
+ u8 AddressH = 0x0f & ( Address >> 16 );
+ u8 AddressM = 0xff & ( Address >> 8 );
+ u8 AddressL = 0xff & Address;
+
+ u8 reg;
+
+ gpio_i2c_write(0x52, 0xff, 0xa6 );
+ gpio_i2c_write(0x52, 0x2b, ( 0x80 | AddressH ) ); //CMD
+ gpio_i2c_write(0x52, 0x2b, AddressM ); //addr[15:8]
+ gpio_i2c_write(0x52, 0x2b, AddressL ); //addr[7:0]
+ gpio_i2c_write(0x52, 0x2b, 0x00 ); //data lenth
+ gpio_i2c_write(0x52, 0x2b, Data ); //data
+ gpio_i2c_write(0x52, 0x2c, 0x00 ); //start Aux
+
+ TIMDelay_Nms( 20 ); //more than 10ms
+ reg = gpio_i2c_read(0x52, 0x25 );
+
+ if( ( reg & 0x0f ) == 0x0c )
+ {
+ return;
+ }
+}
+
+void LT8911EX_link_train( void )
+{
+ gpio_i2c_write(0x52, 0xff, 0x81 );
+ gpio_i2c_write(0x52, 0x06, 0xdf ); // rset VID TX
+ gpio_i2c_write(0x52, 0x06, 0xff );
+
+ gpio_i2c_write(0x52, 0xff, 0x85 );
+
+// gpio_i2c_write(0x52, 0x17, 0xf0 ); // turn off scramble
+
+//#ifdef _eDP_scramble_
+ if( ScrambleMode )
+ {
+ gpio_i2c_write(0x52, 0xa1, 0x82 ); // eDP scramble mode;
+
+ /* Aux operater init */
+ gpio_i2c_write(0x52, 0xff, 0xac );
+ gpio_i2c_write(0x52, 0x00, 0x20 ); //Soft Link train
+ gpio_i2c_write(0x52, 0xff, 0xa6 );
+ gpio_i2c_write(0x52, 0x2a, 0x01 );
+
+#if( eDP_lane == 4)
+ DpcdWrite( 0x0101, 0x84 );
+ TIMDelay_Nms( 10 );
+#endif
+ DpcdWrite( 0x010a, 0x01 );
+ TIMDelay_Nms( 10 );
+ DpcdWrite( 0x0102, 0x00 );
+ TIMDelay_Nms( 10 );
+ DpcdWrite( 0x010a, 0x01 );
+
+ TIMDelay_Nms( 200 );
+ //*/
+ }
+//#else
+ else
+ {
+ gpio_i2c_write(0x52, 0xa1, 0x02 ); // DP scramble mode;
+
+ /* Aux operater init */
+#if( eDP_lane == 4)
+ gpio_i2c_write(0x52, 0xff, 0xac );
+ gpio_i2c_write(0x52, 0x00, 0x20 ); //Soft Link train
+ gpio_i2c_write(0x52, 0xff, 0xa6 );
+ gpio_i2c_write(0x52, 0x2a, 0x01 );
+
+ DpcdWrite( 0x0101, 0x84 );
+ TIMDelay_Nms( 10 );
+#endif
+ }
+//#endif
+
+ /* Aux setup */
+ gpio_i2c_write(0x52, 0xff, 0xac );
+ gpio_i2c_write(0x52, 0x00, 0x60 ); //Soft Link train
+ gpio_i2c_write(0x52, 0xff, 0xa6 );
+ gpio_i2c_write(0x52, 0x2a, 0x00 );
+
+ gpio_i2c_write(0x52, 0xff, 0x81 );
+ gpio_i2c_write(0x52, 0x07, 0xfe );
+ gpio_i2c_write(0x52, 0x07, 0xff );
+ gpio_i2c_write(0x52, 0x0a, 0xfc );
+ gpio_i2c_write(0x52, 0x0a, 0xfe );
+
+ /* link train */
+
+ gpio_i2c_write(0x52, 0xff, 0x85 );
+ gpio_i2c_write(0x52, 0x1a, eDP_lane );
+
+#ifdef _link_train_enable_
+ gpio_i2c_write(0x52, 0xff, 0xac );
+ gpio_i2c_write(0x52, 0x00, 0x64 );
+ gpio_i2c_write(0x52, 0x01, 0x0a );
+ gpio_i2c_write(0x52, 0x0c, 0x85 );
+ gpio_i2c_write(0x52, 0x0c, 0xc5 );
+#else
+ gpio_i2c_write(0x52, 0xff, 0xac );
+ gpio_i2c_write(0x52, 0x00, 0x00 );
+ gpio_i2c_write(0x52, 0x01, 0x0a );
+ gpio_i2c_write(0x52, 0x14, 0x80 );
+ gpio_i2c_write(0x52, 0x14, 0x81 );
+ TIMDelay_Nms( 50 );
+ gpio_i2c_write(0x52, 0x14, 0x84 );
+ TIMDelay_Nms( 50 );
+ gpio_i2c_write(0x52, 0x14, 0xc0 );
+#endif
+}
+
+void LT8911EXB_LinkTrainResultCheck( void )
+{
+#ifdef _link_train_enable_
+ u8 i;
+ u8 val;
+ //int ret;
+
+ gpio_i2c_write(0x52, 0xff, 0xac );
+ for( i = 0; i < 10; i++ )
+ {
+ val = gpio_i2c_read(0x52,0x82 );
+ if( val & 0x20 )
+ {
+ if( ( val & 0x1f ) == 0x1e )
+ {
+#ifdef _uart_debug_
+ uart_send_string("edp link train successed:");
+ uart_send_hex(val);
+#endif
+ return;
+ }else
+ {
+#ifdef _uart_debug_
+ uart_send_string("edp link train failed:");
+ uart_send_hex(val);
+#endif
+ gpio_i2c_write(0x52, 0xff, 0xac );
+ gpio_i2c_write(0x52, 0x00, 0x00 );
+ gpio_i2c_write(0x52, 0x01, 0x0a );
+ gpio_i2c_write(0x52, 0x14, 0x80 );
+ gpio_i2c_write(0x52, 0x14, 0x81 );
+ TIMDelay_Nms( 50 );
+ gpio_i2c_write(0x52, 0x14, 0x84 );
+ TIMDelay_Nms( 50 );
+ gpio_i2c_write(0x52, 0x14, 0xc0 );
+
+ uart_send_string("LT8911_LinkTrainResultCheck: Enable eDP video output while linktrian fail");
+ uart_send_char('\r');
+ uart_send_char('\n');
+ }
+
+#ifdef _uart_debug_
+
+ val = gpio_i2c_read(0x52, 0x83 );
+
+ uart_send_string("panel link rate:");
+ uart_send_hex(val);
+
+ val = gpio_i2c_read(0x52, 0x84 );
+
+ uart_send_string("panel link count:");
+ uart_send_hex(val);
+#endif
+ TIMDelay_Nms( 100 ); // return;
+ }else
+ {
+ uart_send_string("LT8911_LinkTrainResultCheck: link trian on going...");
+
+ uart_send_char('\r');
+ uart_send_char('\n');
+
+ TIMDelay_Nms( 100 );
+ }
+ }
+#endif
+}
+
+void LT8911EXB_video_check( void )
+{
+ u8 temp;
+ u32 reg = 0x00;
+ /* mipi byte clk check*/
+ gpio_i2c_write(0x52, 0xff, 0x85 ); // Change Reg bank
+ gpio_i2c_write(0x52, 0x1d, 0x00 ); //FM select byte clk
+ gpio_i2c_write(0x52, 0x40, 0xf7 );
+ gpio_i2c_write(0x52, 0x41, 0x30 );
+
+ //#ifdef _eDP_scramble_
+ if( ScrambleMode )
+ {
+ gpio_i2c_write(0x52, 0xa1, 0x82 ); //eDP scramble mode;
+ }
+ //#else
+ else
+ {
+ gpio_i2c_write(0x52, 0xa1, 0x02 ); // DP scramble mode;
+ }
+ //#endif
+
+// gpio_i2c_write(0x52, 0x17, 0xf0 ); // 0xf0:Close scramble; 0xD0 : Open scramble
+
+ gpio_i2c_write(0x52, 0xff, 0x81 );
+ gpio_i2c_write(0x52, 0x09, 0x7d );
+ gpio_i2c_write(0x52, 0x09, 0xfd );
+
+ gpio_i2c_write(0x52, 0xff, 0x85 );
+ TIMDelay_Nms( 200 );
+
+ if( gpio_i2c_read(0x52, 0x50 ) == 0x03 )
+ {
+ reg = gpio_i2c_read(0x52, 0x4d );
+ reg = reg * 256 + gpio_i2c_read(0x52, 0x4e );
+ reg = reg * 256 + (gpio_i2c_read(0x52, 0x4f));
+ uart_send_string( "video check: mipi byteclk ="); // mipi byteclk = reg * 1000
+ uart_send_hex(reg);
+ }else
+ {
+ uart_send_string( "video check: mipi clk unstable" );
+ }
+
+
+ gpio_i2c_write(0x52, 0xff, 0xd0 );
+ TIMDelay_Nms( 200 );
+
+ gpio_i2c_read(0x52,0x85);
+ gpio_i2c_read(0x52,0x86);
+}
+
+u8 DpcdRead( u32 Address )
+{
+ u8 DpcdValue = 0x00;
+ u8 AddressH = 0x0f & ( Address >> 16 );
+ u8 AddressM = 0xff & ( Address >> 8 );
+ u8 AddressL = 0xff & Address;
+ u8 reg;
+
+ gpio_i2c_write(0x52, 0xff, 0xac );
+ gpio_i2c_write(0x52, 0x00, 0x20 ); //Soft Link train
+ gpio_i2c_write(0x52, 0xff, 0xa6 );
+ gpio_i2c_write(0x52, 0x2a, 0x01 );
+
+ gpio_i2c_write(0x52, 0xff, 0xa6 );
+ gpio_i2c_write(0x52, 0x2b, ( 0x90 | AddressH ) ); //CMD
+ gpio_i2c_write(0x52, 0x2b, AddressM ); //addr[15:8]
+ gpio_i2c_write(0x52, 0x2b, AddressL ); //addr[7:0]
+ gpio_i2c_write(0x52, 0x2b, 0x00 ); //data lenth
+ gpio_i2c_write(0x52, 0x2c, 0x00 ); //start Aux read edid
+
+ TIMDelay_Nms( 50 ); //more than 10ms
+ reg = gpio_i2c_read(0x52,0x25 );
+ if( ( reg & 0x0f ) == 0x0c )
+ {
+ if( gpio_i2c_read(0x52, 0x39 ) == 0x22 )
+ {
+ gpio_i2c_read(0x52,0x2b );
+ DpcdValue = gpio_i2c_read(0x52, 0x2b );
+ }
+
+ }else
+ {
+ gpio_i2c_write(0x52, 0xff, 0x81 ); // change bank
+ gpio_i2c_write(0x52, 0x07, 0xfe );
+ gpio_i2c_write(0x52, 0x07, 0xff );
+ gpio_i2c_write(0x52, 0x0a, 0xfc );
+ gpio_i2c_write(0x52, 0x0a, 0xfe );
+ }
+
+ return DpcdValue;
+}
+
+void PCR_Status( void ) // for debug
+{
+#ifdef _uart_debug_
+ u8 reg;
+
+ gpio_i2c_write(0x52, 0xff, 0xd0 );
+ reg = gpio_i2c_read(0x52, 0x87 );
+
+ if( reg & 0x10 )
+ {
+ uart_send_string( "PCR Clock stable" );
+ }else
+ {
+ uart_send_string( "PCR Clock unstable" );
+ }
+#endif
+}
\ No newline at end of file
--
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