From aa38e5c1f48e31213ee349aa5cd6f06c85bda70d Mon Sep 17 00:00:00 2001
From: android <android@lingyun.com>
Date: Tue, 25 Jun 2024 21:49:39 +0800
Subject: [PATCH] Add GD32F103RCT6 ADC converter board SDK source code
---
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_conf_template.h | 399
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/offset_tests.c | 33
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q15.c | 140
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/RTOS2/Include/os_tick.h | 71
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q31.c | 123
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.h | 78
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/templates/template.h | 88
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_cm33.h | 3002
mcu_sdk/gd32f103/rk_eFire/System/Src/stm32_board.c | 30
mcu_sdk/gd32f103/rk_eFire/System/Src/system_stm32f1xx.c | 408
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/var.c | 70
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/startup_stm32f101xb.s | 348
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/dct4.c | 89
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h | 3932
mcu_sdk/gd32f103/rk_eFire/System/Inc/iwdg.h | 57
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q15.c | 679
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c | 2296
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q15.c | 138
mcu_sdk/gd32f103/rk_eFire/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h | 1277
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM23.c | 82
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.c | 128
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dac_ex.c | 420
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q7.c | 163
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_f32.c | 16513 +
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c | 505
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f32.c | 192
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dac_ex.h | 277
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Source/irq_ctrl_gic.c | 410
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.c | 131
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c | 142
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h | 262
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_test_data.h | 54
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_matrix_example/arm_matrix_example_f32.c | 233
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f102xb_flash.icf | 31
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_ref.c | 43
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_nn_mult_ref.c | 58
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f103xb_flash.icf | 31
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_test_group.h | 9
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_common_data.c | 499
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f100xb_flash.icf | 31
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usart.h | 2569
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_hcd.c | 1654
mcu_sdk/gd32f103/rk_eFire/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h | 1168
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f101xb_flash.icf | 31
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru.cpp | 221
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM0.c | 56
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_cm0.h | 949
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_tests.h | 14
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd_ex.h | 88
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/cmsis_compiler.h | 266
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/copy.c | 53
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_sc000.h | 1022
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c | 211
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c | 119
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_common_data.c | 85
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM3/RTE_Components.h | 26
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_fw.h | 253
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/shift.c | 73
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_sdmmc.h | 1112
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_tests.c | 79
mcu_sdk/gd32f103/rk_eFire/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_2.c | 272
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f32.c | 84
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.c | 454
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c | 411
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h | 1378
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q15.c | 174
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_test_group.h | 9
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fixed_to_float.c | 53
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Include/core_cm23.h | 1993
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c | 587
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cec.h | 552
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f32.c | 206
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.c | 95
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c | 590
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c | 108
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/sub_tests.c | 33
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/CommonTables/arm_common_tables.c | 22176 ++
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f103x6_sram.icf | 31
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM3/RTE_Components.h | 22
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/startup_stm32f102xb.s | 363
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_templates.h | 46
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h | 850
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/startup_stm32f107xc.s | 509
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q31.c | 384
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q31.c | 383
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.c | 244
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/intrinsics_tests/intrinsics_test_group.h | 9
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c | 621
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q7.c | 791
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_squared_tests.c | 31
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_f32.c | 4273
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_crc.c | 330
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_smartcard.c | 2352
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c | 99
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f107xc.s | 368
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_usart.c | 2798
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/arm_sin_cos_example_f32.c | 161
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q15.c | 163
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/var_tests.c | 34
mcu_sdk/gd32f103/rk_eFire/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c | 1199
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.S | 216
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h | 3832
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c | 1948
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_fast_tests.c | 75
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/correlate.c | 513
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_parameter.h | 43
mcu_sdk/gd32f103/rk_eFire/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h | 129
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_group.c | 19
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_cortex.h | 640
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_tests.h | 11
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/RTOS2/Template/cmsis_os1.c | 361
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c | 549
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/intrinsics_tests/intrinsics_templates.h | 166
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q15.c | 707
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.c | 494
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_sdmmc.c | 1521
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c | 173
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/copy_tests.c | 33
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c | 191
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.c | 147
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.c | 435
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c | 181
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q31.c | 75
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f107xc_sram.icf | 31
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q15.c | 1307
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_sub.c | 58
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_systick.h | 93
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.c | 145
mcu_sdk/gd32f103/rk_eFire/Utiles/Utilities/logger.h | 133
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM4_FP/RTE_Components.h | 22
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Include/cmsis_armcc.h | 544
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/correlate_tests.c | 310
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_fast_tests.c | 57
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f103xb.s | 362
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.c | 93
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_group.c | 14
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_f32.c | 105
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.c | 1124
mcu_sdk/gd32f103/rk_eFire/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h | 155
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/TransformFunctions/arm_rfft_f32.c | 318
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usart.c | 446
mcu_sdk/gd32f103/rk_eFire/App/Inc/main.h | 71
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q31.c | 195
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c | 122
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/sin.c | 11
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q15.c | 84
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f101xb.s | 288
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f101xg_sram.icf | 31
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_tests.c | 94
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/startup_stm32f103xb.s | 393
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c | 339
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c | 141
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_cm0plus.h | 1083
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC300.c | 72
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.c | 76
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c | 272
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c | 670
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c | 559
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.c | 99
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.c | 148
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_conj.c | 40
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.c | 208
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Include/arm_common_tables.h | 121
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/RTOS2/Template/cmsis_os.h | 922
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xe.h | 6497
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c | 149
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.c | 136
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_hcd.h | 308
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.c | 338
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q15.c | 162
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM0/RTE_Components.h | 20
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.c | 120
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_common_data.c | 94
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h | 358
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM4.c | 83
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c | 2673
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_common_data.c | 114
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.c | 341
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM4_FP/RTE_Components.h | 22
mcu_sdk/gd32f103/rk_eFire/MDK-ARM/RTE/_efire/RTE_Components.h | 20
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example_f32.c | 211
mcu_sdk/gd32f103/rk_eFire/Middlewares/Third_Party/FreeRTOS/Source/tasks.c | 5039
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q31.c | 142
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_opt_ref.c | 119
mcu_sdk/gd32f103/rk_eFire/Utiles/Utilities/logger.c | 85
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Include/tz_context.h | 70
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q31.c | 620
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Include/cmsis_armclang.h | 503
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q31.c | 282
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.c | 117
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c | 1127
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_crc.c | 108
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/startup_stm32f105xc.s | 509
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2s.c | 1879
mcu_sdk/gd32f103/rk_eFire/Peripherals/Led/Inc/led.h | 31
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Include/cmsis_armcc.h | 865
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c | 187
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h | 277
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_group.c | 17
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q15.c | 52
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_sparse.c | 485
mcu_sdk/gd32f103/rk_eFire/App/Inc/Commissioning.h | 153
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_pwr.c | 86
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/sin_cos_tests.c | 151
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.c | 115
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.c | 79
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f100xb.s | 315
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c | 379
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xe.h | 6581
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_crc.h | 184
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h | 388
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_trigger_action.c | 37
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q7.c | 778
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c | 204
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/RTOS/Template/cmsis_os.h | 698
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/conv_tests.c | 473
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Include/core_cm4.h | 2129
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_rcc.c | 474
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c | 273
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Include/cmsis_version.h | 39
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/min_tests.c | 36
mcu_sdk/gd32f103/rk_eFire/System/Inc/pinName-ioe.h | 40
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/ref_helper.c | 103
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/fast_math_tests/fast_math_templates.h | 102
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Include/cmsis_compiler.h | 266
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc_ex.h | 412
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/cmsis_version.h | 39
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q31.c | 553
mcu_sdk/gd32f103/rk_eFire/Middlewares/Third_Party/FreeRTOS/Source/timers.c | 1076
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/biquad.c | 713
mcu_sdk/gd32f103/rk_eFire/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h | 779
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_test_group.h | 9
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.c | 134
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/add_tests.c | 33
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_interpolate.c | 291
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/min.c | 85
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_variance_example/arm_variance_example_f32.c | 204
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f102x6_flash.icf | 31
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c | 145
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q31.c | 129
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_timebase_rtc_alarm_template.c | 308
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_scale.c | 64
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_test_group.h | 9
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/std.c | 74
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_example_f32.c | 233
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f32.c | 317
mcu_sdk/gd32f103/rk_eFire/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c | 436
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q15.c | 1910
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/Retarget.c | 106
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c | 191
mcu_sdk/gd32f103/rk_eFire/Peripherals/Led/Src/led.c | 38
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c | 108
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.c | 236
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.c | 113
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h | 235
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c | 123
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c | 147
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_mmc.h | 745
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c | 228
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_fw.c | 9
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_reset_tests.c | 52
mcu_sdk/gd32f103/rk_eFire/MDK-ARM/efire.uvprojx | 712
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/math_helper.c | 491
mcu_sdk/gd32f103/rk_eFire/System/Src/stm32f1xx_it.c | 334
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_cm7.h | 2671
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Include/cmsis_armclang.h | 1869
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c | 89
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f102x6_sram.icf | 31
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c | 127
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h | 320
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q15.c | 172
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.c | 119
mcu_sdk/gd32f103/rk_eFire/System/Inc/usart.h | 113
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/RTOS2/Source/os_tick_gtim.c | 187
mcu_sdk/gd32f103/rk_eFire/System/Src/stm32f1xx_hal_msp.c | 116
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f107xc_flash.icf | 31
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/mean.c | 61
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.c | 137
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.c | 121
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/Legacy/stm32f1xx_hal_can_ex_legacy.h | 128
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM7_SP/RTE_Components.h | 26
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f32.c | 169
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f102xb.s | 295
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c | 175
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_example_f32.c | 259
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/mpu_armv8.h | 333
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c | 448
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q7.c | 423
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/TransformFunctions/arm_dct4_f32.c | 449
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h | 2123
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Include/mpu_armv7.h | 270
mcu_sdk/gd32f103/rk_eFire/MDK-ARM/efire.uvoptx | 904
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Include/core_ca.h | 2614
mcu_sdk/gd32f103/rk_eFire/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h | 133
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h | 731
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_wwdg.c | 422
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru_test_data.h | 23
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_cmplx_mult_tests.c | 59
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Include/cmsis_compiler.h | 201
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q15.c | 120
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv6-m.S | 263
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group_call.h | 126
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f101xe_flash.icf | 31
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.c | 138
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dac.h | 451
mcu_sdk/gd32f103/rk_eFire/Middlewares/Third_Party/FreeRTOS/Source/include/list.h | 411
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c | 98
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nor.c | 1509
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/float_to_fixed.c | 52
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_real_test.c | 31
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q7.c | 162
mcu_sdk/gd32f103/rk_eFire/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM3/port.c | 698
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.c | 128
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/tz_context.h | 70
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_tests.h | 13
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q31.c | 163
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Include/cmsis_gcc.h | 2085
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_group.c | 17
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q31.c | 174
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.c | 142
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_f32.c | 144
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c | 314
mcu_sdk/gd32f103/rk_eFire/System/Src/tim.c | 173
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_tests.c | 144
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h | 740
mcu_sdk/gd32f103/rk_eFire/System/Inc/stm32_board.h | 19
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/cmsis_iccarm.h | 935
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h | 893
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.c | 469
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h | 308
mcu_sdk/gd32f103/rk_eFire/System/Src/gpio.c | 218
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Include/core_cm0.h | 949
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv6-m.s | 195
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h | 10234 +
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_timebase_tim_template.c | 179
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c | 98
mcu_sdk/gd32f103/rk_eFire/System/Inc/board_common.h | 52
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir.c | 325
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q31.c | 169
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref.c | 71
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q7.c | 750
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c | 484
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f103xb.s | 307
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_opt_ref.c | 120
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q7.c | 82
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM7.c | 85
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q15.c | 525
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q15.c | 67
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/intrinsics_tests/intrinsics_test_data.h | 27
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c | 403
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f101x6_flash.icf | 31
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.c | 71
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_add.c | 58
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_opt_q15.c | 531
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q15.c | 382
mcu_sdk/gd32f103/rk_eFire/System/Inc/stm32f1xx_hal_conf.h | 392
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f100xe.s | 447
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c | 258
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mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c | 408
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mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c | 3960
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mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_data.c | 134
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_test_data.h | 48
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q15.c | 272
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c | 408
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM33.c | 99
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/sub.c | 57
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f105xc_sram.icf | 31
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c | 177
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q31.c | 169
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f32.c | 129
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/max.c | 85
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_cm1.h | 976
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Lib/IAR/iar_cortexM3b_math.a | 0
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/dot_prod_tests.c | 33
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_test_group.h | 9
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c | 2564
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.c | 466
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c | 106
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f32.c | 727
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.h | 63
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_dot_prod.c | 72
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_sub_tests.c | 34
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_iwdg.h | 307
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q31.c | 72
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nand.c | 2305
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_cm23.h | 1993
mcu_sdk/gd32f103/rk_eFire/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_1.c | 147
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/type_abbrev.h | 37
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mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f105xc.s | 459
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mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q15.c | 4280
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Include/core_cm33.h | 3002
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mcu_sdk/gd32f103/rk_eFire/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h | 1026
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Include/core_cm7.h | 2671
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mcu_sdk/gd32f103/rk_eFire/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM3/portmacro.h | 252
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mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_mmc.c | 2858
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mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.c | 95
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mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/rms_tests.c | 34
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c | 199
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q15.c | 2229
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mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f32.c | 196
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q31.c | 283
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests_common_data.c | 364
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mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/Retarget.c | 52
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_data.c | 23616 ++
mcu_sdk/gd32f103/rk_eFire/App/Src/app.c | 257
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mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c | 198
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mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Include/core_sc300.h | 1915
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mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_inverse_tests.c | 92
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mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.h | 63
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mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_templates.h | 181
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mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f32.c | 181
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mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.c | 74
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mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c | 149
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mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q31.c | 191
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.c | 93
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mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Lib/ARM/arm_cortexM3l_math.lib | 0
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mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/dct4_tests.c | 197
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mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q31.c | 198
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_test_data.h | 44
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mcu_sdk/gd32f103/rk_eFire/System/Src/usart.c | 483
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mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f101xg.s | 437
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mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.c | 123
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c | 144
mcu_sdk/gd32f103/rk_eFire/App/Src/main.c | 181
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q15.c | 795
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c | 199
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.c | 122
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h | 1960
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c | 235
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mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_data.c | 134
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_f32.c | 635
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q7.c | 120
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_sc300.h | 1915
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q31.c | 293
mcu_sdk/gd32f103/rk_eFire/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h | 720
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mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/mat_helper.c | 193
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mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f32.c | 125
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_call.h | 121
mcu_sdk/gd32f103/rk_eFire/.mxproject | 14
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mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Include/cmsis_iccarm.h | 935
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c | 191
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f105xc_flash.icf | 31
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q31.c | 1389
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f101xb.s | 336
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_lattice.c | 241
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_decimate.c | 386
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q31.c | 136
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c | 134
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/iir_lattice.c | 271
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.c | 157
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_irda.c | 2658
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_ref.c | 43
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ref_functions.h | 250
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_cycle.h | 65
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Lib/GCC/libarm_cortexM3l_math.a | 0
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sd.h | 762
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group_define.h | 87
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.c | 79
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f100xe_sram.icf | 31
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_ref.c | 43
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.c | 71
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/startup_generic.S | 62
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.c | 430
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h | 963
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/startup_stm32f103x6.s | 368
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Include/cmsis_iccarm.h | 559
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.c | 131
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c | 606
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f101x6.s | 278
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c | 145
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_i2c.c | 221
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_dump_str_segments.c | 36
mcu_sdk/gd32f103/rk_eFire/System/Inc/tim.h | 70
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Include/stm32f102x6.h | 6442
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f103xe_flash.icf | 31
mcu_sdk/gd32f103/rk_eFire/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h | 279
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/startup_stm32f103xg.s | 495
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/shift_tests.c | 31
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h | 11761 +
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Include/core_cm1.h | 976
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f101xg.s | 338
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f100xe_flash.icf | 31
mcu_sdk/gd32f103/rk_eFire/MDK-ARM/startup_stm32f103xe.s | 356
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref.c | 70
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_spi.c | 530
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mag.c | 49
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c | 89
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_wwdg.h | 301
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests.c | 38
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_gpio.c | 253
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q31.c | 653
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c | 899
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Include/core_cm0plus.h | 1083
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_f32.c | 569
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/scale_tests.c | 52
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Include/mpu_armv8.h | 333
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f103x6_flash.icf | 31
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_ret.h | 17
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Include/irq_ctrl.h | 186
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q15.c | 107
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q31.c | 7686
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_tim.c | 1198
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c | 3133
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q31.c | 4280
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/all_tests.c | 30
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/rfft.c | 302
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q15.c | 1494
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usb.h | 662
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f102xb.s | 344
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c | 392
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_test_data.h | 33
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2s.h | 556
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/cmsis_gcc.h | 2085
mcu_sdk/gd32f103/rk_eFire/Utiles/Utilities/utilities.h | 193
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MML.c | 99
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c | 109
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c | 213
mcu_sdk/gd32f103/rk_eFire/Utiles/Utilities/utilities.c | 97
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_dac.c | 274
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xg.h | 6707
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f32.c | 620
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_tests.c | 31
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MBL.c | 76
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.h | 63
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Include/stm32f101x6.h | 5309
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_example_q31.c | 411
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h | 3783
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f32.c | 170
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q31.c | 137
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c | 756
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.c | 466
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pccard.h | 284
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_dot_prod_tests.c | 31
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_cmplx_tests.c | 31
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f101xe.s | 326
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.c | 95
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q7.c | 452
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_exti.h | 888
mcu_sdk/gd32f103/rk_eFire/Middlewares/Third_Party/FreeRTOS/Source/queue.c | 2908
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f32.c | 285
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q31.c | 353
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.c | 150
mcu_sdk/gd32f103/rk_eFire/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c | 738
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c | 418
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.c | 128
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.c | 450
mcu_sdk/gd32f103/rk_eFire/System/Inc/FreeRTOSConfig.h | 137
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c | 169
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.c | 524
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f103xe.s | 356
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/Intrinsics/intrinsics.c | 238
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f102x6.s | 285
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_armv8mbl.h | 1918
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q31.c | 162
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Include/stm32f105xc.h | 14334 +
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.c | 433
mcu_sdk/gd32f103/rk_eFire/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h | 756
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c | 412
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/util/util.h | 52
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/negate.c | 53
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f32.c | 76
mcu_sdk/gd32f103/rk_eFire/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h | 852
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.c | 138
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c | 130
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.c | 162
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/bitreversal.c | 30
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_cycle.c | 9
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_family_tests.c | 183
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q15.c | 139
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q15.c | 457
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.c | 110
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref_nonsquare.c | 78
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_data.c | 308
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM7_SP/RTE_Components.h | 22
mcu_sdk/gd32f103/rk_eFire/System/Src/rtc.c | 642
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_templates.h | 370
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Include/cmsis_gcc.h | 679
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_tests.h | 11
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f32.c | 131
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/mult_tests.c | 33
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h | 210
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_pool_ref.c | 96
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Compiler/EventRecorderConf.h | 44
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_cm4.h | 2129
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/cmsis_armclang.h | 1869
mcu_sdk/gd32f103/rk_eFire/Middlewares/Third_Party/FreeRTOS/Source/croutine.c | 353
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q31.c | 600
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_eth.c | 2292
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.c | 118
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.c | 53
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv7-m.S | 235
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/fully_connected_testing_weights.h | 7
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_common_data.c | 757
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c | 109
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/opt_arg.h | 15
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q15.c | 151
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c | 292
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_iwdg.h | 226
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_utils.h | 269
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/abs.c | 53
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q31.c | 338
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_fsmc.c | 1004
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test.h | 100
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mult_cmplx.c | 56
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q31.c | 105
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c | 332
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f32.c | 691
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c | 89
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.c | 492
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q31.c | 252
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/sin_cos.c | 21
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/startup_stm32f100xb.s | 396
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f103x6.s | 297
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/Legacy/stm32f1xx_hal_can_legacy.h | 796
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/max_tests.c | 36
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f107xc.s | 470
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC000.c | 56
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_example_f32.c | 204
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h | 457
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/pid.c | 97
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f103xg.s | 356
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f103xg_sram.icf | 31
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_f32.c | 512
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f32.c | 985
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h | 2347
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32_assert_template.h | 57
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f32.c | 152
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/all_tests.h | 9
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/Include/arm_nnfunctions.h | 1010
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Template/ARMv8-M/tz_context.c | 200
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q15.c | 533
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/RTOS2/Source/os_tick_ptim.c | 165
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f105xc.s | 364
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_usart.h | 645
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/conv.c | 350
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f100xb.s | 405
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f102xb_sram.icf | 31
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c | 103
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example_f32.c | 247
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example_f32.c | 178
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q31.c | 299
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rtc.h | 1003
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h | 1015
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/power_tests.c | 36
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q15.c | 501
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_tests.h | 17
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.c | 154
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h | 786
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h | 410
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q15.c | 171
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/abs_tests.c | 32
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c | 413
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM7_SP/RTE_Components.h | 22
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q7.c | 127
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Include/stm32f103x6.h | 10103
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/splice.h | 8
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f32.c | 472
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_templates.h | 157
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.c | 93
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_exti.c | 215
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q15.c | 426
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h | 220
mcu_sdk/gd32f103/rk_eFire/Board/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h | 607
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/filtering_tests/filtering_tests.h | 15
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h | 98
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/filtering_tests/filtering_test_data.h | 81
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/Include/arm_nnsupportfunctions.h | 202
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q31.c | 53
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_weights.h | 26
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/add.c | 57
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Include/arm_math.h | 7157
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c | 171
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv6-m.S | 203
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c | 207
mcu_sdk/gd32f103/rk_eFire/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h | 181
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f32.c | 153
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c | 136
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Include/core_sc000.h | 1022
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_armv8mml.h | 2927
mcu_sdk/gd32f103/rk_eFire/System/Src/freertos.c | 125
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/templates/test_templates.h | 458
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xg.h | 11945 +
mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/intrinsics_tests/intrinsics_tests.c | 62
957 files changed, 610,256 insertions(+), 0 deletions(-)
diff --git a/mcu_sdk/gd32f103/rk_eFire/.mxproject b/mcu_sdk/gd32f103/rk_eFire/.mxproject
new file mode 100644
index 0000000..ce78f81
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/.mxproject
@@ -0,0 +1,14 @@
+[PreviousGenFiles]
+HeaderPath=D:/working/trunk/NB-IOT/src/Fire/efire/Inc
+HeaderFiles=gpio.h;adc.h;FreeRTOSConfig.h;iwdg.h;rtc.h;stm32f1xx_it.h;stm32f1xx_hal_conf.h;main.h;tim.h;usart.h;
+SourcePath=D:/working/trunk/NB-IOT/src/Fire/efire/Src
+SourceFiles=gpio.c;adc.c;freertos.c;iwdg.c;rtc.c;stm32f1xx_it.c;stm32f1xx_hal_msp.c;main.c;tim.c;usart.c;stm32f1xx_hal_timebase_tim.c;
+
+[PreviousLibFiles]
+LibFiles=Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_iwdg.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h;Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h;Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h;Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h;Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h;Middlewares/Third_Party/FreeRTOS/Source/include/list.h;Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h;Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h;Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h;Middlewares/Third_Party/FreeRTOS/Source/include/portable.h;Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h;Middlewares/Third_Party/FreeRTOS/Source/include/queue.h;Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h;Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h;Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h;Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h;Middlewares/Third_Party/FreeRTOS/Source/include/task.h;Middlewares/Third_Party/FreeRTOS/Source/include/timers.h;Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h;Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM3/portmacro.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;Middlewares/Third_Party/FreeRTOS/Source/croutine.c;Middlewares/Third_Party/FreeRTOS/Source/event_groups.c;Middlewares/Third_Party/FreeRTOS/Source/list.c;Middlewares/Third_Party/FreeRTOS/Source/queue.c;Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c;Middlewares/Third_Party/FreeRTOS/Source/tasks.c;Middlewares/Third_Party/FreeRTOS/Source/timers.c;Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c;Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c;Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM3/port.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_iwdg.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h;Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h;Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h;Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h;Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h;Middlewares/Third_Party/FreeRTOS/Source/include/list.h;Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h;Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h;Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h;Middlewares/Third_Party/FreeRTOS/Source/include/portable.h;Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h;Middlewares/Third_Party/FreeRTOS/Source/include/queue.h;Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h;Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h;Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h;Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h;Middlewares/Third_Party/FreeRTOS/Source/include/task.h;Middlewares/Third_Party/FreeRTOS/Source/include/timers.h;Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h;Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM3/portmacro.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h;
+
+[PreviousUsedKeilFiles]
+SourceFiles=..\Src\main.c;..\Src\gpio.c;..\Src\adc.c;..\Src\freertos.c;..\Src\iwdg.c;..\Src\rtc.c;..\Src\tim.c;..\Src\usart.c;..\Src\stm32f1xx_it.c;..\Src\stm32f1xx_hal_msp.c;..\Src\stm32f1xx_hal_timebase_tim.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;../Middlewares/Third_Party/FreeRTOS/Source/croutine.c;../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c;../Middlewares/Third_Party/FreeRTOS/Source/list.c;../Middlewares/Third_Party/FreeRTOS/Source/queue.c;../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c;../Middlewares/Third_Party/FreeRTOS/Source/tasks.c;../Middlewares/Third_Party/FreeRTOS/Source/timers.c;../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c;../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c;../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM3/port.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../\Src/system_stm32f1xx.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;../Middlewares/Third_Party/FreeRTOS/Source/croutine.c;../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c;../Middlewares/Third_Party/FreeRTOS/Source/list.c;../Middlewares/Third_Party/FreeRTOS/Source/queue.c;../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c;../Middlewares/Third_Party/FreeRTOS/Source/tasks.c;../Middlewares/Third_Party/FreeRTOS/Source/timers.c;../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c;../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c;../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM3/port.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../\Src/system_stm32f1xx.c;../Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;null;../Middlewares/Third_Party/FreeRTOS/Source/croutine.c;../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c;../Middlewares/Third_Party/FreeRTOS/Source/list.c;../Middlewares/Third_Party/FreeRTOS/Source/queue.c;../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c;../Middlewares/Third_Party/FreeRTOS/Source/tasks.c;../Middlewares/Third_Party/FreeRTOS/Source/timers.c;../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c;../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c;../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM3/port.c;
+HeaderPath=..\Drivers\STM32F1xx_HAL_Driver\Inc;..\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy;..\Middlewares\Third_Party\FreeRTOS\Source\include;..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS;..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM3;..\Drivers\CMSIS\Device\ST\STM32F1xx\Include;..\Drivers\CMSIS\Include;..\Inc;
+CDefines=USE_HAL_DRIVER;STM32F103xE;USE_HAL_DRIVER;STM32F103xE;
+
diff --git a/mcu_sdk/gd32f103/rk_eFire/App/Inc/Commissioning.h b/mcu_sdk/gd32f103/rk_eFire/App/Inc/Commissioning.h
new file mode 100644
index 0000000..d4962df
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/App/Inc/Commissioning.h
@@ -0,0 +1,153 @@
+/*!
+ * \file Commissioning.h
+ *
+ * \brief End device commissioning parameters
+ *
+ * \copyright Revised BSD License, see section \ref LICENSE.
+ *
+ * \code
+ * ______ _
+ * / _____) _ | |
+ * ( (____ _____ ____ _| |_ _____ ____| |__
+ * \____ \| ___ | (_ _) ___ |/ ___) _ \
+ * _____) ) ____| | | || |_| ____( (___| | | |
+ * (______/|_____)_|_|_| \__)_____)\____)_| |_|
+ * (C)2013-2017 Semtech
+ *
+ * \endcode
+ *
+ * \author Miguel Luis ( Semtech )
+ *
+ * \author Gregory Cristian ( Semtech )
+ */
+#ifndef __LORA_COMMISSIONING_H__
+#define __LORA_COMMISSIONING_H__
+
+/*!
+ ******************************************************************************
+ ********************************** WARNING ***********************************
+ ******************************************************************************
+ The crypto-element implementation supports both 1.0.x and 1.1.x LoRaWAN
+ versions of the specification.
+ Thus it has been decided to use the 1.1.x keys and EUI name definitions.
+ The below table shows the names equivalence between versions:
+ +---------------------+-------------------------+
+ | 1.0.x | 1.1.x |
+ +=====================+=========================+
+ | LORAWAN_DEVICE_EUI | LORAWAN_DEVICE_EUI |
+ +---------------------+-------------------------+
+ | LORAWAN_APP_EUI | LORAWAN_JOIN_EUI |
+ +---------------------+-------------------------+
+ | LORAWAN_GEN_APP_KEY | LORAWAN_APP_KEY |
+ +---------------------+-------------------------+
+ | LORAWAN_APP_KEY | LORAWAN_NWK_KEY |
+ +---------------------+-------------------------+
+ | LORAWAN_NWK_S_KEY | LORAWAN_F_NWK_S_INT_KEY |
+ +---------------------+-------------------------+
+ | LORAWAN_NWK_S_KEY | LORAWAN_S_NWK_S_INT_KEY |
+ +---------------------+-------------------------+
+ | LORAWAN_NWK_S_KEY | LORAWAN_NWK_S_ENC_KEY |
+ +---------------------+-------------------------+
+ | LORAWAN_APP_S_KEY | LORAWAN_APP_S_KEY |
+ +---------------------+-------------------------+
+ ******************************************************************************
+ ******************************************************************************
+ ******************************************************************************
+ */
+
+/*!
+ * When set to 1 the application uses the Over-the-Air activation procedure
+ * When set to 0 the application uses the Personalization activation procedure
+ */
+//#define OVER_THE_AIR_ACTIVATION (DeviceParamInfor.Settings.DeviceInfor.LoRaStaActiveMode)
+#define LORAWAN_WORK_CHANNEL DeviceParamInfor.Settings.DeviceInfor.WorkChannel
+#define OVER_THE_AIR_ACTIVATION ABP_MODE
+
+/*!
+ * When using ABP activation the MAC layer must know in advance to which server
+ * version it will be connected.
+ */
+#define ABP_ACTIVATION_LRWAN_VERSION_V10x 0x01000300 // 1.0.3.0
+
+#define ABP_ACTIVATION_LRWAN_VERSION ABP_ACTIVATION_LRWAN_VERSION_V10x
+
+/*!
+ * Indicates if the end-device is to be connected to a private or public network
+ */
+#define LORAWAN_PUBLIC_NETWORK true
+
+/*!
+ * IEEE Organizationally Unique Identifier ( OUI ) (big endian)
+ * \remark This is unique to a company or organization
+ */
+#define IEEE_OUI 0x88, 0x00, 0x00
+
+/*!
+ * Mote device IEEE EUI (big endian)
+ *
+ * \remark In this application the value is automatically generated by calling
+ * BoardGetUniqueId function
+ */
+#define LORAWAN_DEVICE_EUI { IEEE_OUI, 0x00, 0x00, 0x88, 0x88, 0x88 }
+
+/*!
+ * App/Join server IEEE EUI (big endian)
+ */
+#define LORAWAN_JOIN_EUI { 0X70, 0XB3, 0XD5, 0X7E, 0XD0, 0X02, 0X63, 0X42 }
+
+/*!
+ * Application root key
+ * WARNING: NOT USED FOR 1.0.x DEVICES
+ */
+#define LORAWAN_APP_KEY { 0x2B, 0x7E, 0x15, 0x16, 0x28, 0xAE, 0xD2, 0xA6, 0xAB, 0xF7, 0x15, 0x88, 0x09, 0xCF, 0x4F, 0x3C }
+
+/*!
+ * Application root key - Used to derive Multicast keys on 1.0.x devices.
+ * WARNING: USED only FOR 1.0.x DEVICES
+ */
+#define LORAWAN_GEN_APP_KEY { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F }
+
+/*!
+ * Network root key
+ * WARNING: FOR 1.0.x DEVICES IT IS THE \ref LORAWAN_APP_KEY
+ */
+#define LORAWAN_NWK_KEY { 0x2B, 0x7E, 0x15, 0x16, 0x28, 0xAE, 0xD2, 0xA6, 0xAB, 0xF7, 0x15, 0x88, 0x09, 0xCF, 0x4F, 0x3C }
+
+/*!
+ * Current network ID
+ */
+#define LORAWAN_NETWORK_ID ( uint32_t )0
+
+/*!
+ * Device address on the network (big endian)
+ *
+ * \remark In this application the value is automatically generated using
+ * a pseudo random generator seeded with a value derived from
+ * BoardUniqueId value if LORAWAN_DEVICE_ADDRESS is set to 0
+ */
+#define LORAWAN_DEVICE_ADDRESS ( uint32_t )0x88888888
+
+/*!
+ * Forwarding Network session integrity key
+ * WARNING: NWK_S_KEY FOR 1.0.x DEVICES
+ */
+#define LORAWAN_F_NWK_S_INT_KEY { 0x2B, 0x7E, 0x15, 0x16, 0x28, 0xAE, 0xD2, 0xA6, 0xAB, 0xF7, 0x15, 0x88, 0x09, 0xCF, 0x4F, 0x3C }
+
+/*!
+ * Serving Network session integrity key
+ * WARNING: NOT USED FOR 1.0.x DEVICES. MUST BE THE SAME AS \ref LORAWAN_F_NWK_S_INT_KEY
+ */
+#define LORAWAN_S_NWK_S_INT_KEY { 0x2B, 0x7E, 0x15, 0x16, 0x28, 0xAE, 0xD2, 0xA6, 0xAB, 0xF7, 0x15, 0x88, 0x09, 0xCF, 0x4F, 0x3C }
+
+/*!
+ * Network session encryption key
+ * WARNING: NOT USED FOR 1.0.x DEVICES. MUST BE THE SAME AS \ref LORAWAN_F_NWK_S_INT_KEY
+ */
+#define LORAWAN_NWK_S_ENC_KEY { 0x2B, 0x7E, 0x15, 0x16, 0x28, 0xAE, 0xD2, 0xA6, 0xAB, 0xF7, 0x15, 0x88, 0x09, 0xCF, 0x4F, 0x3C }
+
+/*!
+ * Application session key
+ */
+#define LORAWAN_APP_S_KEY { 0x2B, 0x7E, 0x15, 0x16, 0x28, 0xAE, 0xD2, 0xA6, 0xAB, 0xF7, 0x15, 0x88, 0x09, 0xCF, 0x4F, 0x3C }
+
+#endif // __LORA_COMMISSIONING_H__
diff --git a/mcu_sdk/gd32f103/rk_eFire/App/Inc/app.h b/mcu_sdk/gd32f103/rk_eFire/App/Inc/app.h
new file mode 100644
index 0000000..f30d153
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/App/Inc/app.h
@@ -0,0 +1,7 @@
+#ifndef __APP_H__
+#define __APP_H__
+
+int8_t Board_USART_Process(void);
+void ADC_Sample(void);
+
+#endif /*End of __APP_H__ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/App/Inc/main.h b/mcu_sdk/gd32f103/rk_eFire/App/Inc/main.h
new file mode 100644
index 0000000..96a2198
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/App/Inc/main.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file : main.h
+ * @brief : Header for main.c file.
+ * This file contains the common defines of the application.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ * www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/mcu_sdk/gd32f103/rk_eFire/App/Src/app.c b/mcu_sdk/gd32f103/rk_eFire/App/Src/app.c
new file mode 100644
index 0000000..eafe571
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/App/Src/app.c
@@ -0,0 +1,257 @@
+#include "board_common.h"
+
+#include "app.h"
+
+
+
+typedef enum
+{
+ T_I = 1,
+ T_V,
+}DATA_TYPE;
+
+typedef enum
+{
+ I_0 = 0,
+ I_1,
+ I_2,
+ I_3,
+}I_CHANNEL;
+
+typedef enum
+{
+ V_0= 0,
+ V_1,
+ V_2,
+ V_3
+}V_CHANNEL;
+
+#define ADC_CHANNEL_MAX_NUM 10
+#define ADC_SAMPLE_BUFFER_SIZE 20
+
+
+#pragma pack (1)
+
+typedef struct
+{
+ uint8_t header[2]; /* 报文头0xAA 0x55 */
+ uint8_t type; /* 1:电流, 2:电压 */
+ uint8_t channel; /* 通道 */
+ uint16_t crc; /* CRC */
+}RxPacket;
+
+#define RX_PACKET_SIZE sizeof(RxPacket)
+typedef union
+{
+ RxPacket packet;
+ uint8_t buffer[RX_PACKET_SIZE];
+}RxPacket_u;
+
+
+typedef struct
+{
+ uint8_t header[2]; /* 报文头0xAA 0x55 */
+ uint8_t type; /* 1:电流, 2:电压 */
+ uint8_t channel; /* 通道 */
+ uint16_t value; /* 数值 */
+ uint16_t crc; /* CRC */
+}RxPacketRes;
+
+#define RX_PACKET_RES_SIZE sizeof(RxPacketRes)
+typedef union
+{
+ RxPacketRes packet;
+ uint8_t buffer[RX_PACKET_RES_SIZE];
+}RxPacketRes_u;
+
+#pragma pack ()
+
+static uint16_t adcSampleBuffer[ADC_CHANNEL_MAX_NUM][ADC_SAMPLE_BUFFER_SIZE] = {0};
+static bool adcDataReadable = false;
+
+void PrintHex(const unsigned char *buffer, unsigned int len)
+{
+ unsigned int i;
+ PRINTF("\r\n");
+ for(i=0; i<len; i++)
+ {
+ PRINTF("%02x ", buffer[i]);
+ if (i!=0 && ((i+1)%16) == 0)
+ PRINTF("\r\n");
+ }
+ PRINTF("\r\n");
+}
+
+static uint16_t CRC16(const uint8_t *Buf , uint32_t usLen)
+{
+ uint16_t i, j;
+ uint16_t usCrc = 0xFFFF;
+ for ( i = 0 ; i < usLen ; i++ )
+ {
+ usCrc ^= Buf[i];
+ for ( j = 0 ; j < 8 ; j++ )
+ {
+ if ( usCrc & 1 )
+ {
+ usCrc >>=1;
+ usCrc ^=0xA001;
+ }
+ else
+ {
+ usCrc >>= 1;
+ }
+ }
+ }
+ return usCrc;
+}
+
+void ADC_Sample(void)
+{
+ /* 采样adc数据 */
+ ADC_SampleData sampleData;
+ memset(&sampleData, 0x0, sizeof(ADC_SampleData));
+ if (ADC1_ADC_GetSampleData(&sampleData, sizeof(ADC_SampleData)) < 0)
+ return ;
+ /*
+ * 将采样数据存储到指定buffer
+ */
+ static uint8_t bufferIndex = 0;
+ uint8_t channel = 0;
+ for (; channel < ADC_CHANNEL_MAX_NUM; channel++)
+ {
+ adcSampleBuffer[channel][bufferIndex] = sampleData.sampleBuffer[channel];
+ }
+
+ if (bufferIndex < ADC_SAMPLE_BUFFER_SIZE)
+ {
+ bufferIndex++;
+ }
+ else
+ {
+ bufferIndex = 0;
+ adcDataReadable = true; /* buffer已经满,数据可读 */
+ }
+
+}
+
+double RootMeanSquareCalc(uint16_t *data, uint8_t num)
+{
+ double sum = 0;
+ uint8_t i = 0;
+
+ for(; i<num; i++)
+ {
+ sum += data[i] * data[i]; /* 平方和 */
+
+ //PRINTF("%d\r\n", data[i]);
+ }
+
+ return sqrt(sum/num);
+}
+
+
+static void ReportChannelData(DATA_TYPE type, uint8_t ch)
+{
+ double rootMeanSquareVref = RootMeanSquareCalc((uint16_t *)&adcSampleBuffer[0], ADC_SAMPLE_BUFFER_SIZE);
+ PRINTF("ref:%f\r\n", rootMeanSquareVref);
+ double rootMeanSquare = 0.0;
+
+ uint32_t v33 = 2500*4095/(uint16_t)rootMeanSquare;
+ rootMeanSquare = RootMeanSquareCalc((uint16_t *)&adcSampleBuffer[1], ADC_SAMPLE_BUFFER_SIZE);
+ uint32_t v12 = 12*v33*rootMeanSquare/4095;
+ uint32_t vo = 0;
+ uint32_t vi = 0;
+ uint32_t v5 = 0;
+ uint32_t value = 0;
+ switch (type)
+ {
+ case T_I:
+ rootMeanSquare = RootMeanSquareCalc((uint16_t *)&adcSampleBuffer[6+ch], ADC_SAMPLE_BUFFER_SIZE);
+ PRINTF("ADC:%f\r\n", rootMeanSquare);
+ vo = 100*2500*rootMeanSquare/rootMeanSquareVref;
+ value = vo/100;
+ PRINTF("vi:%d\t\ti:%d(0.01mA)\r\n", vo,value);
+ break;
+ case T_V:
+ rootMeanSquare = RootMeanSquareCalc((uint16_t *)&adcSampleBuffer[2+ch], ADC_SAMPLE_BUFFER_SIZE);
+ PRINTF("ADC:%f\r\n", rootMeanSquare);
+ vo = 2500*rootMeanSquare/rootMeanSquareVref;
+ vi = 1000*vo/452; /* vo=0.452 x vi */
+ value = vi;
+ PRINTF("vo:%d\t\tvi:%d(1mV)\r\n", vo, vi);
+ break;
+ }
+
+ RxPacketRes_u resPacket;
+ memset(&resPacket, 0x0, sizeof(RxPacketRes_u));
+ resPacket.packet.header[0] = 0xAA;
+ resPacket.packet.header[1] = 0x55;
+ resPacket.packet.type = type;
+ resPacket.packet.channel = ch;
+ resPacket.packet.value = value;
+ resPacket.packet.crc = CRC16(resPacket.buffer, sizeof(RxPacketRes_u)-2);
+
+ PRINTF("Send:");
+ PrintHex((const unsigned char *)resPacket.buffer, sizeof(RxPacketRes_u));
+ Board_USART2Send(resPacket.buffer, sizeof(RxPacketRes_u));
+}
+
+static int ParserRecvPacket(uint8_t *buffer, uint8_t len, RxPacket_u *data)
+{
+ PRINTF("Receive:");
+ PrintHex((const unsigned char *)buffer, len);
+
+ if (len != sizeof(RxPacket_u))
+ return -1;
+
+ RxPacket_u *packet = (RxPacket_u *)buffer;
+ if (packet->packet.header[0] != 0xAA && packet->packet.header[1] != 0x55)
+ return -1;
+
+ uint16_t crc = packet->packet.crc;
+ uint16_t calCrc = CRC16((const uint8_t *)buffer, RX_PACKET_SIZE-2);
+ if (crc != calCrc)
+ return -1;
+ if (adcDataReadable)
+ ReportChannelData(packet->packet.type, packet->packet.channel);
+
+ return 0;
+}
+
+
+int8_t Board_USART_Process(void)
+{
+ uint8_t u8Rx = 0;
+ uint32_t u32TestTimeOut = jiffies + 5000;
+ uint32_t u32RecvTimeOut = jiffies + 200;
+ const uint8_t u8SendBuffer[32] = "Recv OK\r\n";
+ uint8_t u8RecvBuffer[32] = {0};
+ uint8_t u8Index = 0;
+
+ RxPacket_u data;
+ memset(&data, 0x0, sizeof(RxPacket_u));
+ while(1)
+ {
+ while( !Timeout_Happened(u32RecvTimeOut))
+ {
+ if (!Board_USART2Recv(&u8Rx, 200))
+ {
+ u8RecvBuffer[u8Index] = u8Rx;
+ if (u8Index <= (sizeof(u8RecvBuffer)-1))
+ u8Index++;
+ else
+ break;
+ }
+ }
+
+ if(u8Index > 0)
+ {
+ ParserRecvPacket(u8RecvBuffer, u8Index, &data);
+ }
+ u8Index = 0;
+ memset(u8RecvBuffer, 0, sizeof(u8RecvBuffer));
+ u32RecvTimeOut = jiffies + 200;
+ }
+ return -1;
+}
+
diff --git a/mcu_sdk/gd32f103/rk_eFire/App/Src/main.c b/mcu_sdk/gd32f103/rk_eFire/App/Src/main.c
new file mode 100644
index 0000000..693dd7c
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/App/Src/main.c
@@ -0,0 +1,181 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file : main.c
+ * @brief : Main program body
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ * www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "board_common.h"
+
+void SystemClock_Config(void);
+
+void Board_TimerInit(int8_t *name);
+
+/**
+ * @brief The application entry point.
+ * @retval int
+ */
+int main(void)
+{
+ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+ HAL_Init();
+
+ /* Configure the system clock */
+ SystemClock_Config();
+
+ Board_HardwareInit();
+ //Board_IWDG_Init();
+ Board_USART_Process();
+
+
+ while (1)
+ {
+ //ADC1_ADC_GetSampleData();
+ DelayMs(2000);
+ //Board_IWDGFeed();
+ }
+
+}
+
+
+/**
+ * @brief System Clock Configuration
+ * @retval None
+ */
+ #if 0
+void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+
+ /** Initializes the CPU, AHB and APB busses clocks
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE
+ |RCC_OSCILLATORTYPE_LSE;
+
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
+ RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+ RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /** Initializes the CPU, AHB and APB busses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ //PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_ADC;
+
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC;
+ PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+ PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV4;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+ {
+ Error_Handler();
+ }
+}
+ #else
+ void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+
+ /** Initializes the CPU, AHB and APB busses clocks
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE;
+
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
+ RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
+ RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /** Initializes the CPU, AHB and APB busses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ //PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_ADC;
+
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC;
+ PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
+ PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV4;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+ {
+ Error_Handler();
+ }
+}
+ #endif
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @retval None
+ */
+void Error_Handler(void)
+{
+ /* USER CODE BEGIN Error_Handler_Debug */
+ /* User can add his own implementation to report the HAL error return state */
+
+ /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief Reports the name of the source file and the source line number
+ * where the assert_param error has occurred.
+ * @param file: pointer to the source file name
+ * @param line: assert_param error line source number
+ * @retval None
+ */
+void assert_failed(uint8_t *file, uint32_t line)
+{
+ /* USER CODE BEGIN 6 */
+ /* User can add his own implementation to report the file name and line number,
+ tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+ /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/cmsis_armcc.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/cmsis_armcc.h
new file mode 100644
index 0000000..7d751fb
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/cmsis_armcc.h
@@ -0,0 +1,865 @@
+/**************************************************************************//**
+ * @file cmsis_armcc.h
+ * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version V5.0.4
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+ #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
+ (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
+ #define __ARM_ARCH_6M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
+ #define __ARM_ARCH_7M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+ #define __ARM_ARCH_7EM__ 1
+#endif
+
+ /* __ARM_ARCH_8M_BASE__ not applicable */
+ /* __ARM_ARCH_8M_MAIN__ not applicable */
+
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE static __forceinline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __declspec(noreturn)
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT __packed struct
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION __packed union
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); */
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ register uint32_t __regBasePriMax __ASM("basepri_max");
+ __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() do {\
+ __schedule_barrier();\
+ __isb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+ __schedule_barrier();\
+ __dsb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+ __schedule_barrier();\
+ __dmb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+ #define __RBIT __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+ return result;
+}
+#endif
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+#else
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+#else
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+#else
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXB(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXH(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXW(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+ rrx r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32U) ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/cmsis_armclang.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/cmsis_armclang.h
new file mode 100644
index 0000000..d8031b0
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/cmsis_armclang.h
@@ -0,0 +1,1869 @@
+/**************************************************************************//**
+ * @file cmsis_armclang.h
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version V5.0.4
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR() ((uint32_t)0U)
+#endif
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __set_FPSCR __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x) ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF);
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF);
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF);
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV(value) __builtin_bswap32(value)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __builtin_arm_rbit
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/cmsis_compiler.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/cmsis_compiler.h
new file mode 100644
index 0000000..79a2cac
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/cmsis_compiler.h
@@ -0,0 +1,266 @@
+/**************************************************************************//**
+ * @file cmsis_compiler.h
+ * @brief CMSIS compiler generic header file
+ * @version V5.0.4
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+ #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+ #include <cmsis_ccs.h>
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed))
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed))
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __packed__
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __packed__
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __packed__
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __packed__ T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __align(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+ #include <cmsis_csm.h>
+
+ #ifndef __ASM
+ #define __ASM _asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ // NO RETURN is automatically detected hence no warning here
+ #define __NO_RETURN
+ #endif
+ #ifndef __USED
+ #warning No compiler specific solution for __USED. __USED is ignored.
+ #define __USED
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __weak
+ #endif
+ #ifndef __PACKED
+ #define __PACKED @packed
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT @packed struct
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION @packed union
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ @packed struct T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+
+
+#else
+ #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/cmsis_gcc.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/cmsis_gcc.h
new file mode 100644
index 0000000..1bd41a4
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/cmsis_gcc.h
@@ -0,0 +1,2085 @@
+/**************************************************************************//**
+ * @file cmsis_gcc.h
+ * @brief CMSIS compiler GCC header file
+ * @version V5.0.4
+ * @date 09. April 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+ #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_get_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ return __builtin_arm_get_fpscr();
+#else
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#endif
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ __builtin_arm_set_fpscr(fpscr);
+#else
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP() __ASM volatile ("nop")
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI() __ASM volatile ("wfi")
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE() __ASM volatile ("wfe")
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV() __ASM volatile ("sev")
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (int16_t)__builtin_bswap16(value);
+#else
+ int16_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return result;
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+ __extension__ \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/cmsis_iccarm.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/cmsis_iccarm.h
new file mode 100644
index 0000000..3c90a2c
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/cmsis_iccarm.h
@@ -0,0 +1,935 @@
+/**************************************************************************//**
+ * @file cmsis_iccarm.h
+ * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version V5.0.7
+ * @date 19. June 2018
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2018 IAR Systems
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+ #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+ #define __ICCARM_V8 1
+#else
+ #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+ #if __ICCARM_V8
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #elif (__VER__ >= 7080000)
+ /* Needs IAR language extensions */
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #else
+ #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+ #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+ #if __ARM_ARCH == 6
+ #define __ARM_ARCH_6M__ 1
+ #elif __ARM_ARCH == 7
+ #if __ARM_FEATURE_DSP
+ #define __ARM_ARCH_7EM__ 1
+ #else
+ #define __ARM_ARCH_7M__ 1
+ #endif
+ #endif /* __ARM_ARCH */
+ #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+ !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+ #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+ #define __ARM_ARCH_6M__ 1
+ #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+ #define __ARM_ARCH_7M__ 1
+ #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+ #define __ARM_ARCH_7EM__ 1
+ #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #else
+ #error "Unknown target."
+ #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+ #define __IAR_M0_FAMILY 1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+ #define __IAR_M0_FAMILY 1
+#else
+ #define __IAR_M0_FAMILY 0
+#endif
+
+
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+
+#ifndef __NO_RETURN
+ #if __ICCARM_V8
+ #define __NO_RETURN __attribute__((__noreturn__))
+ #else
+ #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+ #endif
+#endif
+
+#ifndef __PACKED
+ #if __ICCARM_V8
+ #define __PACKED __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED __packed
+ #endif
+#endif
+
+#ifndef __PACKED_STRUCT
+ #if __ICCARM_V8
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_STRUCT __packed struct
+ #endif
+#endif
+
+#ifndef __PACKED_UNION
+ #if __ICCARM_V8
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_UNION __packed union
+ #endif
+#endif
+
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+
+#ifndef __FORCEINLINE
+ #define __FORCEINLINE _Pragma("inline=forced")
+#endif
+
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+ return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+ *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+ return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+ *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef __USED
+ #if __ICCARM_V8
+ #define __USED __attribute__((used))
+ #else
+ #define __USED _Pragma("__root")
+ #endif
+#endif
+
+#ifndef __WEAK
+ #if __ICCARM_V8
+ #define __WEAK __attribute__((weak))
+ #else
+ #define __WEAK _Pragma("__weak")
+ #endif
+#endif
+
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+ #define __ICCARM_INTRINSICS_VERSION__ 0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+ #if defined(__CLZ)
+ #undef __CLZ
+ #endif
+ #if defined(__REVSH)
+ #undef __REVSH
+ #endif
+ #if defined(__RBIT)
+ #undef __RBIT
+ #endif
+ #if defined(__SSAT)
+ #undef __SSAT
+ #endif
+ #if defined(__USAT)
+ #undef __USAT
+ #endif
+
+ #include "iccarm_builtin.h"
+
+ #define __disable_fault_irq __iar_builtin_disable_fiq
+ #define __disable_irq __iar_builtin_disable_interrupt
+ #define __enable_fault_irq __iar_builtin_enable_fiq
+ #define __enable_irq __iar_builtin_enable_interrupt
+ #define __arm_rsr __iar_builtin_rsr
+ #define __arm_wsr __iar_builtin_wsr
+
+
+ #define __get_APSR() (__arm_rsr("APSR"))
+ #define __get_BASEPRI() (__arm_rsr("BASEPRI"))
+ #define __get_CONTROL() (__arm_rsr("CONTROL"))
+ #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
+
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ #define __get_FPSCR() (__arm_rsr("FPSCR"))
+ #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
+ #else
+ #define __get_FPSCR() ( 0 )
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #define __get_IPSR() (__arm_rsr("IPSR"))
+ #define __get_MSP() (__arm_rsr("MSP"))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __get_MSPLIM() (0U)
+ #else
+ #define __get_MSPLIM() (__arm_rsr("MSPLIM"))
+ #endif
+ #define __get_PRIMASK() (__arm_rsr("PRIMASK"))
+ #define __get_PSP() (__arm_rsr("PSP"))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __get_PSPLIM() (0U)
+ #else
+ #define __get_PSPLIM() (__arm_rsr("PSPLIM"))
+ #endif
+
+ #define __get_xPSR() (__arm_rsr("xPSR"))
+
+ #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
+ #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
+ #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
+ #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
+ #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __set_MSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
+ #endif
+ #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
+ #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __set_PSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
+ #endif
+
+ #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
+ #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
+ #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
+ #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
+ #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
+ #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
+ #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
+ #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
+ #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
+ #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
+ #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
+ #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
+ #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
+ #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __TZ_get_PSPLIM_NS() (0U)
+ #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+ #else
+ #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
+ #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+ #endif
+
+ #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
+ #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+ #define __NOP __iar_builtin_no_operation
+
+ #define __CLZ __iar_builtin_CLZ
+ #define __CLREX __iar_builtin_CLREX
+
+ #define __DMB __iar_builtin_DMB
+ #define __DSB __iar_builtin_DSB
+ #define __ISB __iar_builtin_ISB
+
+ #define __LDREXB __iar_builtin_LDREXB
+ #define __LDREXH __iar_builtin_LDREXH
+ #define __LDREXW __iar_builtin_LDREX
+
+ #define __RBIT __iar_builtin_RBIT
+ #define __REV __iar_builtin_REV
+ #define __REV16 __iar_builtin_REV16
+
+ __IAR_FT int16_t __REVSH(int16_t val)
+ {
+ return (int16_t) __iar_builtin_REVSH(val);
+ }
+
+ #define __ROR __iar_builtin_ROR
+ #define __RRX __iar_builtin_RRX
+
+ #define __SEV __iar_builtin_SEV
+
+ #if !__IAR_M0_FAMILY
+ #define __SSAT __iar_builtin_SSAT
+ #endif
+
+ #define __STREXB __iar_builtin_STREXB
+ #define __STREXH __iar_builtin_STREXH
+ #define __STREXW __iar_builtin_STREX
+
+ #if !__IAR_M0_FAMILY
+ #define __USAT __iar_builtin_USAT
+ #endif
+
+ #define __WFE __iar_builtin_WFE
+ #define __WFI __iar_builtin_WFI
+
+ #if __ARM_MEDIA__
+ #define __SADD8 __iar_builtin_SADD8
+ #define __QADD8 __iar_builtin_QADD8
+ #define __SHADD8 __iar_builtin_SHADD8
+ #define __UADD8 __iar_builtin_UADD8
+ #define __UQADD8 __iar_builtin_UQADD8
+ #define __UHADD8 __iar_builtin_UHADD8
+ #define __SSUB8 __iar_builtin_SSUB8
+ #define __QSUB8 __iar_builtin_QSUB8
+ #define __SHSUB8 __iar_builtin_SHSUB8
+ #define __USUB8 __iar_builtin_USUB8
+ #define __UQSUB8 __iar_builtin_UQSUB8
+ #define __UHSUB8 __iar_builtin_UHSUB8
+ #define __SADD16 __iar_builtin_SADD16
+ #define __QADD16 __iar_builtin_QADD16
+ #define __SHADD16 __iar_builtin_SHADD16
+ #define __UADD16 __iar_builtin_UADD16
+ #define __UQADD16 __iar_builtin_UQADD16
+ #define __UHADD16 __iar_builtin_UHADD16
+ #define __SSUB16 __iar_builtin_SSUB16
+ #define __QSUB16 __iar_builtin_QSUB16
+ #define __SHSUB16 __iar_builtin_SHSUB16
+ #define __USUB16 __iar_builtin_USUB16
+ #define __UQSUB16 __iar_builtin_UQSUB16
+ #define __UHSUB16 __iar_builtin_UHSUB16
+ #define __SASX __iar_builtin_SASX
+ #define __QASX __iar_builtin_QASX
+ #define __SHASX __iar_builtin_SHASX
+ #define __UASX __iar_builtin_UASX
+ #define __UQASX __iar_builtin_UQASX
+ #define __UHASX __iar_builtin_UHASX
+ #define __SSAX __iar_builtin_SSAX
+ #define __QSAX __iar_builtin_QSAX
+ #define __SHSAX __iar_builtin_SHSAX
+ #define __USAX __iar_builtin_USAX
+ #define __UQSAX __iar_builtin_UQSAX
+ #define __UHSAX __iar_builtin_UHSAX
+ #define __USAD8 __iar_builtin_USAD8
+ #define __USADA8 __iar_builtin_USADA8
+ #define __SSAT16 __iar_builtin_SSAT16
+ #define __USAT16 __iar_builtin_USAT16
+ #define __UXTB16 __iar_builtin_UXTB16
+ #define __UXTAB16 __iar_builtin_UXTAB16
+ #define __SXTB16 __iar_builtin_SXTB16
+ #define __SXTAB16 __iar_builtin_SXTAB16
+ #define __SMUAD __iar_builtin_SMUAD
+ #define __SMUADX __iar_builtin_SMUADX
+ #define __SMMLA __iar_builtin_SMMLA
+ #define __SMLAD __iar_builtin_SMLAD
+ #define __SMLADX __iar_builtin_SMLADX
+ #define __SMLALD __iar_builtin_SMLALD
+ #define __SMLALDX __iar_builtin_SMLALDX
+ #define __SMUSD __iar_builtin_SMUSD
+ #define __SMUSDX __iar_builtin_SMUSDX
+ #define __SMLSD __iar_builtin_SMLSD
+ #define __SMLSDX __iar_builtin_SMLSDX
+ #define __SMLSLD __iar_builtin_SMLSLD
+ #define __SMLSLDX __iar_builtin_SMLSLDX
+ #define __SEL __iar_builtin_SEL
+ #define __QADD __iar_builtin_QADD
+ #define __QSUB __iar_builtin_QSUB
+ #define __PKHBT __iar_builtin_PKHBT
+ #define __PKHTB __iar_builtin_PKHTB
+ #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #define __CLZ __cmsis_iar_clz_not_active
+ #define __SSAT __cmsis_iar_ssat_not_active
+ #define __USAT __cmsis_iar_usat_not_active
+ #define __RBIT __cmsis_iar_rbit_not_active
+ #define __get_APSR __cmsis_iar_get_APSR_not_active
+ #endif
+
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+ #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+ #endif
+
+ #ifdef __INTRINSICS_INCLUDED
+ #error intrinsics.h is already included previously!
+ #endif
+
+ #include <intrinsics.h>
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #undef __CLZ
+ #undef __SSAT
+ #undef __USAT
+ #undef __RBIT
+ #undef __get_APSR
+
+ __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+ {
+ if (data == 0U) { return 32U; }
+
+ uint32_t count = 0U;
+ uint32_t mask = 0x80000000U;
+
+ while ((data & mask) == 0U)
+ {
+ count += 1U;
+ mask = mask >> 1U;
+ }
+ return count;
+ }
+
+ __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+ {
+ uint8_t sc = 31U;
+ uint32_t r = v;
+ for (v >>= 1U; v; v >>= 1U)
+ {
+ r <<= 1U;
+ r |= v & 1U;
+ sc--;
+ }
+ return (r << sc);
+ }
+
+ __STATIC_INLINE uint32_t __get_APSR(void)
+ {
+ uint32_t res;
+ __asm("MRS %0,APSR" : "=r" (res));
+ return res;
+ }
+
+ #endif
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #undef __get_FPSCR
+ #undef __set_FPSCR
+ #define __get_FPSCR() (0)
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #pragma diag_suppress=Pe940
+ #pragma diag_suppress=Pe177
+
+ #define __enable_irq __enable_interrupt
+ #define __disable_irq __disable_interrupt
+ #define __NOP __no_operation
+
+ #define __get_xPSR __get_PSR
+
+ #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+ __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+ {
+ return __LDREX((unsigned long *)ptr);
+ }
+
+ __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+ {
+ return __STREX(value, (unsigned long *)ptr);
+ }
+ #endif
+
+
+ /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+ #if (__CORTEX_M >= 0x03)
+
+ __IAR_FT uint32_t __RRX(uint32_t value)
+ {
+ uint32_t result;
+ __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
+ return(result);
+ }
+
+ __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
+ }
+
+
+ #define __enable_fault_irq __enable_fiq
+ #define __disable_fault_irq __disable_fiq
+
+
+ #endif /* (__CORTEX_M >= 0x03) */
+
+ __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+ {
+ return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+ }
+
+ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+ __IAR_FT uint32_t __get_MSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,MSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_MSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR MSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __get_PSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_PSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
+ {
+ __asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR PSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_SP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,SP_NS" : "=r" (res));
+ return res;
+ }
+ __IAR_FT void __TZ_set_SP_NS(uint32_t value)
+ {
+ __asm volatile("MSR SP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
+ }
+
+ #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+ __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+ {
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+ }
+
+ __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+ {
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+ }
+#endif
+
+#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+ __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+ {
+ uint32_t res;
+ __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+ {
+ uint32_t res;
+ __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+ {
+ uint32_t res;
+ __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+ {
+ __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+ {
+ __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+ {
+ __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+ }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+
+ __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+ {
+ __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+ {
+ __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+ {
+ __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/cmsis_version.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/cmsis_version.h
new file mode 100644
index 0000000..ae3f2e3
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/cmsis_version.h
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file cmsis_version.h
+ * @brief CMSIS Core(M) Version definitions
+ * @version V5.0.2
+ * @date 19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/* CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
+#endif
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_armv8mbl.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_armv8mbl.h
new file mode 100644
index 0000000..ec76ab2
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_armv8mbl.h
@@ -0,0 +1,1918 @@
+/**************************************************************************//**
+ * @file core_armv8mbl.h
+ * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File
+ * @version V5.0.7
+ * @date 22. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MBL_H_GENERIC
+#define __CORE_ARMV8MBL_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_ARMv8MBL
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS definitions */
+#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
+ __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M ( 2U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MBL_H_DEPENDANT
+#define __CORE_ARMV8MBL_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __ARMv8MBL_REV
+ #define __ARMv8MBL_REV 0x0000U
+ #warning "__ARMv8MBL_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ETM_PRESENT
+ #define __ETM_PRESENT 0U
+ #warning "__ETM_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MTB_PRESENT
+ #define __MTB_PRESENT 0U
+ #warning "__MTB_PRESENT not defined in device header file; using default!"
+ #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MBL */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ uint32_t RESERVED0[6U];
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[809U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
+ uint32_t RESERVED4[4U];
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ uint32_t RESERVED0[7U];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_armv8mml.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_armv8mml.h
new file mode 100644
index 0000000..2d0f106
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_armv8mml.h
@@ -0,0 +1,2927 @@
+/**************************************************************************//**
+ * @file core_armv8mml.h
+ * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
+ * @version V5.0.7
+ * @date 06. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MML_H_GENERIC
+#define __CORE_ARMV8MML_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_ARMv8MML
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS Armv8MML definitions */
+#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
+ __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (81U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MML_H_DEPENDANT
+#define __CORE_ARMV8MML_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __ARMv8MML_REV
+ #define __ARMv8MML_REV 0x0000U
+ #warning "__ARMv8MML_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DSP_PRESENT
+ #define __DSP_PRESENT 0U
+ #warning "__DSP_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MML */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[809U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
+ uint32_t RESERVED4[4U];
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_cm0.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_cm0.h
new file mode 100644
index 0000000..6f82227
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_cm0.h
@@ -0,0 +1,949 @@
+/**************************************************************************//**
+ * @file core_cm0.h
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version V5.0.5
+ * @date 28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M0
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+ __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (0U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0_REV
+ #define __CM0_REV 0x0000U
+ #warning "__CM0_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ Address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)0x0U;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)0x0U;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_cm0plus.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_cm0plus.h
new file mode 100644
index 0000000..b9377e8
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_cm0plus.h
@@ -0,0 +1,1083 @@
+/**************************************************************************//**
+ * @file core_cm0plus.h
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version V5.0.6
+ * @date 28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex-M0+
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+ __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (0U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0PLUS_REV
+ #define __CM0PLUS_REV 0x0000U
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0+ header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_cm1.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_cm1.h
new file mode 100644
index 0000000..fd1c407
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_cm1.h
@@ -0,0 +1,976 @@
+/**************************************************************************//**
+ * @file core_cm1.h
+ * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
+ * @version V1.0.0
+ * @date 23. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM1_H_GENERIC
+#define __CORE_CM1_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M1
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM1 definitions */
+#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
+ __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (1U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM1_H_DEPENDANT
+#define __CORE_CM1_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM1_REV
+ #define __CM1_REV 0x0100U
+ #warning "__CM1_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M1 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
+
+#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M1 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ Address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)0x0U;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)0x0U;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_cm23.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_cm23.h
new file mode 100644
index 0000000..8202a8d
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_cm23.h
@@ -0,0 +1,1993 @@
+/**************************************************************************//**
+ * @file core_cm23.h
+ * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
+ * @version V5.0.7
+ * @date 22. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM23_H_GENERIC
+#define __CORE_CM23_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M23
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS definitions */
+#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
+ __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (23U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM23_H_DEPENDANT
+#define __CORE_CM23_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM23_REV
+ #define __CM23_REV 0x0000U
+ #warning "__CM23_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ETM_PRESENT
+ #define __ETM_PRESENT 0U
+ #warning "__ETM_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MTB_PRESENT
+ #define __MTB_PRESENT 0U
+ #warning "__MTB_PRESENT not defined in device header file; using default!"
+ #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M23 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ uint32_t RESERVED0[6U];
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
+ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
+ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ uint32_t RESERVED0[7U];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_cm3.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_cm3.h
new file mode 100644
index 0000000..b0dfbd3
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_cm3.h
@@ -0,0 +1,1941 @@
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V5.0.8
+ * @date 04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M3
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (3U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM3_REV
+ #define __CM3_REV 0x0200U
+ #warning "__CM3_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_cm33.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_cm33.h
new file mode 100644
index 0000000..02f82e2
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_cm33.h
@@ -0,0 +1,3002 @@
+/**************************************************************************//**
+ * @file core_cm33.h
+ * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File
+ * @version V5.0.9
+ * @date 06. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM33_H_GENERIC
+#define __CORE_CM33_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M33
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM33 definitions */
+#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
+ __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (33U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined (__TARGET_FPU_VFP)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined (__ARM_PCS_VFP)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined (__ARMVFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined (__TI_VFP_SUPPORT__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined (__FPU_VFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM33_H_DEPENDANT
+#define __CORE_CM33_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM33_REV
+ #define __CM33_REV 0x0000U
+ #warning "__CM33_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DSP_PRESENT
+ #define __DSP_PRESENT 0U
+ #warning "__DSP_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M33 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
+ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
+ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_cm4.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_cm4.h
new file mode 100644
index 0000000..308b868
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_cm4.h
@@ -0,0 +1,2129 @@
+/**************************************************************************//**
+ * @file core_cm4.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V5.0.8
+ * @date 04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M4
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (4U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM4_REV
+ #define __CM4_REV 0x0000U
+ #warning "__CM4_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_cm7.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_cm7.h
new file mode 100644
index 0000000..ada6c2a
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_cm7.h
@@ -0,0 +1,2671 @@
+/**************************************************************************//**
+ * @file core_cm7.h
+ * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version V5.0.8
+ * @date 04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M7
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+ __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (7U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM7_REV
+ #define __CM7_REV 0x0000U
+ #warning "__CM7_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ICACHE_PRESENT
+ #define __ICACHE_PRESENT 0U
+ #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DCACHE_PRESENT
+ #define __DCACHE_PRESENT 0U
+ #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DTCM_PRESENT
+ #define __DTCM_PRESENT 0U
+ #warning "__DTCM_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[1U];
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED3[93U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED3[981U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = SCB->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## Cache functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_CacheFunctions Cache Functions
+ \brief Functions that configure Instruction and Data cache.
+ @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
+
+
+/**
+ \brief Enable I-Cache
+ \details Turns on I-Cache
+ */
+__STATIC_INLINE void SCB_EnableICache (void)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ __DSB();
+ __ISB();
+ SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Disable I-Cache
+ \details Turns off I-Cache
+ */
+__STATIC_INLINE void SCB_DisableICache (void)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Invalidate I-Cache
+ \details Invalidates I-Cache
+ */
+__STATIC_INLINE void SCB_InvalidateICache (void)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL;
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Enable D-Cache
+ \details Turns on D-Cache
+ */
+__STATIC_INLINE void SCB_EnableDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+ __DSB();
+
+ SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Disable D-Cache
+ \details Turns off D-Cache
+ */
+__STATIC_INLINE void SCB_DisableDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
+ __DSB();
+
+ SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Invalidate D-Cache
+ \details Invalidates D-Cache
+ */
+__STATIC_INLINE void SCB_InvalidateDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Clean D-Cache
+ \details Cleans D-Cache
+ */
+__STATIC_INLINE void SCB_CleanDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+ ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Clean & Invalidate D-Cache
+ \details Cleans and Invalidates D-Cache
+ */
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief D-Cache Invalidate by address
+ \details Invalidates D-Cache for the given address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t)addr;
+ int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCIMVAC = op_addr;
+ op_addr += (uint32_t)linesize;
+ op_size -= linesize;
+ }
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief D-Cache Clean by address
+ \details Cleans D-Cache for the given address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t) addr;
+ int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCCMVAC = op_addr;
+ op_addr += (uint32_t)linesize;
+ op_size -= linesize;
+ }
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief D-Cache Clean and Invalidate by address
+ \details Cleans and invalidates D_Cache for the given address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t) addr;
+ int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCCIMVAC = op_addr;
+ op_addr += (uint32_t)linesize;
+ op_size -= linesize;
+ }
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_sc000.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_sc000.h
new file mode 100644
index 0000000..9086c64
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_sc000.h
@@ -0,0 +1,1022 @@
+/**************************************************************************//**
+ * @file core_sc000.h
+ * @brief CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version V5.0.5
+ * @date 28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup SC000
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+ __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC (000U) /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __SC000_REV
+ #define __SC000_REV 0x0000U
+ #warning "__SC000_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ uint32_t RESERVED1[154U];
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the SC000 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_sc300.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_sc300.h
new file mode 100644
index 0000000..665822d
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/core_sc300.h
@@ -0,0 +1,1915 @@
+/**************************************************************************//**
+ * @file core_sc300.h
+ * @brief CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version V5.0.6
+ * @date 04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup SC3000
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
+ __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC (300U) /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __SC300_REV
+ #define __SC300_REV 0x0000U
+ #warning "__SC300_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED1[129U];
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ uint32_t RESERVED1[1U];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/mpu_armv7.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/mpu_armv7.h
new file mode 100644
index 0000000..7d4b600
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/mpu_armv7.h
@@ -0,0 +1,270 @@
+/******************************************************************************
+ * @file mpu_armv7.h
+ * @brief CMSIS MPU API for Armv7-M MPU
+ * @version V5.0.4
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+ (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
+ ((Region) & MPU_RBAR_REGION_Msk) | \
+ (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+*
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable Region is shareable between multiple bus masters.
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
+ ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
+ (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
+ (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
+ (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable Sub-region disable field.
+* \param Size Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
+ ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
+ (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
+ (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable Region is shareable between multiple bus masters.
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable Sub-region disable field.
+* \param Size Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+ ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+* - TEX: 000b
+* - Shareable
+* - Non-cacheable
+* - Non-bufferable
+*/
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+* - TEX: 000b (if non-shareable) or 010b (if shareable)
+* - Shareable or non-shareable
+* - Non-cacheable
+* - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+* - TEX: 1BBb (reflecting outer cacheability rules)
+* - Shareable or non-shareable
+* - Cacheable or non-cacheable (reflecting inner cacheability rules)
+* - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+ uint32_t RBAR; //!< The region base address register value (RBAR)
+ uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+ __DSB();
+ __ISB();
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+ __DSB();
+ __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+ MPU->RNR = rnr;
+ MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+ MPU->RNR = rnr;
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+ uint32_t i;
+ for (i = 0U; i < len; ++i)
+ {
+ dst[i] = src[i];
+ }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+ while (cnt > MPU_TYPE_RALIASES) {
+ orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+ table += MPU_TYPE_RALIASES;
+ cnt -= MPU_TYPE_RALIASES;
+ }
+ orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/mpu_armv8.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/mpu_armv8.h
new file mode 100644
index 0000000..99ee9f9
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/mpu_armv8.h
@@ -0,0 +1,333 @@
+/******************************************************************************
+ * @file mpu_armv8.h
+ * @brief CMSIS MPU API for Armv8-M MPU
+ * @version V5.0.4
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+ (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable */
+#define ARM_MPU_SH_NON (0U)
+
+/** \brief Normal memory outer shareable */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+ ((BASE & MPU_RBAR_BASE_Msk) | \
+ ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+ ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+ ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+ ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+ ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+ (MPU_RLAR_EN_Msk))
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+ uint32_t RBAR; /*!< Region Base Address Register value */
+ uint32_t RLAR; /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+ __DSB();
+ __ISB();
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+ __DSB();
+ __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+ __DSB();
+ __ISB();
+ MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+ __DSB();
+ __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+ const uint8_t reg = idx / 4U;
+ const uint32_t pos = ((idx % 4U) * 8U);
+ const uint32_t mask = 0xFFU << pos;
+
+ if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+ return; // invalid index
+ }
+
+ mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+ ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+ ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+ mpu->RNR = rnr;
+ mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+ ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{
+ ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+ mpu->RNR = rnr;
+ mpu->RBAR = rbar;
+ mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+ ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+ ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
+}
+#endif
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+ uint32_t i;
+ for (i = 0U; i < len; ++i)
+ {
+ dst[i] = src[i];
+ }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+ if (cnt == 1U) {
+ mpu->RNR = rnr;
+ orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+ } else {
+ uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
+ uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+
+ mpu->RNR = rnrBase;
+ while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+ uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+ orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+ table += c;
+ cnt -= c;
+ rnrOffset = 0U;
+ rnrBase += MPU_TYPE_RALIASES;
+ mpu->RNR = rnrBase;
+ }
+
+ orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+ }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/tz_context.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/tz_context.h
new file mode 100644
index 0000000..d4c1474
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Include/tz_context.h
@@ -0,0 +1,70 @@
+/******************************************************************************
+ * @file tz_context.h
+ * @brief Context Management for Armv8-M TrustZone
+ * @version V1.0.1
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+
+#include <stdint.h>
+
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in] module identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0 no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+
+#endif // TZ_CONTEXT_H
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Template/ARMv8-M/main_s.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Template/ARMv8-M/main_s.c
new file mode 100644
index 0000000..cde9ff0
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Template/ARMv8-M/main_s.c
@@ -0,0 +1,58 @@
+/******************************************************************************
+ * @file main_s.c
+ * @brief Code template for secure main function
+ * @version V1.1.1
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Use CMSE intrinsics */
+#include <arm_cmse.h>
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+/* TZ_START_NS: Start address of non-secure application */
+#ifndef TZ_START_NS
+#define TZ_START_NS (0x200000U)
+#endif
+
+/* typedef for non-secure callback functions */
+typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call));
+
+/* Secure main() */
+int main(void) {
+ funcptr_void NonSecure_ResetHandler;
+
+ /* Add user setup code for secure part here*/
+
+ /* Set non-secure main stack (MSP_NS) */
+ __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS)));
+
+ /* Get non-secure reset handler */
+ NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U)));
+
+ /* Start non-secure state software application */
+ NonSecure_ResetHandler();
+
+ /* Non-secure software does not return, this code is not executed */
+ while (1) {
+ __NOP();
+ }
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Template/ARMv8-M/tz_context.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Template/ARMv8-M/tz_context.c
new file mode 100644
index 0000000..298bbf7
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core/Template/ARMv8-M/tz_context.c
@@ -0,0 +1,200 @@
+/******************************************************************************
+ * @file tz_context.c
+ * @brief Context Management for Armv8-M TrustZone - Sample implementation
+ * @version V1.1.1
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2016-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+#include "tz_context.h"
+
+/// Number of process slots (threads may call secure library code)
+#ifndef TZ_PROCESS_STACK_SLOTS
+#define TZ_PROCESS_STACK_SLOTS 8U
+#endif
+
+/// Stack size of the secure library code
+#ifndef TZ_PROCESS_STACK_SIZE
+#define TZ_PROCESS_STACK_SIZE 256U
+#endif
+
+typedef struct {
+ uint32_t sp_top; // stack space top
+ uint32_t sp_limit; // stack space limit
+ uint32_t sp; // current stack pointer
+} stack_info_t;
+
+static stack_info_t ProcessStackInfo [TZ_PROCESS_STACK_SLOTS];
+static uint64_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U];
+static uint32_t ProcessStackFreeSlot = 0xFFFFFFFFU;
+
+
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+__attribute__((cmse_nonsecure_entry))
+uint32_t TZ_InitContextSystem_S (void) {
+ uint32_t n;
+
+ if (__get_IPSR() == 0U) {
+ return 0U; // Thread Mode
+ }
+
+ for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) {
+ ProcessStackInfo[n].sp = 0U;
+ ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n];
+ ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE;
+ *((uint32_t *)ProcessStackMemory[n]) = n + 1U;
+ }
+ *((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU;
+
+ ProcessStackFreeSlot = 0U;
+
+ // Default process stack pointer and stack limit
+ __set_PSPLIM((uint32_t)ProcessStackMemory);
+ __set_PSP ((uint32_t)ProcessStackMemory);
+
+ // Privileged Thread Mode using PSP
+ __set_CONTROL(0x02U);
+
+ return 1U; // Success
+}
+
+
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in] module identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0 no memory available or internal error
+__attribute__((cmse_nonsecure_entry))
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) {
+ uint32_t slot;
+
+ (void)module; // Ignore (fixed Stack size)
+
+ if (__get_IPSR() == 0U) {
+ return 0U; // Thread Mode
+ }
+
+ if (ProcessStackFreeSlot == 0xFFFFFFFFU) {
+ return 0U; // No slot available
+ }
+
+ slot = ProcessStackFreeSlot;
+ ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]);
+
+ ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top;
+
+ return (slot + 1U);
+}
+
+
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+__attribute__((cmse_nonsecure_entry))
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) {
+ uint32_t slot;
+
+ if (__get_IPSR() == 0U) {
+ return 0U; // Thread Mode
+ }
+
+ if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
+ return 0U; // Invalid ID
+ }
+
+ slot = id - 1U;
+
+ if (ProcessStackInfo[slot].sp == 0U) {
+ return 0U; // Inactive slot
+ }
+ ProcessStackInfo[slot].sp = 0U;
+
+ *((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot;
+ ProcessStackFreeSlot = slot;
+
+ return 1U; // Success
+}
+
+
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+__attribute__((cmse_nonsecure_entry))
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) {
+ uint32_t slot;
+
+ if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
+ return 0U; // Thread Mode or using Main Stack for threads
+ }
+
+ if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
+ return 0U; // Invalid ID
+ }
+
+ slot = id - 1U;
+
+ if (ProcessStackInfo[slot].sp == 0U) {
+ return 0U; // Inactive slot
+ }
+
+ // Setup process stack pointer and stack limit
+ __set_PSPLIM(ProcessStackInfo[slot].sp_limit);
+ __set_PSP (ProcessStackInfo[slot].sp);
+
+ return 1U; // Success
+}
+
+
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+__attribute__((cmse_nonsecure_entry))
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) {
+ uint32_t slot;
+ uint32_t sp;
+
+ if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
+ return 0U; // Thread Mode or using Main Stack for threads
+ }
+
+ if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
+ return 0U; // Invalid ID
+ }
+
+ slot = id - 1U;
+
+ if (ProcessStackInfo[slot].sp == 0U) {
+ return 0U; // Inactive slot
+ }
+
+ sp = __get_PSP();
+ if ((sp < ProcessStackInfo[slot].sp_limit) ||
+ (sp > ProcessStackInfo[slot].sp_top)) {
+ return 0U; // SP out of range
+ }
+ ProcessStackInfo[slot].sp = sp;
+
+ // Default process stack pointer and stack limit
+ __set_PSPLIM((uint32_t)ProcessStackMemory);
+ __set_PSP ((uint32_t)ProcessStackMemory);
+
+ return 1U; // Success
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Include/cmsis_armcc.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Include/cmsis_armcc.h
new file mode 100644
index 0000000..b2ccb1f
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Include/cmsis_armcc.h
@@ -0,0 +1,544 @@
+/**************************************************************************//**
+ * @file cmsis_armcc.h
+ * @brief CMSIS compiler specific macros, functions, instructions
+ * @version V1.0.2
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+ #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if (defined (__TARGET_ARCH_7_A ) && (__TARGET_ARCH_7_A == 1))
+ #define __ARM_ARCH_7A__ 1
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __FORCEINLINE
+ #define __FORCEINLINE __forceinline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE static __forceinline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __declspec(noreturn)
+#endif
+#ifndef CMSIS_DEPRECATED
+ #define CMSIS_DEPRECATED __attribute__((deprecated))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT __packed struct
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+#endif
+
+/* ########################## Core Instruction Access ######################### */
+/**
+ \brief No Operation
+ */
+#define __NOP __nop
+
+/**
+ \brief Wait For Interrupt
+ */
+#define __WFI __wfi
+
+/**
+ \brief Wait For Event
+ */
+#define __WFE __wfe
+
+/**
+ \brief Send Event
+ */
+#define __SEV __sev
+
+/**
+ \brief Instruction Synchronization Barrier
+ */
+#define __ISB() do {\
+ __schedule_barrier();\
+ __isb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Synchronization Barrier
+ */
+#define __DSB() do {\
+ __schedule_barrier();\
+ __dsb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Memory Barrier
+ */
+#define __DMB() do {\
+ __schedule_barrier();\
+ __dmb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+/**
+ \brief Breakpoint
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+/**
+ \brief Reverse bit order of value
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __rbit
+
+/**
+ \brief Count leading zeros
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+#else
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+#else
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+#else
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXB(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXH(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXW(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+/* ########################### Core Function Access ########################### */
+
+/**
+ \brief Get FPSCR (Floating Point Status/Control)
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0U);
+#endif
+}
+
+/**
+ \brief Set FPSCR (Floating Point Status/Control)
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#else
+ (void)fpscr;
+#endif
+}
+
+/** \brief Get CPSR (Current Program Status Register)
+ \return CPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_CPSR(void)
+{
+ register uint32_t __regCPSR __ASM("cpsr");
+ return(__regCPSR);
+}
+
+
+/** \brief Set CPSR (Current Program Status Register)
+ \param [in] cpsr CPSR value to set
+ */
+__STATIC_INLINE void __set_CPSR(uint32_t cpsr)
+{
+ register uint32_t __regCPSR __ASM("cpsr");
+ __regCPSR = cpsr;
+}
+
+/** \brief Get Mode
+ \return Processor Mode
+ */
+__STATIC_INLINE uint32_t __get_mode(void)
+{
+ return (__get_CPSR() & 0x1FU);
+}
+
+/** \brief Set Mode
+ \param [in] mode Mode value to set
+ */
+__STATIC_INLINE __ASM void __set_mode(uint32_t mode)
+{
+ MOV r1, lr
+ MSR CPSR_C, r0
+ BX r1
+}
+
+/** \brief Get Stack Pointer
+ \return Stack Pointer
+ */
+__STATIC_INLINE __ASM uint32_t __get_SP(void)
+{
+ MOV r0, sp
+ BX lr
+}
+
+/** \brief Set Stack Pointer
+ \param [in] stack Stack Pointer value to set
+ */
+__STATIC_INLINE __ASM void __set_SP(uint32_t stack)
+{
+ MOV sp, r0
+ BX lr
+}
+
+
+/** \brief Get USR/SYS Stack Pointer
+ \return USR/SYSStack Pointer
+ */
+__STATIC_INLINE __ASM uint32_t __get_SP_usr(void)
+{
+ ARM
+ PRESERVE8
+
+ MRS R1, CPSR
+ CPS #0x1F ;no effect in USR mode
+ MOV R0, SP
+ MSR CPSR_c, R1 ;no effect in USR mode
+ ISB
+ BX LR
+}
+
+/** \brief Set USR/SYS Stack Pointer
+ \param [in] topOfProcStack USR/SYS Stack Pointer value to set
+ */
+__STATIC_INLINE __ASM void __set_SP_usr(uint32_t topOfProcStack)
+{
+ ARM
+ PRESERVE8
+
+ MRS R1, CPSR
+ CPS #0x1F ;no effect in USR mode
+ MOV SP, R0
+ MSR CPSR_c, R1 ;no effect in USR mode
+ ISB
+ BX LR
+}
+
+/** \brief Get FPEXC (Floating Point Exception Control Register)
+ \return Floating Point Exception Control Register value
+ */
+__STATIC_INLINE uint32_t __get_FPEXC(void)
+{
+#if (__FPU_PRESENT == 1)
+ register uint32_t __regfpexc __ASM("fpexc");
+ return(__regfpexc);
+#else
+ return(0);
+#endif
+}
+
+/** \brief Set FPEXC (Floating Point Exception Control Register)
+ \param [in] fpexc Floating Point Exception Control value to set
+ */
+__STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
+{
+#if (__FPU_PRESENT == 1)
+ register uint32_t __regfpexc __ASM("fpexc");
+ __regfpexc = (fpexc);
+#endif
+}
+
+/*
+ * Include common core functions to access Coprocessor 15 registers
+ */
+
+#define __get_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); (Rt) = tmp; } while(0)
+#define __set_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = (Rt); } while(0)
+#define __get_CP64(cp, op1, Rt, CRm) \
+ do { \
+ uint32_t ltmp, htmp; \
+ __ASM volatile("MRRC p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \
+ (Rt) = ((((uint64_t)htmp) << 32U) | ((uint64_t)ltmp)); \
+ } while(0)
+
+#define __set_CP64(cp, op1, Rt, CRm) \
+ do { \
+ const uint64_t tmp = (Rt); \
+ const uint32_t ltmp = (uint32_t)(tmp); \
+ const uint32_t htmp = (uint32_t)(tmp >> 32U); \
+ __ASM volatile("MCRR p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \
+ } while(0)
+
+#include "cmsis_cp15.h"
+
+/** \brief Enable Floating Point Unit
+
+ Critical section, called from undef handler, so systick is disabled
+ */
+__STATIC_INLINE __ASM void __FPU_Enable(void)
+{
+ ARM
+
+ //Permit access to VFP/NEON, registers by modifying CPACR
+ MRC p15,0,R1,c1,c0,2
+ ORR R1,R1,#0x00F00000
+ MCR p15,0,R1,c1,c0,2
+
+ //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+ ISB
+
+ //Enable VFP/NEON
+ VMRS R1,FPEXC
+ ORR R1,R1,#0x40000000
+ VMSR FPEXC,R1
+
+ //Initialise VFP/NEON registers to 0
+ MOV R2,#0
+
+ //Initialise D16 registers to 0
+ VMOV D0, R2,R2
+ VMOV D1, R2,R2
+ VMOV D2, R2,R2
+ VMOV D3, R2,R2
+ VMOV D4, R2,R2
+ VMOV D5, R2,R2
+ VMOV D6, R2,R2
+ VMOV D7, R2,R2
+ VMOV D8, R2,R2
+ VMOV D9, R2,R2
+ VMOV D10,R2,R2
+ VMOV D11,R2,R2
+ VMOV D12,R2,R2
+ VMOV D13,R2,R2
+ VMOV D14,R2,R2
+ VMOV D15,R2,R2
+
+ IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
+ //Initialise D32 registers to 0
+ VMOV D16,R2,R2
+ VMOV D17,R2,R2
+ VMOV D18,R2,R2
+ VMOV D19,R2,R2
+ VMOV D20,R2,R2
+ VMOV D21,R2,R2
+ VMOV D22,R2,R2
+ VMOV D23,R2,R2
+ VMOV D24,R2,R2
+ VMOV D25,R2,R2
+ VMOV D26,R2,R2
+ VMOV D27,R2,R2
+ VMOV D28,R2,R2
+ VMOV D29,R2,R2
+ VMOV D30,R2,R2
+ VMOV D31,R2,R2
+ ENDIF
+
+ //Initialise FPSCR to a known state
+ VMRS R2,FPSCR
+ LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+ AND R2,R2,R3
+ VMSR FPSCR,R2
+
+ BX LR
+}
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Include/cmsis_armclang.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Include/cmsis_armclang.h
new file mode 100644
index 0000000..e0de5a4
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Include/cmsis_armclang.h
@@ -0,0 +1,503 @@
+/**************************************************************************//**
+ * @file cmsis_armclang.h
+ * @brief CMSIS compiler specific macros, functions, instructions
+ * @version V1.0.2
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __FORCEINLINE
+ #define __FORCEINLINE __attribute__((always_inline))
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef CMSIS_DEPRECATED
+ #define CMSIS_DEPRECATED __attribute__((deprecated))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+#endif
+
+/* ########################## Core Instruction Access ######################### */
+/**
+ \brief No Operation
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ */
+#define __WFI __builtin_arm_wfi
+
+/**
+ \brief Wait For Event
+ */
+#define __WFE __builtin_arm_wfe
+
+/**
+ \brief Send Event
+ */
+#define __SEV __builtin_arm_sev
+
+/**
+ \brief Instruction Synchronization Barrier
+ */
+#define __ISB() do {\
+ __schedule_barrier();\
+ __builtin_arm_isb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Synchronization Barrier
+ */
+#define __DSB() do {\
+ __schedule_barrier();\
+ __builtin_arm_dsb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Memory Barrier
+ */
+#define __DMB() do {\
+ __schedule_barrier();\
+ __builtin_arm_dmb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV(value) __builtin_bswap32(value)
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+/**
+ \brief Reverse bit order of value
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __builtin_arm_rbit
+
+/**
+ \brief Count leading zeros
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ (uint8_t)__builtin_clz
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/* ########################### Core Function Access ########################### */
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#define __get_FPSCR __builtin_arm_get_fpscr
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#define __set_FPSCR __builtin_arm_set_fpscr
+
+/** \brief Get CPSR Register
+ \return CPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
+{
+ uint32_t result;
+ __ASM volatile("MRS %0, cpsr" : "=r" (result) );
+ return(result);
+}
+
+/** \brief Set CPSR Register
+ \param [in] cpsr CPSR value to set
+ */
+__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
+{
+__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
+}
+
+/** \brief Get Mode
+ \return Processor Mode
+ */
+__STATIC_FORCEINLINE uint32_t __get_mode(void)
+{
+ return (__get_CPSR() & 0x1FU);
+}
+
+/** \brief Set Mode
+ \param [in] mode Mode value to set
+ */
+__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
+{
+ __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
+}
+
+/** \brief Get Stack Pointer
+ \return Stack Pointer value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SP()
+{
+ uint32_t result;
+ __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory");
+ return result;
+}
+
+/** \brief Set Stack Pointer
+ \param [in] stack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
+{
+ __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
+}
+
+/** \brief Get USR/SYS Stack Pointer
+ \return USR/SYS Stack Pointer value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SP_usr()
+{
+ uint32_t cpsr;
+ uint32_t result;
+ __ASM volatile(
+ "MRS %0, cpsr \n"
+ "CPS #0x1F \n" // no effect in USR mode
+ "MOV %1, sp \n"
+ "MSR cpsr_c, %2 \n" // no effect in USR mode
+ "ISB" : "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory"
+ );
+ return result;
+}
+
+/** \brief Set USR/SYS Stack Pointer
+ \param [in] topOfProcStack USR/SYS Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
+{
+ uint32_t cpsr;
+ __ASM volatile(
+ "MRS %0, cpsr \n"
+ "CPS #0x1F \n" // no effect in USR mode
+ "MOV sp, %1 \n"
+ "MSR cpsr_c, %2 \n" // no effect in USR mode
+ "ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory"
+ );
+}
+
+/** \brief Get FPEXC
+ \return Floating Point Exception Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
+{
+#if (__FPU_PRESENT == 1)
+ uint32_t result;
+ __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+/** \brief Set FPEXC
+ \param [in] fpexc Floating Point Exception Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
+{
+#if (__FPU_PRESENT == 1)
+ __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
+#endif
+}
+
+/*
+ * Include common core functions to access Coprocessor 15 registers
+ */
+
+#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
+#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
+#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
+#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
+
+#include "cmsis_cp15.h"
+
+/** \brief Enable Floating Point Unit
+
+ Critical section, called from undef handler, so systick is disabled
+ */
+__STATIC_INLINE void __FPU_Enable(void)
+{
+ __ASM volatile(
+ //Permit access to VFP/NEON, registers by modifying CPACR
+ " MRC p15,0,R1,c1,c0,2 \n"
+ " ORR R1,R1,#0x00F00000 \n"
+ " MCR p15,0,R1,c1,c0,2 \n"
+
+ //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+ " ISB \n"
+
+ //Enable VFP/NEON
+ " VMRS R1,FPEXC \n"
+ " ORR R1,R1,#0x40000000 \n"
+ " VMSR FPEXC,R1 \n"
+
+ //Initialise VFP/NEON registers to 0
+ " MOV R2,#0 \n"
+
+ //Initialise D16 registers to 0
+ " VMOV D0, R2,R2 \n"
+ " VMOV D1, R2,R2 \n"
+ " VMOV D2, R2,R2 \n"
+ " VMOV D3, R2,R2 \n"
+ " VMOV D4, R2,R2 \n"
+ " VMOV D5, R2,R2 \n"
+ " VMOV D6, R2,R2 \n"
+ " VMOV D7, R2,R2 \n"
+ " VMOV D8, R2,R2 \n"
+ " VMOV D9, R2,R2 \n"
+ " VMOV D10,R2,R2 \n"
+ " VMOV D11,R2,R2 \n"
+ " VMOV D12,R2,R2 \n"
+ " VMOV D13,R2,R2 \n"
+ " VMOV D14,R2,R2 \n"
+ " VMOV D15,R2,R2 \n"
+
+#if __ARM_NEON == 1
+ //Initialise D32 registers to 0
+ " VMOV D16,R2,R2 \n"
+ " VMOV D17,R2,R2 \n"
+ " VMOV D18,R2,R2 \n"
+ " VMOV D19,R2,R2 \n"
+ " VMOV D20,R2,R2 \n"
+ " VMOV D21,R2,R2 \n"
+ " VMOV D22,R2,R2 \n"
+ " VMOV D23,R2,R2 \n"
+ " VMOV D24,R2,R2 \n"
+ " VMOV D25,R2,R2 \n"
+ " VMOV D26,R2,R2 \n"
+ " VMOV D27,R2,R2 \n"
+ " VMOV D28,R2,R2 \n"
+ " VMOV D29,R2,R2 \n"
+ " VMOV D30,R2,R2 \n"
+ " VMOV D31,R2,R2 \n"
+#endif
+
+ //Initialise FPSCR to a known state
+ " VMRS R2,FPSCR \n"
+ " LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+ " AND R2,R2,R3 \n"
+ " VMSR FPSCR,R2 "
+ );
+}
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Include/cmsis_compiler.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Include/cmsis_compiler.h
new file mode 100644
index 0000000..cd14cbc
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Include/cmsis_compiler.h
@@ -0,0 +1,201 @@
+/**************************************************************************//**
+ * @file cmsis_compiler.h
+ * @brief CMSIS compiler specific macros, functions, instructions
+ * @version V1.0.2
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+ #include "cmsis_iccarm.h"
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+ #include <cmsis_ccs.h>
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef CMSIS_DEPRECATED
+ #define CMSIS_DEPRECATED __attribute__((deprecated))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __UNALIGNED_UINT32
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+ #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef CMSIS_DEPRECATED
+ #define CMSIS_DEPRECATED __attribute__((deprecated))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __UNALIGNED_UINT32
+ struct __packed__ T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __align(x)
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __packed__
+ #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+ #include <cmsis_csm.h>
+
+ #ifndef __ASM
+ #define __ASM _asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ // NO RETURN is automatically detected hence no warning here
+ #define __NO_RETURN
+ #endif
+ #ifndef __USED
+ #warning No compiler specific solution for __USED. __USED is ignored.
+ #define __USED
+ #endif
+ #ifndef CMSIS_DEPRECATED
+ #warning No compiler specific solution for CMSIS_DEPRECATED. CMSIS_DEPRECATED is ignored.
+ #define CMSIS_DEPRECATED
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __weak
+ #endif
+ #ifndef __UNALIGNED_UINT32
+ @packed struct T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __ALIGNED
+ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+ #ifndef __PACKED
+ #define __PACKED @packed
+ #endif
+
+
+#else
+ #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Include/cmsis_cp15.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Include/cmsis_cp15.h
new file mode 100644
index 0000000..75e57b8
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Include/cmsis_cp15.h
@@ -0,0 +1,514 @@
+/**************************************************************************//**
+ * @file cmsis_cp15.h
+ * @brief CMSIS compiler specific macros, functions, instructions
+ * @version V1.0.1
+ * @date 07. Sep 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_CP15_H
+#define __CMSIS_CP15_H
+
+/** \brief Get ACTLR
+ \return Auxiliary Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_ACTLR(void)
+{
+ uint32_t result;
+ __get_CP(15, 0, result, 1, 0, 1);
+ return(result);
+}
+
+/** \brief Set ACTLR
+ \param [in] actlr Auxiliary Control value to set
+ */
+__STATIC_FORCEINLINE void __set_ACTLR(uint32_t actlr)
+{
+ __set_CP(15, 0, actlr, 1, 0, 1);
+}
+
+/** \brief Get CPACR
+ \return Coprocessor Access Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CPACR(void)
+{
+ uint32_t result;
+ __get_CP(15, 0, result, 1, 0, 2);
+ return result;
+}
+
+/** \brief Set CPACR
+ \param [in] cpacr Coprocessor Access Control value to set
+ */
+__STATIC_FORCEINLINE void __set_CPACR(uint32_t cpacr)
+{
+ __set_CP(15, 0, cpacr, 1, 0, 2);
+}
+
+/** \brief Get DFSR
+ \return Data Fault Status Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_DFSR(void)
+{
+ uint32_t result;
+ __get_CP(15, 0, result, 5, 0, 0);
+ return result;
+}
+
+/** \brief Set DFSR
+ \param [in] dfsr Data Fault Status value to set
+ */
+__STATIC_FORCEINLINE void __set_DFSR(uint32_t dfsr)
+{
+ __set_CP(15, 0, dfsr, 5, 0, 0);
+}
+
+/** \brief Get IFSR
+ \return Instruction Fault Status Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IFSR(void)
+{
+ uint32_t result;
+ __get_CP(15, 0, result, 5, 0, 1);
+ return result;
+}
+
+/** \brief Set IFSR
+ \param [in] ifsr Instruction Fault Status value to set
+ */
+__STATIC_FORCEINLINE void __set_IFSR(uint32_t ifsr)
+{
+ __set_CP(15, 0, ifsr, 5, 0, 1);
+}
+
+/** \brief Get ISR
+ \return Interrupt Status Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_ISR(void)
+{
+ uint32_t result;
+ __get_CP(15, 0, result, 12, 1, 0);
+ return result;
+}
+
+/** \brief Get CBAR
+ \return Configuration Base Address register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CBAR(void)
+{
+ uint32_t result;
+ __get_CP(15, 4, result, 15, 0, 0);
+ return result;
+}
+
+/** \brief Get TTBR0
+
+ This function returns the value of the Translation Table Base Register 0.
+
+ \return Translation Table Base Register 0 value
+ */
+__STATIC_FORCEINLINE uint32_t __get_TTBR0(void)
+{
+ uint32_t result;
+ __get_CP(15, 0, result, 2, 0, 0);
+ return result;
+}
+
+/** \brief Set TTBR0
+
+ This function assigns the given value to the Translation Table Base Register 0.
+
+ \param [in] ttbr0 Translation Table Base Register 0 value to set
+ */
+__STATIC_FORCEINLINE void __set_TTBR0(uint32_t ttbr0)
+{
+ __set_CP(15, 0, ttbr0, 2, 0, 0);
+}
+
+/** \brief Get DACR
+
+ This function returns the value of the Domain Access Control Register.
+
+ \return Domain Access Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_DACR(void)
+{
+ uint32_t result;
+ __get_CP(15, 0, result, 3, 0, 0);
+ return result;
+}
+
+/** \brief Set DACR
+
+ This function assigns the given value to the Domain Access Control Register.
+
+ \param [in] dacr Domain Access Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_DACR(uint32_t dacr)
+{
+ __set_CP(15, 0, dacr, 3, 0, 0);
+}
+
+/** \brief Set SCTLR
+
+ This function assigns the given value to the System Control Register.
+
+ \param [in] sctlr System Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr)
+{
+ __set_CP(15, 0, sctlr, 1, 0, 0);
+}
+
+/** \brief Get SCTLR
+ \return System Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SCTLR(void)
+{
+ uint32_t result;
+ __get_CP(15, 0, result, 1, 0, 0);
+ return result;
+}
+
+/** \brief Set ACTRL
+ \param [in] actrl Auxiliary Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_ACTRL(uint32_t actrl)
+{
+ __set_CP(15, 0, actrl, 1, 0, 1);
+}
+
+/** \brief Get ACTRL
+ \return Auxiliary Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_ACTRL(void)
+{
+ uint32_t result;
+ __get_CP(15, 0, result, 1, 0, 1);
+ return result;
+}
+
+/** \brief Get MPIDR
+
+ This function returns the value of the Multiprocessor Affinity Register.
+
+ \return Multiprocessor Affinity Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MPIDR(void)
+{
+ uint32_t result;
+ __get_CP(15, 0, result, 0, 0, 5);
+ return result;
+}
+
+/** \brief Get VBAR
+
+ This function returns the value of the Vector Base Address Register.
+
+ \return Vector Base Address Register
+ */
+__STATIC_FORCEINLINE uint32_t __get_VBAR(void)
+{
+ uint32_t result;
+ __get_CP(15, 0, result, 12, 0, 0);
+ return result;
+}
+
+/** \brief Set VBAR
+
+ This function assigns the given value to the Vector Base Address Register.
+
+ \param [in] vbar Vector Base Address Register value to set
+ */
+__STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar)
+{
+ __set_CP(15, 0, vbar, 12, 0, 0);
+}
+
+/** \brief Get MVBAR
+
+ This function returns the value of the Monitor Vector Base Address Register.
+
+ \return Monitor Vector Base Address Register
+ */
+__STATIC_FORCEINLINE uint32_t __get_MVBAR(void)
+{
+ uint32_t result;
+ __get_CP(15, 0, result, 12, 0, 1);
+ return result;
+}
+
+/** \brief Set MVBAR
+
+ This function assigns the given value to the Monitor Vector Base Address Register.
+
+ \param [in] mvbar Monitor Vector Base Address Register value to set
+ */
+__STATIC_FORCEINLINE void __set_MVBAR(uint32_t mvbar)
+{
+ __set_CP(15, 0, mvbar, 12, 0, 1);
+}
+
+#if (defined(__CORTEX_A) && (__CORTEX_A == 7U) && \
+ defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \
+ defined(DOXYGEN)
+
+/** \brief Set CNTFRQ
+
+ This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ).
+
+ \param [in] value CNTFRQ Register value to set
+*/
+__STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value)
+{
+ __set_CP(15, 0, value, 14, 0, 0);
+}
+
+/** \brief Get CNTFRQ
+
+ This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ).
+
+ \return CNTFRQ Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void)
+{
+ uint32_t result;
+ __get_CP(15, 0, result, 14, 0 , 0);
+ return result;
+}
+
+/** \brief Set CNTP_TVAL
+
+ This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL).
+
+ \param [in] value CNTP_TVAL Register value to set
+*/
+__STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value)
+{
+ __set_CP(15, 0, value, 14, 2, 0);
+}
+
+/** \brief Get CNTP_TVAL
+
+ This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL).
+
+ \return CNTP_TVAL Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void)
+{
+ uint32_t result;
+ __get_CP(15, 0, result, 14, 2, 0);
+ return result;
+}
+
+/** \brief Get CNTPCT
+
+ This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT).
+
+ \return CNTPCT Register value
+ */
+__STATIC_FORCEINLINE uint64_t __get_CNTPCT(void)
+{
+ uint64_t result;
+ __get_CP64(15, 0, result, 14);
+ return result;
+}
+
+/** \brief Set CNTP_CVAL
+
+ This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
+
+ \param [in] value CNTP_CVAL Register value to set
+*/
+__STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value)
+{
+ __set_CP64(15, 2, value, 14);
+}
+
+/** \brief Get CNTP_CVAL
+
+ This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
+
+ \return CNTP_CVAL Register value
+ */
+__STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void)
+{
+ uint64_t result;
+ __get_CP64(15, 2, result, 14);
+ return result;
+}
+
+/** \brief Set CNTP_CTL
+
+ This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
+
+ \param [in] value CNTP_CTL Register value to set
+*/
+__STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value)
+{
+ __set_CP(15, 0, value, 14, 2, 1);
+}
+
+/** \brief Get CNTP_CTL register
+ \return CNTP_CTL Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void)
+{
+ uint32_t result;
+ __get_CP(15, 0, result, 14, 2, 1);
+ return result;
+}
+
+#endif
+
+/** \brief Set TLBIALL
+
+ TLB Invalidate All
+ */
+__STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value)
+{
+ __set_CP(15, 0, value, 8, 7, 0);
+}
+
+/** \brief Set BPIALL.
+
+ Branch Predictor Invalidate All
+ */
+__STATIC_FORCEINLINE void __set_BPIALL(uint32_t value)
+{
+ __set_CP(15, 0, value, 7, 5, 6);
+}
+
+/** \brief Set ICIALLU
+
+ Instruction Cache Invalidate All
+ */
+__STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value)
+{
+ __set_CP(15, 0, value, 7, 5, 0);
+}
+
+/** \brief Set DCCMVAC
+
+ Data cache clean
+ */
+__STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value)
+{
+ __set_CP(15, 0, value, 7, 10, 1);
+}
+
+/** \brief Set DCIMVAC
+
+ Data cache invalidate
+ */
+__STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value)
+{
+ __set_CP(15, 0, value, 7, 6, 1);
+}
+
+/** \brief Set DCCIMVAC
+
+ Data cache clean and invalidate
+ */
+__STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value)
+{
+ __set_CP(15, 0, value, 7, 14, 1);
+}
+
+/** \brief Set CSSELR
+ */
+__STATIC_FORCEINLINE void __set_CSSELR(uint32_t value)
+{
+// __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory");
+ __set_CP(15, 2, value, 0, 0, 0);
+}
+
+/** \brief Get CSSELR
+ \return CSSELR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CSSELR(void)
+{
+ uint32_t result;
+// __ASM volatile("MRC p15, 2, %0, c0, c0, 0" : "=r"(result) : : "memory");
+ __get_CP(15, 2, result, 0, 0, 0);
+ return result;
+}
+
+/** \brief Set CCSIDR
+ \deprecated CCSIDR itself is read-only. Use __set_CSSELR to select cache level instead.
+ */
+CMSIS_DEPRECATED
+__STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value)
+{
+ __set_CSSELR(value);
+}
+
+/** \brief Get CCSIDR
+ \return CCSIDR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CCSIDR(void)
+{
+ uint32_t result;
+// __ASM volatile("MRC p15, 1, %0, c0, c0, 0" : "=r"(result) : : "memory");
+ __get_CP(15, 1, result, 0, 0, 0);
+ return result;
+}
+
+/** \brief Get CLIDR
+ \return CLIDR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CLIDR(void)
+{
+ uint32_t result;
+// __ASM volatile("MRC p15, 1, %0, c0, c0, 1" : "=r"(result) : : "memory");
+ __get_CP(15, 1, result, 0, 0, 1);
+ return result;
+}
+
+/** \brief Set DCISW
+ */
+__STATIC_FORCEINLINE void __set_DCISW(uint32_t value)
+{
+// __ASM volatile("MCR p15, 0, %0, c7, c6, 2" : : "r"(value) : "memory")
+ __set_CP(15, 0, value, 7, 6, 2);
+}
+
+/** \brief Set DCCSW
+ */
+__STATIC_FORCEINLINE void __set_DCCSW(uint32_t value)
+{
+// __ASM volatile("MCR p15, 0, %0, c7, c10, 2" : : "r"(value) : "memory")
+ __set_CP(15, 0, value, 7, 10, 2);
+}
+
+/** \brief Set DCCISW
+ */
+__STATIC_FORCEINLINE void __set_DCCISW(uint32_t value)
+{
+// __ASM volatile("MCR p15, 0, %0, c7, c14, 2" : : "r"(value) : "memory")
+ __set_CP(15, 0, value, 7, 14, 2);
+}
+
+#endif
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Include/cmsis_gcc.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Include/cmsis_gcc.h
new file mode 100644
index 0000000..fb1442c
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Include/cmsis_gcc.h
@@ -0,0 +1,679 @@
+/**************************************************************************//**
+ * @file cmsis_gcc.h
+ * @brief CMSIS compiler specific macros, functions, instructions
+ * @version V1.0.2
+ * @date 09. April 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+ #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM asm
+#endif
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+#ifndef __FORCEINLINE
+ #define __FORCEINLINE __attribute__((always_inline))
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef CMSIS_DEPRECATED
+ #define CMSIS_DEPRECATED __attribute__((deprecated))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+
+/* ########################## Core Instruction Access ######################### */
+/**
+ \brief No Operation
+ */
+#define __NOP() __ASM volatile ("nop")
+
+/**
+ \brief Wait For Interrupt
+ */
+#define __WFI() __ASM volatile ("wfi")
+
+/**
+ \brief Wait For Event
+ */
+#define __WFE() __ASM volatile ("wfe")
+
+/**
+ \brief Send Event
+ */
+#define __SEV() __ASM volatile ("sev")
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+}
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF":::"memory");
+}
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+ __ASM volatile("rev16 %0, %1" : "=r" (result) : "r" (value));
+ return result;
+}
+#endif
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (int16_t)__builtin_bswap16(value);
+#else
+ int16_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U) {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ int32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return result;
+}
+
+/**
+ \brief Count leading zeros
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ (uint8_t)__builtin_clz
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+__extension__ \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+/* ########################### Core Function Access ########################### */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+*/
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ #if __has_builtin(__builtin_arm_get_fpscr)
+ // Re-enable using built-in when GCC has been fixed
+ // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ return __builtin_arm_get_fpscr();
+ #else
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+ #endif
+ #else
+ return(0U);
+ #endif
+}
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+*/
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ #if __has_builtin(__builtin_arm_set_fpscr)
+ // Re-enable using built-in when GCC has been fixed
+ // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ __builtin_arm_set_fpscr(fpscr);
+ #else
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+ #endif
+ #else
+ (void)fpscr;
+ #endif
+}
+
+/** \brief Get CPSR Register
+ \return CPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
+{
+ uint32_t result;
+ __ASM volatile("MRS %0, cpsr" : "=r" (result) );
+ return(result);
+}
+
+/** \brief Set CPSR Register
+ \param [in] cpsr CPSR value to set
+ */
+__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
+{
+__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
+}
+
+/** \brief Get Mode
+ \return Processor Mode
+ */
+__STATIC_FORCEINLINE uint32_t __get_mode(void)
+{
+ return (__get_CPSR() & 0x1FU);
+}
+
+/** \brief Set Mode
+ \param [in] mode Mode value to set
+ */
+__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
+{
+ __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
+}
+
+/** \brief Get Stack Pointer
+ \return Stack Pointer value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SP(void)
+{
+ uint32_t result;
+ __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory");
+ return result;
+}
+
+/** \brief Set Stack Pointer
+ \param [in] stack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
+{
+ __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
+}
+
+/** \brief Get USR/SYS Stack Pointer
+ \return USR/SYS Stack Pointer value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
+{
+ uint32_t cpsr = __get_CPSR();
+ uint32_t result;
+ __ASM volatile(
+ "CPS #0x1F \n"
+ "MOV %0, sp " : "=r"(result) : : "memory"
+ );
+ __set_CPSR(cpsr);
+ __ISB();
+ return result;
+}
+
+/** \brief Set USR/SYS Stack Pointer
+ \param [in] topOfProcStack USR/SYS Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
+{
+ uint32_t cpsr = __get_CPSR();
+ __ASM volatile(
+ "CPS #0x1F \n"
+ "MOV sp, %0 " : : "r" (topOfProcStack) : "memory"
+ );
+ __set_CPSR(cpsr);
+ __ISB();
+}
+
+/** \brief Get FPEXC
+ \return Floating Point Exception Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
+{
+#if (__FPU_PRESENT == 1)
+ uint32_t result;
+ __ASM volatile("VMRS %0, fpexc" : "=r" (result) );
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+/** \brief Set FPEXC
+ \param [in] fpexc Floating Point Exception Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
+{
+#if (__FPU_PRESENT == 1)
+ __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
+#endif
+}
+
+/*
+ * Include common core functions to access Coprocessor 15 registers
+ */
+
+#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
+#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
+#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
+#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
+
+#include "cmsis_cp15.h"
+
+/** \brief Enable Floating Point Unit
+
+ Critical section, called from undef handler, so systick is disabled
+ */
+__STATIC_INLINE void __FPU_Enable(void)
+{
+ __ASM volatile(
+ //Permit access to VFP/NEON, registers by modifying CPACR
+ " MRC p15,0,R1,c1,c0,2 \n"
+ " ORR R1,R1,#0x00F00000 \n"
+ " MCR p15,0,R1,c1,c0,2 \n"
+
+ //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+ " ISB \n"
+
+ //Enable VFP/NEON
+ " VMRS R1,FPEXC \n"
+ " ORR R1,R1,#0x40000000 \n"
+ " VMSR FPEXC,R1 \n"
+
+ //Initialise VFP/NEON registers to 0
+ " MOV R2,#0 \n"
+
+ //Initialise D16 registers to 0
+ " VMOV D0, R2,R2 \n"
+ " VMOV D1, R2,R2 \n"
+ " VMOV D2, R2,R2 \n"
+ " VMOV D3, R2,R2 \n"
+ " VMOV D4, R2,R2 \n"
+ " VMOV D5, R2,R2 \n"
+ " VMOV D6, R2,R2 \n"
+ " VMOV D7, R2,R2 \n"
+ " VMOV D8, R2,R2 \n"
+ " VMOV D9, R2,R2 \n"
+ " VMOV D10,R2,R2 \n"
+ " VMOV D11,R2,R2 \n"
+ " VMOV D12,R2,R2 \n"
+ " VMOV D13,R2,R2 \n"
+ " VMOV D14,R2,R2 \n"
+ " VMOV D15,R2,R2 \n"
+
+#if (defined(__ARM_NEON) && (__ARM_NEON == 1))
+ //Initialise D32 registers to 0
+ " VMOV D16,R2,R2 \n"
+ " VMOV D17,R2,R2 \n"
+ " VMOV D18,R2,R2 \n"
+ " VMOV D19,R2,R2 \n"
+ " VMOV D20,R2,R2 \n"
+ " VMOV D21,R2,R2 \n"
+ " VMOV D22,R2,R2 \n"
+ " VMOV D23,R2,R2 \n"
+ " VMOV D24,R2,R2 \n"
+ " VMOV D25,R2,R2 \n"
+ " VMOV D26,R2,R2 \n"
+ " VMOV D27,R2,R2 \n"
+ " VMOV D28,R2,R2 \n"
+ " VMOV D29,R2,R2 \n"
+ " VMOV D30,R2,R2 \n"
+ " VMOV D31,R2,R2 \n"
+#endif
+
+ //Initialise FPSCR to a known state
+ " VMRS R2,FPSCR \n"
+ " LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+ " AND R2,R2,R3 \n"
+ " VMSR FPSCR,R2 "
+ );
+}
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Include/cmsis_iccarm.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Include/cmsis_iccarm.h
new file mode 100644
index 0000000..c46c397
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Include/cmsis_iccarm.h
@@ -0,0 +1,559 @@
+/**************************************************************************//**
+ * @file cmsis_iccarm.h
+ * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version V5.0.6
+ * @date 02. March 2018
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2018 IAR Systems
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+ #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+ #define __ICCARM_V8 1
+#else
+ #define __ICCARM_V8 0
+#endif
+
+#pragma language=extended
+
+#ifndef __ALIGNED
+ #if __ICCARM_V8
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #elif (__VER__ >= 7080000)
+ /* Needs IAR language extensions */
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #else
+ #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_7A__
+/* Macro already defined */
+#else
+ #if defined(__ARM7A__)
+ #define __ARM_ARCH_7A__ 1
+ #endif
+#endif
+
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+
+#ifndef __NO_RETURN
+ #if __ICCARM_V8
+ #define __NO_RETURN __attribute__((__noreturn__))
+ #else
+ #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+ #endif
+#endif
+
+#ifndef __PACKED
+ /* Needs IAR language extensions */
+ #if __ICCARM_V8
+ #define __PACKED __attribute__((packed, aligned(1)))
+ #else
+ #define __PACKED __packed
+ #endif
+#endif
+
+#ifndef __PACKED_STRUCT
+ /* Needs IAR language extensions */
+ #if __ICCARM_V8
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+ #else
+ #define __PACKED_STRUCT __packed struct
+ #endif
+#endif
+
+#ifndef __PACKED_UNION
+ /* Needs IAR language extensions */
+ #if __ICCARM_V8
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+ #else
+ #define __PACKED_UNION __packed union
+ #endif
+#endif
+
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+
+#ifndef __FORCEINLINE
+ #define __FORCEINLINE _Pragma("inline=forced")
+#endif
+
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef CMSIS_DEPRECATED
+ #define CMSIS_DEPRECATED __attribute__((deprecated))
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma language=save
+ #pragma language=extended
+ __IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+ {
+ return *(__packed uint16_t*)(ptr);
+ }
+ #pragma language=restore
+ #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma language=save
+ #pragma language=extended
+ __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+ {
+ *(__packed uint16_t*)(ptr) = val;;
+ }
+ #pragma language=restore
+ #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma language=save
+ #pragma language=extended
+ __IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+ {
+ return *(__packed uint32_t*)(ptr);
+ }
+ #pragma language=restore
+ #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma language=save
+ #pragma language=extended
+ __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+ {
+ *(__packed uint32_t*)(ptr) = val;;
+ }
+ #pragma language=restore
+ #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#if 0
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma language=save
+ #pragma language=extended
+ __packed struct __iar_u32 { uint32_t v; };
+ #pragma language=restore
+ #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+#endif
+
+#ifndef __USED
+ #if __ICCARM_V8
+ #define __USED __attribute__((used))
+ #else
+ #define __USED _Pragma("__root")
+ #endif
+#endif
+
+#ifndef __WEAK
+ #if __ICCARM_V8
+ #define __WEAK __attribute__((weak))
+ #else
+ #define __WEAK _Pragma("__weak")
+ #endif
+#endif
+
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+ #define __ICCARM_INTRINSICS_VERSION__ 0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+ #if defined(__CLZ)
+ #undef __CLZ
+ #endif
+ #if defined(__REVSH)
+ #undef __REVSH
+ #endif
+ #if defined(__RBIT)
+ #undef __RBIT
+ #endif
+ #if defined(__SSAT)
+ #undef __SSAT
+ #endif
+ #if defined(__USAT)
+ #undef __USAT
+ #endif
+
+ #include "iccarm_builtin.h"
+
+ #define __enable_irq __iar_builtin_enable_interrupt
+ #define __disable_irq __iar_builtin_disable_interrupt
+ #define __enable_fault_irq __iar_builtin_enable_fiq
+ #define __disable_fault_irq __iar_builtin_disable_fiq
+ #define __arm_rsr __iar_builtin_rsr
+ #define __arm_wsr __iar_builtin_wsr
+
+ #if __FPU_PRESENT
+ #define __get_FPSCR() (__arm_rsr("FPSCR"))
+ #else
+ #define __get_FPSCR() ( 0 )
+ #endif
+
+ #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", VALUE))
+
+ #define __get_CPSR() (__arm_rsr("CPSR"))
+ #define __get_mode() (__get_CPSR() & 0x1FU)
+
+ #define __set_CPSR(VALUE) (__arm_wsr("CPSR", (VALUE)))
+ #define __set_mode(VALUE) (__arm_wsr("CPSR_c", (VALUE)))
+
+
+ #define __get_FPEXC() (__arm_rsr("FPEXC"))
+ #define __set_FPEXC(VALUE) (__arm_wsr("FPEXC", VALUE))
+
+ #define __get_CP(cp, op1, RT, CRn, CRm, op2) \
+ ((RT) = __arm_rsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2))
+
+ #define __set_CP(cp, op1, RT, CRn, CRm, op2) \
+ (__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, (RT)))
+
+ #define __get_CP64(cp, op1, Rt, CRm) \
+ __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
+
+ #define __set_CP64(cp, op1, Rt, CRm) \
+ __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
+
+ #include "cmsis_cp15.h"
+
+ #define __NOP __iar_builtin_no_operation
+
+ #define __CLZ __iar_builtin_CLZ
+ #define __CLREX __iar_builtin_CLREX
+
+ #define __DMB __iar_builtin_DMB
+ #define __DSB __iar_builtin_DSB
+ #define __ISB __iar_builtin_ISB
+
+ #define __LDREXB __iar_builtin_LDREXB
+ #define __LDREXH __iar_builtin_LDREXH
+ #define __LDREXW __iar_builtin_LDREX
+
+ #define __RBIT __iar_builtin_RBIT
+ #define __REV __iar_builtin_REV
+ #define __REV16 __iar_builtin_REV16
+
+ __IAR_FT int16_t __REVSH(int16_t val)
+ {
+ return (int16_t) __iar_builtin_REVSH(val);
+ }
+
+ #define __ROR __iar_builtin_ROR
+ #define __RRX __iar_builtin_RRX
+
+ #define __SEV __iar_builtin_SEV
+
+ #define __SSAT __iar_builtin_SSAT
+
+ #define __STREXB __iar_builtin_STREXB
+ #define __STREXH __iar_builtin_STREXH
+ #define __STREXW __iar_builtin_STREX
+
+ #define __USAT __iar_builtin_USAT
+
+ #define __WFE __iar_builtin_WFE
+ #define __WFI __iar_builtin_WFI
+
+ #define __SADD8 __iar_builtin_SADD8
+ #define __QADD8 __iar_builtin_QADD8
+ #define __SHADD8 __iar_builtin_SHADD8
+ #define __UADD8 __iar_builtin_UADD8
+ #define __UQADD8 __iar_builtin_UQADD8
+ #define __UHADD8 __iar_builtin_UHADD8
+ #define __SSUB8 __iar_builtin_SSUB8
+ #define __QSUB8 __iar_builtin_QSUB8
+ #define __SHSUB8 __iar_builtin_SHSUB8
+ #define __USUB8 __iar_builtin_USUB8
+ #define __UQSUB8 __iar_builtin_UQSUB8
+ #define __UHSUB8 __iar_builtin_UHSUB8
+ #define __SADD16 __iar_builtin_SADD16
+ #define __QADD16 __iar_builtin_QADD16
+ #define __SHADD16 __iar_builtin_SHADD16
+ #define __UADD16 __iar_builtin_UADD16
+ #define __UQADD16 __iar_builtin_UQADD16
+ #define __UHADD16 __iar_builtin_UHADD16
+ #define __SSUB16 __iar_builtin_SSUB16
+ #define __QSUB16 __iar_builtin_QSUB16
+ #define __SHSUB16 __iar_builtin_SHSUB16
+ #define __USUB16 __iar_builtin_USUB16
+ #define __UQSUB16 __iar_builtin_UQSUB16
+ #define __UHSUB16 __iar_builtin_UHSUB16
+ #define __SASX __iar_builtin_SASX
+ #define __QASX __iar_builtin_QASX
+ #define __SHASX __iar_builtin_SHASX
+ #define __UASX __iar_builtin_UASX
+ #define __UQASX __iar_builtin_UQASX
+ #define __UHASX __iar_builtin_UHASX
+ #define __SSAX __iar_builtin_SSAX
+ #define __QSAX __iar_builtin_QSAX
+ #define __SHSAX __iar_builtin_SHSAX
+ #define __USAX __iar_builtin_USAX
+ #define __UQSAX __iar_builtin_UQSAX
+ #define __UHSAX __iar_builtin_UHSAX
+ #define __USAD8 __iar_builtin_USAD8
+ #define __USADA8 __iar_builtin_USADA8
+ #define __SSAT16 __iar_builtin_SSAT16
+ #define __USAT16 __iar_builtin_USAT16
+ #define __UXTB16 __iar_builtin_UXTB16
+ #define __UXTAB16 __iar_builtin_UXTAB16
+ #define __SXTB16 __iar_builtin_SXTB16
+ #define __SXTAB16 __iar_builtin_SXTAB16
+ #define __SMUAD __iar_builtin_SMUAD
+ #define __SMUADX __iar_builtin_SMUADX
+ #define __SMMLA __iar_builtin_SMMLA
+ #define __SMLAD __iar_builtin_SMLAD
+ #define __SMLADX __iar_builtin_SMLADX
+ #define __SMLALD __iar_builtin_SMLALD
+ #define __SMLALDX __iar_builtin_SMLALDX
+ #define __SMUSD __iar_builtin_SMUSD
+ #define __SMUSDX __iar_builtin_SMUSDX
+ #define __SMLSD __iar_builtin_SMLSD
+ #define __SMLSDX __iar_builtin_SMLSDX
+ #define __SMLSLD __iar_builtin_SMLSLD
+ #define __SMLSLDX __iar_builtin_SMLSLDX
+ #define __SEL __iar_builtin_SEL
+ #define __QADD __iar_builtin_QADD
+ #define __QSUB __iar_builtin_QSUB
+ #define __PKHBT __iar_builtin_PKHBT
+ #define __PKHTB __iar_builtin_PKHTB
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+ #if !__FPU_PRESENT
+ #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+ #endif
+
+ #ifdef __INTRINSICS_INCLUDED
+ #error intrinsics.h is already included previously!
+ #endif
+
+ #include <intrinsics.h>
+
+ #if !__FPU_PRESENT
+ #define __get_FPSCR() (0)
+ #endif
+
+ #pragma diag_suppress=Pe940
+ #pragma diag_suppress=Pe177
+
+ #define __enable_irq __enable_interrupt
+ #define __disable_irq __disable_interrupt
+ #define __enable_fault_irq __enable_fiq
+ #define __disable_fault_irq __disable_fiq
+ #define __NOP __no_operation
+
+ #define __get_xPSR __get_PSR
+
+ __IAR_FT void __set_mode(uint32_t mode)
+ {
+ __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
+ }
+
+ __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+ {
+ return __LDREX((unsigned long *)ptr);
+ }
+
+ __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+ {
+ return __STREX(value, (unsigned long *)ptr);
+ }
+
+
+ __IAR_FT uint32_t __RRX(uint32_t value)
+ {
+ uint32_t result;
+ __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
+ return(result);
+ }
+
+
+ __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+ {
+ return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+ }
+
+ __IAR_FT uint32_t __get_FPEXC(void)
+ {
+ #if (__FPU_PRESENT == 1)
+ uint32_t result;
+ __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
+ return(result);
+ #else
+ return(0);
+ #endif
+ }
+
+ __IAR_FT void __set_FPEXC(uint32_t fpexc)
+ {
+ #if (__FPU_PRESENT == 1)
+ __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
+ #endif
+ }
+
+
+ #define __get_CP(cp, op1, Rt, CRn, CRm, op2) \
+ __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
+ #define __set_CP(cp, op1, Rt, CRn, CRm, op2) \
+ __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
+ #define __get_CP64(cp, op1, Rt, CRm) \
+ __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
+ #define __set_CP64(cp, op1, Rt, CRm) \
+ __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
+
+ #include "cmsis_cp15.h"
+
+#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
+
+
+__IAR_FT uint32_t __get_SP_usr(void)
+{
+ uint32_t cpsr;
+ uint32_t result;
+ __ASM volatile(
+ "MRS %0, cpsr \n"
+ "CPS #0x1F \n" // no effect in USR mode
+ "MOV %1, sp \n"
+ "MSR cpsr_c, %2 \n" // no effect in USR mode
+ "ISB" : "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory"
+ );
+ return result;
+}
+
+__IAR_FT void __set_SP_usr(uint32_t topOfProcStack)
+{
+ uint32_t cpsr;
+ __ASM volatile(
+ "MRS %0, cpsr \n"
+ "CPS #0x1F \n" // no effect in USR mode
+ "MOV sp, %1 \n"
+ "MSR cpsr_c, %2 \n" // no effect in USR mode
+ "ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory"
+ );
+}
+
+#define __get_mode() (__get_CPSR() & 0x1FU)
+
+__STATIC_INLINE
+void __FPU_Enable(void)
+{
+ __ASM volatile(
+ //Permit access to VFP/NEON, registers by modifying CPACR
+ " MRC p15,0,R1,c1,c0,2 \n"
+ " ORR R1,R1,#0x00F00000 \n"
+ " MCR p15,0,R1,c1,c0,2 \n"
+
+ //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+ " ISB \n"
+
+ //Enable VFP/NEON
+ " VMRS R1,FPEXC \n"
+ " ORR R1,R1,#0x40000000 \n"
+ " VMSR FPEXC,R1 \n"
+
+ //Initialise VFP/NEON registers to 0
+ " MOV R2,#0 \n"
+
+ //Initialise D16 registers to 0
+ " VMOV D0, R2,R2 \n"
+ " VMOV D1, R2,R2 \n"
+ " VMOV D2, R2,R2 \n"
+ " VMOV D3, R2,R2 \n"
+ " VMOV D4, R2,R2 \n"
+ " VMOV D5, R2,R2 \n"
+ " VMOV D6, R2,R2 \n"
+ " VMOV D7, R2,R2 \n"
+ " VMOV D8, R2,R2 \n"
+ " VMOV D9, R2,R2 \n"
+ " VMOV D10,R2,R2 \n"
+ " VMOV D11,R2,R2 \n"
+ " VMOV D12,R2,R2 \n"
+ " VMOV D13,R2,R2 \n"
+ " VMOV D14,R2,R2 \n"
+ " VMOV D15,R2,R2 \n"
+
+#ifdef __ARM_ADVANCED_SIMD__
+ //Initialise D32 registers to 0
+ " VMOV D16,R2,R2 \n"
+ " VMOV D17,R2,R2 \n"
+ " VMOV D18,R2,R2 \n"
+ " VMOV D19,R2,R2 \n"
+ " VMOV D20,R2,R2 \n"
+ " VMOV D21,R2,R2 \n"
+ " VMOV D22,R2,R2 \n"
+ " VMOV D23,R2,R2 \n"
+ " VMOV D24,R2,R2 \n"
+ " VMOV D25,R2,R2 \n"
+ " VMOV D26,R2,R2 \n"
+ " VMOV D27,R2,R2 \n"
+ " VMOV D28,R2,R2 \n"
+ " VMOV D29,R2,R2 \n"
+ " VMOV D30,R2,R2 \n"
+ " VMOV D31,R2,R2 \n"
+#endif
+
+ //Initialise FPSCR to a known state
+ " VMRS R2,FPSCR \n"
+ " MOV32 R3,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+ " AND R2,R2,R3 \n"
+ " VMSR FPSCR,R2 \n");
+}
+
+
+
+#undef __IAR_FT
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Include/core_ca.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Include/core_ca.h
new file mode 100644
index 0000000..c7b451f
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Include/core_ca.h
@@ -0,0 +1,2614 @@
+/**************************************************************************//**
+ * @file core_ca.h
+ * @brief CMSIS Cortex-A Core Peripheral Access Layer Header File
+ * @version V1.0.1
+ * @date 07. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CA_H_GENERIC
+#define __CORE_CA_H_GENERIC
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+
+/* CMSIS CA definitions */
+#define __CA_CMSIS_VERSION_MAIN (1U) /*!< \brief [31:16] CMSIS-Core(A) main version */
+#define __CA_CMSIS_VERSION_SUB (1U) /*!< \brief [15:0] CMSIS-Core(A) sub version */
+#define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \
+ __CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(A) version number */
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CA_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CA_H_DEPENDANT
+#define __CORE_CA_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+ /* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CA_REV
+ #define __CA_REV 0x0000U
+ #warning "__CA_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __GIC_PRESENT
+ #define __GIC_PRESENT 1U
+ #warning "__GIC_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __TIM_PRESENT
+ #define __TIM_PRESENT 1U
+ #warning "__TIM_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __L2C_PRESENT
+ #define __L2C_PRESENT 0U
+ #warning "__L2C_PRESENT not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+#ifdef __cplusplus
+ #define __I volatile /*!< \brief Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< \brief Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< \brief Defines 'write only' permissions */
+#define __IO volatile /*!< \brief Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*!< \brief Defines 'read only' structure member permissions */
+#define __OM volatile /*!< \brief Defines 'write only' structure member permissions */
+#define __IOM volatile /*!< \brief Defines 'read / write' structure member permissions */
+#define RESERVED(N, T) T RESERVED##N; // placeholder struct members used for "reserved" areas
+
+ /*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - CPSR
+ - CP15 Registers
+ - L2C-310 Cache Controller
+ - Generic Interrupt Controller Distributor
+ - Generic Interrupt Controller Interface
+ ******************************************************************************/
+
+/* Core Register CPSR */
+typedef union
+{
+ struct
+ {
+ uint32_t M:5; /*!< \brief bit: 0.. 4 Mode field */
+ uint32_t T:1; /*!< \brief bit: 5 Thumb execution state bit */
+ uint32_t F:1; /*!< \brief bit: 6 FIQ mask bit */
+ uint32_t I:1; /*!< \brief bit: 7 IRQ mask bit */
+ uint32_t A:1; /*!< \brief bit: 8 Asynchronous abort mask bit */
+ uint32_t E:1; /*!< \brief bit: 9 Endianness execution state bit */
+ uint32_t IT1:6; /*!< \brief bit: 10..15 If-Then execution state bits 2-7 */
+ uint32_t GE:4; /*!< \brief bit: 16..19 Greater than or Equal flags */
+ RESERVED(0:4, uint32_t)
+ uint32_t J:1; /*!< \brief bit: 24 Jazelle bit */
+ uint32_t IT0:2; /*!< \brief bit: 25..26 If-Then execution state bits 0-1 */
+ uint32_t Q:1; /*!< \brief bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< \brief bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< \brief bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< \brief bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< \brief bit: 31 Negative condition code flag */
+ } b; /*!< \brief Structure used for bit access */
+ uint32_t w; /*!< \brief Type used for word access */
+} CPSR_Type;
+
+
+
+/* CPSR Register Definitions */
+#define CPSR_N_Pos 31U /*!< \brief CPSR: N Position */
+#define CPSR_N_Msk (1UL << CPSR_N_Pos) /*!< \brief CPSR: N Mask */
+
+#define CPSR_Z_Pos 30U /*!< \brief CPSR: Z Position */
+#define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /*!< \brief CPSR: Z Mask */
+
+#define CPSR_C_Pos 29U /*!< \brief CPSR: C Position */
+#define CPSR_C_Msk (1UL << CPSR_C_Pos) /*!< \brief CPSR: C Mask */
+
+#define CPSR_V_Pos 28U /*!< \brief CPSR: V Position */
+#define CPSR_V_Msk (1UL << CPSR_V_Pos) /*!< \brief CPSR: V Mask */
+
+#define CPSR_Q_Pos 27U /*!< \brief CPSR: Q Position */
+#define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /*!< \brief CPSR: Q Mask */
+
+#define CPSR_IT0_Pos 25U /*!< \brief CPSR: IT0 Position */
+#define CPSR_IT0_Msk (3UL << CPSR_IT0_Pos) /*!< \brief CPSR: IT0 Mask */
+
+#define CPSR_J_Pos 24U /*!< \brief CPSR: J Position */
+#define CPSR_J_Msk (1UL << CPSR_J_Pos) /*!< \brief CPSR: J Mask */
+
+#define CPSR_GE_Pos 16U /*!< \brief CPSR: GE Position */
+#define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /*!< \brief CPSR: GE Mask */
+
+#define CPSR_IT1_Pos 10U /*!< \brief CPSR: IT1 Position */
+#define CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos) /*!< \brief CPSR: IT1 Mask */
+
+#define CPSR_E_Pos 9U /*!< \brief CPSR: E Position */
+#define CPSR_E_Msk (1UL << CPSR_E_Pos) /*!< \brief CPSR: E Mask */
+
+#define CPSR_A_Pos 8U /*!< \brief CPSR: A Position */
+#define CPSR_A_Msk (1UL << CPSR_A_Pos) /*!< \brief CPSR: A Mask */
+
+#define CPSR_I_Pos 7U /*!< \brief CPSR: I Position */
+#define CPSR_I_Msk (1UL << CPSR_I_Pos) /*!< \brief CPSR: I Mask */
+
+#define CPSR_F_Pos 6U /*!< \brief CPSR: F Position */
+#define CPSR_F_Msk (1UL << CPSR_F_Pos) /*!< \brief CPSR: F Mask */
+
+#define CPSR_T_Pos 5U /*!< \brief CPSR: T Position */
+#define CPSR_T_Msk (1UL << CPSR_T_Pos) /*!< \brief CPSR: T Mask */
+
+#define CPSR_M_Pos 0U /*!< \brief CPSR: M Position */
+#define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /*!< \brief CPSR: M Mask */
+
+#define CPSR_M_USR 0x10U /*!< \brief CPSR: M User mode (PL0) */
+#define CPSR_M_FIQ 0x11U /*!< \brief CPSR: M Fast Interrupt mode (PL1) */
+#define CPSR_M_IRQ 0x12U /*!< \brief CPSR: M Interrupt mode (PL1) */
+#define CPSR_M_SVC 0x13U /*!< \brief CPSR: M Supervisor mode (PL1) */
+#define CPSR_M_MON 0x16U /*!< \brief CPSR: M Monitor mode (PL1) */
+#define CPSR_M_ABT 0x17U /*!< \brief CPSR: M Abort mode (PL1) */
+#define CPSR_M_HYP 0x1AU /*!< \brief CPSR: M Hypervisor mode (PL2) */
+#define CPSR_M_UND 0x1BU /*!< \brief CPSR: M Undefined mode (PL1) */
+#define CPSR_M_SYS 0x1FU /*!< \brief CPSR: M System mode (PL1) */
+
+/* CP15 Register SCTLR */
+typedef union
+{
+ struct
+ {
+ uint32_t M:1; /*!< \brief bit: 0 MMU enable */
+ uint32_t A:1; /*!< \brief bit: 1 Alignment check enable */
+ uint32_t C:1; /*!< \brief bit: 2 Cache enable */
+ RESERVED(0:2, uint32_t)
+ uint32_t CP15BEN:1; /*!< \brief bit: 5 CP15 barrier enable */
+ RESERVED(1:1, uint32_t)
+ uint32_t B:1; /*!< \brief bit: 7 Endianness model */
+ RESERVED(2:2, uint32_t)
+ uint32_t SW:1; /*!< \brief bit: 10 SWP and SWPB enable */
+ uint32_t Z:1; /*!< \brief bit: 11 Branch prediction enable */
+ uint32_t I:1; /*!< \brief bit: 12 Instruction cache enable */
+ uint32_t V:1; /*!< \brief bit: 13 Vectors bit */
+ uint32_t RR:1; /*!< \brief bit: 14 Round Robin select */
+ RESERVED(3:2, uint32_t)
+ uint32_t HA:1; /*!< \brief bit: 17 Hardware Access flag enable */
+ RESERVED(4:1, uint32_t)
+ uint32_t WXN:1; /*!< \brief bit: 19 Write permission implies XN */
+ uint32_t UWXN:1; /*!< \brief bit: 20 Unprivileged write permission implies PL1 XN */
+ uint32_t FI:1; /*!< \brief bit: 21 Fast interrupts configuration enable */
+ uint32_t U:1; /*!< \brief bit: 22 Alignment model */
+ RESERVED(5:1, uint32_t)
+ uint32_t VE:1; /*!< \brief bit: 24 Interrupt Vectors Enable */
+ uint32_t EE:1; /*!< \brief bit: 25 Exception Endianness */
+ RESERVED(6:1, uint32_t)
+ uint32_t NMFI:1; /*!< \brief bit: 27 Non-maskable FIQ (NMFI) support */
+ uint32_t TRE:1; /*!< \brief bit: 28 TEX remap enable. */
+ uint32_t AFE:1; /*!< \brief bit: 29 Access flag enable */
+ uint32_t TE:1; /*!< \brief bit: 30 Thumb Exception enable */
+ RESERVED(7:1, uint32_t)
+ } b; /*!< \brief Structure used for bit access */
+ uint32_t w; /*!< \brief Type used for word access */
+} SCTLR_Type;
+
+#define SCTLR_TE_Pos 30U /*!< \brief SCTLR: TE Position */
+#define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /*!< \brief SCTLR: TE Mask */
+
+#define SCTLR_AFE_Pos 29U /*!< \brief SCTLR: AFE Position */
+#define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /*!< \brief SCTLR: AFE Mask */
+
+#define SCTLR_TRE_Pos 28U /*!< \brief SCTLR: TRE Position */
+#define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /*!< \brief SCTLR: TRE Mask */
+
+#define SCTLR_NMFI_Pos 27U /*!< \brief SCTLR: NMFI Position */
+#define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /*!< \brief SCTLR: NMFI Mask */
+
+#define SCTLR_EE_Pos 25U /*!< \brief SCTLR: EE Position */
+#define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /*!< \brief SCTLR: EE Mask */
+
+#define SCTLR_VE_Pos 24U /*!< \brief SCTLR: VE Position */
+#define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /*!< \brief SCTLR: VE Mask */
+
+#define SCTLR_U_Pos 22U /*!< \brief SCTLR: U Position */
+#define SCTLR_U_Msk (1UL << SCTLR_U_Pos) /*!< \brief SCTLR: U Mask */
+
+#define SCTLR_FI_Pos 21U /*!< \brief SCTLR: FI Position */
+#define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /*!< \brief SCTLR: FI Mask */
+
+#define SCTLR_UWXN_Pos 20U /*!< \brief SCTLR: UWXN Position */
+#define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /*!< \brief SCTLR: UWXN Mask */
+
+#define SCTLR_WXN_Pos 19U /*!< \brief SCTLR: WXN Position */
+#define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /*!< \brief SCTLR: WXN Mask */
+
+#define SCTLR_HA_Pos 17U /*!< \brief SCTLR: HA Position */
+#define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) /*!< \brief SCTLR: HA Mask */
+
+#define SCTLR_RR_Pos 14U /*!< \brief SCTLR: RR Position */
+#define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /*!< \brief SCTLR: RR Mask */
+
+#define SCTLR_V_Pos 13U /*!< \brief SCTLR: V Position */
+#define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /*!< \brief SCTLR: V Mask */
+
+#define SCTLR_I_Pos 12U /*!< \brief SCTLR: I Position */
+#define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /*!< \brief SCTLR: I Mask */
+
+#define SCTLR_Z_Pos 11U /*!< \brief SCTLR: Z Position */
+#define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /*!< \brief SCTLR: Z Mask */
+
+#define SCTLR_SW_Pos 10U /*!< \brief SCTLR: SW Position */
+#define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /*!< \brief SCTLR: SW Mask */
+
+#define SCTLR_B_Pos 7U /*!< \brief SCTLR: B Position */
+#define SCTLR_B_Msk (1UL << SCTLR_B_Pos) /*!< \brief SCTLR: B Mask */
+
+#define SCTLR_CP15BEN_Pos 5U /*!< \brief SCTLR: CP15BEN Position */
+#define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /*!< \brief SCTLR: CP15BEN Mask */
+
+#define SCTLR_C_Pos 2U /*!< \brief SCTLR: C Position */
+#define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /*!< \brief SCTLR: C Mask */
+
+#define SCTLR_A_Pos 1U /*!< \brief SCTLR: A Position */
+#define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /*!< \brief SCTLR: A Mask */
+
+#define SCTLR_M_Pos 0U /*!< \brief SCTLR: M Position */
+#define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /*!< \brief SCTLR: M Mask */
+
+/* CP15 Register ACTLR */
+typedef union
+{
+#if __CORTEX_A == 5 || defined(DOXYGEN)
+ /** \brief Structure used for bit access on Cortex-A5 */
+ struct
+ {
+ uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */
+ RESERVED(0:5, uint32_t)
+ uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */
+ uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */
+ RESERVED(1:2, uint32_t)
+ uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */
+ uint32_t DWBST:1; /*!< \brief bit: 11 AXI data write bursts to Normal memory */
+ uint32_t RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */
+ uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */
+ uint32_t BP:2; /*!< \brief bit:16..15 Branch prediction policy */
+ uint32_t RSDIS:1; /*!< \brief bit: 17 Disable return stack operation */
+ uint32_t BTDIS:1; /*!< \brief bit: 18 Disable indirect Branch Target Address Cache (BTAC) */
+ RESERVED(3:9, uint32_t)
+ uint32_t DBDI:1; /*!< \brief bit: 28 Disable branch dual issue */
+ RESERVED(7:3, uint32_t)
+ } b;
+#endif
+#if __CORTEX_A == 7 || defined(DOXYGEN)
+ /** \brief Structure used for bit access on Cortex-A7 */
+ struct
+ {
+ RESERVED(0:6, uint32_t)
+ uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */
+ RESERVED(1:3, uint32_t)
+ uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */
+ uint32_t L2RADIS:1; /*!< \brief bit: 11 L2 Data Cache read-allocate mode disable */
+ uint32_t L1RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */
+ uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */
+ uint32_t DDVM:1; /*!< \brief bit: 15 Disable Distributed Virtual Memory (DVM) transactions */
+ RESERVED(3:12, uint32_t)
+ uint32_t DDI:1; /*!< \brief bit: 28 Disable dual issue */
+ RESERVED(7:3, uint32_t)
+ } b;
+#endif
+#if __CORTEX_A == 9 || defined(DOXYGEN)
+ /** \brief Structure used for bit access on Cortex-A9 */
+ struct
+ {
+ uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */
+ RESERVED(0:1, uint32_t)
+ uint32_t L1PE:1; /*!< \brief bit: 2 Dside prefetch */
+ uint32_t WFLZM:1; /*!< \brief bit: 3 Cache and TLB maintenance broadcast */
+ RESERVED(1:2, uint32_t)
+ uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */
+ uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */
+ uint32_t AOW:1; /*!< \brief bit: 8 Enable allocation in one cache way only */
+ uint32_t PARITY:1; /*!< \brief bit: 9 Support for parity checking, if implemented */
+ RESERVED(7:22, uint32_t)
+ } b;
+#endif
+ uint32_t w; /*!< \brief Type used for word access */
+} ACTLR_Type;
+
+#define ACTLR_DDI_Pos 28U /*!< \brief ACTLR: DDI Position */
+#define ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos) /*!< \brief ACTLR: DDI Mask */
+
+#define ACTLR_DBDI_Pos 28U /*!< \brief ACTLR: DBDI Position */
+#define ACTLR_DBDI_Msk (1UL << ACTLR_DBDI_Pos) /*!< \brief ACTLR: DBDI Mask */
+
+#define ACTLR_BTDIS_Pos 18U /*!< \brief ACTLR: BTDIS Position */
+#define ACTLR_BTDIS_Msk (1UL << ACTLR_BTDIS_Pos) /*!< \brief ACTLR: BTDIS Mask */
+
+#define ACTLR_RSDIS_Pos 17U /*!< \brief ACTLR: RSDIS Position */
+#define ACTLR_RSDIS_Msk (1UL << ACTLR_RSDIS_Pos) /*!< \brief ACTLR: RSDIS Mask */
+
+#define ACTLR_BP_Pos 15U /*!< \brief ACTLR: BP Position */
+#define ACTLR_BP_Msk (3UL << ACTLR_BP_Pos) /*!< \brief ACTLR: BP Mask */
+
+#define ACTLR_DDVM_Pos 15U /*!< \brief ACTLR: DDVM Position */
+#define ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos) /*!< \brief ACTLR: DDVM Mask */
+
+#define ACTLR_L1PCTL_Pos 13U /*!< \brief ACTLR: L1PCTL Position */
+#define ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos) /*!< \brief ACTLR: L1PCTL Mask */
+
+#define ACTLR_RADIS_Pos 12U /*!< \brief ACTLR: RADIS Position */
+#define ACTLR_RADIS_Msk (1UL << ACTLR_RADIS_Pos) /*!< \brief ACTLR: RADIS Mask */
+
+#define ACTLR_L1RADIS_Pos 12U /*!< \brief ACTLR: L1RADIS Position */
+#define ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos) /*!< \brief ACTLR: L1RADIS Mask */
+
+#define ACTLR_DWBST_Pos 11U /*!< \brief ACTLR: DWBST Position */
+#define ACTLR_DWBST_Msk (1UL << ACTLR_DWBST_Pos) /*!< \brief ACTLR: DWBST Mask */
+
+#define ACTLR_L2RADIS_Pos 11U /*!< \brief ACTLR: L2RADIS Position */
+#define ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos) /*!< \brief ACTLR: L2RADIS Mask */
+
+#define ACTLR_DODMBS_Pos 10U /*!< \brief ACTLR: DODMBS Position */
+#define ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos) /*!< \brief ACTLR: DODMBS Mask */
+
+#define ACTLR_PARITY_Pos 9U /*!< \brief ACTLR: PARITY Position */
+#define ACTLR_PARITY_Msk (1UL << ACTLR_PARITY_Pos) /*!< \brief ACTLR: PARITY Mask */
+
+#define ACTLR_AOW_Pos 8U /*!< \brief ACTLR: AOW Position */
+#define ACTLR_AOW_Msk (1UL << ACTLR_AOW_Pos) /*!< \brief ACTLR: AOW Mask */
+
+#define ACTLR_EXCL_Pos 7U /*!< \brief ACTLR: EXCL Position */
+#define ACTLR_EXCL_Msk (1UL << ACTLR_EXCL_Pos) /*!< \brief ACTLR: EXCL Mask */
+
+#define ACTLR_SMP_Pos 6U /*!< \brief ACTLR: SMP Position */
+#define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos) /*!< \brief ACTLR: SMP Mask */
+
+#define ACTLR_WFLZM_Pos 3U /*!< \brief ACTLR: WFLZM Position */
+#define ACTLR_WFLZM_Msk (1UL << ACTLR_WFLZM_Pos) /*!< \brief ACTLR: WFLZM Mask */
+
+#define ACTLR_L1PE_Pos 2U /*!< \brief ACTLR: L1PE Position */
+#define ACTLR_L1PE_Msk (1UL << ACTLR_L1PE_Pos) /*!< \brief ACTLR: L1PE Mask */
+
+#define ACTLR_FW_Pos 0U /*!< \brief ACTLR: FW Position */
+#define ACTLR_FW_Msk (1UL << ACTLR_FW_Pos) /*!< \brief ACTLR: FW Mask */
+
+/* CP15 Register CPACR */
+typedef union
+{
+ struct
+ {
+ uint32_t CP0:2; /*!< \brief bit: 0..1 Access rights for coprocessor 0 */
+ uint32_t CP1:2; /*!< \brief bit: 2..3 Access rights for coprocessor 1 */
+ uint32_t CP2:2; /*!< \brief bit: 4..5 Access rights for coprocessor 2 */
+ uint32_t CP3:2; /*!< \brief bit: 6..7 Access rights for coprocessor 3 */
+ uint32_t CP4:2; /*!< \brief bit: 8..9 Access rights for coprocessor 4 */
+ uint32_t CP5:2; /*!< \brief bit:10..11 Access rights for coprocessor 5 */
+ uint32_t CP6:2; /*!< \brief bit:12..13 Access rights for coprocessor 6 */
+ uint32_t CP7:2; /*!< \brief bit:14..15 Access rights for coprocessor 7 */
+ uint32_t CP8:2; /*!< \brief bit:16..17 Access rights for coprocessor 8 */
+ uint32_t CP9:2; /*!< \brief bit:18..19 Access rights for coprocessor 9 */
+ uint32_t CP10:2; /*!< \brief bit:20..21 Access rights for coprocessor 10 */
+ uint32_t CP11:2; /*!< \brief bit:22..23 Access rights for coprocessor 11 */
+ uint32_t CP12:2; /*!< \brief bit:24..25 Access rights for coprocessor 11 */
+ uint32_t CP13:2; /*!< \brief bit:26..27 Access rights for coprocessor 11 */
+ uint32_t TRCDIS:1; /*!< \brief bit: 28 Disable CP14 access to trace registers */
+ RESERVED(0:1, uint32_t)
+ uint32_t D32DIS:1; /*!< \brief bit: 30 Disable use of registers D16-D31 of the VFP register file */
+ uint32_t ASEDIS:1; /*!< \brief bit: 31 Disable Advanced SIMD Functionality */
+ } b; /*!< \brief Structure used for bit access */
+ uint32_t w; /*!< \brief Type used for word access */
+} CPACR_Type;
+
+#define CPACR_ASEDIS_Pos 31U /*!< \brief CPACR: ASEDIS Position */
+#define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /*!< \brief CPACR: ASEDIS Mask */
+
+#define CPACR_D32DIS_Pos 30U /*!< \brief CPACR: D32DIS Position */
+#define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */
+
+#define CPACR_TRCDIS_Pos 28U /*!< \brief CPACR: D32DIS Position */
+#define CPACR_TRCDIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */
+
+#define CPACR_CP_Pos_(n) (n*2U) /*!< \brief CPACR: CPn Position */
+#define CPACR_CP_Msk_(n) (3UL << CPACR_CP_Pos_(n)) /*!< \brief CPACR: CPn Mask */
+
+#define CPACR_CP_NA 0U /*!< \brief CPACR CPn field: Access denied. */
+#define CPACR_CP_PL1 1U /*!< \brief CPACR CPn field: Accessible from PL1 only. */
+#define CPACR_CP_FA 3U /*!< \brief CPACR CPn field: Full access. */
+
+/* CP15 Register DFSR */
+typedef union
+{
+ struct
+ {
+ uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */
+ uint32_t Domain:4; /*!< \brief bit: 4.. 7 Fault on which domain */
+ RESERVED(0:1, uint32_t)
+ uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */
+ uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */
+ uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */
+ uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
+ uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */
+ RESERVED(1:18, uint32_t)
+ } s; /*!< \brief Structure used for bit access in short format */
+ struct
+ {
+ uint32_t STATUS:5; /*!< \brief bit: 0.. 5 Fault Status bits */
+ RESERVED(0:3, uint32_t)
+ uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */
+ RESERVED(1:1, uint32_t)
+ uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */
+ uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
+ uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */
+ RESERVED(2:18, uint32_t)
+ } l; /*!< \brief Structure used for bit access in long format */
+ uint32_t w; /*!< \brief Type used for word access */
+} DFSR_Type;
+
+#define DFSR_CM_Pos 13U /*!< \brief DFSR: CM Position */
+#define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /*!< \brief DFSR: CM Mask */
+
+#define DFSR_Ext_Pos 12U /*!< \brief DFSR: Ext Position */
+#define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /*!< \brief DFSR: Ext Mask */
+
+#define DFSR_WnR_Pos 11U /*!< \brief DFSR: WnR Position */
+#define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /*!< \brief DFSR: WnR Mask */
+
+#define DFSR_FS1_Pos 10U /*!< \brief DFSR: FS1 Position */
+#define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /*!< \brief DFSR: FS1 Mask */
+
+#define DFSR_LPAE_Pos 9U /*!< \brief DFSR: LPAE Position */
+#define DFSR_LPAE_Msk (1UL << DFSR_LPAE_Pos) /*!< \brief DFSR: LPAE Mask */
+
+#define DFSR_Domain_Pos 4U /*!< \brief DFSR: Domain Position */
+#define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /*!< \brief DFSR: Domain Mask */
+
+#define DFSR_FS0_Pos 0U /*!< \brief DFSR: FS0 Position */
+#define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /*!< \brief DFSR: FS0 Mask */
+
+#define DFSR_STATUS_Pos 0U /*!< \brief DFSR: STATUS Position */
+#define DFSR_STATUS_Msk (0x3FUL << DFSR_STATUS_Pos) /*!< \brief DFSR: STATUS Mask */
+
+/* CP15 Register IFSR */
+typedef union
+{
+ struct
+ {
+ uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */
+ RESERVED(0:5, uint32_t)
+ uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */
+ uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */
+ RESERVED(1:1, uint32_t)
+ uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
+ RESERVED(2:19, uint32_t)
+ } s; /*!< \brief Structure used for bit access in short format */
+ struct
+ {
+ uint32_t STATUS:6; /*!< \brief bit: 0.. 5 Fault Status bits */
+ RESERVED(0:3, uint32_t)
+ uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */
+ RESERVED(1:2, uint32_t)
+ uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
+ RESERVED(2:19, uint32_t)
+ } l; /*!< \brief Structure used for bit access in long format */
+ uint32_t w; /*!< \brief Type used for word access */
+} IFSR_Type;
+
+#define IFSR_ExT_Pos 12U /*!< \brief IFSR: ExT Position */
+#define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /*!< \brief IFSR: ExT Mask */
+
+#define IFSR_FS1_Pos 10U /*!< \brief IFSR: FS1 Position */
+#define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /*!< \brief IFSR: FS1 Mask */
+
+#define IFSR_LPAE_Pos 9U /*!< \brief IFSR: LPAE Position */
+#define IFSR_LPAE_Msk (0x1UL << IFSR_LPAE_Pos) /*!< \brief IFSR: LPAE Mask */
+
+#define IFSR_FS0_Pos 0U /*!< \brief IFSR: FS0 Position */
+#define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /*!< \brief IFSR: FS0 Mask */
+
+#define IFSR_STATUS_Pos 0U /*!< \brief IFSR: STATUS Position */
+#define IFSR_STATUS_Msk (0x3FUL << IFSR_STATUS_Pos) /*!< \brief IFSR: STATUS Mask */
+
+/* CP15 Register ISR */
+typedef union
+{
+ struct
+ {
+ RESERVED(0:6, uint32_t)
+ uint32_t F:1; /*!< \brief bit: 6 FIQ pending bit */
+ uint32_t I:1; /*!< \brief bit: 7 IRQ pending bit */
+ uint32_t A:1; /*!< \brief bit: 8 External abort pending bit */
+ RESERVED(1:23, uint32_t)
+ } b; /*!< \brief Structure used for bit access */
+ uint32_t w; /*!< \brief Type used for word access */
+} ISR_Type;
+
+#define ISR_A_Pos 13U /*!< \brief ISR: A Position */
+#define ISR_A_Msk (1UL << ISR_A_Pos) /*!< \brief ISR: A Mask */
+
+#define ISR_I_Pos 12U /*!< \brief ISR: I Position */
+#define ISR_I_Msk (1UL << ISR_I_Pos) /*!< \brief ISR: I Mask */
+
+#define ISR_F_Pos 11U /*!< \brief ISR: F Position */
+#define ISR_F_Msk (1UL << ISR_F_Pos) /*!< \brief ISR: F Mask */
+
+/* DACR Register */
+#define DACR_D_Pos_(n) (2U*n) /*!< \brief DACR: Dn Position */
+#define DACR_D_Msk_(n) (3UL << DACR_D_Pos_(n)) /*!< \brief DACR: Dn Mask */
+#define DACR_Dn_NOACCESS 0U /*!< \brief DACR Dn field: No access */
+#define DACR_Dn_CLIENT 1U /*!< \brief DACR Dn field: Client */
+#define DACR_Dn_MANAGER 3U /*!< \brief DACR Dn field: Manager */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param [in] field Name of the register bit field.
+ \param [in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param [in] field Name of the register bit field.
+ \param [in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+
+/**
+ \brief Union type to access the L2C_310 Cache Controller.
+*/
+#if (__L2C_PRESENT == 1U) || defined(DOXYGEN)
+typedef struct
+{
+ __IM uint32_t CACHE_ID; /*!< \brief Offset: 0x0000 (R/ ) Cache ID Register */
+ __IM uint32_t CACHE_TYPE; /*!< \brief Offset: 0x0004 (R/ ) Cache Type Register */
+ RESERVED(0[0x3e], uint32_t)
+ __IOM uint32_t CONTROL; /*!< \brief Offset: 0x0100 (R/W) Control Register */
+ __IOM uint32_t AUX_CNT; /*!< \brief Offset: 0x0104 (R/W) Auxiliary Control */
+ RESERVED(1[0x3e], uint32_t)
+ __IOM uint32_t EVENT_CONTROL; /*!< \brief Offset: 0x0200 (R/W) Event Counter Control */
+ __IOM uint32_t EVENT_COUNTER1_CONF; /*!< \brief Offset: 0x0204 (R/W) Event Counter 1 Configuration */
+ __IOM uint32_t EVENT_COUNTER0_CONF; /*!< \brief Offset: 0x0208 (R/W) Event Counter 1 Configuration */
+ RESERVED(2[0x2], uint32_t)
+ __IOM uint32_t INTERRUPT_MASK; /*!< \brief Offset: 0x0214 (R/W) Interrupt Mask */
+ __IM uint32_t MASKED_INT_STATUS; /*!< \brief Offset: 0x0218 (R/ ) Masked Interrupt Status */
+ __IM uint32_t RAW_INT_STATUS; /*!< \brief Offset: 0x021c (R/ ) Raw Interrupt Status */
+ __OM uint32_t INTERRUPT_CLEAR; /*!< \brief Offset: 0x0220 ( /W) Interrupt Clear */
+ RESERVED(3[0x143], uint32_t)
+ __IOM uint32_t CACHE_SYNC; /*!< \brief Offset: 0x0730 (R/W) Cache Sync */
+ RESERVED(4[0xf], uint32_t)
+ __IOM uint32_t INV_LINE_PA; /*!< \brief Offset: 0x0770 (R/W) Invalidate Line By PA */
+ RESERVED(6[2], uint32_t)
+ __IOM uint32_t INV_WAY; /*!< \brief Offset: 0x077c (R/W) Invalidate by Way */
+ RESERVED(5[0xc], uint32_t)
+ __IOM uint32_t CLEAN_LINE_PA; /*!< \brief Offset: 0x07b0 (R/W) Clean Line by PA */
+ RESERVED(7[1], uint32_t)
+ __IOM uint32_t CLEAN_LINE_INDEX_WAY; /*!< \brief Offset: 0x07b8 (R/W) Clean Line by Index/Way */
+ __IOM uint32_t CLEAN_WAY; /*!< \brief Offset: 0x07bc (R/W) Clean by Way */
+ RESERVED(8[0xc], uint32_t)
+ __IOM uint32_t CLEAN_INV_LINE_PA; /*!< \brief Offset: 0x07f0 (R/W) Clean and Invalidate Line by PA */
+ RESERVED(9[1], uint32_t)
+ __IOM uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< \brief Offset: 0x07f8 (R/W) Clean and Invalidate Line by Index/Way */
+ __IOM uint32_t CLEAN_INV_WAY; /*!< \brief Offset: 0x07fc (R/W) Clean and Invalidate by Way */
+ RESERVED(10[0x40], uint32_t)
+ __IOM uint32_t DATA_LOCK_0_WAY; /*!< \brief Offset: 0x0900 (R/W) Data Lockdown 0 by Way */
+ __IOM uint32_t INST_LOCK_0_WAY; /*!< \brief Offset: 0x0904 (R/W) Instruction Lockdown 0 by Way */
+ __IOM uint32_t DATA_LOCK_1_WAY; /*!< \brief Offset: 0x0908 (R/W) Data Lockdown 1 by Way */
+ __IOM uint32_t INST_LOCK_1_WAY; /*!< \brief Offset: 0x090c (R/W) Instruction Lockdown 1 by Way */
+ __IOM uint32_t DATA_LOCK_2_WAY; /*!< \brief Offset: 0x0910 (R/W) Data Lockdown 2 by Way */
+ __IOM uint32_t INST_LOCK_2_WAY; /*!< \brief Offset: 0x0914 (R/W) Instruction Lockdown 2 by Way */
+ __IOM uint32_t DATA_LOCK_3_WAY; /*!< \brief Offset: 0x0918 (R/W) Data Lockdown 3 by Way */
+ __IOM uint32_t INST_LOCK_3_WAY; /*!< \brief Offset: 0x091c (R/W) Instruction Lockdown 3 by Way */
+ __IOM uint32_t DATA_LOCK_4_WAY; /*!< \brief Offset: 0x0920 (R/W) Data Lockdown 4 by Way */
+ __IOM uint32_t INST_LOCK_4_WAY; /*!< \brief Offset: 0x0924 (R/W) Instruction Lockdown 4 by Way */
+ __IOM uint32_t DATA_LOCK_5_WAY; /*!< \brief Offset: 0x0928 (R/W) Data Lockdown 5 by Way */
+ __IOM uint32_t INST_LOCK_5_WAY; /*!< \brief Offset: 0x092c (R/W) Instruction Lockdown 5 by Way */
+ __IOM uint32_t DATA_LOCK_6_WAY; /*!< \brief Offset: 0x0930 (R/W) Data Lockdown 5 by Way */
+ __IOM uint32_t INST_LOCK_6_WAY; /*!< \brief Offset: 0x0934 (R/W) Instruction Lockdown 5 by Way */
+ __IOM uint32_t DATA_LOCK_7_WAY; /*!< \brief Offset: 0x0938 (R/W) Data Lockdown 6 by Way */
+ __IOM uint32_t INST_LOCK_7_WAY; /*!< \brief Offset: 0x093c (R/W) Instruction Lockdown 6 by Way */
+ RESERVED(11[0x4], uint32_t)
+ __IOM uint32_t LOCK_LINE_EN; /*!< \brief Offset: 0x0950 (R/W) Lockdown by Line Enable */
+ __IOM uint32_t UNLOCK_ALL_BY_WAY; /*!< \brief Offset: 0x0954 (R/W) Unlock All Lines by Way */
+ RESERVED(12[0xaa], uint32_t)
+ __IOM uint32_t ADDRESS_FILTER_START; /*!< \brief Offset: 0x0c00 (R/W) Address Filtering Start */
+ __IOM uint32_t ADDRESS_FILTER_END; /*!< \brief Offset: 0x0c04 (R/W) Address Filtering End */
+ RESERVED(13[0xce], uint32_t)
+ __IOM uint32_t DEBUG_CONTROL; /*!< \brief Offset: 0x0f40 (R/W) Debug Control Register */
+} L2C_310_TypeDef;
+
+#define L2C_310 ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \brief L2C_310 register set access pointer */
+#endif
+
+#if (__GIC_PRESENT == 1U) || defined(DOXYGEN)
+
+/** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD)
+*/
+typedef struct
+{
+ __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) Distributor Control Register */
+ __IM uint32_t TYPER; /*!< \brief Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IM uint32_t IIDR; /*!< \brief Offset: 0x008 (R/ ) Distributor Implementer Identification Register */
+ RESERVED(0, uint32_t)
+ __IOM uint32_t STATUSR; /*!< \brief Offset: 0x010 (R/W) Error Reporting Status Register, optional */
+ RESERVED(1[11], uint32_t)
+ __OM uint32_t SETSPI_NSR; /*!< \brief Offset: 0x040 ( /W) Set SPI Register */
+ RESERVED(2, uint32_t)
+ __OM uint32_t CLRSPI_NSR; /*!< \brief Offset: 0x048 ( /W) Clear SPI Register */
+ RESERVED(3, uint32_t)
+ __OM uint32_t SETSPI_SR; /*!< \brief Offset: 0x050 ( /W) Set SPI, Secure Register */
+ RESERVED(4, uint32_t)
+ __OM uint32_t CLRSPI_SR; /*!< \brief Offset: 0x058 ( /W) Clear SPI, Secure Register */
+ RESERVED(5[9], uint32_t)
+ __IOM uint32_t IGROUPR[32]; /*!< \brief Offset: 0x080 (R/W) Interrupt Group Registers */
+ __IOM uint32_t ISENABLER[32]; /*!< \brief Offset: 0x100 (R/W) Interrupt Set-Enable Registers */
+ __IOM uint32_t ICENABLER[32]; /*!< \brief Offset: 0x180 (R/W) Interrupt Clear-Enable Registers */
+ __IOM uint32_t ISPENDR[32]; /*!< \brief Offset: 0x200 (R/W) Interrupt Set-Pending Registers */
+ __IOM uint32_t ICPENDR[32]; /*!< \brief Offset: 0x280 (R/W) Interrupt Clear-Pending Registers */
+ __IOM uint32_t ISACTIVER[32]; /*!< \brief Offset: 0x300 (R/W) Interrupt Set-Active Registers */
+ __IOM uint32_t ICACTIVER[32]; /*!< \brief Offset: 0x380 (R/W) Interrupt Clear-Active Registers */
+ __IOM uint32_t IPRIORITYR[255]; /*!< \brief Offset: 0x400 (R/W) Interrupt Priority Registers */
+ RESERVED(6, uint32_t)
+ __IOM uint32_t ITARGETSR[255]; /*!< \brief Offset: 0x800 (R/W) Interrupt Targets Registers */
+ RESERVED(7, uint32_t)
+ __IOM uint32_t ICFGR[64]; /*!< \brief Offset: 0xC00 (R/W) Interrupt Configuration Registers */
+ __IOM uint32_t IGRPMODR[32]; /*!< \brief Offset: 0xD00 (R/W) Interrupt Group Modifier Registers */
+ RESERVED(8[32], uint32_t)
+ __IOM uint32_t NSACR[64]; /*!< \brief Offset: 0xE00 (R/W) Non-secure Access Control Registers */
+ __OM uint32_t SGIR; /*!< \brief Offset: 0xF00 ( /W) Software Generated Interrupt Register */
+ RESERVED(9[3], uint32_t)
+ __IOM uint32_t CPENDSGIR[4]; /*!< \brief Offset: 0xF10 (R/W) SGI Clear-Pending Registers */
+ __IOM uint32_t SPENDSGIR[4]; /*!< \brief Offset: 0xF20 (R/W) SGI Set-Pending Registers */
+ RESERVED(10[5236], uint32_t)
+ __IOM uint64_t IROUTER[988]; /*!< \brief Offset: 0x6100(R/W) Interrupt Routing Registers */
+} GICDistributor_Type;
+
+#define GICDistributor ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE ) /*!< \brief GIC Distributor register set access pointer */
+
+/** \brief Structure type to access the Generic Interrupt Controller Interface (GICC)
+*/
+typedef struct
+{
+ __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) CPU Interface Control Register */
+ __IOM uint32_t PMR; /*!< \brief Offset: 0x004 (R/W) Interrupt Priority Mask Register */
+ __IOM uint32_t BPR; /*!< \brief Offset: 0x008 (R/W) Binary Point Register */
+ __IM uint32_t IAR; /*!< \brief Offset: 0x00C (R/ ) Interrupt Acknowledge Register */
+ __OM uint32_t EOIR; /*!< \brief Offset: 0x010 ( /W) End Of Interrupt Register */
+ __IM uint32_t RPR; /*!< \brief Offset: 0x014 (R/ ) Running Priority Register */
+ __IM uint32_t HPPIR; /*!< \brief Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register */
+ __IOM uint32_t ABPR; /*!< \brief Offset: 0x01C (R/W) Aliased Binary Point Register */
+ __IM uint32_t AIAR; /*!< \brief Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register */
+ __OM uint32_t AEOIR; /*!< \brief Offset: 0x024 ( /W) Aliased End Of Interrupt Register */
+ __IM uint32_t AHPPIR; /*!< \brief Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register */
+ __IOM uint32_t STATUSR; /*!< \brief Offset: 0x02C (R/W) Error Reporting Status Register, optional */
+ RESERVED(1[40], uint32_t)
+ __IOM uint32_t APR[4]; /*!< \brief Offset: 0x0D0 (R/W) Active Priority Register */
+ __IOM uint32_t NSAPR[4]; /*!< \brief Offset: 0x0E0 (R/W) Non-secure Active Priority Register */
+ RESERVED(2[3], uint32_t)
+ __IM uint32_t IIDR; /*!< \brief Offset: 0x0FC (R/ ) CPU Interface Identification Register */
+ RESERVED(3[960], uint32_t)
+ __OM uint32_t DIR; /*!< \brief Offset: 0x1000( /W) Deactivate Interrupt Register */
+} GICInterface_Type;
+
+#define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE ) /*!< \brief GIC Interface register set access pointer */
+#endif
+
+#if (__TIM_PRESENT == 1U) || defined(DOXYGEN)
+#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN)
+/** \brief Structure type to access the Private Timer
+*/
+typedef struct
+{
+ __IOM uint32_t LOAD; //!< \brief Offset: 0x000 (R/W) Private Timer Load Register
+ __IOM uint32_t COUNTER; //!< \brief Offset: 0x004 (R/W) Private Timer Counter Register
+ __IOM uint32_t CONTROL; //!< \brief Offset: 0x008 (R/W) Private Timer Control Register
+ __IOM uint32_t ISR; //!< \brief Offset: 0x00C (R/W) Private Timer Interrupt Status Register
+ RESERVED(0[4], uint32_t)
+ __IOM uint32_t WLOAD; //!< \brief Offset: 0x020 (R/W) Watchdog Load Register
+ __IOM uint32_t WCOUNTER; //!< \brief Offset: 0x024 (R/W) Watchdog Counter Register
+ __IOM uint32_t WCONTROL; //!< \brief Offset: 0x028 (R/W) Watchdog Control Register
+ __IOM uint32_t WISR; //!< \brief Offset: 0x02C (R/W) Watchdog Interrupt Status Register
+ __IOM uint32_t WRESET; //!< \brief Offset: 0x030 (R/W) Watchdog Reset Status Register
+ __OM uint32_t WDISABLE; //!< \brief Offset: 0x034 ( /W) Watchdog Disable Register
+} Timer_Type;
+#define PTIM ((Timer_Type *) TIMER_BASE ) /*!< \brief Timer register struct */
+#endif
+#endif
+
+ /*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - L1 Cache Functions
+ - L2C-310 Cache Controller Functions
+ - PL1 Timer Functions
+ - GIC Functions
+ - MMU Functions
+ ******************************************************************************/
+
+/* ########################## L1 Cache functions ################################# */
+
+/** \brief Enable Caches by setting I and C bits in SCTLR register.
+*/
+__STATIC_FORCEINLINE void L1C_EnableCaches(void) {
+ __set_SCTLR( __get_SCTLR() | SCTLR_I_Msk | SCTLR_C_Msk);
+ __ISB();
+}
+
+/** \brief Disable Caches by clearing I and C bits in SCTLR register.
+*/
+__STATIC_FORCEINLINE void L1C_DisableCaches(void) {
+ __set_SCTLR( __get_SCTLR() & (~SCTLR_I_Msk) & (~SCTLR_C_Msk));
+ __ISB();
+}
+
+/** \brief Enable Branch Prediction by setting Z bit in SCTLR register.
+*/
+__STATIC_FORCEINLINE void L1C_EnableBTAC(void) {
+ __set_SCTLR( __get_SCTLR() | SCTLR_Z_Msk);
+ __ISB();
+}
+
+/** \brief Disable Branch Prediction by clearing Z bit in SCTLR register.
+*/
+__STATIC_FORCEINLINE void L1C_DisableBTAC(void) {
+ __set_SCTLR( __get_SCTLR() & (~SCTLR_Z_Msk));
+ __ISB();
+}
+
+/** \brief Invalidate entire branch predictor array
+*/
+__STATIC_FORCEINLINE void L1C_InvalidateBTAC(void) {
+ __set_BPIALL(0);
+ __DSB(); //ensure completion of the invalidation
+ __ISB(); //ensure instruction fetch path sees new state
+}
+
+/** \brief Invalidate the whole instruction cache
+*/
+__STATIC_FORCEINLINE void L1C_InvalidateICacheAll(void) {
+ __set_ICIALLU(0);
+ __DSB(); //ensure completion of the invalidation
+ __ISB(); //ensure instruction fetch path sees new I cache state
+}
+
+/** \brief Clean data cache line by address.
+* \param [in] va Pointer to data to clear the cache for.
+*/
+__STATIC_FORCEINLINE void L1C_CleanDCacheMVA(void *va) {
+ __set_DCCMVAC((uint32_t)va);
+ __DMB(); //ensure the ordering of data cache maintenance operations and their effects
+}
+
+/** \brief Invalidate data cache line by address.
+* \param [in] va Pointer to data to invalidate the cache for.
+*/
+__STATIC_FORCEINLINE void L1C_InvalidateDCacheMVA(void *va) {
+ __set_DCIMVAC((uint32_t)va);
+ __DMB(); //ensure the ordering of data cache maintenance operations and their effects
+}
+
+/** \brief Clean and Invalidate data cache by address.
+* \param [in] va Pointer to data to invalidate the cache for.
+*/
+__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheMVA(void *va) {
+ __set_DCCIMVAC((uint32_t)va);
+ __DMB(); //ensure the ordering of data cache maintenance operations and their effects
+}
+
+/** \brief Calculate log2 rounded up
+* - log(0) => 0
+* - log(1) => 0
+* - log(2) => 1
+* - log(3) => 2
+* - log(4) => 2
+* - log(5) => 3
+* : :
+* - log(16) => 4
+* - log(32) => 5
+* : :
+* \param [in] n input value parameter
+* \return log2(n)
+*/
+__STATIC_FORCEINLINE uint8_t __log2_up(uint32_t n)
+{
+ if (n < 2U) {
+ return 0U;
+ }
+ uint8_t log = 0U;
+ uint32_t t = n;
+ while(t > 1U)
+ {
+ log++;
+ t >>= 1U;
+ }
+ if (n & 1U) { log++; }
+ return log;
+}
+
+/** \brief Apply cache maintenance to given cache level.
+* \param [in] level cache level to be maintained
+* \param [in] maint 0 - invalidate, 1 - clean, otherwise - invalidate and clean
+*/
+__STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint)
+{
+ uint32_t Dummy;
+ uint32_t ccsidr;
+ uint32_t num_sets;
+ uint32_t num_ways;
+ uint32_t shift_way;
+ uint32_t log2_linesize;
+ int32_t log2_num_ways;
+
+ Dummy = level << 1U;
+ /* set csselr, select ccsidr register */
+ __set_CSSELR(Dummy);
+ /* get current ccsidr register */
+ ccsidr = __get_CCSIDR();
+ num_sets = ((ccsidr & 0x0FFFE000U) >> 13U) + 1U;
+ num_ways = ((ccsidr & 0x00001FF8U) >> 3U) + 1U;
+ log2_linesize = (ccsidr & 0x00000007U) + 2U + 2U;
+ log2_num_ways = __log2_up(num_ways);
+ if ((log2_num_ways < 0) || (log2_num_ways > 32)) {
+ return; // FATAL ERROR
+ }
+ shift_way = 32U - (uint32_t)log2_num_ways;
+ for(int32_t way = num_ways-1; way >= 0; way--)
+ {
+ for(int32_t set = num_sets-1; set >= 0; set--)
+ {
+ Dummy = (level << 1U) | (((uint32_t)set) << log2_linesize) | (((uint32_t)way) << shift_way);
+ switch (maint)
+ {
+ case 0U: __set_DCISW(Dummy); break;
+ case 1U: __set_DCCSW(Dummy); break;
+ default: __set_DCCISW(Dummy); break;
+ }
+ }
+ }
+ __DMB();
+}
+
+/** \brief Clean and Invalidate the entire data or unified cache
+* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
+* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean
+*/
+__STATIC_FORCEINLINE void L1C_CleanInvalidateCache(uint32_t op) {
+ uint32_t clidr;
+ uint32_t cache_type;
+ clidr = __get_CLIDR();
+ for(uint32_t i = 0U; i<7U; i++)
+ {
+ cache_type = (clidr >> i*3U) & 0x7UL;
+ if ((cache_type >= 2U) && (cache_type <= 4U))
+ {
+ __L1C_MaintainDCacheSetWay(i, op);
+ }
+ }
+}
+
+/** \brief Clean and Invalidate the entire data or unified cache
+* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
+* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean
+* \deprecated Use generic L1C_CleanInvalidateCache instead.
+*/
+CMSIS_DEPRECATED
+__STATIC_FORCEINLINE void __L1C_CleanInvalidateCache(uint32_t op) {
+ L1C_CleanInvalidateCache(op);
+}
+
+/** \brief Invalidate the whole data cache.
+*/
+__STATIC_FORCEINLINE void L1C_InvalidateDCacheAll(void) {
+ L1C_CleanInvalidateCache(0);
+}
+
+/** \brief Clean the whole data cache.
+ */
+__STATIC_FORCEINLINE void L1C_CleanDCacheAll(void) {
+ L1C_CleanInvalidateCache(1);
+}
+
+/** \brief Clean and invalidate the whole data cache.
+ */
+__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheAll(void) {
+ L1C_CleanInvalidateCache(2);
+}
+
+/* ########################## L2 Cache functions ################################# */
+#if (__L2C_PRESENT == 1U) || defined(DOXYGEN)
+/** \brief Cache Sync operation by writing CACHE_SYNC register.
+*/
+__STATIC_INLINE void L2C_Sync(void)
+{
+ L2C_310->CACHE_SYNC = 0x0;
+}
+
+/** \brief Read cache controller cache ID from CACHE_ID register.
+ * \return L2C_310_TypeDef::CACHE_ID
+ */
+__STATIC_INLINE int L2C_GetID (void)
+{
+ return L2C_310->CACHE_ID;
+}
+
+/** \brief Read cache controller cache type from CACHE_TYPE register.
+* \return L2C_310_TypeDef::CACHE_TYPE
+*/
+__STATIC_INLINE int L2C_GetType (void)
+{
+ return L2C_310->CACHE_TYPE;
+}
+
+/** \brief Invalidate all cache by way
+*/
+__STATIC_INLINE void L2C_InvAllByWay (void)
+{
+ unsigned int assoc;
+
+ if (L2C_310->AUX_CNT & (1U << 16U)) {
+ assoc = 16U;
+ } else {
+ assoc = 8U;
+ }
+
+ L2C_310->INV_WAY = (1U << assoc) - 1U;
+ while(L2C_310->INV_WAY & ((1U << assoc) - 1U)); //poll invalidate
+
+ L2C_Sync();
+}
+
+/** \brief Clean and Invalidate all cache by way
+*/
+__STATIC_INLINE void L2C_CleanInvAllByWay (void)
+{
+ unsigned int assoc;
+
+ if (L2C_310->AUX_CNT & (1U << 16U)) {
+ assoc = 16U;
+ } else {
+ assoc = 8U;
+ }
+
+ L2C_310->CLEAN_INV_WAY = (1U << assoc) - 1U;
+ while(L2C_310->CLEAN_INV_WAY & ((1U << assoc) - 1U)); //poll invalidate
+
+ L2C_Sync();
+}
+
+/** \brief Enable Level 2 Cache
+*/
+__STATIC_INLINE void L2C_Enable(void)
+{
+ L2C_310->CONTROL = 0;
+ L2C_310->INTERRUPT_CLEAR = 0x000001FFuL;
+ L2C_310->DEBUG_CONTROL = 0;
+ L2C_310->DATA_LOCK_0_WAY = 0;
+ L2C_310->CACHE_SYNC = 0;
+ L2C_310->CONTROL = 0x01;
+ L2C_Sync();
+}
+
+/** \brief Disable Level 2 Cache
+*/
+__STATIC_INLINE void L2C_Disable(void)
+{
+ L2C_310->CONTROL = 0x00;
+ L2C_Sync();
+}
+
+/** \brief Invalidate cache by physical address
+* \param [in] pa Pointer to data to invalidate cache for.
+*/
+__STATIC_INLINE void L2C_InvPa (void *pa)
+{
+ L2C_310->INV_LINE_PA = (unsigned int)pa;
+ L2C_Sync();
+}
+
+/** \brief Clean cache by physical address
+* \param [in] pa Pointer to data to invalidate cache for.
+*/
+__STATIC_INLINE void L2C_CleanPa (void *pa)
+{
+ L2C_310->CLEAN_LINE_PA = (unsigned int)pa;
+ L2C_Sync();
+}
+
+/** \brief Clean and invalidate cache by physical address
+* \param [in] pa Pointer to data to invalidate cache for.
+*/
+__STATIC_INLINE void L2C_CleanInvPa (void *pa)
+{
+ L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa;
+ L2C_Sync();
+}
+#endif
+
+/* ########################## GIC functions ###################################### */
+#if (__GIC_PRESENT == 1U) || defined(DOXYGEN)
+
+/** \brief Enable the interrupt distributor using the GIC's CTLR register.
+*/
+__STATIC_INLINE void GIC_EnableDistributor(void)
+{
+ GICDistributor->CTLR |= 1U;
+}
+
+/** \brief Disable the interrupt distributor using the GIC's CTLR register.
+*/
+__STATIC_INLINE void GIC_DisableDistributor(void)
+{
+ GICDistributor->CTLR &=~1U;
+}
+
+/** \brief Read the GIC's TYPER register.
+* \return GICDistributor_Type::TYPER
+*/
+__STATIC_INLINE uint32_t GIC_DistributorInfo(void)
+{
+ return (GICDistributor->TYPER);
+}
+
+/** \brief Reads the GIC's IIDR register.
+* \return GICDistributor_Type::IIDR
+*/
+__STATIC_INLINE uint32_t GIC_DistributorImplementer(void)
+{
+ return (GICDistributor->IIDR);
+}
+
+/** \brief Sets the GIC's ITARGETSR register for the given interrupt.
+* \param [in] IRQn Interrupt to be configured.
+* \param [in] cpu_target CPU interfaces to assign this interrupt to.
+*/
+__STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
+{
+ uint32_t mask = GICDistributor->ITARGETSR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U));
+ GICDistributor->ITARGETSR[IRQn / 4U] = mask | ((cpu_target & 0xFFUL) << ((IRQn % 4U) * 8U));
+}
+
+/** \brief Read the GIC's ITARGETSR register.
+* \param [in] IRQn Interrupt to acquire the configuration for.
+* \return GICDistributor_Type::ITARGETSR
+*/
+__STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn)
+{
+ return (GICDistributor->ITARGETSR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
+}
+
+/** \brief Enable the CPU's interrupt interface.
+*/
+__STATIC_INLINE void GIC_EnableInterface(void)
+{
+ GICInterface->CTLR |= 1U; //enable interface
+}
+
+/** \brief Disable the CPU's interrupt interface.
+*/
+__STATIC_INLINE void GIC_DisableInterface(void)
+{
+ GICInterface->CTLR &=~1U; //disable distributor
+}
+
+/** \brief Read the CPU's IAR register.
+* \return GICInterface_Type::IAR
+*/
+__STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void)
+{
+ return (IRQn_Type)(GICInterface->IAR);
+}
+
+/** \brief Writes the given interrupt number to the CPU's EOIR register.
+* \param [in] IRQn The interrupt to be signaled as finished.
+*/
+__STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn)
+{
+ GICInterface->EOIR = IRQn;
+}
+
+/** \brief Enables the given interrupt using GIC's ISENABLER register.
+* \param [in] IRQn The interrupt to be enabled.
+*/
+__STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn)
+{
+ GICDistributor->ISENABLER[IRQn / 32U] = 1U << (IRQn % 32U);
+}
+
+/** \brief Get interrupt enable status using GIC's ISENABLER register.
+* \param [in] IRQn The interrupt to be queried.
+* \return 0 - interrupt is not enabled, 1 - interrupt is enabled.
+*/
+__STATIC_INLINE uint32_t GIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ return (GICDistributor->ISENABLER[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
+}
+
+/** \brief Disables the given interrupt using GIC's ICENABLER register.
+* \param [in] IRQn The interrupt to be disabled.
+*/
+__STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn)
+{
+ GICDistributor->ICENABLER[IRQn / 32U] = 1U << (IRQn % 32U);
+}
+
+/** \brief Get interrupt pending status from GIC's ISPENDR register.
+* \param [in] IRQn The interrupt to be queried.
+* \return 0 - interrupt is not pending, 1 - interrupt is pendig.
+*/
+__STATIC_INLINE uint32_t GIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ uint32_t pend;
+
+ if (IRQn >= 16U) {
+ pend = (GICDistributor->ISPENDR[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
+ } else {
+ // INTID 0-15 Software Generated Interrupt
+ pend = (GICDistributor->SPENDSGIR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
+ // No CPU identification offered
+ if (pend != 0U) {
+ pend = 1U;
+ } else {
+ pend = 0U;
+ }
+ }
+
+ return (pend);
+}
+
+/** \brief Sets the given interrupt as pending using GIC's ISPENDR register.
+* \param [in] IRQn The interrupt to be enabled.
+*/
+__STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if (IRQn >= 16U) {
+ GICDistributor->ISPENDR[IRQn / 32U] = 1U << (IRQn % 32U);
+ } else {
+ // INTID 0-15 Software Generated Interrupt
+ GICDistributor->SPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U);
+ }
+}
+
+/** \brief Clears the given interrupt from being pending using GIC's ICPENDR register.
+* \param [in] IRQn The interrupt to be enabled.
+*/
+__STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if (IRQn >= 16U) {
+ GICDistributor->ICPENDR[IRQn / 32U] = 1U << (IRQn % 32U);
+ } else {
+ // INTID 0-15 Software Generated Interrupt
+ GICDistributor->CPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U);
+ }
+}
+
+/** \brief Sets the interrupt configuration using GIC's ICFGR register.
+* \param [in] IRQn The interrupt to be configured.
+* \param [in] int_config Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1)
+* Bit 1: 0 - level sensitive, 1 - edge triggered
+*/
+__STATIC_INLINE void GIC_SetConfiguration(IRQn_Type IRQn, uint32_t int_config)
+{
+ uint32_t icfgr = GICDistributor->ICFGR[IRQn / 16U];
+ uint32_t shift = (IRQn % 16U) << 1U;
+
+ icfgr &= (~(3U << shift));
+ icfgr |= ( int_config << shift);
+
+ GICDistributor->ICFGR[IRQn / 16U] = icfgr;
+}
+
+/** \brief Get the interrupt configuration from the GIC's ICFGR register.
+* \param [in] IRQn Interrupt to acquire the configuration for.
+* \return Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1)
+* Bit 1: 0 - level sensitive, 1 - edge triggered
+*/
+__STATIC_INLINE uint32_t GIC_GetConfiguration(IRQn_Type IRQn)
+{
+ return (GICDistributor->ICFGR[IRQn / 16U] >> ((IRQn % 16U) >> 1U));
+}
+
+/** \brief Set the priority for the given interrupt in the GIC's IPRIORITYR register.
+* \param [in] IRQn The interrupt to be configured.
+* \param [in] priority The priority for the interrupt, lower values denote higher priorities.
+*/
+__STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ uint32_t mask = GICDistributor->IPRIORITYR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U));
+ GICDistributor->IPRIORITYR[IRQn / 4U] = mask | ((priority & 0xFFUL) << ((IRQn % 4U) * 8U));
+}
+
+/** \brief Read the current interrupt priority from GIC's IPRIORITYR register.
+* \param [in] IRQn The interrupt to be queried.
+*/
+__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)
+{
+ return (GICDistributor->IPRIORITYR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
+}
+
+/** \brief Set the interrupt priority mask using CPU's PMR register.
+* \param [in] priority Priority mask to be set.
+*/
+__STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority)
+{
+ GICInterface->PMR = priority & 0xFFUL; //set priority mask
+}
+
+/** \brief Read the current interrupt priority mask from CPU's PMR register.
+* \result GICInterface_Type::PMR
+*/
+__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void)
+{
+ return GICInterface->PMR;
+}
+
+/** \brief Configures the group priority and subpriority split point using CPU's BPR register.
+* \param [in] binary_point Amount of bits used as subpriority.
+*/
+__STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point)
+{
+ GICInterface->BPR = binary_point & 7U; //set binary point
+}
+
+/** \brief Read the current group priority and subpriority split point from CPU's BPR register.
+* \return GICInterface_Type::BPR
+*/
+__STATIC_INLINE uint32_t GIC_GetBinaryPoint(void)
+{
+ return GICInterface->BPR;
+}
+
+/** \brief Get the status for a given interrupt.
+* \param [in] IRQn The interrupt to get status for.
+* \return 0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active
+*/
+__STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
+{
+ uint32_t pending, active;
+
+ active = ((GICDistributor->ISACTIVER[IRQn / 32U]) >> (IRQn % 32U)) & 1UL;
+ pending = ((GICDistributor->ISPENDR[IRQn / 32U]) >> (IRQn % 32U)) & 1UL;
+
+ return ((active<<1U) | pending);
+}
+
+/** \brief Generate a software interrupt using GIC's SGIR register.
+* \param [in] IRQn Software interrupt to be generated.
+* \param [in] target_list List of CPUs the software interrupt should be forwarded to.
+* \param [in] filter_list Filter to be applied to determine interrupt receivers.
+*/
+__STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
+{
+ GICDistributor->SGIR = ((filter_list & 3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (IRQn & 0x0FUL);
+}
+
+/** \brief Get the interrupt number of the highest interrupt pending from CPU's HPPIR register.
+* \return GICInterface_Type::HPPIR
+*/
+__STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void)
+{
+ return GICInterface->HPPIR;
+}
+
+/** \brief Provides information about the implementer and revision of the CPU interface.
+* \return GICInterface_Type::IIDR
+*/
+__STATIC_INLINE uint32_t GIC_GetInterfaceId(void)
+{
+ return GICInterface->IIDR;
+}
+
+/** \brief Set the interrupt group from the GIC's IGROUPR register.
+* \param [in] IRQn The interrupt to be queried.
+* \param [in] group Interrupt group number: 0 - Group 0, 1 - Group 1
+*/
+__STATIC_INLINE void GIC_SetGroup(IRQn_Type IRQn, uint32_t group)
+{
+ uint32_t igroupr = GICDistributor->IGROUPR[IRQn / 32U];
+ uint32_t shift = (IRQn % 32U);
+
+ igroupr &= (~(1U << shift));
+ igroupr |= ( (group & 1U) << shift);
+
+ GICDistributor->IGROUPR[IRQn / 32U] = igroupr;
+}
+#define GIC_SetSecurity GIC_SetGroup
+
+/** \brief Get the interrupt group from the GIC's IGROUPR register.
+* \param [in] IRQn The interrupt to be queried.
+* \return 0 - Group 0, 1 - Group 1
+*/
+__STATIC_INLINE uint32_t GIC_GetGroup(IRQn_Type IRQn)
+{
+ return (GICDistributor->IGROUPR[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
+}
+#define GIC_GetSecurity GIC_GetGroup
+
+/** \brief Initialize the interrupt distributor.
+*/
+__STATIC_INLINE void GIC_DistInit(void)
+{
+ uint32_t i;
+ uint32_t num_irq = 0U;
+ uint32_t priority_field;
+
+ //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0,
+ //configuring all of the interrupts as Secure.
+
+ //Disable interrupt forwarding
+ GIC_DisableDistributor();
+ //Get the maximum number of interrupts that the GIC supports
+ num_irq = 32U * ((GIC_DistributorInfo() & 0x1FU) + 1U);
+
+ /* Priority level is implementation defined.
+ To determine the number of priority bits implemented write 0xFF to an IPRIORITYR
+ priority field and read back the value stored.*/
+ GIC_SetPriority((IRQn_Type)0U, 0xFFU);
+ priority_field = GIC_GetPriority((IRQn_Type)0U);
+
+ for (i = 32U; i < num_irq; i++)
+ {
+ //Disable the SPI interrupt
+ GIC_DisableIRQ((IRQn_Type)i);
+ //Set level-sensitive (and N-N model)
+ GIC_SetConfiguration((IRQn_Type)i, 0U);
+ //Set priority
+ GIC_SetPriority((IRQn_Type)i, priority_field/2U);
+ //Set target list to CPU0
+ GIC_SetTarget((IRQn_Type)i, 1U);
+ }
+ //Enable distributor
+ GIC_EnableDistributor();
+}
+
+/** \brief Initialize the CPU's interrupt interface
+*/
+__STATIC_INLINE void GIC_CPUInterfaceInit(void)
+{
+ uint32_t i;
+ uint32_t priority_field;
+
+ //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0,
+ //configuring all of the interrupts as Secure.
+
+ //Disable interrupt forwarding
+ GIC_DisableInterface();
+
+ /* Priority level is implementation defined.
+ To determine the number of priority bits implemented write 0xFF to an IPRIORITYR
+ priority field and read back the value stored.*/
+ GIC_SetPriority((IRQn_Type)0U, 0xFFU);
+ priority_field = GIC_GetPriority((IRQn_Type)0U);
+
+ //SGI and PPI
+ for (i = 0U; i < 32U; i++)
+ {
+ if(i > 15U) {
+ //Set level-sensitive (and N-N model) for PPI
+ GIC_SetConfiguration((IRQn_Type)i, 0U);
+ }
+ //Disable SGI and PPI interrupts
+ GIC_DisableIRQ((IRQn_Type)i);
+ //Set priority
+ GIC_SetPriority((IRQn_Type)i, priority_field/2U);
+ }
+ //Enable interface
+ GIC_EnableInterface();
+ //Set binary point to 0
+ GIC_SetBinaryPoint(0U);
+ //Set priority mask
+ GIC_SetInterfacePriorityMask(0xFFU);
+}
+
+/** \brief Initialize and enable the GIC
+*/
+__STATIC_INLINE void GIC_Enable(void)
+{
+ GIC_DistInit();
+ GIC_CPUInterfaceInit(); //per CPU
+}
+#endif
+
+/* ########################## Generic Timer functions ############################ */
+#if (__TIM_PRESENT == 1U) || defined(DOXYGEN)
+
+/* PL1 Physical Timer */
+#if (__CORTEX_A == 7U) || defined(DOXYGEN)
+
+/** \brief Physical Timer Control register */
+typedef union
+{
+ struct
+ {
+ uint32_t ENABLE:1; /*!< \brief bit: 0 Enables the timer. */
+ uint32_t IMASK:1; /*!< \brief bit: 1 Timer output signal mask bit. */
+ uint32_t ISTATUS:1; /*!< \brief bit: 2 The status of the timer. */
+ RESERVED(0:29, uint32_t)
+ } b; /*!< \brief Structure used for bit access */
+ uint32_t w; /*!< \brief Type used for word access */
+} CNTP_CTL_Type;
+
+/** \brief Configures the frequency the timer shall run at.
+* \param [in] value The timer frequency in Hz.
+*/
+__STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value)
+{
+ __set_CNTFRQ(value);
+ __ISB();
+}
+
+/** \brief Sets the reset value of the timer.
+* \param [in] value The value the timer is loaded with.
+*/
+__STATIC_INLINE void PL1_SetLoadValue(uint32_t value)
+{
+ __set_CNTP_TVAL(value);
+ __ISB();
+}
+
+/** \brief Get the current counter value.
+* \return Current counter value.
+*/
+__STATIC_INLINE uint32_t PL1_GetCurrentValue(void)
+{
+ return(__get_CNTP_TVAL());
+}
+
+/** \brief Get the current physical counter value.
+* \return Current physical counter value.
+*/
+__STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue(void)
+{
+ return(__get_CNTPCT());
+}
+
+/** \brief Set the physical compare value.
+* \param [in] value New physical timer compare value.
+*/
+__STATIC_INLINE void PL1_SetPhysicalCompareValue(uint64_t value)
+{
+ __set_CNTP_CVAL(value);
+ __ISB();
+}
+
+/** \brief Get the physical compare value.
+* \return Physical compare value.
+*/
+__STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue(void)
+{
+ return(__get_CNTP_CVAL());
+}
+
+/** \brief Configure the timer by setting the control value.
+* \param [in] value New timer control value.
+*/
+__STATIC_INLINE void PL1_SetControl(uint32_t value)
+{
+ __set_CNTP_CTL(value);
+ __ISB();
+}
+
+/** \brief Get the control value.
+* \return Control value.
+*/
+__STATIC_INLINE uint32_t PL1_GetControl(void)
+{
+ return(__get_CNTP_CTL());
+}
+#endif
+
+/* Private Timer */
+#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN)
+/** \brief Set the load value to timers LOAD register.
+* \param [in] value The load value to be set.
+*/
+__STATIC_INLINE void PTIM_SetLoadValue(uint32_t value)
+{
+ PTIM->LOAD = value;
+}
+
+/** \brief Get the load value from timers LOAD register.
+* \return Timer_Type::LOAD
+*/
+__STATIC_INLINE uint32_t PTIM_GetLoadValue(void)
+{
+ return(PTIM->LOAD);
+}
+
+/** \brief Set current counter value from its COUNTER register.
+*/
+__STATIC_INLINE void PTIM_SetCurrentValue(uint32_t value)
+{
+ PTIM->COUNTER = value;
+}
+
+/** \brief Get current counter value from timers COUNTER register.
+* \result Timer_Type::COUNTER
+*/
+__STATIC_INLINE uint32_t PTIM_GetCurrentValue(void)
+{
+ return(PTIM->COUNTER);
+}
+
+/** \brief Configure the timer using its CONTROL register.
+* \param [in] value The new configuration value to be set.
+*/
+__STATIC_INLINE void PTIM_SetControl(uint32_t value)
+{
+ PTIM->CONTROL = value;
+}
+
+/** ref Timer_Type::CONTROL Get the current timer configuration from its CONTROL register.
+* \return Timer_Type::CONTROL
+*/
+__STATIC_INLINE uint32_t PTIM_GetControl(void)
+{
+ return(PTIM->CONTROL);
+}
+
+/** ref Timer_Type::CONTROL Get the event flag in timers ISR register.
+* \return 0 - flag is not set, 1- flag is set
+*/
+__STATIC_INLINE uint32_t PTIM_GetEventFlag(void)
+{
+ return (PTIM->ISR & 1UL);
+}
+
+/** ref Timer_Type::CONTROL Clears the event flag in timers ISR register.
+*/
+__STATIC_INLINE void PTIM_ClearEventFlag(void)
+{
+ PTIM->ISR = 1;
+}
+#endif
+#endif
+
+/* ########################## MMU functions ###################################### */
+
+#define SECTION_DESCRIPTOR (0x2)
+#define SECTION_MASK (0xFFFFFFFC)
+
+#define SECTION_TEXCB_MASK (0xFFFF8FF3)
+#define SECTION_B_SHIFT (2)
+#define SECTION_C_SHIFT (3)
+#define SECTION_TEX0_SHIFT (12)
+#define SECTION_TEX1_SHIFT (13)
+#define SECTION_TEX2_SHIFT (14)
+
+#define SECTION_XN_MASK (0xFFFFFFEF)
+#define SECTION_XN_SHIFT (4)
+
+#define SECTION_DOMAIN_MASK (0xFFFFFE1F)
+#define SECTION_DOMAIN_SHIFT (5)
+
+#define SECTION_P_MASK (0xFFFFFDFF)
+#define SECTION_P_SHIFT (9)
+
+#define SECTION_AP_MASK (0xFFFF73FF)
+#define SECTION_AP_SHIFT (10)
+#define SECTION_AP2_SHIFT (15)
+
+#define SECTION_S_MASK (0xFFFEFFFF)
+#define SECTION_S_SHIFT (16)
+
+#define SECTION_NG_MASK (0xFFFDFFFF)
+#define SECTION_NG_SHIFT (17)
+
+#define SECTION_NS_MASK (0xFFF7FFFF)
+#define SECTION_NS_SHIFT (19)
+
+#define PAGE_L1_DESCRIPTOR (0x1)
+#define PAGE_L1_MASK (0xFFFFFFFC)
+
+#define PAGE_L2_4K_DESC (0x2)
+#define PAGE_L2_4K_MASK (0xFFFFFFFD)
+
+#define PAGE_L2_64K_DESC (0x1)
+#define PAGE_L2_64K_MASK (0xFFFFFFFC)
+
+#define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
+#define PAGE_4K_B_SHIFT (2)
+#define PAGE_4K_C_SHIFT (3)
+#define PAGE_4K_TEX0_SHIFT (6)
+#define PAGE_4K_TEX1_SHIFT (7)
+#define PAGE_4K_TEX2_SHIFT (8)
+
+#define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
+#define PAGE_64K_B_SHIFT (2)
+#define PAGE_64K_C_SHIFT (3)
+#define PAGE_64K_TEX0_SHIFT (12)
+#define PAGE_64K_TEX1_SHIFT (13)
+#define PAGE_64K_TEX2_SHIFT (14)
+
+#define PAGE_TEXCB_MASK (0xFFFF8FF3)
+#define PAGE_B_SHIFT (2)
+#define PAGE_C_SHIFT (3)
+#define PAGE_TEX_SHIFT (12)
+
+#define PAGE_XN_4K_MASK (0xFFFFFFFE)
+#define PAGE_XN_4K_SHIFT (0)
+#define PAGE_XN_64K_MASK (0xFFFF7FFF)
+#define PAGE_XN_64K_SHIFT (15)
+
+#define PAGE_DOMAIN_MASK (0xFFFFFE1F)
+#define PAGE_DOMAIN_SHIFT (5)
+
+#define PAGE_P_MASK (0xFFFFFDFF)
+#define PAGE_P_SHIFT (9)
+
+#define PAGE_AP_MASK (0xFFFFFDCF)
+#define PAGE_AP_SHIFT (4)
+#define PAGE_AP2_SHIFT (9)
+
+#define PAGE_S_MASK (0xFFFFFBFF)
+#define PAGE_S_SHIFT (10)
+
+#define PAGE_NG_MASK (0xFFFFF7FF)
+#define PAGE_NG_SHIFT (11)
+
+#define PAGE_NS_MASK (0xFFFFFFF7)
+#define PAGE_NS_SHIFT (3)
+
+#define OFFSET_1M (0x00100000)
+#define OFFSET_64K (0x00010000)
+#define OFFSET_4K (0x00001000)
+
+#define DESCRIPTOR_FAULT (0x00000000)
+
+/* Attributes enumerations */
+
+/* Region size attributes */
+typedef enum
+{
+ SECTION,
+ PAGE_4k,
+ PAGE_64k,
+} mmu_region_size_Type;
+
+/* Region type attributes */
+typedef enum
+{
+ NORMAL,
+ DEVICE,
+ SHARED_DEVICE,
+ NON_SHARED_DEVICE,
+ STRONGLY_ORDERED
+} mmu_memory_Type;
+
+/* Region cacheability attributes */
+typedef enum
+{
+ NON_CACHEABLE,
+ WB_WA,
+ WT,
+ WB_NO_WA,
+} mmu_cacheability_Type;
+
+/* Region parity check attributes */
+typedef enum
+{
+ ECC_DISABLED,
+ ECC_ENABLED,
+} mmu_ecc_check_Type;
+
+/* Region execution attributes */
+typedef enum
+{
+ EXECUTE,
+ NON_EXECUTE,
+} mmu_execute_Type;
+
+/* Region global attributes */
+typedef enum
+{
+ GLOBAL,
+ NON_GLOBAL,
+} mmu_global_Type;
+
+/* Region shareability attributes */
+typedef enum
+{
+ NON_SHARED,
+ SHARED,
+} mmu_shared_Type;
+
+/* Region security attributes */
+typedef enum
+{
+ SECURE,
+ NON_SECURE,
+} mmu_secure_Type;
+
+/* Region access attributes */
+typedef enum
+{
+ NO_ACCESS,
+ RW,
+ READ,
+} mmu_access_Type;
+
+/* Memory Region definition */
+typedef struct RegionStruct {
+ mmu_region_size_Type rg_t;
+ mmu_memory_Type mem_t;
+ uint8_t domain;
+ mmu_cacheability_Type inner_norm_t;
+ mmu_cacheability_Type outer_norm_t;
+ mmu_ecc_check_Type e_t;
+ mmu_execute_Type xn_t;
+ mmu_global_Type g_t;
+ mmu_secure_Type sec_t;
+ mmu_access_Type priv_t;
+ mmu_access_Type user_t;
+ mmu_shared_Type sh_t;
+
+} mmu_region_attributes_Type;
+
+//Following macros define the descriptors and attributes
+//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0
+#define section_normal(descriptor_l1, region) region.rg_t = SECTION; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = WB_WA; \
+ region.outer_norm_t = WB_WA; \
+ region.mem_t = NORMAL; \
+ region.sec_t = SECURE; \
+ region.xn_t = EXECUTE; \
+ region.priv_t = RW; \
+ region.user_t = RW; \
+ region.sh_t = NON_SHARED; \
+ MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Normal_NC. Outer & inner non-cacheable, non-shareable, executable, rw, domain 0
+#define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = NON_CACHEABLE; \
+ region.outer_norm_t = NON_CACHEABLE; \
+ region.mem_t = NORMAL; \
+ region.sec_t = SECURE; \
+ region.xn_t = EXECUTE; \
+ region.priv_t = RW; \
+ region.user_t = RW; \
+ region.sh_t = NON_SHARED; \
+ MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0
+#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = WB_WA; \
+ region.outer_norm_t = WB_WA; \
+ region.mem_t = NORMAL; \
+ region.sec_t = SECURE; \
+ region.xn_t = EXECUTE; \
+ region.priv_t = READ; \
+ region.user_t = READ; \
+ region.sh_t = NON_SHARED; \
+ MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Normal_RO. Sect_Normal_Cod, but not executable
+#define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = WB_WA; \
+ region.outer_norm_t = WB_WA; \
+ region.mem_t = NORMAL; \
+ region.sec_t = SECURE; \
+ region.xn_t = NON_EXECUTE; \
+ region.priv_t = READ; \
+ region.user_t = READ; \
+ region.sh_t = NON_SHARED; \
+ MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable
+#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = WB_WA; \
+ region.outer_norm_t = WB_WA; \
+ region.mem_t = NORMAL; \
+ region.sec_t = SECURE; \
+ region.xn_t = NON_EXECUTE; \
+ region.priv_t = RW; \
+ region.user_t = RW; \
+ region.sh_t = NON_SHARED; \
+ MMU_GetSectionDescriptor(&descriptor_l1, region);
+//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
+#define section_so(descriptor_l1, region) region.rg_t = SECTION; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = NON_CACHEABLE; \
+ region.outer_norm_t = NON_CACHEABLE; \
+ region.mem_t = STRONGLY_ORDERED; \
+ region.sec_t = SECURE; \
+ region.xn_t = NON_EXECUTE; \
+ region.priv_t = RW; \
+ region.user_t = RW; \
+ region.sh_t = NON_SHARED; \
+ MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0
+#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = NON_CACHEABLE; \
+ region.outer_norm_t = NON_CACHEABLE; \
+ region.mem_t = STRONGLY_ORDERED; \
+ region.sec_t = SECURE; \
+ region.xn_t = NON_EXECUTE; \
+ region.priv_t = READ; \
+ region.user_t = READ; \
+ region.sh_t = NON_SHARED; \
+ MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Device_RW. Sect_Device_RO, but writeable
+#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = NON_CACHEABLE; \
+ region.outer_norm_t = NON_CACHEABLE; \
+ region.mem_t = STRONGLY_ORDERED; \
+ region.sec_t = SECURE; \
+ region.xn_t = NON_EXECUTE; \
+ region.priv_t = RW; \
+ region.user_t = RW; \
+ region.sh_t = NON_SHARED; \
+ MMU_GetSectionDescriptor(&descriptor_l1, region);
+//Page_4k_Device_RW. Shared device, not executable, rw, domain 0
+#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = NON_CACHEABLE; \
+ region.outer_norm_t = NON_CACHEABLE; \
+ region.mem_t = SHARED_DEVICE; \
+ region.sec_t = SECURE; \
+ region.xn_t = NON_EXECUTE; \
+ region.priv_t = RW; \
+ region.user_t = RW; \
+ region.sh_t = NON_SHARED; \
+ MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
+
+//Page_64k_Device_RW. Shared device, not executable, rw, domain 0
+#define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = NON_CACHEABLE; \
+ region.outer_norm_t = NON_CACHEABLE; \
+ region.mem_t = SHARED_DEVICE; \
+ region.sec_t = SECURE; \
+ region.xn_t = NON_EXECUTE; \
+ region.priv_t = RW; \
+ region.user_t = RW; \
+ region.sh_t = NON_SHARED; \
+ MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
+
+/** \brief Set section execution-never attribute
+
+ \param [out] descriptor_l1 L1 descriptor.
+ \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn)
+{
+ *descriptor_l1 &= SECTION_XN_MASK;
+ *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
+ return 0;
+}
+
+/** \brief Set section domain
+
+ \param [out] descriptor_l1 L1 descriptor.
+ \param [in] domain Section domain
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain)
+{
+ *descriptor_l1 &= SECTION_DOMAIN_MASK;
+ *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
+ return 0;
+}
+
+/** \brief Set section parity check
+
+ \param [out] descriptor_l1 L1 descriptor.
+ \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
+{
+ *descriptor_l1 &= SECTION_P_MASK;
+ *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
+ return 0;
+}
+
+/** \brief Set section access privileges
+
+ \param [out] descriptor_l1 L1 descriptor.
+ \param [in] user User Level Access: NO_ACCESS, RW, READ
+ \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
+ \param [in] afe Access flag enable
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
+{
+ uint32_t ap = 0;
+
+ if (afe == 0) { //full access
+ if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
+ else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
+ else if ((priv == RW) && (user == READ)) { ap = 0x2; }
+ else if ((priv == RW) && (user == RW)) { ap = 0x3; }
+ else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
+ else if ((priv == READ) && (user == READ)) { ap = 0x7; }
+ }
+
+ else { //Simplified access
+ if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
+ else if ((priv == RW) && (user == RW)) { ap = 0x3; }
+ else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
+ else if ((priv == READ) && (user == READ)) { ap = 0x7; }
+ }
+
+ *descriptor_l1 &= SECTION_AP_MASK;
+ *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
+ *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
+
+ return 0;
+}
+
+/** \brief Set section shareability
+
+ \param [out] descriptor_l1 L1 descriptor.
+ \param [in] s_bit Section shareability: NON_SHARED, SHARED
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
+{
+ *descriptor_l1 &= SECTION_S_MASK;
+ *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
+ return 0;
+}
+
+/** \brief Set section Global attribute
+
+ \param [out] descriptor_l1 L1 descriptor.
+ \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit)
+{
+ *descriptor_l1 &= SECTION_NG_MASK;
+ *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
+ return 0;
+}
+
+/** \brief Set section Security attribute
+
+ \param [out] descriptor_l1 L1 descriptor.
+ \param [in] s_bit Section Security attribute: SECURE, NON_SECURE
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
+{
+ *descriptor_l1 &= SECTION_NS_MASK;
+ *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
+ return 0;
+}
+
+/* Page 4k or 64k */
+/** \brief Set 4k/64k page execution-never attribute
+
+ \param [out] descriptor_l2 L2 descriptor.
+ \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
+ \param [in] page Page size: PAGE_4k, PAGE_64k,
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
+{
+ if (page == PAGE_4k)
+ {
+ *descriptor_l2 &= PAGE_XN_4K_MASK;
+ *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
+ }
+ else
+ {
+ *descriptor_l2 &= PAGE_XN_64K_MASK;
+ *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
+ }
+ return 0;
+}
+
+/** \brief Set 4k/64k page domain
+
+ \param [out] descriptor_l1 L1 descriptor.
+ \param [in] domain Page domain
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain)
+{
+ *descriptor_l1 &= PAGE_DOMAIN_MASK;
+ *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
+ return 0;
+}
+
+/** \brief Set 4k/64k page parity check
+
+ \param [out] descriptor_l1 L1 descriptor.
+ \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
+{
+ *descriptor_l1 &= SECTION_P_MASK;
+ *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
+ return 0;
+}
+
+/** \brief Set 4k/64k page access privileges
+
+ \param [out] descriptor_l2 L2 descriptor.
+ \param [in] user User Level Access: NO_ACCESS, RW, READ
+ \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
+ \param [in] afe Access flag enable
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
+{
+ uint32_t ap = 0;
+
+ if (afe == 0) { //full access
+ if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
+ else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
+ else if ((priv == RW) && (user == READ)) { ap = 0x2; }
+ else if ((priv == RW) && (user == RW)) { ap = 0x3; }
+ else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
+ else if ((priv == READ) && (user == READ)) { ap = 0x6; }
+ }
+
+ else { //Simplified access
+ if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
+ else if ((priv == RW) && (user == RW)) { ap = 0x3; }
+ else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
+ else if ((priv == READ) && (user == READ)) { ap = 0x7; }
+ }
+
+ *descriptor_l2 &= PAGE_AP_MASK;
+ *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
+ *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
+
+ return 0;
+}
+
+/** \brief Set 4k/64k page shareability
+
+ \param [out] descriptor_l2 L2 descriptor.
+ \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
+{
+ *descriptor_l2 &= PAGE_S_MASK;
+ *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
+ return 0;
+}
+
+/** \brief Set 4k/64k page Global attribute
+
+ \param [out] descriptor_l2 L2 descriptor.
+ \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit)
+{
+ *descriptor_l2 &= PAGE_NG_MASK;
+ *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
+ return 0;
+}
+
+/** \brief Set 4k/64k page Security attribute
+
+ \param [out] descriptor_l1 L1 descriptor.
+ \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
+{
+ *descriptor_l1 &= PAGE_NS_MASK;
+ *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
+ return 0;
+}
+
+/** \brief Set Section memory attributes
+
+ \param [out] descriptor_l1 L1 descriptor.
+ \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
+ \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
+ \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
+{
+ *descriptor_l1 &= SECTION_TEXCB_MASK;
+
+ if (STRONGLY_ORDERED == mem)
+ {
+ return 0;
+ }
+ else if (SHARED_DEVICE == mem)
+ {
+ *descriptor_l1 |= (1 << SECTION_B_SHIFT);
+ }
+ else if (NON_SHARED_DEVICE == mem)
+ {
+ *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
+ }
+ else if (NORMAL == mem)
+ {
+ *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
+ switch(inner)
+ {
+ case NON_CACHEABLE:
+ break;
+ case WB_WA:
+ *descriptor_l1 |= (1 << SECTION_B_SHIFT);
+ break;
+ case WT:
+ *descriptor_l1 |= 1 << SECTION_C_SHIFT;
+ break;
+ case WB_NO_WA:
+ *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
+ break;
+ }
+ switch(outer)
+ {
+ case NON_CACHEABLE:
+ break;
+ case WB_WA:
+ *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
+ break;
+ case WT:
+ *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
+ break;
+ case WB_NO_WA:
+ *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
+ break;
+ }
+ }
+ return 0;
+}
+
+/** \brief Set 4k/64k page memory attributes
+
+ \param [out] descriptor_l2 L2 descriptor.
+ \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
+ \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
+ \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
+ \param [in] page Page size
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
+{
+ *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
+
+ if (page == PAGE_64k)
+ {
+ //same as section
+ MMU_MemorySection(descriptor_l2, mem, outer, inner);
+ }
+ else
+ {
+ if (STRONGLY_ORDERED == mem)
+ {
+ return 0;
+ }
+ else if (SHARED_DEVICE == mem)
+ {
+ *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
+ }
+ else if (NON_SHARED_DEVICE == mem)
+ {
+ *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
+ }
+ else if (NORMAL == mem)
+ {
+ *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
+ switch(inner)
+ {
+ case NON_CACHEABLE:
+ break;
+ case WB_WA:
+ *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
+ break;
+ case WT:
+ *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
+ break;
+ case WB_NO_WA:
+ *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
+ break;
+ }
+ switch(outer)
+ {
+ case NON_CACHEABLE:
+ break;
+ case WB_WA:
+ *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
+ break;
+ case WT:
+ *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
+ break;
+ case WB_NO_WA:
+ *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
+ break;
+ }
+ }
+ }
+
+ return 0;
+}
+
+/** \brief Create a L1 section descriptor
+
+ \param [out] descriptor L1 descriptor
+ \param [in] reg Section attributes
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
+{
+ *descriptor = 0;
+
+ MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
+ MMU_XNSection(descriptor,reg.xn_t);
+ MMU_DomainSection(descriptor, reg.domain);
+ MMU_PSection(descriptor, reg.e_t);
+ MMU_APSection(descriptor, reg.priv_t, reg.user_t, 1);
+ MMU_SharedSection(descriptor,reg.sh_t);
+ MMU_GlobalSection(descriptor,reg.g_t);
+ MMU_SecureSection(descriptor,reg.sec_t);
+ *descriptor &= SECTION_MASK;
+ *descriptor |= SECTION_DESCRIPTOR;
+
+ return 0;
+}
+
+
+/** \brief Create a L1 and L2 4k/64k page descriptor
+
+ \param [out] descriptor L1 descriptor
+ \param [out] descriptor2 L2 descriptor
+ \param [in] reg 4k/64k page attributes
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
+{
+ *descriptor = 0;
+ *descriptor2 = 0;
+
+ switch (reg.rg_t)
+ {
+ case PAGE_4k:
+ MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
+ MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k);
+ MMU_DomainPage(descriptor, reg.domain);
+ MMU_PPage(descriptor, reg.e_t);
+ MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
+ MMU_SharedPage(descriptor2,reg.sh_t);
+ MMU_GlobalPage(descriptor2,reg.g_t);
+ MMU_SecurePage(descriptor,reg.sec_t);
+ *descriptor &= PAGE_L1_MASK;
+ *descriptor |= PAGE_L1_DESCRIPTOR;
+ *descriptor2 &= PAGE_L2_4K_MASK;
+ *descriptor2 |= PAGE_L2_4K_DESC;
+ break;
+
+ case PAGE_64k:
+ MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
+ MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k);
+ MMU_DomainPage(descriptor, reg.domain);
+ MMU_PPage(descriptor, reg.e_t);
+ MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
+ MMU_SharedPage(descriptor2,reg.sh_t);
+ MMU_GlobalPage(descriptor2,reg.g_t);
+ MMU_SecurePage(descriptor,reg.sec_t);
+ *descriptor &= PAGE_L1_MASK;
+ *descriptor |= PAGE_L1_DESCRIPTOR;
+ *descriptor2 &= PAGE_L2_64K_MASK;
+ *descriptor2 |= PAGE_L2_64K_DESC;
+ break;
+
+ case SECTION:
+ //error
+ break;
+ }
+
+ return 0;
+}
+
+/** \brief Create a 1MB Section
+
+ \param [in] ttb Translation table base address
+ \param [in] base_address Section base address
+ \param [in] count Number of sections to create
+ \param [in] descriptor_l1 L1 descriptor (region attributes)
+
+*/
+__STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
+{
+ uint32_t offset;
+ uint32_t entry;
+ uint32_t i;
+
+ offset = base_address >> 20;
+ entry = (base_address & 0xFFF00000) | descriptor_l1;
+
+ //4 bytes aligned
+ ttb = ttb + offset;
+
+ for (i = 0; i < count; i++ )
+ {
+ //4 bytes aligned
+ *ttb++ = entry;
+ entry += OFFSET_1M;
+ }
+}
+
+/** \brief Create a 4k page entry
+
+ \param [in] ttb L1 table base address
+ \param [in] base_address 4k base address
+ \param [in] count Number of 4k pages to create
+ \param [in] descriptor_l1 L1 descriptor (region attributes)
+ \param [in] ttb_l2 L2 table base address
+ \param [in] descriptor_l2 L2 descriptor (region attributes)
+
+*/
+__STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
+{
+
+ uint32_t offset, offset2;
+ uint32_t entry, entry2;
+ uint32_t i;
+
+ offset = base_address >> 20;
+ entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
+
+ //4 bytes aligned
+ ttb += offset;
+ //create l1_entry
+ *ttb = entry;
+
+ offset2 = (base_address & 0xff000) >> 12;
+ ttb_l2 += offset2;
+ entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
+ for (i = 0; i < count; i++ )
+ {
+ //4 bytes aligned
+ *ttb_l2++ = entry2;
+ entry2 += OFFSET_4K;
+ }
+}
+
+/** \brief Create a 64k page entry
+
+ \param [in] ttb L1 table base address
+ \param [in] base_address 64k base address
+ \param [in] count Number of 64k pages to create
+ \param [in] descriptor_l1 L1 descriptor (region attributes)
+ \param [in] ttb_l2 L2 table base address
+ \param [in] descriptor_l2 L2 descriptor (region attributes)
+
+*/
+__STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
+{
+ uint32_t offset, offset2;
+ uint32_t entry, entry2;
+ uint32_t i,j;
+
+
+ offset = base_address >> 20;
+ entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
+
+ //4 bytes aligned
+ ttb += offset;
+ //create l1_entry
+ *ttb = entry;
+
+ offset2 = (base_address & 0xff000) >> 12;
+ ttb_l2 += offset2;
+ entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
+ for (i = 0; i < count; i++ )
+ {
+ //create 16 entries
+ for (j = 0; j < 16; j++)
+ {
+ //4 bytes aligned
+ *ttb_l2++ = entry2;
+ }
+ entry2 += OFFSET_64K;
+ }
+}
+
+/** \brief Enable MMU
+*/
+__STATIC_INLINE void MMU_Enable(void)
+{
+ // Set M bit 0 to enable the MMU
+ // Set AFE bit to enable simplified access permissions model
+ // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
+ __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
+ __ISB();
+}
+
+/** \brief Disable MMU
+*/
+__STATIC_INLINE void MMU_Disable(void)
+{
+ // Clear M bit 0 to disable the MMU
+ __set_SCTLR( __get_SCTLR() & ~1);
+ __ISB();
+}
+
+/** \brief Invalidate entire unified TLB
+*/
+
+__STATIC_INLINE void MMU_InvalidateTLB(void)
+{
+ __set_TLBIALL(0);
+ __DSB(); //ensure completion of the invalidation
+ __ISB(); //ensure instruction fetch path sees new state
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CA_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Include/irq_ctrl.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Include/irq_ctrl.h
new file mode 100644
index 0000000..a6d313d
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Include/irq_ctrl.h
@@ -0,0 +1,186 @@
+/**************************************************************************//**
+ * @file irq_ctrl.h
+ * @brief Interrupt Controller API header file
+ * @version V1.0.0
+ * @date 23. June 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef IRQ_CTRL_H_
+#define IRQ_CTRL_H_
+
+#include <stdint.h>
+
+#ifndef IRQHANDLER_T
+#define IRQHANDLER_T
+/// Interrupt handler data type
+typedef void (*IRQHandler_t) (void);
+#endif
+
+#ifndef IRQN_ID_T
+#define IRQN_ID_T
+/// Interrupt ID number data type
+typedef int32_t IRQn_ID_t;
+#endif
+
+/* Interrupt mode bit-masks */
+#define IRQ_MODE_TRIG_Pos (0U)
+#define IRQ_MODE_TRIG_Msk (0x07UL /*<< IRQ_MODE_TRIG_Pos*/)
+#define IRQ_MODE_TRIG_LEVEL (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: level triggered interrupt
+#define IRQ_MODE_TRIG_LEVEL_LOW (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: low level triggered interrupt
+#define IRQ_MODE_TRIG_LEVEL_HIGH (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: high level triggered interrupt
+#define IRQ_MODE_TRIG_EDGE (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: edge triggered interrupt
+#define IRQ_MODE_TRIG_EDGE_RISING (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising edge triggered interrupt
+#define IRQ_MODE_TRIG_EDGE_FALLING (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: falling edge triggered interrupt
+#define IRQ_MODE_TRIG_EDGE_BOTH (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising and falling edge triggered interrupt
+
+#define IRQ_MODE_TYPE_Pos (3U)
+#define IRQ_MODE_TYPE_Msk (0x01UL << IRQ_MODE_TYPE_Pos)
+#define IRQ_MODE_TYPE_IRQ (0x00UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU IRQ line
+#define IRQ_MODE_TYPE_FIQ (0x01UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU FIQ line
+
+#define IRQ_MODE_DOMAIN_Pos (4U)
+#define IRQ_MODE_DOMAIN_Msk (0x01UL << IRQ_MODE_DOMAIN_Pos)
+#define IRQ_MODE_DOMAIN_NONSECURE (0x00UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting non-secure domain
+#define IRQ_MODE_DOMAIN_SECURE (0x01UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting secure domain
+
+#define IRQ_MODE_CPU_Pos (5U)
+#define IRQ_MODE_CPU_Msk (0xFFUL << IRQ_MODE_CPU_Pos)
+#define IRQ_MODE_CPU_ALL (0x00UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets all CPUs
+#define IRQ_MODE_CPU_0 (0x01UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 0
+#define IRQ_MODE_CPU_1 (0x02UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 1
+#define IRQ_MODE_CPU_2 (0x04UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 2
+#define IRQ_MODE_CPU_3 (0x08UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 3
+#define IRQ_MODE_CPU_4 (0x10UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 4
+#define IRQ_MODE_CPU_5 (0x20UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 5
+#define IRQ_MODE_CPU_6 (0x40UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 6
+#define IRQ_MODE_CPU_7 (0x80UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 7
+
+#define IRQ_MODE_ERROR (0x80000000UL) ///< Bit indicating mode value error
+
+/* Interrupt priority bit-masks */
+#define IRQ_PRIORITY_Msk (0x0000FFFFUL) ///< Interrupt priority value bit-mask
+#define IRQ_PRIORITY_ERROR (0x80000000UL) ///< Bit indicating priority value error
+
+/// Initialize interrupt controller.
+/// \return 0 on success, -1 on error.
+int32_t IRQ_Initialize (void);
+
+/// Register interrupt handler.
+/// \param[in] irqn interrupt ID number
+/// \param[in] handler interrupt handler function address
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler);
+
+/// Get the registered interrupt handler.
+/// \param[in] irqn interrupt ID number
+/// \return registered interrupt handler function address.
+IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn);
+
+/// Enable interrupt.
+/// \param[in] irqn interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_Enable (IRQn_ID_t irqn);
+
+/// Disable interrupt.
+/// \param[in] irqn interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_Disable (IRQn_ID_t irqn);
+
+/// Get interrupt enable state.
+/// \param[in] irqn interrupt ID number
+/// \return 0 - interrupt is disabled, 1 - interrupt is enabled.
+uint32_t IRQ_GetEnableState (IRQn_ID_t irqn);
+
+/// Configure interrupt request mode.
+/// \param[in] irqn interrupt ID number
+/// \param[in] mode mode configuration
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode);
+
+/// Get interrupt mode configuration.
+/// \param[in] irqn interrupt ID number
+/// \return current interrupt mode configuration with optional IRQ_MODE_ERROR bit set.
+uint32_t IRQ_GetMode (IRQn_ID_t irqn);
+
+/// Get ID number of current interrupt request (IRQ).
+/// \return interrupt ID number.
+IRQn_ID_t IRQ_GetActiveIRQ (void);
+
+/// Get ID number of current fast interrupt request (FIQ).
+/// \return interrupt ID number.
+IRQn_ID_t IRQ_GetActiveFIQ (void);
+
+/// Signal end of interrupt processing.
+/// \param[in] irqn interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn);
+
+/// Set interrupt pending flag.
+/// \param[in] irqn interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetPending (IRQn_ID_t irqn);
+
+/// Get interrupt pending flag.
+/// \param[in] irqn interrupt ID number
+/// \return 0 - interrupt is not pending, 1 - interrupt is pending.
+uint32_t IRQ_GetPending (IRQn_ID_t irqn);
+
+/// Clear interrupt pending flag.
+/// \param[in] irqn interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_ClearPending (IRQn_ID_t irqn);
+
+/// Set interrupt priority value.
+/// \param[in] irqn interrupt ID number
+/// \param[in] priority interrupt priority value
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority);
+
+/// Get interrupt priority.
+/// \param[in] irqn interrupt ID number
+/// \return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set.
+uint32_t IRQ_GetPriority (IRQn_ID_t irqn);
+
+/// Set priority masking threshold.
+/// \param[in] priority priority masking threshold value
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetPriorityMask (uint32_t priority);
+
+/// Get priority masking threshold
+/// \return current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set.
+uint32_t IRQ_GetPriorityMask (void);
+
+/// Set priority grouping field split point
+/// \param[in] bits number of MSB bits included in the group priority field comparison
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetPriorityGroupBits (uint32_t bits);
+
+/// Get priority grouping field split point
+/// \return current number of MSB bits included in the group priority field comparison with
+/// optional IRQ_PRIORITY_ERROR bit set.
+uint32_t IRQ_GetPriorityGroupBits (void);
+
+#endif // IRQ_CTRL_H_
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Source/irq_ctrl_gic.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Source/irq_ctrl_gic.c
new file mode 100644
index 0000000..cf08a53
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/Core_A/Source/irq_ctrl_gic.c
@@ -0,0 +1,410 @@
+/**************************************************************************//**
+ * @file irq_ctrl_gic.c
+ * @brief Interrupt controller handling implementation for GIC
+ * @version V1.0.1
+ * @date 9. April 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stddef.h>
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#include "irq_ctrl.h"
+
+#if defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U)
+
+/// Number of implemented interrupt lines
+#ifndef IRQ_GIC_LINE_COUNT
+#define IRQ_GIC_LINE_COUNT (1020U)
+#endif
+
+static IRQHandler_t IRQTable[IRQ_GIC_LINE_COUNT] = { 0U };
+static uint32_t IRQ_ID0;
+
+/// Initialize interrupt controller.
+__WEAK int32_t IRQ_Initialize (void) {
+ uint32_t i;
+
+ for (i = 0U; i < IRQ_GIC_LINE_COUNT; i++) {
+ IRQTable[i] = (IRQHandler_t)NULL;
+ }
+ GIC_Enable();
+ return (0);
+}
+
+
+/// Register interrupt handler.
+__WEAK int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) {
+ int32_t status;
+
+ if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+ IRQTable[irqn] = handler;
+ status = 0;
+ } else {
+ status = -1;
+ }
+
+ return (status);
+}
+
+
+/// Get the registered interrupt handler.
+__WEAK IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) {
+ IRQHandler_t h;
+
+ // Ignore CPUID field (software generated interrupts)
+ irqn &= 0x3FFU;
+
+ if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+ h = IRQTable[irqn];
+ } else {
+ h = (IRQHandler_t)0;
+ }
+
+ return (h);
+}
+
+
+/// Enable interrupt.
+__WEAK int32_t IRQ_Enable (IRQn_ID_t irqn) {
+ int32_t status;
+
+ if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+ GIC_EnableIRQ ((IRQn_Type)irqn);
+ status = 0;
+ } else {
+ status = -1;
+ }
+
+ return (status);
+}
+
+
+/// Disable interrupt.
+__WEAK int32_t IRQ_Disable (IRQn_ID_t irqn) {
+ int32_t status;
+
+ if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+ GIC_DisableIRQ ((IRQn_Type)irqn);
+ status = 0;
+ } else {
+ status = -1;
+ }
+
+ return (status);
+}
+
+
+/// Get interrupt enable state.
+__WEAK uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) {
+ uint32_t enable;
+
+ if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+ enable = GIC_GetEnableIRQ((IRQn_Type)irqn);
+ } else {
+ enable = 0U;
+ }
+
+ return (enable);
+}
+
+
+/// Configure interrupt request mode.
+__WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {
+ uint32_t val;
+ uint8_t cfg;
+ uint8_t secure;
+ uint8_t cpu;
+ int32_t status = 0;
+
+ if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+ // Check triggering mode
+ val = (mode & IRQ_MODE_TRIG_Msk);
+
+ if (val == IRQ_MODE_TRIG_LEVEL) {
+ cfg = 0x00U;
+ } else if (val == IRQ_MODE_TRIG_EDGE) {
+ cfg = 0x02U;
+ } else {
+ cfg = 0x00U;
+ status = -1;
+ }
+
+ // Check interrupt type
+ val = mode & IRQ_MODE_TYPE_Msk;
+
+ if (val != IRQ_MODE_TYPE_IRQ) {
+ status = -1;
+ }
+
+ // Check interrupt domain
+ val = mode & IRQ_MODE_DOMAIN_Msk;
+
+ if (val == IRQ_MODE_DOMAIN_NONSECURE) {
+ secure = 0U;
+ } else {
+ // Check security extensions support
+ val = GIC_DistributorInfo() & (1UL << 10U);
+
+ if (val != 0U) {
+ // Security extensions are supported
+ secure = 1U;
+ } else {
+ secure = 0U;
+ status = -1;
+ }
+ }
+
+ // Check interrupt CPU targets
+ val = mode & IRQ_MODE_CPU_Msk;
+
+ if (val == IRQ_MODE_CPU_ALL) {
+ cpu = 0xFFU;
+ } else {
+ cpu = val >> IRQ_MODE_CPU_Pos;
+ }
+
+ // Apply configuration if no mode error
+ if (status == 0) {
+ GIC_SetConfiguration((IRQn_Type)irqn, cfg);
+ GIC_SetTarget ((IRQn_Type)irqn, cpu);
+
+ if (secure != 0U) {
+ GIC_SetGroup ((IRQn_Type)irqn, secure);
+ }
+ }
+ }
+
+ return (status);
+}
+
+
+/// Get interrupt mode configuration.
+__WEAK uint32_t IRQ_GetMode (IRQn_ID_t irqn) {
+ uint32_t mode;
+ uint32_t val;
+
+ if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+ mode = IRQ_MODE_TYPE_IRQ;
+
+ // Get trigger mode
+ val = GIC_GetConfiguration((IRQn_Type)irqn);
+
+ if ((val & 2U) != 0U) {
+ // Corresponding interrupt is edge triggered
+ mode |= IRQ_MODE_TRIG_EDGE;
+ } else {
+ // Corresponding interrupt is level triggered
+ mode |= IRQ_MODE_TRIG_LEVEL;
+ }
+
+ // Get interrupt CPU targets
+ mode |= GIC_GetTarget ((IRQn_Type)irqn) << IRQ_MODE_CPU_Pos;
+
+ } else {
+ mode = IRQ_MODE_ERROR;
+ }
+
+ return (mode);
+}
+
+
+/// Get ID number of current interrupt request (IRQ).
+__WEAK IRQn_ID_t IRQ_GetActiveIRQ (void) {
+ IRQn_ID_t irqn;
+ uint32_t prio;
+
+ /* Dummy read to avoid GIC 390 errata 801120 */
+ GIC_GetHighPendingIRQ();
+
+ irqn = GIC_AcknowledgePending();
+
+ __DSB();
+
+ /* Workaround GIC 390 errata 733075 (GIC-390_Errata_Notice_v6.pdf, 09-Jul-2014) */
+ /* The following workaround code is for a single-core system. It would be */
+ /* different in a multi-core system. */
+ /* If the ID is 0 or 0x3FE or 0x3FF, then the GIC CPU interface may be locked-up */
+ /* so unlock it, otherwise service the interrupt as normal. */
+ /* Special IDs 1020=0x3FC and 1021=0x3FD are reserved values in GICv1 and GICv2 */
+ /* so will not occur here. */
+
+ if ((irqn == 0) || (irqn >= 0x3FE)) {
+ /* Unlock the CPU interface with a dummy write to Interrupt Priority Register */
+ prio = GIC_GetPriority((IRQn_Type)0);
+ GIC_SetPriority ((IRQn_Type)0, prio);
+
+ __DSB();
+
+ if ((irqn == 0U) && ((GIC_GetIRQStatus ((IRQn_Type)irqn) & 1U) != 0U) && (IRQ_ID0 == 0U)) {
+ /* If the ID is 0, is active and has not been seen before */
+ IRQ_ID0 = 1U;
+ }
+ /* End of Workaround GIC 390 errata 733075 */
+ }
+
+ return (irqn);
+}
+
+
+/// Get ID number of current fast interrupt request (FIQ).
+__WEAK IRQn_ID_t IRQ_GetActiveFIQ (void) {
+ return ((IRQn_ID_t)-1);
+}
+
+
+/// Signal end of interrupt processing.
+__WEAK int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) {
+ int32_t status;
+ IRQn_Type irq = (IRQn_Type)irqn;
+
+ irqn &= 0x3FFU;
+
+ if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+ GIC_EndInterrupt (irq);
+
+ if (irqn == 0) {
+ IRQ_ID0 = 0U;
+ }
+
+ status = 0;
+ } else {
+ status = -1;
+ }
+
+ return (status);
+}
+
+
+/// Set interrupt pending flag.
+__WEAK int32_t IRQ_SetPending (IRQn_ID_t irqn) {
+ int32_t status;
+
+ if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+ GIC_SetPendingIRQ ((IRQn_Type)irqn);
+ status = 0;
+ } else {
+ status = -1;
+ }
+
+ return (status);
+}
+
+/// Get interrupt pending flag.
+__WEAK uint32_t IRQ_GetPending (IRQn_ID_t irqn) {
+ uint32_t pending;
+
+ if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+ pending = GIC_GetPendingIRQ ((IRQn_Type)irqn);
+ } else {
+ pending = 0U;
+ }
+
+ return (pending & 1U);
+}
+
+
+/// Clear interrupt pending flag.
+__WEAK int32_t IRQ_ClearPending (IRQn_ID_t irqn) {
+ int32_t status;
+
+ if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+ GIC_ClearPendingIRQ ((IRQn_Type)irqn);
+ status = 0;
+ } else {
+ status = -1;
+ }
+
+ return (status);
+}
+
+
+/// Set interrupt priority value.
+__WEAK int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) {
+ int32_t status;
+
+ if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+ GIC_SetPriority ((IRQn_Type)irqn, priority);
+ status = 0;
+ } else {
+ status = -1;
+ }
+
+ return (status);
+}
+
+
+/// Get interrupt priority.
+__WEAK uint32_t IRQ_GetPriority (IRQn_ID_t irqn) {
+ uint32_t priority;
+
+ if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+ priority = GIC_GetPriority ((IRQn_Type)irqn);
+ } else {
+ priority = IRQ_PRIORITY_ERROR;
+ }
+
+ return (priority);
+}
+
+
+/// Set priority masking threshold.
+__WEAK int32_t IRQ_SetPriorityMask (uint32_t priority) {
+ GIC_SetInterfacePriorityMask (priority);
+ return (0);
+}
+
+
+/// Get priority masking threshold
+__WEAK uint32_t IRQ_GetPriorityMask (void) {
+ return GIC_GetInterfacePriorityMask();
+}
+
+
+/// Set priority grouping field split point
+__WEAK int32_t IRQ_SetPriorityGroupBits (uint32_t bits) {
+ int32_t status;
+
+ if (bits == IRQ_PRIORITY_Msk) {
+ bits = 7U;
+ }
+
+ if (bits < 8U) {
+ GIC_SetBinaryPoint (7U - bits);
+ status = 0;
+ } else {
+ status = -1;
+ }
+
+ return (status);
+}
+
+
+/// Get priority grouping field split point
+__WEAK uint32_t IRQ_GetPriorityGroupBits (void) {
+ uint32_t bp;
+
+ bp = GIC_GetBinaryPoint() & 0x07U;
+
+ return (7U - bp);
+}
+
+#endif
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/arr_desc/arr_desc.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/arr_desc/arr_desc.h
new file mode 100644
index 0000000..effab26
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/arr_desc/arr_desc.h
@@ -0,0 +1,220 @@
+#ifndef _ARR_DESC_H_
+#define _ARR_DESC_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+#include <stdint.h>
+#include <string.h> /* memset() */
+#include "../util/util.h" /* CONCAT() */
+
+/*--------------------------------------------------------------------------------*/
+/* Type Definitions */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Array-descriptor struct.
+ */
+typedef struct ARR_DESC_struct
+{
+ void * data_ptr; /* Pointer to the array contents. */
+ int32_t element_count; /* Number of current elements. */
+ int32_t element_size; /* Size of current elements in bytes. */
+ int32_t underlying_size; /* Size of underlying array in bytes. */
+} ARR_DESC_t;
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Prefix of the array variable's name when creating an array and an array
+ * descriptor at the same time.
+ */
+#define ARR_DESC_ARR_PREFIX ARR_DESC_ARR_
+
+/**
+ * Evaluate to the array variable's name when creating an array and an array
+ * descriptor at the same time.
+ */
+#define ARR_DESC_ARR_NAME(name) \
+ CONCAT(ARR_DESC_ARR_PREFIX, name)
+
+/**
+ * Define an #ARR_DESC_t by itself.
+ *
+ * @note The user must supply an array to store the data used by the
+ * #ARR_DESC_t.
+ */
+#define ARR_DESC_INTERNAL_DEFINE(name, data_ptr, \
+ element_count, element_size) \
+ ARR_DESC_t name = { \
+ data_ptr, \
+ element_count, \
+ element_size, \
+ element_count * element_size \
+ } \
+
+/**
+ * Define both an array and an #ARR_DESC_t that describes it.
+ *
+ * @note Use the #CURLY() macro for the content field; it provides the curly
+ * braces necessary for an array initialization.
+ */
+#define ARR_DESC_DEFINE(type, name, element_count, content) \
+ type ARR_DESC_ARR_NAME(name)[element_count] = content; \
+ ARR_DESC_INTERNAL_DEFINE(name, \
+ &ARR_DESC_ARR_NAME(name), \
+ element_count, \
+ sizeof(type)) /* Note the lacking semicolon */
+
+/**
+ * Create a #ARR_DESC_t which refers to a subset of the data in another.
+ *
+ * The new #ARR_DESC_t shares the same underlying array as the aliased
+ * #ARR_DESC_t, but only describes a subset of the originals values.
+ */
+#define ARR_DESC_DEFINE_SUBSET(name, original, element_cnt) \
+ ARR_DESC_INTERNAL_DEFINE(name, \
+ &ARR_DESC_ARR_NAME(original), \
+ element_cnt, \
+ sizeof(ARR_DESC_ARR_NAME(original)[0]) \
+ ) /* Note the lacking semicolon */
+
+/**
+ * Creat an #ARR_DESC_t which points to the data in an existing array.
+ *
+ * @param start_idx Offset in array_ptr of first element.
+ * @param element_cnt Number of elements to include in the #ARR_DESC_t.
+ *
+ * @example
+ *
+ * float my_floats[4] = {0.0f, 1.0f, 2.0f, 3.0f};
+ *
+ * ARR_DESC_DEFINE_USING_ARR(my_arr_desc, my_floats, 1, 3);
+ *
+ * printf("Element 0: %f\n", ARR_DESC_ELT(float, 0, &my_arr_desc));
+ * printf("Element 1: %f\n", ARR_DESC_ELT(float, 1, &my_arr_desc));
+ *
+ * Outputs:
+ *
+ * Element 0: 1.000000
+ * Element 1: 2.000000
+ *
+ * @warning There are no checks in place to catch invalid start indices; This
+ * is left to the user.
+ */
+#define ARR_DESC_DEFINE_USING_ARR(type, name, array_ptr, start_idx, element_cnt) \
+ ARR_DESC_INTERNAL_DEFINE( \
+ name, \
+ (type *) (array_ptr + start_idx), \
+ element_cnt, \
+ sizeof(type) \
+ ) /* Note the lacking semicolon*/
+
+/**
+ * Declare an #ARR_DESC_t object.
+ */
+#define ARR_DESC_DECLARE(name) \
+ extern ARR_DESC_t name /* Note the lacking semicolon */
+
+/**
+ * Evaluate to the number of bytes stored in the #ARR_DESC_t.
+ */
+#define ARR_DESC_BYTES(arr_desc_ptr) \
+ ((arr_desc_ptr)->element_count * (arr_desc_ptr)->element_size)
+
+/**
+ * Set the contents of #ARR_DESC_t to value.
+ */
+#define ARR_DESC_MEMSET(arr_desc_ptr, value, bytes) \
+ do \
+ { \
+ memset((arr_desc_ptr)->data_ptr, \
+ value, \
+ BOUND(0, \
+ (arr_desc_ptr)->underlying_size, \
+ bytes) \
+ ); \
+ } while (0)
+
+/**
+ * Perform a memcpy of 'bytes' bytes from the source #ARR_DESC_t to the
+ * destination #ARR_DESC_t.
+ */
+#define ARR_DESC_MEMCPY(arr_desc_dest_ptr, arr_desc_src_ptr, bytes) \
+ do \
+ { \
+ memcpy((arr_desc_dest_ptr)->data_ptr, \
+ (arr_desc_src_ptr)->data_ptr, \
+ BOUND(0, \
+ (arr_desc_dest_ptr)->underlying_size, \
+ bytes)); \
+ } while (0)
+
+/**
+ * Evaluate to true if the source #ARR_DESC_t contents will fit into the
+ * destination #ARR_DESC_t and false otherwise.
+ */
+#define ARR_DESC_COPYABLE(arr_desc_dest_ptr, arr_desc_src_ptr) \
+ (ARR_DESC_BYTES(arr_desc_src_ptr) <= \
+ (arr_desc_dest_ptr)->underlying_size)
+
+/**
+ * Copy all the data from the source #ARR_DESC_t to the destination
+ * #ARR_DESC_t.
+ *
+ * @note If the destination #ARR_DESC_t is too small to fit the source data the
+ * copy is aborted and nothing happens.
+ */
+#define ARR_DESC_COPY(arr_desc_dest_ptr, arr_desc_src_ptr) \
+ do \
+ { \
+ if (ARR_DESC_COPYABLE(arr_desc_dest_ptr, \
+ arr_desc_src_ptr)) \
+ { \
+ ARR_DESC_MEMCPY(arr_desc_dest_ptr, \
+ arr_desc_src_ptr, \
+ ARR_DESC_BYTES(arr_desc_src_ptr)); \
+ /* Update the properties*/ \
+ (arr_desc_dest_ptr)->element_count = \
+ (arr_desc_src_ptr)->element_count; \
+ (arr_desc_dest_ptr)->element_size = \
+ (arr_desc_src_ptr)->element_size; \
+ } \
+ } while (0)
+
+/**
+ * Compare the data in two #ARR_DESC_t structs for the specified number of
+ * bytes.
+ */
+#define ARR_DESC_MEMCMP(arr_desc_ptr_a, arr_desc_ptr_b, bytes) \
+ memcmp((arr_desc_ptr_a)->data_ptr, \
+ (arr_desc_ptr_b)->data_ptr, \
+ bytes) /* Note the lacking semicolon */ \
+
+/**
+ * Zero out the contents of the #ARR_DESC_t.
+ */
+#define ARR_DESC_ZERO(arr_desc_ptr) \
+ ARR_DESC_MEMSET(arr_desc_ptr, \
+ 0, \
+ (arr_desc_ptr)->underlying_size)
+
+/**
+ * Evaluate to the data address in #ARR_DESC_t at offset.
+ */
+#define ARR_DESC_DATA_ADDR(type, arr_desc_ptr, offset) \
+ ((void*)(((type *) \
+ ((arr_desc_ptr)->data_ptr)) \
+ + offset))
+
+/**
+ * Evaluate to the element in #ARR_DESC_t with type at idx.
+ */
+#define ARR_DESC_ELT(type, idx, arr_desc_ptr) \
+ (*((type *) ARR_DESC_DATA_ADDR(type, \
+ arr_desc_ptr, \
+ idx)))
+
+#endif /* _ARR_DESC_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest.h
new file mode 100644
index 0000000..9d0af06
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest.h
@@ -0,0 +1,17 @@
+#ifndef _JTEST_H_
+#define _JTEST_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "jtest_fw.h"
+#include "jtest_test.h"
+#include "jtest_test_define.h"
+#include "jtest_test_call.h"
+#include "jtest_group.h"
+#include "jtest_group_define.h"
+#include "jtest_group_call.h"
+#include "jtest_cycle.h"
+
+#endif /* _JTEST_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_cycle.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_cycle.h
new file mode 100644
index 0000000..1934af8
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_cycle.h
@@ -0,0 +1,65 @@
+#ifndef _JTEST_CYCLE_H_
+#define _JTEST_CYCLE_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "jtest_fw.h" /* JTEST_DUMP_STRF() */
+#include "jtest_systick.h"
+#include "jtest_util.h" /* STR() */
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Module Variables */
+/*--------------------------------------------------------------------------------*/
+extern const char * JTEST_CYCLE_STRF;
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Wrap the function call, fn_call, to count execution cycles and display the
+ * results.
+ */
+/* skipp function name + param
+#define JTEST_COUNT_CYCLES(fn_call) \
+ do \
+ { \
+ uint32_t __jtest_cycle_end_count; \
+ \
+ JTEST_SYSTICK_RESET(SysTick); \
+ JTEST_SYSTICK_START(SysTick); \
+ \
+ fn_call; \
+ \
+ __jtest_cycle_end_count = \
+ JTEST_SYSTICK_VALUE(SysTick); \
+ \
+ JTEST_SYSTICK_RESET(SysTick); \
+ JTEST_DUMP_STRF(JTEST_CYCLE_STRF, \
+ STR(fn_call), \
+ (JTEST_SYSTICK_INITIAL_VALUE - \
+ __jtest_cycle_end_count)); \
+ } while (0)
+*/
+#define JTEST_COUNT_CYCLES(fn_call) \
+ do \
+ { \
+ uint32_t __jtest_cycle_end_count; \
+ \
+ JTEST_SYSTICK_RESET(SysTick); \
+ JTEST_SYSTICK_START(SysTick); \
+ \
+ fn_call; \
+ \
+ __jtest_cycle_end_count = \
+ JTEST_SYSTICK_VALUE(SysTick); \
+ \
+ JTEST_SYSTICK_RESET(SysTick); \
+ JTEST_DUMP_STRF(JTEST_CYCLE_STRF, \
+ (JTEST_SYSTICK_INITIAL_VALUE - \
+ __jtest_cycle_end_count)); \
+ } while (0)
+
+#endif /* _JTEST_CYCLE_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_define.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_define.h
new file mode 100644
index 0000000..cbec329
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_define.h
@@ -0,0 +1,37 @@
+#ifndef _JTEST_DEFINE_H_
+#define _JTEST_DEFINE_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Makes a symbol for use as a struct name. Names made this way have two parts;
+ * the first parts is a prefix common to all structs of that class. The second
+ * is a specifier which differs for each instance of that struct type.
+ */
+#define JTEST_STRUCT_NAME(prefix, specifier) \
+ CONCAT(prefix, specifier)
+
+/**
+ * Define a struct with type with a name generated by #JTEST_STRUCT_NAME().
+ */
+#define JTEST_DEFINE_STRUCT(type, struct_name) \
+ type struct_name
+
+/**
+ * Declare a struct with type with a name generated by #JTEST_STRUCT_NAME().
+ */
+#define JTEST_DECLARE_STRUCT(struct_definition) \
+ extern struct_definition
+
+/**
+ * Define and initialize a struct (created with JTEST_DEFINE_STRUCT()) and
+ * initialize it with init_values.
+ */
+#define JTEST_INIT_STRUCT(struct_definition, init_values) \
+ struct_definition = { \
+ init_values \
+ }
+
+#endif /* _JTEST_DEFINE_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_fw.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_fw.h
new file mode 100644
index 0000000..13b015d
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_fw.h
@@ -0,0 +1,253 @@
+#ifndef _JTEST_FW_H_
+#define _JTEST_FW_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include <stdint.h> /* int32_t */
+#include <string.h> /* strcpy() */
+#include <stdio.h> /* sprintf() */
+#include "jtest_pf.h" /* Extend JTEST_FW_t with Pass/Fail data */
+#include "jtest_group.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Type Definitions */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * A struct used to interface with the Keil Debugger.
+ */
+typedef struct JTEST_FW_struct
+{
+ /* Action Triggers: The Keil debugger monitors these values for changes. In
+ * response to a change, the debugger executes code on the host. */
+ volatile int32_t test_start;
+ volatile int32_t test_end;
+ volatile int32_t group_start;
+ volatile int32_t group_end;
+ volatile int32_t dump_str;
+ volatile int32_t dump_data;
+ volatile int32_t exit_fw;
+
+ JTEST_GROUP_t * current_group_ptr;
+
+ /* Buffers: The C-code cannot send strings and data directly to the
+ * debugging framework. Instead, the debugger can be told to read 128 byte
+ * (by default) chunks of memory. Data received in this manner requires
+ * post-processing to be legible.*/
+ char * str_buffer;
+ char * data_buffer;
+
+ /* Pass/Fail Data */
+ JTEST_PF_MEMBERS;
+
+} JTEST_FW_t;
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Default name for the JTEST_FW struct.
+ *
+ * Define your own if you want the variable containing the #JTEST_FW_t to have
+ * a different name.
+ */
+#ifndef JTEST_FW
+#define JTEST_FW JTEST_FW
+#endif
+
+/**
+ * Default name for the JTEST_FW_STR_BUFFER.
+ *
+ * Define your own if you want the variable containing the char buffer to have
+ * a different name.
+ */
+#ifndef JTEST_FW_STR_BUFFER
+#define JTEST_FW_STR_BUFFER JTEST_FW_STR_BUFFER
+#endif
+
+/**
+ * Size of the #JTEST_FW_t, output string-buffer.
+ *
+ * If you change this value, make sure the "dump_str_fn" and "dump_data_fn"
+ * functions in jtest_fns.ini uses the same size. If you aren't sure, read the
+ * documentation Keil Debugger Command 'DISPLAY'.
+ */
+#define JTEST_BUF_SIZE 256
+
+
+/**
+ * The maximum number of bytes output at once using #JTEST_DUMP_STRF().
+ */
+#define JTEST_STR_MAX_OUTPUT_SIZE 128
+
+/**
+ * The maximum number of block transimissions needed to send a string from a
+ * buffer with JTEST_BUF_SIZE.
+ */
+#define JTEST_STR_MAX_OUTPUT_SEGMENTS \
+ (JTEST_BUF_SIZE / JTEST_STR_MAX_OUTPUT_SIZE)
+
+/**
+ * Initialize the JTEST framework.
+ */
+#define JTEST_INIT() \
+ do \
+ { \
+ JTEST_FW.str_buffer = JTEST_FW_STR_BUFFER; \
+ } while (0)
+
+/* Debugger Action-triggering Macros */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Dispatch macro to trigger various actions in the Keil Debugger.
+ */
+#define JTEST_TRIGGER_ACTION(action_name) \
+ do \
+ { \
+ action_name(); \
+ } while (0)
+
+/**
+ * Trigger the "Test Start" action in the Keil Debugger.
+ */
+#define JTEST_ACT_TEST_START() \
+ JTEST_TRIGGER_ACTION(test_start)
+
+/**
+ * Trigger the "Test End" action in the Keil Debugger.
+ */
+#define JTEST_ACT_TEST_END() \
+ JTEST_TRIGGER_ACTION(test_end)
+
+
+/**
+ * Trigger the "Group Start" action in the Keil Debugger.
+ */
+#define JTEST_ACT_GROUP_START() \
+ JTEST_TRIGGER_ACTION(group_start)
+
+/**
+ * Trigger the "Group End" action in the Keil Debugger.
+ */
+#define JTEST_ACT_GROUP_END() \
+ JTEST_TRIGGER_ACTION(group_end)
+
+
+/**
+ * Fill the buffer named buf_name with value and dump it to the Keil debugger
+ * using action.
+ */
+#define JTEST_ACT_DUMP(action, buf_name, value) \
+ do \
+ { \
+ JTEST_CLEAR_BUFFER(buf_name); \
+ strcpy(JTEST_FW.buf_name, (value)); \
+ JTEST_TRIGGER_ACTION(action); \
+ } while (0)
+
+/**
+ * Trigger the "Exit Framework" action in the Keil Debugger.
+ */
+#define JTEST_ACT_EXIT_FW() \
+ do \
+ { \
+ JTEST_TRIGGER_ACTION(exit_fw); \
+ } while (0)
+
+
+/* Buffer Manipulation Macros */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Clear the JTEST_FW buffer with name buf_name.
+ */
+#define JTEST_CLEAR_BUFFER(buf_name) \
+ do \
+ { \
+ memset(JTEST_FW.buf_name, 0, JTEST_BUF_SIZE); \
+ } while (0)
+
+/**
+ * Clear the memory needed for the JTEST_FW's string buffer.
+ */
+#define JTEST_CLEAR_STR_BUFFER() \
+ JTEST_CLEAR_BUFFER(str_buffer)
+
+/**
+ * Clear the memory needed for the JTEST_FW's data buffer.
+ */
+#define JTEST_CLEAR_DATA_BUFFER() \
+ JTEST_CLEAR_BUFFER(data_buffer)
+
+/**
+ * Dump the given string to the Keil Debugger.
+ */
+#define JTEST_DUMP_STR(string) \
+ JTEST_ACT_DUMP(dump_str, str_buffer, string)
+
+/**
+ * Dump a formatted string to the Keil Debugger.
+ */
+#define JTEST_DUMP_STRF(format_str, ... ) \
+ do \
+ { \
+ JTEST_CLEAR_STR_BUFFER(); \
+ sprintf(JTEST_FW.str_buffer,format_str, __VA_ARGS__); \
+ jtest_dump_str_segments(); \
+ } while (0)
+
+/* Pass/Fail Macros */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Increment the number of passed tests in #JTEST_FW.
+ */
+#define JTEST_FW_INC_PASSED(amount) \
+ JTEST_PF_INC_PASSED(&JTEST_FW, amount)
+
+/**
+ * Increment the number of passed tests in #JTEST_FW.
+ */
+#define JTEST_FW_INC_FAILED(amount) \
+ JTEST_PF_INC_FAILED(&JTEST_FW, amount)
+
+/* Manipulating the Current Group */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Evaluate to the current_group_ptr in #JTEST_FW.
+ */
+#define JTEST_CURRENT_GROUP_PTR() \
+ (JTEST_FW.current_group_ptr)
+
+#define JTEST_SET_CURRENT_GROUP(group_ptr) \
+ do \
+ { \
+ JTEST_CURRENT_GROUP_PTR() = group_ptr; \
+ } while (0)
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Global Variables */
+/*--------------------------------------------------------------------------------*/
+extern char JTEST_FW_STR_BUFFER[JTEST_BUF_SIZE];
+extern volatile JTEST_FW_t JTEST_FW;
+
+/*--------------------------------------------------------------------------------*/
+/* Function Prototypes */
+/*--------------------------------------------------------------------------------*/
+void jtest_dump_str_segments(void);
+
+void test_start (void);
+void test_end (void);
+void group_start (void);
+void group_end (void);
+void dump_str (void);
+void dump_data (void);
+void exit_fw (void);
+
+
+#endif /* _JTEST_FW_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group.h
new file mode 100644
index 0000000..3b37ae4
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group.h
@@ -0,0 +1,66 @@
+#ifndef _JTEST_GROUP_H_
+#define _JTEST_GROUP_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "jtest_pf.h"
+#include "jtest_util.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Type Definitions */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * A struct which represents a group of #JTEST_TEST_t structs. This struct is
+ * used to run the group of tests, and report on their outcomes.
+ */
+typedef struct JTEST_GROUP_struct
+{
+ void (* group_fn_ptr) (void); /**< Pointer to the test group */
+ char * name_str; /**< Name of the group */
+
+ /* Extend the #JTEST_GROUP_t with Pass/Fail information.*/
+ JTEST_PF_MEMBERS;
+} JTEST_GROUP_t;
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Set the name of JTEST_GROUP_t.
+ */
+#define JTEST_GROUP_SET_NAME(group_ptr, name) \
+ JTEST_SET_STRUCT_ATTRIBUTE(group_ptr, name_str, name)
+
+#define JTEST_GROUP_SET_FN(group_ptr, fn_ptr) \
+ JTEST_SET_STRUCT_ATTRIBUTE(group_ptr, group_fn_ptr, fn_ptr)
+
+/**
+ * Increment the number of tests passed in the JTEST_GROUP_t pointed to by
+ * group_ptr.
+ */
+#define JTEST_GROUP_INC_PASSED(group_ptr, amount) \
+ JTEST_PF_INC_PASSED(group_ptr, amount)
+
+/**
+ * Increment the number of tests failed in the JTEST_GROUP_t pointed to by
+ * group_ptr.
+ */
+#define JTEST_GROUP_INC_FAILED(group_ptr, amount) \
+ JTEST_PF_INC_FAILED(group_ptr, amount)
+
+/**
+ * Reset the pass/fail information of the #JTEST_GROUP_t pointed to by
+ * group_ptr.
+ */
+#define JTEST_GROUP_RESET_PF(group_ptr) \
+ do \
+ { \
+ JTEST_PF_RESET_PASSED(group_ptr); \
+ JTEST_PF_RESET_FAILED(group_ptr); \
+ } while (0)
+
+#endif /* _JTEST_GROUP_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group_call.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group_call.h
new file mode 100644
index 0000000..d565a4c
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group_call.h
@@ -0,0 +1,126 @@
+#ifndef _JTEST_GROUP_CALL_H_
+#define _JTEST_GROUP_CALL_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "jtest_fw.h"
+#include <inttypes.h>
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Execute the test in the #JTEST_GROUP_t struct associated witht he identifier
+ * group_fn.
+ */
+#define JTEST_GROUP_RUN(group_fn) \
+ do \
+ { \
+ JTEST_DUMP_STR("Group Name:\n"); \
+ JTEST_DUMP_STR(JTEST_GROUP_STRUCT_NAME(group_fn).name_str); \
+ JTEST_GROUP_STRUCT_NAME(group_fn).group_fn_ptr(); \
+ } while (0)
+
+
+/**
+ * Update the enclosing #JTEST_GROUP_t's pass/fail information using the
+ * current #JTEST_GROUP_t's.
+ *
+ * @param group_ptr Pointer to the current #JTEST_GROUP_t.
+ * @param parent_ptr Pointer to the enclosing #JTEST_GROUP_t.
+ *
+ * @warning Only run this if the current #JTEST_GROUP_t is being called within
+ * the context of another #JTEST_GROUP_t.
+ */
+#define JTEST_GROUP_UPDATE_PARENT_GROUP_PF(group_ptr, parent_group_ptr) \
+ do \
+ { \
+ JTEST_GROUP_INC_PASSED(parent_group_ptr, \
+ (group_ptr)->passed); \
+ JTEST_GROUP_INC_FAILED(parent_group_ptr, \
+ (group_ptr)->failed); \
+ } while (0)
+
+/**
+ * Update the #JTEST_FW's pass/fail information using the current
+ * #JTEST_GROUP_t's.
+ */
+#define JTEST_GROUP_UPDATE_FW_PF(group_ptr) \
+ do \
+ { \
+ JTEST_FW_INC_PASSED((group_ptr)->passed); \
+ JTEST_FW_INC_FAILED((group_ptr)->failed); \
+ } while (0)
+
+/**
+ * Update the enclosing context with the current #JTEST_GROUP_t's pass/fail
+ * information. If this group isn't in an enclosing group, it updates the
+ * #JTEST_FW's pass/fail info by default.
+ */
+#define JTEST_GROUP_UPDATE_PARENT_GROUP_OR_FW_PF(group_ptr, \
+ parent_group_ptr) \
+ do \
+ { \
+ /* Update the pass fail counts in the parent group */ \
+ if (parent_group_ptr /* Null implies Top*/) \
+ { \
+ JTEST_GROUP_UPDATE_PARENT_GROUP_PF( \
+ group_ptr, \
+ parent_group_ptr); \
+ } else { \
+ JTEST_GROUP_UPDATE_FW_PF( \
+ group_ptr); \
+ } \
+ } while (0)
+
+/**
+ * Dump the results of running the #JTEST_GROUP_t to the Keil Debugger.
+ */
+#define JTEST_GROUP_DUMP_RESULTS(group_ptr) \
+ do \
+ { \
+ JTEST_DUMP_STRF( \
+ "Tests Run: %" PRIu32 "\n" \
+ "----------\n" \
+ " Passed: %" PRIu32 "\n" \
+ " Failed: %" PRIu32 "\n", \
+ (group_ptr)->passed + (group_ptr)->failed, \
+ (group_ptr)->passed, \
+ (group_ptr)->failed); \
+ } while (0)
+
+/**
+ * Call the #JTEST_GROUP_t associated with the identifier group_fn.
+ */
+#define JTEST_GROUP_CALL(group_fn) \
+ do \
+ { /* Save the current group from JTEST_FW_t before swapping */ \
+ /* it to this group (in order to restore it later )*/ \
+ JTEST_GROUP_t * __jtest_temp_group_ptr = \
+ JTEST_CURRENT_GROUP_PTR(); \
+ JTEST_SET_CURRENT_GROUP(&JTEST_GROUP_STRUCT_NAME(group_fn)); \
+ \
+ /* Reset this group's pass/fail count. Each group */ \
+ /* should only remember counts for its last execution. */ \
+ JTEST_GROUP_RESET_PF(JTEST_CURRENT_GROUP_PTR()); \
+ \
+ /* Run the current group */ \
+ JTEST_ACT_GROUP_START(); \
+ JTEST_GROUP_RUN(group_fn); \
+ JTEST_ACT_GROUP_END(); \
+ \
+ /* Update the pass fail counts in the parent group (or FW) */ \
+ JTEST_GROUP_UPDATE_PARENT_GROUP_OR_FW_PF( \
+ JTEST_CURRENT_GROUP_PTR(), \
+ __jtest_temp_group_ptr); \
+ \
+ JTEST_GROUP_DUMP_RESULTS(JTEST_CURRENT_GROUP_PTR()); \
+ \
+ /* Restore the previously current group */ \
+ JTEST_SET_CURRENT_GROUP(__jtest_temp_group_ptr); \
+ } while (0)
+
+#endif /* _JTEST_GROUP_CALL_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group_define.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group_define.h
new file mode 100644
index 0000000..b3a86c0
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group_define.h
@@ -0,0 +1,87 @@
+#ifndef _JTEST_GROUP_DEFINE_H_
+#define _JTEST_GROUP_DEFINE_H_
+
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "jtest_util.h"
+#include "jtest_define.h"
+#include "jtest_group.h"
+
+/* For defining macros with optional arguments */
+#include "opt_arg/opt_arg.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Prefix for all #JTEST_GROUP_t structs.
+ */
+#define JTEST_GROUP_STRUCT_NAME_PREFIX G_JTEST_GROUP_STRUCT_
+
+/**
+ * Define test template used by #JTEST_GROUP_t tests.
+ */
+#define JTEST_GROUP_FN_TEMPLATE(group_fn) \
+ void group_fn(void)
+
+#define JTEST_GROUP_FN_PROTOTYPE JTEST_GROUP_FN_TEMPLATE /**< Alias for
+ #JTEST_GROUP_FN_TEMPLATE. */
+
+/**
+ * Evaluate to the name of the #JTEST_GROUP_t struct associated with group_fn.
+ */
+#define JTEST_GROUP_STRUCT_NAME(group_fn) \
+ JTEST_STRUCT_NAME(JTEST_GROUP_STRUCT_NAME_PREFIX, group_fn)
+
+/**
+ * Define a #JTEST_GROUP_t struct based on the given group_fn.
+ */
+#define JTEST_GROUP_DEFINE_STRUCT(group_fn) \
+ JTEST_DEFINE_STRUCT(JTEST_GROUP_t, \
+ JTEST_GROUP_STRUCT_NAME(group_fn))
+
+/**
+ * Declare a #JTEST_GROUP_t struct based on the given group_fn.
+ */
+#define JTEST_GROUP_DECLARE_STRUCT(group_fn) \
+ JTEST_DECLARE_STRUCT(JTEST_GROUP_DEFINE_STRUCT(group_fn))
+
+/**
+ * Contents needed to initialize a JTEST_GROUP_t struct.
+ */
+#define JTEST_GROUP_STRUCT_INIT(group_fn) \
+ group_fn, \
+ STR_NL(group_fn), \
+ JTEST_PF_MEMBER_INIT
+
+/**
+ * Initialize the contents of a #JTEST_GROUP_t struct.
+ */
+#define JTEST_GROUP_INIT(group_fn) \
+ JTEST_GROUP_DEFINE_STRUCT(group_fn) = { \
+ JTEST_GROUP_STRUCT_INIT(group_fn) \
+ }
+
+/* Test Definition Macro */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Define a #JTEST_GROUP_t object and a test function.
+ */
+#define JTEST_DEFINE_GROUP(group_fn) \
+ JTEST_GROUP_FN_PROTOTYPE(group_fn); \
+ JTEST_GROUP_INIT(group_fn); \
+ JTEST_GROUP_FN_PROTOTYPE(group_fn) /* Notice the lacking semicolon */
+
+/**
+ * Declare a #JTEST_GROUP_t object and a test function prototype.
+ */
+#define JTEST_DECLARE_GROUP(group_fn) \
+ JTEST_GROUP_FN_PROTOTYPE(group_fn); \
+ JTEST_GROUP_DECLARE_STRUCT(group_fn) /* Note the lacking semicolon */
+
+#endif /* _JTEST_GROUP_DEFINE_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_pf.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_pf.h
new file mode 100644
index 0000000..2b005b6
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_pf.h
@@ -0,0 +1,85 @@
+#ifndef _JTEST_PF_H_
+#define _JTEST_PF_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Purpose */
+/*--------------------------------------------------------------------------------*/
+/* jtest_pf.h Contains macros useful for capturing pass/fail data. */
+
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Members that can be added to other structs to extend them pass/fail data and
+ * corresponding functionality.
+ */
+#define JTEST_PF_MEMBERS \
+ uint32_t passed; \
+ uint32_t failed /* Note the lacking semicolon*/ \
+
+/**
+ * Used for initializing JTEST_PF_MEMBERS in a struct declaration.
+ */
+#define JTEST_PF_MEMBER_INIT \
+ 0, \
+ 0
+
+/* Member-Incrementing Macros */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Dispatch macro for incrementing #JTEST_PF_MEMBERS.
+ *
+ * @param xxx Values: 'passed', 'failed'
+ */
+#define JTEST_PF_INC_XXX(xxx, struct_pf_ptr, amount) \
+ do \
+ { \
+ ((struct_pf_ptr)->xxx) += (amount); \
+ } while (0)
+
+/**
+ * Specialization of the #JTEST_PF_INC_XXX macro to increment the passed
+ * member.
+ */
+#define JTEST_PF_INC_PASSED(struct_pf_ptr, amount) \
+ JTEST_PF_INC_XXX(passed, struct_pf_ptr, amount)
+
+
+/**
+ * Specialization of the #JTEST_PF_INC_XXX macro to increment the failed
+ * member.
+ */
+#define JTEST_PF_INC_FAILED(struct_pf_ptr, amount) \
+ JTEST_PF_INC_XXX(failed, struct_pf_ptr, amount)
+
+
+/* Member-Resetting Macros */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Dispatch macro for setting #JTEST_PF_MEMBERS to zero.
+ *
+ * @param xxx Values: 'passed', 'failed'
+ */
+#define JTEST_PF_RESET_XXX(xxx, struct_pf_ptr) \
+ do \
+ { \
+ ((struct_pf_ptr)->xxx) = UINT32_C(0); \
+ } while (0)
+
+/**
+ * Specialization of #JTEST_PF_RESET_XXX for the 'passed' member.
+ */
+#define JTEST_PF_RESET_PASSED(struct_pf_ptr) \
+ JTEST_PF_RESET_XXX(passed, struct_pf_ptr)
+
+/**
+ * Specialization of #JTEST_PF_RESET_XXX for the 'failed' member.
+ */
+#define JTEST_PF_RESET_FAILED(struct_pf_ptr) \
+ JTEST_PF_RESET_XXX(failed, struct_pf_ptr)
+
+#endif /* _JTEST_PF_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_systick.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_systick.h
new file mode 100644
index 0000000..339ecf2
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_systick.h
@@ -0,0 +1,93 @@
+#ifndef _JTEST_SYSTICK_H_
+#define _JTEST_SYSTICK_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+/* Get access to the SysTick structure. */
+#if defined ARMCM0
+ #include "ARMCM0.h"
+#elif defined ARMCM0P
+ #include "ARMCM0plus.h"
+#elif defined ARMCM3
+ #include "ARMCM3.h"
+#elif defined ARMCM4
+ #include "ARMCM4.h"
+#elif defined ARMCM4_FP
+ #include "ARMCM4_FP.h"
+#elif defined ARMCM7
+ #include "ARMCM7.h"
+#elif defined ARMCM7_SP
+ #include "ARMCM7_SP.h"
+#elif defined ARMCM7_DP
+ #include "ARMCM7_DP.h"
+#elif defined ARMSC000
+ #include "ARMSC000.h"
+#elif defined ARMSC300
+ #include "ARMSC300.h"
+#elif defined ARMv8MBL
+ #include "ARMv8MBL.h"
+#elif defined ARMv8MML
+ #include "ARMv8MML.h"
+#elif defined ARMv8MML_DSP
+ #include "ARMv8MML_DSP.h"
+#elif defined ARMv8MML_SP
+ #include "ARMv8MML_SP.h"
+#elif defined ARMv8MML_DSP_SP
+ #include "ARMv8MML_DSP_SP.h"
+#elif defined ARMv8MML_DP
+ #include "ARMv8MML_DP.h"
+#elif defined ARMv8MML_DSP_DP
+ #include "ARMv8MML_DSP_DP.h"
+
+#else
+ #warning "no appropriate header file found!"
+#endif
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Initial value for the SysTick module.
+ *
+ * @note This is also the maximum value, important as SysTick is a decrementing
+ * counter.
+ */
+#define JTEST_SYSTICK_INITIAL_VALUE 0xFFFFFF
+
+/**
+ * Reset the SysTick, decrementing timer to it's maximum value and disable it.
+ *
+ * This macro should leave the SysTick timer in a state that's ready for cycle
+ * counting.
+ */
+#define JTEST_SYSTICK_RESET(systick_ptr) \
+ do \
+ { \
+ (systick_ptr)->LOAD = JTEST_SYSTICK_INITIAL_VALUE; \
+ (systick_ptr)->VAL = 1; \
+ \
+ /* Disable the SysTick module. */ \
+ (systick_ptr)->CTRL = UINT32_C(0x000000); \
+ } while (0)
+
+/**
+ * Start the SysTick timer, sourced by the processor clock.
+ */
+#define JTEST_SYSTICK_START(systick_ptr) \
+ do \
+ { \
+ (systick_ptr)->CTRL = \
+ SysTick_CTRL_ENABLE_Msk | \
+ SysTick_CTRL_CLKSOURCE_Msk; /* Internal clk*/ \
+ } while (0)
+
+/**
+ * Evaluate to the current value of the SysTick timer.
+ */
+#define JTEST_SYSTICK_VALUE(systick_ptr) \
+ ((systick_ptr)->VAL)
+
+#endif /* _JTEST_SYSTICK_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test.h
new file mode 100644
index 0000000..023145f
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test.h
@@ -0,0 +1,100 @@
+#ifndef _JTEST_TEST_H_
+#define _JTEST_TEST_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include <stdint.h>
+#include "jtest_util.h"
+#include "jtest_test_ret.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Type Definitions */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * A struct which represents a Test in the JTEST framework. This struct is
+ * used to enable, run, and describe the test it represents.
+ */
+typedef struct JTEST_TEST_struct
+{
+ JTEST_TEST_RET_t ( * test_fn_ptr)(void); /**< Pointer to the test function. */
+ char * test_fn_str; /**< Name of the test function */
+ char * fut_str; /**< Name of the function under test. */
+
+ /**
+ * Flags that govern how the #JTEST_TEST_t behaves.
+ */
+ union {
+ struct {
+ unsigned enabled : 1;
+ unsigned unused : 7;
+ } bits;
+ uint8_t byte; /* Access all flags at once. */
+ } flags;
+
+} JTEST_TEST_t;
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Assign a test function to the #JTEST_TEST_t struct.
+ */
+#define JTEST_TEST_SET_FN(jtest_test_ptr, fn_ptr) \
+ JTEST_SET_STRUCT_ATTRIBUTE(jtest_test_ptr, test_fn_ptr, fn_ptr)
+
+/**
+ * Specify a function under test (FUT) for the #JTEST_TEST_t struct.
+ */
+#define JTEST_TEST_SET_FUT(jtest_test_ptr, str) \
+ JTEST_SET_STRUCT_ATTRIBUTE(jtest_test_ptr, fut_str, str)
+
+/* Macros concerning JTEST_TEST_t flags */
+/*--------------------------------------------------------------------------------*/
+
+#define JTEST_TEST_FLAG_SET 1 /**< Value of a set #JTEST_TEST_t flag. */
+#define JTEST_TEST_FLAG_CLR 0 /**< Value of a cleared #JTEST_TEST_t flag. */
+
+/**
+ * Evaluate to the flag in #JTEST_TEST_t having flag_name.
+ */
+#define JTEST_TEST_FLAG(jtest_test_ptr, flag_name) \
+ ((jtest_test_ptr)->flags.bits.flag_name)
+
+/**
+ * Dispatch macro for setting and clearing #JTEST_TEST_t flags.
+ *
+ * @param jtest_test_ptr Pointer to a #JTEST_TEST_t struct.
+ * @param flag_name Name of the flag to set in #JTEST_TEST_t.flags.bits
+ * @param xxx Vaid values: "SET" or "CLR"
+ *
+ * @note This function depends on JTEST_TEST_FLAG_SET and JTEST_TEST_FLAG_CLR.
+ */
+#define JTEST_TEST_XXX_FLAG(jtest_test_ptr, flag_name, xxx) \
+ do \
+ { \
+ JTEST_TEST_FLAG(jtest_test_ptr, flag_name) = JTEST_TEST_FLAG_##xxx ; \
+ } while (0)
+
+/**
+ * Specification of #JTEST_TEST_XXX_FLAG to set #JTEST_TEST_t flags.
+ */
+#define JTEST_TEST_SET_FLAG(jtest_test_ptr, flag_name) \
+ JTEST_TEST_XXX_FLAG(jtest_test_ptr, flag_name, SET)
+
+/**
+ * Specification of #JTEST_TEST_XXX_FLAG to clear #JTEST_TEST_t flags.
+ */
+#define JTEST_TEST_CLR_FLAG(jtest_test_ptr, flag_name) \
+ JTEST_TEST_XXX_FLAG(jtest_test_ptr, flag_name, CLR)
+
+/**
+ * Evaluate to true if the #JTEST_TEST_t is enabled.
+ */
+#define JTEST_TEST_IS_ENABLED(jtest_test_ptr) \
+ (JTEST_TEST_FLAG(jtest_test_ptr, enabled) == JTEST_TEST_FLAG_SET)
+
+#endif /* _JTEST_TEST_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_call.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_call.h
new file mode 100644
index 0000000..9325185
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_call.h
@@ -0,0 +1,121 @@
+#ifndef _JTEST_TEST_CALL_H_
+#define _JTEST_TEST_CALL_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+#include "jtest_test.h"
+#include "jtest_test_define.h"
+#include "jtest_fw.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Exectute the test in the #JTEST_TEST_t struct associated with the identifier
+ * test_fn and store the result in retval.
+ */
+#define JTEST_TEST_RUN(retval, test_fn) \
+ do \
+ { \
+ JTEST_DUMP_STR("Test Name:\n"); \
+ JTEST_DUMP_STR(JTEST_TEST_STRUCT_NAME(test_fn).test_fn_str); \
+ JTEST_DUMP_STR("Function Under Test:\n"); \
+ JTEST_DUMP_STR(JTEST_TEST_STRUCT_NAME(test_fn).fut_str); \
+ retval = JTEST_TEST_STRUCT_NAME(test_fn).test_fn_ptr(); \
+ } while (0)
+
+/**
+ * Update the enclosing #JTEST_GROUP_t's pass/fail information based on
+ * test_retval.
+ *
+ * @param test_retval A #JTEST_TEST_RET_enum for the current test.
+ *
+ * @warning Only use if #JTEST_TEST_t is called in the context of a
+ * #JTEST_GROUP_t.
+ */
+#define JTEST_TEST_UPDATE_PARENT_GROUP_PF(test_retval) \
+ do \
+ { \
+ /* Update enclosing JTEST_GROUP_t with pass/fail info */ \
+ if (test_retval == JTEST_TEST_PASSED) \
+ { \
+ JTEST_GROUP_INC_PASSED(JTEST_CURRENT_GROUP_PTR(), 1); \
+ } else { \
+ JTEST_GROUP_INC_FAILED(JTEST_CURRENT_GROUP_PTR(), 1); \
+ } \
+ } while (0)
+
+/**
+ * Update the #JTEST_FW with pass/fail information based on test_retval.
+ *
+ * @param test_retval A #JTEST_TEST_RET_enum for the current test.
+ */
+#define JTEST_TEST_UPDATE_FW_PF(test_retval) \
+ do \
+ { \
+ /* Update the JTEST_FW with pass/fail info */ \
+ if (test_retval == JTEST_TEST_PASSED) \
+ { \
+ JTEST_FW_INC_PASSED( 1); \
+ } else { \
+ JTEST_FW_INC_FAILED(1); \
+ } \
+ } while (0)
+
+/**
+ * Update the enclosing JTEST_GROUP_t's pass/fail information, or the
+ * #JTEST_FW's if this test has no enclosing #JTEST_GROUP_t.
+ *
+ * @param test_retval A #JTEST_TEST_RET_enum for the current test.
+ */
+#define JTEST_TEST_UPDATE_PARENT_GROUP_OR_FW_PF(test_retval) \
+ do \
+ { \
+ /* Update pass-fail information */ \
+ if (JTEST_CURRENT_GROUP_PTR() /* Non-null */) \
+ { \
+ JTEST_TEST_UPDATE_PARENT_GROUP_PF(test_retval); \
+ } else { \
+ JTEST_TEST_UPDATE_FW_PF(test_retval); \
+ } \
+ } while (0)
+
+/**
+ * Dump the results of the test to the Keil Debugger.
+ */
+#define JTEST_TEST_DUMP_RESULTS(test_retval) \
+ do \
+ { \
+ if (test_retval == JTEST_TEST_PASSED) \
+ { \
+ JTEST_DUMP_STR("Test Passed\n"); \
+ } else { \
+ JTEST_DUMP_STR("Test Failed\n"); \
+ } \
+ } while (0)
+
+/**
+ * Call the #JTEST_TEST_t assocaited with the identifier test_fn.
+ */
+#define JTEST_TEST_CALL(test_fn) \
+ do \
+ { \
+ if (JTEST_TEST_IS_ENABLED(&JTEST_TEST_STRUCT_NAME(test_fn))) \
+ { \
+ /* Default to failure */ \
+ JTEST_TEST_RET_t __jtest_test_ret = JTEST_TEST_FAILED; \
+ \
+ JTEST_ACT_TEST_START(); \
+ JTEST_TEST_RUN(__jtest_test_ret, test_fn); \
+ \
+ /* Update pass-fail information */ \
+ JTEST_TEST_UPDATE_PARENT_GROUP_OR_FW_PF(__jtest_test_ret); \
+ \
+ JTEST_TEST_DUMP_RESULTS(__jtest_test_ret); \
+ JTEST_ACT_TEST_END(); \
+ } \
+ } while (0)
+
+#endif /* _JTEST_TEST_CALL_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_define.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_define.h
new file mode 100644
index 0000000..1447dd0
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_define.h
@@ -0,0 +1,133 @@
+#ifndef _JTEST_TEST_DEFINE_H_
+#define _JTEST_TEST_DEFINE_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "jtest_util.h"
+#include "jtest_define.h"
+#include "jtest_test.h"
+
+/* For defining macros with optional arguments */
+#include "opt_arg/opt_arg.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Prefix for all #JTEST_TEST_t structs.
+ */
+#define JTEST_TEST_STRUCT_NAME_PREFIX G_JTEST_TEST_STRUCT_
+
+/**
+ * Define test template used by #JTEST_TEST_t tests.
+ */
+#define JTEST_TEST_FN_TEMPLATE(test_fn) \
+ JTEST_TEST_RET_t test_fn(void)
+
+#define JTEST_TEST_FN_PROTOTYPE JTEST_TEST_FN_TEMPLATE /**< Alias for
+ * #JTEST_TEST_FN_TEMPLATE. */
+
+/**
+ * Evaluate to the name of the #JTEST_TEST_t struct associated with test_fn.
+ */
+#define JTEST_TEST_STRUCT_NAME(test_fn) \
+ JTEST_STRUCT_NAME(JTEST_TEST_STRUCT_NAME_PREFIX, test_fn)
+
+/**
+ * Define a #JTEST_TEST_t struct based on the given test_fn.
+ */
+#define JTEST_TEST_DEFINE_STRUCT(test_fn) \
+ JTEST_DEFINE_STRUCT(JTEST_TEST_t, \
+ JTEST_TEST_STRUCT_NAME(test_fn))
+
+/**
+ * Declare a #JTEST_TEST_t struct based on the given test_fn.
+ */
+#define JTEST_TEST_DECLARE_STRUCT(test_fn) \
+ JTEST_DECLARE_STRUCT(JTEST_TEST_DEFINE_STRUCT(test_fn))
+
+/**
+ * Contents needed to initialize a JTEST_TEST_t struct.
+ */
+#define JTEST_TEST_STRUCT_INIT(test_fn, fut, enable) \
+ test_fn, \
+ STR_NL(test_fn), \
+ STR_NL(fut), \
+ { \
+ { \
+ enable, \
+ 0 \
+ } \
+ } \
+
+
+/**
+ * Initialize the contents of a #JTEST_TEST_t struct.
+ */
+#define JTEST_TEST_INIT(test_fn, fut, enable) \
+ JTEST_TEST_DEFINE_STRUCT(test_fn) = { \
+ JTEST_TEST_STRUCT_INIT(test_fn, fut, enable) \
+ }
+
+/* Test Definition Macro */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Define a #JTEST_TEST_t object and a test function.
+ */
+#define _JTEST_DEFINE_TEST(test_fn, fut, enable) \
+ JTEST_TEST_FN_PROTOTYPE(test_fn); \
+ JTEST_TEST_INIT(test_fn, fut, enable); \
+ JTEST_TEST_FN_PROTOTYPE(test_fn) /* Notice the lacking semicolon */
+
+/**
+ * Declare a #JTEST_TEST_t object and a test function prototype.
+ */
+#define JTEST_DECLARE_TEST(test_fn) \
+ JTEST_TEST_FN_PROTOTYPE(test_fn); \
+ JTEST_TEST_DECLARE_STRUCT(test_fn) /* Note the lacking semicolon */
+
+/*--------------------------------------------------------------------------------*/
+/* Macros with optional arguments */
+/*--------------------------------------------------------------------------------*/
+
+/* Top-level Interface */
+#define JTEST_DEFINE_TEST(...) \
+ JTEST_DEFINE_TEST_(PP_NARG(__VA_ARGS__), ##__VA_ARGS__)
+
+/* Dispatch Macro*/
+#define JTEST_DEFINE_TEST_(N, ...) \
+ SPLICE(JTEST_DEFINE_TEST_, N)(__VA_ARGS__)
+
+/* Default Arguments */
+#define JTEST_DEFINE_TEST_DEFAULT_FUT /* Blank */
+#define JTEST_DEFINE_TEST_DEFAULT_ENABLE \
+ JTEST_TRUE /* Tests enabled by
+ * default. */
+
+/* Dispatch Cases*/
+#define JTEST_DEFINE_TEST_1(_1) \
+ _JTEST_DEFINE_TEST( \
+ _1, \
+ JTEST_DEFINE_TEST_DEFAULT_FUT, \
+ JTEST_DEFINE_TEST_DEFAULT_ENABLE \
+ )
+
+#define JTEST_DEFINE_TEST_2(_1, _2) \
+ _JTEST_DEFINE_TEST( \
+ _1, \
+ _2, \
+ JTEST_DEFINE_TEST_DEFAULT_ENABLE \
+ )
+
+#define JTEST_DEFINE_TEST_3(_1, _2, _3) \
+ _JTEST_DEFINE_TEST( \
+ _1, \
+ _2, \
+ _3 \
+ )
+
+#endif /* _JTEST_TEST_DEFINE_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_ret.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_ret.h
new file mode 100644
index 0000000..c3176e5
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_ret.h
@@ -0,0 +1,17 @@
+#ifndef _JTEST_TEST_RET_H_
+#define _JTEST_TEST_RET_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Type Definitions */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Values a #JTEST_TEST_t can return.
+ */
+typedef enum JTEST_TEST_RET_enum
+{
+ JTEST_TEST_PASSED,
+ JTEST_TEST_FAILED
+} JTEST_TEST_RET_t;
+
+#endif /* _JTEST_TEST_RET_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_util.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_util.h
new file mode 100644
index 0000000..3e07d2e
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_util.h
@@ -0,0 +1,27 @@
+#ifndef _JTEST_UTIL_H_
+#define _JTEST_UTIL_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "util/util.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/* Define boolean values for the framework. */
+#define JTEST_TRUE 1 /**< Value used for TRUE in JTEST. */
+#define JTEST_FALSE 0 /**< Value used for FALSE in JTEST. */
+
+/**
+ * Set the value of the attribute in the struct to by struct_ptr to value.
+ */
+#define JTEST_SET_STRUCT_ATTRIBUTE(struct_ptr, attribute, value) \
+ do \
+ { \
+ (struct_ptr)->attribute = (value); \
+ } while (0)
+
+#endif /* _JTEST_UTIL_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/opt_arg.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/opt_arg.h
new file mode 100644
index 0000000..683be1d
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/opt_arg.h
@@ -0,0 +1,15 @@
+#ifndef _OPT_ARG_H_
+#define _OPT_ARG_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "pp_narg.h"
+#include "splice.h"
+
+/* If you are Joseph Jaoudi, you have a snippet which expands into an
+ example. If you are not Joseph, but possess his code, study the examples. If
+ you have no examples, turn back contact Joseph. */
+
+#endif /* _OPT_ARG_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/pp_narg.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/pp_narg.h
new file mode 100644
index 0000000..d3248f4
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/pp_narg.h
@@ -0,0 +1,25 @@
+#ifndef _PP_NARG_H_
+#define _PP_NARG_H_
+
+#define PP_NARG(...) \
+ PP_NARG_(__VA_ARGS__,PP_RSEQ_N())
+#define PP_NARG_(...) \
+ PP_ARG_N(__VA_ARGS__)
+#define PP_ARG_N( \
+ _1, _2, _3, _4, _5, _6, _7, _8, _9,_10, \
+ _11,_12,_13,_14,_15,_16,_17,_18,_19,_20, \
+ _21,_22,_23,_24,_25,_26,_27,_28,_29,_30, \
+ _31,_32,_33,_34,_35,_36,_37,_38,_39,_40, \
+ _41,_42,_43,_44,_45,_46,_47,_48,_49,_50, \
+ _51,_52,_53,_54,_55,_56,_57,_58,_59,_60, \
+ _61,_62,_63,N,...) N
+#define PP_RSEQ_N() \
+ 63,62,61,60, \
+ 59,58,57,56,55,54,53,52,51,50, \
+ 49,48,47,46,45,44,43,42,41,40, \
+ 39,38,37,36,35,34,33,32,31,30, \
+ 29,28,27,26,25,24,23,22,21,20, \
+ 19,18,17,16,15,14,13,12,11,10, \
+ 9,8,7,6,5,4,3,2,1,0
+
+#endif /* _PP_NARG_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/splice.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/splice.h
new file mode 100644
index 0000000..ec9142b
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/splice.h
@@ -0,0 +1,8 @@
+#ifndef _SPLICE_H_
+#define _SPLICE_H_
+
+#define SPLICE(a,b) SPLICE_1(a,b)
+#define SPLICE_1(a,b) SPLICE_2(a,b)
+#define SPLICE_2(a,b) a##b
+
+#endif /* _SPLICE_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/util/util.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/util/util.h
new file mode 100644
index 0000000..91f7df1
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/util/util.h
@@ -0,0 +1,52 @@
+#ifndef _UTIL_H_
+#define _UTIL_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Convert a symbol to a string and add a 'NewLine'.
+ */
+#define STR_NL(x) STR1_NL(x)
+#define STR1_NL(x) (STR2_NL(x)"\n")
+#define STR2_NL(x) #x
+
+/**
+ * Convert a symbol to a string.
+ */
+#define STR(x) STR1(x)
+#define STR1(x) STR2(x)
+#define STR2(x) #x
+
+/**
+ * Concatenate two symbols.
+ */
+#define CONCAT(a, b) CONCAT1(a, b)
+#define CONCAT1(a, b) CONCAT2(a, b)
+#define CONCAT2(a, b) a##b
+
+
+/**
+ * Place curly braces around a varaible number of macro arguments.
+ */
+#define CURLY(...) {__VA_ARGS__}
+
+/**
+ * Place parenthesis around a variable number of macro arguments.
+ */
+#define PAREN(...) (__VA_ARGS__)
+#if 0
+/* Standard min/max macros. */
+#define MIN(x,y) (((x) < (y)) ? (x) : (y) )
+#define MAX(x,y) (((x) > (y)) ? (x) : (y) )
+
+/**
+ * Bound value using low and high limits.
+ *
+ * Evaluate to a number in the range, endpoint inclusive.
+ */
+#define BOUND(low, high, value) \
+ MAX(MIN(high, value), low)
+#endif
+#endif /* _UTIL_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_cycle.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_cycle.c
new file mode 100644
index 0000000..24d552d
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_cycle.c
@@ -0,0 +1,9 @@
+#include "../inc/jtest_cycle.h"
+#include <inttypes.h>
+
+/*--------------------------------------------------------------------------------*/
+/* Define Module Variables */
+/*--------------------------------------------------------------------------------*/
+
+/* const char * JTEST_CYCLE_STRF = "Running: %s\nCycles: %" PRIu32 "\n"; */
+const char * JTEST_CYCLE_STRF = "Cycles: %" PRIu32 "\n"; /* function name + parameter string skipped */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_dump_str_segments.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_dump_str_segments.c
new file mode 100644
index 0000000..c3a9bf8
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_dump_str_segments.c
@@ -0,0 +1,36 @@
+#include "jtest_fw.h"
+
+/**
+ * Dump the JTEST_FW.str_buffer the Keil framework in pieces.
+ *
+ * The JTEST_FW.str_buffer contains more characters than the Keil framework can
+ * dump at once. This function dumps them in blocks.
+ */
+void jtest_dump_str_segments(void)
+{
+ uint32_t seg_idx = 0;
+ uint32_t memmove_idx = 0;
+ uint32_t seg_cnt =
+ (strlen(JTEST_FW.str_buffer) / JTEST_STR_MAX_OUTPUT_SIZE) + 1;
+
+ for( seg_idx = 0; seg_idx < seg_cnt; ++seg_idx)
+ {
+ JTEST_TRIGGER_ACTION(dump_str);
+
+ if (seg_idx < JTEST_STR_MAX_OUTPUT_SEGMENTS)
+ {
+ memmove_idx = 0;
+ while (memmove_idx < (seg_cnt - seg_idx -1) )
+ {
+ memmove(
+ JTEST_FW.str_buffer+
+ (memmove_idx* JTEST_STR_MAX_OUTPUT_SIZE),
+ JTEST_FW.str_buffer+
+ ((memmove_idx+1)*JTEST_STR_MAX_OUTPUT_SIZE),
+ JTEST_BUF_SIZE);
+ ++memmove_idx;
+ }
+ }
+ }
+ return;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_fw.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_fw.c
new file mode 100644
index 0000000..69d7a63
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_fw.c
@@ -0,0 +1,9 @@
+#include "../inc/jtest.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Define Global Variables */
+/*--------------------------------------------------------------------------------*/
+
+char JTEST_FW_STR_BUFFER[JTEST_BUF_SIZE] = {0};
+
+volatile JTEST_FW_t JTEST_FW = {0};
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_trigger_action.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_trigger_action.c
new file mode 100644
index 0000000..a3901da
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_trigger_action.c
@@ -0,0 +1,37 @@
+
+#include "jtest_fw.h"
+
+void test_start (void) {
+// ;
+ JTEST_FW.test_start++;
+}
+
+void test_end (void) {
+// ;
+ JTEST_FW.test_end++;
+}
+
+void group_start (void) {
+// ;
+ JTEST_FW.group_start++;
+}
+
+void group_end (void) {
+// ;
+ JTEST_FW.group_end++;
+}
+
+void dump_str (void) {
+// ;
+ JTEST_FW.dump_str++;
+}
+
+void dump_data (void) {
+// ;
+ JTEST_FW.dump_data++;
+}
+
+void exit_fw (void) {
+// ;
+ JTEST_FW.exit_fw++;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/all_tests.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/all_tests.h
new file mode 100644
index 0000000..df1e998
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/all_tests.h
@@ -0,0 +1,9 @@
+#ifndef _ALL_TESTS_H_
+#define _ALL_TESTS_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Test Groups */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(all_tests);
+
+#endif /* _ALL_TESTS_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_templates.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_templates.h
new file mode 100644
index 0000000..958ef78
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_templates.h
@@ -0,0 +1,267 @@
+#ifndef _BASIC_MATH_TEMPLATES_H_
+#define _BASIC_MATH_TEMPLATES_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+#include "test_templates.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Group Specific Templates */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Compare the outputs used by basic math tests for the function under test and
+ * the reference function.
+ */
+#define BASIC_MATH_COMPARE_INTERFACE(block_size, output_type) \
+ TEST_ASSERT_BUFFERS_EQUAL( \
+ basic_math_output_ref.data_ptr, \
+ basic_math_output_fut.data_ptr, \
+ block_size * sizeof(output_type))
+
+/*
+ * Comparison SNR thresholds for the data types used in basic_math_tests.
+ */
+#define BASIC_MATH_SNR_THRESHOLD_float32_t 120
+#define BASIC_MATH_SNR_THRESHOLD_q31_t 100
+#define BASIC_MATH_SNR_THRESHOLD_q15_t 75
+#define BASIC_MATH_SNR_THRESHOLD_q7_t 25
+
+/**
+ * Compare reference and fut outputs using SNR.
+ *
+ * @note The outputs are converted to float32_t before comparison.
+ */
+#define BASIC_MATH_SNR_COMPARE_INTERFACE(block_size, output_type) \
+ do \
+ { \
+ TEST_CONVERT_AND_ASSERT_SNR( \
+ basic_math_output_f32_ref, \
+ basic_math_output_ref.data_ptr, \
+ basic_math_output_f32_fut, \
+ basic_math_output_fut.data_ptr, \
+ block_size, \
+ output_type, \
+ BASIC_MATH_SNR_THRESHOLD_##output_type \
+ ); \
+ } while (0)
+
+
+/**
+ * Compare reference and fut outputs using SNR.
+ *
+ * @note The outputs are converted to float32_t before comparison.
+ */
+#define BASIC_MATH_SNR_ELT1_COMPARE_INTERFACE(block_size, output_type) \
+ do \
+ { \
+ TEST_CONVERT_AND_ASSERT_SNR( \
+ basic_math_output_f32_ref, \
+ basic_math_output_ref.data_ptr, \
+ basic_math_output_f32_fut, \
+ basic_math_output_fut.data_ptr, \
+ 1, \
+ output_type, \
+ BASIC_MATH_SNR_THRESHOLD_##output_type \
+ ); \
+ } while (0)
+
+
+
+/*--------------------------------------------------------------------------------*/
+/* Input Interfaces */
+/*--------------------------------------------------------------------------------*/
+/*
+ * General:
+ * Input interfaces provide inputs to functions inside test templates. They
+ * ONLY provide the inputs. The output variables should be hard coded.
+ *
+ * The input interfaces must have the following format:
+ *
+ * ARM_xxx_INPUT_INTERFACE() or
+ * REF_xxx_INPUT_INTERFACE()
+ *
+ * The xxx must be lowercase, and is intended to be the indentifying substring
+ * in the function's name. Acceptable values are 'sub' or 'add' from the
+ * functions arm_add_q31.
+ */
+
+#define ARM_abs_INPUT_INTERFACE(input, block_size) \
+ PAREN(input, basic_math_output_fut.data_ptr, block_size)
+
+#define REF_abs_INPUT_INTERFACE(input, block_size) \
+ PAREN(input, basic_math_output_ref.data_ptr, block_size)
+
+#define ARM_add_INPUT_INTERFACE(input_a, input_b, block_size) \
+ PAREN(input_a, input_b, basic_math_output_fut.data_ptr, block_size) \
+
+#define REF_add_INPUT_INTERFACE(input_a, input_b, block_size) \
+ PAREN(input_a, input_b, basic_math_output_ref.data_ptr, block_size) \
+
+#define ARM_dot_prod_INPUT_INTERFACE(input_a, input_b, block_size) \
+ PAREN(input_a, input_b, block_size, basic_math_output_fut.data_ptr) \
+
+#define REF_dot_prod_INPUT_INTERFACE(input_a, input_b, block_size) \
+ PAREN(input_a, input_b, block_size, basic_math_output_ref.data_ptr) \
+
+#define ARM_mult_INPUT_INTERFACE(input_a, input_b, block_size) \
+ PAREN(input_a, input_b, basic_math_output_fut.data_ptr, block_size) \
+
+#define REF_mult_INPUT_INTERFACE(input_a, input_b, block_size) \
+ PAREN(input_a, input_b, basic_math_output_ref.data_ptr, block_size) \
+
+#define ARM_negate_INPUT_INTERFACE(input, block_size) \
+ PAREN(input, basic_math_output_fut.data_ptr, block_size)
+
+#define REF_negate_INPUT_INTERFACE(input, block_size) \
+ PAREN(input, basic_math_output_ref.data_ptr, block_size)
+
+#define ARM_offset_INPUT_INTERFACE(input, elt, block_size) \
+ PAREN(input, elt, basic_math_output_fut.data_ptr, block_size) \
+
+#define REF_offset_INPUT_INTERFACE(input, elt, block_size) \
+ PAREN(input, elt, basic_math_output_ref.data_ptr, block_size) \
+
+#define ARM_shift_INPUT_INTERFACE(input, elt, block_size) \
+ PAREN(input, elt, basic_math_output_fut.data_ptr, block_size) \
+
+#define REF_shift_INPUT_INTERFACE(input, elt, block_size) \
+ PAREN(input, elt, basic_math_output_ref.data_ptr, block_size) \
+
+#define ARM_scale_float_INPUT_INTERFACE(input, elt, block_size) \
+ PAREN(input, elt, basic_math_output_fut.data_ptr, block_size) \
+
+#define REF_scale_float_INPUT_INTERFACE(input, elt, block_size) \
+ PAREN(input, elt, basic_math_output_ref.data_ptr, block_size) \
+
+/* These two are for the fixed point functions */
+#define ARM_scale_INPUT_INTERFACE(input, elt1, elt2, block_size) \
+ PAREN(input, elt1, elt2, basic_math_output_fut.data_ptr, block_size) \
+
+#define REF_scale_INPUT_INTERFACE(input, elt1, elt2, block_size) \
+ PAREN(input, elt1, elt2, basic_math_output_ref.data_ptr, block_size) \
+
+#define ARM_sub_INPUT_INTERFACE(input_a, input_b, block_size) \
+ PAREN(input_a, input_b, basic_math_output_fut.data_ptr, block_size) \
+
+#define REF_sub_INPUT_INTERFACE(input_a, input_b, block_size) \
+ PAREN(input_a, input_b, basic_math_output_ref.data_ptr, block_size) \
+
+
+/*--------------------------------------------------------------------------------*/
+/* Test Templates */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Specialization of #TEST_TEMPLATE_BUF1_BLK() for basic math tests.
+ *
+ * @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
+ * REF_xxx_INPUT_INTERFACEs.
+ */
+#define BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_BLK(fn_name, \
+ suffix, \
+ input_type, \
+ output_type) \
+ JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \
+ arm_##fn_name##_##suffix) \
+ { \
+ TEST_TEMPLATE_BUF1_BLK( \
+ basic_math_f_all, \
+ basic_math_block_sizes, \
+ input_type, \
+ output_type, \
+ arm_##fn_name##_##suffix, \
+ ARM_##fn_name##_INPUT_INTERFACE, \
+ ref_##fn_name##_##suffix, \
+ REF_##fn_name##_INPUT_INTERFACE, \
+ BASIC_MATH_COMPARE_INTERFACE); \
+ }
+
+/**
+ * Specialization of #TEST_TEMPLATE_BUF2_BLK() for basic math tests.
+ *
+ * @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
+ * REF_xxx_INPUT_INTERFACEs.
+ */
+#define BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK(fn_name, \
+ suffix, \
+ input_type, \
+ output_type, \
+ comparison_interface) \
+ JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \
+ arm_##fn_name##_##suffix) \
+ { \
+ TEST_TEMPLATE_BUF2_BLK( \
+ basic_math_f_all, \
+ basic_math_f_all, \
+ basic_math_block_sizes, \
+ input_type, \
+ output_type, \
+ arm_##fn_name##_##suffix, \
+ ARM_##fn_name##_INPUT_INTERFACE, \
+ ref_##fn_name##_##suffix, \
+ REF_##fn_name##_INPUT_INTERFACE, \
+ comparison_interface); \
+ }
+
+/**
+ * Specialization of #TEST_TEMPLATE_BUF1_ELT1_BLK() for basic math tests.
+ *
+ * @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
+ * REF_xxx_INPUT_INTERFACEs.
+ */
+#define BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_ELT1_BLK(fn_name, \
+ suffix, \
+ input_type, \
+ elt_type, \
+ output_type) \
+ JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \
+ arm_##fn_name##_##suffix) \
+ { \
+ TEST_TEMPLATE_BUF1_ELT1_BLK( \
+ basic_math_f_all, \
+ basic_math_elts, \
+ basic_math_block_sizes, \
+ input_type, \
+ elt_type, \
+ output_type, \
+ arm_##fn_name##_##suffix, \
+ ARM_##fn_name##_INPUT_INTERFACE, \
+ ref_##fn_name##_##suffix, \
+ REF_##fn_name##_INPUT_INTERFACE, \
+ BASIC_MATH_COMPARE_INTERFACE); \
+ }
+
+/**
+ * Specialization of #TEST_TEMPLATE_BUF1_ELT2_BLK() for basic math tests.
+ *
+ * @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
+ * REF_xxx_INPUT_INTERFACEs.
+ */
+#define BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_ELT2_BLK(fn_name, \
+ suffix, \
+ input_type, \
+ elt1_type, \
+ elt2_type, \
+ output_type) \
+ JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \
+ arm_##fn_name##_##suffix) \
+ { \
+ TEST_TEMPLATE_BUF1_ELT2_BLK( \
+ basic_math_f_all, \
+ basic_math_elts, \
+ basic_math_elts2, \
+ basic_math_block_sizes, \
+ input_type, \
+ elt1_type, \
+ elt2_type, \
+ output_type, \
+ arm_##fn_name##_##suffix, \
+ ARM_##fn_name##_INPUT_INTERFACE, \
+ ref_##fn_name##_##suffix, \
+ REF_##fn_name##_INPUT_INTERFACE, \
+ BASIC_MATH_COMPARE_INTERFACE); \
+ }
+
+#endif /* _BASIC_MATH_TEMPLATES_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_test_data.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_test_data.h
new file mode 100644
index 0000000..2f0b239
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_test_data.h
@@ -0,0 +1,46 @@
+#ifndef ARM_BASIC_MATH_TEST_DATA_H
+#define ARM_BASIC_MATH_TEST_DATA_H
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "arr_desc.h"
+#include "arm_math.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+#define BASIC_MATH_MAX_INPUT_ELEMENTS 32
+#define BASIC_MATH_BIGGEST_INPUT_TYPE float32_t
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Variables */
+/*--------------------------------------------------------------------------------*/
+
+/* Input/Output Buffers */
+ARR_DESC_DECLARE(basic_math_output_fut);
+ARR_DESC_DECLARE(basic_math_output_ref);
+
+extern BASIC_MATH_BIGGEST_INPUT_TYPE
+basic_math_output_f32_ref[BASIC_MATH_MAX_INPUT_ELEMENTS];
+
+extern BASIC_MATH_BIGGEST_INPUT_TYPE
+basic_math_output_f32_fut[BASIC_MATH_MAX_INPUT_ELEMENTS];
+
+/* Block Sizes*/
+ARR_DESC_DECLARE(basic_math_block_sizes);
+
+/* Numbers */
+ARR_DESC_DECLARE(basic_math_elts);
+ARR_DESC_DECLARE(basic_math_elts2);
+ARR_DESC_DECLARE(basic_math_eltsf);
+
+/* Float Inputs */
+ARR_DESC_DECLARE(basic_math_zeros);
+ARR_DESC_DECLARE(basic_math_f_2);
+ARR_DESC_DECLARE(basic_math_f_15);
+ARR_DESC_DECLARE(basic_math_f_32);
+ARR_DESC_DECLARE(basic_math_f_all);
+
+#endif
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_test_group.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_test_group.h
new file mode 100644
index 0000000..ece92c7
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_test_group.h
@@ -0,0 +1,9 @@
+#ifndef _BASIC_MATH_TEST_GROUP_H_
+#define _BASIC_MATH_TEST_GROUP_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Test Groups */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(basic_math_tests);
+
+#endif /* _BASIC_MATH_TEST_GROUP_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_tests.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_tests.h
new file mode 100644
index 0000000..0550444
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_tests.h
@@ -0,0 +1,17 @@
+#ifndef _BASIC_MATH_TESTS_H_
+#define _BASIC_MATH_TESTS_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Test/Group Declarations */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(abs_tests);
+JTEST_DECLARE_GROUP(add_tests);
+JTEST_DECLARE_GROUP(dot_prod_tests);
+JTEST_DECLARE_GROUP(mult_tests);
+JTEST_DECLARE_GROUP(negate_tests);
+JTEST_DECLARE_GROUP(offset_tests);
+JTEST_DECLARE_GROUP(scale_tests);
+JTEST_DECLARE_GROUP(shift_tests);
+JTEST_DECLARE_GROUP(sub_tests);
+
+#endif /* _BASIC_MATH_TESTS_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_templates.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_templates.h
new file mode 100644
index 0000000..3b7f22f
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_templates.h
@@ -0,0 +1,222 @@
+#ifndef _COMPLEX_MATH_TEMPLATES_H_
+#define _COMPLEX_MATH_TEMPLATES_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+#include "test_templates.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Group Specific Templates */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Compare the real outputs from the function under test and the reference
+ * function.
+ */
+#define COMPLEX_MATH_COMPARE_RE_INTERFACE(block_size, output_type) \
+ TEST_ASSERT_BUFFERS_EQUAL( \
+ complex_math_output_ref_a.data_ptr, \
+ complex_math_output_fut_a.data_ptr, \
+ block_size * sizeof(output_type))
+
+/**
+ * Compare the real and imaginary outputs from the function under test and the
+ * reference function.
+ */
+#define COMPLEX_MATH_COMPARE_CMPLX_INTERFACE(block_size, output_type) \
+ do \
+ { \
+ COMPLEX_MATH_COMPARE_RE_INTERFACE(block_size * 2, output_type); \
+ } while (0)
+
+
+/*
+ * Comparison SNR thresholds for the data types used in complex_math_tests.
+ */
+#define COMPLEX_MATH_SNR_THRESHOLD_float32_t 120
+#define COMPLEX_MATH_SNR_THRESHOLD_q31_t 100
+#define COMPLEX_MATH_SNR_THRESHOLD_q15_t 75
+
+/**
+ * Compare reference and fut outputs using SNR.
+ *
+ * The output_suffix specifies which output buffers to use for the
+ * comparison. An output_suffix of 'a' expands to the following buffers:
+ *
+ * - complex_math_output_f32_ref_a
+ * - complex_math_output_f32_fut_a
+ * - complex_math_output_ref_a
+ * - complex_math_output_fut_a
+ *
+ * @note The outputs are converted to float32_t before comparison.
+ */
+#define COMPLEX_MATH_SNR_COMPARE_OUT_INTERFACE(block_size, \
+ output_type, \
+ output_suffix) \
+ do \
+ { \
+ TEST_CONVERT_AND_ASSERT_SNR( \
+ complex_math_output_f32_ref_##output_suffix, \
+ complex_math_output_ref_##output_suffix.data_ptr, \
+ complex_math_output_f32_fut_##output_suffix, \
+ complex_math_output_fut_##output_suffix.data_ptr, \
+ block_size, \
+ output_type, \
+ COMPLEX_MATH_SNR_THRESHOLD_##output_type \
+ ); \
+ } while (0)
+
+/**
+ * Specification of #COMPLEX_MATH_SNR_COMPARE_INTERFACE() for real outputs.
+ */
+#define COMPLEX_MATH_SNR_COMPARE_RE_INTERFACE(block_size, \
+ output_type) \
+ COMPLEX_MATH_SNR_COMPARE_OUT_INTERFACE(block_size, \
+ output_type, \
+ a)
+
+/**
+ * Specification of #COMPLEX_MATH_SNR_COMPARE_INTERFACE() for complex outputs.
+ */
+#define COMPLEX_MATH_SNR_COMPARE_CMPLX_INTERFACE(block_size, \
+ output_type) \
+ COMPLEX_MATH_SNR_COMPARE_OUT_INTERFACE(block_size * 2, \
+ output_type, \
+ a)
+
+/**
+ * Compare reference and fut split outputs using SNR.
+ *
+ * 'Split' refers to two separate output buffers; one for real and one for
+ * complex.
+ */
+#define COMPLEX_MATH_SNR_COMPARE_SPLIT_INTERFACE(block_size, \
+ output_type) \
+ do \
+ { \
+ COMPLEX_MATH_SNR_COMPARE_OUT_INTERFACE(block_size, \
+ output_type, \
+ a); \
+ COMPLEX_MATH_SNR_COMPARE_OUT_INTERFACE(block_size, \
+ output_type, \
+ b); \
+ } while (0)
+
+
+/*--------------------------------------------------------------------------------*/
+/* Input Interfaces */
+/*--------------------------------------------------------------------------------*/
+/*
+ * General:
+ * Input interfaces provide inputs to functions inside test templates. They
+ * ONLY provide the inputs. The output variables should be hard coded.
+ *
+ * The input interfaces must have the following format:
+ *
+ * ARM_xxx_INPUT_INTERFACE() or
+ * REF_xxx_INPUT_INTERFACE()
+ *
+ * The xxx must be lowercase, and is intended to be the indentifying substring
+ * in the function's name. Acceptable values are 'sub' or 'add' from the
+ * functions arm_add_q31.
+ */
+
+#define ARM_cmplx_conj_INPUT_INTERFACE(input, block_size) \
+ PAREN(input, complex_math_output_fut_a.data_ptr, block_size)
+
+#define REF_cmplx_conj_INPUT_INTERFACE(input, block_size) \
+ PAREN(input, complex_math_output_ref_a.data_ptr, block_size)
+
+#define ARM_cmplx_dot_prod_INPUT_INTERFACE(input_a, input_b, block_size) \
+ PAREN(input_a, input_b, block_size, \
+ complex_math_output_fut_a.data_ptr, \
+ complex_math_output_fut_b.data_ptr)
+
+#define REF_cmplx_dot_prod_INPUT_INTERFACE(input_a, input_b, block_size) \
+ PAREN(input_a, input_b, block_size, \
+ complex_math_output_ref_a.data_ptr, \
+ complex_math_output_ref_b.data_ptr)
+
+#define ARM_cmplx_mag_INPUT_INTERFACE(input, block_size) \
+ PAREN(input, complex_math_output_fut_a.data_ptr, block_size)
+
+#define REF_cmplx_mag_INPUT_INTERFACE(input, block_size) \
+ PAREN(input, complex_math_output_ref_a.data_ptr, block_size)
+
+#define ARM_cmplx_mag_squared_INPUT_INTERFACE(input, block_size) \
+ PAREN(input, complex_math_output_fut_a.data_ptr, block_size)
+
+#define REF_cmplx_mag_squared_INPUT_INTERFACE(input, block_size) \
+ PAREN(input, complex_math_output_ref_a.data_ptr, block_size)
+
+#define ARM_cmplx_mult_cmplx_INPUT_INTERFACE(input_a, input_b, block_size) \
+ PAREN(input_a, input_b, complex_math_output_fut_a.data_ptr, block_size)
+
+#define REF_cmplx_mult_cmplx_INPUT_INTERFACE(input_a, input_b, block_size) \
+ PAREN(input_a, input_b, complex_math_output_ref_a.data_ptr, block_size)
+
+#define ARM_cmplx_mult_real_INPUT_INTERFACE(input_a, input_b, block_size) \
+ PAREN(input_a, input_b, complex_math_output_fut_a.data_ptr, block_size)
+
+#define REF_cmplx_mult_real_INPUT_INTERFACE(input_a, input_b, block_size) \
+ PAREN(input_a, input_b, complex_math_output_ref_a.data_ptr, block_size)
+
+/*--------------------------------------------------------------------------------*/
+/* Test Templates */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Specialization of #TEST_TEMPLATE_BUF1_BLK() for complex math tests.
+ *
+ * @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
+ * REF_xxx_INPUT_INTERFACEs.
+ */
+#define COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF1_BLK(fn_name, \
+ suffix, \
+ input_type, \
+ output_type, \
+ comparison_interface) \
+ JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \
+ arm_##fn_name##_##suffix) \
+ { \
+ TEST_TEMPLATE_BUF1_BLK( \
+ complex_math_f_all, \
+ complex_math_block_sizes, \
+ input_type, \
+ output_type, \
+ arm_##fn_name##_##suffix, \
+ ARM_##fn_name##_INPUT_INTERFACE, \
+ ref_##fn_name##_##suffix, \
+ REF_##fn_name##_INPUT_INTERFACE, \
+ comparison_interface); \
+ }
+
+/**
+ * Specialization of #TEST_TEMPLATE_BUF2_BLK1() for complex math tests.
+ *
+ * @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
+ * REF_xxx_INPUT_INTERFACEs.
+ */
+#define COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK(fn_name, \
+ suffix, \
+ input_type, \
+ output_type, \
+ comparison_interface) \
+ JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \
+ arm_##fn_name##_##suffix) \
+ { \
+ TEST_TEMPLATE_BUF2_BLK( \
+ complex_math_f_all, \
+ complex_math_f_all, \
+ complex_math_block_sizes, \
+ input_type, \
+ output_type, \
+ arm_##fn_name##_##suffix, \
+ ARM_##fn_name##_INPUT_INTERFACE, \
+ ref_##fn_name##_##suffix, \
+ REF_##fn_name##_INPUT_INTERFACE, \
+ comparison_interface); \
+ }
+
+#endif /* _COMPLEX_MATH_TEMPLATES_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_test_data.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_test_data.h
new file mode 100644
index 0000000..df561b4
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_test_data.h
@@ -0,0 +1,50 @@
+#ifndef _COMPLEX_MATH_TEST_DATA_H_
+#define _COMPLEX_MATH_TEST_DATA_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "arr_desc.h"
+#include "arm_math.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+#define COMPLEX_MATH_MAX_INPUT_ELEMENTS 32
+#define COMPLEX_MATH_BIGGEST_INPUT_TYPE float32_t
+
+/*--------------------------------------------------------------------------------*/
+/* Decalare Variables */
+/*--------------------------------------------------------------------------------*/
+
+/* Input/Output Buffers */
+ARR_DESC_DECLARE(complex_math_output_fut_a);
+ARR_DESC_DECLARE(complex_math_output_fut_b);
+ARR_DESC_DECLARE(complex_math_output_ref_a);
+ARR_DESC_DECLARE(complex_math_output_ref_b);
+
+extern COMPLEX_MATH_BIGGEST_INPUT_TYPE
+complex_math_output_f32_ref_a[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2];
+
+extern COMPLEX_MATH_BIGGEST_INPUT_TYPE
+complex_math_output_f32_ref_b[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2];
+
+extern COMPLEX_MATH_BIGGEST_INPUT_TYPE
+complex_math_output_f32_fut_a[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2];
+
+extern COMPLEX_MATH_BIGGEST_INPUT_TYPE
+complex_math_output_f32_fut_b[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2];
+
+/* Block Sizes*/
+ARR_DESC_DECLARE(complex_math_block_sizes);
+
+/* Float Inputs */
+ARR_DESC_DECLARE(complex_math_zeros);
+ARR_DESC_DECLARE(complex_math_f_2);
+ARR_DESC_DECLARE(complex_math_f_15);
+ARR_DESC_DECLARE(complex_math_f_32);
+ARR_DESC_DECLARE(complex_math_f_all);
+
+
+#endif /* _COMPLEX_MATH_TEST_DATA_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_test_group.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_test_group.h
new file mode 100644
index 0000000..5c2ea1f
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_test_group.h
@@ -0,0 +1,9 @@
+#ifndef _COMPLEX_MATH_TEST_GROUP_H_
+#define _COMPLEX_MATH_TEST_GROUP_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Test Groups */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(complex_math_tests);
+
+#endif /* _COMPLEX_MATH_TEST_GROUP_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_tests.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_tests.h
new file mode 100644
index 0000000..ab4f0ae
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_tests.h
@@ -0,0 +1,14 @@
+#ifndef _COMPLEX_MATH_TESTS_H_
+#define _COMPLEX_MATH_TESTS_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Test/Group Declarations */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(cmplx_conj_tests);
+JTEST_DECLARE_GROUP(cmplx_dot_prod_tests);
+JTEST_DECLARE_GROUP(cmplx_mag_tests);
+JTEST_DECLARE_GROUP(cmplx_mag_squared_tests);
+JTEST_DECLARE_GROUP(cmplx_mult_cmplx_tests);
+JTEST_DECLARE_GROUP(cmplx_mult_real_tests);
+
+#endif /* _COMPLEX_MATH_TESTS_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_templates.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_templates.h
new file mode 100644
index 0000000..f7956fb
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_templates.h
@@ -0,0 +1,46 @@
+#ifndef _CONTROLLER_TEMPLATES_H_
+#define _CONTROLLER_TEMPLATES_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "test_templates.h"
+#include <string.h> /* memcpy() */
+
+/*--------------------------------------------------------------------------------*/
+/* Group Specific Templates */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Comparison SNR thresholds for the data types used in transform_tests.
+ */
+#define CONTROLLER_SNR_THRESHOLD_float32_t 110
+#define CONTROLLER_SNR_THRESHOLD_q31_t 100
+#define CONTROLLER_SNR_THRESHOLD_q15_t 45
+
+/**
+ * Compare the outputs from the function under test and the reference
+ * function using SNR.
+ */
+#define CONTROLLER_SNR_COMPARE_INTERFACE(block_size, \
+ output_type) \
+ do \
+ { \
+ TEST_CONVERT_AND_ASSERT_SNR( \
+ controller_output_f32_ref, \
+ (output_type *) controller_output_ref, \
+ controller_output_f32_fut, \
+ (output_type *) controller_output_fut, \
+ block_size, \
+ output_type, \
+ CONTROLLER_SNR_THRESHOLD_##output_type \
+ ); \
+ } while (0)
+
+
+/*--------------------------------------------------------------------------------*/
+/* TEST Templates */
+/*--------------------------------------------------------------------------------*/
+
+#endif /* _CONTROLLER_TEMPLATES_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_test_data.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_test_data.h
new file mode 100644
index 0000000..5aa63eb
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_test_data.h
@@ -0,0 +1,33 @@
+#ifndef _CONTROLLER_TEST_DATA_H_
+#define _CONTROLLER_TEST_DATA_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+#define CONTROLLER_MAX_LEN 1024
+#define CONTROLLER_MAX_COEFFS_LEN (12 * 3)
+#define TRANFORM_BIGGEST_INPUT_TYPE float32_t
+
+/*--------------------------------------------------------------------------------*/
+/* Variable Declarations */
+/*--------------------------------------------------------------------------------*/
+
+extern float32_t controller_output_fut[CONTROLLER_MAX_LEN];
+extern float32_t controller_output_ref[CONTROLLER_MAX_LEN];
+extern float32_t controller_output_f32_fut[CONTROLLER_MAX_LEN];
+extern float32_t controller_output_f32_ref[CONTROLLER_MAX_LEN];
+extern const float32_t controller_f32_inputs[CONTROLLER_MAX_LEN];
+extern const q31_t controller_q31_inputs[CONTROLLER_MAX_LEN];
+extern const q15_t * controller_q15_inputs;
+extern const float32_t controller_f32_coeffs[CONTROLLER_MAX_COEFFS_LEN];
+extern const q31_t controller_q31_coeffs[CONTROLLER_MAX_COEFFS_LEN];
+extern const q15_t controller_q15_coeffs[CONTROLLER_MAX_COEFFS_LEN];
+
+#endif /* _CONTROLLER_TEST_DATA_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_test_group.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_test_group.h
new file mode 100644
index 0000000..baead25
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_test_group.h
@@ -0,0 +1,9 @@
+#ifndef _CONTROLLER_TEST_GROUP_H_
+#define _CONTROLLER_TEST_GROUP_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Test Group */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(controller_tests);
+
+#endif /* _CONTROLLER_TEST_GROUP_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_tests.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_tests.h
new file mode 100644
index 0000000..41996a8
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_tests.h
@@ -0,0 +1,11 @@
+#ifndef _CONTROLLER_TESTS_H_
+#define _CONTROLLER_TESTS_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Test/Group Declarations */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(pid_reset_tests);
+JTEST_DECLARE_GROUP(sin_cos_tests);
+JTEST_DECLARE_GROUP(pid_tests);
+
+#endif /* _CONTROLLER_TESTS_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/fast_math_tests/fast_math_templates.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/fast_math_tests/fast_math_templates.h
new file mode 100644
index 0000000..5b49512
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/fast_math_tests/fast_math_templates.h
@@ -0,0 +1,102 @@
+#ifndef _FAST_MATH_TEMPLATES_H_
+#define _FAST_MATH_TEMPLATES_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "test_templates.h"
+#include <string.h> /* memcpy() */
+
+/*--------------------------------------------------------------------------------*/
+/* Group Specific Templates */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Comparison SNR thresholds for the data types used in transform_tests.
+ */
+#define FAST_MATH_SNR_THRESHOLD_float32_t 95
+#define FAST_MATH_SNR_THRESHOLD_q31_t 95
+#define FAST_MATH_SNR_THRESHOLD_q15_t 45
+
+/**
+ * Compare the outputs from the function under test and the reference
+ * function using SNR.
+ */
+#define FAST_MATH_SNR_COMPARE_INTERFACE(block_size, \
+ output_type) \
+ do \
+ { \
+ TEST_CONVERT_AND_ASSERT_SNR( \
+ fast_math_output_f32_ref, \
+ (output_type *) fast_math_output_ref, \
+ fast_math_output_f32_fut, \
+ (output_type *) fast_math_output_fut, \
+ block_size, \
+ output_type, \
+ FAST_MATH_SNR_THRESHOLD_##output_type \
+ ); \
+ } while (0)
+
+
+/*--------------------------------------------------------------------------------*/
+/* TEST Templates */
+/*--------------------------------------------------------------------------------*/
+
+#define SQRT_TEST_TEMPLATE_ELT1(suffix) \
+ \
+ JTEST_DEFINE_TEST(arm_sqrt_##suffix##_test, arm_sqrt_##suffix) \
+ { \
+ uint32_t i; \
+ \
+ JTEST_COUNT_CYCLES( \
+ for(i=0;i<FAST_MATH_MAX_LEN;i++) \
+ { \
+ arm_sqrt_##suffix( \
+ (suffix##_t)fast_math_##suffix##_inputs[i] \
+ ,(suffix##_t*)fast_math_output_fut + i); \
+ }); \
+ \
+ for(i=0;i<FAST_MATH_MAX_LEN;i++) \
+ { \
+ ref_sqrt_##suffix( \
+ (suffix##_t)fast_math_##suffix##_inputs[i] \
+ ,(suffix##_t*)fast_math_output_ref + i); \
+ } \
+ \
+ FAST_MATH_SNR_COMPARE_INTERFACE( \
+ FAST_MATH_MAX_LEN, \
+ suffix##_t); \
+ \
+ return JTEST_TEST_PASSED; \
+ }
+
+
+#define SIN_COS_TEST_TEMPLATE_ELT1(suffix, type, func) \
+ \
+ JTEST_DEFINE_TEST(arm_##func##_##suffix##_test, arm_##func##_##suffix) \
+ { \
+ uint32_t i; \
+ \
+ JTEST_COUNT_CYCLES( \
+ for(i=0;i<FAST_MATH_MAX_LEN;i++) \
+ { \
+ *((type*)fast_math_output_fut + i) = arm_##func##_##suffix( \
+ fast_math_##suffix##_inputs[i]); \
+ }); \
+ \
+ JTEST_COUNT_CYCLES( \
+ for(i=0;i<FAST_MATH_MAX_LEN;i++) \
+ { \
+ *((type*)fast_math_output_ref + i) = ref_##func##_##suffix( \
+ fast_math_##suffix##_inputs[i]); \
+ }); \
+ \
+ FAST_MATH_SNR_COMPARE_INTERFACE( \
+ FAST_MATH_MAX_LEN, \
+ type); \
+ \
+ return JTEST_TEST_PASSED; \
+ }
+
+#endif /* _FAST_MATH_TEMPLATES_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/fast_math_tests/fast_math_test_data.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/fast_math_tests/fast_math_test_data.h
new file mode 100644
index 0000000..0279be0
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/fast_math_tests/fast_math_test_data.h
@@ -0,0 +1,29 @@
+#ifndef _FAST_MATH_TEST_DATA_H_
+#define _FAST_MATH_TEST_DATA_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+#define FAST_MATH_MAX_LEN 1024
+#define TRANFORM_BIGGEST_INPUT_TYPE float32_t
+
+/*--------------------------------------------------------------------------------*/
+/* Variable Declarations */
+/*--------------------------------------------------------------------------------*/
+
+extern float32_t fast_math_output_fut[FAST_MATH_MAX_LEN];
+extern float32_t fast_math_output_ref[FAST_MATH_MAX_LEN];
+extern float32_t fast_math_output_f32_fut[FAST_MATH_MAX_LEN];
+extern float32_t fast_math_output_f32_ref[FAST_MATH_MAX_LEN];
+extern const float32_t fast_math_f32_inputs[FAST_MATH_MAX_LEN];
+extern const q31_t fast_math_q31_inputs[FAST_MATH_MAX_LEN];
+extern const q15_t * fast_math_q15_inputs;
+
+#endif /* _FAST_MATH_TEST_DATA_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/fast_math_tests/fast_math_test_group.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/fast_math_tests/fast_math_test_group.h
new file mode 100644
index 0000000..3282118
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/fast_math_tests/fast_math_test_group.h
@@ -0,0 +1,9 @@
+#ifndef _FAST_MATH_TEST_GROUP_H_
+#define _FAST_MATH_TEST_GROUP_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Test Groups */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(fast_math_tests);
+
+#endif /* _FAST_MATH_TEST_GROUP_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/filtering_tests/filtering_templates.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/filtering_tests/filtering_templates.h
new file mode 100644
index 0000000..f3eb564
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/filtering_tests/filtering_templates.h
@@ -0,0 +1,91 @@
+#ifndef _FILTERING_TEMPLATES_H_
+#define _FILTERING_TEMPLATES_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+#include "test_templates.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Group Specific Templates */
+/*--------------------------------------------------------------------------------*/
+
+/*
+ * Comparison SNR thresholds for the data types used in statistics_tests.
+ */
+#define FILTERING_SNR_THRESHOLD_float64_t 120
+#define FILTERING_SNR_THRESHOLD_float32_t 99
+#define FILTERING_SNR_THRESHOLD_q31_t 90
+#define FILTERING_SNR_THRESHOLD_q15_t 60
+#define FILTERING_SNR_THRESHOLD_q7_t 30
+
+/**
+ * Compare reference and fut outputs using SNR.
+ *
+ * @note The outputs are converted to float32_t before comparison.
+ */
+#define FILTERING_SNR_COMPARE_INTERFACE(block_size, \
+ output_type) \
+ FILTERING_SNR_COMPARE_INTERFACE_OFFSET(0, block_size, output_type)
+
+/**
+ * Compare reference and fut outputs starting at some offset using SNR.
+ */
+#define FILTERING_SNR_COMPARE_INTERFACE_OFFSET(offset, \
+ block_size, \
+ output_type) \
+ do \
+ { \
+ TEST_CONVERT_AND_ASSERT_SNR( \
+ filtering_output_f32_ref, \
+ (output_type *) filtering_output_ref + offset, \
+ filtering_output_f32_fut, \
+ (output_type *) filtering_output_fut + offset, \
+ block_size, \
+ output_type, \
+ FILTERING_SNR_THRESHOLD_##output_type \
+ ); \
+ } while (0)
+
+/**
+ * Compare reference and fut outputs starting at some offset using SNR.
+ * Special case for float64_t
+ */
+#define FILTERING_DBL_SNR_COMPARE_INTERFACE(block_size, \
+ output_type) \
+ do \
+ { \
+ TEST_ASSERT_DBL_SNR( \
+ (float64_t*)filtering_output_ref, \
+ (float64_t*)filtering_output_fut, \
+ block_size, \
+ FILTERING_SNR_THRESHOLD_##output_type \
+ ); \
+ } while (0)
+
+/*--------------------------------------------------------------------------------*/
+/* Input Interfaces */
+/*--------------------------------------------------------------------------------*/
+/*
+ * General:
+ * Input interfaces provide inputs to functions inside test templates. They
+ * ONLY provide the inputs. The output variables should be hard coded.
+ *
+ * The input interfaces must have the following format:
+ *
+ * ARM_xxx_INPUT_INTERFACE() or
+ * REF_xxx_INPUT_INTERFACE()
+ *
+ * The xxx must be lowercase, and is intended to be the indentifying substring
+ * in the function's name. Acceptable values are 'sub' or 'add' from the
+ * functions arm_add_q31.
+ */
+
+
+/*--------------------------------------------------------------------------------*/
+/* Test Templates */
+/*--------------------------------------------------------------------------------*/
+
+
+
+#endif /* _FILTERING_TEMPLATES_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/filtering_tests/filtering_test_data.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/filtering_tests/filtering_test_data.h
new file mode 100644
index 0000000..ee07291
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/filtering_tests/filtering_test_data.h
@@ -0,0 +1,81 @@
+#ifndef FILTERING_TEST_DATA_H
+#define FILTERING_TEST_DATA_H
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "arr_desc.h"
+#include "arm_math.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+#define FILTERING_MAX_BLOCKSIZE 33
+#define LMS_MAX_BLOCKSIZE 512
+#define FILTERING_MAX_NUMTAPS 34
+#define FILTERING_MAX_NUMSTAGES 14
+#define FILTERING_MAX_POSTSHIFT 8
+#define FILTERING_MAX_TAP_DELAY 0xFF
+#define FILTERING_MAX_L 3
+#define FILTERING_MAX_M 33
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Variables */
+/*--------------------------------------------------------------------------------*/
+
+/* Input/Output Buffers */
+extern float32_t filtering_output_fut[LMS_MAX_BLOCKSIZE*2];
+extern float32_t filtering_output_ref[LMS_MAX_BLOCKSIZE*2];
+extern float32_t filtering_output_f32_fut[LMS_MAX_BLOCKSIZE*2];
+extern float32_t filtering_output_f32_ref[LMS_MAX_BLOCKSIZE*2];
+extern float32_t filtering_input_lms[LMS_MAX_BLOCKSIZE*2];
+extern float32_t filtering_pState[LMS_MAX_BLOCKSIZE + FILTERING_MAX_NUMTAPS];
+extern float32_t filtering_scratch[FILTERING_MAX_BLOCKSIZE * 3];
+extern float32_t filtering_scratch2[FILTERING_MAX_BLOCKSIZE * 3];
+extern float32_t filtering_coeffs_lms[FILTERING_MAX_NUMTAPS];
+
+extern const float64_t filtering_f64_inputs[FILTERING_MAX_BLOCKSIZE * FILTERING_MAX_M + FILTERING_MAX_NUMTAPS];
+extern const float32_t filtering_f32_inputs[FILTERING_MAX_BLOCKSIZE * FILTERING_MAX_M + FILTERING_MAX_NUMTAPS];
+extern const q31_t filtering_q31_inputs[FILTERING_MAX_BLOCKSIZE * FILTERING_MAX_M + FILTERING_MAX_NUMTAPS];
+extern const q15_t * filtering_q15_inputs;
+extern const q7_t * filtering_q7_inputs;
+
+/* Block Sizes */
+ARR_DESC_DECLARE(filtering_blocksizes);
+ARR_DESC_DECLARE(lms_blocksizes);
+ARR_DESC_DECLARE(filtering_numtaps);
+ARR_DESC_DECLARE(filtering_numtaps2);
+ARR_DESC_DECLARE(filtering_postshifts);
+ARR_DESC_DECLARE(filtering_numstages);
+ARR_DESC_DECLARE(filtering_Ls);
+ARR_DESC_DECLARE(filtering_Ms);
+
+/* Coefficient Lists */
+extern const float64_t filtering_coeffs_f64[FILTERING_MAX_NUMSTAGES * 6 + 2];
+extern const float64_t filtering_coeffs_b_f64[FILTERING_MAX_NUMSTAGES * 6 + 2];
+extern const float32_t filtering_coeffs_f32[FILTERING_MAX_NUMSTAGES * 6 + 2];
+extern const float32_t filtering_coeffs_b_f32[FILTERING_MAX_NUMSTAGES * 6 + 2];
+extern const float32_t *filtering_coeffs_c_f32;
+extern float32_t filtering_coeffs_lms_f32[FILTERING_MAX_NUMTAPS];
+extern const q31_t filtering_coeffs_q31[FILTERING_MAX_NUMSTAGES * 6 + 2];
+extern const q31_t *filtering_coeffs_b_q31;
+extern const q31_t *filtering_coeffs_c_q31;
+extern q31_t filtering_coeffs_lms_q31[FILTERING_MAX_NUMTAPS];
+extern const q15_t filtering_coeffs_q15[FILTERING_MAX_NUMSTAGES * 6 + 4];
+extern const q15_t *filtering_coeffs_b_q15;
+extern const q15_t *filtering_coeffs_c_q15;
+extern q15_t filtering_coeffs_lms_q15[FILTERING_MAX_NUMTAPS];
+extern const q7_t filtering_coeffs_q7[FILTERING_MAX_NUMSTAGES * 6 + 8];
+extern const q7_t *filtering_coeffs_b_q7;
+extern const q7_t *filtering_coeffs_c_q7;
+
+/* Tap Delay Lists */
+extern const int32_t filtering_tap_delay[FILTERING_MAX_NUMTAPS];
+
+/* Numbers */
+
+/* Float Inputs */
+
+#endif
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/filtering_tests/filtering_test_group.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/filtering_tests/filtering_test_group.h
new file mode 100644
index 0000000..a5f6877
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/filtering_tests/filtering_test_group.h
@@ -0,0 +1,9 @@
+#ifndef _FILTERING_TEST_GROUP_H_
+#define _FILTERING_TEST_GROUP_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Test Groups */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(filtering_tests);
+
+#endif /* _FILTERING_TEST_GROUP_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/filtering_tests/filtering_tests.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/filtering_tests/filtering_tests.h
new file mode 100644
index 0000000..4caeca9
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/filtering_tests/filtering_tests.h
@@ -0,0 +1,15 @@
+#ifndef _FILTERING_TESTS_H_
+#define _FILTERING_TESTS_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Test/Group Declarations */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DECLARE_GROUP(biquad_tests);
+JTEST_DECLARE_GROUP(conv_tests);
+JTEST_DECLARE_GROUP(correlate_tests);
+JTEST_DECLARE_GROUP(fir_tests);
+JTEST_DECLARE_GROUP(iir_tests);
+JTEST_DECLARE_GROUP(lms_tests);
+
+#endif /* _FILTERING_TESTS_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/intrinsics_tests/intrinsics_templates.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/intrinsics_tests/intrinsics_templates.h
new file mode 100644
index 0000000..5872fe9
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/intrinsics_tests/intrinsics_templates.h
@@ -0,0 +1,166 @@
+#ifndef _INTRINSICS_TEMPLATES_H_
+#define _INTRINSICS_TEMPLATES_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "test_templates.h"
+#include <string.h> /* memcpy() */
+
+/*--------------------------------------------------------------------------------*/
+/* Group Specific Templates */
+/*--------------------------------------------------------------------------------*/
+
+/**
+* Comparison SNR thresholds for the data types used in transform_tests.
+*/
+#define INTRINSICS_SNR_THRESHOLD_q63_t 120
+#define INTRINSICS_SNR_THRESHOLD_q31_t 95
+
+/**
+* Compare the outputs from the function under test and the reference
+* function using SNR.
+*/
+#define INTRINSICS_SNR_COMPARE_INTERFACE(block_size, \
+ output_type) \
+ do \
+ { \
+ TEST_CONVERT_AND_ASSERT_SNR( \
+ intrinsics_output_f32_ref, \
+ (output_type##_t *) intrinsics_output_ref, \
+ intrinsics_output_f32_fut, \
+ (output_type##_t *) intrinsics_output_fut, \
+ block_size, \
+ output_type, \
+ INTRINSICS_SNR_THRESHOLD_##output_type##_t \
+ ); \
+ } while (0)
+
+
+/*--------------------------------------------------------------------------------*/
+/* TEST Templates */
+/*--------------------------------------------------------------------------------*/
+
+#define INTRINSICS_TEST_TEMPLATE_ELT1(functionName, dataType) \
+ \
+ JTEST_DEFINE_TEST(functionName##_test, functionName) \
+ { \
+ uint32_t i; \
+ \
+ JTEST_COUNT_CYCLES( \
+ for(i=0;i<INTRINSICS_MAX_LEN;i++) \
+ { \
+ *((dataType##_t*)intrinsics_output_fut + i) = \
+ functionName( \
+ (dataType##_t)intrinsics_##dataType##_inputs[i]); \
+ }); \
+ \
+ for(i=0;i<INTRINSICS_MAX_LEN;i++) \
+ { \
+ *((dataType##_t*)intrinsics_output_ref + i) = \
+ ref##functionName( \
+ (dataType##_t)intrinsics_##dataType##_inputs[i]); \
+ } \
+ \
+ INTRINSICS_SNR_COMPARE_INTERFACE( \
+ INTRINSICS_MAX_LEN, \
+ dataType); \
+ \
+ return JTEST_TEST_PASSED; \
+ }
+
+#define INTRINSICS_TEST_TEMPLATE_ELT2(functionName, dataType) \
+ \
+ JTEST_DEFINE_TEST(functionName##_test, functionName) \
+ { \
+ uint32_t i; \
+ \
+ JTEST_COUNT_CYCLES( \
+ for(i=0;i<INTRINSICS_MAX_LEN;i++) \
+ { \
+ *((dataType##_t*)intrinsics_output_fut + i) = \
+ functionName( \
+ (dataType##_t)intrinsics_##dataType##_inputs[i] \
+ ,(dataType##_t)intrinsics_##dataType##_inputs[i]); \
+ }); \
+ \
+ for(i=0;i<INTRINSICS_MAX_LEN;i++) \
+ { \
+ *((dataType##_t*)intrinsics_output_ref + i) = \
+ ref##functionName( \
+ (dataType##_t)intrinsics_##dataType##_inputs[i] \
+ ,(dataType##_t)intrinsics_##dataType##_inputs[i]); \
+ } \
+ \
+ INTRINSICS_SNR_COMPARE_INTERFACE( \
+ INTRINSICS_MAX_LEN, \
+ dataType); \
+ \
+ return JTEST_TEST_PASSED; \
+ }
+
+#define INTRINSICS_TEST_TEMPLATE_ELT3(functionName, dataType) \
+ \
+ JTEST_DEFINE_TEST(functionName##_test, functionName) \
+ { \
+ uint32_t i; \
+ \
+ JTEST_COUNT_CYCLES( \
+ for(i=0;i<INTRINSICS_MAX_LEN;i++) \
+ { \
+ *((dataType##_t*)intrinsics_output_fut + i) = \
+ functionName( \
+ (dataType##_t)intrinsics_##dataType##_inputs[i] \
+ ,(dataType##_t)intrinsics_##dataType##_inputs[i] \
+ ,(dataType##_t)intrinsics_##dataType##_inputs[i]); \
+ }); \
+ \
+ for(i=0;i<INTRINSICS_MAX_LEN;i++) \
+ { \
+ *((dataType##_t*)intrinsics_output_ref + i) = \
+ ref##functionName( \
+ (dataType##_t)intrinsics_##dataType##_inputs[i] \
+ ,(dataType##_t)intrinsics_##dataType##_inputs[i] \
+ ,(dataType##_t)intrinsics_##dataType##_inputs[i]); \
+ } \
+ \
+ INTRINSICS_SNR_COMPARE_INTERFACE( \
+ INTRINSICS_MAX_LEN, \
+ dataType); \
+ \
+ return JTEST_TEST_PASSED; \
+ }
+
+#define INTRINSICS_TEST_TEMPLATE_ELT4(functionName, dataType, dataType2) \
+ JTEST_DEFINE_TEST(functionName##_test, functionName) \
+ { \
+ uint32_t i; \
+ \
+ JTEST_COUNT_CYCLES( \
+ for(i=0;i<INTRINSICS_MAX_LEN;i++) \
+ { \
+ *((dataType2##_t*)intrinsics_output_fut + i) = \
+ functionName( \
+ (dataType##_t)intrinsics_##dataType##_inputs[i] \
+ ,(dataType##_t)intrinsics_##dataType##_inputs[i] \
+ ,(dataType2##_t)intrinsics_##dataType2##_inputs[i]); \
+ }); \
+ \
+ for(i=0;i<INTRINSICS_MAX_LEN;i++) \
+ { \
+ *((dataType2##_t*)intrinsics_output_ref + i) = \
+ ref##functionName( \
+ (dataType##_t)intrinsics_##dataType##_inputs[i] \
+ ,(dataType##_t)intrinsics_##dataType##_inputs[i] \
+ ,(dataType2##_t)intrinsics_##dataType2##_inputs[i]); \
+ } \
+ \
+ INTRINSICS_SNR_COMPARE_INTERFACE( \
+ INTRINSICS_MAX_LEN, \
+ dataType2); \
+ \
+ return JTEST_TEST_PASSED; \
+ }
+
+#endif /* _INTRINSICS_TEMPLATES_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/intrinsics_tests/intrinsics_test_data.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/intrinsics_tests/intrinsics_test_data.h
new file mode 100644
index 0000000..130e4e8
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/intrinsics_tests/intrinsics_test_data.h
@@ -0,0 +1,27 @@
+#ifndef _INTRINSICS_TEST_DATA_H_
+#define _INTRINSICS_TEST_DATA_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+#define INTRINSICS_MAX_LEN 1024
+
+/*--------------------------------------------------------------------------------*/
+/* Variable Declarations */
+/*--------------------------------------------------------------------------------*/
+
+extern q63_t intrinsics_output_fut[INTRINSICS_MAX_LEN];
+extern q63_t intrinsics_output_ref[INTRINSICS_MAX_LEN];
+extern float32_t intrinsics_output_f32_fut[INTRINSICS_MAX_LEN];
+extern float32_t intrinsics_output_f32_ref[INTRINSICS_MAX_LEN];
+extern const q63_t intrinsics_q63_inputs[INTRINSICS_MAX_LEN];
+extern const q31_t *intrinsics_q31_inputs;
+
+#endif /* _INTRINSICS_TEST_DATA_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/intrinsics_tests/intrinsics_test_group.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/intrinsics_tests/intrinsics_test_group.h
new file mode 100644
index 0000000..d21d626
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/intrinsics_tests/intrinsics_test_group.h
@@ -0,0 +1,9 @@
+#ifndef _INTRINSICS_TEST_GROUP_H_
+#define _INTRINSICS_TEST_GROUP_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Test Groups */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(intrinsics_tests);
+
+#endif /* _INTRINSICS_TEST_GROUP_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/math_helper.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/math_helper.h
new file mode 100644
index 0000000..1ca7acb
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/math_helper.h
@@ -0,0 +1,52 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010 ARM Limited. All rights reserved.
+*
+* $Date: 29. November 2010
+* $Revision: V1.0.3
+*
+* Project: CMSIS DSP Library
+*
+* Title: math_helper.h
+*
+*
+* Description: Prototypes of all helper functions required.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Version 1.0.3 2010/11/29
+* Re-organized the CMSIS folders and updated documentation.
+*
+* Version 1.0.2 2010/11/11
+* Documentation updated.
+*
+* Version 1.0.1 2010/10/05
+* Production release and review comments incorporated.
+*
+* Version 1.0.0 2010/09/20
+* Production release and review comments incorporated.
+*
+* Version 0.0.7 2010/06/10
+* Misra-C changes done
+* -------------------------------------------------------------------- */
+
+#ifndef MATH_HELPER_H
+#define MATH_HELPER_H
+
+#include "arm_math.h"
+
+float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize);
+double arm_snr_f64(double *pRef, double *pTest, uint32_t buffSize);
+void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples);
+void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits);
+void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits);
+void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples);
+void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_clip_f32(float *pIn, uint32_t numSamples);
+uint32_t arm_calc_guard_bits(uint32_t num_adds);
+void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits);
+uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples);
+uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples);
+uint32_t arm_calc_2pow(uint32_t guard_bits);
+#endif
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_templates.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_templates.h
new file mode 100644
index 0000000..98f3552
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_templates.h
@@ -0,0 +1,370 @@
+#ifndef _MATRIX_TEMPLATES_H_
+#define _MATRIX_TEMPLATES_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+#include "test_templates.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Group Specific Templates */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Compare the outputs from the function under test and the reference
+ * function.
+ */
+#define MATRIX_COMPARE_INTERFACE(output_type, output_content_type) \
+ TEST_ASSERT_BUFFERS_EQUAL( \
+ ((output_type *) &matrix_output_ref)->pData, \
+ ((output_type *) &matrix_output_fut)->pData, \
+ ((output_type *) &matrix_output_fut)->numRows * \
+ ((output_type *) &matrix_output_ref)->numCols * \
+ sizeof(output_content_type))
+
+/**
+ * Comparison SNR thresholds for the data types used in matrix_tests.
+ */
+#define MATRIX_SNR_THRESHOLD 120
+
+/**
+ * Compare the outputs from the function under test and the reference
+ * function using SNR.
+ */
+#define MATRIX_SNR_COMPARE_INTERFACE(output_type, output_content_type) \
+ do \
+ { \
+ TEST_CONVERT_AND_ASSERT_SNR( \
+ (float32_t *)matrix_output_f32_ref, \
+ ((output_type *) &matrix_output_ref)->pData, \
+ (float32_t *)matrix_output_f32_fut, \
+ ((output_type *) &matrix_output_ref)->pData, \
+ ((output_type *) &matrix_output_fut)->numRows * \
+ ((output_type *) &matrix_output_ref)->numCols, \
+ output_content_type, \
+ MATRIX_SNR_THRESHOLD \
+ ); \
+ } while (0)
+
+/**
+ * Compare the outputs from the function under test and the reference
+ * function using SNR. This is special for float64_t
+ */
+#define MATRIX_DBL_SNR_COMPARE_INTERFACE(output_type) \
+ do \
+ { \
+ TEST_ASSERT_DBL_SNR( \
+ (float64_t *)matrix_output_f32_ref, \
+ (float64_t *)matrix_output_f32_fut, \
+ ((output_type *) &matrix_output_fut)->numRows * \
+ ((output_type *) &matrix_output_ref)->numCols, \
+ MATRIX_SNR_THRESHOLD \
+ ); \
+ } while (0)
+
+/*--------------------------------------------------------------------------------*/
+/* Input Interfaces */
+/*--------------------------------------------------------------------------------*/
+/*
+ * General:
+ * Input interfaces provide inputs to functions inside test templates. They
+ * ONLY provide the inputs. The output variables should be hard coded.
+ *
+ * The input interfaces must have the following format:
+ *
+ * ARM_xxx_INPUT_INTERFACE() or
+ * REF_xxx_INPUT_INTERFACE()
+ *
+ * The xxx must be lowercase, and is intended to be the indentifying substring
+ * in the function's name. Acceptable values are 'sub' or 'add' from the
+ * functions arm_add_q31.
+ */
+
+#define ARM_mat_add_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \
+ PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_fut)
+
+#define REF_mat_add_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \
+ PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_ref)
+
+#define ARM_mat_cmplx_mult_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \
+ PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_fut)
+
+#define REF_mat_cmplx_mult_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \
+ PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_ref)
+
+#define ARM_mat_inverse_INPUT_INTERFACE(input_ptr) \
+ PAREN(input_ptr, (void *) &matrix_output_fut)
+
+#define REF_mat_inverse_INPUT_INTERFACE(input_ptr) \
+ PAREN(input_ptr, (void *) &matrix_output_ref)
+
+#define ARM_mat_mult_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \
+ PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_fut)
+
+#define REF_mat_mult_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \
+ PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_ref)
+
+#define ARM_mat_mult_fast_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \
+ PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_fut)
+
+#define REF_mat_mult_fast_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \
+ PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_ref)
+
+#define ARM_mat_sub_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \
+ PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_fut)
+
+#define REF_mat_sub_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \
+ PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_ref)
+
+#define ARM_mat_trans_INPUT_INTERFACE(input_ptr) \
+ PAREN(input_ptr, (void *) &matrix_output_fut)
+
+#define REF_mat_trans_INPUT_INTERFACE(input_ptr) \
+ PAREN(input_ptr, (void *) &matrix_output_ref)
+
+/*--------------------------------------------------------------------------------*/
+/* Dimension Validation Interfaces */
+/*--------------------------------------------------------------------------------*/
+
+#define MATRIX_TEST_VALID_ADDITIVE_DIMENSIONS(input_type, \
+ matrix_a_ptr, \
+ matrix_b_ptr) \
+ ((((input_type) (matrix_a_ptr))->numRows == \
+ ((input_type) (matrix_b_ptr))->numRows) && \
+ (((input_type) (matrix_a_ptr))->numCols == \
+ ((input_type) (matrix_b_ptr))->numCols))
+
+#define MATRIX_TEST_VALID_MULTIPLICATIVE_DIMENSIONS(input_type, \
+ matrix_a_ptr, \
+ matrix_b_ptr) \
+ (((input_type) (matrix_a_ptr))->numCols == \
+ ((input_type) (matrix_b_ptr))->numRows)
+
+#define MATRIX_TEST_VALID_SQUARE_DIMENSIONS(input_type, \
+ matrix_ptr) \
+ (((input_type)(matrix_ptr))->numRows == \
+ ((input_type)(matrix_ptr))->numCols)
+
+#define MATRIX_TEST_VALID_DIMENSIONS_ALWAYS(input_type, \
+ matrix_ptr) \
+ (1 == 1) \
+
+/*--------------------------------------------------------------------------------*/
+/* Output Configuration Interfaces */
+/*--------------------------------------------------------------------------------*/
+/* The matrix tests assume the output matrix is always the correct size. These
+ * interfaces size the properly size the output matrices according to the input
+ * matrices and the operation at hand.*/
+
+#define MATRIX_TEST_CONFIG_ADDITIVE_OUTPUT(input_type, \
+ matrix_a_ptr, \
+ matrix_b_ptr) \
+ do \
+ { \
+ ((input_type) &matrix_output_fut)->numRows = \
+ ((input_type)(matrix_a_ptr))->numRows; \
+ ((input_type) &matrix_output_fut)->numCols = \
+ ((input_type)(matrix_a_ptr))->numCols; \
+ ((input_type) &matrix_output_ref)->numRows = \
+ ((input_type)(matrix_a_ptr))->numRows; \
+ ((input_type) &matrix_output_ref)->numCols = \
+ ((input_type)(matrix_a_ptr))->numCols; \
+ } while (0)
+
+#define MATRIX_TEST_CONFIG_MULTIPLICATIVE_OUTPUT(input_type, \
+ matrix_a_ptr, \
+ matrix_b_ptr) \
+ do \
+ { \
+ ((input_type) &matrix_output_fut)->numRows = \
+ ((input_type)(matrix_a_ptr))->numRows; \
+ ((input_type) &matrix_output_fut)->numCols = \
+ ((input_type)(matrix_b_ptr))->numCols; \
+ ((input_type) &matrix_output_ref)->numRows = \
+ ((input_type)(matrix_a_ptr))->numRows; \
+ ((input_type) &matrix_output_ref)->numCols = \
+ ((input_type)(matrix_b_ptr))->numCols; \
+ } while (0)
+
+#define MATRIX_TEST_CONFIG_SAMESIZE_OUTPUT(input_type, \
+ matrix_ptr) \
+ do \
+ { \
+ ((input_type) &matrix_output_fut)->numRows = \
+ ((input_type)(matrix_ptr))->numRows; \
+ ((input_type) &matrix_output_fut)->numCols = \
+ ((input_type)(matrix_ptr))->numCols; \
+ ((input_type) &matrix_output_ref)->numRows = \
+ ((input_type)(matrix_ptr))->numRows; \
+ ((input_type) &matrix_output_ref)->numCols = \
+ ((input_type)(matrix_ptr))->numCols; \
+ } while (0)
+
+#define MATRIX_TEST_CONFIG_TRANSPOSE_OUTPUT(input_type, \
+ matrix_ptr) \
+ do \
+ { \
+ ((input_type) &matrix_output_fut)->numRows = \
+ ((input_type)(matrix_ptr))->numCols; \
+ ((input_type) &matrix_output_fut)->numCols = \
+ ((input_type)(matrix_ptr))->numRows; \
+ ((input_type) &matrix_output_ref)->numRows = \
+ ((input_type)(matrix_ptr))->numCols; \
+ ((input_type) &matrix_output_ref)->numCols = \
+ ((input_type)(matrix_ptr))->numRows; \
+ } while (0)
+
+/*--------------------------------------------------------------------------------*/
+/* TEST Templates */
+/*--------------------------------------------------------------------------------*/
+
+#define MATRIX_TEST_TEMPLATE_ELT1(arr_desc_inputs, \
+ input_type, \
+ output_type, output_content_type, \
+ fut, fut_arg_interface, \
+ ref, ref_arg_interface, \
+ output_config_interface, \
+ dim_validation_interface, \
+ compare_interface) \
+ do \
+ { \
+ TEMPLATE_DO_ARR_DESC( \
+ input_idx, input_type, input, arr_desc_inputs \
+ , \
+ JTEST_DUMP_STRF("Matrix Dimensions: %dx%d\n", \
+ (int)input->numRows, \
+ (int)input->numCols); \
+ \
+ if (dim_validation_interface(input_type, \
+ input)) { \
+ output_config_interface(input_type, \
+ input); \
+ TEST_CALL_FUT_AND_REF( \
+ fut, fut_arg_interface(input), \
+ ref, ref_arg_interface(input)); \
+ compare_interface(output_type, \
+ output_content_type); \
+ } else { \
+ arm_status matrix_test_retval; \
+ TEST_CALL_FUT( \
+ matrix_test_retval = fut, \
+ fut_arg_interface(input)); \
+ \
+ /* If dimensions are known bad, the fut should */ \
+ /* detect it. */ \
+ if ( matrix_test_retval != ARM_MATH_SIZE_MISMATCH) { \
+ return JTEST_TEST_FAILED; \
+ } \
+ }); \
+ return JTEST_TEST_PASSED; \
+ } while (0)
+
+
+#define MATRIX_TEST_TEMPLATE_ELT2(arr_desc_inputs_a, \
+ arr_desc_inputs_b, \
+ input_type, \
+ output_type, output_content_type, \
+ fut, fut_arg_interface, \
+ ref, ref_arg_interface, \
+ output_config_interface, \
+ dim_validation_interface, \
+ compare_interface) \
+ do \
+ { \
+ TEMPLATE_DO_ARR_DESC( \
+ input_a_idx, input_type, input_a, arr_desc_inputs_a \
+ , \
+ input_type input_b = ARR_DESC_ELT( \
+ input_type, input_a_idx, \
+ &(arr_desc_inputs_b)); \
+ \
+ JTEST_DUMP_STRF("Matrix Dimensions: A %dx%d B %dx%d\n", \
+ (int)input_a->numRows, \
+ (int)input_a->numCols, \
+ (int)input_b->numRows, \
+ (int)input_b->numCols); \
+ \
+ if (dim_validation_interface(input_type, \
+ input_a, \
+ input_b)) { \
+ \
+ output_config_interface(input_type, \
+ input_a, \
+ input_b); \
+ \
+ TEST_CALL_FUT_AND_REF( \
+ fut, fut_arg_interface(input_a, input_b), \
+ ref, ref_arg_interface(input_a, input_b)); \
+ \
+ compare_interface(output_type, output_content_type); \
+ \
+ } else { \
+ arm_status matrix_test_retval; \
+ TEST_CALL_FUT( \
+ matrix_test_retval = fut, fut_arg_interface(input_a, input_b)); \
+ \
+ /* If dimensions are known bad, the fut should */ \
+ /* detect it. */ \
+ if ( matrix_test_retval != ARM_MATH_SIZE_MISMATCH) { \
+ return JTEST_TEST_FAILED; \
+ } \
+ }); \
+ return JTEST_TEST_PASSED; \
+ } while (0)
+
+/**
+ * Specialization of #MATRIX_TEST_TEMPLATE_ELT2() for matrix tests.
+ *
+ * @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
+ * REF_xxx_INPUT_INTERFACEs.
+ */
+#define MATRIX_DEFINE_TEST_TEMPLATE_ELT2(fn_name, suffix, \
+ output_config_interface, \
+ dim_validation_interface, \
+ comparison_interface) \
+ JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \
+ arm_##fn_name##_##suffix) \
+ { \
+ MATRIX_TEST_TEMPLATE_ELT2( \
+ matrix_##suffix##_a_inputs, \
+ matrix_##suffix##_b_inputs, \
+ arm_matrix_instance_##suffix * , \
+ arm_matrix_instance_##suffix, \
+ TYPE_FROM_ABBREV(suffix), \
+ arm_##fn_name##_##suffix, \
+ ARM_##fn_name##_INPUT_INTERFACE, \
+ ref_##fn_name##_##suffix, \
+ REF_##fn_name##_INPUT_INTERFACE, \
+ output_config_interface, \
+ dim_validation_interface, \
+ comparison_interface); \
+ } \
+
+/**
+ * Specialization of #MATRIX_TEST_TEMPLATE_ELT1() for matrix tests.
+ *
+ * @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
+ * REF_xxx_INPUT_INTERFACEs.
+ */
+#define MATRIX_DEFINE_TEST_TEMPLATE_ELT1(fn_name, suffix, \
+ output_config_interface, \
+ dim_validation_interface) \
+ JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \
+ arm_##fn_name##_##suffix) \
+ { \
+ MATRIX_TEST_TEMPLATE_ELT1( \
+ matrix_##suffix##_a_inputs, \
+ arm_matrix_instance_##suffix * , \
+ arm_matrix_instance_##suffix, \
+ TYPE_FROM_ABBREV(suffix), \
+ arm_##fn_name##_##suffix, \
+ ARM_##fn_name##_INPUT_INTERFACE, \
+ ref_##fn_name##_##suffix, \
+ REF_##fn_name##_INPUT_INTERFACE, \
+ output_config_interface, \
+ dim_validation_interface, \
+ MATRIX_COMPARE_INTERFACE); \
+ } \
+
+
+#endif /* _MATRIX_TEMPLATES_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_test_data.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_test_data.h
new file mode 100644
index 0000000..5940ae3
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_test_data.h
@@ -0,0 +1,54 @@
+#ifndef _MATRIX_TEST_DATA_H_
+#define _MATRIX_TEST_DATA_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "arr_desc.h"
+#include "arm_math.h" /* float32_t */
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+#define MATRIX_TEST_MAX_ROWS 4
+#define MATRIX_TEST_MAX_COLS 4
+#define MATRIX_TEST_BIGGEST_INPUT_TYPE float64_t
+#define MATRIX_TEST_MAX_ELTS (MATRIX_TEST_MAX_ROWS * MATRIX_TEST_MAX_COLS)
+#define MATRIX_MAX_COEFFS_LEN 16
+#define MATRIX_MAX_SHIFTS_LEN 5
+
+/**
+ * Declare the matrix inputs defined by MATRIX_DEFINE_INPUTS.
+ */
+#define MATRIX_DECLARE_INPUTS(suffix) \
+ ARR_DESC_DECLARE(matrix_##suffix##_a_inputs); \
+ ARR_DESC_DECLARE(matrix_##suffix##_b_inputs); \
+ ARR_DESC_DECLARE(matrix_##suffix##_invertible_inputs)
+
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Variables */
+/*--------------------------------------------------------------------------------*/
+
+/* Input/Output Buffers */
+extern arm_matrix_instance_f32 matrix_output_fut;
+extern arm_matrix_instance_f32 matrix_output_ref;
+extern arm_matrix_instance_f64 matrix_output_fut64;
+extern arm_matrix_instance_f64 matrix_output_ref64;
+extern MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_output_f32_fut[MATRIX_TEST_MAX_ELTS];
+extern MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_output_f32_ref[MATRIX_TEST_MAX_ELTS];
+extern MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_output_scratch[MATRIX_TEST_MAX_ELTS];
+
+/* Matrix Inputs */
+MATRIX_DECLARE_INPUTS(f64);
+MATRIX_DECLARE_INPUTS(f32);
+MATRIX_DECLARE_INPUTS(q31);
+MATRIX_DECLARE_INPUTS(q15);
+
+extern const float32_t matrix_f32_scale_values[MATRIX_MAX_COEFFS_LEN];
+extern const q31_t matrix_q31_scale_values[MATRIX_MAX_COEFFS_LEN];
+extern const q15_t matrix_q15_scale_values[MATRIX_MAX_COEFFS_LEN];
+extern const int32_t matrix_shift_values[MATRIX_MAX_SHIFTS_LEN];
+
+#endif /* _MATRIX_TEST_DATA_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_test_group.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_test_group.h
new file mode 100644
index 0000000..017b125
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_test_group.h
@@ -0,0 +1,9 @@
+#ifndef _MATRIX_TEST_GROUP_H_
+#define _MATRIX_TEST_GROUP_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Test Groups */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(matrix_tests);
+
+#endif /* _MATRIX_TEST_GROUP_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_tests.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_tests.h
new file mode 100644
index 0000000..9947c02
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_tests.h
@@ -0,0 +1,17 @@
+#ifndef _MATRIX_TESTS_H_
+#define _MATRIX_TESTS_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Test/Group Declarations */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(mat_add_tests);
+JTEST_DECLARE_GROUP(mat_cmplx_mult_tests);
+JTEST_DECLARE_GROUP(mat_init_tests);
+JTEST_DECLARE_GROUP(mat_inverse_tests);
+JTEST_DECLARE_GROUP(mat_mult_tests);
+JTEST_DECLARE_GROUP(mat_mult_fast_tests);
+JTEST_DECLARE_GROUP(mat_sub_tests);
+JTEST_DECLARE_GROUP(mat_trans_tests);
+JTEST_DECLARE_GROUP(mat_scale_tests);
+
+#endif /* _MATRIX_TESTS_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_templates.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_templates.h
new file mode 100644
index 0000000..ddca35c
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_templates.h
@@ -0,0 +1,157 @@
+#ifndef _STATISTICS_TEMPLATES_H_
+#define _STATISTICS_TEMPLATES_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "test_templates.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Group Specific Templates */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Compare the outputs from the function under test and the reference function.
+ */
+#define STATISTICS_COMPARE_INTERFACE(block_size, \
+ output_type) \
+ do \
+ { \
+ TEST_ASSERT_BUFFERS_EQUAL( \
+ statistics_output_ref.data_ptr, \
+ statistics_output_fut.data_ptr, \
+ 1 * sizeof(output_type) /* All fns return one value*/ \
+ ); \
+ TEST_ASSERT_EQUAL( \
+ statistics_idx_fut, \
+ statistics_idx_ref); \
+ } while (0) \
+
+/*
+ * Comparison SNR thresholds for the data types used in statistics_tests.
+ */
+#define STATISTICS_SNR_THRESHOLD_float32_t 120
+#define STATISTICS_SNR_THRESHOLD_q31_t 100
+#define STATISTICS_SNR_THRESHOLD_q15_t 60
+#define STATISTICS_SNR_THRESHOLD_q7_t 30
+
+/**
+ * Compare reference and fut outputs using SNR.
+ *
+ * @note The outputs are converted to float32_t before comparison.
+ */
+#define STATISTICS_SNR_COMPARE_INTERFACE(block_size, \
+ output_type) \
+ do \
+ { \
+ TEST_CONVERT_AND_ASSERT_SNR( \
+ statistics_output_f32_ref, \
+ statistics_output_ref.data_ptr, \
+ statistics_output_f32_fut, \
+ statistics_output_fut.data_ptr, \
+ 1, /* All fns return one element*/ \
+ output_type, \
+ STATISTICS_SNR_THRESHOLD_##output_type \
+ ); \
+ } while (0)
+
+
+
+/*--------------------------------------------------------------------------------*/
+/* Input Interfaces */
+/*--------------------------------------------------------------------------------*/
+/*
+ * General:
+ * Input interfaces provide inputs to functions inside test templates. They
+ * ONLY provide the inputs. The output variables should be hard coded.
+ *
+ * The input interfaces must have the following format:
+ *
+ * ARM_xxx_INPUT_INTERFACE() or
+ * REF_xxx_INPUT_INTERFACE()
+ *
+ * The xxx must be lowercase, and is intended to be the indentifying substring
+ * in the function's name. Acceptable values are 'sub' or 'add' from the
+ * functions arm_add_q31.
+ */
+
+#define ARM_max_INPUT_INTERFACE(input, block_size) \
+ PAREN(input, block_size, \
+ statistics_output_fut.data_ptr, &statistics_idx_fut)
+
+#define REF_max_INPUT_INTERFACE(input, block_size) \
+ PAREN(input, block_size, \
+ statistics_output_ref.data_ptr, &statistics_idx_ref)
+
+#define ARM_mean_INPUT_INTERFACE(input, block_size) \
+ PAREN(input, block_size, statistics_output_fut.data_ptr)
+
+#define REF_mean_INPUT_INTERFACE(input, block_size) \
+ PAREN(input, block_size, statistics_output_ref.data_ptr)
+
+#define ARM_min_INPUT_INTERFACE(input, block_size) \
+ PAREN(input, block_size, \
+ statistics_output_fut.data_ptr, &statistics_idx_fut)
+
+#define REF_min_INPUT_INTERFACE(input, block_size) \
+ PAREN(input, block_size, \
+ statistics_output_ref.data_ptr, &statistics_idx_ref)
+
+#define ARM_power_INPUT_INTERFACE(input, block_size) \
+ PAREN(input, block_size, statistics_output_fut.data_ptr)
+
+#define REF_power_INPUT_INTERFACE(input, block_size) \
+ PAREN(input, block_size, statistics_output_ref.data_ptr)
+
+#define ARM_rms_INPUT_INTERFACE(input, block_size) \
+ PAREN(input, block_size, statistics_output_fut.data_ptr)
+
+#define REF_rms_INPUT_INTERFACE(input, block_size) \
+ PAREN(input, block_size, statistics_output_ref.data_ptr)
+
+#define ARM_std_INPUT_INTERFACE(input, block_size) \
+ PAREN(input, block_size, statistics_output_fut.data_ptr)
+
+#define REF_std_INPUT_INTERFACE(input, block_size) \
+ PAREN(input, block_size, statistics_output_ref.data_ptr)
+
+#define ARM_var_INPUT_INTERFACE(input, block_size) \
+ PAREN(input, block_size, statistics_output_fut.data_ptr)
+
+#define REF_var_INPUT_INTERFACE(input, block_size) \
+ PAREN(input, block_size, statistics_output_ref.data_ptr)
+
+
+/*--------------------------------------------------------------------------------*/
+/* Test Templates */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Specialization of #TEST_TEMPLATE_BUF1_BLK() for statistics tests.
+ *
+ * @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
+ * REF_xxx_INPUT_INTERFACEs.
+ */
+#define STATISTICS_DEFINE_TEST_TEMPLATE_BUF1_BLK(fn_name, \
+ suffix, \
+ input_type, \
+ output_type, \
+ comparison_interface) \
+ JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \
+ arm_##fn_name##_##suffix) \
+ { \
+ TEST_TEMPLATE_BUF1_BLK( \
+ statistics_f_all, \
+ statistics_block_sizes, \
+ input_type, \
+ output_type, \
+ arm_##fn_name##_##suffix, \
+ ARM_##fn_name##_INPUT_INTERFACE, \
+ ref_##fn_name##_##suffix, \
+ REF_##fn_name##_INPUT_INTERFACE, \
+ comparison_interface); \
+ }
+
+
+#endif /* _STATISTICS_TEMPLATES_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_test_data.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_test_data.h
new file mode 100644
index 0000000..3e1ee09
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_test_data.h
@@ -0,0 +1,44 @@
+#ifndef _STATISTICS_TEST_DATA_H_
+#define _STATISTICS_TEST_DATA_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "arr_desc.h"
+#include "arm_math.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+#define STATISTICS_MAX_INPUT_ELEMENTS 32
+#define STATISTICS_BIGGEST_INPUT_TYPE float32_t
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Variables */
+/*--------------------------------------------------------------------------------*/
+
+/* Input/Output Buffers */
+ARR_DESC_DECLARE(statistics_output_fut);
+ARR_DESC_DECLARE(statistics_output_ref);
+extern uint32_t statistics_idx_fut;
+extern uint32_t statistics_idx_ref;
+
+extern STATISTICS_BIGGEST_INPUT_TYPE
+statistics_output_f32_ref[STATISTICS_MAX_INPUT_ELEMENTS];
+
+extern STATISTICS_BIGGEST_INPUT_TYPE
+statistics_output_f32_fut[STATISTICS_MAX_INPUT_ELEMENTS];
+
+
+/* Block Sizes */
+ARR_DESC_DECLARE(statistics_block_sizes);
+
+/* Float Inputs */
+ARR_DESC_DECLARE(statistics_zeros);
+ARR_DESC_DECLARE(statistics_f_2);
+ARR_DESC_DECLARE(statistics_f_15);
+ARR_DESC_DECLARE(statistics_f_32);
+ARR_DESC_DECLARE(statistics_f_all);
+
+#endif /* _STATISTICS_TEST_DATA_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_test_group.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_test_group.h
new file mode 100644
index 0000000..d1446ed
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_test_group.h
@@ -0,0 +1,9 @@
+#ifndef _STATISTICS_TEST_GROUP_H_
+#define _STATISTICS_TEST_GROUP_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Test Groups */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(statistics_tests);
+
+#endif /* _STATISTICS_TEST_GROUP_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_tests.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_tests.h
new file mode 100644
index 0000000..20df03e
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_tests.h
@@ -0,0 +1,15 @@
+#ifndef _STATISTICS_TESTS_H_
+#define _STATISTICS_TESTS_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Test/Group Declarations */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(max_tests);
+JTEST_DECLARE_GROUP(mean_tests);
+JTEST_DECLARE_GROUP(min_tests);
+JTEST_DECLARE_GROUP(power_tests);
+JTEST_DECLARE_GROUP(rms_tests);
+JTEST_DECLARE_GROUP(std_tests);
+JTEST_DECLARE_GROUP(var_tests);
+
+#endif /* _STATISTICS_TESTS_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_templates.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_templates.h
new file mode 100644
index 0000000..bc94791
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_templates.h
@@ -0,0 +1,120 @@
+#ifndef _SUPPORT_TEMPLATES_H_
+#define _SUPPORT_TEMPLATES_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "test_templates.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Group Specific Templates */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Compare the outputs from the function under test and the reference function.
+ */
+#define SUPPORT_COMPARE_INTERFACE(block_size, \
+ output_type) \
+ do \
+ { \
+ TEST_ASSERT_BUFFERS_EQUAL( \
+ support_output_ref.data_ptr, \
+ support_output_fut.data_ptr, \
+ block_size * sizeof(output_type)); \
+ } while (0) \
+
+/*--------------------------------------------------------------------------------*/
+/* Input Interfaces */
+/*--------------------------------------------------------------------------------*/
+/*
+ * General:
+ * Input interfaces provide inputs to functions inside test templates. They
+ * ONLY provide the inputs. The output variables should be hard coded.
+ *
+ * The input interfaces must have the following format:
+ *
+ * ARM_xxx_INPUT_INTERFACE() or
+ * REF_xxx_INPUT_INTERFACE()
+ *
+ * The xxx must be lowercase, and is intended to be the indentifying substring
+ * in the function's name. Acceptable values are 'sub' or 'add' from the
+ * functions arm_add_q31.
+ */
+
+#define ARM_copy_INPUT_INTERFACE(input, block_size) \
+ PAREN(input, support_output_fut.data_ptr, block_size)
+
+#define REF_copy_INPUT_INTERFACE(input, block_size) \
+ PAREN(input, support_output_ref.data_ptr, block_size)
+
+#define ARM_fill_INPUT_INTERFACE(elt, block_size) \
+ PAREN(elt, support_output_fut.data_ptr, block_size)
+
+#define REF_fill_INPUT_INTERFACE(elt, block_size) \
+ PAREN(elt, support_output_ref.data_ptr, block_size)
+
+#define ARM_x_to_y_INPUT_INTERFACE(input, block_size) \
+ PAREN(input, support_output_fut.data_ptr, block_size)
+
+#define REF_x_to_y_INPUT_INTERFACE(input, block_size) \
+ PAREN(input, support_output_ref.data_ptr, block_size)
+
+/*--------------------------------------------------------------------------------*/
+/* Test Templates */
+/*--------------------------------------------------------------------------------*/
+
+
+/**
+ * Specialization of #TEST_TEMPLATE_BUF1_BLK() for support tests.
+ *
+ * @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
+ * REF_xxx_INPUT_INTERFACEs.
+ */
+#define SUPPORT_DEFINE_TEST_TEMPLATE_BUF1_BLK(fn_name, \
+ suffix, \
+ input_type, \
+ output_type, \
+ comparison_interface) \
+ JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \
+ arm_##fn_name##_##suffix) \
+ { \
+ TEST_TEMPLATE_BUF1_BLK( \
+ support_f_all, \
+ support_block_sizes, \
+ input_type, \
+ output_type, \
+ arm_##fn_name##_##suffix, \
+ ARM_##fn_name##_INPUT_INTERFACE, \
+ ref_##fn_name##_##suffix, \
+ REF_##fn_name##_INPUT_INTERFACE, \
+ comparison_interface); \
+ }
+
+/**
+ * Specialization of #TEST_TEMPLATE_ELT1_BLK() for support tests.
+ *
+ * @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
+ * REF_xxx_INPUT_INTERFACEs.
+ */
+#define SUPPORT_DEFINE_TEST_TEMPLATE_ELT1_BLK(fn_name, \
+ suffix, \
+ elt_type, \
+ output_type, \
+ comparison_interface) \
+ JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \
+ arm_##fn_name##_##suffix) \
+ { \
+ TEST_TEMPLATE_ELT1_BLK( \
+ support_elts, \
+ support_block_sizes, \
+ elt_type, \
+ output_type, \
+ arm_##fn_name##_##suffix, \
+ ARM_##fn_name##_INPUT_INTERFACE, \
+ ref_##fn_name##_##suffix, \
+ REF_##fn_name##_INPUT_INTERFACE, \
+ comparison_interface); \
+ }
+
+#endif /* _SUPPORT_TEMPLATES_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_test_data.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_test_data.h
new file mode 100644
index 0000000..cc6c636
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_test_data.h
@@ -0,0 +1,31 @@
+#ifndef ARM_SUPPORT_TEST_DATA_H
+#define ARM_SUPPORT_TEST_DATA_H
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "arr_desc.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Variables */
+/*--------------------------------------------------------------------------------*/
+
+/* Input/Output Buffers */
+ARR_DESC_DECLARE(support_output_fut);
+ARR_DESC_DECLARE(support_output_ref);
+
+/* Block Sizes*/
+ARR_DESC_DECLARE(support_block_sizes);
+
+/* Numbers */
+ARR_DESC_DECLARE(support_elts);
+
+/* Float Inputs */
+ARR_DESC_DECLARE(support_zeros);
+ARR_DESC_DECLARE(support_f_2);
+ARR_DESC_DECLARE(support_f_15);
+ARR_DESC_DECLARE(support_f_32);
+ARR_DESC_DECLARE(support_f_all);
+
+#endif
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_test_group.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_test_group.h
new file mode 100644
index 0000000..ef3a768
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_test_group.h
@@ -0,0 +1,9 @@
+#ifndef _SUPPORT_TEST_GROUP_H_
+#define _SUPPORT_TEST_GROUP_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Test Groups */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(support_tests);
+
+#endif /* _SUPPORT_TEST_GROUP_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_tests.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_tests.h
new file mode 100644
index 0000000..2eab273
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_tests.h
@@ -0,0 +1,11 @@
+#ifndef _SUPPORT_TESTS_H_
+#define _SUPPORT_TESTS_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Test/Group Declarations */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(copy_tests);
+JTEST_DECLARE_GROUP(fill_tests);
+JTEST_DECLARE_GROUP(x_to_y_tests);
+
+#endif /* _SUPPORT_TESTS_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/templates/template.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/templates/template.h
new file mode 100644
index 0000000..e4577d1
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/templates/template.h
@@ -0,0 +1,88 @@
+#ifndef _TEMPLATE_H_
+#define _TEMPLATE_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Looping and Iteration */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Template for the general structure of a loop.
+ */
+#define TEMPLATE_LOOP(setup, loop_def, body) \
+ do \
+ { \
+ setup; \
+ loop_def { \
+ body; \
+ } \
+ } while (0)
+
+/**
+ * Template for looping over an array-like sequence.
+ */
+#define TEMPLATE_DO_ARR_LIKE(iter_idx, type, \
+ arr, arr_length, \
+ iter_elem_setup, \
+ body) \
+ do \
+ { \
+ TEMPLATE_LOOP( \
+ int iter_idx, \
+ for(iter_idx = 0; iter_idx < (arr_length); ++iter_idx), \
+ iter_elem_setup; \
+ body); \
+ } while (0)
+
+/**
+ * Template for looping over the contents of an array.
+ */
+#define TEMPLATE_DO_ARR(iter_idx, type, iter_elem, arr, arr_length, body) \
+ do \
+ { \
+ TEMPLATE_DO_ARR_LIKE( \
+ iter_idx, type, arr, arr_length, \
+ type iter_elem = (arr)[iter_idx], \
+ body); \
+ } while (0)
+
+/**
+ * Template for looping over the contents of an #ARR_DESC.
+ */
+#define TEMPLATE_DO_ARR_DESC(iter_idx, type, iter_elem, arr_desc, body) \
+ do \
+ { \
+ TEMPLATE_DO_ARR_LIKE( \
+ iter_idx, type, arr_desc, (arr_desc).element_count, \
+ type iter_elem = ARR_DESC_ELT(type, iter_idx, &(arr_desc)), \
+ body); \
+ } while (0)
+
+/*--------------------------------------------------------------------------------*/
+/* Test Definition */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Template for the general structure of a test.
+ */
+#define TEMPLATE_TEST(setup, body, teardown) \
+ do \
+ { \
+ setup; \
+ body; \
+ teardown; \
+ } while (0)
+
+/**
+ * Template for calling a function.
+ *
+ * @note Surround function arguments with the #PAREN() macro.
+ *
+ * @example
+ * void my_func(int arg1, int arg2);
+ *
+ * TEMPLATE_CALL_FN(my_func, PAREN(3, 7));
+ */
+#define TEMPLATE_CALL_FN(fn, fn_args) \
+ fn fn_args
+
+#endif /* _TEMPLATE_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/templates/test_templates.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/templates/test_templates.h
new file mode 100644
index 0000000..700bbe1
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/templates/test_templates.h
@@ -0,0 +1,458 @@
+#ifndef _TEST_TEMPLATES_H_
+#define _TEST_TEMPLATES_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+#include "template.h"
+#include <string.h> /* memcmp() */
+#include <inttypes.h> /* PRIu32 */
+#include "math_helper.h" /* arm_snr_f32() */
+
+/*--------------------------------------------------------------------------------*/
+/* Function Aliases for use in Templates. */
+/*--------------------------------------------------------------------------------*/
+#define ref_q31_t_to_float ref_q31_to_float
+#define ref_q15_t_to_float ref_q15_to_float
+#define ref_q7_t_to_float ref_q7_to_float
+#define ref_float_to_q31_t ref_float_to_q31
+#define ref_float_to_q15_t ref_float_to_q15
+#define ref_float_to_q7_t ref_float_to_q7
+#define ref_float32_t_to_float ref_copy_f32
+#define ref_float_to_float32_t ref_copy_f32
+
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Call the function-under-test.
+ */
+#define TEST_CALL_FUT(fut, fut_args) \
+ JTEST_COUNT_CYCLES(TEMPLATE_CALL_FN(fut, fut_args))
+
+/**
+ * Call the reference-function.
+ */
+#define TEST_CALL_REF(ref, ref_args) \
+ TEMPLATE_CALL_FN(ref, ref_args)
+
+/**
+ * Call the function-under-test and the reference-function.
+ */
+#define TEST_CALL_FUT_AND_REF(fut, fut_args, ref, ref_args) \
+ do { \
+ TEST_CALL_FUT(fut, fut_args); \
+ TEST_CALL_REF(ref, ref_args); \
+ } while (0)
+
+/**
+ * This macro eats a variable number of arguments and evaluates to a null
+ * statement.
+ */
+#define TEST_NULL_STATEMENT(...) (void) "TEST_NULL_STATEMENT"
+
+/**
+ * A function name, Usable in any template where a fut or ref name is accepted,
+ * that evaluates to a #TEST_NULL_STATEMENT().
+ */
+#define TEST_NULL_FN TEST_NULL_STATEMENT
+
+/**
+ * Assert that buffers A and B are byte-equivalent for a number of bytes.
+ */
+#define TEST_ASSERT_BUFFERS_EQUAL(buf_a, buf_b, bytes) \
+ do \
+ { \
+ if (memcmp(buf_a, buf_b, bytes) != 0) \
+ { \
+ return JTEST_TEST_FAILED; \
+ } \
+ } while (0)
+
+/**
+ * Assert that the two entities are equal.
+ */
+#define TEST_ASSERT_EQUAL(a, b) \
+ do \
+ { \
+ if ((a) != (b)) \
+ { \
+ return JTEST_TEST_FAILED; \
+ } \
+ } while (0)
+
+/**
+ * Convert elements to from src_type to float.
+ */
+#define TEST_CONVERT_TO_FLOAT(src_ptr, dst_ptr, block_size, src_type) \
+ do \
+ { \
+ ref_##src_type##_to_float( \
+ src_ptr, \
+ dst_ptr, \
+ block_size); \
+ } while (0) \
+
+/**
+ * Convert elements to from float to dst_type .
+ */
+#define TEST_CONVERT_FLOAT_TO(src_ptr, dst_ptr, block_size, dst_type) \
+ do \
+ { \
+ ref_float_to_##dst_type( \
+ src_ptr, \
+ dst_ptr, \
+ block_size); \
+ } while (0) \
+
+/**
+ * Assert that the SNR between a reference and test sample is above a given
+ * threshold.
+ */
+#define TEST_ASSERT_SNR(ref_ptr, tst_ptr, block_size, threshold) \
+ do \
+ { \
+ float32_t snr = arm_snr_f32(ref_ptr, tst_ptr, block_size); \
+ if ( snr <= threshold) \
+ { \
+ JTEST_DUMP_STRF("SNR: %f\n", snr); \
+ return JTEST_TEST_FAILED; \
+ } \
+ } while (0) \
+
+/**
+ * Assert that the SNR between a reference and test sample is above a given
+ * threshold. Special case for float64_t
+ */
+#define TEST_ASSERT_DBL_SNR(ref_ptr, tst_ptr, block_size, threshold) \
+ do \
+ { \
+ float64_t snr = arm_snr_f64(ref_ptr, tst_ptr, block_size); \
+ if ( snr <= threshold) \
+ { \
+ JTEST_DUMP_STRF("SNR: %f\n", snr); \
+ return JTEST_TEST_FAILED; \
+ } \
+ } while (0) \
+
+/**
+ * Compare test and reference elements by converting to float and
+ * calculating an SNR.
+ *
+ * This macro is a merger of the #TEST_CONVERT_TO_FLOAT() and
+ * #TEST_ASSERT_SNR() macros.
+ */
+#define TEST_CONVERT_AND_ASSERT_SNR(ref_dst_ptr, ref_src_ptr, \
+ tst_dst_ptr, tst_src_ptr, \
+ block_size, \
+ tst_src_type, \
+ threshold) \
+ do \
+ { \
+ TEST_CONVERT_TO_FLOAT(ref_src_ptr, \
+ ref_dst_ptr, \
+ block_size, \
+ tst_src_type); \
+ TEST_CONVERT_TO_FLOAT(tst_src_ptr, \
+ tst_dst_ptr, \
+ block_size, \
+ tst_src_type); \
+ TEST_ASSERT_SNR(ref_dst_ptr, \
+ tst_dst_ptr, \
+ block_size, \
+ threshold); \
+ } while (0)
+
+/**
+ * Execute statements only if the combination of block size, function type
+ * specifier, and input ARR_DESC_t are valid.
+ *
+ * @example An ARR_DESC_t that contains 64 bytes cant service a 32 element
+ * block size if they are extracted in float32_t increments.
+ *
+ * 8 * 32 = 256 > 64.
+ */
+#define TEST_DO_VALID_BLOCKSIZE(block_size, fn_type_spec, \
+ input_arr_desc, body) \
+ do \
+ { \
+ if (block_size * sizeof(fn_type_spec) <= \
+ ARR_DESC_BYTES(input_arr_desc)) \
+ { \
+ JTEST_DUMP_STRF("Block Size: %"PRIu32"\n", block_size); \
+ body; \
+ } \
+ } while (0) \
+
+/**
+ * Template for tests that rely on one input buffer and a blocksize parameter.
+ *
+ * The buffer is an #ARR_DESC_t. It is iterated over and it's values are
+ * passed to the function under test and reference functions through their
+ * appropriate argument interfaces. The argument interfaces this template to
+ * execute structurally similar functions.
+ *
+ */
+#define TEST_TEMPLATE_BUF1_BLK(arr_desc_inputs, \
+ arr_desc_block_sizes, \
+ input_type, output_type, \
+ fut, fut_arg_interface, \
+ ref, ref_arg_interface, \
+ compare_interface) \
+ do \
+ { \
+ TEMPLATE_DO_ARR_DESC( \
+ input_idx, ARR_DESC_t *, input_ptr, arr_desc_inputs \
+ , \
+ TEMPLATE_DO_ARR_DESC( \
+ block_size_idx, uint32_t, block_size, arr_desc_block_sizes \
+ , \
+ void * input_data_ptr = input_ptr->data_ptr; \
+ \
+ TEST_DO_VALID_BLOCKSIZE( \
+ block_size, input_type, input_ptr \
+ , \
+ TEST_CALL_FUT_AND_REF( \
+ fut, fut_arg_interface( \
+ input_data_ptr, block_size), \
+ ref, ref_arg_interface( \
+ input_data_ptr, block_size)); \
+ \
+ compare_interface(block_size, output_type)))); \
+ \
+ return JTEST_TEST_PASSED; \
+ \
+ } while (0)
+
+/**
+ * Template for tests that rely on an input buffer and an element.
+ *
+ * An element can is any thing which doesn't walk and talk like a
+ * sequence. Examples include numbers, and structures.
+ */
+#define TEST_TEMPLATE_BUF1_ELT1(arr_desc_inputs, \
+ arr_desc_elts, \
+ input_type, elt_type, output_type, \
+ fut, fut_arg_interface, \
+ ref, ref_arg_interface, \
+ compare_interface) \
+ do \
+ { \
+ TEMPLATE_DO_ARR_DESC( \
+ input_idx, ARR_DESC_t *, input_ptr, arr_desc_inputs \
+ , \
+ TEMPLATE_DO_ARR_DESC( \
+ elt_idx, elt_type, elt, arr_desc_elts \
+ , \
+ void * input_data_ptr = input_ptr->data_ptr; \
+ TEST_CALL_FUT_AND_REF( \
+ fut, fut_arg_interface(input_data_ptr, elt), \
+ ref, ref_arg_interface(input_data_ptr, elt)); \
+ \
+ compare_interface(output_type))); \
+ return JTEST_TEST_PASSED; \
+ } while (0)
+
+/**
+ * Template for tests that rely on an input buffer, an element, and a blocksize
+ * parameter.
+ */
+#define TEST_TEMPLATE_BUF1_ELT1_BLK(arr_desc_inputs, \
+ arr_desc_elts, \
+ arr_desc_block_sizes, \
+ input_type, elt_type, output_type, \
+ fut, fut_arg_interface, \
+ ref, ref_arg_interface, \
+ compare_interface); \
+ do \
+ { \
+ TEMPLATE_DO_ARR_DESC( \
+ inut_idx, ARR_DESC_t *, input_ptr, arr_desc_inputs \
+ , \
+ TEMPLATE_DO_ARR_DESC( \
+ block_size_idx, uint32_t, block_size, \
+ arr_desc_block_sizes \
+ , \
+ TEMPLATE_DO_ARR_DESC( \
+ elt_idx, elt_type, elt, arr_desc_elts \
+ , \
+ void * input_data_ptr = input_ptr->data_ptr; \
+ TEST_DO_VALID_BLOCKSIZE( \
+ block_size, input_type, input_ptr, \
+ \
+ TEST_CALL_FUT_AND_REF( \
+ fut, fut_arg_interface( \
+ input_data_ptr, elt, block_size), \
+ ref, ref_arg_interface( \
+ input_data_ptr, elt, block_size)); \
+ compare_interface(block_size, output_type))))); \
+ return JTEST_TEST_PASSED; \
+ } while (0)
+
+/**
+ * Template for tests that rely on an input buffer, two elements, and a blocksize
+ * parameter.
+ */
+#define TEST_TEMPLATE_BUF1_ELT2_BLK(arr_desc_inputs, \
+ arr_desc_elt1s, \
+ arr_desc_elt2s, \
+ arr_desc_block_sizes, \
+ input_type, elt1_type, \
+ elt2_type, output_type, \
+ fut, fut_arg_interface, \
+ ref, ref_arg_interface, \
+ compare_interface) \
+ do \
+ { \
+ TEMPLATE_DO_ARR_DESC( \
+ inut_idx, ARR_DESC_t *, input_ptr, arr_desc_inputs \
+ , \
+ TEMPLATE_DO_ARR_DESC( \
+ block_size_idx, uint32_t, block_size, \
+ arr_desc_block_sizes \
+ , \
+ TEMPLATE_DO_ARR_DESC( \
+ elt1_idx, elt1_type, elt1, arr_desc_elt1s \
+ , \
+ TEMPLATE_DO_ARR_DESC( \
+ elt2_idx, elt2_type, elt2, arr_desc_elt2s \
+ , \
+ void * input_data_ptr = input_ptr->data_ptr; \
+ TEST_DO_VALID_BLOCKSIZE( \
+ block_size, input_type, input_ptr, \
+ TEST_CALL_FUT_AND_REF( \
+ fut, fut_arg_interface( \
+ input_data_ptr, elt1, elt2, block_size), \
+ ref, ref_arg_interface( \
+ input_data_ptr, elt1, elt2, block_size)); \
+ compare_interface(block_size, output_type)))))); \
+ return JTEST_TEST_PASSED; \
+ } while (0)
+
+/**
+ * Template for tests that rely on two input buffers and a blocksize parameter.
+ *
+ * The two #ARR_DESC_t, input buffers are iterated through in parallel. The
+ * length of the first #ARR_DESC_t determines the length of the iteration.
+ */
+#define TEST_TEMPLATE_BUF2_BLK(arr_desc_inputs_a, \
+ arr_desc_inputs_b, \
+ arr_desc_block_sizes, \
+ input_type, output_type, \
+ fut, fut_arg_interface, \
+ ref, ref_arg_interface, \
+ compare_interface) \
+ do \
+ { \
+ /* Iterate over two input arrays in parallel.*/ \
+ TEMPLATE_DO_ARR_DESC( \
+ input_idx, ARR_DESC_t *, input_ptr, arr_desc_inputs_a \
+ , \
+ TEMPLATE_DO_ARR_DESC( \
+ block_size_idx, uint32_t, block_size, arr_desc_block_sizes, \
+ void * input_a_ptr = input_ptr->data_ptr; \
+ void * input_b_ptr = ARR_DESC_ELT( \
+ ARR_DESC_t *, input_idx, \
+ &(arr_desc_inputs_b))->data_ptr; \
+ \
+ TEST_DO_VALID_BLOCKSIZE( \
+ block_size, input_type, input_ptr \
+ , \
+ TEST_CALL_FUT_AND_REF( \
+ fut, fut_arg_interface( \
+ input_a_ptr, input_b_ptr, block_size), \
+ ref, ref_arg_interface( \
+ input_a_ptr, input_b_ptr, block_size)); \
+ \
+ compare_interface(block_size, output_type)))); \
+ return JTEST_TEST_PASSED; \
+ } while (0)
+
+/**
+ * Test template that uses a single element.
+ */
+#define TEST_TEMPLATE_ELT1(arr_desc_elts, \
+ elt_type, output_type, \
+ fut, fut_arg_interface, \
+ ref, ref_arg_interface, \
+ compare_interface) \
+ do \
+ { \
+ TEMPLATE_DO_ARR_DESC( \
+ elt_idx, elt_type, elt, arr_desc_elts \
+ , \
+ TEST_CALL_FUT_AND_REF( \
+ fut, fut_arg_interface( \
+ elt), \
+ ref, ref_arg_interface( \
+ elt)); \
+ /* Comparison interfaces typically accept */ \
+ /* a block_size. Pass a dummy value 1.*/ \
+ compare_interface(1, output_type)); \
+ return JTEST_TEST_PASSED; \
+ } while (0)
+
+/**
+ * Test template that iterates over two sets of elements in parallel.
+ *
+ * The length of the first set determines the number of iteratsions.
+ */
+#define TEST_TEMPLATE_ELT2(arr_desc_elts_a, \
+ arr_desc_elts_b, \
+ elt_a_type, elt_b_type, output_type, \
+ fut, fut_arg_interface, \
+ ref, ref_arg_interface, \
+ compare_interface) \
+ do \
+ { \
+ TEMPLATE_DO_ARR_DESC( \
+ elt_a_idx, elt_a_type, elt_a, arr_desc_elts_a \
+ , \
+ elt_b_type * elt_b = ARR_DESC_ELT( \
+ elt_b_type, \
+ elt_a_idx, \
+ arr_desc_elts_b); \
+ \
+ TEST_CALL_FUT_AND_REF( \
+ fut, fut_arg_interface( \
+ elt_a, elt_b), \
+ ref, ref_arg_interface( \
+ elt_a, elt_b)); \
+ /* Comparison interfaces typically accept */ \
+ /* a block_size. Pass a dummy value 1.*/ \
+ compare_interface(1, output_type)); \
+ return JTEST_TEST_PASSED; \
+ } while (0)
+
+/**
+ * Test template that uses an element and a block size.
+ */
+#define TEST_TEMPLATE_ELT1_BLK(arr_desc_elts, \
+ arr_desc_block_sizes, \
+ elt_type, output_type, \
+ fut, fut_arg_interface, \
+ ref, ref_arg_interface, \
+ compare_interface) \
+ do \
+ { \
+ TEMPLATE_DO_ARR_DESC( \
+ block_size_idx, uint32_t, block_size, \
+ arr_desc_block_sizes \
+ , \
+ TEMPLATE_DO_ARR_DESC( \
+ elt_idx, elt_type, elt, arr_desc_elts \
+ , \
+ JTEST_DUMP_STRF("Block Size: %d\n", \
+ (int)block_size); \
+ TEST_CALL_FUT_AND_REF( \
+ fut, fut_arg_interface( \
+ elt, block_size), \
+ ref, ref_arg_interface( \
+ elt, block_size)); \
+ compare_interface(block_size, output_type))); \
+ return JTEST_TEST_PASSED; \
+ } while (0)
+
+#endif /* _TEST_TEMPLATES_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_templates.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_templates.h
new file mode 100644
index 0000000..c6314b5
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_templates.h
@@ -0,0 +1,181 @@
+#ifndef _TRANSFORM_TEMPLATES_H_
+#define _TRANSFORM_TEMPLATES_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "test_templates.h"
+#include <string.h> /* memcpy() */
+
+/*--------------------------------------------------------------------------------*/
+/* Group Specific Templates */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Comparison SNR thresholds for the data types used in transform_tests.
+ */
+#define TRANSFORM_SNR_THRESHOLD_float32_t 90
+#define TRANSFORM_SNR_THRESHOLD_q31_t 90
+#define TRANSFORM_SNR_THRESHOLD_q15_t 30
+
+#define DCT4_TRANSFORM_SNR_THRESHOLD_float32_t 80
+#define DCT4_TRANSFORM_SNR_THRESHOLD_q31_t 75
+#define DCT4_TRANSFORM_SNR_THRESHOLD_q15_t 11
+
+/**
+ * Compare the outputs from the function under test and the reference
+ * function using SNR.
+ */
+#define TRANSFORM_SNR_COMPARE_INTERFACE(block_size, \
+ output_type) \
+ do \
+ { \
+ TEST_CONVERT_AND_ASSERT_SNR( \
+ transform_fft_output_f32_ref, \
+ (output_type *) transform_fft_output_ref, \
+ transform_fft_output_f32_fut, \
+ (output_type *) transform_fft_output_fut, \
+ block_size, \
+ output_type, \
+ TRANSFORM_SNR_THRESHOLD_##output_type \
+ ); \
+ } while (0)
+
+/**
+ * Compare the outputs from the function under test and the reference
+ * function using SNR.
+ */
+#define DCT_TRANSFORM_SNR_COMPARE_INTERFACE(block_size, \
+ output_type) \
+ do \
+ { \
+ TEST_CONVERT_AND_ASSERT_SNR( \
+ transform_fft_output_f32_ref, \
+ (output_type *) transform_fft_output_ref, \
+ transform_fft_output_f32_fut, \
+ (output_type *) transform_fft_output_fut, \
+ block_size, \
+ output_type, \
+ DCT4_TRANSFORM_SNR_THRESHOLD_##output_type \
+ ); \
+ } while (0) \
+
+/**
+ * Specialization on #TRANSFORM_SNR_COMPARE_INTERFACE() to fix the block_size
+ * for complex datasets.
+ */
+#define TRANSFORM_SNR_COMPARE_CMPLX_INTERFACE(block_size, output_type) \
+ /* Complex numbers have two components*/ \
+ TRANSFORM_SNR_COMPARE_INTERFACE(block_size * 2, output_type )
+
+/**
+ * This macro copys data from the input_ptr into input arrays.
+ *
+ * Some functions modify their input data; in order to provide the same data to
+ * multiple tests, copies must be made so the changes from one function don't
+ * impact the others.
+ */
+#define TRANSFORM_COPY_INPUTS(input_ptr, \
+ bytes) \
+ do \
+ { \
+ memcpy( \
+ transform_fft_input_fut, \
+ input_ptr, \
+ bytes); \
+ memcpy( \
+ transform_fft_input_ref, \
+ input_ptr, \
+ bytes); \
+ } while (0)
+
+/**
+ * This macro copys data from the input_ptr into input arrays. It also creates
+ * symmetric input data for rfft inverse.
+ *
+ * The 4.534234f just makes the middle entry of the array semi random. It's
+ * actual value doesn't seem to matter much.
+ *
+ * Some functions modify their input data; in order to provide the same data to
+ * multiple tests, copies must be made so the changes from one function don't
+ * impact the others.
+ */
+#define TRANSFORM_PREPARE_INVERSE_INPUTS(input_ptr, \
+ fftlen, input_type, bytes) \
+ do \
+ { \
+ uint32_t i; \
+ \
+ memcpy( \
+ transform_fft_input_fut, \
+ input_ptr, \
+ bytes); \
+ \
+ ((input_type*)transform_fft_input_fut)[1] = 0; \
+ ((input_type*)transform_fft_input_fut)[fftlen + 0] = 0; \
+ ((input_type*)transform_fft_input_fut)[fftlen + 1] = 0; \
+ for(i=1;i<fftlen/2;i++) \
+ { \
+ *((input_type*)transform_fft_input_fut + fftlen + 2*i + 0) = \
+ *((input_type*)transform_fft_input_fut + fftlen - 2*i + 0); \
+ *((input_type*)transform_fft_input_fut + fftlen + 2*i + 1) = \
+ -(*((input_type*)transform_fft_input_fut + fftlen - 2*i + 1)); \
+ \
+ } \
+ \
+ memcpy( \
+ transform_fft_input_ref, \
+ transform_fft_input_fut, \
+ bytes * 2); \
+ } while (0)
+
+/**
+ * This macro copys data from the input_ptr into the in-place input arrays.
+ *
+ * Some functions modify their input data; in order to provide the same data to
+ * multiple tests, copies must be made so the changes from one function don't
+ * impact the others.
+ */
+#define TRANSFORM_PREPARE_INPLACE_INPUTS_DOWNSHIFT(input_ptr, \
+ bytes, \
+ type) \
+ do \
+ { \
+ uint32_t i; \
+ memcpy( \
+ transform_fft_inplace_input_fut, \
+ input_ptr, \
+ bytes); \
+ memcpy( \
+ transform_fft_inplace_input_ref, \
+ input_ptr, \
+ bytes); \
+ for(i=0;i<bytes/sizeof(type);i++) { \
+ *((type*)transform_fft_inplace_input_fut + i) >>= 1; \
+ *((type*)transform_fft_inplace_input_ref + i) >>= 1;} \
+ } while (0)
+
+/**
+ * This macro copys data from the input_ptr into the in-place input arrays.
+ *
+ * Some functions modify their input data; in order to provide the same data to
+ * multiple tests, copies must be made so the changes from one function don't
+ * impact the others.
+ */
+#define TRANSFORM_PREPARE_INPLACE_INPUTS(input_ptr, \
+ bytes) \
+ do \
+ { \
+ memcpy( \
+ transform_fft_inplace_input_fut, \
+ input_ptr, \
+ bytes); \
+ memcpy( \
+ transform_fft_inplace_input_ref, \
+ input_ptr, \
+ bytes); \
+ } while (0)
+
+
+#endif /* _TRANSFORM_TEMPLATES_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_test_data.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_test_data.h
new file mode 100644
index 0000000..bda5e12
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_test_data.h
@@ -0,0 +1,48 @@
+#ifndef _TRANSFORM_TEST_DATA_H_
+#define _TRANSFORM_TEST_DATA_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "arr_desc.h"
+#include "arm_math.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+#define TRANSFORM_MAX_FFT_LEN 4096
+#define TRANFORM_BIGGEST_INPUT_TYPE float32_t
+
+/*--------------------------------------------------------------------------------*/
+/* Variable Declarations */
+/*--------------------------------------------------------------------------------*/
+
+/* Lengths are multiplied by 2 to accomodate complex numbers*/
+extern float32_t transform_fft_output_fut[TRANSFORM_MAX_FFT_LEN * 2];
+extern float32_t transform_fft_output_ref[TRANSFORM_MAX_FFT_LEN * 2];
+extern float32_t transform_fft_input_fut[TRANSFORM_MAX_FFT_LEN * 2];
+extern float32_t transform_fft_input_ref[TRANSFORM_MAX_FFT_LEN * 2];
+extern float32_t transform_fft_output_f32_fut[TRANSFORM_MAX_FFT_LEN * 2];
+extern float32_t transform_fft_output_f32_ref[TRANSFORM_MAX_FFT_LEN * 2];
+extern float32_t * transform_fft_inplace_input_fut;
+extern float32_t * transform_fft_inplace_input_ref;
+extern float32_t transform_fft_f32_inputs[TRANSFORM_MAX_FFT_LEN * 2];
+extern q31_t transform_fft_q31_inputs[TRANSFORM_MAX_FFT_LEN * 2];
+extern q15_t * transform_fft_q15_inputs;
+extern q15_t dct4_transform_fft_q15_inputs[TRANSFORM_MAX_FFT_LEN * 2];
+
+/* FFT Lengths */
+ARR_DESC_DECLARE(transform_radix2_fftlens);
+ARR_DESC_DECLARE(transform_radix4_fftlens);
+ARR_DESC_DECLARE(transform_rfft_fftlens);
+ARR_DESC_DECLARE(transform_rfft_fast_fftlens);
+ARR_DESC_DECLARE(transform_dct_fftlens);
+
+/* CFFT Structs */
+ARR_DESC_DECLARE(transform_cfft_f32_structs);
+ARR_DESC_DECLARE(transform_cfft_q31_structs);
+ARR_DESC_DECLARE(transform_cfft_q15_structs);
+
+#endif /* _TRANSFORM_TEST_DATA_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_test_group.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_test_group.h
new file mode 100644
index 0000000..c1c7c9e
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_test_group.h
@@ -0,0 +1,9 @@
+#ifndef _TRANSFORM_TEST_GROUP_H_
+#define _TRANSFORM_TEST_GROUP_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Test Groups */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(transform_tests);
+
+#endif /* _TRANSFORM_TEST_GROUP_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_tests.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_tests.h
new file mode 100644
index 0000000..874c83f
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_tests.h
@@ -0,0 +1,13 @@
+#ifndef _TRANSFORM_TESTS_H_
+#define _TRANSFORM_TESTS_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Test/Group Declarations */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(cfft_tests);
+JTEST_DECLARE_GROUP(cfft_family_tests);
+JTEST_DECLARE_GROUP(dct4_tests);
+JTEST_DECLARE_GROUP(rfft_tests);
+JTEST_DECLARE_GROUP(rfft_fast_tests);
+
+#endif /* _TRANSFORM_TESTS_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/type_abbrev.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/type_abbrev.h
new file mode 100644
index 0000000..5909124
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/type_abbrev.h
@@ -0,0 +1,37 @@
+#ifndef _TYPE_ABBREV_H_
+#define _TYPE_ABBREV_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Expand the abbreviation for a type into the type itself.
+ */
+#define TYPE_FROM_ABBREV(abbrev) \
+ TYPE_ABBREV_##abbrev \
+
+/**
+ * Expand the type to an abbreviation for that type.
+ *
+ * Inverse of #TYPE_FROM_ABBREV().
+ *
+ * @note Should be able to get a type back by writing.
+ * TYPE_FROM_ABBREV(ABBREV_FROM_TYPE(type))
+ */
+#define ABBREV_FROM_TYPE(type) \
+ TYPE_SUFFIX_##type
+
+#define TYPE_ABBREV_f64 float64_t
+#define TYPE_ABBREV_f32 float32_t
+#define TYPE_ABBREV_q31 q31_t
+#define TYPE_ABBREV_q15 q15_t
+#define TYPE_ABBREV_q7 q7_t
+
+#define TYPE_SUFFIX_float64_t f64
+#define TYPE_SUFFIX_float32_t f32
+#define TYPE_SUFFIX_q31_t q31
+#define TYPE_SUFFIX_q15_t q15
+#define TYPE_SUFFIX_q7_t q7
+
+#endif /* _TYPE_ABBREV_H_ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/Retarget.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/Retarget.c
new file mode 100644
index 0000000..ffac3df
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/Retarget.c
@@ -0,0 +1,52 @@
+/*----------------------------------------------------------------------------
+ * Name: Retarget.c
+ * Purpose: 'Retarget' layer for target-dependent low level functions
+ * Note(s):
+ *----------------------------------------------------------------------------
+ * This file is part of the uVision/ARM development tools.
+ * This software may only be used under the terms of a valid, current,
+ * end user licence from KEIL for a compatible version of KEIL software
+ * development tools. Nothing else gives you the right to use this software.
+ *
+ * This software is supplied "AS IS" without warranties of any kind.
+ *
+ * Copyright (c) 2011 Keil - An ARM Company. All rights reserved.
+ *----------------------------------------------------------------------------*/
+
+#include <stdio.h>
+#include <rt_misc.h>
+#include "Serial.h"
+
+#pragma import(__use_no_semihosting_swi)
+
+
+
+struct __FILE { int handle; /* Add whatever you need here */ };
+FILE __stdout;
+FILE __stdin;
+
+
+int fputc(int c, FILE *f) {
+ return (SER_PutChar(c));
+}
+
+
+int fgetc(FILE *f) {
+ return (SER_GetChar());
+}
+
+
+int ferror(FILE *f) {
+ /* Your implementation of ferror */
+ return EOF;
+}
+
+
+void _ttywrch(int c) {
+ SER_PutChar(c);
+}
+
+
+void _sys_exit(int return_code) {
+label: goto label; /* endless loop */
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv6-m.s b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv6-m.s
new file mode 100644
index 0000000..fa814eb
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv6-m.s
@@ -0,0 +1,195 @@
+;/* File: startup_armv6-m.s
+; * Purpose: startup file for armv7-m architecture devices.
+; * Should be used with ARMCC
+; * Version: V2.00
+; * Date: 16 November 2015
+; *
+; */
+;/* Copyright (c) 2011 - 2014 ARM LIMITED
+;
+; All rights reserved.
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; - Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; - Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; - Neither the name of ARM nor the names of its contributors may be used
+; to endorse or promote products derived from this software without
+; specific prior written permission.
+; *
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; POSSIBILITY OF SUCH DAMAGE.
+; ---------------------------------------------------------------------------*/
+;/*
+; //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000C00
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ BKPT #0
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ BKPT #0
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+ ALIGN
+
+; User Initial Stack & Heap
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+
+;/*
+; __user_setup_stackheap() returns the:
+; - heap base in r0 (if the program uses the heap)
+; - stack base in sp
+; - heap limit in r2 (if the program uses the heap and uses two-region memory).
+; */
+ EXPORT __user_setup_stackheap
+
+__user_setup_stackheap PROC
+ LDR R0, = __initial_sp
+ MOV SP, R0
+ IF Heap_Size > 0
+ LDR R2, = __heap_limit
+ LDR R0, = __heap_base
+ ELSE
+ MOV R0, #0
+ MOV R2, #0
+ ENDIF
+ BX LR
+ ENDP
+
+
+;/*
+;__user_initial_stackheap() returns the:
+; - heap base in r0
+; - stack base in r1, that is, the highest address in the stack region
+; - heap limit in r2
+; - stack limit in r3, that is, the lowest address in the stack region.
+; */
+;
+;/* DEPRICATED
+; EXPORT __user_initial_stackheap
+;
+;__user_initial_stackheap PROC
+; LDR R0, = Heap_Mem
+; LDR R1, =(Stack_Mem + Stack_Size)
+; LDR R2, = (Heap_Mem + Heap_Size)
+; LDR R3, = Stack_Mem
+; BX LR
+; ENDP
+; */
+
+ ALIGN
+
+ ENDIF
+
+
+ END
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv7-m.s b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv7-m.s
new file mode 100644
index 0000000..899f2de
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv7-m.s
@@ -0,0 +1,218 @@
+;/* File: startup_armv7-m.s
+; * Purpose: startup file for armv7-m architecture devices.
+; * Should be used with ARMCC
+; * Version: V2.00
+; * Date: 16 November 2015
+; *
+; */
+;/* Copyright (c) 2011 - 2014 ARM LIMITED
+;
+; All rights reserved.
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; - Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; - Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; - Neither the name of ARM nor the names of its contributors may be used
+; to endorse or promote products derived from this software without
+; specific prior written permission.
+; *
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; POSSIBILITY OF SUCH DAMAGE.
+; ---------------------------------------------------------------------------*/
+;/*
+; //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000C00
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ BKPT #0
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ BKPT #0
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ BKPT #0
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ BKPT #0
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ BKPT #0
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+ ALIGN
+
+; User Initial Stack & Heap
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+
+;/*
+; __user_setup_stackheap() returns the:
+; - heap base in r0 (if the program uses the heap)
+; - stack base in sp
+; - heap limit in r2 (if the program uses the heap and uses two-region memory).
+; */
+ EXPORT __user_setup_stackheap
+
+__user_setup_stackheap PROC
+ LDR R0, = __initial_sp
+ MOV SP, R0
+ IF Heap_Size > 0
+ LDR R2, = __heap_limit
+ LDR R0, = __heap_base
+ ELSE
+ MOV R0, #0
+ MOV R2, #0
+ ENDIF
+ BX LR
+ ENDP
+
+
+;/*
+;__user_initial_stackheap() returns the:
+; - heap base in r0
+; - stack base in r1, that is, the highest address in the stack region
+; - heap limit in r2
+; - stack limit in r3, that is, the lowest address in the stack region.
+; */
+;
+;/* DEPRICATED
+; EXPORT __user_initial_stackheap
+;
+;__user_initial_stackheap PROC
+; LDR R0, = Heap_Mem
+; LDR R1, =(Stack_Mem + Stack_Size)
+; LDR R2, = (Heap_Mem + Heap_Size)
+; LDR R3, = Stack_Mem
+; BX LR
+; ENDP
+; */
+
+ ALIGN
+
+ ENDIF
+
+
+ END
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv6-m.S b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv6-m.S
new file mode 100644
index 0000000..2e60478
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv6-m.S
@@ -0,0 +1,203 @@
+/* File: startup_armv6-m.S
+ * Purpose: startup file for armv6-m architecture devices.
+ * Should be used with ARMCLANG
+ * Version: V2.00
+ * Date: 16 November 2015
+ *
+ */
+/* Copyright (c) 2011 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+/*
+ ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+
+ .syntax unified
+ .arch armv6-m
+
+/* .eabi_attribute Tag_ABI_align8_preserved,1 www.support.code-red-tech.com/CodeRedWiki/Preserve8 */
+.eabi_attribute 25, 1 /* Tag_ABI_align_preserved */
+
+
+/*
+ ;<h> Stack Configuration
+ ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ ;</h>
+*/
+ .equ Stack_Size, 0x00000400
+
+ .section STACK, "w"
+ .align 3
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+__StackTop: /* formerly known as __initial_sp */
+
+
+/*
+ ;<h> Heap Configuration
+ ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ ;</h>
+*/
+ .equ Heap_Size, 0x00000C00
+
+ .section HEAP, "w"
+ .align 3
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+__HeapLimit:
+
+
+ .section RESET, "x"
+ .align 2
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
+__Vectors:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+__Vectors_End:
+
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+
+
+ .text
+ .thumb
+ .align 2
+
+ .globl Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+ .thumb_func
+Reset_Handler:
+ bl SystemInit
+ bl __main
+
+ .globl NMI_Handler
+ .weak NMI_Handler
+ .type NMI_Handler, %function
+ .thumb_func
+NMI_Handler:
+ bkpt #0
+ b .
+
+ .globl HardFault_Handler
+ .weak HardFault_Handler
+ .type HardFault_Handler, %function
+ .thumb_func
+HardFault_Handler:
+ bkpt #0
+ b .
+
+ .globl SVC_Handler
+ .weak SVC_Handler
+ .type SVC_Handler, %function
+ .thumb_func
+SVC_Handler:
+ bkpt #0
+ b .
+
+ .globl PendSV_Handler
+ .weak PendSV_Handler
+ .type PendSV_Handler, %function
+ .thumb_func
+PendSV_Handler:
+ bkpt #0
+ b .
+
+ .globl SysTick_Handler
+ .weak SysTick_Handler
+ .type SysTick_Handler, %function
+ .thumb_func
+SysTick_Handler:
+ bkpt #0
+ b .
+
+
+ .global __use_two_region_memory
+
+/*
+ __user_setup_stackheap() returns the:
+ - heap base in r0 (if the program uses the heap)
+ - stack base in sp
+ - heap limit in r2 (if the program uses the heap and uses two-region memory).
+ */
+ .globl __user_setup_stackheap
+ .type __user_setup_stackheap, %function
+ .thumb_func
+__user_setup_stackheap:
+ ldr r0, =__StackTop
+ mov sp, r0
+ .if Heap_Size
+ ldr r0, =__HeapBase
+ ldr r2, =__HeapLimit
+ .else
+ mov r0, #0
+ mov r2, #0
+ .endif
+ bx lr
+
+
+/*
+__user_initial_stackheap() returns the:
+ - heap base in r0
+ - stack base in r1, that is, the highest address in the stack region
+ - heap limit in r2
+ - stack limit in r3, that is, the lowest address in the stack region.
+ */
+/* DEPRICATED
+ .globl __user_initial_stackheap
+ .type __user_initial_stackheap, %function
+ .thumb_func
+__user_initial_stackheap:
+ ldr r0, = __HeapBase
+ ldr r1, = __StackTop
+ ldr r2, = __HeapLimit
+ ldr r3, = __StackLimit
+ bx lr
+*/
+
+ .end
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv7-m.S b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv7-m.S
new file mode 100644
index 0000000..93ba4a9
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv7-m.S
@@ -0,0 +1,235 @@
+/* File: startup_armv7-m.S
+ * Purpose: startup file for armv7-m architecture devices.
+ * Should be used with ARMCLANG
+ * Version: V2.00
+ * Date: 16 November 2015
+ *
+ */
+/* Copyright (c) 2011 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+/*
+ ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+
+ .syntax unified
+ .arch armv6-m
+
+/* .eabi_attribute Tag_ABI_align8_preserved,1 www.support.code-red-tech.com/CodeRedWiki/Preserve8 */
+.eabi_attribute 25, 1 /* Tag_ABI_align_preserved */
+
+
+/*
+ ;<h> Stack Configuration
+ ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ ;</h>
+*/
+ .equ Stack_Size, 0x00000400
+
+ .section STACK, "w"
+ .align 3
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+__StackTop: /* formerly known as __initial_sp */
+
+
+/*
+ ;<h> Heap Configuration
+ ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ ;</h>
+*/
+ .equ Heap_Size, 0x00000C00
+
+ .section HEAP, "w"
+ .align 3
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+__HeapLimit:
+
+
+ .section RESET, "x"
+ .align 2
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
+__Vectors:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+__Vectors_End:
+
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+
+
+ .text
+ .thumb
+ .align 2
+
+ .globl Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+ .thumb_func
+Reset_Handler:
+ bl SystemInit
+ bl __main
+
+ .globl NMI_Handler
+ .weak NMI_Handler
+ .type NMI_Handler, %function
+ .thumb_func
+NMI_Handler:
+ bkpt #0
+ b .
+
+ .globl HardFault_Handler
+ .weak HardFault_Handler
+ .type HardFault_Handler, %function
+ .thumb_func
+HardFault_Handler:
+ bkpt #0
+ b .
+
+ .globl MemManage_Handler
+ .weak MemManage_Handler
+ .type MemManage_Handler, %function
+ .thumb_func
+MemManage_Handler:
+ bkpt #0
+ b .
+
+ .globl BusFault_Handler
+ .weak BusFault_Handler
+ .type BusFault_Handler, %function
+ .thumb_func
+BusFault_Handler:
+ bkpt #0
+ b .
+
+ .globl UsageFault_Handler
+ .weak UsageFault_Handler
+ .type UsageFault_Handler, %function
+ .thumb_func
+UsageFault_Handler:
+ bkpt #0
+ b .
+
+ .globl SVC_Handler
+ .weak SVC_Handler
+ .type SVC_Handler, %function
+ .thumb_func
+SVC_Handler:
+ bkpt #0
+ b .
+
+ .globl DebugMon_Handler
+ .weak DebugMon_Handler
+ .type DebugMon_Handler, %function
+ .thumb_func
+DebugMon_Handler:
+ bkpt #0
+ b .
+
+ .globl PendSV_Handler
+ .weak PendSV_Handler
+ .type PendSV_Handler, %function
+ .thumb_func
+PendSV_Handler:
+ bkpt #0
+ b .
+
+ .globl SysTick_Handler
+ .weak SysTick_Handler
+ .type SysTick_Handler, %function
+ .thumb_func
+SysTick_Handler:
+ bkpt #0
+ b .
+
+
+ .global __use_two_region_memory
+
+/*
+ __user_setup_stackheap() returns the:
+ - heap base in r0 (if the program uses the heap)
+ - stack base in sp
+ - heap limit in r2 (if the program uses the heap and uses two-region memory).
+ */
+ .globl __user_setup_stackheap
+ .type __user_setup_stackheap, %function
+ .thumb_func
+__user_setup_stackheap:
+ ldr r0, =__StackTop
+ mov sp, r0
+ .if Heap_Size
+ ldr r0, =__HeapBase
+ ldr r2, =__HeapLimit
+ .else
+ mov r0, #0
+ mov r2, #0
+ .endif
+ bx lr
+
+
+/*
+__user_initial_stackheap() returns the:
+ - heap base in r0
+ - stack base in r1, that is, the highest address in the stack region
+ - heap limit in r2
+ - stack limit in r3, that is, the lowest address in the stack region.
+ */
+/* DEPRICATED
+ .globl __user_initial_stackheap
+ .type __user_initial_stackheap, %function
+ .thumb_func
+__user_initial_stackheap:
+ ldr r0, = __HeapBase
+ ldr r1, = __StackTop
+ ldr r2, = __HeapLimit
+ ldr r3, = __StackLimit
+ bx lr
+*/
+
+ .end
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/Retarget.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/Retarget.c
new file mode 100644
index 0000000..0ab6c13
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/Retarget.c
@@ -0,0 +1,106 @@
+/*----------------------------------------------------------------------------
+ * Name: Retarget.c
+ * Purpose: 'Retarget' layer for target-dependent low level functions
+ * Note(s):
+ *----------------------------------------------------------------------------
+ * This file is part of the uVision/ARM development tools.
+ * This software may only be used under the terms of a valid, current,
+ * end user licence from KEIL for a compatible version of KEIL software
+ * development tools. Nothing else gives you the right to use this software.
+ *
+ * This software is supplied "AS IS" without warranties of any kind.
+ *
+ * Copyright (c) 2012 Keil - An ARM Company. All rights reserved.
+ *----------------------------------------------------------------------------*/
+
+#include <sys/stat.h>
+#include <string.h>
+#include <errno.h>
+
+int SER_PutChar (int c) {
+
+ return (c);
+}
+
+int SER_GetChar (void) {
+
+ return (-1);
+}
+
+/*-- GCC - Newlib runtime support --------------------------------------------*/
+
+extern int __HeapBase;
+extern int __HeapLimit;
+
+int _open (const char * path, int flags, ...)
+{
+ return (-1);
+}
+
+int _close (int fd)
+{
+ return (-1);
+}
+
+int _lseek (int fd, int ptr, int dir)
+{
+ return (0);
+}
+
+int __attribute__((weak)) _fstat (int fd, struct stat * st)
+{
+ memset (st, 0, sizeof (* st));
+ st->st_mode = S_IFCHR;
+ return (0);
+}
+
+int _isatty (int fd)
+{
+ return (1);
+}
+
+int _read (int fd, char * ptr, int len)
+{
+ char c;
+ int i;
+
+ for (i = 0; i < len; i++)
+ {
+ c = SER_GetChar();
+ if (c == 0x0D) break;
+ *ptr++ = c;
+ SER_PutChar(c);
+ }
+ return (len - i);
+}
+
+int _write (int fd, char * ptr, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++) SER_PutChar (*ptr++);
+ return (i);
+}
+
+caddr_t _sbrk (int incr)
+{
+ static char * heap;
+ char * prev_heap;
+
+ if (heap == NULL)
+ {
+ heap = (char *)&__HeapBase;
+ }
+
+ prev_heap = heap;
+
+ if ((heap + incr) > (char *)&__HeapLimit)
+ {
+ errno = ENOMEM;
+ return (caddr_t) -1;
+ }
+
+ heap += incr;
+
+ return (caddr_t) prev_heap;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv6-m.S b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv6-m.S
new file mode 100644
index 0000000..c928912
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv6-m.S
@@ -0,0 +1,263 @@
+/* File: startup_armv6-m.S
+ * Purpose: startup file for armv6-m architecture devices.
+ * Should be used with GCC for ARM Embedded Processors
+ * Version: V2.00
+ * Date: 16 November 2015
+ *
+ */
+/* Copyright (c) 2011 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+ .syntax unified
+ .arch armv6-m
+
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x00000400
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x00000C00
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ .size __Vectors, . - __Vectors
+
+ .text
+ .thumb
+ .thumb_func
+ .align 1
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ blt .L_loop0_0_done
+ ldr r0, [r1, r3]
+ str r0, [r2, r3]
+ b .L_loop0_0
+
+.L_loop0_0_done:
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .L_loop1_done
+
+.L_loop1:
+ subs r3, #4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .L_loop1
+
+.L_loop1_done:
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ blt .L_loop2_0_done
+ str r0, [r1, r2]
+ b .L_loop2_0
+.L_loop2_0_done:
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+
+ subs r2, r1
+ ble .L_loop3_done
+
+.L_loop3:
+ subs r2, #4
+ str r0, [r1, r2]
+ bgt .L_loop3
+.L_loop3_done:
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifndef __NO_SYSTEM_INIT
+ bl SystemInit
+#endif
+
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+ .thumb_func
+ .weak Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ bkpt #0
+ b .
+ .size Default_Handler, . - Default_Handler
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_handler NMI_Handler
+ def_irq_handler HardFault_Handler
+ def_irq_handler SVC_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ .end
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv7-m.S b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv7-m.S
new file mode 100644
index 0000000..2320877
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv7-m.S
@@ -0,0 +1,257 @@
+/* File: startup_armv7-m.S
+ * Purpose: startup file for armv7-m architecture devices.
+ * Should be used with GCC for ARM Embedded Processors
+ * Version: V2.00
+ * Date: 16 November 2015
+ *
+ */
+/* Copyright (c) 2011 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+ .syntax unified
+ .arch armv7-m
+
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x00000400
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x00000C00
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ .size __Vectors, . - __Vectors
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.L_loop1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.L_loop3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifndef __NO_SYSTEM_INIT
+ bl SystemInit
+#endif
+
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+ .thumb_func
+ .weak Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ bkpt #0
+ b .
+ .size Default_Handler, . - Default_Handler
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_handler NMI_Handler
+ def_irq_handler HardFault_Handler
+ def_irq_handler MemManage_Handler
+ def_irq_handler BusFault_Handler
+ def_irq_handler UsageFault_Handler
+ def_irq_handler SVC_Handler
+ def_irq_handler DebugMon_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ .end
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/startup_generic.S b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/startup_generic.S
new file mode 100644
index 0000000..1826a78
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/startup_generic.S
@@ -0,0 +1,62 @@
+
+#if defined (__CC_ARM)
+ #if (defined (ARM_MATH_CM0))
+ #include "ARMCC\startup_armv6-m.s"
+ #elif (defined (ARM_MATH_CM0P))
+ #include "ARMCC\startup_armv6-m.s"
+ #elif (defined (ARM_MATH_CM3))
+ #include "ARMCC\startup_armv7-m.s"
+ #elif (defined (ARM_MATH_CM4))
+ #include "ARMCC\startup_armv7-m.s"
+ #elif (defined (ARM_MATH_CM7))
+ #include "ARMCC\startup_armv7-m.s"
+ #elif (defined (ARM_MATH_ARMV8MBL))
+ #include "ARMCC\startup_armv6-m.s"
+ #elif (defined (ARM_MATH_ARMV8MML))
+ #include "ARMCC\startup_armv7-m.s"
+ #else
+ #error "No appropriate startup file found!"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if (defined (ARM_MATH_CM0))
+ #include "ARMCLANG\startup_armv6-m.S"
+ #elif (defined (ARM_MATH_CM0P))
+ #include "ARMCLANG\startup_armv6-m.S"
+ #elif (defined (ARM_MATH_CM3))
+ #include "ARMCLANG\startup_armv7-m.S"
+ #elif (defined (ARM_MATH_CM4))
+ #include "ARMCLANG\startup_armv7-m.S"
+ #elif (defined (ARM_MATH_CM7))
+ #include "ARMCLANG\startup_armv7-m.S"
+ #elif (defined (ARM_MATH_ARMV8MBL))
+ #include "ARMCLANG\startup_armv6-m.S"
+ #elif (defined (ARM_MATH_ARMV8MML))
+ #include "ARMCLANG\startup_armv7-m.S"
+ #else
+ #error "No appropriate startup file found!"
+ #endif
+
+#elif defined (__GNUC__)
+ #if (defined (ARM_MATH_CM0))
+ #include "GCC\startup_armv6-m.S"
+ #elif (defined (ARM_MATH_CM0P))
+ #include "GCC\startup_armv6-m.S"
+ #elif (defined (ARM_MATH_CM3))
+ #include "GCC\startup_armv7-m.S"
+ #elif (defined (ARM_MATH_CM4))
+ #include "GCC\startup_armv7-m.S"
+ #elif (defined (ARM_MATH_CM7))
+ #include "GCC\startup_armv7-m.S"
+ #elif (defined (ARM_MATH_ARMV8MBL))
+ #include "GCC\startup_armv6-m.S"
+ #elif (defined (ARM_MATH_ARMV8MML))
+ #include "GCC\startup_armv7-m.S"
+ #else
+ #error "No appropriate startup file found!"
+ #endif
+
+#else
+ #error "Compiler not supported!"
+#endif
+
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM0.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM0.c
new file mode 100644
index 0000000..b272255
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM0.c
@@ -0,0 +1,56 @@
+/**************************************************************************//**
+ * @file system_ARMCM0.c
+ * @brief CMSIS Device System Source File for
+ * ARMCM0 Device Series
+ * @version V5.00
+ * @date 07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ARMCM0.h"
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL ( 5000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM23.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM23.c
new file mode 100644
index 0000000..791ee34
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM23.c
@@ -0,0 +1,82 @@
+/**************************************************************************//**
+ * @file system_ARMCM23.c
+ * @brief CMSIS Device System Source File for
+ * ARMCM23 Device Series
+ * @version V5.00
+ * @date 21. October 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM23)
+ #include "ARMCM23.h"
+#elif defined (ARMCM23_TZ)
+ #include "ARMCM23_TZ.h"
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #include "partition_ARMCM23.h"
+ #endif
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL ( 5000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+ Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ TZ_SAU_Setup();
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM3.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM3.c
new file mode 100644
index 0000000..2544c43
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM3.c
@@ -0,0 +1,68 @@
+/**************************************************************************//**
+ * @file system_ARMCM3.c
+ * @brief CMSIS Device System Source File for
+ * ARMCM3 Device Series
+ * @version V5.00
+ * @date 07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ARMCM3.h"
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL ( 5000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+ Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM33.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM33.c
new file mode 100644
index 0000000..287119c
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM33.c
@@ -0,0 +1,99 @@
+/**************************************************************************//**
+ * @file system_ARMCM33.c
+ * @brief CMSIS Device System Source File for
+ * ARMCM33 Device Series
+ * @version V5.00
+ * @date 02. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM33)
+ #include "ARMCM33.h"
+#elif defined (ARMCM33_TZ)
+ #include "ARMCM33_TZ.h"
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #include "partition_ARMCM33.h"
+ #endif
+#elif defined (ARMCM33_DSP_FP)
+ #include "ARMCM33_DSP_FP.h"
+#elif defined (ARMCM33_DSP_FP_TZ)
+ #include "ARMCM33_DSP_FP_TZ.h"
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #include "partition_ARMCM33.h"
+ #endif
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL ( 5000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+ Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+ SCB->CPACR |= ((3U << 10U*2U) | /* set CP10 Full Access */
+ (3U << 11U*2U) ); /* set CP11 Full Access */
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ TZ_SAU_Setup();
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM4.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM4.c
new file mode 100644
index 0000000..cea212e
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM4.c
@@ -0,0 +1,83 @@
+/**************************************************************************//**
+ * @file system_ARMCM4.c
+ * @brief CMSIS Device System Source File for
+ * ARMCM4 Device Series
+ * @version V5.00
+ * @date 07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM4)
+ #include "ARMCM4.h"
+#elif defined (ARMCM4_FP)
+ #include "ARMCM4_FP.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL ( 5000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+ Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+ SCB->CPACR |= ((3U << 10U*2U) | /* set CP10 Full Access */
+ (3U << 11U*2U) ); /* set CP11 Full Access */
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM7.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM7.c
new file mode 100644
index 0000000..6a99c08
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM7.c
@@ -0,0 +1,85 @@
+/**************************************************************************//**
+ * @file system_ARMCM7.c
+ * @brief CMSIS Device System Source File for
+ * ARMCM7 Device Series
+ * @version V5.00
+ * @date 07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM7)
+ #include "ARMCM7.h"
+#elif defined (ARMCM7_SP)
+ #include "ARMCM7_SP.h"
+#elif defined (ARMCM7_DP)
+ #include "ARMCM7_DP.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL ( 5000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+ Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+ SCB->CPACR |= ((3U << 10U*2U) | /* set CP10 Full Access */
+ (3U << 11U*2U) ); /* set CP11 Full Access */
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC000.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC000.c
new file mode 100644
index 0000000..7fda345
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC000.c
@@ -0,0 +1,56 @@
+/**************************************************************************//**
+ * @file system_ARMSC000.c
+ * @brief CMSIS Device System Source File for
+ * for ARMSC000 Device Series
+ * @version V5.00
+ * @date 07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ARMSC000.h"
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL ( 5000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC300.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC300.c
new file mode 100644
index 0000000..3db4ee7
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC300.c
@@ -0,0 +1,72 @@
+/**************************************************************************//**
+ * @file system_ARMSC300.c
+ * @brief CMSIS Device System Source File for
+ * ARMSC300 Device Series
+ * @version V5.00
+ * @date 07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ARMSC300.h"
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL ( 5000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+ Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MBL.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MBL.c
new file mode 100644
index 0000000..8310b8f
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MBL.c
@@ -0,0 +1,76 @@
+/**************************************************************************//**
+ * @file system_ARMv8MBL.c
+ * @brief CMSIS Device System Source File for
+ * ARMv8MBL Device Series
+ * @version V5.00
+ * @date 07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ARMv8MBL.h"
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #include "partition_ARMv8MBL.h"
+#endif
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL ( 5000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+ Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ TZ_SAU_Setup();
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MML.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MML.c
new file mode 100644
index 0000000..bd77100
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MML.c
@@ -0,0 +1,99 @@
+/**************************************************************************//**
+ * @file system_ARMv8MML.c
+ * @brief CMSIS Device System Source File for
+ * ARMv8MML Device Series
+ * @version V5.00
+ * @date 02. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMv8MML)
+ #include "ARMv8MML.h"
+#elif defined (ARMv8MML_DSP)
+ #include "ARMv8MML_DSP.h"
+#elif defined (ARMv8MML_SP)
+ #include "ARMv8MML_SP.h"
+#elif defined (ARMv8MML_DSP_SP)
+ #include "ARMv8MML_DSP_SP.h"
+#elif defined (ARMv8MML_DP)
+ #include "ARMv8MML_DP.h"
+#elif defined (ARMv8MML_DSP_DP)
+ #include "ARMv8MML_DSP_DP.h"
+#else
+ #error device not specified!
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #include "partition_ARMv8MML.h"
+#endif
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL ( 5000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+ Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+ SCB->CPACR |= ((3U << 10U*2U) | /* set CP10 Full Access */
+ (3U << 11U*2U) ); /* set CP11 Full Access */
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ TZ_SAU_Setup();
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_generic.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_generic.c
new file mode 100644
index 0000000..37d82ab
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_generic.c
@@ -0,0 +1,27 @@
+
+#if (defined (ARMCM0))
+ #include "system_ARMCM0.c"
+
+#elif (defined (ARMCM0P))
+ #include "system_ARMCM0plus.c"
+
+#elif (defined (ARMCM3))
+ #include "system_ARMCM3.c"
+
+#elif (defined (ARMCM4) || defined (ARMCM4_FP))
+ #include "system_ARMCM4.c"
+
+#elif (defined (ARMCM7) || defined (ARMCM7_SP) || defined (ARMCM7_DP))
+ #include "system_ARMCM7.c"
+
+#elif defined (ARMv8MBL)
+ #include "system_ARMv8MBL.c"
+
+#elif (defined (ARMv8MML) || defined (ARMv8MML_DSP) || \
+ defined (ARMv8MML_SP) || defined (ARMv8MML_DSP_SP) || \
+ defined (ARMv8MML_DP) || defined (ARMv8MML_DSP_DP) )
+ #include "system_ARMv8MML.c"
+
+#else
+ #error "No appropriate system file found!"
+#endif
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/all_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/all_tests.c
new file mode 100644
index 0000000..7b7a8fd
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/all_tests.c
@@ -0,0 +1,30 @@
+#include "jtest.h"
+#include "basic_math_test_group.h"
+#include "complex_math_test_group.h"
+#include "controller_test_group.h"
+#include "fast_math_test_group.h"
+#include "filtering_test_group.h"
+#include "matrix_test_group.h"
+#include "statistics_test_group.h"
+#include "support_test_group.h"
+#include "transform_test_group.h"
+#include "intrinsics_test_group.h"
+
+JTEST_DEFINE_GROUP(all_tests)
+{
+ /*
+ To skip a test, comment it out
+ */
+ JTEST_GROUP_CALL(basic_math_tests);
+ JTEST_GROUP_CALL(complex_math_tests);
+ JTEST_GROUP_CALL(controller_tests);
+ JTEST_GROUP_CALL(fast_math_tests);
+ JTEST_GROUP_CALL(filtering_tests);
+ JTEST_GROUP_CALL(matrix_tests);
+ JTEST_GROUP_CALL(statistics_tests);
+ JTEST_GROUP_CALL(support_tests);
+ JTEST_GROUP_CALL(transform_tests);
+ JTEST_GROUP_CALL(intrinsics_tests);
+
+ return;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/abs_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/abs_tests.c
new file mode 100644
index 0000000..6e6bedb
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/abs_tests.c
@@ -0,0 +1,32 @@
+#include "jtest.h"
+#include "basic_math_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "basic_math_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_ABS_TEST(suffix) \
+ BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_BLK( \
+ abs, \
+ suffix, \
+ TYPE_FROM_ABBREV(suffix), \
+ TYPE_FROM_ABBREV(suffix))
+
+JTEST_ARM_ABS_TEST(f32);
+JTEST_ARM_ABS_TEST(q31);
+JTEST_ARM_ABS_TEST(q15);
+JTEST_ARM_ABS_TEST(q7 );
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(abs_tests)
+{
+ JTEST_TEST_CALL(arm_abs_f32_test);
+ JTEST_TEST_CALL(arm_abs_q31_test);
+ JTEST_TEST_CALL(arm_abs_q15_test);
+ JTEST_TEST_CALL(arm_abs_q7_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/add_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/add_tests.c
new file mode 100644
index 0000000..a2d043c
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/add_tests.c
@@ -0,0 +1,33 @@
+#include "jtest.h"
+#include "basic_math_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "basic_math_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_ADD_TEST(suffix) \
+ BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK( \
+ add, \
+ suffix, \
+ TYPE_FROM_ABBREV(suffix), \
+ TYPE_FROM_ABBREV(suffix), \
+ BASIC_MATH_COMPARE_INTERFACE)
+
+JTEST_ARM_ADD_TEST(f32);
+JTEST_ARM_ADD_TEST(q31);
+JTEST_ARM_ADD_TEST(q15);
+JTEST_ARM_ADD_TEST(q7);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(add_tests)
+{
+ JTEST_TEST_CALL(arm_add_f32_test);
+ JTEST_TEST_CALL(arm_add_q31_test);
+ JTEST_TEST_CALL(arm_add_q15_test);
+ JTEST_TEST_CALL(arm_add_q7_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_common_data.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_common_data.c
new file mode 100644
index 0000000..86728f9
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_common_data.c
@@ -0,0 +1,101 @@
+#include "basic_math_test_data.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Input/Output Buffers */
+/*--------------------------------------------------------------------------------*/
+
+ARR_DESC_DEFINE(BASIC_MATH_BIGGEST_INPUT_TYPE,
+ basic_math_output_fut,
+ BASIC_MATH_MAX_INPUT_ELEMENTS,
+ CURLY(0));
+
+ARR_DESC_DEFINE(BASIC_MATH_BIGGEST_INPUT_TYPE,
+ basic_math_output_ref,
+ BASIC_MATH_MAX_INPUT_ELEMENTS,
+ CURLY(0));
+
+BASIC_MATH_BIGGEST_INPUT_TYPE
+basic_math_output_f32_ref[BASIC_MATH_MAX_INPUT_ELEMENTS];
+
+BASIC_MATH_BIGGEST_INPUT_TYPE
+basic_math_output_f32_fut[BASIC_MATH_MAX_INPUT_ELEMENTS];
+
+/*--------------------------------------------------------------------------------*/
+/* Block Sizes */
+/*--------------------------------------------------------------------------------*/
+
+/*
+ To change test parameter values add/remove values inside CURLY and update
+ the preceeding parameter to reflect the number of values inside CURLY.
+*/
+
+ARR_DESC_DEFINE(uint32_t,
+ basic_math_block_sizes,
+ 4,
+ CURLY( 2, 7, 15, 32));
+
+/*--------------------------------------------------------------------------------*/
+/* Numbers */
+/*--------------------------------------------------------------------------------*/
+
+/*
+ To change test parameter values add/remove values inside CURLY and update
+ the preceeding parameter to reflect the number of values inside CURLY.
+*/
+
+ARR_DESC_DEFINE(uint32_t,
+ basic_math_elts,
+ 4,
+ CURLY( 0, 1, 0x80000000, 0x7fffffff));
+
+ARR_DESC_DEFINE(int8_t,
+ basic_math_elts2,
+ 5,
+ CURLY( 0, 3, -3, -7, 7));
+
+ARR_DESC_DEFINE(float32_t,
+ basic_math_eltsf,
+ 6,
+ CURLY( 0.0f, 1.0f, 1.254001, -1.665584, -127.435646, 245.34634267));
+
+/*--------------------------------------------------------------------------------*/
+/* Test Data */
+/*--------------------------------------------------------------------------------*/
+
+ARR_DESC_DEFINE(float32_t,
+ basic_math_f_32,
+ 32,
+ CURLY(
+ -0.432565, -1.665584, 0.125332, 0.287676, -1.146471,
+ 1.190915, 1.189164, -0.037633, 0.327292, 0.174639,
+ -0.186709, 0.725791, -0.588317, 2.183186, -0.136396,
+ 0.113931, 1.066768, 0.059281, -0.095648, -0.832349,
+ 0.294411, -1.336182, 0.714325, 1.623562, -0.691776,
+ 0.857997, 1.254001, -1.593730, -1.440964, 0.571148,
+ -0.399886, 0.689997
+ ));
+
+/* Alias the 32 element array with wrappers that end sooner. */
+ARR_DESC_DEFINE_SUBSET(basic_math_f_15,
+ basic_math_f_32,
+ 15);
+
+ARR_DESC_DEFINE_SUBSET(basic_math_f_2,
+ basic_math_f_32,
+ 2);
+
+ARR_DESC_DEFINE(float32_t,
+ basic_math_zeros,
+ 32,
+ CURLY(0));
+
+/* Aggregate all float datasets. */
+ARR_DESC_DEFINE(ARR_DESC_t *,
+ basic_math_f_all,
+ 4,
+ CURLY(
+ &basic_math_zeros,
+ &basic_math_f_2,
+ &basic_math_f_15,
+ &basic_math_f_32
+ ));
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_group.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_group.c
new file mode 100644
index 0000000..7b219fe
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_group.c
@@ -0,0 +1,17 @@
+#include "jtest.h"
+#include "basic_math_tests.h"
+
+JTEST_DEFINE_GROUP(basic_math_tests)
+{
+ JTEST_GROUP_CALL(abs_tests);
+ JTEST_GROUP_CALL(add_tests);
+ JTEST_GROUP_CALL(dot_prod_tests);
+ JTEST_GROUP_CALL(mult_tests);
+ JTEST_GROUP_CALL(negate_tests);
+ JTEST_GROUP_CALL(offset_tests);
+ JTEST_GROUP_CALL(scale_tests);
+ JTEST_GROUP_CALL(shift_tests);
+ JTEST_GROUP_CALL(sub_tests);
+
+ return;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/dot_prod_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/dot_prod_tests.c
new file mode 100644
index 0000000..ed758a1
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/dot_prod_tests.c
@@ -0,0 +1,33 @@
+#include "jtest.h"
+#include "basic_math_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "basic_math_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_DOT_PROD_TEST(suffix) \
+ BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK( \
+ dot_prod, \
+ suffix, \
+ TYPE_FROM_ABBREV(suffix), \
+ TYPE_FROM_ABBREV(suffix), \
+ BASIC_MATH_SNR_ELT1_COMPARE_INTERFACE)
+
+JTEST_ARM_DOT_PROD_TEST(f32);
+JTEST_ARM_DOT_PROD_TEST(q31);
+JTEST_ARM_DOT_PROD_TEST(q15);
+JTEST_ARM_DOT_PROD_TEST(q7);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(dot_prod_tests)
+{
+ JTEST_TEST_CALL(arm_dot_prod_f32_test);
+ JTEST_TEST_CALL(arm_dot_prod_q31_test);
+ JTEST_TEST_CALL(arm_dot_prod_q15_test);
+ JTEST_TEST_CALL(arm_dot_prod_q7_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/mult_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/mult_tests.c
new file mode 100644
index 0000000..a94bf68
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/mult_tests.c
@@ -0,0 +1,33 @@
+#include "jtest.h"
+#include "basic_math_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "basic_math_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_MULT_TEST(suffix, compare_interface) \
+ BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK( \
+ mult, \
+ suffix, \
+ TYPE_FROM_ABBREV(suffix), \
+ TYPE_FROM_ABBREV(suffix), \
+ compare_interface)
+
+JTEST_ARM_MULT_TEST(f32, BASIC_MATH_COMPARE_INTERFACE);
+JTEST_ARM_MULT_TEST(q31, BASIC_MATH_SNR_COMPARE_INTERFACE);
+JTEST_ARM_MULT_TEST(q15, BASIC_MATH_COMPARE_INTERFACE);
+JTEST_ARM_MULT_TEST(q7 , BASIC_MATH_COMPARE_INTERFACE);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(mult_tests)
+{
+ JTEST_TEST_CALL(arm_mult_f32_test);
+ JTEST_TEST_CALL(arm_mult_q31_test);
+ JTEST_TEST_CALL(arm_mult_q15_test);
+ JTEST_TEST_CALL(arm_mult_q7_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/negate_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/negate_tests.c
new file mode 100644
index 0000000..276cdac
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/negate_tests.c
@@ -0,0 +1,32 @@
+#include "jtest.h"
+#include "basic_math_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "basic_math_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_NEGATE_TEST(suffix) \
+ BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_BLK( \
+ negate, \
+ suffix, \
+ TYPE_FROM_ABBREV(suffix), \
+ TYPE_FROM_ABBREV(suffix))
+
+JTEST_ARM_NEGATE_TEST(f32);
+JTEST_ARM_NEGATE_TEST(q31);
+JTEST_ARM_NEGATE_TEST(q15);
+JTEST_ARM_NEGATE_TEST(q7);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(negate_tests)
+{
+ JTEST_TEST_CALL(arm_negate_f32_test);
+ JTEST_TEST_CALL(arm_negate_q31_test);
+ JTEST_TEST_CALL(arm_negate_q15_test);
+ JTEST_TEST_CALL(arm_negate_q7_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/offset_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/offset_tests.c
new file mode 100644
index 0000000..4e10f78
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/offset_tests.c
@@ -0,0 +1,33 @@
+#include "jtest.h"
+#include "basic_math_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "basic_math_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_OFFSET_TEST(suffix) \
+ BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_ELT1_BLK( \
+ offset, \
+ suffix, \
+ TYPE_FROM_ABBREV(suffix), \
+ TYPE_FROM_ABBREV(suffix), \
+ TYPE_FROM_ABBREV(suffix))
+
+JTEST_ARM_OFFSET_TEST(f32);
+JTEST_ARM_OFFSET_TEST(q31);
+JTEST_ARM_OFFSET_TEST(q15);
+JTEST_ARM_OFFSET_TEST(q7);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(offset_tests)
+{
+ JTEST_TEST_CALL(arm_offset_f32_test);
+ JTEST_TEST_CALL(arm_offset_q31_test);
+ JTEST_TEST_CALL(arm_offset_q15_test);
+ JTEST_TEST_CALL(arm_offset_q7_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/scale_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/scale_tests.c
new file mode 100644
index 0000000..2839a8f
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/scale_tests.c
@@ -0,0 +1,52 @@
+#include "jtest.h"
+#include "basic_math_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "basic_math_templates.h"
+#include "type_abbrev.h"
+
+
+#define JTEST_ARM_SCALE_TEST(suffix) \
+ BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_ELT2_BLK( \
+ scale, \
+ suffix, \
+ TYPE_FROM_ABBREV(suffix), \
+ TYPE_FROM_ABBREV(suffix), /*elt1_type*/ \
+ int8_t, /*elt2_type*/ \
+ TYPE_FROM_ABBREV(suffix))
+
+/* float32_t defined separately because it has less arguments */
+JTEST_DEFINE_TEST(arm_scale_f32_test,
+ arm_scale_f32)
+{
+ TEST_TEMPLATE_BUF1_ELT1_BLK(
+ basic_math_f_all,
+ basic_math_eltsf,
+ basic_math_block_sizes,
+ float32_t,
+ float32_t,
+ float32_t,
+ arm_scale_f32,
+ ARM_scale_float_INPUT_INTERFACE,
+ ref_scale_f32,
+ REF_scale_float_INPUT_INTERFACE,
+ BASIC_MATH_COMPARE_INTERFACE);
+}
+
+JTEST_ARM_SCALE_TEST(q31);
+JTEST_ARM_SCALE_TEST(q15);
+JTEST_ARM_SCALE_TEST(q7);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(scale_tests)
+{
+ JTEST_TEST_CALL(arm_scale_f32_test);
+ JTEST_TEST_CALL(arm_scale_q31_test);
+ JTEST_TEST_CALL(arm_scale_q15_test);
+ JTEST_TEST_CALL(arm_scale_q7_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/shift_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/shift_tests.c
new file mode 100644
index 0000000..ed83b63
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/shift_tests.c
@@ -0,0 +1,31 @@
+#include "jtest.h"
+#include "basic_math_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "basic_math_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_SHIFT_TEST(suffix) \
+ BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_ELT1_BLK( \
+ shift, \
+ suffix, \
+ TYPE_FROM_ABBREV(suffix), \
+ int8_t, /*elt_type*/ \
+ TYPE_FROM_ABBREV(suffix))
+
+JTEST_ARM_SHIFT_TEST(q31);
+JTEST_ARM_SHIFT_TEST(q15);
+JTEST_ARM_SHIFT_TEST(q7);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(shift_tests)
+{
+ JTEST_TEST_CALL(arm_shift_q31_test);
+ JTEST_TEST_CALL(arm_shift_q15_test);
+ JTEST_TEST_CALL(arm_shift_q7_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/sub_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/sub_tests.c
new file mode 100644
index 0000000..a486842
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/sub_tests.c
@@ -0,0 +1,33 @@
+#include "jtest.h"
+#include "basic_math_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "basic_math_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_SUB_TEST(suffix) \
+ BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK( \
+ sub, \
+ suffix, \
+ TYPE_FROM_ABBREV(suffix), \
+ TYPE_FROM_ABBREV(suffix), \
+ BASIC_MATH_COMPARE_INTERFACE)
+
+JTEST_ARM_SUB_TEST(f32);
+JTEST_ARM_SUB_TEST(q31);
+JTEST_ARM_SUB_TEST(q15);
+JTEST_ARM_SUB_TEST(q7);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(sub_tests)
+{
+ JTEST_TEST_CALL(arm_sub_f32_test);
+ JTEST_TEST_CALL(arm_sub_q31_test);
+ JTEST_TEST_CALL(arm_sub_q15_test);
+ JTEST_TEST_CALL(arm_sub_q7_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_conj_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_conj_tests.c
new file mode 100644
index 0000000..7fcc0bc
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_conj_tests.c
@@ -0,0 +1,31 @@
+#include "jtest.h"
+#include "complex_math_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "complex_math_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_CMPLX_CONJ_TEST(suffix) \
+ COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF1_BLK( \
+ cmplx_conj, \
+ suffix, \
+ TYPE_FROM_ABBREV(suffix), \
+ TYPE_FROM_ABBREV(suffix), \
+ COMPLEX_MATH_SNR_COMPARE_CMPLX_INTERFACE)
+
+JTEST_ARM_CMPLX_CONJ_TEST(f32);
+JTEST_ARM_CMPLX_CONJ_TEST(q31);
+JTEST_ARM_CMPLX_CONJ_TEST(q15);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(cmplx_conj_tests)
+{
+ JTEST_TEST_CALL(arm_cmplx_conj_f32_test);
+ JTEST_TEST_CALL(arm_cmplx_conj_q31_test);
+ JTEST_TEST_CALL(arm_cmplx_conj_q15_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_dot_prod_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_dot_prod_tests.c
new file mode 100644
index 0000000..bcdaf5b
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_dot_prod_tests.c
@@ -0,0 +1,31 @@
+#include "jtest.h"
+#include "complex_math_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "complex_math_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_CMPLX_DOT_PROD_TEST(suffix, comparison_interface) \
+ COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK( \
+ cmplx_dot_prod, \
+ suffix, \
+ TYPE_FROM_ABBREV(suffix), \
+ TYPE_FROM_ABBREV(suffix), \
+ comparison_interface)
+
+JTEST_ARM_CMPLX_DOT_PROD_TEST(f32, COMPLEX_MATH_SNR_COMPARE_SPLIT_INTERFACE);
+JTEST_ARM_CMPLX_DOT_PROD_TEST(q31, COMPLEX_MATH_SNR_COMPARE_SPLIT_INTERFACE);
+JTEST_ARM_CMPLX_DOT_PROD_TEST(q15, COMPLEX_MATH_SNR_COMPARE_SPLIT_INTERFACE);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(cmplx_dot_prod_tests)
+{
+ JTEST_TEST_CALL(arm_cmplx_dot_prod_f32_test);
+ JTEST_TEST_CALL(arm_cmplx_dot_prod_q31_test);
+ JTEST_TEST_CALL(arm_cmplx_dot_prod_q15_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_squared_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_squared_tests.c
new file mode 100644
index 0000000..9ca11fc
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_squared_tests.c
@@ -0,0 +1,31 @@
+#include "jtest.h"
+#include "complex_math_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "complex_math_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_CMPLX_MAG_SQUARED_TEST(suffix) \
+ COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF1_BLK( \
+ cmplx_mag_squared, \
+ suffix, \
+ TYPE_FROM_ABBREV(suffix), \
+ TYPE_FROM_ABBREV(suffix), \
+ COMPLEX_MATH_COMPARE_RE_INTERFACE)
+
+JTEST_ARM_CMPLX_MAG_SQUARED_TEST(f32);
+JTEST_ARM_CMPLX_MAG_SQUARED_TEST(q31);
+JTEST_ARM_CMPLX_MAG_SQUARED_TEST(q15);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(cmplx_mag_squared_tests)
+{
+ JTEST_TEST_CALL(arm_cmplx_mag_squared_f32_test);
+ JTEST_TEST_CALL(arm_cmplx_mag_squared_q31_test);
+ JTEST_TEST_CALL(arm_cmplx_mag_squared_q15_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_tests.c
new file mode 100644
index 0000000..8711957
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_tests.c
@@ -0,0 +1,31 @@
+#include "jtest.h"
+#include "complex_math_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "complex_math_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_CMPLX_MAG_TEST(suffix, comparison_interface) \
+ COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF1_BLK( \
+ cmplx_mag, \
+ suffix, \
+ TYPE_FROM_ABBREV(suffix), \
+ TYPE_FROM_ABBREV(suffix), \
+ comparison_interface)
+
+JTEST_ARM_CMPLX_MAG_TEST(f32, COMPLEX_MATH_COMPARE_RE_INTERFACE);
+JTEST_ARM_CMPLX_MAG_TEST(q31, COMPLEX_MATH_SNR_COMPARE_RE_INTERFACE);
+JTEST_ARM_CMPLX_MAG_TEST(q15, COMPLEX_MATH_SNR_COMPARE_RE_INTERFACE);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(cmplx_mag_tests)
+{
+ JTEST_TEST_CALL(arm_cmplx_mag_f32_test);
+ JTEST_TEST_CALL(arm_cmplx_mag_q31_test);
+ JTEST_TEST_CALL(arm_cmplx_mag_q15_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_cmplx_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_cmplx_tests.c
new file mode 100644
index 0000000..22c5a70
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_cmplx_tests.c
@@ -0,0 +1,31 @@
+#include "jtest.h"
+#include "complex_math_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "complex_math_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_CMPLX_MULT_CMPLX_TEST(suffix) \
+ COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK( \
+ cmplx_mult_cmplx, \
+ suffix, \
+ TYPE_FROM_ABBREV(suffix), \
+ TYPE_FROM_ABBREV(suffix), \
+ COMPLEX_MATH_COMPARE_CMPLX_INTERFACE)
+
+JTEST_ARM_CMPLX_MULT_CMPLX_TEST(f32);
+JTEST_ARM_CMPLX_MULT_CMPLX_TEST(q31);
+JTEST_ARM_CMPLX_MULT_CMPLX_TEST(q15);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(cmplx_mult_cmplx_tests)
+{
+ JTEST_TEST_CALL(arm_cmplx_mult_cmplx_f32_test);
+ JTEST_TEST_CALL(arm_cmplx_mult_cmplx_q31_test);
+ JTEST_TEST_CALL(arm_cmplx_mult_cmplx_q15_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_real_test.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_real_test.c
new file mode 100644
index 0000000..fce7b82
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_real_test.c
@@ -0,0 +1,31 @@
+#include "jtest.h"
+#include "complex_math_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "complex_math_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_CMPLX_MULT_REAL_TEST(suffix, comparison_interface) \
+ COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK( \
+ cmplx_mult_real, \
+ suffix, \
+ TYPE_FROM_ABBREV(suffix), \
+ TYPE_FROM_ABBREV(suffix), \
+ comparison_interface)
+
+JTEST_ARM_CMPLX_MULT_REAL_TEST(f32, COMPLEX_MATH_COMPARE_CMPLX_INTERFACE);
+JTEST_ARM_CMPLX_MULT_REAL_TEST(q31, COMPLEX_MATH_SNR_COMPARE_CMPLX_INTERFACE);
+JTEST_ARM_CMPLX_MULT_REAL_TEST(q15, COMPLEX_MATH_COMPARE_CMPLX_INTERFACE);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(cmplx_mult_real_tests)
+{
+ JTEST_TEST_CALL(arm_cmplx_mult_real_f32_test);
+ JTEST_TEST_CALL(arm_cmplx_mult_real_q31_test);
+ JTEST_TEST_CALL(arm_cmplx_mult_real_q15_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_common_data.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_common_data.c
new file mode 100644
index 0000000..396dc2f
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_common_data.c
@@ -0,0 +1,114 @@
+#include "complex_math_test_data.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Input/Output Buffers */
+/*--------------------------------------------------------------------------------*/
+
+ARR_DESC_DEFINE(COMPLEX_MATH_BIGGEST_INPUT_TYPE,
+ complex_math_output_fut_a,
+ COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2 /*Complex data has two parts*/,
+ CURLY(0));
+
+ARR_DESC_DEFINE(COMPLEX_MATH_BIGGEST_INPUT_TYPE,
+ complex_math_output_fut_b,
+ COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2 /*Complex data has two parts*/,
+ CURLY(0));
+
+ARR_DESC_DEFINE(COMPLEX_MATH_BIGGEST_INPUT_TYPE,
+ complex_math_output_ref_a,
+ COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2 /*Complex data has two parts*/,
+ CURLY(0));
+
+
+ARR_DESC_DEFINE(COMPLEX_MATH_BIGGEST_INPUT_TYPE,
+ complex_math_output_ref_b,
+ COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2 /*Complex data has two parts*/,
+ CURLY(0));
+
+
+COMPLEX_MATH_BIGGEST_INPUT_TYPE
+complex_math_output_f32_ref_a[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2];
+
+COMPLEX_MATH_BIGGEST_INPUT_TYPE
+complex_math_output_f32_ref_b[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2];
+
+COMPLEX_MATH_BIGGEST_INPUT_TYPE
+complex_math_output_f32_fut_a[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2];
+
+COMPLEX_MATH_BIGGEST_INPUT_TYPE
+complex_math_output_f32_fut_b[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2];
+
+/*--------------------------------------------------------------------------------*/
+/* Block Sizes */
+/*--------------------------------------------------------------------------------*/
+
+ARR_DESC_DEFINE(uint32_t,
+ complex_math_block_sizes,
+ 4,
+ CURLY(1, 2, 15, 32));
+
+/*--------------------------------------------------------------------------------*/
+/* Test Data */
+/*--------------------------------------------------------------------------------*/
+
+ARR_DESC_DEFINE(float32_t,
+ complex_math_f_32,
+ 32 * 2 /*Complex data has two parts*/,
+ CURLY(
+ -0.432564811528220680 , 0.815622288876143300,
+ -1.665584378238097000 , 0.711908323500893280,
+ 0.125332306474830680 , 1.290249754932477000,
+ 0.287676420358548850 , 0.668600505682040320,
+ -1.146471350681463700 , 1.190838074243369100,
+ 1.190915465642998800 , -1.202457114773944000,
+ 1.189164201652103100 , -0.019789557768770449,
+ -0.037633276593317645 , -0.156717298831980680,
+ 0.327292361408654140 , -1.604085562001158500,
+ 0.174639142820924520 , 0.257304234677489860,
+ -0.186708577681439360 , -1.056472928081482400,
+ 0.725790548293302700 , 1.415141485872338600,
+ -0.588316543014188680 , -0.805090404196879830,
+ 2.183185818197101100 , 0.528743010962224870,
+ -0.136395883086595700 , 0.219320672667622370,
+ 0.113931313520809620 , -0.921901624355539130,
+ 1.066768211359188800 , -2.170674494305262500,
+ 0.059281460523605348 , -0.059187824521191180,
+ -0.095648405483669041 , -1.010633706474247400,
+ -0.832349463650022490 , 0.614463048895480980,
+ 0.294410816392640380 , 0.507740785341985520,
+ -1.336181857937804000 , 1.692429870190521400,
+ 0.714324551818952160 , 0.591282586924175900,
+ 1.623562064446270700 , -0.643595202682526120,
+ -0.691775701702286750 , 0.380337251713910140,
+ 0.857996672828262640 , -1.009115524340785000,
+ 1.254001421602532400 , -0.019510669530289293,
+ -1.593729576447476800 , -0.048220789145312269,
+ -1.440964431901020000 , 0.000043191841625545,
+ 0.571147623658177950 , -0.317859451247687890,
+ -0.399885577715363150 , 1.095003738787492500,
+ 0.689997375464345140 , -1.873990257640960800
+ ));
+
+ARR_DESC_DEFINE_SUBSET(complex_math_f_15,
+ complex_math_f_32,
+ 15 * 2 /*Complex data has two parts*/);
+
+ARR_DESC_DEFINE_SUBSET(complex_math_f_2,
+ complex_math_f_32,
+ 2 * 2 /*Complex data has two parts*/);
+
+ARR_DESC_DEFINE(float32_t,
+ complex_math_zeros,
+ 32 * 2 /*Complex data has two parts*/,
+ CURLY(0));
+
+/* Aggregate all float datasets */
+ARR_DESC_DEFINE(ARR_DESC_t *,
+ complex_math_f_all,
+ 4,
+ CURLY(
+ &complex_math_zeros,
+ &complex_math_f_2,
+ &complex_math_f_15,
+ &complex_math_f_32
+ ));
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_group.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_group.c
new file mode 100644
index 0000000..38546fb
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_group.c
@@ -0,0 +1,14 @@
+#include "jtest.h"
+#include "complex_math_tests.h"
+
+JTEST_DEFINE_GROUP(complex_math_tests)
+{
+ JTEST_GROUP_CALL(cmplx_conj_tests);
+ JTEST_GROUP_CALL(cmplx_dot_prod_tests);
+ JTEST_GROUP_CALL(cmplx_mag_tests);
+ JTEST_GROUP_CALL(cmplx_mag_squared_tests);
+ JTEST_GROUP_CALL(cmplx_mult_cmplx_tests);
+ JTEST_GROUP_CALL(cmplx_mult_real_tests);
+
+ return;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_common_data.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_common_data.c
new file mode 100644
index 0000000..661a487
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_common_data.c
@@ -0,0 +1,499 @@
+#include "controller_test_data.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Input/Output Buffers */
+/*--------------------------------------------------------------------------------*/
+
+float32_t controller_output_fut[CONTROLLER_MAX_LEN] = {0};
+float32_t controller_output_ref[CONTROLLER_MAX_LEN] = {0};
+float32_t controller_output_f32_fut[CONTROLLER_MAX_LEN] = {0};
+float32_t controller_output_f32_ref[CONTROLLER_MAX_LEN] = {0};
+
+const q31_t controller_q31_inputs[CONTROLLER_MAX_LEN] =
+{
+ 0xC14A5524, 0xCCABDA17, 0xAD6F5B56, 0xFDAFCE3B, 0xA9B226EB, 0x41F6F6A,
+ 0xA5CE38BF, 0x3A978AFA, 0xBA44B82A, 0x855C0F8, 0x3D060524, 0x93D5E570,
+ 0x97D7791D, 0xFFE0C38C, 0x26749841, 0xC0A6EE54, 0x218EC386, 0x39FF3726,
+ 0x8DC1F7CA, 0x702F2CF5, 0xC1142FF1, 0xEC1476AB, 0x15F640DD, 0xE62CCE49,
+ 0x3805DE7E, 0xF70871FE, 0xCF8BD360, 0x8D19A8A0, 0xD764F821, 0xA58558CF,
+ 0x8C0CE04D, 0x50A46C19, 0x66D2370D, 0x50FA359A, 0xB646AE24, 0x6CE00F5C,
+ 0xE6D48948, 0xB55BD831, 0x3B72950A, 0x9EB69530, 0x73394127, 0x773FA6F4,
+ 0x9805A980, 0x838DE587, 0x9CF597F4, 0xA2AD1691, 0xFA81A473, 0x7CDC7D7F,
+ 0x4A5190D0, 0xED895BB9, 0x8FD60F35, 0x1A21D530, 0xA0EB6DDA, 0xBDE6A516,
+ 0x2501A3E1, 0x5ED893C8, 0xE1E175B1, 0xACBBB2F3, 0xED350907, 0xDB140D7E,
+ 0xEEAE272D, 0xBE229841, 0xC18BFB88, 0xA6BB9B80, 0xBCF090E4, 0x24DB166C,
+ 0xF9AB7E42, 0x62DF28D1, 0xC7004665, 0xE3F56FC6, 0x419E0C75, 0x46BE9F38,
+ 0x2432B9B2, 0x758D83E0, 0xDCE12926, 0x3F57CB74, 0x1F4458E2, 0xF1DD639,
+ 0x83A1FB49, 0x173AFC76, 0x86EF7531, 0x48D32F34, 0x7D3E3063, 0x8F2FB549,
+ 0x5C314C9, 0x18CBEB6D, 0xA6F8B697, 0x447B9E9C, 0x2E32BA33, 0xD074D715,
+ 0x81ACD746, 0xE55A4E04, 0x4891860F, 0x1DA3EB4F, 0xE0E6A27F, 0x20BFDEB4,
+ 0xD0B3A25B, 0x40C10544, 0xC15656C, 0x15405EAE, 0x9858E3E1, 0xA36A9C4E,
+ 0x88BD21F9, 0xAACF7A68, 0x773665E5, 0xCEDFDF66, 0x617A9610, 0x524FC968,
+ 0xC2D086CD, 0x5F008079, 0x24DCA447, 0x6A4F5599, 0xB706CD4A, 0x1DE70608,
+ 0xA33A2EE5, 0x137E488E, 0x98061B7B, 0x4079D69D, 0xA4A897D5, 0xC4CEC8F5,
+ 0xD75F7883, 0x22406802, 0xF1AD70BB, 0x9D4ADD79, 0xBCBC7CE4, 0xB358C0D8,
+ 0x85792E47, 0xA7ADAC05, 0x3D19EEAB, 0x331AC0AF, 0x33035831, 0x13D93987,
+ 0xFC542094, 0x845F317E, 0xDDC4BF8B, 0x1379E50C, 0x5C20193F, 0xFDD58298,
+ 0x9D482B82, 0x4A6BE062, 0xDC8A757B, 0x272917C1, 0x90E1EFBC, 0x355AD882,
+ 0xE6F8EA35, 0x604555A1, 0x7DFFFBB, 0xF58AE216, 0x9A11B463, 0xD3541BAD,
+ 0xA1576756, 0x483BED8D, 0x1F05AFCC, 0xCEA63DFB, 0x55B84677, 0xFB2E04F2,
+ 0x787AF96C, 0x84A12CD3, 0x460A9BD, 0x9DB22DD8, 0x1A8C7F28, 0x861E452E,
+ 0x932D3F78, 0x7652D852, 0x73357BBA, 0xEBBB0A58, 0x62536AFA, 0x3F6B65EF,
+ 0x6DC57B58, 0x9EB798CE, 0xE6B0A740, 0xDFF68B47, 0x3247FB8F, 0xFFF3D302,
+ 0xA9FD3E40, 0x475A43D1, 0x6FF9528A, 0x2018A09D, 0x47E0F9C9, 0x4CF5F6D3,
+ 0x2807CE34, 0xDD6FD8ED, 0x234045D1, 0x51CEB5F9, 0x25297896, 0x6443A0FE,
+ 0x8F4449A9, 0xD4C3E1C6, 0xF01D52F1, 0x4E09C820, 0xF18F0810, 0xE1548689,
+ 0xF9DE5A1F, 0x5286DC23, 0x48AC3A4B, 0xEA0C1BE0, 0xA1B785DB, 0x7086465D,
+ 0x1CC10929, 0x1E1D716E, 0xED231D4C, 0x2049D108, 0xB8FF9971, 0x949CF8D4,
+ 0x441F1E8B, 0xC3D95372, 0x69C324B4, 0xA10BFDC9, 0xC781DE78, 0x82476137,
+ 0xE163DDF, 0x390DEEC2, 0xAF68CE5B, 0x8E680ABD, 0x8223A615, 0x92593380,
+ 0x7B1465FE, 0x865AE957, 0x930F53EB, 0xED772EF7, 0x10E916B6, 0xE3BCFA68,
+ 0x2ACB80BB, 0xE51C5590, 0x994714B5, 0xF30984EE, 0x59BBE1B4, 0xB4867DBC,
+ 0xB91C706C, 0xBC16C218, 0xA8931CD0, 0x129A66AB, 0x13171F4D, 0x62882872,
+ 0x4B167FD4, 0xE6902F4C, 0xFA794932, 0xD4B152C, 0xB0856EA9, 0x39466D55,
+ 0x3669E451, 0x8F5B9E8C, 0x877A3C6A, 0x51B956B4, 0x367EAD2A, 0x9D2C662A,
+ 0x78FB6880, 0x4E6D40B6, 0x4070EFDC, 0x4DF9679C, 0x20306EDB, 0xE381AAE7,
+ 0xA55DA748, 0x9B8B617B, 0x3E036FAD, 0x84E4C4A7, 0xD5A3F517, 0x669BA988,
+ 0x98FDDE8C, 0x67BD85CE, 0x34BBB46C, 0x76994800, 0x85B9D8B6, 0x6DFA2FEF,
+ 0x205DB5C, 0x9F843C4C, 0x72721B52, 0x73EF6B86, 0x5FB98B61, 0xC323DDAC,
+ 0x31D424B4, 0xF68C0D7E, 0x162FAF9D, 0x7B2A7A99, 0xF9392693, 0xC42D12C0,
+ 0x8692A73E, 0xD9A1EE80, 0xDD956856, 0x44E7BDAC, 0x8D874532, 0x5F5C9DD0,
+ 0x5D167858, 0x8559FEA2, 0x9D821476, 0xD9654ED2, 0x594C0DC7, 0x1A87B506,
+ 0x3F693200, 0x7A651AB5, 0xA0CCBC8A, 0x9F9E662C, 0x78EF631, 0x2A09DA0,
+ 0xB088C72F, 0x92EE0D42, 0x360DCD5F, 0xF333FE48, 0x8D63CC06, 0x233A8ACB,
+ 0x706651ED, 0x7AA5C079, 0x262239D1, 0x3EBBEBB6, 0xA25A4F3D, 0x32581A06,
+ 0x6E6FD780, 0x5773F7C7, 0x75ED1DDC, 0x90DF2D15, 0xBC79A9BC, 0xB7175917,
+ 0x354E381C, 0x762AADD7, 0xF643DAC1, 0xF3BBF49E, 0xD2FECE7E, 0x6C8140F4,
+ 0xD7694875, 0x92D30822, 0xC742A7CF, 0xB792ED98, 0x121CFE24, 0xA04E1EE7,
+ 0x58CE268, 0x215A080, 0x316CB323, 0xFAB14A31, 0xE1C13C03, 0xFD8EF4F1,
+ 0xF3F446D0, 0x6C6CEA0A, 0xBBFDF9FB, 0x67242969, 0xBE55A4EB, 0x8FF5534,
+ 0x52F0DF1C, 0x9710ADE3, 0xD40F4A21, 0x7984E8E7, 0x419545EB, 0x993F7880,
+ 0xAB246B20, 0x408AABC4, 0xCBF6EA49, 0xC0894C55, 0x4CAA6398, 0xA47856E9,
+ 0xAF2AE47D, 0x22F55D33, 0xF0D37915, 0xD0634C72, 0xD983671, 0x2BCC5AF8,
+ 0x9A77D48, 0xC11B5CFA, 0xF107CD7E, 0x3A6B3593, 0xE1425F05, 0x6271812A,
+ 0x5B838310, 0xBD8418CA, 0x10A58792, 0x239F7137, 0xA13D5071, 0x7F9930D4,
+ 0xA462664F, 0x54180F8E, 0x291585BA, 0xE586B87A, 0x144B2C12, 0x98E425C7,
+ 0xBAA4B373, 0x18F0D03C, 0x99462AC0, 0xD8B4D2EF, 0x72473895, 0xA6BF5435,
+ 0xEDAD53B, 0xE0912FA6, 0x5C33F331, 0x3D93CD7, 0x4D03D752, 0x20699929,
+ 0xB89962F9, 0x36E781E9, 0xF58B642C, 0x5FCA69E3, 0x5960A7F4, 0xAD5AAFD0,
+ 0xDF18324A, 0x3DB1E5AA, 0x76BA3876, 0x1BC29AF6, 0xBCC18841, 0x73A60174,
+ 0x625BFF58, 0x67C57724, 0x4458E53C, 0xE157B095, 0x2B370837, 0x83DF6CE3,
+ 0xDD08EEFA, 0x3F52A7C2, 0x191B4785, 0x60843D82, 0xB0DE11F1, 0x105EA26C,
+ 0x6E1C7AA2, 0x47AADD14, 0xB6676D03, 0x3B8D4DF6, 0x737A694, 0x409521DC,
+ 0x744206A, 0xC722023F, 0x2BE4EAD5, 0x63E11D76, 0xCA4A09AB, 0x5CF2D2B9,
+ 0x31586916, 0xCDFD7D84, 0xB203F634, 0xAD7329D4, 0xC524582F, 0x2E53E6C1,
+ 0xBB0E019B, 0xB8538C6A, 0x6A2542D, 0x8A6A00E5, 0x119725CC, 0x5406D347,
+ 0x1B6FFAF1, 0xECCF71F1, 0x981117F2, 0x7167CA76, 0x74F4B880, 0x77A55F47,
+ 0x59EADB62, 0x4A331D95, 0xBCBBA76F, 0xA45C4D50, 0xC718D5, 0x87CE05D1,
+ 0x60D47AD5, 0xA5CA9C40, 0xB0061766, 0xE69B39DF, 0xBD5F1320, 0x9930EAD3,
+ 0xA8B38325, 0x8DD090F, 0x6A6EEF37, 0x2DF16F66, 0xAB514C7E, 0x31109C58,
+ 0xFD48C7FC, 0x515341CA, 0x77AB8EA6, 0x41328DAF, 0xBAF8D31E, 0xA4B31611,
+ 0xED37F331, 0x7A832A22, 0xA22591C7, 0x722D1F89, 0x3B19CF18, 0x261B8A4D,
+ 0xC3F6F6DB, 0xCF8CED61, 0x990FA250, 0xA02E72A9, 0x560DCEA2, 0xB08E67B4,
+ 0x3674E663, 0x97CC3852, 0xA7EB2EAC, 0xFFDE0AA8, 0xA64719A, 0x23269EDD,
+ 0x3C0B339E, 0x86284D40, 0x48D82ECB, 0xA4D4CCF8, 0x43631B91, 0x4BF0C248,
+ 0xB6497B9B, 0x6827BC58, 0xE30B7AF9, 0xA0CCBF26, 0x6C3B7B71, 0xD744B3ED,
+ 0xFA25D2F6, 0x4CDE642D, 0xD65B8142, 0xA6F9207F, 0xE7A207BE, 0xDB506684,
+ 0x44DA4780, 0x9175EA0C, 0x156104AF, 0x4155E1B0, 0x6E3A6886, 0x9DBA1EA2,
+ 0x5423D9C8, 0xCC024E22, 0x758F852A, 0x1DD6395, 0x2D19CBAD, 0xE164F5A1,
+ 0xC2084602, 0x89C274AD, 0x13CB5562, 0xD7FE2D5B, 0xE07A4EE5, 0x1672BA91,
+ 0x4F624CCF, 0x2E5EA4A3, 0x28FEEFAF, 0xBDDA6EF4, 0x32AFD40C, 0x99A5FB3B,
+ 0xDD1D73A3, 0xA342CB3E, 0xA78445F5, 0x53979C3B, 0x427D7943, 0x5221B58C,
+ 0xA6CE9A5E, 0xFB50ECA4, 0xBB86E36E, 0x60839F6D, 0xC5E1C2F3, 0xA1B7FB04,
+ 0xFBB65E0C, 0x78B80F5E, 0xFD8D972B, 0x3BF3BA90, 0x2D572D9, 0x2B5BC920,
+ 0xB6A0DE01, 0xD274D306, 0xC7C6C855, 0x9CAA669B, 0xB04AA641, 0x4D6B1760,
+ 0x3E17ED79, 0xD23241B0, 0xA4A6F957, 0xCBDE76AF, 0x4E5F9493, 0x4C215DA5,
+ 0x33A052B, 0x1A4D80C2, 0x40AEEBCA, 0x390D106B, 0xE9E8E018, 0x5AF3D6CF,
+ 0xE35E1D4, 0xC4FB1C6, 0x14B6299B, 0x8D2E25F0, 0xCCBF932A, 0xC5AC18B6,
+ 0x2227567D, 0x86B5CE2F, 0x26344534, 0x22C515EC, 0x2442B70D, 0xEC3721C6,
+ 0x34EF687D, 0x9C06323A, 0xEAF3EA60, 0x60396F52, 0xEAE78AA1, 0xC9D06CBC,
+ 0x6F95F6C8, 0x584CC258, 0xBA9A27BB, 0x66DF8D47, 0x9D4804EA, 0x57DD9E67,
+ 0xF89C7895, 0xF5336111, 0x25C122C8, 0x62742114, 0xCFBF6D26, 0xBF9F6482,
+ 0xE6F02CD9, 0x11083202, 0xC99E2618, 0x7EBC9351, 0x440112F1, 0xC9DFFBC1,
+ 0x3BF4DC25, 0xB1BA7FA0, 0x61AF9AED, 0x6B1F7D29, 0xAD865294, 0xE3E01129,
+ 0x7E9E77A5, 0x100435D7, 0x9FE3A71, 0x88597C81, 0x722849FA, 0x31C5A0AF,
+ 0xFBA178DC, 0x7F102D31, 0x5CA07864, 0x950E6F98, 0x82C34882, 0x5D041F11,
+ 0x8C613C57, 0xD398CFD1, 0x426F38AD, 0x5599AB1D, 0xFAFA078D, 0xAB25B413,
+ 0xD94B32CF, 0xB288FE38, 0x2893BB46, 0x9A0B4168, 0xA91BCA94, 0x653A5E8D,
+ 0x2174EBBE, 0xDEFE6415, 0x30DA429C, 0xD0C5E40C, 0xB4719AA4, 0xD29CE7A6,
+ 0x905957CD, 0xCD287499, 0x83CA0AA7, 0xA8385832, 0x25A0CA02, 0xC20D47A4,
+ 0xB562F556, 0x4BC19E4C, 0xD9E215C7, 0x27E838B4, 0xC58612F4, 0xA2827F6F,
+ 0xC49DCDBA, 0x679B7362, 0x4E495845, 0xCFD2F0D1, 0x395E76A0, 0x375A655E,
+ 0x92E2058F, 0x73F9F0CA, 0x61EFF3B3, 0x51FFD362, 0xE7410345, 0x7FDA8B3B,
+ 0xA219E2E8, 0x17ABE543, 0x26557412, 0x4B30084D, 0xA68E191D, 0xFE0D93DF,
+ 0x73EF127D, 0x4DECDDB1, 0x77FAF45F, 0xD6002898, 0x92DD0A40, 0x157F6DDF,
+ 0xC2A55F8E, 0x4359F924, 0xFB630C3F, 0x338B6B58, 0xB2945F75, 0x4FA23A0E,
+ 0x836EB8C0, 0xB3B18FD, 0x86114337, 0x24668ACB, 0x99BB82F0, 0x924C8A47,
+ 0xBA959701, 0x81155ABF, 0x8C612D71, 0x36074CA7, 0xD1668C41, 0xE35F58C7,
+ 0x7FC2802D, 0x8E6A7CF3, 0x65B07D07, 0x815F6A6B, 0x791BF0DD, 0x6E47D719,
+ 0xC24394C7, 0xE84A6EB, 0xF194AFEE, 0x464A2F52, 0x677579FD, 0xEBA775AE,
+ 0x1F6EEFF, 0x9A795237, 0x78D9D45F, 0x9D0B344D, 0xBBD34AB7, 0x2F85B12A,
+ 0x16C5C2AD, 0x3990985D, 0x88DF3351, 0x82811AA5, 0x6D351F41, 0x4066A69D,
+ 0x86B660BF, 0x6EDB4768, 0xDDD78CF0, 0xB5D74F6E, 0xE89E220C, 0x91439687,
+ 0x947CC9C9, 0x3857E2BD, 0x302F8AE4, 0x1DABE7F8, 0x4832D6C9, 0x37D58FCB,
+ 0x4EA8A711, 0xCD7BAC98, 0x19DBF8BC, 0xD8DE8DC2, 0xEAFF7E7B, 0xB7629C93,
+ 0x792C6E19, 0xF7009192, 0xFF88439D, 0x2E196A66, 0xEC71B78C, 0xEAF4BB3A,
+ 0x7C16225E, 0x668F337, 0xCBEE1608, 0x6D5B5552, 0x345DC590, 0x681209CC,
+ 0x7B24A819, 0xD08A1416, 0x99888FE3, 0x9FC7288A, 0x24BD8502, 0xEA1D9678,
+ 0x20EECA0, 0x59BEA057, 0x5ADE91EB, 0xDEA8E49D, 0xFA200E6F, 0x9149C81D,
+ 0xF2281E93, 0x8A5B0451, 0x67312D58, 0xE3B849F1, 0xD2217960, 0x7CDF59F3,
+ 0x33C775C0, 0x9EBA8799, 0x7DF9506, 0xB4E96110, 0xB8FCF3E3, 0xDEA059B2,
+ 0x8229B6EA, 0x316486F6, 0x43919185, 0x6C0D90F3, 0x1C6F3DF8, 0x38DB92A9,
+ 0x5CD41244, 0x2C9F0A7B, 0xDF4A315F, 0xF7CE9C66, 0x4C800860, 0x318D53E0,
+ 0xF105C20D, 0xD753E1F2, 0x750810BA, 0xA17ECCA5, 0x2010140, 0x4D884763,
+ 0xC2BB0DA7, 0xB2D5BA74, 0x141CECD4, 0x887FDFC3, 0xC64B53, 0x2D2A85F6,
+ 0x15532B45, 0x5D5CBCE1, 0xBEB9A16A, 0xA214611B, 0x9FC5AC5F, 0x11AE5DD7,
+ 0xA0B9A5A9, 0xFC648AF4, 0x740009AC, 0xED0E0321, 0xB8E6A61, 0x8910C544,
+ 0xC74F26C8, 0x9525CCF3, 0xB41AEB59, 0xE61984CE, 0x598B2197, 0xA412E59D,
+ 0xE1976DD4, 0xB29BBE16, 0x88FD9FB0, 0xB04006F3, 0xB45E309, 0xD5CC15F1,
+ 0xD9DAF630, 0xDC809335, 0x803ED52, 0xB537F5A5, 0xA994F6EB, 0xF5288568,
+ 0xF66FD264, 0x2EA2B3A6, 0x647619F3, 0xFFB38C7A, 0x1BC03B9, 0xB6BC3061,
+ 0xBF30596E, 0xBE2AD27B, 0x8AC04220, 0x641979A3, 0x9ECCBB89, 0xA144FBC1,
+ 0x4E8FAE26, 0x8C5A9D90, 0x299ED467, 0xD7C9C7E3, 0x1D4865ED, 0x76F31C3D,
+ 0xCEE81CDF, 0xB479195E, 0x6FFB3AE1, 0xDC8A398, 0x300F7364, 0xC7940AFA,
+ 0x3B85BE3E, 0xD98CC40D, 0xA24A3D89, 0x3A674204, 0x22888A38, 0x2E77F2D,
+ 0xA2841C9C, 0xCF0689C3, 0x9FE98922, 0x89335017, 0x2D6B69A7, 0xFEDB63F9,
+ 0x899AF4EF, 0x9F9F9B40, 0xA4BE97E8, 0xA51DAF7A, 0x16AC50D3, 0xA8D7ED6,
+ 0xED193443, 0x7615EF1B, 0xB0DF6A4E, 0x64FFE794, 0xE3DB2C9A, 0x7435B022,
+ 0x556E825C, 0x23802AF9, 0xC25098A4, 0xE75A18BB, 0x70B2A7B9, 0x7FB81BF,
+ 0x63EF910, 0x6C669591, 0x6574DD2B, 0xCF6E379D, 0xD2B3AFAC, 0x1E6A1101,
+ 0x1DE22385, 0x2338191F, 0xC69704B6, 0xCBABC599, 0x54EB4809, 0x7839BE6D,
+ 0xD50017DD, 0x39B1A0E1, 0x288D52D3, 0x2D52668C, 0x20D22A68, 0x4E1207D1,
+ 0x3FCC0EFE, 0x47F3FE64, 0x25177A90, 0xB4BFDD4D, 0xDA8DBDCE, 0x6F7275A8,
+ 0x6BEAA655, 0xAA1810FC, 0xE4DB593A, 0x8A4D4BC0, 0x2C402E93, 0xF1C0F7F9,
+ 0x6F0CC577, 0x70412414, 0x752F9DC1, 0xD82E38EA, 0xAC455F7B, 0x4DCD4EDB,
+ 0x92BC2696, 0xFB03F135, 0x4FCA1F8C, 0xBD5E75F6, 0x502F41B0, 0x3616D3F1,
+ 0x2E5B8E31, 0x2026EB19, 0x57E783D7, 0x467BBE00, 0x4703ABA3, 0x1F776B9C,
+ 0xE2570A84, 0xFEC7DB48, 0x1BD5012, 0xFD0A2D5D, 0x7FCC29F2, 0x291304B6,
+ 0x99D5D8ED, 0xC7551C8, 0xFD12F38F, 0xBADE8892, 0xDF749997, 0xA5DAE2F,
+ 0x2B9FA269, 0x5C13CFED, 0x15E9A399, 0x54437F4E, 0xA72DB2AB, 0x56186AA1,
+ 0xFE4DB55C, 0xA34D7836, 0x2A879760, 0xC63FA94, 0xAC18B207, 0x5FC78B3,
+ 0x7F10621E, 0xA769E6B2, 0xEC9F4A11, 0xCE3F982C, 0x62BA2EF5, 0xA5F239CD,
+ 0x73D63FED, 0xE36E9F5E, 0x8AC1DA0E, 0x3F3DB3EB, 0x738326EA, 0x35C366B1,
+ 0xCD476E86, 0x82F6B208, 0xF11A9FC1, 0x426AC396, 0x7E4D1B93, 0x75E4EDB7,
+ 0xAF3C44A7, 0x51A5EF5C, 0xFAD2463D, 0x8A5639CA, 0xC995AC78, 0xCC4BE4F6,
+ 0x3AFE7F8D, 0x66993D04, 0x4386FF37, 0xCBC1C6C2, 0x55A8F5EC, 0xE81A9A75,
+ 0x30A67E1B, 0x4A4A7D0C, 0x20F7F993, 0x1891805, 0x738976AD, 0xD426E7D6,
+ 0x3C5CEEBF, 0x4499187F, 0xABF17C97, 0x447C317F, 0x68D8419C, 0x7AAB6456,
+ 0x421BCF29, 0xF6740F9C, 0x8916BB8D, 0x3D72AAB, 0x9AD54DD7, 0x7549C6EE,
+ 0x7317342B, 0xA18546D4, 0x1056BDA7, 0x54BBCCCE, 0x8CE63E46, 0x5D146234,
+ 0x33BE6C63, 0xB250C4E5, 0x89D72335, 0x87C36BA, 0xB65530CC, 0x2DFAC48C,
+ 0x1663D16F, 0x59B80AA, 0x950274EA, 0x92532D4A, 0x3CEF802D, 0x492FBDA5,
+ 0xA63A2574, 0xEF8005C2, 0x94A18651, 0xAF627ABA, 0x6829B238, 0xA698F646,
+ 0xD2598516, 0x10144D36, 0xD9B1D1B9, 0xAB2ACF05, 0x5395B699, 0xA7851C75,
+ 0x1806C6F3, 0xAE970306, 0x3284B145, 0x98F4FE8F
+};
+
+/* The source data is random across the q31_t range. Accessing it by word should
+ remain random. */
+const q15_t * controller_q15_inputs = (q15_t *) controller_q31_inputs;
+
+const float32_t controller_f32_inputs[CONTROLLER_MAX_LEN] =
+{
+ 43.0264275639 , -17.0525215570 , -94.8488973910 , -8.1924989580 ,
+ 7.2830326091 , 66.8368719314 , 33.9778190671 , 117.8652289772 ,
+ -129.6077797465, -14.6420815368 , 18.0239223278 , 20.6760530292 ,
+ 55.0375037651 , 1.8674609862 , -85.6534302408 , -33.5750364909 ,
+ 29.2110949614 , 110.4727049460 , -94.1914619387 , -1.4084169343 ,
+ 83.5181653041 , 47.3073514127 , -13.3420621181 , 30.3389699104 ,
+ 12.1188124277 , 100.9730921941 , -114.0146362390, -77.5823200409 ,
+ 37.2019034618 , 40.0026301128 , -58.3387276630 , -34.9472398600 ,
+ -5.1169678311 , -87.7660091118 , -150.5888601131, 56.0349370503 ,
+ 50.2168884079 , -74.2313236767 , 22.3648603560 , -6.8676387051 ,
+ 74.8957303680 , -90.1292012823 , -55.1436241586 , -66.6732976100 ,
+ -6.7918147615 , 7.7612697081 , 35.7892605979 , -20.0470508830 ,
+ 41.8369017546 , -143.7378056984, -41.9127158600 , -108.3531841158,
+ -57.1917422289 , -124.2808828105, 38.9316388820 , -77.9212517405 ,
+ 37.1990818377 , -28.9545952748 , -155.6371057564, 45.8088886393 ,
+ 36.2537018275 , -6.5727656016 , -104.2070491921, 45.5583813729 ,
+ -19.7674717059 , -80.4802190947 , -1.4444563441 , -42.2142256438 ,
+ 36.6546339194 , -57.0866498590 , 44.4677067511 , 65.7285753407 ,
+ -103.8158864647, 25.4348723711 , -153.5419639389, 39.3608409474 ,
+ 49.1658103436 , 79.5570602275 , 75.2944095996 , 58.9394700746 ,
+ -53.1018534392 , 33.4172444014 , 35.6224682287 , -64.4353396418 ,
+ -125.8464291251, -47.6072111617 , -26.2177687594 , -12.0061322096 ,
+ -17.7887967585 , -28.2926175090 , -62.0691715749 , 40.5098573604 ,
+ -191.1123732593, 119.6750713043 , 19.6182375803 , -26.7615252921 ,
+ 2.2957847015 , -108.3436451287, -50.5906164995 , -5.6360985100 ,
+ -11.6772204201 , -84.2765293757 , -60.9317810068 , 82.0446350218 ,
+ -70.2048296348 , 72.8738253222 , 60.2450218115 , 114.2741231228 ,
+ 46.8180775285 , 6.9915412654 , -8.9909197429 , -78.9165936808 ,
+ 66.4731535459 , -68.4235455651 , -79.8254597080 , -10.6308477115 ,
+ -62.6161569330 , -55.7744410292 , -11.8408366528 , 98.1034940997 ,
+ 35.8213741877 , -54.4694482732 , 86.9631830044 , -53.0343838122 ,
+ -47.4898642865 , -47.2010929590 , -31.3312639685 , -23.0908245172 ,
+ 12.0258009869 , -5.1098204703 , -9.8420230737 , -107.3328761158,
+ 44.6810431959 , -17.9083820345 , -60.9753512872 , -7.5915088994 ,
+ 17.2250813329 , 57.9176125648 , 124.3004161362 , -63.1950908493 ,
+ 120.5788885640 , -44.1734238117 , -91.7408095116 , -43.5696066595 ,
+ -49.9560710099 , -167.8513443296, -70.9437505499 , -46.4109705355 ,
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+ -102.0850899209, 53.2360193126 , -25.8997883369 , 75.1445512333 ,
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+ 107.5017084384 , -113.7909124666, -43.9735396033 , 7.6880981388 ,
+ 46.7384653508 , 9.9047443751 , 81.8646964362 , 132.3812863877 ,
+ -95.6959050236 , -68.5015813484 , 65.8586404494 , 18.5039353889 ,
+ -30.1786166621 , -90.3098515667 , -22.9356228552 , -20.5778272423 ,
+ -2.2127786675 , -35.4418447703 , -51.8722915974 , -107.9024439078,
+ -51.5940748232 , -51.7463262677 , 74.2795485984 , 94.2205022462 ,
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+ -15.7183814485 , 78.2063383182 , 0.1516414969 , 37.9304181609 ,
+ 20.6185902740 , -22.2164106778 , 6.1160554677 , 2.4061326953 ,
+ -111.6681824598, -60.0858917090 , 75.1698614693 , -76.5787410444 ,
+ 28.3391655715 , -2.4946186443 , -68.0378899682 , 104.0893199171 ,
+ -51.8319647254 , 38.8521710524 , 75.9114239564 , 73.9206172905 ,
+ -103.2533029987, 6.9002718274 , -36.6346436319 , -25.1990926265 ,
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+ 49.7370635809 , -13.2957534126 , 36.6746826778 , -31.7005492589 ,
+ 148.4894964268 , 79.7890632353 , 16.8856024809 , 16.1690460177 ,
+ 39.2665169484 , 117.2461167794 , -37.4827984831 , -47.8387803604 ,
+ -95.7025286193 , 34.3058214285 , -124.9536456028, 56.1640195764 ,
+ 94.3636873606 , 35.3992852810 , -38.3920852159 , -100.5738062016,
+ -29.7837022314 , 42.9133913996 , -34.2715618187 , -14.3589115627 ,
+ -16.5935468750 , 20.4574192236 , -88.7897972666 , -38.6285080386 ,
+ 53.3203422726 , 98.5991486746 , 122.7305462474 , 67.7902817187 ,
+ 5.1764117389 , 5.0632821624 , 21.9288789574 , -78.3140512638 ,
+ -21.2069682335 , 23.6342010925 , 34.4445769455 , 59.1346766615 ,
+ 28.9978778000 , 39.8121180845 , -17.1650033520 , -56.9174900874 ,
+ 17.8157086148 , -112.8801457350, -122.4019040408, 140.8669393157 ,
+ -65.4664329639 , 40.6952775518 , 32.7260891658 , -43.2565155866 ,
+ 19.3945751928 , -20.1815002000 , -67.6601711640 , -18.1921178207 ,
+ -35.6802153684 , 49.9550290306 , 131.4925251016 , -31.2940938167 ,
+ -5.2848453344 , -109.5580577933, 20.2437599390 , -8.8782958734 ,
+ 54.1836717264 , 7.2555852190 , -3.5698316137 , -51.9236786262 ,
+ 6.7861547980 , -104.4814551670, 45.8458629668 , 70.0890876844 ,
+ 38.3572837740 , 61.8024165129 , 68.0176962024 , -12.8193934080 ,
+ -21.4661610917 , -0.9377108815 , -74.2100679061 , 71.0490808147 ,
+ 91.9813889497 , -14.5797640164 , 3.5036749129 , -138.3605478356,
+ -48.1501349794 , -16.0636922482 , -12.1334197606 , 15.0562207637 ,
+ -34.0878176054 , 55.1075126157 , 97.3829871877 , 0.2053358099 ,
+ -94.8713267382 , 51.5460954054 , 21.2966946363 , 58.1331025047 ,
+ -23.4599044132 , -19.3315856528 , -8.4497193577 , -1.9594679356 ,
+ -33.1906549336 , -144.6825417978, -57.1218958072 , 35.7353406097 ,
+ 61.4666549819 , 14.6536253128 , 82.1632196866 , -44.6230161723 ,
+ -91.1022589278 , -18.5737673927 , -136.8975612334, 56.9606788003 ,
+ 70.7059960183 , -68.2829345081 , -10.2629800455 , -53.6385325047 ,
+ -68.7928766204 , 88.2444688302 , 83.1412324801 , -102.9206928160,
+ -68.2329763159 , -69.7552955469 , 108.2132269009 , -28.2582329307 ,
+ 5.6685898328 , -36.0392956840 , 43.3269513128 , -8.6436416796 ,
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+ 13.5938214364 , -23.6296332202 , 49.1171161163 , 53.1636857935 ,
+ -62.9672053166 , -54.2594757384 , 48.3838956696 , 8.0469071555 ,
+ -33.6472086213 , -120.5381752144, 55.0880453111 , 17.8990740563 ,
+ 144.9402232336 , 101.7886229203 , -73.3666393712 , -16.4721379138 ,
+ -12.7447935685 , 101.8245160983 , -49.7026860415 , -15.1227790364 ,
+ 65.7430288442 , -131.8695390036, 10.2750933946 , 90.9752774838 ,
+ -26.5859990591 , -95.6962772568 , 76.2174589344 , 24.8796848060 ,
+ -38.8938223046 , 54.1687774852 , -37.3585968996 , -34.6848570502 ,
+ 33.0151011570 , -55.8345877671 , -3.9009101671 , -31.5024971691 ,
+ -9.6863895491 , 91.8719195957 , -58.9993249744 , -25.6887030614 ,
+ -8.0829472205 , 4.6386491741 , -71.4019697167 , -21.3734669095 ,
+ 86.2079144404 , 79.6823974266 , -0.0910915997 , 44.8067718095 ,
+ 58.7204020766 , 72.6856808976 , -50.3373732478 , -116.1175365534,
+ -15.0884909384 , 5.4593772059 , -63.6553527905 , 37.3460388205 ,
+ -32.2399421679 , 95.7569350513 , -7.3700141964 , -56.0370832967 ,
+ -41.7377150439 , -42.0042856519 , 12.5134312941 , 93.7845584531 ,
+ -32.4801087157 , -33.3976050318 , -24.2252126001 , -46.3199064467 ,
+ -20.3704610276 , 15.8571376404 , 88.9127217235 , -33.1132582267 ,
+ -1.0005675836 , -28.1780471904 , 150.9349379135 , 38.0600520828 ,
+ 36.4338677563 , -3.3709201641 , 29.7709773016 , 16.5064119077 ,
+ 21.3147729463 , 110.6714300904 , 18.8406036507 , 14.8963298097 ,
+ 50.9975960392 , 16.3991140350 , -194.0805845907, -41.6723945839 ,
+ -74.8991127408 , -6.4587655805 , -0.6883628218 , -49.8709647175 ,
+ 194.2265120473 , 64.3043624521 , 16.0040882780 , 68.4032551772 ,
+ -43.4050313128 , 84.6826289824 , -28.1357565943 , 134.6895584120 ,
+ -7.9746152680 , -95.6692886462 , -48.9444370342 , 79.4479343188 ,
+ -50.5345228122 , 52.4800633307 , -14.7735051703 , -20.1510237050 ,
+ 22.5049816980 , 64.4191999102 , 24.8385648232 , 99.4265041360 ,
+ 62.0189508473 , -28.3892600378 , -109.8842008564, -79.0407483407 ,
+ 18.3408112020 , 49.1650536089 , 31.5419844924 , -36.1160722679 ,
+ -132.9148081329, 10.4053531567 , -129.2463715470, -43.4602207151 ,
+ -24.2420653292 , 91.5388317556 , 21.4762248190 , -44.3810909139 ,
+ 18.4098011282 , -45.8691164539 , -20.9831197962 , 16.2076792914 ,
+ 66.0224147666 , -13.6794615513 , 101.2163279622 , -62.4462618603 ,
+ 22.2040981785 , -52.3208382802 , -24.7909079016 , 58.5150375093 ,
+ 18.8569705105 , -55.6083430939 , 131.0273367422 , -34.5209015065 ,
+ 121.4357296573 , -77.2590299593 , -51.5929566898 , 5.0247131098 ,
+ -23.8451707592 , -4.5912313547 , 31.1387246821 , 61.7019310824 ,
+ 49.1912429744 , -50.5836913031 , -74.8182600630 , -21.6209317022 ,
+ 20.9409464654 , -72.7870824583 , -28.3530746820 , -45.0794425434 ,
+ -13.4910629905 , -62.0158772255 , -34.1421181246 , 44.2844972784 ,
+ 8.4213193211 , 79.9349022793 , 60.0160502260 , 32.2272994080 ,
+ -72.2893887746 , 17.3063698247 , -134.6335742431, 64.6499736261 ,
+ 7.1411921919 , -37.5517577873 , 6.2405670930 , 117.1920927305 ,
+ 128.7420689815 , -3.1556854963 , -13.4100422909 , -11.9336372907 ,
+ -8.6022400553 , -102.0033506666, -78.4696575074 , 15.0765861403 ,
+ -111.5219718576, -13.4162786508 , 38.2437013694 , 61.1637732561 ,
+ -34.4804160003 , 107.4438003830 , -79.4193067813 , -81.1842853968 ,
+ -26.2622970331 , 132.3205425408 , -119.1464268477, 67.3048866598 ,
+ 103.3266736715 , -58.1865815617 , 27.6231908601 , -11.2004371750 ,
+ 26.0340617206 , 12.5696123916 , 0.6442714420 , -30.7393043544 ,
+ 1.5314955897 , 49.9110088250 , -106.1358721920, 51.1608329944 ,
+ -32.8684239794 , -27.7215905745 , -11.6450303367 , -36.7731678028 ,
+ 59.9383486599 , -4.6301990580 , 5.0361682939 , -10.5669407980 ,
+ 124.0908762205 , 35.8305364082 , -123.6216777114, -74.2569079167 ,
+ -56.7651776816 , 16.0736385582 , 23.5030632215 , -110.6764295938,
+ 44.3086821806 , 9.4452708243 , 5.3300080251 , 39.0483916714 ,
+ 151.4550562868 , 62.8957092621 , -116.8103461233, 5.1129927759 ,
+ -33.2252515135 , -9.4522506046 , 22.7026048372 , -15.5264414569 ,
+ 71.2087620034 , 19.1191568332 , 50.3019546809 , -5.6096922409 ,
+ 22.9344126462 , -7.7591876203 , 31.8949515564 , -58.4253952381 ,
+ 66.4341297173 , -19.0583083044 , 96.7695087855 , 20.4934280047 ,
+ 4.9544603116 , -20.8288135920 , -173.2659655408, -62.4883621640 ,
+ -48.5528422703 , 12.1437504278 , 60.2482234666 , -19.6072312919 ,
+ -34.6320214291 , 129.0089698963 , -50.9042160618 , 98.3952661477 ,
+ -4.7051792479 , -13.1768910826 , 69.5138802139 , 58.5748201565 ,
+ -45.9385652563 , 151.7952104306 , 34.2541941013 , -58.0417838381 ,
+ 28.1480473670 , 46.4006562684 , 97.7001828545 , 4.0855607626 ,
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+ -60.9338593128 , -41.2220734230 , 49.9393070783 , 95.0974764854 ,
+ 49.2498366456 , 58.6214364590 , 34.1113830569 , 45.6634098874 ,
+ -22.5356086770 , -97.1978653617 , 86.5565049535 , 70.6118545777 ,
+ -30.6978082909 , 118.7238621666 , 14.5922386932 , 11.3449652072 ,
+ 65.6007783405 , 82.6369678204 , -52.0390492248 , -47.0160551227 ,
+ -95.5142448634 , 99.7162626888 , -36.5523815090 , -42.8042935534 ,
+ 68.3566199798 , -13.8451547552 , -71.1629911780 , 36.2989433752 ,
+ -32.4867163365 , 112.4079947071 , -75.6295117422 , 47.5276421639 ,
+ 51.8078250755 , -26.8715188457 , -9.6291144797 , 40.1999849640 ,
+ -38.4634033246 , 40.9764960915 , -26.1715730268 , 36.5996396515 ,
+ -26.9924731886 , 53.7879986570 , -83.1658398348 , 23.6381378489 ,
+ 43.8794937753 , -55.4133836419 , 90.0266130838 , 14.1036181982 ,
+ -18.1225736715 , 85.1363181151 , -62.5970846379 , -18.5291947838 ,
+ -25.7341986703 , -49.7061342931 , -59.0442763971 , 50.8960636803 ,
+ -87.6471123430 , -36.7217762531 , 22.5952364054 , 11.1107885650 ,
+ -0.5377327229 , 160.8145792630 , 73.3103441505 , 10.1656872354 ,
+ -50.4554350397 , -57.3478171016 , -15.4201715357 , -26.9135446491 ,
+ -4.9891264771 , -37.0226770057 , -80.9919535641 , 50.4418660876 ,
+ -25.8517575250 , -69.9538258421 , -17.5730160671 , 15.9405836751 ,
+ 113.9545230349 , -46.1040379057 , -94.2458635014 , -69.0338522452 ,
+ 43.5813790265 , 107.1836101171 , -55.1012654323 , -77.1529555887 ,
+ -33.1530320656 , -94.5582659641 , -53.6837586872 , 27.0680381378 ,
+ 93.9385415207 , -61.0955216188 , 18.0530957225 , 7.9150142320 ,
+ -12.1218191587 , 34.0173961457 , 40.0084937565 , 9.8119275580 ,
+ 44.2065861274 , -1.8718514394 , 67.4740024215 , 46.7391150131 ,
+ 207.2404815875 , 45.1635364462 , 43.3580102761 , -44.0244218674 ,
+ 83.2387206007 , -8.6441851856 , 12.3993902588 , -22.5091685270 ,
+ -19.8332981376 , 97.9196509289 , -76.6720306234 , 28.9740705859 ,
+ 121.9415248016 , 9.6656982611 , -51.0996453694 , 37.3704374740 ,
+ 74.7589840907 , -113.4066752631, 120.0029566342 , -105.3786221360,
+ 81.8152755619 , -13.4979932982 , -21.4680758393 , -85.1088235539 ,
+ -65.3610798409 , -35.0444139470 , -48.0220794487 , -41.6210317362 ,
+ 33.1212995259 , -82.1480936443 , -10.5479715135 , 76.4601917004 ,
+ 42.1983651157 , 92.6104239912 , -42.3536237955 , -24.5644182272 ,
+ 30.4446637772 , -90.2899420489 , 63.6723540422 , 103.0895811428 ,
+ 64.1706769263 , -10.7069812309 , 21.8927240409 , 6.3571071738 ,
+ 57.1457649358 , -52.9866276448 , 66.0981829072 , -29.5372056881 ,
+ -79.2252039810 , -136.2440652798, -57.0106422562 , 86.8203548141 ,
+ 66.4244149837 , 53.3230426111 , -66.1283059222 , -131.0402660353,
+ 8.0548411081 , 122.9088988100 , 1.2626894208 , -60.5059112373 ,
+ -68.8707203082 , -6.4747987200 , 85.8411327244 , 99.9624156733 ,
+ 90.4197864338 , -35.9630441182 , -22.9158275507 , -17.3660128776 ,
+ 16.7845345761 , 34.7219749782 , -39.3513765878 , 1.0460702756 ,
+ -60.9494500182 , 20.0900333387 , -85.9636743832 , 88.4400782168 ,
+ 15.0729628728 , 61.5499846243 , 11.8579871757 , 107.8617581581 ,
+ -42.9393027864 , -62.8422307621 , -19.0589600542 , 4.0750325807 ,
+ -36.0651825425 , 55.7638724501 , -10.4691736080 , -55.5672537178 ,
+ -61.2061519915 , -21.1885348576 , -131.2535612498, 24.7463552676 ,
+ 22.9426321237 , 14.3038202264 , -138.0926317438, -59.0892900856 ,
+ -162.5416439986, 7.1307658250 , -141.1236672256, -4.7173618068 ,
+ -16.7741532807 , -68.2615451173 , -2.6608701102 , 84.1978109826 ,
+ -11.3446202072 , 59.9630033088 , -1.8994925010 , -37.9301641959 ,
+ -119.4435600954, -11.4587491646 , 12.2423215240 , -7.3169898616 ,
+ -67.0373621128 , 36.0198843055 , 53.9791315249 , -134.5885680695,
+ -83.8330811965 , -16.6714816463 , -8.8498552035 , -24.0513088196 ,
+ -22.9444328877 , -37.7961441531 , 25.1975736186 , -136.1611637464,
+ -5.0843464033 , -10.3939554694 , 20.7422826935 , 75.6854136623 ,
+ 46.4179626736 , -57.0052830175 , 7.3457235521 , -51.5504447254 ,
+ -158.4375751701, -200.2426967181, -48.1234996261 , 1.6623945527 ,
+ 21.1746524375 , 99.4092980367 , -2.3206772903 , 45.7989166757 ,
+ 2.0181548348 , -88.0556010969 , -59.1527212096 , 47.3607925077 ,
+ -10.4181140309 , 56.3558125650 , -8.9799125560 , -30.0376711812 ,
+ -36.7132904688 , 35.7785050392 , -13.0763909369 , -2.1855594714 ,
+ 18.1550954005 , -28.6711803575 , -55.4495172398 , -2.8812973198 ,
+ -59.9575059158 , 40.0588875786 , 57.4713686602 , -3.2835144853 ,
+ -36.7193552111 , -64.9415131516 , -166.9555466445, -23.5556853844 ,
+ -54.9408569587 , -35.2310451959 , 21.3345143458 , 65.7590671151 ,
+ 51.2214538168 , 46.1271939944 , -42.2235267919 , 127.2329928299 ,
+ 105.2391778600 , 17.6726845966 , -129.9021148044, 8.7065613044 ,
+ -94.0987112511 , -3.5375742950 , -23.1385452379 , 60.6219530633 ,
+ 92.5445564235 , 48.5111974469 , -52.5699309159 , -60.0634811685 ,
+ 25.9034368684 , 140.0249495491 , 1.5918852392 , 38.0266038291 ,
+ 17.5588710703 , 3.4294066089 , -27.6748782173 , 59.6182974489 ,
+ -35.2924781853 , -38.6198576115 , -13.6119803198 , 7.8375587489 ,
+ 22.7250686519 , -28.3524510951 , -34.4269062817 , 22.6464817325 ,
+ -61.6528147860 , -5.9782002429 , 61.4730771294 , 43.5582379527 ,
+ 55.6862408270 , 87.8745651631 , 46.3401042715 , -19.8780979663 ,
+ 74.1272633369 , 29.8590452377 , -12.8665765140 , 34.2931401219 ,
+ 53.9279617551 , -16.9017895140 , -70.1527553166 , -79.6367897992 ,
+ 109.3728271017 , -129.2214826835, -53.4644539730 , -51.5654458993 ,
+ 17.6062148433 , 3.5090251835 , 74.2615941204 , -109.3431097845,
+ 40.1403465151 , 28.8714561280 , 94.0868659302 , -19.0047033845 ,
+ -60.0967410050 , -19.0998457619 , -67.2027075128 , 72.0711434846 ,
+ -17.8737851232 , 123.7050551274 , 132.6331504104 , 25.5018761009 ,
+ -36.7817189239 , -29.1580893235 , -6.5848563828 , 90.2868948516 ,
+ -35.7017258498 , -68.5675432955 , -52.4888589786 , 47.1377730021 ,
+ -7.4546621940 , -52.0657517138 , -49.0404829633 , -114.6910280126,
+ -117.6819819437, -32.7856729408 , 31.8232065591 , 12.1192973039 ,
+ 35.2678513420 , -1.0336778293 , 30.7021249679 , 127.0442906046 ,
+ -84.8457819393 , 28.9862843096 , -47.3524701726 , -126.1094998460,
+ -2.9700276582 , -2.4956545870 , -53.8624121141 , -85.2114117637 ,
+ 76.9057985618 , 137.1205201755 , -19.0830817212 , 14.3407526579 ,
+ -56.5921994449 , -25.6084873186 , -44.9470801106 , -133.3139496090,
+ 0.3487447576 , 33.4499716730 , 34.7126257844 , -9.3307383323 ,
+ 27.2996276947 , 10.8765676134 , -91.1032360444 , -90.9584216222 ,
+ 1.6981490570 , 96.8557438791 , 56.7726390913 , -44.3246449237 ,
+ 52.3260643361 , 21.5551140465 , 27.4535327381 , 2.0072717479 ,
+ 7.4823125629 , 77.1185863870 , 16.1372262663 , -10.7206012957
+};
+
+const float32_t controller_f32_coeffs[CONTROLLER_MAX_COEFFS_LEN] =
+{
+ /* S->Kp, S->Ki, S->Kd; */
+ 0.0000000000 , -1.0336778293 , 56.7726390913 ,
+ 0.3487447576 , 0.0000000000 , 27.4535327381 ,
+ -29.1580893235, 1.6981490570 , 0.0000000000 ,
+ 0.0000000000 , 0.0000000000 , -2.4956545870 ,
+ 0.0000000000 , 8.7065613044 , 0.0000000000 ,
+ 0.0000000000 , 0.0000000000 , 0.0000000000 ,
+ 18.1550954005 , -5.9782002429 , 2.0072717479 ,
+ 33.1212995259 , -82.1480936443, -10.5479715135,
+ -23.6296332202, 49.1171161163 , 53.1636857935 ,
+ 7.2830326091 , 66.8368719314 , 33.9778190671 ,
+ 9.4452708243 , 5.3300080251 , 39.0483916714 ,
+ 6.9915412654 , -8.9909197429 , -78.9165936808
+};
+
+const q31_t controller_q31_coeffs[CONTROLLER_MAX_COEFFS_LEN] =
+{
+ 0x00000000, 0xFEF760E4, 0x38C5CBAD,
+ 0x00594756, 0x00000000, 0x1B741AB9,
+ 0xE2D78775, 0x01B2B9E6, 0x00000000,
+ 0x00000000, 0x00000000, 0xFD811CC8,
+ 0x00000000, 0x08B4E134, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000,
+ 0x1227B455, 0xFA0594AB, 0x0201DC90,
+ 0x211F0D7C, 0xADDA1689, 0xF573B824,
+ 0xE85ED05B, 0x311DFB52, 0x3529E750,
+ 0x074874D3, 0x42D63D3D, 0x21FA525A,
+ 0x0971FD45, 0x05547B68, 0x270C6366,
+ 0x06FDD5A6, 0xF7025315, 0xB1155A1E
+};
+
+
+const q15_t controller_q15_coeffs[CONTROLLER_MAX_COEFFS_LEN] =
+{
+ 0x0000, 0xFEF7, 0x38C6,
+ 0x0059, 0x0000, 0x1B74,
+ 0xE2D8, 0x01B3, 0x0000,
+ 0x0000, 0x0000, 0xFD81,
+ 0x0000, 0x08B5, 0x0000,
+ 0x0000, 0x0000, 0x0000,
+ 0x1228, 0xFA06, 0x0202,
+ 0x211F, 0xADDA, 0xF574,
+ 0xE85F, 0x311E, 0x352A,
+ 0x0748, 0x42D6, 0x21FA,
+ 0x0972, 0x0554, 0x270C,
+ 0x06FE, 0xF702, 0xB115
+};
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_group.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_group.c
new file mode 100644
index 0000000..0f9709e
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_group.c
@@ -0,0 +1,13 @@
+#include "jtest.h"
+#include "controller_tests.h"
+
+JTEST_DEFINE_GROUP(controller_tests)
+{
+ /*
+ To skip a test, comment it out.
+ */
+ JTEST_GROUP_CALL(pid_reset_tests);
+ JTEST_GROUP_CALL(pid_tests);
+ JTEST_GROUP_CALL(sin_cos_tests);
+ return;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_reset_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_reset_tests.c
new file mode 100644
index 0000000..a930dbb
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_reset_tests.c
@@ -0,0 +1,52 @@
+#include "jtest.h"
+#include "arr_desc.h"
+#include "arm_math.h"
+#include "type_abbrev.h"
+#include "test_templates.h"
+
+/* Bucket of zeros. For comparison with the output of arm_pid_reset_xxx. */
+ARR_DESC_DEFINE(float32_t, zeroes, 3, CURLY(0));
+
+/**
+ * Define a JTEST_TEST_t for the function arm_pid_reset_xxx function having
+ * suffix.
+ */
+#define ARM_PID_RESET_TEST(suffix) \
+ JTEST_DEFINE_TEST(arm_pid_reset_##suffix##_test, \
+ arm_pid_reset_##suffix) \
+ { \
+ /* Initialise the pid_instance */ \
+ arm_pid_instance_##suffix pid_inst = { 0 }; \
+ pid_inst.state[0] = (TYPE_FROM_ABBREV(suffix)) 0xffffffff; \
+ pid_inst.state[1] = (TYPE_FROM_ABBREV(suffix)) 0xffffffff; \
+ pid_inst.state[2] = (TYPE_FROM_ABBREV(suffix)) 0xffffffff; \
+ \
+ /* Display cycle count and run test */ \
+ JTEST_COUNT_CYCLES(arm_pid_reset_##suffix(&pid_inst)); \
+ \
+ /* Test correctness */ \
+ TEST_ASSERT_BUFFERS_EQUAL( \
+ pid_inst.state, \
+ zeroes.data_ptr, \
+ 3 * sizeof(TYPE_FROM_ABBREV(suffix))); \
+ \
+ return JTEST_TEST_PASSED; \
+ }
+
+ARM_PID_RESET_TEST(f32);
+ARM_PID_RESET_TEST(q31);
+ARM_PID_RESET_TEST(q15);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(pid_reset_tests)
+{
+ /*
+ To skip a test, comment it out.
+ */
+ JTEST_TEST_CALL(arm_pid_reset_f32_test);
+ JTEST_TEST_CALL(arm_pid_reset_q31_test);
+ JTEST_TEST_CALL(arm_pid_reset_q15_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_tests.c
new file mode 100644
index 0000000..2e1c56e
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_tests.c
@@ -0,0 +1,79 @@
+#include "jtest.h"
+#include "arr_desc.h"
+#include "arm_math.h"
+#include "ref.h"
+#include "type_abbrev.h"
+#include "test_templates.h"
+#include "controller_test_data.h"
+#include "controller_templates.h"
+
+/**
+ * Define a JTEST_TEST_t for the function arm_pid_xxx function having
+ * suffix.
+ */
+#define ARM_PID_TEST(suffix,type) \
+ JTEST_DEFINE_TEST(arm_pid_##suffix##_test, arm_pid_##suffix) \
+ { \
+ uint32_t i,j; \
+ \
+ arm_pid_instance_##suffix fut_pid_inst = { 0 }; \
+ arm_pid_instance_##suffix ref_pid_inst = { 0 }; \
+ \
+ for(i=0;i<CONTROLLER_MAX_COEFFS_LEN/3;i++) \
+ { \
+ fut_pid_inst.Kp = controller_##suffix##_coeffs[i*3+0]; \
+ fut_pid_inst.Ki = controller_##suffix##_coeffs[i*3+1]; \
+ fut_pid_inst.Kd = controller_##suffix##_coeffs[i*3+2]; \
+ ref_pid_inst.Kp = controller_##suffix##_coeffs[i*3+0]; \
+ ref_pid_inst.Ki = controller_##suffix##_coeffs[i*3+1]; \
+ ref_pid_inst.Kd = controller_##suffix##_coeffs[i*3+2]; \
+ \
+ arm_pid_init_##suffix(&fut_pid_inst, 1); \
+ arm_pid_init_##suffix(&ref_pid_inst, 1); \
+ \
+ /* Display parameter values */ \
+ JTEST_DUMP_STRF("Block Size: %d\n", \
+ (int)CONTROLLER_MAX_LEN); \
+ \
+ /* Display cycle count and run test */ \
+ JTEST_COUNT_CYCLES( \
+ for(j=0;j<CONTROLLER_MAX_LEN;j++) \
+ { \
+ *((type*)controller_output_fut + j) = \
+ arm_pid_##suffix(&fut_pid_inst, \
+ controller_##suffix##_inputs[j]); \
+ }); \
+ \
+ for(j=0;j<CONTROLLER_MAX_LEN;j++) \
+ { \
+ *((type*)controller_output_ref + j) = \
+ ref_pid_##suffix(&ref_pid_inst, \
+ controller_##suffix##_inputs[j]); \
+ } \
+ \
+ /* Test correctness */ \
+ CONTROLLER_SNR_COMPARE_INTERFACE( \
+ CONTROLLER_MAX_LEN, \
+ type); \
+ } \
+ \
+ return JTEST_TEST_PASSED; \
+ }
+
+ARM_PID_TEST(f32,float32_t);
+ARM_PID_TEST(q31,q31_t);
+ARM_PID_TEST(q15,q15_t);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(pid_tests)
+{
+ /*
+ To skip a test, comment it out.
+ */
+ JTEST_TEST_CALL(arm_pid_f32_test);
+ JTEST_TEST_CALL(arm_pid_q31_test);
+ JTEST_TEST_CALL(arm_pid_q15_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/sin_cos_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/sin_cos_tests.c
new file mode 100644
index 0000000..e3887ac
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/sin_cos_tests.c
@@ -0,0 +1,151 @@
+#include "jtest.h"
+#include "arr_desc.h"
+#include "arm_math.h"
+#include "ref.h"
+#include "type_abbrev.h"
+#include "test_templates.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Input Data */
+/*--------------------------------------------------------------------------------*/
+
+ARR_DESC_DEFINE(float32_t,
+ arm_sin_cos_degrees_f32,
+ 9,
+ CURLY(
+ 0,
+ 17,
+ 45,
+ 90,
+ 180,
+ 360,
+ 362,
+ -73,
+ -191.111
+ ));
+
+/* The Q31 version of the function maps numbers in the range [-1, 0.9999999]
+ * to degrees in the range [-180, 179]*/
+ARR_DESC_DEFINE(q31_t,
+ arm_sin_cos_degrees_q31,
+ 6,
+ CURLY(
+ 0,
+ 0x80000000, /* -1 */
+ 0x7fffffff, /* 0.99999 */
+ /* Randoms */
+ 0xf7badafa,
+ 0x285954a1,
+ 0xb9d09511
+ ));
+
+/*--------------------------------------------------------------------------------*/
+/* Output Variables */
+/*--------------------------------------------------------------------------------*/
+float32_t sin_val_fut = 0;
+float32_t cos_val_fut = 0;
+float32_t sin_val_ref = 0;
+float32_t cos_val_ref = 0;
+
+/*--------------------------------------------------------------------------------*/
+/* Test Definitions */
+/*--------------------------------------------------------------------------------*/
+
+#define MAX_DELTA_f32 50.0e-8f
+#define ABS(x) ((x) > 0 ? (x) : -(x))
+
+/*
+ Function to test correctness of sin_cos output by comparing it with reference library
+*/
+#define COMPARISON_INTERFACE(type, threshold) \
+ if ( (ABS((type) sin_val_ref - (type) sin_val_fut) > \
+ (type) threshold ) || \
+ (ABS((type) cos_val_ref - (type) cos_val_fut) > \
+ (type) threshold)) \
+ { \
+ JTEST_DUMP_STRF("Error: %f %f\n", \
+ ABS((type) sin_val_ref - (type) sin_val_fut), \
+ ABS((type) cos_val_ref - (type) cos_val_fut)); \
+ return JTEST_TEST_FAILED; \
+ }
+
+/*
+ Sine and cosine test function for float32_t input
+*/
+JTEST_DEFINE_TEST(arm_sin_cos_f32_test, arm_sin_cos_f32)
+{
+ /* Test function for all input degree values */
+ TEMPLATE_DO_ARR_DESC(
+ degree_idx, TYPE_FROM_ABBREV(f32),
+ degree, arm_sin_cos_degrees_f32
+ ,
+ /* Display cycle count and run test */
+ JTEST_COUNT_CYCLES(
+ arm_sin_cos_f32(
+ degree,
+ (TYPE_FROM_ABBREV(f32) *) &sin_val_fut,
+ (TYPE_FROM_ABBREV(f32) *) &cos_val_fut)
+ );
+ ref_sin_cos_f32(
+ degree,
+ (TYPE_FROM_ABBREV(f32) *) &sin_val_ref,
+ (TYPE_FROM_ABBREV(f32) *) &cos_val_ref);
+
+ /* Test correctness */
+ COMPARISON_INTERFACE(
+ TYPE_FROM_ABBREV(f32),
+ MAX_DELTA_f32));
+
+ return JTEST_TEST_PASSED;
+}
+
+
+/*
+ Sine and cosine test function for q31_t input
+*/
+JTEST_DEFINE_TEST(arm_sin_cos_q31_test,
+ arm_sin_cos_q31)
+{
+ /* Test function for all input degree values */
+ TEMPLATE_DO_ARR_DESC(
+ degree_idx, TYPE_FROM_ABBREV(q31),
+ degree, arm_sin_cos_degrees_q31
+ ,
+ /* Display cycle count and run test */
+ JTEST_COUNT_CYCLES(
+ arm_sin_cos_q31(
+ degree,
+ (TYPE_FROM_ABBREV(q31) *) &sin_val_fut,
+ (TYPE_FROM_ABBREV(q31) *) &cos_val_fut)
+ );
+ ref_sin_cos_q31(
+ degree,
+ (TYPE_FROM_ABBREV(q31) *) &sin_val_ref,
+ (TYPE_FROM_ABBREV(q31) *) &cos_val_ref);
+
+ /* Convert q31 numbers to float for comparison purposes. */
+ ref_q31_t_to_float((TYPE_FROM_ABBREV(q31) *) &sin_val_fut, &sin_val_fut, 1);
+ ref_q31_t_to_float((TYPE_FROM_ABBREV(q31) *) &cos_val_fut, &cos_val_fut, 1);
+ ref_q31_t_to_float((TYPE_FROM_ABBREV(q31) *) &sin_val_ref, &sin_val_ref, 1);
+ ref_q31_t_to_float((TYPE_FROM_ABBREV(q31) *) &cos_val_ref, &cos_val_ref, 1);
+
+ /* Test correctness */
+ COMPARISON_INTERFACE(
+ TYPE_FROM_ABBREV(f32),
+ MAX_DELTA_f32));
+
+ return JTEST_TEST_PASSED;
+}
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(sin_cos_tests)
+{
+ /*
+ To skip a test, comment it out.
+ */
+ JTEST_TEST_CALL(arm_sin_cos_f32_test);
+ JTEST_TEST_CALL(arm_sin_cos_q31_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests.c
new file mode 100644
index 0000000..50ec433
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests.c
@@ -0,0 +1,38 @@
+#include "jtest.h"
+#include "ref.h"
+#include "arr_desc.h"
+#include "fast_math_templates.h"
+#include "fast_math_test_data.h"
+#include "type_abbrev.h"
+
+SQRT_TEST_TEMPLATE_ELT1(q31);
+SQRT_TEST_TEMPLATE_ELT1(q15);
+
+SIN_COS_TEST_TEMPLATE_ELT1(f32, float32_t, sin);
+SIN_COS_TEST_TEMPLATE_ELT1(q31, q31_t, sin);
+SIN_COS_TEST_TEMPLATE_ELT1(q15, q15_t, sin);
+
+SIN_COS_TEST_TEMPLATE_ELT1(f32, float32_t, cos);
+SIN_COS_TEST_TEMPLATE_ELT1(q31, q31_t, cos);
+SIN_COS_TEST_TEMPLATE_ELT1(q15, q15_t, cos);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(fast_math_tests)
+{
+ /*
+ To skip a test, comment it out.
+ */
+ JTEST_TEST_CALL(arm_sqrt_q31_test);
+ JTEST_TEST_CALL(arm_sqrt_q15_test);
+
+ JTEST_TEST_CALL(arm_sin_f32_test);
+ JTEST_TEST_CALL(arm_sin_q31_test);
+ JTEST_TEST_CALL(arm_sin_q15_test);
+
+ JTEST_TEST_CALL(arm_cos_f32_test);
+ JTEST_TEST_CALL(arm_cos_q31_test);
+ JTEST_TEST_CALL(arm_cos_q15_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests_common_data.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests_common_data.c
new file mode 100644
index 0000000..cf806e3
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests_common_data.c
@@ -0,0 +1,364 @@
+#include "fast_math_test_data.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Input/Output Buffers */
+/*--------------------------------------------------------------------------------*/
+
+float32_t fast_math_output_fut[FAST_MATH_MAX_LEN] = {0};
+float32_t fast_math_output_ref[FAST_MATH_MAX_LEN] = {0};
+float32_t fast_math_output_f32_fut[FAST_MATH_MAX_LEN] = {0};
+float32_t fast_math_output_f32_ref[FAST_MATH_MAX_LEN] = {0};
+
+const q31_t fast_math_q31_inputs[FAST_MATH_MAX_LEN] =
+{
+ 0x414A5524, 0x4CAB5A17, 0x2D6F5B56, 0x7DAF4E3B, 0x29B226EB, 0x41F6F6A ,
+ 0x25CE38BF, 0x3A970AFA, 0x3A44382A, 0x05540F8 , 0x3D060524, 0x13D56570,
+ 0x17D7791D, 0x7FE0438C, 0x26741841, 0x40A66E54, 0x218E4386, 0x39FF3726,
+ 0x0DC177CA, 0x702F2CF5, 0x41142FF1, 0x6C1476AB, 0x15F640DD, 0x662C4E49,
+ 0x38055E7E, 0x770871FE, 0x4F8B5360, 0x0D1928A0, 0x57647821, 0x258558CF,
+ 0x0C0C604D, 0x50A46C19, 0x66D2370D, 0x50FA359A, 0x36462E24, 0x6CE00F5C,
+ 0x66D40948, 0x355B5831, 0x3B72150A, 0x1EB61530, 0x73394127, 0x773F26F4,
+ 0x18052980, 0x038D6587, 0x1CF517F4, 0x22AD1691, 0x7A812473, 0x7CDC7D7F,
+ 0x4A5110D0, 0x6D895BB9, 0x0FD60F35, 0x1A215530, 0x20EB6DDA, 0x3DE62516,
+ 0x250123E1, 0x5ED813C8, 0x61E175B1, 0x2CBB32F3, 0x6D350907, 0x5B140D7E,
+ 0x6EAE272D, 0x3E221841, 0x418B7B88, 0x26BB1B80, 0x3CF010E4, 0x24DB166C,
+ 0x79AB7E42, 0x62DF28D1, 0x47004665, 0x63F56FC6, 0x419E0C75, 0x46BE1F38,
+ 0x243239B2, 0x758D03E0, 0x5CE12926, 0x3F574B74, 0x1F4458E2, 0x71D5639 ,
+ 0x03A17B49, 0x173A7C76, 0x06EF7531, 0x48D32F34, 0x7D3E3063, 0x0F2F3549,
+ 0x5C314C9 , 0x18CB6B6D, 0x26F83697, 0x447B1E9C, 0x2E323A33, 0x50745715,
+ 0x01AC5746, 0x655A4E04, 0x4891060F, 0x1DA36B4F, 0x60E6227F, 0x20BF5EB4,
+ 0x50B3225B, 0x40C10544, 0x415656C , 0x15405EAE, 0x185863E1, 0x236A1C4E,
+ 0x08BD21F9, 0x2ACF7A68, 0x773665E5, 0x4EDF5F66, 0x617A1610, 0x524F4968,
+ 0x42D006CD, 0x5F000079, 0x24DC2447, 0x6A4F5599, 0x37064D4A, 0x1DE70608,
+ 0x233A2EE5, 0x137E488E, 0x18061B7B, 0x4079569D, 0x24A817D5, 0x44CE48F5,
+ 0x575F7883, 0x22406802, 0x71AD70BB, 0x1D4A5D79, 0x3CBC7CE4, 0x335840D8,
+ 0x05792E47, 0x27AD2C05, 0x3D196EAB, 0x331A40AF, 0x33035831, 0x13D93987,
+ 0x7C542094, 0x045F317E, 0x5DC43F8B, 0x1379650C, 0x5C20193F, 0x7DD50298,
+ 0x1D482B82, 0x4A6B6062, 0x5C8A757B, 0x272917C1, 0x10E16FBC, 0x355A5882,
+ 0x66F86A35, 0x604555A1, 0x7DF7FBB , 0x758A6216, 0x1A113463, 0x53541BAD,
+ 0x21576756, 0x483B6D8D, 0x1F052FCC, 0x4EA63DFB, 0x55B84677, 0x7B2E04F2,
+ 0x787A796C, 0x04A12CD3, 0x46029BD , 0x1DB22DD8, 0x1A8C7F28, 0x061E452E,
+ 0x132D3F78, 0x76525852, 0x73357BBA, 0x6BBB0A58, 0x62536AFA, 0x3F6B65EF,
+ 0x6DC57B58, 0x1EB718CE, 0x66B02740, 0x5FF60B47, 0x32477B8F, 0x7FF35302,
+ 0x29FD3E40, 0x475A43D1, 0x6FF9528A, 0x2018209D, 0x47E079C9, 0x4CF576D3,
+ 0x28074E34, 0x5D6F58ED, 0x234045D1, 0x51CE35F9, 0x25297896, 0x644320FE,
+ 0x0F4449A9, 0x54C361C6, 0x701D52F1, 0x4E094820, 0x718F0810, 0x61540689,
+ 0x79DE5A1F, 0x52865C23, 0x48AC3A4B, 0x6A0C1BE0, 0x21B705DB, 0x7086465D,
+ 0x1CC10929, 0x1E1D716E, 0x6D231D4C, 0x20495108, 0x38FF1971, 0x149C78D4,
+ 0x441F1E8B, 0x43D95372, 0x69C324B4, 0x210B7DC9, 0x47815E78, 0x02476137,
+ 0x6163DDF , 0x390D6EC2, 0x2F684E5B, 0x0E680ABD, 0x02232615, 0x12593380,
+ 0x7B1465FE, 0x065A6957, 0x130F53EB, 0x6D772EF7, 0x10E916B6, 0x63BC7A68,
+ 0x2ACB00BB, 0x651C5590, 0x194714B5, 0x730904EE, 0x59BB61B4, 0x34867DBC,
+ 0x391C706C, 0x3C164218, 0x28931CD0, 0x129A66AB, 0x13171F4D, 0x62882872,
+ 0x4B167FD4, 0x66902F4C, 0x7A794932, 0x54B152C , 0x30856EA9, 0x39466D55,
+ 0x36696451, 0x0F5B1E8C, 0x077A3C6A, 0x51B956B4, 0x367E2D2A, 0x1D2C662A,
+ 0x78FB6880, 0x4E6D40B6, 0x40706FDC, 0x4DF9679C, 0x20306EDB, 0x63812AE7,
+ 0x255D2748, 0x1B8B617B, 0x3E036FAD, 0x04E444A7, 0x55A37517, 0x669B2988,
+ 0x18FD5E8C, 0x67BD05CE, 0x34BB346C, 0x76994800, 0x05B958B6, 0x6DFA2FEF,
+ 0x2055B5C , 0x1F843C4C, 0x72721B52, 0x73EF6B86, 0x5FB90B61, 0x43235DAC,
+ 0x31D424B4, 0x768C0D7E, 0x162F2F9D, 0x7B2A7A99, 0x79392693, 0x442D12C0,
+ 0x0692273E, 0x59A16E80, 0x5D956856, 0x44E73DAC, 0x0D874532, 0x5F5C1DD0,
+ 0x5D167858, 0x05597EA2, 0x1D821476, 0x59654ED2, 0x594C0DC7, 0x1A873506,
+ 0x3F693200, 0x7A651AB5, 0x20CC3C8A, 0x1F9E662C, 0x78E7631 , 0x2A01DA0 ,
+ 0x3088472F, 0x12EE0D42, 0x360D4D5F, 0x73337E48, 0x0D634C06, 0x233A0ACB,
+ 0x706651ED, 0x7AA54079, 0x262239D1, 0x3EBB6BB6, 0x225A4F3D, 0x32581A06,
+ 0x6E6F5780, 0x577377C7, 0x75ED1DDC, 0x10DF2D15, 0x3C7929BC, 0x37175917,
+ 0x354E381C, 0x762A2DD7, 0x76435AC1, 0x73BB749E, 0x52FE4E7E, 0x6C8140F4,
+ 0x57694875, 0x12D30822, 0x474227CF, 0x37926D98, 0x121C7E24, 0x204E1EE7,
+ 0x58C6268 , 0x2152080 , 0x316C3323, 0x7AB14A31, 0x61C13C03, 0x7D8E74F1,
+ 0x73F446D0, 0x6C6C6A0A, 0x3BFD79FB, 0x67242969, 0x3E5524EB, 0x0FF5534 ,
+ 0x52F05F1C, 0x17102DE3, 0x540F4A21, 0x798468E7, 0x419545EB, 0x193F7880,
+ 0x2B246B20, 0x408A2BC4, 0x4BF66A49, 0x40894C55, 0x4CAA6398, 0x247856E9,
+ 0x2F2A647D, 0x22F55D33, 0x70D37915, 0x50634C72, 0x5983671 , 0x2BCC5AF8,
+ 0x1A77D48 , 0x411B5CFA, 0x71074D7E, 0x3A6B3593, 0x61425F05, 0x6271012A,
+ 0x5B830310, 0x3D8418CA, 0x10A50792, 0x239F7137, 0x213D5071, 0x7F9930D4,
+ 0x2462664F, 0x54180F8E, 0x291505BA, 0x6586387A, 0x144B2C12, 0x18E425C7,
+ 0x3AA43373, 0x18F0503C, 0x19462AC0, 0x58B452EF, 0x72473895, 0x26BF5435,
+ 0x6DA553B , 0x60912FA6, 0x5C337331, 0x3D93CD7 , 0x4D035752, 0x20691929,
+ 0x389962F9, 0x36E701E9, 0x758B642C, 0x5FCA69E3, 0x596027F4, 0x2D5A2FD0,
+ 0x5F18324A, 0x3DB165AA, 0x76BA3876, 0x1BC21AF6, 0x3CC10841, 0x73A60174,
+ 0x625B7F58, 0x67C57724, 0x4458653C, 0x61573095, 0x2B370837, 0x03DF6CE3,
+ 0x5D086EFA, 0x3F5227C2, 0x191B4785, 0x60843D82, 0x30DE11F1, 0x105E226C,
+ 0x6E1C7AA2, 0x47AA5D14, 0x36676D03, 0x3B8D4DF6, 0x7372694 , 0x409521DC,
+ 0x744206A , 0x4722023F, 0x2BE46AD5, 0x63E11D76, 0x4A4A09AB, 0x5CF252B9,
+ 0x31586916, 0x4DFD7D84, 0x32037634, 0x2D7329D4, 0x4524582F, 0x2E5366C1,
+ 0x3B0E019B, 0x38530C6A, 0x6A2542D , 0x0A6A00E5, 0x119725CC, 0x54065347,
+ 0x1B6F7AF1, 0x6CCF71F1, 0x181117F2, 0x71674A76, 0x74F43880, 0x77A55F47,
+ 0x59EA5B62, 0x4A331D95, 0x3CBB276F, 0x245C4D50, 0x4718D5 , 0x07CE05D1,
+ 0x60D47AD5, 0x25CA1C40, 0x30061766, 0x669B39DF, 0x3D5F1320, 0x19306AD3,
+ 0x28B30325, 0x0DD090F , 0x6A6E6F37, 0x2DF16F66, 0x2B514C7E, 0x31101C58,
+ 0x7D4847FC, 0x515341CA, 0x77AB0EA6, 0x41320DAF, 0x3AF8531E, 0x24B31611,
+ 0x6D377331, 0x7A832A22, 0x222511C7, 0x722D1F89, 0x3B194F18, 0x261B0A4D,
+ 0x43F676DB, 0x4F8C6D61, 0x190F2250, 0x202E72A9, 0x560D4EA2, 0x308E67B4,
+ 0x36746663, 0x17CC3852, 0x27EB2EAC, 0x7FDE0AA8, 0x264719A , 0x23261EDD,
+ 0x3C0B339E, 0x06284D40, 0x48D82ECB, 0x24D44CF8, 0x43631B91, 0x4BF04248,
+ 0x36497B9B, 0x68273C58, 0x630B7AF9, 0x20CC3F26, 0x6C3B7B71, 0x574433ED,
+ 0x7A2552F6, 0x4CDE642D, 0x565B0142, 0x26F9207F, 0x67A207BE, 0x5B506684,
+ 0x44DA4780, 0x11756A0C, 0x156104AF, 0x415561B0, 0x6E3A6886, 0x1DBA1EA2,
+ 0x542359C8, 0x4C024E22, 0x758F052A, 0x1DD6395 , 0x2D194BAD, 0x616475A1,
+ 0x42084602, 0x09C274AD, 0x13CB5562, 0x57FE2D5B, 0x607A4EE5, 0x16723A91,
+ 0x4F624CCF, 0x2E5E24A3, 0x28FE6FAF, 0x3DDA6EF4, 0x32AF540C, 0x19A57B3B,
+ 0x5D1D73A3, 0x23424B3E, 0x278445F5, 0x53971C3B, 0x427D7943, 0x5221358C,
+ 0x26CE1A5E, 0x7B506CA4, 0x3B86636E, 0x60831F6D, 0x45E142F3, 0x21B77B04,
+ 0x7BB65E0C, 0x78B80F5E, 0x7D8D172B, 0x3BF33A90, 0x2D572D9 , 0x2B5B4920,
+ 0x36A05E01, 0x52745306, 0x47C64855, 0x1CAA669B, 0x304A2641, 0x4D6B1760,
+ 0x3E176D79, 0x523241B0, 0x24A67957, 0x4BDE76AF, 0x4E5F1493, 0x4C215DA5,
+ 0x33A052B , 0x1A4D00C2, 0x40AE6BCA, 0x390D106B, 0x69E86018, 0x5AF356CF,
+ 0x63561D4 , 0x44F31C6 , 0x14B6299B, 0x0D2E25F0, 0x4CBF132A, 0x45AC18B6,
+ 0x2227567D, 0x06B54E2F, 0x26344534, 0x22C515EC, 0x2442370D, 0x6C3721C6,
+ 0x34EF687D, 0x1C06323A, 0x6AF36A60, 0x60396F52, 0x6AE70AA1, 0x49D06CBC,
+ 0x6F9576C8, 0x584C4258, 0x3A9A27BB, 0x66DF0D47, 0x1D4804EA, 0x57DD1E67,
+ 0x789C7895, 0x75336111, 0x25C122C8, 0x62742114, 0x4FBF6D26, 0x3F9F6482,
+ 0x66F02CD9, 0x11083202, 0x499E2618, 0x7EBC1351, 0x440112F1, 0x49DF7BC1,
+ 0x3BF45C25, 0x31BA7FA0, 0x61AF1AED, 0x6B1F7D29, 0x2D865294, 0x63E01129,
+ 0x7E9E77A5, 0x100435D7, 0x1FE3A71 , 0x08597C81, 0x722849FA, 0x31C520AF,
+ 0x7BA178DC, 0x7F102D31, 0x5CA07864, 0x150E6F98, 0x02C34882, 0x5D041F11,
+ 0x0C613C57, 0x53984FD1, 0x426F38AD, 0x55992B1D, 0x7AFA078D, 0x2B253413,
+ 0x594B32CF, 0x32887E38, 0x28933B46, 0x1A0B4168, 0x291B4A94, 0x653A5E8D,
+ 0x21746BBE, 0x5EFE6415, 0x30DA429C, 0x50C5640C, 0x34711AA4, 0x529C67A6,
+ 0x105957CD, 0x4D287499, 0x03CA0AA7, 0x28385832, 0x25A04A02, 0x420D47A4,
+ 0x35627556, 0x4BC11E4C, 0x59E215C7, 0x27E838B4, 0x458612F4, 0x22827F6F,
+ 0x449D4DBA, 0x679B7362, 0x4E495845, 0x4FD270D1, 0x395E76A0, 0x375A655E,
+ 0x12E2058F, 0x73F970CA, 0x61EF73B3, 0x51FF5362, 0x67410345, 0x7FDA0B3B,
+ 0x221962E8, 0x17AB6543, 0x26557412, 0x4B30084D, 0x268E191D, 0x7E0D13DF,
+ 0x73EF127D, 0x4DEC5DB1, 0x77FA745F, 0x56002898, 0x12DD0A40, 0x157F6DDF,
+ 0x42A55F8E, 0x43597924, 0x7B630C3F, 0x338B6B58, 0x32945F75, 0x4FA23A0E,
+ 0x036E38C0, 0x33B18FD , 0x06114337, 0x24660ACB, 0x19BB02F0, 0x124C0A47,
+ 0x3A951701, 0x01155ABF, 0x0C612D71, 0x36074CA7, 0x51660C41, 0x635F58C7,
+ 0x7FC2002D, 0x0E6A7CF3, 0x65B07D07, 0x015F6A6B, 0x791B70DD, 0x6E475719,
+ 0x424314C7, 0x68426EB , 0x71942FEE, 0x464A2F52, 0x677579FD, 0x6BA775AE,
+ 0x1F66EFF , 0x1A795237, 0x78D9545F, 0x1D0B344D, 0x3BD34AB7, 0x2F85312A,
+ 0x16C542AD, 0x3990185D, 0x08DF3351, 0x02811AA5, 0x6D351F41, 0x4066269D,
+ 0x06B660BF, 0x6EDB4768, 0x5DD70CF0, 0x35D74F6E, 0x689E220C, 0x11431687,
+ 0x147C49C9, 0x385762BD, 0x302F0AE4, 0x1DAB67F8, 0x483256C9, 0x37D50FCB,
+ 0x4EA82711, 0x4D7B2C98, 0x19DB78BC, 0x58DE0DC2, 0x6AFF7E7B, 0x37621C93,
+ 0x792C6E19, 0x77001192, 0x7F88439D, 0x2E196A66, 0x6C71378C, 0x6AF43B3A,
+ 0x7C16225E, 0x6687337 , 0x4BEE1608, 0x6D5B5552, 0x345D4590, 0x681209CC,
+ 0x7B242819, 0x508A1416, 0x19880FE3, 0x1FC7288A, 0x24BD0502, 0x6A1D1678,
+ 0x20E6CA0 , 0x59BE2057, 0x5ADE11EB, 0x5EA8649D, 0x7A200E6F, 0x1149481D,
+ 0x72281E93, 0x0A5B0451, 0x67312D58, 0x63B849F1, 0x52217960, 0x7CDF59F3,
+ 0x33C775C0, 0x1EBA0799, 0x7DF1506 , 0x34E96110, 0x38FC73E3, 0x5EA059B2,
+ 0x022936EA, 0x316406F6, 0x43911185, 0x6C0D10F3, 0x1C6F3DF8, 0x38DB12A9,
+ 0x5CD41244, 0x2C9F0A7B, 0x5F4A315F, 0x77CE1C66, 0x4C800860, 0x318D53E0,
+ 0x7105420D, 0x575361F2, 0x750810BA, 0x217E4CA5, 0x2010140 , 0x4D884763,
+ 0x42BB0DA7, 0x32D53A74, 0x141C6CD4, 0x087F5FC3, 0x464B53 , 0x2D2A05F6,
+ 0x15532B45, 0x5D5C3CE1, 0x3EB9216A, 0x2214611B, 0x1FC52C5F, 0x11AE5DD7,
+ 0x20B925A9, 0x7C640AF4, 0x740009AC, 0x6D0E0321, 0x38E6A61 , 0x09104544,
+ 0x474F26C8, 0x15254CF3, 0x341A6B59, 0x661904CE, 0x598B2197, 0x2412659D,
+ 0x61976DD4, 0x329B3E16, 0x08FD1FB0, 0x304006F3, 0x3456309 , 0x55CC15F1,
+ 0x59DA7630, 0x5C801335, 0x0036D52 , 0x353775A5, 0x299476EB, 0x75280568,
+ 0x766F5264, 0x2EA233A6, 0x647619F3, 0x7FB30C7A, 0x1BC03B9 , 0x36BC3061,
+ 0x3F30596E, 0x3E2A527B, 0x0AC04220, 0x641979A3, 0x1ECC3B89, 0x21447BC1,
+ 0x4E8F2E26, 0x0C5A1D90, 0x299E5467, 0x57C947E3, 0x1D4865ED, 0x76F31C3D,
+ 0x4EE81CDF, 0x3479195E, 0x6FFB3AE1, 0x5C82398 , 0x300F7364, 0x47940AFA,
+ 0x3B853E3E, 0x598C440D, 0x224A3D89, 0x3A674204, 0x22880A38, 0x2E77F2D ,
+ 0x22841C9C, 0x4F0609C3, 0x1FE90922, 0x09335017, 0x2D6B69A7, 0x7EDB63F9,
+ 0x099A74EF, 0x1F9F1B40, 0x24BE17E8, 0x251D2F7A, 0x16AC50D3, 0x28D7ED6 ,
+ 0x6D193443, 0x76156F1B, 0x30DF6A4E, 0x64FF6794, 0x63DB2C9A, 0x74353022,
+ 0x556E025C, 0x23802AF9, 0x425018A4, 0x675A18BB, 0x70B227B9, 0x7FB01BF ,
+ 0x63E7910 , 0x6C661591, 0x65745D2B, 0x4F6E379D, 0x52B32FAC, 0x1E6A1101,
+ 0x1DE22385, 0x2338191F, 0x469704B6, 0x4BAB4599, 0x54EB4809, 0x78393E6D,
+ 0x550017DD, 0x39B120E1, 0x288D52D3, 0x2D52668C, 0x20D22A68, 0x4E1207D1,
+ 0x3FCC0EFE, 0x47F37E64, 0x25177A90, 0x34BF5D4D, 0x5A8D3DCE, 0x6F7275A8,
+ 0x6BEA2655, 0x2A1810FC, 0x64DB593A, 0x0A4D4BC0, 0x2C402E93, 0x71C077F9,
+ 0x6F0C4577, 0x70412414, 0x752F1DC1, 0x582E38EA, 0x2C455F7B, 0x4DCD4EDB,
+ 0x12BC2696, 0x7B037135, 0x4FCA1F8C, 0x3D5E75F6, 0x502F41B0, 0x361653F1,
+ 0x2E5B0E31, 0x20266B19, 0x57E703D7, 0x467B3E00, 0x47032BA3, 0x1F776B9C,
+ 0x62570A84, 0x7EC75B48, 0x1BD5012 , 0x7D0A2D5D, 0x7FCC29F2, 0x291304B6,
+ 0x19D558ED, 0x47551C8 , 0x7D12738F, 0x3ADE0892, 0x5F741997, 0x25D2E2F ,
+ 0x2B9F2269, 0x5C134FED, 0x15E92399, 0x54437F4E, 0x272D32AB, 0x56186AA1,
+ 0x7E4D355C, 0x234D7836, 0x2A871760, 0x4637A94 , 0x2C183207, 0x5FC78B3 ,
+ 0x7F10621E, 0x276966B2, 0x6C9F4A11, 0x4E3F182C, 0x62BA2EF5, 0x25F239CD,
+ 0x73D63FED, 0x636E1F5E, 0x0AC15A0E, 0x3F3D33EB, 0x738326EA, 0x35C366B1,
+ 0x4D476E86, 0x02F63208, 0x711A1FC1, 0x426A4396, 0x7E4D1B93, 0x75E46DB7,
+ 0x2F3C44A7, 0x51A56F5C, 0x7AD2463D, 0x0A5639CA, 0x49952C78, 0x4C4B64F6,
+ 0x3AFE7F8D, 0x66993D04, 0x43867F37, 0x4BC146C2, 0x55A875EC, 0x681A1A75,
+ 0x30A67E1B, 0x4A4A7D0C, 0x20F77993, 0x1891805 , 0x738976AD, 0x542667D6,
+ 0x3C5C6EBF, 0x4499187F, 0x2BF17C97, 0x447C317F, 0x68D8419C, 0x7AAB6456,
+ 0x421B4F29, 0x76740F9C, 0x09163B8D, 0x3D72AAB , 0x1AD54DD7, 0x754946EE,
+ 0x7317342B, 0x218546D4, 0x10563DA7, 0x54BB4CCE, 0x0CE63E46, 0x5D146234,
+ 0x33BE6C63, 0x325044E5, 0x09D72335, 0x07C36BA , 0x365530CC, 0x2DFA448C,
+ 0x1663516F, 0x59B00AA , 0x150274EA, 0x12532D4A, 0x3CEF002D, 0x492F3DA5,
+ 0x263A2574, 0x6F8005C2, 0x14A10651, 0x2F627ABA, 0x68293238, 0x26987646,
+ 0x52590516, 0x10144D36, 0x59B151B9, 0x2B2A4F05, 0x53953699, 0x27851C75,
+ 0x180646F3, 0x2E970306, 0x32843145, 0x18F4FE8F
+};
+
+/* The source data is random across the q31_t range. Accessing it by word should
+ remain random. */
+const q15_t * fast_math_q15_inputs = (q15_t *) fast_math_q31_inputs;
+
+const float32_t fast_math_f32_inputs[FAST_MATH_MAX_LEN] =
+{
+ -1.5E-07, 5.0545058, 6.1958757, 0.1884450, 3.3656774, 0.5471223,
+ -5.0396892, 6.2149808, 0.4206357, 5.9024140, 0.1142128, 4.2966847,
+ -4.9243615, 3.3560853, 5.5628775, 5.6486144, 3.9328821, 0.8662564,
+ -1.3684878, 1.1444261, 0.2627620, 0.6719343, 3.8732286, 5.9040643,
+ -2.2271110, 2.5800587, 6.1848498, 5.9412493, 4.2514839, 6.2096863,
+ -4.8181437, 2.1155439, 4.1618680, 1.5341357, 1.8567268, 4.2736867,
+ -3.3165594, 2.5861183, 3.7864876, 4.7156566, 3.6664471, 3.4670146,
+ -3.6666823, 3.2158594, 0.5189454, 4.5211925, 6.2590334, 2.2276047,
+ -6.1025991, 2.1768018, 5.5703194, 2.8569321, 2.5976403, 1.3680509,
+ -0.7895111, 1.9409676, 4.5622487, 4.9189303, 4.3591961, 0.0615894,
+ -5.2980657, 5.7951829, 4.8440482, 0.2680398, 2.3762136, 4.4254964,
+ -4.5836656, 1.4091744, 1.6905207, 4.2287795, 3.0001720, 3.9189258,
+ -1.4856273, 1.1129014, 5.2128031, 4.8187110, 5.8715002, 0.6778860,
+ -1.1449692, 0.6226340, 3.0772767, 1.2141962, 5.6290528, 0.6225986,
+ -0.2775005, 3.5015887, 4.8537297, 1.9599772, 1.1245801, 2.1297213,
+ -1.3203840, 3.2053828, 5.6948550, 3.9516457, 0.6379562, 2.4558128,
+ -0.3431663, 3.1496534, 2.7125841, 6.2678565, 5.0994494, 3.0514394,
+ -5.6199810, 0.8642307, 2.4504731, 5.8267510, 5.7647838, 4.4835177,
+ 3.8851284, 2.1569414, 5.8812331, 0.7839784, 4.5904032, 4.0619375,
+ 5.2348483, 2.5024810, 4.7112719, 5.2478452, 2.0260784, 3.4699621,
+ 6.1520498, 3.4514073, 2.0761128, 3.8922546, 2.2659464, 4.7532896,
+ 2.6006151, 3.0934955, 4.3652005, 6.1118673, 2.0593452, 5.2640727,
+ 4.6437278, 5.9952549, 0.2005758, 2.2422740, 4.1635768, 1.7687265,
+ 1.4475395, 4.4681525, 3.9243074, 3.7109036, 4.1496541, 0.2987948,
+ 2.1914796, 2.8358565, 1.5136507, 4.4927603, 5.3795520, 1.7687650,
+ 4.5933278, 0.8655898, 5.2572843, 0.8708603, 3.6958286, 2.3006310,
+ 5.0690197, 3.1653480, 3.0762120, 5.5106597, 2.2188555, 2.8239372,
+ 6.0540393, 0.2657649, 6.1132775, 1.1888217, 4.1916405, 3.6847088,
+ 4.2418564, 2.2683684, 3.8973243, 5.0966113, 0.1209983, 0.5269928,
+ 6.1248595, 4.0925498, 1.4529100, 2.5352096, 0.7666775, 1.6866509,
+ 1.6200953, 2.0839142, 0.9565145, 2.1865966, 0.7644026, 5.5552975,
+ 0.5923686, 5.8436176, 2.5071164, 0.2978322, 2.1511962, 4.6242118,
+ 4.9931353, 3.4237447, 4.3116692, 5.6148598, 0.3442670, 1.9079607,
+ 0.2902301, 1.2282167, 4.5249352, 4.5349096, 5.5153742, 3.6595342,
+ 0.4441228, 5.7977751, 5.0288862, 1.7966571, 3.4159368, 6.1875316,
+ 4.4967379, 5.2714014, 2.7222564, 2.9570223, 3.5230663, 1.6907520,
+ 4.7062218, 3.1660203, 4.0640250, 1.9336225, 0.8716326, 2.9881129,
+ 2.2773988, 4.9518627, 4.9027432, 4.2003861, 0.8388295, 0.1354396,
+ 3.5175829, 1.8901016, 5.9024853, 6.1631993, 1.8008890, 5.0317023,
+ 5.6304337, 3.7543702, 5.5544410, 5.9296402, 3.4504620, 4.5765894,
+ 3.6238793, 0.1624673, 2.8056369, 4.0608350, 3.2748147, 2.3393094,
+ 5.8881908, 5.2121085, 5.3349614, 2.3407017, 3.7270886, 5.4824095,
+ 5.8653636, 4.2000849, 1.2992148, 4.1082644, 0.4527132, 2.5555406,
+ 4.1904544, 5.8667713, 5.0953493, 3.0445066, 4.7547955, 2.6203864,
+ 6.1059115, 6.2076281, 5.4295991, 2.4434288, 2.8572272, 1.5499814,
+ 4.9286757, 5.5470323, 5.7410198, 3.5078076, 3.7627993, 0.9354200,
+ 5.6530665, 2.8299063, 1.2922774, 5.6526739, 4.7914663, 5.5448250,
+ 1.7903950, 4.2300036, 4.1737937, 0.7716694, 2.5592571, 1.7296789,
+ 4.5029688, 1.7805566, 5.6309835, 5.1935484, 2.4506089, 3.1284165,
+ 4.3655898, 5.2424950, 3.8304163, 3.6111801, 2.0485834, 2.8678003,
+ 4.4849099, 5.5568808, 4.5292698, 0.1169475, 4.2397456, 2.7552322,
+ 2.7509053, 0.7353640, 5.1187960, 2.0411269, 1.5470969, 2.1533307,
+ 2.3605433, 3.4340988, 3.5306485, 2.4870244, 2.5015301, 3.2381477,
+ 4.1313862, 5.9747764, 4.5386496, 2.5137752, 5.2268018, 0.8440727,
+ 0.3799239, 0.5293398, 0.0000000, 2.0371338, 1.8958053, 0.0733938,
+ 3.3923238, 0.5992443, 0.9205800, 3.9655772, 5.3992694, 6.1212150,
+ 3.5866836, 6.2633946, 3.4780043, 3.2387210, 2.0777367, 2.7017810,
+ 3.0901098, 0.4463392, 5.5778300, 0.4061048, 2.7406309, 5.1938664,
+ 2.4789345, 3.8545764, 5.1436714, 5.5683790, 5.8503469, 1.1987353,
+ 1.6247202, 5.6414565, 3.7282025, 3.1657206, 3.8503962, 5.1485818,
+ 3.3419582, 1.2696753, 2.8518968, 2.6886436, 6.0698884, 3.8959208,
+ 4.3692639, 4.5249277, 2.1796068, 3.2483466, 3.4978155, 0.9832885,
+ 3.5315023, 4.3655778, 2.6794992, 5.2544420, 4.5954405, 2.2621418,
+ 2.8539005, 2.4277593, 4.8729535, 4.6135614, 2.7035154, 4.3589760,
+ 5.9389515, 4.9274787, 4.4332387, 0.6869673, 2.4500066, 3.7127639,
+ 2.8863700, 0.3162955, 1.4368865, 5.2413645, 0.0982985, 5.4268554,
+ 0.4905223, 4.2037186, 3.1429204, 1.3696954, 3.5915675, 0.7677371,
+ 4.2170618, 3.7673071, 0.3517086, 0.3540136, 0.9581898, 0.1232828,
+ 2.7342886, 5.2290017, 3.8791769, 3.2680695, 5.4278441, 0.6138541,
+ 5.7054603, 0.6786889, 3.2483864, 0.8994758, 3.5146290, 0.0287746,
+ 4.8172051, 5.3325973, 5.7605579, 6.2013046, 3.1738449, 1.7053924,
+ 0.6330341, 3.1909083, 3.6794907, 4.7933610, 0.5212697, 4.1569315,
+ 3.2482749, 1.0747264, 5.8971330, 3.7101152, 2.7685894, 5.9182512,
+ 4.1212281, 2.8396586, 5.2759745, 3.3465722, 3.4801751, 4.2729777,
+ 2.3071222, 1.5035072, 3.6374836, 5.4468120, 2.5558538, 0.7075818,
+ 2.7887656, 1.8861142, 2.5219880, 5.2361777, 2.5360737, 2.4515477,
+ 2.2647672, 0.8812504, 1.6344462, 0.5454754, 2.6979830, 1.6165554,
+ 1.8695956, 2.6694641, 0.7490013, 3.1105972, 4.4384875, 1.5304166,
+ 4.9327408, 0.4655185, 2.4748426, 0.0213259, 1.3865538, 0.0081717,
+ 1.1886509, 0.8952537, 1.6843712, 1.0988793, 0.8711572, 3.7629093,
+ 5.6615138, 5.9022971, 1.3897429, 3.0327137, 2.3625475, 3.2910070,
+ 1.6642436, 0.4295011, 2.7415239, 1.0923508, 0.1640358, 5.9984205,
+ 2.7055177, 6.0416507, 4.7903915, 0.0461730, 4.2728088, 4.4356194,
+ 4.0534637, 3.4702651, 1.3704176, 4.8529200, 1.4327442, 2.3302118,
+ 5.5978709, 5.3807748, 2.5285646, 1.9981730, 3.8241692, 5.7189253,
+ 5.7120324, 3.7170973, 2.0896078, 5.3599569, 2.7796679, 5.6822331,
+ 0.2084724, 3.3453343, 4.5018856, 1.1265867, 2.1144987, 1.1794352,
+ 2.0227281, 2.5375066, 3.4467437, 0.3062336, 3.4729184, 1.7266910,
+ 1.5174002, 1.5277262, 0.9686124, 6.0093412, 5.8789338, 5.1441345,
+ 4.5758041, 1.1046577, 2.2642776, 1.1862024, 0.0075297, 1.9881224,
+ 4.3958232, 3.9285942, 3.4121603, 2.7585521, 1.8059588, 3.1520171,
+ 4.7849358, 4.7903511, 3.6194660, 4.6977042, 4.0560129, 0.7742111,
+ 3.1692252, 2.1819072, 0.5789810, 0.9289656, 1.2451370, 4.2239985,
+ 2.7112647, 4.3630684, 1.6134250, 0.0613154, 3.3444332, 1.7554715,
+ 5.9453394, 5.6953510, 2.4673100, 0.1561700, 4.2187618, 5.2600982,
+ 6.1041123, 0.3577199, 2.8294680, 3.6597688, 4.3142726, 4.5203293,
+ 4.0843265, 4.5673388, 2.3489542, 3.6541880, 0.7295941, 0.3622530,
+ 6.1560465, 1.7896003, 3.7383338, 6.0454361, 1.1672793, 1.2129049,
+ 2.1466132, 5.8615704, 2.4546365, 1.7166712, 0.9547117, 2.4951084,
+ 2.3544507, 0.8238180, 2.7334414, 0.5749942, 3.8618151, 0.0689837,
+ 3.6019012, 4.9620190, 1.4788531, 2.8149909, 3.5773830, 0.3857966,
+ 3.1182750, 4.0357856, 1.3902536, 5.2593808, 6.1014456, 5.3179177,
+ 3.1792883, 1.7522271, 4.6911344, 1.4886775, 6.0151778, 3.8972087,
+ 3.7715583, 1.0845061, 0.5676653, 1.6038597, 5.3945577, 5.7244031,
+ 4.3959286, 4.5564551, 1.4444168, 3.6194506, 5.0933266, 2.5374227,
+ 6.2105471, 0.5654792, 2.0165320, 3.2132771, 0.3808010, 4.5596317,
+ 3.4969429, 3.3260664, 5.2149334, 5.3957421, 4.9576149, 1.9970040,
+ 2.8413032, 4.7263877, 0.6902815, 0.6895316, 1.6957291, 3.2963937,
+ 6.1113470, 4.4636294, 1.9594738, 1.8312791, 5.3429527, 5.7280497,
+ 4.0166905, 1.6045389, 0.5571039, 5.2669152, 3.6738954, 5.9571429,
+ 0.3834561, 3.6734096, 1.7913869, 5.2007946, 1.2000032, 2.7804978,
+ 2.4718774, 5.1935175, 4.2529065, 1.3044083, 1.9987109, 0.8407592,
+ 4.2189258, 3.5876427, 1.0666779, 0.9277486, 2.9912971, 5.7057758,
+ 3.4694180, 0.2069675, 0.3384307, 5.0583614, 2.8360719, 2.4042372,
+ 4.9614777, 2.2888819, 3.3448533, 4.4714710, 5.4756485, 2.0652177,
+ 4.0848120, 6.1250762, 0.4773170, 3.6883502, 2.6005256, 1.9423615,
+ 1.6577182, 4.7674690, 6.2531264, 1.1722630, 4.9080805, 1.2302350,
+ 6.2351753, 5.0407581, 2.6654950, 4.5795867, 3.1312479, 5.0830358,
+ 2.2400117, 0.4602021, 3.7133088, 5.7188788, 1.2174673, 2.7166470,
+ 4.7071094, 0.2462034, 5.9459353, 4.7983010, 3.5111731, 1.1551193,
+ 3.1287047, 3.2537199, 6.2470131, 5.3711915, 6.0469623, 4.2659122,
+ 2.5352740, 5.8746469, 3.0126903, 1.4563896, 2.4899651, 4.4301324,
+ 3.5095299, 4.7540509, 6.2547920, 6.0471349, 3.3619258, 6.0561746,
+ 0.7264988, 0.3232592, 1.9122808, 3.6454528, 3.3361480, 5.6624574,
+ 3.3963785, 2.7142142, 3.4096772, 4.4762342, 0.1047703, 5.0323343,
+ 0.8954125, 3.0063438, 1.6137441, 2.3190715, 4.1579916, 1.0656836,
+ 1.7516517, 1.2454643, 1.2256706, 2.0535941, 5.5313259, 2.9600203,
+ 2.5382144, 1.1261446, 6.0879353, 2.5601199, 5.3060708, 3.8662016,
+ 2.3663172, 5.5114955, 4.9313732, 2.9213939, 5.1143679, 5.6450910,
+ 2.6969853, 2.1006537, 3.7488443, 5.6673754, 4.4112136, 2.3716204,
+ 4.6178643, 5.9948046, 3.4105954, 3.3935850, 1.9547595, 0.4475800,
+ 1.1434170, 0.5842667, 2.9121888, 0.0586379, 5.7492774, 4.0384655,
+ 0.0089162, 0.1909163, 1.3098570, 2.8586366, 0.7996361, 0.0543350,
+ 4.5683759, 2.2249794, 4.9036865, 2.7435946, 2.7429546, 0.3092155,
+ 0.3118464, 0.5723993, 3.7324447, 1.5147758, 5.2864780, 5.3860266,
+ 6.0545540, 3.0718480, 1.3842492, 1.4213108, 3.3727372, 4.7884765,
+ 2.1838288, 2.8980046, 4.0169897, 5.7637923, 1.0151904, 4.4964699,
+ 3.6300404, 2.7224978, 5.5558613, 2.4696170, 1.1245340, 3.9793522,
+ 3.9207111, 2.0605178, 5.0451799, 6.2799046, 6.1636676, 0.7981966,
+ 1.4592079, 0.1484872, 3.8166117, 0.6962355, 2.5601436, 5.5548184,
+ 3.4440198, 2.3185147, 1.3090764, 2.7705283, 6.0079576, 0.7792778,
+ 2.9578927, 5.3840384, 0.2726304, 4.3456090, 6.1511471, 1.7798247,
+ 0.8405677, 4.3057392, 5.7142715, 3.8382030, 5.6547587, 1.2153801,
+ 4.7401894, 2.1756202, 2.6303011, 0.9784166, 5.1459324, 3.9265103,
+ 4.6405120, 5.0586705, 0.4223724, 5.9739917, 3.1263686, 4.7447217,
+ 4.6646686, 5.2221411, 0.9833301, 2.8733554, 3.8836400, 5.8570808,
+ -5.2470141, 5.6261119, 3.6600718, 3.6615062, 5.3716581, 0.2190677,
+ -5.5632585, 2.5618482, 0.2285950, 4.6881858, 0.9728179, 0.9042027,
+ -3.8073530, 1.5989503, 2.0367209, 2.5245268, 2.5533189, 2.4265105,
+ -3.8314979, 1.0486053, 1.1818174, 0.5945707, 2.0306392, 4.8355201,
+ -1.4710068, 4.6518534, 4.3531065, 5.1778361, 5.2023364, 1.8432851,
+ -1.9438243, 3.2862931, 2.0439139, 5.2266206, 5.0912323, 3.4997233,
+ -1.6522518, 4.2761236, 1.4680860, 2.8678051, 2.4163051, 3.3841326,
+ -6.2310582, 4.7451897, 6.1603795, 1.4751828, 3.3210347, 0.3231823,
+ -4.7555888, 3.7823504, 5.3857498, 6.2095284, 5.8401232, 2.5730582,
+ -0.0021455, 3.3984387, 1.3052100, 1.3777994, 2.0471011, 0.6028680,
+ -4.6968925, 4.7030205, 3.4136510, 2.1245480, 5.2297066, 3.4719134,
+ -6.0164208, 5.6098372, 2.2399783, 3.4331443, 2.1782657, 3.9131853,
+ -5.0053405, 4.6864702, 0.7887674, 5.1672539, 0.1580253, 2.6039335,
+ -4.5955687, 4.9095176, 2.3077255, 4.6801428, 5.6062801, 1.5243220,
+ -0.8142818, 1.4141432, 2.1992023, 1.8038058, 5.8275790, 0.3224138,
+ -3.7238350, 1.0235240, 5.2678588, 1.0528164, 3.1554195, 6.2789723,
+ -2.2330890, 0.2957980, 1.3424690, 2.4996969, 2.0964990, 1.4426353,
+ -5.8818165, 4.2926017, 6.0451393, 2.7518666, 5.9083095, 0.0366581,
+ -3.8346722, 5.0333074, 1.4638661, 5.8588735, 4.7957215, 5.1927356,
+ -3.6031780, 4.9799375, 2.0674268, 1.4040530, 1.9627813, 3.6726693,
+ -5.2145043, 1.8250297, 2.5293238, 5.4164658, 3.8625225, 6.2278165,
+ -1.2798778, 5.1975080, 4.2465638, 1.5641957, 2.9894493, 2.5074636,
+ -3.7663816, 5.0298329, 0.6601666, 5.1612735, 5.2847013, 2.2274284,
+ -2.7022061, 3.5954850, 4.4034117, 4.6650751, 4.7619266, 2.4449681,
+ -2.6973871, 6.0088907, 3.6000853, 5.3389611
+};
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/biquad_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/biquad_tests.c
new file mode 100644
index 0000000..3157d1c
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/biquad_tests.c
@@ -0,0 +1,244 @@
+#include "jtest.h"
+#include "filtering_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "filtering_templates.h"
+#include "type_abbrev.h"
+
+#define BIQUAD_DEFINE_TEST(suffix, instance_name, config_suffix, output_type) \
+ JTEST_DEFINE_TEST(arm_biquad_cascade_##config_suffix##_##suffix##_test, \
+ arm_biquad_cascade_##config_suffix##_##suffix) \
+ { \
+ instance_name biquad_inst_fut = { 0 }; \
+ instance_name biquad_inst_ref = { 0 }; \
+ \
+ TEMPLATE_DO_ARR_DESC( \
+ blocksize_idx, uint32_t, blockSize, filtering_blocksizes \
+ , \
+ TEMPLATE_DO_ARR_DESC( \
+ numstages_idx, uint16_t, numStages, filtering_numstages \
+ , \
+ /* Initialize the BIQUAD Instances */ \
+ arm_biquad_cascade_##config_suffix##_init_##suffix( \
+ &biquad_inst_fut, numStages, \
+ (output_type*)filtering_coeffs_b_##suffix, \
+ (void *) filtering_pState); \
+ \
+ /* Display test parameter values */ \
+ JTEST_DUMP_STRF("Block Size: %d\n" \
+ "Number of Stages: %d\n", \
+ (int)blockSize, \
+ (int)numStages); \
+ \
+ JTEST_COUNT_CYCLES( \
+ arm_biquad_cascade_##config_suffix##_##suffix( \
+ &biquad_inst_fut, \
+ (void *) filtering_##suffix##_inputs, \
+ (void *) filtering_output_fut, \
+ blockSize)); \
+ \
+ arm_biquad_cascade_##config_suffix##_init_##suffix( \
+ &biquad_inst_ref, numStages, \
+ (output_type*)filtering_coeffs_b_##suffix, \
+ (void *) filtering_pState); \
+ \
+ ref_biquad_cascade_##config_suffix##_##suffix( \
+ &biquad_inst_ref, \
+ (void *) filtering_##suffix##_inputs, \
+ (void *) filtering_output_ref, \
+ blockSize); \
+ \
+ FILTERING_SNR_COMPARE_INTERFACE( \
+ blockSize, \
+ output_type))); \
+ \
+ return JTEST_TEST_PASSED; \
+ }
+
+#define BIQUAD_WITH_POSTSHIFT_DEFINE_TEST(suffix, config_suffix, speed, output_type) \
+ JTEST_DEFINE_TEST(arm_biquad_cascade_##config_suffix##speed##_##suffix##_test, \
+ arm_biquad_cascade_##config_suffix##speed##_##suffix) \
+ { \
+ arm_biquad_casd_##config_suffix##_inst_##suffix biquad_inst_fut = { 0 }; \
+ arm_biquad_casd_##config_suffix##_inst_##suffix biquad_inst_ref = { 0 }; \
+ \
+ TEMPLATE_DO_ARR_DESC( \
+ blocksize_idx, uint32_t, blockSize, filtering_blocksizes \
+ , \
+ TEMPLATE_DO_ARR_DESC( \
+ numstages_idx, uint16_t, numStages, filtering_numstages \
+ , \
+ TEMPLATE_DO_ARR_DESC( \
+ postshifts_idx, uint8_t, postShift, filtering_postshifts \
+ , \
+ /* Display test parameter values */ \
+ JTEST_DUMP_STRF("Block Size: %d\n" \
+ "Number of Stages: %d\n" \
+ "Post Shift: %d\n", \
+ (int)blockSize, \
+ (int)numStages, \
+ (int)postShift); \
+ \
+ /* Initialize the BIQUAD Instances */ \
+ arm_biquad_cascade_##config_suffix##_init_##suffix( \
+ &biquad_inst_fut, numStages, \
+ (output_type*)filtering_coeffs_b_##suffix, \
+ (void *) filtering_pState, postShift); \
+ \
+ JTEST_COUNT_CYCLES( \
+ arm_biquad_cascade_##config_suffix##speed##_##suffix( \
+ &biquad_inst_fut, \
+ (void *) filtering_##suffix##_inputs, \
+ (void *) filtering_output_fut, \
+ blockSize)); \
+ \
+ arm_biquad_cascade_##config_suffix##_init_##suffix( \
+ &biquad_inst_ref, numStages, \
+ (output_type*)filtering_coeffs_b_##suffix, \
+ (void *) filtering_pState, postShift); \
+ \
+ ref_biquad_cascade_##config_suffix##speed##_##suffix( \
+ &biquad_inst_ref, \
+ (void *) filtering_##suffix##_inputs, \
+ (void *) filtering_output_ref, \
+ blockSize); \
+ \
+ FILTERING_SNR_COMPARE_INTERFACE( \
+ blockSize, \
+ output_type)))); \
+ \
+ return JTEST_TEST_PASSED; \
+ }
+
+
+JTEST_DEFINE_TEST(arm_biquad_cas_df1_32x64_q31_test,
+ arm_biquad_cas_df1_32x64_q31)
+{
+ arm_biquad_cas_df1_32x64_ins_q31 biquad_inst_fut = { 0 };
+ arm_biquad_cas_df1_32x64_ins_q31 biquad_inst_ref = { 0 };
+
+ TEMPLATE_DO_ARR_DESC(
+ blocksize_idx, uint32_t, blockSize, filtering_blocksizes
+ ,
+ TEMPLATE_DO_ARR_DESC(
+ numstages_idx, uint16_t, numStages, filtering_numstages
+ ,
+ TEMPLATE_DO_ARR_DESC(
+ postshifts_idx, uint8_t, postShift, filtering_postshifts
+ ,
+ /* Initialize the BIQUAD Instances */
+ arm_biquad_cas_df1_32x64_init_q31(
+ &biquad_inst_fut, numStages,
+ (q31_t*)filtering_coeffs_b_q31,
+ (void *) filtering_pState, postShift);
+
+ /* Display test parameter values */
+ JTEST_DUMP_STRF("Block Size: %d\n"
+ "Number of Stages: %d\n",
+ (int)blockSize,
+ (int)numStages);
+
+ JTEST_COUNT_CYCLES(
+ arm_biquad_cas_df1_32x64_q31(
+ &biquad_inst_fut,
+ (void *) filtering_q31_inputs,
+ (void *) filtering_output_fut,
+ blockSize));
+
+ arm_biquad_cas_df1_32x64_init_q31(
+ &biquad_inst_ref, numStages,
+ (q31_t*)filtering_coeffs_b_q31,
+ (void *) filtering_pState, postShift);
+
+ ref_biquad_cas_df1_32x64_q31(
+ &biquad_inst_ref,
+ (void *) filtering_q31_inputs,
+ (void *) filtering_output_ref,
+ blockSize);
+
+ FILTERING_SNR_COMPARE_INTERFACE(
+ blockSize,
+ q31_t))));
+
+ return JTEST_TEST_PASSED;
+}
+
+JTEST_DEFINE_TEST(arm_biquad_cascade_df2T_f64_test,
+ arm_biquad_cascade_df2T_f64)
+{
+ arm_biquad_cascade_df2T_instance_f64 biquad_inst_fut = { 0 };
+ arm_biquad_cascade_df2T_instance_f64 biquad_inst_ref = { 0 };
+
+ TEMPLATE_DO_ARR_DESC(
+ blocksize_idx, uint32_t, blockSize, filtering_blocksizes
+ ,
+ TEMPLATE_DO_ARR_DESC(
+ numstages_idx, uint16_t, numStages, filtering_numstages
+ ,
+ /* Display test parameter values */
+ JTEST_DUMP_STRF("Block Size: %d\n"
+ "Number of Stages: %d\n",
+ (int)blockSize,
+ (int)numStages);
+
+ /* Initialize the BIQUAD Instances */
+ arm_biquad_cascade_df2T_init_f64(
+ &biquad_inst_fut, numStages,
+ (float64_t*)filtering_coeffs_b_f64,
+ (void *) filtering_pState);
+
+ JTEST_COUNT_CYCLES(
+ arm_biquad_cascade_df2T_f64(
+ &biquad_inst_fut,
+ (void *) filtering_f64_inputs,
+ (void *) filtering_output_fut,
+ blockSize));
+
+ arm_biquad_cascade_df2T_init_f64(
+ &biquad_inst_ref, numStages,
+ (float64_t*)filtering_coeffs_b_f64,
+ (void *) filtering_pState);
+
+ ref_biquad_cascade_df2T_f64(
+ &biquad_inst_ref,
+ (void *) filtering_f64_inputs,
+ (void *) filtering_output_ref,
+ blockSize);
+
+ FILTERING_DBL_SNR_COMPARE_INTERFACE(
+ blockSize,
+ float64_t)));
+
+ return JTEST_TEST_PASSED;
+}
+
+
+BIQUAD_DEFINE_TEST(f32,arm_biquad_casd_df1_inst_f32, df1,float32_t);
+BIQUAD_DEFINE_TEST(f32,arm_biquad_cascade_df2T_instance_f32,df2T,float32_t);
+BIQUAD_DEFINE_TEST(f32,arm_biquad_cascade_stereo_df2T_instance_f32,stereo_df2T,float32_t);
+BIQUAD_WITH_POSTSHIFT_DEFINE_TEST(q31,df1,,q31_t);
+BIQUAD_WITH_POSTSHIFT_DEFINE_TEST(q15,df1,,q15_t);
+BIQUAD_WITH_POSTSHIFT_DEFINE_TEST(q31,df1,_fast,q31_t);
+BIQUAD_WITH_POSTSHIFT_DEFINE_TEST(q15,df1,_fast,q15_t);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(biquad_tests)
+{
+ /*
+ To skip a test, comment it out.
+ */
+ JTEST_TEST_CALL(arm_biquad_cascade_df1_f32_test);
+ JTEST_TEST_CALL(arm_biquad_cascade_df2T_f32_test);
+ JTEST_TEST_CALL(arm_biquad_cascade_stereo_df2T_f32_test);
+ JTEST_TEST_CALL(arm_biquad_cascade_df2T_f64_test);
+ JTEST_TEST_CALL(arm_biquad_cascade_df1_q31_test);
+ JTEST_TEST_CALL(arm_biquad_cascade_df1_q15_test);
+ JTEST_TEST_CALL(arm_biquad_cascade_df1_fast_q31_test);
+ JTEST_TEST_CALL(arm_biquad_cascade_df1_fast_q15_test);
+ JTEST_TEST_CALL(arm_biquad_cas_df1_32x64_q31_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/conv_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/conv_tests.c
new file mode 100644
index 0000000..c2fdf0f
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/conv_tests.c
@@ -0,0 +1,473 @@
+#include "jtest.h"
+#include "filtering_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "filtering_templates.h"
+#include "type_abbrev.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Header Stuff */
+/*--------------------------------------------------------------------------------*/
+
+#define CONV_MAX_INPUT_ELTS 32
+#define CONV_MAX_OUTPUT_ELTS (CONV_MAX_INPUT_ELTS * 2)
+
+#define CONV_TEST_VALID_PARTIAL_PARAMS(input_a_len, input_b_len, \
+ first_index, num_points) \
+ (((((input_a_len) + (input_b_len) - 1)) >= num_points + first_index ) \
+ && (num_points > 0))
+
+/*--------------------------------------------------------------------------------*/
+/* Input Interfaces */
+/*--------------------------------------------------------------------------------*/
+/*
+ * General:
+ * Input interfaces provide inputs to functions inside test templates. They
+ * ONLY provide the inputs. The output variables should be hard coded.
+ *
+ * The input interfaces must have the following format:
+ *
+ * ARM_xxx_INPUT_INTERFACE() or
+ * REF_xxx_INPUT_INTERFACE()
+ *
+ * The xxx must be lowercase, and is intended to be the indentifying substring
+ * in the function's name. Acceptable values are 'sub' or 'add' from the
+ * functions arm_add_q31.
+ */
+
+#define CONV_arm_conv_INPUT_INTERFACE(input_a, input_a_len, input_b, input_b_len) \
+ PAREN(input_a, input_a_len, input_b, input_b_len, (void*)filtering_output_fut)
+
+#define CONV_ref_conv_INPUT_INTERFACE(input_a, input_a_len, input_b, input_b_len) \
+ PAREN(input_a, input_a_len, input_b, input_b_len, (void*)filtering_output_ref)
+
+#define CONV_arm_conv_opt_INPUT_INTERFACE( \
+ input_a, input_a_len, \
+ input_b, input_b_len) \
+ PAREN(input_a, input_a_len, input_b, input_b_len, \
+ (void*) filtering_output_fut, \
+ (void*) filtering_scratch, \
+ (void*) filtering_scratch2)
+
+#define CONV_ref_conv_opt_INPUT_INTERFACE( \
+ input_a, input_a_len, \
+ input_b, input_b_len) \
+ PAREN(input_a, input_a_len, input_b, input_b_len, \
+ (void*) filtering_output_ref, \
+ (void*) filtering_scratch, \
+ (void*) filtering_scratch2)
+
+#define CONV_arm_conv_fast_INPUT_INTERFACE(input_a, input_a_len, \
+ input_b, input_b_len) \
+ PAREN(input_a, input_a_len, input_b, input_b_len, (void*)filtering_output_fut)
+
+#define CONV_ref_conv_fast_INPUT_INTERFACE(input_a, input_a_len, \
+ input_b, input_b_len) \
+ PAREN(input_a, input_a_len, input_b, input_b_len, (void*)filtering_output_ref)
+
+#define CONV_arm_conv_fast_opt_INPUT_INTERFACE( \
+ input_a, input_a_len, \
+ input_b, input_b_len) \
+ PAREN(input_a, input_a_len, input_b, input_b_len, \
+ (void*) filtering_output_fut, \
+ (void*) filtering_scratch, \
+ (void*) filtering_scratch2)
+
+#define CONV_ref_conv_fast_opt_INPUT_INTERFACE( \
+ input_a, input_a_len, \
+ input_b, input_b_len) \
+ PAREN(input_a, input_a_len, input_b, input_b_len, \
+ (void*) filtering_output_ref, \
+ (void*) filtering_scratch, \
+ (void*) filtering_scratch2)
+
+#define CONV_arm_conv_partial_INPUT_INTERFACE(input_a, input_a_len, \
+ input_b, input_b_len, \
+ first_index, num_points) \
+ PAREN(input_a, input_a_len, input_b, input_b_len, \
+ (void*)filtering_output_fut, first_index, num_points)
+
+#define CONV_ref_conv_partial_INPUT_INTERFACE(input_a, input_a_len, \
+ input_b, input_b_len, \
+ first_index, num_points) \
+ PAREN(input_a, input_a_len, input_b, input_b_len, \
+ (void*)filtering_output_ref, first_index, num_points)
+
+#define CONV_arm_conv_partial_fast_INPUT_INTERFACE(input_a, input_a_len, \
+ input_b, input_b_len, \
+ first_index, num_points) \
+ PAREN(input_a, input_a_len, input_b, input_b_len, \
+ (void*)filtering_output_fut, first_index, num_points)
+
+#define CONV_ref_conv_partial_fast_INPUT_INTERFACE(input_a, input_a_len, \
+ input_b, input_b_len, \
+ first_index, num_points) \
+ PAREN(input_a, input_a_len, input_b, input_b_len, \
+ (void*)filtering_output_ref, first_index, num_points)
+
+#define CONV_arm_conv_partial_opt_INPUT_INTERFACE(input_a, input_a_len, \
+ input_b, input_b_len, \
+ first_index, num_points) \
+ PAREN(input_a, input_a_len, input_b, input_b_len, \
+ (void*)filtering_output_fut, first_index, num_points, \
+ (void*) filtering_scratch, \
+ (void*) filtering_scratch2)
+
+#define CONV_ref_conv_partial_opt_INPUT_INTERFACE(input_a, input_a_len, \
+ input_b, input_b_len, \
+ first_index, num_points) \
+ PAREN(input_a, input_a_len, input_b, input_b_len, \
+ (void*)filtering_output_ref, first_index, num_points, \
+ (void*) filtering_scratch, \
+ (void*) filtering_scratch2)
+
+#define CONV_arm_conv_partial_fast_opt_INPUT_INTERFACE(input_a, input_a_len, \
+ input_b, input_b_len, \
+ first_index, num_points) \
+ PAREN(input_a, input_a_len, input_b, input_b_len, \
+ (void*)filtering_output_fut, first_index, num_points, \
+ (void*) filtering_scratch, \
+ (void*) filtering_scratch2)
+
+#define CONV_ref_conv_partial_fast_opt_INPUT_INTERFACE(input_a, input_a_len, \
+ input_b, input_b_len, \
+ first_index, num_points) \
+ PAREN(input_a, input_a_len, input_b, input_b_len, \
+ (void*)filtering_output_ref, first_index, num_points, \
+ (void*) filtering_scratch, \
+ (void*) filtering_scratch2)
+
+/*--------------------------------------------------------------------------------*/
+/* Convolution Inputs */
+/*--------------------------------------------------------------------------------*/
+
+/* The following symbols alias the filtering_q31_inputs array:
+ *
+ * - filtering_q15_inputs
+ * - filtering_q7_inputs
+ *
+ * The aliasing conflicts with the instantiation of #ARR_DESC_t structs.
+ *
+ * These macro-level aliases allow the #CONV_DEFINE_RAND_INPUT_ARR_DESCS() macro
+ * to correctly select the filtering_q31_input or filtering_f32_input array,
+ * within a template, by type_suffix.
+ *
+ */
+#define CONV_f32_INPUTS filtering_f32_inputs
+#define CONV_q31_INPUTS filtering_q31_inputs
+#define CONV_q15_INPUTS filtering_q31_inputs
+#define CONV_q7_INPUTS filtering_q31_inputs
+
+/**
+ * Defines #ARR_DESC_t objects that wrap existing, type-specific, common
+ * inputs.
+ */
+#define CONV_DEFINE_RAND_INPUT_ARR_DESCS(type_suffix) \
+ ARR_DESC_DEFINE_USING_ARR( \
+ TYPE_FROM_ABBREV(type_suffix), \
+ conv_input_rand1_##type_suffix, \
+ CONV_##type_suffix##_INPUTS, \
+ 0, \
+ CONV_MAX_INPUT_ELTS); \
+ \
+ ARR_DESC_DEFINE_USING_ARR( \
+ TYPE_FROM_ABBREV(type_suffix), \
+ conv_input_rand2_##type_suffix, \
+ CONV_##type_suffix##_INPUTS, \
+ 1, \
+ CONV_MAX_INPUT_ELTS) /* Note the lacking semicolon */
+
+CONV_DEFINE_RAND_INPUT_ARR_DESCS(f32);
+CONV_DEFINE_RAND_INPUT_ARR_DESCS(q31);
+CONV_DEFINE_RAND_INPUT_ARR_DESCS(q15);
+CONV_DEFINE_RAND_INPUT_ARR_DESCS(q7);
+ARR_DESC_DEFINE(float32_t, conv_input_zeros, CONV_MAX_INPUT_ELTS, CURLY(0));
+
+/**
+ * Define Input #ARR_DESC_t arrays by type suffix.
+ *
+ * Taking inputs in parallel from the 'a' and 'b' arrays yields the following
+ * test cases (star is convolution):
+ *
+ * - zero_array * zero_array
+ * - zero_array * random_array
+ * - random_array * zero_array
+ * - random_array * different_random_arary
+ */
+#define CONV_DEFINE_ALL_INPUTS(type_suffix) \
+ ARR_DESC_DEFINE(ARR_DESC_t *, \
+ conv_##type_suffix##_a_inputs, \
+ 4, \
+ CURLY( \
+ &conv_input_zeros, \
+ &conv_input_zeros, \
+ &conv_input_rand1_##type_suffix, \
+ &conv_input_rand1_##type_suffix \
+ )); \
+ ARR_DESC_DEFINE(ARR_DESC_t *, \
+ conv_##type_suffix##_b_inputs, \
+ 4, \
+ CURLY( \
+ &conv_input_zeros, \
+ &conv_input_rand1_##type_suffix, \
+ &conv_input_zeros, \
+ &conv_input_rand2_##type_suffix \
+ )) /* Note the lacking semicolon */
+
+CONV_DEFINE_ALL_INPUTS(f32);
+CONV_DEFINE_ALL_INPUTS(q31);
+CONV_DEFINE_ALL_INPUTS(q15);
+CONV_DEFINE_ALL_INPUTS(q7);
+
+/*--------------------------------------------------------------------------------*/
+/* Convolution Lengths */
+/*--------------------------------------------------------------------------------*/
+
+/*
+ * The conv_lens_a and conv_lens_b #ARR_DESC_t objects are accessed in parallel
+ * to provide convolution-length pairs. Taken in parallel they provide the
+ * following cases:
+ *
+ * - 1 * 1 : Shortest convolution possible.
+ * - 1 * 2 : Short convolution , one side is degenerate .
+ * - 17 * 1 : Medium convolution , one side is degenerate .
+ * - 15 * MAX : Longest convolution , one side is degenerate .
+ * MAX * MAX : Longest convolution.
+ */
+ARR_DESC_DEFINE(uint32_t,
+ conv_lens_a,
+ 5,
+ CURLY(
+ 1,
+ 1,
+ 17,
+ 15,
+ CONV_MAX_INPUT_ELTS
+ ));
+
+ARR_DESC_DEFINE(uint32_t,
+ conv_lens_b,
+ 5,
+ CURLY(
+ 1,
+ 2,
+ 1,
+ CONV_MAX_INPUT_ELTS,
+ CONV_MAX_INPUT_ELTS
+ ));
+
+/*--------------------------------------------------------------------------------*/
+/* Partial Indexing */
+/*--------------------------------------------------------------------------------*/
+
+ARR_DESC_DEFINE(uint32_t,
+ first_index_arr_desc,
+ 4,
+ CURLY(
+ 0,
+ 1,
+ CONV_MAX_INPUT_ELTS / 2,
+ CONV_MAX_INPUT_ELTS
+ ));
+
+ARR_DESC_DEFINE(uint32_t,
+ num_points_arr_desc,
+ 3,
+ CURLY(
+ 1,
+ CONV_MAX_OUTPUT_ELTS / 2,
+ CONV_MAX_OUTPUT_ELTS
+ ));
+
+/*--------------------------------------------------------------------------------*/
+/* Convolution Tests */
+/*--------------------------------------------------------------------------------*/
+
+#define CONV_TEST_TEMPLATE(fut, fut_arg_interface, \
+ ref, ref_arg_interface, \
+ suffix, output_type) \
+ JTEST_DEFINE_TEST(fut##_tests, fut) \
+ { \
+ TEMPLATE_DO_ARR_DESC( \
+ input_idx, ARR_DESC_t *, input_ptr, conv_##suffix##_a_inputs \
+ , \
+ void * input_a_ptr = input_ptr->data_ptr; \
+ void * input_b_ptr = ARR_DESC_ELT( \
+ ARR_DESC_t *, input_idx, \
+ &(conv_##suffix##_b_inputs))->data_ptr; \
+ \
+ TEMPLATE_DO_ARR_DESC( \
+ conv_len_idx, uint32_t, conv_len_a, conv_lens_a \
+ , \
+ uint32_t conv_len_b = ARR_DESC_ELT( \
+ uint32_t, conv_len_idx, &(conv_lens_b)); \
+ \
+ JTEST_DUMP_STRF("Input A Length: %d\n" \
+ "Input B Length: %d\n", \
+ (int)conv_len_a, \
+ (int)conv_len_b); \
+ \
+ TEST_CALL_FUT_AND_REF( \
+ fut, fut_arg_interface( \
+ input_a_ptr, conv_len_a, input_b_ptr, conv_len_b), \
+ ref, ref_arg_interface( \
+ input_a_ptr, conv_len_a, input_b_ptr, conv_len_b)); \
+ \
+ FILTERING_SNR_COMPARE_INTERFACE( \
+ conv_len_a + conv_len_b - 1, \
+ output_type))); \
+ \
+ return JTEST_TEST_PASSED; \
+ } \
+ \
+
+#define CONV_PARTIAL_TEST_TEMPLATE(fut, fut_arg_interface, \
+ ref, ref_arg_interface, \
+ suffix, output_type) \
+ JTEST_DEFINE_TEST(fut##_tests, fut) \
+ { \
+ TEMPLATE_DO_ARR_DESC( \
+ input_idx, ARR_DESC_t *, input_ptr, conv_##suffix##_a_inputs \
+ , \
+ void * input_a_ptr = input_ptr->data_ptr; \
+ void * input_b_ptr = ARR_DESC_ELT( \
+ ARR_DESC_t *, input_idx, \
+ &(conv_##suffix##_b_inputs))->data_ptr; \
+ TEMPLATE_DO_ARR_DESC( \
+ conv_len_idx, uint32_t, conv_len_a, conv_lens_a \
+ , \
+ uint32_t conv_len_b = ARR_DESC_ELT( \
+ uint32_t, conv_len_idx, &(conv_lens_b)); \
+ \
+ TEMPLATE_DO_ARR_DESC( \
+ first_index_idx, uint32_t, first_index, \
+ first_index_arr_desc \
+ , \
+ TEMPLATE_DO_ARR_DESC( \
+ num_points_idx, uint32_t, num_points, \
+ num_points_arr_desc \
+ , \
+ if (CONV_TEST_VALID_PARTIAL_PARAMS( \
+ conv_len_a, conv_len_b, \
+ first_index, num_points)) \
+ { \
+ /* Display test parameter values */ \
+ JTEST_DUMP_STRF("Input A Length: %d\n" \
+ "Input B Length: %d\n" \
+ "First Sample Index: %d\n" \
+ "Number of Output Points: %d\n", \
+ (int)conv_len_a, \
+ (int)conv_len_b, \
+ (int)first_index, \
+ (int)num_points); \
+ \
+ memset(filtering_output_ref,0, \
+ (2*CONV_MAX_INPUT_ELTS)*sizeof(output_type)); \
+ memset(filtering_output_fut,0, \
+ (2*CONV_MAX_INPUT_ELTS)*sizeof(output_type)); \
+ \
+ TEST_CALL_FUT_AND_REF( \
+ fut, fut_arg_interface( \
+ input_a_ptr, conv_len_a, \
+ input_b_ptr, conv_len_b, \
+ first_index, num_points), \
+ ref, ref_arg_interface( \
+ input_a_ptr, conv_len_a, \
+ input_b_ptr, conv_len_b, \
+ first_index, num_points)); \
+ \
+ FILTERING_SNR_COMPARE_INTERFACE_OFFSET( \
+ first_index, \
+ num_points, \
+ output_type); \
+ } else { \
+ /* FUT should return ARM_MATH_ARGUMENT_ERROR*/ \
+ /* if first_index and num_points don't make */ \
+ /* sense*/ \
+ \
+ arm_status conv_test_retval; \
+ TEST_CALL_FUT( \
+ conv_test_retval = fut, \
+ fut_arg_interface( \
+ input_a_ptr, conv_len_a, \
+ input_b_ptr, conv_len_b, \
+ first_index, num_points)); \
+ \
+ if (conv_test_retval != ARM_MATH_ARGUMENT_ERROR) { \
+ JTEST_DUMP_STR("FUT failed to raise error."); \
+ /* return JTEST_TEST_FAILED; */ \
+ } \
+ })))); \
+ \
+ return JTEST_TEST_PASSED; \
+ }
+
+#define CONV_DEFINE_TEST(fn_name, suffix, output_type, test_template) \
+ test_template( \
+ arm_##fn_name##_##suffix, \
+ CONV_arm_##fn_name##_INPUT_INTERFACE, \
+ ref_##fn_name##_##suffix, \
+ CONV_ref_##fn_name##_INPUT_INTERFACE, \
+ suffix, \
+ output_type \
+ ) /* Note the lacking semicolon*/
+
+/* Tests on functions without partial outputs */
+CONV_DEFINE_TEST(conv , f32, float32_t, CONV_TEST_TEMPLATE);
+CONV_DEFINE_TEST(conv , q31, q31_t , CONV_TEST_TEMPLATE);
+CONV_DEFINE_TEST(conv , q15, q15_t , CONV_TEST_TEMPLATE);
+CONV_DEFINE_TEST(conv , q7 , q7_t , CONV_TEST_TEMPLATE);
+CONV_DEFINE_TEST(conv_opt , q15, q15_t , CONV_TEST_TEMPLATE);
+CONV_DEFINE_TEST(conv_opt , q7 , q7_t , CONV_TEST_TEMPLATE);
+CONV_DEFINE_TEST(conv_fast , q31, q31_t , CONV_TEST_TEMPLATE);
+CONV_DEFINE_TEST(conv_fast , q15, q15_t , CONV_TEST_TEMPLATE);
+CONV_DEFINE_TEST(conv_fast_opt , q15, q15_t , CONV_TEST_TEMPLATE);
+
+/* Tests on functions with partial outputs */
+CONV_DEFINE_TEST(conv_partial , f32, float32_t, CONV_PARTIAL_TEST_TEMPLATE);
+CONV_DEFINE_TEST(conv_partial , q31, q31_t , CONV_PARTIAL_TEST_TEMPLATE);
+CONV_DEFINE_TEST(conv_partial , q15, q15_t , CONV_PARTIAL_TEST_TEMPLATE);
+CONV_DEFINE_TEST(conv_partial , q7 , q7_t , CONV_PARTIAL_TEST_TEMPLATE);
+CONV_DEFINE_TEST(conv_partial_fast , q31, q31_t , CONV_PARTIAL_TEST_TEMPLATE);
+CONV_DEFINE_TEST(conv_partial_fast , q15, q15_t , CONV_PARTIAL_TEST_TEMPLATE);
+CONV_DEFINE_TEST(conv_partial_fast_opt , q15, q15_t , CONV_PARTIAL_TEST_TEMPLATE);
+CONV_DEFINE_TEST(conv_partial_opt , q15, q15_t , CONV_PARTIAL_TEST_TEMPLATE);
+CONV_DEFINE_TEST(conv_partial_opt , q7 , q7_t , CONV_PARTIAL_TEST_TEMPLATE);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(conv_tests)
+{
+ /*
+ To skip a test, comment it out.
+ */
+ JTEST_TEST_CALL(arm_conv_f32_tests);
+ JTEST_TEST_CALL(arm_conv_q31_tests);
+ JTEST_TEST_CALL(arm_conv_q15_tests);
+ JTEST_TEST_CALL(arm_conv_q7_tests);
+
+ JTEST_TEST_CALL(arm_conv_opt_q15_tests);
+ JTEST_TEST_CALL(arm_conv_opt_q7_tests);
+
+ JTEST_TEST_CALL(arm_conv_fast_q31_tests);
+ JTEST_TEST_CALL(arm_conv_fast_q15_tests);
+
+ JTEST_TEST_CALL(arm_conv_fast_opt_q15_tests);
+
+ JTEST_TEST_CALL(arm_conv_partial_f32_tests);
+ JTEST_TEST_CALL(arm_conv_partial_q31_tests);
+ JTEST_TEST_CALL(arm_conv_partial_q15_tests);
+ JTEST_TEST_CALL(arm_conv_partial_q7_tests);
+
+ JTEST_TEST_CALL(arm_conv_partial_fast_q31_tests);
+ JTEST_TEST_CALL(arm_conv_partial_fast_q15_tests);
+
+ JTEST_TEST_CALL(arm_conv_partial_fast_opt_q15_tests);
+
+ JTEST_TEST_CALL(arm_conv_partial_opt_q15_tests);
+ JTEST_TEST_CALL(arm_conv_partial_opt_q7_tests);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/correlate_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/correlate_tests.c
new file mode 100644
index 0000000..689b075
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/correlate_tests.c
@@ -0,0 +1,310 @@
+#include "jtest.h"
+#include "filtering_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "filtering_templates.h"
+#include "type_abbrev.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Header Stuff */
+/*--------------------------------------------------------------------------------*/
+
+#define CORRELATE_MAX_INPUT_ELTS 32
+#define CORRELATE_MAX_OUTPUT_ELTS (CORRELATE_MAX_INPUT_ELTS * 2)
+
+/*--------------------------------------------------------------------------------*/
+/* Input Interfaces */
+/*--------------------------------------------------------------------------------*/
+/*
+ * General:
+ * Input interfaces provide inputs to functions inside test templates. They
+ * ONLY provide the inputs. The output variables should be hard coded.
+ *
+ * The input interfaces must have the following format:
+ *
+ * ARM_xxx_INPUT_INTERFACE() or
+ * REF_xxx_INPUT_INTERFACE()
+ *
+ * The xxx must be lowercase, and is intended to be the indentifying substring
+ * in the function's name. Acceptable values are 'sub' or 'add' from the
+ * functions arm_add_q31.
+ */
+
+#define CORRELATE_arm_correlate_INPUT_INTERFACE(input_a, input_a_len, input_b, input_b_len) \
+ PAREN(input_a, input_a_len, input_b, input_b_len, (void*)filtering_output_fut)
+
+#define CORRELATE_ref_correlate_INPUT_INTERFACE(input_a, input_a_len, input_b, input_b_len) \
+ PAREN(input_a, input_a_len, input_b, input_b_len, (void*)filtering_output_ref)
+
+#define CORRELATE_arm_correlate_opt_INPUT_INTERFACE( \
+ input_a, input_a_len, \
+ input_b, input_b_len) \
+ PAREN(input_a, input_a_len, input_b, input_b_len, \
+ (void*) filtering_output_fut, \
+ (void*) filtering_scratch)
+
+#define CORRELATE_arm_correlate_opt_q7_INPUT_INTERFACE( \
+ input_a, input_a_len, \
+ input_b, input_b_len) \
+ PAREN(input_a, input_a_len, input_b, input_b_len, \
+ (void*) filtering_output_fut, \
+ (void*) filtering_scratch, \
+ (void*) filtering_scratch2)
+
+#define CORRELATE_ref_correlate_opt_INPUT_INTERFACE( \
+ input_a, input_a_len, \
+ input_b, input_b_len) \
+ PAREN(input_a, input_a_len, input_b, input_b_len, \
+ (void*) filtering_output_ref, \
+ (void*) filtering_scratch)
+
+#define CORRELATE_ref_correlate_opt_q7_INPUT_INTERFACE( \
+ input_a, input_a_len, \
+ input_b, input_b_len) \
+ PAREN(input_a, input_a_len, input_b, input_b_len, \
+ (void*) filtering_output_ref, \
+ (void*) filtering_scratch, \
+ (void*) filtering_scratch2)
+
+#define CORRELATE_arm_correlate_fast_INPUT_INTERFACE(input_a, input_a_len, \
+ input_b, input_b_len) \
+ PAREN(input_a, input_a_len, input_b, input_b_len, (void*)filtering_output_fut)
+
+#define CORRELATE_ref_correlate_fast_INPUT_INTERFACE(input_a, input_a_len, \
+ input_b, input_b_len) \
+ PAREN(input_a, input_a_len, input_b, input_b_len, (void*)filtering_output_ref)
+
+#define CORRELATE_arm_correlate_fast_opt_INPUT_INTERFACE( \
+ input_a, input_a_len, \
+ input_b, input_b_len) \
+ PAREN(input_a, input_a_len, input_b, input_b_len, \
+ (void*) filtering_output_fut, \
+ (void*) filtering_scratch)
+
+#define CORRELATE_ref_correlate_fast_opt_INPUT_INTERFACE( \
+ input_a, input_a_len, \
+ input_b, input_b_len) \
+ PAREN(input_a, input_a_len, input_b, input_b_len, \
+ (void*) filtering_output_ref, \
+ (void*) filtering_scratch)
+
+/*--------------------------------------------------------------------------------*/
+/* Convolution Inputs */
+/*--------------------------------------------------------------------------------*/
+
+/* The following symbols alias the filtering_q31_inputs array:
+ *
+ * - filtering_q15_inputs
+ * - filtering_q7_inputs
+ *
+ * The aliasing conflicts with the instantiation of #ARR_DESC_t structs.
+ *
+ * These macro-level aliases allow the #CORRELATE_DEFINE_RAND_INPUT_ARR_DESCS() macro
+ * to correctly select the filtering_q31_input or filtering_f32_input array,
+ * within a template, by type_suffix.
+ *
+ */
+#define CORRELATE_f32_INPUTS filtering_f32_inputs
+#define CORRELATE_q31_INPUTS filtering_q31_inputs
+#define CORRELATE_q15_INPUTS filtering_q31_inputs
+#define CORRELATE_q7_INPUTS filtering_q31_inputs
+
+/**
+ * Defines #ARR_DESC_t objects that wrap existing, type-specific, common
+ * inputs.
+ */
+#define CORRELATE_DEFINE_RAND_INPUT_ARR_DESCS(type_suffix) \
+ ARR_DESC_DEFINE_USING_ARR( \
+ TYPE_FROM_ABBREV(type_suffix), \
+ correlate_input_rand1_##type_suffix, \
+ CORRELATE_##type_suffix##_INPUTS, \
+ 0, \
+ CORRELATE_MAX_INPUT_ELTS); \
+ \
+ ARR_DESC_DEFINE_USING_ARR( \
+ TYPE_FROM_ABBREV(type_suffix), \
+ correlate_input_rand2_##type_suffix, \
+ CORRELATE_##type_suffix##_INPUTS, \
+ 1, \
+ CORRELATE_MAX_INPUT_ELTS) /* Note the lacking semicolon */
+
+CORRELATE_DEFINE_RAND_INPUT_ARR_DESCS(f32);
+CORRELATE_DEFINE_RAND_INPUT_ARR_DESCS(q31);
+CORRELATE_DEFINE_RAND_INPUT_ARR_DESCS(q15);
+CORRELATE_DEFINE_RAND_INPUT_ARR_DESCS(q7);
+ARR_DESC_DEFINE(float32_t, correlate_input_zeros, CORRELATE_MAX_INPUT_ELTS, CURLY(0));
+
+/**
+ * Define Input #ARR_DESC_t arrays by type suffix.
+ *
+ * Taking inputs in parallel from the 'a' and 'b' arrays yields the following
+ * test cases (star is correlate):
+ *
+ * - zero_array * zero_array
+ * - zero_array * random_array
+ * - random_array * zero_array
+ * - random_array * different_random_arary
+ */
+#define CORRELATE_DEFINE_ALL_INPUTS(type_suffix) \
+ ARR_DESC_DEFINE(ARR_DESC_t *, \
+ correlate_##type_suffix##_a_inputs, \
+ 4, \
+ CURLY( \
+ &correlate_input_zeros, \
+ &correlate_input_zeros, \
+ &correlate_input_rand1_##type_suffix, \
+ &correlate_input_rand1_##type_suffix \
+ )); \
+ ARR_DESC_DEFINE(ARR_DESC_t *, \
+ correlate_##type_suffix##_b_inputs, \
+ 4, \
+ CURLY( \
+ &correlate_input_zeros, \
+ &correlate_input_rand1_##type_suffix, \
+ &correlate_input_zeros, \
+ &correlate_input_rand2_##type_suffix \
+ )) /* Note the lacking semicolon */
+
+CORRELATE_DEFINE_ALL_INPUTS(f32);
+CORRELATE_DEFINE_ALL_INPUTS(q31);
+CORRELATE_DEFINE_ALL_INPUTS(q15);
+CORRELATE_DEFINE_ALL_INPUTS(q7);
+
+/*--------------------------------------------------------------------------------*/
+/* Convolution Lengths */
+/*--------------------------------------------------------------------------------*/
+
+/*
+ * The correlate_lens_a and correlate_lens_b #ARR_DESC_t objects are accessed in parallel
+ * to provide correlate-length pairs. Taken in parallel they provide the
+ * following cases:
+ *
+ * - 1 * 1 : Shortest correlate possible.
+ * - 1 * 2 : Short correlate , one side is degenerate.
+ * - 17 * 1 : Medium correlate, one side is degenerate.
+ * - 15 * MAX : Longest correlate.
+ * MAX * MAX : Longest correlate.
+ */
+ARR_DESC_DEFINE(uint32_t,
+ correlate_lens_a,
+ 5,
+ CURLY(
+ 1,
+ 1,
+ 17,
+ 15,
+ CORRELATE_MAX_INPUT_ELTS
+ ));
+
+ARR_DESC_DEFINE(uint32_t,
+ correlate_lens_b,
+ 5,
+ CURLY(
+ 1,
+ 2,
+ 1,
+ CORRELATE_MAX_INPUT_ELTS,
+ CORRELATE_MAX_INPUT_ELTS
+ ));
+
+/*--------------------------------------------------------------------------------*/
+/* Convolution Tests */
+/*--------------------------------------------------------------------------------*/
+
+#define CORRELATE_TEST_TEMPLATE(fut, fut_arg_interface, \
+ ref, ref_arg_interface, \
+ suffix, output_type) \
+ JTEST_DEFINE_TEST(fut##_tests, fut) \
+ { \
+ TEMPLATE_DO_ARR_DESC( \
+ input_idx, ARR_DESC_t *, input_ptr, correlate_##suffix##_a_inputs \
+ , \
+ void * input_a_ptr = input_ptr->data_ptr; \
+ void * input_b_ptr = ARR_DESC_ELT( \
+ ARR_DESC_t *, input_idx, \
+ &(correlate_##suffix##_b_inputs))->data_ptr; \
+ \
+ TEMPLATE_DO_ARR_DESC( \
+ correlate_len_idx, uint32_t, correlate_len_a, correlate_lens_a \
+ , \
+ uint32_t correlate_len_b = ARR_DESC_ELT( \
+ uint32_t, correlate_len_idx, &(correlate_lens_b)); \
+ \
+ /* Display test parameter values */ \
+ JTEST_DUMP_STRF("Input A Length: %d\n" \
+ "Input B Length: %d\n", \
+ (int)correlate_len_a, \
+ (int)correlate_len_b); \
+ \
+ memset(filtering_output_ref,0, \
+ (2*CORRELATE_MAX_INPUT_ELTS)*sizeof(output_type)); \
+ memset(filtering_output_fut,0, \
+ (2*CORRELATE_MAX_INPUT_ELTS)*sizeof(output_type)); \
+ \
+ TEST_CALL_FUT_AND_REF( \
+ fut, fut_arg_interface( \
+ input_a_ptr, correlate_len_a, input_b_ptr, correlate_len_b), \
+ ref, ref_arg_interface( \
+ input_a_ptr, correlate_len_a, input_b_ptr, correlate_len_b)); \
+ \
+ FILTERING_SNR_COMPARE_INTERFACE( \
+ correlate_len_a + correlate_len_b - 2, \
+ output_type))); \
+ \
+ return JTEST_TEST_PASSED; \
+ }
+
+#define CORRELATE_DEFINE_TEST(fn_name, suffix, output_type, test_template) \
+ test_template( \
+ arm_##fn_name##_##suffix, \
+ CORRELATE_arm_##fn_name##_INPUT_INTERFACE, \
+ ref_##fn_name##_##suffix, \
+ CORRELATE_ref_##fn_name##_INPUT_INTERFACE, \
+ suffix, \
+ output_type \
+ ) /* Note the lacking semicolon*/
+
+/* Tests on functions without partial outputs */
+CORRELATE_DEFINE_TEST(correlate , f32, float32_t, CORRELATE_TEST_TEMPLATE);
+CORRELATE_DEFINE_TEST(correlate , q31, q31_t , CORRELATE_TEST_TEMPLATE);
+CORRELATE_DEFINE_TEST(correlate , q15, q15_t , CORRELATE_TEST_TEMPLATE);
+CORRELATE_DEFINE_TEST(correlate , q7 , q7_t , CORRELATE_TEST_TEMPLATE);
+CORRELATE_DEFINE_TEST(correlate_opt , q15, q15_t , CORRELATE_TEST_TEMPLATE);
+
+CORRELATE_TEST_TEMPLATE(
+ arm_correlate_opt_q7,
+ CORRELATE_arm_correlate_opt_q7_INPUT_INTERFACE,
+ ref_correlate_opt_q7,
+ CORRELATE_ref_correlate_opt_q7_INPUT_INTERFACE,
+ q7,
+ q7_t
+ );
+
+CORRELATE_DEFINE_TEST(correlate_fast , q31, q31_t , CORRELATE_TEST_TEMPLATE);
+CORRELATE_DEFINE_TEST(correlate_fast , q15, q15_t , CORRELATE_TEST_TEMPLATE);
+CORRELATE_DEFINE_TEST(correlate_fast_opt , q15, q15_t , CORRELATE_TEST_TEMPLATE);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(correlate_tests)
+{
+ /*
+ To skip a test, comment it out.
+ */
+ JTEST_TEST_CALL(arm_correlate_f32_tests);
+ JTEST_TEST_CALL(arm_correlate_q31_tests);
+ JTEST_TEST_CALL(arm_correlate_q15_tests);
+ JTEST_TEST_CALL(arm_correlate_q7_tests);
+
+ JTEST_TEST_CALL(arm_correlate_opt_q15_tests);
+ JTEST_TEST_CALL(arm_correlate_opt_q7_tests);
+
+ JTEST_TEST_CALL(arm_correlate_fast_q31_tests);
+ JTEST_TEST_CALL(arm_correlate_fast_q15_tests);
+
+ JTEST_TEST_CALL(arm_correlate_fast_opt_q15_tests);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_common_data.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_common_data.c
new file mode 100644
index 0000000..3bd1afb
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_common_data.c
@@ -0,0 +1,757 @@
+#include "filtering_test_data.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Input/Output Buffers */
+/*--------------------------------------------------------------------------------*/
+
+//must be max(LMS_MAX_BLOCKSIZE*2, FILTERING_MAX_BLOCKSIZE * FILTERING_MAX_L)
+float32_t filtering_output_fut[LMS_MAX_BLOCKSIZE*2] = {0};
+float32_t filtering_output_ref[LMS_MAX_BLOCKSIZE*2] = {0};
+float32_t filtering_output_f32_fut[LMS_MAX_BLOCKSIZE*2] = {0};
+float32_t filtering_output_f32_ref[LMS_MAX_BLOCKSIZE*2] = {0};
+float32_t filtering_input_lms[LMS_MAX_BLOCKSIZE*2] = {0};
+float32_t filtering_pState[LMS_MAX_BLOCKSIZE + FILTERING_MAX_NUMTAPS] = {0};
+float32_t filtering_scratch[FILTERING_MAX_BLOCKSIZE * 3] = {0};
+float32_t filtering_scratch2[FILTERING_MAX_BLOCKSIZE * 3] = {0};
+float32_t filtering_coeffs_lms[FILTERING_MAX_NUMTAPS];
+
+const q31_t filtering_q31_inputs[FILTERING_MAX_BLOCKSIZE * FILTERING_MAX_M + FILTERING_MAX_NUMTAPS] =
+{
+ 0xC14A5524, 0xCCABDA17, 0xAD6F5B56, 0xFDAFCE3B, 0xA9B226EB,
+ 0x41F6F6A, 0xA5CE38BF, 0x3A978AFA, 0xBA44B82A, 0x855C0F8,
+ 0x3D060524, 0x93D5E570, 0x97D7791D, 0xFFE0C38C, 0x26749841,
+ 0xC0A6EE54, 0x218EC386, 0x39FF3726, 0x8DC1F7CA, 0x702F2CF5,
+ 0xC1142FF1, 0xEC1476AB, 0x15F640DD, 0xE62CCE49, 0x3805DE7E,
+ 0xF70871FE, 0xCF8BD360, 0x8D19A8A0, 0xD764F821, 0xA58558CF,
+ 0x8C0CE04D, 0x50A46C19, 0x66D2370D, 0x50FA359A, 0xB646AE24,
+ 0x6CE00F5C, 0xE6D48948, 0xB55BD831, 0x3B72950A, 0x9EB69530,
+ 0x73394127, 0x773FA6F4, 0x9805A980, 0x838DE587, 0x9CF597F4,
+ 0xA2AD1691, 0xFA81A473, 0x7CDC7D7F, 0x4A5190D0, 0xED895BB9,
+ 0x8FD60F35, 0x1A21D530, 0xA0EB6DDA, 0xBDE6A516, 0x2501A3E1,
+ 0x5ED893C8, 0xE1E175B1, 0xACBBB2F3, 0xED350907, 0xDB140D7E,
+ 0xEEAE272D, 0xBE229841, 0xC18BFB88, 0xA6BB9B80, 0xBCF090E4,
+ 0x24DB166C, 0xF9AB7E42, 0x62DF28D1, 0xC7004665, 0xE3F56FC6,
+ 0x419E0C75, 0x46BE9F38, 0x2432B9B2, 0x758D83E0, 0xDCE12926,
+ 0x3F57CB74, 0x1F4458E2, 0xF1DD639, 0x83A1FB49, 0x173AFC76,
+ 0x86EF7531, 0x48D32F34, 0x7D3E3063, 0x8F2FB549, 0x5C314C9,
+ 0x18CBEB6D, 0xA6F8B697, 0x447B9E9C, 0x2E32BA33, 0xD074D715,
+ 0x81ACD746, 0xE55A4E04, 0x4891860F, 0x1DA3EB4F, 0xE0E6A27F,
+ 0x20BFDEB4, 0xD0B3A25B, 0x40C10544, 0xC15656C, 0x15405EAE,
+ 0x9858E3E1, 0xA36A9C4E, 0x88BD21F9, 0xAACF7A68, 0x773665E5,
+ 0xCEDFDF66, 0x617A9610, 0x524FC968, 0xC2D086CD, 0x5F008079,
+ 0x24DCA447, 0x6A4F5599, 0xB706CD4A, 0x1DE70608, 0xA33A2EE5,
+ 0x137E488E, 0x98061B7B, 0x4079D69D, 0xA4A897D5, 0xC4CEC8F5,
+ 0xD75F7883, 0x22406802, 0xF1AD70BB, 0x9D4ADD79, 0xBCBC7CE4,
+ 0xB358C0D8, 0x85792E47, 0xA7ADAC05, 0x3D19EEAB, 0x331AC0AF,
+ 0x33035831, 0x13D93987, 0xFC542094, 0x845F317E, 0xDDC4BF8B,
+ 0x1379E50C, 0x5C20193F, 0xFDD58298, 0x9D482B82, 0x4A6BE062,
+ 0xDC8A757B, 0x272917C1, 0x90E1EFBC, 0x355AD882, 0xE6F8EA35,
+ 0x604555A1, 0x7DFFFBB, 0xF58AE216, 0x9A11B463, 0xD3541BAD,
+ 0xA1576756, 0x483BED8D, 0x1F05AFCC, 0xCEA63DFB, 0x55B84677,
+ 0xFB2E04F2, 0x787AF96C, 0x84A12CD3, 0x460A9BD, 0x9DB22DD8,
+ 0x1A8C7F28, 0x861E452E, 0x932D3F78, 0x7652D852, 0x73357BBA,
+ 0xEBBB0A58, 0x62536AFA, 0x3F6B65EF, 0x6DC57B58, 0x9EB798CE,
+ 0xE6B0A740, 0xDFF68B47, 0x3247FB8F, 0xFFF3D302, 0xA9FD3E40,
+ 0x475A43D1, 0x6FF9528A, 0x2018A09D, 0x47E0F9C9, 0x4CF5F6D3,
+ 0x2807CE34, 0xDD6FD8ED, 0x234045D1, 0x51CEB5F9, 0x25297896,
+ 0x6443A0FE, 0x8F4449A9, 0xD4C3E1C6, 0xF01D52F1, 0x4E09C820,
+ 0xF18F0810, 0xE1548689, 0xF9DE5A1F, 0x5286DC23, 0x48AC3A4B,
+ 0xEA0C1BE0, 0xA1B785DB, 0x7086465D, 0x1CC10929, 0x1E1D716E,
+ 0xED231D4C, 0x2049D108, 0xB8FF9971, 0x949CF8D4, 0x441F1E8B,
+ 0xC3D95372, 0x69C324B4, 0xA10BFDC9, 0xC781DE78, 0x82476137,
+ 0xE163DDF, 0x390DEEC2, 0xAF68CE5B, 0x8E680ABD, 0x8223A615,
+ 0x92593380, 0x7B1465FE, 0x865AE957, 0x930F53EB, 0xED772EF7,
+ 0x10E916B6, 0xE3BCFA68, 0x2ACB80BB, 0xE51C5590, 0x994714B5,
+ 0xF30984EE, 0x59BBE1B4, 0xB4867DBC, 0xB91C706C, 0xBC16C218,
+ 0xA8931CD0, 0x129A66AB, 0x13171F4D, 0x62882872, 0x4B167FD4,
+ 0xE6902F4C, 0xFA794932, 0xD4B152C, 0xB0856EA9, 0x39466D55,
+ 0x3669E451, 0x8F5B9E8C, 0x877A3C6A, 0x51B956B4, 0x367EAD2A,
+ 0x9D2C662A, 0x78FB6880, 0x4E6D40B6, 0x4070EFDC, 0x4DF9679C,
+ 0x20306EDB, 0xE381AAE7, 0xA55DA748, 0x9B8B617B, 0x3E036FAD,
+ 0x84E4C4A7, 0xD5A3F517, 0x669BA988, 0x98FDDE8C, 0x67BD85CE,
+ 0x34BBB46C, 0x76994800, 0x85B9D8B6, 0x6DFA2FEF, 0x205DB5C,
+ 0x9F843C4C, 0x72721B52, 0x73EF6B86, 0x5FB98B61, 0xC323DDAC,
+ 0x31D424B4, 0xF68C0D7E, 0x162FAF9D, 0x7B2A7A99, 0xF9392693,
+ 0xC42D12C0, 0x8692A73E, 0xD9A1EE80, 0xDD956856, 0x44E7BDAC,
+ 0x8D874532, 0x5F5C9DD0, 0x5D167858, 0x8559FEA2, 0x9D821476,
+ 0xD9654ED2, 0x594C0DC7, 0x1A87B506, 0x3F693200, 0x7A651AB5,
+ 0xA0CCBC8A, 0x9F9E662C, 0x78EF631, 0x2A09DA0, 0xB088C72F,
+ 0x92EE0D42, 0x360DCD5F, 0xF333FE48, 0x8D63CC06, 0x233A8ACB,
+ 0x706651ED, 0x7AA5C079, 0x262239D1, 0x3EBBEBB6, 0xA25A4F3D,
+ 0x32581A06, 0x6E6FD780, 0x5773F7C7, 0x75ED1DDC, 0x90DF2D15,
+ 0xBC79A9BC, 0xB7175917, 0x354E381C, 0x762AADD7, 0xF643DAC1,
+ 0xF3BBF49E, 0xD2FECE7E, 0x6C8140F4, 0xD7694875, 0x92D30822,
+ 0xC742A7CF, 0xB792ED98, 0x121CFE24, 0xA04E1EE7, 0x58CE268,
+ 0x215A080, 0x316CB323, 0xFAB14A31, 0xE1C13C03, 0xFD8EF4F1,
+ 0xF3F446D0, 0x6C6CEA0A, 0xBBFDF9FB, 0x67242969, 0xBE55A4EB,
+ 0x8FF5534, 0x52F0DF1C, 0x9710ADE3, 0xD40F4A21, 0x7984E8E7,
+ 0x419545EB, 0x993F7880, 0xAB246B20, 0x408AABC4, 0xCBF6EA49,
+ 0xC0894C55, 0x4CAA6398, 0xA47856E9, 0xAF2AE47D, 0x22F55D33,
+ 0xF0D37915, 0xD0634C72, 0xD983671, 0x2BCC5AF8, 0x9A77D48,
+ 0xC11B5CFA, 0xF107CD7E, 0x3A6B3593, 0xE1425F05, 0x6271812A,
+ 0x5B838310, 0xBD8418CA, 0x10A58792, 0x239F7137, 0xA13D5071,
+ 0x7F9930D4, 0xA462664F, 0x54180F8E, 0x291585BA, 0xE586B87A,
+ 0x144B2C12, 0x98E425C7, 0xBAA4B373, 0x18F0D03C, 0x99462AC0,
+ 0xD8B4D2EF, 0x72473895, 0xA6BF5435, 0xEDAD53B, 0xE0912FA6,
+ 0x5C33F331, 0x3D93CD7, 0x4D03D752, 0x20699929, 0xB89962F9,
+ 0x36E781E9, 0xF58B642C, 0x5FCA69E3, 0x5960A7F4, 0xAD5AAFD0,
+ 0xDF18324A, 0x3DB1E5AA, 0x76BA3876, 0x1BC29AF6, 0xBCC18841,
+ 0x73A60174, 0x625BFF58, 0x67C57724, 0x4458E53C, 0xE157B095,
+ 0x2B370837, 0x83DF6CE3, 0xDD08EEFA, 0x3F52A7C2, 0x191B4785,
+ 0x60843D82, 0xB0DE11F1, 0x105EA26C, 0x6E1C7AA2, 0x47AADD14,
+ 0xB6676D03, 0x3B8D4DF6, 0x737A694, 0x409521DC, 0x744206A,
+ 0xC722023F, 0x2BE4EAD5, 0x63E11D76, 0xCA4A09AB, 0x5CF2D2B9,
+ 0x31586916, 0xCDFD7D84, 0xB203F634, 0xAD7329D4, 0xC524582F,
+ 0x2E53E6C1, 0xBB0E019B, 0xB8538C6A, 0x6A2542D, 0x8A6A00E5,
+ 0x119725CC, 0x5406D347, 0x1B6FFAF1, 0xECCF71F1, 0x981117F2,
+ 0x7167CA76, 0x74F4B880, 0x77A55F47, 0x59EADB62, 0x4A331D95,
+ 0xBCBBA76F, 0xA45C4D50, 0xC718D5, 0x87CE05D1, 0x60D47AD5,
+ 0xA5CA9C40, 0xB0061766, 0xE69B39DF, 0xBD5F1320, 0x9930EAD3,
+ 0xA8B38325, 0x8DD090F, 0x6A6EEF37, 0x2DF16F66, 0xAB514C7E,
+ 0x31109C58, 0xFD48C7FC, 0x515341CA, 0x77AB8EA6, 0x41328DAF,
+ 0xBAF8D31E, 0xA4B31611, 0xED37F331, 0x7A832A22, 0xA22591C7,
+ 0x722D1F89, 0x3B19CF18, 0x261B8A4D, 0xC3F6F6DB, 0xCF8CED61,
+ 0x990FA250, 0xA02E72A9, 0x560DCEA2, 0xB08E67B4, 0x3674E663,
+ 0x97CC3852, 0xA7EB2EAC, 0xFFDE0AA8, 0xA64719A, 0x23269EDD,
+ 0x3C0B339E, 0x86284D40, 0x48D82ECB, 0xA4D4CCF8, 0x43631B91,
+ 0x4BF0C248, 0xB6497B9B, 0x6827BC58, 0xE30B7AF9, 0xA0CCBF26,
+ 0x6C3B7B71, 0xD744B3ED, 0xFA25D2F6, 0x4CDE642D, 0xD65B8142,
+ 0xA6F9207F, 0xE7A207BE, 0xDB506684, 0x44DA4780, 0x9175EA0C,
+ 0x156104AF, 0x4155E1B0, 0x6E3A6886, 0x9DBA1EA2, 0x5423D9C8,
+ 0xCC024E22, 0x758F852A, 0x1DD6395, 0x2D19CBAD, 0xE164F5A1,
+ 0xC2084602, 0x89C274AD, 0x13CB5562, 0xD7FE2D5B, 0xE07A4EE5,
+ 0x1672BA91, 0x4F624CCF, 0x2E5EA4A3, 0x28FEEFAF, 0xBDDA6EF4,
+ 0x32AFD40C, 0x99A5FB3B, 0xDD1D73A3, 0xA342CB3E, 0xA78445F5,
+ 0x53979C3B, 0x427D7943, 0x5221B58C, 0xA6CE9A5E, 0xFB50ECA4,
+ 0xBB86E36E, 0x60839F6D, 0xC5E1C2F3, 0xA1B7FB04, 0xFBB65E0C,
+ 0x78B80F5E, 0xFD8D972B, 0x3BF3BA90, 0x2D572D9, 0x2B5BC920,
+ 0xB6A0DE01, 0xD274D306, 0xC7C6C855, 0x9CAA669B, 0xB04AA641,
+ 0x4D6B1760, 0x3E17ED79, 0xD23241B0, 0xA4A6F957, 0xCBDE76AF,
+ 0x4E5F9493, 0x4C215DA5, 0x33A052B, 0x1A4D80C2, 0x40AEEBCA,
+ 0x390D106B, 0xE9E8E018, 0x5AF3D6CF, 0xE35E1D4, 0xC4FB1C6,
+ 0x14B6299B, 0x8D2E25F0, 0xCCBF932A, 0xC5AC18B6, 0x2227567D,
+ 0x86B5CE2F, 0x26344534, 0x22C515EC, 0x2442B70D, 0xEC3721C6,
+ 0x34EF687D, 0x9C06323A, 0xEAF3EA60, 0x60396F52, 0xEAE78AA1,
+ 0xC9D06CBC, 0x6F95F6C8, 0x584CC258, 0xBA9A27BB, 0x66DF8D47,
+ 0x9D4804EA, 0x57DD9E67, 0xF89C7895, 0xF5336111, 0x25C122C8,
+ 0x62742114, 0xCFBF6D26, 0xBF9F6482, 0xE6F02CD9, 0x11083202,
+ 0xC99E2618, 0x7EBC9351, 0x440112F1, 0xC9DFFBC1, 0x3BF4DC25,
+ 0xB1BA7FA0, 0x61AF9AED, 0x6B1F7D29, 0xAD865294, 0xE3E01129,
+ 0x7E9E77A5, 0x100435D7, 0x9FE3A71, 0x88597C81, 0x722849FA,
+ 0x31C5A0AF, 0xFBA178DC, 0x7F102D31, 0x5CA07864, 0x950E6F98,
+ 0x82C34882, 0x5D041F11, 0x8C613C57, 0xD398CFD1, 0x426F38AD,
+ 0x5599AB1D, 0xFAFA078D, 0xAB25B413, 0xD94B32CF, 0xB288FE38,
+ 0x2893BB46, 0x9A0B4168, 0xA91BCA94, 0x653A5E8D, 0x2174EBBE,
+ 0xDEFE6415, 0x30DA429C, 0xD0C5E40C, 0xB4719AA4, 0xD29CE7A6,
+ 0x905957CD, 0xCD287499, 0x83CA0AA7, 0xA8385832, 0x25A0CA02,
+ 0xC20D47A4, 0xB562F556, 0x4BC19E4C, 0xD9E215C7, 0x27E838B4,
+ 0xC58612F4, 0xA2827F6F, 0xC49DCDBA, 0x679B7362, 0x4E495845,
+ 0xCFD2F0D1, 0x395E76A0, 0x375A655E, 0x92E2058F, 0x73F9F0CA,
+ 0x61EFF3B3, 0x51FFD362, 0xE7410345, 0x7FDA8B3B, 0xA219E2E8,
+ 0x17ABE543, 0x26557412, 0x4B30084D, 0xA68E191D, 0xFE0D93DF,
+ 0x73EF127D, 0x4DECDDB1, 0x77FAF45F, 0xD6002898, 0x92DD0A40,
+ 0x157F6DDF, 0xC2A55F8E, 0x4359F924, 0xFB630C3F, 0x338B6B58,
+ 0xB2945F75, 0x4FA23A0E, 0x836EB8C0, 0xB3B18FD, 0x86114337,
+ 0x24668ACB, 0x99BB82F0, 0x924C8A47, 0xBA959701, 0x81155ABF,
+ 0x8C612D71, 0x36074CA7, 0xD1668C41, 0xE35F58C7, 0x7FC2802D,
+ 0x8E6A7CF3, 0x65B07D07, 0x815F6A6B, 0x791BF0DD, 0x6E47D719,
+ 0xC24394C7, 0xE84A6EB, 0xF194AFEE, 0x464A2F52, 0x677579FD,
+ 0xEBA775AE, 0x1F6EEFF, 0x9A795237, 0x78D9D45F, 0x9D0B344D,
+ 0xBBD34AB7, 0x2F85B12A, 0x16C5C2AD, 0x3990985D, 0x88DF3351,
+ 0x82811AA5, 0x6D351F41, 0x4066A69D, 0x86B660BF, 0x6EDB4768,
+ 0xDDD78CF0, 0xB5D74F6E, 0xE89E220C, 0x91439687, 0x947CC9C9,
+ 0x3857E2BD, 0x302F8AE4, 0x1DABE7F8, 0x4832D6C9, 0x37D58FCB,
+ 0x4EA8A711, 0xCD7BAC98, 0x19DBF8BC, 0xD8DE8DC2, 0xEAFF7E7B,
+ 0xB7629C93, 0x792C6E19, 0xF7009192, 0xFF88439D, 0x2E196A66,
+ 0xEC71B78C, 0xEAF4BB3A, 0x7C16225E, 0x668F337, 0xCBEE1608,
+ 0x6D5B5552, 0x345DC590, 0x681209CC, 0x7B24A819, 0xD08A1416,
+ 0x99888FE3, 0x9FC7288A, 0x24BD8502, 0xEA1D9678, 0x20EECA0,
+ 0x59BEA057, 0x5ADE91EB, 0xDEA8E49D, 0xFA200E6F, 0x9149C81D,
+ 0xF2281E93, 0x8A5B0451, 0x67312D58, 0xE3B849F1, 0xD2217960,
+ 0x7CDF59F3, 0x33C775C0, 0x9EBA8799, 0x7DF9506, 0xB4E96110,
+ 0xB8FCF3E3, 0xDEA059B2, 0x8229B6EA, 0x316486F6, 0x43919185,
+ 0x6C0D90F3, 0x1C6F3DF8, 0x38DB92A9, 0x5CD41244, 0x2C9F0A7B,
+ 0xDF4A315F, 0xF7CE9C66, 0x4C800860, 0x318D53E0, 0xF105C20D,
+ 0xD753E1F2, 0x750810BA, 0xA17ECCA5, 0x2010140, 0x4D884763,
+ 0xC2BB0DA7, 0xB2D5BA74, 0x141CECD4, 0x887FDFC3, 0xC64B53,
+ 0x2D2A85F6, 0x15532B45, 0x5D5CBCE1, 0xBEB9A16A, 0xA214611B,
+ 0x9FC5AC5F, 0x11AE5DD7, 0xA0B9A5A9, 0xFC648AF4, 0x740009AC,
+ 0xED0E0321, 0xB8E6A61, 0x8910C544, 0xC74F26C8, 0x9525CCF3,
+ 0xB41AEB59, 0xE61984CE, 0x598B2197, 0xA412E59D, 0xE1976DD4,
+ 0xB29BBE16, 0x88FD9FB0, 0xB04006F3, 0xB45E309, 0xD5CC15F1,
+ 0xD9DAF630, 0xDC809335, 0x803ED52, 0xB537F5A5, 0xA994F6EB,
+ 0xF5288568, 0xF66FD264, 0x2EA2B3A6, 0x647619F3, 0xFFB38C7A,
+ 0x1BC03B9, 0xB6BC3061, 0xBF30596E, 0xBE2AD27B, 0x8AC04220,
+ 0x641979A3, 0x9ECCBB89, 0xA144FBC1, 0x4E8FAE26, 0x8C5A9D90,
+ 0x299ED467, 0xD7C9C7E3, 0x1D4865ED, 0x76F31C3D, 0xCEE81CDF,
+ 0xB479195E, 0x6FFB3AE1, 0xDC8A398, 0x300F7364, 0xC7940AFA,
+ 0x3B85BE3E, 0xD98CC40D, 0xA24A3D89, 0x3A674204, 0x22888A38,
+ 0x2E77F2D, 0xA2841C9C, 0xCF0689C3, 0x9FE98922, 0x89335017,
+ 0x2D6B69A7, 0xFEDB63F9, 0x899AF4EF, 0x9F9F9B40, 0xA4BE97E8,
+ 0xA51DAF7A, 0x16AC50D3, 0xA8D7ED6, 0xED193443, 0x7615EF1B,
+ 0xB0DF6A4E, 0x64FFE794, 0xE3DB2C9A, 0x7435B022, 0x556E825C,
+ 0x23802AF9, 0xC25098A4, 0xE75A18BB, 0x70B2A7B9, 0x7FB81BF,
+ 0x63EF910, 0x6C669591, 0x6574DD2B, 0xCF6E379D, 0xD2B3AFAC,
+ 0x1E6A1101, 0x1DE22385, 0x2338191F, 0xC69704B6, 0xCBABC599,
+ 0x54EB4809, 0x7839BE6D, 0xD50017DD, 0x39B1A0E1, 0x288D52D3,
+ 0x2D52668C, 0x20D22A68, 0x4E1207D1, 0x3FCC0EFE, 0x47F3FE64,
+ 0x25177A90, 0xB4BFDD4D, 0xDA8DBDCE, 0x6F7275A8, 0x6BEAA655,
+ 0xAA1810FC, 0xE4DB593A, 0x8A4D4BC0, 0x2C402E93, 0xF1C0F7F9,
+ 0x6F0CC577, 0x70412414, 0x752F9DC1, 0xD82E38EA, 0xAC455F7B,
+ 0x4DCD4EDB, 0x92BC2696, 0xFB03F135, 0x4FCA1F8C, 0xBD5E75F6,
+ 0x502F41B0, 0x3616D3F1, 0x2E5B8E31, 0x2026EB19, 0x57E783D7,
+ 0x467BBE00, 0x4703ABA3, 0x1F776B9C, 0xE2570A84, 0xFEC7DB48,
+ 0x1BD5012, 0xFD0A2D5D, 0x7FCC29F2, 0x291304B6, 0x99D5D8ED,
+ 0xC7551C8, 0xFD12F38F, 0xBADE8892, 0xDF749997, 0xA5DAE2F,
+ 0x2B9FA269, 0x5C13CFED, 0x15E9A399, 0x54437F4E, 0xA72DB2AB,
+ 0x56186AA1, 0xFE4DB55C, 0xA34D7836, 0x2A879760, 0xC63FA94,
+ 0xAC18B207, 0x5FC78B3, 0x7F10621E, 0xA769E6B2, 0xEC9F4A11,
+ 0xCE3F982C, 0x62BA2EF5, 0xA5F239CD, 0x73D63FED, 0xE36E9F5E,
+ 0x8AC1DA0E, 0x3F3DB3EB, 0x738326EA, 0x35C366B1, 0xCD476E86,
+ 0x82F6B208, 0xF11A9FC1, 0x426AC396, 0x7E4D1B93, 0x75E4EDB7,
+ 0xAF3C44A7, 0x51A5EF5C, 0xFAD2463D, 0x8A5639CA, 0xC995AC78,
+ 0xCC4BE4F6, 0x3AFE7F8D, 0x66993D04, 0x4386FF37, 0xCBC1C6C2,
+ 0x55A8F5EC, 0xE81A9A75, 0x30A67E1B, 0x4A4A7D0C, 0x20F7F993,
+ 0x1891805, 0x738976AD, 0xD426E7D6, 0x3C5CEEBF, 0x4499187F,
+ 0xABF17C97, 0x447C317F, 0x68D8419C, 0x7AAB6456, 0x421BCF29,
+ 0xF6740F9C, 0x8916BB8D, 0x3D72AAB, 0x9AD54DD7, 0x7549C6EE,
+ 0x7317342B, 0xA18546D4, 0x1056BDA7, 0x54BBCCCE, 0x8CE63E46,
+ 0x5D146234, 0x33BE6C63, 0xB250C4E5, 0x89D72335, 0x87C36BA,
+ 0xB65530CC, 0x2DFAC48C, 0x1663D16F, 0x59B80AA, 0x950274EA,
+ 0x92532D4A, 0x3CEF802D, 0x492FBDA5, 0xA63A2574, 0xEF8005C2,
+ 0x94A18651, 0xAF627ABA, 0x6829B238, 0xA698F646, 0xD2598516,
+ 0x10144D36, 0xD9B1D1B9, 0xAB2ACF05, 0x5395B699, 0xA7851C75,
+ 0x1806C6F3, 0xAE970306, 0x3284B145, 0x98F4FE8F, 0xECDD35CC,
+ 0xDDC1EE0E, 0xC4848865, 0x925826BD, 0x4078BE39, 0x68A8561A,
+ 0x323045DC, 0xA933B37F, 0xBA2AEE2E, 0x4F24F65D, 0x349EE246,
+ 0xF97B9D0E, 0x46DC5759, 0x4529F425, 0x80D17B42, 0x8E16F709,
+ 0x1B42206A, 0x4934A526, 0x391BB6DE, 0xB52EF45C, 0x26C30290,
+ 0xCBA23CAA, 0xA501A8C3, 0xD922C4F8, 0xE8824E53, 0x6F4255DC,
+ 0x5960B544, 0x58BC69D6, 0xCA936323, 0xFDDF053C, 0xC2E002D6,
+ 0x7D750755, 0x8A3F9CD1, 0x35F8F6F8, 0xFB7BD154, 0x65CFF94F,
+ 0x390A58DD, 0xD97C4093, 0x501CA2A3, 0x8EA5DEBC, 0xCA93461F,
+ 0xE02D984C, 0x126F8517, 0x39FDD887, 0x46241AE9, 0x777E854D,
+ 0xE2B36349, 0x58E3FA9F, 0x971DEF1E, 0x8E156228, 0xC0E14E9,
+ 0xA9A01BE6, 0xB318C990, 0x971680D6, 0xA1F359CE, 0x487E23F4,
+ 0x7DE465B0, 0x4E4C905E, 0x2A652959, 0x116FF167, 0x5C74AAB9,
+ 0x467BBE00, 0x4703ABA3, 0x1F776B9C, 0xE2570A84, 0xFEC7DB48,
+ 0x1BD5012, 0xFD0A2D5D, 0x7FCC29F2, 0x291304B6, 0x99D5D8ED,
+ 0xC7551C8, 0xFD12F38F, 0xBADE8892, 0xDF749997, 0xA5DAE2F,
+ 0x2B9FA269, 0x5C13CFED, 0x15E9A399, 0x54437F4E, 0xA72DB2AB,
+ 0x56186AA1, 0xFE4DB55C, 0xA34D7836, 0x2A879760, 0xC63FA94,
+ 0xAC18B207, 0x5FC78B3, 0x7F10621E, 0xA769E6B2, 0xEC9F4A11,
+ 0xCE3F982C, 0x62BA2EF5, 0xA5F239CD, 0x4FEFC920, 0x28DF4EB8,
+ 0x29EBF45A, 0x1E350CF6
+ };
+
+/* The source data is random across the q31_t range. Accessing it by word should
+ remain random. */
+const q15_t * filtering_q15_inputs = (q15_t *) filtering_q31_inputs;
+const q7_t * filtering_q7_inputs = (q7_t *) filtering_q31_inputs;
+
+const float32_t filtering_f32_inputs[FILTERING_MAX_BLOCKSIZE * FILTERING_MAX_M + FILTERING_MAX_NUMTAPS] =
+{
+ 43.0264275639 , -17.0525215570 , -94.8488973910 , -8.1924989580 , 7.2830326091 , 66.8368719314 , 33.9778190671 , 117.8652289772 ,
+ -129.6077797465, -14.6420815368 , 18.0239223278 , 20.6760530292 , 55.0375037651 , 1.8674609862 , -85.6534302408 , -33.5750364909 ,
+ 29.2110949614 , 110.4727049460 , -94.1914619387 , -1.4084169343 , 83.5181653041 , 47.3073514127 , -13.3420621181 , 30.3389699104 ,
+ 12.1188124277 , 100.9730921941 , -114.0146362390, -77.5823200409 , 37.2019034618 , 40.0026301128 , -58.3387276630 , -34.9472398600 ,
+ -5.1169678311 , -87.7660091118 , -150.5888601131, 56.0349370503 , 50.2168884079 , -74.2313236767 , 22.3648603560 , -6.8676387051 ,
+ 74.8957303680 , -90.1292012823 , -55.1436241586 , -66.6732976100 , -6.7918147615 , 7.7612697081 , 35.7892605979 , -20.0470508830 ,
+ 41.8369017546 , -143.7378056984, -41.9127158600 , -108.3531841158, -57.1917422289 , -124.2808828105, 38.9316388820 , -77.9212517405 ,
+ 37.1990818377 , -28.9545952748 , -155.6371057564, 45.8088886393 , 36.2537018275 , -6.5727656016 , -104.2070491921, 45.5583813729 ,
+ -19.7674717059 , -80.4802190947 , -1.4444563441 , -42.2142256438 , 36.6546339194 , -57.0866498590 , 44.4677067511 , 65.7285753407 ,
+ -103.8158864647, 25.4348723711 , -153.5419639389, 39.3608409474 , 49.1658103436 , 79.5570602275 , 75.2944095996 , 58.9394700746 ,
+ -53.1018534392 , 33.4172444014 , 35.6224682287 , -64.4353396418 , -125.8464291251, -47.6072111617 , -26.2177687594 , -12.0061322096 ,
+ -17.7887967585 , -28.2926175090 , -62.0691715749 , 40.5098573604 , -191.1123732593, 119.6750713043 , 19.6182375803 , -26.7615252921 ,
+ 2.2957847015 , -108.3436451287, -50.5906164995 , -5.6360985100 , -11.6772204201 , -84.2765293757 , -60.9317810068 , 82.0446350218 ,
+ -70.2048296348 , 72.8738253222 , 60.2450218115 , 114.2741231228 , 46.8180775285 , 6.9915412654 , -8.9909197429 , -78.9165936808 ,
+ 66.4731535459 , -68.4235455651 , -79.8254597080 , -10.6308477115 , -62.6161569330 , -55.7744410292 , -11.8408366528 , 98.1034940997 ,
+ 35.8213741877 , -54.4694482732 , 86.9631830044 , -53.0343838122 , -47.4898642865 , -47.2010929590 , -31.3312639685 , -23.0908245172 ,
+ 12.0258009869 , -5.1098204703 , -9.8420230737 , -107.3328761158, 44.6810431959 , -17.9083820345 , -60.9753512872 , -7.5915088994 ,
+ 17.2250813329 , 57.9176125648 , 124.3004161362 , -63.1950908493 , 120.5788885640 , -44.1734238117 , -91.7408095116 , -43.5696066595 ,
+ -49.9560710099 , -167.8513443296, -70.9437505499 , -46.4109705355 , -64.2264526456 , -13.9995803916 , -100.9548186356, 9.9101010575 ,
+ -50.0615130815 , -55.7590145012 , -60.3195153388 , 61.7913378549 , -102.0850899209, 53.2360193126 , -25.8997883369 , 75.1445512333 ,
+ -113.8148602310, 17.8027281119 , -19.5006822722 , -44.2169628471 , 107.5017084384 , -113.7909124666, -43.9735396033 , 7.6880981388 ,
+ 46.7384653508 , 9.9047443751 , 81.8646964362 , 132.3812863877 , -95.6959050236 , -68.5015813484 , 65.8586404494 , 18.5039353889 ,
+ -30.1786166621 , -90.3098515667 , -22.9356228552 , -20.5778272423 , -2.2127786675 , -35.4418447703 , -51.8722915974 , -107.9024439078,
+ -51.5940748232 , -51.7463262677 , 74.2795485984 , 94.2205022462 , 9.7016384049 , -47.3556083155 , -36.7822314478 , -151.6455525363,
+ -15.7183814485 , 78.2063383182 , 0.1516414969 , 37.9304181609 , 20.6185902740 , -22.2164106778 , 6.1160554677 , 2.4061326953 ,
+ -111.6681824598, -60.0858917090 , 75.1698614693 , -76.5787410444 , 28.3391655715 , -2.4946186443 , -68.0378899682 , 104.0893199171 ,
+ -51.8319647254 , 38.8521710524 , 75.9114239564 , 73.9206172905 , -103.2533029987, 6.9002718274 , -36.6346436319 , -25.1990926265 ,
+ 1.5852145953 , -50.6438436795 , 21.5018844428 , -151.9305562846, -51.7326681814 , 21.4475994143 , 42.2564011921 , -74.0520586926 ,
+ 49.7370635809 , -13.2957534126 , 36.6746826778 , -31.7005492589 , 148.4894964268 , 79.7890632353 , 16.8856024809 , 16.1690460177 ,
+ 39.2665169484 , 117.2461167794 , -37.4827984831 , -47.8387803604 , -95.7025286193 , 34.3058214285 , -124.9536456028, 56.1640195764 ,
+ 94.3636873606 , 35.3992852810 , -38.3920852159 , -100.5738062016, -29.7837022314 , 42.9133913996 , -34.2715618187 , -14.3589115627 ,
+ -16.5935468750 , 20.4574192236 , -88.7897972666 , -38.6285080386 , 53.3203422726 , 98.5991486746 , 122.7305462474 , 67.7902817187 ,
+ 5.1764117389 , 5.0632821624 , 21.9288789574 , -78.3140512638 , -21.2069682335 , 23.6342010925 , 34.4445769455 , 59.1346766615 ,
+ 28.9978778000 , 39.8121180845 , -17.1650033520 , -56.9174900874 , 17.8157086148 , -112.8801457350, -122.4019040408, 140.8669393157 ,
+ -65.4664329639 , 40.6952775518 , 32.7260891658 , -43.2565155866 , 19.3945751928 , -20.1815002000 , -67.6601711640 , -18.1921178207 ,
+ -35.6802153684 , 49.9550290306 , 131.4925251016 , -31.2940938167 , -5.2848453344 , -109.5580577933, 20.2437599390 , -8.8782958734 ,
+ 54.1836717264 , 7.2555852190 , -3.5698316137 , -51.9236786262 , 6.7861547980 , -104.4814551670, 45.8458629668 , 70.0890876844 ,
+ 38.3572837740 , 61.8024165129 , 68.0176962024 , -12.8193934080 , -21.4661610917 , -0.9377108815 , -74.2100679061 , 71.0490808147 ,
+ 91.9813889497 , -14.5797640164 , 3.5036749129 , -138.3605478356, -48.1501349794 , -16.0636922482 , -12.1334197606 , 15.0562207637 ,
+ -34.0878176054 , 55.1075126157 , 97.3829871877 , 0.2053358099 , -94.8713267382 , 51.5460954054 , 21.2966946363 , 58.1331025047 ,
+ -23.4599044132 , -19.3315856528 , -8.4497193577 , -1.9594679356 , -33.1906549336 , -144.6825417978, -57.1218958072 , 35.7353406097 ,
+ 61.4666549819 , 14.6536253128 , 82.1632196866 , -44.6230161723 , -91.1022589278 , -18.5737673927 , -136.8975612334, 56.9606788003 ,
+ 70.7059960183 , -68.2829345081 , -10.2629800455 , -53.6385325047 , -68.7928766204 , 88.2444688302 , 83.1412324801 , -102.9206928160,
+ -68.2329763159 , -69.7552955469 , 108.2132269009 , -28.2582329307 , 5.6685898328 , -36.0392956840 , 43.3269513128 , -8.6436416796 ,
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+ 65.7430288442 , -131.8695390036, 10.2750933946 , 90.9752774838 , -26.5859990591 , -95.6962772568 , 76.2174589344 , 24.8796848060 ,
+ -38.8938223046 , 54.1687774852 , -37.3585968996 , -34.6848570502 , 33.0151011570 , -55.8345877671 , -3.9009101671 , -31.5024971691 ,
+ -9.6863895491 , 91.8719195957 , -58.9993249744 , -25.6887030614 , -8.0829472205 , 4.6386491741 , -71.4019697167 , -21.3734669095 ,
+ 86.2079144404 , 79.6823974266 , -0.0910915997 , 44.8067718095 , 58.7204020766 , 72.6856808976 , -50.3373732478 , -116.1175365534,
+ -15.0884909384 , 5.4593772059 , -63.6553527905 , 37.3460388205 , -32.2399421679 , 95.7569350513 , -7.3700141964 , -56.0370832967 ,
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+ -20.3704610276 , 15.8571376404 , 88.9127217235 , -33.1132582267 , -1.0005675836 , -28.1780471904 , 150.9349379135 , 38.0600520828 ,
+ 36.4338677563 , -3.3709201641 , 29.7709773016 , 16.5064119077 , 21.3147729463 , 110.6714300904 , 18.8406036507 , 14.8963298097 ,
+ 50.9975960392 , 16.3991140350 , -194.0805845907, -41.6723945839 , -74.8991127408 , -6.4587655805 , -0.6883628218 , -49.8709647175 ,
+ 194.2265120473 , 64.3043624521 , 16.0040882780 , 68.4032551772 , -43.4050313128 , 84.6826289824 , -28.1357565943 , 134.6895584120 ,
+ -7.9746152680 , -95.6692886462 , -48.9444370342 , 79.4479343188 , -50.5345228122 , 52.4800633307 , -14.7735051703 , -20.1510237050 ,
+ 22.5049816980 , 64.4191999102 , 24.8385648232 , 99.4265041360 , 62.0189508473 , -28.3892600378 , -109.8842008564, -79.0407483407 ,
+ 18.3408112020 , 49.1650536089 , 31.5419844924 , -36.1160722679 , -132.9148081329, 10.4053531567 , -129.2463715470, -43.4602207151 ,
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+ 66.0224147666 , -13.6794615513 , 101.2163279622 , -62.4462618603 , 22.2040981785 , -52.3208382802 , -24.7909079016 , 58.5150375093 ,
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+ 8.4213193211 , 79.9349022793 , 60.0160502260 , 32.2272994080 , -72.2893887746 , 17.3063698247 , -134.6335742431, 64.6499736261 ,
+ 7.1411921919 , -37.5517577873 , 6.2405670930 , 117.1920927305 , 128.7420689815 , -3.1556854963 , -13.4100422909 , -11.9336372907 ,
+ -8.6022400553 , -102.0033506666, -78.4696575074 , 15.0765861403 , -111.5219718576, -13.4162786508 , 38.2437013694 , 61.1637732561 ,
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+ 59.9383486599 , -4.6301990580 , 5.0361682939 , -10.5669407980 , 124.0908762205 , 35.8305364082 , -123.6216777114, -74.2569079167 ,
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+ 151.4550562868 , 62.8957092621 , -116.8103461233, 5.1129927759 , -33.2252515135 , -9.4522506046 , 22.7026048372 , -15.5264414569 ,
+ 71.2087620034 , 19.1191568332 , 50.3019546809 , -5.6096922409 , 22.9344126462 , -7.7591876203 , 31.8949515564 , -58.4253952381 ,
+ 66.4341297173 , -19.0583083044 , 96.7695087855 , 20.4934280047 , 4.9544603116 , -20.8288135920 , -173.2659655408, -62.4883621640 ,
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+ 28.1480473670 , 46.4006562684 , 97.7001828545 , 4.0855607626 , -32.6097018162 , 16.8913949959 , 105.7266202978 , -89.3978374651 ,
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+ 68.3566199798 , -13.8451547552 , -71.1629911780 , 36.2989433752 , -32.4867163365 , 112.4079947071 , -75.6295117422 , 47.5276421639 ,
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+ -26.9924731886 , 53.7879986570 , -83.1658398348 , 23.6381378489 , 43.8794937753 , -55.4133836419 , 90.0266130838 , 14.1036181982 ,
+ -18.1225736715 , 85.1363181151 , -62.5970846379 , -18.5291947838 , -25.7341986703 , -49.7061342931 , -59.0442763971 , 50.8960636803 ,
+ -87.6471123430 , -36.7217762531 , 22.5952364054 , 11.1107885650 , -0.5377327229 , 160.8145792630 , 73.3103441505 , 10.1656872354 ,
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+ -25.8517575250 , -69.9538258421 , -17.5730160671 , 15.9405836751 , 113.9545230349 , -46.1040379057 , -94.2458635014 , -69.0338522452 ,
+ 43.5813790265 , 107.1836101171 , -55.1012654323 , -77.1529555887 , -33.1530320656 , -94.5582659641 , -53.6837586872 , 27.0680381378 ,
+ 93.9385415207 , -61.0955216188 , 18.0530957225 , 7.9150142320 , -12.1218191587 , 34.0173961457 , 40.0084937565 , 9.8119275580 ,
+ 44.2065861274 , -1.8718514394 , 67.4740024215 , 46.7391150131 , 207.2404815875 , 45.1635364462 , 43.3580102761 , -44.0244218674 ,
+ 83.2387206007 , -8.6441851856 , 12.3993902588 , -22.5091685270 , -19.8332981376 , 97.9196509289 , -76.6720306234 , 28.9740705859 ,
+ 121.9415248016 , 9.6656982611 , -51.0996453694 , 37.3704374740 , 74.7589840907 , -113.4066752631, 120.0029566342 , -105.3786221360,
+ 81.8152755619 , -13.4979932982 , -21.4680758393 , -85.1088235539 , -65.3610798409 , -35.0444139470 , -48.0220794487 , -41.6210317362 ,
+ 33.1212995259 , -82.1480936443 , -10.5479715135 , 76.4601917004 , 42.1983651157 , 92.6104239912 , -42.3536237955 , -24.5644182272 ,
+ 30.4446637772 , -90.2899420489 , 63.6723540422 , 103.0895811428 , 64.1706769263 , -10.7069812309 , 21.8927240409 , 6.3571071738 ,
+ 57.1457649358 , -52.9866276448 , 66.0981829072 , -29.5372056881 , -79.2252039810 , -136.2440652798, -57.0106422562 , 86.8203548141 ,
+ 66.4244149837 , 53.3230426111 , -66.1283059222 , -131.0402660353, 8.0548411081 , 122.9088988100 , 1.2626894208 , -60.5059112373 ,
+ -68.8707203082 , -6.4747987200 , 85.8411327244 , 99.9624156733 , 90.4197864338 , -35.9630441182 , -22.9158275507 , -17.3660128776 ,
+ 16.7845345761 , 34.7219749782 , -39.3513765878 , 1.0460702756 , -60.9494500182 , 20.0900333387 , -85.9636743832 , 88.4400782168 ,
+ 15.0729628728 , 61.5499846243 , 11.8579871757 , 107.8617581581 , -42.9393027864 , -62.8422307621 , -19.0589600542 , 4.0750325807 ,
+ -36.0651825425 , 55.7638724501 , -10.4691736080 , -55.5672537178 , -61.2061519915 , -21.1885348576 , -131.2535612498, 24.7463552676 ,
+ 22.9426321237 , 14.3038202264 , -138.0926317438, -59.0892900856 , -162.5416439986, 7.1307658250 , -141.1236672256, -4.7173618068 ,
+ -16.7741532807 , -68.2615451173 , -2.6608701102 , 84.1978109826 , -11.3446202072 , 59.9630033088 , -1.8994925010 , -37.9301641959 ,
+ -119.4435600954, -11.4587491646 , 12.2423215240 , -7.3169898616 , -67.0373621128 , 36.0198843055 , 53.9791315249 , -134.5885680695,
+ -83.8330811965 , -16.6714816463 , -8.8498552035 , -24.0513088196 , -22.9444328877 , -37.7961441531 , 25.1975736186 , -136.1611637464,
+ -5.0843464033 , -10.3939554694 , 20.7422826935 , 75.6854136623 , 46.4179626736 , -57.0052830175 , 7.3457235521 , -51.5504447254 ,
+ -158.4375751701, -200.2426967181, -48.1234996261 , 1.6623945527 , 21.1746524375 , 99.4092980367 , -2.3206772903 , 45.7989166757 ,
+ 2.0181548348 , -88.0556010969 , -59.1527212096 , 47.3607925077 , -10.4181140309 , 56.3558125650 , -8.9799125560 , -30.0376711812 ,
+ -36.7132904688 , 35.7785050392 , -13.0763909369 , -2.1855594714 , 18.1550954005 , -28.6711803575 , -55.4495172398 , -2.8812973198 ,
+ -59.9575059158 , 40.0588875786 , 57.4713686602 , -3.2835144853 , -36.7193552111 , -64.9415131516 , -166.9555466445, -23.5556853844 ,
+ -54.9408569587 , -35.2310451959 , 21.3345143458 , 65.7590671151 , 51.2214538168 , 46.1271939944 , -42.2235267919 , 127.2329928299 ,
+ 105.2391778600 , 17.6726845966 , -129.9021148044, 8.7065613044 , -94.0987112511 , -3.5375742950 , -23.1385452379 , 60.6219530633 ,
+ 92.5445564235 , 48.5111974469 , -52.5699309159 , -60.0634811685 , 25.9034368684 , 140.0249495491 , 1.5918852392 , 38.0266038291 ,
+ 17.5588710703 , 3.4294066089 , -27.6748782173 , 59.6182974489 , -35.2924781853 , -38.6198576115 , -13.6119803198 , 7.8375587489 ,
+ 22.7250686519 , -28.3524510951 , -34.4269062817 , 22.6464817325 , -61.6528147860 , -5.9782002429 , 61.4730771294 , 43.5582379527 ,
+ 55.6862408270 , 87.8745651631 , 46.3401042715 , -19.8780979663 , 74.1272633369 , 29.8590452377 , -12.8665765140 , 34.2931401219 ,
+ 53.9279617551 , -16.9017895140 , -70.1527553166 , -79.6367897992 , 109.3728271017 , -129.2214826835, -53.4644539730 , -51.5654458993 ,
+ 17.6062148433 , 3.5090251835 , 74.2615941204 , -109.3431097845, 40.1403465151 , 28.8714561280 , 94.0868659302 , -19.0047033845 ,
+ -60.0967410050 , -19.0998457619 , -67.2027075128 , 72.0711434846 , -17.8737851232 , 123.7050551274 , 132.6331504104 , 25.5018761009 ,
+ -36.7817189239 , -29.1580893235 , -6.5848563828 , 90.2868948516 , -35.7017258498 , -68.5675432955 , -52.4888589786 , 47.1377730021 ,
+ -7.4546621940 , -52.0657517138 , -49.0404829633 , -114.6910280126, -117.6819819437, -32.7856729408 , 31.8232065591 , 12.1192973039 ,
+ 35.2678513420 , -1.0336778293 , 30.7021249679 , 127.0442906046 , -84.8457819393 , 28.9862843096 , -47.3524701726 , -126.1094998460,
+ -2.9700276582 , -2.4956545870 , -53.8624121141 , -85.2114117637 , 76.9057985618 , 137.1205201755 , -19.0830817212 , 14.3407526579 ,
+ -56.5921994449 , -25.6084873186 , -44.9470801106 , -133.3139496090, 0.3487447576 , 33.4499716730 , 34.7126257844 , -9.3307383323 ,
+ 27.2996276947 , 10.8765676134 , -91.1032360444 , -90.9584216222 , 1.6981490570 , 96.8557438791 , 56.7726390913 , -44.3246449237 ,
+ 52.3260643361 , 21.5551140465 , 27.4535327381 , 2.0072717479 , 7.4823125629 , 77.1185863870 , 16.1372262663 , -10.7206012957 ,
+ 66.8830091413 , 49.3523828287 , 54.0855375598 , 30.8570349345 , -10.9255375390 , 62.3910624674 , 30.9238561381 , 0.3352881853 ,
+ 72.1022806197 , -28.8319885008 , 23.3335288806 , 46.8999035980 , -67.0984424822 , -164.7917209112, 42.5767681360 , -92.4668227688 ,
+ 43.8491734282 , -17.1126540408 , 37.4819594334 , 69.0774409673 , -39.3530526854 , -14.0693747124 , -60.2520781215 , -80.3860105519 ,
+ 32.6689956840 , 15.3393042576 , -18.5529761307 , 97.3942151573 , -4.4462855745 , 13.7614349817 , 158.3358780719 , -44.7258299667 ,
+ -17.7741912819 , 116.5136962268 , -33.6261057820 , 22.8344441288 , -155.1423976144, 5.7070117893 , -22.7906543902 , -45.0633909283 ,
+ -13.9329987929 , -66.0848932507 , 1.1383038109 , 123.8386958483 , 67.6662401589 , 45.9152963554 , -27.4397697462 , 97.9596747354 ,
+ -6.3544655181 , 29.0832146722 , 96.3468162499 , 32.4535976137 , -91.0650399301 , 2.7293262791 , 70.7853483111 , -92.3655274571 ,
+ 69.0359217256 , 83.1530567979 , 35.8375091111 , 7.3393552348 , -95.1770165365 , 76.4905790891 , 55.6253140577 , -29.5315327050 ,
+ -16.5935468750 , 20.4574192236 , -88.7897972666 , -38.6285080386 , 53.3203422726 , 98.5991486746 , 122.7305462474 , 67.7902817187 ,
+ 5.1764117389 , 5.0632821624 , 21.9288789574 , -78.3140512638 , -21.2069682335 , 23.6342010925 , 34.4445769455 , 59.1346766615 ,
+ 28.9978778000 , 39.8121180845 , -17.1650033520 , -56.9174900874 , 17.8157086148 , -112.8801457350, -122.4019040408, 140.8669393157 ,
+ -65.4664329639 , 40.6952775518 , 32.7260891658 , -43.2565155866 , 19.3945751928 , -20.1815002000 , -67.6601711640 , -18.1921178207 ,
+ -35.6802153684 , -19.6571455162
+};
+
+const float64_t filtering_f64_inputs[FILTERING_MAX_BLOCKSIZE * FILTERING_MAX_M + FILTERING_MAX_NUMTAPS] =
+{
+ 43.0264275639 , -17.0525215570 , -94.8488973910 , -8.1924989580 , 7.2830326091 , 66.8368719314 , 33.9778190671 , 117.8652289772 ,
+ -129.6077797465, -14.6420815368 , 18.0239223278 , 20.6760530292 , 55.0375037651 , 1.8674609862 , -85.6534302408 , -33.5750364909 ,
+ 29.2110949614 , 110.4727049460 , -94.1914619387 , -1.4084169343 , 83.5181653041 , 47.3073514127 , -13.3420621181 , 30.3389699104 ,
+ 12.1188124277 , 100.9730921941 , -114.0146362390, -77.5823200409 , 37.2019034618 , 40.0026301128 , -58.3387276630 , -34.9472398600 ,
+ -5.1169678311 , -87.7660091118 , -150.5888601131, 56.0349370503 , 50.2168884079 , -74.2313236767 , 22.3648603560 , -6.8676387051 ,
+ 74.8957303680 , -90.1292012823 , -55.1436241586 , -66.6732976100 , -6.7918147615 , 7.7612697081 , 35.7892605979 , -20.0470508830 ,
+ 41.8369017546 , -143.7378056984, -41.9127158600 , -108.3531841158, -57.1917422289 , -124.2808828105, 38.9316388820 , -77.9212517405 ,
+ 37.1990818377 , -28.9545952748 , -155.6371057564, 45.8088886393 , 36.2537018275 , -6.5727656016 , -104.2070491921, 45.5583813729 ,
+ -19.7674717059 , -80.4802190947 , -1.4444563441 , -42.2142256438 , 36.6546339194 , -57.0866498590 , 44.4677067511 , 65.7285753407 ,
+ -103.8158864647, 25.4348723711 , -153.5419639389, 39.3608409474 , 49.1658103436 , 79.5570602275 , 75.2944095996 , 58.9394700746 ,
+ -53.1018534392 , 33.4172444014 , 35.6224682287 , -64.4353396418 , -125.8464291251, -47.6072111617 , -26.2177687594 , -12.0061322096 ,
+ -17.7887967585 , -28.2926175090 , -62.0691715749 , 40.5098573604 , -191.1123732593, 119.6750713043 , 19.6182375803 , -26.7615252921 ,
+ 2.2957847015 , -108.3436451287, -50.5906164995 , -5.6360985100 , -11.6772204201 , -84.2765293757 , -60.9317810068 , 82.0446350218 ,
+ -70.2048296348 , 72.8738253222 , 60.2450218115 , 114.2741231228 , 46.8180775285 , 6.9915412654 , -8.9909197429 , -78.9165936808 ,
+ 66.4731535459 , -68.4235455651 , -79.8254597080 , -10.6308477115 , -62.6161569330 , -55.7744410292 , -11.8408366528 , 98.1034940997 ,
+ 35.8213741877 , -54.4694482732 , 86.9631830044 , -53.0343838122 , -47.4898642865 , -47.2010929590 , -31.3312639685 , -23.0908245172 ,
+ 12.0258009869 , -5.1098204703 , -9.8420230737 , -107.3328761158, 44.6810431959 , -17.9083820345 , -60.9753512872 , -7.5915088994 ,
+ 17.2250813329 , 57.9176125648 , 124.3004161362 , -63.1950908493 , 120.5788885640 , -44.1734238117 , -91.7408095116 , -43.5696066595 ,
+ -49.9560710099 , -167.8513443296, -70.9437505499 , -46.4109705355 , -64.2264526456 , -13.9995803916 , -100.9548186356, 9.9101010575 ,
+ -50.0615130815 , -55.7590145012 , -60.3195153388 , 61.7913378549 , -102.0850899209, 53.2360193126 , -25.8997883369 , 75.1445512333 ,
+ -113.8148602310, 17.8027281119 , -19.5006822722 , -44.2169628471 , 107.5017084384 , -113.7909124666, -43.9735396033 , 7.6880981388 ,
+ 46.7384653508 , 9.9047443751 , 81.8646964362 , 132.3812863877 , -95.6959050236 , -68.5015813484 , 65.8586404494 , 18.5039353889 ,
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+ 52.3260643361 , 21.5551140465 , 27.4535327381 , 2.0072717479 , 7.4823125629 , 77.1185863870 , 16.1372262663 , -10.7206012957 ,
+ 66.8830091413 , 49.3523828287 , 54.0855375598 , 30.8570349345 , -10.9255375390 , 62.3910624674 , 30.9238561381 , 0.3352881853 ,
+ 72.1022806197 , -28.8319885008 , 23.3335288806 , 46.8999035980 , -67.0984424822 , -164.7917209112, 42.5767681360 , -92.4668227688 ,
+ 43.8491734282 , -17.1126540408 , 37.4819594334 , 69.0774409673 , -39.3530526854 , -14.0693747124 , -60.2520781215 , -80.3860105519 ,
+ 32.6689956840 , 15.3393042576 , -18.5529761307 , 97.3942151573 , -4.4462855745 , 13.7614349817 , 158.3358780719 , -44.7258299667 ,
+ -17.7741912819 , 116.5136962268 , -33.6261057820 , 22.8344441288 , -155.1423976144, 5.7070117893 , -22.7906543902 , -45.0633909283 ,
+ -13.9329987929 , -66.0848932507 , 1.1383038109 , 123.8386958483 , 67.6662401589 , 45.9152963554 , -27.4397697462 , 97.9596747354 ,
+ -6.3544655181 , 29.0832146722 , 96.3468162499 , 32.4535976137 , -91.0650399301 , 2.7293262791 , 70.7853483111 , -92.3655274571 ,
+ 69.0359217256 , 83.1530567979 , 35.8375091111 , 7.3393552348 , -95.1770165365 , 76.4905790891 , 55.6253140577 , -29.5315327050 ,
+ -16.5935468750 , 20.4574192236 , -88.7897972666 , -38.6285080386 , 53.3203422726 , 98.5991486746 , 122.7305462474 , 67.7902817187 ,
+ 5.1764117389 , 5.0632821624 , 21.9288789574 , -78.3140512638 , -21.2069682335 , 23.6342010925 , 34.4445769455 , 59.1346766615 ,
+ 28.9978778000 , 39.8121180845 , -17.1650033520 , -56.9174900874 , 17.8157086148 , -112.8801457350, -122.4019040408, 140.8669393157 ,
+ -65.4664329639 , 40.6952775518 , 32.7260891658 , -43.2565155866 , 19.3945751928 , -20.1815002000 , -67.6601711640 , -18.1921178207 ,
+ -35.6802153684 , -19.6571455162
+};
+
+/*--------------------------------------------------------------------------------*/
+/* Blocksizes */
+/*--------------------------------------------------------------------------------*/
+ARR_DESC_DEFINE(uint32_t,
+ filtering_blocksizes,
+ 5,
+ CURLY(
+ 1, 7, 14, 32, FILTERING_MAX_BLOCKSIZE));
+
+ARR_DESC_DEFINE(uint32_t,
+ lms_blocksizes,
+ 3,
+ CURLY(
+ 128, 256, LMS_MAX_BLOCKSIZE));
+
+ARR_DESC_DEFINE(uint16_t,
+ filtering_numtaps,
+ 5,
+ CURLY(
+ 4, 6, 14, 32, FILTERING_MAX_NUMTAPS));
+
+ARR_DESC_DEFINE(uint16_t,
+ filtering_numtaps2,
+ 5,
+ CURLY(
+ 6, 12, 18, 24, 30));
+
+ARR_DESC_DEFINE(uint16_t,
+ filtering_numstages,
+ 3,
+ CURLY(
+ 1, 7, FILTERING_MAX_NUMSTAGES));
+
+ARR_DESC_DEFINE(uint8_t,
+ filtering_postshifts,
+ 3,
+ CURLY(
+ 0, 1, FILTERING_MAX_POSTSHIFT));
+
+ARR_DESC_DEFINE(uint8_t,
+ filtering_Ls,
+ 3,
+ CURLY(
+ 1, 2, FILTERING_MAX_L));
+
+ARR_DESC_DEFINE(uint8_t,
+ filtering_Ms,
+ 6,
+ CURLY(
+ 1, 2, 4, 7, 11, FILTERING_MAX_M));
+
+
+/*--------------------------------------------------------------------------------*/
+/* Coefficient Lists */
+/*--------------------------------------------------------------------------------*/
+
+// There must be at least max( FILTERING_MAX_NUMTAPS + 2 , FILTERING_MAX_NUMSTAGES * 6 + 2) coefficients
+const float32_t filtering_coeffs_f32[FILTERING_MAX_NUMSTAGES * 6 + 2] =
+{
+ -13.0572f, 0.0f , -97.4724f, 8.4111f , -7.2193f , -53.7577f, 22.2630f ,
+ -1.0509f , -25.9198f, 26.5207f , -12.6697f, -78.7453f, -0.6540f , 0.3119f ,
+ 13.4595f , -6.7225f , -4.1313f , -38.5974f, 3.2700f , -51.6191f, -22.4314f,
+ 0.2481f , 32.9779f , -37.6421f, 5.4469f , -7.0023f , 24.3657f , 9.9140f ,
+ 0.2870f , -13.0499f, 29.3333f , -53.1396f, -2.7555f , 0.5377f , 35.3491f ,
+ -3.7134f , 0.8548f , 4.7469f , -10.5865f, -2.7285f , -1.5912f , -13.3502f,
+ 6.8532f , -8.2304f , -8.1193f , 3.8257f , -2.1703f , 13.5727f , 14.2736f ,
+ -0.9855f , -8.9334f , -13.8883f, 11.8430f , -2.2024f , 0.9795f , 15.6191f ,
+ 5.2121f , 10.8102f , -9.4171f , 6.0411f , -0.9131f , 10.6992f , -3.2634f ,
+ 7.5849f , -4.9305f , -6.0549f , -7.9409f , 1.5827f , 13.3177f , 8.6727f ,
+ -13.2268f , 11.1239f , 0.2481f , 32.9779f , -37.6421f, 5.4469f , -13.8883f,
+ 11.8430f , -2.2024f , 0.9795f , 15.6191f , 0.2481f , 32.9779f , -37.6421f,
+ 3.2700f , -51.6191f
+};
+const float64_t filtering_coeffs_f64[FILTERING_MAX_NUMSTAGES * 6 + 2] =
+{
+ -13.0572f, 0.0f , -97.4724f, 8.4111f , -7.2193f , -53.7577f, 22.2630f ,
+ -1.0509f , -25.9198f, 26.5207f , -12.6697f, -78.7453f, -0.6540f , 0.3119f ,
+ 13.4595f , -6.7225f , -4.1313f , -38.5974f, 3.2700f , -51.6191f, -22.4314f,
+ 0.2481f , 32.9779f , -37.6421f, 5.4469f , -7.0023f , 24.3657f , 9.9140f ,
+ 0.2870f , -13.0499f, 29.3333f , -53.1396f, -2.7555f , 0.5377f , 35.3491f ,
+ -3.7134f , 0.8548f , 4.7469f , -10.5865f, -2.7285f , -1.5912f , -13.3502f,
+ 6.8532f , -8.2304f , -8.1193f , 3.8257f , -2.1703f , 13.5727f , 14.2736f ,
+ -0.9855f , -8.9334f , -13.8883f, 11.8430f , -2.2024f , 0.9795f , 15.6191f ,
+ 5.2121f , 10.8102f , -9.4171f , 6.0411f , -0.9131f , 10.6992f , -3.2634f ,
+ 7.5849f , -4.9305f , -6.0549f , -7.9409f , 1.5827f , 13.3177f , 8.6727f ,
+ -13.2268f , 11.1239f , 0.2481f , 32.9779f , -37.6421f, 5.4469f , -13.8883f,
+ 11.8430f , -2.2024f , 0.9795f , 15.6191f , 0.2481f , 32.9779f , -37.6421f,
+ 3.2700f , -51.6191f
+};
+
+const float32_t filtering_coeffs_b_f32[FILTERING_MAX_NUMSTAGES * 6 + 2] =
+{
+ -0.0572f, 0.0f , -0.4724f, 0.4111f , -0.9999f, -0.7577f, 0.2630f ,
+ -0.0509f, -1.0000f, 0.5207f , -0.6697f, -0.7453f, -0.6540f, 0.3119f ,
+ 0.4595f , -0.7225f, -0.1313f, -0.5974f, 0.2700f , -0.6191f, -0.4314f,
+ 0.2481f , 0.9779f , -0.6421f, 0.4469f , -0.0023f, 0.3657f , 0.9140f ,
+ 0.2870f , -0.0499f, 0.3333f , -0.1396f, -0.7555f, 0.5377f , 0.3491f ,
+ 0.2369f , -0.5310f, -0.5904f, 0.6263f , 0.0205f , 0.1088f , -0.2926f,
+ -0.4187f, -0.5094f, 0.4479f , -0.3594f, -0.3102f, 0.6748f , 0.7620f ,
+ 0.0033f , -0.9195f, 0.3192f , -0.1705f, 0.5524f , -0.5025f, 0.4898f ,
+ -0.0119f, -0.3982f, -0.7818f, -0.9186f, -0.0944f, 0.7228f , 0.7014f ,
+ 0.4850f , -0.6814f, 0.4914f , -0.6286f, 0.5130f , -0.8585f, 0.3000f ,
+ 0.6068f , 0.4978f , -0.7225f, -0.1313f, -0.5974f, 0.2700f , -0.6191f,
+ 0.2481f , 0.9779f , -0.6421f, 0.4469f , -0.0023f, 0.3657f , 0.9140f ,
+ 0.2369f , -0.5310f
+};
+
+const float64_t filtering_coeffs_b_f64[FILTERING_MAX_NUMSTAGES * 6 + 2] =
+{
+ -0.0572f, 0.0f , -0.4724f, 0.4111f , -0.9999f, -0.7577f, 0.2630f ,
+ -0.0509f, -1.0000f, 0.5207f , -0.6697f, -0.7453f, -0.6540f, 0.3119f ,
+ 0.4595f , -0.7225f, -0.1313f, -0.5974f, 0.2700f , -0.6191f, -0.4314f,
+ 0.2481f , 0.9779f , -0.6421f, 0.4469f , -0.0023f, 0.3657f , 0.9140f ,
+ 0.2870f , -0.0499f, 0.3333f , -0.1396f, -0.7555f, 0.5377f , 0.3491f ,
+ 0.2369f , -0.5310f, -0.5904f, 0.6263f , 0.0205f , 0.1088f , -0.2926f,
+ -0.4187f, -0.5094f, 0.4479f , -0.3594f, -0.3102f, 0.6748f , 0.7620f ,
+ 0.0033f , -0.9195f, 0.3192f , -0.1705f, 0.5524f , -0.5025f, 0.4898f ,
+ -0.0119f, -0.3982f, -0.7818f, -0.9186f, -0.0944f, 0.7228f , 0.7014f ,
+ 0.4850f , -0.6814f, 0.4914f , -0.6286f, 0.5130f , -0.8585f, 0.3000f ,
+ 0.6068f , 0.4978f , -0.7225f, -0.1313f, -0.5974f, 0.2700f , -0.6191f,
+ 0.2481f , 0.9779f , -0.6421f, 0.4469f , -0.0023f, 0.3657f , 0.9140f ,
+ 0.2369f , -0.5310f
+};
+
+const float32_t *filtering_coeffs_c_f32 = filtering_coeffs_b_f32 + 1;
+
+const q31_t filtering_coeffs_q31[FILTERING_MAX_NUMSTAGES * 6 + 2] =
+{
+ 0xEEDA759C, 0x00000000, 0x80000000, 0x0B0BA027, 0xF6850544, 0xB967E3EC,
+ 0x1D3C4F64, 0xFFFFFFFF, 0xDDF65B14, 0x22D3A62D, 0xEF5CBB89, 0x98979EE0,
+ 0xFF242597, 0x0068D9E9, 0x11ACC4F3, 0xF72C0F21, 0xFA9326BC, 0xCD506BD5,
+ 0x044B50CD, 0xBC36D4BC, 0xE28B1589, 0x0053690B, 0x2B4E6639, 0xCE919690,
+ 0x0727234D, 0xF6CDFB14, 0x1FFF2FCF, 0x0D04DC35, 0x00607E4D, 0xEEDCF04A,
+ 0x268530EF, 0xBA37B050, 0x7FFFFFFF, 0xEF5CBB89, 0x00000000, 0x2B4E6639,
+ 0xFF242597, 0x0068D9E9, 0x11ACC4F3, 0xF72C0F21, 0xFA9326BC, 0xCD506BD5,
+ 0x1D3C4F64, 0xFFFFFFFF, 0xDDF65B14, 0x22D3A62D, 0xEF5CBB89, 0x98979EE0,
+ 0x044B50CD, 0xBC36D4BC, 0xE28B1589, 0x0053690B, 0x2B4E6639, 0xCE919690,
+ 0x0727234D, 0xF6CDFB14, 0x1FFF2FCF, 0x0D04DC35, 0x00607E4D, 0xEEDCF04A,
+ 0xE28B1589, 0x0053690B, 0x044B50CD, 0xBC36D4BC, 0xE28B1589, 0xB967E3EC,
+ 0x044B50CD, 0xBC36D4BC, 0xE28B1589, 0x0053690B, 0x2B4E6639, 0xCE919690,
+ 0x1FFF2FCF, 0x0D04DC35, 0x00607E4D, 0xEEDCF04A, 0xFFFFFFFF, 0xDDF65B14,
+ 0xFF242597, 0x0068D9E9, 0x11ACC4F3, 0xF72C0F21, 0xFA9326BC, 0xCD506BD5,
+ 0x2B4E6639, 0xCE919690
+};
+
+const q31_t *filtering_coeffs_b_q31 = filtering_coeffs_q31 + 1;
+const q31_t *filtering_coeffs_c_q31 = filtering_coeffs_q31 + 2;
+
+//fourth coefficient MUST be zero for arm_biquad_cascade_df1_fast_q15 to work
+//every 6th coefficient after that must also be zero
+const q15_t filtering_coeffs_q15[FILTERING_MAX_NUMSTAGES * 6 + 4] =
+{
+ 0xBA37, 0xEEDA, 0x8000, 0x0000, 0x0B0B, 0xF685, 0xB967,
+ 0x1D3C, 0xFFFF, 0x0000, 0x22D3, 0xEF5C, 0x9897,
+ 0xFF24, 0x0068, 0x0000, 0xF72C, 0xFA93, 0xCD50,
+ 0x044B, 0xBC36, 0x0000, 0x0053, 0x2B4E, 0xCE91,
+ 0x0727, 0xF6CD, 0x0000, 0x0D04, 0x0060, 0xEEDC,
+ 0x2685, 0xBA37, 0x0000, 0xDDF6, 0x0000, 0x2B4E,
+ 0xFF24, 0x0068, 0x0000, 0xF72C, 0xFA93, 0xCD50,
+ 0x1D3C, 0xFFFF, 0x0000, 0x22D3, 0xEF5C, 0x9897,
+ 0x044B, 0xBC36, 0x0000, 0x0053, 0x2B4E, 0xCE91,
+ 0x0727, 0xF6CD, 0x0000, 0x0D04, 0x0060, 0xEEDC,
+ 0xE28B, 0x0053, 0x0000, 0xBC36, 0xE28B, 0xB967,
+ 0x044B, 0xBC36, 0x0000, 0x0053, 0x2B4E, 0xCE91,
+ 0x044B, 0xBC36, 0x0000, 0x0053, 0x2B4E, 0xCE91,
+ 0x0727, 0xF6CD, 0x0000, 0x0D04, 0x0060, 0xEEDC,
+ 0xE28B, 0x11AC, 0x0000,
+};
+
+const q15_t *filtering_coeffs_b_q15 = filtering_coeffs_q15 + 2;
+const q15_t *filtering_coeffs_c_q15 = filtering_coeffs_q15 + 4;
+
+const q7_t filtering_coeffs_q7[FILTERING_MAX_NUMSTAGES * 6 + 8] =
+{
+ 0xEE, 0x00, 0x80, 0x0B, 0xF6, 0xB9,
+ 0x1D, 0xFF, 0xDD, 0x22, 0xEF, 0x98,
+ 0xFF, 0x00, 0x11, 0xF7, 0xFA, 0xCD,
+ 0x04, 0xBC, 0xE2, 0x00, 0x2B, 0xCE,
+ 0x07, 0xF6, 0x1F, 0x0D, 0x00, 0xEE,
+ 0x26, 0xBA, 0x7F, 0x00, 0x80, 0x2B,
+ 0xFF, 0x00, 0x11, 0xF7, 0xFA, 0xCD,
+ 0x1D, 0xFF, 0xDD, 0x22, 0xEF, 0x98,
+ 0x04, 0xBC, 0xE2, 0x00, 0x2B, 0xCE,
+ 0x07, 0xF6, 0x1F, 0x0D, 0x00, 0xEE,
+ 0xE2, 0x00, 0x04, 0xBC, 0xE2, 0xB9,
+ 0x04, 0xBC, 0xE2, 0x00, 0x2B, 0xCE,
+ 0x07, 0xF6, 0x1F, 0x0D, 0x00, 0xEE,
+ 0x26, 0xBA, 0x7F, 0x00, 0x80, 0x2B,
+ 0x07, 0xF6, 0x1F, 0x0D, 0x00, 0xEE,
+ 0xFA, 0xCD
+};
+
+const q7_t *filtering_coeffs_b_q7 = filtering_coeffs_q7 + 4;
+const q7_t *filtering_coeffs_c_q7 = filtering_coeffs_q7 + 8;
+
+/*--------------------------------------------------------------------------------*/
+/* Tap Delay Lists */
+/*--------------------------------------------------------------------------------*/
+//const int32_t filtering_tap_delay[FILTERING_MAX_NUMTAPS] = {
+// 0xEE, 0x00, 0x10, 0x0B, 0xF6, 0xD9,
+// 0x1D, 0xFF, 0xDD, 0x1A, 0xEF, 0xE8,
+// 0xFF, 0x00, 0x11, 0xF7, 0xFA, 0xDD,
+// 0x04, 0xEC, 0xE2, 0x00, 0x2B, 0xFE,
+// 0x07, 0xF6, 0x1F, 0x0D, 0x00, 0xEE,
+// 0x20, 0xDF, 0x21
+//};
+
+const int32_t filtering_tap_delay[FILTERING_MAX_NUMTAPS] = {
+ 0x00, 0x01, 0x10, 0x0B, 0x03, 0x05,
+ 0x1D, 0x21, 0x11, 0x1A, 0x1F, 0x07,
+ 0x20, 0x01, 0x10, 0x0B, 0x03, 0x05,
+ 0x1D, 0x21, 0x11, 0x1A, 0x1F, 0x07,
+ 0x00, 0x01, 0x10, 0x0B, 0x03, 0x05,
+ 0x1D, 0x21, 0x11
+};
+
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_group.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_group.c
new file mode 100644
index 0000000..21ac7fc
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_group.c
@@ -0,0 +1,17 @@
+#include "jtest.h"
+#include "filtering_tests.h"
+
+JTEST_DEFINE_GROUP(filtering_tests)
+{
+ /*
+ To skip a test, comment it out.
+ */
+ JTEST_GROUP_CALL(biquad_tests);
+ JTEST_GROUP_CALL(conv_tests);
+ JTEST_GROUP_CALL(correlate_tests);
+ JTEST_GROUP_CALL(fir_tests);
+ JTEST_GROUP_CALL(iir_tests);
+ JTEST_GROUP_CALL(lms_tests);
+
+ return;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/fir_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/fir_tests.c
new file mode 100644
index 0000000..40e52b2
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/fir_tests.c
@@ -0,0 +1,402 @@
+#include "jtest.h"
+#include "filtering_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "filtering_templates.h"
+#include "type_abbrev.h"
+
+#define FIR_DEFINE_TEST(suffix, config_suffix, output_type) \
+ JTEST_DEFINE_TEST(arm_fir##config_suffix##_##suffix##_test, \
+ arm_fir##config_suffix##_##suffix) \
+ { \
+ arm_fir_instance_##suffix fir_inst_fut = { 0 }; \
+ arm_fir_instance_##suffix fir_inst_ref = { 0 }; \
+ \
+ TEMPLATE_DO_ARR_DESC( \
+ blocksize_idx, uint32_t, blockSize, filtering_blocksizes \
+ , \
+ TEMPLATE_DO_ARR_DESC( \
+ numtaps_idx, uint16_t, numTaps, filtering_numtaps \
+ , \
+ /* Initialize the FIR Instances */ \
+ arm_fir_init_##suffix( \
+ &fir_inst_fut, numTaps, \
+ (output_type*)filtering_coeffs_##suffix, \
+ (void *) filtering_pState, blockSize); \
+ \
+ /* Display test parameter values */ \
+ JTEST_DUMP_STRF("Block Size: %d\n" \
+ "Number of Taps: %d\n", \
+ (int)blockSize, \
+ (int)numTaps); \
+ \
+ JTEST_COUNT_CYCLES( \
+ arm_fir##config_suffix##_##suffix( \
+ &fir_inst_fut, \
+ (void *) filtering_##suffix##_inputs, \
+ (void *) filtering_output_fut, \
+ blockSize)); \
+ \
+ arm_fir_init_##suffix( \
+ &fir_inst_ref, numTaps, \
+ (output_type*)filtering_coeffs_##suffix, \
+ (void *) filtering_pState, blockSize); \
+ \
+ ref_fir##config_suffix##_##suffix( \
+ &fir_inst_ref, \
+ (void *) filtering_##suffix##_inputs, \
+ (void *) filtering_output_ref, \
+ blockSize); \
+ \
+ FILTERING_SNR_COMPARE_INTERFACE( \
+ blockSize, \
+ output_type))); \
+ \
+ return JTEST_TEST_PASSED; \
+ }
+
+#define FIR_INTERPOLATE_DEFINE_TEST(suffix, output_type) \
+ JTEST_DEFINE_TEST(arm_fir_interpolate_##suffix##_test, \
+ arm_fir_interpolate_##suffix) \
+ { \
+ arm_fir_interpolate_instance_##suffix fir_inst_fut = { 0 }; \
+ arm_fir_interpolate_instance_##suffix fir_inst_ref = { 0 }; \
+ \
+ TEMPLATE_DO_ARR_DESC( \
+ blocksize_idx, uint32_t, blockSize, filtering_blocksizes \
+ , \
+ TEMPLATE_DO_ARR_DESC( \
+ numtaps_idx, uint16_t, numTaps, filtering_numtaps2 \
+ , \
+ TEMPLATE_DO_ARR_DESC( \
+ L_idx, uint8_t, L, filtering_Ls \
+ , \
+ /* Display test parameter values */ \
+ JTEST_DUMP_STRF("Block Size: %d\n" \
+ "Number of Taps: %d\n" \
+ "Upsample factor: %d\n", \
+ (int)blockSize, \
+ (int)numTaps, \
+ (int)L); \
+ \
+ /* Initialize the FIR Instances */ \
+ arm_fir_interpolate_init_##suffix( \
+ &fir_inst_fut, L, numTaps, \
+ (output_type*)filtering_coeffs_##suffix, \
+ (void *) filtering_pState, blockSize); \
+ \
+ JTEST_COUNT_CYCLES( \
+ arm_fir_interpolate_##suffix( \
+ &fir_inst_fut, \
+ (void *) filtering_##suffix##_inputs, \
+ (void *) filtering_output_fut, \
+ blockSize)); \
+ \
+ arm_fir_interpolate_init_##suffix( \
+ &fir_inst_ref, L, numTaps, \
+ (output_type*)filtering_coeffs_##suffix, \
+ (void *) filtering_pState, blockSize); \
+ \
+ ref_fir_interpolate_##suffix( \
+ &fir_inst_ref, \
+ (void *) filtering_##suffix##_inputs, \
+ (void *) filtering_output_ref, \
+ blockSize); \
+ \
+ FILTERING_SNR_COMPARE_INTERFACE( \
+ blockSize * (uint32_t)L, \
+ output_type)))); \
+ \
+ return JTEST_TEST_PASSED; \
+ }
+
+#define FIR_DECIMATE_DEFINE_TEST(suffix, config_suffix, output_type) \
+ JTEST_DEFINE_TEST(arm_fir_decimate##config_suffix##_##suffix##_test, \
+ arm_fir_decimate##config_suffix##_##suffix) \
+ { \
+ arm_fir_decimate_instance_##suffix fir_inst_fut = { 0 }; \
+ arm_fir_decimate_instance_##suffix fir_inst_ref = { 0 }; \
+ \
+ TEMPLATE_DO_ARR_DESC( \
+ blocksize_idx, uint32_t, blockSize, filtering_blocksizes \
+ , \
+ TEMPLATE_DO_ARR_DESC( \
+ numtaps_idx, uint16_t, numTaps, filtering_numtaps \
+ , \
+ TEMPLATE_DO_ARR_DESC( \
+ M_idx, uint8_t, M, filtering_Ms \
+ , \
+ if (blockSize % M == 0) \
+ { \
+ /* Display test parameter values */ \
+ JTEST_DUMP_STRF("Block Size: %d\n" \
+ "Number of Taps: %d\n" \
+ "Decimation Factor: %d\n", \
+ (int)blockSize, \
+ (int)numTaps, \
+ (int)M); \
+ \
+ /* Initialize the FIR Instances */ \
+ arm_fir_decimate_init_##suffix( \
+ &fir_inst_fut, numTaps, M, \
+ (output_type*)filtering_coeffs_##suffix, \
+ (void *) filtering_pState, blockSize); \
+ \
+ JTEST_COUNT_CYCLES( \
+ arm_fir_decimate##config_suffix##_##suffix( \
+ &fir_inst_fut, \
+ (void *) filtering_##suffix##_inputs, \
+ (void *) filtering_output_fut, \
+ blockSize)); \
+ \
+ arm_fir_decimate_init_##suffix( \
+ &fir_inst_ref, numTaps, M, \
+ (output_type*)filtering_coeffs_##suffix, \
+ (void *) filtering_pState, blockSize); \
+ \
+ ref_fir_decimate##config_suffix##_##suffix( \
+ &fir_inst_ref, \
+ (void *) filtering_##suffix##_inputs, \
+ (void *) filtering_output_ref, \
+ blockSize); \
+ \
+ FILTERING_SNR_COMPARE_INTERFACE( \
+ blockSize / M, \
+ output_type); \
+ }))); \
+ \
+ return JTEST_TEST_PASSED; \
+ }
+
+#define FIR_LATTICE_DEFINE_TEST(suffix, output_type) \
+ JTEST_DEFINE_TEST(arm_fir_lattice_##suffix##_test, \
+ arm_fir_lattice_##suffix) \
+ { \
+ arm_fir_lattice_instance_##suffix fir_inst_fut = { 0 }; \
+ arm_fir_lattice_instance_##suffix fir_inst_ref = { 0 }; \
+ \
+ TEMPLATE_DO_ARR_DESC( \
+ blocksize_idx, uint32_t, blockSize, filtering_blocksizes \
+ , \
+ TEMPLATE_DO_ARR_DESC( \
+ numstages_idx, uint16_t, numStages, filtering_numstages \
+ , \
+ /* Display test parameter values */ \
+ JTEST_DUMP_STRF("Block Size: %d\n" \
+ "Number of Stages: %d\n", \
+ (int)blockSize, \
+ (int)numStages); \
+ \
+ /* Initialize the FIR Instances */ \
+ arm_fir_lattice_init_##suffix( \
+ &fir_inst_fut, numStages, \
+ (output_type*)filtering_coeffs_##suffix, \
+ (void *) filtering_pState); \
+ \
+ JTEST_COUNT_CYCLES( \
+ arm_fir_lattice_##suffix( \
+ &fir_inst_fut, \
+ (void *) filtering_##suffix##_inputs, \
+ (void *) filtering_output_fut, \
+ blockSize)); \
+ \
+ arm_fir_lattice_init_##suffix( \
+ &fir_inst_ref, numStages, \
+ (output_type*)filtering_coeffs_##suffix, \
+ (void *) filtering_pState); \
+ \
+ ref_fir_lattice_##suffix( \
+ &fir_inst_ref, \
+ (void *) filtering_##suffix##_inputs, \
+ (void *) filtering_output_ref, \
+ blockSize); \
+ \
+ FILTERING_SNR_COMPARE_INTERFACE( \
+ blockSize, \
+ output_type))); \
+ \
+ return JTEST_TEST_PASSED; \
+ }
+
+
+#define FIR_SPARSE_DEFINE_TEST(suffix, output_type) \
+ JTEST_DEFINE_TEST(arm_fir_sparse_##suffix##_test, \
+ arm_fir_sparse_##suffix) \
+ { \
+ arm_fir_sparse_instance_##suffix fir_inst_fut = { 0 }; \
+ arm_fir_sparse_instance_##suffix fir_inst_ref = { 0 }; \
+ \
+ TEMPLATE_DO_ARR_DESC( \
+ blocksize_idx, uint32_t, blockSize, filtering_blocksizes \
+ , \
+ TEMPLATE_DO_ARR_DESC( \
+ numtaps_idx, uint16_t, numTaps, filtering_numtaps \
+ , \
+ /* Display test parameter values */ \
+ JTEST_DUMP_STRF("Block Size: %d\n" \
+ "Number of Taps: %d\n" \
+ "Tap Delay: %d\n", \
+ (int)blockSize, \
+ (int)numTaps, \
+ (int)FILTERING_MAX_TAP_DELAY); \
+ \
+ /* Initialize the FIR Instances */ \
+ arm_fir_sparse_init_##suffix( \
+ &fir_inst_fut, numTaps, \
+ (output_type*)filtering_coeffs_##suffix, \
+ (void *) filtering_pState, \
+ (int32_t*)filtering_tap_delay, \
+ FILTERING_MAX_TAP_DELAY, blockSize); \
+ \
+ JTEST_COUNT_CYCLES( \
+ arm_fir_sparse_##suffix( \
+ &fir_inst_fut, \
+ (void *) filtering_##suffix##_inputs, \
+ (void *) filtering_output_fut, \
+ (void *) filtering_scratch, \
+ blockSize)); \
+ \
+ arm_fir_sparse_init_##suffix( \
+ &fir_inst_ref, numTaps, \
+ (output_type*)filtering_coeffs_##suffix, \
+ (void *) filtering_pState, \
+ (int32_t*)filtering_tap_delay, \
+ FILTERING_MAX_TAP_DELAY, blockSize); \
+ \
+ ref_fir_sparse_##suffix( \
+ &fir_inst_ref, \
+ (void *) filtering_##suffix##_inputs, \
+ (void *) filtering_output_ref, \
+ (void *) filtering_scratch, \
+ blockSize); \
+ \
+ FILTERING_SNR_COMPARE_INTERFACE( \
+ blockSize, \
+ output_type))); \
+ \
+ return JTEST_TEST_PASSED; \
+ }
+
+#define FIR_SPARSE2_DEFINE_TEST(suffix, output_type) \
+ JTEST_DEFINE_TEST(arm_fir_sparse_##suffix##_test, \
+ arm_fir_sparse_##suffix) \
+ { \
+ arm_fir_sparse_instance_##suffix fir_inst_fut = { 0 }; \
+ arm_fir_sparse_instance_##suffix fir_inst_ref = { 0 }; \
+ \
+ TEMPLATE_DO_ARR_DESC( \
+ blocksize_idx, uint32_t, blockSize, filtering_blocksizes \
+ , \
+ TEMPLATE_DO_ARR_DESC( \
+ numtaps_idx, uint16_t, numTaps, filtering_numtaps \
+ , \
+ /* Display test parameter values */ \
+ JTEST_DUMP_STRF("Block Size: %d\n" \
+ "Number of Taps: %d\n" \
+ "Tap Delay: %d\n", \
+ (int)blockSize, \
+ (int)numTaps, \
+ (int)FILTERING_MAX_TAP_DELAY); \
+ \
+ /* Initialize the FIR Instances */ \
+ arm_fir_sparse_init_##suffix( \
+ &fir_inst_fut, numTaps, \
+ (output_type*)filtering_coeffs_##suffix, \
+ (void *) filtering_pState, \
+ (int32_t*)filtering_tap_delay, \
+ FILTERING_MAX_TAP_DELAY, blockSize); \
+ \
+ JTEST_COUNT_CYCLES( \
+ arm_fir_sparse_##suffix( \
+ &fir_inst_fut, \
+ (void *) filtering_##suffix##_inputs, \
+ (void *) filtering_output_fut, \
+ (void *) filtering_scratch, \
+ (void *) filtering_scratch2, \
+ blockSize)); \
+ \
+ arm_fir_sparse_init_##suffix( \
+ &fir_inst_ref, numTaps, \
+ (output_type*)filtering_coeffs_##suffix, \
+ (void *) filtering_pState, \
+ (int32_t*)filtering_tap_delay, \
+ FILTERING_MAX_TAP_DELAY, blockSize); \
+ \
+ ref_fir_sparse_##suffix( \
+ &fir_inst_ref, \
+ (void *) filtering_##suffix##_inputs, \
+ (void *) filtering_output_ref, \
+ (void *) filtering_scratch, \
+ (void *) filtering_scratch2, \
+ blockSize); \
+ \
+ FILTERING_SNR_COMPARE_INTERFACE( \
+ blockSize, \
+ output_type))); \
+ \
+ return JTEST_TEST_PASSED; \
+ }
+
+FIR_DEFINE_TEST(f32,,float32_t);
+FIR_DEFINE_TEST(q31,,q31_t);
+FIR_DEFINE_TEST(q15,,q15_t);
+FIR_DEFINE_TEST(q31,_fast,q31_t);
+FIR_DEFINE_TEST(q15,_fast,q15_t);
+FIR_DEFINE_TEST(q7,,q7_t);
+
+FIR_LATTICE_DEFINE_TEST(f32,float32_t);
+FIR_LATTICE_DEFINE_TEST(q31,q31_t);
+FIR_LATTICE_DEFINE_TEST(q15,q15_t);
+
+FIR_INTERPOLATE_DEFINE_TEST(f32,float32_t);
+FIR_INTERPOLATE_DEFINE_TEST(q31,q31_t);
+FIR_INTERPOLATE_DEFINE_TEST(q15,q15_t);
+
+FIR_DECIMATE_DEFINE_TEST(f32,,float32_t);
+FIR_DECIMATE_DEFINE_TEST(q31,,q31_t);
+FIR_DECIMATE_DEFINE_TEST(q15,,q15_t);
+FIR_DECIMATE_DEFINE_TEST(q31,_fast,q31_t);
+FIR_DECIMATE_DEFINE_TEST(q15,_fast,q15_t);
+
+FIR_SPARSE_DEFINE_TEST(f32,float32_t);
+FIR_SPARSE_DEFINE_TEST(q31,q31_t);
+FIR_SPARSE2_DEFINE_TEST(q15,q15_t);
+FIR_SPARSE2_DEFINE_TEST(q7,q7_t);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(fir_tests)
+{
+ /*
+ To skip a test, comment it out.
+ */
+ JTEST_TEST_CALL(arm_fir_f32_test);
+ JTEST_TEST_CALL(arm_fir_q31_test);
+ JTEST_TEST_CALL(arm_fir_q15_test);
+ JTEST_TEST_CALL(arm_fir_q7_test);
+ JTEST_TEST_CALL(arm_fir_fast_q31_test);
+ JTEST_TEST_CALL(arm_fir_fast_q15_test);
+
+ JTEST_TEST_CALL(arm_fir_lattice_f32_test);
+ JTEST_TEST_CALL(arm_fir_lattice_q31_test);
+ JTEST_TEST_CALL(arm_fir_lattice_q15_test);
+
+ JTEST_TEST_CALL(arm_fir_interpolate_f32_test);
+ JTEST_TEST_CALL(arm_fir_interpolate_q31_test);
+ JTEST_TEST_CALL(arm_fir_interpolate_q15_test);
+
+ JTEST_TEST_CALL(arm_fir_decimate_f32_test);
+ JTEST_TEST_CALL(arm_fir_decimate_q31_test);
+ JTEST_TEST_CALL(arm_fir_decimate_q15_test);
+ JTEST_TEST_CALL(arm_fir_decimate_fast_q31_test);
+ JTEST_TEST_CALL(arm_fir_decimate_fast_q15_test);
+
+ JTEST_TEST_CALL(arm_fir_sparse_f32_test);
+ JTEST_TEST_CALL(arm_fir_sparse_q31_test);
+ JTEST_TEST_CALL(arm_fir_sparse_q15_test);
+ JTEST_TEST_CALL(arm_fir_sparse_q7_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/iir_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/iir_tests.c
new file mode 100644
index 0000000..8d31c3f
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/iir_tests.c
@@ -0,0 +1,76 @@
+#include "jtest.h"
+#include "filtering_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "filtering_templates.h"
+#include "type_abbrev.h"
+
+#define IIR_DEFINE_TEST(suffix, output_type) \
+ JTEST_DEFINE_TEST(arm_iir_lattice_##suffix##_test, \
+ arm_iir_lattice_##suffix) \
+ { \
+ arm_iir_lattice_instance_##suffix iir_inst_fut = { 0 }; \
+ arm_iir_lattice_instance_##suffix iir_inst_ref = { 0 }; \
+ \
+ TEMPLATE_DO_ARR_DESC( \
+ blocksize_idx, uint32_t, blockSize, filtering_blocksizes \
+ , \
+ TEMPLATE_DO_ARR_DESC( \
+ numstages_idx, uint16_t, numStages, filtering_numstages \
+ , \
+ /* Display test parameter values */ \
+ JTEST_DUMP_STRF("Block Size: %d\n" \
+ "Number of Stages: %d\n", \
+ (int)blockSize, \
+ (int)numStages); \
+ \
+ /* Initialize the IIR Instances */ \
+ arm_iir_lattice_init_##suffix( \
+ &iir_inst_fut, numStages, (output_type*)filtering_coeffs_b_##suffix, \
+ (output_type*)filtering_coeffs_c_##suffix, \
+ (void *) filtering_pState, blockSize); \
+ \
+ JTEST_COUNT_CYCLES( \
+ arm_iir_lattice_##suffix( \
+ &iir_inst_fut, \
+ (void *) filtering_##suffix##_inputs, \
+ (void *) filtering_output_fut, \
+ blockSize)); \
+ \
+ arm_iir_lattice_init_##suffix( \
+ &iir_inst_ref, numStages, (output_type*)filtering_coeffs_b_##suffix, \
+ (output_type*)filtering_coeffs_c_##suffix, \
+ (void *) filtering_pState, blockSize); \
+ \
+ ref_iir_lattice_##suffix( \
+ &iir_inst_ref, \
+ (void *) filtering_##suffix##_inputs, \
+ (void *) filtering_output_ref, \
+ blockSize); \
+ \
+ FILTERING_SNR_COMPARE_INTERFACE( \
+ blockSize, \
+ output_type))); \
+ \
+ return JTEST_TEST_PASSED; \
+ }
+
+IIR_DEFINE_TEST(f32, float32_t);
+IIR_DEFINE_TEST(q31, q31_t);
+IIR_DEFINE_TEST(q15, q15_t);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(iir_tests)
+{
+ /*
+ To skip a test, comment it out.
+ */
+ JTEST_TEST_CALL(arm_iir_lattice_f32_test);
+ JTEST_TEST_CALL(arm_iir_lattice_q31_test);
+ JTEST_TEST_CALL(arm_iir_lattice_q15_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/lms_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/lms_tests.c
new file mode 100644
index 0000000..06e96b6
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/lms_tests.c
@@ -0,0 +1,219 @@
+#include "jtest.h"
+#include "filtering_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "filtering_templates.h"
+#include "type_abbrev.h"
+
+static const float32_t mu_f32 = 0.00854f;//1.0f;
+static const float32_t mu2_f32 = 1.0f;
+static const q31_t mu_q31 = 0x7fffffff;
+static const q15_t mu_q15 = 0x7fff;
+
+#define LMS_DEFINE_TEST(suffix, config_suffix, output_type, mu) \
+ JTEST_DEFINE_TEST(arm_lms##config_suffix##_##suffix##_test, \
+ arm_lms##config_suffix##_##suffix) \
+ { \
+ arm_lms##config_suffix##_instance_##suffix lms_inst_fut = { 0 }; \
+ arm_lms##config_suffix##_instance_##suffix lms_inst_ref = { 0 }; \
+ arm_fir_instance_##suffix fir_inst = { 0 }; \
+ uint32_t i; \
+ \
+ TEMPLATE_DO_ARR_DESC( \
+ blocksize_idx, uint32_t, blockSize, lms_blocksizes \
+ , \
+ TEMPLATE_DO_ARR_DESC( \
+ numtaps_idx, uint16_t, numTaps, filtering_numtaps \
+ , \
+ /* Initialize the FIR Instances */ \
+ arm_fir_init_##suffix( \
+ &fir_inst, numTaps, \
+ (output_type*)filtering_coeffs_##suffix, \
+ (void *) filtering_pState, blockSize); \
+ \
+ ref_fir_##suffix( \
+ &fir_inst, \
+ (void *) filtering_##suffix##_inputs, \
+ (void *) filtering_input_lms, \
+ blockSize); \
+ \
+ for(i=0;i<numTaps;i++) \
+ { \
+ *((output_type*)filtering_coeffs_lms + i) = (output_type)0; \
+ } \
+ \
+ for(i=0;i<blockSize;i++) \
+ { \
+ /* scaled down so that lms will converge */ \
+ /* scaled down by almost the max of the abs(input) */ \
+ *((output_type*)filtering_input_lms + i) = \
+ *((output_type*)filtering_input_lms + i) / 200.0f; \
+ \
+ *((output_type*)filtering_output_f32_fut + i) = \
+ *((output_type*)filtering_##suffix##_inputs + i) / 200.0f; \
+ } \
+ \
+ /* Display test parameter values */ \
+ JTEST_DUMP_STRF("Block Size: %d\n" \
+ "Number of Taps: %d\n", \
+ (int)blockSize, \
+ (int)numTaps); \
+ \
+ /* Initialize the LMS Instances */ \
+ arm_lms##config_suffix##_init_##suffix( \
+ &lms_inst_fut, numTaps, \
+ (output_type*)filtering_coeffs_lms, \
+ (void *) filtering_pState, mu, blockSize); \
+ \
+ JTEST_COUNT_CYCLES( \
+ arm_lms##config_suffix##_##suffix( \
+ &lms_inst_fut, \
+ (void *) filtering_output_f32_fut, \
+ (void *) filtering_input_lms, \
+ (void *) filtering_output_fut, \
+ (void *) ((output_type*)filtering_output_fut+blockSize), \
+ blockSize)); \
+ \
+ for(i=0;i<numTaps;i++) \
+ { \
+ *((output_type*)filtering_coeffs_lms + i) = (output_type)0; \
+ } \
+ \
+ arm_lms##config_suffix##_init_##suffix( \
+ &lms_inst_ref, numTaps, \
+ (output_type*)filtering_coeffs_lms, \
+ (void *) filtering_pState, mu, blockSize); \
+ \
+ ref_lms##config_suffix##_##suffix( \
+ &lms_inst_ref, \
+ (void *) filtering_output_f32_fut, \
+ (void *) filtering_input_lms, \
+ (void *) filtering_output_ref, \
+ (void *) ((output_type*)filtering_output_fut+blockSize), \
+ blockSize); \
+ \
+ FILTERING_SNR_COMPARE_INTERFACE( \
+ blockSize, \
+ output_type))); \
+ \
+ return JTEST_TEST_PASSED; \
+ }
+
+#define LMS_WITH_POSTSHIFT_DEFINE_TEST(suffix, config_suffix, output_type) \
+ JTEST_DEFINE_TEST(arm_lms##config_suffix##_##suffix##_test, \
+ arm_lms##config_suffix##_##suffix) \
+ { \
+ arm_lms##config_suffix##_instance_##suffix lms_inst_fut = { 0 }; \
+ arm_lms##config_suffix##_instance_##suffix lms_inst_ref = { 0 }; \
+ arm_fir_instance_##suffix fir_inst = { 0 }; \
+ uint32_t i; \
+ \
+ TEMPLATE_DO_ARR_DESC( \
+ blocksize_idx, uint32_t, blockSize, lms_blocksizes \
+ , \
+ TEMPLATE_DO_ARR_DESC( \
+ numtaps_idx, uint16_t, numTaps, filtering_numtaps \
+ , \
+ TEMPLATE_DO_ARR_DESC( \
+ postshifts_idx, uint8_t, postShift, filtering_postshifts \
+ , \
+ /* Initialize the FIR Instances */ \
+ arm_fir_init_##suffix( \
+ &fir_inst, numTaps, \
+ (output_type*)filtering_coeffs_##suffix, \
+ (void *) filtering_pState, blockSize); \
+ \
+ ref_fir_##suffix( \
+ &fir_inst, \
+ (void *) filtering_##suffix##_inputs, \
+ (void *) filtering_input_lms, \
+ blockSize); \
+ \
+ for(i=0;i<numTaps;i++) \
+ { \
+ *((output_type*)filtering_coeffs_lms + i) = (output_type)0; \
+ } \
+ \
+ for(i=0;i<blockSize;i++) \
+ { \
+ /* scaled down so that lms will converge */ \
+ /* scaled down by log2(numTaps) bits */ \
+ *((output_type*)filtering_output_f32_fut + i) = \
+ *((output_type*)filtering_##suffix##_inputs + i) >> 6; \
+ } \
+ \
+ /* Display test parameter values */ \
+ JTEST_DUMP_STRF("Block Size: %d\n" \
+ "Number of Taps: %d\n" \
+ "Post Shift: %d\n", \
+ (int)blockSize, \
+ (int)numTaps, \
+ (int)postShift); \
+ \
+ /* Initialize the LMS Instances */ \
+ arm_lms##config_suffix##_init_##suffix( \
+ &lms_inst_fut, numTaps, \
+ (output_type*)filtering_coeffs_lms, \
+ (void *) filtering_pState, mu_##suffix, blockSize, postShift); \
+ \
+ JTEST_COUNT_CYCLES( \
+ arm_lms##config_suffix##_##suffix( \
+ &lms_inst_fut, \
+ (void *) filtering_output_f32_fut, \
+ (void *) filtering_input_lms, \
+ (void *) filtering_output_fut, \
+ (void *) ((output_type*)filtering_output_fut+blockSize), \
+ blockSize)); \
+ \
+ for(i=0;i<numTaps;i++) \
+ { \
+ *((output_type*)filtering_coeffs_lms + i) = (output_type)0; \
+ } \
+ \
+ arm_lms##config_suffix##_init_##suffix( \
+ &lms_inst_ref, numTaps, \
+ (output_type*)filtering_coeffs_lms, \
+ (void *) filtering_pState, mu_##suffix, blockSize, postShift); \
+ \
+ ref_lms##config_suffix##_##suffix( \
+ &lms_inst_ref, \
+ (void *) filtering_output_f32_fut, \
+ (void *) filtering_input_lms, \
+ (void *) filtering_output_ref, \
+ (void *) ((output_type*)filtering_output_ref+blockSize), \
+ blockSize); \
+ \
+ FILTERING_SNR_COMPARE_INTERFACE( \
+ blockSize, \
+ output_type)))); \
+ \
+ return JTEST_TEST_PASSED; \
+ }
+
+LMS_DEFINE_TEST(f32,,float32_t, mu_f32);
+LMS_WITH_POSTSHIFT_DEFINE_TEST(q31,,q31_t);
+LMS_WITH_POSTSHIFT_DEFINE_TEST(q15,,q15_t);
+
+LMS_DEFINE_TEST(f32,_norm,float32_t, mu2_f32);
+LMS_WITH_POSTSHIFT_DEFINE_TEST(q31,_norm,q31_t);
+LMS_WITH_POSTSHIFT_DEFINE_TEST(q15,_norm,q15_t);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(lms_tests)
+{
+ /*
+ To skip a test, comment it out.
+ */
+ JTEST_TEST_CALL(arm_lms_f32_test);
+ JTEST_TEST_CALL(arm_lms_q31_test);
+ JTEST_TEST_CALL(arm_lms_q15_test);
+
+ JTEST_TEST_CALL(arm_lms_norm_f32_test);
+ JTEST_TEST_CALL(arm_lms_norm_q31_test);
+ JTEST_TEST_CALL(arm_lms_norm_q15_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/intrinsics_tests/intrinsics_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/intrinsics_tests/intrinsics_tests.c
new file mode 100644
index 0000000..5e826e7
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/intrinsics_tests/intrinsics_tests.c
@@ -0,0 +1,62 @@
+#include "jtest.h"
+#include "ref.h"
+#include "arr_desc.h"
+#include "intrinsics_templates.h"
+#include "intrinsics_test_data.h"
+#include "type_abbrev.h"
+
+INTRINSICS_TEST_TEMPLATE_ELT2(__QADD8, q31);
+INTRINSICS_TEST_TEMPLATE_ELT2(__QSUB8, q31);
+INTRINSICS_TEST_TEMPLATE_ELT2(__QADD16, q31);
+INTRINSICS_TEST_TEMPLATE_ELT2(__SHADD16, q31);
+INTRINSICS_TEST_TEMPLATE_ELT2(__QSUB16, q31);
+INTRINSICS_TEST_TEMPLATE_ELT2(__SHSUB16, q31);
+INTRINSICS_TEST_TEMPLATE_ELT2(__QASX, q31);
+INTRINSICS_TEST_TEMPLATE_ELT2(__SHASX, q31);
+INTRINSICS_TEST_TEMPLATE_ELT2(__QSAX, q31);
+INTRINSICS_TEST_TEMPLATE_ELT2(__SHSAX, q31);
+INTRINSICS_TEST_TEMPLATE_ELT2(__SMUSDX, q31);
+INTRINSICS_TEST_TEMPLATE_ELT2(__SMUADX, q31);
+INTRINSICS_TEST_TEMPLATE_ELT2(__QADD, q31);
+INTRINSICS_TEST_TEMPLATE_ELT2(__QSUB, q31);
+INTRINSICS_TEST_TEMPLATE_ELT3(__SMLAD, q31);
+INTRINSICS_TEST_TEMPLATE_ELT3(__SMLADX, q31);
+INTRINSICS_TEST_TEMPLATE_ELT3(__SMLSDX, q31);
+INTRINSICS_TEST_TEMPLATE_ELT4(__SMLALD, q31, q63);
+INTRINSICS_TEST_TEMPLATE_ELT4(__SMLALDX, q31, q63);
+INTRINSICS_TEST_TEMPLATE_ELT2(__SMUAD, q31);
+INTRINSICS_TEST_TEMPLATE_ELT2(__SMUSD, q31);
+INTRINSICS_TEST_TEMPLATE_ELT1(__SXTB16, q31);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(intrinsics_tests)
+{
+ /*
+ To skip a test, comment it out.
+ */
+ JTEST_TEST_CALL(__QADD8_test);
+ JTEST_TEST_CALL(__QSUB8_test);
+ JTEST_TEST_CALL(__QADD16_test);
+ JTEST_TEST_CALL(__SHADD16_test);
+ JTEST_TEST_CALL(__QSUB16_test);
+ JTEST_TEST_CALL(__SHSUB16_test);
+ JTEST_TEST_CALL(__QASX_test);
+ JTEST_TEST_CALL(__SHASX_test);
+ JTEST_TEST_CALL(__QSAX_test);
+ JTEST_TEST_CALL(__SHSAX_test);
+ JTEST_TEST_CALL(__SMUSDX_test);
+ JTEST_TEST_CALL(__SMUADX_test);
+ JTEST_TEST_CALL(__QADD_test);
+ JTEST_TEST_CALL(__QSUB_test);
+ JTEST_TEST_CALL(__SMLAD_test);
+ JTEST_TEST_CALL(__SMLADX_test);
+ JTEST_TEST_CALL(__SMLSDX_test);
+ JTEST_TEST_CALL(__SMLALD_test);
+ JTEST_TEST_CALL(__SMLALDX_test);
+ JTEST_TEST_CALL(__SMUAD_test);
+ JTEST_TEST_CALL(__SMUSD_test);
+ JTEST_TEST_CALL(__SXTB16_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/intrinsics_tests/intrinsics_tests_common_data.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/intrinsics_tests/intrinsics_tests_common_data.c
new file mode 100644
index 0000000..621656d
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/intrinsics_tests/intrinsics_tests_common_data.c
@@ -0,0 +1,189 @@
+#include "intrinsics_test_data.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Input/Output Buffers */
+/*--------------------------------------------------------------------------------*/
+
+q63_t intrinsics_output_fut[INTRINSICS_MAX_LEN] = {0};
+q63_t intrinsics_output_ref[INTRINSICS_MAX_LEN] = {0};
+float32_t intrinsics_output_f32_fut[INTRINSICS_MAX_LEN] = {0};
+float32_t intrinsics_output_f32_ref[INTRINSICS_MAX_LEN] = {0};
+
+const q63_t intrinsics_q63_inputs[INTRINSICS_MAX_LEN] =
+{
+ 0xF7D2D6F5414A5524, 0x5297DAF44CAB5A17, 0x54129B222D6F5B56, 0x54141F6F7DAF4E3B, 0x44C414A529B226EB, 0x22D4CAB541F6F6A ,
+ 0x6053A44325CE38BF, 0x33D055403A970AFA, 0x0133D0603A44382A, 0x32513D5605540F8 , 0x03A25CE33D060524, 0x03A3A97013D56570,
+ 0x3402674117D7791D, 0x72140A667FE0438C, 0x439218E426741841, 0x11739FF340A66E54, 0x67F17D77218E4386, 0x4267FE0439FF3726,
+ 0x46C411420DC177CA, 0x7156C147702F2CF5, 0x26615F6441142FF1, 0x20D662C46C1476AB, 0x7700DC1715F640DD, 0x441702F2662C4E49,
+ 0x50D4F8B538055E7E, 0x5570D192770871FE, 0x725576474F8B5360, 0x538258550D1928A0, 0x2773805557647821, 0x74F77087258558CF,
+ 0x05066D230C0C604D, 0x63650FA350A46C19, 0x66C3646266D2370D, 0x30C6CE0050FA359A, 0x3500C0C636462E24, 0x26650A466CE00F5C,
+ 0x21E3B72166D40948, 0x0731EB61355B5831, 0x577733943B72150A, 0x166773F21EB61530, 0x13566D4073394127, 0x43B355B5773F26F4,
+ 0x7221CF5118052980, 0x27A22AD1038D6587, 0x67C7A8121CF517F4, 0x1187CDC722AD1691, 0x103180527A812473, 0x21C038D67CDC7D7F,
+ 0x21A0FD604A5110D0, 0x1201A2156D895BB9, 0x53D20EB60FD60F35, 0x04A3DE621A215530, 0x56D4A51120EB6DDA, 0x60F6D8953DE62516,
+ 0x02C61E17250123E1, 0x26D2CBB35ED813C8, 0x15B6D35061E175B1, 0x7255B1402CBB32F3, 0x35E250126D350907, 0x0615ED815B140D7E,
+ 0x126418B76EAE272D, 0x23C26BB13E221841, 0x1243CF01418B7B88, 0x76E24DB126BB1B80, 0x13E6EAE23CF010E4, 0x1413E22124DB166C,
+ 0x1634700479AB7E42, 0x74163F5662DF28D1, 0x246419E047004665, 0x47946BE163F56FC6, 0x66279AB7419E0C75, 0x04762DF246BE1F38,
+ 0x63F5CE12243239B2, 0x31F3F574758D03E0, 0x0711F4455CE12926, 0x22471D563F574B74, 0x475243231F4458E2, 0x55C758D071D5639 ,
+ 0x34806EF703A17B49, 0x77D48D32173A7C76, 0x70F7D3E306EF7531, 0x7030F2F348D32F34, 0x21703A177D3E3063, 0x306173A70F2F3549,
+ 0x54426F835C314C9 , 0x42E447B118CB6B6D, 0x6502E32326F83697, 0x35C50745447B1E9C, 0x1185C3142E323A33, 0x32618CB650745715,
+ 0x51D4891001AC5746, 0x5601DA36655A4E04, 0x42060E624891060F, 0x00120BF51DA36B4F, 0x66501AC560E6227F, 0x248655A420BF5EB4,
+ 0x1154156550B3225B, 0x2181540540C10544, 0x02318586415656C , 0x550236A115405EAE, 0x54050B32185863E1, 0x64140C10236A1C4E,
+ 0x44E7736608BD21F9, 0x2614EDF52ACF7A68, 0x752617A1773665E5, 0x608524F44EDF5F66, 0x52A08BD2617A1610, 0x1772ACF7524F4968,
+ 0x06A24DC242D006CD, 0x0376A4F55F000079, 0x01D3706424DC2447, 0x2421DE706A4F5599, 0x55F42D0037064D4A, 0x4245F0001DE70608,
+ 0x44018061233A2EE5, 0x22440795137E488E, 0x44424A8118061B7B, 0x12344CE44079569D, 0x513233A224A817D5, 0x118137E444CE48F5,
+ 0x41D71AD7575F7883, 0x73C1D4A522406802, 0x6333CBC771AD70BB, 0x757335841D4A5D79, 0x522575F73CBC7CE4, 0x77122406335840D8,
+ 0x3333D19605792E47, 0x233331A427AD2C05, 0x213330353D196EAB, 0x60513D93331A40AF, 0x4270579233035831, 0x53D27AD213D93987,
+ 0x0135DC437C542094, 0x25C13796045F317E, 0x37D5C2015DC43F8B, 0x37C7DD501379650C, 0x6047C5425C20193F, 0x15D045F37DD50298,
+ 0x5275C8A71D482B82, 0x210272914A6B6062, 0x63510E165C8A757B, 0x71D355A5272917C1, 0x14A1D48210E16FBC, 0x65C4A6B6355A5882,
+ 0x1757DF7F66F86A35, 0x61A758A6604555A1, 0x5531A1137DF7FBB , 0xF6653541758A6216, 0x66066F861A113463, 0x37D6045553541BAD,
+ 0x04E1F05221576756, 0x6554EA63483B6D8D, 0x67B55B841F052FCC, 0x2217B2E04EA63DFB, 0x3482157655B84677, 0x41F483B67B2E04F2,
+ 0x41D46029787A796C, 0x71A1DB2204A12CD3, 0x2061A8C746029BD , 0x978061E41DB22DD8, 0x204787A71A8C7F28, 0x74604A12061E452E,
+ 0x66B73357132D3F78, 0x3626BBB076525852, 0x53F6253673357BBA, 0x7133F6B66BBB0A58, 0x076132D362536AFA, 0x673765253F6B65EF,
+ 0x55F66B026DC57B58, 0x7325FF601EB718CE, 0x17F3247766B02740, 0x26D7FF355FF60B47, 0x01E6DC5732477B8F, 0x7661EB717FF35302,
+ 0x7206FF9529FD3E40, 0x34720182475A43D1, 0x44C47E076FF9528A, 0x5294CF572018209D, 0x24729FD347E079C9, 0x76F475A44CF576D3,
+ 0x2512340428074E34, 0x42551CE35D6F58ED, 0x56425297234045D1, 0x4286443251CE35F9, 0x35D2807425297896, 0x7235D6F5644320FE,
+ 0x04E701D50F4449A9, 0x4714E09454C361C6, 0x661718F0701D52F1, 0x50F615404E094820, 0x4540F444718F0810, 0x07054C3661540689,
+ 0x46A48AC379DE5A1F, 0x5216A0C152865C23, 0x57021B7048AC3A4B, 0x379708646A0C1BE0, 0x15279DE521B705DB, 0x048528657086465D,
+ 0x7206D2311CC10929, 0x038204951E1D716E, 0x71438FF16D231D4C, 0x11C149C720495108, 0x51E1CC1038FF1971, 0x16D1E1D7149C78D4,
+ 0x62169C32441F1E8B, 0x147210B743D95372, 0x5024781569C324B4, 0x24402476210B7DC9, 0x743441F147815E78, 0x56943D9502476137,
+ 0x30E2F6846163DDF , 0xD020E680390D6EC2, 0x612022322F684E5B, 0x461125930E680ABD, 0x0396163D02232615, 0x22F390D612593380,
+ 0x76D130F57B1465FE, 0x6106D772065A6957, 0x66310E91130F53EB, 0x57B63BC76D772EF7, 0x2067B14610E916B6, 0x113065A663BC7A68,
+ 0x773194712ACB00BB, 0x05973090651C5590, 0x53459BB6194714B5, 0x12A34867730904EE, 0x0652ACB059BB61B4, 0x619651C534867DBC,
+ 0x21228931391C706C, 0x713129A63C164218, 0x4621317128931CD0, 0x13962882129A66AB, 0x63C391C713171F4D, 0x1283C16462882872,
+ 0x6547A7944B167FD4, 0x73054B1566902F4C, 0x239308567A794932, 0x44B3946654B152C , 0x5664B16730856EA9, 0x67A6690239466D55,
+ 0x651077A336696451, 0x63651B950F5B1E8C, 0x11D367E2077A3C6A, 0x3361D2C651B956B4, 0x50F36696367E2D2A, 0x2070F5B11D2C662A,
+ 0x24D4070678FB6880, 0x6204DF964E6D40B6, 0x4632030640706FDC, 0x678638124DF9679C, 0x64E78FB620306EDB, 0x6404E6D463812AE7,
+ 0x2043E036255D2748, 0x25504E441B8B617B, 0x66655A373E036FAD, 0x625669B204E444A7, 0x41B255D255A37517, 0x73E1B8B6669B2988,
+ 0x27634BB318FD5E8C, 0x5057699467BD05CE, 0x06D05B9534BB346C, 0x3186DFA276994800, 0x46718FD505B958B6, 0x53467BD06DFA2FEF,
+ 0x573727212055B5C , 0xB5F73EF61F843C4C, 0x3435FB9072721B52, 0x1204323573EF6B86, 0x61F2055B5FB90B61, 0x0721F84343235DAC,
+ 0x17B162F231D424B4, 0x2797B2A7768C0D7E, 0x04479392162F2F9D, 0x231442D17B2A7A99, 0x77631D4279392693, 0x216768C0442D12C0,
+ 0x1445D9560692273E, 0x20D44E7359A16E80, 0x65F0D8745D956856, 0x6065F5C144E73DAC, 0x359069220D874532, 0x45D59A165F5C1DD0,
+ 0x3591D8215D167858, 0x7595965405597EA2, 0x71A594C01D821476, 0x15D1A87359654ED2, 0x4055D167594C0DC7, 0x01D055971A873506,
+ 0xD1F20CC33F693200, 0x3781F9E67A651AB5, 0x12A78E7620CC3C8A, 0x33F2A01D1F9E662C, 0x67A3F69378E7631 , 0x6207A6512A01DA0 ,
+ 0x073360D43088472F, 0x40D7333712EE0D42, 0x0230D634360D4D5F, 0x430233A073337E48, 0x712308840D634C06, 0x43612EE0233A0ACB,
+ 0x13E26223706651ED, 0x5223EBB67AA54079, 0x432225A4262239D1, 0x370325813EBB6BB6, 0x67A70665225A4F3D, 0x4267AA5432581A06,
+ 0x51075ED16E6F5780, 0x53C10DF2577377C7, 0x7373C79275ED1DDC, 0x16E3717510DF2D15, 0x2576E6F53C7929BC, 0x2755773737175917,
+ 0x47376435354E381C, 0x35273BB7762A2DD7, 0x26C52FE476435AC1, 0x5356C81473BB749E, 0x776354E352FE4E7E, 0x476762A26C8140F4,
+ 0x1374742257694875, 0x4123792612D30822, 0x020121C7474227CF, 0x257204E137926D98, 0x61257694121C7E24, 0x74712D30204E1EE7,
+ 0x77A316C358C6268 , 0x2617AB142152080 , 0x07D61C13316C3323, 0x3587D8E77AB14A31, 0x42158C6261C13C03, 0x331215207D8E74F1,
+ 0x5673BFD773F446D0, 0x43E672426C6C6A0A, 0x60F3E5523BFD79FB, 0x7730FF5567242969, 0x26C73F443E5524EB, 0x23B6C6C60FF5534 ,
+ 0x779540F452F05F1C, 0x5417984617102DE3, 0x21941954540F4A21, 0x452193F7798468E7, 0x61752F05419545EB, 0x45417102193F7880,
+ 0x5404BF662B246B20, 0x64C40894408A2BC4, 0x2244CAA64BF66A49, 0x62B2478540894C55, 0x4402B2464CAA6398, 0x64B408A2247856E9,
+ 0x55070D372F2A647D, 0x6595063422F55D33, 0x52B5983670D37915, 0x72F2BCC550634C72, 0x4222F2A65983671 , 0x67022F552BCC5AF8,
+ 0x03A710741A77D48 , 0xD613A6B3411B5CFA, 0x5626142571074D7E, 0x41A627103A6B3593, 0x3411A77D61425F05, 0x571411B56271012A,
+ 0x32310A505B830310, 0x021239F73D8418CA, 0x17F213D510A50792, 0x05B7F993239F7137, 0x73D5B830213D5071, 0x5103D8417F9930D4,
+ 0x265291502462664F, 0x6146586354180F8E, 0x018144B2291505BA, 0x02418E426586387A, 0x35424626144B2C12, 0x2295418018E425C7,
+ 0x558194623AA43373, 0x37258B4518F0503C, 0x5267247319462AC0, 0x23A26BF558B452EF, 0x5183AA4372473895, 0x31918F0526BF5435,
+ 0x13D5C3376DA553B , 0x54D3D93C60912FA6, 0x2204D0355C337331, 0x76D206913D93CD7 , 0xC606DA554D035752, 0x55C6091220691929,
+ 0x25F758B6389962F9, 0x6595FCA636E701E9, 0x02D59602758B642C, 0x6382D5A25FCA69E3, 0x63638996596027F4, 0x27536E702D5A2FD0,
+ 0x01B76BA35F18324A, 0x33C1BC213DB165AA, 0x6733CC1076BA3876, 0x35F73A601BC21AF6, 0x13D5F1833CC10841, 0x0763DB1673A60174,
+ 0x66144586625B7F58, 0x72B6157367C57724, 0x7032B3704458653C, 0x66203DF661573095, 0x367625B72B370837, 0x04467C5703DF6CE3,
+ 0x260191B45D086EFA, 0x630608433F5227C2, 0x21030DE1191B4785, 0x45D105E260843D82, 0x33F5D08630DE11F1, 0x1193F522105E226C,
+ 0x23B366766E1C7AA2, 0x7733B8D447AA5D14, 0x5407372636676D03, 0x66E409523B8D4DF6, 0x4476E1C77372694 , 0x63647AA5409521DC,
+ 0x5632BE46744206A , 0x04A63E114722023F, 0x05C4A4A02BE46AD5, 0x6745CF2563E11D76, 0x147744204A4A09AB, 0x02B472205CF252B9,
+ 0x62D3203731586916, 0x6452D7324DFD7D84, 0x72E4524532037634, 0x7312E5362D7329D4, 0x24D315864524582F, 0x5324DFD72E5366C1,
+ 0x50A6A2543B0E019B, 0x0110A6A038530C6A, 0x054119726A2542D , 0x43B540650A6A00E5, 0x0383B0E0119725CC, 0x26A3853054065347,
+ 0x571181111B6F7AF1, 0x774716746CCF71F1, 0x77774F43181117F2, 0x11B77A5571674A76, 0x46C1B6F774F43880, 0x3186CCF777A55F47,
+ 0x0243CBB259EA5B62, 0x547245C44A331D95, 0x1074718D3CBB276F, 0x25907CE0245C4D50, 0x44A59EA54718D5 , 0xD3C4A33107CE05D1,
+ 0x6663006160D47AD5, 0x73D669B325CA1C40, 0x1193D5F130061766, 0x16019306669B39DF, 0x32560D473D5F1320, 0x13025CA119306AD3,
+ 0x12D6A6E628B30325, 0x02B2DF160DD090F , 0x9312B5146A6E6F37, 0x628311012DF16F66, 0x60D28B302B514C7E, 0x46A0DD0931101C58,
+ 0x14177AB07D4847FC, 0x43A41320515341CA, 0x4243AF8577AB0EA6, 0x07D24B3141320DAF, 0x0517D4843AF8531E, 0x5775153424B31611,
+ 0x072222516D377331, 0x73B722D17A832A22, 0x2263B194222511C7, 0x16D261B0722D1F89, 0x17A6D3773B194F18, 0x4227A832261B0A4D,
+ 0x620190F243F676DB, 0x756202E74F8C6D61, 0x630560D4190F2250, 0x243308E6202E72A9, 0x74F43F67560D4EA2, 0x4194F8C6308E67B4,
+ 0x17F27EB236746663, 0x6267FDE017CC3852, 0x3232647127EB2EAC, 0x236232617FDE0AA8, 0x01736746264719A , 0x12717CC323261EDD,
+ 0x42448D823C0B339E, 0x34324D4406284D40, 0x44B4363148D82ECB, 0x23C4BF0424D44CF8, 0x4063C0B343631B91, 0x148062844BF04248,
+ 0x320630B736497B9B, 0x76C20CC368273C58, 0x3576C3B7630B7AF9, 0x7365744320CC3F26, 0x368364976C3B7B71, 0x76368273574433ED,
+ 0x626565B07A2552F6, 0x56726F924CDE642D, 0x65B67A20565B0142, 0x07A5B50626F9207F, 0x24C7A25567A207BE, 0x0564CDE65B506684,
+ 0x1411561044DA4780, 0x46E4155611756A0C, 0x61D6E3A6156104AF, 0x0441DBA1415561B0, 0x61144DA46E3A6886, 0x615117561DBA1EA2,
+ 0x71D758F0542359C8, 0x52D1DD634C024E22, 0x4612D194758F052A, 0x054616471DD6395 , 0x34C542352D194BAD, 0x4754C024616475A1,
+ 0x35713CB542084602, 0x46057FE209C274AD, 0x716607A413CB5562, 0x5421672357FE2D5B, 0x20942084607A4EE5, 0x41309C2716723A91,
+ 0x73D28FE64F624CCF, 0x4323DDA62E5E24A3, 0x21932AF528FE6FAF, 0x64F19A573DDA6EF4, 0x62E4F62432AF540C, 0x5282E5E219A57B3B,
+ 0x353278445D1D73A3, 0x7425397123424B3E, 0x452427D7278445F5, 0x45D5221353971C3B, 0x1235D1D7427D7943, 0x727234245221358C,
+ 0x7603B86626CE1A5E, 0x145608317B506CA4, 0x62145E143B86636E, 0x62621B7760831F6D, 0x17B26CE145E142F3, 0x43B7B50621B77B04,
+ 0x43B7D8D17BB65E0C, 0x52D3BF3378B80F5E, 0x02B2D5727D8D172B, 0x17B2B5B43BF33A90, 0x3787BB652D572D9 , 0x27D78B802B5B4920,
+ 0x11C47C6436A05E01, 0x5301CAA652745306, 0x54D304A247C64855, 0x4364D6B11CAA669B, 0x65236A05304A2641, 0x247527454D6B1760,
+ 0x54B24A673E176D79, 0x64E4BDE7523241B0, 0x44C4E5F124A67957, 0x73E4C2154BDE76AF, 0x7523E1764E5F1493, 0x124523244C215DA5,
+ 0x53940AE633A052B , 0x569390D11A4D00C2, 0x05A69E8640AE6BCA, 0x6335AF35390D106B, 0x11A33A0569E86018, 0x6401A4D05AF356CF,
+ 0x10D14B6263561D4 , 0x14C0D2E244F31C6 , 0x1454CBF114B6299B, 0x26345AC10D2E25F0, 0x244635614CBF132A, 0x11444F3145AC18B6,
+ 0x222263442227567D, 0x52422C5106B54E2F, 0x46C2442326344534, 0x4226C37222C515EC, 0x106222752442370D, 0x32606B546C3721C6,
+ 0x6606AF3634EF687D, 0x66A603961C06323A, 0x3496AE706AF36A60, 0x63449D0660396F52, 0x61C34EF66AE70AA1, 0x06A1C06349D06CBC,
+ 0x1663A9A26F9576C8, 0x71D66DF0584C4258, 0x4571D4803A9A27BB, 0x26F57DD166DF0D47, 0x0586F9571D4804EA, 0x03A584C457DD1E67,
+ 0x66225C12789C7895, 0x74F6274275336111, 0x63F4FBF625C122C8, 0x2783F9F662742114, 0x275789C74FBF6D26, 0x625753363F9F6482,
+ 0x77E499E266F02CD9, 0x2447EBC111083202, 0x34944011499E2618, 0x26649DF77EBC1351, 0x11166F02440112F1, 0x1491108349DF7BC1,
+ 0x16B61AF13BF45C25, 0x52D6B1F731BA7FA0, 0x7632D86561AF1AED, 0x13B63E016B1F7D29, 0x7313BF452D865294, 0x56131BA763E01129,
+ 0x2081FE3A7E9E77A5, 0x77208597100435D7, 0x331722841FE3A71 , 0xA7E31C5208597C81, 0x7107E9E7722849FA, 0x41F1004331C520AF,
+ 0x1155CA077BA178DC, 0x702150E67F102D31, 0x25D02C345CA07864, 0x77B5D041150E6F98, 0x67F7BA1702C34882, 0x45C7F1025D041F11,
+ 0x355426F30C613C57, 0x37A5599253984FD1, 0x42B7AFA0426F38AD, 0x30C2B25355992B1D, 0x2530C6137AFA078D, 0x042539842B253413,
+ 0x51A28933594B32CF, 0x3291A0B432887E38, 0x765291B428933B46, 0x359653A51A0B4168, 0x432594B3291B4A94, 0x42832887653A5E8D,
+ 0x65030DA421746BBE, 0x63450C565EFE6415, 0x6523471130DA429C, 0x421529C650C5640C, 0x65E2174634711AA4, 0x1305EFE6529C67A6,
+ 0x42803CA0105957CD, 0x525283854D287499, 0x74225A0403CA0AA7, 0x010420D428385832, 0x54D1059525A04A02, 0x4034D287420D47A4,
+ 0x72759E2135627556, 0x74527E834BC11E4C, 0x1224586159E215C7, 0x1352282727E838B4, 0x34B35627458612F4, 0x1594BC1122827F6F,
+ 0x64F4E495449D4DBA, 0x4394FD27679B7362, 0x737395E74E495845, 0x544375A64FD270D1, 0x767449D4395E76A0, 0x74E679B7375A655E,
+ 0x05161EF712E2058F, 0x06751FF573F970CA, 0x77F6741061EF73B3, 0x7127FDA051FF5362, 0x57312E2067410345, 0x06173F977FDA0B3B,
+ 0x14B26557221962E8, 0x6264B30017AB6543, 0x67E268E126557412, 0x7227E0D14B30084D, 0x01722196268E191D, 0x12617AB67E0D13DF,
+ 0x65677FA773EF127D, 0x112560024DEC5DB1, 0x51512DD077FA745F, 0x773157F656002898, 0x24D73EF112DD0A40, 0x0774DEC5157F6DDF,
+ 0x3337B63042A55F8E, 0x532338B643597924, 0x74F329457B630C3F, 0x0424FA23338B6B58, 0x64342A5532945F75, 0x57B435974FA23A0E,
+ 0x02406114036E38C0, 0x3192466033B18FD , 0x81219BB006114337, 0x403124C024660ACB, 0x033036E319BB02F0, 0x00633B18124C0A47,
+ 0x5360C6123A951701, 0x1513607401155ABF, 0x563516600C612D71, 0x23A635F536074CA7, 0x4013A95151660C41, 0x00C01155635F58C7,
+ 0x50165B077FC2002D, 0x079015F60E6A7CF3, 0x76E791B765B07D07, 0x77F6E475015F6A6B, 0x60E7FC20791B70DD, 0x7650E6A76E475719,
+ 0x74671942424314C7, 0x167464A268426EB , 0x66B6775771942FEE, 0x2426BA77464A2F52, 0x26842431677579FD, 0x771684266BA775AE,
+ 0x31D78D951F66EFF , 0xE3B1D0B31A795237, 0x52F3BD3478D9545F, 0x51F2F8531D0B344D, 0x31A1F66E3BD34AB7, 0x4781A7952F85312A,
+ 0x20208DF316C542AD, 0x46D028113990185D, 0x1406D35108DF3351, 0x3164066202811AA5, 0x13916C546D351F41, 0x108399014066269D,
+ 0x1355DD7006B660BF, 0x66835D746EDB4768, 0x411689E25DD70CF0, 0x0061143135D74F6E, 0x46E06B66689E220C, 0x25D6EDB411431687,
+ 0x01D302F0147C49C9, 0x4481DAB6385762BD, 0x63748325302F0AE4, 0x01437D501DAB67F8, 0x638147C4483256C9, 0x5303857637D50FCB,
+ 0x15819DB74EA82711, 0x26A58DE04D7B2C98, 0x2376AFF719DB78BC, 0x74E3762158DE0DC2, 0x04D4EA826AFF7E7B, 0x7194D7B237621C93,
+ 0x32E7F884792C6E19, 0x66C2E19677001192, 0x16A6C7137F88439D, 0x4796AF432E196A66, 0x677792C66C71378C, 0x37F770016AF43B3A,
+ 0x06D4BEE17C16225E, 0x2346D5B56687337 , 0x368345D44BEE1608, 0x17C681206D5B5552, 0x5667C162345D4590, 0x44B66873681209CC,
+ 0x11F198807B242819, 0x2241FC72508A1416, 0x16A24BD019880FE3, 0x07B6A1D11FC7288A, 0x2507B24224BD0502, 0x019508A16A1D1678,
+ 0x45E5ADE120E6CA0 , 0xC7A5EA8659BE2057, 0x2117A2005ADE11EB, 0x120114945EA8649D, 0x65920E6C7A200E6F, 0x05A59BE21149481D,
+ 0x5636731272281E93, 0x15263B840A5B0451, 0x07C5221767312D58, 0x2727CDF563B849F1, 0x40A7228152217960, 0x7670A5B07CDF59F3,
+ 0x5347DF1533C775C0, 0x73834E961EBA0799, 0x05E38FC77DF1506 , 0x5335EA0534E96110, 0x61E33C7738FC73E3, 0x77D1EBA05EA059B2,
+ 0x16C43911022936EA, 0x31C6C0D1316406F6, 0x0381C6F343911185, 0x10238DB16C0D10F3, 0x131022931C6F3DF8, 0x3433164038DB12A9,
+ 0x5775F4A35CD41244, 0x14C77CE12C9F0A7B, 0x0314C8005F4A315F, 0x35C318D577CE1C66, 0x12C5CD414C800860, 0x05F2C9F0318D53E0,
+ 0x421750817105420D, 0x420217E4575361F2, 0x64D20101750810BA, 0x1714D884217E4CA5, 0x457710542010140 , 0x175575364D884763,
+ 0x008141C642BB0DA7, 0x046087F532D53A74, 0x32D464B5141C6CD4, 0x6422D2A0087F5FC3, 0x53242BB0464B53 , 0x51432D532D2A05F6,
+ 0x5223EB9215532B45, 0x21F221465D5C3CE1, 0x3111FC523EB9216A, 0x21511AE52214611B, 0x65D155321FC52C5F, 0x23E5D5C311AE5DD7,
+ 0x46D7400020B925A9, 0x2386D0E07C640AF4, 0x00938E6A740009AC, 0x020091046D0E0321, 0x07C20B9238E6A61 , 0xA747C64009104544,
+ 0x666341A6474F26C8, 0x2596619015254CF3, 0x424598B2341A6B59, 0x64724126661904CE, 0x015474F2598B2197, 0x234152542412659D,
+ 0x13008FD161976DD4, 0x63430400329B3E16, 0x3553456308FD1FB0, 0x16155CC1304006F3, 0x032619763456309 , 0x308329B355CC15F1,
+ 0x0350036D59DA7630, 0x729353775C801335, 0x175299470036D52 , 0xD5975280353775A5, 0x75C59DA7299476EB, 0x7005C80175280568,
+ 0x37F64761766F5264, 0x51B7FB302EA233A6, 0x3361BC03647619F3, 0x17636BC37FB30C7A, 0x02E766F51BC03B9 , 0x3642EA2336BC3061,
+ 0x7640AC043F30596E, 0x51E641973E2A527B, 0x5211ECC30AC04220, 0x43F21447641979A3, 0x73E3F3051ECC3B89, 0x30A3E2A521447BC1,
+ 0x157299E54E8F2E26, 0x21D57C940C5A1D90, 0x1761D486299E5467, 0x54E76F3157C947E3, 0x40C4E8F21D4865ED, 0x6290C5A176F31C3D,
+ 0x05C6FFB34EE81CDF, 0x1305C8233479195E, 0x147300F76FFB3AE1, 0x34E479405C82398 , 0x3344EE81300F7364, 0x76F3479147940AFA,
+ 0xF3A224A33B853E3E, 0x3223A674598C440D, 0x42E22880224A3D89, 0x33B2E77F3A674204, 0x4593B85322880A38, 0x022598C42E77F2D ,
+ 0x6091FE9022841C9C, 0x12D093354F0609C3, 0x07E2D6B61FE90922, 0x0227EDB609335017, 0x54F228412D6B69A7, 0x61F4F0607EDB63F9,
+ 0xE2524BE1099A74EF, 0x716251D21F9F1B40, 0x12816AC524BE17E8, 0x10928D7E251D2F7A, 0x21F099A716AC50D3, 0x5241F9F128D7ED6 ,
+ 0x36430DF66D193443, 0x36364FF676156F1B, 0x67463DB230DF6A4E, 0x66D7435364FF6794, 0x6766D19363DB2C9A, 0x2307615674353022,
+ 0x16742501556E025C, 0x070675A123802AF9, 0x27F70B22425018A4, 0x1557FB01675A18BB, 0x123556E070B227B9, 0x242238027FB01BF ,
+ 0x14F6574563E7910 , 0x9524F6E36C661591, 0x11E52B3265745D2B, 0x5631E6A14F6E379D, 0x36C63E7952B32FAC, 0x2656C6611E6A1101,
+ 0x34B469701DE22385, 0x2544BAB42338191F, 0x17854EB4469704B6, 0x01D783934BAB4599, 0x4231DE2254EB4809, 0x4462338178393E6D,
+ 0x02D288D5550017DD, 0x1202D52639B120E1, 0x24E20D22288D52D3, 0x5554E1202D52668C, 0x6395500120D22A68, 0x22839B124E1207D1,
+ 0x734251773FCC0EFE, 0x05A34BF547F37E64, 0x76F5A8D325177A90, 0x73F6F72734BF5D4D, 0x5473FCC05A8D3DCE, 0x32547F376F7275A8,
+ 0x70A64DB56BEA2655, 0x22C0A4D42A1810FC, 0x1712C40264DB593A, 0x56B71C070A4D4BC0, 0x42A6BEA22C402E93, 0x2642A18171C077F9,
+ 0x458752F16F0C4577, 0x42C582E370412414, 0x24D2C455752F1DC1, 0x16F4DCD4582E38EA, 0x3706F0C42C455F7B, 0x575704124DCD4EDB,
+ 0x53D4FCA112BC2696, 0x2503D5E77B037135, 0x736502F44FCA1F8C, 0x112361653D5E75F6, 0x77B12BC2502F41B0, 0x44F7B037361653F1,
+ 0x64657E702E5B0E31, 0x047467B320266B19, 0x61F4703257E703D7, 0x02E1F776467B3E00, 0x3202E5B047032BA3, 0x257202661F776B9C,
+ 0x07D1BD5062570A84, 0x07F7D0A27EC75B48, 0x5297FCC21BD5012 , 0x062291307D0A2D5D, 0x27E625707FCC29F2, 0x21B7EC75291304B6,
+ 0xE3A7D12719D558ED, 0x55F3ADE047551C8 , 0x1255F7417D12738F, 0x71925D2E3ADE0892, 0x04719D555F741997, 0x17D4755125D2E2F ,
+ 0x65415E922B9F2269, 0x227544375C134FED, 0x456272D315E92399, 0x22B5618654437F4E, 0x75C2B9F2272D32AB, 0x3155C13456186AA1,
+ 0x8462A8717E4D355C, 0x32C4637A234D7836, 0x75F2C1832A871760, 0x17E5FC784637A94 , 0xA237E4D32C183207, 0x32A234D75FC78B3 ,
+ 0x34E6C9F47F10621E, 0x6624E3F1276966B2, 0x62562BA26C9F4A11, 0x47F25F234E3F182C, 0x1277F10662BA2EF5, 0x26C2769625F239CD,
+ 0x63F0AC1573D63FED, 0x3733F3D3636E1F5E, 0x135738320AC15A0E, 0x57335C363F3D33EB, 0x36373D63738326EA, 0x20A636E135C366B1,
+ 0x642711A14D476E86, 0x67E426A402F63208, 0x3757E4D1711A1FC1, 0x14D75E46426A4396, 0x4024D4767E4D1B93, 0x17102F6375E46DB7,
+ 0x60A7AD242F3C44A7, 0x4490A56351A56F5C, 0x64C499527AD2463D, 0x42F4C4B60A5639CA, 0x3512F3C449952C78, 0x27A51A564C4B64F6,
+ 0x14B438673AFE7F8D, 0x7554BC1466993D04, 0x36855A8743867F37, 0x73A681A14BC146C2, 0x4663AFE755A875EC, 0x74366993681A1A75,
+ 0x61820F7730A67E1B, 0x773189184A4A7D0C, 0x7547389720F77993, 0x730542661891805 , 0x84A30A67738976AD, 0x7204A4A7542667D6,
+ 0x6442BF173C5C6EBF, 0x668447C34499187F, 0x17A68D842BF17C97, 0x73C7AAB6447C317F, 0x3443C5C668D8419C, 0x42B449917AAB6456,
+ 0x43D09163421B4F29, 0x41A3D72A76740F9C, 0x0751AD5409163B8D, 0x342754943D72AAB , 0xA76421B41AD54DD7, 0x40976740754946EE,
+ 0x654105637317342B, 0x30C54BB4218546D4, 0x45D0CE6310563DA7, 0x3735D14654BB4CCE, 0x421731730CE63E46, 0x310218545D146234,
+ 0x40709D7233BE6C63, 0x63607C36325044E5, 0x42D3655309D72335, 0x2332DFA407C36BA , 0x63233BE6365530CC, 0x309325042DFA448C,
+ 0x312150271663516F, 0x53C1253259B00AA , 0x0493CEF0150274EA, 0x716492F312532D4A, 0x259166353CEF002D, 0x01559B00492F3DA5,
+ 0x72F14A10263A2574, 0x2682F6276F8005C2, 0x0266829314A10651, 0x026269872F627ABA, 0x76F263A268293238, 0x3146F80026987646,
+ 0x12B59B1552590516, 0x0532B2A410144D36, 0x4275395359B151B9, 0x552278512B2A4F05, 0x4105259053953699, 0x3591014427851C75,
+ 0xF4F32843180646F3, 0x54718F4F2E970306, 0x6623953632843145, 0x318D315E18F4FE8F
+};
+
+/* The source data is random across the q63_t range. Accessing it by word should
+ remain random. */
+const q31_t * intrinsics_q31_inputs = (q31_t *) intrinsics_q63_inputs;
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/main.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/main.c
new file mode 100644
index 0000000..1f07b8b
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/main.c
@@ -0,0 +1,27 @@
+#include "jtest.h"
+#include "all_tests.h"
+#include "arm_math.h"
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+asm(" .global __ARM_use_no_argv\n");
+#endif
+
+
+void debug_init(void)
+{
+ uint32_t * SHCSR_ptr = (uint32_t *) 0xE000ED24; /* System Handler Control and State Register */
+ *SHCSR_ptr |= 0x70000; /* Enable UsageFault, BusFault, and MemManage fault*/
+}
+
+int main(void)
+{
+ debug_init();
+
+ JTEST_INIT(); /* Initialize test framework. */
+
+ JTEST_GROUP_CALL(all_tests); /* Run all tests. */
+
+ JTEST_ACT_EXIT_FW(); /* Exit test framework. */
+ while (1); /* Never return. */
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/math_helper.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/math_helper.c
new file mode 100644
index 0000000..ef09e40
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/math_helper.c
@@ -0,0 +1,491 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010 ARM Limited. All rights reserved.
+*
+* $Date: 29. November 2010
+* $Revision: V1.0.3
+*
+* Project: CMSIS DSP Library
+*
+* Title: math_helper.c
+*
+* Description: Definition of all helper functions required.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Version 1.0.3 2010/11/29
+* Re-organized the CMSIS folders and updated documentation.
+*
+* Version 1.0.2 2010/11/11
+* Documentation updated.
+*
+* Version 1.0.1 2010/10/05
+* Production release and review comments incorporated.
+*
+* Version 1.0.0 2010/09/20
+* Production release and review comments incorporated.
+*
+* Version 0.0.7 2010/06/10
+* Misra-C changes done
+* -------------------------------------------------------------------- */
+
+/* ----------------------------------------------------------------------
+* Include standard header files
+* -------------------------------------------------------------------- */
+#include<math.h>
+
+/* ----------------------------------------------------------------------
+* Include project header files
+* -------------------------------------------------------------------- */
+#include "math_helper.h"
+
+/**
+ * @brief Caluclation of SNR
+ * @param float* Pointer to the reference buffer
+ * @param float* Pointer to the test buffer
+ * @param uint32_t total number of samples
+ * @return float SNR
+ * The function Caluclates signal to noise ratio for the reference output
+ * and test output
+ */
+
+float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize)
+{
+ float EnergySignal = 0.0, EnergyError = 0.0;
+ uint32_t i;
+ float SNR;
+ int temp;
+ int *test;
+
+ for (i = 0; i < buffSize; i++)
+ {
+ /* Checking for a NAN value in pRef array */
+ test = (int *)(&pRef[i]);
+ temp = *test;
+
+ if (temp == 0x7FC00000)
+ {
+ return(0);
+ }
+
+ /* Checking for a NAN value in pTest array */
+ test = (int *)(&pTest[i]);
+ temp = *test;
+
+ if (temp == 0x7FC00000)
+ {
+ return(0);
+ }
+ EnergySignal += pRef[i] * pRef[i];
+ EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]);
+ }
+
+ /* Checking for a NAN value in EnergyError */
+ test = (int *)(&EnergyError);
+ temp = *test;
+
+ if (temp == 0x7FC00000)
+ {
+ return(0);
+ }
+
+
+ SNR = 10 * log10f (EnergySignal / EnergyError);
+
+ return (SNR);
+
+}
+
+
+
+double arm_snr_f64(double *pRef, double *pTest, uint32_t buffSize)
+{
+ double EnergySignal = 0.0, EnergyError = 0.0;
+ uint32_t i;
+ double SNR;
+ int temp;
+ int *test;
+
+ for (i = 0; i < buffSize; i++)
+ {
+ /* Checking for a NAN value in pRef array */
+ test = (int *)(&pRef[i]);
+ temp = *test;
+
+ if (temp == 0x7FC00000)
+ {
+ return(0);
+ }
+
+ /* Checking for a NAN value in pTest array */
+ test = (int *)(&pTest[i]);
+ temp = *test;
+
+ if (temp == 0x7FC00000)
+ {
+ return(0);
+ }
+ EnergySignal += pRef[i] * pRef[i];
+ EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]);
+ }
+
+ /* Checking for a NAN value in EnergyError */
+ test = (int *)(&EnergyError);
+ temp = *test;
+
+ if (temp == 0x7FC00000)
+ {
+ return(0);
+ }
+
+
+ SNR = 10 * log10 (EnergySignal / EnergyError);
+
+ return (SNR);
+
+}
+
+/**
+ * @brief Provide guard bits for Input buffer
+ * @param q15_t* Pointer to input buffer
+ * @param uint32_t blockSize
+ * @param uint32_t guard_bits
+ * @return none
+ * The function Provides the guard bits for the buffer
+ * to avoid overflow
+ */
+
+void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < blockSize; i++)
+ {
+ input_buf[i] = input_buf[i] >> guard_bits;
+ }
+}
+
+/**
+ * @brief Converts float to fixed in q12.20 format
+ * @param uint32_t number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point(q12.20) values
+ */
+
+void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 1048576.0f corresponds to pow(2, 20) */
+ pOut[i] = (q31_t) (pIn[i] * 1048576.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 1.0)
+ {
+ pOut[i] = 0x000FFFFF;
+ }
+ }
+}
+
+/**
+ * @brief Compare MATLAB Reference Output and ARM Test output
+ * @param q15_t* Pointer to Ref buffer
+ * @param q15_t* Pointer to Test buffer
+ * @param uint32_t number of samples in the buffer
+ * @return none
+ */
+
+uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples)
+{
+ uint32_t i;
+ int32_t diff, diffCrnt = 0;
+ uint32_t maxDiff = 0;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ diff = pIn[i] - pOut[i];
+ diffCrnt = (diff > 0) ? diff : -diff;
+
+ if (diffCrnt > maxDiff)
+ {
+ maxDiff = diffCrnt;
+ }
+ }
+
+ return(maxDiff);
+}
+
+/**
+ * @brief Compare MATLAB Reference Output and ARM Test output
+ * @param q31_t* Pointer to Ref buffer
+ * @param q31_t* Pointer to Test buffer
+ * @param uint32_t number of samples in the buffer
+ * @return none
+ */
+
+uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples)
+{
+ uint32_t i;
+ int32_t diff, diffCrnt = 0;
+ uint32_t maxDiff = 0;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ diff = pIn[i] - pOut[i];
+ diffCrnt = (diff > 0) ? diff : -diff;
+
+ if (diffCrnt > maxDiff)
+ {
+ maxDiff = diffCrnt;
+ }
+ }
+
+ return(maxDiff);
+}
+
+/**
+ * @brief Provide guard bits for Input buffer
+ * @param q31_t* Pointer to input buffer
+ * @param uint32_t blockSize
+ * @param uint32_t guard_bits
+ * @return none
+ * The function Provides the guard bits for the buffer
+ * to avoid overflow
+ */
+
+void arm_provide_guard_bits_q31 (q31_t * input_buf,
+ uint32_t blockSize,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < blockSize; i++)
+ {
+ input_buf[i] = input_buf[i] >> guard_bits;
+ }
+}
+
+/**
+ * @brief Provide guard bits for Input buffer
+ * @param q31_t* Pointer to input buffer
+ * @param uint32_t blockSize
+ * @param uint32_t guard_bits
+ * @return none
+ * The function Provides the guard bits for the buffer
+ * to avoid overflow
+ */
+
+void arm_provide_guard_bits_q7 (q7_t * input_buf,
+ uint32_t blockSize,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < blockSize; i++)
+ {
+ input_buf[i] = input_buf[i] >> guard_bits;
+ }
+}
+
+
+
+/**
+ * @brief Caluclates number of guard bits
+ * @param uint32_t number of additions
+ * @return none
+ * The function Caluclates the number of guard bits
+ * depending on the numtaps
+ */
+
+uint32_t arm_calc_guard_bits (uint32_t num_adds)
+{
+ uint32_t i = 1, j = 0;
+
+ if (num_adds == 1)
+ {
+ return (0);
+ }
+
+ while (i < num_adds)
+ {
+ i = i * 2;
+ j++;
+ }
+
+ return (j);
+}
+
+/**
+ * @brief Converts Q15 to floating-point
+ * @param uint32_t number of samples in the buffer
+ * @return none
+ */
+
+void arm_apply_guard_bits (float32_t * pIn,
+ uint32_t numSamples,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ pIn[i] = pIn[i] * arm_calc_2pow(guard_bits);
+ }
+}
+
+/**
+ * @brief Calculates pow(2, numShifts)
+ * @param uint32_t number of shifts
+ * @return pow(2, numShifts)
+ */
+uint32_t arm_calc_2pow(uint32_t numShifts)
+{
+
+ uint32_t i, val = 1;
+
+ for (i = 0; i < numShifts; i++)
+ {
+ val = val * 2;
+ }
+
+ return(val);
+}
+
+
+
+/**
+ * @brief Converts float to fixed q14
+ * @param uint32_t number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q14 (float *pIn, q15_t * pOut,
+ uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 16384.0f corresponds to pow(2, 14) */
+ pOut[i] = (q15_t) (pIn[i] * 16384.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 2.0)
+ {
+ pOut[i] = 0x7FFF;
+ }
+
+ }
+
+}
+
+
+/**
+ * @brief Converts float to fixed q30 format
+ * @param uint32_t number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q30 (float *pIn, q31_t * pOut,
+ uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 1073741824.0f corresponds to pow(2, 30) */
+ pOut[i] = (q31_t) (pIn[i] * 1073741824.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 2.0)
+ {
+ pOut[i] = 0x7FFFFFFF;
+ }
+ }
+}
+
+/**
+ * @brief Converts float to fixed q30 format
+ * @param uint32_t number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q29 (float *pIn, q31_t * pOut,
+ uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 1073741824.0f corresponds to pow(2, 30) */
+ pOut[i] = (q31_t) (pIn[i] * 536870912.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 4.0)
+ {
+ pOut[i] = 0x7FFFFFFF;
+ }
+ }
+}
+
+
+/**
+ * @brief Converts float to fixed q28 format
+ * @param uint32_t number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q28 (float *pIn, q31_t * pOut,
+ uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 268435456.0f corresponds to pow(2, 28) */
+ pOut[i] = (q31_t) (pIn[i] * 268435456.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 8.0)
+ {
+ pOut[i] = 0x7FFFFFFF;
+ }
+ }
+}
+
+/**
+ * @brief Clip the float values to +/- 1
+ * @param pIn input buffer
+ * @param numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_clip_f32 (float *pIn, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ if (pIn[i] > 1.0f)
+ {
+ pIn[i] = 1.0;
+ }
+ else if ( pIn[i] < -1.0f)
+ {
+ pIn[i] = -1.0;
+ }
+
+ }
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_add_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_add_tests.c
new file mode 100644
index 0000000..c536899
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_add_tests.c
@@ -0,0 +1,31 @@
+#include "jtest.h"
+#include "matrix_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "matrix_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_MAT_ADD_TEST(suffix) \
+ MATRIX_DEFINE_TEST_TEMPLATE_ELT2( \
+ mat_add, \
+ suffix, \
+ MATRIX_TEST_CONFIG_ADDITIVE_OUTPUT, \
+ MATRIX_TEST_VALID_ADDITIVE_DIMENSIONS, \
+ MATRIX_COMPARE_INTERFACE)
+
+JTEST_ARM_MAT_ADD_TEST(f32);
+JTEST_ARM_MAT_ADD_TEST(q31);
+JTEST_ARM_MAT_ADD_TEST(q15);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(mat_add_tests)
+{
+ JTEST_TEST_CALL(arm_mat_add_f32_test);
+ JTEST_TEST_CALL(arm_mat_add_q31_test);
+ JTEST_TEST_CALL(arm_mat_add_q15_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_cmplx_mult_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_cmplx_mult_tests.c
new file mode 100644
index 0000000..50cd57e
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_cmplx_mult_tests.c
@@ -0,0 +1,59 @@
+#include "jtest.h"
+#include "matrix_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "matrix_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_MAT_CMPLX_MULT_TEST(suffix, comparison_interface) \
+ MATRIX_DEFINE_TEST_TEMPLATE_ELT2( \
+ mat_cmplx_mult, \
+ suffix, \
+ MATRIX_TEST_CONFIG_MULTIPLICATIVE_OUTPUT, \
+ MATRIX_TEST_VALID_MULTIPLICATIVE_DIMENSIONS, \
+ comparison_interface)
+
+JTEST_ARM_MAT_CMPLX_MULT_TEST(f32, MATRIX_SNR_COMPARE_INTERFACE);
+JTEST_ARM_MAT_CMPLX_MULT_TEST(q31, MATRIX_COMPARE_INTERFACE);
+
+/*--------------------------------------------------------------------------------*/
+/* Q15 Uses a Different interface than the others. */
+/*--------------------------------------------------------------------------------*/
+
+#define ARM_mat_cmplx_mult_q15_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \
+ PAREN(input_a_ptr, input_b_ptr, \
+ (void *) &matrix_output_fut, \
+ (q15_t *) matrix_output_scratch)
+
+JTEST_DEFINE_TEST(arm_mat_cmplx_mult_q15_test, arm_mat_cmplx_mult_q15)
+{
+ MATRIX_TEST_TEMPLATE_ELT2(
+ matrix_q15_a_inputs,
+ matrix_q15_b_inputs,
+ arm_matrix_instance_q15 * ,
+ arm_matrix_instance_q15,
+ TYPE_FROM_ABBREV(q15),
+ arm_mat_cmplx_mult_q15,
+ ARM_mat_cmplx_mult_q15_INPUT_INTERFACE,
+ ref_mat_cmplx_mult_q15,
+ REF_mat_cmplx_mult_INPUT_INTERFACE,
+ MATRIX_TEST_CONFIG_MULTIPLICATIVE_OUTPUT,
+ MATRIX_TEST_VALID_MULTIPLICATIVE_DIMENSIONS,
+ MATRIX_COMPARE_INTERFACE);
+}
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(mat_cmplx_mult_tests)
+{
+ /*
+ To skip a test, comment it out.
+ */
+ JTEST_TEST_CALL(arm_mat_cmplx_mult_f32_test);
+ JTEST_TEST_CALL(arm_mat_cmplx_mult_q31_test);
+ JTEST_TEST_CALL(arm_mat_cmplx_mult_q15_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_init_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_init_tests.c
new file mode 100644
index 0000000..7d879ee
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_init_tests.c
@@ -0,0 +1,58 @@
+#include "jtest.h"
+#include "matrix_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "matrix_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_MAT_INIT_TEST(suffix) \
+ JTEST_DEFINE_TEST(arm_mat_init_##suffix##_test, \
+ arm_mat_init_##suffix) \
+ { \
+ const uint16_t rows = 4; \
+ const uint16_t cols = 2; \
+ arm_matrix_instance_##suffix matrix = {0}; \
+ /* TYPE_FROM_ABBREV(suffix) data[rows*cols] = {0}; */ \
+ TYPE_FROM_ABBREV(suffix) data[4*2] = {0}; \
+ \
+ arm_mat_init_##suffix(&matrix, \
+ rows, \
+ cols, \
+ data); \
+ \
+ JTEST_DUMP_STRF("Matrix Dimensions: %dx%d\n", \
+ (int)matrix.numRows, \
+ (int)matrix.numCols); \
+ \
+ if ((matrix.numRows == rows) && \
+ (matrix.numCols == cols) && \
+ (matrix.pData == data)) \
+ { \
+ return JTEST_TEST_PASSED; \
+ } \
+ else \
+ { \
+ return JTEST_TEST_FAILED; \
+ } \
+ \
+ }
+
+JTEST_ARM_MAT_INIT_TEST(f32);
+JTEST_ARM_MAT_INIT_TEST(q31);
+JTEST_ARM_MAT_INIT_TEST(q15);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(mat_init_tests)
+{
+ /*
+ To skip a test, comment it out.
+ */
+ JTEST_TEST_CALL(arm_mat_init_f32_test);
+ JTEST_TEST_CALL(arm_mat_init_q31_test);
+ JTEST_TEST_CALL(arm_mat_init_q15_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_inverse_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_inverse_tests.c
new file mode 100644
index 0000000..372ac1d
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_inverse_tests.c
@@ -0,0 +1,92 @@
+#include "jtest.h"
+#include "matrix_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "matrix_templates.h"
+#include "type_abbrev.h"
+
+JTEST_DEFINE_TEST(arm_mat_inverse_f32_test, arm_mat_inverse_f32)
+{
+ TEMPLATE_DO_ARR_DESC(
+ mat_idx, arm_matrix_instance_f32 *, mat_ptr, matrix_f32_invertible_inputs
+ ,
+ JTEST_DUMP_STRF("Matrix Dimensions: %dx%d\n",
+ (int)mat_ptr->numRows,
+ (int)mat_ptr->numCols);
+
+ if (MATRIX_TEST_VALID_SQUARE_DIMENSIONS(arm_matrix_instance_f32 *, mat_ptr))
+ {
+ MATRIX_TEST_CONFIG_SAMESIZE_OUTPUT(arm_matrix_instance_f32 *, mat_ptr);
+
+ /* arm_mat_inverse_f32() modifies its source input. Use the scratch
+ * buffer to store a copy of the intended input. */
+ {
+ float32_t * original_pdata_ptr = mat_ptr->pData;
+
+ memcpy(matrix_output_scratch,
+ mat_ptr->pData,
+ mat_ptr->numRows * mat_ptr->numCols * sizeof(float32_t));
+ mat_ptr->pData = (void*) &matrix_output_scratch;
+
+ JTEST_COUNT_CYCLES(arm_mat_inverse_f32(mat_ptr, &matrix_output_fut));
+ mat_ptr->pData = original_pdata_ptr;
+ }
+
+ ref_mat_inverse_f32(mat_ptr, &matrix_output_ref);
+
+ MATRIX_SNR_COMPARE_INTERFACE(arm_matrix_instance_f32,
+ float32_t);
+ });
+
+ return JTEST_TEST_PASSED;
+}
+
+JTEST_DEFINE_TEST(arm_mat_inverse_f64_test, arm_mat_inverse_f64)
+{
+ TEMPLATE_DO_ARR_DESC(
+ mat_idx, arm_matrix_instance_f64 *, mat_ptr, matrix_f64_invertible_inputs
+ ,
+ JTEST_DUMP_STRF("Matrix Dimensions: %dx%d\n",
+ (int)mat_ptr->numRows,
+ (int)mat_ptr->numCols);
+
+ if (MATRIX_TEST_VALID_SQUARE_DIMENSIONS(arm_matrix_instance_f64 *, mat_ptr))
+ {
+ MATRIX_TEST_CONFIG_SAMESIZE_OUTPUT(arm_matrix_instance_f64 *, mat_ptr);
+
+ /* arm_mat_inverse_f64() modifies its source input. Use the scratch
+ * buffer to store a copy of the intended input. */
+ {
+ float64_t * original_pdata_ptr = mat_ptr->pData;
+
+ memcpy(matrix_output_scratch,
+ mat_ptr->pData,
+ mat_ptr->numRows * mat_ptr->numCols * sizeof(float64_t));
+ mat_ptr->pData = (void*) &matrix_output_scratch;
+
+ JTEST_COUNT_CYCLES(arm_mat_inverse_f64(mat_ptr, &matrix_output_fut64));
+ mat_ptr->pData = original_pdata_ptr;
+ }
+
+ ref_mat_inverse_f64(mat_ptr, &matrix_output_ref64);
+
+ MATRIX_DBL_SNR_COMPARE_INTERFACE(arm_matrix_instance_f64);
+ });
+
+ return JTEST_TEST_PASSED;
+}
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(mat_inverse_tests)
+{
+ /*
+ To skip a test, comment it out.
+ */
+ JTEST_TEST_CALL(arm_mat_inverse_f32_test);
+ JTEST_TEST_CALL(arm_mat_inverse_f64_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_fast_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_fast_tests.c
new file mode 100644
index 0000000..313aa04
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_fast_tests.c
@@ -0,0 +1,57 @@
+#include "jtest.h"
+#include "matrix_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "matrix_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_MAT_MULT_FAST_TEST(suffix) \
+ MATRIX_DEFINE_TEST_TEMPLATE_ELT2( \
+ mat_mult_fast, \
+ suffix, \
+ MATRIX_TEST_CONFIG_MULTIPLICATIVE_OUTPUT, \
+ MATRIX_TEST_VALID_MULTIPLICATIVE_DIMENSIONS, \
+ MATRIX_SNR_COMPARE_INTERFACE)
+
+JTEST_ARM_MAT_MULT_FAST_TEST(q31);
+
+/*--------------------------------------------------------------------------------*/
+/* Q15 Uses a Different interface than the others. */
+/*--------------------------------------------------------------------------------*/
+
+#define ARM_mat_mult_fast_q15_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \
+ PAREN(input_a_ptr, input_b_ptr, \
+ (void *) &matrix_output_fut, \
+ (q15_t *) matrix_output_scratch)
+
+JTEST_DEFINE_TEST(arm_mat_mult_fast_q15_test, arm_mat_mult_fast_q15)
+{
+ MATRIX_TEST_TEMPLATE_ELT2(
+ matrix_q15_a_inputs,
+ matrix_q15_b_inputs,
+ arm_matrix_instance_q15 * ,
+ arm_matrix_instance_q15,
+ TYPE_FROM_ABBREV(q15),
+ arm_mat_mult_fast_q15,
+ ARM_mat_mult_fast_q15_INPUT_INTERFACE,
+ ref_mat_mult_fast_q15,
+ REF_mat_mult_fast_INPUT_INTERFACE,
+ MATRIX_TEST_CONFIG_MULTIPLICATIVE_OUTPUT,
+ MATRIX_TEST_VALID_MULTIPLICATIVE_DIMENSIONS,
+ MATRIX_SNR_COMPARE_INTERFACE);
+}
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(mat_mult_fast_tests)
+{
+ /*
+ To skip a test, comment it out.
+ */
+ JTEST_TEST_CALL(arm_mat_mult_fast_q31_test);
+ JTEST_TEST_CALL(arm_mat_mult_fast_q15_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_tests.c
new file mode 100644
index 0000000..c74bdc8
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_tests.c
@@ -0,0 +1,59 @@
+#include "jtest.h"
+#include "matrix_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "matrix_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_MAT_MULT_TEST(suffix) \
+ MATRIX_DEFINE_TEST_TEMPLATE_ELT2( \
+ mat_mult, \
+ suffix, \
+ MATRIX_TEST_CONFIG_MULTIPLICATIVE_OUTPUT, \
+ MATRIX_TEST_VALID_MULTIPLICATIVE_DIMENSIONS, \
+ MATRIX_COMPARE_INTERFACE)
+
+JTEST_ARM_MAT_MULT_TEST(f32);
+JTEST_ARM_MAT_MULT_TEST(q31);
+
+/*--------------------------------------------------------------------------------*/
+/* Q15 Uses a Different interface than the others. */
+/*--------------------------------------------------------------------------------*/
+
+#define ARM_mat_mult_q15_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \
+ PAREN(input_a_ptr, input_b_ptr, \
+ (void *) &matrix_output_fut, \
+ (q15_t *) matrix_output_scratch)
+
+JTEST_DEFINE_TEST(arm_mat_mult_q15_test, arm_mat_mult_q15)
+{
+ MATRIX_TEST_TEMPLATE_ELT2(
+ matrix_q15_a_inputs,
+ matrix_q15_b_inputs,
+ arm_matrix_instance_q15 * ,
+ arm_matrix_instance_q15,
+ TYPE_FROM_ABBREV(q15),
+ arm_mat_mult_q15,
+ ARM_mat_mult_q15_INPUT_INTERFACE,
+ ref_mat_mult_q15,
+ REF_mat_mult_INPUT_INTERFACE,
+ MATRIX_TEST_CONFIG_MULTIPLICATIVE_OUTPUT,
+ MATRIX_TEST_VALID_MULTIPLICATIVE_DIMENSIONS,
+ MATRIX_COMPARE_INTERFACE);
+}
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(mat_mult_tests)
+{
+ /*
+ To skip a test, comment it out.
+ */
+ JTEST_TEST_CALL(arm_mat_mult_f32_test);
+ JTEST_TEST_CALL(arm_mat_mult_q31_test);
+ JTEST_TEST_CALL(arm_mat_mult_q15_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_scale_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_scale_tests.c
new file mode 100644
index 0000000..63fba94
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_scale_tests.c
@@ -0,0 +1,90 @@
+#include "jtest.h"
+#include "matrix_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "matrix_templates.h"
+#include "type_abbrev.h"
+
+/* This is for the two fixed point cases */
+#define JTEST_ARM_MAT_SCALE_TEST(suffix,type) \
+ JTEST_DEFINE_TEST(arm_mat_scale_##suffix##_test, arm_mat_scale_##suffix) \
+ { \
+ uint32_t i,j; \
+ \
+ TEMPLATE_DO_ARR_DESC( \
+ mat_idx, arm_matrix_instance_##suffix *, \
+ mat_ptr, matrix_##suffix##_b_inputs \
+ , \
+ MATRIX_TEST_CONFIG_SAMESIZE_OUTPUT( \
+ arm_matrix_instance_##suffix *, mat_ptr); \
+ \
+ for(i=0;i<MATRIX_MAX_COEFFS_LEN;i++) \
+ { \
+ for(j=0;j<MATRIX_MAX_SHIFTS_LEN;j++) \
+ { \
+ JTEST_DUMP_STRF("Matrix Dimensions: %dx%d\n", \
+ (int)mat_ptr->numRows, \
+ (int)mat_ptr->numCols); \
+ \
+ JTEST_COUNT_CYCLES( \
+ arm_mat_scale_##suffix(mat_ptr, \
+ matrix_##suffix##_scale_values[i], \
+ matrix_shift_values[j], \
+ (arm_matrix_instance_##suffix*) &matrix_output_fut)); \
+ \
+ ref_mat_scale_##suffix(mat_ptr, \
+ matrix_##suffix##_scale_values[i], \
+ matrix_shift_values[j], \
+ (arm_matrix_instance_##suffix*) &matrix_output_ref); \
+ \
+ MATRIX_SNR_COMPARE_INTERFACE(arm_matrix_instance_##suffix, \
+ type); \
+ } \
+ }); \
+ \
+ return JTEST_TEST_PASSED; \
+ }
+
+JTEST_DEFINE_TEST(arm_mat_scale_f32_test, arm_mat_scale_f32)
+{
+ uint32_t i;
+
+ TEMPLATE_DO_ARR_DESC(
+ mat_idx, arm_matrix_instance_f32 *, mat_ptr, matrix_f32_b_inputs
+ ,
+ MATRIX_TEST_CONFIG_SAMESIZE_OUTPUT(arm_matrix_instance_f32 *, mat_ptr);
+
+ for(i=0;i<MATRIX_MAX_COEFFS_LEN;i++)
+ {
+ JTEST_DUMP_STRF("Matrix Dimensions: %dx%d\n",
+ (int)mat_ptr->numRows,
+ (int)mat_ptr->numCols);
+ JTEST_COUNT_CYCLES(arm_mat_scale_f32(mat_ptr, matrix_f32_scale_values[i], &matrix_output_fut));
+
+ ref_mat_scale_f32(mat_ptr, matrix_f32_scale_values[i], &matrix_output_ref);
+
+ MATRIX_SNR_COMPARE_INTERFACE(arm_matrix_instance_f32,
+ float32_t);
+ });
+
+ return JTEST_TEST_PASSED;
+}
+
+JTEST_ARM_MAT_SCALE_TEST(q31,q31_t);
+JTEST_ARM_MAT_SCALE_TEST(q15,q15_t);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(mat_scale_tests)
+{
+ /*
+ To skip a test, comment it out.
+ */
+ JTEST_TEST_CALL(arm_mat_scale_f32_test);
+ JTEST_TEST_CALL(arm_mat_scale_q31_test);
+ JTEST_TEST_CALL(arm_mat_scale_q15_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_sub_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_sub_tests.c
new file mode 100644
index 0000000..245c28e
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_sub_tests.c
@@ -0,0 +1,34 @@
+#include "jtest.h"
+#include "matrix_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "matrix_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_MAT_SUB_TEST(suffix) \
+ MATRIX_DEFINE_TEST_TEMPLATE_ELT2( \
+ mat_sub, \
+ suffix, \
+ MATRIX_TEST_CONFIG_ADDITIVE_OUTPUT, \
+ MATRIX_TEST_VALID_ADDITIVE_DIMENSIONS, \
+ MATRIX_COMPARE_INTERFACE)
+
+JTEST_ARM_MAT_SUB_TEST(f32);
+JTEST_ARM_MAT_SUB_TEST(q31);
+JTEST_ARM_MAT_SUB_TEST(q15);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(mat_sub_tests)
+{
+ /*
+ To skip a test, comment it out.
+ */
+ JTEST_TEST_CALL(arm_mat_sub_f32_test);
+ JTEST_TEST_CALL(arm_mat_sub_q31_test);
+ JTEST_TEST_CALL(arm_mat_sub_q15_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_trans_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_trans_tests.c
new file mode 100644
index 0000000..e49c80b
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_trans_tests.c
@@ -0,0 +1,33 @@
+#include "jtest.h"
+#include "matrix_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "matrix_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_MAT_TRANS_TEST(suffix) \
+ MATRIX_DEFINE_TEST_TEMPLATE_ELT1( \
+ mat_trans, \
+ suffix, \
+ MATRIX_TEST_CONFIG_TRANSPOSE_OUTPUT, \
+ MATRIX_TEST_VALID_DIMENSIONS_ALWAYS)
+
+JTEST_ARM_MAT_TRANS_TEST(f32);
+JTEST_ARM_MAT_TRANS_TEST(q31);
+JTEST_ARM_MAT_TRANS_TEST(q15);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(mat_trans_tests)
+{
+ /*
+ To skip a test, comment it out.
+ */
+ JTEST_TEST_CALL(arm_mat_trans_f32_test);
+ JTEST_TEST_CALL(arm_mat_trans_q31_test);
+ JTEST_TEST_CALL(arm_mat_trans_q15_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_common_data.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_common_data.c
new file mode 100644
index 0000000..033fe10
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_common_data.c
@@ -0,0 +1,255 @@
+#include "arm_math.h"
+#include "matrix_test_data.h"
+#include "type_abbrev.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Input/Output Buffers */
+/*--------------------------------------------------------------------------------*/
+
+MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_output_fut_data[2*MATRIX_TEST_MAX_ELTS] = {0};
+MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_output_ref_data[2*MATRIX_TEST_MAX_ELTS] = {0};
+MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_output_scratch[MATRIX_TEST_MAX_ELTS] = {0};
+
+MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_output_f32_fut[MATRIX_TEST_MAX_ELTS];
+MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_output_f32_ref[MATRIX_TEST_MAX_ELTS];
+
+arm_matrix_instance_f32 matrix_output_fut = {
+ 0,
+ 0,
+ (float32_t *) &matrix_output_fut_data
+};
+
+arm_matrix_instance_f32 matrix_output_ref = {
+ 0,
+ 0,
+ (float32_t *) &matrix_output_ref_data
+};
+
+arm_matrix_instance_f64 matrix_output_fut64 = {
+ 0,
+ 0,
+ (float64_t *) &matrix_output_fut_data
+};
+
+arm_matrix_instance_f64 matrix_output_ref64 = {
+ 0,
+ 0,
+ (float64_t *) &matrix_output_ref_data
+};
+
+/*--------------------------------------------------------------------------------*/
+/* Data Buckets */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Pool of random data to base matrix inputs from.
+ */
+float32_t matrix_f32_100_rand[100] = {
+ -45.0345569674258, -11.0261163038747, -14.6841428777929,
+ 0.0345569674258, -11.0261163038747, -14.6841428777929,
+ -20.3679194392227, 27.5712678608402, -12.1390617339732,
+ -19.8753669720509, 42.3379642103244, -23.7788252219155,
+ -23.7517765301667, 40.2716109915281, -25.8308714086167,
+ 32.1194040197959, 24.4692807074156, -1.32083675968276,
+ 31.1580458282477, -2.90766514824093, -6.97926086704160,
+ 10.2843089382083, 30.1014622769739, 44.4787189721646,
+ -9.60878544118853, -48.4596562348445, -31.1044984967456,
+ -6.41414114190809, 3.28255887994549, -26.9511839788442,
+ -31.5183679875864, 21.1215780433683, -47.0779722437854,
+ -0.913590753192006, -40.3545474831611, -45.6976198342192,
+ 18.6775433365315, -5.32162505701938, -14.9272896423117,
+ 34.4308792695389, 40.4880968679893, -27.8253265982760,
+ 42.8854139478045, -1.07473615999811, -36.8026707393665,
+ -33.1009970537296, -31.6488844262730, -19.3650527983443,
+ 43.9001561999887, -30.5235710432951, 47.9748378356085,
+ -38.2582349144194, 23.0330862855453, -16.2280590178623,
+ 44.2050590775485, 14.9115474956452, -13.1515403509664,
+ 0.850865538112700, 37.5942811492984, -27.4078219027601,
+ -6.11300268738968, -20.3324126781673, -1.13910261964209,
+ 40.0053846417662, 45.6134540229802, 23.1722385658670,
+ 12.5618560729690, 1.07715641721097, 5.01563428984222,
+ -32.9291952852141, -38.8880776559401, -18.1221698074118,
+ 7.85250610234389, -13.0753218879785, 7.52085950784656,
+ 14.7745963136307, 28.0227435151377, 31.7627708322262,
+ 12.2475086001227, -27.2335702183447, -24.1935304087933,
+ -7.58332402861928, -26.2716420228479, -38.8797244706213,
+ -44.0220457052844, -4.90762935690551, -41.8874231134215,
+ 29.4831416883453, 8.70447045314168, -6.43013158961009,
+ -9.12801538874479, 0.785828466111815, -4.11511718200689,
+ 28.0252068321138, -26.5220086627594, 4.70088922863450,
+ 42.9385970968730, 14.4318130193692, -29.2257707266972,
+ 46.3088539286913
+};
+
+float64_t matrix_f64_100_rand[100] = {
+ -45.0345569674258, -11.0261163038747, -14.6841428777929,
+ 0.0345569674258, -11.0261163038747, -14.6841428777929,
+ -20.3679194392227, 27.5712678608402, -12.1390617339732,
+ -19.8753669720509, 42.3379642103244, -23.7788252219155,
+ -23.7517765301667, 40.2716109915281, -25.8308714086167,
+ 32.1194040197959, 24.4692807074156, -1.32083675968276,
+ 31.1580458282477, -2.90766514824093, -6.97926086704160,
+ 10.2843089382083, 30.1014622769739, 44.4787189721646,
+ -9.60878544118853, -48.4596562348445, -31.1044984967456,
+ -6.41414114190809, 3.28255887994549, -26.9511839788442,
+ -31.5183679875864, 21.1215780433683, -47.0779722437854,
+ -0.913590753192006, -40.3545474831611, -45.6976198342192,
+ 18.6775433365315, -5.32162505701938, -14.9272896423117,
+ 34.4308792695389, 40.4880968679893, -27.8253265982760,
+ 42.8854139478045, -1.07473615999811, -36.8026707393665,
+ -33.1009970537296, -31.6488844262730, -19.3650527983443,
+ 43.9001561999887, -30.5235710432951, 47.9748378356085,
+ -38.2582349144194, 23.0330862855453, -16.2280590178623,
+ 44.2050590775485, 14.9115474956452, -13.1515403509664,
+ 0.850865538112700, 37.5942811492984, -27.4078219027601,
+ -6.11300268738968, -20.3324126781673, -1.13910261964209,
+ 40.0053846417662, 45.6134540229802, 23.1722385658670,
+ 12.5618560729690, 1.07715641721097, 5.01563428984222,
+ -32.9291952852141, -38.8880776559401, -18.1221698074118,
+ 7.85250610234389, -13.0753218879785, 7.52085950784656,
+ 14.7745963136307, 28.0227435151377, 31.7627708322262,
+ 12.2475086001227, -27.2335702183447, -24.1935304087933,
+ -7.58332402861928, -26.2716420228479, -38.8797244706213,
+ -44.0220457052844, -4.90762935690551, -41.8874231134215,
+ 29.4831416883453, 8.70447045314168, -6.43013158961009,
+ -9.12801538874479, 0.785828466111815, -4.11511718200689,
+ 28.0252068321138, -26.5220086627594, 4.70088922863450,
+ 42.9385970968730, 14.4318130193692, -29.2257707266972,
+ 46.3088539286913
+};
+
+MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_zeros[MATRIX_TEST_MAX_ELTS] = {0};
+
+const float32_t matrix_f32_scale_values[MATRIX_MAX_COEFFS_LEN] =
+{
+ 43.0264275639 , -17.0525215570 , -94.8488973910 , -8.1924989580 ,
+ 7.2830326091 , 66.8368719314 , 33.9778190671 , 117.8652289772 ,
+ -129.6077797465, -14.6420815368 , 18.0239223278 , 1.0000000000 ,
+ 55.0375037651 , 1.8674609862 , 0.00000000000 , -33.5750364909
+};
+
+const q31_t matrix_q31_scale_values[MATRIX_MAX_COEFFS_LEN] =
+{
+ 0x0201DC90, 0x211F0D7C, 0x80000000, 0xF573B824,
+ 0xE85ED05B, 0x311DFB52, 0x3529E750, 0x00000000,
+ 0x7FFFFFFF, 0x21FA525A, 0x0971FD45, 0x05547B68,
+ 0x270C6366, 0x06FDD5A6, 0xF7025315, 0xB1155A1E
+};
+
+const q15_t matrix_q15_scale_values[MATRIX_MAX_COEFFS_LEN] =
+{
+ 0x0201, 0x211F, 0x8000, 0xF573,
+ 0xE85E, 0x311D, 0x3529, 0x0000,
+ 0x7FFF, 0x21FA, 0x0971, 0x0554,
+ 0x270C, 0x06FD, 0xF702, 0xB115
+};
+
+const int32_t matrix_shift_values[MATRIX_MAX_SHIFTS_LEN] =
+{
+ -16, -7, 0, 7, 16
+};
+
+/*--------------------------------------------------------------------------------*/
+/* Matrix Definitions */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Define matrices by suffix (f32, q31, q15) for use in test cases.
+ *
+ * The rand1 and rand2 suffixes get their data from the same pool of random
+ * data, but their starting points differ by 1 element.
+ *
+ * Makes available:
+ * - matrix_`suffix`_1x1_rand1/2
+ * - matrix_`suffix`_1x4_rand1/2
+ * - matrix_`suffix`_2x4_rand1/2
+ * - matrix_`suffix`_4x4_rand1/2
+ */
+#define MATRIX_DEFINE_MATRICES(suffix) \
+ arm_matrix_instance_##suffix matrix_##suffix##_1x1_rand1 = \
+ {1, 1, (TYPE_FROM_ABBREV(suffix) *) matrix_f32_100_rand }; \
+ arm_matrix_instance_##suffix matrix_##suffix##_1x1_rand2 = \
+ {1, 1, (TYPE_FROM_ABBREV(suffix) *) (matrix_f32_100_rand+1)}; \
+ arm_matrix_instance_##suffix matrix_##suffix##_1x1_zeros = \
+ {1, 1, (TYPE_FROM_ABBREV(suffix) *) matrix_zeros}; \
+ \
+ arm_matrix_instance_##suffix matrix_##suffix##_1x4_rand1 = \
+ {1, 4, (TYPE_FROM_ABBREV(suffix) *) matrix_f32_100_rand }; \
+ arm_matrix_instance_##suffix matrix_##suffix##_1x4_rand2 = \
+ {1, 4, (TYPE_FROM_ABBREV(suffix) *) (matrix_f32_100_rand+1)}; \
+ arm_matrix_instance_##suffix matrix_##suffix##_1x4_zeros = \
+ {1, 4, (TYPE_FROM_ABBREV(suffix) *) matrix_zeros}; \
+ \
+ arm_matrix_instance_##suffix matrix_##suffix##_2x4_rand1 = \
+ {2, 4, (TYPE_FROM_ABBREV(suffix) *) matrix_f32_100_rand }; \
+ arm_matrix_instance_##suffix matrix_##suffix##_2x4_rand2 = \
+ {2, 4, (TYPE_FROM_ABBREV(suffix) *) (matrix_f32_100_rand+1)}; \
+ arm_matrix_instance_##suffix matrix_##suffix##_2x4_zeros = \
+ {2, 4, (TYPE_FROM_ABBREV(suffix) *) matrix_zeros}; \
+ \
+ arm_matrix_instance_##suffix matrix_##suffix##_4x4_rand1 = \
+ {4, 4, (TYPE_FROM_ABBREV(suffix) *) matrix_f32_100_rand }; \
+ arm_matrix_instance_##suffix matrix_##suffix##_4x4_rand2 = \
+ {4, 4, (TYPE_FROM_ABBREV(suffix) *) (matrix_f32_100_rand+1)}; \
+ arm_matrix_instance_##suffix matrix_##suffix##_4x4_zeros = \
+ {4, 4, (TYPE_FROM_ABBREV(suffix) *) matrix_zeros}
+
+MATRIX_DEFINE_MATRICES(f64);
+MATRIX_DEFINE_MATRICES(f32);
+MATRIX_DEFINE_MATRICES(q31);
+MATRIX_DEFINE_MATRICES(q15);
+
+/*--------------------------------------------------------------------------------*/
+/* Matrix-Input Arrays */
+/*--------------------------------------------------------------------------------*/
+
+/* Define Input #ARR_DESC_t by suffix.
+ *
+ * Taking inputs in parallel from the 'a' and 'b' arrays yields the following
+ * test cases:
+ * - 1x1 multiplication by zero
+ * - 1x1 multiplication between random numbers
+ * - 1x1 * 1x4 valid dimension interaction
+ * - 1x1 * 2x4 invalid dimension interaction
+ * - 2x4 * 4x4 larger valid dimension interaction
+ * - 4x4 * 4x4 larger valid dimension interaction
+ */
+#define MATRIX_DEFINE_INPUTS(suffix) \
+ ARR_DESC_DEFINE(arm_matrix_instance_##suffix *, \
+ matrix_##suffix##_a_inputs, \
+ 6, \
+ CURLY( \
+ &matrix_##suffix##_1x1_rand1, \
+ &matrix_##suffix##_1x1_rand1, \
+ &matrix_##suffix##_1x1_rand1, \
+ &matrix_##suffix##_1x1_rand1, \
+ &matrix_##suffix##_2x4_rand1, \
+ &matrix_##suffix##_4x4_rand1 \
+ )); \
+ \
+ ARR_DESC_DEFINE(arm_matrix_instance_##suffix *, \
+ matrix_##suffix##_b_inputs, \
+ 6, \
+ CURLY( \
+ &matrix_##suffix##_1x1_zeros, \
+ &matrix_##suffix##_1x1_rand2, \
+ &matrix_##suffix##_1x4_rand2, \
+ &matrix_##suffix##_2x4_rand2, \
+ &matrix_##suffix##_4x4_rand2, \
+ &matrix_##suffix##_4x4_rand2 \
+ )); \
+ \
+ ARR_DESC_DEFINE(arm_matrix_instance_##suffix *, \
+ matrix_##suffix##_invertible_inputs, \
+ 4, \
+ CURLY( \
+ &matrix_##suffix##_1x1_rand1, \
+ &matrix_##suffix##_1x1_rand2, \
+ &matrix_##suffix##_4x4_rand1, \
+ &matrix_##suffix##_4x4_rand2 \
+ )) \
+
+MATRIX_DEFINE_INPUTS(f64);
+MATRIX_DEFINE_INPUTS(f32);
+MATRIX_DEFINE_INPUTS(q31);
+MATRIX_DEFINE_INPUTS(q15);
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_group.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_group.c
new file mode 100644
index 0000000..c87439d
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_group.c
@@ -0,0 +1,19 @@
+#include "jtest.h"
+#include "matrix_tests.h"
+
+JTEST_DEFINE_GROUP(matrix_tests)
+{
+ /*
+ To skip a test, comment it out.
+ */
+ JTEST_GROUP_CALL(mat_add_tests);
+ JTEST_GROUP_CALL(mat_cmplx_mult_tests);
+ JTEST_GROUP_CALL(mat_init_tests);
+ JTEST_GROUP_CALL(mat_inverse_tests);
+ JTEST_GROUP_CALL(mat_mult_tests);
+ JTEST_GROUP_CALL(mat_mult_fast_tests);
+ JTEST_GROUP_CALL(mat_sub_tests);
+ JTEST_GROUP_CALL(mat_trans_tests);
+ JTEST_GROUP_CALL(mat_scale_tests);
+ return;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/max_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/max_tests.c
new file mode 100644
index 0000000..d60973b
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/max_tests.c
@@ -0,0 +1,36 @@
+#include "jtest.h"
+#include "statistics_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "statistics_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_MAX_TEST(suffix) \
+ STATISTICS_DEFINE_TEST_TEMPLATE_BUF1_BLK( \
+ max, \
+ suffix, \
+ TYPE_FROM_ABBREV(suffix), \
+ TYPE_FROM_ABBREV(suffix), \
+ STATISTICS_COMPARE_INTERFACE)
+
+JTEST_ARM_MAX_TEST(f32);
+JTEST_ARM_MAX_TEST(q31);
+JTEST_ARM_MAX_TEST(q15);
+JTEST_ARM_MAX_TEST(q7);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(max_tests)
+{
+ /*
+ To skip a test, comment it out.
+ */
+ JTEST_TEST_CALL(arm_max_f32_test);
+ JTEST_TEST_CALL(arm_max_q31_test);
+ JTEST_TEST_CALL(arm_max_q15_test);
+ JTEST_TEST_CALL(arm_max_q7_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/mean_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/mean_tests.c
new file mode 100644
index 0000000..291c10a
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/mean_tests.c
@@ -0,0 +1,36 @@
+#include "jtest.h"
+#include "statistics_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "statistics_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_MEAN_TEST(suffix) \
+ STATISTICS_DEFINE_TEST_TEMPLATE_BUF1_BLK( \
+ mean, \
+ suffix, \
+ TYPE_FROM_ABBREV(suffix), \
+ TYPE_FROM_ABBREV(suffix), \
+ STATISTICS_COMPARE_INTERFACE)
+
+JTEST_ARM_MEAN_TEST(f32);
+JTEST_ARM_MEAN_TEST(q31);
+JTEST_ARM_MEAN_TEST(q15);
+JTEST_ARM_MEAN_TEST(q7);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(mean_tests)
+{
+ /*
+ To skip a test, comment it out.
+ */
+ JTEST_TEST_CALL(arm_mean_f32_test);
+ JTEST_TEST_CALL(arm_mean_q31_test);
+ JTEST_TEST_CALL(arm_mean_q15_test);
+ JTEST_TEST_CALL(arm_mean_q7_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/min_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/min_tests.c
new file mode 100644
index 0000000..9d831d0
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/min_tests.c
@@ -0,0 +1,36 @@
+#include "jtest.h"
+#include "statistics_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "statistics_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_MIN_TEST(suffix) \
+ STATISTICS_DEFINE_TEST_TEMPLATE_BUF1_BLK( \
+ min, \
+ suffix, \
+ TYPE_FROM_ABBREV(suffix), \
+ TYPE_FROM_ABBREV(suffix), \
+ STATISTICS_COMPARE_INTERFACE)
+
+JTEST_ARM_MIN_TEST(f32);
+JTEST_ARM_MIN_TEST(q31);
+JTEST_ARM_MIN_TEST(q15);
+JTEST_ARM_MIN_TEST(q7);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(min_tests)
+{
+ /*
+ To skip a test, comment it out.
+ */
+ JTEST_TEST_CALL(arm_min_f32_test);
+ JTEST_TEST_CALL(arm_min_q31_test);
+ JTEST_TEST_CALL(arm_min_q15_test);
+ JTEST_TEST_CALL(arm_min_q7_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/power_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/power_tests.c
new file mode 100644
index 0000000..12c30ea
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/power_tests.c
@@ -0,0 +1,36 @@
+#include "jtest.h"
+#include "statistics_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "statistics_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_POWER_TEST(suffix, output_type) \
+ STATISTICS_DEFINE_TEST_TEMPLATE_BUF1_BLK( \
+ power, \
+ suffix, \
+ TYPE_FROM_ABBREV(suffix), \
+ TYPE_FROM_ABBREV(suffix), \
+ STATISTICS_SNR_COMPARE_INTERFACE)
+
+JTEST_ARM_POWER_TEST(f32, float32_t);
+JTEST_ARM_POWER_TEST(q31, q63_t);
+JTEST_ARM_POWER_TEST(q15, q63_t);
+JTEST_ARM_POWER_TEST(q7, q31_t);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(power_tests)
+{
+ /*
+ To skip a test, comment it out.
+ */
+ JTEST_TEST_CALL(arm_power_f32_test);
+ JTEST_TEST_CALL(arm_power_q31_test);
+ JTEST_TEST_CALL(arm_power_q15_test);
+ JTEST_TEST_CALL(arm_power_q7_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/rms_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/rms_tests.c
new file mode 100644
index 0000000..d9b1a24
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/rms_tests.c
@@ -0,0 +1,34 @@
+#include "jtest.h"
+#include "statistics_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "statistics_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_RMS_TEST(suffix) \
+ STATISTICS_DEFINE_TEST_TEMPLATE_BUF1_BLK( \
+ rms, \
+ suffix, \
+ TYPE_FROM_ABBREV(suffix), \
+ TYPE_FROM_ABBREV(suffix), \
+ STATISTICS_SNR_COMPARE_INTERFACE)
+
+JTEST_ARM_RMS_TEST(f32);
+JTEST_ARM_RMS_TEST(q31);
+JTEST_ARM_RMS_TEST(q15);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(rms_tests)
+{
+ /*
+ To skip a test, comment it out.
+ */
+ JTEST_TEST_CALL(arm_rms_f32_test);
+ JTEST_TEST_CALL(arm_rms_q31_test);
+ JTEST_TEST_CALL(arm_rms_q15_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_common_data.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_common_data.c
new file mode 100644
index 0000000..ebf4580
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_common_data.c
@@ -0,0 +1,94 @@
+#include "statistics_test_data.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Input/Output Buffers */
+/*--------------------------------------------------------------------------------*/
+
+
+ARR_DESC_DEFINE(STATISTICS_BIGGEST_INPUT_TYPE,
+ statistics_output_fut,
+ STATISTICS_MAX_INPUT_ELEMENTS,
+ CURLY(0));
+
+ARR_DESC_DEFINE(STATISTICS_BIGGEST_INPUT_TYPE,
+ statistics_output_ref,
+ STATISTICS_MAX_INPUT_ELEMENTS,
+ CURLY(0));
+
+uint32_t statistics_idx_fut = 0;
+uint32_t statistics_idx_ref = 0;
+
+STATISTICS_BIGGEST_INPUT_TYPE
+statistics_output_f32_ref[STATISTICS_MAX_INPUT_ELEMENTS];
+
+STATISTICS_BIGGEST_INPUT_TYPE
+statistics_output_f32_fut[STATISTICS_MAX_INPUT_ELEMENTS];
+
+/*--------------------------------------------------------------------------------*/
+/* Block Sizes */
+/*--------------------------------------------------------------------------------*/
+
+/*
+ To change test parameter values add/remove values inside CURLY and update
+ the preceeding parameter to reflect the number of values inside CURLY.
+*/
+
+ARR_DESC_DEFINE(uint32_t,
+ statistics_block_sizes,
+ 4,
+ CURLY(1, 2, 15, 32));
+
+/*--------------------------------------------------------------------------------*/
+/* Test Data */
+/*--------------------------------------------------------------------------------*/
+
+ARR_DESC_DEFINE(float32_t,
+ statistics_f_32,
+ 32,
+ CURLY(
+ -0.0865129623056441 , -0.3331168756476194,
+ 0.0250664612949661 , 0.0575352840717098,
+ -0.2292942701362928 , 0.2381830931285998,
+ 0.2378328403304206 , -0.0075266553186635,
+ 0.0654584722817308 , 0.0349278285641849,
+ -0.0373417155362879 , 0.1451581096586606,
+ -0.1176633086028378 , 0.4366371636394202,
+ -0.0272791766173191 , 0.0227862627041619,
+ 0.2133536422718378 , 0.0118562921047211,
+ -0.0191296810967338 , -0.1664698927300045,
+ 0.0588821632785281 , -0.2672363715875608,
+ 0.1428649103637904 , 0.3247124128892542,
+ -0.1383551403404573 , 0.1715993345656525,
+ 0.2508002843205065 , -0.3187459152894954,
+ -0.2881928863802040 , 0.1142295247316356,
+ -0.0799771155430726 , 0.1379994750928690
+ ));
+
+
+ARR_DESC_DEFINE_SUBSET(statistics_f_31,
+ statistics_f_32,
+ 31);
+
+ARR_DESC_DEFINE_SUBSET(statistics_f_15,
+ statistics_f_32,
+ 15);
+
+ARR_DESC_DEFINE_SUBSET(statistics_f_2,
+ statistics_f_32,
+ 2);
+
+ARR_DESC_DEFINE(float32_t,
+ statistics_zeros,
+ 32,
+ CURLY(0));
+
+/* Aggregate all float datasets */
+ARR_DESC_DEFINE(ARR_DESC_t *,
+ statistics_f_all,
+ 4,
+ CURLY(
+ &statistics_zeros,
+ &statistics_f_2,
+ &statistics_f_15,
+ &statistics_f_32
+ ));
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_group.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_group.c
new file mode 100644
index 0000000..6a610a6
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_group.c
@@ -0,0 +1,14 @@
+#include "jtest.h"
+#include "statistics_tests.h"
+
+JTEST_DEFINE_GROUP(statistics_tests)
+{
+ JTEST_GROUP_CALL(max_tests);
+ JTEST_GROUP_CALL(mean_tests);
+ JTEST_GROUP_CALL(min_tests);
+ JTEST_GROUP_CALL(power_tests);
+ JTEST_GROUP_CALL(rms_tests);
+ JTEST_GROUP_CALL(std_tests);
+ JTEST_GROUP_CALL(var_tests);
+ return;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/std_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/std_tests.c
new file mode 100644
index 0000000..b80ed71
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/std_tests.c
@@ -0,0 +1,34 @@
+#include "jtest.h"
+#include "statistics_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "statistics_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_STD_TEST(suffix) \
+ STATISTICS_DEFINE_TEST_TEMPLATE_BUF1_BLK( \
+ std, \
+ suffix, \
+ TYPE_FROM_ABBREV(suffix), \
+ TYPE_FROM_ABBREV(suffix), \
+ STATISTICS_SNR_COMPARE_INTERFACE)
+
+JTEST_ARM_STD_TEST(f32);
+JTEST_ARM_STD_TEST(q31);
+JTEST_ARM_STD_TEST(q15);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(std_tests)
+{
+ /*
+ To skip a test, comment it out.
+ */
+ JTEST_TEST_CALL(arm_std_f32_test);
+ JTEST_TEST_CALL(arm_std_q31_test);
+ JTEST_TEST_CALL(arm_std_q15_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/var_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/var_tests.c
new file mode 100644
index 0000000..3aa7c27
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/var_tests.c
@@ -0,0 +1,34 @@
+#include "jtest.h"
+#include "statistics_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "statistics_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_VAR_TEST(suffix) \
+ STATISTICS_DEFINE_TEST_TEMPLATE_BUF1_BLK( \
+ var, \
+ suffix, \
+ TYPE_FROM_ABBREV(suffix), \
+ TYPE_FROM_ABBREV(suffix), \
+ STATISTICS_SNR_COMPARE_INTERFACE)
+
+JTEST_ARM_VAR_TEST(f32);
+JTEST_ARM_VAR_TEST(q31);
+JTEST_ARM_VAR_TEST(q15);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(var_tests)
+{
+ /*
+ To skip a test, comment it out.
+ */
+ JTEST_TEST_CALL(arm_var_f32_test);
+ JTEST_TEST_CALL(arm_var_q31_test);
+ JTEST_TEST_CALL(arm_var_q15_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/copy_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/copy_tests.c
new file mode 100644
index 0000000..3804f63
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/copy_tests.c
@@ -0,0 +1,33 @@
+#include "jtest.h"
+#include "support_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "support_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_COPY_TEST(suffix) \
+ SUPPORT_DEFINE_TEST_TEMPLATE_BUF1_BLK( \
+ copy, \
+ suffix, \
+ TYPE_FROM_ABBREV(suffix), \
+ TYPE_FROM_ABBREV(suffix), \
+ SUPPORT_COMPARE_INTERFACE)
+
+JTEST_ARM_COPY_TEST(f32);
+JTEST_ARM_COPY_TEST(q31);
+JTEST_ARM_COPY_TEST(q15);
+JTEST_ARM_COPY_TEST(q7);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(copy_tests)
+{
+ JTEST_TEST_CALL(arm_copy_f32_test);
+ JTEST_TEST_CALL(arm_copy_q31_test);
+ JTEST_TEST_CALL(arm_copy_q15_test);
+ JTEST_TEST_CALL(arm_copy_q7_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/fill_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/fill_tests.c
new file mode 100644
index 0000000..fc5892d
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/fill_tests.c
@@ -0,0 +1,36 @@
+#include "jtest.h"
+#include "support_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "support_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_FILL_TEST(suffix) \
+ SUPPORT_DEFINE_TEST_TEMPLATE_ELT1_BLK( \
+ fill, \
+ suffix, \
+ TYPE_FROM_ABBREV(suffix), \
+ TYPE_FROM_ABBREV(suffix), \
+ SUPPORT_COMPARE_INTERFACE)
+
+JTEST_ARM_FILL_TEST(f32);
+JTEST_ARM_FILL_TEST(q31);
+JTEST_ARM_FILL_TEST(q15);
+JTEST_ARM_FILL_TEST(q7);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(fill_tests)
+{
+ /*
+ To skip a test, comment it out.
+ */
+ JTEST_TEST_CALL(arm_fill_f32_test);
+ JTEST_TEST_CALL(arm_fill_q31_test);
+ JTEST_TEST_CALL(arm_fill_q15_test);
+ JTEST_TEST_CALL(arm_fill_q7_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_common_data.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_common_data.c
new file mode 100644
index 0000000..f4b5911
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_common_data.c
@@ -0,0 +1,85 @@
+#include "arm_math.h"
+#include "support_test_data.h"
+
+#define MAX_INPUT_ELEMENTS 32
+#define BIGGEST_INPUT_TYPE float32_t
+
+/*--------------------------------------------------------------------------------*/
+/* Input/Output Buffers */
+/*--------------------------------------------------------------------------------*/
+
+ARR_DESC_DEFINE(BIGGEST_INPUT_TYPE,
+ support_output_fut,
+ MAX_INPUT_ELEMENTS,
+ CURLY(0));
+
+ARR_DESC_DEFINE(BIGGEST_INPUT_TYPE,
+ support_output_ref,
+ MAX_INPUT_ELEMENTS,
+ CURLY(0));
+
+/*--------------------------------------------------------------------------------*/
+/* Block Sizes */
+/*--------------------------------------------------------------------------------*/
+
+/*
+ To change test parameter values add/remove values inside CURLY and update
+ the preceeding parameter to reflect the number of values inside CURLY.
+*/
+
+ARR_DESC_DEFINE(uint32_t,
+ support_block_sizes,
+ 4,
+ CURLY( 2, 7, 15, 32));
+
+/*--------------------------------------------------------------------------------*/
+/* Numbers */
+/*--------------------------------------------------------------------------------*/
+
+ARR_DESC_DEFINE(uint32_t,
+ support_elts,
+ 4,
+ CURLY( 0, 1, 0x80000000, 0x7fffffff));
+
+/*--------------------------------------------------------------------------------*/
+/* Test Data */
+/*--------------------------------------------------------------------------------*/
+
+ARR_DESC_DEFINE(float32_t,
+ support_f_32,
+ 32,
+ CURLY(
+ 0.24865986 , -0.13364227, -0.27233250 , -7.33488200,
+ 0.42190653 , 1.17435880 , -0.49824914 , 0.87883663,
+ 0.63066370 , 1.80275680 , -84.83916000, -2.06773800,
+ 7.63452500 , 1.01487610 , -0.65785825 , 1.78019030,
+ -0.34160388, 0.68546050 , -1.81721590 , -0.10340453,
+ -4.48600340, -1.69763480, -1.26022340 , -1.58457480,
+ 0.51993870 , 2.83526470 , -0.21502694 , -0.57690346,
+ -0.22945681, 0.79509383 , 0.07275216 , -2.16279080
+ ));
+
+/* Alias the 32 element array with wrappers that end sooner. */
+ARR_DESC_DEFINE_SUBSET(support_f_15,
+ support_f_32,
+ 15);
+
+ARR_DESC_DEFINE_SUBSET(support_f_2,
+ support_f_32,
+ 2);
+
+ARR_DESC_DEFINE(float32_t,
+ support_zeros,
+ 32,
+ CURLY(0));
+
+/* Aggregate all float datasets. */
+ARR_DESC_DEFINE(ARR_DESC_t *,
+ support_f_all,
+ 4,
+ CURLY(
+ &support_zeros,
+ &support_f_2,
+ &support_f_15,
+ &support_f_32
+ ));
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_group.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_group.c
new file mode 100644
index 0000000..7cc2732
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_group.c
@@ -0,0 +1,10 @@
+#include "jtest.h"
+#include "support_tests.h"
+
+JTEST_DEFINE_GROUP(support_tests)
+{
+ JTEST_GROUP_CALL(copy_tests);
+ JTEST_GROUP_CALL(fill_tests);
+ JTEST_GROUP_CALL(x_to_y_tests);
+ return;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/x_to_y_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/x_to_y_tests.c
new file mode 100644
index 0000000..4667031
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/x_to_y_tests.c
@@ -0,0 +1,80 @@
+#include "jtest.h"
+#include "support_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h" /* FUTs */
+#include "ref.h" /* Reference Functions */
+#include "test_templates.h"
+#include "support_templates.h"
+#include "type_abbrev.h"
+
+/* Aliases to play nicely with templates. */
+#define arm_f32_to_q31 arm_float_to_q31
+#define arm_f32_to_q15 arm_float_to_q15
+#define arm_f32_to_q7 arm_float_to_q7
+#define arm_q31_to_f32 arm_q31_to_float
+#define arm_q15_to_f32 arm_q15_to_float
+#define arm_q7_to_f32 arm_q7_to_float
+#define ref_f32_to_q31 ref_float_to_q31
+#define ref_f32_to_q15 ref_float_to_q15
+#define ref_f32_to_q7 ref_float_to_q7
+#define ref_q31_to_f32 ref_q31_to_float
+#define ref_q15_to_f32 ref_q15_to_float
+#define ref_q7_to_f32 ref_q7_to_float
+
+#define JTEST_ARM_X_TO_Y_TEST(prefix, suffix) \
+ JTEST_DEFINE_TEST(arm_##prefix##_to_##suffix##_test, \
+ arm_##prefix##_to_##suffix) \
+ { \
+ TEST_TEMPLATE_BUF1_BLK( \
+ support_f_all, \
+ support_block_sizes, \
+ TYPE_FROM_ABBREV(prefix), \
+ TYPE_FROM_ABBREV(suffix), \
+ arm_##prefix##_to_##suffix, \
+ ARM_x_to_y_INPUT_INTERFACE, \
+ ref_##prefix##_to_##suffix, \
+ REF_x_to_y_INPUT_INTERFACE, \
+ SUPPORT_COMPARE_INTERFACE); \
+ }
+
+JTEST_ARM_X_TO_Y_TEST(f32, q31);
+JTEST_ARM_X_TO_Y_TEST(f32, q15);
+JTEST_ARM_X_TO_Y_TEST(f32, q7);
+
+JTEST_ARM_X_TO_Y_TEST(q31, f32);
+JTEST_ARM_X_TO_Y_TEST(q31, q15);
+JTEST_ARM_X_TO_Y_TEST(q31, q7);
+
+JTEST_ARM_X_TO_Y_TEST(q15, f32);
+JTEST_ARM_X_TO_Y_TEST(q15, q31);
+JTEST_ARM_X_TO_Y_TEST(q15, q7);
+
+JTEST_ARM_X_TO_Y_TEST(q7, f32);
+JTEST_ARM_X_TO_Y_TEST(q7, q31);
+JTEST_ARM_X_TO_Y_TEST(q7, q15);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(x_to_y_tests)
+{
+ /*
+ To skip a test, comment it out.
+ */
+ JTEST_TEST_CALL(arm_f32_to_q31_test);
+ JTEST_TEST_CALL(arm_f32_to_q15_test);
+ JTEST_TEST_CALL(arm_f32_to_q7_test);
+
+ JTEST_TEST_CALL(arm_q31_to_f32_test);
+ JTEST_TEST_CALL(arm_q31_to_q15_test);
+ JTEST_TEST_CALL(arm_q31_to_q7_test);
+
+ JTEST_TEST_CALL(arm_q15_to_f32_test);
+ JTEST_TEST_CALL(arm_q15_to_q31_test);
+ JTEST_TEST_CALL(arm_q15_to_q7_test);
+
+ JTEST_TEST_CALL(arm_q7_to_f32_test);
+ JTEST_TEST_CALL(arm_q7_to_q31_test);
+ JTEST_TEST_CALL(arm_q7_to_q15_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_family_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_family_tests.c
new file mode 100644
index 0000000..d3e775e
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_family_tests.c
@@ -0,0 +1,183 @@
+#include "jtest.h"
+#include "ref.h"
+#include "arr_desc.h"
+#include "transform_templates.h"
+#include "transform_test_data.h"
+#include "type_abbrev.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+#define CFFT_FN_NAME(fn_specifier, type_suffix) \
+ arm_cfft_##fn_specifier##_##type_suffix \
+
+#define CFFT_TEST_NAME(fn_specifier, type_suffix, config_suffix) \
+ arm_cfft_##fn_specifier##_##type_suffix##_##config_suffix##_test \
+
+/*--------------------------------------------------------------------------------*/
+/* Function Aliases */
+/*--------------------------------------------------------------------------------*/
+
+/* These aliases allow expansions in the CFFT_FAMILY_DEFINE_TEST() template to
+ make sense */
+#define arm_cfft_mag_init_f32 arm_cfft_radix4_init_f32
+#define arm_cfft_mag_init_q31 arm_cfft_radix4_init_q31
+#define arm_cfft_mag_init_q15 arm_cfft_radix4_init_q15
+#define arm_cfft_mag_instance_f32 arm_cfft_radix4_instance_f32
+#define arm_cfft_mag_instance_q31 arm_cfft_radix4_instance_q31
+#define arm_cfft_mag_instance_q15 arm_cfft_radix4_instance_q15
+#define transform_mag_fftlens transform_radix4_fftlens
+
+/*--------------------------------------------------------------------------------*/
+/* Test Definition */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Defines a test for the family of CFFT transforms.
+ *
+ * The family of CFFT transforms includes:
+ *
+ * - arm_cfft_radix4_xxx
+ * - arm_cfft_radix2_xxx
+ * - arm_cfft_mag_xxx
+ *
+ * Where xxx can be f32, q31, or q15.
+ *
+ * @param fn_specifier Allowed values: radix4, radix2, mag.
+ * @param type_suffix Allowed values: f32, q31, q15.
+ *
+ * @param config_suffix Used to differentiate test names based configuration
+ * (in this case whether the ifft_flag is set or not.)
+
+ * @param comparison_interface Macro name used to compare reference and fut
+ * outputs.
+ *
+ * @param output_tpe The type of variable contained in the output
+ * (e.g. float32_t, uint32_t, etc).
+ *
+ * @param ifft_flag Determines whether the arm_cfft_instance_xxx is configured
+ * for an inverse FFT.
+ */
+#define CFFT_FAMILY_DEFINE_TEST(fn_specifier, \
+ type_suffix, \
+ config_suffix, /* Delineate between test configs*/ \
+ comparison_interface, \
+ output_type, \
+ ifft_flag) \
+ JTEST_DEFINE_TEST(CFFT_TEST_NAME(fn_specifier, type_suffix, \
+ config_suffix), \
+ CFFT_FN_NAME(fn_specifier, type_suffix)) \
+ { \
+ arm_cfft_##fn_specifier##_instance_##type_suffix cfft_inst_fut; \
+ arm_cfft_##fn_specifier##_instance_##type_suffix cfft_inst_ref; \
+ \
+ TEMPLATE_DO_ARR_DESC( \
+ fftlen_idx, uint16_t, fftlen, transform_##fn_specifier##_fftlens \
+ , \
+ \
+ /* Initialize the cfft instance */ \
+ arm_cfft_##fn_specifier##_init_##type_suffix( \
+ &cfft_inst_fut, fftlen, ifft_flag, (uint8_t)1); \
+ arm_cfft_##fn_specifier##_init_##type_suffix( \
+ &cfft_inst_ref, fftlen, ifft_flag, (uint8_t)1); \
+ \
+ TRANSFORM_PREPARE_INPLACE_INPUTS( \
+ transform_fft_##type_suffix##_inputs, \
+ fftlen * \
+ sizeof(TYPE_FROM_ABBREV(type_suffix)) * \
+ 2 /*complex_inputs*/); \
+ \
+ /* Display parameter values */ \
+ JTEST_DUMP_STRF("Block Size: %d\n" \
+ "Inverse-transform flag: %d\n", \
+ (int)fftlen, \
+ (int)ifft_flag); \
+ \
+ /* Display cycle count and run test */ \
+ JTEST_COUNT_CYCLES( \
+ arm_cfft_##fn_specifier##_##type_suffix( \
+ &cfft_inst_fut, \
+ (void*) transform_fft_inplace_input_fut)); \
+ \
+ ref_cfft_##fn_specifier##_##type_suffix( \
+ &cfft_inst_ref, \
+ (void *) transform_fft_inplace_input_ref); \
+ \
+ /* Test correctness */ \
+ comparison_interface( \
+ fftlen, \
+ output_type)); \
+ \
+ return JTEST_TEST_PASSED; \
+ }
+
+/**
+ * Bulk wrapper for all tests instantiated using #CFFT_FAMILY_DEFINE_TEST().
+ *
+ * This macro allows several test definitions to share the same config_suffix
+ * and ifft_flag settings.
+ */
+#define CFFT_FAMILY_DEFINE_ALL_TESTS(config_suffix, ifft_flag) \
+ /* Radix2 tests*/ \
+ CFFT_FAMILY_DEFINE_TEST(radix2, q31, config_suffix, \
+ TRANSFORM_SNR_COMPARE_CMPLX_INTERFACE, \
+ TYPE_FROM_ABBREV(q31), \
+ ifft_flag); \
+ CFFT_FAMILY_DEFINE_TEST(radix2, q15, config_suffix, \
+ TRANSFORM_SNR_COMPARE_CMPLX_INTERFACE, \
+ TYPE_FROM_ABBREV(q15), \
+ ifft_flag); \
+ /* Radix4 tests*/ \
+ CFFT_FAMILY_DEFINE_TEST(radix4, q31, config_suffix, \
+ TRANSFORM_SNR_COMPARE_CMPLX_INTERFACE, \
+ TYPE_FROM_ABBREV(q31), \
+ ifft_flag); \
+ CFFT_FAMILY_DEFINE_TEST(radix4, q15, config_suffix, \
+ TRANSFORM_SNR_COMPARE_CMPLX_INTERFACE, \
+ TYPE_FROM_ABBREV(q15), \
+ ifft_flag)
+ /* /\* Mag tests*\/ \ */
+ /* CFFT_FAMILY_DEFINE_TEST(mag, f32, config_suffix, \ */
+ /* TRANSFORM_SNR_COMPARE_INTERFACE, \ */
+ /* TYPE_FROM_ABBREV(f32), \ */
+ /* ifft_flag); \ */
+ /* CFFT_FAMILY_DEFINE_TEST(mag, q31, config_suffix, \ */
+ /* TRANSFORM_SNR_COMPARE_INTERFACE, \ */
+ /* TYPE_FROM_ABBREV(q31), \ */
+ /* ifft_flag); \ */
+ /* CFFT_FAMILY_DEFINE_TEST(mag, q15, config_suffix, \ */
+ /* TRANSFORM_SNR_COMPARE_INTERFACE, \ */
+ /* TYPE_FROM_ABBREV(q15), \ */
+ /* ifft_flag) */
+
+CFFT_FAMILY_DEFINE_ALL_TESTS(forward, 0U);
+CFFT_FAMILY_DEFINE_ALL_TESTS(inverse, 1U);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(cfft_family_tests)
+{
+ /* Forward FFT tests */
+ JTEST_TEST_CALL(arm_cfft_radix2_q31_forward_test);
+ JTEST_TEST_CALL(arm_cfft_radix2_q15_forward_test);
+ JTEST_TEST_CALL(arm_cfft_radix4_q31_forward_test);
+ JTEST_TEST_CALL(arm_cfft_radix4_q15_forward_test);
+
+ /* Inverse FFT Tests */
+ JTEST_TEST_CALL(arm_cfft_radix2_q31_inverse_test);
+ JTEST_TEST_CALL(arm_cfft_radix2_q15_inverse_test);
+ JTEST_TEST_CALL(arm_cfft_radix4_q31_inverse_test);
+ JTEST_TEST_CALL(arm_cfft_radix4_q15_inverse_test);
+
+ /* Magnitude tests removed from the DSP Library. Keeping them here in case
+ minds are changed. */
+ /* JTEST_TEST_CALL(arm_cfft_mag_f32_forward_test); */
+ /* JTEST_TEST_CALL(arm_cfft_mag_q31_forward_test); */
+ /* JTEST_TEST_CALL(arm_cfft_mag_q15_forward_test); */
+ /* JTEST_TEST_CALL(arm_cfft_mag_f32_inverse_test); */
+ /* JTEST_TEST_CALL(arm_cfft_mag_q31_inverse_test); */
+ /* JTEST_TEST_CALL(arm_cfft_mag_q15_inverse_test); */
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_tests.c
new file mode 100644
index 0000000..f26c6f6
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_tests.c
@@ -0,0 +1,144 @@
+#include "jtest.h"
+#include "ref.h"
+#include "arr_desc.h"
+#include "transform_templates.h"
+#include "transform_test_data.h"
+
+#define CFFT_SNR_THRESHOLD 120
+
+/*
+ CFFT function test template. Arguments are: inverse-transform flag, function
+ suffix (q7/q15/q31/f32) and the output type (q7_t, q15_t, q31_t, float32_t)
+*/
+#define CFFT_TEST_BODY(ifft_flag, suffix, output_type) \
+ do \
+ { \
+ /* Go through all arm_cfft_instances */ \
+ TEMPLATE_DO_ARR_DESC( \
+ cfft_inst_idx, const arm_cfft_instance_##suffix *, cfft_inst_ptr, \
+ transform_cfft_##suffix##_structs \
+ , \
+ \
+ TRANSFORM_PREPARE_INPLACE_INPUTS( \
+ transform_fft_##suffix##_inputs, \
+ cfft_inst_ptr->fftLen * \
+ sizeof(output_type) * \
+ 2 /*complex_inputs*/); \
+ \
+ /* Display parameter values */ \
+ JTEST_DUMP_STRF("Block Size: %d\n" \
+ "Inverse-transform flag: %d\n", \
+ (int)cfft_inst_ptr->fftLen, \
+ (int)ifft_flag); \
+ \
+ /* Display cycle count and run test */ \
+ JTEST_COUNT_CYCLES( \
+ arm_cfft_##suffix(cfft_inst_ptr, \
+ (void *) transform_fft_inplace_input_fut, \
+ ifft_flag, /* IFFT Flag */ \
+ 1)); /* Bitreverse flag */ \
+ ref_cfft_##suffix(cfft_inst_ptr, \
+ (void *) transform_fft_inplace_input_ref, \
+ ifft_flag, /* IFFT Flag */ \
+ 1); /* Bitreverse flag */ \
+ \
+ /* Test correctness */ \
+ TRANSFORM_SNR_COMPARE_CMPLX_INTERFACE( \
+ cfft_inst_ptr->fftLen, \
+ output_type)); \
+ \
+ return JTEST_TEST_PASSED; \
+ } while (0)
+
+
+/*
+ CFFT function with downshift test template. Arguments are: inverse-transform flag,
+ function suffix (q7/q15/q31/f32) and the output type (q7_t, q15_t, q31_t, float32_t)
+*/
+#define CFFT_DOWNSHIFT_INPUT_TEST_BODY(ifft_flag, suffix, output_type) \
+ do \
+ { \
+ /* Go through all arm_cfft_instances */ \
+ TEMPLATE_DO_ARR_DESC( \
+ cfft_inst_idx, const arm_cfft_instance_##suffix *, cfft_inst_ptr, \
+ transform_cfft_##suffix##_structs \
+ , \
+ \
+ TRANSFORM_PREPARE_INPLACE_INPUTS_DOWNSHIFT( \
+ transform_fft_##suffix##_inputs, \
+ cfft_inst_ptr->fftLen * \
+ sizeof(output_type) * \
+ 2 /*complex_inputs*/, output_type); \
+ \
+ /* Display parameter values */ \
+ JTEST_DUMP_STRF("Block Size: %d\n" \
+ "Inverse-transform flag: %d\n", \
+ (int)cfft_inst_ptr->fftLen, \
+ (int)ifft_flag); \
+ \
+ /* Display cycle count and run test */ \
+ JTEST_COUNT_CYCLES( \
+ arm_cfft_##suffix(cfft_inst_ptr, \
+ (void *) transform_fft_inplace_input_fut, \
+ ifft_flag, /* IFFT Flag */ \
+ 1)); /* Bitreverse flag */ \
+ ref_cfft_##suffix(cfft_inst_ptr, \
+ (void *) transform_fft_inplace_input_ref, \
+ ifft_flag, /* IFFT Flag */ \
+ 1); /* Bitreverse flag */ \
+ \
+ /* Test correctness */ \
+ TRANSFORM_SNR_COMPARE_CMPLX_INTERFACE( \
+ cfft_inst_ptr->fftLen, \
+ output_type)); \
+ \
+ return JTEST_TEST_PASSED; \
+ } while (0)
+
+
+/* Test declarations */
+JTEST_DEFINE_TEST(cfft_f32_test, cfft_f32)
+{
+ CFFT_TEST_BODY((uint8_t) 0, f32, float32_t);
+}
+
+JTEST_DEFINE_TEST(cfft_f32_ifft_test, cfft_f32)
+{
+ CFFT_TEST_BODY((uint8_t) 1, f32, float32_t);
+}
+
+JTEST_DEFINE_TEST(cfft_q31_test, cfft_q31)
+{
+ CFFT_TEST_BODY((uint8_t) 0, q31, q31_t);
+}
+
+JTEST_DEFINE_TEST(cfft_q31_ifft_test, cfft_q31)
+{
+ CFFT_TEST_BODY((uint8_t) 1, q31, q31_t);
+}
+
+JTEST_DEFINE_TEST(cfft_q15_test, cfft_q15)
+{
+ CFFT_TEST_BODY((uint8_t) 0, q15, q15_t);
+}
+
+JTEST_DEFINE_TEST(cfft_q15_ifft_test, cfft_q15)
+{
+ CFFT_TEST_BODY((uint8_t) 1, q15, q15_t);
+}
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(cfft_tests)
+{
+ JTEST_TEST_CALL(cfft_f32_test);
+ JTEST_TEST_CALL(cfft_f32_ifft_test);
+
+ JTEST_TEST_CALL(cfft_q31_test);
+ JTEST_TEST_CALL(cfft_q31_ifft_test);
+
+ JTEST_TEST_CALL(cfft_q15_test);
+ JTEST_TEST_CALL(cfft_q15_ifft_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/dct4_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/dct4_tests.c
new file mode 100644
index 0000000..aae5a42
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/dct4_tests.c
@@ -0,0 +1,197 @@
+#include "jtest.h"
+#include "ref.h"
+#include "arm_math.h"
+#include "arr_desc.h"
+#include "transform_templates.h"
+#include "transform_test_data.h"
+#include "type_abbrev.h"
+#include <math.h> /* sqrtf() */
+
+/*--------------------------------------------------------------------------------*/
+/* Aliases to aid macro expansion */
+/*--------------------------------------------------------------------------------*/
+#define ref_sqrt_f32(x) sqrtf(x)
+
+/*--------------------------------------------------------------------------------*/
+/* Test Definitions */
+/*--------------------------------------------------------------------------------*/
+
+/*
+DCT function test template. Arguments are: function configuration suffix
+(q7/q15/q31/f32) and input type (q7_t/q15_t/q31_t/float32_t)
+*/
+#define DCT4_DEFINE_TEST(suffix, input_type) \
+ JTEST_DEFINE_TEST(arm_dct4_##suffix##_test, arm_dct4_##suffix) \
+ { \
+ CONCAT(arm_dct4_instance_,suffix) dct4_inst_fut = {0}; \
+ CONCAT(arm_rfft_instance_,suffix) rfft_inst_fut = {0}; \
+ CONCAT(arm_cfft_radix4_instance_,suffix) cfft_inst_fut = {0}; \
+ \
+ CONCAT(arm_dct4_instance_,suffix) dct4_inst_ref = {0}; \
+ CONCAT(arm_rfft_instance_,suffix) rfft_inst_ref = {0}; \
+ CONCAT(arm_cfft_radix4_instance_,suffix) cfft_inst_ref = {0}; \
+ \
+ /* Go through all dct lengths */ \
+ TEMPLATE_DO_ARR_DESC( \
+ fftlen_idx, uint16_t, fftlen, transform_dct_fftlens \
+ , \
+ \
+ float32_t normalize_f32 = \
+ ref_sqrt_f32((2.0f/(float32_t)fftlen)); \
+ input_type normalize; \
+ \
+ /* Calculate normalized DCT4 value for input_type. */ \
+ TEST_CONVERT_FLOAT_TO(&normalize_f32, &normalize, \
+ 1, input_type); \
+ \
+ /* Initialize the DCT4, RFFT, and CFFT instances */ \
+ arm_dct4_init_##suffix( \
+ &dct4_inst_fut, &rfft_inst_fut, &cfft_inst_fut, \
+ fftlen, \
+ fftlen/2, \
+ normalize); \
+ \
+ arm_dct4_init_##suffix( \
+ &dct4_inst_ref, &rfft_inst_ref, &cfft_inst_ref, \
+ fftlen, \
+ fftlen/2, \
+ normalize); \
+ \
+ memset( transform_fft_input_fut,0, \
+ fftlen*sizeof(input_type)); \
+ \
+ TRANSFORM_PREPARE_INPLACE_INPUTS( \
+ transform_fft_##suffix##_inputs, \
+ fftlen * sizeof(input_type)); \
+ \
+ /* Display parameter values */ \
+ JTEST_DUMP_STRF("Block Size: %d\n", \
+ (int)fftlen); \
+ \
+ /* Input provided as a scratch buffer. Inplace input is \
+ * actual input. Display cycle count and run test*/ \
+ JTEST_COUNT_CYCLES( \
+ arm_dct4_##suffix( \
+ &dct4_inst_fut, \
+ (void *) transform_fft_input_fut, \
+ (void *) transform_fft_inplace_input_fut)); \
+ \
+ memset( transform_fft_input_ref,0, \
+ fftlen*sizeof(input_type)); \
+ \
+ /* Input provided as a scratch buffer. Inplace input is */ \
+ /* actual input. */ \
+ ref_dct4_##suffix( \
+ &dct4_inst_ref, \
+ (void *) transform_fft_input_ref, \
+ (void *) transform_fft_inplace_input_ref); \
+ \
+ /* Test correctness */ \
+ DCT_TRANSFORM_SNR_COMPARE_INTERFACE( \
+ fftlen, \
+ input_type)); \
+ \
+ return JTEST_TEST_PASSED; \
+ }
+
+/*
+ DCT function test template for fixed point data. Arguments are: function
+ suffix (q7/q15/q31/f32), input type (q7_t/q15_t/q31_t/float32_t) and prefix
+ (dct_4)
+*/
+#define DCT4_FIXED_POINT_DEFINE_TEST(suffix, input_type, prefix) \
+ JTEST_DEFINE_TEST(arm_dct4_##suffix##_test, arm_dct4_##suffix) \
+ { \
+ CONCAT(arm_dct4_instance_,suffix) dct4_inst_fut = {0}; \
+ CONCAT(arm_rfft_instance_,suffix) rfft_inst_fut = {0}; \
+ CONCAT(arm_cfft_radix4_instance_,suffix) cfft_inst_fut = {0}; \
+ \
+ CONCAT(arm_dct4_instance_,suffix) dct4_inst_ref = {0}; \
+ CONCAT(arm_rfft_instance_,suffix) rfft_inst_ref = {0}; \
+ CONCAT(arm_cfft_radix4_instance_,suffix) cfft_inst_ref = {0}; \
+ \
+ TEMPLATE_DO_ARR_DESC( \
+ fftlen_idx, uint16_t, fftlen, transform_dct_fftlens \
+ , \
+ uint32_t i; \
+ float32_t normalize_f32 = \
+ ref_sqrt_f32((2.0f/(float32_t)fftlen)); \
+ input_type normalize; \
+ \
+ /* Calculate normalized DCT4 value for input_type. */ \
+ TEST_CONVERT_FLOAT_TO(&normalize_f32, &normalize, \
+ 1, input_type); \
+ \
+ /* Initialize the DCT4, RFFT, and CFFT instances */ \
+ arm_dct4_init_##suffix( \
+ &dct4_inst_fut, &rfft_inst_fut, &cfft_inst_fut, \
+ fftlen, \
+ fftlen/2, \
+ normalize); \
+ \
+ arm_dct4_init_##suffix( \
+ &dct4_inst_ref, &rfft_inst_ref, &cfft_inst_ref, \
+ fftlen, \
+ fftlen/2, \
+ normalize); \
+ \
+ /* Input samples need to be downscaled by 1 bit to \
+ * avoid saturations in the Q31 DCT process, \
+ * as the conversion from DCT2 to DCT4 involves \
+ * one subtraction. \
+ */ \
+ for(i=0; i < fftlen; i++) \
+ { \
+ ((input_type*)transform_fft_inplace_input_fut)[i] = \
+ prefix##transform_fft_##suffix##_inputs[i] >> 1; \
+ ((input_type*)transform_fft_inplace_input_ref)[i] = \
+ prefix##transform_fft_##suffix##_inputs[i] >> 1; \
+ } \
+ \
+ memset( transform_fft_input_fut,0, \
+ fftlen*sizeof(input_type)); \
+ \
+ /* Display test parameter values */ \
+ JTEST_DUMP_STRF("Block Size: %d\n", \
+ (int)fftlen); \
+ \
+ /* Input provided as a scratch buffer. Inplace input is \
+ * actual input. */ \
+ JTEST_COUNT_CYCLES( \
+ arm_dct4_##suffix( \
+ &dct4_inst_fut, \
+ (void *) transform_fft_input_fut, \
+ (void *) transform_fft_inplace_input_fut)); \
+ \
+ memset( transform_fft_input_ref,0, \
+ fftlen*sizeof(input_type)); \
+ \
+ /* Input provided as a scratch buffer. Inplace input is */ \
+ /* actual input. */ \
+ ref_dct4_##suffix( \
+ &dct4_inst_ref, \
+ (void *) transform_fft_input_ref, \
+ (void *) transform_fft_inplace_input_ref); \
+ \
+ /* Test correctness */ \
+ DCT_TRANSFORM_SNR_COMPARE_INTERFACE( \
+ fftlen, \
+ input_type)); \
+ \
+ return JTEST_TEST_PASSED; \
+ }
+
+DCT4_DEFINE_TEST(f32, float32_t);
+DCT4_FIXED_POINT_DEFINE_TEST(q31, q31_t,);
+DCT4_FIXED_POINT_DEFINE_TEST(q15, q15_t, dct4_);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(dct4_tests)
+{
+ JTEST_TEST_CALL(arm_dct4_f32_test);
+ JTEST_TEST_CALL(arm_dct4_q31_test);
+ JTEST_TEST_CALL(arm_dct4_q15_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_fast_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_fast_tests.c
new file mode 100644
index 0000000..d8a8e17
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_fast_tests.c
@@ -0,0 +1,75 @@
+#include "jtest.h"
+#include "ref.h"
+#include "arr_desc.h"
+#include "transform_templates.h"
+#include "transform_test_data.h"
+#include "type_abbrev.h"
+
+/*
+FFT fast function test template. Arguments are: function configuration suffix
+(q7/q15/q31/f32) and inverse-transform flag
+*/
+#define RFFT_FAST_DEFINE_TEST(config_suffix, ifft_flag) \
+ JTEST_DEFINE_TEST(arm_rfft_fast_f32_##config_suffix##_test, \
+ arm_fft_f32) \
+ { \
+ arm_rfft_fast_instance_f32 rfft_inst_fut = {{0}, 0, 0}; \
+ arm_rfft_fast_instance_f32 rfft_inst_ref = {{0}, 0, 0}; \
+ \
+ /* Go through all FFT lengths */ \
+ TEMPLATE_DO_ARR_DESC( \
+ fftlen_idx, uint16_t, fftlen, transform_rfft_fast_fftlens \
+ , \
+ \
+ /* Initialize the RFFT and CFFT Instances */ \
+ arm_rfft_fast_init_f32( \
+ &rfft_inst_fut, fftlen); \
+ \
+ arm_rfft_fast_init_f32( \
+ &rfft_inst_ref, fftlen); \
+ \
+ TRANSFORM_COPY_INPUTS( \
+ transform_fft_f32_inputs, \
+ fftlen * \
+ sizeof(float32_t)); \
+ \
+ /* Display parameter values */ \
+ JTEST_DUMP_STRF("Block Size: %d\n" \
+ "Inverse-transform flag: %d\n", \
+ (int)fftlen, \
+ (int)ifft_flag); \
+ \
+ /* Display cycle count and run test */ \
+ JTEST_COUNT_CYCLES( \
+ arm_rfft_fast_f32( \
+ &rfft_inst_fut, \
+ (void *) transform_fft_input_fut, \
+ (void *) transform_fft_output_fut, \
+ ifft_flag)); \
+ \
+ ref_rfft_fast_f32( \
+ &rfft_inst_ref, \
+ (void *) transform_fft_input_ref, \
+ (void *) transform_fft_output_ref, \
+ ifft_flag); \
+ \
+ /* Test correctness */ \
+ TRANSFORM_SNR_COMPARE_INTERFACE( \
+ fftlen, \
+ float32_t)); \
+ \
+ return JTEST_TEST_PASSED; \
+ }
+
+RFFT_FAST_DEFINE_TEST(forward, 0U);
+RFFT_FAST_DEFINE_TEST(inverse, 1U);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(rfft_fast_tests)
+{
+ JTEST_TEST_CALL(arm_rfft_fast_f32_forward_test);
+ JTEST_TEST_CALL(arm_rfft_fast_f32_inverse_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_tests.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_tests.c
new file mode 100644
index 0000000..6fbc8e6
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_tests.c
@@ -0,0 +1,94 @@
+#include "jtest.h"
+#include "ref.h"
+#include "arr_desc.h"
+#include "transform_templates.h"
+#include "transform_test_data.h"
+#include "type_abbrev.h"
+
+/*
+ FFT function test template. Arguments are: function suffix (q7/q15/q31/f32)
+ function configuration suffix (same as function suffix), inverse-transform flag,
+ input and output type (both q7_t/q15_t/q31_t/float32_t)
+*/
+#define RFFT_DEFINE_TEST(suffix, config_suffix, \
+ ifft_flag, input_type, output_type) \
+ JTEST_DEFINE_TEST(arm_rfft_##suffix##_##config_suffix##_test, \
+ arm_rfft_##suffix) \
+ { \
+ CONCAT(arm_rfft_instance_, suffix) rfft_inst_fut = {0}; \
+ CONCAT(arm_rfft_instance_, suffix) rfft_inst_ref = {0}; \
+ \
+ /* Go through all arm_rfft lengths */ \
+ TEMPLATE_DO_ARR_DESC( \
+ fftlen_idx, uint16_t, fftlen, transform_rfft_fftlens \
+ , \
+ \
+ /* Initialize the RFFT and CFFT Instances */ \
+ arm_rfft_init_##suffix( \
+ &rfft_inst_fut, \
+ (uint32_t) fftlen, ifft_flag, 1U); \
+ \
+ arm_rfft_init_##suffix( \
+ &rfft_inst_ref, \
+ (uint32_t) fftlen, ifft_flag, 1U); \
+ \
+ if (ifft_flag) \
+ { \
+ TRANSFORM_PREPARE_INVERSE_INPUTS( \
+ transform_fft_##suffix##_inputs, \
+ fftlen, input_type, \
+ fftlen * \
+ sizeof(input_type)); \
+ } \
+ else \
+ { \
+ TRANSFORM_COPY_INPUTS( \
+ transform_fft_##suffix##_inputs, \
+ fftlen * \
+ sizeof(input_type)); \
+ } \
+ \
+ /* Display parameter values */ \
+ JTEST_DUMP_STRF("Block Size: %d\n" \
+ "Inverse-transform flag: %d\n", \
+ (int)fftlen, \
+ (int)ifft_flag); \
+ \
+ /* Display cycle count and run test */ \
+ JTEST_COUNT_CYCLES( \
+ arm_rfft_##suffix( \
+ &rfft_inst_fut, \
+ (void *) transform_fft_input_fut, \
+ (void *) transform_fft_output_fut)); \
+ \
+ ref_rfft_##suffix( \
+ &rfft_inst_ref, \
+ (void *) transform_fft_input_ref, \
+ (void *) transform_fft_output_ref); \
+ \
+ /* Test correctness */ \
+ TRANSFORM_SNR_COMPARE_INTERFACE( \
+ fftlen, \
+ output_type)); \
+ \
+ return JTEST_TEST_PASSED; \
+ }
+
+RFFT_DEFINE_TEST(q31, forward, 0U, TYPE_FROM_ABBREV(q31), TYPE_FROM_ABBREV(q31));
+RFFT_DEFINE_TEST(q15, forward, 0U, TYPE_FROM_ABBREV(q15), TYPE_FROM_ABBREV(q15));
+//RFFT_DEFINE_TEST(f32, inverse, 1U, TYPE_FROM_ABBREV(f32), TYPE_FROM_ABBREV(f32));
+RFFT_DEFINE_TEST(q31, inverse, 1U, TYPE_FROM_ABBREV(q31), TYPE_FROM_ABBREV(q31));
+RFFT_DEFINE_TEST(q15, inverse, 1U, TYPE_FROM_ABBREV(q15), TYPE_FROM_ABBREV(q15));
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(rfft_tests)
+{
+ JTEST_TEST_CALL(arm_rfft_q31_forward_test);
+ JTEST_TEST_CALL(arm_rfft_q15_forward_test);
+ //JTEST_TEST_CALL(arm_rfft_f32_inverse_test);
+ JTEST_TEST_CALL(arm_rfft_q31_inverse_test);
+ JTEST_TEST_CALL(arm_rfft_q15_inverse_test);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/transform_test_group.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/transform_test_group.c
new file mode 100644
index 0000000..f071068
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/transform_test_group.c
@@ -0,0 +1,11 @@
+#include "jtest.h"
+#include "transform_tests.h"
+
+JTEST_DEFINE_GROUP(transform_tests)
+{
+ JTEST_GROUP_CALL(cfft_tests);
+ JTEST_GROUP_CALL(cfft_family_tests);
+ JTEST_GROUP_CALL(rfft_tests);
+ JTEST_GROUP_CALL(rfft_fast_tests);
+ JTEST_GROUP_CALL(dct4_tests);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/transform_tests_common_data.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/transform_tests_common_data.c
new file mode 100644
index 0000000..98987b3
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/transform_tests_common_data.c
@@ -0,0 +1,3311 @@
+#include "transform_test_data.h"
+#include "arm_const_structs.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Input/Output Buffers */
+/*--------------------------------------------------------------------------------*/
+
+float32_t transform_fft_output_fut[TRANSFORM_MAX_FFT_LEN * 2] = {0};
+float32_t transform_fft_output_ref[TRANSFORM_MAX_FFT_LEN * 2] = {0};
+float32_t transform_fft_input_fut[TRANSFORM_MAX_FFT_LEN * 2] = {0};
+float32_t transform_fft_input_ref[TRANSFORM_MAX_FFT_LEN * 2] = {0};
+float32_t transform_fft_output_f32_fut[TRANSFORM_MAX_FFT_LEN * 2] = {0};
+float32_t transform_fft_output_f32_ref[TRANSFORM_MAX_FFT_LEN * 2] = {0};
+
+/* Some of the transform function modify their inputs in-place, so that they
+ * become the outputs. */
+float32_t * transform_fft_inplace_input_fut = transform_fft_output_fut;
+float32_t * transform_fft_inplace_input_ref = transform_fft_output_ref;
+
+q31_t transform_fft_q31_inputs[TRANSFORM_MAX_FFT_LEN * 2] =
+{
+ 0xC14A5524, 0xCCABDA17, 0xAD6F5B56, 0xFDAFCE3B, 0xA9B226EB,
+ 0x41F6F6A, 0xA5CE38BF, 0x3A978AFA, 0xBA44B82A, 0x855C0F8,
+ 0x3D060524, 0x93D5E570, 0x97D7791D, 0xFFE0C38C, 0x26749841,
+ 0xC0A6EE54, 0x218EC386, 0x39FF3726, 0x8DC1F7CA, 0x702F2CF5,
+ 0xC1142FF1, 0xEC1476AB, 0x15F640DD, 0xE62CCE49, 0x3805DE7E,
+ 0xF70871FE, 0xCF8BD360, 0x8D19A8A0, 0xD764F821, 0xA58558CF,
+ 0x8C0CE04D, 0x50A46C19, 0x66D2370D, 0x50FA359A, 0xB646AE24,
+ 0x6CE00F5C, 0xE6D48948, 0xB55BD831, 0x3B72950A, 0x9EB69530,
+ 0x73394127, 0x773FA6F4, 0x9805A980, 0x838DE587, 0x9CF597F4,
+ 0xA2AD1691, 0xFA81A473, 0x7CDC7D7F, 0x4A5190D0, 0xED895BB9,
+ 0x8FD60F35, 0x1A21D530, 0xA0EB6DDA, 0xBDE6A516, 0x2501A3E1,
+ 0x5ED893C8, 0xE1E175B1, 0xACBBB2F3, 0xED350907, 0xDB140D7E,
+ 0xEEAE272D, 0xBE229841, 0xC18BFB88, 0xA6BB9B80, 0xBCF090E4,
+ 0x24DB166C, 0xF9AB7E42, 0x62DF28D1, 0xC7004665, 0xE3F56FC6,
+ 0x419E0C75, 0x46BE9F38, 0x2432B9B2, 0x758D83E0, 0xDCE12926,
+ 0x3F57CB74, 0x1F4458E2, 0xF1DD639, 0x83A1FB49, 0x173AFC76,
+ 0x86EF7531, 0x48D32F34, 0x7D3E3063, 0x8F2FB549, 0x5C314C9,
+ 0x18CBEB6D, 0xA6F8B697, 0x447B9E9C, 0x2E32BA33, 0xD074D715,
+ 0x81ACD746, 0xE55A4E04, 0x4891860F, 0x1DA3EB4F, 0xE0E6A27F,
+ 0x20BFDEB4, 0xD0B3A25B, 0x40C10544, 0xC15656C, 0x15405EAE,
+ 0x9858E3E1, 0xA36A9C4E, 0x88BD21F9, 0xAACF7A68, 0x773665E5,
+ 0xCEDFDF66, 0x617A9610, 0x524FC968, 0xC2D086CD, 0x5F008079,
+ 0x24DCA447, 0x6A4F5599, 0xB706CD4A, 0x1DE70608, 0xA33A2EE5,
+ 0x137E488E, 0x98061B7B, 0x4079D69D, 0xA4A897D5, 0xC4CEC8F5,
+ 0xD75F7883, 0x22406802, 0xF1AD70BB, 0x9D4ADD79, 0xBCBC7CE4,
+ 0xB358C0D8, 0x85792E47, 0xA7ADAC05, 0x3D19EEAB, 0x331AC0AF,
+ 0x33035831, 0x13D93987, 0xFC542094, 0x845F317E, 0xDDC4BF8B,
+ 0x1379E50C, 0x5C20193F, 0xFDD58298, 0x9D482B82, 0x4A6BE062,
+ 0xDC8A757B, 0x272917C1, 0x90E1EFBC, 0x355AD882, 0xE6F8EA35,
+ 0x604555A1, 0x7DFFFBB, 0xF58AE216, 0x9A11B463, 0xD3541BAD,
+ 0xA1576756, 0x483BED8D, 0x1F05AFCC, 0xCEA63DFB, 0x55B84677,
+ 0xFB2E04F2, 0x787AF96C, 0x84A12CD3, 0x460A9BD, 0x9DB22DD8,
+ 0x1A8C7F28, 0x861E452E, 0x932D3F78, 0x7652D852, 0x73357BBA,
+ 0xEBBB0A58, 0x62536AFA, 0x3F6B65EF, 0x6DC57B58, 0x9EB798CE,
+ 0xE6B0A740, 0xDFF68B47, 0x3247FB8F, 0xFFF3D302, 0xA9FD3E40,
+ 0x475A43D1, 0x6FF9528A, 0x2018A09D, 0x47E0F9C9, 0x4CF5F6D3,
+ 0x2807CE34, 0xDD6FD8ED, 0x234045D1, 0x51CEB5F9, 0x25297896,
+ 0x6443A0FE, 0x8F4449A9, 0xD4C3E1C6, 0xF01D52F1, 0x4E09C820,
+ 0xF18F0810, 0xE1548689, 0xF9DE5A1F, 0x5286DC23, 0x48AC3A4B,
+ 0xEA0C1BE0, 0xA1B785DB, 0x7086465D, 0x1CC10929, 0x1E1D716E,
+ 0xED231D4C, 0x2049D108, 0xB8FF9971, 0x949CF8D4, 0x441F1E8B,
+ 0xC3D95372, 0x69C324B4, 0xA10BFDC9, 0xC781DE78, 0x82476137,
+ 0xE163DDF, 0x390DEEC2, 0xAF68CE5B, 0x8E680ABD, 0x8223A615,
+ 0x92593380, 0x7B1465FE, 0x865AE957, 0x930F53EB, 0xED772EF7,
+ 0x10E916B6, 0xE3BCFA68, 0x2ACB80BB, 0xE51C5590, 0x994714B5,
+ 0xF30984EE, 0x59BBE1B4, 0xB4867DBC, 0xB91C706C, 0xBC16C218,
+ 0xA8931CD0, 0x129A66AB, 0x13171F4D, 0x62882872, 0x4B167FD4,
+ 0xE6902F4C, 0xFA794932, 0xD4B152C, 0xB0856EA9, 0x39466D55,
+ 0x3669E451, 0x8F5B9E8C, 0x877A3C6A, 0x51B956B4, 0x367EAD2A,
+ 0x9D2C662A, 0x78FB6880, 0x4E6D40B6, 0x4070EFDC, 0x4DF9679C,
+ 0x20306EDB, 0xE381AAE7, 0xA55DA748, 0x9B8B617B, 0x3E036FAD,
+ 0x84E4C4A7, 0xD5A3F517, 0x669BA988, 0x98FDDE8C, 0x67BD85CE,
+ 0x34BBB46C, 0x76994800, 0x85B9D8B6, 0x6DFA2FEF, 0x205DB5C,
+ 0x9F843C4C, 0x72721B52, 0x73EF6B86, 0x5FB98B61, 0xC323DDAC,
+ 0x31D424B4, 0xF68C0D7E, 0x162FAF9D, 0x7B2A7A99, 0xF9392693,
+ 0xC42D12C0, 0x8692A73E, 0xD9A1EE80, 0xDD956856, 0x44E7BDAC,
+ 0x8D874532, 0x5F5C9DD0, 0x5D167858, 0x8559FEA2, 0x9D821476,
+ 0xD9654ED2, 0x594C0DC7, 0x1A87B506, 0x3F693200, 0x7A651AB5,
+ 0xA0CCBC8A, 0x9F9E662C, 0x78EF631, 0x2A09DA0, 0xB088C72F,
+ 0x92EE0D42, 0x360DCD5F, 0xF333FE48, 0x8D63CC06, 0x233A8ACB,
+ 0x706651ED, 0x7AA5C079, 0x262239D1, 0x3EBBEBB6, 0xA25A4F3D,
+ 0x32581A06, 0x6E6FD780, 0x5773F7C7, 0x75ED1DDC, 0x90DF2D15,
+ 0xBC79A9BC, 0xB7175917, 0x354E381C, 0x762AADD7, 0xF643DAC1,
+ 0xF3BBF49E, 0xD2FECE7E, 0x6C8140F4, 0xD7694875, 0x92D30822,
+ 0xC742A7CF, 0xB792ED98, 0x121CFE24, 0xA04E1EE7, 0x58CE268,
+ 0x215A080, 0x316CB323, 0xFAB14A31, 0xE1C13C03, 0xFD8EF4F1,
+ 0xF3F446D0, 0x6C6CEA0A, 0xBBFDF9FB, 0x67242969, 0xBE55A4EB,
+ 0x8FF5534, 0x52F0DF1C, 0x9710ADE3, 0xD40F4A21, 0x7984E8E7,
+ 0x419545EB, 0x993F7880, 0xAB246B20, 0x408AABC4, 0xCBF6EA49,
+ 0xC0894C55, 0x4CAA6398, 0xA47856E9, 0xAF2AE47D, 0x22F55D33,
+ 0xF0D37915, 0xD0634C72, 0xD983671, 0x2BCC5AF8, 0x9A77D48,
+ 0xC11B5CFA, 0xF107CD7E, 0x3A6B3593, 0xE1425F05, 0x6271812A,
+ 0x5B838310, 0xBD8418CA, 0x10A58792, 0x239F7137, 0xA13D5071,
+ 0x7F9930D4, 0xA462664F, 0x54180F8E, 0x291585BA, 0xE586B87A,
+ 0x144B2C12, 0x98E425C7, 0xBAA4B373, 0x18F0D03C, 0x99462AC0,
+ 0xD8B4D2EF, 0x72473895, 0xA6BF5435, 0xEDAD53B, 0xE0912FA6,
+ 0x5C33F331, 0x3D93CD7, 0x4D03D752, 0x20699929, 0xB89962F9,
+ 0x36E781E9, 0xF58B642C, 0x5FCA69E3, 0x5960A7F4, 0xAD5AAFD0,
+ 0xDF18324A, 0x3DB1E5AA, 0x76BA3876, 0x1BC29AF6, 0xBCC18841,
+ 0x73A60174, 0x625BFF58, 0x67C57724, 0x4458E53C, 0xE157B095,
+ 0x2B370837, 0x83DF6CE3, 0xDD08EEFA, 0x3F52A7C2, 0x191B4785,
+ 0x60843D82, 0xB0DE11F1, 0x105EA26C, 0x6E1C7AA2, 0x47AADD14,
+ 0xB6676D03, 0x3B8D4DF6, 0x737A694, 0x409521DC, 0x744206A,
+ 0xC722023F, 0x2BE4EAD5, 0x63E11D76, 0xCA4A09AB, 0x5CF2D2B9,
+ 0x31586916, 0xCDFD7D84, 0xB203F634, 0xAD7329D4, 0xC524582F,
+ 0x2E53E6C1, 0xBB0E019B, 0xB8538C6A, 0x6A2542D, 0x8A6A00E5,
+ 0x119725CC, 0x5406D347, 0x1B6FFAF1, 0xECCF71F1, 0x981117F2,
+ 0x7167CA76, 0x74F4B880, 0x77A55F47, 0x59EADB62, 0x4A331D95,
+ 0xBCBBA76F, 0xA45C4D50, 0xC718D5, 0x87CE05D1, 0x60D47AD5,
+ 0xA5CA9C40, 0xB0061766, 0xE69B39DF, 0xBD5F1320, 0x9930EAD3,
+ 0xA8B38325, 0x8DD090F, 0x6A6EEF37, 0x2DF16F66, 0xAB514C7E,
+ 0x31109C58, 0xFD48C7FC, 0x515341CA, 0x77AB8EA6, 0x41328DAF,
+ 0xBAF8D31E, 0xA4B31611, 0xED37F331, 0x7A832A22, 0xA22591C7,
+ 0x722D1F89, 0x3B19CF18, 0x261B8A4D, 0xC3F6F6DB, 0xCF8CED61,
+ 0x990FA250, 0xA02E72A9, 0x560DCEA2, 0xB08E67B4, 0x3674E663,
+ 0x97CC3852, 0xA7EB2EAC, 0xFFDE0AA8, 0xA64719A, 0x23269EDD,
+ 0x3C0B339E, 0x86284D40, 0x48D82ECB, 0xA4D4CCF8, 0x43631B91,
+ 0x4BF0C248, 0xB6497B9B, 0x6827BC58, 0xE30B7AF9, 0xA0CCBF26,
+ 0x6C3B7B71, 0xD744B3ED, 0xFA25D2F6, 0x4CDE642D, 0xD65B8142,
+ 0xA6F9207F, 0xE7A207BE, 0xDB506684, 0x44DA4780, 0x9175EA0C,
+ 0x156104AF, 0x4155E1B0, 0x6E3A6886, 0x9DBA1EA2, 0x5423D9C8,
+ 0xCC024E22, 0x758F852A, 0x1DD6395, 0x2D19CBAD, 0xE164F5A1,
+ 0xC2084602, 0x89C274AD, 0x13CB5562, 0xD7FE2D5B, 0xE07A4EE5,
+ 0x1672BA91, 0x4F624CCF, 0x2E5EA4A3, 0x28FEEFAF, 0xBDDA6EF4,
+ 0x32AFD40C, 0x99A5FB3B, 0xDD1D73A3, 0xA342CB3E, 0xA78445F5,
+ 0x53979C3B, 0x427D7943, 0x5221B58C, 0xA6CE9A5E, 0xFB50ECA4,
+ 0xBB86E36E, 0x60839F6D, 0xC5E1C2F3, 0xA1B7FB04, 0xFBB65E0C,
+ 0x78B80F5E, 0xFD8D972B, 0x3BF3BA90, 0x2D572D9, 0x2B5BC920,
+ 0xB6A0DE01, 0xD274D306, 0xC7C6C855, 0x9CAA669B, 0xB04AA641,
+ 0x4D6B1760, 0x3E17ED79, 0xD23241B0, 0xA4A6F957, 0xCBDE76AF,
+ 0x4E5F9493, 0x4C215DA5, 0x33A052B, 0x1A4D80C2, 0x40AEEBCA,
+ 0x390D106B, 0xE9E8E018, 0x5AF3D6CF, 0xE35E1D4, 0xC4FB1C6,
+ 0x14B6299B, 0x8D2E25F0, 0xCCBF932A, 0xC5AC18B6, 0x2227567D,
+ 0x86B5CE2F, 0x26344534, 0x22C515EC, 0x2442B70D, 0xEC3721C6,
+ 0x34EF687D, 0x9C06323A, 0xEAF3EA60, 0x60396F52, 0xEAE78AA1,
+ 0xC9D06CBC, 0x6F95F6C8, 0x584CC258, 0xBA9A27BB, 0x66DF8D47,
+ 0x9D4804EA, 0x57DD9E67, 0xF89C7895, 0xF5336111, 0x25C122C8,
+ 0x62742114, 0xCFBF6D26, 0xBF9F6482, 0xE6F02CD9, 0x11083202,
+ 0xC99E2618, 0x7EBC9351, 0x440112F1, 0xC9DFFBC1, 0x3BF4DC25,
+ 0xB1BA7FA0, 0x61AF9AED, 0x6B1F7D29, 0xAD865294, 0xE3E01129,
+ 0x7E9E77A5, 0x100435D7, 0x9FE3A71, 0x88597C81, 0x722849FA,
+ 0x31C5A0AF, 0xFBA178DC, 0x7F102D31, 0x5CA07864, 0x950E6F98,
+ 0x82C34882, 0x5D041F11, 0x8C613C57, 0xD398CFD1, 0x426F38AD,
+ 0x5599AB1D, 0xFAFA078D, 0xAB25B413, 0xD94B32CF, 0xB288FE38,
+ 0x2893BB46, 0x9A0B4168, 0xA91BCA94, 0x653A5E8D, 0x2174EBBE,
+ 0xDEFE6415, 0x30DA429C, 0xD0C5E40C, 0xB4719AA4, 0xD29CE7A6,
+ 0x905957CD, 0xCD287499, 0x83CA0AA7, 0xA8385832, 0x25A0CA02,
+ 0xC20D47A4, 0xB562F556, 0x4BC19E4C, 0xD9E215C7, 0x27E838B4,
+ 0xC58612F4, 0xA2827F6F, 0xC49DCDBA, 0x679B7362, 0x4E495845,
+ 0xCFD2F0D1, 0x395E76A0, 0x375A655E, 0x92E2058F, 0x73F9F0CA,
+ 0x61EFF3B3, 0x51FFD362, 0xE7410345, 0x7FDA8B3B, 0xA219E2E8,
+ 0x17ABE543, 0x26557412, 0x4B30084D, 0xA68E191D, 0xFE0D93DF,
+ 0x73EF127D, 0x4DECDDB1, 0x77FAF45F, 0xD6002898, 0x92DD0A40,
+ 0x157F6DDF, 0xC2A55F8E, 0x4359F924, 0xFB630C3F, 0x338B6B58,
+ 0xB2945F75, 0x4FA23A0E, 0x836EB8C0, 0xB3B18FD, 0x86114337,
+ 0x24668ACB, 0x99BB82F0, 0x924C8A47, 0xBA959701, 0x81155ABF,
+ 0x8C612D71, 0x36074CA7, 0xD1668C41, 0xE35F58C7, 0x7FC2802D,
+ 0x8E6A7CF3, 0x65B07D07, 0x815F6A6B, 0x791BF0DD, 0x6E47D719,
+ 0xC24394C7, 0xE84A6EB, 0xF194AFEE, 0x464A2F52, 0x677579FD,
+ 0xEBA775AE, 0x1F6EEFF, 0x9A795237, 0x78D9D45F, 0x9D0B344D,
+ 0xBBD34AB7, 0x2F85B12A, 0x16C5C2AD, 0x3990985D, 0x88DF3351,
+ 0x82811AA5, 0x6D351F41, 0x4066A69D, 0x86B660BF, 0x6EDB4768,
+ 0xDDD78CF0, 0xB5D74F6E, 0xE89E220C, 0x91439687, 0x947CC9C9,
+ 0x3857E2BD, 0x302F8AE4, 0x1DABE7F8, 0x4832D6C9, 0x37D58FCB,
+ 0x4EA8A711, 0xCD7BAC98, 0x19DBF8BC, 0xD8DE8DC2, 0xEAFF7E7B,
+ 0xB7629C93, 0x792C6E19, 0xF7009192, 0xFF88439D, 0x2E196A66,
+ 0xEC71B78C, 0xEAF4BB3A, 0x7C16225E, 0x668F337, 0xCBEE1608,
+ 0x6D5B5552, 0x345DC590, 0x681209CC, 0x7B24A819, 0xD08A1416,
+ 0x99888FE3, 0x9FC7288A, 0x24BD8502, 0xEA1D9678, 0x20EECA0,
+ 0x59BEA057, 0x5ADE91EB, 0xDEA8E49D, 0xFA200E6F, 0x9149C81D,
+ 0xF2281E93, 0x8A5B0451, 0x67312D58, 0xE3B849F1, 0xD2217960,
+ 0x7CDF59F3, 0x33C775C0, 0x9EBA8799, 0x7DF9506, 0xB4E96110,
+ 0xB8FCF3E3, 0xDEA059B2, 0x8229B6EA, 0x316486F6, 0x43919185,
+ 0x6C0D90F3, 0x1C6F3DF8, 0x38DB92A9, 0x5CD41244, 0x2C9F0A7B,
+ 0xDF4A315F, 0xF7CE9C66, 0x4C800860, 0x318D53E0, 0xF105C20D,
+ 0xD753E1F2, 0x750810BA, 0xA17ECCA5, 0x2010140, 0x4D884763,
+ 0xC2BB0DA7, 0xB2D5BA74, 0x141CECD4, 0x887FDFC3, 0xC64B53,
+ 0x2D2A85F6, 0x15532B45, 0x5D5CBCE1, 0xBEB9A16A, 0xA214611B,
+ 0x9FC5AC5F, 0x11AE5DD7, 0xA0B9A5A9, 0xFC648AF4, 0x740009AC,
+ 0xED0E0321, 0xB8E6A61, 0x8910C544, 0xC74F26C8, 0x9525CCF3,
+ 0xB41AEB59, 0xE61984CE, 0x598B2197, 0xA412E59D, 0xE1976DD4,
+ 0xB29BBE16, 0x88FD9FB0, 0xB04006F3, 0xB45E309, 0xD5CC15F1,
+ 0xD9DAF630, 0xDC809335, 0x803ED52, 0xB537F5A5, 0xA994F6EB,
+ 0xF5288568, 0xF66FD264, 0x2EA2B3A6, 0x647619F3, 0xFFB38C7A,
+ 0x1BC03B9, 0xB6BC3061, 0xBF30596E, 0xBE2AD27B, 0x8AC04220,
+ 0x641979A3, 0x9ECCBB89, 0xA144FBC1, 0x4E8FAE26, 0x8C5A9D90,
+ 0x299ED467, 0xD7C9C7E3, 0x1D4865ED, 0x76F31C3D, 0xCEE81CDF,
+ 0xB479195E, 0x6FFB3AE1, 0xDC8A398, 0x300F7364, 0xC7940AFA,
+ 0x3B85BE3E, 0xD98CC40D, 0xA24A3D89, 0x3A674204, 0x22888A38,
+ 0x2E77F2D, 0xA2841C9C, 0xCF0689C3, 0x9FE98922, 0x89335017,
+ 0x2D6B69A7, 0xFEDB63F9, 0x899AF4EF, 0x9F9F9B40, 0xA4BE97E8,
+ 0xA51DAF7A, 0x16AC50D3, 0xA8D7ED6, 0xED193443, 0x7615EF1B,
+ 0xB0DF6A4E, 0x64FFE794, 0xE3DB2C9A, 0x7435B022, 0x556E825C,
+ 0x23802AF9, 0xC25098A4, 0xE75A18BB, 0x70B2A7B9, 0x7FB81BF,
+ 0x63EF910, 0x6C669591, 0x6574DD2B, 0xCF6E379D, 0xD2B3AFAC,
+ 0x1E6A1101, 0x1DE22385, 0x2338191F, 0xC69704B6, 0xCBABC599,
+ 0x54EB4809, 0x7839BE6D, 0xD50017DD, 0x39B1A0E1, 0x288D52D3,
+ 0x2D52668C, 0x20D22A68, 0x4E1207D1, 0x3FCC0EFE, 0x47F3FE64,
+ 0x25177A90, 0xB4BFDD4D, 0xDA8DBDCE, 0x6F7275A8, 0x6BEAA655,
+ 0xAA1810FC, 0xE4DB593A, 0x8A4D4BC0, 0x2C402E93, 0xF1C0F7F9,
+ 0x6F0CC577, 0x70412414, 0x752F9DC1, 0xD82E38EA, 0xAC455F7B,
+ 0x4DCD4EDB, 0x92BC2696, 0xFB03F135, 0x4FCA1F8C, 0xBD5E75F6,
+ 0x502F41B0, 0x3616D3F1, 0x2E5B8E31, 0x2026EB19, 0x57E783D7,
+ 0x467BBE00, 0x4703ABA3, 0x1F776B9C, 0xE2570A84, 0xFEC7DB48,
+ 0x1BD5012, 0xFD0A2D5D, 0x7FCC29F2, 0x291304B6, 0x99D5D8ED,
+ 0xC7551C8, 0xFD12F38F, 0xBADE8892, 0xDF749997, 0xA5DAE2F,
+ 0x2B9FA269, 0x5C13CFED, 0x15E9A399, 0x54437F4E, 0xA72DB2AB,
+ 0x56186AA1, 0xFE4DB55C, 0xA34D7836, 0x2A879760, 0xC63FA94,
+ 0xAC18B207, 0x5FC78B3, 0x7F10621E, 0xA769E6B2, 0xEC9F4A11,
+ 0xCE3F982C, 0x62BA2EF5, 0xA5F239CD, 0x73D63FED, 0xE36E9F5E,
+ 0x8AC1DA0E, 0x3F3DB3EB, 0x738326EA, 0x35C366B1, 0xCD476E86,
+ 0x82F6B208, 0xF11A9FC1, 0x426AC396, 0x7E4D1B93, 0x75E4EDB7,
+ 0xAF3C44A7, 0x51A5EF5C, 0xFAD2463D, 0x8A5639CA, 0xC995AC78,
+ 0xCC4BE4F6, 0x3AFE7F8D, 0x66993D04, 0x4386FF37, 0xCBC1C6C2,
+ 0x55A8F5EC, 0xE81A9A75, 0x30A67E1B, 0x4A4A7D0C, 0x20F7F993,
+ 0x1891805, 0x738976AD, 0xD426E7D6, 0x3C5CEEBF, 0x4499187F,
+ 0xABF17C97, 0x447C317F, 0x68D8419C, 0x7AAB6456, 0x421BCF29,
+ 0xF6740F9C, 0x8916BB8D, 0x3D72AAB, 0x9AD54DD7, 0x7549C6EE,
+ 0x7317342B, 0xA18546D4, 0x1056BDA7, 0x54BBCCCE, 0x8CE63E46,
+ 0x5D146234, 0x33BE6C63, 0xB250C4E5, 0x89D72335, 0x87C36BA,
+ 0xB65530CC, 0x2DFAC48C, 0x1663D16F, 0x59B80AA, 0x950274EA,
+ 0x92532D4A, 0x3CEF802D, 0x492FBDA5, 0xA63A2574, 0xEF8005C2,
+ 0x94A18651, 0xAF627ABA, 0x6829B238, 0xA698F646, 0xD2598516,
+ 0x10144D36, 0xD9B1D1B9, 0xAB2ACF05, 0x5395B699, 0xA7851C75,
+ 0x1806C6F3, 0xAE970306, 0x3284B145, 0x98F4FE8F, 0xECDD35CC,
+ 0xDDC1EE0E, 0xC4848865, 0x925826BD, 0x4078BE39, 0x68A8561A,
+ 0x323045DC, 0xA933B37F, 0xBA2AEE2E, 0x4F24F65D, 0x349EE246,
+ 0xF97B9D0E, 0x46DC5759, 0x4529F425, 0x80D17B42, 0x8E16F709,
+ 0x1B42206A, 0x4934A526, 0x391BB6DE, 0xB52EF45C, 0x26C30290,
+ 0xCBA23CAA, 0xA501A8C3, 0xD922C4F8, 0xE8824E53, 0x6F4255DC,
+ 0x5960B544, 0x58BC69D6, 0xCA936323, 0xFDDF053C, 0xC2E002D6,
+ 0x7D750755, 0x8A3F9CD1, 0x35F8F6F8, 0xFB7BD154, 0x65CFF94F,
+ 0x390A58DD, 0xD97C4093, 0x501CA2A3, 0x8EA5DEBC, 0xCA93461F,
+ 0xE02D984C, 0x126F8517, 0x39FDD887, 0x46241AE9, 0x777E854D,
+ 0xE2B36349, 0x58E3FA9F, 0x971DEF1E, 0x8E156228, 0xC0E14E9,
+ 0xA9A01BE6, 0xB318C990, 0x971680D6, 0xA1F359CE, 0x487E23F4,
+ 0x7DE465B0, 0x4E4C905E, 0x2A652959, 0x116FF167, 0x5C74AAB9,
+ 0x4FEFC920, 0x28DF4EB8, 0x29EBF45A, 0x1E350CF6, 0x7134F224,
+ 0x22CCF1B6, 0x3890ACCD, 0x9BC304F0, 0x7A37B14E, 0xF3724F9C,
+ 0xDAC493BE, 0x504692EB, 0x82A56D75, 0x42BC73F0, 0xADA92177,
+ 0x2D9D9FD2, 0x41D874F, 0xEFCFD8FE, 0x8E83A5A2, 0xB84AF0DA,
+ 0x65F9B035, 0x6DF4EEE0, 0x7D403714, 0x1CCB8B3A, 0x25B30F14,
+ 0x5384B044, 0xD21FB429, 0x2C407A2, 0x88622917, 0x92D49C25,
+ 0x845AA406, 0x532D7675, 0xC0B7713D, 0x30E6933B, 0xD270DE3B,
+ 0x78771A87, 0x1949A28, 0xAEC00040, 0x10A092F4, 0xBD9D5066,
+ 0xDE166CB7, 0xE8ECE4D3, 0x867417C9, 0xCF0657E4, 0xD7D550F7,
+ 0xCD472B6D, 0x8CD0F002, 0xD7D47B7C, 0xA2E5475F, 0x2B66B40,
+ 0x397A7C9F, 0x6C4BC024, 0x9FDA402, 0xD981917E, 0xA3A6C8E,
+ 0xC9A42042, 0xCF0D1D5B, 0x1A96C11B, 0x9271030B, 0x4BD5D13C,
+ 0xCDA08C03, 0x1E4B3256, 0xDBB263E, 0x94B1E758, 0x5CF0232F,
+ 0xC76F252E, 0x27FF7F55, 0xA55DC287, 0x72886B75, 0x38AA73C2,
+ 0xA5759CFB, 0xF0A75C8C, 0x7059CBE3, 0x6519FBE2, 0x8C3B4162,
+ 0x5A19A4DE, 0x9D93E753, 0xA9EDF8B5, 0xD68126CD, 0xEA6A7399,
+ 0xA73005B4, 0x45BC5168, 0xABD166BA, 0x4D0CC0DF, 0xE1376FF9,
+ 0x393FB309, 0xE995744E, 0xD5EF71BE, 0x66C2BF35, 0x88D62A85,
+ 0x14121E08, 0x7006CE98, 0x7F0A7076, 0x7DB9C751, 0xDC7056CD,
+ 0xC1517CD, 0x65BCE88, 0x1B0F1E71, 0x54C2DA11, 0x101BFDD8,
+ 0x28096AAD, 0xC365859F, 0xACE13396, 0x7CB432BC, 0xB19EA011,
+ 0xAD9BC7D2, 0x3AF387B1, 0xCCE30470, 0x5335FC46, 0x40D13C16,
+ 0xD548B4CC, 0xC476A7BD, 0x66BC0663, 0xB7C6960F, 0x12D1E821,
+ 0x9A536C48, 0x42641630, 0x740C9A48, 0xF61664E8, 0x3B11E69A,
+ 0xBD79E1F1, 0x3F930B7D, 0xD98B085D, 0x2151962F, 0xD4D7F80E,
+ 0x88975123, 0x5302989, 0x12F5CA2B, 0x37C29573, 0xD1D2A3A6,
+ 0x46DA55DA, 0x2EC8C098, 0x802A42DF, 0xD07A11E5, 0xD5BF4B16,
+ 0x171BCB96, 0xB5843001, 0x57BDCAA7, 0xDDD36F33, 0x633D0AA0,
+ 0x313B7064, 0x68BD30CE, 0xC986B6C3, 0x2271824F, 0x9951E552,
+ 0x15939472, 0xDC668F83, 0x1D98A441, 0xA4A1676, 0x631C444B,
+ 0x6EB61C7C, 0x8EEE0B5E, 0x23F82C1F, 0x6C4B53C1, 0x41116D6,
+ 0xEBC1627A, 0xC8839049, 0x7F07A8F6, 0xD1F74661, 0x7D9892DD,
+ 0xF010EC90, 0x37C8A4F4, 0x6ABA986E, 0x68B1E4F6, 0x8066EE05,
+ 0x5E964158, 0x88D477A6, 0x776CF1E1, 0xB7AB3B60, 0x183D58C0,
+ 0xA7E13F2F, 0xDD435AD0, 0xF37DF46E, 0xD3F3F774, 0xB6B24A9A,
+ 0xC097D9F2, 0x54EE718C, 0x4469BDB, 0x4F20DAC, 0xB4002AD5,
+ 0x2E7AB56, 0xCDB4B18C, 0xF2ACE62D, 0x54BD40DE, 0x46DCCA2,
+ 0x5B7F32F9, 0xA8CB257D, 0xB138C149, 0x71474D19, 0x6F71C293,
+ 0xD88FBC7D, 0x9E0A7F86, 0x14B92605, 0x1CBACDC, 0x29159263,
+ 0xBB719E18, 0xD41B37EE, 0xA236E27E, 0xE916BAE3, 0xED34D9DA,
+ 0xFDDE09B6, 0x4FE72C56, 0x16927460, 0x8CFFF9A, 0xA9465741,
+ 0x2B1CD6E0, 0x6BA277FD, 0xE06F70EC, 0x7CB2715, 0xFEDC13C8,
+ 0x7049632E, 0xC6448831, 0xF72CA3A, 0x9B2BE231, 0xC16A8438,
+ 0x948EB7E, 0x64041803, 0x82A43295, 0x226D95CE, 0x84AFC1EE,
+ 0xB2EF3B82, 0xAC18A45C, 0x74DE3ADE, 0xD0E6FAD4, 0xE10C242E,
+ 0x797DF7BA, 0x812CD7B8, 0xED45B681, 0x8F6CCDE8, 0xC2376DFF,
+ 0xCABE35D6, 0xD450395B, 0x13493CE3, 0x870E1BF5, 0x7B0BF341,
+ 0xEBD572F2, 0xAE22B3F1, 0x7ED22DF8, 0xEFE826ED, 0xF147F4BD,
+ 0xA12DA6F2, 0xF3871967, 0xE4423B70, 0x298472D9, 0x45E03E3D,
+ 0x2BE705AC, 0x41E3AE6C, 0xA29DF92C, 0x54B33739, 0x8EA8F7A9,
+ 0xDEFF7BC9, 0x77D06961, 0x71981BA1, 0xBA5A5647, 0x4A8E0E2E,
+ 0x9F519F5D, 0x31BBA940, 0x3D3A0532, 0x7090F0AD, 0x8B47D658,
+ 0x8D198BAF, 0x9ED929B6, 0x323BB81, 0x97210404, 0x7B8790DA,
+ 0xD8438C25, 0xDFBB1C93, 0x2C3F415B, 0x14738C42, 0xB46C2C7A,
+ 0xA3627CAB, 0xFC540D08, 0xE8227979, 0x672B87FE, 0xB257C949,
+ 0x9C2B31FF, 0x97AAACA8, 0xC662B448, 0x5BFEFC7C, 0xC2FDEDDE,
+ 0xAD306CED, 0x639A2576, 0x9ECC1378, 0xA72D71B3, 0x94E11CDB,
+ 0x8BF14832, 0x945C1728, 0x49AE595B, 0x526DD500, 0x40A7D344,
+ 0x8EB1DA34, 0x731E17C5, 0xA7CF41A4, 0xCB068104, 0xC842B8E,
+ 0x7F5733E1, 0xAC9CB3B, 0x2E3F58C0, 0xFD8BC4F, 0xFFBCBBAA,
+ 0x620248F9, 0x27AC344D, 0xF2E5958B, 0x773EBC3A, 0xEA6078F7,
+ 0x6B32D1D7, 0xC00DF984, 0xE73C86AA, 0x712026DB, 0x2CE271FF,
+ 0x38578573, 0x816605D0, 0x673509A9, 0x8D693AC8, 0x2533C371,
+ 0x6783E269, 0xC5731F9, 0xF2A8041E, 0xBB3C008F, 0x2B290D9A,
+ 0x122A4BA4, 0x645A69B, 0xB86CC256, 0x9369B8C3, 0x90CF4CEB,
+ 0x573005D0, 0x4F7DB793, 0xD6AC972E, 0x178BFB66, 0xC430DCEE,
+ 0xD1A8138B, 0xBF6EC4C8, 0x693E6FAF, 0x54119B44, 0x9C904669,
+ 0x4D95F608, 0xDB59E550, 0xD85DDBBC, 0xD15818AE, 0x680778D8,
+ 0x3B67A234, 0xEBE9DAF3, 0xEB8E049B, 0xDD9E0EB8, 0x5D4FB1FB,
+ 0xCEA62C1C, 0x948AF719, 0xA7E58E36, 0x800EAD97, 0xCD895A65,
+ 0x72E63F92, 0xA9A82DD3, 0x8CC07793, 0xE70EBE82, 0x1F69534,
+ 0xAB727A31, 0x1582EF9, 0x7247F677, 0x5FFD7E2C, 0x950EA9DF,
+ 0xFF38A172, 0xDD75DB84, 0x3A416207, 0xD6A23DA7, 0x3BBE70D0,
+ 0x538C25CA, 0x2958DF9, 0xD7B9C83E, 0x61F35964, 0x1E05B36,
+ 0xDD57CDCF, 0x997335B, 0x3A65762A, 0xC5836CD0, 0x9EF2B7F1,
+ 0x5094196, 0x6949A654, 0xB7FD3E5D, 0x6070C271, 0x30364C38,
+ 0xDCAFFFA5, 0xCD4ED281, 0x9865FE7C, 0x75F665AD, 0x6ABADB10,
+ 0xAB43129, 0x26B7A5B8, 0xA321DDBD, 0x467AD732, 0x153A1AE,
+ 0xAD6B1842, 0xBE19B6BE, 0xC1E22C82, 0x73372EA5, 0xF9EF4AD7,
+ 0x24C81977, 0xD8451807, 0xCD10ADC8, 0x8FBD95E2, 0xE0789969,
+ 0xC77A80F2, 0xF1165BCE, 0x3488C653, 0x16F3E378, 0x8D71B29A,
+ 0x628EC98A, 0x40963234, 0xF918E028, 0x9A584D33, 0xC174E2FE,
+ 0x417C5145, 0x1C751175, 0xB21E0C12, 0x30218ECC, 0x9D7731BD,
+ 0xA07DBA0F, 0xE7504D39, 0x3E37F16B, 0xD3BAB050, 0x6F3DE64,
+ 0x1998A7BA, 0xA61A6D07, 0x424FBED7, 0xCD6B3236, 0x68E71248,
+ 0x58CC3DFB, 0x584FA4F5, 0xFFE8E2BD, 0x9F0E3D75, 0x788DD779,
+ 0x978ED891, 0x7E1BFFC8, 0xB812A1C9, 0x5CCC1A32, 0xF1A47219,
+ 0xD6BA6E71, 0xAFA86EB5, 0x28D128E2, 0x9EDD53B, 0x9AAB7E9C,
+ 0x493B76F2, 0x31C5C89, 0xCE5FC3B6, 0x974CC3F5, 0xCBBD90FB,
+ 0x61DE988E, 0x99B927CB, 0x972EFCCD, 0x2719AD6, 0xE06E4B29,
+ 0x48215B1, 0x37EDE8E4, 0xABF9F87F, 0x8BC1C626, 0x5B19EC05,
+ 0x212A2AE1, 0x28446975, 0x20D04126, 0xFC453267, 0x967D9524,
+ 0xDF1CDF8, 0xFB17DCA3, 0x11E68AC6, 0x3AD7D667, 0xD133EF43,
+ 0x5EC41DA3, 0x587AA639, 0x17ADAE3, 0x816DF77A, 0x37D0726A,
+ 0x49DC33D9, 0x6C9737E, 0xA6A2F950, 0xEC5F352C, 0x50D1E06D,
+ 0xC10009A6, 0x2F70F8BE, 0x382269B1, 0x4C29E7CB, 0xBD474FF3,
+ 0xD19A4F6, 0xC3CCE458, 0xE09B348, 0xD15A0DC5, 0x1C10D20E,
+ 0x4AFDED15, 0x3C109DC1, 0xD8C117F5, 0xB501DDF5, 0x39C92B5F,
+ 0xE76FCA13, 0x76DBAA1B, 0xB0730EBF, 0x67DD1FBC, 0xD8B87AB6,
+ 0xA826225B, 0xAB2F7089, 0x499FA36D, 0xF26455B, 0xDC79F8EF,
+ 0x987E765E, 0xA13E60C7, 0x500C7803, 0x492C871D, 0x970DE4EE,
+ 0xD1423DC1, 0xB66048A3, 0x804895AB, 0xC079A15F, 0x5E6FD682,
+ 0xE936476E, 0x8DECE38F, 0x76A011D, 0x53575B91, 0xB263D36A,
+ 0x8F2624C1, 0x26B34937, 0x75A7EC2F, 0xE33ED24, 0xBF1BE7C7,
+ 0x8D6BA785, 0x1D9FE802, 0xB8F4EC20, 0xD5C714B2, 0xC1326D06,
+ 0xFCA78B3F, 0xC0065015, 0xA4B9F286, 0x53F92A8B, 0xF4B02DBB,
+ 0xEC47E64C, 0xA29FFB12, 0xBA94FFB2, 0xB6980EB2, 0x7415C83F,
+ 0x93F91A24, 0x4C6F7615, 0x34431174, 0xC7D63B4, 0xB1599158,
+ 0xA3A01FCE, 0xBD477764, 0x6B16EC41, 0x772D8BF5, 0x90F0A785,
+ 0x8F72672C, 0x7AD22CDC, 0x70824998, 0x1BED16D5, 0x596E84FF,
+ 0x48B5B4F4, 0xB20D0B81, 0xF00F7AFF, 0x80F618DA, 0xD10AFE11,
+ 0xA8EA3109, 0x91BA5E43, 0x31345A01, 0xEB0EF0F8, 0xCC6E7FB5,
+ 0x3348AE52, 0xEBB124D9, 0x447E58B1, 0xF2A3D592, 0x7F3EE5D8,
+ 0xD3D7B836, 0x9C98DCD4, 0x27F0B7A0, 0xA9655FD9, 0xAB48E5F8,
+ 0x7F996D8E, 0xAC13B08B, 0x2530AC6D, 0xAA542552, 0xD4E6B42A,
+ 0x6432AA64, 0xEAC84F76, 0x41D5F959, 0xCDE91DDF, 0xA0AA485A,
+ 0x6453698, 0x277C18A4, 0x161A497, 0x66FECAE2, 0x1B64683,
+ 0x948DD228, 0x1F3C5950, 0xFFC271FB, 0x15C4DF12, 0x7C78252B,
+ 0x9D4EBB89, 0xE6FA1D49, 0x6B032100, 0xB65DD3CC, 0x106BC9B5,
+ 0xE0223D45, 0xF7779B03, 0x4B0EA0C2, 0x3CB5AAF2, 0x9A458E5F,
+ 0x524090ED, 0x3BB1F18F, 0xB4DD065E, 0xA8F13E4F, 0xC4949ABB,
+ 0xD8142D31, 0x99069DE6, 0x989D2A16, 0xC72D929, 0xA2AC5754,
+ 0x7E29B714, 0x6E25C15F, 0xE8777078, 0x467DDCEA, 0xF94B2ACB,
+ 0xDF429476, 0x69AE316, 0x363C664D, 0x85D6AA1E, 0xD727E39E,
+ 0x5AF440A3, 0x2F0BB16D, 0x461D52D, 0x610559B6, 0xC28066D9,
+ 0x3C13AE61, 0xA965B865, 0x2BCE3D4A, 0x361C4848, 0x46B94657,
+ 0xF2AE634D, 0xD7FD4B8B, 0x70C175D8, 0x33128DF, 0xB9718A3B,
+ 0x8EF80C0F, 0xAB12E738, 0x124B8055, 0x43448325, 0x9F05E427,
+ 0xA0A9F843, 0x57A9A3FA, 0x492EEA32, 0xE73D2B18, 0xF3113C2C,
+ 0x2BA9B42D, 0xFF0B320, 0x3A18CD71, 0x59804367, 0xC37F9B87,
+ 0xB8A990, 0xAFE9F267, 0x1892892B, 0x25B9C66D, 0x52D4056E,
+ 0xCC1508CA, 0xAD213DB2, 0x8B43F743, 0xAA9705AD, 0x9BC756A2,
+ 0x43F42526, 0x596FEE87, 0x2B8AFF32, 0x46DEDB48, 0xBF06317C,
+ 0x876D4CF2, 0x16951456, 0x2B051AFD, 0xFD093E9D, 0x2F113180,
+ 0x77BFC4C0, 0x29200C52, 0x182D384E, 0x54AE29E0, 0xF90961E8,
+ 0x6072B8F8, 0x3D346F4E, 0x9AA5DBA4, 0xE5E22EC6, 0x392170DA,
+ 0x40939B9B, 0x65B89151, 0xC54AB94, 0xAD7280BC, 0xA3D4395E,
+ 0x3B5754D2, 0x9E77A6A2, 0x9A737F56, 0x9B2D432D, 0x8FDDA7E7,
+ 0x5958516E, 0x7F52CD74, 0xC1761A50, 0x2B80C01F, 0x5AA99F54,
+ 0x36FAA395, 0x5DB4B3AD, 0x82024C73, 0x988CEFE0, 0xB44498C0,
+ 0xF9561A4, 0x280470E6, 0x6966F3A0, 0x47E374F4, 0xF00F4CFF,
+ 0xBC5C4DB2, 0xE287924F, 0x1ED57369, 0x484FE06D, 0xE92E6564,
+ 0x7429DAD2, 0x1473AF49, 0x9619E0CD, 0xE6EC2B63, 0xF7A983B5,
+ 0xEC43C28F, 0x4C98EBE7, 0xA61FDF89, 0xA867E5ED, 0x1088A7C,
+ 0xCF1CEAE8, 0x223AA207, 0x686F4F7B, 0xEBB013E1, 0xDDC01886,
+ 0x77478D4E, 0x2FFCEAEB, 0xFCA58846, 0x1208668E, 0x32F8252,
+ 0x65C9F3ED, 0xC7584B2F, 0xF3EB26B2, 0x90890270, 0x5D97ED04,
+ 0xF5B5B18A, 0xCF415DF9, 0x4CF4683F, 0xE2E3F29F, 0x850E4BEF,
+ 0xDBABF6E2, 0xBD183286, 0x2F36215C, 0xD8CA1DD3, 0x4309CC6F,
+ 0x9FA52446, 0xBD94348E, 0x8693D9B6, 0x61E880C2, 0xA1851D5E,
+ 0xAAB94F80, 0xF8919C00, 0x74D82ECA, 0x4466A1B6, 0xA0A98E8C,
+ 0x95B6D1D, 0xE5393A4C, 0x5A40CFFB, 0x67013370, 0x571B0FDA,
+ 0x9E7E805C, 0x15E32653, 0x2CFE7902, 0xA02E0906, 0xA8883783,
+ 0x7A68B719, 0x3402833A, 0x68BFD324, 0xE0B43DA3, 0xF9DB0F,
+ 0xC9510610, 0x690D30B, 0xE79AB417, 0xC917E4C0, 0x7B05CE55,
+ 0xE116EFDB, 0x69E3B158, 0xF91ED58D, 0x1832D16A, 0x91F4EA17,
+ 0x3D24C408, 0x76A2C6D0, 0x99B19825, 0x2BF52475, 0xAD49289D,
+ 0x66238CD7, 0xAC1571F5, 0xA2EABC02, 0x889337AE, 0x3219AFFB,
+ 0x104B8779, 0x810488A8, 0xAC35416A, 0x2C6DEF85, 0x2ED109F5,
+ 0xCC8C6732, 0x97CD8E90, 0x339F3E81, 0x91486206, 0x2708D41D,
+ 0x1F2B19A7, 0x51A60303, 0x5E90E440, 0xB63092C8, 0xF1031823,
+ 0x971A06, 0xB624F6A2, 0x58AC0181, 0xA983D599, 0xA776D877,
+ 0xB727FE1, 0x55AC01B1, 0x4298EA17, 0x4D6BB9AA, 0x31C55C65,
+ 0x6A266780, 0x4FD92256, 0x817DB37A, 0x46A14DF1, 0xEC7D9F14,
+ 0x98D1C1B7, 0x911DF80D, 0xBFBF24E1, 0x9B4DBC6A, 0xE1F71BA4,
+ 0x9EE5E44A, 0xD1868C4C, 0x6FB45D76, 0x11EC8672, 0x1CED7F0C,
+ 0x1524A040, 0xA49DE9D3, 0x99FF328A, 0xC392F619, 0x52A856CC,
+ 0xDB0B0AE6, 0x67F0162E, 0x2C20D410, 0x4E23C4D, 0x828032EA,
+ 0xC2E7DFFA, 0x908CF524, 0x919F61EE, 0xF001C6F, 0xA81DDF65,
+ 0x5EC56647, 0x28385ACF, 0xBDD764C0, 0x75C853AB, 0xDF0ADD73,
+ 0xEEA9C63D, 0x804949F5, 0x658ACD0A, 0xD12F3F50, 0x1FD4F7EE,
+ 0x7F023D80, 0xD2CB08B5, 0x477EA9A1, 0x872DB719, 0x7B8B6AE9,
+ 0x84F6AC4, 0x81634EB4, 0xD1A89CF, 0xB3F4F3B9, 0x3A6B024B,
+ 0xAA2CA2C5, 0x9C902C0C, 0xC40E4135, 0x3C6E612F, 0x11219414,
+ 0x1F184277, 0x11B6B30C, 0xDD8A6A5A, 0xA0D21C9D, 0x55377022,
+ 0xD0708FBD, 0x8D761020, 0x54FCFCFC, 0x477801BD, 0xD6919EB8,
+ 0x9AD29078, 0x36F8D9B8, 0xAE525B8C, 0xCA7ED140, 0x2D8F8B97,
+ 0xD1B79EAA, 0x2E26FB2A, 0xFB396E32, 0x399129A3, 0x28B55FA1,
+ 0x2ECB2CF0, 0xDF1CBF7C, 0xDE57A70D, 0x33410B33, 0x7C5759BF,
+ 0xF534264B, 0x16C8C221, 0x874A3A63, 0xD05808ED, 0x679674BC,
+ 0x24B060C9, 0x4B162B53, 0xC7D01208, 0xE753DE61, 0xFA9840E4,
+ 0xA4FEC439, 0x4143E13F, 0x327E9EE8, 0x319D901E, 0xC40FC209,
+ 0xB1E1FFFC, 0xE737D52B, 0xD074E058, 0xAD8892EE, 0x86B93396,
+ 0x49C13F4B, 0x60A5721C, 0xD4C4F599, 0x14B38EBB, 0x86BA655,
+ 0x95F4E0C, 0x4217E99A, 0xD0CA3861, 0xBDD3617B, 0xB0BDBF4D,
+ 0x99E3389A, 0x8200DCFA, 0xEC22C8AC, 0xBA8DDB32, 0x3F7DDFC8,
+ 0xC7DDC171, 0x211CF31, 0xCC31A0C7, 0x99A84F32, 0xC9FFD317,
+ 0x2267733A, 0xFBD05569, 0x306BC05F, 0x6E2685D5, 0x43FBF7D1,
+ 0x5A2DB2D3, 0xE6491D4B, 0xAD078066, 0x7CAF7AAD, 0x2B1FEBA5,
+ 0x3418A0EC, 0xC359E9B7, 0xB024E024, 0x58F22A6B, 0x18EEE710,
+ 0x4755B9C5, 0x528D3273, 0xC8F9255, 0x635E5F9D, 0xABDF5BAD,
+ 0x8410F054, 0xEA068528, 0x438345EB, 0x56EF340, 0xBD86A7DE,
+ 0x543A126A, 0x5F259D83, 0x67EDA87A, 0xFF24F98E, 0x684E6504,
+ 0xE4EB57B, 0xD2D3B758, 0x4474D10F, 0xA94594B7, 0x3E4BEB07,
+ 0x95C3F257, 0x478B6FA8, 0xBCC7EFD8, 0x1023D258, 0xB4ACD6C0,
+ 0x36129B10, 0x16D7D9A3, 0xEA63BE7E, 0x25EC12A1, 0x21B95589,
+ 0x3A673799, 0xB8E04594, 0xAE98693C, 0x9879B8F9, 0x601A3F62,
+ 0xCF9897C0, 0x87CD1798, 0x629788F1, 0xC1337B31, 0x59D84E67,
+ 0xF13FA484, 0x5E8C7B3F, 0x7DEDE9F6, 0x9779F496, 0x74C4EE89,
+ 0xB3D9AC8F, 0x44118EFC, 0xB4FE8E45, 0xC9934560, 0x93D739E8,
+ 0xCD013773, 0x102411F1, 0x9DB63EFB, 0x63165875, 0xB8B97E98,
+ 0x6B4223D0, 0x6F34352B, 0xDB038A46, 0xC187163E, 0x17FE20D8,
+ 0x82A1BC9F, 0xB6860AAF, 0x11D5F9E0, 0x5371E14E, 0x20BC8445,
+ 0x607589A0, 0x8DDCCF44, 0xCDCD53C2, 0xCBCB32D8, 0xC512E661,
+ 0x1EB4E6CE, 0x228E99A0, 0x28EE0177, 0x76ED3F3D, 0xA3DA3300,
+ 0x17C57F91, 0xA1855C6, 0x3531FA3, 0xA93A8241, 0xC45D540C,
+ 0x365D42EF, 0x2CA39696, 0xE460F7D1, 0xCA32CCB3, 0xA6D9D934,
+ 0xAD01079C, 0x9B07D89C, 0x226CE0A5, 0x60D67762, 0xD35A4B7B,
+ 0xFF0A698F, 0xDB73BF89, 0xF41FBA9A, 0xCACDF26D, 0xBF594213,
+ 0xCD4D3E90, 0xD12F3EB8, 0xE689D238, 0x8CD4C0CA, 0xEB3E841E,
+ 0xA513EF0F, 0x2DF4B65D, 0x90161625, 0x9C02AC36, 0x208F328D,
+ 0x12BF5D93, 0x7C8C355C, 0x3CDFCA22, 0x29381080, 0x3FF6CA14,
+ 0x9F269C74, 0x8A48070B, 0x3BDF51BD, 0x85932156, 0xA7B6F9FF,
+ 0x80554507, 0x43820D97, 0x59B7214A, 0xFC3ECC27, 0xED39DB19,
+ 0x2B9BDB43, 0xABD4E298, 0xC2C5953E, 0xD3DB0C09, 0x66EC81DA,
+ 0x7F41EDE1, 0x5146E8D7, 0x49171DF2, 0xB334BF9A, 0x3AADC9E6,
+ 0x56E12468, 0xA2D4B032, 0x662B1F49, 0x9C448B1F, 0xA219526C,
+ 0x56D66A27, 0x41609345, 0x8E685EFA, 0x392DA3A4, 0xDE58C26B,
+ 0x9C779FC9, 0xCA834F65, 0xA1E34DC4, 0xEC5BE6EA, 0x3737B7AB,
+ 0x2E9B7D0A, 0x929E96B9, 0xE38B0019, 0xC1E4115B, 0xD8141740,
+ 0x66977F67, 0x7D4CE4B3, 0x245AB554, 0x26F98B88, 0xEC78F24D,
+ 0xE1F34C1A, 0x5737AD34, 0xC1A19AC6, 0x3291E363, 0x4E824FF3,
+ 0xAC42BDF3, 0x7C2DACE8, 0x8D5C97F6, 0xD120875, 0xC4E5C39D,
+ 0xE22AE85D, 0x290FF39D, 0xD495E52A, 0x95414374, 0xD65757A6,
+ 0x1E7657F9, 0xF5073D56, 0xC2AA7589, 0xC166A0B3, 0xA0DF8CDE,
+ 0x4057EAE5, 0xBAC4DD2F, 0xB51F621F, 0xA96F90E3, 0x392B5D6F,
+ 0xC31E9CA1, 0xCCC02FD3, 0x5181074, 0x7BC15C18, 0xCA9232A4,
+ 0xD1D104E9, 0x5F0C5D3, 0x4947F6D2, 0x3C923E97, 0x6B486C35,
+ 0x9C8ADA96, 0x175C4D87, 0x39A1A0FE, 0x417F201B, 0xD080E114,
+ 0x4847B147, 0xFD634E49, 0xBC0BF4CA, 0xECABB1DF, 0x869B0263,
+ 0xCD797C28, 0xD2A4683, 0xD50F6A0B, 0x2CA40138, 0x8DA4EB55,
+ 0x5D198E5A, 0xA98DB40D, 0x96CA0E68, 0xA8D92294, 0xC4813E60,
+ 0x81CD6B09, 0xEBBEBF80, 0x6777688, 0xCDAF6EC5, 0xEB85653E,
+ 0x3BB780DD, 0x73718A21, 0x70E8A324, 0x654DE06A, 0x2CB2494A,
+ 0xFC1DA829, 0x64059A2F, 0x61CE9D0D, 0x5BC51CAB, 0xDF7DE6AE,
+ 0x1596B477, 0xB0F9EA86, 0x9D87D85B, 0x877620A7, 0x586F3AD6,
+ 0x96AE645E, 0x65E9D5D7, 0xDB69CEB, 0x2753EF35, 0xC226F633,
+ 0xBD373F9D, 0xF2A0E198, 0x4372EEC3, 0xA66F7010, 0xD30E1D18,
+ 0x152C0DFB, 0xEB86FC75, 0xC208FE7E, 0xB36625A4, 0xBBE2DE8,
+ 0xEC49F9C9, 0xCE724FFE, 0x2D509471, 0xCA6C24B6, 0x1BA93DDF,
+ 0xEABE9550, 0xB512D359, 0x83F76766, 0xC8267976, 0x7E50802B,
+ 0xE3EC2199, 0xD3269B8E, 0xC515B0CE, 0xB5752537, 0x70474BD,
+ 0x7F50EBE, 0xF9FC0B38, 0xD899D19C, 0x317AA41D, 0x6B706374,
+ 0x66479538, 0x560455A3, 0xD770DD85, 0x55BB61BD, 0x6DE6723A,
+ 0x3F89034B, 0x9C9650BC, 0xE569992C, 0x7B8F4D95, 0x3FB7C516,
+ 0x7C28C04B, 0xA12DE6B9, 0x8CFC5AFE, 0xA734A25A, 0xCF1483E8,
+ 0x1AB22339, 0xAA94F43F, 0x16319A1E, 0x2C9AA4D0, 0xE9D2618,
+ 0x790B699B, 0x3AD9C3A1, 0x55A778DA, 0x6517152F, 0x2139AB74,
+ 0x12F762CC, 0x4BE02E6F, 0xE69400F7, 0xDC48DCD0, 0x563DB028,
+ 0x32299125, 0x7C9145A9, 0xFB88067B, 0xF070F6FF, 0x3D9A42FF,
+ 0xC5D20DC, 0xF96F7EE1, 0xA9C209A3, 0x9A192F36, 0x3E158AD,
+ 0x1265DF79, 0x2E49E297, 0x99D3A002, 0xE6AFDDCB, 0x3B56751D,
+ 0xB248A31F, 0xE6BE0FFD, 0xBBAB635E, 0xB383C45C, 0xA9DC9F2D,
+ 0x735CE03F, 0x69992E32, 0xD1E6A77, 0xE38A7F46, 0xC1E59620,
+ 0xFAE7F99A, 0xBDFB440C, 0x9F53F99C, 0x224EA340, 0xAB5D1AF0,
+ 0x35F3126D, 0x99430549, 0x83E12C62, 0x6403957B, 0x7B119103,
+ 0xC8382BAB, 0x99A85991, 0x9BF370AF, 0xDFA83CAF, 0xDBEC2CC3,
+ 0x416D8EBA, 0x774E58FF, 0x29C222F, 0x3DE60561, 0xDF038931,
+ 0x8297C377, 0x9867C08, 0x58ADEAED, 0xD88F0856, 0x6E4C2A39,
+ 0x2599DF28, 0xD7A6D06A, 0x433B35BE, 0xDAD3175B, 0xC358D423,
+ 0x84BF4580, 0xE7D3BE65, 0x9EC8CDBA, 0xCE901946, 0xC4B4D088,
+ 0x98B1245D, 0xFBB0CC10, 0xE8CB9C76, 0xDE665AF2, 0x28E46D8B,
+ 0xF7012A56, 0xE29F8C07, 0x8BF87AFB, 0x2907C051, 0x820923CB,
+ 0xC3E95542, 0x6AB5559E, 0x314BD068, 0x1CEB5637, 0xD1D830D,
+ 0xC442D6C2, 0x5F6074F4, 0x37F08A2A, 0x21F782BE, 0xF378B1AE,
+ 0xB7FC74DA, 0x4ACB450F, 0x365F3092, 0xFB0C842C, 0x5DD80554,
+ 0x741C4F79, 0x290716E0, 0x76E56BA9, 0x10006310, 0x42A183C7,
+ 0x5F1FB962, 0x8DE2BA39, 0x6176B6D9, 0xFC059A44, 0x9907DE39,
+ 0x71A5EA7B, 0x42309616, 0x1DDE34DD, 0xF0DFA4BF, 0xF69B5E2F,
+ 0xD145268, 0x49A3E7B, 0x90508840, 0x861DE564, 0x904730CB,
+ 0xC844CD6F, 0xD5A2CEB6, 0xCE895F0D, 0x73EEE4D6, 0xEB4565CF,
+ 0x533ED4ED, 0xF4AAB655, 0x591BC278, 0xBD1D929D, 0x80AD7DA6,
+ 0x527B3C51, 0x40F627DD, 0xDA420FFD, 0xB9A6F685, 0x5F6D9BC2,
+ 0x4F67DE58, 0xFB5F87F0, 0x47540936, 0xB2083BC8, 0xAD48DD69,
+ 0x63F7CA5A, 0x28D5372D, 0x61DA54B0, 0x7DA88170, 0xA2DA7B83,
+ 0xE1D70E32, 0xA3ADEA46, 0x97026868, 0x60FA4303, 0xA4104416,
+ 0x3DB4A8CC, 0x72F0F53B, 0xFF270297, 0xD5600E97, 0xD7D25D62,
+ 0x46DBCAC5, 0xFD61775D, 0x93E100DB, 0xBFE0E0C0, 0x8CE51426,
+ 0x8216C272, 0xE7300A56, 0x5A61C30E, 0xA7667C78, 0xBD23D39B,
+ 0xDC425756, 0x7AE9A42B, 0x249E8C42, 0xABB91D5C, 0xBD1334D5,
+ 0x8BCE967D, 0x5CF89EEA, 0xDB125339, 0x225E3C4C, 0xC5DDA12,
+ 0xA92903F8, 0xF2F29634, 0xD2AB3419, 0x396DAE59, 0xA02C965E,
+ 0x450B8DEF, 0x1E4911B2, 0x4F94BA94, 0x6802E7C0, 0x779671B7,
+ 0xC0B06A93, 0x65BF0119, 0x3D672B7F, 0xE7E68CA, 0xF173FBF,
+ 0x503C50F4, 0x3D8CA779, 0xD9BC10B2, 0xE6B89F78, 0xFC04B6F2,
+ 0x74B0E1B4, 0x3BB8594A, 0x5866C0E6, 0x125FBE40, 0x21239465,
+ 0xC00E2791, 0xD7957B76, 0x331D18CA, 0x87D0C340, 0x8D7347DF,
+ 0x296D2AA1, 0x8EAA71DF, 0x1D477388, 0x4F666705, 0x211D2B0D,
+ 0xA41C0741, 0xD8F7CEEC, 0x4C6EDC5E, 0xFE5DC02A, 0xAA83AED3,
+ 0x9AE501A6, 0xFF82168C, 0xDC638114, 0x4C345BA0, 0xDD7E0F1D,
+ 0x4C072ABD, 0xFF606768, 0x3CE74279, 0x93DED13D, 0xAB7A9752,
+ 0xAF27666, 0x784EDE4F, 0x7F4BE8A7, 0x9A45141D, 0x69E507FF,
+ 0x78BAC3AC, 0xDB2A62AC, 0x52561515, 0xA9DFA9A8, 0xCC51778C,
+ 0x886CC6A, 0x5246AD23, 0x68A7480, 0xBC267A85, 0x1FF771F4,
+ 0x5199BC1E, 0xF8CCD05A, 0x7BD65764, 0xC61A33FA, 0xC9F24B8E,
+ 0xBC0B1D9F, 0xE43E103, 0xBE3D7AAF, 0x39154AD2, 0x941C2098,
+ 0x1C26174D, 0xC63D21F1, 0xFBC6D732, 0x8C43AE71, 0x1495C044,
+ 0x9483EE96, 0x909A94F0, 0xC1B02D9E, 0xDF9A2114, 0x2F4883E9,
+ 0x4806958A, 0x209A2722, 0xFE514205, 0xEB85D85F, 0xC25BED82,
+ 0xEB2CEABE, 0x8B2A2EDA, 0x68641725, 0x10570304, 0xE53EE68B,
+ 0xC43FB1C1, 0x8F763232, 0x41ECC1D0, 0xE3E44CBD, 0xA1A68EC0,
+ 0xDAFA770A, 0x6996A5A8, 0x38407C06, 0x4FAD77B4, 0xE30E2912,
+ 0x47EE2FD, 0x2CDA167F, 0x88F915F1, 0xF3DF6195, 0x530FBEDE,
+ 0x2CFC1C0C, 0x47B21171, 0xDEC1A586, 0x2031A43A, 0xDAAD77AD,
+ 0x8BE637E6, 0xA6AC1EBB, 0x6AB9F2A3, 0xBFB5ED6C, 0x15792C44,
+ 0xFD3AB89D, 0x27A7E24E, 0x3E76999F, 0x77EE2E6A, 0xE505F3B7,
+ 0x429839A6, 0x6BEE7B15, 0xF61F0084, 0xFC20752C, 0x4BF79989,
+ 0xC8B4F8E8, 0x46B33427, 0x9F4BA3E8, 0x41B9354D, 0xEED27E23,
+ 0xA7FC575F, 0x279180C5, 0x141C3A06, 0x2C2FCEF9, 0x4403AA1F,
+ 0xD4496B6C, 0x25C33091, 0x452C754, 0x80534A0, 0x80842F72,
+ 0x3DB756B1, 0xEFD010BD, 0x1DE7F9EA, 0x5F9B1769, 0x55D9839F,
+ 0xD5B11F46, 0x941D69AE, 0x8C4F3D35, 0xE710E268, 0x2DFBC983,
+ 0x5D417C19, 0x7C2561F9, 0x25415FCF, 0xF331B119, 0x235B632F,
+ 0x9B1463A9, 0x8249E513, 0xB6F14826, 0x1005E62C, 0x2B1B4F3E,
+ 0xEF793550, 0xA90F6AA2, 0x77BFECE6, 0xA6E1C13E, 0xBCB6E143,
+ 0x2496D0ED, 0xF4A8D5F0, 0x29C27A0C, 0x7D231D55, 0xB8526623,
+ 0xDDDCB82C, 0x2A18B465, 0xB5FD564D, 0xA9647CB5, 0x4300919B,
+ 0x9FB2B27A, 0xDB25B0D9, 0xBB5D5711, 0xAA747FC4, 0xAA831194,
+ 0x9603ED14, 0xAF921A0E, 0xFA1447D7, 0x8B766768, 0xE8F1C89E,
+ 0xB7985D4, 0x6C5C1AEE, 0x2EA66EF3, 0xD176E7D9, 0x228CD940,
+ 0xD90C84B4, 0x36253A66, 0xADD7AE4F, 0xF25D5CA5, 0xD34F702F,
+ 0xA535AA29, 0xFCF10FB, 0x3D075696, 0x63EF7EF3, 0x81554091,
+ 0xC7EEFC78, 0xE0DCDB21, 0x62EFF001, 0x9ACFD7CD, 0xAEBA43ED,
+ 0x371BA99B, 0x508B7A31, 0xFF447B05, 0xA239F5D2, 0xA5620A57,
+ 0xA16B995A, 0xC334401E, 0x535F51AB, 0xAEA26D82, 0x81D72269,
+ 0x3C0BA1D2, 0x80590850, 0x818A26AA, 0xC43E6B02, 0xF72DFB63,
+ 0xE7AE3F6A, 0xD31AB683, 0xB99D787A, 0x691FFB53, 0x37EA1E35,
+ 0xC2C9FFF8, 0x2A13F6D4, 0x4CC79564, 0x6DD5F2DE, 0xC53560B,
+ 0x5A562B6F, 0x3F2C49F1, 0x6953F4CC, 0x8BA12AF2, 0x98A08428,
+ 0xA1EF80B3, 0xA977E388, 0x1A3DD9D1, 0x687A3424, 0x2759B568,
+ 0xC626A765, 0x7887651E, 0xFC9005E1, 0xE84376A4, 0x387BCF66,
+ 0xF7AA4980, 0xBAEE372C, 0xE89CF460, 0xA275FC1A, 0xA5EF8668,
+ 0x899F85CE, 0x9CB086A3, 0xF16158AC, 0x4C49EBC0, 0xDCE10FAA,
+ 0x4B46ABDA, 0x56947FA1, 0xAD4E7245, 0x54C23373, 0x8B0B6C4D,
+ 0x82590F05, 0x5E292D4C, 0x277B63C5, 0x9D51D8CF, 0x86D379EF,
+ 0x52CBEF63, 0x7A62AF4C, 0xAC1FA33E, 0x25D454AE, 0x1CDA792D,
+ 0x17434813, 0x759F50A7, 0xEEB0D38A, 0xB30964A6, 0x941230A0,
+ 0xA464FA3C, 0x9F8685AF, 0xB9A018F4, 0x8080362, 0x2D565F63,
+ 0xAB60790A, 0x67252A3C, 0x1715B01D, 0x5384E7F3, 0x79299519,
+ 0xA9786ABE, 0x1107A1FC, 0xE0D9B037, 0x4DD34883, 0xA7D476E3,
+ 0x5B194AE9, 0x89E50FB1, 0xA9676565, 0xC77CF621, 0x93612BF2,
+ 0xE027B80, 0x359C7FBF, 0x39B166FB, 0x1F3B28DF, 0x2848DE70,
+ 0xFFE261DD, 0xB78D413C, 0xE011DD7B, 0x286F752B, 0x74A8D775,
+ 0x5E540B67, 0xFAF973F, 0xC0035501, 0xB0F16059, 0x1C981017,
+ 0xD4871112, 0x9745C0BC, 0x6D85B805, 0xA40253E8, 0x2B0D55CD,
+ 0x8FF7EDC4, 0x47EB4ECB, 0xC41A2F17, 0x41C9702F, 0x8549DEE0,
+ 0x865FD46C, 0x64A1F181, 0x24E64D11, 0x13337A33, 0xE8CB0924,
+ 0x8A2DC003, 0x113C04C7, 0x1CA62E13, 0xC360E708, 0x57DE03AB,
+ 0x4D8F2BB5, 0x2CE2E2A1, 0x2580C90D, 0xBF162A7C, 0xEB1490A8,
+ 0xBCABC2A7, 0xFBC4C25C, 0xBC83AB6A, 0x25C47DCB, 0x8FE447A9,
+ 0x2C0F77CF, 0x6D896845, 0x63CEF5AE, 0xB2FF0326, 0x14D71520,
+ 0xA1C15C8E, 0xE53550FB, 0x676B299D, 0xC20A5C14, 0xDB3EC54,
+ 0x359733CE, 0x8A619B1E, 0xCDB53E, 0xD285EED5, 0xA6E0181E,
+ 0xB81AA3EF, 0x41F8E1A2, 0xE3DEDC6D, 0x4F7CBE5B, 0x24006857,
+ 0xACB9B719, 0x4E725B2D, 0x8536AF54, 0x329509E7, 0x72E7C0A7,
+ 0xBA97CC78, 0xD822798F, 0x9DFC6780, 0x63E263CA, 0x7B2397A5,
+ 0xA42C0C0B, 0x1D5EC588, 0x292F1E7C, 0x2BF5A75, 0xFCD8786B,
+ 0x14EB1952, 0x84031982, 0xA0800A40, 0x629C9211, 0x3B17F481,
+ 0x50861D9D, 0x8371A304, 0xB3D21511, 0x720E2C6C, 0x5A07F87E,
+ 0x868F95BD, 0x8617E7B, 0xD7762105, 0x90707C5A, 0x777473F4,
+ 0x67737DC4, 0xC4154562, 0x1840CEB3, 0x373635EE, 0x4E6D4EBA,
+ 0x1736A5EC, 0x4D3E335B, 0x59FDB9A1, 0x9162B39A, 0x3F9E1502,
+ 0xF661B3DA, 0x77BE0255, 0x65EC8603, 0x21FCA0B, 0x55291C5C,
+ 0x69F57B1, 0x5DE1E0D6, 0xA6296E1D, 0x595A45F8, 0x90B166DF,
+ 0x61ABB34E, 0xC6D48B5B, 0xB05EF88F, 0x368B0C6E, 0x94C36250,
+ 0xB435D440, 0xEFB62847, 0x1473E647, 0x9A101218, 0xC7AA11BF,
+ 0x80C241E3, 0xAF648F26, 0xDF48753D, 0x7073509A, 0xAB52665F,
+ 0xD1ECCFC0, 0x7BE293F1, 0x396CA014, 0x84336AB9, 0xF9B7E448,
+ 0x9566C90E, 0x239F7C25, 0x91A452B3, 0x1E9A4F1C, 0xCCE286F6,
+ 0xF46520D6, 0x2943A671, 0xAAA30DCF, 0x28D190CE, 0x88E3D0C9,
+ 0x423944F0, 0x81E6712, 0x2714B6B2, 0xF927748, 0x59A5430F,
+ 0xCBA530A9, 0x91E12A0E, 0x92598CBE, 0xE61058F5, 0x2604B4B,
+ 0x4CB7C3A7, 0x43B5812F, 0xFD90660, 0xD73DF50D, 0xAD3AE409,
+ 0xF74D721B, 0xCC2A88D1, 0xCED79510, 0xE64714DD, 0x3BDF0A8A,
+ 0xC2C7B689, 0x25B387D8, 0x968DA1A2, 0x8EA5D185, 0xF05F03E1,
+ 0xFDDC5B50, 0x78AECEF, 0xE32FBBA2, 0xD512F0AD, 0x5410D1B5,
+ 0xDBFD9FFF, 0xC0F2DD4E, 0xF66F8DBA, 0xF5EBA3C8, 0x65F96FE3,
+ 0xF7C8962D, 0x8E48A78, 0x255BEDC7, 0xE8FD3698, 0xFD1C4903,
+ 0xFDE9830, 0xCDBCF434, 0x16540D39, 0x418EF731, 0xB2F80637,
+ 0xDFCC0C9D, 0xB53DC5BC, 0x5A68B10C, 0xC4DCB3DD, 0x8B3778F4,
+ 0x7788B194, 0xECBD4903, 0xFD390223, 0x79598BFB, 0xBDECB9D9,
+ 0x29576BE3, 0x220F82A5, 0xDBB262F6, 0x1876EF0, 0xE2D9C444,
+ 0x32D5ADEF, 0x5F8739ED, 0xAF427122, 0x171E7D7D, 0xA5468BB4,
+ 0x94451936, 0x51565032, 0x3CE3CD5, 0xF231F54, 0x98614C6E,
+ 0xCE18455D, 0x958D2BD2, 0xA5934FE0, 0x3543931E, 0x77D9C2FB,
+ 0x3D3ED736, 0x6762E077, 0xF1B052A, 0x88AF353B, 0xB2A38925,
+ 0x8C919686, 0x715EEAAC, 0x34BA46DD, 0xEB486F1C, 0xDF58D7CA,
+ 0x90B97BE6, 0x37335293, 0x499414CC, 0x7F725BAF, 0x5ABEBF8,
+ 0xE9344F69, 0x1C110FD, 0xA937AD4C, 0xA7CDD9C0, 0x750FD5FE,
+ 0x7A7B6D40, 0x41EA948A, 0xA10EE17C, 0x7689C967, 0x9F411C02,
+ 0x6C40C3FD, 0xA6FFC648, 0xC6D6F914, 0xA100AF92, 0x4CD97ED5,
+ 0x17D9CCBF, 0x915833F, 0x788D78C0, 0xC81903A3, 0x6DE5BAF0,
+ 0x3E4D6DCC, 0x98415810, 0xEC23B7AD, 0x822471B0, 0xD2CF5D5A,
+ 0xA1BACAD5, 0x40843135, 0x430135A, 0xA7655BAD, 0x7A2472BE,
+ 0xCC3D44CC, 0xD1BC9E10, 0x7C215C92, 0x717FA7DD, 0x7EF7D128,
+ 0x1BC85798, 0x7C6E19CA, 0xE3FAB7E4, 0xBC884D38, 0x3E220CA,
+ 0xE7AE4D8, 0xC8EDD021, 0xF3F05D3E, 0xDE302EB8, 0x40CEFF27,
+ 0x56C0550A, 0x96162C92, 0xC004EA48, 0xE0C29A65, 0x496AE22B,
+ 0xC7468E6F, 0x8E31BD1F, 0xA53763CF, 0x166CC258, 0x1A2B9CC4,
+ 0xDBBADE7B, 0xF8D21AC9, 0xB21CA593, 0xB92F0DEE, 0x9A4391F,
+ 0xCDB4D373, 0xB687B3F5, 0x877BF0A0, 0xFD7395DD, 0x1C56AA87,
+ 0xCA146BB9, 0x21A2314B, 0x8207A2AC, 0xAA874DC0, 0x4F404E64,
+ 0xB69FDE48, 0x324FD456, 0x45F19CF, 0xFC7E6D0E, 0xC8A01C04,
+ 0x76C63378, 0xC526F7B3, 0xFDCD2EEF, 0xFFB2F9B9, 0x2DDE75AF,
+ 0x5ADF2F86, 0xC9AC84D3, 0x70FF53A0, 0x3FB077C, 0xC2795B30,
+ 0xF5438170, 0x557D7080, 0xB784684E, 0xCD089E1D, 0x332B71B0,
+ 0x493C3C2A, 0x1D1DED89, 0x8240E170, 0xA7D17522, 0x48C542AD,
+ 0xCB357D8F, 0x21E37C1, 0x3B000B34, 0xAAAE4818, 0xCD1EB4B3,
+ 0x1736CA0E, 0xDDF8EA2B, 0x76E21C4C, 0x6EE99A3C, 0x27F71B20,
+ 0xF6AE929C, 0x3C9CAF6C, 0x5CA7DA97, 0x8EF033C5, 0x8C7EC36B,
+ 0x3CB1CFAD, 0x1C5ABBB7, 0xDEF7A78C, 0x9CBC4A73, 0xB3871393,
+ 0x8C61DF59, 0x54DF941C, 0xCDD23FE8, 0x758EAD7E, 0x49BE795B,
+ 0xC960C6B, 0xE9B76479, 0xC88843F7, 0x82DC3137, 0xEDEE1A1E,
+ 0xC6568A7D, 0x42F7F484, 0xA6115655, 0x494779B5, 0xD95FE16A,
+ 0xB2AB15F4, 0x64C185B3, 0x9A46066E, 0x8BAE077E, 0xBAAE323F,
+ 0x79A965C6, 0x764B71F0, 0x3654F6D3, 0x96B4B2AB, 0x15C2B523,
+ 0x720AF416, 0xE6D0F423, 0xFAE44868, 0x6E776BC2, 0x264D41A8,
+ 0x3FE4BEE, 0x1598B97B, 0x15A70419, 0xA13CD124, 0x751A09E2,
+ 0xF7F7C12B, 0x718AC211, 0x11D03CD1, 0x2F9247BE, 0x77C210E1,
+ 0xA2268AAB, 0x2E99F0DD, 0x949D5CC5, 0xA8A309F2, 0x749EC6BE,
+ 0x5BD5124A, 0x8BF599E9, 0x3919AD4F, 0xA40901C2, 0xA1D4CC03,
+ 0x6ADCA36F, 0x9D5CCB0F, 0x870E2A58, 0xCEBC6333, 0xB2FA28A4,
+ 0x579C76A, 0x444849D0, 0x33887308, 0xB3BE3C75, 0x93745501,
+ 0xC289F137, 0x89739C7, 0x97C73423, 0xD627FB64, 0x6EE36F05,
+ 0x1F4B4B98, 0xFBB7A8AC, 0x60941E62, 0xC3A8ABDC, 0x4AC5E7C9,
+ 0x88ACE940, 0x5AA2AE59, 0x9F10C0B7, 0x8F45920B, 0x5FDE21BE,
+ 0x1D47779A, 0x3ED27D8B, 0x69FF2BB1, 0xCB1409FB, 0xF27F4FFF,
+ 0xA19E3DDC, 0x206050FD, 0xAD98C2D5, 0x4DA4BC0C, 0x95D9B019,
+ 0x556ABBFA, 0xBC78B5A, 0xF0F224F8, 0xA9785F8F, 0xED1CE98C,
+ 0xD368072E, 0xE212ACE5, 0xBB7F76E0, 0xB02F237F, 0x6D85C5AF,
+ 0x31539988, 0x4312BA19, 0x1D5023A7, 0x7320504B, 0x70563ABD,
+ 0x2553791A, 0xE9768150, 0xC1B2AF4B, 0x3AF0FD24, 0x3818D0E8,
+ 0x7F356F58, 0x98A15B0D, 0xAFA943C4, 0xB2B38831, 0x2E411F37,
+ 0xE3D5AF87, 0x67BEEC5A, 0x825E60CC, 0x1C44D856, 0x1A59493A,
+ 0x13BAABCF, 0xAEAA4D44, 0x5CFF2A6E, 0xFB47865B, 0xE778E607,
+ 0x101500E8, 0x2C17E66A, 0xA0B30350, 0xFC649CDF, 0x8B9802D9,
+ 0xAB87D61A, 0x21F38439, 0xD3D11051, 0x1FDA9955, 0xCB9313B8,
+ 0x327D1A94, 0x35293099, 0xB803B298, 0x5B8E6883, 0xFA309C3,
+ 0xDFDA8B2, 0xDF89211F, 0x9918F18E, 0xF0C05CB1, 0x71D8A4B7,
+ 0xE681031D, 0x537012F6, 0x4DF822F2, 0x34B75C8C, 0x4429F85E,
+ 0x5D3C4C4D, 0xFB0FC6C7, 0x25F4ECDD, 0xB19D5EFD, 0xD70FD7CF,
+ 0xD95C45D5, 0xCDAC06B8, 0x9C3B963B, 0xAB2F2A9C, 0x4D3D4F7D,
+ 0x12692C03, 0xB1AEF97E, 0xF243EFA7, 0x78C4C8DF, 0x182D9C17,
+ 0x8D2AF450, 0x7596BD9B, 0xE8E7C9C2, 0x86F617F8, 0x1F37A708,
+ 0x3F648305, 0x27FF6DF6, 0x4D5FF17D, 0xA9541C2D, 0x9773013,
+ 0x78B2313C, 0x82C0B20F, 0xD36A4F02, 0x8DB2BC4F, 0x9296D8BF,
+ 0xA983CC7, 0x31AEE908, 0x48CD7E6F, 0x9CB1DD7F, 0xAB89D57,
+ 0x5156132E, 0x6345AA59, 0x8D2CB12D, 0x94D3AE56, 0xA4E91B27,
+ 0xEE58338, 0x8620EA15, 0x5454D04E, 0x1142ACF0, 0xCA059044,
+ 0x31811D8A, 0xD498290, 0xB65F1B67, 0x462745F3, 0xA899191C,
+ 0xB9C19F48, 0x824659FE, 0x9A257101, 0xC330F34B, 0x42109127,
+ 0x9DA8504B, 0x6C3A989F, 0x5F426E6C, 0x2B922D32, 0x373C66FD,
+ 0xAFE3418B, 0xE3788682, 0x83B46626, 0xD0106A4E, 0xFD10B903,
+ 0xB0F6531C, 0xC65419E0, 0x3963952B, 0xB8799DF9, 0x3EEB8C1D,
+ 0x5C4D3C08, 0x6DD028A6, 0xA55678A0, 0xB8247141, 0xC1267586,
+ 0xF6746B19, 0x46C38465, 0x483D24B, 0x99BF79DC, 0x78F778C3,
+ 0xAFF40193, 0x58872B07, 0x6DA7F4FA, 0x66B5CEA3, 0xDD2D8C79,
+ 0x2A8D289B, 0xB5789670, 0x66AEFCE3, 0x56FB52B3, 0x20FE3BE1,
+ 0xCCDFB492, 0xB0F263E8, 0xD0707433, 0x5E58F5DC, 0x4ABEBE63,
+ 0x8A45CD95, 0x97037830, 0xBDB1F1B5, 0xA1BE2990, 0x57B718FA,
+ 0xD50EC023, 0x810DD849, 0xE650D43F, 0x3895C77D, 0xE142C382,
+ 0x35551E5B, 0x3B94330, 0xE92D8A91, 0x50BC837D, 0x61499A8F,
+ 0x2639B468, 0xF8FF36E1, 0x74956FC6, 0xFF0F4192, 0x6BBA0C53,
+ 0x5B44FF85, 0xBBE4A1DF, 0x12D6CB14, 0x6C679A10, 0x3C0F554D,
+ 0xECBADA32, 0x8A99BA10, 0x738C03C4, 0xB8902AC3, 0x7008D470,
+ 0x49BC2ED9, 0xFBE19B5A, 0xA1E4879A, 0x36129694, 0x94987C3C,
+ 0xE54B84D8, 0x9CFAEF1E, 0x527127DC, 0xA8FCAE0, 0x8699252C,
+ 0xDAAD4629, 0xC41F3866, 0x2559C272, 0xB1C25848, 0x3F9B1702,
+ 0x7C448BF3, 0x8CCEDF5C, 0x3A37F712, 0xFB9E4F83, 0x5754E801,
+ 0xB38FD367, 0x780F4825, 0x959330C4, 0xF6276BE5, 0xAE3E2018,
+ 0x182DC907, 0x88E733F9, 0x6FF870A, 0x79EF2D01, 0x3EAC0D6D,
+ 0x20D4FF88, 0xAE6EB8C1, 0x80810451, 0xC228E035, 0xBD942803,
+ 0x3F3733F2, 0x9F8F16F6, 0xAAA65031, 0x55E839BC, 0x7EAD3461,
+ 0x5F5BEE8A, 0x8668BDBA, 0x399366DB, 0x2A54237E, 0x776789E,
+ 0x7B171AF5, 0x8C9FCB92, 0xD87465F2, 0xFA3CAAB5, 0xBA5B131E,
+ 0x1FD2D438, 0xDCAA9DA, 0xE1BF0AAA, 0x1EAEA8AE, 0xEB46A646,
+ 0x989D1EA2, 0x98E8B45F, 0x12A2415B, 0xD107D293, 0x5F54D087,
+ 0x95AF5C33, 0x2A12BA88, 0x6381D0FF, 0x688EA1E0, 0xACC60CA2,
+ 0xF19636C6, 0xD4D465E2, 0x2A50DC57, 0xFB595CCF, 0xF5C63674,
+ 0xB4965626, 0xB903D3D0, 0xD9581548, 0xBBD9E82E, 0xE22BCEF3,
+ 0x9FE759D, 0x6E8D8F4E, 0x655325D2, 0xE1986814, 0xEA2B93BF,
+ 0x88085C18, 0xF82BFCB0, 0x3FCF713F, 0xADE03EDC, 0x2D2DDCBC,
+ 0xEDE2694E, 0xF6DFB11D, 0x5CF35A5A, 0xD38C82D3, 0x52DE32CF,
+ 0xB88EA70E, 0xF7FB134F, 0xAEC78D1E, 0x58402C66, 0x54CD1763,
+ 0x78A7EB4, 0x88F49C30, 0xDC17F8C0, 0x9C49A368, 0x926E18EB,
+ 0x4DD461E1, 0xA6BD8F3C, 0x6D2E4C31, 0x657506D9, 0x445EF83F,
+ 0x77E28461, 0xF715400F, 0xBB76D1D, 0x9B670CD2, 0xCEB9EB90,
+ 0x7F297088, 0xD3929A52, 0x9B62909, 0x46474012, 0x3D74DFDF,
+ 0x46288EF0, 0xF0C51C07, 0xEC642B66, 0x3C76B83C, 0x1E72D08F,
+ 0x9F95DC1E, 0x106883C5, 0xB6A867BD, 0xA532C423, 0x95076036,
+ 0xA9DBEA73, 0xA3F8C65D, 0x799CF6BF, 0xA4508346, 0xB37CACB2,
+ 0xF6A07B5A, 0xA2C24137, 0x2E1D8DEF, 0xD28C26AD, 0xCE745089,
+ 0x3B7D9638, 0x7189CE82, 0xBC3F7850, 0x5660A9B8, 0x13895B5C,
+ 0xFA59A643, 0x9B0FF4AF, 0xFD2B4FD3, 0x4C0C4E52, 0x272631DE,
+ 0xA52FAE47, 0x65850A25, 0xD51ACF2B, 0xD206E6EB, 0x3CDC96EB,
+ 0xA6FF9E3A, 0xFC601E27, 0x658EF7F0, 0xB45FF508, 0x36A9A571,
+ 0xCE75E7E9, 0xC4BF9261, 0x3A261099, 0xF1B1CE3E, 0x3D28A165,
+ 0x3435D2FF, 0x70830AAE, 0x8DFE14F7, 0x3E27CDC1, 0x97BE4BA1,
+ 0x33F8D0E2, 0x9B2E7BCD, 0x1923B1C, 0xAA248E78, 0xFDA8AEB9,
+ 0x7825E511, 0xBF20B777, 0x218E4234, 0x7B5D1181, 0xA08988A0,
+ 0xD9009231, 0xEB15A567, 0x47E045A0, 0x3C515808, 0x35194ACB,
+ 0xA476304A, 0xEF738BD6, 0xD035FB8C, 0x3B2013F4, 0x4DE60F26,
+ 0x361431DC, 0x82ECB228, 0xAB22266, 0x4E056EEE, 0x6642D288,
+ 0x48D851E3, 0xE05D55D9, 0xDC2D6D4F, 0x158F7F48, 0x5D7F7D5A,
+ 0xC2835158, 0x793509C5, 0x479DF33C, 0xDEF0696A, 0x9FC2BECD,
+ 0xF4EFC675, 0xF8D1FF02, 0x493D3BD6, 0x7FA1C10F, 0x641B324D,
+ 0x996DBDDD, 0x24098529, 0x81CCFC35, 0x47F0BE17, 0x5E241815,
+ 0xF7F62788, 0x261CDAF5, 0x10CBC4B8, 0x5D6C6A7B, 0xD671AE81,
+ 0xB2C8DCD9, 0xD215CB7E, 0x3403AB1B, 0xA7C5999, 0x4675A50,
+ 0x369C560C, 0x32C619D9, 0x4FD2E12E, 0xB4A20359, 0x37E93502,
+ 0x5EC0CE10, 0xB374340, 0xB0DF0419, 0x5960ED4F, 0xF0A7770E,
+ 0x7F504F30, 0x54A92972, 0x3E9848B8, 0xCD980ABE, 0xDE69D570,
+ 0xA9FDFFBD, 0x9812C681, 0xDAFCCF4E, 0x2B636CB5, 0xB2B9FF2D,
+ 0xB9972800, 0x701231C6, 0x2E1108F8, 0x8C323A3E, 0x20A17A77,
+ 0xF2C6CC7, 0x44C5FD1C, 0x731622D4, 0x9BF0C91E, 0xB61CD1B1,
+ 0x61FA9CF2, 0x5E460518, 0xF75A1C06, 0x417CCEE2, 0xB45E0FB5,
+ 0x53DC30E8, 0x500CBD7F, 0xED61DAE3, 0xEFE91818, 0xB56814BA,
+ 0xD37D84C8, 0xD5DA9ED7, 0x5F40F92, 0xF1507FAD, 0x2CC74A65,
+ 0x32AA6279, 0x33731317, 0x30E09F03, 0xE1D9C403, 0xC21E638A,
+ 0xA7394D05, 0x3879F710, 0xDBB52C37, 0xB7780268, 0xE268E178,
+ 0x9F8072D3, 0x97CC035A, 0xEE65287D, 0xA197441A, 0x21C8AFA4,
+ 0xB81B50A9, 0xAF6ACC93, 0x7BB55B77, 0x564A0BD4, 0x17F7A6A9,
+ 0x36627846, 0xDCE746EA, 0xBB9762DE, 0x47B5B8F0, 0xEF5DA4AD,
+ 0x1922E420, 0x15F9299D, 0x243DAB0D, 0x953C67A3, 0xF3DA71D8,
+ 0x57122A3E, 0x423A78B, 0xC4A53000, 0xFBE92583, 0x968F3AE,
+ 0x61629123, 0x792FA07B, 0xBF45729D, 0x99DDD38E, 0xA14565FC,
+ 0x268E9E3F, 0x7EC9286, 0xCCA1D92A, 0xF06519DA, 0x22396664,
+ 0xD5DAC24D, 0x71BB4DD5, 0x7D329BB3, 0x401DAB69, 0x19D3E40A,
+ 0xB6F40F32, 0xE8D1CAF8, 0x5CD5F35D, 0x6F662316, 0xD38D1A6C,
+ 0xF86E720F, 0xE165D1B9, 0x1BC14E79, 0xC19FB43D, 0x891C013B,
+ 0x44AED4DC, 0xA7351AAC, 0x5F707A18, 0x3850148, 0x4A425E1,
+ 0xF7DD6EBD, 0xE0C3FD0E, 0x8266A425, 0x3BA17650, 0x48753ADB,
+ 0x679FA015, 0x88771712, 0x2174B185, 0x29F9A85A, 0x1560964A,
+ 0x198E4FCD, 0xD3410A86, 0x9186793D, 0xDAFC5C35, 0x971F4CC8,
+ 0x1F8F0E8B, 0x11A884F2, 0x66E6D2AC, 0xE85ECDB0, 0x86C76472,
+ 0xDF3B3320, 0xEEF446A6, 0x834CF19B, 0xECEA602A, 0x46C680AD,
+ 0x807BA92F, 0x4B3FC42B, 0xEC229845, 0x3FE389C1, 0x63E042D7,
+ 0x6C855119, 0x7B1ADF33, 0xE1B9CAE0, 0x62C20BAE, 0xEDF0E919,
+ 0xA50FC7EB, 0x2399262F, 0xD6F88130, 0xE2ADA5DB, 0x7D07BC3C,
+ 0x36A922F3, 0x7693B84E, 0x3015CD0C, 0x1D1047A7, 0x5D3A75A5,
+ 0xEE6F1CA9, 0x734BD19F, 0x3308DD73, 0xCEBBC9FA, 0xF79DD5A6,
+ 0xA41CF168, 0xED762FD8, 0x6642159, 0xA63C5CD6, 0xCB96A282,
+ 0xA29D9F5C, 0x45CC6CD4, 0x344611EF, 0xC345FE03, 0xC55ADDE0,
+ 0xB2B8374C, 0x14F730B1, 0x301D9266, 0xA2D98FD8, 0xBC107DF,
+ 0x59905EE3, 0xDB3560DF, 0x1D49F4F3, 0x785F8E0B, 0x8B116097,
+ 0x56154F60, 0xE312D829, 0xE0AFAE9B, 0xEAE3692E, 0x95915B8F,
+ 0x83BEEE75, 0x48C1C92, 0x8166D95E, 0x697FECA8, 0x135DEBF9,
+ 0xF83E6507, 0x11570809, 0x4862CBDE, 0x820E288D, 0x6CA59B2B,
+ 0x49DF6AD5, 0x86F41C43, 0xDD128A28, 0x601198A0, 0x3DDD49CB,
+ 0x95F3ACCE, 0x500CD9D6, 0xF54A50F2, 0x9936957B, 0x7C881875,
+ 0x743B055D, 0x44FD7934, 0xAF2253BB, 0xA2F4A27C, 0xBA8E1C2B,
+ 0xCCFA3259, 0x892FC73F, 0x283E74B4, 0x86119027, 0x87961F02,
+ 0x1D015187, 0xBA83B762, 0x61948B32, 0xAC741667, 0xFA9E0E39,
+ 0xD440D9CB, 0xED93F9F, 0x5FA97905, 0x2F5F82D8, 0x92EC7646,
+ 0xC60B3F9, 0xAA28822A, 0x7BA7CD3D, 0x3E41A20B, 0xDE4441A9,
+ 0xC75E539B, 0xD9D568C2, 0x2DCAE06, 0x7762550, 0x21C2D5EE,
+ 0x95CB6C94, 0xE31FC800, 0x3C03C172, 0xE166E564, 0x359C5102,
+ 0x7F717599, 0xBE301B47, 0xB207FA5C, 0x38B8B24B, 0xE6EFF05D,
+ 0x9F09D305, 0x31A27808, 0xC56D934F, 0xB440BD60, 0x52B1AAC4,
+ 0x78654045, 0x106A67B8, 0xF2A861E5, 0xC45D72B0, 0xA8FF8296,
+ 0x97F475A6, 0xDC222733, 0x7A835D7A, 0x45774E9A, 0x9E558C34,
+ 0x1124605D, 0x1689FED3, 0x70AB9928, 0xADBF8E55, 0x9C09EE27,
+ 0xF95A8C49, 0x75CD52D7, 0x4FC7275A, 0xA46C29F6, 0x747D788,
+ 0xA3347E5, 0x5B08AB02, 0x13CDC08C, 0xEDB65176, 0x6B36600A,
+ 0x26F5AD2A, 0x39949D1, 0xA1C8F6E5, 0xEBF0CEFF, 0xAB60A06B,
+ 0x10E522E8, 0x80E056D8, 0x1B301392, 0xDC3E0B07, 0xE10174EE,
+ 0x25DC4733, 0xB4E5A24A, 0x4B569CFE, 0xCCFE9F0D, 0x19BDC038,
+ 0xF8A0A718, 0x9944E8E0, 0x9591528, 0xBF27BDF1, 0x2C160255,
+ 0xF9E2F1B, 0xCE4FD96B, 0x703B2A77, 0xDB6EB2A7, 0xBFC2FA6A,
+ 0x11D00F81, 0x9540FD8D, 0x75849882, 0x183AC87C, 0x91DD1783,
+ 0xA3A0CC0D, 0x47F1CED1, 0x4DA4EE62, 0x819BA59E, 0xD5DA1DA5,
+ 0xDC218BF5, 0x899CC3A1, 0x1DECAD82, 0x77E193A5, 0x9F390C10,
+ 0xF5FCD674, 0x1E43657A, 0x6B61D25E, 0x99B9140E, 0xFEFB9CF9,
+ 0x6569445D, 0x14C9A2AF, 0x85A33FB1, 0xE4029ADE, 0x4FABD0FB,
+ 0xDE02379B, 0x65C8311F, 0x3CF60630, 0xC8B179FF, 0x9D83CE64,
+ 0xFF683C7E, 0x6D796948, 0x249B0AFA, 0xC5A65FDF, 0x252DA26D,
+ 0xFE92E52E, 0x90D081E5, 0xC5A8E180, 0xEBDB0943, 0xB0E7C78B,
+ 0xD5A89E4D, 0x684EE280, 0x8AAB613C, 0x6BD1547, 0xD12F7355,
+ 0x9C5D1363, 0x91E410A4, 0xDC841FBA, 0x703A9371, 0x79F8663,
+ 0x553650FC, 0x633CA726, 0x20107BD7, 0x2565F252, 0xCDD93830,
+ 0x3446CF7, 0x92B6B42A, 0xA070B2D1, 0x5E0384D1, 0x7CC5A19C,
+ 0x6890558F, 0x10D308AA, 0xDFF3016C, 0x1093AA3B, 0x8927683A,
+ 0x9259502B, 0x2B544B7C, 0x419B1B1A, 0x22D9E939, 0x568ECCEE,
+ 0x4F3CE09B, 0x8B990521, 0x8D6906A3, 0xC15DEDC4, 0x98384A4A,
+ 0x8F2F2652, 0xEDB9D614, 0x1D010AC3, 0xA2CDC134, 0xEEE9A9ED,
+ 0x241DB9A2, 0xE9DB9AE7, 0x7A788F9E, 0xBD0778B7, 0x27373539,
+ 0x7C6B4A4B, 0x3C7A6B37, 0xDE1C625, 0xC1256E67, 0xB8E69163,
+ 0xCC05D09B, 0x728A1427, 0xECAC2530, 0x1DD40BC8, 0xEFE42E56,
+ 0xB4266BE0, 0x9AD3F869, 0xDDFC2F60, 0xEF29B3F7, 0x7C15F90A,
+ 0x705C2992, 0x99AC7AEA, 0xCF1F09A0, 0xB41F14D9, 0xBF3C252C,
+ 0xF3483286, 0xD3AC398E, 0xB84BC93D, 0x6B780D11, 0xF682D379,
+ 0xB8A062C2, 0x9A003A9E, 0xF18F54FC, 0xDE81BB83, 0xE84C5234,
+ 0x37CB67FA, 0xDB685C6, 0xBF2BF28D, 0x8CDE583, 0x94CCD0BD,
+ 0x8BCAF516, 0x31BE93C2, 0x3ED4B623, 0xCD23346E, 0x8254E7A0,
+ 0x6091EF1F, 0x17A42562, 0xC9821677, 0x447B6623, 0x19D9356C,
+ 0x4A1C1953, 0xD1F3B7F9, 0x99F8388D, 0x62F22304, 0x5EDF1ECA,
+ 0xB6C9FC2F, 0x42968E22, 0x531BD76E, 0x25E6A95A, 0xA1669784,
+ 0x8B915BD2, 0xA5E21483, 0x5ABE3226, 0x605C0E15, 0xFDE713CC,
+ 0xFAC58D3B, 0x44FAF6E8, 0x41E2D699, 0x8EE11E34, 0xB03BE4F6,
+ 0x75054C0D, 0x1AF2D37, 0xF38E6829, 0xE7F2A519, 0xC9CF2CFF,
+ 0x996DDE8, 0x395AC493, 0x42AFF184, 0xB380B71C, 0x11AA0B90,
+ 0x66DC636, 0x56557CA8, 0xCB8CAA43, 0x9EBF806E, 0x63F66159,
+ 0xA011191D, 0x17B0AED3, 0xB9621251, 0x2B189E3, 0xD45A5D7,
+ 0x23009D12, 0x5DEB7918, 0xFDFB1FC8, 0x46808A73, 0x91D29330,
+ 0xF872C15D, 0x7BE90206, 0x257E9FCB, 0x2E52FF67, 0x1852DDF9,
+ 0x6A2C5C49, 0x6ACF891B, 0x29FFB0E2, 0x76E32CD2, 0x588799,
+ 0xD71D970E, 0x9B079EC8, 0xEBD25420, 0xDDB60276, 0x761B106F,
+ 0x871473C4, 0xBC697CE2, 0x5378E0E9, 0x8DAECE28, 0xE5B275FA,
+ 0x6E6E332, 0x853884E7, 0xD0FFF1A2, 0x722D372, 0xDD5A754D,
+ 0x87CDDA3C, 0xA9B629C0, 0xAB2E650D, 0x1709413D, 0xDAE63819,
+ 0xC60DE8CA, 0x9F344BD6, 0x8E651EF9, 0x3B6A8019, 0x95CC1296,
+ 0xB12DAEAB, 0x8D550156, 0xF14E85AA, 0xD2547469, 0x6336E320,
+ 0x223B05B9, 0xB88AD493, 0xEE14916F, 0xC78AF1FE, 0x65FC2787,
+ 0x778FA85F, 0xBA23A57E, 0x957EA954, 0xAE4F9577, 0x47C38D4F,
+ 0xDB7BCDC9, 0xBA13E42E, 0x46B01094, 0x1A15F5E4, 0x315AB789,
+ 0x9E44B54F, 0x8C690B2F, 0xDC4954CD, 0xF176F3FF, 0x9B154C06,
+ 0x112BD6D0, 0xCB120BBC, 0x11101771, 0x1F29A19D, 0xC3F8193A,
+ 0x805D6739, 0xE3B00ACB, 0x23DD9494, 0x4F88EBA5, 0xE6F32E0E,
+ 0x4B76F089, 0x43B66BEB, 0xF2420B12, 0x2CFC5E01, 0x1C68D3DC,
+ 0x30C1BD38, 0xF3A0FCCA, 0x2AF13CD5, 0x13E38185, 0x2DEE2A21,
+ 0xFC318E26, 0x1954D4B6, 0x3FB86424, 0x24D698F1, 0x4AB76D48,
+ 0xA9E87BD9, 0xCE1DD2F2, 0xF5904D9F, 0xF614DB18, 0xF83111D,
+ 0x1FB56EFD, 0x5CBD08D8, 0x2D8D4884, 0xE388C534, 0x413D5BB8,
+ 0xEB6D14D6, 0xAE54E361, 0xF73D926B, 0x43F27197, 0x7C50A2E5,
+ 0x10EDBD6C, 0xD151B569, 0x47C50C06, 0x8FD59E74, 0x551C6841,
+ 0x2EC2B6DC, 0x5CEAB3A9, 0x1E6A1609, 0x3FB07FED, 0xC0D5849A,
+ 0x6354A21B, 0xEBF18830, 0x2BB3EBBD, 0x9D4DF510, 0xBBBE1103,
+ 0x918D6DDF, 0x3FEE7A8B, 0x4FC47254, 0xE0E1EA65, 0xF3DDB31A,
+ 0xADF8DE67, 0xADA31FAF, 0x2BC0B8A2, 0x184B7432, 0xFDB2E733,
+ 0x236B014, 0x21062C, 0x8FAAD8D7, 0xA1DA7E44, 0x3EF7F42F,
+ 0xA67AAB82, 0x9238F0D8, 0x42F93C63, 0xEF0F4BA1, 0xE61DC644,
+ 0x994EF92C, 0x71A58613, 0x371665E5, 0x82E77BA1, 0x2FFA1DAE,
+ 0xFE19AAA0, 0x95C72A53, 0x6A21395F, 0xC03F853C, 0xBC7B73BC,
+ 0xED62A949, 0x4F7D3C52, 0xCACFB353, 0xA1629BE9, 0x16255784,
+ 0xAE465FC4, 0xE7FC2626, 0x5E9B0FC2, 0xD109084D, 0xE30E7B89,
+ 0x94CD7424, 0x6127AF6E, 0x7D08ED7, 0xFA0B9293, 0x450A112F,
+ 0xD0D79344, 0xA204F8B0, 0x5F825780, 0xD681148D, 0x71C6AE83,
+ 0x1DF62587, 0x99ABC8A6, 0xCFEE8131, 0xFCD11719, 0xD0D48B0E,
+ 0xCC4A710E, 0x7414791C, 0x22167734, 0xD17FE049, 0x5BF15C46,
+ 0x30B718E0, 0x6E85104E, 0x52F72575, 0xA17F09E1, 0xCDA7B24E,
+ 0xDAF7D03B, 0x3632D94B, 0xBAF4E9EE, 0x390CD998, 0x168C055E,
+ 0xBC2D8D0D, 0x35E9F642, 0x89757E1A, 0x2BB98011, 0xC19BCD15,
+ 0xEEB73587, 0x6A5194EB, 0xC2C1B4BA, 0x3C8F73FC, 0x8F075D29,
+ 0x42D39406, 0x6674167A, 0xC0904A73, 0x1158FE6B, 0x4CAD2FAD,
+ 0x9A7EC8A5, 0x651960A6, 0xD0329ECA, 0xF5130525, 0xCC7C40CD,
+ 0x259AA3D8, 0x9669412D, 0xB92D39A5, 0x29B217D2, 0x27A07E25,
+ 0x9AFFD359, 0x7E8F5AC9, 0xCF7C0F61, 0x5B4F8D7D, 0x31C4E97E,
+ 0xBDB9599C, 0xA85BD7E0, 0x87F0BAAB, 0x2852E628, 0x377BD41D,
+ 0x4B54844, 0xDABF47AE, 0xA1B7AF6B, 0xCCF57165, 0xA90C4348,
+ 0xDC1CE2FB, 0x42582D37, 0x2892F4E0, 0xB89AC8E9, 0xB2718E40,
+ 0x93BCCE08, 0x5606C693, 0x1952D10D, 0x96609D8F, 0xEE3BC3C7,
+ 0x2DFA50E8, 0x5582FD75, 0xBDC2618C, 0xA3D922EE, 0x8F766106,
+ 0x184ED901, 0xDAABDE09, 0x40CBD4E2, 0x4A9A2A70, 0x9814D393,
+ 0xE394A090, 0x9EA06A4F, 0x2EC8C8A2, 0xFD2EAFF0, 0x2F6C96B5,
+ 0xBB17EF37, 0xDA677FE2, 0x2357E330, 0xA8C9DDED, 0x735A7B2C,
+ 0x41C2B39C, 0x787E099A, 0xFBF8204F, 0xA56A4B69, 0x7DE2860,
+ 0x34299BB3, 0xD1CAE881, 0x5F452DDC, 0x700904E8, 0xC3B47017,
+ 0xF7040305, 0x5C42BE94, 0x88AAAE53, 0x9FCAAD72, 0x2774D420,
+ 0xDD685357, 0x80499592, 0xC5FB26E7, 0x90BA598F, 0x4A13D60A,
+ 0xC6D5F72, 0x97C35532, 0x6580493F, 0x9D31E266, 0xEF926A38,
+ 0xF68CF9C6, 0xF770C570, 0xCA18C06A, 0xFA2BB2, 0xFBA375DC,
+ 0xC2FE76ED, 0xB91611FA, 0x528A8EA5, 0x360A527, 0xF631D04B,
+ 0xF0C67ECF, 0x4E490A69, 0x19DB46F0, 0x497DFBF4, 0x58E490FC,
+ 0x24A51378, 0x186BDC14, 0x90E633A3, 0x6D6F8D95, 0x2FDE02DD,
+ 0x4B2714A6, 0x6FC87FE0, 0x21569667, 0xDCC31F06, 0xC9D9DFD0,
+ 0x830AA4A4, 0x78FBFE69, 0xDF17CD55, 0x3952AAA7, 0x9A4B5A7D,
+ 0xB1EBF3EF, 0x4F3BC1C9, 0xDFEEBF40, 0xAB130CC8, 0x1EB84425,
+ 0x4625E802, 0x20B990D6, 0x4E36869F, 0x5EEC0472, 0x29194460,
+ 0xCA425ECA, 0xEB0742C, 0x17D07C02, 0xF38BCA14, 0xBC9D555E,
+ 0xF15822E7, 0x89CF96E0, 0xAA848F9C, 0x90731AC9, 0x86EECBE3,
+ 0x308F3257, 0x5FF375DC, 0x1E62C041, 0xFDB6A3E7, 0xDFEBED8E,
+ 0x8FC77E76, 0x6973E542, 0x2AD1616C, 0x99B549C6, 0xD28CF364,
+ 0x88C87768, 0xECA2CFB, 0xA0D0B060, 0x42DFFD8, 0xAF80A6DE,
+ 0xFF323760, 0x1CB2DAAA, 0xD11DE4FC, 0xEEBF565A, 0x9C986CAC,
+ 0xC1C95B3F, 0x6868BF0, 0xF5604930, 0x316DD9EF, 0x1231D331,
+ 0x95E38E67, 0x7D30C191, 0x354804BA, 0x265EE5E, 0xC6728C70,
+ 0xD36F32D0, 0xBBEA0ECA, 0xD055ED76, 0x9135E317, 0x8A7B9770,
+ 0x4D1344B0, 0xE9F29AE3, 0x7BA303B9, 0x2C38AEC, 0x82ABCBA6,
+ 0x7729F177, 0x71793932, 0x6FE6E38D, 0x1F8416B, 0x147D8310,
+ 0x6A962FEC, 0xFE2F100E, 0x4FB1D511, 0x3D38AB33, 0x58ADC416,
+ 0x64B07504, 0x458CC4B4, 0x584BC93E, 0xDE49B6D1, 0x7347876,
+ 0x4A2C3EB6, 0xDF5DE09C, 0xBFD376DC, 0xC9F451C5, 0x5F793A0,
+ 0x892952A2, 0x15060767, 0xE1E3B589, 0x4D513C3F, 0xAF3D2CC7,
+ 0x289DAA2E, 0x8C711417, 0x62E5E006, 0x3BECED98, 0x99E73ACC,
+ 0xDE156054, 0x1283655B, 0x5123FC41, 0x3DE21841, 0xC032F050,
+ 0x94B5151F, 0xA5577757, 0xCC0C8DF, 0xBDB52821, 0xD530FAAD,
+ 0xD070D8FC, 0x46F5BB68, 0xB02DFF88, 0xD4923EA8, 0xC85A5622,
+ 0x93E834A3, 0x38E84468, 0x79408C75, 0xCCB635, 0xE76BADA2,
+ 0xC2296DA1, 0x711543BB, 0xF441F4A2, 0xBD18127C, 0x8385BFB9,
+ 0xD350D4D, 0x90FAF999, 0xABD1A695, 0xFCEE12C7, 0xF428912A,
+ 0xC9759F80, 0x6DB6491, 0xD1421D30, 0xBC398DC4, 0xB8E0A889,
+ 0xC854AA72, 0x82CAAF64, 0xBB6A65BC, 0x6DCB2D0B, 0xD215ADB,
+ 0xF45033DE, 0xC1300029, 0x665C61DF, 0x756D1875, 0xBD2CF722,
+ 0xC477E3C7, 0xDDD97C9B, 0x89AE48E4, 0x65000FDC, 0x1FD717CD,
+ 0xBEEA764A, 0x8FC2DCB7, 0xA162EFB3, 0xD4AC2490, 0xCDA9A72A,
+ 0xBFB4EE17, 0x66C73CBB, 0x6B7CB021, 0xCC5AF099, 0x5389E8B7,
+ 0x7668286B, 0x31A223BC, 0xA66475FF, 0x9C3DDA93, 0x2F3171FE,
+ 0xDB89A7DA, 0x1699616B, 0xA380F010, 0xB05D7388, 0xD774EA44,
+ 0x64D6091C, 0xF23298F8, 0x71C88081, 0xF90C4A04, 0x2FBEEA4F,
+ 0x2F9178BB, 0xF8723D8A, 0x1C07FCC8, 0x36D24E08, 0xE02A8B61,
+ 0xFD6312AE, 0xA7DDCE9B, 0xAE45AC52, 0xCA2EC55C, 0xEEC6BE42,
+ 0x244F3D79, 0x994FB339, 0x8316CC43, 0xE3CEC898, 0x8D37639,
+ 0x833D21BB, 0x4333A2F7, 0x95F3B0C0, 0x7258174C, 0xBFCF0EF7,
+ 0x9A7F4883, 0x71F2406B, 0x16B2BA04, 0xE1BCEA70, 0xE3C6798A,
+ 0x3FBF481C, 0xF5A8D117, 0xB37ED250, 0x49AB5E0D, 0x2793A7EB,
+ 0x45DF69A7, 0x4EE4B815, 0x98259530, 0xC223CA40, 0xDB7B208A,
+ 0x4AD3C0F7, 0xE7C33E50, 0x49FD7631, 0xA228021B, 0x2C27FCB2,
+ 0x5F77BCF4, 0x65D593D4, 0x7C700797, 0x6E67920A, 0xEABAF033,
+ 0xBFC8B68B, 0x8835B368, 0x90CACC99, 0x6B90E022, 0xF2466D89,
+ 0x432DED25, 0xEFC94B45, 0x3116C3E, 0x1BBFBC45, 0x8FBC3D21,
+ 0xFB2039AA, 0x50679156, 0x450F8837, 0x73C7F87D, 0xC27898A7,
+ 0x7F48E602, 0x5064FCB3, 0x1EB6F58F, 0xE647C845, 0xBC8E84EC,
+ 0x5C4B8FFC, 0x440A88B7, 0xA490480E, 0x371DC115, 0xE1F236FE,
+ 0x4D65A2C5, 0xA965B0B7, 0xD05512FB, 0xDFAB9656, 0x191C627C,
+ 0x56B7FAC3, 0xF304A2E4, 0xC7ED6DF0, 0xD09B8C49, 0x1A1E777B,
+ 0xE70746BA, 0xEB582E9C, 0xFA6014DD, 0xB3B67784, 0xD3F64D81,
+ 0x318872EA, 0x4D241611, 0x134DF119, 0x2EA55DFA, 0x71A8D182,
+ 0x15AFE856, 0xD5CD885A, 0x5EA2B899, 0xF87BC7FC, 0x25DE8D6,
+ 0x93837315, 0x341C3698, 0x58534F, 0xF10652DF, 0x18C92AA4,
+ 0x17E969AB, 0xC12D08D, 0x6B0D0FBD, 0x40ACD3E2, 0x8C3AD43C,
+ 0xFDE55C9D, 0x25A58094, 0xBBCAB168, 0x2F06ECA1, 0x9D23A101,
+ 0x6F850449, 0x769C743A, 0xB63FD349, 0x3B3C852F, 0x1EC89061,
+ 0xFE8C7369, 0xA19C0F73, 0xB682F1D3, 0x48DAE3D4, 0x7F9FD390,
+ 0xEF784A6E, 0xCB23F15, 0x7BEB1E0E, 0xCBE90203, 0x6979F11D,
+ 0x251C50A4, 0xDAD9C59F, 0x5E4E5BFD, 0xCCD4DF48, 0x72BD66E,
+ 0xE7FB1B35, 0x75B4B83B, 0x29E9282A, 0x2590317D, 0x7835F9A1,
+ 0x25D3602C, 0xCFEC2E4F, 0x9CA2B0E7, 0xA4714302, 0x8F3D53C4,
+ 0xDE00F109, 0xC26D6273, 0x3E8DC623, 0xE3A972E2, 0xF67DF096,
+ 0x781682A5, 0x6C16F144, 0x49DC8D17, 0xB2EB82EA, 0x3CB93D91,
+ 0x44D4D3C4, 0x556040F, 0x1406DD74, 0x55FA83ED, 0x91C35357,
+ 0xF5A1C63, 0xA64E34D0, 0x7DF58C80, 0x62E97E52, 0xFBA1A2FE,
+ 0x8CB29D60, 0xDC1AEDE5, 0xB260BBF, 0x1AD9C6A6, 0xC60E9788,
+ 0xAD9DFA42, 0x2E422C17, 0x51CB5E86, 0xEB840466, 0x2666D5D8,
+ 0x7A0F7C62, 0xDE052A31, 0x6F0330C4, 0x9142D4AD, 0xDC8578C9,
+ 0x978F3E76, 0xEE43CB4D, 0x14E7EFC7, 0xB50B064B, 0xD7FB2900,
+ 0x67C4F4A3, 0x4D1193D7, 0x5091FB73, 0x3EB9C846, 0x960BE069,
+ 0x88250E7E, 0x94503385, 0x1C1F244A, 0xCFD72CE3, 0x8CD5F105,
+ 0x2B34131F, 0x60D266E2, 0x16BA806A, 0x25C25A42, 0x5FF6C068,
+ 0xD23A191F, 0x7AB5C53D, 0x9EA37FBB, 0xD1AD4B07, 0x40BCB39C,
+ 0xF45C8526, 0x80FEF5BF, 0x197D6D43, 0xD56FD4D0, 0xF39E498B,
+ 0xFB4F6847, 0x84DF289A, 0x2246F5CF, 0xF979B823, 0x42DCD843,
+ 0x1AB1BB0C, 0xABEC5FCE, 0x6E7EBC1, 0xE013DB54, 0x73BC8A04,
+ 0x88D0F71E, 0x4D93B6D8, 0x57B0B7CF, 0x99371728, 0x86B129E9,
+ 0xF4EB3DD2, 0x6956AA9D, 0x4C84AA0, 0xFD22CA10, 0x36E6915F,
+ 0xC830D7EA, 0x1EE1666, 0x1036A43F, 0x3FC86E7C, 0xF10F9CD2,
+ 0xEFF5F21B, 0xBF9082E0, 0xDD0DD00C, 0x80524F27, 0xDD5A3222,
+ 0xEA53B93F, 0x7FDA09AC, 0x89840C97, 0xC3A9BDCF, 0x1EC26899,
+ 0xEBCAF99C, 0x2EBB3226, 0x936A3254, 0x2E1E1786, 0x57E4CB9C,
+ 0xE5CDBE5, 0xFBA2458C, 0x48F3D0EF, 0x74FD06AB, 0x96C30795,
+ 0x14FEF0E9, 0x2F5FBA0C, 0x3CCEA60E, 0x7BA0354A, 0xCD7329FF,
+ 0xD4169550, 0x5FAA5E66, 0xF0C25CA2, 0xEBCC8065, 0x3F147D8F,
+ 0x5ED3293E, 0x6457117D, 0xE4CF4B98, 0x11F1E74E, 0xC13F47EC,
+ 0xBC7E22DC, 0x22512D19, 0x9140ACBB, 0x490D52F, 0x3E2D54C2,
+ 0x9FCBBC1B, 0x89646A33, 0x9FE4B65F, 0x92CE9ECC, 0xFBD59FB9,
+ 0xCE95DAD1, 0xBBCDE794, 0x9C0FA1C6, 0xCFD90F8B, 0x494C1770,
+ 0x21AD2AAE, 0x58EC00A6, 0xB0848A25, 0xEC4FEB5E, 0xFF1517EC,
+ 0x52871C07, 0x105E05B0, 0x178B1913, 0x18023805, 0xB16BBC6B,
+ 0xF8522A7F, 0xB17DEC22, 0x3808ACAC, 0xBC5B9043, 0xBEC01BA4,
+ 0xBC6CDA0B, 0x17906D50, 0x8422829F, 0x51C9AFB9, 0x54F78CEF,
+ 0x72CEEA16, 0x76A74B94, 0x7EC063E2, 0x51C65B1D, 0xD97ED9B8,
+ 0xDE89F034, 0xB5AEEFA0, 0xB88D3E9D, 0x9D4C57AE, 0xC8CEA9C1,
+ 0x941A74D3, 0x8E2FC33, 0xEDCEB551, 0xB91FA3E4, 0x8BA2261F,
+ 0xE558E0F2, 0xA4E81979, 0xAAE31455, 0x70B62249, 0xD48D1A67,
+ 0x11767EB6, 0x823DFECA, 0xC815C538, 0x2AB67EE6, 0x22FA86BA,
+ 0xD7A1F96C, 0xBA96E382, 0xB75B3FB7, 0xCB705FAF, 0xD1B9D3E2,
+ 0xD4C8DC2F, 0xF954B0A5, 0xDABE493B, 0xCA3FBB37, 0xBBDC387C,
+ 0xA30C87D6, 0xB5B493D5, 0x584F5615, 0x90FB6370, 0x5544A92D,
+ 0x980F7FA2, 0xF1459235, 0x130B11BD, 0xC7A44998, 0xFEBCA776,
+ 0x7943BE84, 0x72C99B04, 0x353F6042, 0x66F5C2F2, 0x9C5B2CC5,
+ 0x9FF06E41, 0xAC9E5492, 0xFF9A1CC8, 0x4429DE05, 0x97845307,
+ 0xDBA36668, 0x40BEBB2F, 0x606DBA6A, 0xDE7A4225, 0x9AF7FB71,
+ 0xE97A0E6C, 0x99C2AA59, 0xE00C525B, 0x5D4F9521, 0x89C5D7BB,
+ 0x18481C9F, 0xA27A1F59, 0x2A6267A3, 0xC467981A, 0xE04CE94D,
+ 0xAAB2AC1D, 0x5FD1AC86, 0x8F33E395, 0xE1FBE285, 0x636C2961,
+ 0xD838584E, 0x2F845D90, 0xAD52A8ED, 0x8F8C841B, 0x829A3861,
+ 0xAA0FF413, 0xA079F240, 0xB15D507B, 0x93722B10, 0x833AF929,
+ 0x4FB5B879, 0xEDD3031D, 0xE22CE740, 0x9ADF835A, 0x13A0C7A3,
+ 0xD5791B98, 0x99D9409F, 0x9F776A0E, 0x8665EC9F, 0x7301EF7C,
+ 0x9B341035, 0x59EADE7F, 0x242C1ECA, 0x20FD13FD, 0xE22DAF76,
+ 0x3859E84D, 0x6ED83DA, 0x54ABF391, 0xC43F4740, 0x4661F86,
+ 0xC6442213, 0x7FEAF294, 0xC0CAC024, 0x38B9FA9C, 0xFFF33259,
+ 0x1AD86335, 0xB365445F, 0x54B58378, 0xFD7AE96A, 0xE019B245,
+ 0xCF51C4EC, 0x604D7EE, 0x7B40C023, 0xA5E168B0, 0xD7B8C643,
+ 0x91C028D3, 0xCB939A6B, 0x169B0123, 0x96FF8CFA, 0xFCB3E126,
+ 0xB95C01B1, 0x1758BFB6, 0x50F50968, 0xF774D536, 0xC5A8BFE7,
+ 0xE2496BE, 0x6FB8D434, 0x3F7FEDB9, 0x9BDEE991, 0x1CBD2009,
+ 0x2CE74DB4, 0x1CB51025, 0xE965ECE6, 0x89100034, 0xA089E8C0,
+ 0x5860A65B, 0x9C4D349E, 0x54898852, 0xD07C9738, 0xBC677E89,
+ 0x75B5D0C1, 0xCFD435AF, 0xED550357, 0xAED9301, 0xDCD1734A,
+ 0xEDCD21D7, 0x69F6A592, 0xEF8009F7, 0x44374358, 0x9405770D,
+ 0x668AC4FA, 0x50507E61, 0x2DB19DDC, 0xA9BDD137, 0xFB722699,
+ 0xBC067E88, 0x88740174, 0x717CCEDC, 0x9F7F1E11, 0x389F4CC,
+ 0xCF4D0018, 0x24588FF1, 0x25C9F951, 0xDA660468, 0x6C09D91C,
+ 0xC9F788E, 0xDD4DF43F, 0x8B04484A, 0xC7F67DDB, 0xD2939F8B,
+ 0x96BCFDE5, 0xF6DD10D8, 0x1124A3BC, 0x7C281FBB, 0x5FAFA71B,
+ 0x58A9C493, 0x4747793C, 0xD3B79E72, 0x357AA675, 0x8E94A74B,
+ 0x1994025, 0x95D10FB8, 0x5C64AE63, 0x9E37973F, 0xFCE67009,
+ 0x8480F94E, 0x34DA26F7, 0x126CFB46, 0x206AAA6B, 0xBA0A6200,
+ 0x8DF3F67F, 0x4936802F, 0x950F62F8, 0x17E64C44, 0xC70E523E,
+ 0x2F910727, 0xAF7C5BC, 0x9EA24508, 0x1E945729, 0x55E48FBD,
+ 0x897CB57, 0x8C134FEB, 0x54E68223, 0x91912044, 0x7A461BDB,
+ 0xCE91309, 0x72135AF, 0xBF94D484, 0xDD752690, 0x32248D12,
+ 0xEA092355, 0xC24CA220, 0xE8A95D65, 0xE4E2EAE6, 0x664763E9,
+ 0x71F1AA47, 0x832550FF, 0xFFA73B6B, 0x96F5DFF6, 0x60CB9B66,
+ 0x75F29F5C, 0xF863AC8F, 0xF16993FC, 0x3503801C, 0x3D1E8B2,
+ 0x583CDFF6, 0x62AD49F2, 0x8261843F, 0x826EA9B6, 0x5E2EF3,
+ 0x8D3848EC, 0x7391A581, 0xDFC466FB, 0xB38DCBD1, 0x4145C3C0,
+ 0x73F322D7, 0x2B55F284, 0x6B19FBA6, 0xD9446AD1, 0x36C330C5,
+ 0xB71E4B29, 0xF29F504E, 0xB4FA4CFB, 0x290B6941, 0xA2197E21,
+ 0xF2AAE27F, 0x1A1728B5, 0xAFF5632, 0x6AEE763B, 0x2962A376,
+ 0x965D67E7, 0x231A8B76, 0xBD3596FC, 0xD4AE3E8D, 0x58D4D740,
+ 0x4EA3B6DC, 0x5479A7F5, 0x110A4791, 0x9A772A63, 0x728C4794,
+ 0x6D6A0801, 0x3F89D9E1, 0x326D1BC4, 0x49B3798, 0x5E2B3CA8,
+ 0x742C385A, 0x89450FE0, 0x24236A74, 0x81AC9891, 0x7BEF3C66,
+ 0xACECD674, 0x29009073, 0x94D6BDBF, 0xF2C6CDF4, 0xDBC21EE3,
+ 0xC65C89A4, 0x35DC5337, 0xBA281430, 0x787521B0, 0xADF8317E,
+ 0xD5739B77, 0x8567F3A2, 0x374E0CAC, 0x5AFFF50F, 0x9654D41,
+ 0x4A86EDEF, 0xE16C9A62, 0x59D15E49, 0xA69769C8, 0xA9197100,
+ 0x1E04CB9F, 0xA926CCB8, 0x5047C429, 0xB7E369C, 0x812F5F0A,
+ 0xA53EA5BA, 0x9AE5C105, 0xD4C7CC5D, 0xC99E02F9, 0x5BCDFE96,
+ 0xCDBAA854, 0xCF209B89, 0xBE08E9B, 0x5C73AED2, 0xBD959602,
+ 0x63C309AB, 0xEE289A4, 0xEDA954C9, 0x5C54F616, 0x3BC34487,
+ 0x47A3C772, 0xAB0084A4, 0x2CFB8D44, 0xF5F8411D, 0x43F6361D,
+ 0x12B8467F, 0xCDC437A5, 0xAC96A375, 0x7962CD18, 0x5D728EF4,
+ 0x66B11DEF, 0x73C87A6, 0xA35AEF9A, 0xC84F12F7, 0xB1EDE9B4,
+ 0x2F6A1752, 0xCF8DA321, 0x2E37F4E0, 0x4985F516, 0x684E49AF,
+ 0x56287772, 0xF74F95EF, 0xD994FF05, 0xC1D23E99, 0x81214F78,
+ 0xA5DF2934, 0xC2B686DB, 0xABC54017, 0x6918D067, 0x737A798C,
+ 0x3904B21C, 0xD4CB6EFF, 0xC256E4F8, 0x38B0CD4D, 0xE2D27089,
+ 0x75A00DC2, 0xDC1D5E7B, 0xE2295307, 0x2F0A683C, 0xD00AF450,
+ 0xE45C3252, 0xD86804C8, 0xF9628DB9, 0xEA011DB9, 0x6A67523A,
+ 0x488B54B3, 0xA292CDEA, 0xB1D1D89A, 0x17415325, 0x3EAD3D80,
+ 0x5D092525, 0xB5880E29, 0x1104A8AF, 0xBC177790, 0xEC730159,
+ 0x11B0A1AD, 0xB809FD7C, 0xB23FE31, 0xCCBED7C8, 0x45B7F7BF,
+ 0x9491B0EB, 0x1B1A90F9, 0xE34F4317, 0xF060A5B3, 0xF795EF1,
+ 0x8254A941, 0xC6CC30E4, 0x770FC40C, 0x17EC9C1F, 0x20DA83EF,
+ 0xF9CCBFC9, 0x9D0675AD, 0xACEA7EB3, 0x56326F5C, 0x74D4DF3A,
+ 0xA8FF9A9, 0x8F55E3E2, 0x5B0D12F1, 0x12DDB28C, 0x95FADBED,
+ 0x81F48694, 0xABEE8392, 0x90E96B15, 0x2C44972E, 0x4E2D3A4F,
+ 0xE8D34D14, 0x83C03E59, 0xDC295E2E, 0xDDEA452F, 0xC2A2A33F,
+ 0x617210DE, 0x69542DB0, 0x1DD96D24, 0x3E3871D0, 0x9DDDAF6C,
+ 0xBD326CD5, 0xD87CE143, 0xF3C79B3A, 0x7F811CCD, 0xDE1B1502,
+ 0x8075EA04, 0x9D09F1DC, 0x8CCBD152, 0x669F35C, 0xC9414276,
+ 0xA2BFFE0E, 0xF8AAE650, 0x190C1AE7, 0x2DBB4A7D, 0x575B247D,
+ 0x3A599D3E, 0xB09B4DFC, 0xCE4904A0, 0x63C72670, 0x15A3BD05,
+ 0x799B50CD, 0x19A2718C, 0x4142750D, 0x9013BE74, 0x21288938,
+ 0x590BD2BB, 0xE4303149, 0x46B308C0, 0xD2BB7D56, 0x1BFB248,
+ 0x943B2E72, 0xCAB18644, 0xFCC921C4, 0x5308C4D9, 0x9098CEE2,
+ 0x435B219F, 0x69F1BBE5, 0x155216D4, 0x83F2A4A5, 0xE177744D,
+ 0x37DF6FDE, 0x9D9EA50A, 0xDFA8D408, 0x6C72E71E, 0xEA617E3E,
+ 0xDAD6C13B, 0xB83A850D, 0x45F6BEB5, 0x6AFB346D, 0x400B29FB,
+ 0xBC8E57DE, 0xC6C1081A, 0x4F6A9545, 0xF878303F, 0xB9E519DC,
+ 0xCCF25FBA, 0xCAE069A5, 0xB79B082E, 0xF70BB7E7, 0xE6A5535C,
+ 0xB769EA37, 0xE07CCBCE, 0xA9F04406, 0xBB7E5A7A, 0x10C986,
+ 0x5EB448A0, 0x3B154163, 0xCB832FD3, 0x50100140, 0x6963216B,
+ 0xEF480040, 0x75B83F45, 0x4A07D8C5, 0xEFDF39B2, 0xDB139034,
+ 0x5BE9C8C9, 0x1915F818, 0x852ACD9, 0x58BFF825, 0x64AF5C20,
+ 0x1F13AFAA, 0x8A5A1E9D, 0x57870533, 0x98A418CB, 0xCEBDAD9D,
+ 0xFA54CB95, 0x707D0BBA, 0x26EE1F10, 0x428CAAC6, 0x33AC77D0,
+ 0x6879957E, 0x522DCDE5, 0xE29E9579, 0x4AB0C59C, 0xB5FA1395,
+ 0x4C0BA116, 0x297A0F00, 0x440CD4CD, 0x63BCFEC0, 0xAC14638B,
+ 0x3C7DF738, 0xC213D3AE, 0x5CA0779D, 0xB49A3458, 0x678D95A9,
+ 0x281735D2, 0x1911DA83, 0x3A5EA479, 0x2C1090F6, 0x40C0D5E7,
+ 0x33AD6433, 0x49B076BB, 0xA1C1D333, 0x80474C82, 0xC62FE221,
+ 0x87F4E57A, 0x4C5C1506, 0xAD5E1E10, 0xE435A8C6, 0x96D7E0E8,
+ 0x53E54D01, 0x7EECEA8B, 0x699C41E0, 0x181C6479, 0xAE6E687E,
+ 0x2FD27BB7, 0xDF60DD39, 0xC38A3AC, 0x5AC51EC3, 0x8F1205E1,
+ 0xBD71109C, 0xCB2CCA62, 0x236D9D16, 0x45ACA6BD, 0xB33BDCE1,
+ 0xE1D9134F, 0x410F24FB, 0x3BF34DF6, 0xB799F963, 0x1B2D4C07,
+ 0x8D92C15, 0x9CA0073, 0x76772A47, 0xFBB63B16, 0x78F3C3B7,
+ 0xF118B4A6, 0x8E86A34A, 0x56693D7E, 0x381EA186, 0xCB9B430D,
+ 0xAD11DC36, 0x599B3370, 0x7A6B80C0, 0xF2A282DC, 0xF58F96FF,
+ 0x97AADB3A, 0x5AA06FD, 0x44A43553, 0xBE8097C6, 0x4CF5002D,
+ 0xBADE20DD, 0xFEC25B7, 0xC8B50C4E, 0xF0C899D4, 0x815F9958,
+ 0x77772B46, 0x7413F82A, 0x7203A939, 0xF4623F73, 0x35EE625C,
+ 0x2723BC68, 0x33790B09, 0xA58391E4, 0xA27C7C25, 0xBC032556,
+ 0x1D812AD4, 0x301BB65D, 0x22FAF223, 0xDCBB79DE, 0x78CE1CBF,
+ 0x570C796B, 0x17EF8909, 0x8E2C32E5, 0xB54FF82F, 0x7702F70,
+ 0x1C0A78C2, 0xCB3078DF, 0x7155531A, 0xEAC77450, 0xB9DC2EDF,
+ 0xA8B6A1A6, 0x57FC52F0, 0x6B5543E4, 0x40679BEA, 0xE46813E7,
+ 0x65525695, 0x6C9CD43C, 0x5E5BD786, 0x44212626, 0x847A8357,
+ 0x7E39813D, 0x9FE22F0E, 0x29EC985A, 0xC91CF47C, 0xB31A26AC,
+ 0xA4C8B43C, 0x8EAB7865, 0xF6F2F67E, 0x3F73A8DC, 0x4FAF5455,
+ 0xE1253CAD, 0x3001A083, 0x532DEAE4, 0x6A110DF6, 0x585D0FDE,
+ 0x19071CC0, 0x1A351A69, 0x2FEAD890, 0x33902499, 0xA218C193,
+ 0x2294A970, 0xB0544EA1, 0xC54B25F0, 0x6C89048C, 0xC8203390,
+ 0x237F30DA, 0xE8F10E5F, 0x6B57E331, 0x43744B6E, 0x2EEF4BB4,
+ 0xEBD13AA, 0xA9024B04, 0x22895C31, 0x321C459A, 0xFCEFD3EE,
+ 0x94772392, 0xA094B3F3, 0xC070FBB2, 0xF30ADCDF, 0x8D294C6E,
+ 0x89E4C299, 0x47DE058E, 0x841A807E, 0xDEA7608F, 0x3A45D7AE,
+ 0xFE08A063, 0xF2C65E08, 0x4C653ADB, 0x8E4BED1C, 0xC85C1323,
+ 0x63DF1750, 0x4EF4B72F, 0x209903A9, 0x3ECCC1C6, 0x4283795A,
+ 0x205AC943, 0x38B1ABE3, 0x1241AC5D, 0x7C645871, 0x747695BB,
+ 0x29206570, 0x31BACE6E, 0xFDEEDAC9, 0x4DEFF536, 0xCD6CFDC0,
+ 0xEB0FAB42, 0x7DFA5EB6, 0x8363D9BA, 0xCFCD2514, 0x69FEB823,
+ 0x10BDBDCD, 0xE4C27020, 0x56DCF966, 0x9C97BD95, 0xCDAB9269,
+ 0x8316F55E, 0xC62F7354, 0x5415281A, 0x31EBDCED, 0xCDF7A05D,
+ 0x5F674F71, 0xF70EE58B, 0x26037964, 0x584174B4, 0xFEA5520C,
+ 0xD01A8007, 0x7F2772E8, 0xC2FF1456, 0x7B2CA1FB, 0xE938BBD0,
+ 0xD96CCCF2, 0x9AE8088B, 0xF3A25E6B, 0x3780417E, 0xB9E2917D,
+ 0x95872990, 0x12D99C68, 0x2FC5DDB0, 0x55437D2B, 0xDB9C14B7,
+ 0x6BBE6AF9, 0xFBDC9201, 0xDCB32A70, 0x1CABF45D, 0xD8BCBF4F,
+ 0x271AE6A5, 0xD34B8953, 0x58BBFB3A, 0x537F049A, 0x55B51226,
+ 0xCD809DC9, 0x846DB4EB, 0xED476D72, 0xEFC8F8AF, 0x6AA3228D,
+ 0xA363F656, 0x2207127, 0xA1BBE245, 0x2AB58A00, 0x637810C9,
+ 0x91F61AD, 0x347D333B, 0x1E9598E3, 0x2E7BD8C6, 0x8DCE469F,
+ 0x73B82620, 0x9257D4E0, 0xD9580F88, 0xE8EF6D53, 0x2D9FAC45,
+ 0xB56E2C6, 0x9B369045, 0xB50702C6, 0x955D3700, 0x577CC21E,
+ 0xED02FCBA, 0x73320B99, 0xB55DE16B, 0x7F578129, 0x3F6FD052,
+ 0xF211A764, 0x9B7F9204, 0xC61EDC01, 0x1363AA4F, 0xEFAF1CF2,
+ 0xE5AF97EC, 0xEEAD4FB7, 0xF41B649, 0x373087FB, 0xE81355EB,
+ 0xE04FF410, 0xFD04F4F7, 0xFA269CEE, 0xBE8D7535, 0x5FC007DE,
+ 0xCF085F76, 0x94D7201F, 0xAF49F41D, 0x8D6E7F, 0x9D63B6ED,
+ 0x9A2A0877, 0xF06123D9, 0x6624C891, 0x508266E4, 0x6921EAA4,
+ 0xD6E69A49, 0xCDA0F920, 0xA5870B5E, 0x1A93A2CF, 0xE3A030C6,
+ 0x6EC03FE5, 0x37FDBDF6, 0xBEFD0BFF, 0x3D3CBD0E, 0x2DDBFD7D,
+ 0x8B58AE2B, 0xCAD61AF3, 0x624F4677, 0xC402CF5E, 0x431D2CC1,
+ 0x5C205AE5, 0xFC3B8ED4, 0x501C36DA, 0xBC9217E5, 0x6752573D,
+ 0x3BE702E, 0x8E06CF12, 0x81494C86, 0xB2DC2F63, 0x792EC845,
+ 0xC6BDEDB5, 0xB255BA4B, 0x6C66C28D, 0xD1A16904, 0x93ABFF21,
+ 0x94827FC4, 0x87825689, 0x314D1F33, 0xC0D8B98A, 0xC84AC57D,
+ 0xEBDB0F92, 0xBA4F473B, 0x61130498, 0xA534064B, 0x3DC04FBD,
+ 0xD0A701F2, 0xA671765D, 0x17464B7E, 0x4CCCB84, 0xC297BAED,
+ 0xAAF8C84A, 0x631313F, 0x8E0FD926, 0x1699F616, 0xD9808C9D,
+ 0x55BF5BC2, 0x27FD10B0, 0xAE975927, 0x92B3F52F, 0x9025C6B3,
+ 0x95E5E313, 0x4CB83334, 0xE4A1E7B8, 0x74F7D3D5, 0xDDDC42B9,
+ 0x5A89BEF1, 0xF66A6AE5, 0x33730C23, 0xEB7F079E, 0x742FEF19,
+ 0x2C68CAC5, 0x2410679F, 0x9D1632DA, 0x458F4AAD, 0x8889E6AE,
+ 0xA3B48216, 0xC9AF4AEC, 0xA506C8F6, 0xB6AF9E59, 0xC6340436,
+ 0xA6B294E, 0xF35CF92B, 0xEB3A4113, 0x98070AD1, 0x9E61E01E,
+ 0x58C2893A, 0xCC1F8C34, 0xCAD665A0, 0xD0414D39, 0x643BDCD8,
+ 0x8AF801AD, 0x9ADBB106, 0x2BD02351, 0x8F890436, 0x546747D0,
+ 0x6DC33C48, 0x95FA7FD6, 0x5F12C5A5, 0x5DF2761D, 0x9A9B2F8A,
+ 0x8C61276B, 0xACCC7F4, 0x37A5829D, 0xF1A0F1, 0xAAED57E0,
+ 0x180CD2A3, 0xDC393CA7, 0x504E7405, 0x89DE2F7, 0xA4D8C4EA,
+ 0xD8BECE01, 0xD664017C, 0xF57FA30, 0x6049928D, 0x9832E166,
+ 0x176AAC31, 0xA793F88A, 0xCFFA8B54, 0xA30DF1EF, 0x3B6C7611,
+ 0xDEFC961, 0x9BFB79F1, 0x1483D430, 0xC3A77C0C, 0x42AC1FA0,
+ 0xFA3605B6, 0x9A2EBDF0, 0x684D414E, 0xD9308E10, 0x64D68C19,
+ 0xA8A9B67B, 0xF5E7B9D4, 0xC7B70ACE, 0xA6EB6DB8, 0x8A22FBE2,
+ 0x3AFFDDA1, 0xFB61F7D5, 0xE057717B, 0x846D96CB, 0x20A4B400,
+ 0x574089BB, 0x9F3D2DBD, 0xEEDDDB4B, 0x5E64EA6B, 0x6781DC90,
+ 0xCFD86A6, 0xA92441CD, 0xAC5DCCD6, 0xE6BB5582, 0x32FA6B3F,
+ 0x3ABB8A64, 0xA49D2003, 0xA965E430, 0xEC4053BB, 0x95859D40,
+ 0x2672832, 0xCAC3E608, 0xF8C13A53, 0xB04EC2A3, 0x87F54941,
+ 0x62A3A924, 0xE0B48702, 0xE8700446, 0x95BD4B11, 0xCFCFDF9A,
+ 0x19F67E7D, 0x60853AC6, 0x468F963, 0x298066B9, 0xEE53E89A,
+ 0xFC63E607, 0x6FA101E5, 0x8B2F1F84, 0x24AE7C1C, 0x385008FF,
+ 0x96E75EB6, 0xF1175277, 0xE5B4A577, 0xB0C97AC, 0xC21CC45A,
+ 0x5C680DF8, 0xDEB046DC, 0x1487FC03, 0x1D90CE3C, 0x712563BF,
+ 0x65A26CD9, 0x4D094F62, 0xB5DFE29C, 0xF58B2A62, 0x9420A9DC,
+ 0xCEC7537F, 0xC46D1FCA, 0xAD5D7B10, 0x68777A24, 0x6C096D2,
+ 0xD787D72, 0xC7743F50, 0xB3D05F4D, 0x53E0A7E3, 0x9E627C6D,
+ 0x1AA0959F, 0xD1E00E47, 0x8874BA26, 0xCEAC0958, 0x10F67BBD,
+ 0x712C6597, 0x3478BD73, 0x4D6F116, 0xD30BC24B, 0xB98C565A,
+ 0xD7C5B116, 0xA8CDAC4F, 0x4144673, 0x848F37E3, 0xADD946EE,
+ 0x6F17EAE3, 0xEA0FA265, 0x41DB99E0, 0x6BCFDA5A, 0xB46ECED5,
+ 0xAF67610E, 0xC7E9DF2C, 0x5CC6F0C6, 0xAB2C2BA, 0x6BCC3881,
+ 0xE482C243, 0xD8053417, 0xFFDB6E41, 0xF13EEB84, 0xE8292661,
+ 0xEB9940A6, 0xF0B45F98, 0x1CA82AF4, 0xCCA7771D, 0xDD5F3CFE,
+ 0x58BD8E91, 0xDF9E3342, 0xA1003957, 0x4621AF52, 0xF926F465,
+ 0x209925AD, 0xB1C72F09, 0x3FAB8ED, 0xA15C0A17, 0xDBE73D2C,
+ 0xF917CE51, 0xED047661, 0x7361B752, 0x1AAA57A8, 0x31445667,
+ 0xFEC0FD81, 0xE3073574, 0x7D36F720, 0xF418181A, 0x1CB8758E,
+ 0x8E85AFBA, 0x407E9AD9, 0xF724E308, 0xD030D3ED, 0x4610418E,
+ 0xE799EA4D, 0xF8B68F92, 0xB84B9ACD, 0x4B8168C0, 0x9888977,
+ 0x216F3B3E, 0x5C49C1DB, 0x759E718D, 0x7C4309FF, 0xBF6DEE2C,
+ 0xE566F231, 0x774B0A7A, 0xBE55CCFF, 0x3081B8CD, 0x2284369E,
+ 0x2FDF7473, 0x3AF68AC7, 0x6047E9B8, 0x3743BA0E, 0x691D261,
+ 0xADC440E1, 0x24150207, 0xFBFE466C, 0xF767E860, 0x8157332E,
+ 0xFB54D774, 0x1AF34C22, 0x74E05695, 0x2101FD57, 0x2904274C,
+ 0xA1294E9A, 0xF43CA18F, 0x4FA79EB5, 0xAFD1C9EE, 0x6EB3953F,
+ 0xDDFCB3AA, 0xDB48F7BA, 0xE1742183, 0x8A78CEBD, 0x225CD669,
+ 0xD76B771A, 0x3520113, 0x428B2892, 0x3A5CE8DD, 0xAB4AC42C,
+ 0x2928BE8D, 0xC34E3031, 0x93F0CB9B, 0xB7A6FDB4, 0xEEB2B85E,
+ 0xC393597B, 0x9D8457EF, 0x91F0F0FA, 0xC54AEA3C, 0xC639521,
+ 0xB668AFE4, 0xE4CCE3CD, 0x86223A5D, 0x6A51A2EB, 0x4333C505,
+ 0x3233B8B7, 0x1D01F51E, 0xF0C691A6, 0x699EBC2C, 0x7FEE8DBC,
+ 0xCC50E42A, 0x7951DB68, 0x8CF01752, 0x33D33841, 0xB46E353A,
+ 0x700B65B, 0x59ACA844, 0x38631893, 0xC32D0F92, 0x6897EFDD,
+ 0x3F93BCDD, 0xD50E33C3, 0xD0075F1D, 0xB3CB6096, 0x875896CB,
+ 0x5DF6651, 0x8E2D197F, 0xCDF68F10, 0xC74018CE, 0x83E6C42A,
+ 0x994DEA76, 0xF932D8AF, 0x98775C2D, 0xF79CAAE5, 0xF2BEB839,
+ 0x7318C6DB, 0x3AFD6D85, 0x37F18BDF, 0x10194867, 0xA73B5205,
+ 0x3F06A1BD, 0xBC8026DF, 0x531CF753, 0xCAFAED74, 0x817C9E70,
+ 0x32338A3F, 0xA5177C74, 0x9A3C131F, 0x90F9AF0, 0xE9281B62,
+ 0xEDD87C1E, 0x16577CB0, 0x5E3F7AC3, 0x4E49E1EA, 0x495C1B67,
+ 0xC282F5FE, 0xF8993B1, 0x47563C68, 0x49FA0716, 0x26A55B80,
+ 0xDF870F8D, 0xFBB8DDA5, 0x130EA4E3, 0xB0B66F1A, 0xD7B92F0F,
+ 0x55FD4759, 0x6D11AC86, 0x8AB0B6F8, 0xD8C8C8B0, 0x758DA8A,
+ 0x9CD589F, 0xB808C0A0, 0xB2C7A3F3, 0xBA40DA44, 0x937532CF,
+ 0x279CFDB2, 0x545896EA, 0x387A8F38, 0xB2E5F9D0, 0x7566CA0D,
+ 0x51B45DC4, 0xA93B6EAE, 0x1C22D8D5, 0xEB96BD1D, 0xB8F40750,
+ 0xCB7DCF85, 0x188F6018, 0x95BA817E, 0xF7C19E4E, 0xAAF97DDA,
+ 0xE5BD967B, 0x1604352F, 0x3758C3BB, 0xE2FA13D1, 0xE3666F4E,
+ 0x218059EA, 0x2F4750EA, 0x2F065B46, 0x8FC4F43F, 0x2F45422F,
+ 0x45928A5E, 0x77055776, 0xBB8103E1, 0x160EFF29, 0xA704F79B,
+ 0x6655E735, 0x2C19DC79, 0xE407A7CD, 0x9F4AE1F0, 0xBED7DCE5,
+ 0xA870A304, 0xDC413709, 0x903181E, 0x7C1F6803, 0x44971A01,
+ 0xF7A81ED1, 0x5DDFB023, 0x2D90CFBB, 0x7F7A432A, 0x35F3F5B0,
+ 0x7D935FC5, 0x1D99E7BB, 0x8EFC82B0, 0xAB0DEF56, 0x70702FA1,
+ 0xCF0064DF, 0xDD9DEAA9, 0xF05F927B, 0xB483A6DD, 0x9B7388B8,
+ 0x2FD82389, 0xAC982F20, 0xC86AD76F, 0x15C6977C, 0xAB10A137,
+ 0x1433E4A0, 0x2762D44, 0x1CB5399B, 0x310A54D8, 0xD4B8623A,
+ 0x40FAB5F3, 0xC2D51618, 0xC1F4AF55, 0x17C18E1C, 0x4F37D33F,
+ 0x2DC9F168, 0xF5BB9754, 0x716FB1F4, 0x7CFB1CE8, 0x1333224D,
+ 0x344C13B3, 0x7798CB50, 0xB4278C76, 0xD7CC1B03, 0x168B21E5,
+ 0xF7D77AAB, 0x3B651846, 0x639EB0CD, 0x68EB3E8B, 0xEC82FE45,
+ 0x622A71DE, 0xAA05B6CB, 0x878B59B1, 0x3E7FB616, 0x1D650408,
+ 0xF21F8C64, 0x9BF7BF7A, 0xA0874898, 0xFE4E3C6E, 0xFA36122E,
+ 0x1BCDF4FB, 0xC371B365, 0x8F791BB3, 0x9833AD98, 0xE84887FC,
+ 0xF8988AB6, 0x180916E2, 0xB587E39C, 0xD5C884C6, 0x27B6BFEB,
+ 0xD8868D1E, 0x689DA503, 0x936B4EFC, 0xDE0DB3C, 0x7950FDCB,
+ 0xA61C81C5, 0x9F1C93B2, 0xC983179A, 0x6F847EB0, 0x6F7F899D,
+ 0xD270412, 0xCC255717, 0x763112A0, 0x8725C96D, 0x48BC2863,
+ 0x85F13BF0, 0x6D8E0251, 0xB7E66CC3, 0xA4F5829F, 0x8779F381,
+ 0x16A5E04F, 0x3DF42C14, 0x367F06A3, 0x3BF8666C, 0xC6649CFB,
+ 0x4DD9808F, 0xB4F9AFD, 0xC2642410, 0x9740E4F6, 0x8FB667BE,
+ 0x4D4B0D3E, 0xE9B236F7, 0x6E30550C, 0x79DA7B48, 0xE721889D,
+ 0x79D9B21A, 0xA06B8C2E, 0x997B1696, 0x4383FC27, 0x8B77D293,
+ 0x6FAE2A9F, 0xB45ED194, 0xF38E2C59, 0xEAA0D05C, 0xA3BC449A,
+ 0x6EB0BB4B, 0x6B242CFF, 0x7FCA0B8A, 0x47221D33, 0x4E18FE39,
+ 0xF4691580, 0x6D03D791, 0x3B937AC5, 0x9CB761C3, 0x42812232,
+ 0xFB987D6C, 0x86AD164E, 0x5D8CED49, 0x22D6D058, 0x42FADF98,
+ 0x9363A1B3, 0x83C6DB74, 0x7AF44F4E, 0x20086D60, 0x7A37665E,
+ 0xC4A29C82, 0x330F278B, 0x8750B539, 0xDD2E83D0, 0xB8E002B1,
+ 0xF2A9323F, 0x91B60885, 0xDE83F01D, 0xACA126, 0x2F0FADA2,
+ 0xC0E879A6, 0x7C715655, 0x16642BA2, 0x43B9C083, 0x95F6789D,
+ 0xE6576886, 0x46BEF133, 0x84199FC3, 0xC45BA082, 0x26489AC1,
+ 0xA4FE268A, 0x633A25B0, 0x4FCD341D, 0x8E7374B3, 0x7F8A3466,
+ 0xC82B53F7, 0x2E2114DC, 0x59213BE7, 0xE72A2395, 0xAC5F982B,
+ 0x8F63E9D8, 0xA68BA42E, 0xF0E30E92, 0x580FD13A, 0xB2FCB7EA,
+ 0xF3E4C077, 0x2C8588B, 0xC31F5E5, 0x104982D9, 0x2C2F03E3,
+ 0x8F1791C, 0xCE14310F, 0x1696133B, 0x1BC68D6D, 0xFC488B95,
+ 0xE0E7FC31, 0xBDF0152B, 0x24F78B82, 0x45BD4367, 0xC89AF4B9,
+ 0x9698650F, 0xFB2E131A, 0x82B7A451, 0x9F6990FE, 0xB6EDE6BB,
+ 0x68D5D90, 0x51FE559E, 0x9B54ECE, 0xC09D3AB2, 0xD9BA990B,
+ 0x4CF02BC, 0x70067D7, 0x3568DF20, 0xFF1D7AE4, 0xF1C67DE3,
+ 0x5ACC7F95, 0x89ED16EB, 0x6EDCDC94, 0xDF367991, 0xF1D48A79,
+ 0x21AA30FB, 0xADA2B5B3, 0xC40A5761, 0x5769556B, 0x5E1510A2,
+ 0x5741566A, 0x25B88D83, 0xFD22574E, 0x6E9B2CD2, 0xF5CE960B,
+ 0x67F938EF, 0x1A1E3672, 0xFBCE5BDB, 0x756BACAB, 0x2F177A71,
+ 0x31F3EFC6, 0xB8263FBA, 0x9A1F772A, 0x84DC1FB0, 0xC907ED89,
+ 0xAD3C6092, 0xC225B6C8, 0x37EE4F54, 0x4BDDACF2, 0xB5E944CB,
+ 0xDC26F39E, 0x3BCE02DC, 0xC01F2632, 0x89AFE3ED, 0x600757F7,
+ 0x4804A684, 0xC4F3FCB8, 0xEBCAA904, 0xE0069A2E, 0xA2FBD213,
+ 0xDB736C4, 0xA6930699, 0x71FB43C0, 0xF66C955C, 0xFBD39B5,
+ 0xC87D1801, 0xE9D2DD1A, 0x78DA23CE, 0xCADBA5C9, 0x77015761,
+ 0xF5581BDF, 0xDEB4DAA0, 0xAF7E41B0, 0x71347196, 0xF8A29A93,
+ 0x8DA3BAE6, 0x73396AAD, 0xD4DF7765, 0x326AFF23, 0x27888A0C,
+ 0xE48AC062, 0xB9F18047, 0xDE9830DA, 0x8EF78C4D, 0xFBC1896E,
+ 0x9BB566A6, 0xB640ED13, 0x8B0D9D1E, 0xD84B471D, 0x4040EFB4,
+ 0xF6DF7908, 0xCB8ACF04, 0x253494DD, 0xA85F6D88, 0x1326822,
+ 0x61EFDFB8, 0x1C78154F, 0xB13866B1, 0x3ABE5DBB, 0xBB5907BF,
+ 0xA1A57FDF, 0x410549C8, 0xA9A364F4, 0x2A371B73, 0x24AC7296,
+ 0xA01C035C, 0xE839029C, 0x6E12051E, 0xE6A549FD, 0x345F10FF,
+ 0x3BB57347, 0xBDBF3A6A, 0x2A41C3C8, 0x6E0232B0, 0xAE66D42E,
+ 0x3BE90433, 0xE185FBF2, 0x9BCA91FE, 0xF4FFB74E, 0x142B6971,
+ 0xA75CD7B, 0x9B900DDD, 0xEC56B79, 0x2FE0CD8D, 0x87BE8237,
+ 0xB38A7226, 0xB5D8B437, 0xAAADC41D, 0x8014E227, 0x38D84DD1,
+ 0xEDF5294F, 0x862F0F, 0xD69F77F6, 0x409C3B68, 0x2F12B0FC,
+ 0x32A670B9, 0x5746EE2, 0x96B4901A, 0x57208639, 0xA282A77D,
+ 0xE9D9F48E, 0x651ADDA6, 0xFF5E974C, 0x37C833C, 0x41F2BD58,
+ 0xDFE1D009, 0x32222DA6, 0x22201781, 0x64A06BAF, 0x8F188902,
+ 0xA9C2A07B, 0x617C7DF7, 0x842DA704, 0x40AFDB72, 0x49625110,
+ 0x72484F13, 0x7340AC89, 0x6C6A2F36, 0x828EF5F9, 0x20344923,
+ 0x21D3304F, 0xD6EEB7C3, 0x8F99732F, 0xEBA045D5, 0x5C0065D4,
+ 0xEEB5E899, 0x1B079C47, 0x6198EE3B, 0x946A805F, 0x7C19F966,
+ 0x75E8F043, 0xFD9880BE, 0x47BF619, 0x9C001ADB, 0x7438184B,
+ 0xA3787EF2, 0xA461EF4E, 0xEB515D0E, 0x64EFA69D, 0xD41F3145,
+ 0xD08A900B, 0x495968AC, 0x746639C9, 0x43E85DCB, 0x62E55B3,
+ 0x6B913D8E, 0x2685D73B, 0xE4F98C19, 0xB404BD4B, 0xFEA327C5,
+ 0x1E0CC908, 0x71BC53EA, 0x530AAECB, 0xBD2977B, 0xB661A52,
+ 0x86560EE2, 0x250E2591, 0xDA57D5B3, 0x347D3C22, 0x6CE15221,
+ 0x6E5288EB, 0xA79875F3, 0xCA89972F, 0x36E93777, 0x257262E1,
+ 0xD1D4E5A4, 0xF7ED5D52, 0xECE58036, 0x644ACA69, 0xCA36DFB8,
+ 0x60EAB44D, 0x46FB8AB3, 0x81E6C199, 0xD5AA5C63, 0x4A7CB01D,
+ 0xFCC109CD, 0xD999C46B, 0x3FA4C688, 0xC95C0FBE, 0xA1E9DD3,
+ 0xBE9EAEF6, 0x1A3014D7, 0x729A662, 0xDC8178FD, 0x7FCAA1EF,
+ 0xD4005420, 0x2A904DAD, 0xEE7E52DB, 0x886C0F23, 0x12D49E10,
+ 0x2B3F3B39, 0x3373A6C6, 0x5D0759F5, 0x8CF5EF25, 0xCE02371C,
+ 0x2FFEEFDE, 0x5D9CFD69, 0x2B5BB7D0, 0x5A378EA9, 0x5BED8331,
+ 0x9C1A37CA, 0x702799F, 0x4D37A8EB, 0x370CEDF8, 0x43B95BE0,
+ 0xA0C1E534, 0x204130B2, 0x8E4995AC, 0xCF1C3C28, 0x3E901F78,
+ 0xB0F43C57, 0xED4B7492, 0xABD3C5CD, 0xEA95ABC4, 0xE03B739A,
+ 0x58388E80, 0xFDF22044, 0xF4379C7E, 0x87CFA0C, 0xAE9CA79E,
+ 0x41DCB004, 0x8F69512D, 0x73ED4756, 0xE215297A, 0xD931A6AD,
+ 0x59866B3D, 0x61825B1D, 0x4F5099E1, 0x25AE168B, 0x1272D5C6,
+ 0xBE071035, 0x24314F71, 0x82F4B23F, 0x6C7F3385, 0x36CF0505,
+ 0xB71C0E3D, 0xE9F881D0, 0x27F0C290, 0xF4BE30D7, 0x88315CE8,
+ 0x9E04FD20, 0xDE197591, 0xCF0D2FF4, 0x67A4C473, 0x158447BF,
+ 0xA4B37C88, 0x27918292, 0x5FDE3DF0, 0xE8A93C3D, 0x886287E8,
+ 0x746E199B, 0x9A894103, 0x7A529374, 0xA195E2AF, 0xAA3EB0C6,
+ 0xF70788A9, 0xCE2B7F30, 0x9C4724AA, 0x902EB7A8, 0x2CBBB407,
+ 0x3799651F, 0x9016E9D0, 0xD1C0ABC8, 0xC7684FDD, 0xE4670051,
+ 0x25B69E83, 0x1CEC9BBF, 0xD066D2B4, 0x2AD4BF14, 0x7AFBD3CF,
+ 0xCB8E5EFA, 0x63B67572, 0x89F7E3F3, 0x8E8D39E6, 0x60617ECD,
+ 0x9EECEA31, 0x59E57FAB, 0x807AFCD6, 0xFD0397B8, 0x3C57D963,
+ 0x9A972CF5, 0xFC47B628, 0x9CCFAA8B, 0x405869C3, 0x3CC128C1,
+ 0xE154C33E, 0xBE53F87D, 0xD23C7947, 0x4CBEB3BB, 0x1F068FFA,
+ 0x8A7D350A, 0xB822F33E, 0xFB3BB431, 0x741D2D0F, 0x81FAFE09,
+ 0x80B8BA3C, 0x30B4BE94, 0x4B2A2909, 0x31740925, 0xE68C0BC9,
+ 0x8E7F31D4, 0x29DA2599, 0xB9D267C9, 0xEDE811D2, 0x8BC7CBC3,
+ 0x69DDA8B6, 0x879E1212, 0xF915F0F1, 0xBBCDB1AD, 0x3A01011A,
+ 0x7CD005C4, 0x475FC718, 0xF03F454B, 0x7457F264, 0xB22D9DFD,
+ 0x569DE931, 0xB585EFEB, 0x9A183445, 0x9CB353AC, 0xE3AA9817,
+ 0x32E0722, 0xF0C7595E, 0x316DBD6A, 0x96D0F65C, 0xA6F0ECCE,
+ 0xCB8A9494, 0x5B077241, 0xD36BBC7, 0x9C4CD0F9, 0x108F5B32,
+ 0xC43C599A, 0x7B10108A, 0xA4106EE9, 0x3860CF99, 0x87B782C,
+ 0xF667524C, 0x129929C, 0xEA85C1D5, 0x1A07973E, 0xB9524891,
+ 0xBC02BD1F, 0xF378D7F, 0xD0BED4D7, 0x5B782DE2, 0x738681A,
+ 0x4BA1192C, 0x46DF1224, 0x4529AED7, 0x9B1DB01D, 0x810AA334,
+ 0x661982C8, 0xD3B32F94, 0xF50AC9D6, 0xCE9107C4, 0x203078BF,
+ 0x6B0F3B2B, 0xCF63520C, 0xACA9E5BF, 0x7FBE448E, 0x51BD1E2F,
+ 0xDF958295, 0x114A9693, 0x60FCBB39, 0x6669B642, 0xC490D54,
+ 0xD19C8DBC, 0x14CC7B2A, 0x7106D506, 0xAFDADD98, 0xAF398DF4,
+ 0x88AC5400, 0x1912BF0A, 0x5389D050, 0x5AF6233, 0xF10842A3,
+ 0x94DD7008, 0x93812804, 0xD8111DFD, 0xB7C97490, 0x7748A45E,
+ 0xE70A47A0, 0xC29B718E, 0x55783AEC, 0xA2789E21, 0x97488EBC,
+ 0xD9222F6A, 0xBF74BDD2, 0x9A983E5C, 0x6CC067D5, 0xBCFDD3B2,
+ 0xD7A2A5FE, 0x4733F2F5, 0xC7AA3556, 0x1CDB485D, 0x31755CA0,
+ 0xB9F8E9A7, 0x1346410D, 0x7D885AD7, 0xA30030D8, 0x9813B41C,
+ 0x8A64EFD4, 0x273F4CED, 0xFEDDC3FD, 0xF34D9687, 0x6B67F2DC,
+ 0x13F72B5A, 0x96445DDB, 0xAC94658B, 0x8FBF54BC, 0xA7C13389,
+ 0x95814EA3, 0x7823E5BC, 0x544C27DB, 0xECE6439B, 0xD1141B27,
+ 0x7A95ACF4, 0x806E58E7, 0xD07B5422, 0xFD0353AE, 0xC1840431,
+ 0x1DD89E9, 0xA102016D, 0x3730505, 0x1F91E46A, 0x3279C793,
+ 0xA060010D, 0x9BF86C80, 0xD0C35484, 0x33E81EF7, 0x1C4D3EA7,
+ 0x6C2A9935, 0xD65E2FB1, 0xBB1CA42E, 0xEA3E3609, 0x7B478C84,
+ 0x70C1DF93, 0xA872CA92, 0x7C025178, 0xF3B19C7D, 0x6F2BD89B,
+ 0x1AD7BBDC, 0x39A48FCC, 0xAB5B72E1, 0x821761B9, 0xD2368C1,
+ 0x20ABB349, 0x29A3F960, 0xFDB18DF1, 0xC4118A52, 0x5E28E88A,
+ 0x549A3386, 0xD81024CE, 0x82DAD5E0, 0xB20BCD42, 0x9DEA0D36,
+ 0x49A4992D, 0xAFCB2026, 0xCE7536E8, 0x2C191A65, 0x24FEE0D6,
+ 0xA769AB6D, 0xF47E292E, 0xCB501191, 0x6DE13907, 0xF1343277,
+ 0xB32AA746, 0xB055DB9E, 0x87CB8583, 0xA546A4C3, 0xF06F809C,
+ 0x8FE7A8AA, 0xD0E4037F, 0xD81FCF88, 0xF85830C2, 0x3D6F4840,
+ 0x5A43700E, 0xCD300C58, 0x3B81C27C, 0x8AF86EA8, 0xF65935FC,
+ 0x46367D7, 0x7FB75E63, 0xBB28A406, 0x173F982, 0xCB92DD14,
+ 0xAAA0B1D1, 0x1BCA8892, 0x64D21, 0xFF081A44, 0x8706E93B,
+ 0xB7DEFAD9, 0x4A6DEF76, 0xDA1670DF, 0x94ABCEBA, 0x465DA4C6,
+ 0x2484496C, 0x97BB3321, 0xEFB09CB, 0x2988AA2E, 0x2722344E,
+ 0x5301B744, 0xC5E16C47, 0xF7E05D01, 0xCBE7C20F, 0x4882A6EA,
+ 0x7168CF40, 0xA98A2747, 0x35F8E15A, 0x5FAF49F9, 0xD2008D24,
+ 0xCC45A63, 0x858A3255, 0xE4C095B6, 0x7074F7A5, 0x699C98FD,
+ 0xF0BFE2EA, 0xBDA35C64, 0xE83B891D, 0x7CD09FEA, 0xE8735FDD,
+ 0xFEA27F06, 0x631D71D3, 0xA08136CD, 0x42395363, 0xDCBA6E41,
+ 0x1562897, 0x4B1061A9, 0xB4F9640B, 0x38D24E3E, 0x76DF4423,
+ 0x94B5ED97, 0xFE6AB3B6, 0x6B329B8B, 0x37AFD275, 0xC9ABA12A,
+ 0xEC9693B, 0xD49B5585, 0xE0C2BEF7, 0x315D40A8, 0x34FBE3A,
+ 0xEBE81550, 0x569F6FC8, 0x5A9C8404, 0x9DBA0090, 0xFE985DE8,
+ 0xFF4209AE, 0x89F9E7AF, 0xF841164C, 0x6B4B8F5D, 0x95CB1085,
+ 0x1990660C, 0x31263B36, 0xCF8F435C, 0xDEBCF88A, 0xD1EE25C2,
+ 0x53D80B69, 0x9EB8F01C, 0xD682EA3C, 0xEEE79205, 0xA7EFAC65,
+ 0xE9AA6899, 0x3C1E197E, 0xC8ABE1E9, 0x7BEFE9CA, 0xE792E7D4,
+ 0xA955D60F, 0x3FE8A02F, 0xC963FDC1, 0xB3D53E43, 0xE28FFC12,
+ 0x7D5BECCC, 0x18E9F223, 0xBC8B0465, 0x7ED8EEFE, 0xBB90FFEE,
+ 0x904A9F3A, 0xBC467FF, 0x8AD43A15, 0xF3FC404A, 0x2492D5F4,
+ 0xBB3F5025, 0xBED0B8BF, 0x467FE6C2, 0x36E55C77, 0x8E2CAC4F,
+ 0xD12D325F, 0x68A4D268, 0xB1AA0895, 0x755B98FC, 0x2314C4FF,
+ 0xC3667346, 0x8003B9E8, 0x1185476D, 0x227B69D8, 0x5BADD019,
+ 0xB06567BF, 0x2B837581, 0x9E11F7, 0x158E67AE, 0x339AA6FC,
+ 0x8FE50AD9, 0x65902A97, 0x42917220, 0xF9AD39C, 0x2DAAD225,
+ 0x9673B896, 0xFAE150D6, 0xBEDE3417, 0xD233D722, 0x7E67F33C,
+ 0x6E150E30, 0xC856792A, 0x28EF69BA, 0xE2AC7866, 0x928D0A4A,
+ 0x8032C4A9, 0x3D413533, 0xC1BA5CCA, 0xD2BDAC83, 0x94198A14,
+ 0x3A25972F, 0x253EC030, 0x42D7A1F5, 0x97C28C1C, 0xBE4D0710,
+ 0x92F31B62, 0x73CA2F55, 0x15FC5417, 0xEF76B1C6, 0x655A963D,
+ 0xBC17C3FD, 0xD5BED3BC, 0xAB0E4857, 0x38BAD61A, 0x8C17E47F,
+ 0xE3C27887, 0x45D2A34, 0x6D48333A, 0xF400B767, 0x6ACF41B0,
+ 0x88DA15A9, 0x3FA0EAB1, 0xAF7B3786, 0x87F182FF, 0x4112A079,
+ 0x53360864, 0xDB5CE625, 0x630678D7, 0x63E01F17, 0x7BF658F1,
+ 0xB5E4F1A3, 0xB30E4393, 0x27454C31, 0x8E7E0E2, 0x2151A5F,
+ 0x2892E2B2, 0x92B53840, 0x1EB3D483, 0xA4273A65, 0xF0CC632,
+ 0x99AC2694, 0xE0A19111, 0xC7FBA613, 0x46C8F873, 0x88A27741,
+ 0x7E9A5972, 0xC2E76F79, 0xA5CA8180, 0xA28FF0EE, 0x2A1F7DE1,
+ 0xCC130B22, 0x50ECFD8A, 0xF5BAA999, 0x5FA2EC9C, 0xC1B5C5C4,
+ 0x90EC0E5D, 0x9C26620A, 0xA97D2935, 0xE1C08B89, 0xCB574B80,
+ 0xB3DE8B61, 0x1AF89CA0, 0xFD4A77DC, 0xED9485E1, 0xAF804C92,
+ 0x6B8EB167, 0xDCC836B6, 0x85A7FFFD, 0xD4E9A94A, 0x77DDCC31,
+ 0x8897B5F9, 0xA4FA88D3, 0x8ECB3E82, 0xBC175E89, 0x963A073E,
+ 0x547520C7, 0xEEB81BFB, 0x1D8B1867, 0x78833A4, 0xE40A0CCB,
+ 0xF8D5452F, 0x954BDCF6, 0xAC228FFA, 0xE6B32DF3, 0x181ED541,
+ 0xACE26A73, 0xF1C1440D, 0xA1B93EDD, 0xE90FF70A, 0xF6741843,
+ 0x4DF581AC, 0xBE785B32, 0x751509B5, 0xC30AD864, 0xC18D8A72,
+ 0x3BF07FD4, 0x827B4CBA, 0x7DD39A4F, 0x2CFEFE25, 0xE071F371,
+ 0xC0C3F6CB, 0x1FD70F85, 0xFDABDA88, 0x8F308991, 0x4CD794F9,
+ 0x5D18B022, 0xC13D5FC2, 0xD84337F, 0xED868BB8, 0x9904CD2,
+ 0x7551499C, 0x124B262, 0x5139C2A5, 0xEF56F59B, 0xE8B87B40,
+ 0x2F030010, 0x42D2E271, 0x4E344F3F, 0xC87CDFE1, 0x44A615C7,
+ 0xC32DB543, 0xCFC889E4, 0x60078825, 0x786F5917, 0x2DF9E82,
+ 0xEE26DA93, 0x48D0C94, 0xE97D5456, 0xF487F2EB, 0x35A47D65,
+ 0x183DA0CA, 0x1A7E1218, 0x8D2674C5, 0xB38D0910, 0x5D9C871C,
+ 0x7B463ED1, 0xBBC90FFD, 0x31DED99F, 0x5171DCFA, 0xF9413D0B,
+ 0x632A00FD, 0x7B6DA34C, 0xA475C597, 0x8E157360, 0x5911736B,
+ 0xCA19D544, 0xF487D465, 0x6E749BB9, 0x888BFB52, 0x3FDAD497,
+ 0xDB5D401A, 0x7015A4EC, 0xC1F571, 0xB2D7671A, 0x8203032F,
+ 0x5A755E9, 0x24F25BF5, 0x4D2AC51B, 0xE5950FA7, 0x20196F5B,
+ 0x68E90D90, 0x5D24196C, 0x9CFCD1C0, 0x745C0318, 0xEEB977E8,
+ 0x14AA16D, 0x80662EE1, 0x7BD55DE3, 0x35EE2B08, 0xD3E8051F,
+ 0x3D0EA4B5, 0xD551399E, 0x8FF94435, 0xDD4E34ED, 0x9139E4A3,
+ 0xE6AF7E5E, 0xE1ED4EAF, 0x638D2846, 0x7084F7EB, 0xF9705E17,
+ 0x2E7A89DC, 0x45855252, 0xBA8E51C7, 0x8510425C, 0xA97AF6D,
+ 0xF0C27DA, 0x9E00CA15, 0x3BCC0651, 0xEEC38CA9, 0x19597B08,
+ 0x4C68AB5D, 0x16CA41DB, 0x35EFBEF9, 0x1E441529, 0x25131FA1,
+ 0xC3D8483C, 0xD8650832, 0x60D271E3, 0x47C92A47, 0x9EFBB554,
+ 0xBF5DBFBF, 0xFF421FA2, 0x3A38F28, 0xAE4EE06B, 0x819945D1,
+ 0xC43101, 0xA3EE9278, 0x5BAE3EE4, 0x57ACE55E, 0xC3D95551,
+ 0xC00717B0, 0x38EC1B28, 0x123597, 0x6314F3F7, 0xB3F99DAB,
+ 0x7226CE1E, 0xE8350DE6, 0xD7C582CA, 0xBB1D38D, 0x54E656FE,
+ 0x400B60BD, 0x48291A06, 0x97819179, 0x850BF937, 0x93888A87,
+ 0xF51E684F, 0x4B111E, 0xC6B37E02, 0x6C923547, 0xEF25AF3B,
+ 0x8C12CE8E, 0x89296F4F, 0x3BE2C3DA, 0x8A29A35B, 0xBBE2E80C,
+ 0x79D0188D, 0xBD4320BC, 0xAFF4F0A9, 0x7FAE6C37, 0xCCA1777E,
+ 0xB06D2AE1, 0x26B6398C, 0x5A3E5876, 0xE814DF4E, 0xC43E9677,
+ 0x4C962CE8, 0x6C274FF8, 0x8B5A1A03, 0x963E1401, 0xD8CE0DF7,
+ 0x659190E7, 0x3AD63330, 0x894BFEDB, 0xEB4CF73A, 0x3731BC86,
+ 0x30FE0433, 0x94F5FD2, 0x8417999C, 0x337E86B8, 0xAFE08EF6,
+ 0x5B5F05DC, 0x8001C95F, 0x8C8092DC, 0x5EBC7995, 0xDCBE88EE,
+ 0x9C602950, 0xE3376596, 0x5D80E318, 0xAF3AC8C3, 0x8C7EDCC6,
+ 0x3E795E7, 0xDA8987AB, 0x7B7B4E3C, 0x3239CD40, 0x1B527DED,
+ 0xC95DEF29, 0xE40D047D, 0xE53C10C5, 0x5BAF528B, 0xA47921F9,
+ 0x6DCB9B0A, 0x7EA11040, 0xBBEFCCD5, 0x502F33FA, 0xAB5EBE8F,
+ 0xD59C448, 0x8C34FF3D, 0x4A3255A2, 0x4CFFDCB1, 0x3880A182,
+ 0x3499DAAF, 0xA1319450, 0xC550CCE5, 0x51026E2C, 0x73C4F05D,
+ 0x21F5FAAC, 0xE1C31B7D, 0xA390E6E6, 0x7B1582ED, 0xB92B4C3B,
+ 0x41C1128E, 0xF728F655, 0x3BC8AE16, 0x8A2A4E57, 0x9A8A7DE,
+ 0x86065598, 0x4328A574, 0xDBDAFC7D, 0x2C5EE98, 0xEAB5CE80,
+ 0xF7E8F60C, 0x7B4C3C0E, 0xE4A2F720, 0x90330B1D, 0xB6783BF2,
+ 0x48A8C26B, 0x847F1AAC, 0x351DB247, 0x43E84AC5, 0xAF726AA3,
+ 0x5CB4C059, 0x2C5784DE, 0xBA1111FB, 0x9F427968, 0xE41D29D1,
+ 0x2CAA8CA7, 0x764C8B63, 0xBDAA6F10, 0x280277B6, 0xE4A908B6,
+ 0xA6A9783, 0xD0643B01, 0x44FE52AD, 0x60B04A5, 0x194C190E,
+ 0xF73DA669, 0x12EE11C8, 0x2C769D96, 0x694787A4, 0x9FB03623,
+ 0xAC6F837C, 0xFC1E5935, 0x16246787, 0x4F94B817, 0xA3A4281F,
+ 0x1535252D, 0x13F8F1CB, 0xAAF6A508, 0xB38E10E, 0x7A4B238,
+ 0xC6A47410, 0xC864256, 0xF3C25E27, 0x94CE51D4, 0xF4ECAEEA,
+ 0x32684D74, 0x1AC8765, 0xDE6F6313, 0xF8C09409, 0xFB21FD21,
+ 0x6DB586BA, 0x241894B5, 0x65806E1F, 0x4B9D0DE7, 0x32DDDD16,
+ 0x3B16F0B0, 0xB56CAAF0, 0xC533ED5C, 0xADE48431, 0xB5893123,
+ 0xE977699C, 0xB295808B, 0x7A252898, 0xE3748392, 0x687A8ACD,
+ 0xB792504E, 0xBF4E2D8A, 0xB5EC4376, 0x754D9C34, 0x17BE53CC,
+ 0xC817A127, 0x732346E2, 0x29593976, 0x41D6AF89, 0x9072FAEC,
+ 0xC2B22666, 0x16A150DF, 0x4D379A36, 0xE732017F, 0xA6D12516,
+ 0xEA3DB9B5, 0x6E4C766B, 0xCA0ADEF5, 0x75E98F68, 0xC31687C3,
+ 0x62F16F66, 0x6486B129, 0xE237231B, 0xC6653007, 0x2BE06DFC,
+ 0x2BC32DC4, 0x9E3DD054, 0x47AA701E, 0x7741E537, 0xA09F9CD8,
+ 0x9D40881, 0x4F02F58, 0x6A5F31BB, 0x32BBBD23, 0x4520EB05,
+ 0x1DBFDD00, 0x6CCEC7D, 0x48CFC70C, 0xB41FBC13, 0x5B377E90,
+ 0x3B87923D, 0xC09F6D28, 0xC1CF24FB, 0xDD6BE459, 0x8B8BDD37,
+ 0xF7B103C8, 0xC1611360, 0xA8B8FCC8, 0xC16D4E2, 0x6AD23606,
+ 0x951A051, 0x6FC3B984, 0x95876867, 0xA0E1A04C, 0x8267F62C,
+ 0xC4B69588, 0xF53421DF, 0xC348685B, 0x59769E2B, 0x21F0FF90,
+ 0x2B978BB4, 0x3FDA987B, 0x216F4FFF, 0x95C68589, 0x2286F5D8,
+ 0x81E2702D, 0x88E2D01F, 0xE6F6B356, 0x2EA0C31, 0xA5E11CAF,
+ 0xE17DC578, 0x2115A0EA, 0x8DC2B323, 0xEB86957, 0xF3C7BECB,
+ 0xBCD805EC, 0x1121C3F5, 0xE6DEF224, 0x8EA2EE24, 0x2703D7B7,
+ 0x24D73574, 0x4068552C, 0xA85F5B6A, 0x65B563E, 0x4050954C,
+ 0xC7043820, 0x91E4A088, 0x19084C84, 0x7250FB54, 0xC1EC72,
+ 0x9FDB2412, 0x3B78E4E9, 0x588C2D17, 0x345C3232, 0xBC7CCB29,
+ 0xCB5F1F0A, 0x24EDD656, 0x7A9F0605, 0xC2EDB0E5, 0x7F01D20D,
+ 0x8EB211A2, 0x74AC4C1A, 0x37EDEDDB, 0x55B9AFF2, 0x100C4193,
+ 0x43CDF2C3, 0x9C75E7C1, 0xC43ABEFF, 0xB9704827, 0xDD4E6376,
+ 0xEA5FA0D3, 0xC6E14A66, 0xCB163673, 0x9515389, 0x5D3D30C5,
+ 0xD1FF8777, 0xC1347921, 0x21A5BAC, 0xD6CB5F87, 0xC6CE680B,
+ 0x46D1E5FB, 0x9B98BC15, 0x8D1446D6, 0x184659E7, 0xAAC79D5A,
+ 0x773E019E, 0xA1B9F814, 0x933D3D0B, 0x11DB7615, 0xC206A22A,
+ 0xE4EF5BA1, 0xF0EFA194, 0xDE0E6C2B, 0xBE185B42, 0xC28FDE0C,
+ 0xE416DD8A, 0xC636753F, 0xAFD119E, 0xB0198B17, 0x94C4115C,
+ 0x76EDF82A, 0x66818700, 0x6F003485, 0x993DFB2B, 0xF5A1F91E,
+ 0xDAB0080C, 0x7DF290D2, 0x72F65E9B, 0xBC126473, 0xF6050B10,
+ 0xB7380CA, 0x3352530, 0x9A403054, 0xB12581C1, 0x6F8E0370,
+ 0xBB5C1ED1, 0xCE738AFF, 0xE9F605DB, 0xA976BFE4, 0x68C9D107,
+ 0xA2BD1833, 0x545ACCE2, 0x965FBAF, 0x12D998F, 0x2C16B1CD,
+ 0xB20788BF, 0x96AADE36, 0xDF821415, 0xF1EBD654, 0x33F3C413,
+ 0xF2F2A6BF, 0x2DFB0ABA, 0x96845EC5, 0xB24622DD, 0xA83EEE5F,
+ 0x49DF9AF8, 0xB8DCFB8A, 0x16F7643, 0x436EFD30, 0xD90C9F8,
+ 0x9C10CD4E, 0x600CB15B, 0xE686606A, 0x5EC0502C, 0x23B2DCE5,
+ 0xDD5DE18D, 0x235A755C, 0xCB58A693, 0xACBEAFDE, 0xCA201FB5,
+ 0x2AE90380, 0x4F7455EC, 0xCA923312, 0x1BD202DD, 0x2D92B9E3,
+ 0xA2670F18, 0x831728C, 0x77D33D8C, 0x12400BDA, 0x9508A626,
+ 0x9253042B, 0x63C70C8C, 0x5496452F, 0x9237D610, 0x10448F3A,
+ 0x9303C709, 0x660D7EC, 0xDF6750F0, 0xBC4F14F2, 0x8F59720C,
+ 0xEE5AB051, 0xD5EC1228, 0xCC3E04CE, 0xE9E4D3B9, 0x8676FA58,
+ 0xF523860E, 0xF87D9BED, 0x4A6D02C9, 0xC5AD6CF0, 0x65F09045,
+ 0x8C620984, 0xDC40B4CD, 0x4216C291, 0x7A44C04B, 0x1E2B5D31,
+ 0xA0E77B7D, 0x12076C51, 0x22262FA1, 0x483B54F1, 0x2A7EF465,
+ 0xD1395E25, 0xB564369F, 0xC94A47A4, 0xFD678BAA, 0xECEE926A,
+ 0xE41A06AE, 0xE8F293C1, 0x3EB052BE, 0xD0959EF1, 0x93FF1935,
+ 0x4D65E4F1, 0xE87FC1F9, 0x3BD4BB2B, 0xD5F24F5B, 0x54FF70D4,
+ 0x968C7B60, 0x44F9BDE4, 0xF4894BDF, 0x3CFDDF7B, 0xD5CC3F10,
+ 0xD7F952C2, 0xEA3DCB60, 0xEFDAC96A, 0xBBF8F5EB, 0x41526813,
+ 0x714E3D51, 0x5E15A386, 0x1286AF4F, 0x5E1E5A3E, 0x676C9938,
+ 0xA716071B, 0x14D79998, 0x5CB794ED, 0xD815EDED, 0xCB1CA55A,
+ 0x9D6D74FD, 0xBE032C25, 0xF3FE1425, 0xC0CB5217, 0x3931A93F,
+ 0x82DB8222, 0xD8FF587F, 0x5AD4E8AC, 0xBCF00442, 0x4298A961,
+ 0x9F8CC3C2, 0x60E2347F, 0x7E090E, 0x691B735, 0x3D4C4D83,
+ 0x5612B097, 0x7B8DA321, 0x2C28A057, 0xF8FE8901, 0xDA39D0DD,
+ 0x465CE561, 0xA78756, 0x3B771E01, 0xE638B09, 0x201853B5,
+ 0xF934D7D2, 0xBD515A83, 0xC1B5C34E, 0x89159FA9, 0x2DDE3EBE,
+ 0xE27771DB, 0xB5983F05, 0xA3FD869D, 0x8ABA53CB, 0x55C8606C,
+ 0xDAB769C3, 0x4C4C2EAC, 0x18EE2A56, 0x88452A07, 0x9767C386,
+ 0x5C0418D6, 0xF79CA785, 0xF291195D, 0x9B0C286F, 0x68460BED,
+ 0xBF0079E5, 0x9906D932, 0x2F9E5535, 0x2A3C4947, 0xF0E240C3,
+ 0xE835A264, 0x43F38C0, 0x82DAADD8, 0x313612B1, 0x560D56FB,
+ 0x61BD734A, 0x58FD6B36, 0x2C45C40B, 0x55F70159, 0xA21A817D,
+ 0xAAA6FCE, 0x85BFDFB9, 0x1C71DE25, 0x56CB4C2C, 0x50FD91E5,
+ 0xF2340E88, 0x72BD5702, 0xB4FFBD3A, 0x1B35B171, 0xE94A34BD,
+ 0xC4C77575, 0x95B10420, 0x2471BC3F, 0xCB429841, 0x6DC5347F,
+ 0xC93CF782, 0xF1D26B2C, 0xEB2A260F, 0x67C3AE9, 0x34A56A4,
+ 0xF1F3D01B, 0xD8295F22, 0x7F9E5D4A, 0xE4DB3DEA, 0xE1531DCB,
+ 0x2C5FF857, 0x73622A7C, 0xC2691F1, 0xBC622B61, 0xE6A08C89,
+ 0xBA1807D4, 0x43ADBE43, 0xD90D427C, 0xC7A5C24, 0x613ED316,
+ 0xEC810B10, 0x1049BF74, 0x9A14C123, 0xA7B24E7E, 0x73254165,
+ 0x2C54081E, 0x14FF25AA, 0x7A12F3B4, 0xB4DF7C56, 0x89BFE8FC,
+ 0x5D5A04A6, 0xBE007173, 0x829DF863, 0x63E5E57D, 0x58F64C28,
+ 0x31A38144, 0xE843289B, 0xB48DFAF1, 0x2B335C2A, 0xEC3C96CE,
+ 0x255543F6, 0x33F17311, 0x3C60C51A, 0xE5D0D660, 0x5E162559,
+ 0xA2D9416, 0x9DDE4967, 0x28156A65, 0x71650796, 0x74EE54D1,
+ 0x3E8C19F7, 0x797C1E42, 0x2C536DFD, 0x2F3EED4D, 0x3BFC7C95,
+ 0x8EAEF87D, 0x18F5B02A, 0xA3532651, 0x24508E13, 0x280B9049,
+ 0xE4FC61CB, 0x388BA30F, 0xEC180A43, 0xBFDE77A4, 0x98CDB399,
+ 0xF82B586D, 0x38525AE7, 0x9D857BE8, 0xDD939D18, 0xD5CA6EBA,
+ 0xB70DDBA, 0xDFF43867, 0xD06AB2D0, 0xD8C78BB, 0x78F6AE4F,
+ 0x4C9A58CC, 0x9F9AA50E, 0x7D6A3912, 0xD897C7E4, 0x82F5939D,
+ 0xA4A9FFF5, 0x2CB56FDE, 0x3E082D4B, 0xB829DC58, 0xE4515CEB,
+ 0xCE585A33, 0x27901244, 0x68860E95, 0xE156A451, 0x9E351FE0,
+ 0xC69BD757, 0x4B2C4A2B, 0xD5DE5A91, 0x3557B0DE, 0x99E910B0,
+ 0x975BE470, 0xDB4DE130, 0xE4C6DA1D, 0xC2BC058F, 0x37544906,
+ 0x12CC200E, 0x54569133, 0x6586FC03, 0xF183C0CF, 0x642583E,
+ 0xFBE882CD, 0x8A098C35, 0xE8300988, 0xFE835E55, 0xEA74FD24,
+ 0xF3127AB2, 0xEE8379F2, 0x3F136FD2, 0x472AA942, 0x3BC1A7D7,
+ 0x5B6A8A98, 0xF039CCF3, 0x5E55425B, 0x3F801B4, 0x44556FB4,
+ 0xCC966D37, 0x56E32B90, 0x2BCDA2E5, 0xC70F1125, 0x8C2A015C,
+ 0x3D37FCA7, 0x2118A4EF, 0xCE051A9C, 0xCB84DCB9, 0x8451C9E0,
+ 0x4BDB1900, 0x8FC71D5D, 0xF61FD749, 0xA696D2E0, 0x6EED502A,
+ 0xB345CE8B, 0x76FCDA8E, 0xBE4A45F8, 0x8375E9E7, 0x625FF29B,
+ 0xCEC61240, 0x3876B21D, 0xBA8C8F59, 0x8CD169C6, 0x9F82251F,
+ 0x2E6EC495, 0x99319E, 0xB0160B46, 0x8B77EDD8, 0x6217902B,
+ 0x76FA6AD0, 0xB541F2BC, 0x961EA91C, 0x6F554C1F, 0xBD92328D,
+ 0xA9C077FD, 0x90A5311C, 0xEFE9B1FB, 0x9C84AA8C, 0x812517C3,
+ 0xFE71D7F4, 0xC4F6A5BF, 0x8B75A262, 0xC726EB36, 0x5F803035,
+ 0xCECDE2B7, 0xF61152A8, 0x78557ED1, 0x50F3BB55, 0xDD830290,
+ 0xB125B524, 0xC8683B0D, 0xE5FD573B, 0x48B13066, 0x62AE556E,
+ 0x5A637C89, 0x498D69F, 0x3F3A5BE5, 0xB98B86D7, 0x20CF4AF4,
+ 0xA3E55E7D, 0xEE93FC6F, 0xCCA95763, 0x5B3C5706, 0x8342B013,
+ 0xA0C7BDB9, 0x83D686E4, 0x6934B64, 0x324D75C3, 0x9A100C81,
+ 0x72E7E9AE, 0xC729A8AC, 0x9E8489E0, 0xFE5BC233, 0x64709AE9,
+ 0x113437BC, 0x296DEBC0, 0xC4376603, 0x9F0CD7EE, 0x6412AB97,
+ 0x3EECEFCD, 0x62DCD50, 0x15DFF1, 0xEEFDCF8E, 0x119849C1,
+ 0xDAAC93FF, 0xD531AF57, 0x82A10F47, 0xD55B7A97, 0x2F3A268B,
+ 0x4F1CC181, 0xAE01C1AC, 0xF3CF6F61, 0xE8BDAED5, 0x7397FD99,
+ 0xDD36A03C, 0x9BAED7C3, 0x51404903, 0xB9867B61, 0x3880A4FD,
+ 0x42B90A49, 0xA94696C1, 0x546DEA1D, 0xEE73A3DE, 0x1A4BAC37,
+ 0xBC6AF7AE, 0x7DD5B57B, 0xD2F121F, 0xD2BCCA1E, 0xD5DC4753,
+ 0xA135C08C, 0x78E97831, 0x9B91C00B, 0xFFF2C044, 0x147B797F,
+ 0x299CFB60, 0x71083BB, 0xB39A6C4F, 0x4814E3E1, 0xBD246AB0,
+ 0xBCD61250, 0x2D0870, 0xC660435C, 0xCA11681E, 0xADA4C80E,
+ 0x790C8875, 0x8C4F0D08, 0x48D90C74, 0xE874E9AA, 0xA8013EE8,
+ 0xB2D23A7A, 0xAF73A16E, 0x2485512C, 0x698E0CB2, 0x2FF566C9,
+ 0xC1B0C3C6, 0x2BE17C0E, 0xC42C3907, 0xD8A2EA94, 0x8991D24C,
+ 0x19B939F1, 0xF936F8B3, 0xA72D7EF1, 0x97EED001, 0xBF9C5156,
+ 0x75F08A67, 0x9AFD5756, 0x5D9D359C, 0xF905B7EC, 0x2B1553E1,
+ 0x9E0FD4E1, 0x8DC4814C, 0x89F28E6D, 0x14174915, 0x1F3A4217,
+ 0xA8F367F9, 0x93EE87C5, 0xAD70C6D8, 0xF04D465C, 0xE403D72B,
+ 0xA686EC0F, 0xCD3A5728, 0xA1BD007, 0x9E21E401, 0xAE8517CF,
+ 0x6DDB79FC, 0x8CB2C475, 0x6F71544, 0xBEAC91CF, 0x4739DC4E,
+ 0x6CF4F788, 0x36BAD9AC, 0xF23568D4, 0x250BAB0A, 0x4633384F,
+ 0x54F6F251, 0x454F9605, 0xCB1A346, 0x632E207F, 0x3017539C,
+ 0x174A33ED, 0xBDCFD2DE, 0xC17F3D39, 0x17B8A9A2, 0xC267FB51,
+ 0x9322387D, 0x348760C, 0x3C14D7E0, 0xE4E4254E, 0xCA72AA41,
+ 0xB6102ED3, 0x6317A3F, 0xD3B6B9F7, 0xA8C71BB7, 0x6E452957,
+ 0x3F896E32, 0xE38A4A58, 0x9893F432, 0x110A21D4, 0xE835FEBE,
+ 0x90F51080, 0xD0AC5AF, 0x4FCB9903, 0xFE547785, 0x144B285D,
+ 0xD0ECC753, 0xAE503BA4, 0x57CEAABC, 0x95713FE6, 0x5B0F4F86,
+ 0xD94BD751, 0x4017F139, 0xF60F5E1D, 0xB9A63351, 0xF7F94F6A,
+ 0x7E556ECC, 0xBFDB8642, 0xB70D07D, 0x351BEA77, 0xD1F3CAD,
+ 0xA3D7EF4D, 0x1EAA28E3, 0x98A2EA79, 0xD8647392, 0x1B896804,
+ 0x35CA6A08, 0x305258F, 0xE58BD955, 0xABCB6278, 0x87CF1146,
+ 0x13145966, 0x45BB55CD, 0x818AA368, 0xA027F11F, 0x64C427A3,
+ 0xEC831B99, 0xF2BD53F9, 0x7FDA7301, 0x35BE80D4, 0x5256E6FB,
+ 0xC97D33AE, 0x30921709, 0xC2724BEC, 0x78F5436F, 0x4F5749CD,
+ 0x9007F551, 0x327C31C0, 0x89782D13, 0x119AD125, 0xB1071A01,
+ 0x63100C70, 0x83120035, 0xA8E2E403, 0x7E213FA3, 0xBF06AAC4,
+ 0xBA68C4D9, 0x4B568927, 0x1DDD40F, 0x10FC10E8, 0xBBD7230A,
+ 0x96475640, 0x8C8E6EC1, 0x44A1134A, 0xEF0F40F0, 0x51E2A5E0,
+ 0x61AE6D65, 0x9DE72FD6, 0xB1711336, 0x90BEB84, 0xD610EFC6,
+ 0x3D231F91, 0xB5885164, 0x2CB2112C, 0x36F50789, 0x3DEF2AB9,
+ 0x1D9DC1DA, 0xA37DB070, 0x2AA92EB, 0x2D57ED6E, 0xD6E2C2CD,
+ 0xB78FC54C, 0x767A565E, 0x1D1F5AAE, 0x89F256DB, 0x716A97D,
+ 0x1344431D, 0xFAF015FB, 0xFED59649, 0xC479882A, 0xEEFC3D1E,
+ 0x840AE162, 0xD963A347, 0x75462C25, 0xDA990E07, 0x9A57DE31,
+ 0x74A35F20, 0x91852CD6, 0x3F16DE14, 0x5FA6A255, 0x47D00F85,
+ 0x1B4836C9, 0xC73D0290, 0xE301026B, 0x592068D6, 0x7C32A301,
+ 0x3A3C04C4, 0xB5BD3BAF, 0xB8C3BF60, 0x76723A1B, 0xD05BC35E,
+ 0x7679021C, 0x6298096, 0x590BA59C, 0xBB30A2F6, 0xE5F6B06C,
+ 0x21BD2A9E, 0xAC68D7DA, 0xEDA2ED5A, 0xA10E60FA, 0xABDBF569,
+ 0x17F5868E, 0x82AA8505, 0x384BD8FC, 0x68DC2746, 0x8F029C0D,
+ 0x3755EB11, 0xAEF4BB79, 0x453B87BA, 0x9926977F, 0x1FA1B806,
+ 0xC905618, 0x9BFE8E92, 0xF6F68A5A, 0xAA955D92, 0x44F57A4A,
+ 0x2186E272, 0x62EB01DA, 0x85A2D502, 0xB087955D, 0x26FF2BA0,
+ 0x8D462C04, 0xE024573B, 0x609CDBD7, 0xA99B9D19, 0xFEEB3F60,
+ 0x12903A0D, 0x46480C6, 0xDD0BD1B9, 0x6C60C43, 0x5E11A4FE,
+ 0x935E9E58, 0x8A7F6D33, 0xA505132D, 0xBB2E3E12, 0xF48633F4,
+ 0xF3BA8CF7, 0xC25D4EDD, 0x788672B8, 0xB2812608, 0xACB3A62,
+ 0x2EEB679A, 0x443A71B9, 0xC42F4B12, 0xD28B3482, 0x5571FA8A,
+ 0x5C0B3D55, 0x8B8619C6, 0xF564F10C, 0xD9A7C914, 0xFBD1EF46,
+ 0xCEABC573, 0xEC609D28, 0x5839413B, 0x5019E901, 0x248FFF30,
+ 0x7BFFB801, 0x7FD46584, 0x43702812, 0x3A5A0880, 0x7E3E9EDA,
+ 0xCA4623E3, 0x2FB87A70, 0xFE70D956, 0xCE9EB3E6, 0x9A2CD2F1,
+ 0x92EFB0C8, 0xC7E23873, 0x53B63A86, 0xB9D93548, 0x3C022B2,
+ 0xCF4F22A6, 0x981E70BC, 0x4A05F3AB, 0xD763E93B, 0x6EAF767D,
+ 0x4162629D, 0xD82A25E7, 0x6CDD19A3, 0x13524F68, 0xE5F23FDC,
+ 0xB37F311F, 0x35FD43B6, 0x36626469, 0x1E409CF6, 0xE4C04F9D,
+ 0xC1B58001, 0xD131078F, 0x9DE279A, 0x80B62212, 0x526405DD,
+ 0xC17777C1, 0x7045FCDC, 0x53862AEC, 0x5D583056, 0xEB532222,
+ 0x5837EA32, 0x719C06A4, 0x43D4F131, 0x577C6DDB, 0x9E5815A7,
+ 0x8189DDD9, 0x170F154F, 0xEF813B20, 0x4DD83A53, 0xB09A28FD,
+ 0x8D0DBED5, 0x1836596D, 0xC5BB2696, 0xA69FC859, 0xD6FF5E0D,
+ 0xCCC65761, 0xC818C6F7, 0x7A25F980, 0xF949133, 0xC515C093,
+ 0xA8AD04B5, 0x6768AC1C, 0xB5BE2C4A, 0x4F04616F, 0xBD28E4E3,
+ 0x4CCA6347, 0x5F61C031
+};
+
+/* The source data is random across the q31_t range. Accessing it by word should
+ remain random. */
+q15_t * transform_fft_q15_inputs = (q15_t *) transform_fft_q31_inputs;
+
+q15_t dct4_transform_fft_q15_inputs[TRANSFORM_MAX_FFT_LEN * 2] =
+{
+ 0x0000, 0x2d5c, 0x54d5, 0x714b, 0x7f0d, 0x7c51, 0x6972, 0x48e4,
+ 0x1edf, 0xf0da, 0xc4cb, 0xa06c, 0x8874, 0x8001, 0x882a, 0x9fe2,
+ 0xc413, 0xf00c, 0x1e16, 0x4839, 0x68fc, 0x7c1f, 0x7f25, 0x71ab,
+ 0x5570, 0x2e1e, 0x00cf, 0xd367, 0xabc7, 0x8f16, 0x810d, 0x837e,
+ 0x9619, 0xb672, 0xe057, 0x0e58, 0x3a7c, 0x5f0a, 0x7741, 0x7ffe,
+ 0x781e, 0x60a7, 0x3ca4, 0x10c2, 0xe2b4, 0xb873, 0x977b, 0x8415,
+ 0x80c3, 0x8df6, 0xa9f6, 0xd121, 0xfe61, 0x2bd6, 0x539c, 0x7087,
+ 0x7ed8, 0x7cb1, 0x6a5c, 0x4a38, 0x2072, 0xf277, 0xc63d, 0xa182,
+ 0x890b, 0x8005, 0x879b, 0x9ed2, 0xc2a6, 0xee70, 0x1c81, 0x46e0,
+ 0x680c, 0x7bb7, 0x7f53, 0x7268, 0x56a3, 0x2fa0, 0x026f, 0xd4ed,
+ 0xad02, 0x8fdc, 0x8145, 0x8321, 0x9531, 0xb51f, 0xdec5, 0x0cba,
+ 0x390a, 0x5df1, 0x76a8, 0x7ff7, 0x78ab, 0x61b5, 0x3e10, 0x125e,
+ 0xe449, 0xb9cd, 0x986d, 0x847f, 0x8099, 0x8d3c, 0xa8c4, 0xcf9f,
+ 0xfcc2, 0x2a4f, 0x5260, 0x6fbf, 0x7e9d, 0x7d0c, 0x6b40, 0x4b89,
+ 0x2203, 0xf414, 0xc7b1, 0xa29c, 0x89a7, 0x800e, 0x8710, 0x9dc5,
+ 0xc13a, 0xecd5, 0x1aec, 0x4585, 0x6718, 0x7b4a, 0x7f7b, 0x7320,
+ 0x57d3, 0x3121, 0x040e, 0xd675, 0xae40, 0x90a7, 0x8182, 0x82c8,
+ 0x944f, 0xb3d0, 0xdd35, 0x0b1d, 0x3795, 0x5cd5, 0x760a, 0x7fec,
+ 0x7933, 0x62bf, 0x3f7a, 0x13f8, 0xe5df, 0xbb2a, 0x9964, 0x84ef,
+ 0x8073, 0x8c86, 0xa796, 0xce20, 0xfb23, 0x28c6, 0x5120, 0x6ef2,
+ 0x7e5e, 0x7d63, 0x6c21, 0x4cd7, 0x2393, 0xf5b2, 0xc927, 0xa3ba,
+ 0x8a47, 0x801c, 0x868b, 0x9cbd, 0xbfd1, 0xeb3b, 0x1955, 0x4427,
+ 0x6620, 0x7ad7, 0x7f9d, 0x73d3, 0x5900, 0x329f, 0x05ad, 0xd7ff,
+ 0xaf81, 0x9176, 0x81c4, 0x8274, 0x9370, 0xb284, 0xdba6, 0x097f,
+ 0x361d, 0x5bb5, 0x7566, 0x7fda, 0x79b6, 0x63c6, 0x40e2, 0x1592,
+ 0xe777, 0xbc8a, 0x9a5e, 0x8564, 0x8053, 0x8bd5, 0xa66b, 0xcca2,
+ 0xf983, 0x273c, 0x4fdd, 0x6e21, 0x7e19, 0x7db3, 0x6cfd, 0x4e21,
+ 0x2521, 0xf750, 0xca9f, 0xa4dc, 0x8aed, 0x8030, 0x860a, 0x9bb9,
+ 0xbe6b, 0xe9a1, 0x17bd, 0x42c6, 0x6523, 0x7a60, 0x7fbb, 0x7481,
+ 0x5a29, 0x341c, 0x074c, 0xd98a, 0xb0c6, 0x924a, 0x820b, 0x8226,
+ 0x9297, 0xb13b, 0xda18, 0x07e0, 0x34a4, 0x5a92, 0x74bf, 0x7fc4,
+ 0x7a34, 0x64c8, 0x4247, 0x172b, 0xe90f, 0xbdec, 0x9b5d, 0x85dd,
+ 0x8038, 0x8b29, 0xa544, 0xcb27, 0xf7e5, 0x25af, 0x4e97, 0x6d4b,
+ 0x7dcf, 0x7dff, 0x6dd5, 0x4f69, 0x26ae, 0xf8ef, 0xcc1a, 0xa601,
+ 0x8b97, 0x8049, 0x858f, 0x9ab9, 0xbd08, 0xe809, 0x1625, 0x4162,
+ 0x6422, 0x79e4, 0x7fd3, 0x752b, 0x5b4e, 0x3596, 0x08eb, 0xdb17,
+ 0xb20e, 0x9322, 0x8258, 0x81dd, 0x91c1, 0xaff5, 0xd88c, 0x0641,
+ 0x3328, 0x596a, 0x7412, 0x7fa8, 0x7aad, 0x65c6, 0x43a9, 0x18c3,
+ 0xeaa8, 0xbf51, 0x9c5f, 0x865c, 0x8023, 0x8a82, 0xa421, 0xc9ad,
+ 0xf646, 0x2422, 0x4d4d, 0x6c70, 0x7d80, 0x7e46, 0x6ea8, 0x50ad,
+ 0x2839, 0xfa8e, 0xcd97, 0xa72b, 0x8c46, 0x8067, 0x8518, 0x99bd,
+ 0xbba7, 0xe671, 0x148b, 0x3ffb, 0x631e, 0x7963, 0x7fe6, 0x75d0,
+ 0x5c6f, 0x370f, 0x0a89, 0xdca6, 0xb359, 0x93ff, 0x82a9, 0x8199,
+ 0x90f0, 0xaeb2, 0xd702, 0x04a2, 0x31aa, 0x583f, 0x7360, 0x7f88,
+ 0x7b21, 0x66c0, 0x4508, 0x1a5a, 0xec42, 0xc0b9, 0x9d66, 0x86e0,
+ 0x8012, 0x89e0, 0xa302, 0xc836, 0xf4a8, 0x2292, 0x4c01, 0x6b91,
+ 0x7d2c, 0x7e87, 0x6f76, 0x51ee, 0x29c3, 0xfc2d, 0xcf16, 0xa858,
+ 0x8cfa, 0x808b, 0x84a7, 0x98c5, 0xba4a, 0xe4da, 0x12f1, 0x3e92,
+ 0x6215, 0x78dc, 0x7ff4, 0x7670, 0x5d8c, 0x3884, 0x0c27, 0xde36,
+ 0xb4a7, 0x94e0, 0x8300, 0x815a, 0x9024, 0xad73, 0xd579, 0x0303,
+ 0x302a, 0x5711, 0x72aa, 0x7f61, 0x7b90, 0x67b5, 0x4664, 0x1bf0,
+ 0xeddd, 0xc223, 0x9e71, 0x8769, 0x8007, 0x8942, 0xa1e6, 0xc6c2,
+ 0xf30b, 0x2102, 0x4ab1, 0x6aae, 0x7cd2, 0x7ec3, 0x7040, 0x532b,
+ 0x2b4b, 0xfdcc, 0xd097, 0xa988, 0x8db3, 0x80b4, 0x843a, 0x97d1,
+ 0xb8ef, 0xe345, 0x1155, 0x3d27, 0x6108, 0x7851, 0x7ffc, 0x770b,
+ 0x5ea6, 0x39f8, 0x0dc4, 0xdfc7, 0xb5f8, 0x95c5, 0x835c, 0x8120,
+ 0x8f5d, 0xac37, 0xd3f2, 0x0164, 0x2ea8, 0x55de, 0x71ef, 0x7f36,
+ 0x7bfa, 0x68a7, 0x47be, 0x1d85, 0xef79, 0xc390, 0x9f80, 0x87f6,
+ 0x8001, 0x88a9, 0xa0cf, 0xc54f, 0xf16e, 0x1f70, 0x495e, 0x69c6,
+ 0x7c74, 0x7efa, 0x7106, 0x5465, 0x2cd1, 0xff6c, 0xd219, 0xaabc,
+ 0x8e70, 0x80e2, 0x83d3, 0x96e2, 0xb796, 0xe1b1, 0x0fb9, 0x3bb8,
+ 0x5ff7, 0x77c1, 0x7fff, 0x77a1, 0x5fbc, 0x3b69, 0x0f61, 0xe15a,
+ 0xb74d, 0x96af, 0x83bd, 0x80ec, 0x8e9a, 0xaaff, 0xd26d, 0xffc5,
+ 0x2d24, 0x54a8, 0x712f, 0x7f05, 0x7c5f, 0x6994, 0x4914, 0x1f19,
+ 0xf115, 0xc500, 0xa093, 0x8889, 0x8001, 0x8816, 0x9fbb, 0xc3df,
+ 0xefd1, 0x1ddc, 0x4808, 0x68da, 0x7c10, 0x7f2c, 0x71c6, 0x559c,
+ 0x2e55, 0x010a, 0xd39e, 0xabf4, 0x8f32, 0x8115, 0x8371, 0x95f7,
+ 0xb641, 0xe01e, 0x0e1d, 0x3a48, 0x5ee2, 0x772c, 0x7ffd, 0x7832,
+ 0x60cd, 0x3cd8, 0x10fd, 0xe2ee, 0xb8a4, 0x979e, 0x8423, 0x80bd,
+ 0x8ddb, 0xa9ca, 0xd0ea, 0xfe26, 0x2b9f, 0x536f, 0x706b, 0x7ed0,
+ 0x7cbf, 0x6a7c, 0x4a68, 0x20ab, 0xf2b2, 0xc672, 0xa1aa, 0x8921,
+ 0x8006, 0x8787, 0x9eab, 0xc272, 0xee36, 0x1c48, 0x46af, 0x67ea,
+ 0x7ba8, 0x7f59, 0x7282, 0x56cf, 0x2fd7, 0x02aa, 0xd525, 0xad2f,
+ 0x8ff9, 0x814d, 0x8314, 0x9511, 0xb4ef, 0xde8c, 0x0c80, 0x38d5,
+ 0x5dc9, 0x7692, 0x7ff6, 0x78bf, 0x61db, 0x3e44, 0x1298, 0xe483,
+ 0xb9ff, 0x9890, 0x848f, 0x8093, 0x8d22, 0xa899, 0xcf68, 0xfc87,
+ 0x2a17, 0x5232, 0x6fa2, 0x7e95, 0x7d19, 0x6b61, 0x4bb8, 0x223c,
+ 0xf44f, 0xc7e6, 0xa2c5, 0x89bd, 0x8010, 0x86fd, 0x9d9f, 0xc107,
+ 0xec9b, 0x1ab2, 0x4553, 0x66f5, 0x7b3a, 0x7f80, 0x7339, 0x57fe,
+ 0x3157, 0x0449, 0xd6ad, 0xae6d, 0x90c4, 0x818b, 0x82bc, 0x942f,
+ 0xb3a0, 0xdcfc, 0x0ae2, 0x375f, 0x5cad, 0x75f3, 0x7fe9, 0x7946,
+ 0x62e5, 0x3fae, 0x1433, 0xe619, 0xbb5c, 0x9987, 0x84ff, 0x806f,
+ 0x8c6d, 0xa76b, 0xcde9, 0xfae7, 0x288e, 0x50f2, 0x6ed5, 0x7e54,
+ 0x7d6e, 0x6c41, 0x4d06, 0x23cc, 0xf5ed, 0xc95c, 0xa3e3, 0x8a5f,
+ 0x801f, 0x8678, 0x9c98, 0xbf9e, 0xeb00, 0x191b, 0x43f5, 0x65fc,
+ 0x7ac7, 0x7fa2, 0x73ec, 0x592a, 0x32d6, 0x05e8, 0xd837, 0xafaf,
+ 0x9194, 0x81ce, 0x8269, 0x9351, 0xb255, 0xdb6d, 0x0944, 0x35e8,
+ 0x5b8c, 0x754f, 0x7fd8, 0x79c8, 0x63eb, 0x4115, 0x15cc, 0xe7b1,
+ 0xbcbc, 0x9a82, 0x8575, 0x804f, 0x8bbd, 0xa641, 0xcc6c, 0xf948,
+ 0x2703, 0x4faf, 0x6e03, 0x7e0f, 0x7dbf, 0x6d1c, 0x4e50, 0x255a,
+ 0xf78b, 0xcad5, 0xa505, 0x8b05, 0x8033, 0x85f8, 0x9b94, 0xbe39,
+ 0xe967, 0x1783, 0x4293, 0x64ff, 0x7a4f, 0x7fbf, 0x749a, 0x5a52,
+ 0x3452, 0x0787, 0xd9c3, 0xb0f4, 0x9268, 0x8216, 0x821b, 0x9278,
+ 0xb10c, 0xd9e0, 0x07a5, 0x346e, 0x5a68, 0x74a6, 0x7fc0, 0x7a46,
+ 0x64ec, 0x4279, 0x1765, 0xe949, 0xbe1f, 0x9b81, 0x85ef, 0x8035,
+ 0x8b11, 0xa51b, 0xcaf1, 0xf7aa, 0x2577, 0x4e68, 0x6d2c, 0x7dc4,
+ 0x7e0a, 0x6df3, 0x4f97, 0x26e6, 0xf92a, 0xcc50, 0xa62c, 0x8bb0,
+ 0x804d, 0x857d, 0x9a95, 0xbcd6, 0xe7cf, 0x15ea, 0x412f, 0x63fe,
+ 0x79d2, 0x7fd6, 0x7543, 0x5b77, 0x35cc, 0x0925, 0xdb50, 0xb23d,
+ 0x9341, 0x8263, 0x81d3, 0x91a3, 0xafc7, 0xd854, 0x0606, 0x32f2,
+ 0x5940, 0x73f9, 0x7fa4, 0x7abe, 0x65ea, 0x43db, 0x18fd, 0xeae2,
+ 0xbf84, 0x9c85, 0x866f, 0x8020, 0x8a6b, 0xa3f8, 0xc978, 0xf60b,
+ 0x23e9, 0x4d1e, 0x6c51, 0x7d74, 0x7e4f, 0x6ec5, 0x50db, 0x2871,
+ 0xfac9, 0xcdcd, 0xa755, 0x8c60, 0x806c, 0x8508, 0x9999, 0xbb75,
+ 0xe637, 0x1451, 0x3fc8, 0x62f8, 0x7950, 0x7fe8, 0x75e7, 0x5c98,
+ 0x3744, 0x0ac4, 0xdcdf, 0xb388, 0x941e, 0x82b5, 0x8190, 0x90d3,
+ 0xae85, 0xd6ca, 0x0467, 0x3173, 0x5814, 0x7347, 0x7f82, 0x7b31,
+ 0x66e3, 0x453a, 0x1a94, 0xec7d, 0xc0ec, 0x9d8c, 0x86f3, 0x8011,
+ 0x89c9, 0xa2d9, 0xc801, 0xf46d, 0x2259, 0x4bd1, 0x6b71, 0x7d1f,
+ 0x7e90, 0x6f93, 0x521b, 0x29fb, 0xfc68, 0xcf4c, 0xa883, 0x8d14,
+ 0x8090, 0x8497, 0x98a2, 0xba18, 0xe4a1, 0x12b6, 0x3e5f, 0x61ef,
+ 0x78c9, 0x7ff5, 0x7686, 0x5db5, 0x38b9, 0x0c61, 0xde6f, 0xb4d7,
+ 0x9500, 0x830d, 0x8152, 0x9007, 0xad46, 0xd541, 0x02c8, 0x2ff3,
+ 0x56e5, 0x7290, 0x7f5c, 0x7ba0, 0x67d8, 0x4696, 0x1c2a, 0xee17,
+ 0xc257, 0x9e97, 0x877d, 0x8006, 0x892c, 0xa1be, 0xc68d, 0xf2d0,
+ 0x20c8, 0x4a81, 0x6a8d, 0x7cc5, 0x7ecc, 0x705d, 0x5358, 0x2b82,
+ 0xfe08, 0xd0ce, 0xa9b4, 0x8dce, 0x80ba, 0x842b, 0x97af, 0xb8bd,
+ 0xe30b, 0x111b, 0x3cf3, 0x60e1, 0x783d, 0x7ffd, 0x7721, 0x5ece,
+ 0x3a2d, 0x0dff, 0xe000, 0xb629, 0x95e6, 0x836a, 0x8119, 0x8f41,
+ 0xac0b, 0xd3bb, 0x0129, 0x2e71, 0x55b2, 0x71d4, 0x7f2f, 0x7c09,
+ 0x68c9, 0x47ef, 0x1dbf, 0xefb3, 0xc3c4, 0x9fa7, 0x880b, 0x8001,
+ 0x8894, 0xa0a7, 0xc51b, 0xf133, 0x1f36, 0x492d, 0x69a5, 0x7c66,
+ 0x7f02, 0x7121, 0x5492, 0x2d08, 0xffa7, 0xd251, 0xaae8, 0x8e8b,
+ 0x80e9, 0x83c5, 0x96c1, 0xb766, 0xe177, 0x0f7f, 0x3b84, 0x5fd0,
+ 0x77ac, 0x7fff, 0x77b6, 0x5fe3, 0x3b9d, 0x0f9b, 0xe193, 0xb77d,
+ 0x96d1, 0x83cc, 0x80e5, 0x8e7e, 0xaad3, 0xd236, 0xff8a, 0x2ced,
+ 0x547c, 0x7114, 0x7efe, 0x7c6d, 0x69b5, 0x4945, 0x1f52, 0xf150,
+ 0xc534, 0xa0ba, 0x889e, 0x8001, 0x8801, 0x9f94, 0xc3ab, 0xef97,
+ 0x1da3, 0x47d7, 0x68b8, 0x7c02, 0x7f33, 0x71e1, 0x55c8, 0x2e8c,
+ 0x0145, 0xd3d6, 0xac20, 0x8f4e, 0x811c, 0x8363, 0x95d6, 0xb611,
+ 0xdfe5, 0x0de2, 0x3a13, 0x5eba, 0x7716, 0x7ffd, 0x7847, 0x60f4,
+ 0x3d0c, 0x1137, 0xe327, 0xb8d5, 0x97c0, 0x8432, 0x80b7, 0x8dc1,
+ 0xa99f, 0xd0b3, 0xfdeb, 0x2b67, 0x5342, 0x704f, 0x7ec8, 0x7ccc,
+ 0x6a9d, 0x4a98, 0x20e4, 0xf2ed, 0xc6a6, 0xa1d2, 0x8937, 0x8007,
+ 0x8773, 0x9e85, 0xc23e, 0xedfb, 0x1c0e, 0x467e, 0x67c7, 0x7b98,
+ 0x7f5e, 0x729d, 0x56fa, 0x300e, 0x02e5, 0xd55c, 0xad5c, 0x9015,
+ 0x8156, 0x8307, 0x94f0, 0xb4c0, 0xde53, 0x0c45, 0x38a0, 0x5da1,
+ 0x767b, 0x7ff5, 0x78d2, 0x6201, 0x3e78, 0x12d3, 0xe4bd, 0xba30,
+ 0x98b3, 0x849e, 0x808e, 0x8d08, 0xa86e, 0xcf32, 0xfc4c, 0x29df,
+ 0x5205, 0x6f85, 0x7e8c, 0x7d25, 0x6b81, 0x4be8, 0x2275, 0xf48a,
+ 0xc81b, 0xa2ed, 0x89d4, 0x8011, 0x86ea, 0x9d7a, 0xc0d3, 0xec60,
+ 0x1a78, 0x4522, 0x66d2, 0x7b2a, 0x7f85, 0x7353, 0x5829, 0x318e,
+ 0x0484, 0xd6e5, 0xae9b, 0x90e1, 0x8194, 0x82b0, 0x940f, 0xb371,
+ 0xdcc3, 0x0aa7, 0x372a, 0x5c84, 0x75dc, 0x7fe7, 0x7959, 0x630a,
+ 0x3fe1, 0x146d, 0xe653, 0xbb8e, 0x99aa, 0x8510, 0x806a, 0x8c53,
+ 0xa741, 0xcdb3, 0xfaac, 0x2856, 0x50c4, 0x6eb7, 0x7e4b, 0x7d7a,
+ 0x6c60, 0x4d35, 0x2404, 0xf628, 0xc992, 0xa40c, 0x8a76, 0x8021,
+ 0x8666, 0x9c72, 0xbf6b, 0xeac6, 0x18e1, 0x43c2, 0x65d8, 0x7ab6,
+ 0x7fa6, 0x7405, 0x5955, 0x330c, 0x0623, 0xd86f, 0xafdd, 0x91b2,
+ 0x81d8, 0x825e, 0x9332, 0xb226, 0xdb34, 0x0909, 0x35b2, 0x5b63,
+ 0x7537, 0x7fd5, 0x79db, 0x6410, 0x4148, 0x1607, 0xe7eb, 0xbcee,
+ 0x9aa6, 0x8586, 0x804b, 0x8ba4, 0xa617, 0xcc36, 0xf90d, 0x26cb,
+ 0x4f80, 0x6de4, 0x7e05, 0x7dca, 0x6d3b, 0x4e7f, 0x2592, 0xf7c6,
+ 0xcb0b, 0xa52f, 0x8b1d, 0x8037, 0x85e6, 0x9b6f, 0xbe06, 0xe92d,
+ 0x1749, 0x4261, 0x64db, 0x7a3d, 0x7fc2, 0x74b2, 0x5a7c, 0x3488,
+ 0x07c2, 0xd9fb, 0xb123, 0x9287, 0x8220, 0x8211, 0x9259, 0xb0de,
+ 0xd9a7, 0x076a, 0x3438, 0x5a3e, 0x748e, 0x7fbd, 0x7a57, 0x6511,
+ 0x42ac, 0x179f, 0xe983, 0xbe51, 0x9ba6, 0x8601, 0x8032, 0x8af9,
+ 0xa4f1, 0xcabb, 0xf76f, 0x253e, 0x4e39, 0x6d0d, 0x7db9, 0x7e14,
+ 0x6e11, 0x4fc5, 0x271f, 0xf965, 0xcc86, 0xa656, 0x8bc9, 0x8051,
+ 0x856c, 0x9a70, 0xbca3, 0xe795, 0x15b0, 0x40fc, 0x63d9, 0x79c0,
+ 0x7fd9, 0x755a, 0x5ba0, 0x3602, 0x0960, 0xdb89, 0xb26c, 0x9360,
+ 0x826e, 0x81c9, 0x9185, 0xaf99, 0xd81c, 0x05cb, 0x32bb, 0x5916,
+ 0x73e0, 0x7fa0, 0x7acf, 0x660d, 0x440d, 0x1937, 0xeb1d, 0xbfb7,
+ 0x9caa, 0x8681, 0x801e, 0x8a53, 0xa3cf, 0xc942, 0xf5d0, 0x23b0,
+ 0x4cef, 0x6c31, 0x7d69, 0x7e59, 0x6ee3, 0x5108, 0x28a9, 0xfb04,
+ 0xce04, 0xa780, 0x8c79, 0x8071, 0x84f7, 0x9976, 0xbb43, 0xe5fd,
+ 0x1416, 0x3f95, 0x62d3, 0x793d, 0x7feb, 0x75fe, 0x5cc0, 0x3779,
+ 0x0aff, 0xdd18, 0xb3b8, 0x943e, 0x82c2, 0x8186, 0x90b6, 0xae57,
+ 0xd692, 0x042c, 0x313d, 0x57ea, 0x732d, 0x7f7d, 0x7b41, 0x6706,
+ 0x456b, 0x1ace, 0xecb7, 0xc120, 0x9db2, 0x8706, 0x800f, 0x89b2,
+ 0xa2b1, 0xc7cc, 0xf433, 0x2220, 0x4ba1, 0x6b51, 0x7d13, 0x7e99,
+ 0x6fb0, 0x5248, 0x2a32, 0xfca3, 0xcf83, 0xa8ae, 0x8d2e, 0x8096,
+ 0x8487, 0x987f, 0xb9e6, 0xe467, 0x127c, 0x3e2b, 0x61c9, 0x78b5,
+ 0x7ff7, 0x769c, 0x5ddd, 0x38ee, 0x0c9c, 0xdea8, 0xb507, 0x9521,
+ 0x831a, 0x8149, 0x8feb, 0xad19, 0xd50a, 0x028d, 0x2fbc, 0x56ba,
+ 0x7275, 0x7f56, 0x7baf, 0x67fa, 0x46c7, 0x1c64, 0xee52, 0xc28b,
+ 0x9ebe, 0x8791, 0x8005, 0x8916, 0xa196, 0xc658, 0xf295, 0x208f,
+ 0x4a51, 0x6a6c, 0x7cb8, 0x7ed4, 0x7079, 0x5385, 0x2bba, 0xfe43,
+ 0xd104, 0xa9df, 0x8de8, 0x80c0, 0x841c, 0x978d, 0xb88c, 0xe2d2,
+ 0x10e0, 0x3cbf, 0x60bb, 0x7828, 0x7ffe, 0x7736, 0x5ef5, 0x3a61,
+ 0x0e39, 0xe03a, 0xb659, 0x9608, 0x8377, 0x8111, 0x8f25, 0xabde,
+ 0xd383, 0x00ee, 0x2e3a, 0x5586, 0x71b9, 0x7f29, 0x7c17, 0x68eb,
+ 0x4820, 0x1df8, 0xefee, 0xc3f9, 0x9fce, 0x8820, 0x8001, 0x887f,
+ 0xa080, 0xc4e6, 0xf0f8, 0x1efd, 0x48fd, 0x6983, 0x7c58, 0x7f09,
+ 0x713d, 0x54be, 0x2d3f, 0xffe2, 0xd288, 0xab15, 0x8ea7, 0x80f0,
+ 0x83b6, 0x969f, 0xb735, 0xe13e, 0x0f44, 0x3b50, 0x5fa9, 0x7797,
+ 0x7fff, 0x77cb, 0x600a, 0x3bd2, 0x0fd6, 0xe1cd, 0xb7ae, 0x96f3,
+ 0x83da, 0x80de, 0x8e63, 0xaaa7, 0xd1ff, 0xff4f, 0x2cb6, 0x5450,
+ 0x70f8, 0x7ef7, 0x7c7b, 0x69d6, 0x4975, 0x1f8b, 0xf18a, 0xc569,
+ 0xa0e2, 0x88b4, 0x8002, 0x87ed, 0x9f6d, 0xc377, 0xef5c, 0x1d69,
+ 0x47a6, 0x6896, 0x7bf3, 0x7f39, 0x71fc, 0x55f4, 0x2ec3, 0x0181,
+ 0xd40d, 0xac4d, 0x8f6a, 0x8124, 0x8356, 0x95b5, 0xb5e1, 0xdfab,
+ 0x0da7, 0x39de, 0x5e93, 0x7700, 0x7ffc, 0x785b, 0x611b, 0x3d40,
+ 0x1172, 0xe361, 0xb906, 0x97e2, 0x8441, 0x80b1, 0x8da6, 0xa973,
+ 0xd07c, 0xfdb0, 0x2b30, 0x5315, 0x7032, 0x7ebf, 0x7cd9, 0x6abe,
+ 0x4ac8, 0x211d, 0xf327, 0xc6db, 0xa1fa, 0x894d, 0x8008, 0x875f,
+ 0x9e5f, 0xc20a, 0xedc1, 0x1bd4, 0x464c, 0x67a4, 0x7b89, 0x7f64,
+ 0x72b7, 0x5726, 0x3045, 0x0320, 0xd594, 0xad89, 0x9032, 0x815e,
+ 0x82fa, 0x94d0, 0xb490, 0xde1a, 0x0c0a, 0x386b, 0x5d79, 0x7665,
+ 0x7ff3, 0x78e6, 0x6227, 0x3eab, 0x130d, 0xe4f7, 0xba62, 0x98d6,
+ 0x84ae, 0x8088, 0x8cee, 0xa843, 0xcefb, 0xfc10, 0x29a8, 0x51d8,
+ 0x6f68, 0x7e83, 0x7d32, 0x6ba1, 0x4c18, 0x22ae, 0xf4c5, 0xc850,
+ 0xa316, 0x89eb, 0x8013, 0x86d7, 0x9d54, 0xc0a0, 0xec26, 0x1a3e,
+ 0x44f0, 0x66af, 0x7b19, 0x7f8a, 0x736d, 0x5854, 0x31c4, 0x04bf,
+ 0xd71d, 0xaec9, 0x90ff, 0x819d, 0x82a4, 0x93ef, 0xb342, 0xdc8a,
+ 0x0a6c, 0x36f5, 0x5c5b, 0x75c5, 0x7fe5, 0x796c, 0x6330, 0x4014,
+ 0x14a7, 0xe68d, 0xbbc0, 0x99ce, 0x8520, 0x8065, 0x8c3a, 0xa716,
+ 0xcd7c, 0xfa71, 0x281e, 0x5097, 0x6e99, 0x7e41, 0x7d86, 0x6c80,
+ 0x4d64, 0x243d, 0xf663, 0xc9c7, 0xa435, 0x8a8d, 0x8024, 0x8653,
+ 0x9c4d, 0xbf38, 0xea8c, 0x18a7, 0x4390, 0x65b4, 0x7aa5, 0x7fab,
+ 0x741e, 0x597f, 0x3342, 0x065e, 0xd8a8, 0xb00b, 0x91d0, 0x81e2,
+ 0x8252, 0x9313, 0xb1f7, 0xdafc, 0x08ce, 0x357c, 0x5b39, 0x751f,
+ 0x7fd2, 0x79ed, 0x6434, 0x417b, 0x1641, 0xe825, 0xbd20, 0x9aca,
+ 0x8597, 0x8047, 0x8b8b, 0xa5ed, 0xcc00, 0xf8d2, 0x2693, 0x4f52,
+ 0x6dc6, 0x7dfa, 0x7dd4, 0x6d5a, 0x4ead, 0x25cb, 0xf801, 0xcb41,
+ 0xa559, 0x8b35, 0x803a, 0x85d5, 0x9b4b, 0xbdd3, 0xe8f3, 0x170f,
+ 0x422e, 0x64b6, 0x7a2c, 0x7fc6, 0x74ca, 0x5aa6, 0x34be, 0x07fd,
+ 0xda34, 0xb151, 0x92a5, 0x822b, 0x8206, 0x923b, 0xb0af, 0xd96f,
+ 0x072f, 0x3402, 0x5a14, 0x7475, 0x7fb9, 0x7a69, 0x6535, 0x42de,
+ 0x17da, 0xe9bd, 0xbe84, 0x9bcb, 0x8613, 0x802f, 0x8ae1, 0xa4c8,
+ 0xca85, 0xf734, 0x2506, 0x4e0a, 0x6cee, 0x7dae, 0x7e1e, 0x6e2f,
+ 0x4ff3, 0x2757, 0xf9a0, 0xccbc, 0xa680, 0x8be1, 0x8055, 0x855b,
+ 0x9a4d, 0xbc71, 0xe75a, 0x1576, 0x40c9, 0x63b4, 0x79ad, 0x7fdc,
+ 0x7572, 0x5bca, 0x3637, 0x099b, 0xdbc1, 0xb29b, 0x9380, 0x827a,
+ 0x81bf, 0x9168, 0xaf6b, 0xd7e4, 0x0590, 0x3285, 0x58eb, 0x73c7,
+ 0x7f9b, 0x7adf, 0x6631, 0x443f, 0x1971, 0xeb57, 0xbfea, 0x9ccf,
+ 0x8694, 0x801b, 0x8a3c, 0xa3a6, 0xc90d, 0xf596, 0x2377, 0x4cc0,
+ 0x6c12, 0x7d5d, 0x7e62, 0x6f00, 0x5136, 0x28e1, 0xfb3f, 0xce3a,
+ 0xa7ab, 0x8c93, 0x8076, 0x84e7, 0x9952, 0xbb12, 0xe5c3, 0x13dc,
+ 0x3f62, 0x62ad, 0x792a, 0x7fed, 0x7615, 0x5ce9, 0x37ae, 0x0b39,
+ 0xdd50, 0xb3e7, 0x945e, 0x82ce, 0x817d, 0x9099, 0xae2a, 0xd65a,
+ 0x03f1, 0x3106, 0x57bf, 0x7313, 0x7f78, 0x7b51, 0x6729, 0x459d,
+ 0x1b08, 0xecf1, 0xc153, 0x9dd8, 0x871a, 0x800d, 0x899c, 0xa288,
+ 0xc797, 0xf3f8, 0x21e7, 0x4b72, 0x6b31, 0x7d06, 0x7ea2, 0x6fcd,
+ 0x5276, 0x2a6a, 0xfcde, 0xcfba, 0xa8d9, 0x8d48, 0x809c, 0x8478,
+ 0x985c, 0xb9b5, 0xe42d, 0x1241, 0x3df7, 0x61a2, 0x78a1, 0x7ff8,
+ 0x76b3, 0x5e05, 0x3923, 0x0cd7, 0xdee1, 0xb537, 0x9541, 0x8327,
+ 0x8141, 0x8fce, 0xacec, 0xd4d2, 0x0252, 0x2f86, 0x568e, 0x725b,
+ 0x7f50, 0x7bbe, 0x681d, 0x46f8, 0x1c9d, 0xee8d, 0xc2bf, 0x9ee4,
+ 0x87a5, 0x8004, 0x8900, 0xa16f, 0xc623, 0xf25a, 0x2056, 0x4a20,
+ 0x6a4c, 0x7cab, 0x7edb, 0x7095, 0x53b2, 0x2bf1, 0xfe7e, 0xd13c,
+ 0xaa0b, 0x8e03, 0x80c7, 0x840d, 0x976b, 0xb85b, 0xe298, 0x10a6,
+ 0x3c8b, 0x6094, 0x7814, 0x7ffe, 0x774c, 0x5f1d, 0x3a96, 0x0e74,
+ 0xe073, 0xb689, 0x9629, 0x8385, 0x810a, 0x8f09, 0xabb2, 0xd34c,
+ 0x00b2, 0x2e03, 0x555a, 0x719e, 0x7f22, 0x7c26, 0x690c, 0x4850,
+ 0x1e32, 0xf028, 0xc42d, 0x9ff5, 0x8835, 0x8001, 0x886a, 0xa059,
+ 0xc4b2, 0xf0be, 0x1ec4, 0x48cc, 0x6962, 0x7c4a, 0x7f10, 0x7158,
+ 0x54ea, 0x2d77, 0x001c, 0xd2bf, 0xab41, 0x8ec2, 0x80f7, 0x83a8,
+ 0x967d, 0xb705, 0xe105, 0x0f09, 0x3b1b, 0x5f81, 0x7782, 0x7fff,
+ 0x77e0, 0x6031, 0x3c06, 0x1011, 0xe206, 0xb7df, 0x9715, 0x83e8,
+ 0x80d7, 0x8e48, 0xaa7b, 0xd1c7, 0xff14, 0x2c7e, 0x5423, 0x70dc,
+ 0x7eef, 0x7c88, 0x69f8, 0x49a6, 0x1fc5, 0xf1c5, 0xc59d, 0xa10a,
+ 0x88c9, 0x8002, 0x87d8, 0x9f46, 0xc343, 0xef21, 0x1d30, 0x4775,
+ 0x6874, 0x7be4, 0x7f40, 0x7217, 0x561f, 0x2efa, 0x01bc, 0xd445,
+ 0xac7a, 0x8f86, 0x812c, 0x8348, 0x9594, 0xb5b1, 0xdf72, 0x0d6c,
+ 0x39aa, 0x5e6b, 0x76ea, 0x7ffb, 0x786f, 0x6141, 0x3d74, 0x11ac,
+ 0xe39b, 0xb938, 0x9805, 0x8451, 0x80ab, 0x8d8b, 0xa947, 0xd045,
+ 0xfd75, 0x2af8, 0x52e8, 0x7016, 0x7eb7, 0x7ce6, 0x6ade, 0x4af8,
+ 0x2156, 0xf362, 0xc710, 0xa222, 0x8963, 0x8009, 0x874b, 0x9e38,
+ 0xc1d6, 0xed86, 0x1b9b, 0x461b, 0x6782, 0x7b79, 0x7f6a, 0x72d1,
+ 0x5751, 0x307b, 0x035b, 0xd5cc, 0xadb6, 0x904f, 0x8167, 0x82ed,
+ 0x94b0, 0xb460, 0xdde1, 0x0bcf, 0x3836, 0x5d50, 0x764e, 0x7ff1,
+ 0x78f9, 0x624d, 0x3edf, 0x1347, 0xe530, 0xba93, 0x98f9, 0x84be,
+ 0x8083, 0x8cd4, 0xa818, 0xcec5, 0xfbd5, 0x2970, 0x51aa, 0x6f4b,
+ 0x7e7a, 0x7d3e, 0x6bc1, 0x4c47, 0x22e7, 0xf500, 0xc885, 0xa33e,
+ 0x8a02, 0x8015, 0x86c4, 0x9d2e, 0xc06d, 0xebeb, 0x1a04, 0x44be,
+ 0x668b, 0x7b09, 0x7f8f, 0x7386, 0x587f, 0x31fb, 0x04fa, 0xd755,
+ 0xaef6, 0x911c, 0x81a7, 0x8298, 0x93d0, 0xb312, 0xdc51, 0x0a31,
+ 0x36bf, 0x5c32, 0x75ad, 0x7fe2, 0x797e, 0x6355, 0x4047, 0x14e2,
+ 0xe6c7, 0xbbf2, 0x99f2, 0x8531, 0x8060, 0x8c21, 0xa6ec, 0xcd46,
+ 0xfa36, 0x27e6, 0x5069, 0x6e7b, 0x7e37, 0x7d91, 0x6c9f, 0x4d93,
+ 0x2476, 0xf69e, 0xc9fd, 0xa45f, 0x8aa5, 0x8027, 0x8641, 0x9c28,
+ 0xbf05, 0xea51, 0x186d, 0x435e, 0x6590, 0x7a94, 0x7faf, 0x7437,
+ 0x59a9, 0x3378, 0x0699, 0xd8e0, 0xb039, 0x91ee, 0x81ec, 0x8247,
+ 0x92f4, 0xb1c8, 0xdac3, 0x0893, 0x3547, 0x5b10, 0x7507, 0x7fce,
+ 0x79ff, 0x6459, 0x41ad, 0x167b, 0xe85f, 0xbd53, 0x9aee, 0x85a8,
+ 0x8043, 0x8b73, 0xa5c3, 0xcbca, 0xf897, 0x265a, 0x4f24, 0x6da7,
+ 0x7df0, 0x7ddf, 0x6d78, 0x4edc, 0x2603, 0xf83c, 0xcb77, 0xa583,
+ 0x8b4d, 0x803e, 0x85c3, 0x9b26, 0xbda1, 0xe8b8, 0x16d5, 0x41fb,
+ 0x6492, 0x7a1a, 0x7fc9, 0x74e2, 0x5ad0, 0x34f4, 0x0838, 0xda6c,
+ 0xb180, 0x92c4, 0x8236, 0x81fc, 0x921d, 0xb081, 0xd937, 0x06f4,
+ 0x33cc, 0x59ea, 0x745d, 0x7fb5, 0x7a7a, 0x6559, 0x4311, 0x1814,
+ 0xe9f8, 0xbeb7, 0x9bef, 0x8625, 0x802b, 0x8ac9, 0xa49e, 0xca50,
+ 0xf6f9, 0x24cd, 0x4ddc, 0x6ccf, 0x7da3, 0x7e28, 0x6e4d, 0x5022,
+ 0x278f, 0xf9db, 0xccf3, 0xa6aa, 0x8bfa, 0x805a, 0x854a, 0x9a29,
+ 0xbc3f, 0xe720, 0x153c, 0x4096, 0x638f, 0x799b, 0x7fdf, 0x7589,
+ 0x5bf3, 0x366d, 0x09d6, 0xdbfa, 0xb2ca, 0x939f, 0x8286, 0x81b5,
+ 0x914a, 0xaf3d, 0xd7ab, 0x0555, 0x324f, 0x58c1, 0x73ad, 0x7f96,
+ 0x7af0, 0x6655, 0x4471, 0x19ab, 0xeb91, 0xc01e, 0x9cf5, 0x86a7,
+ 0x8019, 0x8a25, 0xa37d, 0xc8d8, 0xf55b, 0x233e, 0x4c90, 0x6bf2,
+ 0x7d51, 0x7e6c, 0x6f1e, 0x5164, 0x2919, 0xfb7a, 0xce71, 0xa7d6,
+ 0x8cac, 0x807b, 0x84d7, 0x992f, 0xbae0, 0xe589, 0x13a1, 0x3f2e,
+ 0x6287, 0x7917, 0x7fef, 0x762b, 0x5d12, 0x37e4, 0x0b74, 0xdd89,
+ 0xb417, 0x947e, 0x82da, 0x8174, 0x907c, 0xadfc, 0xd622, 0x03b6,
+ 0x30d0, 0x5793, 0x72f9, 0x7f73, 0x7b61, 0x674c, 0x45cf, 0x1b42,
+ 0xed2c, 0xc187, 0x9dfe, 0x872d, 0x800b, 0x8985, 0xa260, 0xc762,
+ 0xf3bd, 0x21ae, 0x4b42, 0x6b10, 0x7cfa, 0x7eaa, 0x6fea, 0x52a3,
+ 0x2aa2, 0xfd1a, 0xcff1, 0xa905, 0x8d63, 0x80a1, 0x8468, 0x983a,
+ 0xb984, 0xe3f4, 0x1207, 0x3dc4, 0x617c, 0x788e, 0x7ff9, 0x76c9,
+ 0x5e2d, 0x3958, 0x0d12, 0xdf1a, 0xb567, 0x9562, 0x8334, 0x8139,
+ 0x8fb2, 0xacbf, 0xd49a, 0x0217, 0x2f4f, 0x5663, 0x7240, 0x7f49,
+ 0x7bcd, 0x683f, 0x4729, 0x1cd7, 0xeec7, 0xc2f3, 0x9f0b, 0x87b9,
+ 0x8003, 0x88eb, 0xa147, 0xc5ee, 0xf220, 0x201d, 0x49f0, 0x6a2b,
+ 0x7c9d, 0x7ee3, 0x70b1, 0x53de, 0x2c29, 0xfeb9, 0xd173, 0xaa37,
+ 0x8e1e, 0x80cd, 0x83ff, 0x9749, 0xb82a, 0xe25f, 0x106b, 0x3c56,
+ 0x606d, 0x7800, 0x7fff, 0x7761, 0x5f44, 0x3aca, 0x0eaf, 0xe0ac,
+ 0xb6ba, 0x964a, 0x8393, 0x8102, 0x8eed, 0xab85, 0xd314, 0x0077,
+ 0x2dcc, 0x552e, 0x7183, 0x7f1b, 0x7c34, 0x692e, 0x4881, 0x1e6b,
+ 0xf063, 0xc461, 0xa01c, 0x8849, 0x8001, 0x8855, 0xa031, 0xc47d,
+ 0xf083, 0x1e8a, 0x489c, 0x6940, 0x7c3c, 0x7f17, 0x7174, 0x5516,
+ 0x2dae, 0x0057, 0xd2f6, 0xab6d, 0x8ede, 0x80fe, 0x839a, 0x965c,
+ 0xb6d4, 0xe0cb, 0x0ecf, 0x3ae7, 0x5f5a, 0x776c, 0x7fff, 0x77f4,
+ 0x6058, 0x3c3a, 0x104b, 0xe240, 0xb810, 0x9736, 0x83f7, 0x80d1,
+ 0x8e2d, 0xaa4f, 0xd190, 0xfed9, 0x2c47, 0x53f7, 0x70c0, 0x7ee7,
+ 0x7c96, 0x6a19, 0x49d6, 0x1ffe, 0xf200, 0xc5d2, 0xa131, 0x88df,
+ 0x8003, 0x87c4, 0x9f20, 0xc30f, 0xeee7, 0x1cf6, 0x4744, 0x6852,
+ 0x7bd5, 0x7f46, 0x7232, 0x564b, 0x2f31, 0x01f7, 0xd47c, 0xaca7,
+ 0x8fa3, 0x8134, 0x833b, 0x9574, 0xb581, 0xdf39, 0x0d32, 0x3975,
+ 0x5e43, 0x76d5, 0x7ffa, 0x7883, 0x6167, 0x3da8, 0x11e7, 0xe3d4,
+ 0xb969, 0x9827, 0x8460, 0x80a5, 0x8d71, 0xa91c, 0xd00e, 0xfd3a,
+ 0x2ac0, 0x52bb, 0x6ff9, 0x7eaf, 0x7cf3, 0x6aff, 0x4b28, 0x2190,
+ 0xf39d, 0xc745, 0xa24a, 0x8979, 0x800b, 0x8738, 0x9e12, 0xc1a3,
+ 0xed4c, 0x1b61, 0x45e9, 0x675f, 0x7b6a, 0x7f70, 0x72eb, 0x577c,
+ 0x30b2, 0x0396, 0xd604, 0xade4, 0x906c, 0x8170, 0x82e1, 0x9490,
+ 0xb430, 0xdda8, 0x0b94, 0x3800, 0x5d28, 0x7638, 0x7ff0, 0x790c,
+ 0x6273, 0x3f12, 0x1382, 0xe56a, 0xbac5, 0x991c, 0x84ce, 0x807e,
+ 0x8cba, 0xa7ed, 0xce8e, 0xfb9a, 0x2938, 0x517d, 0x6f2e, 0x7e71,
+ 0x7d4a, 0x6be1, 0x4c77, 0x2320, 0xf53b, 0xc8bb, 0xa367, 0x8a19,
+ 0x8018, 0x86b1, 0x9d09, 0xc039, 0xebb1, 0x19ca, 0x448c, 0x6668,
+ 0x7af9, 0x7f94, 0x73a0, 0x58aa, 0x3231, 0x0535, 0xd78d, 0xaf24,
+ 0x913a, 0x81b0, 0x828c, 0x93b0, 0xb2e3, 0xdc19, 0x09f6, 0x368a,
+ 0x5c09, 0x7596, 0x7fe0, 0x7991, 0x637a, 0x407a, 0x151c, 0xe701,
+ 0xbc24, 0x9a15, 0x8541, 0x805c, 0x8c08, 0xa6c1, 0xcd10, 0xf9fb,
+ 0x27ae, 0x503b, 0x6e5e, 0x7e2d, 0x7d9d, 0x6cbe, 0x4dc2, 0x24ae,
+ 0xf6d9, 0xca33, 0xa488, 0x8abd, 0x802a, 0x862f, 0x9c03, 0xbed2,
+ 0xea17, 0x1833, 0x432c, 0x656c, 0x7a83, 0x7fb3, 0x744f, 0x59d3,
+ 0x33ae, 0x06d4, 0xd918, 0xb068, 0x920c, 0x81f6, 0x823c, 0x92d5,
+ 0xb199, 0xda8b, 0x0858, 0x3511, 0x5ae6, 0x74ef, 0x7fcb, 0x7a10,
+ 0x647e, 0x41e0, 0x16b5, 0xe899, 0xbd85, 0x9b13, 0x85ba, 0x8040,
+ 0x8b5a, 0xa599, 0xcb94, 0xf85c, 0x2622, 0x4ef5, 0x6d89, 0x7de5,
+ 0x7dea, 0x6d97, 0x4f0b, 0x263c, 0xf877, 0xcbad, 0xa5ac, 0x8b66,
+ 0x8041, 0x85b2, 0x9b02, 0xbd6e, 0xe87e, 0x169b, 0x41c9, 0x646d,
+ 0x7a08, 0x7fcd, 0x74fa, 0x5af9, 0x3529, 0x0873, 0xdaa5, 0xb1af,
+ 0x92e3, 0x8241, 0x81f1, 0x91fe, 0xb053, 0xd8fe, 0x06b9, 0x3396,
+ 0x59c0, 0x7444, 0x7fb1, 0x7a8b, 0x657d, 0x4343, 0x184e, 0xea32,
+ 0xbeea, 0x9c14, 0x8637, 0x8028, 0x8ab2, 0xa475, 0xca1a, 0xf6be,
+ 0x2494, 0x4dad, 0x6cb0, 0x7d97, 0x7e32, 0x6e6b, 0x5050, 0x27c7,
+ 0xfa16, 0xcd29, 0xa6d5, 0x8c13, 0x805e, 0x853a, 0x9a05, 0xbc0d,
+ 0xe6e7, 0x1501, 0x4063, 0x6369, 0x7988, 0x7fe1, 0x75a1, 0x5c1c,
+ 0x36a2, 0x0a11, 0xdc33, 0xb2f9, 0x93bf, 0x8291, 0x81ac, 0x912c,
+ 0xaf0f, 0xd773, 0x051a, 0x3218, 0x5896, 0x7394, 0x7f92, 0x7b00,
+ 0x6678, 0x44a3, 0x19e5, 0xebcc, 0xc051, 0x9d1a, 0x86b9, 0x8017,
+ 0x8a0e, 0xa354, 0xc8a2, 0xf520, 0x2306, 0x4c61, 0x6bd2, 0x7d45,
+ 0x7e75, 0x6f3b, 0x5191, 0x2951, 0xfbb5, 0xcea7, 0xa800, 0x8cc6,
+ 0x8080, 0x84c7, 0x990c, 0xbaae, 0xe550, 0x1367, 0x3efb, 0x6262,
+ 0x7904, 0x7ff0, 0x7642, 0x5d3a, 0x3819, 0x0baf, 0xddc2, 0xb446,
+ 0x949e, 0x82e7, 0x816c, 0x905f, 0xadcf, 0xd5ea, 0x037b, 0x3099,
+ 0x5768, 0x72df, 0x7f6d, 0x7b71, 0x676f, 0x4600, 0x1b7b, 0xed66,
+ 0xc1ba, 0x9e24, 0x8741, 0x800a, 0x896f, 0xa238, 0xc72d, 0xf382,
+ 0x2175, 0x4b12, 0x6af0, 0x7ced, 0x7eb3, 0x7006, 0x52d0, 0x2ada,
+ 0xfd55, 0xd027, 0xa930, 0x8d7d, 0x80a7, 0x8459, 0x9817, 0xb952,
+ 0xe3ba, 0x11cc, 0x3d90, 0x6156, 0x787a, 0x7ffa, 0x76df, 0x5e55,
+ 0x398d, 0x0d4d, 0xdf53, 0xb597, 0x9583, 0x8341, 0x8131, 0x8f96,
+ 0xac92, 0xd463, 0x01dc, 0x2f18, 0x5637, 0x7226, 0x7f43, 0x7bdc,
+ 0x6861, 0x475a, 0x1d11, 0xef02, 0xc327, 0x9f32, 0x87cd, 0x8003,
+ 0x88d5, 0xa11f, 0xc5ba, 0xf1e5, 0x1fe4, 0x49c0, 0x6a0a, 0x7c90,
+ 0x7eeb, 0x70cd, 0x540b, 0x2c60, 0xfef4, 0xd1aa, 0xaa63, 0x8e39,
+ 0x80d4, 0x83f0, 0x9727, 0xb7f9, 0xe225, 0x1030, 0x3c22, 0x6046,
+ 0x77eb, 0x7fff, 0x7776, 0x5f6c, 0x3aff, 0x0eea, 0xe0e6, 0xb6ea,
+ 0x966b, 0x83a1, 0x80fb, 0x8ed1, 0xab59, 0xd2dd, 0x003c, 0x2d95,
+ 0x5502, 0x7167, 0x7f14, 0x7c42, 0x6950, 0x48b2, 0x1ea4, 0xf09e,
+ 0xc495, 0xa043, 0x885e, 0x8001, 0x8840, 0xa00a, 0xc449, 0xf048,
+ 0x1e51, 0x486b, 0x691f, 0x7c2e, 0x7f1e, 0x718f, 0x5543, 0x2de5,
+ 0x0092, 0xd32e, 0xab9a, 0x8efa, 0x8105, 0x838c, 0x963b, 0xb6a4,
+ 0xe092, 0x0e94, 0x3ab2, 0x5f32, 0x7757, 0x7fff, 0x7809, 0x607f,
+ 0x3c6e, 0x1086, 0xe279, 0xb841, 0x9758, 0x8405, 0x80ca, 0x8e12,
+ 0xaa23, 0xd159, 0xfe9e, 0x2c0f, 0x53ca, 0x70a4, 0x7ee0, 0x7ca3,
+ 0x6a3a, 0x4a06, 0x2037, 0xf23b, 0xc607, 0xa159, 0x88f5, 0x8004,
+ 0x87b0, 0x9ef9, 0xc2db, 0xeeac, 0x1cbd, 0x4713, 0x682f, 0x7bc6,
+ 0x7f4c, 0x724c, 0x5677, 0x2f68, 0x0232, 0xd4b4, 0xacd4, 0x8fbf,
+ 0x813c, 0x832e, 0x9553, 0xb551, 0xdf00, 0x0cf7, 0x3940, 0x5e1b,
+ 0x76bf, 0x7ff9, 0x7897, 0x618e, 0x3ddb, 0x1221, 0xe40e, 0xb99a,
+ 0x984a, 0x846f, 0x809f, 0x8d57, 0xa8f1, 0xcfd7, 0xfcfe, 0x2a88,
+ 0x528e, 0x6fdd, 0x7ea6, 0x7cff, 0x6b1f, 0x4b58, 0x21c9, 0xf3d8,
+ 0xc77a, 0xa273, 0x8990, 0x800c, 0x8724, 0x9dec, 0xc16f, 0xed11,
+ 0x1b27, 0x45b8, 0x673c, 0x7b5a, 0x7f75, 0x7305, 0x57a7, 0x30e9,
+ 0x03d1, 0xd63c, 0xae11, 0x9089, 0x8179, 0x82d4, 0x9470, 0xb401,
+ 0xdd6f, 0x0b59, 0x37cb, 0x5cff, 0x7621, 0x7fee, 0x7920, 0x6299,
+ 0x3f46, 0x13bc, 0xe5a4, 0xbaf7, 0x993f, 0x84de, 0x8079, 0x8ca0,
+ 0xa7c2, 0xce58, 0xfb5f, 0x2900, 0x514f, 0x6f10, 0x7e67, 0x7d56,
+ 0x6c00, 0x4ca6, 0x2359, 0xf576, 0xc8f0, 0xa390, 0x8a30, 0x801a,
+ 0x869e, 0x9ce3, 0xc006, 0xeb77, 0x1991, 0x445a, 0x6644, 0x7ae8,
+ 0x7f99, 0x73b9, 0x58d4, 0x3268, 0x0570, 0xd7c5, 0xaf52, 0x9157,
+ 0x81ba, 0x8280, 0x9391, 0xb2b4, 0xdbe0, 0x09bb, 0x3654, 0x5be0,
+ 0x757f, 0x7fdd, 0x79a3, 0x63a0, 0x40ae, 0x1556, 0xe73b, 0xbc56,
+ 0x9a39, 0x8552, 0x8058, 0x8bef, 0xa697, 0xccda, 0xf9c0, 0x2775,
+ 0x500c, 0x6e40, 0x7e23, 0x7da8, 0x6cdd, 0x4df1, 0x24e7, 0xf714,
+ 0xca68, 0xa4b1, 0x8ad4, 0x802d, 0x861d, 0x9bdf, 0xbea0, 0xe9dd,
+ 0x17f9, 0x42f9, 0x6548, 0x7a72, 0x7fb7, 0x7468, 0x59fd, 0x33e4,
+ 0x070f, 0xd950, 0xb096, 0x922a, 0x8200, 0x8231, 0x92b6, 0xb16b,
+ 0xda52, 0x081d, 0x34db, 0x5abd, 0x74d7, 0x7fc8, 0x7a22, 0x64a2,
+ 0x4213, 0x16ef, 0xe8d3, 0xbdb8, 0x9b37, 0x85cb, 0x803c, 0x8b42,
+ 0xa56f, 0xcb5e, 0xf821, 0x25e9, 0x4ec7, 0x6d6a, 0x7dda, 0x7df4,
+ 0x6db5, 0x4f39, 0x2674, 0xf8b2, 0xcbe3, 0xa5d6, 0x8b7e, 0x8045,
+ 0x85a0, 0x9ade, 0xbd3c, 0xe844, 0x1660, 0x4196, 0x6448, 0x79f6,
+ 0x7fd0, 0x7512, 0x5b23, 0x355f, 0x08ae, 0xdadd, 0xb1dd, 0x9302,
+ 0x824c, 0x81e7, 0x91e0, 0xb024, 0xd8c6, 0x067e, 0x3360, 0x5996,
+ 0x742b, 0x7fad, 0x7a9c, 0x65a1, 0x4375, 0x1888, 0xea6c, 0xbf1d,
+ 0x9c39, 0x8649, 0x8026, 0x8a9a, 0xa44c, 0xc9e4, 0xf683, 0x245c,
+ 0x4d7e, 0x6c90, 0x7d8c, 0x7e3c, 0x6e89, 0x507e, 0x2800, 0xfa51,
+ 0xcd5f, 0xa6ff, 0x8c2c, 0x8063, 0x8529, 0x99e1, 0xbbdb, 0xe6ad,
+ 0x14c7, 0x4030, 0x6344, 0x7976, 0x7fe4, 0x75b8, 0x5c45, 0x36d8,
+ 0x0a4c, 0xdc6c, 0xb328, 0x93de, 0x829d, 0x81a2, 0x910f, 0xaee1,
+ 0xd73b, 0x04df, 0x31e2, 0x586b, 0x737b, 0x7f8d, 0x7b11, 0x669b,
+ 0x44d5, 0x1a1f, 0xec06, 0xc084, 0x9d40, 0x86cc, 0x8014, 0x89f7,
+ 0xa32c, 0xc86d, 0xf4e5, 0x22cd, 0x4c31, 0x6bb2, 0x7d38, 0x7e7e,
+ 0x6f58, 0x51bf, 0x2989, 0xfbf0, 0xcede, 0xa82b, 0x8ce0, 0x8085,
+ 0x84b7, 0x98e9, 0xba7c, 0xe516, 0x132d, 0x3ec7, 0x623c, 0x78f0,
+ 0x7ff2, 0x7659, 0x5d63, 0x384e, 0x0bea, 0xddfb, 0xb476, 0x94bf,
+ 0x82f3, 0x8163, 0x9042, 0xada2, 0xd5b2, 0x0340, 0x3062, 0x573d,
+ 0x72c5, 0x7f67, 0x7b80, 0x6792, 0x4632, 0x1bb5, 0xeda1, 0xc1ee,
+ 0x9e4a, 0x8754, 0x8009, 0x8959, 0xa210, 0xc6f8, 0xf347, 0x213c,
+ 0x4ae2, 0x6acf, 0x7ce0, 0x7ebb, 0x7023, 0x52fd, 0x2b11, 0xfd90,
+ 0xd05e, 0xa95b, 0x8d98, 0x80ad, 0x844a, 0x97f5, 0xb921, 0xe380,
+ 0x1191, 0x3d5c, 0x612f, 0x7866, 0x7ffb, 0x76f4, 0x5e7d, 0x39c2,
+ 0x0d87, 0xdf8c, 0xb5c7, 0x95a4, 0x834e, 0x8129, 0x8f79, 0xac65,
+ 0xd42b, 0x01a1, 0x2ee1, 0x560b, 0x720b, 0x7f3d, 0x7beb, 0x6884,
+ 0x478c, 0x1d4a, 0xef3c, 0xc35b, 0x9f58, 0x87e1, 0x8002, 0x88bf,
+ 0xa0f7, 0xc585, 0xf1aa, 0x1faa, 0x4990, 0x69e8, 0x7c82, 0x7ef3,
+ 0x70e9, 0x5438, 0x2c98, 0xff2f, 0xd1e1, 0xaa8f, 0x8e54, 0x80db,
+ 0x83e2, 0x9705, 0xb7c9, 0xe1ec, 0x0ff6, 0x3bee, 0x601f, 0x77d6,
+ 0x7fff, 0x778b, 0x5f93, 0x3b33, 0x0f24, 0xe11f, 0xb71b, 0x968d,
+ 0x83af, 0x80f3, 0x8eb6, 0xab2c, 0xd2a6, 0x0001, 0x2d5d, 0x54d6,
+ 0x714c, 0x7f0d, 0x7c50, 0x6971, 0x48e3, 0x1ede, 0xf0d9, 0xc4ca,
+ 0xa06b, 0x8873, 0x8001, 0x882b, 0x9fe3, 0xc415, 0xf00e, 0x1e17,
+ 0x483a, 0x68fd, 0x7c1f, 0x7f25, 0x71aa, 0x556f, 0x2e1c, 0x00ce,
+ 0xd365, 0xabc6, 0x8f16, 0x810d, 0x837f, 0x9619, 0xb673, 0xe059,
+ 0x0e59, 0x3a7e, 0x5f0b, 0x7742, 0x7ffe, 0x781d, 0x60a6, 0x3ca2,
+ 0x10c0, 0xe2b3, 0xb872, 0x977a, 0x8414, 0x80c4, 0x8df7, 0xa9f7,
+ 0xd122, 0xfe63, 0x2bd8, 0x539d, 0x7088, 0x7ed8, 0x7cb1, 0x6a5b,
+ 0x4a36, 0x2070, 0xf275, 0xc63b, 0xa181, 0x890a, 0x8005, 0x879b,
+ 0x9ed3, 0xc2a7, 0xee72, 0x1c83, 0x46e2, 0x680d, 0x7bb7, 0x7f52,
+ 0x7267, 0x56a2, 0x2f9f, 0x026d, 0xd4ec, 0xad01, 0x8fdb, 0x8145,
+ 0x8321, 0x9532, 0xb521, 0xdec7, 0x0cbc, 0x390b, 0x5df3, 0x76a8,
+ 0x7ff7, 0x78aa, 0x61b4, 0x3e0f, 0x125c, 0xe448, 0xb9cc, 0x986c,
+ 0x847f, 0x8099, 0x8d3c, 0xa8c5, 0xcfa1, 0xfcc3, 0x2a51, 0x5261,
+ 0x6fc0, 0x7e9e, 0x7d0c, 0x6b40, 0x4b87, 0x2202, 0xf413, 0xc7af,
+ 0xa29b, 0x89a6, 0x800e, 0x8711, 0x9dc6, 0xc13c, 0xecd7, 0x1aed,
+ 0x4586, 0x6719, 0x7b4a, 0x7f7a, 0x731f, 0x57d2, 0x311f, 0x040c,
+ 0xd674, 0xae3f, 0x90a6, 0x8182, 0x82c8, 0x9450, 0xb3d1, 0xdd36,
+ 0x0b1e, 0x3796, 0x5cd7, 0x760a, 0x7fec, 0x7933, 0x62be, 0x3f79,
+ 0x13f7, 0xe5de, 0xbb28, 0x9963, 0x84ee, 0x8074, 0x8c87, 0xa797,
+ 0xce21, 0xfb24, 0x28c8, 0x5121, 0x6ef3, 0x7e5e, 0x7d62, 0x6c20,
+ 0x4cd5, 0x2391, 0xf5b1, 0xc925, 0xa3b9, 0x8a47, 0x801c, 0x868b,
+ 0x9cbe, 0xbfd3, 0xeb3c, 0x1957, 0x4428, 0x6621, 0x7ad8, 0x7f9d,
+ 0x73d2, 0x58ff, 0x329e, 0x05ab, 0xd7fd, 0xaf80, 0x9175, 0x81c4,
+ 0x8275, 0x9371, 0xb285, 0xdba7, 0x0980, 0x361f, 0x5bb7, 0x7567,
+ 0x7fdb, 0x79b6, 0x63c5, 0x40e1, 0x1591, 0xe775, 0xbc88, 0x9a5d,
+ 0x8563, 0x8053, 0x8bd6, 0xa66d, 0xcca3, 0xf985, 0x273d, 0x4fde,
+ 0x6e22, 0x7e19, 0x7db3, 0x6cfc, 0x4e20, 0x2520, 0xf74f, 0xca9e,
+ 0xa4db, 0x8aec, 0x8030, 0x860b, 0x9bba, 0xbe6d, 0xe9a3, 0x17bf,
+ 0x42c7, 0x6524, 0x7a61, 0x7fbb, 0x7481, 0x5a27, 0x341b, 0x074a,
+ 0xd989, 0xb0c4, 0x9249, 0x820b, 0x8226, 0x9297, 0xb13c, 0xda1a,
+ 0x07e2, 0x34a5, 0x5a93, 0x74bf, 0x7fc4, 0x7a34, 0x64c7, 0x4245,
+ 0x172a, 0xe90d, 0xbdeb, 0x9b5c, 0x85dd, 0x8038, 0x8b2a, 0xa546,
+ 0xcb28, 0xf7e6, 0x25b1, 0x4e98, 0x6d4c, 0x7dcf, 0x7dff, 0x6dd4,
+ 0x4f67, 0x26ac, 0xf8ed, 0xcc19, 0xa600, 0x8b97, 0x8049, 0x858f,
+ 0x9aba, 0xbd09, 0xe80a, 0x1626, 0x4163, 0x6424, 0x79e4, 0x7fd3,
+ 0x752a, 0x5b4c, 0x3595, 0x08e9, 0xdb16, 0xb20c, 0x9321, 0x8257,
+ 0x81dd, 0x91c2, 0xaff6, 0xd88e, 0x0643, 0x3329, 0x596c, 0x7412,
+ 0x7fa9, 0x7aad, 0x65c5, 0x43a7, 0x18c2, 0xeaa6, 0xbf50, 0x9c5e,
+ 0x865c, 0x8023, 0x8a83, 0xa422, 0xc9af, 0xf648, 0x2423, 0x4d4f,
+ 0x6c71, 0x7d80, 0x7e46, 0x6ea7, 0x50ac, 0x2838, 0xfa8c, 0xcd95,
+ 0xa72a, 0x8c46, 0x8067, 0x8518, 0x99be, 0xbba9, 0xe673, 0x148d,
+ 0x3ffd, 0x631f, 0x7963, 0x7fe6, 0x75cf, 0x5c6e, 0x370d, 0x0a87,
+ 0xdca4, 0xb357, 0x93fe, 0x82a9, 0x8199, 0x90f1, 0xaeb4, 0xd703,
+ 0x04a4, 0x31ab, 0x5840, 0x7361, 0x7f88, 0x7b21, 0x66bf, 0x4507,
+ 0x1a59, 0xec41, 0xc0b7, 0x9d65, 0x86df, 0x8012, 0x89e0, 0xa303,
+ 0xc838, 0xf4aa, 0x2294, 0x4c02, 0x6b92, 0x7d2c, 0x7e87, 0x6f75,
+ 0x51ec, 0x29c1, 0xfc2c, 0xcf14, 0xa856, 0x8cfa, 0x808b, 0x84a7,
+ 0x98c6, 0xba4b, 0xe4dc, 0x12f2, 0x3e94, 0x6216, 0x78dd, 0x7ff4,
+ 0x766f, 0x5d8b, 0x3883, 0x0c25, 0xde34, 0xb4a6, 0x94df, 0x8300,
+ 0x815a, 0x9025, 0xad74, 0xd57b, 0x0305, 0x302c, 0x5712, 0x72ab,
+ 0x7f62, 0x7b90, 0x67b4, 0x4663, 0x1bef, 0xeddb, 0xc222, 0x9e70,
+ 0x8768, 0x8007, 0x8943, 0xa1e8, 0xc6c3, 0xf30c, 0x2103, 0x4ab2,
+ 0x6aaf, 0x7cd3, 0x7ec3, 0x703f, 0x532a, 0x2b49, 0xfdcb, 0xd095,
+ 0xa987, 0x8db2, 0x80b3, 0x843b, 0x97d2, 0xb8f0, 0xe347, 0x1157,
+ 0x3d28, 0x6109, 0x7852, 0x7ffc, 0x770a, 0x5ea5, 0x39f7, 0x0dc2,
+ 0xdfc6, 0xb5f7, 0x95c4, 0x835c, 0x8121, 0x8f5d, 0xac39, 0xd3f4,
+ 0x0165, 0x2eaa, 0x55df, 0x71f0, 0x7f36, 0x7bfa, 0x68a6, 0x47bd,
+ 0x1d84, 0xef77, 0xc38f, 0x9f7f, 0x87f6, 0x8001, 0x88aa, 0xa0d0,
+ 0xc551, 0xf16f, 0x1f71, 0x495f, 0x69c7, 0x7c74, 0x7efa, 0x7105,
+ 0x5464, 0x2ccf, 0xff6a, 0xd218, 0xaabb, 0x8e6f, 0x80e1, 0x83d3,
+ 0x96e3, 0xb798, 0xe1b2, 0x0fbb, 0x3bba, 0x5ff8, 0x77c1, 0x7fff,
+ 0x77a0, 0x5fbb, 0x3b68, 0x0f5f, 0xe158, 0xb74b, 0x96ae, 0x83bd,
+ 0x80ec, 0x8e9a, 0xab00, 0xd26f, 0xffc7, 0x2d26, 0x54aa, 0x7130,
+ 0x7f06, 0x7c5e, 0x6993, 0x4913, 0x1f17, 0xf113, 0xc4fe, 0xa092,
+ 0x8889, 0x8001, 0x8816, 0x9fbc, 0xc3e1, 0xefd3, 0x1dde, 0x4809,
+ 0x68db, 0x7c11, 0x7f2c, 0x71c5, 0x559b, 0x2e53, 0x0109, 0xd39d,
+ 0xabf3, 0x8f31, 0x8115, 0x8371, 0x95f8, 0xb643, 0xe01f, 0x0e1e,
+ 0x3a49, 0x5ee3, 0x772c, 0x7ffd, 0x7832, 0x60cc, 0x3cd6, 0x10fb,
+ 0xe2ec, 0xb8a3, 0x979d, 0x8423, 0x80bd, 0x8ddc, 0xa9cb, 0xd0eb,
+ 0xfe28, 0x2ba0, 0x5370, 0x706c, 0x7ed0, 0x7cbe, 0x6a7b, 0x4a67,
+ 0x20aa, 0xf2b0, 0xc670, 0xa1a9, 0x8920, 0x8006, 0x8787, 0x9eac,
+ 0xc273, 0xee37, 0x1c49, 0x46b0, 0x67eb, 0x7ba8, 0x7f58, 0x7281,
+ 0x56ce, 0x2fd6, 0x02a8, 0xd523, 0xad2e, 0x8ff8, 0x814d, 0x8314,
+ 0x9512, 0xb4f1, 0xde8e, 0x0c81, 0x38d6, 0x5dca, 0x7692, 0x7ff6,
+ 0x78be, 0x61da, 0x3e43, 0x1296, 0xe481, 0xb9fd, 0x988f, 0x848e,
+ 0x8093, 0x8d22, 0xa89a, 0xcf6a, 0xfc88, 0x2a19, 0x5234, 0x6fa3,
+ 0x7e95, 0x7d19, 0x6b60, 0x4bb7, 0x223b, 0xf44e, 0xc7e4, 0xa2c3,
+ 0x89bd, 0x8010, 0x86fe, 0x9da0, 0xc108, 0xec9c, 0x1ab4, 0x4555
+};
+
+float32_t transform_fft_f32_inputs[TRANSFORM_MAX_FFT_LEN * 2] =
+{
+ 43.0264275639, -17.0525215570, -94.8488973910, -8.1924989580, 7.2830326091, 66.8368719314, 33.9778190671, 117.8652289772,
+ -129.6077797465, -14.6420815368, 18.0239223278, 20.6760530292, 55.0375037651, 1.8674609862, -85.6534302408, -33.5750364909,
+ 29.2110949614, 110.4727049460, -94.1914619387, -1.4084169343, 83.5181653041, 47.3073514127, -13.3420621181, 30.3389699104,
+ 12.1188124277, 100.9730921941, -114.0146362390, -77.5823200409, 37.2019034618, 40.0026301128, -58.3387276630, -34.9472398600,
+ -5.1169678311, -87.7660091118, -150.5888601131, 56.0349370503, 50.2168884079, -74.2313236767, 22.3648603560, -6.8676387051,
+ 74.8957303680, -90.1292012823, -55.1436241586, -66.6732976100, -6.7918147615, 7.7612697081, 35.7892605979, -20.0470508830,
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+ 70.3534390616, 71.5844311614, 4.0715727994, 25.4390606947, -51.0777668722, 138.3617611366, -34.2478029347, -58.8492260984,
+ -108.6623124843, 58.3034938571, -36.9304647333, 116.5902412201, -24.4020501110, -74.7544840602, 67.7889120207, -9.1455389450,
+ -46.4456521441, 83.2551857934, -113.9346066504, 46.2851467498, -17.4102217179, 41.6989724702, -23.8829078702, 76.1395799790,
+ -27.1608730178, -133.8787483532, -59.9242635982, 120.5266415560, 124.9797395465, 35.5722660007, -20.2412573812, 20.5492611902,
+ -111.8745990845, 41.7389321101, 44.5758622786, 54.2189628306, -44.4745944890, -75.9761098966, 104.0472151578, 113.7219003284,
+ 33.0330354214, -6.0923562541, -14.8744671800, 62.5024055272, 3.7922184446, 1.1256712478, -30.2126827228, -83.4988699637,
+ -103.7060854897, -65.4982917403, 30.8897494352, 66.1124672663, 65.0983461952, -52.5486436649, -4.5556524541, -26.5924272500,
+ -94.1546367179, -0.3559369287, -45.0649519841, -68.1274094478, -7.0521865275, -5.6612786174, -12.5790011432, 51.2524661231,
+ -3.6515125298, 92.9598974936, -21.0468658542, -40.8243392179, -7.4342227950, 11.1119231703, 37.3371820746, 21.3179018153,
+ 50.2932980480, -24.1611515405, -41.7851721122, -24.8691439055, -28.3180388219, 121.1894536511, 15.7968116384, 17.9498027226,
+ -55.3386005430, -80.6689826830, 31.9394747713, -28.1978017432, -1.5538441529, -4.0360096323, 73.9611531119, 17.7253526010,
+ -24.8578563772, 18.4583438017, 75.2580204243, -13.6139802015, 24.6918362443, -63.0552815767, -4.0312608443, -14.8879121339,
+ -2.8237511683, -81.5024576341, -4.2344562157, 107.1587476255, -131.2910041645, -25.6467586377, 0.4733397655, 62.8634326464,
+ 63.1852609425, 16.5913941858, -96.6896044528, 81.2969911064, 18.2956425408, -81.6677471269, -39.2708721333, -34.3080597347,
+ 22.5610412882, 57.2574226391, 77.9308780964, -39.9342842346, 58.5581960994, -5.7939281526, 104.9927182940, -99.3837066580,
+ 25.9917768621, -32.1605915683, -30.4589523848, 64.8295771021, -28.2183758982, -37.9771330859, -178.0772548046, 84.2925125233,
+ 45.4981954662, 49.2815212900, -45.1224250038, -5.9322404186, -6.1309915876, 76.9070873365, -11.5475730308, 18.2569564924,
+ -124.4953563688, 53.8646820493, -40.0231506068, -74.3908746450, -63.2011642999, -18.9826189881, 69.7917580387, -34.8403308318,
+ -36.4625632706, 17.1934091336, -20.8063613141, -1.9067935434, 5.2259139474, 60.8368210348, 81.3087550974, -42.6679999668,
+ -95.5963552311, -115.2609753741, 11.1809831183, -48.3640194531, 75.1073797772, 30.8228127170, -15.0904157375, 11.0538529673,
+ 107.4505154927, -66.3486660110, -32.0311111189, 38.4346222125, 8.9422998706, -57.6098106212, 15.9132097612, -132.1845158340,
+ 36.1916704283, -10.5055186124, -87.5658217149, 107.8931306399, 96.0334082800, 53.7264664477, -72.0623965686, -1.9038197721,
+ 26.1152808779, 119.6235796272, 48.3325601149, 117.6457486801, 28.0275495741, -11.7030018715, 52.9236279862, 100.1176831736,
+ -83.2423151898, 7.5280868233, -15.3686195277, -5.3432329923, -27.9181052724, -64.4492860287, 129.7502751613, -82.3246020383,
+ 37.3256155504, 34.7298938660, -57.0561320806, -44.9581455455, 93.3481469867, -54.3803550243, 26.4501204966, 18.8116878139,
+ -74.4902220818, 15.4659232518, -49.1948332727, 34.0006040345, 56.7177639954, -28.8367897421, 83.8692564278, 35.6745892475,
+ -45.7509262432, 30.3970223242, 106.1786129556, -35.7843870107, 7.1339227808, 13.0894885560, 56.4666438735, -23.8687514544,
+ -111.5694112759, -58.7858061292, -61.2783887765, 44.1738302093, 54.7407844064, 14.3538652267, 108.5956394164, -22.3846808158,
+ 2.5449431771, 70.3512724427, 29.5403015688, -0.7212818796, 143.3497258886, -17.2553350633, -99.7681623907, 42.6913312311,
+ 35.7338157369, -54.6728371746, -38.0299088541, 10.1471440532, -124.7095236710, -190.8743243033, 139.7543496645, -42.2528776639,
+ 39.0975372290, 27.8686903911, 22.7337255980, 42.7990612235, -41.6771094483, -23.0843729437, 49.7020046877, 11.0018909876,
+ -16.5079644797, -158.2821637063, 42.1950179525, -30.4282660128, 67.9797563487, -53.8121334664, 52.8306609341, -5.2861803454,
+ 59.3808475761, 158.1836295178, -26.8953096767, 78.8646320997, -113.9365510474, -37.1949934282, 53.6970193167, -9.6523467804,
+ 7.7358952669, -74.6220593088, 107.4394203873, 17.2364088475, -36.5357935724, -23.9301386540, 17.8174243490, 14.1204969615,
+ -8.2599377000, 4.2743586584, -46.4363395746, -63.5670279031, 9.6872641411, 21.0630349930, 108.9834586896, -124.7597975398,
+ 29.4251821664, 23.8313097730, -40.8359610210, 91.9520219869, 95.7936525792, -109.5783337883, -60.1100153384, -19.9591228893,
+};
+
+/*--------------------------------------------------------------------------------*/
+/* FFT Lengths */
+/*--------------------------------------------------------------------------------*/
+
+/*
+ To change test parameter values add/remove values inside CURLY and update
+ the preceeding parameter to reflect the number of values inside CURLY.
+*/
+
+ARR_DESC_DEFINE(uint16_t,
+ transform_radix2_fftlens,
+ 7,
+ CURLY(
+ 16, 32, 64, 128, 256,
+ 512, 1024/*, 2048 , 4096 */));
+
+ARR_DESC_DEFINE(uint16_t,
+ transform_radix4_fftlens,
+ 4,
+ CURLY(
+ 16, 64, 256, 1024/* , 4096 */));
+
+ARR_DESC_DEFINE(uint16_t,
+ transform_rfft_fftlens,
+ 6,
+ CURLY(
+ 32, 64, 128, 256,
+ 512, 1024/*, 2048 , 4096, 8192*/));
+
+ARR_DESC_DEFINE(uint16_t,
+ transform_dct_fftlens,
+ 3,
+ CURLY(
+ 128, 512, 2048/*, 8192*/));
+
+ARR_DESC_DEFINE(uint16_t,
+ transform_rfft_fast_fftlens,
+ 7,
+ CURLY(
+ 32, 64, 128, 256,
+ 512, 1024, 2048));
+
+/*--------------------------------------------------------------------------------*/
+/* CFFT_F32 Structs */
+/*--------------------------------------------------------------------------------*/
+
+/* Uses radix2 lengths */
+ARR_DESC_DEFINE(const arm_cfft_instance_f32 *,
+ transform_cfft_f32_structs,
+ 5,
+ CURLY(
+ &arm_cfft_sR_f32_len16,
+ &arm_cfft_sR_f32_len32,
+ &arm_cfft_sR_f32_len64,
+ &arm_cfft_sR_f32_len128,
+ &arm_cfft_sR_f32_len256/*,
+ &arm_cfft_sR_f32_len512, */
+ /* &arm_cfft_sR_f32_len1024, */
+ /* &arm_cfft_sR_f32_len2048, */
+ /* &arm_cfft_sR_f32_len4096 */
+ ));
+
+/*--------------------------------------------------------------------------------*/
+/* CFFT_Q31 Structs */
+/*--------------------------------------------------------------------------------*/
+
+/* Uses radix2 lengths */
+ARR_DESC_DEFINE(const arm_cfft_instance_q31 *,
+ transform_cfft_q31_structs,
+ 5,
+ CURLY(
+ &arm_cfft_sR_q31_len16,
+ &arm_cfft_sR_q31_len32,
+ &arm_cfft_sR_q31_len64,
+ &arm_cfft_sR_q31_len128,
+ &arm_cfft_sR_q31_len256/*,
+ &arm_cfft_sR_q31_len512, */
+ /* &arm_cfft_sR_q31_len1024, */
+ /* &arm_cfft_sR_q31_len2048, */
+ /* &arm_cfft_sR_q31_len4096 */
+ ));
+
+/*--------------------------------------------------------------------------------*/
+/* CFFT_q15 Structs */
+/*--------------------------------------------------------------------------------*/
+
+/* Uses radix2 lengths */
+ARR_DESC_DEFINE(const arm_cfft_instance_q15 *,
+ transform_cfft_q15_structs,
+ 5,
+ CURLY(
+ &arm_cfft_sR_q15_len16,
+ &arm_cfft_sR_q15_len32,
+ &arm_cfft_sR_q15_len64,
+ &arm_cfft_sR_q15_len128,
+ &arm_cfft_sR_q15_len256/*,
+ &arm_cfft_sR_q15_len512, */
+ /* &arm_cfft_sR_q15_len1024, */
+ /* &arm_cfft_sR_q15_len2048, */
+ /* &arm_cfft_sR_q15_len4096 */
+ ));
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/inc/ref.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/inc/ref.h
new file mode 100644
index 0000000..4ab5c3c
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/inc/ref.h
@@ -0,0 +1,1396 @@
+
+#ifndef _REF_H
+#define _REF_H
+
+#include <math.h>
+#include <stdint.h>
+#include "arm_math.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#ifndef PI
+#define PI 3.14159265358979f
+#endif
+
+ /**
+ * @brief 8-bit fractional data type in 1.7 format.
+ */
+// typedef int8_t q7_t;
+
+ /**
+ * @brief 16-bit fractional data type in 1.15 format.
+ */
+// typedef int16_t q15_t;
+
+ /**
+ * @brief 32-bit fractional data type in 1.31 format.
+ */
+// typedef int32_t q31_t;
+
+ /**
+ * @brief 64-bit fractional data type in 1.63 format.
+ */
+// typedef int64_t q63_t;
+
+ /**
+ * @brief 32-bit floating-point type definition.
+ */
+// typedef float float32_t;
+
+ /**
+ * @brief 64-bit floating-point type definition.
+ */
+// typedef double float64_t;
+
+
+ /**
+ * @brief Error status returned by some functions in the library.
+ */
+
+ typedef enum
+ {
+ REF_Q7 = 0,
+ REF_Q15,
+ REF_Q31,
+ REF_F32,
+ } dataType;
+
+
+#define FLT_MAX 3.40282347e+38F
+#define DBL_MAX 1.79769313486231571e+308
+
+#define FLT_MIN 1.175494351e-38F
+#define DBL_MIN 2.22507385850720138e-308
+
+#define SCHAR_MIN (-128)
+ /* mimimum value for an object of type signed char */
+#define SCHAR_MAX 127
+ /* maximum value for an object of type signed char */
+#define UCHAR_MAX 255
+ /* maximum value for an object of type unsigned char */
+#define SHRT_MIN (-0x8000)
+ /* minimum value for an object of type short int */
+#define SHRT_MAX 0x7fff
+ /* maximum value for an object of type short int */
+#define USHRT_MAX 65535
+ /* maximum value for an object of type unsigned short int */
+#define INT_MIN (~0x7fffffff) /* -2147483648 and 0x80000000 are unsigned */
+ /* minimum value for an object of type int */
+#define INT_MAX 0x7fffffff
+ /* maximum value for an object of type int */
+#define UINT_MAX 0xffffffffU
+ /* maximum value for an object of type unsigned int */
+#define LONG_MIN (~0x7fffffffL)
+ /* minimum value for an object of type long int */
+#define LONG_MAX 0x7fffffffL
+ /* maximum value for an object of type long int */
+#define ULONG_MAX 0xffffffffUL
+ /* maximum value for an object of type unsigned long int */
+
+ /*
+ * Ref Lib Global Variables
+ */
+extern float32_t scratchArray[];
+extern arm_cfft_instance_f32 ref_cfft_sR_f32_len8192;
+
+ /*
+ * Ref Lib Functions
+ */
+
+ /*
+ * Helper Functions
+ */
+q31_t ref_sat_n(q31_t num, uint32_t bits);
+
+q31_t ref_sat_q31(q63_t num);
+
+q15_t ref_sat_q15(q31_t num);
+
+q7_t ref_sat_q7(q15_t num);
+
+float32_t ref_pow(float32_t a, uint32_t b);
+
+extern float32_t tempMatrixArray[];
+
+float32_t ref_detrm(float32_t *pSrc, float32_t *temp, uint32_t size);
+
+void ref_cofact(float32_t *pSrc, float32_t *pDst, float32_t *temp, uint32_t size);
+
+float64_t ref_detrm64(float64_t *pSrc, float64_t *temp, uint32_t size);
+
+void ref_cofact64(float64_t *pSrc, float64_t *pDst, float64_t *temp, uint32_t size);
+
+ /*
+ * Basic Math Functions
+ */
+void ref_abs_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+void ref_abs_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+void ref_abs_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+void ref_abs_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+void ref_add_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+void ref_add_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+void ref_add_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+void ref_add_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+void ref_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result);
+
+void ref_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+void ref_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+void ref_dot_prod_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result);
+
+void ref_mult_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+void ref_mult_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+void ref_mult_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+void ref_mult_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+void ref_negate_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+void ref_negate_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+void ref_negate_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+void ref_negate_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+void ref_offset_f32(
+ float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+void ref_offset_q31(
+ q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+void ref_offset_q15(
+ q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+void ref_offset_q7(
+ q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+void ref_scale_f32(
+ float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+void ref_scale_q31(
+ q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+void ref_scale_q15(
+ q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+void ref_scale_q7(
+ q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+void ref_shift_q31(
+ q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+void ref_shift_q15(
+ q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+void ref_shift_q7(
+ q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+void ref_sub_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+void ref_sub_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+void ref_sub_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+void ref_sub_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /*
+ * Complex Math Functions
+ */
+void ref_cmplx_conj_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+void ref_cmplx_conj_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+void ref_cmplx_conj_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+void ref_cmplx_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult);
+
+void ref_cmplx_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult);
+
+void ref_cmplx_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult);
+
+void ref_cmplx_mag_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+void ref_cmplx_mag_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+void ref_cmplx_mag_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+void ref_cmplx_mag_squared_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+void ref_cmplx_mag_squared_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+void ref_cmplx_mag_squared_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+void ref_cmplx_mult_cmplx_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+void ref_cmplx_mult_cmplx_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+void ref_cmplx_mult_cmplx_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+void ref_cmplx_mult_real_f32(
+ float32_t * pSrcCmplx,
+ float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples);
+
+void ref_cmplx_mult_real_q31(
+ q31_t * pSrcCmplx,
+ q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples);
+
+void ref_cmplx_mult_real_q15(
+ q15_t * pSrcCmplx,
+ q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples);
+
+ /*
+ * Controller Functions
+ */
+void ref_sin_cos_f32(
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCosVal);
+
+void ref_sin_cos_q31(
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal);
+
+float32_t ref_pid_f32(
+ arm_pid_instance_f32 * S,
+ float32_t in);
+
+q31_t ref_pid_q31(
+ arm_pid_instance_q31 * S,
+ q31_t in);
+
+q15_t ref_pid_q15(
+ arm_pid_instance_q15 * S,
+ q15_t in);
+
+ /*
+ * Fast Math Functions
+ */
+#define ref_sin_f32(a) sinf(a)
+
+q31_t ref_sin_q31(q31_t x);
+
+q15_t ref_sin_q15(q15_t x);
+
+#define ref_cos_f32(a) cosf(a)
+
+q31_t ref_cos_q31(q31_t x);
+
+q15_t ref_cos_q15(q15_t x);
+
+arm_status ref_sqrt_q31(q31_t in, q31_t * pOut);
+
+arm_status ref_sqrt_q15(q15_t in, q15_t * pOut);
+
+ /*
+ * Filtering Functions
+ */
+void ref_biquad_cascade_df2T_f32(
+ const arm_biquad_cascade_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+void ref_biquad_cascade_stereo_df2T_f32(
+ const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+void ref_biquad_cascade_df2T_f64(
+ const arm_biquad_cascade_df2T_instance_f64 * S,
+ float64_t * pSrc,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+void ref_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+void ref_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+void ref_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+void ref_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+void ref_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+void ref_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+void ref_conv_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+arm_status ref_conv_partial_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+void ref_conv_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+void ref_conv_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+arm_status ref_conv_partial_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+arm_status ref_conv_partial_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+void ref_conv_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+#define ref_conv_opt_q15(pSrcA, srcALen, pSrcB, srcBLen, pDst, \
+ pScratch1, pScratch2) \
+ ref_conv_q15(pSrcA, srcALen, pSrcB, srcBLen, pDst)
+
+void ref_conv_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+void ref_conv_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+arm_status ref_conv_partial_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+#define ref_conv_partial_opt_q15(pSrcA, srcALen, pSrcB, srcBLen, pDst, \
+ firstIndex, numPoints, \
+ pScratch1, pScratch2) \
+ ref_conv_partial_q15(pSrcA, srcALen, pSrcB, srcBLen, pDst, \
+ firstIndex, numPoints)
+
+arm_status ref_conv_partial_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+arm_status ref_conv_partial_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+void ref_conv_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+#define ref_conv_opt_q7(pSrcA, srcALen, pSrcB, srcBLen, pDst, \
+ pScratch1, pScratch2) \
+ ref_conv_q7(pSrcA, srcALen, pSrcB, srcBLen, pDst)
+
+arm_status ref_conv_partial_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+#define ref_conv_partial_opt_q7(pSrcA, srcALen, pSrcB, srcBLen, pDst, \
+ firstIndex, numPoints, \
+ pScratch1, pScratch2) \
+ ref_conv_partial_q7(pSrcA, srcALen, pSrcB, srcBLen, pDst, \
+ firstIndex, numPoints)
+
+void ref_correlate_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+void ref_correlate_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+void ref_correlate_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+void ref_correlate_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+#define ref_correlate_opt_q15(pSrcA, srcALen, pSrcB, srcBLen, pDst, \
+ pScratch1) \
+ ref_correlate_q15(pSrcA, srcALen, pSrcB, srcBLen, pDst)
+
+void ref_correlate_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+void ref_correlate_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+void ref_correlate_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+#define ref_correlate_opt_q7(pSrcA, srcALen, pSrcB, srcBLen, pDst, \
+ pScratch1, pScratch2) \
+ ref_correlate_q7(pSrcA, srcALen, pSrcB, srcBLen, pDst)
+
+void ref_fir_f32(
+ const arm_fir_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+void ref_fir_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+void ref_fir_fast_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+void ref_fir_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+void ref_fir_fast_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+void ref_fir_q7(
+ const arm_fir_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+void ref_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+void ref_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+void ref_fir_decimate_fast_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+void ref_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+void ref_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+void ref_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+void ref_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+void ref_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+void ref_fir_sparse_f32(
+ arm_fir_sparse_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize);
+
+void ref_fir_sparse_q31(
+ arm_fir_sparse_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize);
+
+void ref_fir_sparse_q15(
+ arm_fir_sparse_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+void ref_fir_sparse_q7(
+ arm_fir_sparse_instance_q7 * S,
+ q7_t *pSrc,
+ q7_t *pDst,
+ q7_t *pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+void ref_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+void ref_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+void ref_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+void ref_lms_f32(
+ const arm_lms_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+void ref_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+void ref_lms_q31(
+ const arm_lms_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+void ref_lms_norm_q31(
+ arm_lms_norm_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+void ref_lms_q15(
+ const arm_lms_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+void ref_lms_norm_q15(
+ arm_lms_norm_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+void ref_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+void ref_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+void ref_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /*
+ * Matrix Functions
+ */
+arm_status ref_mat_cmplx_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+arm_status ref_mat_cmplx_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+arm_status ref_mat_cmplx_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+arm_status ref_mat_inverse_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst);
+
+arm_status ref_mat_inverse_f64(
+ const arm_matrix_instance_f64 * pSrc,
+ arm_matrix_instance_f64 * pDst);
+
+arm_status ref_mat_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+arm_status ref_mat_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+/* Alias for testing purposes*/
+#define ref_mat_mult_fast_q31 ref_mat_mult_q31
+
+arm_status ref_mat_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+/* Alias for testing purposes*/
+#define ref_mat_mult_fast_q15 ref_mat_mult_q15
+
+arm_status ref_mat_scale_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32 * pDst);
+
+arm_status ref_mat_scale_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ q31_t scale,
+ int32_t shift,
+ arm_matrix_instance_q31 * pDst);
+
+arm_status ref_mat_scale_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ q15_t scale,
+ int32_t shift,
+ arm_matrix_instance_q15 * pDst);
+
+arm_status ref_mat_sub_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+arm_status ref_mat_sub_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+arm_status ref_mat_sub_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+arm_status ref_mat_trans_f64(
+ const arm_matrix_instance_f64 * pSrc,
+ arm_matrix_instance_f64 * pDst);
+
+arm_status ref_mat_trans_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst);
+
+arm_status ref_mat_trans_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst);
+
+arm_status ref_mat_trans_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst);
+
+arm_status ref_mat_add_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+arm_status ref_mat_add_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+arm_status ref_mat_add_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+ /*
+ * Statistics Functions
+ */
+void ref_max_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+void ref_max_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+void ref_max_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+void ref_max_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex);
+
+void ref_mean_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+void ref_mean_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+void ref_mean_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+void ref_mean_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult);
+
+void ref_min_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+void ref_min_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+void ref_min_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+void ref_min_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex);
+
+void ref_power_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+void ref_power_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+void ref_power_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+void ref_power_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+void ref_rms_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+void ref_rms_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+void ref_rms_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+void ref_std_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+void ref_std_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+void ref_std_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+void ref_var_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+void ref_var_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+void ref_var_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+ /*
+ * Support Functions
+ */
+void ref_copy_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+void ref_copy_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+void ref_copy_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+void ref_copy_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+void ref_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+void ref_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+void ref_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+void ref_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+void ref_q31_to_q15(
+ q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+void ref_q31_to_q7(
+ q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+void ref_q15_to_q31(
+ q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+void ref_q15_to_q7(
+ q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+void ref_q7_to_q31(
+ q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+void ref_q7_to_q15(
+ q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+void ref_q63_to_float(
+ q63_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+void ref_q31_to_float(
+ q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+void ref_q15_to_float(
+ q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+void ref_q7_to_float(
+ q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+void ref_float_to_q31(
+ float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+void ref_float_to_q15(
+ float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+void ref_float_to_q7(
+ float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /*
+ * Transform Functions
+ */
+void ref_cfft_f32(
+ const arm_cfft_instance_f32 * S,
+ float32_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+void ref_cfft_q31(
+ const arm_cfft_instance_q31 * S,
+ q31_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+void ref_cfft_q15(
+ const arm_cfft_instance_q15 * S,
+ q15_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+void ref_cfft_radix2_f32(
+ const arm_cfft_radix2_instance_f32 * S,
+ float32_t * pSrc);
+
+void ref_cfft_radix2_q31(
+ const arm_cfft_radix2_instance_q31 * S,
+ q31_t * pSrc);
+
+void ref_cfft_radix2_q15(
+ const arm_cfft_radix2_instance_q15 * S,
+ q15_t * pSrc);
+
+void ref_cfft_radix4_f32(
+ const arm_cfft_radix4_instance_f32 * S,
+ float32_t * pSrc);
+
+void ref_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc);
+
+void ref_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc);
+
+void ref_rfft_f32(
+ arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst);
+
+void ref_rfft_fast_f32(
+ arm_rfft_fast_instance_f32 * S,
+ float32_t * p, float32_t * pOut,
+ uint8_t ifftFlag);
+
+void ref_rfft_q31(
+ const arm_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst);
+
+void ref_rfft_q15(
+ const arm_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst);
+
+void ref_dct4_f32(
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer);
+
+void ref_dct4_q31(
+ const arm_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer);
+
+void ref_dct4_q15(
+ const arm_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer);
+
+ /*
+ * Intrinsics
+ */
+q31_t ref__QADD8(q31_t x, q31_t y);
+q31_t ref__QSUB8(q31_t x, q31_t y);
+q31_t ref__QADD16(q31_t x, q31_t y);
+q31_t ref__SHADD16(q31_t x, q31_t y);
+q31_t ref__QSUB16(q31_t x, q31_t y);
+q31_t ref__SHSUB16(q31_t x, q31_t y);
+q31_t ref__QASX(q31_t x, q31_t y);
+q31_t ref__SHASX(q31_t x, q31_t y);
+q31_t ref__QSAX(q31_t x, q31_t y);
+q31_t ref__SHSAX(q31_t x, q31_t y);
+q31_t ref__SMUSDX(q31_t x, q31_t y);
+q31_t ref__SMUADX(q31_t x, q31_t y);
+q31_t ref__QADD(q31_t x, q31_t y);
+q31_t ref__QSUB(q31_t x, q31_t y);
+q31_t ref__SMLAD(q31_t x, q31_t y, q31_t sum);
+q31_t ref__SMLADX(q31_t x, q31_t y, q31_t sum);
+q31_t ref__SMLSDX(q31_t x, q31_t y, q31_t sum);
+q63_t ref__SMLALD(q31_t x, q31_t y, q63_t sum);
+q63_t ref__SMLALDX(q31_t x, q31_t y, q63_t sum);
+q31_t ref__SMUAD(q31_t x, q31_t y);
+q31_t ref__SMUSD(q31_t x, q31_t y);
+q31_t ref__SXTB16(q31_t x);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/abs.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/abs.c
new file mode 100644
index 0000000..baca23f
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/abs.c
@@ -0,0 +1,53 @@
+#include "ref.h"
+
+void ref_abs_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = pSrc[i] < 0 ? -pSrc[i] : pSrc[i];
+ }
+}
+
+void ref_abs_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = pSrc[i] < 0 ? -pSrc[i] : pSrc[i];
+ }
+}
+
+void ref_abs_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = pSrc[i] < 0 ? -pSrc[i] : pSrc[i];
+ }
+}
+
+void ref_abs_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = pSrc[i] < 0 ? -pSrc[i] : pSrc[i];
+ }
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/add.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/add.c
new file mode 100644
index 0000000..489c8a0
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/add.c
@@ -0,0 +1,57 @@
+#include "ref.h"
+
+void ref_add_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = pSrcA[i] + pSrcB[i];
+ }
+}
+
+void ref_add_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = ref_sat_q31( (q63_t)pSrcA[i] + pSrcB[i] );
+ }
+}
+
+void ref_add_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = ref_sat_q15( (q31_t)pSrcA[i] + pSrcB[i] );
+ }
+}
+
+void ref_add_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = ref_sat_q7( (q15_t)pSrcA[i] + pSrcB[i] );
+ }
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/dot_prod.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/dot_prod.c
new file mode 100644
index 0000000..08f6178
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/dot_prod.c
@@ -0,0 +1,65 @@
+#include "ref.h"
+
+void ref_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result)
+{
+ uint32_t i;
+ float32_t sum = 0.0f;
+
+ for(i=0;i<blockSize;i++)
+ {
+ sum += pSrcA[i] * pSrcB[i];
+ }
+ *result = sum;
+}
+
+void ref_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result)
+{
+ uint32_t i;
+ q63_t sum = 0.0f;
+
+ for(i=0;i<blockSize;i++)
+ {
+ sum += ((q63_t)pSrcA[i] * pSrcB[i]) >> 14; //16.48
+ }
+ *result = sum;
+}
+
+void ref_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result)
+{
+ uint32_t i;
+ q63_t sum = 0.0f;
+
+ for(i=0;i<blockSize;i++)
+ {
+ sum += (q31_t)pSrcA[i] * pSrcB[i]; //34.30
+ }
+ *result = sum;
+}
+
+void ref_dot_prod_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result)
+{
+ uint32_t i;
+ q31_t sum = 0.0f;
+
+ for(i=0;i<blockSize;i++)
+ {
+ sum += (q31_t)pSrcA[i] * pSrcB[i]; //18.14
+ }
+ *result = sum;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/mult.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/mult.c
new file mode 100644
index 0000000..a77c870
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/mult.c
@@ -0,0 +1,64 @@
+#include "ref.h"
+
+void ref_mult_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = pSrcA[i] * pSrcB[i];
+ }
+}
+
+void ref_mult_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+ q63_t temp;
+
+ for(i=0;i<blockSize;i++)
+ {
+ temp = ((q63_t)pSrcA[i] * pSrcB[i]) >> 32;
+ temp = temp << 1;
+ pDst[i] = ref_sat_q31(temp);
+ }
+}
+
+void ref_mult_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+ q31_t temp;
+
+ for(i=0;i<blockSize;i++)
+ {
+ temp = ((q31_t)pSrcA[i] * pSrcB[i]) >> 15; //this comment is for JD, this is specifically 15 and not 16 like the q31 case might imply. This is because CMSIS DSP lib does it this way. No other reason.
+ pDst[i] = ref_sat_q15(temp);
+ }
+}
+
+void ref_mult_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+ q15_t temp;
+
+ for(i=0;i<blockSize;i++)
+ {
+ temp = ((q15_t)pSrcA[i] * pSrcB[i]) >> 7;
+ pDst[i] = ref_sat_q7(temp);
+ }
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/negate.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/negate.c
new file mode 100644
index 0000000..192da1b
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/negate.c
@@ -0,0 +1,53 @@
+#include "ref.h"
+
+void ref_negate_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = -pSrc[i];
+ }
+}
+
+void ref_negate_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = -pSrc[i];
+ }
+}
+
+void ref_negate_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = -pSrc[i];
+ }
+}
+
+void ref_negate_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = -pSrc[i];
+ }
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/offset.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/offset.c
new file mode 100644
index 0000000..b076e75
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/offset.c
@@ -0,0 +1,57 @@
+#include "ref.h"
+
+void ref_offset_f32(
+ float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = pSrc[i] + offset;
+ }
+}
+
+void ref_offset_q31(
+ q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = ref_sat_q31( (q63_t)pSrc[i] + offset );
+ }
+}
+
+void ref_offset_q15(
+ q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = ref_sat_q15( (q31_t)pSrc[i] + offset );
+ }
+}
+
+void ref_offset_q7(
+ q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = ref_sat_q7( (q15_t)pSrc[i] + offset );
+ }
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/scale.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/scale.c
new file mode 100644
index 0000000..5ab655c
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/scale.c
@@ -0,0 +1,69 @@
+#include "ref.h"
+
+void ref_scale_f32(
+ float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = pSrc[i] * scale;
+ }
+}
+
+void ref_scale_q31(
+ q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+ int8_t kShift = shift + 1; /* Shift to apply after scaling */
+ int8_t sign = (kShift & 0x80);
+ q63_t temp;
+
+ for(i=0;i<blockSize;i++)
+ {
+ temp = ((q63_t) pSrc[i] * scaleFract) >> 32;
+ if (sign)
+ pDst[i] = temp >> -kShift;
+ else
+ pDst[i] = ref_sat_q31( (q63_t)temp << kShift );
+ }
+}
+
+void ref_scale_q15(
+ q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+ int8_t kShift = 15 - shift; /* Shift to apply after scaling */
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = ref_sat_q15(((q31_t) pSrc[i] * scaleFract) >> kShift);
+ }
+}
+
+void ref_scale_q7(
+ q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+ int8_t kShift = 7 - shift; /* Shift to apply after scaling */
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = ref_sat_q7(((q15_t) pSrc[i] * scaleFract) >> kShift);
+ }
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/shift.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/shift.c
new file mode 100644
index 0000000..3bc53ad
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/shift.c
@@ -0,0 +1,73 @@
+#include "ref.h"
+
+void ref_shift_q31(
+ q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ if (shiftBits < 0)
+ {
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = pSrc[i] << shiftBits;
+ }
+ }
+ else
+ {
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = pSrc[i] >> -shiftBits;
+ }
+ }
+}
+
+void ref_shift_q15(
+ q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ if (shiftBits < 0)
+ {
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = pSrc[i] << shiftBits;
+ }
+ }
+ else
+ {
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = pSrc[i] >> -shiftBits;
+ }
+ }
+}
+
+void ref_shift_q7(
+ q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ if (shiftBits < 0)
+ {
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = pSrc[i] << shiftBits;
+ }
+ }
+ else
+ {
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = pSrc[i] >> -shiftBits;
+ }
+ }
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/sub.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/sub.c
new file mode 100644
index 0000000..da89e95
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/sub.c
@@ -0,0 +1,57 @@
+#include "ref.h"
+
+void ref_sub_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = pSrcA[i] - pSrcB[i];
+ }
+}
+
+void ref_sub_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = ref_sat_q31( (q63_t)pSrcA[i] - pSrcB[i] );
+ }
+}
+
+void ref_sub_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = ref_sat_q15( (q31_t)pSrcA[i] - pSrcB[i] );
+ }
+}
+
+void ref_sub_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = ref_sat_q7( (q15_t)pSrcA[i] - pSrcB[i] );
+ }
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_conj.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_conj.c
new file mode 100644
index 0000000..6b80de0
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_conj.c
@@ -0,0 +1,40 @@
+#include "ref.h"
+
+void ref_cmplx_conj_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples)
+{
+ uint32_t i;
+ for(i=0;i<numSamples*2;i+=2)
+ {
+ pDst[i] = pSrc[i];
+ pDst[i+1] = -pSrc[i+1];
+ }
+}
+
+void ref_cmplx_conj_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples)
+{
+ uint32_t i;
+ for(i=0;i<numSamples*2;i+=2)
+ {
+ pDst[i] = pSrc[i];
+ pDst[i+1] = -pSrc[i+1];
+ }
+}
+
+void ref_cmplx_conj_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples)
+{
+ uint32_t i;
+ for(i=0;i<numSamples*2;i+=2)
+ {
+ pDst[i] = pSrc[i];
+ pDst[i+1] = -pSrc[i+1];
+ }
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_dot_prod.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_dot_prod.c
new file mode 100644
index 0000000..19b1e1c
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_dot_prod.c
@@ -0,0 +1,72 @@
+#include "ref.h"
+
+void ref_cmplx_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult)
+{
+ float32_t sumr, sumi;
+ uint32_t i;
+
+ sumr = 0;
+ sumi = 0;
+
+ for(i=0;i<numSamples*2;i+=2)
+ {
+ sumr += pSrcA[i] * pSrcB[i] - pSrcA[i+1] * pSrcB[i+1];
+ sumi += pSrcA[i] * pSrcB[i+1] + pSrcA[i+1] * pSrcB[i];
+ }
+
+ *realResult = sumr;
+ *imagResult = sumi;
+}
+
+void ref_cmplx_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult)
+{
+ q63_t sumr, sumi;
+ uint32_t i;
+
+ sumr = 0;
+ sumi = 0;
+
+ for(i=0;i<numSamples*2;i+=2)
+ {
+ //shifting down 14 here to provide guard bits
+ sumr += (((q63_t)pSrcA[i] * pSrcB[i] ) >> 14) - (((q63_t)pSrcA[i+1] * pSrcB[i+1]) >> 14);
+ sumi += (((q63_t)pSrcA[i] * pSrcB[i+1]) >> 14) + (((q63_t)pSrcA[i+1] * pSrcB[i] ) >> 14);
+ }
+
+ *realResult = sumr;
+ *imagResult = sumi;
+}
+
+void ref_cmplx_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult)
+{
+ q63_t sumr, sumi;
+ uint32_t i;
+
+ sumr = 0;
+ sumi = 0;
+
+ for(i=0;i<numSamples*2;i+=2)
+ {
+ sumr += (q31_t)pSrcA[i] * pSrcB[i] - (q31_t)pSrcA[i+1] * pSrcB[i+1];
+ sumi += (q31_t)pSrcA[i] * pSrcB[i+1] + (q31_t)pSrcA[i+1] * pSrcB[i];
+ }
+
+ //shifting down 6 at the end here because there are already 32 guard bits available, this method is more accurate
+ *realResult = (q31_t)(sumr >> 6);
+ *imagResult = (q31_t)(sumi >> 6);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mag.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mag.c
new file mode 100644
index 0000000..b5ac28d
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mag.c
@@ -0,0 +1,49 @@
+#include "ref.h"
+
+void ref_cmplx_mag_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples)
+{
+ uint32_t i;
+
+ for(i=0;i<numSamples*2;i+=2)
+ {
+ *pDst++ = sqrtf(pSrc[i] * pSrc[i] + pSrc[i+1] * pSrc[i+1]);
+ }
+}
+
+void ref_cmplx_mag_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples)
+{
+ uint32_t i;
+ q31_t acc0,acc1,out;
+
+ for(i=0;i<numSamples*2;i+=2)
+ {
+ acc0 = (q31_t)(((q63_t)pSrc[i] * pSrc[i]) >> 33);
+ acc1 = (q31_t)(((q63_t)pSrc[i+1] * pSrc[i+1]) >> 33);
+ out = acc0 + acc1;
+ *pDst++ = (q31_t)(sqrtf((float)out / 2147483648.0f) * 2147483648.0f);
+ }
+}
+
+void ref_cmplx_mag_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples)
+{
+ uint32_t i;
+ q31_t acc0,acc1;
+ q15_t out;
+
+ for(i=0;i<numSamples*2;i+=2)
+ {
+ acc0 = pSrc[i] * pSrc[i];
+ acc1 = pSrc[i+1] * pSrc[i+1];
+ out = (q15_t) (((q63_t) acc0 + acc1) >> 17);
+ *pDst++ = (q15_t)(sqrtf((float)out / 32768.0f) * 32768.0f);
+ }
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mag_squared.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mag_squared.c
new file mode 100644
index 0000000..aec7bd5
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mag_squared.c
@@ -0,0 +1,46 @@
+#include "ref.h"
+
+void ref_cmplx_mag_squared_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples)
+{
+ uint32_t i;
+
+ for(i=0;i<numSamples*2;i+=2)
+ {
+ *pDst++ = pSrc[i] * pSrc[i] + pSrc[i+1] * pSrc[i+1];
+ }
+}
+
+void ref_cmplx_mag_squared_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples)
+{
+ uint32_t i;
+ q31_t acc0,acc1;
+
+ for(i=0;i<numSamples*2;i+=2)
+ {
+ acc0 = (q31_t)(((q63_t)pSrc[i] * pSrc[i]) >> 33);
+ acc1 = (q31_t)(((q63_t)pSrc[i+1] * pSrc[i+1]) >> 33);
+ *pDst++ = acc0 + acc1;
+ }
+}
+
+void ref_cmplx_mag_squared_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples)
+{
+ uint32_t i;
+ q31_t acc0,acc1;
+
+ for(i=0;i<numSamples*2;i+=2)
+ {
+ acc0 = pSrc[i] * pSrc[i];
+ acc1 = pSrc[i+1] * pSrc[i+1];
+ *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
+ }
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mult_cmplx.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mult_cmplx.c
new file mode 100644
index 0000000..c7a5409
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mult_cmplx.c
@@ -0,0 +1,56 @@
+#include "ref.h"
+
+void ref_cmplx_mult_cmplx_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples)
+{
+ uint32_t i;
+
+ for(i=0;i<numSamples*2;i+=2)
+ {
+ pDst[i] = pSrcA[i] * pSrcB[i] - pSrcA[i+1] * pSrcB[i+1];
+ pDst[i+1] = pSrcA[i] * pSrcB[i+1] + pSrcA[i+1] * pSrcB[i];
+ }
+}
+
+void ref_cmplx_mult_cmplx_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples)
+{
+ uint32_t i;
+ q31_t mul1, mul2, mul3, mul4;
+
+ for(i=0;i<numSamples*2;i+=2)
+ {
+ mul1 = ((q63_t)pSrcA[i] * pSrcB[i]) >> 33;
+ mul2 = ((q63_t)pSrcA[i+1] * pSrcB[i+1]) >> 33;
+ mul3 = ((q63_t)pSrcA[i] * pSrcB[i+1]) >> 33;
+ mul4 = ((q63_t)pSrcA[i+1] * pSrcB[i]) >> 33;
+ pDst[i] = mul1 - mul2;
+ pDst[i+1] = mul3 + mul4;
+ }
+}
+
+void ref_cmplx_mult_cmplx_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples)
+{
+ uint32_t i;
+ q31_t mul1, mul2, mul3, mul4;
+
+ for(i=0;i<numSamples*2;i+=2)
+ {
+ mul1 = ((q31_t)pSrcA[i] * pSrcB[i]) >> 17;
+ mul2 = ((q31_t)pSrcA[i+1] * pSrcB[i+1]) >> 17;
+ mul3 = ((q31_t)pSrcA[i] * pSrcB[i+1]) >> 17;
+ mul4 = ((q31_t)pSrcA[i+1] * pSrcB[i]) >> 17;
+ pDst[i] = mul1 - mul2;
+ pDst[i+1] = mul3 + mul4;
+ }
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mult_real.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mult_real.c
new file mode 100644
index 0000000..dc4928e
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mult_real.c
@@ -0,0 +1,52 @@
+#include "ref.h"
+
+void ref_cmplx_mult_real_f32(
+ float32_t * pSrcCmplx,
+ float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples)
+{
+ uint32_t i;
+
+ for(i=0;i<numSamples;i++)
+ {
+ pCmplxDst[2*i+0] = pSrcCmplx[2*i+0] * pSrcReal[i];
+ pCmplxDst[2*i+1] = pSrcCmplx[2*i+1] * pSrcReal[i];
+ }
+}
+
+void ref_cmplx_mult_real_q31(
+ q31_t * pSrcCmplx,
+ q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples)
+{
+ uint32_t i;
+ q31_t tempR, tempI;
+
+ for(i=0;i<numSamples;i++)
+ {
+ tempR = ((q63_t) pSrcCmplx[2*i+0] * pSrcReal[i]) >> 32;
+ tempI = ((q63_t) pSrcCmplx[2*i+1] * pSrcReal[i]) >> 32;
+ pCmplxDst[2*i+0] = ref_sat_n(tempR, 31) << 1;
+ pCmplxDst[2*i+1] = ref_sat_n(tempI, 31) << 1;
+ }
+}
+
+void ref_cmplx_mult_real_q15(
+ q15_t * pSrcCmplx,
+ q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples)
+{
+ uint32_t i;
+ q31_t tempR, tempI;
+
+ for(i=0;i<numSamples;i++)
+ {
+ tempR = ((q31_t) pSrcCmplx[2*i+0] * pSrcReal[i]) >> 15;
+ tempI = ((q31_t) pSrcCmplx[2*i+1] * pSrcReal[i]) >> 15;
+ pCmplxDst[2*i+0] = ref_sat_q15(tempR);
+ pCmplxDst[2*i+1] = ref_sat_q15(tempI);
+ }
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/pid.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/pid.c
new file mode 100644
index 0000000..51aa633
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/pid.c
@@ -0,0 +1,97 @@
+#include "ref.h"
+
+float32_t ref_pid_f32(
+ arm_pid_instance_f32 * S,
+ float32_t in)
+{
+ float32_t out;
+
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
+ out = S->state[2] + S->A0 * in + S->A1 * S->state[0] + S->A2 * S->state[1];
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+}
+
+q31_t ref_pid_q31(
+ arm_pid_instance_q31 * S,
+ q31_t in)
+{
+ q63_t acc;
+ q31_t out;
+
+ /* acc = A0 * x[n] */
+ acc = (q63_t) S->A0 * in;
+
+ /* acc += A1 * x[n-1] */
+ acc += (q63_t) S->A1 * S->state[0];
+
+ /* acc += A2 * x[n-2] */
+ acc += (q63_t) S->A2 * S->state[1];
+
+ /* convert output to 1.31 format to add y[n-1] */
+ out = (q31_t) (acc >> 31U);
+
+ /* out += y[n-1] */
+ out += S->state[2];
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+}
+
+q15_t ref_pid_q15(
+ arm_pid_instance_q15 * S,
+ q15_t in)
+{
+ q63_t acc;
+ q15_t out;
+ q15_t A1, A2;
+
+#if defined (ARM_MATH_DSP)
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ A2 = S->A1 >> 16;
+ A1 = (q15_t)S->A1;
+#else
+ A1 = S->A1 >> 16;
+ A2 = (q15_t)S->A1;
+#endif
+
+#else
+
+ A1 = S->A1;
+ A2 = S->A2;
+
+#endif
+
+ /* acc = A0 * x[n] */
+ acc = ((q31_t) S->A0) * in;
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc += (q31_t) A1 * S->state[0];
+ acc += (q31_t) A2 * S->state[1];
+
+ /* acc += y[n-1] */
+ acc += (q31_t) S->state[2] << 15;
+
+ /* saturate the output */
+ out = ref_sat_q15(acc >> 15);
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/sin_cos.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/sin_cos.c
new file mode 100644
index 0000000..22c91a0
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/sin_cos.c
@@ -0,0 +1,21 @@
+#include "ref.h"
+
+void ref_sin_cos_f32(
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCosVal)
+{
+ //theta is given in degrees
+ *pSinVal = sinf(theta * 6.28318530717959f / 360.0f);
+ *pCosVal = cosf(theta * 6.28318530717959f / 360.0f);
+}
+
+void ref_sin_cos_q31(
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal)
+{
+ //theta is given in the range [-1,1) to represent [-pi,pi)
+ *pSinVal = (q31_t)(sinf((float32_t)theta * 3.14159265358979f / 2147483648.0f) * 2147483648.0f);
+ *pCosVal = (q31_t)(cosf((float32_t)theta * 3.14159265358979f / 2147483648.0f) * 2147483648.0f);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/cos.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/cos.c
new file mode 100644
index 0000000..ab6c98e
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/cos.c
@@ -0,0 +1,11 @@
+#include "ref.h"
+
+q31_t ref_cos_q31(q31_t x)
+{
+ return (q31_t)(cosf((float32_t)x * 6.28318530717959f / 2147483648.0f) * 2147483648.0f);
+}
+
+q15_t ref_cos_q15(q15_t x)
+{
+ return (q15_t)(cosf((float32_t)x * 6.28318530717959f / 32768.0f) * 32768.0f);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/sin.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/sin.c
new file mode 100644
index 0000000..3f303a5
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/sin.c
@@ -0,0 +1,11 @@
+#include "ref.h"
+
+q31_t ref_sin_q31(q31_t x)
+{
+ return (q31_t)(sinf((float32_t)x * 6.28318530717959f / 2147483648.0f) * 2147483648.0f);
+}
+
+q15_t ref_sin_q15(q15_t x)
+{
+ return (q15_t)(sinf((float32_t)x * 6.28318530717959f / 32768.0f) * 32768.0f);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/sqrt.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/sqrt.c
new file mode 100644
index 0000000..9dc34af
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/sqrt.c
@@ -0,0 +1,15 @@
+#include "ref.h"
+
+arm_status ref_sqrt_q31(q31_t in, q31_t * pOut)
+{
+ *pOut = (q31_t)(sqrtf((float32_t)in / 2147483648.0f) * 2147483648.0f);
+
+ return ARM_MATH_SUCCESS;
+}
+
+arm_status ref_sqrt_q15(q15_t in, q15_t * pOut)
+{
+ *pOut = (q15_t)(sqrtf((float32_t)in / 32768.0f) * 32768.0f);
+
+ return ARM_MATH_SUCCESS;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/biquad.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/biquad.c
new file mode 100644
index 0000000..1fe7c54
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/biquad.c
@@ -0,0 +1,713 @@
+#include "ref.h"
+
+void ref_biquad_cascade_df2T_f32(
+ const arm_biquad_cascade_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pIn = pSrc; /* source pointer */
+ float32_t *pOut = pDst; /* destination pointer */
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */
+ float32_t acc; /* accumulator */
+ float32_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ float32_t Xn; /* temporary input */
+ float32_t d1, d2; /* state variables */
+ uint32_t sample, stage = S->numStages; /* loop counters */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /*Reading the state values */
+ d1 = pState[0];
+ d2 = pState[1];
+
+ sample = blockSize;
+
+ while (sample > 0U)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* y[n] = b0 * x[n] + d1 */
+ acc = (b0 * Xn) + d1;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = acc;
+
+ /* Every time after the output is computed state should be updated. */
+ /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+ d1 = (b1 * Xn + a1 * acc) + d2;
+
+ /* d2 = b2 * x[n] + a2 * y[n] */
+ d2 = (b2 * Xn) + (a2 * acc);
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* Store the updated state variables back into the state array */
+ *pState++ = d1;
+ *pState++ = d2;
+
+ /* The current stage input is given as the output to the next stage */
+ pIn = pDst;
+
+ /*Reset the output working pointer */
+ pOut = pDst;
+
+ /* decrement the loop counter */
+ stage--;
+
+ } while (stage > 0U);
+}
+
+
+void ref_biquad_cascade_stereo_df2T_f32(
+ const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pIn = pSrc; /* source pointer */
+ float32_t *pOut = pDst; /* destination pointer */
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */
+ float32_t acc1a, acc1b; /* accumulator */
+ float32_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ float32_t Xn1a, Xn1b; /* temporary input */
+ float32_t d1a, d2a, d1b, d2b; /* state variables */
+ uint32_t sample, stage = S->numStages; /* loop counters */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /*Reading the state values */
+ d1a = pState[0];
+ d2a = pState[1];
+ d1b = pState[2];
+ d2b = pState[3];
+
+ sample = blockSize;
+
+ while (sample > 0U)
+ {
+ /* Read the input */
+ Xn1a = *pIn++; //Channel a
+ Xn1b = *pIn++; //Channel b
+
+ /* y[n] = b0 * x[n] + d1 */
+ acc1a = (b0 * Xn1a) + d1a;
+ acc1b = (b0 * Xn1b) + d1b;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = acc1a;
+ *pOut++ = acc1b;
+
+ /* Every time after the output is computed state should be updated. */
+ /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+ d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a;
+ d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b;
+
+ /* d2 = b2 * x[n] + a2 * y[n] */
+ d2a = (b2 * Xn1a) + (a2 * acc1a);
+ d2b = (b2 * Xn1b) + (a2 * acc1b);
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* Store the updated state variables back into the state array */
+ *pState++ = d1a;
+ *pState++ = d2a;
+ *pState++ = d1b;
+ *pState++ = d2b;
+
+ /* The current stage input is given as the output to the next stage */
+ pIn = pDst;
+
+ /*Reset the output working pointer */
+ pOut = pDst;
+
+ /* decrement the loop counter */
+ stage--;
+
+ } while (stage > 0U);
+
+}
+
+void ref_biquad_cascade_df2T_f64(
+ const arm_biquad_cascade_df2T_instance_f64 * S,
+ float64_t * pSrc,
+ float64_t * pDst,
+ uint32_t blockSize)
+{
+ float64_t *pIn = pSrc; /* source pointer */
+ float64_t *pOut = pDst; /* destination pointer */
+ float64_t *pState = S->pState; /* State pointer */
+ float64_t *pCoeffs = S->pCoeffs; /* coefficient pointer */
+ float64_t acc; /* accumulator */
+ float64_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ float64_t Xn; /* temporary input */
+ float64_t d1, d2; /* state variables */
+ uint32_t sample, stage = S->numStages; /* loop counters */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /*Reading the state values */
+ d1 = pState[0];
+ d2 = pState[1];
+
+ sample = blockSize;
+
+ while (sample > 0U)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* y[n] = b0 * x[n] + d1 */
+ acc = (b0 * Xn) + d1;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = acc;
+
+ /* Every time after the output is computed state should be updated. */
+ /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+ d1 = (b1 * Xn + a1 * acc) + d2;
+
+ /* d2 = b2 * x[n] + a2 * y[n] */
+ d2 = (b2 * Xn) + (a2 * acc);
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* Store the updated state variables back into the state array */
+ *pState++ = d1;
+ *pState++ = d2;
+
+ /* The current stage input is given as the output to the next stage */
+ pIn = pDst;
+
+ /*Reset the output working pointer */
+ pOut = pDst;
+
+ /* decrement the loop counter */
+ stage--;
+
+ } while (stage > 0U);
+}
+
+void ref_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pIn = pSrc; /* source pointer */
+ float32_t *pOut = pDst; /* destination pointer */
+ float32_t *pState = S->pState; /* pState pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */
+ float32_t acc; /* Simulates the accumulator */
+ float32_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ float32_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */
+ float32_t Xn; /* temporary input */
+ uint32_t sample, stage = S->numStages; /* loop counters */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the pState values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* The variables acc holds the output value that is computed:
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize;
+
+ while (sample > 0U)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = acc;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ Yn1 = acc;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = Xn1;
+ *pState++ = Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent numStages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset the output pointer */
+ pOut = pDst;
+
+ /* decrement the loop counter */
+ stage--;
+
+ } while (stage > 0U);
+}
+
+void ref_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pIn = pSrc; /* input pointer initialization */
+ q31_t *pOut = pDst; /* output pointer initialization */
+ q63_t *pState = S->pState; /* state pointer initialization */
+ q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */
+ q63_t acc; /* accumulator */
+ q31_t Xn1, Xn2; /* Input Filter state variables */
+ q63_t Yn1, Yn2; /* Output Filter state variables */
+ q31_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ q31_t Xn; /* temporary input */
+ int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */
+ uint32_t sample, stage = S->numStages; /* loop counters */
+ q31_t acc_l, acc_h; /* temporary output */
+ uint32_t uShift = ((uint32_t) S->postShift + 1U);
+ uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the state values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ sample = blockSize;
+
+ while (sample > 0U)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ acc = (q63_t)Xn*b0 + (q63_t)Xn1*b1 + (q63_t)Xn2*b2;
+ /* acc += a1 * y[n-1] */
+ acc += mult32x64(Yn1, a1);
+ /* acc += a2 * y[n-2] */
+ acc += mult32x64(Yn2, a2);
+
+ /* Every time after the output is computed state should be updated. */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+
+ /* The result is converted to 1.63, Yn1 variable is reused */
+ Yn1 = acc << shift;
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer in 1.31 format. */
+ *pOut++ = acc_h;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* The first stage output is given as input to the second stage. */
+ pIn = pDst;
+
+ /* Reset to destination buffer working pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = (q63_t) Xn1;
+ *pState++ = (q63_t) Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ } while (--stage);
+}
+
+void ref_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q63_t acc; /* accumulator */
+ uint32_t uShift = ((uint32_t) S->postShift + 1U);
+ uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */
+ q31_t *pIn = pSrc; /* input pointer initialization */
+ q31_t *pOut = pDst; /* output pointer initialization */
+ q31_t *pState = S->pState; /* pState pointer initialization */
+ q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */
+ q31_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */
+ q31_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ q31_t Xn; /* temporary input */
+ uint32_t sample, stage = S->numStages; /* loop counters */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the state values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* The variables acc holds the output value that is computed:
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize;
+
+ while (sample > 0U)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ acc = (q63_t) b0 *Xn;
+
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) b1 *Xn1;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) b2 *Xn2;
+ /* acc += a1 * y[n-1] */
+ acc += (q63_t) a1 *Yn1;
+ /* acc += a2 * y[n-2] */
+ acc += (q63_t) a2 *Yn2;
+
+ /* The result is converted to 1.31 */
+ acc = acc >> lShift;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ Yn1 = (q31_t) acc;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = (q31_t) acc;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent stages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset to destination pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = Xn1;
+ *pState++ = Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ } while (--stage);
+}
+
+
+void ref_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t acc = 0; /* accumulator */
+ q31_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */
+ q31_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ q31_t *pIn = pSrc; /* input pointer initialization */
+ q31_t *pOut = pDst; /* output pointer initialization */
+ q31_t *pState = S->pState; /* pState pointer initialization */
+ q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */
+ q31_t Xn; /* temporary input */
+ int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */
+ uint32_t sample, stage = S->numStages; /* loop counters */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the state values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ sample = blockSize;
+
+ while (sample > 0U)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ mult_32x32_keep32_R(acc, b0, Xn);
+ multAcc_32x32_keep32_R(acc, b1, Xn1);
+ multAcc_32x32_keep32_R(acc, b2, Xn2);
+ multAcc_32x32_keep32_R(acc, a1, Yn1);
+ multAcc_32x32_keep32_R(acc, a2, Yn2);
+
+ /* The result is converted to 1.31 */
+ acc <<= shift;
+
+ /* Every time after the output is computed state should be updated. */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ Yn1 = acc;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = acc;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent stages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset to destination pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = Xn1;
+ *pState++ = Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ } while (--stage);
+}
+
+void ref_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pIn = pSrc; /* Source pointer */
+ q15_t *pOut = pDst; /* Destination pointer */
+ q15_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ q15_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */
+ q15_t Xn; /* temporary input */
+ q31_t acc; /* Accumulator */
+ int32_t shift = (15 - (int32_t) S->postShift); /* Post shift */
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ uint32_t sample, stage = (uint32_t) S->numStages; /* Stage loop counter */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ pCoeffs++; // skip the 0 coefficient
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the state values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ sample = blockSize;
+
+ while (sample > 0U)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ acc = (q31_t)b0*Xn + (q31_t)b1*Xn1 + (q31_t)b2*Xn2 + (q31_t)a1*Yn1 + (q31_t)a2*Yn2;
+
+ /* The result is converted to 1.15 */
+ acc = ref_sat_q15(acc >> shift);
+
+ /* Every time after the output is computed state should be updated. */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ Yn1 = (q15_t) acc;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = (q15_t) acc;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent stages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset to destination pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = Xn1;
+ *pState++ = Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ } while (--stage);
+}
+
+void ref_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pIn = pSrc; /* Source pointer */
+ q15_t *pOut = pDst; /* Destination pointer */
+ q15_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ q15_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */
+ q15_t Xn; /* temporary input */
+ q63_t acc; /* Accumulator */
+ int32_t shift = (15 - (int32_t) S->postShift); /* Post shift */
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ uint32_t sample, stage = (uint32_t) S->numStages; /* Stage loop counter */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ pCoeffs++; // skip the 0 coefficient
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the state values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ sample = blockSize;
+
+ while (sample > 0U)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ acc = (q31_t)b0*Xn + (q31_t)b1*Xn1 + (q31_t)b2*Xn2 + (q31_t)a1*Yn1 + (q31_t)a2*Yn2;
+
+ /* The result is converted to 1.15 */
+ acc = ref_sat_q15(acc >> shift);
+
+ /* Every time after the output is computed state should be updated. */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ Yn1 = (q15_t) acc;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = (q15_t) acc;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent stages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset to destination pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = Xn1;
+ *pState++ = Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ } while (--stage);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/conv.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/conv.c
new file mode 100644
index 0000000..dc1b103
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/conv.c
@@ -0,0 +1,350 @@
+#include "ref.h"
+
+void ref_conv_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst)
+{
+ float32_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counters */
+
+ /* Loop to calculate convolution for output length number of times */
+ for (i = 0; i < srcALen + srcBLen - 1; i++)
+ {
+ /* Initialize sum with zero to carry out MAC operations */
+ sum = 0.0f;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if ((i - j < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += pSrcB[i - j] * pSrcA[j];
+ }
+ }
+ /* Store the output in the destination buffer */
+ pDst[i] = sum;
+ }
+}
+
+arm_status ref_conv_partial_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+ ref_conv_f32(pSrcA,srcALen,pSrcB,srcBLen,pDst);
+
+ return ARM_MATH_SUCCESS;
+}
+
+void ref_conv_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst)
+{
+ q63_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counter */
+
+ /* Loop to calculate output of convolution for output length number of times */
+ for (i = 0; i < srcALen + srcBLen - 1; i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if ((i - j < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += (q63_t) pSrcA[j] * (pSrcB[i - j]);
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = (q31_t)(sum >> 31U);
+ }
+}
+
+void ref_conv_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst)
+{
+ q31_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counter */
+
+ /* Loop to calculate output of convolution for output length number of times */
+ for (i = 0; i < srcALen + srcBLen - 1; i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if ((i - j < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum = (q31_t) ((((q63_t)sum << 32) +
+ ((q63_t)pSrcA[j] * pSrcB[i - j])) >> 32);
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = (q31_t)(sum << 1U);
+ }
+}
+
+arm_status ref_conv_partial_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+ ref_conv_q31(pSrcA,srcALen,pSrcB,srcBLen,pDst);
+
+ return ARM_MATH_SUCCESS;
+}
+
+arm_status ref_conv_partial_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+ ref_conv_fast_q31(pSrcA,srcALen,pSrcB,srcBLen,pDst);
+
+ return ARM_MATH_SUCCESS;
+}
+
+void ref_conv_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst)
+{
+ q63_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counter */
+
+ /* Loop to calculate output of convolution for output length number of times */
+ for (i = 0; i < srcALen + srcBLen - 1; i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if ((i - j < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += (q31_t)pSrcA[j] * pSrcB[i - j];
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = ref_sat_q15(sum >> 15U);
+ }
+}
+
+arm_status ref_conv_partial_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+ q31_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counter */
+
+ /* Loop to calculate output of convolution for output length number of times */
+ for (i = 0; i < srcALen + srcBLen - 1; i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if ((i - j < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += (q31_t)pSrcA[j] * pSrcB[i - j];
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = ref_sat_q15(sum >> 15U);
+ }
+
+ return ARM_MATH_SUCCESS;
+}
+
+void ref_conv_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst)
+{
+ q31_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counter */
+
+ /* Loop to calculate output of convolution for output length number of times */
+ for (i = 0; i < srcALen + srcBLen - 1; i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if ((i - j < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += (q31_t)pSrcA[j] * pSrcB[i - j];
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = sum >> 15U;
+ }
+}
+
+void ref_conv_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+ q31_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counter */
+
+ /* Loop to calculate output of convolution for output length number of times */
+ for (i = 0; i < srcALen + srcBLen - 1; i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if ((i - j < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += (q31_t)pSrcA[j] * pSrcB[i - j];
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = ref_sat_q15(sum >> 15U);
+ }
+}
+
+arm_status ref_conv_partial_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+ ref_conv_q15(pSrcA,srcALen,pSrcB,srcBLen,pDst);
+
+ return ARM_MATH_SUCCESS;
+}
+
+arm_status ref_conv_partial_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+ ref_conv_fast_q15(pSrcA,srcALen,pSrcB,srcBLen,pDst);
+
+ return ARM_MATH_SUCCESS;
+}
+
+
+void ref_conv_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst)
+{
+ q31_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counter */
+
+ /* Loop to calculate output of convolution for output length number of times */
+ for (i = 0; i < srcALen + srcBLen - 1; i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if ((i - j < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += (q15_t)pSrcA[j] * pSrcB[i - j];
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = (q7_t)ref_sat_q7(sum >> 7);
+ }
+}
+
+arm_status ref_conv_partial_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+ ref_conv_q7(pSrcA,srcALen,pSrcB,srcBLen,pDst);
+
+ return ARM_MATH_SUCCESS;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/correlate.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/correlate.c
new file mode 100644
index 0000000..ff1d95b
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/correlate.c
@@ -0,0 +1,513 @@
+#include "ref.h"
+
+void ref_correlate_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst)
+{
+ float32_t *pIn1 = pSrcA; /* inputA pointer */
+ float32_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */
+ float32_t sum; /* Accumulator */
+ uint32_t i = 0U, j; /* loop counters */
+ uint32_t inv = 0U; /* Reverse order flag */
+ uint32_t tot = 0U; /* Length */
+
+ /* The algorithm implementation is based on the lengths of the inputs.
+ * srcB is always made to slide across srcA.
+ * So srcBLen is always considered as shorter or equal to srcALen
+ * But CORR(x, y) is reverse of CORR(y, x)
+ * So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer
+ * and a variable, inv is set to 1
+ * If lengths are not equal then zero pad has to be done to make the two
+ * inputs of same length. But to improve the performance, we include zeroes
+ * in the output instead of zero padding either of the the inputs
+ * If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the
+ * starting of the output buffer
+ * If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the
+ * ending of the output buffer
+ * Once the zero padding is done the remaining of the output is calcualted
+ * using convolution but with the shorter signal time shifted.
+ */
+
+ /* Calculate the length of the remaining sequence */
+ tot = srcALen + srcBLen - 2U;
+
+ if (srcALen > srcBLen)
+ {
+ /* Calculating the number of zeros to be padded to the output */
+ /* Initialise the pointer after zero padding */
+ pDst += srcALen - srcBLen;
+ }
+ else if (srcALen < srcBLen)
+ {
+ /* Initialization to inputB pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization to the end of inputA pointer */
+ pIn2 = pSrcA + srcALen - 1U;
+
+ /* Initialisation of the pointer after zero padding */
+ pDst += tot;
+
+ /* Swapping the lengths */
+ j = srcALen;
+ srcALen = srcBLen;
+ srcBLen = j;
+
+ /* Setting the reverse flag */
+ inv = 1;
+ }
+
+ /* Loop to calculate convolution for output length number of times */
+ for (i = 0U; i <= tot; i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0.0f;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0U; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if ((i - j < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += pIn1[j] * pIn2[-((int32_t)i - j)];
+ }
+ }
+ /* Store the output in the destination buffer */
+ if (inv == 1)
+ *pDst-- = sum;
+ else
+ *pDst++ = sum;
+ }
+}
+
+void ref_correlate_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst)
+{
+ q31_t *pIn1 = pSrcA; /* inputA pointer */
+ q31_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */
+ q63_t sum; /* Accumulators */
+ uint32_t i = 0U, j; /* loop counters */
+ uint32_t inv = 0U; /* Reverse order flag */
+ uint32_t tot = 0U; /* Length */
+
+ /* Calculate the length of the remaining sequence */
+ tot = ((srcALen + srcBLen) - 2U);
+
+ if (srcALen > srcBLen)
+ {
+ /* Calculating the number of zeros to be padded to the output */
+ j = srcALen - srcBLen;
+
+ /* Initialise the pointer after zero padding */
+ pDst += j;
+ }
+
+ else if (srcALen < srcBLen)
+ {
+ /* Initialization to inputB pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization to the end of inputA pointer */
+ pIn2 = pSrcA + (srcALen - 1U);
+
+ /* Initialisation of the pointer after zero padding */
+ pDst = pDst + tot;
+
+ /* Swapping the lengths */
+ j = srcALen;
+ srcALen = srcBLen;
+ srcBLen = j;
+
+ /* Setting the reverse flag */
+ inv = 1;
+
+ }
+
+ /* Loop to calculate correlation for output length number of times */
+ for (i = 0U; i <= tot; i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to correlation equation */
+ for (j = 0U; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if ((((i - j) < srcBLen) && (j < srcALen)))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q63_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
+ }
+ }
+ /* Store the output in the destination buffer */
+ if (inv == 1)
+ *pDst-- = (q31_t)(sum >> 31U);
+ else
+ *pDst++ = (q31_t)(sum >> 31U);
+ }
+}
+
+void ref_correlate_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst)
+{
+ q31_t *pIn1 = pSrcA; /* inputA pointer */
+ q31_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */
+ q63_t sum; /* Accumulators */
+ uint32_t i = 0U, j; /* loop counters */
+ uint32_t inv = 0U; /* Reverse order flag */
+ uint32_t tot = 0U; /* Length */
+
+ /* Calculate the length of the remaining sequence */
+ tot = ((srcALen + srcBLen) - 2U);
+
+ if (srcALen > srcBLen)
+ {
+ /* Calculating the number of zeros to be padded to the output */
+ j = srcALen - srcBLen;
+
+ /* Initialise the pointer after zero padding */
+ pDst += j;
+ }
+
+ else if (srcALen < srcBLen)
+ {
+ /* Initialization to inputB pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization to the end of inputA pointer */
+ pIn2 = pSrcA + (srcALen - 1U);
+
+ /* Initialisation of the pointer after zero padding */
+ pDst = pDst + tot;
+
+ /* Swapping the lengths */
+ j = srcALen;
+ srcALen = srcBLen;
+ srcBLen = j;
+
+ /* Setting the reverse flag */
+ inv = 1;
+
+ }
+
+ /* Loop to calculate correlation for output length number of times */
+ for (i = 0U; i <= tot; i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to correlation equation */
+ for (j = 0U; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if ((((i - j) < srcBLen) && (j < srcALen)))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) pIn1[j] * pIn2[-((int32_t) i - j)])) >> 32);
+ }
+ }
+ /* Store the output in the destination buffer */
+ if (inv == 1)
+ *pDst-- = (q31_t)(sum << 1U);
+ else
+ *pDst++ = (q31_t)(sum << 1U);
+ }
+}
+
+void ref_correlate_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst)
+{
+ q15_t *pIn1 = pSrcA; /* inputA pointer */
+ q15_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */
+ q63_t sum; /* Accumulators */
+ uint32_t i = 0U, j; /* loop counters */
+ uint32_t inv = 0U; /* Reverse order flag */
+ uint32_t tot = 0U; /* Length */
+
+ /* Calculate the length of the remaining sequence */
+ tot = ((srcALen + srcBLen) - 2U);
+
+ if (srcALen > srcBLen)
+ {
+ /* Calculating the number of zeros to be padded to the output */
+ j = srcALen - srcBLen;
+
+ /* Initialise the pointer after zero padding */
+ pDst += j;
+ }
+
+ else if (srcALen < srcBLen)
+ {
+ /* Initialization to inputB pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization to the end of inputA pointer */
+ pIn2 = pSrcA + (srcALen - 1U);
+
+ /* Initialisation of the pointer after zero padding */
+ pDst = pDst + tot;
+
+ /* Swapping the lengths */
+ j = srcALen;
+ srcALen = srcBLen;
+ srcBLen = j;
+
+ /* Setting the reverse flag */
+ inv = 1;
+
+ }
+
+ /* Loop to calculate convolution for output length number of times */
+ for (i = 0U; i <= tot; i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0U; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if ((((i - j) < srcBLen) && (j < srcALen)))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q31_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
+ }
+ }
+ /* Store the output in the destination buffer */
+ if (inv == 1)
+ *pDst-- = (q15_t) ref_sat_q15(sum >> 15U);
+ else
+ *pDst++ = (q15_t) ref_sat_q15(sum >> 15U);
+ }
+}
+
+void ref_correlate_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst)
+{
+ q15_t *pIn1 = pSrcA; /* inputA pointer */
+ q15_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */
+ q63_t sum; /* Accumulators */
+ uint32_t i = 0U, j; /* loop counters */
+ uint32_t inv = 0U; /* Reverse order flag */
+ uint32_t tot = 0U; /* Length */
+
+ /* Calculate the length of the remaining sequence */
+ tot = ((srcALen + srcBLen) - 2U);
+
+ if (srcALen > srcBLen)
+ {
+ /* Calculating the number of zeros to be padded to the output */
+ j = srcALen - srcBLen;
+
+ /* Initialise the pointer after zero padding */
+ pDst += j;
+ }
+
+ else if (srcALen < srcBLen)
+ {
+ /* Initialization to inputB pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization to the end of inputA pointer */
+ pIn2 = pSrcA + (srcALen - 1U);
+
+ /* Initialisation of the pointer after zero padding */
+ pDst = pDst + tot;
+
+ /* Swapping the lengths */
+ j = srcALen;
+ srcALen = srcBLen;
+ srcBLen = j;
+
+ /* Setting the reverse flag */
+ inv = 1;
+
+ }
+
+ /* Loop to calculate convolution for output length number of times */
+ for (i = 0U; i <= tot; i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0U; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if ((((i - j) < srcBLen) && (j < srcALen)))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q31_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
+ }
+ }
+ /* Store the output in the destination buffer */
+ if (inv == 1)
+ *pDst-- = (q15_t)(sum >> 15U);
+ else
+ *pDst++ = (q15_t)(sum >> 15U);
+ }
+}
+
+void ref_correlate_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch)
+{
+ q15_t *pIn1 = pSrcA; /* inputA pointer */
+ q15_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */
+ q31_t sum; /* Accumulators */
+ uint32_t i = 0U, j; /* loop counters */
+ uint32_t inv = 0U; /* Reverse order flag */
+ uint32_t tot = 0U; /* Length */
+
+ /* Calculate the length of the remaining sequence */
+ tot = ((srcALen + srcBLen) - 2U);
+
+ if (srcALen > srcBLen)
+ {
+ /* Calculating the number of zeros to be padded to the output */
+ j = srcALen - srcBLen;
+
+ /* Initialise the pointer after zero padding */
+ pDst += j;
+ }
+
+ else if (srcALen < srcBLen)
+ {
+ /* Initialization to inputB pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization to the end of inputA pointer */
+ pIn2 = pSrcA + (srcALen - 1U);
+
+ /* Initialisation of the pointer after zero padding */
+ pDst = pDst + tot;
+
+ /* Swapping the lengths */
+ j = srcALen;
+ srcALen = srcBLen;
+ srcBLen = j;
+
+ /* Setting the reverse flag */
+ inv = 1;
+
+ }
+
+ /* Loop to calculate convolution for output length number of times */
+ for (i = 0U; i <= tot; i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0U; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if ((((i - j) < srcBLen) && (j < srcALen)))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q31_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
+ }
+ }
+ /* Store the output in the destination buffer */
+ if (inv == 1)
+ *pDst-- = (q15_t) ref_sat_q15(sum >> 15U);
+ else
+ *pDst++ = (q15_t) ref_sat_q15(sum >> 15U);
+ }
+}
+
+void ref_correlate_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst)
+{
+ q7_t *pIn1 = pSrcA; /* inputA pointer */
+ q7_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */
+ q31_t sum; /* Accumulator */
+ uint32_t i = 0U, j; /* loop counters */
+ uint32_t inv = 0U; /* Reverse order flag */
+ uint32_t tot = 0U; /* Length */
+
+ /* Calculate the length of the remaining sequence */
+ tot = ((srcALen + srcBLen) - 2U);
+
+ if (srcALen > srcBLen)
+ {
+ /* Calculating the number of zeros to be padded to the output */
+ j = srcALen - srcBLen;
+
+ /* Initialise the pointer after zero padding */
+ pDst += j;
+ }
+
+ else if (srcALen < srcBLen)
+ {
+ /* Initialization to inputB pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization to the end of inputA pointer */
+ pIn2 = pSrcA + (srcALen - 1U);
+
+ /* Initialisation of the pointer after zero padding */
+ pDst = pDst + tot;
+
+ /* Swapping the lengths */
+ j = srcALen;
+ srcALen = srcBLen;
+ srcBLen = j;
+
+ /* Setting the reverse flag */
+ inv = 1;
+
+ }
+
+ /* Loop to calculate convolution for output length number of times */
+ for (i = 0U; i <= tot; i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0U; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if ((((i - j) < srcBLen) && (j < srcALen)))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q15_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
+ }
+ }
+ /* Store the output in the destination buffer */
+ if (inv == 1)
+ *pDst-- = (q7_t) __SSAT((sum >> 7U), 8U);
+ else
+ *pDst++ = (q7_t) __SSAT((sum >> 7U), 8U);
+ }
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir.c
new file mode 100644
index 0000000..3e72b87
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir.c
@@ -0,0 +1,325 @@
+#include "ref.h"
+
+void ref_fir_f32(
+ const arm_fir_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCurnt; /* Points to the current sample of the state */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i; /* Loop counters */
+ float32_t acc;
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+ while (blockSize > 0U)
+ {
+ /* Copy one sample at a time into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc = 0.0f;
+
+ for(i=0;i<numTaps;i++)
+ {
+ /* Perform the multiply-accumulates */
+ acc += pState[i] * pCoeffs[i];
+ }
+
+ /* The result is store in the destination buffer. */
+ *pDst++ = acc;
+
+ /* Advance state pointer by 1 for the next sample */
+ pState++;
+
+ blockSize--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the starting of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ /* Copy data */
+ for(i=0;i<numTaps-1;i++)
+ {
+ pStateCurnt[i] = pState[i];
+ }
+}
+
+void ref_fir_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i; /* Loop counters */
+ q63_t acc;
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+ while (blockSize > 0U)
+ {
+ /* Copy one sample at a time into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc = 0.0f;
+
+ for(i=0;i<numTaps;i++)
+ {
+ /* Perform the multiply-accumulates */
+ acc += (q63_t)pState[i] * pCoeffs[i];
+ }
+
+ /* The result is store in the destination buffer. */
+ *pDst++ = (q31_t)(acc >> 31);
+
+ /* Advance state pointer by 1 for the next sample */
+ pState++;
+
+ blockSize--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the starting of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ /* Copy data */
+ for(i=0;i<numTaps-1;i++)
+ {
+ pStateCurnt[i] = pState[i];
+ }
+}
+
+void ref_fir_fast_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i; /* Loop counters */
+ q31_t acc;
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+ while (blockSize > 0U)
+ {
+ /* Copy one sample at a time into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc = 0.0f;
+
+ for(i=0;i<numTaps;i++)
+ {
+ /* Perform the multiply-accumulates */
+ acc = (q31_t) (((((q63_t) acc) << 32) + ((q63_t) pState[i] * pCoeffs[i]) + 0x80000000LL ) >> 32);
+ }
+
+ /* The result is store in the destination buffer. */
+ *pDst++ = (q31_t)(acc << 1);
+
+ /* Advance state pointer by 1 for the next sample */
+ pState++;
+
+ blockSize--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the starting of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ /* Copy data */
+ for(i=0;i<numTaps-1;i++)
+ {
+ pStateCurnt[i] = pState[i];
+ }
+}
+
+void ref_fir_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i; /* Loop counters */
+ q63_t acc;
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+ while (blockSize > 0U)
+ {
+ /* Copy one sample at a time into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc = 0.0f;
+
+ for(i=0;i<numTaps;i++)
+ {
+ /* Perform the multiply-accumulates */
+ acc += (q31_t)pState[i] * pCoeffs[i];
+ }
+
+ /* The result is store in the destination buffer. */
+ *pDst++ = ref_sat_q15(acc >> 15);
+
+ /* Advance state pointer by 1 for the next sample */
+ pState++;
+
+ blockSize--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the starting of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ /* Copy data */
+ for(i=0;i<numTaps;i++)
+ {
+ pStateCurnt[i] = pState[i];
+ }
+}
+
+void ref_fir_fast_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i; /* Loop counters */
+ q31_t acc;
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+ while (blockSize > 0U)
+ {
+ /* Copy one sample at a time into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc = 0.0f;
+
+ for(i=0;i<numTaps;i++)
+ {
+ /* Perform the multiply-accumulates */
+ acc += (q31_t)pState[i] * pCoeffs[i];
+ }
+
+ /* The result is store in the destination buffer. */
+ *pDst++ = ref_sat_q15(acc >> 15);
+
+ /* Advance state pointer by 1 for the next sample */
+ pState++;
+
+ blockSize--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the starting of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ /* Copy data */
+ for(i=0;i<numTaps-1;i++)
+ {
+ pStateCurnt[i] = pState[i];
+ }
+}
+
+void ref_fir_q7(
+ const arm_fir_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ q7_t *pState = S->pState; /* State pointer */
+ q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q7_t *pStateCurnt; /* Points to the current sample of the state */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i; /* Loop counters */
+ q31_t acc;
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+ while (blockSize > 0U)
+ {
+ /* Copy one sample at a time into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc = 0.0f;
+
+ for(i=0;i<numTaps;i++)
+ {
+ /* Perform the multiply-accumulates */
+ acc += (q31_t)pState[i] * pCoeffs[i];
+ }
+
+ /* The result is store in the destination buffer. */
+ *pDst++ = ref_sat_q7(acc >> 7);
+
+ /* Advance state pointer by 1 for the next sample */
+ pState++;
+
+ blockSize--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the starting of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ /* Copy data */
+ for(i=0;i<numTaps-1;i++)
+ {
+ pStateCurnt[i] = pState[i];
+ }
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_decimate.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_decimate.c
new file mode 100644
index 0000000..7cbf127
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_decimate.c
@@ -0,0 +1,386 @@
+#include "ref.h"
+
+void ref_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCurnt; /* Points to the current sample of the state */
+ float32_t sum0; /* Accumulator */
+ float32_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i, blkCnt; /* Loop counters */
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + numTaps - 1U;
+
+ /* Total number of output samples to be computed */
+ blkCnt = blockSize / S->M;
+
+ while (blkCnt > 0U)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+ } while (--i);
+
+ /* Set accumulator to zero */
+ sum0 = 0.0f;
+
+ for(i=0;i<numTaps;i++)
+ {
+ /* Read coefficients */
+ c0 = pCoeffs[i];
+
+ /* Fetch 1 state variable */
+ x0 = pState[i];
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState += S->M;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = sum0;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the start of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ /* Copy numTaps number of values */
+ i = numTaps - 1U;
+
+ /* copy data */
+ while (i > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+}
+
+void ref_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+ q31_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ q63_t sum0; /* Accumulator */
+ uint32_t numTaps = S->numTaps; /* Number of taps */
+ uint32_t i, blkCnt; /* Loop counters */
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + numTaps - 1U;
+
+ /* Total number of output samples to be computed */
+ blkCnt = blockSize / S->M;
+
+ while (blkCnt > 0U)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while (--i);
+
+ /* Set accumulator to zero */
+ sum0 = 0;
+
+ for(i=0;i<numTaps;i++)
+ {
+ /* Read coefficients */
+ c0 = pCoeffs[i];
+
+ /* Fetch 1 state variable */
+ x0 = pState[i];
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t)x0 * c0;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = (q31_t) (sum0 >> 31);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the start of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = numTaps - 1U;
+
+ /* copy data */
+ while (i > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+}
+
+void ref_fir_decimate_fast_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+ q31_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ q31_t sum0; /* Accumulator */
+ uint32_t numTaps = S->numTaps; /* Number of taps */
+ uint32_t i, blkCnt; /* Loop counters */
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + numTaps - 1U;
+
+ /* Total number of output samples to be computed */
+ blkCnt = blockSize / S->M;
+
+ while (blkCnt > 0U)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while (--i);
+
+ /* Set accumulator to zero */
+ sum0 = 0;
+
+ for(i=0;i<numTaps;i++)
+ {
+ /* Read coefficients */
+ c0 = pCoeffs[i];
+
+ /* Fetch 1 state variable */
+ x0 = pState[i];
+
+ /* Perform the multiply-accumulate */
+ sum0 = (q31_t)((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = (q31_t) (sum0 << 1);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the start of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = numTaps - 1U;
+
+ /* copy data */
+ while (i > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+}
+
+void ref_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q31_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ q63_t sum0; /* Accumulator */
+ uint32_t numTaps = S->numTaps; /* Number of taps */
+ uint32_t i, blkCnt; /* Loop counters */
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + numTaps - 1U;
+
+ /* Total number of output samples to be computed */
+ blkCnt = blockSize / S->M;
+
+ while (blkCnt > 0U)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while (--i);
+
+ /* Set accumulator to zero */
+ sum0 = 0;
+
+ for(i=0;i<numTaps;i++)
+ {
+ /* Read coefficients */
+ c0 = pCoeffs[i];
+
+ /* Fetch 1 state variable */
+ x0 = pState[i];
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q31_t)x0 * c0;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = ref_sat_q15(sum0 >> 15);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the start of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = numTaps - 1U;
+
+ /* copy data */
+ while (i > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+}
+
+void ref_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ q31_t sum0; /* Accumulator */
+ uint32_t numTaps = S->numTaps; /* Number of taps */
+ uint32_t i, blkCnt; /* Loop counters */
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + numTaps - 1U;
+
+ /* Total number of output samples to be computed */
+ blkCnt = blockSize / S->M;
+
+ while (blkCnt > 0U)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while (--i);
+
+ /* Set accumulator to zero */
+ sum0 = 0;
+
+ for(i=0;i<numTaps;i++)
+ {
+ /* Read coefficients */
+ c0 = pCoeffs[i];
+
+ /* Fetch 1 state variable */
+ x0 = pState[i];
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = ref_sat_q15(sum0 >> 15);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the start of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = numTaps - 1U;
+
+ /* copy data */
+ while (i > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+}
+
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_interpolate.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_interpolate.c
new file mode 100644
index 0000000..8abb089
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_interpolate.c
@@ -0,0 +1,291 @@
+#include "ref.h"
+
+void ref_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCurnt; /* Points to the current sample of the state */
+ float32_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */
+ float32_t sum; /* Accumulator */
+ uint32_t i, blkCnt; /* Loop counters */
+ uint16_t phaseLen = S->phaseLength, tapCnt; /* Length of each polyphase filter component */
+
+
+ /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + phaseLen - 1;
+
+ /* Total number of intput samples */
+ blkCnt = blockSize;
+
+ /* Loop over the blockSize. */
+ while (blkCnt > 0U)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Loop over the Interpolation factor. */
+ i = S->L;
+
+ while (i > 0U)
+ {
+ /* Set accumulator to zero */
+ sum = 0.0f;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + i - 1;
+
+ /* Loop over the polyPhase length */
+ tapCnt = phaseLen;
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *ptr1++ * *ptr2;
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = sum;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last phaseLen - 1 samples to the start of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ tapCnt = phaseLen - 1U;
+
+ while (tapCnt > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+}
+
+void ref_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+ q31_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */
+
+ /* Run the below code for Cortex-M0 */
+
+ q63_t sum; /* Accumulator */
+ q31_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t i, blkCnt; /* Loop counters */
+ uint16_t phaseLen = S->phaseLength, tapCnt; /* Length of each polyphase filter component */
+
+
+ /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (q31_t)phaseLen - 1;
+
+ /* Total number of intput samples */
+ blkCnt = blockSize;
+
+ /* Loop over the blockSize. */
+ while (blkCnt > 0U)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Loop over the Interpolation factor. */
+ i = S->L;
+
+ while (i > 0U)
+ {
+ /* Set accumulator to zero */
+ sum = 0;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + i - 1;
+
+ tapCnt = phaseLen;
+
+ while (tapCnt > 0U)
+ {
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *ptr1++;
+
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) x0 *c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = (q31_t)(sum >> 31);
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ tapCnt = phaseLen - 1U;
+
+ /* copy data */
+ while (tapCnt > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+}
+
+void ref_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */
+ q63_t sum; /* Accumulator */
+ q15_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t i, blkCnt, tapCnt; /* Loop counters */
+ uint16_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */
+
+
+ /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + phaseLen - 1;
+
+ /* Total number of intput samples */
+ blkCnt = blockSize;
+
+ /* Loop over the blockSize. */
+ while (blkCnt > 0U)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Loop over the Interpolation factor. */
+ i = S->L;
+
+ while (i > 0U)
+ {
+ /* Set accumulator to zero */
+ sum = 0;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + i - 1;
+
+ /* Loop over the polyPhase length */
+ tapCnt = (uint32_t)phaseLen;
+
+ while (tapCnt > 0U)
+ {
+ /* Read the coefficient */
+ c0 = *ptr2;
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *ptr1++;
+
+ /* Perform the multiply-accumulate */
+ sum += (q31_t) x0 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Store the result after converting to 1.15 format in the destination buffer */
+ *pDst++ = ref_sat_q15(sum >> 15);
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last phaseLen - 1 samples to the start of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = (uint32_t) phaseLen - 1U;
+
+ while (i > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_lattice.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_lattice.c
new file mode 100644
index 0000000..6466106
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_lattice.c
@@ -0,0 +1,241 @@
+#include "ref.h"
+
+void ref_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *px; /* temporary state pointer */
+ float32_t *pk; /* temporary coefficient pointer */
+ float32_t fcurr, fnext, gcurr, gnext; /* temporary variables */
+ uint32_t numStages = S->numStages; /* Length of the filter */
+ uint32_t blkCnt, stageCnt; /* temporary variables for counts */
+
+ pState = &S->pState[0];
+
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* f0(n) = x(n) */
+ fcurr = *pSrc++;
+
+ /* Initialize coeff pointer */
+ pk = pCoeffs;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* read g0(n-1) from state buffer */
+ gcurr = *px;
+
+ /* for sample 1 processing */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext = fcurr + ((*pk) * gcurr);
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext = (fcurr * (*pk++)) + gcurr;
+
+ /* save f0(n) in state buffer */
+ *px++ = fcurr;
+
+ /* f1(n) is saved in fcurr
+ for next stage processing */
+ fcurr = fnext;
+
+ stageCnt = (numStages - 1U);
+
+ /* stage loop */
+ while (stageCnt > 0U)
+ {
+ /* read g2(n) from state buffer */
+ gcurr = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = gnext;
+
+ /* Sample processing for K2, K3.... */
+ /* f2(n) = f1(n) + K2 * g1(n-1) */
+ fnext = fcurr + ((*pk) * gcurr);
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ gnext = (fcurr * (*pk++)) + gcurr;
+
+ /* f1(n) is saved in fcurr1
+ for next stage processing */
+ fcurr = fnext;
+
+ stageCnt--;
+ }
+
+ /* y(n) = fN(n) */
+ *pDst++ = fcurr;
+
+ blkCnt--;
+ }
+}
+
+void ref_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *px; /* temporary state pointer */
+ q31_t *pk; /* temporary coefficient pointer */
+ q31_t fcurr, fnext, gcurr, gnext; /* temporary variables */
+ uint32_t numStages = S->numStages; /* Length of the filter */
+ uint32_t blkCnt, stageCnt; /* temporary variables for counts */
+
+ pState = &S->pState[0];
+
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* f0(n) = x(n) */
+ fcurr = *pSrc++;
+
+ /* Initialize coeff pointer */
+ pk = pCoeffs;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* read g0(n-1) from state buffer */
+ gcurr = *px;
+
+ /* for sample 1 processing */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext = (q31_t) (((q63_t) gcurr * (*pk)) >> 31) + fcurr;
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext = (q31_t) (((q63_t) fcurr * (*pk++)) >> 31) + gcurr;
+ /* save g1(n) in state buffer */
+ *px++ = fcurr;
+
+ /* f1(n) is saved in fcurr1
+ for next stage processing */
+ fcurr = fnext;
+
+ stageCnt = (numStages - 1U);
+
+ /* stage loop */
+ while (stageCnt > 0U)
+ {
+ /* read g2(n) from state buffer */
+ gcurr = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = gnext;
+
+ /* Sample processing for K2, K3.... */
+ /* f2(n) = f1(n) + K2 * g1(n-1) */
+ fnext = (q31_t) (((q63_t) gcurr * (*pk)) >> 31) + fcurr;
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ gnext = (q31_t) (((q63_t) fcurr * (*pk++)) >> 31) + gcurr;
+
+ /* f1(n) is saved in fcurr1
+ for next stage processing */
+ fcurr = fnext;
+
+ stageCnt--;
+
+ }
+
+ /* y(n) = fN(n) */
+ *pDst++ = fcurr;
+
+ blkCnt--;
+
+ }
+}
+
+void ref_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *px; /* temporary state pointer */
+ q15_t *pk; /* temporary coefficient pointer */
+ q31_t fcurnt, fnext, gcurnt, gnext; /* temporary variables */
+ uint32_t numStages = S->numStages; /* Length of the filter */
+ uint32_t blkCnt, stageCnt; /* temporary variables for counts */
+
+ pState = &S->pState[0];
+
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* f0(n) = x(n) */
+ fcurnt = *pSrc++;
+
+ /* Initialize coeff pointer */
+ pk = (pCoeffs);
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* read g0(n-1) from state buffer */
+ gcurnt = *px;
+
+ /* for sample 1 processing */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext = ((gcurnt * (*pk)) >> 15U) + fcurnt;
+ fnext = ref_sat_q15(fnext);
+
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext = ((fcurnt * (*pk++)) >> 15U) + gcurnt;
+ gnext = ref_sat_q15(gnext);
+
+ /* save f0(n) in state buffer */
+ *px++ = (q15_t) fcurnt;
+
+ /* f1(n) is saved in fcurnt
+ for next stage processing */
+ fcurnt = fnext;
+
+ stageCnt = (numStages - 1U);
+
+ /* stage loop */
+ while (stageCnt > 0U)
+ {
+ /* read g1(n-1) from state buffer */
+ gcurnt = *px;
+
+ /* save g0(n-1) in state buffer */
+ *px++ = (q15_t) gnext;
+
+ /* Sample processing for K2, K3.... */
+ /* f2(n) = f1(n) + K2 * g1(n-1) */
+ fnext = ((gcurnt * (*pk)) >> 15U) + fcurnt;
+ fnext = ref_sat_q15(fnext);
+
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ gnext = ((fcurnt * (*pk++)) >> 15U) + gcurnt;
+ gnext = ref_sat_q15(gnext);
+
+
+ /* f1(n) is saved in fcurnt
+ for next stage processing */
+ fcurnt = fnext;
+
+ stageCnt--;
+
+ }
+
+ /* y(n) = fN(n) */
+ *pDst++ = ref_sat_q15(fcurnt);
+
+
+ blkCnt--;
+
+ }
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_sparse.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_sparse.c
new file mode 100644
index 0000000..0638313
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_sparse.c
@@ -0,0 +1,485 @@
+#include "ref.h"
+
+void ref_fir_sparse_f32(
+ arm_fir_sparse_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *px; /* Scratch buffer pointer */
+ float32_t *py = pState; /* Temporary pointers for state buffer */
+ float32_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */
+ float32_t *pOut; /* Destination pointer */
+ int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */
+ uint32_t delaySize = S->maxDelay + blockSize; /* state length */
+ uint16_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ int32_t readIndex; /* Read index of the state buffer */
+ uint32_t tapCnt, blkCnt; /* loop counters */
+ float32_t coeff = *pCoeffs++; /* Read the first coefficient value */
+
+
+ /* BlockSize of Input samples are copied into the state buffer */
+ /* StateIndex points to the starting position to write in the state buffer */
+ arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1,
+ (int32_t *) pSrc, 1, blockSize);
+
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if (readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+ (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+ blockSize);
+
+ /* Working pointer for the scratch buffer */
+ px = pb;
+
+ /* Working pointer for destination buffer */
+ pOut = pDst;
+
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* Perform Multiplications and store in destination buffer */
+ *pOut++ = *px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Loop over the number of taps. */
+ tapCnt = (uint32_t) numTaps - 1U;
+
+ while (tapCnt > 0U)
+ {
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if (readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+ (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+ blockSize);
+
+ /* Working pointer for the scratch buffer */
+ px = pb;
+
+ /* Working pointer for destination buffer */
+ pOut = pDst;
+
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* Perform Multiply-Accumulate */
+ *pOut++ += *px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Decrement the tap loop counter */
+ tapCnt--;
+ }
+}
+
+void ref_fir_sparse_q31(
+ arm_fir_sparse_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *px; /* Scratch buffer pointer */
+ q31_t *py = pState; /* Temporary pointers for state buffer */
+ q31_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */
+ q31_t *pOut; /* Destination pointer */
+ q63_t out; /* Temporary output variable */
+ int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */
+ uint32_t delaySize = S->maxDelay + blockSize; /* state length */
+ uint16_t numTaps = S->numTaps; /* Filter order */
+ int32_t readIndex; /* Read index of the state buffer */
+ uint32_t tapCnt, blkCnt; /* loop counters */
+ q31_t coeff = *pCoeffs++; /* Read the first coefficient value */
+ q31_t in;
+
+
+ /* BlockSize of Input samples are copied into the state buffer */
+ /* StateIndex points to the starting position to write in the state buffer */
+ arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1,
+ (int32_t *) pSrc, 1, blockSize);
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if (readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+ (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+ blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pOut = pDst;
+
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* Perform Multiplications and store in the destination buffer */
+ *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Loop over the number of taps. */
+ tapCnt = (uint32_t) numTaps - 1U;
+
+ while (tapCnt > 0U)
+ {
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if (readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+ (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+ blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pOut = pDst;
+
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* Perform Multiply-Accumulate */
+ out = *pOut;
+ out += ((q63_t) * px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Decrement the tap loop counter */
+ tapCnt--;
+ }
+
+ /* Working output pointer is updated */
+ pOut = pDst;
+
+ /* Output is converted into 1.31 format. */
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ in = *pOut << 1;
+ *pOut++ = in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+void ref_fir_sparse_q15(
+ arm_fir_sparse_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pIn = pSrc; /* Working pointer for input */
+ q15_t *pOut = pDst; /* Working pointer for output */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *px; /* Temporary pointers for scratch buffer */
+ q15_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */
+ q15_t *py = pState; /* Temporary pointers for state buffer */
+ int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */
+ uint32_t delaySize = S->maxDelay + blockSize; /* state length */
+ uint16_t numTaps = S->numTaps; /* Filter order */
+ int32_t readIndex; /* Read index of the state buffer */
+ uint32_t tapCnt, blkCnt; /* loop counters */
+ q15_t coeff = *pCoeffs++; /* Read the first coefficient value */
+ q31_t *pScr2 = pScratchOut; /* Working pointer for pScratchOut */
+
+ /* BlockSize of Input samples are copied into the state buffer */
+ /* StateIndex points to the starting position to write in the state buffer */
+ arm_circularWrite_q15(py, delaySize, &S->stateIndex, 1, pIn, 1, blockSize);
+
+ /* Loop over the number of taps. */
+ tapCnt = numTaps;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if (readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q15(py, delaySize, &readIndex, 1,
+ pb, pb, blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* Perform multiplication and store in the scratch buffer */
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Loop over the number of taps. */
+ tapCnt = (uint32_t) numTaps - 1U;
+
+ while (tapCnt > 0U)
+ {
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if (readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q15(py, delaySize, &readIndex, 1,
+ pb, pb, blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* Perform Multiply-Accumulate */
+ *pScratchOut++ += (q31_t) * px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Decrement the tap loop counter */
+ tapCnt--;
+ }
+
+ /* All the output values are in pScratchOut buffer.
+ Convert them into 1.15 format, saturate and store in the destination buffer. */
+ /* Loop over the blockSize. */
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16);
+ blkCnt--;
+ }
+}
+
+void ref_fir_sparse_q7(
+ arm_fir_sparse_instance_q7 * S,
+ q7_t *pSrc,
+ q7_t *pDst,
+ q7_t *pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize)
+{
+ q7_t *pState = S->pState; /* State pointer */
+ q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q7_t *px; /* Scratch buffer pointer */
+ q7_t *py = pState; /* Temporary pointers for state buffer */
+ q7_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */
+ q7_t *pOut = pDst; /* Destination pointer */
+ int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */
+ uint32_t delaySize = S->maxDelay + blockSize; /* state length */
+ uint16_t numTaps = S->numTaps; /* Filter order */
+ int32_t readIndex; /* Read index of the state buffer */
+ uint32_t tapCnt, blkCnt; /* loop counters */
+ q7_t coeff = *pCoeffs++; /* Read the coefficient value */
+ q31_t *pScr2 = pScratchOut; /* Working pointer for scratch buffer of output values */
+ q31_t in;
+
+ /* BlockSize of Input samples are copied into the state buffer */
+ /* StateIndex points to the starting position to write in the state buffer */
+ arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1,
+ blockSize);
+
+ /* Loop over the number of taps. */
+ tapCnt = numTaps;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if (readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+ (int32_t) blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+ /* Loop over the blockSize */
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* Perform multiplication and store in the scratch buffer */
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Loop over the number of taps. */
+ tapCnt = (uint32_t) numTaps - 1U;
+
+ while (tapCnt > 0U)
+ {
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if (readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+ (int32_t) blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+ /* Loop over the blockSize */
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* Perform Multiply-Accumulate */
+ in = *pScratchOut + ((q31_t) * px++ * coeff);
+ *pScratchOut++ = in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Decrement the tap loop counter */
+ tapCnt--;
+ }
+
+ /* All the output values are in pScratchOut buffer.
+ Convert them into 1.15 format, saturate and store in the destination buffer. */
+ /* Loop over the blockSize. */
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/iir_lattice.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/iir_lattice.c
new file mode 100644
index 0000000..ab37d5f
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/iir_lattice.c
@@ -0,0 +1,271 @@
+#include "ref.h"
+
+void ref_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t fcurr, fnext = 0, gcurr, gnext; /* Temporary variables for lattice stages */
+ float32_t acc; /* Accumlator */
+ uint32_t blkCnt, tapCnt; /* temporary variables for counts */
+ float32_t *px1, *px2, *pk, *pv; /* temporary pointers for state and coef */
+ uint32_t numStages = S->numStages; /* number of stages */
+ float32_t *pState; /* State pointer */
+ float32_t *pStateCurnt; /* State current pointer */
+
+ blkCnt = blockSize;
+ pState = &S->pState[0];
+
+ /* Sample processing */
+ while (blkCnt > 0U)
+ {
+ /* Read Sample from input buffer */
+ /* fN(n) = x(n) */
+ fcurr = *pSrc++;
+
+ /* Initialize state read pointer */
+ px1 = pState;
+ /* Initialize state write pointer */
+ px2 = pState;
+ /* Set accumulator to zero */
+ acc = 0.0f;
+ /* Initialize Ladder coeff pointer */
+ pv = &S->pvCoeffs[0];
+ /* Initialize Reflection coeff pointer */
+ pk = &S->pkCoeffs[0];
+
+ /* Process sample for numStages */
+ tapCnt = numStages;
+
+ while (tapCnt > 0U)
+ {
+ gcurr = *px1++;
+ /* Process sample for last taps */
+ fnext = fcurr - (*pk) * gcurr;
+ gnext = fnext * (*pk++) + gcurr;
+
+ /* Output samples for last taps */
+ acc += gnext * (*pv++);
+ *px2++ = gnext;
+ fcurr = fnext;
+
+ /* Decrementing loop counter */
+ tapCnt--;
+ }
+
+ /* y(n) += g0(n) * v0 */
+ acc += fnext * (*pv);
+
+ *px2++ = fnext;
+
+ /* write out into pDst */
+ *pDst++ = acc;
+
+ /* Advance the state pointer by 1 to process the next group of samples */
+ pState = pState + 1U;
+ blkCnt--;
+ }
+
+ /* Processing is complete. Now copy last S->numStages samples to start of the buffer
+ for the preperation of next frame process */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = &S->pState[0];
+ pState = &S->pState[blockSize];
+
+ tapCnt = numStages;
+
+ /* Copy the data */
+ while (tapCnt > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+}
+
+void ref_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t fcurr, fnext = 0, gcurr = 0, gnext; /* Temporary variables for lattice stages */
+ q63_t acc; /* Accumlator */
+ uint32_t blkCnt, tapCnt; /* Temporary variables for counts */
+ q31_t *px1, *px2, *pk, *pv; /* Temporary pointers for state and coef */
+ uint32_t numStages = S->numStages; /* number of stages */
+ q31_t *pState; /* State pointer */
+ q31_t *pStateCurnt; /* State current pointer */
+
+ blkCnt = blockSize;
+ pState = &S->pState[0];
+
+ /* Sample processing */
+ while (blkCnt > 0U)
+ {
+ /* Read Sample from input buffer */
+ /* fN(n) = x(n) */
+ fcurr = *pSrc++;
+
+ /* Initialize state read pointer */
+ px1 = pState;
+ /* Initialize state write pointer */
+ px2 = pState;
+ /* Set accumulator to zero */
+ acc = 0;
+ /* Initialize Ladder coeff pointer */
+ pv = &S->pvCoeffs[0];
+ /* Initialize Reflection coeff pointer */
+ pk = &S->pkCoeffs[0];
+
+ tapCnt = numStages;
+
+ while (tapCnt > 0U)
+ {
+ gcurr = *px1++;
+ /* Process sample */
+ /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+ fnext =
+ ref_sat_q31(((q63_t) fcurr -
+ ((q31_t) (((q63_t) gcurr * (*pk)) >> 31))));
+ /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+ gnext =
+ ref_sat_q31(((q63_t) gcurr +
+ ((q31_t) (((q63_t) fnext * (*pk++)) >> 31))));
+ /* Output samples */
+ /* y(n) += gN(n) * vN */
+ acc += ((q63_t) gnext * *pv++);
+ /* write gN-1(n-1) into state for next sample processing */
+ *px2++ = gnext;
+ /* Update f values for next coefficient processing */
+ fcurr = fnext;
+
+ tapCnt--;
+ }
+
+ /* y(n) += g0(n) * v0 */
+ acc += (q63_t) fnext *(*pv++);
+
+ *px2++ = fnext;
+
+ /* write out into pDst */
+ *pDst++ = (q31_t) (acc >> 31U);
+
+ /* Advance the state pointer by 1 to process the next group of samples */
+ pState = pState + 1U;
+ blkCnt--;
+ }
+
+ /* Processing is complete. Now copy last S->numStages samples to start of the buffer
+ for the preperation of next frame process */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = &S->pState[0];
+ pState = &S->pState[blockSize];
+
+ tapCnt = numStages;
+
+ /* Copy the remaining q31_t data */
+ while (tapCnt > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+}
+
+void ref_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t fcurr, fnext = 0, gcurr = 0, gnext; /* Temporary variables for lattice stages */
+ uint32_t stgCnt; /* Temporary variables for counts */
+ q63_t acc; /* Accumlator */
+ uint32_t blkCnt, tapCnt; /* Temporary variables for counts */
+ q15_t *px1, *px2, *pk, *pv; /* temporary pointers for state and coef */
+ uint32_t numStages = S->numStages; /* number of stages */
+ q15_t *pState; /* State pointer */
+ q15_t *pStateCurnt; /* State current pointer */
+ q15_t out; /* Temporary variable for output */
+
+ blkCnt = blockSize;
+ pState = &S->pState[0];
+
+ /* Sample processing */
+ while (blkCnt > 0U)
+ {
+ /* Read Sample from input buffer */
+ /* fN(n) = x(n) */
+ fcurr = *pSrc++;
+
+ /* Initialize state read pointer */
+ px1 = pState;
+ /* Initialize state write pointer */
+ px2 = pState;
+ /* Set accumulator to zero */
+ acc = 0;
+ /* Initialize Ladder coeff pointer */
+ pv = &S->pvCoeffs[0];
+ /* Initialize Reflection coeff pointer */
+ pk = &S->pkCoeffs[0];
+
+ tapCnt = numStages;
+
+ while (tapCnt > 0U)
+ {
+ gcurr = *px1++;
+ /* Process sample */
+ /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+ fnext = fcurr - ((gcurr * (*pk)) >> 15);
+ fnext = ref_sat_q15(fnext);
+ /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+ gnext = ((fnext * (*pk++)) >> 15) + gcurr;
+ gnext = ref_sat_q15(gnext);
+ /* Output samples */
+ /* y(n) += gN(n) * vN */
+ acc += (q31_t) ((gnext * (*pv++)));
+ /* write gN(n) into state for next sample processing */
+ *px2++ = (q15_t) gnext;
+ /* Update f values for next coefficient processing */
+ fcurr = fnext;
+
+ tapCnt--;
+ }
+
+ /* y(n) += g0(n) * v0 */
+ acc += (q31_t) ((fnext * (*pv++)));
+
+ out = ref_sat_q15(acc >> 15);
+ *px2++ = (q15_t) fnext;
+
+ /* write out into pDst */
+ *pDst++ = out;
+
+ /* Advance the state pointer by 1 to process the next group of samples */
+ pState = pState + 1U;
+ blkCnt--;
+ }
+
+ /* Processing is complete. Now copy last S->numStages samples to start of the buffer
+ for the preperation of next frame process */
+ /* Points to the start of the state buffer */
+ pStateCurnt = &S->pState[0];
+ pState = &S->pState[blockSize];
+
+ stgCnt = numStages;
+
+ /* copy data */
+ while (stgCnt > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ stgCnt--;
+ }
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/lms.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/lms.c
new file mode 100644
index 0000000..fee99f9
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/lms.c
@@ -0,0 +1,695 @@
+#include "ref.h"
+
+void ref_lms_f32(
+ const arm_lms_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCurnt; /* Points to the current sample of the state */
+ float32_t mu = S->mu; /* Adaptive factor */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i, blkCnt; /* Loop counters */
+ float32_t sum, e, d; /* accumulator, error, reference data sample */
+ float32_t w = 0.0f; /* weight factor */
+
+ e = 0.0f;
+ d = 0.0f;
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[numTaps - 1U]);
+
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ sum = 0.0f;
+
+ for(i=0;i<numTaps;i++)
+ { /* Perform the multiply-accumulate */
+ sum += pState[i] * pCoeffs[i];
+ }
+
+ /* The result is stored in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Compute and store error */
+ d = *pRef++;
+ e = d - sum;
+ *pErr++ = e;
+
+ /* Weighting factor for the LMS version */
+ w = e * mu;
+
+ for(i=0;i<numTaps;i++)
+ { /* Perform the multiply-accumulate */
+ pCoeffs[i] += w * pState[i];
+ }
+
+ /* Advance state pointer by 1 for the next sample */
+ pState++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ * start of the state buffer. This prepares the state buffer for the
+ * next function call. */
+ for(i=0;i<numTaps-1;i++)
+ {
+ S->pState[i] = pState[i];
+ }
+}
+
+void ref_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCurnt; /* Points to the current sample of the state */
+ float32_t mu = S->mu; /* Adaptive factor */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i, blkCnt; /* Loop counters */
+ float32_t energy; /* Energy of the input */
+ float32_t sum, e, d; /* accumulator, error, reference data sample */
+ float32_t w, x0, in; /* weight factor, temporary variable to hold input sample and state */
+
+ /* Initializations of error, difference, Coefficient update */
+ e = 0.0f;
+ d = 0.0f;
+ w = 0.0f;
+
+ energy = S->energy;
+ x0 = S->x0;
+
+ /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[numTaps - 1U]);
+
+ for(blkCnt = blockSize; blkCnt > 0U; blkCnt--)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc;
+
+ /* Read the sample from input buffer */
+ in = *pSrc++;
+
+ /* Update the energy calculation */
+ energy -= x0 * x0;
+ energy += in * in;
+
+ /* Set the accumulator to zero */
+ sum = 0.0f;
+
+ for(i=0;i<numTaps;i++)
+ { /* Perform the multiply-accumulate */
+ sum += pState[i] * pCoeffs[i];
+ }
+
+ /* The result in the accumulator is stored in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Compute and store error */
+ d = *pRef++;
+ e = d - sum;
+ *pErr++ = e;
+
+ /* Calculation of Weighting factor for updating filter coefficients */
+ /* epsilon value 0.000000119209289f */
+ w = e * mu / (energy + 0.000000119209289f);
+
+ for(i=0;i<numTaps;i++)
+ {
+ /* Perform the multiply-accumulate */
+ pCoeffs[i] += w * pState[i];
+ }
+
+ x0 = *pState;
+
+ /* Advance state pointer by 1 for the next sample */
+ pState++;
+ }
+
+ S->energy = energy;
+ S->x0 = x0;
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ * start of the state buffer. This prepares the state buffer for the
+ * next function call. */
+ for(i=0;i<numTaps-1;i++)
+ {
+ S->pState[i] = pState[i];
+ }
+}
+
+void ref_lms_q31(
+ const arm_lms_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+ q31_t mu = S->mu; /* Adaptive factor */
+ q31_t *px; /* Temporary pointer for state */
+ q31_t *pb; /* Temporary pointer for coefficient buffer */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+ q63_t acc; /* Accumulator */
+ q31_t e = 0; /* error of data sample */
+ q31_t alpha; /* Intermediate constant for taps update */
+ q31_t coef; /* Temporary variable for coef */
+ q31_t acc_l, acc_h; /* temporary input */
+ uint32_t uShift = (uint32_t)S->postShift + 1;
+ uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */
+
+ /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+ for(blkCnt = blockSize; blkCnt > 0U; blkCnt--)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize pCoeffs pointer */
+ pb = pCoeffs;
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ acc += (q63_t)(*px++) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Converting the result to 1.31 format */
+ /* Store the result from accumulator into the destination buffer. */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ acc = (uint32_t)acc_l >> lShift | acc_h << uShift;
+
+ *pOut++ = (q31_t)acc;
+
+ /* Compute and store error */
+ e = *pRef++ - (q31_t)acc;
+
+ *pErr++ = (q31_t)e;
+
+ /* Weighting factor for the LMS version */
+ alpha = (q31_t)(((q63_t)e * mu) >> 31);
+
+ /* Initialize pState pointer */
+ /* Advance state pointer by 1 for the next sample */
+ px = pState++;
+
+ /* Initialize pCoeffs pointer */
+ pb = pCoeffs;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ coef = (q31_t)(((q63_t) alpha * (*px++)) >> 32);
+ *pb = ref_sat_q31((q63_t)*pb + (coef << 1));
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+ }
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ start of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Copy (numTaps - 1U) samples */
+ tapCnt = numTaps - 1;
+
+ /* Copy the data */
+ while (tapCnt > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+}
+
+void ref_lms_norm_q31(
+ arm_lms_norm_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+ q31_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
+ q31_t mu = S->mu; /* Adaptive factor */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+ q63_t energy; /* Energy of the input */
+ q63_t acc; /* Accumulator */
+ q31_t e = 0, d = 0; /* error, reference data sample */
+ q31_t w = 0, in; /* weight factor and state */
+ q31_t x0; /* temporary variable to hold input sample */
+ q63_t errorXmu; /* Temporary variables to store error and mu product and reciprocal of energy */
+ q31_t coef; /* Temporary variable for coef */
+ q31_t acc_l, acc_h; /* temporary input */
+ uint32_t uShift = ((uint32_t) S->postShift + 1U);
+ uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */
+
+ energy = S->energy;
+ x0 = S->x0;
+
+ /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+ for(blkCnt = blockSize; blkCnt > 0U; blkCnt--)
+ {
+
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize pCoeffs pointer */
+ pb = pCoeffs;
+
+ /* Read the sample from input buffer */
+ in = *pSrc++;
+
+ /* Update the energy calculation */
+ energy = (q31_t)((((q63_t)energy << 32) - (((q63_t)x0 * x0) << 1)) >> 32) & 0xffffffff;
+ energy = (q31_t)(((((q63_t)in * in) << 1) + ((q63_t)energy << 32)) >> 32) & 0xffffffff;
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Converting the result to 1.31 format */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ acc = (uint32_t)acc_l >> lShift | acc_h << uShift;
+
+ /* Store the result from accumulator into the destination buffer. */
+ *pOut++ = (q31_t)acc;
+
+ /* Compute and store error */
+ d = *pRef++;
+ e = d - (q31_t)acc;
+ *pErr++ = e;
+
+ /* Calculation of product of (e * mu) */
+ errorXmu = (q63_t)e * mu;
+
+ /* Weighting factor for the normalized version */
+ w = ref_sat_q31(errorXmu / (energy + DELTA_Q31));
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ /* coef is in 2.30 format */
+ coef = (q31_t)(((q63_t)w * (*px++)) >> 32);
+ /* get coef in 1.31 format by left shifting */
+ *pb = ref_sat_q31((q63_t)*pb + (coef << 1U));
+ /* update coefficient buffer to next coefficient */
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Read the sample from state buffer */
+ x0 = *pState;
+
+ /* Advance state pointer by 1 for the next sample */
+ pState++;
+ }
+
+ /* Save energy and x0 values for the next frame */
+ S->energy = (q31_t)energy;
+ S->x0 = x0;
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ start of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Loop for (numTaps - 1U) samples copy */
+ tapCnt = numTaps - 1;
+
+ /* Copy the remaining q31_t data */
+ while (tapCnt > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+}
+
+void ref_lms_q15(
+ const arm_lms_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t mu = S->mu; /* Adaptive factor */
+ q15_t *px; /* Temporary pointer for state */
+ q15_t *pb; /* Temporary pointer for coefficient buffer */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+ q63_t acc; /* Accumulator */
+ q15_t e = 0; /* error of data sample */
+ q15_t alpha; /* Intermediate constant for taps update */
+ q31_t coef; /* Teporary variable for coefficient */
+ q31_t acc_l, acc_h;
+ int32_t lShift = 15 - (int32_t)S->postShift; /* Post shift */
+ int32_t uShift = 32 - lShift;
+
+ /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+ for(blkCnt = blockSize; blkCnt > 0U; blkCnt--)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize pCoeffs pointer */
+ pb = pCoeffs;
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ acc += (q63_t)((q31_t)(*px++) * (*pb++));
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc = (uint32_t)acc_l >> lShift | acc_h << uShift;
+
+ /* Converting the result to 1.15 format and saturate the output */
+ acc = ref_sat_q15(acc);
+
+ /* Store the result from accumulator into the destination buffer. */
+ *pOut++ = (q15_t)acc;
+
+ /* Compute and store error */
+ e = *pRef++ - (q15_t)acc;
+
+ *pErr++ = (q15_t)e;
+
+ /* Compute alpha i.e. intermediate constant for taps update */
+ alpha = (q15_t)(((q31_t)e * mu) >> 15);
+
+ /* Initialize pState pointer */
+ /* Advance state pointer by 1 for the next sample */
+ px = pState++;
+
+ /* Initialize pCoeffs pointer */
+ pb = pCoeffs;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+ *pb++ = (q15_t) ref_sat_q15(coef);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+ }
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ start of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Copy (numTaps - 1U) samples */
+ tapCnt = numTaps - 1;
+
+ /* Copy the data */
+ while (tapCnt > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+}
+
+void ref_lms_norm_q15(
+ arm_lms_norm_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
+ q15_t mu = S->mu; /* Adaptive factor */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+ q31_t energy; /* Energy of the input */
+ q63_t acc; /* Accumulator */
+ q15_t e = 0, d = 0; /* error, reference data sample */
+ q15_t w = 0, in; /* weight factor and state */
+ q15_t x0; /* temporary variable to hold input sample */
+ q15_t errorXmu, oneByEnergy; /* Temporary variables to store error and mu product and reciprocal of energy */
+ //q31_t errorXmu; /* Temporary variables to store error and mu product and reciprocal of energy */
+ q15_t postShift; /* Post shift to be applied to weight after reciprocal calculation */
+ q31_t coef; /* Teporary variable for coefficient */
+ q31_t acc_l, acc_h;
+ int32_t lShift = 15 - (int32_t)S->postShift; /* Post shift */
+ int32_t uShift = 32 - lShift;
+
+ energy = S->energy;
+ x0 = S->x0;
+
+ /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+ for(blkCnt = blockSize; blkCnt > 0U; blkCnt--)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize pCoeffs pointer */
+ pb = pCoeffs;
+
+ /* Read the sample from input buffer */
+ in = *pSrc++;
+
+ /* Update the energy calculation */
+ energy -= (((q31_t)x0 * x0) >> 15) & 0xffff;
+ energy += (((q31_t)in * in) >> 15) & 0xffff;
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ acc += (q31_t)*px++ * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Converting the result to 1.15 format and saturate the output */
+ acc = ref_sat_q15(acc);
+
+ /* Store the result from accumulator into the destination buffer. */
+ *pOut++ = (q15_t) acc;
+
+ /* Compute and store error */
+ d = *pRef++;
+ e = d - (q15_t) acc;
+ *pErr++ = e;
+
+#if 0
+ /* Calculation of e * mu value */
+ errorXmu = (q31_t) e * mu;
+
+ /* Calculation of (e * mu) /energy value */
+ acc = errorXmu / (energy + DELTA_Q15);
+#endif
+
+ /* Calculation of 1/energy */
+ postShift = arm_recip_q15((q15_t) energy + DELTA_Q15,
+ &oneByEnergy, S->recipTable);
+
+ /* Calculation of e * mu value */
+ errorXmu = (q15_t) (((q31_t) e * mu) >> 15);
+
+ /* Calculation of (e * mu) * (1/energy) value */
+ acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift));
+
+ /* Weighting factor for the normalized version */
+ w = ref_sat_q15((q31_t)acc);
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ coef = *pb + (((q31_t)w * (*px++)) >> 15);
+ *pb++ = ref_sat_q15(coef);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Read the sample from state buffer */
+ x0 = *pState;
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1U;
+ }
+
+ /* Save energy and x0 values for the next frame */
+ S->energy = (q15_t)energy;
+ S->x0 = x0;
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ satrt of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* copy (numTaps - 1U) data */
+ tapCnt = numTaps - 1;
+
+ /* copy data */
+ while (tapCnt > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/mat_helper.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/mat_helper.c
new file mode 100644
index 0000000..0174ccf
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/mat_helper.c
@@ -0,0 +1,193 @@
+#include "ref.h"
+
+float32_t ref_detrm(float32_t *pSrc, float32_t *temp, uint32_t size)
+{
+ float32_t s = 1, det = 0;
+ int i, j, m, n, c;
+
+ if ( size == 1 )
+ {
+ return ( pSrc[ 0 ] );
+ }
+ else
+ {
+ det = 0;
+
+ for ( c = 0;c < size;c++ )
+ {
+ m = 0;
+ n = 0;
+
+ for ( i = 0;i < size;i++ )
+ {
+ for ( j = 0;j < size;j++ )
+ {
+ temp[ i*size + j ] = 0;
+
+ if ( i != 0 && j != c )
+ {
+ temp[ m*(size-1) + n ] = pSrc[ i*size + j ];
+
+ if ( n < ( size - 2 ) )
+ {
+ n++;
+ }
+ else
+ {
+ n = 0;
+ m++;
+ }
+ }
+ }
+ }
+
+ det += s * ( pSrc[ c ] * ref_detrm( temp, temp + size*size, size - 1 ) );
+ s = -s;
+ }
+ }
+
+ return ( det );
+}
+
+
+void ref_cofact(float32_t *pSrc, float32_t *pDst, float32_t *temp, uint32_t size)
+{
+ int p, q, m, n, i, j;
+
+ if (size == 1)
+ {
+ pDst[0] = 1;
+ return;
+ }
+
+ for ( q = 0;q < size;q++ )
+ {
+ for ( p = 0;p < size;p++ )
+ {
+ m = 0;
+ n = 0;
+
+ for ( i = 0;i < size;i++ )
+ {
+ for ( j = 0;j < size;j++ )
+ {
+ temp[ i*size + j ] = 0;
+
+ if ( i != q && j != p )
+ {
+ temp[ m*(size-1) + n ] = pSrc[ i*size + j ];
+
+ if ( n < ( size - 2 ) )
+ {
+ n++;
+ }
+ else
+ {
+ n = 0;
+ m++;
+ }
+ }
+ }
+ }
+
+ pDst[ q*size + p ] = ref_pow( -1, q + p ) * ref_detrm( temp, temp + (size-1)*(size-1), size - 1 );
+ }
+ }
+}
+
+
+
+float64_t ref_detrm64(float64_t *pSrc, float64_t *temp, uint32_t size)
+{
+ float64_t s = 1, det = 0;
+ int i, j, m, n, c;
+
+ if ( size == 1 )
+ {
+ return ( pSrc[ 0 ] );
+ }
+ else
+ {
+ det = 0;
+
+ for ( c = 0;c < size;c++ )
+ {
+ m = 0;
+ n = 0;
+
+ for ( i = 0;i < size;i++ )
+ {
+ for ( j = 0;j < size;j++ )
+ {
+ temp[ i*size + j ] = 0;
+
+ if ( i != 0 && j != c )
+ {
+ temp[ m*(size-1) + n ] = pSrc[ i*size + j ];
+
+ if ( n < ( size - 2 ) )
+ {
+ n++;
+ }
+ else
+ {
+ n = 0;
+ m++;
+ }
+ }
+ }
+ }
+
+ det += s * ( pSrc[ c ] * ref_detrm64( temp, temp + size*size, size - 1 ) );
+ s = -s;
+ }
+ }
+
+ return ( det );
+}
+
+
+void ref_cofact64(float64_t *pSrc, float64_t *pDst, float64_t *temp, uint32_t size)
+{
+ int p, q, m, n, i, j;
+
+ if (size == 1)
+ {
+ pDst[0] = 1;
+ return;
+ }
+
+ for ( q = 0;q < size;q++ )
+ {
+ for ( p = 0;p < size;p++ )
+ {
+ m = 0;
+ n = 0;
+
+ for ( i = 0;i < size;i++ )
+ {
+ for ( j = 0;j < size;j++ )
+ {
+ temp[ i*size + j ] = 0;
+
+ if ( i != q && j != p )
+ {
+ temp[ m*(size-1) + n ] = pSrc[ i*size + j ];
+
+ if ( n < ( size - 2 ) )
+ {
+ n++;
+ }
+ else
+ {
+ n = 0;
+ m++;
+ }
+ }
+ }
+ }
+
+ pDst[ q*size + p ] = ref_pow( -1, q + p ) * ref_detrm64( temp, temp + (size-1)*(size-1), size - 1 );
+ }
+ }
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/ref_helper.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/ref_helper.c
new file mode 100644
index 0000000..57ecf1b
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/ref_helper.c
@@ -0,0 +1,103 @@
+#include "ref.h"
+
+float32_t scratchArray[8192*2];
+
+arm_cfft_instance_f32 ref_cfft_sR_f32_len8192 = { 8192, 0, 0, 0 };
+
+q31_t ref_sat_n(q31_t num, uint32_t bits)
+{
+ int32_t posMax, negMin;
+ uint32_t i;
+
+ posMax = 1;
+ for (i = 0; i < (bits - 1); i++)
+ {
+ posMax = posMax * 2;
+ }
+
+ if (num > 0)
+ {
+ posMax = (posMax - 1);
+
+ if (num > posMax)
+ {
+ num = posMax;
+ }
+ }
+ else
+ {
+ negMin = -posMax;
+
+ if (num < negMin)
+ {
+ num = negMin;
+ }
+ }
+ return (num);
+}
+
+q31_t ref_sat_q31(q63_t num)
+{
+ if (num > (q63_t)INT_MAX)
+ {
+ return INT_MAX;
+ }
+ else if (num < (q63_t)0xffffffff80000000ll)
+ {
+ return INT_MIN;
+ }
+ else
+ {
+ return (q31_t)num;
+ }
+}
+
+q15_t ref_sat_q15(q31_t num)
+{
+ if (num > (q31_t)SHRT_MAX)
+ {
+ return SHRT_MAX;
+ }
+ else if (num < (q31_t)0xffff8000)
+ {
+ return SHRT_MIN;
+ }
+ else
+ {
+ return (q15_t)num;
+ }
+}
+
+q7_t ref_sat_q7(q15_t num)
+{
+ if (num > (q15_t)SCHAR_MAX)
+ {
+ return SCHAR_MAX;
+ }
+ else if (num < (q15_t)0xff80)
+ {
+ return SCHAR_MIN;
+ }
+ else
+ {
+ return (q7_t)num;
+ }
+}
+
+float32_t ref_pow(float32_t a, uint32_t b)
+{
+ uint32_t i;
+ float32_t r = a;
+
+ for(i=1;i<b;i++)
+ {
+ r *= a;
+ }
+
+ if ( b == 0)
+ {
+ return 1;
+ }
+
+ return r;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/Intrinsics/intrinsics.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/Intrinsics/intrinsics.c
new file mode 100644
index 0000000..7412adb
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/Intrinsics/intrinsics.c
@@ -0,0 +1,238 @@
+#include "ref.h"
+
+q31_t ref__QADD8(q31_t x, q31_t y)
+{
+ q31_t sum;
+ q7_t r, s, t, u;
+
+ r = (q7_t) x;
+ s = (q7_t) y;
+
+ r = ref_sat_n((q31_t) (r + s), 8);
+ s = ref_sat_n(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+ t = ref_sat_n(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+ u = ref_sat_n(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+ sum =
+ (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+ (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+ return sum;
+
+}
+
+q31_t ref__QSUB8(q31_t x, q31_t y)
+{
+ q31_t sum;
+ q31_t r, s, t, u;
+
+ r = (q7_t) x;
+ s = (q7_t) y;
+
+ r = ref_sat_n((r - s), 8);
+ s = ref_sat_n(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+ t = ref_sat_n(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+ u = ref_sat_n(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+ sum = (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & 0x000000FF);
+
+ return sum;
+}
+
+q31_t ref__QADD16(q31_t x, q31_t y)
+{
+ q31_t sum;
+ q31_t r, s;
+
+ r = (q15_t) x;
+ s = (q15_t) y;
+
+ r = ref_sat_q15(r + s);
+ s = (q31_t)ref_sat_q15(((q31_t) ((x >> 16) + (y >> 16)))) << 16;
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+
+}
+
+q31_t ref__SHADD16(q31_t x, q31_t y)
+{
+ q31_t sum;
+ q31_t r, s;
+
+ r = (q15_t) x;
+ s = (q15_t) y;
+
+ r = (r + s) >> 1;
+ s = ((q31_t) (((x >> 16) + (y >> 16)) >> 1) << 16);
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+
+}
+
+q31_t ref__QSUB16(q31_t x, q31_t y)
+{
+ q31_t sum;
+ q31_t r, s;
+
+ r = (q15_t) x;
+ s = (q15_t) y;
+
+ r = ref_sat_q15(r - s);
+ s = (q31_t)ref_sat_q15(((q31_t) ((x >> 16) - (y >> 16)))) << 16;
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+}
+
+q31_t ref__SHSUB16(q31_t x, q31_t y)
+{
+ q31_t diff;
+ q31_t r, s;
+
+ r = (q15_t) x;
+ s = (q15_t) y;
+
+ r = ((r >> 1) - (s >> 1));
+ s = (((x >> 17) - (y >> 17)) << 16);
+
+ diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return diff;
+}
+
+q31_t ref__QASX(q31_t x, q31_t y)
+{
+ q31_t sum = 0;
+ q31_t xL, xH, yL, yH;
+
+ // extract bottom halfword and sign extend
+ xL = (q15_t)(x & 0xffff);
+ // extract bottom halfword and sign extend
+ yL = (q15_t)(y & 0xffff);
+ // extract top halfword and sign extend
+ xH = (q15_t)(x >> 16);
+ // extract top halfword and sign extend
+ yH = (q15_t)(y >> 16);
+
+ sum = (((q31_t)ref_sat_q15(xH + yL )) << 16) |
+ (((q31_t)ref_sat_q15(xL - yH )) & 0xffff);
+
+ return sum;
+}
+
+q31_t ref__SHASX(q31_t x, q31_t y)
+{
+ q31_t sum;
+ q31_t r, s;
+
+ r = (q15_t) x;
+ s = (q15_t) y;
+
+ r = (r - (y >> 16)) / 2;
+ s = (((x >> 16) + s) << 15);
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+}
+
+q31_t ref__QSAX(q31_t x, q31_t y)
+{
+ q31_t sum = 0;
+ q31_t xL, xH, yL, yH;
+
+ // extract bottom halfword and sign extend
+ xL = (q15_t)(x & 0xffff);
+ // extract bottom halfword and sign extend
+ yL = (q15_t)(y & 0xffff);
+ // extract top halfword and sign extend
+ xH = (q15_t)(x >> 16);
+ // extract top halfword and sign extend
+ yH = (q15_t)(y >> 16);
+
+ sum = (((q31_t)ref_sat_q15(xH - yL )) << 16) |
+ (((q31_t)ref_sat_q15(xL + yH )) & 0xffff);
+
+ return sum;
+}
+
+q31_t ref__SHSAX(q31_t x, q31_t y)
+{
+ q31_t sum;
+ q31_t r, s;
+
+ r = (q15_t) x;
+ s = (q15_t) y;
+
+ r = (r + (y >> 16)) / 2;
+ s = (((x >> 16) - s) << 15);
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+}
+
+q31_t ref__SMUSDX(q31_t x, q31_t y)
+{
+ return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) - ((q15_t) (x >> 16) * (q15_t) y)));
+}
+
+q31_t ref__SMUADX(q31_t x, q31_t y)
+{
+ return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) + ((q15_t) (x >> 16) * (q15_t) y)));
+}
+
+q31_t ref__QADD(q31_t x, q31_t y)
+{
+ return ref_sat_q31((q63_t) x + y);
+}
+
+q31_t ref__QSUB(q31_t x, q31_t y)
+{
+ return ref_sat_q31((q63_t) x - y);
+}
+
+q31_t ref__SMLAD(q31_t x, q31_t y, q31_t sum)
+{
+ return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y));
+}
+
+q31_t ref__SMLADX(q31_t x, q31_t y, q31_t sum)
+{
+ return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) + ((q15_t) x * (q15_t) (y >> 16)));
+}
+
+q31_t ref__SMLSDX(q31_t x, q31_t y, q31_t sum)
+{
+ return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) + ((q15_t) x * (q15_t) (y >> 16)));
+}
+
+q63_t ref__SMLALD(q31_t x, q31_t y, q63_t sum)
+{
+ return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y));
+}
+
+q63_t ref__SMLALDX(q31_t x, q31_t y, q63_t sum)
+{
+ return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16));
+}
+
+q31_t ref__SMUAD(q31_t x, q31_t y)
+{
+ return (((x >> 16) * (y >> 16)) + (((x << 16) >> 16) * ((y << 16) >> 16)));
+}
+
+q31_t ref__SMUSD(q31_t x, q31_t y)
+{
+ return (-((x >> 16) * (y >> 16)) + (((x << 16) >> 16) * ((y << 16) >> 16)));
+}
+
+q31_t ref__SXTB16(q31_t x)
+{
+ return ((((x << 24) >> 24) & 0x0000FFFF) | (((x << 8) >> 8) & 0xFFFF0000));
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_add.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_add.c
new file mode 100644
index 0000000..a6e0067
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_add.c
@@ -0,0 +1,58 @@
+#include "ref.h"
+
+arm_status ref_mat_add_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst)
+{
+ uint32_t i;
+ uint32_t numSamples; /* total number of elements in the matrix */
+
+ /* Total number of samples in the input matrix */
+ numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+ for(i=0;i<numSamples;i++)
+ {
+ pDst->pData[i] = pSrcA->pData[i] + pSrcB->pData[i];
+ }
+
+ return ARM_MATH_SUCCESS;
+}
+
+arm_status ref_mat_add_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst)
+{
+ uint32_t i;
+ uint32_t numSamples; /* total number of elements in the matrix */
+
+ /* Total number of samples in the input matrix */
+ numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+ for(i=0;i<numSamples;i++)
+ {
+ pDst->pData[i] = ref_sat_q31( (q63_t)pSrcA->pData[i] + pSrcB->pData[i]);
+ }
+
+ return ARM_MATH_SUCCESS;
+}
+
+arm_status ref_mat_add_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst)
+{
+ uint32_t i;
+ uint32_t numSamples; /* total number of elements in the matrix */
+
+ /* Total number of samples in the input matrix */
+ numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+ for(i=0;i<numSamples;i++)
+ {
+ pDst->pData[i] = ref_sat_q15( (q31_t)pSrcA->pData[i] + pSrcB->pData[i]);
+ }
+
+ return ARM_MATH_SUCCESS;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_cmplx_mult.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_cmplx_mult.c
new file mode 100644
index 0000000..9364619
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_cmplx_mult.c
@@ -0,0 +1,118 @@
+#include "ref.h"
+
+arm_status ref_mat_cmplx_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst)
+{
+ uint32_t r,c,i,outR,outC,innerSize;
+ float32_t sumR,sumI;
+ float32_t a0,b0,c0,d0;
+
+ outR = pSrcA->numRows;
+ outC = pSrcB->numCols;
+ innerSize = pSrcA->numCols;
+
+ for(r=0;r<outR;r++)
+ {
+ for(c=0;c<outC;c++)
+ {
+ sumR = 0;
+ sumI = 0;
+
+ for(i=0;i<innerSize;i++)
+ {
+ a0 = pSrcA->pData[2*(r*innerSize + i) + 0];
+ b0 = pSrcA->pData[2*(r*innerSize + i) + 1];
+ c0 = pSrcB->pData[2*(i*outC + c) + 0];
+ d0 = pSrcB->pData[2*(i*outC + c) + 1];
+
+ sumR += a0 * c0 - b0 * d0;
+ sumI += b0 * c0 + a0 * d0;
+ }
+
+ pDst->pData[2*(r*outC + c) + 0] = sumR;
+ pDst->pData[2*(r*outC + c) + 1] = sumI;
+ }
+ }
+
+ return ARM_MATH_SUCCESS;
+}
+
+arm_status ref_mat_cmplx_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst)
+{
+ uint32_t r,c,i,outR,outC,innerSize;
+ q63_t sumR,sumI;
+ q31_t a0,b0,c0,d0;
+
+ outR = pSrcA->numRows;
+ outC = pSrcB->numCols;
+ innerSize = pSrcA->numCols;
+
+ for(r=0;r<outR;r++)
+ {
+ for(c=0;c<outC;c++)
+ {
+ sumR = 0;
+ sumI = 0;
+
+ for(i=0;i<innerSize;i++)
+ {
+ a0 = pSrcA->pData[2*(r*innerSize + i) + 0];
+ b0 = pSrcA->pData[2*(r*innerSize + i) + 1];
+ c0 = pSrcB->pData[2*(i*outC + c) + 0];
+ d0 = pSrcB->pData[2*(i*outC + c) + 1];
+
+ sumR += (q63_t)a0 * c0 - (q63_t)b0 * d0;
+ sumI += (q63_t)b0 * c0 + (q63_t)a0 * d0;
+ }
+
+ pDst->pData[2*(r*outC + c) + 0] = ref_sat_q31(sumR >> 31);
+ pDst->pData[2*(r*outC + c) + 1] = ref_sat_q31(sumI >> 31);
+ }
+ }
+
+ return ARM_MATH_SUCCESS;
+}
+
+arm_status ref_mat_cmplx_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst)
+{
+ uint32_t r,c,i,outR,outC,innerSize;
+ q63_t sumR,sumI;
+ q15_t a0,b0,c0,d0;
+
+ outR = pSrcA->numRows;
+ outC = pSrcB->numCols;
+ innerSize = pSrcA->numCols;
+
+ for(r=0;r<outR;r++)
+ {
+ for(c=0;c<outC;c++)
+ {
+ sumR = 0;
+ sumI = 0;
+
+ for(i=0;i<innerSize;i++)
+ {
+ a0 = pSrcA->pData[2*(r*innerSize + i) + 0];
+ b0 = pSrcA->pData[2*(r*innerSize + i) + 1];
+ c0 = pSrcB->pData[2*(i*outC + c) + 0];
+ d0 = pSrcB->pData[2*(i*outC + c) + 1];
+
+ sumR += (q31_t)a0 * c0 - (q31_t)b0 * d0;
+ sumI += (q31_t)b0 * c0 + (q31_t)a0 * d0;
+ }
+
+ pDst->pData[2*(r*outC + c) + 0] = ref_sat_q15(sumR >> 15);
+ pDst->pData[2*(r*outC + c) + 1] = ref_sat_q15(sumI >> 15);
+ }
+ }
+
+ return ARM_MATH_SUCCESS;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_inverse.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_inverse.c
new file mode 100644
index 0000000..74d3ccc
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_inverse.c
@@ -0,0 +1,57 @@
+#include "ref.h"
+
+arm_status ref_mat_inverse_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst)
+{
+ float32_t det;
+ uint32_t i, size;
+ arm_matrix_instance_f32 tmp;
+
+ tmp.numCols = pSrc->numCols;
+ tmp.numRows = pSrc->numRows;
+ tmp.pData = scratchArray;
+
+ det = ref_detrm(pSrc->pData,scratchArray,pSrc->numCols);
+
+ size = pSrc->numCols * pSrc->numCols;
+
+ ref_cofact(pSrc->pData,scratchArray,scratchArray + size,pSrc->numCols);
+
+ ref_mat_trans_f32(&tmp,pDst);
+
+ for(i=0;i<size;i++)
+ {
+ pDst->pData[i] /= det;
+ }
+
+ return ARM_MATH_SUCCESS;
+}
+
+arm_status ref_mat_inverse_f64(
+ const arm_matrix_instance_f64 * pSrc,
+ arm_matrix_instance_f64 * pDst)
+{
+ float64_t det;
+ uint32_t i, size;
+ arm_matrix_instance_f64 tmp;
+
+ tmp.numCols = pSrc->numCols;
+ tmp.numRows = pSrc->numRows;
+ tmp.pData = (float64_t*)scratchArray;
+
+ det = ref_detrm64(pSrc->pData,(float64_t*)scratchArray,pSrc->numCols);
+
+ size = pSrc->numCols * pSrc->numCols;
+
+ ref_cofact64(pSrc->pData,(float64_t*)scratchArray,(float64_t*)scratchArray + size,pSrc->numCols);
+
+ ref_mat_trans_f64(&tmp,pDst);
+
+ for(i=0;i<size;i++)
+ {
+ pDst->pData[i] /= det;
+ }
+
+ return ARM_MATH_SUCCESS;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_mult.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_mult.c
new file mode 100644
index 0000000..e9ef432
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_mult.c
@@ -0,0 +1,91 @@
+#include "ref.h"
+
+arm_status ref_mat_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst)
+{
+ uint32_t r,c,i,outR,outC,innerSize;
+ float32_t sum;
+
+ outR = pSrcA->numRows;
+ outC = pSrcB->numCols;
+ innerSize = pSrcA->numCols;
+
+ for(r=0;r<outR;r++)
+ {
+ for(c=0;c<outC;c++)
+ {
+ sum = 0;
+
+ for(i=0;i<innerSize;i++)
+ {
+ sum += pSrcA->pData[r*innerSize + i] * pSrcB->pData[i*outC + c];
+ }
+
+ pDst->pData[r*outC + c] = sum;
+ }
+ }
+
+ return ARM_MATH_SUCCESS;
+}
+
+arm_status ref_mat_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst)
+{
+ uint32_t r,c,i,outR,outC,innerSize;
+ q63_t sum;
+
+ outR = pSrcA->numRows;
+ outC = pSrcB->numCols;
+ innerSize = pSrcA->numCols;
+
+ for(r=0;r<outR;r++)
+ {
+ for(c=0;c<outC;c++)
+ {
+ sum = 0;
+
+ for(i=0;i<innerSize;i++)
+ {
+ sum += (q63_t)(pSrcA->pData[r*innerSize + i]) * pSrcB->pData[i*outC + c];
+ }
+
+ pDst->pData[r*outC + c] = ref_sat_q31(sum >> 31);
+ }
+ }
+
+ return ARM_MATH_SUCCESS;
+}
+
+arm_status ref_mat_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst)
+{
+ uint32_t r,c,i,outR,outC,innerSize;
+ q63_t sum;
+
+ outR = pSrcA->numRows;
+ outC = pSrcB->numCols;
+ innerSize = pSrcA->numCols;
+
+ for(r=0;r<outR;r++)
+ {
+ for(c=0;c<outC;c++)
+ {
+ sum = 0;
+
+ for(i=0;i<innerSize;i++)
+ {
+ sum += (q31_t)(pSrcA->pData[r*innerSize + i]) * pSrcB->pData[i*outC + c];
+ }
+
+ pDst->pData[r*outC + c] = ref_sat_q15(sum >> 15);
+ }
+ }
+
+ return ARM_MATH_SUCCESS;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_scale.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_scale.c
new file mode 100644
index 0000000..d426ad6
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_scale.c
@@ -0,0 +1,64 @@
+#include "ref.h"
+
+arm_status ref_mat_scale_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32 * pDst)
+{
+ uint32_t i;
+ uint32_t numSamples; /* total number of elements in the matrix */
+
+ /* Total number of samples in the input matrix */
+ numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
+
+ for(i=0;i<numSamples;i++)
+ {
+ pDst->pData[i] = pSrc->pData[i] * scale;
+ }
+
+ return ARM_MATH_SUCCESS;
+}
+
+arm_status ref_mat_scale_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ q31_t scale,
+ int32_t shift,
+ arm_matrix_instance_q31 * pDst)
+{
+ uint32_t i;
+ uint32_t numSamples; /* total number of elements in the matrix */
+ int32_t totShift = shift + 1;
+ q31_t tmp;
+
+ /* Total number of samples in the input matrix */
+ numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
+
+ for(i=0;i<numSamples;i++)
+ {
+ tmp = ((q63_t)pSrc->pData[i] * scale) >> 32;
+ pDst->pData[i] = ref_sat_q31((q63_t)tmp << totShift );
+ }
+
+ return ARM_MATH_SUCCESS;
+}
+
+arm_status ref_mat_scale_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ q15_t scale,
+ int32_t shift,
+ arm_matrix_instance_q15 * pDst)
+{
+ uint32_t i;
+ uint32_t numSamples; /* total number of elements in the matrix */
+ int32_t totShift = 15 - shift;
+
+ /* Total number of samples in the input matrix */
+ numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
+
+ for(i=0;i<numSamples;i++)
+ {
+ pDst->pData[i] = ref_sat_q15( ((q31_t)pSrc->pData[i] * scale) >> totShift);
+ }
+
+ return ARM_MATH_SUCCESS;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_sub.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_sub.c
new file mode 100644
index 0000000..bbd23f0
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_sub.c
@@ -0,0 +1,58 @@
+#include "ref.h"
+
+arm_status ref_mat_sub_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst)
+{
+ uint32_t i;
+ uint32_t numSamples; /* total number of elements in the matrix */
+
+ /* Total number of samples in the input matrix */
+ numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+ for(i=0;i<numSamples;i++)
+ {
+ pDst->pData[i] = pSrcA->pData[i] - pSrcB->pData[i];
+ }
+
+ return ARM_MATH_SUCCESS;
+}
+
+arm_status ref_mat_sub_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst)
+{
+ uint32_t i;
+ uint32_t numSamples; /* total number of elements in the matrix */
+
+ /* Total number of samples in the input matrix */
+ numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+ for(i=0;i<numSamples;i++)
+ {
+ pDst->pData[i] = ref_sat_q31( (q63_t)pSrcA->pData[i] - pSrcB->pData[i]);
+ }
+
+ return ARM_MATH_SUCCESS;
+}
+
+arm_status ref_mat_sub_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst)
+{
+ uint32_t i;
+ uint32_t numSamples; /* total number of elements in the matrix */
+
+ /* Total number of samples in the input matrix */
+ numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+ for(i=0;i<numSamples;i++)
+ {
+ pDst->pData[i] = ref_sat_q15( (q31_t)pSrcA->pData[i] - pSrcB->pData[i]);
+ }
+
+ return ARM_MATH_SUCCESS;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_trans.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_trans.c
new file mode 100644
index 0000000..8cb9a8d
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_trans.c
@@ -0,0 +1,77 @@
+#include "ref.h"
+
+arm_status ref_mat_trans_f64(
+ const arm_matrix_instance_f64 * pSrc,
+ arm_matrix_instance_f64 * pDst)
+{
+ uint64_t r,c;
+ uint64_t numR = pSrc->numRows;
+ uint64_t numC = pSrc->numCols;
+
+ for(r=0;r<numR;r++)
+ {
+ for(c=0;c<numC;c++)
+ {
+ pDst->pData[c*numR + r] = pSrc->pData[r*numC + c];
+ }
+ }
+
+ return ARM_MATH_SUCCESS;
+}
+
+arm_status ref_mat_trans_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst)
+{
+ uint32_t r,c;
+ uint32_t numR = pSrc->numRows;
+ uint32_t numC = pSrc->numCols;
+
+ for(r=0;r<numR;r++)
+ {
+ for(c=0;c<numC;c++)
+ {
+ pDst->pData[c*numR + r] = pSrc->pData[r*numC + c];
+ }
+ }
+
+ return ARM_MATH_SUCCESS;
+}
+
+arm_status ref_mat_trans_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst)
+{
+ uint32_t r,c;
+ uint32_t numR = pSrc->numRows;
+ uint32_t numC = pSrc->numCols;
+
+ for(r=0;r<numR;r++)
+ {
+ for(c=0;c<numC;c++)
+ {
+ pDst->pData[c*numR + r] = pSrc->pData[r*numC + c];
+ }
+ }
+
+ return ARM_MATH_SUCCESS;
+}
+
+arm_status ref_mat_trans_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst)
+{
+ uint32_t r,c;
+ uint32_t numR = pSrc->numRows;
+ uint32_t numC = pSrc->numCols;
+
+ for(r=0;r<numR;r++)
+ {
+ for(c=0;c<numC;c++)
+ {
+ pDst->pData[c*numR + r] = pSrc->pData[r*numC + c];
+ }
+ }
+
+ return ARM_MATH_SUCCESS;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/max.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/max.c
new file mode 100644
index 0000000..02b4127
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/max.c
@@ -0,0 +1,85 @@
+#include "ref.h"
+
+void ref_max_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex)
+{
+ uint32_t i, ind=0;
+ float32_t max=-FLT_MAX;
+
+ for(i=0;i<blockSize;i++)
+ {
+ if (max < pSrc[i])
+ {
+ max = pSrc[i];
+ ind = i;
+ }
+ }
+ *pResult = max;
+ *pIndex = ind;
+}
+
+void ref_max_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex)
+{
+ uint32_t i, ind=0;
+ q31_t max=INT_MIN;
+
+ for(i=0;i<blockSize;i++)
+ {
+ if (max < pSrc[i])
+ {
+ max = pSrc[i];
+ ind = i;
+ }
+ }
+ *pResult = max;
+ *pIndex = ind;
+}
+
+void ref_max_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex)
+{
+ uint32_t i, ind=0;
+ q15_t max=SHRT_MIN;
+
+ for(i=0;i<blockSize;i++)
+ {
+ if (max < pSrc[i])
+ {
+ max = pSrc[i];
+ ind = i;
+ }
+ }
+ *pResult = max;
+ *pIndex = ind;
+}
+
+void ref_max_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex)
+{
+ uint32_t i, ind=0;
+ q7_t max=SCHAR_MIN;
+
+ for(i=0;i<blockSize;i++)
+ {
+ if (max < pSrc[i])
+ {
+ max = pSrc[i];
+ ind = i;
+ }
+ }
+ *pResult = max;
+ *pIndex = ind;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/mean.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/mean.c
new file mode 100644
index 0000000..d4b4da4
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/mean.c
@@ -0,0 +1,61 @@
+#include "ref.h"
+
+void ref_mean_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult)
+{
+ uint32_t i;
+ float32_t sum=0;
+
+ for(i=0;i<blockSize;i++)
+ {
+ sum += pSrc[i];
+ }
+ *pResult = sum / (float32_t)blockSize;
+}
+
+void ref_mean_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult)
+{
+ uint32_t i;
+ q63_t sum=0;
+
+ for(i=0;i<blockSize;i++)
+ {
+ sum += pSrc[i];
+ }
+ *pResult = (q31_t) (sum / (int32_t) blockSize);
+}
+
+void ref_mean_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult)
+{
+ uint32_t i;
+ q31_t sum=0;
+
+ for(i=0;i<blockSize;i++)
+ {
+ sum += pSrc[i];
+ }
+ *pResult = (q15_t) (sum / (int32_t) blockSize);
+}
+
+void ref_mean_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult)
+{
+ uint32_t i;
+ q31_t sum=0;
+
+ for(i=0;i<blockSize;i++)
+ {
+ sum += pSrc[i];
+ }
+ *pResult = (q7_t) (sum / (int32_t) blockSize);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/min.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/min.c
new file mode 100644
index 0000000..6072b1a
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/min.c
@@ -0,0 +1,85 @@
+#include "ref.h"
+
+void ref_min_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex)
+{
+ uint32_t i, ind=0;
+ float32_t min=FLT_MAX;
+
+ for(i=0;i<blockSize;i++)
+ {
+ if (min > pSrc[i])
+ {
+ min = pSrc[i];
+ ind = i;
+ }
+ }
+ *pResult = min;
+ *pIndex = ind;
+}
+
+void ref_min_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex)
+{
+ uint32_t i, ind=0;
+ q31_t min=INT_MAX;
+
+ for(i=0;i<blockSize;i++)
+ {
+ if (min > pSrc[i])
+ {
+ min = pSrc[i];
+ ind = i;
+ }
+ }
+ *pResult = min;
+ *pIndex = ind;
+}
+
+void ref_min_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex)
+{
+ uint32_t i, ind=0;
+ q15_t min=SHRT_MAX;
+
+ for(i=0;i<blockSize;i++)
+ {
+ if (min > pSrc[i])
+ {
+ min = pSrc[i];
+ ind = i;
+ }
+ }
+ *pResult = min;
+ *pIndex = ind;
+}
+
+void ref_min_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex)
+{
+ uint32_t i, ind=0;
+ q7_t min=SCHAR_MAX;
+
+ for(i=0;i<blockSize;i++)
+ {
+ if (min > pSrc[i])
+ {
+ min = pSrc[i];
+ ind = i;
+ }
+ }
+ *pResult = min;
+ *pIndex = ind;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/power.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/power.c
new file mode 100644
index 0000000..8202e04
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/power.c
@@ -0,0 +1,61 @@
+#include "ref.h"
+
+void ref_power_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult)
+{
+ uint32_t i;
+ float32_t sumsq=0;
+
+ for(i=0;i<blockSize;i++)
+ {
+ sumsq += pSrc[i] * pSrc[i];
+ }
+ *pResult = sumsq;
+}
+
+void ref_power_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult)
+{
+ uint32_t i;
+ q63_t sumsq=0;
+
+ for(i=0;i<blockSize;i++)
+ {
+ sumsq += ((q63_t)pSrc[i] * pSrc[i]) >> 14;
+ }
+ *pResult = sumsq;
+}
+
+void ref_power_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult)
+{
+ uint32_t i;
+ q63_t sumsq=0;
+
+ for(i=0;i<blockSize;i++)
+ {
+ sumsq += (q63_t)pSrc[i] * pSrc[i];
+ }
+ *pResult = sumsq;
+}
+
+void ref_power_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult)
+{
+ uint32_t i;
+ q31_t sumsq=0;
+
+ for(i=0;i<blockSize;i++)
+ {
+ sumsq += (q31_t)pSrc[i] * pSrc[i];
+ }
+ *pResult = sumsq;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/rms.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/rms.c
new file mode 100644
index 0000000..d3ff5bf
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/rms.c
@@ -0,0 +1,65 @@
+#include "ref.h"
+
+void ref_rms_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult)
+{
+ uint32_t i;
+ float32_t sumsq=0;
+
+ for(i=0;i<blockSize;i++)
+ {
+ sumsq += pSrc[i] * pSrc[i];
+ }
+ *pResult = sqrtf(sumsq / (float32_t)blockSize);
+}
+
+void ref_rms_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult)
+{
+ uint32_t i;
+ q63_t sumsq=0;
+ q63_t tmp1;
+ q31_t tmp2;
+
+ float help_float;
+
+ for(i=0;i<blockSize;i++)
+ {
+ sumsq += (q63_t)pSrc[i] * pSrc[i];
+ }
+ tmp1 = (sumsq / (q63_t)blockSize) >> 31;
+ tmp2 = ref_sat_q31(tmp1);
+
+ /* GCC M0 problem: __aeabi_f2iz(QNAN) returns not 0 */
+ help_float = (sqrtf((float)tmp2 / 2147483648.0f) * 2147483648.0f);
+ /* Checking for a NAN value in help_float */
+ if (((*((int *)(&help_float))) & 0x7FC00000) == 0x7FC00000) {
+ help_float = 0;
+ }
+ *pResult = (q31_t)(help_float);
+
+// *pResult = (q31_t)(sqrtf((float)tmp2 / 2147483648.0f) * 2147483648.0f);
+}
+
+void ref_rms_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult)
+{
+ uint32_t i;
+ q63_t sumsq=0;
+ q31_t tmp1;
+ q15_t tmp2;
+
+ for(i=0;i<blockSize;i++)
+ {
+ sumsq += (q63_t)pSrc[i] * pSrc[i];
+ }
+ tmp1 = (sumsq / (q63_t)blockSize) >> 15;
+ tmp2 = ref_sat_q15(tmp1);
+ *pResult = (q15_t)(sqrtf((float)tmp2 / 32768.0f) * 32768.0f);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/std.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/std.c
new file mode 100644
index 0000000..c0c1ba3
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/std.c
@@ -0,0 +1,74 @@
+#include "ref.h"
+
+void ref_std_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult)
+{
+ uint32_t i;
+ float32_t sum=0, sumsq=0;
+
+ if (blockSize == 1)
+ {
+ *pResult = 0;
+ return;
+ }
+
+ for(i=0;i<blockSize;i++)
+ {
+ sum += pSrc[i];
+ sumsq += pSrc[i] * pSrc[i];
+ }
+ *pResult = sqrtf((sumsq - sum * sum / (float32_t)blockSize) / ((float32_t)blockSize - 1));
+}
+
+void ref_std_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult)
+{
+ uint32_t i;
+ q63_t sum=0, sumsq=0;
+ q31_t in;
+
+ if (blockSize == 1)
+ {
+ *pResult = 0;
+ return;
+ }
+
+ for(i=0;i<blockSize;i++)
+ {
+ in = pSrc[i] >> 8;
+ sum += in;
+ sumsq += (q63_t)in * in;
+ }
+ sumsq /= (q63_t)(blockSize - 1);
+ sum = sum * sum / (q63_t)(blockSize * (blockSize - 1));
+ *pResult = (q31_t)(sqrtf((float)( (sumsq - sum) >> 15) / 2147483648.0f ) * 2147483648.0f);
+}
+
+void ref_std_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult)
+{
+ uint32_t i;
+ q31_t sum=0;
+ q63_t sumsq=0;
+
+ if (blockSize == 1)
+ {
+ *pResult = 0;
+ return;
+ }
+
+ for(i=0;i<blockSize;i++)
+ {
+ sum += pSrc[i];
+ sumsq += (q63_t)pSrc[i] * pSrc[i];
+ }
+ sumsq /= (q63_t)(blockSize - 1);
+ sum = (q31_t)((q63_t)sum * sum / (q63_t)(blockSize * (blockSize - 1)));
+ *pResult = (q15_t)(sqrtf((float)ref_sat_q15( (sumsq - sum) >> 15) / 32768.0f ) * 32768.0f);
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/var.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/var.c
new file mode 100644
index 0000000..f5da3a6
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/var.c
@@ -0,0 +1,70 @@
+#include "ref.h"
+
+void ref_var_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult)
+{
+ uint32_t i;
+ float32_t sum=0, sumsq=0;
+
+ if (blockSize == 1)
+ {
+ *pResult = 0;
+ return;
+ }
+
+ for(i=0;i<blockSize;i++)
+ {
+ sum += pSrc[i];
+ sumsq += pSrc[i] * pSrc[i];
+ }
+ *pResult = (sumsq - sum * sum / (float32_t)blockSize) / ((float32_t)blockSize - 1);
+}
+
+void ref_var_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult)
+{
+ uint32_t i;
+ q63_t sum=0, sumsq=0;
+ q31_t in;
+
+ if (blockSize == 1)
+ {
+ *pResult = 0;
+ return;
+ }
+
+ for(i=0;i<blockSize;i++)
+ {
+ in = pSrc[i] >> 8;
+ sum += in;
+ sumsq += (q63_t)in * in;
+ }
+ *pResult = (sumsq - sum * sum / (q31_t)blockSize) / ((q31_t)blockSize - 1) >> 15;
+}
+
+void ref_var_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult)
+{
+ uint32_t i;
+ q31_t sum=0;
+ q63_t sumsq=0;
+
+ if (blockSize == 1)
+ {
+ *pResult = 0;
+ return;
+ }
+
+ for(i=0;i<blockSize;i++)
+ {
+ sum += pSrc[i];
+ sumsq += (q63_t)pSrc[i] * pSrc[i];
+ }
+ *pResult = (q31_t)((sumsq - (q63_t)sum * sum / (q63_t)blockSize) / ((q63_t)blockSize - 1)) >> 15;
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/copy.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/copy.c
new file mode 100644
index 0000000..08089f5
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/copy.c
@@ -0,0 +1,53 @@
+#include "ref.h"
+
+void ref_copy_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = pSrc[i];
+ }
+}
+
+void ref_copy_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = pSrc[i];
+ }
+}
+
+void ref_copy_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = pSrc[i];
+ }
+}
+
+void ref_copy_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = pSrc[i];
+ }
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fill.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fill.c
new file mode 100644
index 0000000..6082351
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fill.c
@@ -0,0 +1,53 @@
+#include "ref.h"
+
+void ref_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = value;
+ }
+}
+
+void ref_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = value;
+ }
+}
+
+void ref_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = value;
+ }
+}
+
+void ref_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = value;
+ }
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fixed_to_fixed.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fixed_to_fixed.c
new file mode 100644
index 0000000..f0c1d0f
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fixed_to_fixed.c
@@ -0,0 +1,79 @@
+#include "ref.h"
+
+void ref_q31_to_q15(
+ q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = pSrc[i] >> 16;
+ }
+}
+
+void ref_q31_to_q7(
+ q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = pSrc[i] >> 24;
+ }
+}
+
+void ref_q15_to_q31(
+ q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = ((q31_t)pSrc[i]) << 16;
+ }
+}
+
+void ref_q15_to_q7(
+ q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = pSrc[i] >> 8;
+ }
+}
+
+void ref_q7_to_q31(
+ q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = ((q31_t)pSrc[i]) << 24;
+ }
+}
+
+void ref_q7_to_q15(
+ q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = ((q15_t)pSrc[i]) << 8;
+ }
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fixed_to_float.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fixed_to_float.c
new file mode 100644
index 0000000..296a50e
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fixed_to_float.c
@@ -0,0 +1,53 @@
+#include "ref.h"
+
+void ref_q63_to_float(
+ q63_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = ((float32_t)pSrc[i]) / 9223372036854775808.0f;
+ }
+}
+
+void ref_q31_to_float(
+ q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = ((float32_t)pSrc[i]) / 2147483648.0f;
+ }
+}
+
+void ref_q15_to_float(
+ q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = ((float32_t)pSrc[i]) / 32768.0f;
+ }
+}
+
+void ref_q7_to_float(
+ q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+
+ for(i=0;i<blockSize;i++)
+ {
+ pDst[i] = ((float32_t)pSrc[i]) / 128.0f;
+ }
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/float_to_fixed.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/float_to_fixed.c
new file mode 100644
index 0000000..107556b
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/float_to_fixed.c
@@ -0,0 +1,52 @@
+#include "ref.h"
+
+void ref_float_to_q31(
+ float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+ float32_t in;
+
+ for(i=0;i<blockSize;i++)
+ {
+ in = pSrc[i];
+ in *= 2147483648.0f; //scale up
+ in += in > 0.0f ? 0.5f : -0.5f; //round
+ pDst[i] = ref_sat_q31((q63_t)in); //cast and saturate
+ }
+}
+
+void ref_float_to_q15(
+ float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+ float32_t in;
+
+ for(i=0;i<blockSize;i++)
+ {
+ in = pSrc[i];
+ in *= 32768.0f;
+ in += in > 0.0f ? 0.5f : -0.5f;
+ pDst[i] = ref_sat_q15((q31_t)in);
+ }
+}
+
+void ref_float_to_q7(
+ float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i;
+ float32_t in;
+
+ for(i=0;i<blockSize;i++)
+ {
+ in = pSrc[i];
+ in *= 128.0f;
+ in += in > 0.0f ? 0.5f : -0.5f;
+ pDst[i] = ref_sat_q7((q15_t)in);
+ }
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/bitreversal.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/bitreversal.c
new file mode 100644
index 0000000..4751821
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/bitreversal.c
@@ -0,0 +1,30 @@
+#include "ref.h"
+
+
+;/*
+;* @brief In-place bit reversal function.
+;* @param[in, out] *pSrc points to the in-place buffer of unknown 32-bit data type.
+;* @param[in] bitRevLen bit reversal table length
+;* @param[in] *pBitRevTab points to bit reversal table.
+;* @return none.
+;*/
+void arm_bitreversal_32(uint32_t *pSrc, uint32_t bitRevLen, uint32_t *pBitRevTab)
+{
+ uint32_t a,b,i,tmp;
+
+ for(i=0; i<bitRevLen; i++)
+ {
+ a = pBitRevTab[2*i];
+ b = pBitRevTab[2*i + 1];
+
+ //real
+ tmp = pSrc[a];
+ pSrc[a] = pSrc[b];
+ pSrc[b] = tmp;
+
+ //complex
+ tmp = pSrc[a+1];
+ pSrc[a+1] = pSrc[b+1];
+ pSrc[b+1] = tmp;
+ }
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/cfft.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/cfft.c
new file mode 100644
index 0000000..ede4da6
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/cfft.c
@@ -0,0 +1,598 @@
+#include "ref.h"
+#include "arm_const_structs.h"
+
+void ref_cfft_f32(
+ const arm_cfft_instance_f32 * S,
+ float32_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag)
+{
+ int n, mmax, m, j, istep, i;
+ float32_t wtemp, wr, wpr, wpi, wi, theta;
+ float32_t tempr, tempi;
+ float32_t * data = p1;
+ uint32_t N = S->fftLen;
+ int32_t dir = (ifftFlag) ? -1 : 1;
+
+ // decrement pointer since the original version used fortran style indexing.
+ data--;
+
+ n = N << 1;
+ j = 1;
+ for (i = 1; i < n; i += 2) {
+ if (j > i) {
+ tempr = data[j]; data[j] = data[i]; data[i] = tempr;
+ tempr = data[j+1]; data[j+1] = data[i+1]; data[i+1] = tempr;
+ }
+ m = n >> 1;
+ while (m >= 2 && j > m) {
+ j -= m;
+ m >>= 1;
+ }
+ j += m;
+ }
+ mmax = 2;
+ while (n > mmax) {
+ istep = 2*mmax;
+ theta = -6.283185307179586f/(dir*mmax);
+ wtemp = sinf(0.5f*theta);
+ wpr = -2.0f*wtemp*wtemp;
+ wpi = sinf(theta);
+ wr = 1.0f;
+ wi = 0.0f;
+ for (m = 1; m < mmax; m += 2) {
+ for (i = m; i <= n; i += istep) {
+ j =i + mmax;
+ tempr = wr*data[j] - wi*data[j+1];
+ tempi = wr*data[j+1] + wi*data[j];
+ data[j] = data[i] - tempr;
+ data[j+1] = data[i+1] - tempi;
+ data[i] += tempr;
+ data[i+1] += tempi;
+ }
+ wr = (wtemp = wr)*wpr - wi*wpi + wr;
+ wi = wi*wpr + wtemp*wpi + wi;
+ }
+ mmax = istep;
+ }
+
+ // Inverse transform is scaled by 1/N
+ if (ifftFlag)
+ {
+ data++;
+ for(i = 0; i<2*N; i++)
+ {
+ data[i] /= N;
+ }
+ }
+}
+
+void ref_cfft_q31(
+ const arm_cfft_instance_q31 * S,
+ q31_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag)
+{
+ uint32_t i;
+ float32_t *fSrc = (float32_t*)p1;
+
+ for(i=0;i<S->fftLen*2;i++)
+ {
+ //read the q31 data, cast to float, scale down for float
+ fSrc[i] = (float32_t)p1[i] / 2147483648.0f;
+ }
+
+ switch(S->fftLen)
+ {
+ case 16:
+ ref_cfft_f32(&arm_cfft_sR_f32_len16, fSrc, ifftFlag, bitReverseFlag);
+ break;
+
+ case 32:
+ ref_cfft_f32(&arm_cfft_sR_f32_len32, fSrc, ifftFlag, bitReverseFlag);
+ break;
+
+ case 64:
+ ref_cfft_f32(&arm_cfft_sR_f32_len64, fSrc, ifftFlag, bitReverseFlag);
+ break;
+
+ case 128:
+ ref_cfft_f32(&arm_cfft_sR_f32_len128, fSrc, ifftFlag, bitReverseFlag);
+ break;
+
+ case 256:
+ ref_cfft_f32(&arm_cfft_sR_f32_len256, fSrc, ifftFlag, bitReverseFlag);
+ break;
+
+ case 512:
+ ref_cfft_f32(&arm_cfft_sR_f32_len512, fSrc, ifftFlag, bitReverseFlag);
+ break;
+
+ case 1024:
+ ref_cfft_f32(&arm_cfft_sR_f32_len1024, fSrc, ifftFlag, bitReverseFlag);
+ break;
+
+ case 2048:
+ ref_cfft_f32(&arm_cfft_sR_f32_len2048, fSrc, ifftFlag, bitReverseFlag);
+ break;
+
+ case 4096:
+ ref_cfft_f32(&arm_cfft_sR_f32_len4096, fSrc, ifftFlag, bitReverseFlag);
+ break;
+ }
+
+ if (ifftFlag)
+ {
+ for(i=0;i<S->fftLen*2;i++)
+ {
+ //read the float data, scale up for q31, cast to q31
+ p1[i] = (q31_t)( fSrc[i] * 2147483648.0f );
+ }
+ }
+ else
+ {
+ for(i=0;i<S->fftLen*2;i++)
+ {
+ //read the float data, scale up for q31, cast to q31
+ p1[i] = (q31_t)( fSrc[i] * 2147483648.0f / (float32_t)S->fftLen);
+ }
+ }
+}
+
+void ref_cfft_q15(
+ const arm_cfft_instance_q15 * S,
+ q15_t * pSrc,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag)
+{
+ uint32_t i;
+ float32_t *fSrc = (float32_t*)pSrc;
+
+ for(i=0;i<S->fftLen*2;i++)
+ {
+ //read the q15 data, cast to float, scale down for float, place in temporary buffer
+ scratchArray[i] = (float32_t)pSrc[i] / 32768.0f;
+ }
+
+ for(i=0;i<S->fftLen*2;i++)
+ {
+ //copy from temp buffer to final buffer
+ fSrc[i] = scratchArray[i];
+ }
+
+ switch(S->fftLen)
+ {
+ case 16:
+ ref_cfft_f32(&arm_cfft_sR_f32_len16, fSrc, ifftFlag, bitReverseFlag);
+ break;
+
+ case 32:
+ ref_cfft_f32(&arm_cfft_sR_f32_len32, fSrc, ifftFlag, bitReverseFlag);
+ break;
+
+ case 64:
+ ref_cfft_f32(&arm_cfft_sR_f32_len64, fSrc, ifftFlag, bitReverseFlag);
+ break;
+
+ case 128:
+ ref_cfft_f32(&arm_cfft_sR_f32_len128, fSrc, ifftFlag, bitReverseFlag);
+ break;
+
+ case 256:
+ ref_cfft_f32(&arm_cfft_sR_f32_len256, fSrc, ifftFlag, bitReverseFlag);
+ break;
+
+ case 512:
+ ref_cfft_f32(&arm_cfft_sR_f32_len512, fSrc, ifftFlag, bitReverseFlag);
+ break;
+
+ case 1024:
+ ref_cfft_f32(&arm_cfft_sR_f32_len1024, fSrc, ifftFlag, bitReverseFlag);
+ break;
+
+ case 2048:
+ ref_cfft_f32(&arm_cfft_sR_f32_len2048, fSrc, ifftFlag, bitReverseFlag);
+ break;
+
+ case 4096:
+ ref_cfft_f32(&arm_cfft_sR_f32_len4096, fSrc, ifftFlag, bitReverseFlag);
+ break;
+ }
+
+ if (ifftFlag)
+ {
+ for(i=0;i<S->fftLen*2;i++)
+ {
+ //read the float data, scale up for q15, cast to q15
+ pSrc[i] = (q15_t)( fSrc[i] * 32768.0f );
+ }
+ }
+ else
+ {
+ for(i=0;i<S->fftLen*2;i++)
+ {
+ //read the float data, scale up for q15, cast to q15
+ pSrc[i] = (q15_t)( fSrc[i] * 32768.0f / (float32_t)S->fftLen);
+ }
+ }
+}
+
+void ref_cfft_radix2_f32(
+ const arm_cfft_radix2_instance_f32 * S,
+ float32_t * pSrc)
+{
+ switch(S->fftLen)
+ {
+ case 16:
+ ref_cfft_f32(&arm_cfft_sR_f32_len16, pSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 32:
+ ref_cfft_f32(&arm_cfft_sR_f32_len32, pSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 64:
+ ref_cfft_f32(&arm_cfft_sR_f32_len64, pSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 128:
+ ref_cfft_f32(&arm_cfft_sR_f32_len128, pSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 256:
+ ref_cfft_f32(&arm_cfft_sR_f32_len256, pSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 512:
+ ref_cfft_f32(&arm_cfft_sR_f32_len512, pSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 1024:
+ ref_cfft_f32(&arm_cfft_sR_f32_len1024, pSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 2048:
+ ref_cfft_f32(&arm_cfft_sR_f32_len2048, pSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 4096:
+ ref_cfft_f32(&arm_cfft_sR_f32_len4096, pSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+ }
+}
+
+void ref_cfft_radix2_q31(
+ const arm_cfft_radix2_instance_q31 * S,
+ q31_t * pSrc)
+{
+ uint32_t i;
+ float32_t *fSrc = (float32_t*)pSrc;
+
+ for(i=0;i<S->fftLen*2;i++)
+ {
+ //read the q31 data, cast to float, scale down for float
+ fSrc[i] = (float32_t)pSrc[i] / 2147483648.0f;
+ }
+
+ switch(S->fftLen)
+ {
+ case 16:
+ ref_cfft_f32(&arm_cfft_sR_f32_len16, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 32:
+ ref_cfft_f32(&arm_cfft_sR_f32_len32, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 64:
+ ref_cfft_f32(&arm_cfft_sR_f32_len64, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 128:
+ ref_cfft_f32(&arm_cfft_sR_f32_len128, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 256:
+ ref_cfft_f32(&arm_cfft_sR_f32_len256, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 512:
+ ref_cfft_f32(&arm_cfft_sR_f32_len512, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 1024:
+ ref_cfft_f32(&arm_cfft_sR_f32_len1024, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 2048:
+ ref_cfft_f32(&arm_cfft_sR_f32_len2048, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 4096:
+ ref_cfft_f32(&arm_cfft_sR_f32_len4096, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+ }
+
+ if (S->ifftFlag)
+ {
+ for(i=0;i<S->fftLen*2;i++)
+ {
+ //read the float data, scale up for q31, cast to q31
+ pSrc[i] = (q31_t)( fSrc[i] * 2147483648.0f );
+ }
+ }
+ else
+ {
+ for(i=0;i<S->fftLen*2;i++)
+ {
+ //read the float data, scale up for q31, cast to q31
+ pSrc[i] = (q31_t)( fSrc[i] * 2147483648.0f / (float32_t)S->fftLen);
+ }
+ }
+}
+
+void ref_cfft_radix2_q15(
+ const arm_cfft_radix2_instance_q15 * S,
+ q15_t * pSrc)
+{
+ uint32_t i;
+ float32_t *fSrc = (float32_t*)pSrc;
+
+ for(i=0;i<S->fftLen*2;i++)
+ {
+ //read the q15 data, cast to float, scale down for float, place in temporary buffer
+ scratchArray[i] = (float32_t)pSrc[i] / 32768.0f;
+ }
+
+ for(i=0;i<S->fftLen*2;i++)
+ {
+ //copy from temp buffer to final buffer
+ fSrc[i] = scratchArray[i];
+ }
+
+ switch(S->fftLen)
+ {
+ case 16:
+ ref_cfft_f32(&arm_cfft_sR_f32_len16, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 32:
+ ref_cfft_f32(&arm_cfft_sR_f32_len32, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 64:
+ ref_cfft_f32(&arm_cfft_sR_f32_len64, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 128:
+ ref_cfft_f32(&arm_cfft_sR_f32_len128, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 256:
+ ref_cfft_f32(&arm_cfft_sR_f32_len256, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 512:
+ ref_cfft_f32(&arm_cfft_sR_f32_len512, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 1024:
+ ref_cfft_f32(&arm_cfft_sR_f32_len1024, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 2048:
+ ref_cfft_f32(&arm_cfft_sR_f32_len2048, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 4096:
+ ref_cfft_f32(&arm_cfft_sR_f32_len4096, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+ }
+
+ if (S->ifftFlag)
+ {
+ for(i=0;i<S->fftLen*2;i++)
+ {
+ //read the float data, scale up for q15, cast to q15
+ pSrc[i] = (q15_t)( fSrc[i] * 32768.0f );
+ }
+ }
+ else
+ {
+ for(i=0;i<S->fftLen*2;i++)
+ {
+ //read the float data, scale up for q15, cast to q15
+ pSrc[i] = (q15_t)( fSrc[i] * 32768.0f / (float32_t)S->fftLen);
+ }
+ }
+}
+
+void ref_cfft_radix4_f32(
+ const arm_cfft_radix4_instance_f32 * S,
+ float32_t * pSrc)
+{
+ switch(S->fftLen)
+ {
+ case 16:
+ ref_cfft_f32(&arm_cfft_sR_f32_len16, pSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 32:
+ ref_cfft_f32(&arm_cfft_sR_f32_len32, pSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 64:
+ ref_cfft_f32(&arm_cfft_sR_f32_len64, pSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 128:
+ ref_cfft_f32(&arm_cfft_sR_f32_len128, pSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 256:
+ ref_cfft_f32(&arm_cfft_sR_f32_len256, pSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 512:
+ ref_cfft_f32(&arm_cfft_sR_f32_len512, pSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 1024:
+ ref_cfft_f32(&arm_cfft_sR_f32_len1024, pSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 2048:
+ ref_cfft_f32(&arm_cfft_sR_f32_len2048, pSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 4096:
+ ref_cfft_f32(&arm_cfft_sR_f32_len4096, pSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+ }
+}
+
+void ref_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc)
+{
+ uint32_t i;
+ float32_t *fSrc = (float32_t*)pSrc;
+
+ for(i=0;i<S->fftLen*2;i++)
+ {
+ //read the q31 data, cast to float, scale down for float
+ fSrc[i] = (float32_t)pSrc[i] / 2147483648.0f;
+ }
+
+ switch(S->fftLen)
+ {
+ case 16:
+ ref_cfft_f32(&arm_cfft_sR_f32_len16, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 32:
+ ref_cfft_f32(&arm_cfft_sR_f32_len32, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 64:
+ ref_cfft_f32(&arm_cfft_sR_f32_len64, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 128:
+ ref_cfft_f32(&arm_cfft_sR_f32_len128, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 256:
+ ref_cfft_f32(&arm_cfft_sR_f32_len256, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 512:
+ ref_cfft_f32(&arm_cfft_sR_f32_len512, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 1024:
+ ref_cfft_f32(&arm_cfft_sR_f32_len1024, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 2048:
+ ref_cfft_f32(&arm_cfft_sR_f32_len2048, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 4096:
+ ref_cfft_f32(&arm_cfft_sR_f32_len4096, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+ }
+
+ if (S->ifftFlag)
+ {
+ for(i=0;i<S->fftLen*2;i++)
+ {
+ //read the float data, scale up for q31, cast to q31
+ pSrc[i] = (q31_t)( fSrc[i] * 2147483648.0f );
+ }
+ }
+ else
+ {
+ for(i=0;i<S->fftLen*2;i++)
+ {
+ //read the float data, scale up for q31, cast to q31
+ pSrc[i] = (q31_t)( fSrc[i] * 2147483648.0f / (float32_t)S->fftLen);
+ }
+ }
+}
+
+void ref_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc)
+{
+ uint32_t i;
+ float32_t *fSrc = (float32_t*)pSrc;
+
+ for(i=0;i<S->fftLen*2;i++)
+ {
+ //read the q15 data, cast to float, scale down for float, place in temporary buffer
+ scratchArray[i] = (float32_t)pSrc[i] / 32768.0f;
+ }
+
+ for(i=0;i<S->fftLen*2;i++)
+ {
+ //copy from temp buffer to final buffer
+ fSrc[i] = scratchArray[i];
+ }
+
+ switch(S->fftLen)
+ {
+ case 16:
+ ref_cfft_f32(&arm_cfft_sR_f32_len16, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 32:
+ ref_cfft_f32(&arm_cfft_sR_f32_len32, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 64:
+ ref_cfft_f32(&arm_cfft_sR_f32_len64, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 128:
+ ref_cfft_f32(&arm_cfft_sR_f32_len128, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 256:
+ ref_cfft_f32(&arm_cfft_sR_f32_len256, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 512:
+ ref_cfft_f32(&arm_cfft_sR_f32_len512, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 1024:
+ ref_cfft_f32(&arm_cfft_sR_f32_len1024, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 2048:
+ ref_cfft_f32(&arm_cfft_sR_f32_len2048, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+
+ case 4096:
+ ref_cfft_f32(&arm_cfft_sR_f32_len4096, fSrc, S->ifftFlag, S->bitReverseFlag);
+ break;
+ }
+
+ if (S->ifftFlag)
+ {
+ for(i=0;i<S->fftLen*2;i++)
+ {
+ //read the float data, scale up for q15, cast to q15
+ pSrc[i] = (q15_t)( fSrc[i] * 32768.0f );
+ }
+ }
+ else
+ {
+ for(i=0;i<S->fftLen*2;i++)
+ {
+ //read the float data, scale up for q15, cast to q15
+ pSrc[i] = (q15_t)( fSrc[i] * 32768.0f / (float32_t)S->fftLen);
+ }
+ }
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/dct4.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/dct4.c
new file mode 100644
index 0000000..9c1f207
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/dct4.c
@@ -0,0 +1,89 @@
+#include "ref.h"
+
+void ref_dct4_f32(
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer)
+{
+ uint32_t n,k;
+ float32_t sum;
+ float32_t pi_by_N = 3.14159265358979f / (float32_t)S->N;
+ float32_t tmp;
+ float32_t normalize = sqrtf(2.0f / (float32_t)S->N);
+
+ for(k=0;k<S->N;k++)
+ {
+ sum=0.0f;
+ tmp = ((float32_t)k + 0.5f)*pi_by_N;
+ for(n=0;n<S->N;n++)
+ {
+ sum += pInlineBuffer[n] * cosf(tmp * ((float32_t)n + 0.5f));
+ }
+ scratchArray[k] = normalize * sum;
+ }
+
+ for(k=0;k<S->N;k++)
+ {
+ pInlineBuffer[k] = scratchArray[k];
+ }
+}
+
+void ref_dct4_q31(
+ const arm_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer)
+{
+ arm_dct4_instance_f32 SS;
+ float32_t *fSrc = (float32_t*)pInlineBuffer;
+ uint32_t i;
+
+ SS.N = S->N;
+
+ for(i=0;i<S->N;i++)
+ {
+ //read the q31 data, cast to float, scale down for float
+ fSrc[i] = (float32_t)pInlineBuffer[i] / 2147483648.0f;
+ }
+
+ ref_dct4_f32(&SS,(float32_t*)0,fSrc);
+
+ for(i=0;i<S->N;i++)
+ {
+ fSrc[i] = fSrc[i] * 2147483648.0f / (float32_t)S->N ;
+ fSrc[i] += (fSrc[i] > 0) ? 0.5f : -0.5f;
+ pInlineBuffer[i] = (q31_t)fSrc[i];
+ }
+}
+
+void ref_dct4_q15(
+ const arm_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer)
+{
+ arm_dct4_instance_f32 SS;
+ float32_t *fSrc = (float32_t*)pInlineBuffer;
+ uint32_t i;
+
+ SS.N = S->N;
+
+ for(i=0;i<S->N;i++)
+ {
+ //read the q15 data, cast to float, scale down for float, place in temporary buffer
+ scratchArray[i] = (float32_t)pInlineBuffer[i] / 32768.0f;
+ }
+
+ for(i=0;i<S->N;i++)
+ {
+ //copy from temp buffer to final buffer
+ fSrc[i] = scratchArray[i];
+ }
+
+ ref_dct4_f32(&SS,(float32_t*)0,fSrc);
+
+ for(i=0;i<S->N;i++)
+ {
+ fSrc[i] = fSrc[i] * 32768.0f / (float32_t)S->N;
+ fSrc[i] += (fSrc[i] > 0) ? 0.5f : -0.5f;
+ pInlineBuffer[i] = (q15_t)fSrc[i];
+ }
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/rfft.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/rfft.c
new file mode 100644
index 0000000..79738f0
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/rfft.c
@@ -0,0 +1,302 @@
+#include "ref.h"
+#include "arm_const_structs.h"
+
+void ref_rfft_f32(
+ arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst)
+{
+ uint32_t i;
+
+ if (S->ifftFlagR)
+ {
+ for(i=0;i<S->fftLenReal*2;i++)
+ {
+ pDst[i] = pSrc[i];
+ }
+ }
+ else
+ {
+ for(i=0;i<S->fftLenReal;i++)
+ {
+ pDst[2*i+0] = pSrc[i];
+ pDst[2*i+1] = 0.0f;
+ }
+ }
+
+ switch(S->fftLenReal)
+ {
+ case 128:
+ ref_cfft_f32(&arm_cfft_sR_f32_len128, pDst, S->ifftFlagR, S->bitReverseFlagR);
+ break;
+
+ case 512:
+ ref_cfft_f32(&arm_cfft_sR_f32_len512, pDst, S->ifftFlagR, S->bitReverseFlagR);
+ break;
+
+ case 2048:
+ ref_cfft_f32(&arm_cfft_sR_f32_len2048, pDst, S->ifftFlagR, S->bitReverseFlagR);
+ break;
+
+ case 8192:
+ ref_cfft_f32(&ref_cfft_sR_f32_len8192, pDst, S->ifftFlagR, S->bitReverseFlagR);
+ break;
+ }
+
+ if (S->ifftFlagR)
+ {
+ //throw away the imaginary part which should be all zeros
+ for(i=0;i<S->fftLenReal;i++)
+ {
+ pDst[i] = pDst[2*i];
+ }
+ }
+}
+
+void ref_rfft_fast_f32(
+ arm_rfft_fast_instance_f32 * S,
+ float32_t * p, float32_t * pOut,
+ uint8_t ifftFlag)
+{
+ uint32_t i,j;
+
+ if (ifftFlag)
+ {
+ for(i=0;i<S->fftLenRFFT;i++)
+ {
+ pOut[i] = p[i];
+ }
+ //unpack first sample's complex part into middle sample's real part
+ pOut[S->fftLenRFFT] = pOut[1];
+ pOut[S->fftLenRFFT+1] = 0;
+ pOut[1] = 0;
+ j=4;
+ for(i = S->fftLenRFFT / 2 + 1;i < S->fftLenRFFT;i++)
+ {
+ pOut[2*i+0] = p[2*i+0 - j];
+ pOut[2*i+1] = -p[2*i+1 - j];
+ j+=4;
+ }
+ }
+ else
+ {
+ for(i=0;i<S->fftLenRFFT;i++)
+ {
+ pOut[2*i+0] = p[i];
+ pOut[2*i+1] = 0.0f;
+ }
+ }
+
+ switch(S->fftLenRFFT)
+ {
+ case 32:
+ ref_cfft_f32(&arm_cfft_sR_f32_len32, pOut, ifftFlag, 1);
+ break;
+
+ case 64:
+ ref_cfft_f32(&arm_cfft_sR_f32_len64, pOut, ifftFlag, 1);
+ break;
+
+ case 128:
+ ref_cfft_f32(&arm_cfft_sR_f32_len128, pOut, ifftFlag, 1);
+ break;
+
+ case 256:
+ ref_cfft_f32(&arm_cfft_sR_f32_len256, pOut, ifftFlag, 1);
+ break;
+
+ case 512:
+ ref_cfft_f32(&arm_cfft_sR_f32_len512, pOut, ifftFlag, 1);
+ break;
+
+ case 1024:
+ ref_cfft_f32(&arm_cfft_sR_f32_len1024, pOut, ifftFlag, 1);
+ break;
+
+ case 2048:
+ ref_cfft_f32(&arm_cfft_sR_f32_len2048, pOut, ifftFlag, 1);
+ break;
+
+ case 4096:
+ ref_cfft_f32(&arm_cfft_sR_f32_len4096, pOut, ifftFlag, 1);
+ break;
+ }
+
+ if (ifftFlag)
+ {
+ //throw away the imaginary part which should be all zeros
+ for(i=0;i<S->fftLenRFFT;i++)
+ {
+ pOut[i] = pOut[2*i];
+ }
+ }
+ else
+ {
+ //pack last sample's real part into first sample's complex part
+ pOut[1] = pOut[S->fftLenRFFT];
+ }
+}
+
+void ref_rfft_q31(
+ const arm_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst)
+{
+ uint32_t i;
+ float32_t *fDst = (float32_t*)pDst;
+
+ if (S->ifftFlagR)
+ {
+ for(i=0;i<S->fftLenReal*2;i++)
+ {
+ fDst[i] = (float32_t)pSrc[i] / 2147483648.0f;
+ }
+ }
+ else
+ {
+ for(i=0;i<S->fftLenReal;i++)
+ {
+ fDst[2*i+0] = (float32_t)pSrc[i] / 2147483648.0f;
+ fDst[2*i+1] = 0.0f;
+ }
+ }
+
+ switch(S->fftLenReal)
+ {
+ case 32:
+ ref_cfft_f32(&arm_cfft_sR_f32_len32, fDst, S->ifftFlagR, S->bitReverseFlagR);
+ break;
+
+ case 64:
+ ref_cfft_f32(&arm_cfft_sR_f32_len64, fDst, S->ifftFlagR, S->bitReverseFlagR);
+ break;
+
+ case 128:
+ ref_cfft_f32(&arm_cfft_sR_f32_len128, fDst, S->ifftFlagR, S->bitReverseFlagR);
+ break;
+
+ case 256:
+ ref_cfft_f32(&arm_cfft_sR_f32_len256, fDst, S->ifftFlagR, S->bitReverseFlagR);
+ break;
+
+ case 512:
+ ref_cfft_f32(&arm_cfft_sR_f32_len512, fDst, S->ifftFlagR, S->bitReverseFlagR);
+ break;
+
+ case 1024:
+ ref_cfft_f32(&arm_cfft_sR_f32_len1024, fDst, S->ifftFlagR, S->bitReverseFlagR);
+ break;
+
+ case 2048:
+ ref_cfft_f32(&arm_cfft_sR_f32_len2048, fDst, S->ifftFlagR, S->bitReverseFlagR);
+ break;
+
+ case 4096:
+ ref_cfft_f32(&arm_cfft_sR_f32_len4096, fDst, S->ifftFlagR, S->bitReverseFlagR);
+ break;
+
+ case 8192:
+ ref_cfft_f32(&ref_cfft_sR_f32_len8192, fDst, S->ifftFlagR, S->bitReverseFlagR);
+ break;
+ }
+
+ if (S->ifftFlagR)
+ {
+ //throw away the imaginary part which should be all zeros
+ for(i=0;i<S->fftLenReal;i++)
+ {
+ //read the float data, scale up for q31, cast to q31
+ pDst[i] = (q31_t)( fDst[2*i] * 2147483648.0f);
+ }
+ }
+ else
+ {
+ for(i=0;i<S->fftLenReal;i++)
+ {
+ //read the float data, scale up for q31, cast to q31
+ pDst[i] = (q31_t)( fDst[i] * 2147483648.0f / (float32_t)S->fftLenReal);
+ }
+ }
+}
+
+void ref_rfft_q15(
+ const arm_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst)
+{
+ uint32_t i;
+ float32_t *fDst = (float32_t*)pDst;
+
+
+ if (S->ifftFlagR)
+ {
+ for(i=0;i<S->fftLenReal*2;i++)
+ {
+ fDst[i] = (float32_t)pSrc[i] / 32768.0f;
+ }
+ }
+ else
+ {
+ for(i=0;i<S->fftLenReal;i++)
+ {
+ //read the q15 data, cast to float, scale down for float
+ fDst[2*i+0] = (float32_t)pSrc[i] / 32768.0f;
+ fDst[2*i+1] = 0.0f;
+ }
+ }
+
+ switch(S->fftLenReal)
+ {
+ case 32:
+ ref_cfft_f32(&arm_cfft_sR_f32_len32, fDst, S->ifftFlagR, S->bitReverseFlagR);
+ break;
+
+ case 64:
+ ref_cfft_f32(&arm_cfft_sR_f32_len64, fDst, S->ifftFlagR, S->bitReverseFlagR);
+ break;
+
+ case 128:
+ ref_cfft_f32(&arm_cfft_sR_f32_len128, fDst, S->ifftFlagR, S->bitReverseFlagR);
+ break;
+
+ case 256:
+ ref_cfft_f32(&arm_cfft_sR_f32_len256, fDst, S->ifftFlagR, S->bitReverseFlagR);
+ break;
+
+ case 512:
+ ref_cfft_f32(&arm_cfft_sR_f32_len512, fDst, S->ifftFlagR, S->bitReverseFlagR);
+ break;
+
+ case 1024:
+ ref_cfft_f32(&arm_cfft_sR_f32_len1024, fDst, S->ifftFlagR, S->bitReverseFlagR);
+ break;
+
+ case 2048:
+ ref_cfft_f32(&arm_cfft_sR_f32_len2048, fDst, S->ifftFlagR, S->bitReverseFlagR);
+ break;
+
+ case 4096:
+ ref_cfft_f32(&arm_cfft_sR_f32_len4096, fDst, S->ifftFlagR, S->bitReverseFlagR);
+ break;
+
+ case 8192:
+ ref_cfft_f32(&ref_cfft_sR_f32_len8192, fDst, S->ifftFlagR, S->bitReverseFlagR);
+ break;
+ }
+
+ if (S->ifftFlagR)
+ {
+ //throw away the imaginary part which should be all zeros
+ for(i=0;i<S->fftLenReal;i++)
+ {
+ pDst[i] = (q15_t)( fDst[2*i] * 32768.0f);
+ }
+ }
+ else
+ {
+ for(i=0;i<S->fftLenReal;i++)
+ {
+ pDst[i] = (q15_t)( fDst[i] * 32768.0f / (float32_t)S->fftLenReal);
+ }
+ }
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example_f32.c
new file mode 100644
index 0000000..e6842de
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example_f32.c
@@ -0,0 +1,211 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.0
+*
+* Project: CMSIS DSP Library
+* Title: arm_class_marks_example_f32.c
+*
+* Description: Example code to calculate Minimum, Maximum
+* Mean, std and variance of marks obtained in a class
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+/**
+ * @ingroup groupExamples
+ */
+
+/**
+ * @defgroup ClassMarks Class Marks Example
+ *
+ * \par Description:
+ * \par
+ * Demonstrates the use the Maximum, Minimum, Mean, Standard Deviation, Variance
+ * and Matrix functions to calculate statistical values of marks obtained in a class.
+ *
+ * \note This example also demonstrates the usage of static initialization.
+ *
+ * \par Variables Description:
+ * \par
+ * \li \c testMarks_f32 points to the marks scored by 20 students in 4 subjects
+ * \li \c max_marks Maximum of all marks
+ * \li \c min_marks Minimum of all marks
+ * \li \c mean Mean of all marks
+ * \li \c var Variance of the marks
+ * \li \c std Standard deviation of the marks
+ * \li \c numStudents Total number of students in the class
+ *
+ * \par CMSIS DSP Software Library Functions Used:
+ * \par
+ * - arm_mat_init_f32()
+ * - arm_mat_mult_f32()
+ * - arm_max_f32()
+ * - arm_min_f32()
+ * - arm_mean_f32()
+ * - arm_std_f32()
+ * - arm_var_f32()
+ *
+ * <b> Refer </b>
+ * \link arm_class_marks_example_f32.c \endlink
+ *
+ */
+
+
+/** \example arm_class_marks_example_f32.c
+ */
+#include "arm_math.h"
+
+#define USE_STATIC_INIT
+
+ /* ----------------------------------------------------------------------
+** Global defines
+** ------------------------------------------------------------------- */
+
+#define TEST_LENGTH_SAMPLES (20*4)
+
+/* ----------------------------------------------------------------------
+** List of Marks scored by 20 students for 4 subjects
+** ------------------------------------------------------------------- */
+const float32_t testMarks_f32[TEST_LENGTH_SAMPLES] =
+{
+ 42.000000, 37.000000, 81.000000, 28.000000,
+ 83.000000, 72.000000, 36.000000, 38.000000,
+ 32.000000, 51.000000, 63.000000, 64.000000,
+ 97.000000, 82.000000, 95.000000, 90.000000,
+ 66.000000, 51.000000, 54.000000, 42.000000,
+ 67.000000, 56.000000, 45.000000, 57.000000,
+ 67.000000, 69.000000, 35.000000, 52.000000,
+ 29.000000, 81.000000, 58.000000, 47.000000,
+ 38.000000, 76.000000, 100.000000, 29.000000,
+ 33.000000, 47.000000, 29.000000, 50.000000,
+ 34.000000, 41.000000, 61.000000, 46.000000,
+ 52.000000, 50.000000, 48.000000, 36.000000,
+ 47.000000, 55.000000, 44.000000, 40.000000,
+ 100.000000, 94.000000, 84.000000, 37.000000,
+ 32.000000, 71.000000, 47.000000, 77.000000,
+ 31.000000, 50.000000, 49.000000, 35.000000,
+ 63.000000, 67.000000, 40.000000, 31.000000,
+ 29.000000, 68.000000, 61.000000, 38.000000,
+ 31.000000, 28.000000, 28.000000, 76.000000,
+ 55.000000, 33.000000, 29.000000, 39.000000
+};
+
+
+/* ----------------------------------------------------------------------
+* Number of subjects X 1
+* ------------------------------------------------------------------- */
+const float32_t testUnity_f32[4] =
+{
+ 1.000, 1.000, 1.000, 1.000
+};
+
+
+/* ----------------------------------------------------------------------
+** f32 Output buffer
+** ------------------------------------------------------------------- */
+static float32_t testOutput[TEST_LENGTH_SAMPLES];
+
+
+/* ------------------------------------------------------------------
+* Global defines
+*------------------------------------------------------------------- */
+#define NUMSTUDENTS 20
+#define NUMSUBJECTS 4
+
+/* ------------------------------------------------------------------
+* Global variables
+*------------------------------------------------------------------- */
+
+ uint32_t numStudents = 20;
+ uint32_t numSubjects = 4;
+float32_t max_marks, min_marks, mean, std, var;
+ uint32_t student_num;
+
+/* ----------------------------------------------------------------------------------
+* Main f32 test function. It returns maximum marks secured and student number
+* ------------------------------------------------------------------------------- */
+
+int32_t main()
+{
+
+#ifndef USE_STATIC_INIT
+
+ arm_matrix_instance_f32 srcA;
+ arm_matrix_instance_f32 srcB;
+ arm_matrix_instance_f32 dstC;
+
+ /* Input and output matrices initializations */
+ arm_mat_init_f32(&srcA, numStudents, numSubjects, (float32_t *)testMarks_f32);
+ arm_mat_init_f32(&srcB, numSubjects, 1, (float32_t *)testUnity_f32);
+ arm_mat_init_f32(&dstC, numStudents, 1, testOutput);
+
+#else
+
+ /* Static Initializations of Input and output matrix sizes and array */
+ arm_matrix_instance_f32 srcA = {NUMSTUDENTS, NUMSUBJECTS, (float32_t *)testMarks_f32};
+ arm_matrix_instance_f32 srcB = {NUMSUBJECTS, 1, (float32_t *)testUnity_f32};
+ arm_matrix_instance_f32 dstC = {NUMSTUDENTS, 1, testOutput};
+
+#endif
+
+
+ /* ----------------------------------------------------------------------
+ *Call the Matrix multiplication process function
+ * ------------------------------------------------------------------- */
+ arm_mat_mult_f32(&srcA, &srcB, &dstC);
+
+ /* ----------------------------------------------------------------------
+ ** Call the Max function to calculate max marks among numStudents
+ ** ------------------------------------------------------------------- */
+ arm_max_f32(testOutput, numStudents, &max_marks, &student_num);
+
+ /* ----------------------------------------------------------------------
+ ** Call the Min function to calculate min marks among numStudents
+ ** ------------------------------------------------------------------- */
+ arm_min_f32(testOutput, numStudents, &min_marks, &student_num);
+
+ /* ----------------------------------------------------------------------
+ ** Call the Mean function to calculate mean
+ ** ------------------------------------------------------------------- */
+ arm_mean_f32(testOutput, numStudents, &mean);
+
+ /* ----------------------------------------------------------------------
+ ** Call the std function to calculate standard deviation
+ ** ------------------------------------------------------------------- */
+ arm_std_f32(testOutput, numStudents, &std);
+
+ /* ----------------------------------------------------------------------
+ ** Call the var function to calculate variance
+ ** ------------------------------------------------------------------- */
+ arm_var_f32(testOutput, numStudents, &var);
+
+ while (1); /* main function does not return */
+}
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example_f32.c
new file mode 100644
index 0000000..e4665fe
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example_f32.c
@@ -0,0 +1,247 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.0
+*
+* Project: CMSIS DSP Library
+* Title: arm_convolution_example_f32.c
+*
+* Description: Example code demonstrating Convolution of two input signals using fft.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+/**
+ * @ingroup groupExamples
+ */
+
+/**
+ * @defgroup ConvolutionExample Convolution Example
+ *
+ * \par Description:
+ * \par
+ * Demonstrates the convolution theorem with the use of the Complex FFT, Complex-by-Complex
+ * Multiplication, and Support Functions.
+ *
+ * \par Algorithm:
+ * \par
+ * The convolution theorem states that convolution in the time domain corresponds to
+ * multiplication in the frequency domain. Therefore, the Fourier transform of the convoution of
+ * two signals is equal to the product of their individual Fourier transforms.
+ * The Fourier transform of a signal can be evaluated efficiently using the Fast Fourier Transform (FFT).
+ * \par
+ * Two input signals, <code>a[n]</code> and <code>b[n]</code>, with lengths \c n1 and \c n2 respectively,
+ * are zero padded so that their lengths become \c N, which is greater than or equal to <code>(n1+n2-1)</code>
+ * and is a power of 4 as FFT implementation is radix-4.
+ * The convolution of <code>a[n]</code> and <code>b[n]</code> is obtained by taking the FFT of the input
+ * signals, multiplying the Fourier transforms of the two signals, and taking the inverse FFT of
+ * the multiplied result.
+ * \par
+ * This is denoted by the following equations:
+ * <pre> A[k] = FFT(a[n],N)
+ * B[k] = FFT(b[n],N)
+ * conv(a[n], b[n]) = IFFT(A[k] * B[k], N)</pre>
+ * where <code>A[k]</code> and <code>B[k]</code> are the N-point FFTs of the signals <code>a[n]</code>
+ * and <code>b[n]</code> respectively.
+ * The length of the convolved signal is <code>(n1+n2-1)</code>.
+ *
+ * \par Block Diagram:
+ * \par
+ * \image html Convolution.gif
+ *
+ * \par Variables Description:
+ * \par
+ * \li \c testInputA_f32 points to the first input sequence
+ * \li \c srcALen length of the first input sequence
+ * \li \c testInputB_f32 points to the second input sequence
+ * \li \c srcBLen length of the second input sequence
+ * \li \c outLen length of convolution output sequence, <code>(srcALen + srcBLen - 1)</code>
+ * \li \c AxB points to the output array where the product of individual FFTs of inputs is stored.
+ *
+ * \par CMSIS DSP Software Library Functions Used:
+ * \par
+ * - arm_fill_f32()
+ * - arm_copy_f32()
+ * - arm_cfft_radix4_init_f32()
+ * - arm_cfft_radix4_f32()
+ * - arm_cmplx_mult_cmplx_f32()
+ *
+ * <b> Refer </b>
+ * \link arm_convolution_example_f32.c \endlink
+ *
+ */
+
+
+/** \example arm_convolution_example_f32.c
+ */
+
+#include "arm_math.h"
+#include "math_helper.h"
+
+/* ----------------------------------------------------------------------
+* Defines each of the tests performed
+* ------------------------------------------------------------------- */
+#define MAX_BLOCKSIZE 128
+#define DELTA (0.000001f)
+#define SNR_THRESHOLD 90
+
+/* ----------------------------------------------------------------------
+* Declare I/O buffers
+* ------------------------------------------------------------------- */
+float32_t Ak[MAX_BLOCKSIZE]; /* Input A */
+float32_t Bk[MAX_BLOCKSIZE]; /* Input B */
+float32_t AxB[MAX_BLOCKSIZE * 2]; /* Output */
+
+/* ----------------------------------------------------------------------
+* Test input data for Floating point Convolution example for 32-blockSize
+* Generated by the MATLAB randn() function
+* ------------------------------------------------------------------- */
+float32_t testInputA_f32[64] =
+{
+ -0.808920, 1.357369, 1.180861, -0.504544, 1.762637, -0.703285,
+ 1.696966, 0.620571, -0.151093, -0.100235, -0.872382, -0.403579,
+ -0.860749, -0.382648, -1.052338, 0.128113, -0.646269, 1.093377,
+ -2.209198, 0.471706, 0.408901, 1.266242, 0.598252, 1.176827,
+ -0.203421, 0.213596, -0.851964, -0.466958, 0.021841, -0.698938,
+ -0.604107, 0.461778, -0.318219, 0.942520, 0.577585, 0.417619,
+ 0.614665, 0.563679, -1.295073, -0.764437, 0.952194, -0.859222,
+ -0.618554, -2.268542, -1.210592, 1.655853, -2.627219, -0.994249,
+ -1.374704, 0.343799, 0.025619, 1.227481, -0.708031, 0.069355,
+ -1.845228, -1.570886, 1.010668, -1.802084, 1.630088, 1.286090,
+ -0.161050, -0.940794, 0.367961, 0.291907
+
+};
+
+float32_t testInputB_f32[64] =
+{
+ 0.933724, 0.046881, 1.316470, 0.438345, 0.332682, 2.094885,
+ 0.512081, 0.035546, 0.050894, -2.320371, 0.168711, -1.830493,
+ -0.444834, -1.003242, -0.531494, -1.365600, -0.155420, -0.757692,
+ -0.431880, -0.380021, 0.096243, -0.695835, 0.558850, -1.648962,
+ 0.020369, -0.363630, 0.887146, 0.845503, -0.252864, -0.330397,
+ 1.269131, -1.109295, -1.027876, 0.135940, 0.116721, -0.293399,
+ -1.349799, 0.166078, -0.802201, 0.369367, -0.964568, -2.266011,
+ 0.465178, 0.651222, -0.325426, 0.320245, -0.784178, -0.579456,
+ 0.093374, 0.604778, -0.048225, 0.376297, -0.394412, 0.578182,
+ -1.218141, -1.387326, 0.692462, -0.631297, 0.153137, -0.638952,
+ 0.635474, -0.970468, 1.334057, -0.111370
+};
+
+const float testRefOutput_f32[127] =
+{
+ -0.818943, 1.229484, -0.533664, 1.016604, 0.341875, -1.963656,
+ 5.171476, 3.478033, 7.616361, 6.648384, 0.479069, 1.792012,
+ -1.295591, -7.447818, 0.315830, -10.657445, -2.483469, -6.524236,
+ -7.380591, -3.739005, -8.388957, 0.184147, -1.554888, 3.786508,
+ -1.684421, 5.400610, -1.578126, 7.403361, 8.315999, 2.080267,
+ 11.077776, 2.749673, 7.138962, 2.748762, 0.660363, 0.981552,
+ 1.442275, 0.552721, -2.576892, 4.703989, 0.989156, 8.759344,
+ -0.564825, -3.994680, 0.954710, -5.014144, 6.592329, 1.599488,
+ -13.979146, -0.391891, -4.453369, -2.311242, -2.948764, 1.761415,
+ -0.138322, 10.433007, -2.309103, 4.297153, 8.535523, 3.209462,
+ 8.695819, 5.569919, 2.514304, 5.582029, 2.060199, 0.642280,
+ 7.024616, 1.686615, -6.481756, 1.343084, -3.526451, 1.099073,
+ -2.965764, -0.173723, -4.111484, 6.528384, -6.965658, 1.726291,
+ 1.535172, 11.023435, 2.338401, -4.690188, 1.298210, 3.943885,
+ 8.407885, 5.168365, 0.684131, 1.559181, 1.859998, 2.852417,
+ 8.574070, -6.369078, 6.023458, 11.837963, -6.027632, 4.469678,
+ -6.799093, -2.674048, 6.250367, -6.809971, -3.459360, 9.112410,
+ -2.711621, -1.336678, 1.564249, -1.564297, -1.296760, 8.904013,
+ -3.230109, 6.878013, -7.819823, 3.369909, -1.657410, -2.007358,
+ -4.112825, 1.370685, -3.420525, -6.276605, 3.244873, -3.352638,
+ 1.545372, 0.902211, 0.197489, -1.408732, 0.523390, 0.348440, 0
+};
+
+
+/* ----------------------------------------------------------------------
+* Declare Global variables
+* ------------------------------------------------------------------- */
+uint32_t srcALen = 64; /* Length of Input A */
+uint32_t srcBLen = 64; /* Length of Input B */
+uint32_t outLen; /* Length of convolution output */
+float32_t snr; /* output SNR */
+
+int32_t main(void)
+{
+ arm_status status; /* Status of the example */
+ arm_cfft_radix4_instance_f32 cfft_instance; /* CFFT Structure instance */
+
+ /* CFFT Structure instance pointer */
+ arm_cfft_radix4_instance_f32 *cfft_instance_ptr =
+ (arm_cfft_radix4_instance_f32*) &cfft_instance;
+
+ /* output length of convolution */
+ outLen = srcALen + srcBLen - 1;
+
+ /* Initialise the fft input buffers with all zeros */
+ arm_fill_f32(0.0, Ak, MAX_BLOCKSIZE);
+ arm_fill_f32(0.0, Bk, MAX_BLOCKSIZE);
+
+ /* Copy the input values to the fft input buffers */
+ arm_copy_f32(testInputA_f32, Ak, MAX_BLOCKSIZE/2);
+ arm_copy_f32(testInputB_f32, Bk, MAX_BLOCKSIZE/2);
+
+ /* Initialize the CFFT function to compute 64 point fft */
+ status = arm_cfft_radix4_init_f32(cfft_instance_ptr, 64, 0, 1);
+
+ /* Transform input a[n] from time domain to frequency domain A[k] */
+ arm_cfft_radix4_f32(cfft_instance_ptr, Ak);
+ /* Transform input b[n] from time domain to frequency domain B[k] */
+ arm_cfft_radix4_f32(cfft_instance_ptr, Bk);
+
+ /* Complex Multiplication of the two input buffers in frequency domain */
+ arm_cmplx_mult_cmplx_f32(Ak, Bk, AxB, MAX_BLOCKSIZE/2);
+
+ /* Initialize the CIFFT function to compute 64 point ifft */
+ status = arm_cfft_radix4_init_f32(cfft_instance_ptr, 64, 1, 1);
+
+ /* Transform the multiplication output from frequency domain to time domain,
+ that gives the convolved output */
+ arm_cfft_radix4_f32(cfft_instance_ptr, AxB);
+
+ /* SNR Calculation */
+ snr = arm_snr_f32((float32_t *)testRefOutput_f32, AxB, srcALen + srcBLen - 1);
+
+ /* Compare the SNR with threshold to test whether the
+ computed output is matched with the reference output values. */
+ if ( snr > SNR_THRESHOLD)
+ {
+ status = ARM_MATH_SUCCESS;
+ }
+
+ if ( status != ARM_MATH_SUCCESS)
+ {
+ while (1);
+ }
+
+ while (1); /* main function does not return */
+}
+
+ /** \endlink */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.c
new file mode 100644
index 0000000..f615e6f
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.c
@@ -0,0 +1,466 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.0 b
+*
+* Project: CMSIS DSP Library
+*
+* Title: math_helper.c
+*
+* Description: Definition of all helper functions required.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+/* ----------------------------------------------------------------------
+* Include standard header files
+* -------------------------------------------------------------------- */
+#include<math.h>
+
+/* ----------------------------------------------------------------------
+* Include project header files
+* -------------------------------------------------------------------- */
+#include "math_helper.h"
+
+/**
+ * @brief Caluclation of SNR
+ * @param[in] pRef Pointer to the reference buffer
+ * @param[in] pTest Pointer to the test buffer
+ * @param[in] buffSize total number of samples
+ * @return SNR
+ * The function Caluclates signal to noise ratio for the reference output
+ * and test output
+ */
+
+float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize)
+{
+ float EnergySignal = 0.0, EnergyError = 0.0;
+ uint32_t i;
+ float SNR;
+ int temp;
+ int *test;
+
+ for (i = 0; i < buffSize; i++)
+ {
+ /* Checking for a NAN value in pRef array */
+ test = (int *)(&pRef[i]);
+ temp = *test;
+
+ if (temp == 0x7FC00000)
+ {
+ return(0);
+ }
+
+ /* Checking for a NAN value in pTest array */
+ test = (int *)(&pTest[i]);
+ temp = *test;
+
+ if (temp == 0x7FC00000)
+ {
+ return(0);
+ }
+ EnergySignal += pRef[i] * pRef[i];
+ EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]);
+ }
+
+ /* Checking for a NAN value in EnergyError */
+ test = (int *)(&EnergyError);
+ temp = *test;
+
+ if (temp == 0x7FC00000)
+ {
+ return(0);
+ }
+
+
+ SNR = 10 * log10 (EnergySignal / EnergyError);
+
+ return (SNR);
+
+}
+
+
+/**
+ * @brief Provide guard bits for Input buffer
+ * @param[in,out] input_buf Pointer to input buffer
+ * @param[in] blockSize block Size
+ * @param[in] guard_bits guard bits
+ * @return none
+ * The function Provides the guard bits for the buffer
+ * to avoid overflow
+ */
+
+void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < blockSize; i++)
+ {
+ input_buf[i] = input_buf[i] >> guard_bits;
+ }
+}
+
+/**
+ * @brief Converts float to fixed in q12.20 format
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to outputbuffer
+ * @param[in] numSamples number of samples in the input buffer
+ * @return none
+ * The function converts floating point values to fixed point(q12.20) values
+ */
+
+void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 1048576.0f corresponds to pow(2, 20) */
+ pOut[i] = (q31_t) (pIn[i] * 1048576.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 1.0)
+ {
+ pOut[i] = 0x000FFFFF;
+ }
+ }
+}
+
+/**
+ * @brief Compare MATLAB Reference Output and ARM Test output
+ * @param[in] pIn Pointer to Ref buffer
+ * @param[in] pOut Pointer to Test buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return maximum difference
+ */
+
+uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t *pOut, uint32_t numSamples)
+{
+ uint32_t i;
+ int32_t diff, diffCrnt = 0;
+ uint32_t maxDiff = 0;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ diff = pIn[i] - pOut[i];
+ diffCrnt = (diff > 0) ? diff : -diff;
+
+ if (diffCrnt > maxDiff)
+ {
+ maxDiff = diffCrnt;
+ }
+ }
+
+ return(maxDiff);
+}
+
+/**
+ * @brief Compare MATLAB Reference Output and ARM Test output
+ * @param[in] pIn Pointer to Ref buffer
+ * @param[in] pOut Pointer to Test buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return maximum difference
+ */
+
+uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples)
+{
+ uint32_t i;
+ int32_t diff, diffCrnt = 0;
+ uint32_t maxDiff = 0;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ diff = pIn[i] - pOut[i];
+ diffCrnt = (diff > 0) ? diff : -diff;
+
+ if (diffCrnt > maxDiff)
+ {
+ maxDiff = diffCrnt;
+ }
+ }
+
+ return(maxDiff);
+}
+
+/**
+ * @brief Provide guard bits for Input buffer
+ * @param[in,out] input_buf Pointer to input buffer
+ * @param[in] blockSize block Size
+ * @param[in] guard_bits guard bits
+ * @return none
+ * The function Provides the guard bits for the buffer
+ * to avoid overflow
+ */
+
+void arm_provide_guard_bits_q31 (q31_t * input_buf,
+ uint32_t blockSize,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < blockSize; i++)
+ {
+ input_buf[i] = input_buf[i] >> guard_bits;
+ }
+}
+
+/**
+ * @brief Provide guard bits for Input buffer
+ * @param[in,out] input_buf Pointer to input buffer
+ * @param[in] blockSize block Size
+ * @param[in] guard_bits guard bits
+ * @return none
+ * The function Provides the guard bits for the buffer
+ * to avoid overflow
+ */
+
+void arm_provide_guard_bits_q7 (q7_t * input_buf,
+ uint32_t blockSize,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < blockSize; i++)
+ {
+ input_buf[i] = input_buf[i] >> guard_bits;
+ }
+}
+
+
+
+/**
+ * @brief Caluclates number of guard bits
+ * @param[in] num_adds number of additions
+ * @return guard bits
+ * The function Caluclates the number of guard bits
+ * depending on the numtaps
+ */
+
+uint32_t arm_calc_guard_bits (uint32_t num_adds)
+{
+ uint32_t i = 1, j = 0;
+
+ if (num_adds == 1)
+ {
+ return (0);
+ }
+
+ while (i < num_adds)
+ {
+ i = i * 2;
+ j++;
+ }
+
+ return (j);
+}
+
+/**
+ * @brief Apply guard bits to buffer
+ * @param[in,out] pIn pointer to input buffer
+ * @param[in] numSamples number of samples in the input buffer
+ * @param[in] guard_bits guard bits
+ * @return none
+ */
+
+void arm_apply_guard_bits (float32_t *pIn,
+ uint32_t numSamples,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ pIn[i] = pIn[i] * arm_calc_2pow(guard_bits);
+ }
+}
+
+/**
+ * @brief Calculates pow(2, numShifts)
+ * @param[in] numShifts number of shifts
+ * @return pow(2, numShifts)
+ */
+uint32_t arm_calc_2pow(uint32_t numShifts)
+{
+
+ uint32_t i, val = 1;
+
+ for (i = 0; i < numShifts; i++)
+ {
+ val = val * 2;
+ }
+
+ return(val);
+}
+
+
+
+/**
+ * @brief Converts float to fixed q14
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to output buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 16384.0f corresponds to pow(2, 14) */
+ pOut[i] = (q15_t) (pIn[i] * 16384.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 2.0)
+ {
+ pOut[i] = 0x7FFF;
+ }
+
+ }
+
+}
+
+
+/**
+ * @brief Converts float to fixed q30 format
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to output buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q30 (float *pIn, q31_t * pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 1073741824.0f corresponds to pow(2, 30) */
+ pOut[i] = (q31_t) (pIn[i] * 1073741824.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 2.0)
+ {
+ pOut[i] = 0x7FFFFFFF;
+ }
+ }
+}
+
+/**
+ * @brief Converts float to fixed q30 format
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to output buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 1073741824.0f corresponds to pow(2, 30) */
+ pOut[i] = (q31_t) (pIn[i] * 536870912.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 4.0)
+ {
+ pOut[i] = 0x7FFFFFFF;
+ }
+ }
+}
+
+
+/**
+ * @brief Converts float to fixed q28 format
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to output buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 268435456.0f corresponds to pow(2, 28) */
+ pOut[i] = (q31_t) (pIn[i] * 268435456.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 8.0)
+ {
+ pOut[i] = 0x7FFFFFFF;
+ }
+ }
+}
+
+/**
+ * @brief Clip the float values to +/- 1
+ * @param[in,out] pIn input buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_clip_f32 (float *pIn, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ if (pIn[i] > 1.0f)
+ {
+ pIn[i] = 1.0;
+ }
+ else if ( pIn[i] < -1.0f)
+ {
+ pIn[i] = -1.0;
+ }
+
+ }
+}
+
+
+
+
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.h
new file mode 100644
index 0000000..5a18734
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.h
@@ -0,0 +1,63 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.0
+*
+* Project: CMSIS DSP Library
+*
+* Title: math_helper.h
+*
+* Description: Prototypes of all helper functions required.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+#ifndef MATH_HELPER_H
+#define MATH_HELPER_H
+
+float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize);
+void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples);
+void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits);
+void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits);
+void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples);
+void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_clip_f32(float *pIn, uint32_t numSamples);
+uint32_t arm_calc_guard_bits(uint32_t num_adds);
+void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits);
+uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples);
+uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples);
+uint32_t arm_calc_2pow(uint32_t guard_bits);
+#endif
+
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example_f32.c
new file mode 100644
index 0000000..5a05071
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example_f32.c
@@ -0,0 +1,178 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.0
+*
+* Project: CMSIS DSP Library
+* Title: arm_dotproduct_example_f32.c
+*
+* Description: Example code computing dot product of two vectors.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+ * @ingroup groupExamples
+ */
+
+/**
+ * @defgroup DotproductExample Dot Product Example
+ *
+ * \par Description:
+ * \par
+ * Demonstrates the use of the Multiply and Add functions to perform the dot product.
+ * The dot product of two vectors is obtained by multiplying corresponding elements
+ * and summing the products.
+
+ * \par Algorithm:
+ * \par
+ * The two input vectors \c A and \c B with length \c n, are multiplied element-by-element
+ * and then added to obtain dot product.
+ * \par
+ * This is denoted by the following equation:
+ * <pre> dotProduct = A[0] * B[0] + A[1] * B[1] + ... + A[n-1] * B[n-1]</pre>
+ *
+ * \par Block Diagram:
+ * \par
+ * \image html dotProduct.gif
+ *
+ * \par Variables Description:
+ * \par
+ * \li \c srcA_buf_f32 points to first input vector
+ * \li \c srcB_buf_f32 points to second input vector
+ * \li \c testOutput stores dot product of the two input vectors.
+ *
+ * \par CMSIS DSP Software Library Functions Used:
+ * \par
+ * - arm_mult_f32()
+ * - arm_add_f32()
+ *
+ * <b> Refer </b>
+ * \link arm_dotproduct_example_f32.c \endlink
+ *
+ */
+
+
+/** \example arm_dotproduct_example_f32.c
+ */
+
+#include <math.h>
+#include "arm_math.h"
+
+/* ----------------------------------------------------------------------
+* Defines each of the tests performed
+* ------------------------------------------------------------------- */
+#define MAX_BLOCKSIZE 32
+#define DELTA (0.000001f)
+
+/* ----------------------------------------------------------------------
+* Test input data for Floating point Dot Product example for 32-blockSize
+* Generated by the MATLAB randn() function
+* ------------------------------------------------------------------- */
+/* ----------------------------------------------------------------------
+** Test input data of srcA for blockSize 32
+** ------------------------------------------------------------------- */
+float32_t srcA_buf_f32[MAX_BLOCKSIZE] =
+{
+ -0.4325648115282207, -1.6655843782380970, 0.1253323064748307,
+ 0.2876764203585489, -1.1464713506814637, 1.1909154656429988,
+ 1.1891642016521031, -0.0376332765933176, 0.3272923614086541,
+ 0.1746391428209245, -0.1867085776814394, 0.7257905482933027,
+ -0.5883165430141887, 2.1831858181971011, -0.1363958830865957,
+ 0.1139313135208096, 1.0667682113591888, 0.0592814605236053,
+ -0.0956484054836690, -0.8323494636500225, 0.2944108163926404,
+ -1.3361818579378040, 0.7143245518189522, 1.6235620644462707,
+ -0.6917757017022868, 0.8579966728282626, 1.2540014216025324,
+ -1.5937295764474768, -1.4409644319010200, 0.5711476236581780,
+ -0.3998855777153632, 0.6899973754643451
+};
+
+/* ----------------------------------------------------------------------
+** Test input data of srcB for blockSize 32
+** ------------------------------------------------------------------- */
+float32_t srcB_buf_f32[MAX_BLOCKSIZE] =
+{
+ 1.7491401329284098, 0.1325982188803279, 0.3252281811989881,
+ -0.7938091410349637, 0.3149236145048914, -0.5272704888029532,
+ 0.9322666565031119, 1.1646643544607362, -2.0456694357357357,
+ -0.6443728590041911, 1.7410657940825480, 0.4867684246821860,
+ 1.0488288293660140, 1.4885752747099299, 1.2705014969484090,
+ -1.8561241921210170, 2.1343209047321410, 1.4358467535865909,
+ -0.9173023332875400, -1.1060770780029008, 0.8105708062681296,
+ 0.6985430696369063, -0.4015827425012831, 1.2687512030669628,
+ -0.7836083053674872, 0.2132664971465569, 0.7878984786088954,
+ 0.8966819356782295, -0.1869172943544062, 1.0131816724341454,
+ 0.2484350696132857, 0.0596083377937976
+};
+
+/* Reference dot product output */
+float32_t refDotProdOut = 5.9273644806352142;
+
+/* ----------------------------------------------------------------------
+* Declare Global variables
+* ------------------------------------------------------------------- */
+float32_t multOutput[MAX_BLOCKSIZE]; /* Intermediate output */
+float32_t testOutput; /* Final ouput */
+
+arm_status status; /* Status of the example */
+
+int32_t main(void)
+{
+ uint32_t i; /* Loop counter */
+ float32_t diff; /* Difference between reference and test outputs */
+
+ /* Multiplication of two input buffers */
+ arm_mult_f32(srcA_buf_f32, srcB_buf_f32, multOutput, MAX_BLOCKSIZE);
+
+ /* Accumulate the multiplication output values to
+ get the dot product of the two inputs */
+ for(i=0; i< MAX_BLOCKSIZE; i++)
+ {
+ arm_add_f32(&testOutput, &multOutput[i], &testOutput, 1);
+ }
+
+ /* absolute value of difference between ref and test */
+ diff = fabsf(refDotProdOut - testOutput);
+
+ /* Comparison of dot product value with reference */
+ if (diff > DELTA)
+ {
+ status = ARM_MATH_TEST_FAILURE;
+ }
+
+ if ( status == ARM_MATH_TEST_FAILURE)
+ {
+ while (1);
+ }
+
+ while (1); /* main function does not return */
+}
+
+ /** \endlink */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_data.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_data.c
new file mode 100644
index 0000000..10f3e12
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_data.c
@@ -0,0 +1,308 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.0
+*
+* Project: CMSIS DSP Library
+* Title: arm_fft_bin_data.c
+*
+* Description: Data file used for example code
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/* ----------------------------------------------------------------------
+Test Input signal contains 10KHz signal + Uniformly distributed white noise
+** ------------------------------------------------------------------- */
+
+float32_t testInput_f32_10khz[2048] =
+{
+-0.865129623056441, 0.000000000000000, -2.655020678073846, 0.000000000000000, 0.600664612949661, 0.000000000000000, 0.080378093886515, 0.000000000000000,
+-2.899160484012034, 0.000000000000000, 2.563004262857762, 0.000000000000000, 3.078328403304206, 0.000000000000000, 0.105906778385130, 0.000000000000000,
+0.048366940168201, 0.000000000000000, -0.145696461188734, 0.000000000000000, -0.023417155362879, 0.000000000000000, 2.127729174988954, 0.000000000000000,
+-1.176633086028377, 0.000000000000000, 3.690223557991855, 0.000000000000000, -0.622791766173194, 0.000000000000000, 0.722837373872203, 0.000000000000000,
+2.739754205367484, 0.000000000000000, -0.062610410524552, 0.000000000000000, -0.891296810967338, 0.000000000000000, -1.845872258871811, 0.000000000000000,
+1.195039415434387, 0.000000000000000, -2.177388969045026, 0.000000000000000, 1.078649103637905, 0.000000000000000, 2.570976050490193, 0.000000000000000,
+-1.383551403404574, 0.000000000000000, 2.392141424058873, 0.000000000000000, 2.858002843205065, 0.000000000000000, -3.682433899725536, 0.000000000000000,
+-3.488146646451150, 0.000000000000000, 1.323468578888120, 0.000000000000000, -0.099771155430726, 0.000000000000000, 1.561168082500454, 0.000000000000000,
+1.025026795103179, 0.000000000000000, 0.928841900171200, 0.000000000000000, 2.930499509864950, 0.000000000000000, 2.013349089766430, 0.000000000000000,
+2.381676148486737, 0.000000000000000, -3.081062307950236, 0.000000000000000, -0.389579115537544, 0.000000000000000, 0.181540149166620, 0.000000000000000,
+-2.601953341353208, 0.000000000000000, 0.333435137783218, 0.000000000000000, -2.812945856162965, 0.000000000000000, 2.649109640172910, 0.000000000000000,
+-1.003963025744654, 0.000000000000000, 1.552460768755035, 0.000000000000000, 0.088641345335247, 0.000000000000000, -2.519951327113426, 0.000000000000000,
+-4.341348988610527, 0.000000000000000, 0.557772429359965, 0.000000000000000, -1.671267412948494, 0.000000000000000, 0.733951350960387, 0.000000000000000,
+0.409263788034864, 0.000000000000000, 3.566033071952806, 0.000000000000000, 1.882565173848352, 0.000000000000000, -1.106017073793287, 0.000000000000000,
+0.154456720778718, 0.000000000000000, -2.513205795512153, 0.000000000000000, 0.310978660939421, 0.000000000000000, 0.579706500111723, 0.000000000000000,
+0.000086383683251, 0.000000000000000, -1.311866980897721, 0.000000000000000, 1.840007477574986, 0.000000000000000, -3.253005768451345, 0.000000000000000,
+1.462584328739432, 0.000000000000000, 1.610103610851738, 0.000000000000000, 0.761914676858907, 0.000000000000000, 0.974541361089834, 0.000000000000000,
+0.686845845885983, 0.000000000000000, 1.849153122025191, 0.000000000000000, 0.787800410401453, 0.000000000000000, -1.187438909666279, 0.000000000000000,
+-0.754937911044720, 0.000000000000000, 0.084373858395232, 0.000000000000000, -2.600269011710521, 0.000000000000000, -0.962982842142644, 0.000000000000000,
+-0.369328108540868, 0.000000000000000, 0.810791418361879, 0.000000000000000, 3.587016488699641, 0.000000000000000, -0.520776145083723, 0.000000000000000,
+0.640249919627884, 0.000000000000000, 1.103122489464969, 0.000000000000000, 2.231779881455556, 0.000000000000000, -1.308035392685241, 0.000000000000000,
+0.424070304330106, 0.000000000000000, -0.200383932651189, 0.000000000000000, -2.365526783356541, 0.000000000000000, -0.989114757436628, 0.000000000000000,
+2.770807688959777, 0.000000000000000, -0.444172737462307, 0.000000000000000, 0.079760979374078, 0.000000000000000, -0.005199118412183, 0.000000000000000,
+-0.664712668309527, 0.000000000000000, -0.624171857561896, 0.000000000000000, 0.537306979007338, 0.000000000000000, -2.575955675497642, 0.000000000000000,
+1.562363235756780, 0.000000000000000, 1.814069369848895, 0.000000000000000, -1.293428583392509, 0.000000000000000, -1.026188449495686, 0.000000000000000,
+-2.981771815588717, 0.000000000000000, -4.223468103075124, 0.000000000000000, 2.672674782004045, 0.000000000000000, -0.856096801117735, 0.000000000000000,
+0.048517345512563, 0.000000000000000, -0.026860721136222, 0.000000000000000, 0.392932277758187, 0.000000000000000, -1.331740855093099, 0.000000000000000,
+-1.894292129477081, 0.000000000000000, -1.425006468460681, 0.000000000000000, -2.721772427617057, 0.000000000000000, -1.616831100216806, 0.000000000000000,
+3.551177651488947, 0.000000000000000, -0.069685667896087, 0.000000000000000, -3.134634907409102, 0.000000000000000, -0.263627598944639, 0.000000000000000,
+-1.650469945991350, 0.000000000000000, -2.203580339374399, 0.000000000000000, -0.872203246123242, 0.000000000000000, 1.230782812607287, 0.000000000000000,
+0.257288860093291, 0.000000000000000, 1.989083106173137, 0.000000000000000, -1.985638729453261, 0.000000000000000, -1.416185105842892, 0.000000000000000,
+-1.131097688325772, 0.000000000000000, -2.245130805416057, 0.000000000000000, -1.938873996219074, 0.000000000000000, 2.043608361562645, 0.000000000000000,
+-0.583727989880841, 0.000000000000000, -1.785266378212929, 0.000000000000000, 1.961457586224753, 0.000000000000000, 1.139400099963223, 0.000000000000000,
+-1.979519343363991, 0.000000000000000, 2.003023322818429, 0.000000000000000, 0.229004069076829, 0.000000000000000, 3.452808862193135, 0.000000000000000,
+2.882273808365857, 0.000000000000000, -1.549450501844438, 0.000000000000000, -3.283872089931876, 0.000000000000000, -0.327025884099064, 0.000000000000000,
+-0.054979977136430, 0.000000000000000, -1.192280531479012, 0.000000000000000, 0.645539328365578, 0.000000000000000, 2.300832863404618, 0.000000000000000,
+-1.092951789535240, 0.000000000000000, -1.017368249363773, 0.000000000000000, -0.142673056169787, 0.000000000000000, 0.831073544881250, 0.000000000000000,
+-2.314612531587064, 0.000000000000000, -2.221456299106321, 0.000000000000000, 0.460261143885226, 0.000000000000000, 0.050585301888595, 0.000000000000000,
+0.364373329183988, 0.000000000000000, -1.685956552069538, 0.000000000000000, 0.050664512351055, 0.000000000000000, -0.193355783902718, 0.000000000000000,
+-0.158660446046828, 0.000000000000000, 2.394156453841953, 0.000000000000000, -1.562965718554525, 0.000000000000000, -2.199750600869900, 0.000000000000000,
+1.544984022381773, 0.000000000000000, -1.988307216807315, 0.000000000000000, -0.628240722541046, 0.000000000000000, -1.436235771505429, 0.000000000000000,
+1.677013691147313, 0.000000000000000, 1.600741781678228, 0.000000000000000, -0.757380959134706, 0.000000000000000, -4.784797439515566, 0.000000000000000,
+0.265121462834569, 0.000000000000000, 3.862029485934378, 0.000000000000000, 2.386823577249430, 0.000000000000000, -3.655779745436893, 0.000000000000000,
+-0.763541621368016, 0.000000000000000, -1.182140388432962, 0.000000000000000, -1.349106114858063, 0.000000000000000, -2.287533624396759, 0.000000000000000,
+-0.028603745188423, 0.000000000000000, -1.353580755934427, 0.000000000000000, 0.461602380352937, 0.000000000000000, -0.059599055078928, 0.000000000000000,
+-0.929946734342228, 0.000000000000000, 0.065773089295561, 0.000000000000000, 1.106565863102982, 0.000000000000000, 4.719295086373593, 0.000000000000000,
+-2.108377703544395, 0.000000000000000, -2.226393620240159, 0.000000000000000, 1.375668397437521, 0.000000000000000, -0.960772428525443, 0.000000000000000,
+-2.156313465390571, 0.000000000000000, 1.126060012375311, 0.000000000000000, 2.756485137030720, 0.000000000000000, 0.739639690862600, 0.000000000000000,
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+2.038151304801731, 0.000000000000000, 3.016122489841263, 0.000000000000000, -4.829481812137012, 0.000000000000000, -1.668436615909279, 0.000000000000000,
+0.958586784636918, 0.000000000000000, 1.550652410058678, 0.000000000000000, -1.456305257976716, 0.000000000000000, -0.079588392344731, 0.000000000000000,
+-2.453213599392345, 0.000000000000000, 0.296795909127105, 0.000000000000000, -0.253426616607643, 0.000000000000000, 1.418937160028195, 0.000000000000000,
+-1.672949529066915, 0.000000000000000, -1.620990298572947, 0.000000000000000, -1.085103073196045, 0.000000000000000, 0.738606361195386, 0.000000000000000,
+-2.097831202853255, 0.000000000000000, 2.711952282071310, 0.000000000000000, 1.498539238246888, 0.000000000000000, 1.317457282535915, 0.000000000000000,
+-0.302765938349717, 0.000000000000000, -0.044623707947201, 0.000000000000000, 2.337405215062395, 0.000000000000000, -3.980689173859100, 0.000000000000000,
+
+
+};
+
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_example_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_example_f32.c
new file mode 100644
index 0000000..91d15b5
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_example_f32.c
@@ -0,0 +1,158 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.0
+*
+* Project: CMSIS DSP Library
+* Title: arm_fft_bin_example_f32.c
+*
+* Description: Example code demonstrating calculation of Max energy bin of
+* frequency domain of input signal.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+ * @ingroup groupExamples
+ */
+
+/**
+ * @defgroup FrequencyBin Frequency Bin Example
+ *
+ * \par Description
+ * \par
+ * Demonstrates the calculation of the maximum energy bin in the frequency
+ * domain of the input signal with the use of Complex FFT, Complex
+ * Magnitude, and Maximum functions.
+ *
+ * \par Algorithm:
+ * \par
+ * The input test signal contains a 10 kHz signal with uniformly distributed white noise.
+ * Calculating the FFT of the input signal will give us the maximum energy of the
+ * bin corresponding to the input frequency of 10 kHz.
+ *
+ * \par Block Diagram:
+ * \image html FFTBin.gif "Block Diagram"
+ * \par
+ * The figure below shows the time domain signal of 10 kHz signal with
+ * uniformly distributed white noise, and the next figure shows the input
+ * in the frequency domain. The bin with maximum energy corresponds to 10 kHz signal.
+ * \par
+ * \image html FFTBinInput.gif "Input signal in Time domain"
+ * \image html FFTBinOutput.gif "Input signal in Frequency domain"
+ *
+ * \par Variables Description:
+ * \par
+ * \li \c testInput_f32_10khz points to the input data
+ * \li \c testOutput points to the output data
+ * \li \c fftSize length of FFT
+ * \li \c ifftFlag flag for the selection of CFFT/CIFFT
+ * \li \c doBitReverse Flag for selection of normal order or bit reversed order
+ * \li \c refIndex reference index value at which maximum energy of bin ocuurs
+ * \li \c testIndex calculated index value at which maximum energy of bin ocuurs
+ *
+ * \par CMSIS DSP Software Library Functions Used:
+ * \par
+ * - arm_cfft_f32()
+ * - arm_cmplx_mag_f32()
+ * - arm_max_f32()
+ *
+ * <b> Refer </b>
+ * \link arm_fft_bin_example_f32.c \endlink
+ *
+ */
+
+
+/** \example arm_fft_bin_example_f32.c
+ */
+
+
+#include "arm_math.h"
+#include "arm_const_structs.h"
+
+#define TEST_LENGTH_SAMPLES 2048
+
+/* -------------------------------------------------------------------
+* External Input and Output buffer Declarations for FFT Bin Example
+* ------------------------------------------------------------------- */
+extern float32_t testInput_f32_10khz[TEST_LENGTH_SAMPLES];
+static float32_t testOutput[TEST_LENGTH_SAMPLES/2];
+
+/* ------------------------------------------------------------------
+* Global variables for FFT Bin Example
+* ------------------------------------------------------------------- */
+uint32_t fftSize = 1024;
+uint32_t ifftFlag = 0;
+uint32_t doBitReverse = 1;
+
+/* Reference index at which max energy of bin ocuurs */
+uint32_t refIndex = 213, testIndex = 0;
+
+/* ----------------------------------------------------------------------
+* Max magnitude FFT Bin test
+* ------------------------------------------------------------------- */
+
+int32_t main(void)
+{
+
+ arm_status status;
+ float32_t maxValue;
+
+ status = ARM_MATH_SUCCESS;
+
+ /* Process the data through the CFFT/CIFFT module */
+ arm_cfft_f32(&arm_cfft_sR_f32_len1024, testInput_f32_10khz, ifftFlag, doBitReverse);
+
+ /* Process the data through the Complex Magnitude Module for
+ calculating the magnitude at each bin */
+ arm_cmplx_mag_f32(testInput_f32_10khz, testOutput, fftSize);
+
+ /* Calculates maxValue and returns corresponding BIN value */
+ arm_max_f32(testOutput, fftSize, &maxValue, &testIndex);
+
+ if (testIndex != refIndex)
+ {
+ status = ARM_MATH_TEST_FAILURE;
+ }
+
+ /* ----------------------------------------------------------------------
+ ** Loop here if the signals fail the PASS check.
+ ** This denotes a test failure
+ ** ------------------------------------------------------------------- */
+
+ if ( status != ARM_MATH_SUCCESS)
+ {
+ while (1);
+ }
+
+ while (1); /* main function does not return */
+}
+
+ /** \endlink */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_data.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_data.c
new file mode 100644
index 0000000..3a95fc5
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_data.c
@@ -0,0 +1,134 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.0
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_data.c
+*
+* Description: Data file used for example code
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/* ----------------------------------------------------------------------
+** Test input signal contains 1000Hz + 15000 Hz
+** ------------------------------------------------------------------- */
+
+float32_t testInput_f32_1kHz_15kHz[320] =
+{
++0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f,
++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f,
++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f,
+-0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f,
+-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f,
+-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f,
++0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f,
++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f,
++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f,
++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f,
+-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f,
+-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f,
++0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f,
++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f,
++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f,
++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f,
+-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f,
+-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f,
+-0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f,
++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f,
++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f,
+-0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f,
+-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f,
+-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f,
++0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f,
++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f,
++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f,
++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f,
+-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f,
+-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f,
+-0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f,
++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f,
++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f,
++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f,
+-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f,
+-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f,
+-0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f,
++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f,
++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f,
++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f,
+};
+
+float32_t refOutput[320] =
+{
++0.0000000000f, -0.0010797829f, -0.0007681386f, -0.0001982932f, +0.0000644313f, +0.0020854271f, +0.0036891871f, +0.0015855941f,
+-0.0026280805f, -0.0075907658f, -0.0119390538f, -0.0086665968f, +0.0088981202f, +0.0430539279f, +0.0974468742f, +0.1740405600f,
++0.2681416601f, +0.3747720089f, +0.4893362230f, +0.6024154672f, +0.7058740791f, +0.7968348987f, +0.8715901940f, +0.9277881093f,
++0.9682182661f, +0.9934674267f, +1.0012052245f, +0.9925859371f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f,
++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, -0.0000000000f, -0.1309866321f,
+-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f,
+-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f,
+-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f,
++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f,
++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f,
++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, -0.0000000000f, -0.1309866321f,
+-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f,
+-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f,
+-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f,
++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f,
++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f,
++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, -0.0000000000f, -0.1309866321f,
+-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f,
+-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f,
+-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f,
++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f,
++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f,
++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, +0.0000000000f, -0.1309866321f,
+-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f,
+-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f,
+-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f,
++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f,
++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f,
++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, +0.0000000000f, -0.1309866321f,
+-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f,
+-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f,
+-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, -0.0000000000f, +0.1309866321f,
++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f,
++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f,
++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, +0.0000000000f, -0.1309866321f,
+-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f,
+-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f,
+-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f,
++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f,
++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f
+};
+
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_example_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_example_f32.c
new file mode 100644
index 0000000..3dd9f5a
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_example_f32.c
@@ -0,0 +1,233 @@
+/* ----------------------------------------------------------------------
+ * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+ *
+* $Date: 17. January 2013
+* $Revision: V1.4.0
+*
+* Project: CMSIS DSP Library
+ * Title: arm_fir_example_f32.c
+ *
+ * Description: Example code demonstrating how an FIR filter can be used
+ * as a low pass filter.
+ *
+ * Target Processor: Cortex-M4/Cortex-M3
+ *
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+ * @ingroup groupExamples
+ */
+
+/**
+ * @defgroup FIRLPF FIR Lowpass Filter Example
+ *
+ * \par Description:
+ * \par
+ * Removes high frequency signal components from the input using an FIR lowpass filter.
+ * The example demonstrates how to configure an FIR filter and then pass data through
+ * it in a block-by-block fashion.
+ * \image html FIRLPF_signalflow.gif
+ *
+ * \par Algorithm:
+ * \par
+ * The input signal is a sum of two sine waves: 1 kHz and 15 kHz.
+ * This is processed by an FIR lowpass filter with cutoff frequency 6 kHz.
+ * The lowpass filter eliminates the 15 kHz signal leaving only the 1 kHz sine wave at the output.
+ * \par
+ * The lowpass filter was designed using MATLAB with a sample rate of 48 kHz and
+ * a length of 29 points.
+ * The MATLAB code to generate the filter coefficients is shown below:
+ * <pre>
+ * h = fir1(28, 6/24);
+ * </pre>
+ * The first argument is the "order" of the filter and is always one less than the desired length.
+ * The second argument is the normalized cutoff frequency. This is in the range 0 (DC) to 1.0 (Nyquist).
+ * A 6 kHz cutoff with a Nyquist frequency of 24 kHz lies at a normalized frequency of 6/24 = 0.25.
+ * The CMSIS FIR filter function requires the coefficients to be in time reversed order.
+ * <pre>
+ * fliplr(h)
+ * </pre>
+ * The resulting filter coefficients and are shown below.
+ * Note that the filter is symmetric (a property of linear phase FIR filters)
+ * and the point of symmetry is sample 14. Thus the filter will have a delay of
+ * 14 samples for all frequencies.
+ * \par
+ * \image html FIRLPF_coeffs.gif
+ * \par
+ * The frequency response of the filter is shown next.
+ * The passband gain of the filter is 1.0 and it reaches 0.5 at the cutoff frequency 6 kHz.
+ * \par
+ * \image html FIRLPF_response.gif
+ * \par
+ * The input signal is shown below.
+ * The left hand side shows the signal in the time domain while the right hand side is a frequency domain representation.
+ * The two sine wave components can be clearly seen.
+ * \par
+ * \image html FIRLPF_input.gif
+ * \par
+ * The output of the filter is shown below. The 15 kHz component has been eliminated.
+ * \par
+ * \image html FIRLPF_output.gif
+ *
+ * \par Variables Description:
+ * \par
+ * \li \c testInput_f32_1kHz_15kHz points to the input data
+ * \li \c refOutput points to the reference output data
+ * \li \c testOutput points to the test output data
+ * \li \c firStateF32 points to state buffer
+ * \li \c firCoeffs32 points to coefficient buffer
+ * \li \c blockSize number of samples processed at a time
+ * \li \c numBlocks number of frames
+ *
+ * \par CMSIS DSP Software Library Functions Used:
+ * \par
+ * - arm_fir_init_f32()
+ * - arm_fir_f32()
+ *
+ * <b> Refer </b>
+ * \link arm_fir_example_f32.c \endlink
+ *
+ */
+
+
+/** \example arm_fir_example_f32.c
+ */
+
+/* ----------------------------------------------------------------------
+** Include Files
+** ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "math_helper.h"
+
+/* ----------------------------------------------------------------------
+** Macro Defines
+** ------------------------------------------------------------------- */
+
+#define TEST_LENGTH_SAMPLES 320
+#define SNR_THRESHOLD_F32 140.0f
+#define BLOCK_SIZE 32
+#define NUM_TAPS 29
+
+/* -------------------------------------------------------------------
+ * The input signal and reference output (computed with MATLAB)
+ * are defined externally in arm_fir_lpf_data.c.
+ * ------------------------------------------------------------------- */
+
+extern float32_t testInput_f32_1kHz_15kHz[TEST_LENGTH_SAMPLES];
+extern float32_t refOutput[TEST_LENGTH_SAMPLES];
+
+/* -------------------------------------------------------------------
+ * Declare Test output buffer
+ * ------------------------------------------------------------------- */
+
+static float32_t testOutput[TEST_LENGTH_SAMPLES];
+
+/* -------------------------------------------------------------------
+ * Declare State buffer of size (numTaps + blockSize - 1)
+ * ------------------------------------------------------------------- */
+
+static float32_t firStateF32[BLOCK_SIZE + NUM_TAPS - 1];
+
+/* ----------------------------------------------------------------------
+** FIR Coefficients buffer generated using fir1() MATLAB function.
+** fir1(28, 6/24)
+** ------------------------------------------------------------------- */
+
+const float32_t firCoeffs32[NUM_TAPS] = {
+ -0.0018225230f, -0.0015879294f, +0.0000000000f, +0.0036977508f, +0.0080754303f, +0.0085302217f, -0.0000000000f, -0.0173976984f,
+ -0.0341458607f, -0.0333591565f, +0.0000000000f, +0.0676308395f, +0.1522061835f, +0.2229246956f, +0.2504960933f, +0.2229246956f,
+ +0.1522061835f, +0.0676308395f, +0.0000000000f, -0.0333591565f, -0.0341458607f, -0.0173976984f, -0.0000000000f, +0.0085302217f,
+ +0.0080754303f, +0.0036977508f, +0.0000000000f, -0.0015879294f, -0.0018225230f
+};
+
+/* ------------------------------------------------------------------
+ * Global variables for FIR LPF Example
+ * ------------------------------------------------------------------- */
+
+uint32_t blockSize = BLOCK_SIZE;
+uint32_t numBlocks = TEST_LENGTH_SAMPLES/BLOCK_SIZE;
+
+float32_t snr;
+
+/* ----------------------------------------------------------------------
+ * FIR LPF Example
+ * ------------------------------------------------------------------- */
+
+int32_t main(void)
+{
+ uint32_t i;
+ arm_fir_instance_f32 S;
+ arm_status status;
+ float32_t *inputF32, *outputF32;
+
+ /* Initialize input and output buffer pointers */
+ inputF32 = &testInput_f32_1kHz_15kHz[0];
+ outputF32 = &testOutput[0];
+
+ /* Call FIR init function to initialize the instance structure. */
+ arm_fir_init_f32(&S, NUM_TAPS, (float32_t *)&firCoeffs32[0], &firStateF32[0], blockSize);
+
+ /* ----------------------------------------------------------------------
+ ** Call the FIR process function for every blockSize samples
+ ** ------------------------------------------------------------------- */
+
+ for(i=0; i < numBlocks; i++)
+ {
+ arm_fir_f32(&S, inputF32 + (i * blockSize), outputF32 + (i * blockSize), blockSize);
+ }
+
+ /* ----------------------------------------------------------------------
+ ** Compare the generated output against the reference output computed
+ ** in MATLAB.
+ ** ------------------------------------------------------------------- */
+
+ snr = arm_snr_f32(&refOutput[0], &testOutput[0], TEST_LENGTH_SAMPLES);
+
+ if (snr < SNR_THRESHOLD_F32)
+ {
+ status = ARM_MATH_TEST_FAILURE;
+ }
+ else
+ {
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* ----------------------------------------------------------------------
+ ** Loop here if the signal does not match the reference output.
+ ** ------------------------------------------------------------------- */
+
+ if ( status != ARM_MATH_SUCCESS)
+ {
+ while (1);
+ }
+
+ while (1); /* main function does not return */
+}
+
+/** \endlink */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.c
new file mode 100644
index 0000000..f615e6f
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.c
@@ -0,0 +1,466 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.0 b
+*
+* Project: CMSIS DSP Library
+*
+* Title: math_helper.c
+*
+* Description: Definition of all helper functions required.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+/* ----------------------------------------------------------------------
+* Include standard header files
+* -------------------------------------------------------------------- */
+#include<math.h>
+
+/* ----------------------------------------------------------------------
+* Include project header files
+* -------------------------------------------------------------------- */
+#include "math_helper.h"
+
+/**
+ * @brief Caluclation of SNR
+ * @param[in] pRef Pointer to the reference buffer
+ * @param[in] pTest Pointer to the test buffer
+ * @param[in] buffSize total number of samples
+ * @return SNR
+ * The function Caluclates signal to noise ratio for the reference output
+ * and test output
+ */
+
+float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize)
+{
+ float EnergySignal = 0.0, EnergyError = 0.0;
+ uint32_t i;
+ float SNR;
+ int temp;
+ int *test;
+
+ for (i = 0; i < buffSize; i++)
+ {
+ /* Checking for a NAN value in pRef array */
+ test = (int *)(&pRef[i]);
+ temp = *test;
+
+ if (temp == 0x7FC00000)
+ {
+ return(0);
+ }
+
+ /* Checking for a NAN value in pTest array */
+ test = (int *)(&pTest[i]);
+ temp = *test;
+
+ if (temp == 0x7FC00000)
+ {
+ return(0);
+ }
+ EnergySignal += pRef[i] * pRef[i];
+ EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]);
+ }
+
+ /* Checking for a NAN value in EnergyError */
+ test = (int *)(&EnergyError);
+ temp = *test;
+
+ if (temp == 0x7FC00000)
+ {
+ return(0);
+ }
+
+
+ SNR = 10 * log10 (EnergySignal / EnergyError);
+
+ return (SNR);
+
+}
+
+
+/**
+ * @brief Provide guard bits for Input buffer
+ * @param[in,out] input_buf Pointer to input buffer
+ * @param[in] blockSize block Size
+ * @param[in] guard_bits guard bits
+ * @return none
+ * The function Provides the guard bits for the buffer
+ * to avoid overflow
+ */
+
+void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < blockSize; i++)
+ {
+ input_buf[i] = input_buf[i] >> guard_bits;
+ }
+}
+
+/**
+ * @brief Converts float to fixed in q12.20 format
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to outputbuffer
+ * @param[in] numSamples number of samples in the input buffer
+ * @return none
+ * The function converts floating point values to fixed point(q12.20) values
+ */
+
+void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 1048576.0f corresponds to pow(2, 20) */
+ pOut[i] = (q31_t) (pIn[i] * 1048576.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 1.0)
+ {
+ pOut[i] = 0x000FFFFF;
+ }
+ }
+}
+
+/**
+ * @brief Compare MATLAB Reference Output and ARM Test output
+ * @param[in] pIn Pointer to Ref buffer
+ * @param[in] pOut Pointer to Test buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return maximum difference
+ */
+
+uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t *pOut, uint32_t numSamples)
+{
+ uint32_t i;
+ int32_t diff, diffCrnt = 0;
+ uint32_t maxDiff = 0;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ diff = pIn[i] - pOut[i];
+ diffCrnt = (diff > 0) ? diff : -diff;
+
+ if (diffCrnt > maxDiff)
+ {
+ maxDiff = diffCrnt;
+ }
+ }
+
+ return(maxDiff);
+}
+
+/**
+ * @brief Compare MATLAB Reference Output and ARM Test output
+ * @param[in] pIn Pointer to Ref buffer
+ * @param[in] pOut Pointer to Test buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return maximum difference
+ */
+
+uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples)
+{
+ uint32_t i;
+ int32_t diff, diffCrnt = 0;
+ uint32_t maxDiff = 0;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ diff = pIn[i] - pOut[i];
+ diffCrnt = (diff > 0) ? diff : -diff;
+
+ if (diffCrnt > maxDiff)
+ {
+ maxDiff = diffCrnt;
+ }
+ }
+
+ return(maxDiff);
+}
+
+/**
+ * @brief Provide guard bits for Input buffer
+ * @param[in,out] input_buf Pointer to input buffer
+ * @param[in] blockSize block Size
+ * @param[in] guard_bits guard bits
+ * @return none
+ * The function Provides the guard bits for the buffer
+ * to avoid overflow
+ */
+
+void arm_provide_guard_bits_q31 (q31_t * input_buf,
+ uint32_t blockSize,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < blockSize; i++)
+ {
+ input_buf[i] = input_buf[i] >> guard_bits;
+ }
+}
+
+/**
+ * @brief Provide guard bits for Input buffer
+ * @param[in,out] input_buf Pointer to input buffer
+ * @param[in] blockSize block Size
+ * @param[in] guard_bits guard bits
+ * @return none
+ * The function Provides the guard bits for the buffer
+ * to avoid overflow
+ */
+
+void arm_provide_guard_bits_q7 (q7_t * input_buf,
+ uint32_t blockSize,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < blockSize; i++)
+ {
+ input_buf[i] = input_buf[i] >> guard_bits;
+ }
+}
+
+
+
+/**
+ * @brief Caluclates number of guard bits
+ * @param[in] num_adds number of additions
+ * @return guard bits
+ * The function Caluclates the number of guard bits
+ * depending on the numtaps
+ */
+
+uint32_t arm_calc_guard_bits (uint32_t num_adds)
+{
+ uint32_t i = 1, j = 0;
+
+ if (num_adds == 1)
+ {
+ return (0);
+ }
+
+ while (i < num_adds)
+ {
+ i = i * 2;
+ j++;
+ }
+
+ return (j);
+}
+
+/**
+ * @brief Apply guard bits to buffer
+ * @param[in,out] pIn pointer to input buffer
+ * @param[in] numSamples number of samples in the input buffer
+ * @param[in] guard_bits guard bits
+ * @return none
+ */
+
+void arm_apply_guard_bits (float32_t *pIn,
+ uint32_t numSamples,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ pIn[i] = pIn[i] * arm_calc_2pow(guard_bits);
+ }
+}
+
+/**
+ * @brief Calculates pow(2, numShifts)
+ * @param[in] numShifts number of shifts
+ * @return pow(2, numShifts)
+ */
+uint32_t arm_calc_2pow(uint32_t numShifts)
+{
+
+ uint32_t i, val = 1;
+
+ for (i = 0; i < numShifts; i++)
+ {
+ val = val * 2;
+ }
+
+ return(val);
+}
+
+
+
+/**
+ * @brief Converts float to fixed q14
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to output buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 16384.0f corresponds to pow(2, 14) */
+ pOut[i] = (q15_t) (pIn[i] * 16384.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 2.0)
+ {
+ pOut[i] = 0x7FFF;
+ }
+
+ }
+
+}
+
+
+/**
+ * @brief Converts float to fixed q30 format
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to output buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q30 (float *pIn, q31_t * pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 1073741824.0f corresponds to pow(2, 30) */
+ pOut[i] = (q31_t) (pIn[i] * 1073741824.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 2.0)
+ {
+ pOut[i] = 0x7FFFFFFF;
+ }
+ }
+}
+
+/**
+ * @brief Converts float to fixed q30 format
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to output buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 1073741824.0f corresponds to pow(2, 30) */
+ pOut[i] = (q31_t) (pIn[i] * 536870912.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 4.0)
+ {
+ pOut[i] = 0x7FFFFFFF;
+ }
+ }
+}
+
+
+/**
+ * @brief Converts float to fixed q28 format
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to output buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 268435456.0f corresponds to pow(2, 28) */
+ pOut[i] = (q31_t) (pIn[i] * 268435456.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 8.0)
+ {
+ pOut[i] = 0x7FFFFFFF;
+ }
+ }
+}
+
+/**
+ * @brief Clip the float values to +/- 1
+ * @param[in,out] pIn input buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_clip_f32 (float *pIn, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ if (pIn[i] > 1.0f)
+ {
+ pIn[i] = 1.0;
+ }
+ else if ( pIn[i] < -1.0f)
+ {
+ pIn[i] = -1.0;
+ }
+
+ }
+}
+
+
+
+
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.h
new file mode 100644
index 0000000..5a18734
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.h
@@ -0,0 +1,63 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.0
+*
+* Project: CMSIS DSP Library
+*
+* Title: math_helper.h
+*
+* Description: Prototypes of all helper functions required.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+#ifndef MATH_HELPER_H
+#define MATH_HELPER_H
+
+float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize);
+void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples);
+void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits);
+void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits);
+void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples);
+void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_clip_f32(float *pIn, uint32_t numSamples);
+uint32_t arm_calc_guard_bits(uint32_t num_adds);
+void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits);
+uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples);
+uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples);
+uint32_t arm_calc_2pow(uint32_t guard_bits);
+#endif
+
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_data.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_data.c
new file mode 100644
index 0000000..b6ab8c9
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_data.c
@@ -0,0 +1,134 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.0
+*
+* Project: CMSIS DSP Library
+* Title: arm_graphic_equalizer_data.c
+*
+* Description: Data file used for example code
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+float32_t testRefOutput_f32[320] = {
+
+0.000000000000000000, 0.001898396760225296, 0.004215449094772339, 0.007432077080011368, 0.010948467999696732, 0.015026375651359558, 0.019191544502973557, 0.023574527353048325,
+0.027919445186853409, 0.032277785241603851, 0.036551639437675476, 0.040732793509960175, 0.044799156486988068, 0.048710610717535019, 0.052476800978183746, 0.056059073656797409,
+0.059482168406248093, 0.062726479023694992, 0.065821025520563126, 0.068763464689254761, 0.071577839553356171, 0.074270240962505341, 0.076856281608343124, 0.079344697296619415,
+0.081745062023401260, 0.084067162126302719, 0.086318407207727432, 0.088509257882833481, 0.090647127479314804, 0.092742368578910828, 0.094802625477313995, 0.096837285906076431,
+0.098853722214698792, 0.100859899073839190, 0.102862443774938580, 0.104867763817310330, 0.106881409883499150, 0.108908228576183320, 0.110952425748109820, 0.113017357885837550,
+0.115105822682380680, 0.117219865322113040, 0.119361080229282380, 0.121530555188655850, 0.123729091137647630, 0.125957202166318890, 0.128215309232473370, 0.130503740161657330,
+0.132822841405868530, 0.135173004120588300, 0.137554679065942760, 0.139968376606702800, 0.142414685338735580, 0.144894234836101530, 0.147407654672861100, 0.149955596774816510,
+0.152538605034351350, 0.155157200992107390, 0.157811731100082400, 0.160502441227436070, 0.163229387253522870, 0.165992442518472670, 0.168791320174932480, 0.171625509858131410,
+0.174494370818138120, 0.177397061139345170, 0.180332608520984650, 0.183299910277128220, 0.186297744512557980, 0.189324837177991870, 0.192379791289567950, 0.195461250841617580,
+0.198567759245634080, 0.201697919517755510, 0.204850304871797560, 0.208023533225059510, 0.211216274648904800, 0.214427210390567780, 0.217655111104249950, 0.220898788422346120,
+0.224157124757766720, 0.227429077029228210, 0.230713658034801480, 0.234009962528944020, 0.237317133694887160, 0.240634419023990630, 0.243961080908775330, 0.247296508401632310,
+0.250640105456113820, 0.253991369158029560, 0.257349837571382520, 0.260715119540691380, 0.264086868613958360, 0.267464816570281980, 0.270848698914051060, 0.274238351732492450,
+0.277633611112833020, 0.281034380197525020, 0.284440591931343080, 0.287852220237255100, 0.291269283741712570, 0.294691801071166990, 0.298119872808456420, 0.301553562283515930,
+0.304993014782667160, 0.308438356965780260, 0.311889752745628360, 0.315347377210855480, 0.318811416625976560, 0.322282072156667710, 0.325759567320346830, 0.329244095832109450,
+0.332735907286405560, 0.336235217750072480, 0.339742250740528110, 0.343257248401641850, 0.346780419349670410, 0.350311983376741410, 0.353852160274982450, 0.357401121407747270,
+0.360959105193614960, 0.364526227116584780, 0.368102725595235820, 0.371688675135374070, 0.375284302979707720, 0.378889638930559160, 0.382504884153604510, 0.386130042374134060,
+0.389765247702598570, 0.393410529941320420, 0.397065933793783190, 0.400731507688760760, 0.404407206922769550, 0.408093083649873730, 0.411789052188396450, 0.415495119988918300,
+0.419211201369762420, 0.422937240451574330, 0.426673140376806260, 0.430418811738491060, 0.434174135327339170, 0.437938995659351350, 0.441713258624076840, 0.445496778935194020,
+0.449289388954639430, 0.453090950846672060, 0.456901267170906070, 0.460720170289278030, 0.464547459036111830, 0.468382950872182850, 0.472226426005363460, 0.476077698171138760,
+0.479936532676219940, 0.483802750706672670, 0.487676106393337250, 0.491556398570537570, 0.495443399995565410, 0.499336875975131990, 0.503236617892980580, 0.507142387330532070,
+0.511053957045078280, 0.514971107244491580, 0.518893606960773470, 0.522821225225925450, 0.526753749698400500, 0.530690938234329220, 0.534632585942745210, 0.538578454405069350,
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+0.574245333671569820, 0.578221492469310760, 0.582199502736330030, 0.586179181933403020, 0.590160276740789410, 0.594142623245716090, 0.598125983029603960, 0.602110169827938080,
+0.606094967573881150, 0.610080175101757050, 0.614065583795309070, 0.618050977587699890, 0.622036151587963100, 0.626020893454551700, 0.630004994571208950, 0.633988231420516970,
+0.637970402836799620, 0.641951277852058410, 0.645930647850036620, 0.649908289313316350, 0.653883971273899080, 0.657857488840818410, 0.661828581243753430, 0.665797054767608640,
+0.669762641191482540, 0.673725124448537830, 0.677684243768453600, 0.681639779359102250, 0.685591462999582290, 0.689539063721895220, 0.693482317030429840, 0.697420965880155560,
+0.701354760676622390, 0.705283410847187040, 0.709206689149141310, 0.713124278932809830, 0.717035952955484390, 0.720941375941038130, 0.724840316921472550, 0.728732451796531680,
+0.732617516070604320, 0.736495196819305420, 0.740365199744701390, 0.744227230548858640, 0.748080968856811520, 0.751926124095916750, 0.755762357264757160, 0.759589381515979770,
+0.763406842947006230, 0.767214450985193250, 0.771011855453252790, 0.774798732250928880, 0.778574761003255840, 0.782339565455913540, 0.786092851310968400, 0.789834223687648770,
+0.793563373386859890, 0.797279909253120420, 0.800983514636754990, 0.804673787206411360, 0.808350402861833570, 0.812012966722249980, 0.815661124885082240, 0.819294504821300510,
+0.822912722826004030, 0.826515413820743560, 0.830102190375328060, 0.833672653883695600, 0.837226435542106630, 0.840763118118047710, 0.844282336533069610, 0.847783654928207400,
+0.851266715675592420, 0.854731071740388870, 0.858176350593566890, 0.861602116376161580, 0.865007970482110980, 0.868393491953611370, 0.871758259832859040, 0.875101849436759950,
+0.878423850983381270, 0.881723806262016300, 0.885001312941312790, 0.888255912810564040, 0.891487173736095430, 0.894694659858942030, 0.897877920418977740, 0.901036512106657030,
+0.904169965535402300, 0.907277844846248630, 0.910359673202037810, 0.913415014743804930, 0.916443370282649990, 0.919444311410188670, 0.922417331486940380, 0.925361987203359600,
+0.928277771919965740, 0.931164238601922990, 0.934020876884460450, 0.936847217381000520, 0.939642757177352910, 0.942407000809907910, 0.945139460265636440, 0.947839632630348210,
+0.950507018715143200, 0.953141096979379650, 0.955741371959447860, 0.958307322114706040, 0.960838429629802700, 0.963334184139966960, 0.965794049203395840, 0.968217510730028150,
+0.970604017376899720, 0.972953058779239650, 0.975264083594083790, 0.977536566555500030, 0.979769956320524220, 0.981963708996772770, 0.984117280691862110, 0.986230112612247470,
+0.988301653414964680, 0.990331344306468960, 0.992318630218505860, 0.994262944906950000, 0.996163722127676010, 0.998020399361848830, 0.999832402914762500, 1.001599155366420700,
+1.003320086747407900, 1.004994612187147100, 1.006622135639190700, 1.008202098309993700, 1.009733878076076500, 1.011216927319765100, 1.012650609016418500, 1.014034371823072400,
+1.015367589890956900, 1.016649682074785200, 1.017880033701658200, 1.019058048725128200, 1.020183108747005500, 1.021254621446132700, 1.022271949797868700, 1.023234523832798000,
+
+};
+/* ----------------------------------------------------------------------
+** Test input - logarithmic chirp signal
+** ------------------------------------------------------------------- */
+
+float32_t testInput_f32[320] =
+ {
+ 0.000000000000000061, 0.002622410992047861, 0.005253663973466970, 0.007893770384930297, 0.010542741395035495, 0.013200587895525877, 0.015867320496454066, 0.018542949521290073,
+0.021227485001971542, 0.023920936673895138, 0.026623313970853074, 0.029334626019908643, 0.032054881636210709, 0.034784089317753723, 0.037522257240071598, 0.040269393250875855,
+0.043025504864628375, 0.045790599257054837, 0.048564683259595690, 0.051347763353792118, 0.054139845665610427, 0.056940935959702531, 0.059751039633601337, 0.062570161711849828,
+0.065398306840066575, 0.068235479278943648, 0.071081682898178900, 0.073936921170339814, 0.076801197164660218, 0.079674513540768196, 0.082556872542344922, 0.085448275990715375,
+0.088348725278367082, 0.091258221362398390, 0.094176764757897533, 0.097104355531246703, 0.100040993293358240, 0.102986677192832010, 0.105941405909045980, 0.108905177645166230,
+0.111877990121087980, 0.114859840566297130, 0.117850725712659680, 0.120850641787131110, 0.123859584504392860, 0.126877549059407400, 0.129904530119898690, 0.132940521818751430,
+0.135985517746334080, 0.139039510942737950, 0.142102493889940090, 0.145174458503884160, 0.148255396126476810, 0.151345297517508140, 0.154444152846483080, 0.157551951684374300,
+0.160668682995289720, 0.163794335128054890, 0.166928895807713030, 0.170072352126936720, 0.173224690537355760, 0.176385896840798810, 0.179555956180445340, 0.182734853031894270,
+0.185922571194139130, 0.189119093780459800, 0.192324403209221870, 0.195538481194587030, 0.198761308737133020, 0.201992866114384050, 0.205233132871247170, 0.208482087810360570,
+0.211739708982344370, 0.215005973675965020, 0.218280858408200220, 0.221564338914212730, 0.224856390137231970, 0.228156986218334190, 0.231466100486134670, 0.234783705446379690,
+0.238109772771442410, 0.241444273289723230, 0.244787176974952890, 0.248138452935395580, 0.251498069402956710, 0.254865993722190930, 0.258242192339209860, 0.261626630790492030,
+0.265019273691591620, 0.268420084725748410, 0.271829026632395280, 0.275246061195565440, 0.278671149232197430, 0.282104250580339830, 0.285545324087251580, 0.288994327597401960,
+0.292451217940364990, 0.295915950918612280, 0.299388481295203350, 0.302868762781368150, 0.306356748023990040, 0.309852388592980640, 0.313355634968552230, 0.316866436528383590,
+0.320384741534681720, 0.323910497121136620, 0.327443649279772870, 0.330984142847692230, 0.334531921493712690, 0.338086927704900790, 0.341649102772995210, 0.345218386780727190,
+0.348794718588032520, 0.352378035818156910, 0.355968274843654950, 0.359565370772282730, 0.363169257432780890, 0.366779867360555120, 0.370397131783246010, 0.374020980606193880,
+0.377651342397795690, 0.381288144374756830, 0.384931312387234990, 0.388580770903877330, 0.392236442996751310, 0.395898250326170650, 0.399566113125414350, 0.403239950185338420,
+0.406919678838884410, 0.410605214945482130, 0.414296472875345100, 0.417993365493664670, 0.421695804144698540, 0.425403698635752780, 0.429116957221065130, 0.432835486585582130,
+0.436559191828633180, 0.440287976447505720, 0.444021742320914510, 0.447760389692375140, 0.451503817153472210, 0.455251921627031540, 0.459004598350192470, 0.462761740857380200,
+0.466523240963184150, 0.470288988745136360, 0.474058872526396560, 0.477832778858340690, 0.481610592503056990, 0.485392196415748600, 0.489177471727042850, 0.492966297725213780,
+0.496758551838309250, 0.500554109616195060, 0.504352844712508190, 0.508154628866524960, 0.511959331884944910, 0.515766821623591440, 0.519576963969030530, 0.523389622820107150,
+0.527204660069405030, 0.531021935584629400, 0.534841307189911630, 0.538662630647041900, 0.542485759636628150, 0.546310545739186690, 0.550136838416161340, 0.553964484990880020,
+0.557793330629441700, 0.561623218321546380, 0.565453988861259300, 0.569285480827721570, 0.573117530565801950, 0.576949972166696630, 0.580782637448476910, 0.584615355936589420,
+0.588447954844309340, 0.592280259053150400, 0.596112091093235260, 0.599943271123626440, 0.603773616912622660, 0.607602943818024150, 0.611431064767369080, 0.615257790238142090,
+0.619082928237961740, 0.622906284284749700, 0.626727661386881850, 0.630546860023327600, 0.634363678123782030, 0.638177911048790960, 0.641989351569874020, 0.645797789849653410,
+0.649603013421986450, 0.653404807172108140, 0.657202953316791350, 0.660997231384523490, 0.664787418195706640, 0.668573287842887610, 0.672354611671016960, 0.676131158257749170,
+0.679902693393781730, 0.683668980063242500, 0.687429778424128110, 0.691184845788802130, 0.694933936604551380, 0.698676802434213370, 0.702413191936877570, 0.706142850848662460,
+0.709865521963579990, 0.713580945114492330, 0.717288857154159800, 0.720988991936399870, 0.724681080297347790, 0.728364850036839040, 0.732040025899910680, 0.735706329558433620,
+0.739363479592880620, 0.743011191474238440, 0.746649177546067850, 0.750277147006723990, 0.753894805891742180, 0.757501857056394940, 0.761098000158428880, 0.764682931640995540,
+0.768256344715771980, 0.771817929346292900, 0.775367372231492210, 0.778904356789468790, 0.782428563141483460, 0.785939668096195860, 0.789437345134148760, 0.792921264392515420,
+0.796391092650110770, 0.799846493312681210, 0.803287126398485760, 0.806712648524170680, 0.810122712890953390, 0.813516969271127150, 0.816895063994893090, 0.820256639937531280,
+0.823601336506926020, 0.826928789631450890, 0.830238631748229430, 0.833530491791779850, 0.836803995183058700, 0.840058763818912760, 0.843294416061954100, 0.846510566730867220,
+0.849706827091166740, 0.852882804846411770, 0.856038104129895340, 0.859172325496819990, 0.862285065916973510, 0.865375918767918860, 0.868444473828712590, 0.871490317274166260,
+0.874513031669661770, 0.877512195966544280, 0.880487385498096800, 0.883438171976119850, 0.886364123488128100, 0.889264804495180530, 0.892139775830360640, 0.894988594697921020,
+0.897810814673113080, 0.900605985702712770, 0.903373654106265470, 0.906113362578062300, 0.908824650189867690, 0.911507052394417540, 0.914160101029702910, 0.916783324324059180,
+0.919376246902079860, 0.921938389791372770, 0.924469270430179120, 0.926968402675872660, 0.929435296814361430, 0.931869459570409790, 0.934270394118903560, 0.936637600097074200,
+0.938970573617708970, 0.941268807283364040, 0.943531790201601380, 0.945759008001275100, 0.947949942849885320, 0.950104073472023970, 0.952220875168933280, 0.954299819839202090,
+0.956340376000621160, 0.958342008813221960, 0.960304180103520260, 0.962226348389994210, 0.964107968909812760, 0.965948493646846980, 0.967747371360983650, 0.969504047618768740,
+0.971217964825405680, 0.972888562258134030, 0.974515276101013520, 0.976097539481141750, 0.977634782506330400, 0.979126432304266880, 0.980571913063189360, 0.981970646074102120,
+0.983322049774557390, 0.984625539794035220, 0.985880529000944810, 0.987086427551279730, 0.988242642938953360, 0.989348580047844540, 0.990403641205582440, 0.991407226239099710,
+0.992358732531984260, 0.993257555083659870, 0.994103086570423680, 0.994894717408374870, 0.995631835818261310, 0.996313827892278070, 0.996940077662846650, 0.997509967173408010,
+
+ };
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_example_q31.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_example_q31.c
new file mode 100644
index 0000000..c263d18
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_example_q31.c
@@ -0,0 +1,411 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.0
+*
+* Project: CMSIS DSP Library
+* Title: arm_graphic_equalizer_example_q31.c
+*
+* Description: Example showing an audio graphic equalizer constructed
+* out of Biquad filters.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+ * @ingroup groupExamples
+ */
+
+/**
+ * @defgroup GEQ5Band Graphic Audio Equalizer Example
+ *
+ * \par Description:
+ * \par
+ * This example demonstrates how a 5-band graphic equalizer can be constructed
+ * using the Biquad cascade functions.
+ * A graphic equalizer is used in audio applications to vary the tonal quality
+ * of the audio.
+ *
+ * \par Block Diagram:
+ * \par
+ * The design is based on a cascade of 5 filter sections.
+ * \image html GEQ_signalflow.gif
+ * Each filter section is 4th order and consists of a cascade of two Biquads.
+ * Each filter has a nominal gain of 0 dB (1.0 in linear units) and
+ * boosts or cuts signals within a specific frequency range.
+ * The edge frequencies between the 5 bands are 100, 500, 2000, and 6000 Hz.
+ * Each band has an adjustable boost or cut in the range of +/- 9 dB.
+ * For example, the band that extends from 500 to 2000 Hz has the response shown below:
+ * \par
+ * \image html GEQ_bandresponse.gif
+ * \par
+ * With 1 dB steps, each filter has a total of 19 different settings.
+ * The filter coefficients for all possible 19 settings were precomputed
+ * in MATLAB and stored in a table. With 5 different tables, there are
+ * a total of 5 x 19 = 95 different 4th order filters.
+ * All 95 responses are shown below:
+ * \par
+ * \image html GEQ_allbandresponse.gif
+ * \par
+ * Each 4th order filter has 10 coefficents for a grand total of 950 different filter
+ * coefficients that must be tabulated. The input and output data is in Q31 format.
+ * For better noise performance, the two low frequency bands are implemented using the high
+ * precision 32x64-bit Biquad filters. The remaining 3 high frequency bands use standard
+ * 32x32-bit Biquad filters. The input signal used in the example is a logarithmic chirp.
+ * \par
+ * \image html GEQ_inputchirp.gif
+ * \par
+ * The array <code>bandGains</code> specifies the gain in dB to apply in each band.
+ * For example, if <code>bandGains={0, -3, 6, 4, -6};</code> then the output signal will be:
+ * \par
+ * \image html GEQ_outputchirp.gif
+ * \par
+ * \note The output chirp signal follows the gain or boost of each band.
+ * \par
+ *
+ * \par Variables Description:
+ * \par
+ * \li \c testInput_f32 points to the input data
+ * \li \c testRefOutput_f32 points to the reference output data
+ * \li \c testOutput points to the test output data
+ * \li \c inputQ31 temporary input buffer
+ * \li \c outputQ31 temporary output buffer
+ * \li \c biquadStateBand1Q31 points to state buffer for band1
+ * \li \c biquadStateBand2Q31 points to state buffer for band2
+ * \li \c biquadStateBand3Q31 points to state buffer for band3
+ * \li \c biquadStateBand4Q31 points to state buffer for band4
+ * \li \c biquadStateBand5Q31 points to state buffer for band5
+ * \li \c coeffTable points to coefficient buffer for all bands
+ * \li \c gainDB gain buffer which has gains applied for all the bands
+ *
+ * \par CMSIS DSP Software Library Functions Used:
+ * \par
+ * - arm_biquad_cas_df1_32x64_init_q31()
+ * - arm_biquad_cas_df1_32x64_q31()
+ * - arm_biquad_cascade_df1_init_q31()
+ * - arm_biquad_cascade_df1_q31()
+ * - arm_scale_q31()
+ * - arm_scale_f32()
+ * - arm_float_to_q31()
+ * - arm_q31_to_float()
+ *
+ * <b> Refer </b>
+ * \link arm_graphic_equalizer_example_q31.c \endlink
+ *
+ */
+
+
+/** \example arm_graphic_equalizer_example_q31.c
+ */
+
+
+#include "arm_math.h"
+#include "math_helper.h"
+
+/* Length of the overall data in the test */
+#define TESTLENGTH 320
+
+/* Block size for the underlying processing */
+#define BLOCKSIZE 32
+
+/* Total number of blocks to run */
+#define NUMBLOCKS (TESTLENGTH/BLOCKSIZE)
+
+/* Number of 2nd order Biquad stages per filter */
+#define NUMSTAGES 2
+
+#define SNR_THRESHOLD_F32 98
+
+/* -------------------------------------------------------------------
+ * External Declarations for Input and Output buffers
+ * ------------------------------------------------------------------- */
+
+extern float32_t testInput_f32[TESTLENGTH];
+static float32_t testOutput[TESTLENGTH];
+
+extern float32_t testRefOutput_f32[TESTLENGTH];
+
+/* ----------------------------------------------------------------------
+** Q31 state buffers for Band1, Band2, Band3, Band4, Band5
+** ------------------------------------------------------------------- */
+
+static q63_t biquadStateBand1Q31[4 * 2];
+static q63_t biquadStateBand2Q31[4 * 2];
+static q31_t biquadStateBand3Q31[4 * 2];
+static q31_t biquadStateBand4Q31[4 * 2];
+static q31_t biquadStateBand5Q31[4 * 2];
+
+/* ----------------------------------------------------------------------
+** Q31 input and output buffers
+** ------------------------------------------------------------------- */
+
+q31_t inputQ31[BLOCKSIZE];
+q31_t outputQ31[BLOCKSIZE];
+
+/* ----------------------------------------------------------------------
+** Entire coefficient table. There are 10 coefficients per 4th order Biquad
+** cascade filter. The first 10 coefficients correspond to the -9 dB gain
+** setting of band 1; the next 10 coefficient correspond to the -8 dB gain
+** setting of band 1; and so on. There are 10*19=190 coefficients in total
+** for band 1 (gains = -9, -8, -7, ..., 9). After this come the 190 coefficients
+** for band 2.
+**
+** The coefficients are in Q29 format and require a postShift of 2.
+** ------------------------------------------------------------------- */
+
+const q31_t coeffTable[950] = {
+
+ /* Band 1, -9 dB gain */
+ 535576962, -1071153923, 535576962, 1073741824, -536870912, 535576962, -1063501998, 527979313, 1060865294, -524146981,
+ /* Band 1, -8 dB gain */
+ 535723226, -1071446451, 535723226, 1073741824, -536870912, 535723226, -1063568947, 527903217, 1061230578, -524503778,
+ 535868593, -1071737186, 535868593, 1073741824, -536870912, 535868593, -1063627467, 527819780, 1061585502, -524850686,
+ 536013181, -1072026363, 536013181, 1073741824, -536870912, 536013181, -1063677598, 527728935, 1061930361, -525187972,
+ 536157109, -1072314217, 536157109, 1073741824, -536870912, 536157109, -1063719372, 527630607, 1062265438, -525515897,
+ 536300492, -1072600983, 536300492, 1073741824, -536870912, 536300492, -1063752815, 527524720, 1062591011, -525834716,
+ 536443447, -1072886894, 536443447, 1073741824, -536870912, 536443447, -1063777945, 527411186, 1062907350, -526144676,
+ 536586091, -1073172183, 536586091, 1073741824, -536870912, 536586091, -1063794775, 527289917, 1063214717, -526446017,
+ 536728541, -1073457082, 536728541, 1073741824, -536870912, 536728541, -1063803308, 527160815, 1063513366, -526738975,
+ 536870912, -1073741824, 536870912, 1073741824, -536870912, 536870912, -1063803543, 527023777, 1063803543, -527023777,
+ 537013321, -1074026642, 537013321, 1073741824, -536870912, 537013321, -1063795470, 526878696, 1064085490, -527300648,
+ 537155884, -1074311768, 537155884, 1073741824, -536870912, 537155884, -1063779073, 526725455, 1064359439, -527569803,
+ 537298718, -1074597435, 537298718, 1073741824, -536870912, 537298718, -1063754328, 526563934, 1064625617, -527831454,
+ 537441939, -1074883878, 537441939, 1073741824, -536870912, 537441939, -1063721205, 526394005, 1064884245, -528085806,
+ 537585666, -1075171331, 537585666, 1073741824, -536870912, 537585666, -1063679666, 526215534, 1065135536, -528333059,
+ 537730015, -1075460030, 537730015, 1073741824, -536870912, 537730015, -1063629666, 526028380, 1065379699, -528573409,
+ 537875106, -1075750212, 537875106, 1073741824, -536870912, 537875106, -1063571152, 525832396, 1065616936, -528807045,
+ 538021057, -1076042114, 538021057, 1073741824, -536870912, 538021057, -1063504065, 525627429, 1065847444, -529034151,
+ 538167989, -1076335977, 538167989, 1073741824, -536870912, 538167989, -1063428338, 525413317, 1066071412, -529254907,
+
+ /* Band 2, -9 dB gain */
+ 531784976, -1055497692, 523873415, 1066213307, -529420241, 531784976, -1040357886, 509828014, 1028908252, -494627367,
+ /* Band 2, -8 dB gain */
+ 532357636, -1056601982, 524400080, 1066115844, -529326645, 532357636, -1040623406, 509562600, 1030462237, -496062122,
+ 532927392, -1057707729, 524931110, 1066024274, -529239070, 532927392, -1040848253, 509262081, 1031969246, -497457090,
+ 533494678, -1058816094, 525467240, 1065939047, -529157961, 533494678, -1041032161, 508925950, 1033429976, -498812573,
+ 534059929, -1059928204, 526009170, 1065860582, -529083734, 534059929, -1041174868, 508553717, 1034845124, -500128887,
+ 534623580, -1061045148, 526557561, 1065789260, -529016764, 534623580, -1041276126, 508144920, 1036215393, -501406373,
+ 535186068, -1062167969, 527113032, 1065725420, -528957385, 535186068, -1041335703, 507699125, 1037541500, -502645399,
+ 535747827, -1063297666, 527676151, 1065669351, -528905879, 535747827, -1041353386, 507215934, 1038824183, -503846368,
+ 536309295, -1064435183, 528247436, 1065621289, -528862476, 536309295, -1041328990, 506694984, 1040064203, -505009724,
+ 536870912, -1065581413, 528827349, 1065581413, -528827349, 536870912, -1041262354, 506135953, 1041262354, -506135953,
+ 537433117, -1066737194, 529416295, 1065549847, -528800610, 537433117, -1041153346, 505538564, 1042419457, -507225588,
+ 537996352, -1067903307, 530014622, 1065526651, -528782316, 537996352, -1041001864, 504902578, 1043536370, -508279208,
+ 538561061, -1069080480, 530622620, 1065511830, -528772462, 538561061, -1040807833, 504227800, 1044613981, -509297437,
+ 539127690, -1070269387, 531240527, 1065505333, -528770987, 539127690, -1040571205, 503514074, 1045653211, -510280946,
+ 539696690, -1071470656, 531868525, 1065507054, -528777778, 539696690, -1040291951, 502761277, 1046655011, -511230450,
+ 540268512, -1072684867, 532506750, 1065516837, -528792672, 540268512, -1039970063, 501969320, 1047620358, -512146700,
+ 540843613, -1073912567, 533155297, 1065534483, -528815459, 540843613, -1039605542, 501138139, 1048550251, -513030484,
+ 541422451, -1075154268, 533814224, 1065559750, -528845892, 541422451, -1039198394, 500267687, 1049445708, -513882621,
+ 542005489, -1076410460, 534483561, 1065592362, -528883686, 542005489, -1038748624, 499357932, 1050307760, -514703956,
+ 518903861, -1001986830, 486725277, 1037235801, -502367695, 518903861, -945834422, 446371043, 902366163, -400700571,
+ 520899989, -1005630916, 488289126, 1036926846, -502147311, 520899989, -946490935, 445581846, 907921945, -404936158,
+ 522893209, -1009290002, 489869792, 1036650484, -501961419, 522893209, -947006359, 444685310, 913306106, -409075225,
+ 524884763, -1012968199, 491470256, 1036407567, -501810737, 524884763, -947377809, 443679533, 918521018, -413116221,
+ 526875910, -1016669649, 493093518, 1036198712, -501695739, 526875910, -947602324, 442562672, 923569247, -417057897,
+ 528867927, -1020398503, 494742575, 1036024293, -501616651, 528867927, -947676875, 441332970, 928453558, -420899319,
+ 530862111, -1024158905, 496420407, 1035884447, -501573457, 530862111, -947598385, 439988777, 933176909, -424639872,
+ 532859778, -1027954970, 498129955, 1035779077, -501565907, 532859778, -947363742, 438528571, 937742446, -428279254,
+ 534862260, -1031790763, 499874098, 1035707863, -501593525, 534862260, -946969823, 436950987, 942153486, -431817474,
+ 536870912, -1035670279, 501655630, 1035670279, -501655630, 536870912, -946413508, 435254839, 946413508, -435254839,
+ 538887107, -1039597419, 503477238, 1035665609, -501751354, 538887107, -945691703, 433439146, 950526127, -438591937,
+ 540912240, -1043575967, 505341475, 1035692963, -501879659, 540912240, -944801359, 431503152, 954495080, -441829621,
+ 542947726, -1047609569, 507250741, 1035751307, -502039364, 542947726, -943739490, 429446349, 958324201, -444968987,
+ 544995000, -1051701717, 509207261, 1035839473, -502229165, 544995000, -942503190, 427268492, 962017400, -448011351,
+ 547055523, -1055855728, 511213065, 1035956193, -502447657, 547055523, -941089647, 424969617, 965578640, -450958226,
+ 549130774, -1060074734, 513269973, 1036100110, -502693359, 549130774, -939496155, 422550049, 969011913, -453811298,
+ 551222259, -1064361672, 515379585, 1036269804, -502964731, 551222259, -937720119, 420010407, 972321228, -456572401,
+ 553331507, -1068719280, 517543273, 1036463810, -503260192, 553331507, -935759057, 417351601, 975510582, -459243495,
+ 555460072, -1073150100, 519762181, 1036680633, -503578144, 555460072, -933610600, 414574832, 978583948, -461826644,
+ 494084017, -851422604, 404056273, 930151631, -423619864, 494084017, -673714108, 339502486, 561843007, -265801750,
+ 498713542, -859177141, 406587077, 929211656, -423786402, 498713542, -673274906, 338185129, 573719128, -272222942,
+ 503369016, -867012190, 409148384, 928362985, -424054784, 503369016, -672533059, 336693984, 585290277, -278599028,
+ 508052536, -874935599, 411746438, 927604291, -424422151, 508052536, -671478538, 335026905, 596558312, -284920289,
+ 512766286, -882955583, 414387826, 926933782, -424885216, 512766286, -670100998, 333182045, 607525792, -291177811,
+ 517512534, -891080712, 417079474, 926349262, -425440318, 517512534, -668389789, 331157902, 618195914, -297363485,
+ 522293635, -899319903, 419828635, 925848177, -426083491, 522293635, -666333963, 328953368, 628572440, -303470012,
+ 527112032, -907682405, 422642886, 925427679, -426810526, 527112032, -663922286, 326567785, 638659631, -309490882,
+ 531970251, -916177781, 425530105, 925084675, -427617023, 531970251, -661143261, 324000998, 648462180, -315420352,
+ 536870912, -924815881, 428498454, 924815881, -428498454, 536870912, -657985147, 321253420, 657985147, -321253420,
+ 541816719, -933606817, 431556352, 924617870, -429450209, 541816719, -654435997, 318326093, 667233900, -326985786,
+ 546810467, -942560921, 434712438, 924487114, -430467639, 546810467, -650483688, 315220754, 676214053, -332613816,
+ 551855042, -951688708, 437975532, 924420027, -431546101, 551855042, -646115970, 311939896, 684931422, -338134495,
+ 556953421, -961000826, 441354588, 924413001, -432680993, 556953421, -641320513, 308486839, 693391970, -343545389,
+ 562108672, -970508005, 444858642, 924462435, -433867780, 562108672, -636084967, 304865786, 701601770, -348844597,
+ 567323959, -980220994, 448496743, 924564764, -435102022, 567323959, -630397020, 301081886, 709566963, -354030710,
+ 572602539, -990150500, 452277894, 924716482, -436379394, 572602539, -624244471, 297141281, 717293726, -359102767,
+ 577947763, -1000307125, 456210977, 924914158, -437695705, 577947763, -617615296, 293051155, 724788245, -364060214,
+ 583363084, -1010701292, 460304674, 925154455, -439046908, 583363084, -610497723, 288819761, 732056685, -368902865,
+ 387379495, -506912469, 196933274, 840112184, -347208270, 387379495, 506912469, 196933274, -840112184, -347208270,
+ 401658082, -532275898, 207149427, 833765363, -343175316, 401658082, 532275898, 207149427, -833765363, -343175316,
+ 416472483, -558722695, 217902617, 827270154, -339107319, 416472483, 558722695, 217902617, -827270154, -339107319,
+ 431841949, -586290861, 229212798, 820624988, -335007540, 431841949, 586290861, 229212798, -820624988, -335007540,
+ 447786335, -615019650, 241100489, 813828443, -330879528, 447786335, 615019650, 241100489, -813828443, -330879528,
+ 464326111, -644949597, 253586805, 806879270, -326727141, 464326111, 644949597, 253586805, -806879270, -326727141,
+ 481482377, -676122557, 266693475, 799776409, -322554559, 481482377, 676122557, 266693475, -799776409, -322554559,
+ 499276882, -708581728, 280442865, 792519013, -318366296, 499276882, 708581728, 280442865, -792519013, -318366296,
+ 517732032, -742371685, 294857996, 785106465, -314167221, 517732032, 742371685, 294857996, -785106465, -314167221,
+ 536870912, -777538408, 309962566, 777538408, -309962566, 536870912, 777538408, 309962566, -777538408, -309962566,
+ 556717294, -814129313, 325780968, 769814766, -305757943, 556717294, 814129313, 325780968, -769814766, -305757943,
+ 577295658, -852193284, 342338310, 761935777, -301559360, 577295658, 852193284, 342338310, -761935777, -301559360,
+ 598631206, -891780698, 359660433, 753902014, -297373230, 598631206, 891780698, 359660433, -753902014, -297373230,
+ 620749877, -932943463, 377773927, 745714425, -293206383, 620749877, 932943463, 377773927, -745714425, -293206383,
+ 643678365, -975735041, 396706151, 737374355, -289066077, 643678365, 975735041, 396706151, -737374355, -289066077,
+ 667444134, -1020210487, 416485252, 728883588, -284960004, 667444134, 1020210487, 416485252, -728883588, -284960004,
+ 692075438, -1066426476, 437140179, 720244375, -280896294, 692075438, 1066426476, 437140179, -720244375, -280896294,
+ 717601336, -1114441339, 458700704, 711459472, -276883515, 717601336, 1114441339, 458700704, -711459472, -276883515,
+ 744051710, -1164315096, 481197437, 702532174, -272930673, 744051710, 1164315096, 481197437, -702532174, -272930673
+
+};
+
+/* ----------------------------------------------------------------------
+** Desired gains, in dB, per band
+** ------------------------------------------------------------------- */
+
+int gainDB[5] = {0, -3, 6, 4, -6};
+
+float32_t snr;
+
+
+/* ----------------------------------------------------------------------
+ * Graphic equalizer Example
+ * ------------------------------------------------------------------- */
+
+int32_t main(void)
+{
+ float32_t *inputF32, *outputF32;
+ arm_biquad_cas_df1_32x64_ins_q31 S1;
+ arm_biquad_cas_df1_32x64_ins_q31 S2;
+ arm_biquad_casd_df1_inst_q31 S3;
+ arm_biquad_casd_df1_inst_q31 S4;
+ arm_biquad_casd_df1_inst_q31 S5;
+ int i;
+ int32_t status;
+
+ inputF32 = &testInput_f32[0];
+ outputF32 = &testOutput[0];
+
+ /* Initialize the state and coefficient buffers for all Biquad sections */
+
+ arm_biquad_cas_df1_32x64_init_q31(&S1, NUMSTAGES,
+ (q31_t *) &coeffTable[190*0 + 10*(gainDB[0] + 9)],
+ &biquadStateBand1Q31[0], 2);
+
+ arm_biquad_cas_df1_32x64_init_q31(&S2, NUMSTAGES,
+ (q31_t *) &coeffTable[190*1 + 10*(gainDB[1] + 9)],
+ &biquadStateBand2Q31[0], 2);
+
+ arm_biquad_cascade_df1_init_q31(&S3, NUMSTAGES,
+ (q31_t *) &coeffTable[190*2 + 10*(gainDB[2] + 9)],
+ &biquadStateBand3Q31[0], 2);
+
+ arm_biquad_cascade_df1_init_q31(&S4, NUMSTAGES,
+ (q31_t *) &coeffTable[190*3 + 10*(gainDB[3] + 9)],
+ &biquadStateBand4Q31[0], 2);
+
+ arm_biquad_cascade_df1_init_q31(&S5, NUMSTAGES,
+ (q31_t *) &coeffTable[190*4 + 10*(gainDB[4] + 9)],
+ &biquadStateBand5Q31[0], 2);
+
+
+ /* Call the process functions and needs to change filter coefficients
+ for varying the gain of each band */
+
+ for(i=0; i < NUMBLOCKS; i++)
+ {
+
+ /* ----------------------------------------------------------------------
+ ** Convert block of input data from float to Q31
+ ** ------------------------------------------------------------------- */
+
+ arm_float_to_q31(inputF32 + (i*BLOCKSIZE), inputQ31, BLOCKSIZE);
+
+ /* ----------------------------------------------------------------------
+ ** Scale down by 1/8. This provides additional headroom so that the
+ ** graphic EQ can apply gain.
+ ** ------------------------------------------------------------------- */
+
+ arm_scale_q31(inputQ31, 0x7FFFFFFF, -3, inputQ31, BLOCKSIZE);
+
+ /* ----------------------------------------------------------------------
+ ** Call the Q31 Biquad Cascade DF1 32x64 process function for band1, band2
+ ** ------------------------------------------------------------------- */
+
+ arm_biquad_cas_df1_32x64_q31(&S1, inputQ31, outputQ31, BLOCKSIZE);
+ arm_biquad_cas_df1_32x64_q31(&S2, outputQ31, outputQ31, BLOCKSIZE);
+
+ /* ----------------------------------------------------------------------
+ ** Call the Q31 Biquad Cascade DF1 process function for band3, band4, band5
+ ** ------------------------------------------------------------------- */
+
+ arm_biquad_cascade_df1_q31(&S3, outputQ31, outputQ31, BLOCKSIZE);
+ arm_biquad_cascade_df1_q31(&S4, outputQ31, outputQ31, BLOCKSIZE);
+ arm_biquad_cascade_df1_q31(&S5, outputQ31, outputQ31, BLOCKSIZE);
+
+ /* ----------------------------------------------------------------------
+ ** Convert Q31 result back to float
+ ** ------------------------------------------------------------------- */
+
+ arm_q31_to_float(outputQ31, outputF32 + (i * BLOCKSIZE), BLOCKSIZE);
+
+ /* ----------------------------------------------------------------------
+ ** Scale back up
+ ** ------------------------------------------------------------------- */
+
+ arm_scale_f32(outputF32 + (i * BLOCKSIZE), 8.0f, outputF32 + (i * BLOCKSIZE), BLOCKSIZE);
+ };
+
+ snr = arm_snr_f32(testRefOutput_f32, testOutput, TESTLENGTH);
+
+ if (snr < SNR_THRESHOLD_F32)
+ {
+ status = ARM_MATH_TEST_FAILURE;
+ }
+ else
+ {
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* ----------------------------------------------------------------------
+ ** Loop here if the signal does not match the reference output.
+ ** ------------------------------------------------------------------- */
+
+ if ( status != ARM_MATH_SUCCESS)
+ {
+ while (1);
+ }
+
+ while (1); /* main function does not return */
+}
+
+/** \endlink */
+
+
+
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.c
new file mode 100644
index 0000000..f615e6f
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.c
@@ -0,0 +1,466 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.0 b
+*
+* Project: CMSIS DSP Library
+*
+* Title: math_helper.c
+*
+* Description: Definition of all helper functions required.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+/* ----------------------------------------------------------------------
+* Include standard header files
+* -------------------------------------------------------------------- */
+#include<math.h>
+
+/* ----------------------------------------------------------------------
+* Include project header files
+* -------------------------------------------------------------------- */
+#include "math_helper.h"
+
+/**
+ * @brief Caluclation of SNR
+ * @param[in] pRef Pointer to the reference buffer
+ * @param[in] pTest Pointer to the test buffer
+ * @param[in] buffSize total number of samples
+ * @return SNR
+ * The function Caluclates signal to noise ratio for the reference output
+ * and test output
+ */
+
+float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize)
+{
+ float EnergySignal = 0.0, EnergyError = 0.0;
+ uint32_t i;
+ float SNR;
+ int temp;
+ int *test;
+
+ for (i = 0; i < buffSize; i++)
+ {
+ /* Checking for a NAN value in pRef array */
+ test = (int *)(&pRef[i]);
+ temp = *test;
+
+ if (temp == 0x7FC00000)
+ {
+ return(0);
+ }
+
+ /* Checking for a NAN value in pTest array */
+ test = (int *)(&pTest[i]);
+ temp = *test;
+
+ if (temp == 0x7FC00000)
+ {
+ return(0);
+ }
+ EnergySignal += pRef[i] * pRef[i];
+ EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]);
+ }
+
+ /* Checking for a NAN value in EnergyError */
+ test = (int *)(&EnergyError);
+ temp = *test;
+
+ if (temp == 0x7FC00000)
+ {
+ return(0);
+ }
+
+
+ SNR = 10 * log10 (EnergySignal / EnergyError);
+
+ return (SNR);
+
+}
+
+
+/**
+ * @brief Provide guard bits for Input buffer
+ * @param[in,out] input_buf Pointer to input buffer
+ * @param[in] blockSize block Size
+ * @param[in] guard_bits guard bits
+ * @return none
+ * The function Provides the guard bits for the buffer
+ * to avoid overflow
+ */
+
+void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < blockSize; i++)
+ {
+ input_buf[i] = input_buf[i] >> guard_bits;
+ }
+}
+
+/**
+ * @brief Converts float to fixed in q12.20 format
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to outputbuffer
+ * @param[in] numSamples number of samples in the input buffer
+ * @return none
+ * The function converts floating point values to fixed point(q12.20) values
+ */
+
+void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 1048576.0f corresponds to pow(2, 20) */
+ pOut[i] = (q31_t) (pIn[i] * 1048576.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 1.0)
+ {
+ pOut[i] = 0x000FFFFF;
+ }
+ }
+}
+
+/**
+ * @brief Compare MATLAB Reference Output and ARM Test output
+ * @param[in] pIn Pointer to Ref buffer
+ * @param[in] pOut Pointer to Test buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return maximum difference
+ */
+
+uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t *pOut, uint32_t numSamples)
+{
+ uint32_t i;
+ int32_t diff, diffCrnt = 0;
+ uint32_t maxDiff = 0;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ diff = pIn[i] - pOut[i];
+ diffCrnt = (diff > 0) ? diff : -diff;
+
+ if (diffCrnt > maxDiff)
+ {
+ maxDiff = diffCrnt;
+ }
+ }
+
+ return(maxDiff);
+}
+
+/**
+ * @brief Compare MATLAB Reference Output and ARM Test output
+ * @param[in] pIn Pointer to Ref buffer
+ * @param[in] pOut Pointer to Test buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return maximum difference
+ */
+
+uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples)
+{
+ uint32_t i;
+ int32_t diff, diffCrnt = 0;
+ uint32_t maxDiff = 0;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ diff = pIn[i] - pOut[i];
+ diffCrnt = (diff > 0) ? diff : -diff;
+
+ if (diffCrnt > maxDiff)
+ {
+ maxDiff = diffCrnt;
+ }
+ }
+
+ return(maxDiff);
+}
+
+/**
+ * @brief Provide guard bits for Input buffer
+ * @param[in,out] input_buf Pointer to input buffer
+ * @param[in] blockSize block Size
+ * @param[in] guard_bits guard bits
+ * @return none
+ * The function Provides the guard bits for the buffer
+ * to avoid overflow
+ */
+
+void arm_provide_guard_bits_q31 (q31_t * input_buf,
+ uint32_t blockSize,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < blockSize; i++)
+ {
+ input_buf[i] = input_buf[i] >> guard_bits;
+ }
+}
+
+/**
+ * @brief Provide guard bits for Input buffer
+ * @param[in,out] input_buf Pointer to input buffer
+ * @param[in] blockSize block Size
+ * @param[in] guard_bits guard bits
+ * @return none
+ * The function Provides the guard bits for the buffer
+ * to avoid overflow
+ */
+
+void arm_provide_guard_bits_q7 (q7_t * input_buf,
+ uint32_t blockSize,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < blockSize; i++)
+ {
+ input_buf[i] = input_buf[i] >> guard_bits;
+ }
+}
+
+
+
+/**
+ * @brief Caluclates number of guard bits
+ * @param[in] num_adds number of additions
+ * @return guard bits
+ * The function Caluclates the number of guard bits
+ * depending on the numtaps
+ */
+
+uint32_t arm_calc_guard_bits (uint32_t num_adds)
+{
+ uint32_t i = 1, j = 0;
+
+ if (num_adds == 1)
+ {
+ return (0);
+ }
+
+ while (i < num_adds)
+ {
+ i = i * 2;
+ j++;
+ }
+
+ return (j);
+}
+
+/**
+ * @brief Apply guard bits to buffer
+ * @param[in,out] pIn pointer to input buffer
+ * @param[in] numSamples number of samples in the input buffer
+ * @param[in] guard_bits guard bits
+ * @return none
+ */
+
+void arm_apply_guard_bits (float32_t *pIn,
+ uint32_t numSamples,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ pIn[i] = pIn[i] * arm_calc_2pow(guard_bits);
+ }
+}
+
+/**
+ * @brief Calculates pow(2, numShifts)
+ * @param[in] numShifts number of shifts
+ * @return pow(2, numShifts)
+ */
+uint32_t arm_calc_2pow(uint32_t numShifts)
+{
+
+ uint32_t i, val = 1;
+
+ for (i = 0; i < numShifts; i++)
+ {
+ val = val * 2;
+ }
+
+ return(val);
+}
+
+
+
+/**
+ * @brief Converts float to fixed q14
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to output buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 16384.0f corresponds to pow(2, 14) */
+ pOut[i] = (q15_t) (pIn[i] * 16384.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 2.0)
+ {
+ pOut[i] = 0x7FFF;
+ }
+
+ }
+
+}
+
+
+/**
+ * @brief Converts float to fixed q30 format
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to output buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q30 (float *pIn, q31_t * pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 1073741824.0f corresponds to pow(2, 30) */
+ pOut[i] = (q31_t) (pIn[i] * 1073741824.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 2.0)
+ {
+ pOut[i] = 0x7FFFFFFF;
+ }
+ }
+}
+
+/**
+ * @brief Converts float to fixed q30 format
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to output buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 1073741824.0f corresponds to pow(2, 30) */
+ pOut[i] = (q31_t) (pIn[i] * 536870912.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 4.0)
+ {
+ pOut[i] = 0x7FFFFFFF;
+ }
+ }
+}
+
+
+/**
+ * @brief Converts float to fixed q28 format
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to output buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 268435456.0f corresponds to pow(2, 28) */
+ pOut[i] = (q31_t) (pIn[i] * 268435456.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 8.0)
+ {
+ pOut[i] = 0x7FFFFFFF;
+ }
+ }
+}
+
+/**
+ * @brief Clip the float values to +/- 1
+ * @param[in,out] pIn input buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_clip_f32 (float *pIn, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ if (pIn[i] > 1.0f)
+ {
+ pIn[i] = 1.0;
+ }
+ else if ( pIn[i] < -1.0f)
+ {
+ pIn[i] = -1.0;
+ }
+
+ }
+}
+
+
+
+
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.h
new file mode 100644
index 0000000..5a18734
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.h
@@ -0,0 +1,63 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.0
+*
+* Project: CMSIS DSP Library
+*
+* Title: math_helper.h
+*
+* Description: Prototypes of all helper functions required.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+#ifndef MATH_HELPER_H
+#define MATH_HELPER_H
+
+float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize);
+void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples);
+void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits);
+void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits);
+void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples);
+void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_clip_f32(float *pIn, uint32_t numSamples);
+uint32_t arm_calc_guard_bits(uint32_t num_adds);
+void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits);
+uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples);
+uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples);
+uint32_t arm_calc_2pow(uint32_t guard_bits);
+#endif
+
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_data.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_data.c
new file mode 100644
index 0000000..309326e
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_data.c
@@ -0,0 +1,23616 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.0
+*
+* Project: CMSIS DSP Library
+* Title: arm_linear_interp_data.c
+*
+* Description: Data file used for example. Generation method described
+* below
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/* ----------------------------------------------------------------------
+* Table generated from following MATLAB Command
+* x = -pi: 0.00005 : (2*pi - 0.00005);
+* y = sin(x);
+* where pi value is 3.141592653589793
+* --------------------------------------------------------------------*/
+
+float arm_linear_interep_table[188495] = {
+
+
+-0.000000000000000122, -0.000049999999979173, -0.000099999999833667, -0.000149999999437717, -0.000199999998666767, -0.000249999997395817, -0.000299999995500311, -0.000349999992854362,
+-0.000399999989333412, -0.000449999984812462, -0.000499999979166956, -0.000549999972271007, -0.000599999964000057, -0.000649999954229107, -0.000699999942833602, -0.000749999929687653,
+-0.000799999914666704, -0.000849999897645755, -0.000899999878500250, -0.000949999857104302, -0.000999999833333354, -0.001049999807062851, -0.001099999778166904, -0.001149999746520957,
+-0.001199999712000011, -0.001249999674479510, -0.001299999633833566, -0.001349999589937622, -0.001399999542666680, -0.001449999491896183, -0.001499999437500243, -0.001549999379354304,
+-0.001599999317333367, -0.001649999251312876, -0.001699999181166942, -0.001749999106771011, -0.001799999028000082, -0.001849998944729599, -0.001899998856833675, -0.001949998764187754,
+-0.001999998666666836, -0.002049998564146365, -0.002099998456500453, -0.002149998343604546, -0.002199998225334087, -0.002249998101563188, -0.002299997972167294, -0.002349997837021405,
+-0.002399997696000966, -0.002449997548980088, -0.002499997395834216, -0.002549997236438351, -0.002599997070667937, -0.002649996898397086, -0.002699996719501243, -0.002749996533855408,
+-0.002799996341335026, -0.002849996141814208, -0.002899995935168401, -0.002949995721272604, -0.002999995500002261, -0.003049995271231486, -0.003099995034835722, -0.003149994790690415,
+-0.003199994538669677, -0.003249994278648952, -0.003299994010503243, -0.003349993734107991, -0.003399993449337312, -0.003449993156066649, -0.003499992854171003, -0.003549992543525819,
+-0.003599992224005209, -0.003649991895484619, -0.003699991557839049, -0.003749991210943944, -0.003799990854673418, -0.003849990488902914, -0.003899990113507434, -0.003949989728362423,
+-0.003999989333341993, -0.004049988928321590, -0.004099988513176658, -0.004149988087781312, -0.004199987652010995, -0.004249987205740709, -0.004299986748845899, -0.004349986281200678,
+-0.004399985802680492, -0.004449985313160341, -0.004499984812515671, -0.004549984300620594, -0.004599983777350557, -0.004649983242580561, -0.004699982696186050, -0.004749982138041138,
+-0.004799981568021272, -0.004849980986001451, -0.004899980391857122, -0.004949979785462398, -0.004999979166692725, -0.005049978535423547, -0.005099977891528979, -0.005149977234884466,
+-0.005199976565365011, -0.005249975882846058, -0.005299975187201721, -0.005349974478307446, -0.005399973756038235, -0.005449973020269535, -0.005499972270875456, -0.005549971507731448,
+-0.005599970730712511, -0.005649969939694091, -0.005699969134550302, -0.005749968315156590, -0.005799967481387958, -0.005849966633119851, -0.005899965770226383, -0.005949964892583000,
+-0.005999964000064706, -0.006049963092546945, -0.006099962169903833, -0.006149961232010816, -0.006199960278743339, -0.006249959309975518, -0.006299958325582797, -0.006349957325440182,
+-0.006399956309423117, -0.006449955277405718, -0.006499954229263430, -0.006549953164871257, -0.006599952084104644, -0.006649950986837708, -0.006699949872945895, -0.006749948742304206,
+-0.006799947594788089, -0.006849946430271660, -0.006899945248630365, -0.006949944049739206, -0.006999942833473632, -0.007049941599707755, -0.007099940348317025, -0.007149939079176889,
+-0.007199937792161461, -0.007249936487146187, -0.007299935164006074, -0.007349933822616566, -0.007399932462851779, -0.007449931084587162, -0.007499929687697716, -0.007549928272058891,
+-0.007599926837544801, -0.007649925384030893, -0.007699923911392173, -0.007749922419504085, -0.007799920908240749, -0.007849919377477610, -0.007899917827089672, -0.007949916256952384,
+-0.007999914666939863, -0.008049913056927554, -0.008099911426790906, -0.008149909776404035, -0.008199908105642390, -0.008249906414380975, -0.008299904702495238, -0.008349902969859295,
+-0.008399901216348595, -0.008449899441838141, -0.008499897646203384, -0.008549895829318437, -0.008599893991058752, -0.008649892131299332, -0.008699890249915625, -0.008749888346781748,
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+};
+
+
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_example_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_example_f32.c
new file mode 100644
index 0000000..87908ed
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_example_f32.c
@@ -0,0 +1,204 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.0
+*
+* Project: CMSIS DSP Library
+* Title: arm_linear_interp_example_f32.c
+*
+* Description: Example code demonstrating usage of sin function
+* and uses linear interpolation to get higher precision
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+
+/**
+ * @ingroup groupExamples
+ */
+
+/**
+ * @defgroup LinearInterpExample Linear Interpolate Example
+ *
+ * <b> CMSIS DSP Software Library -- Linear Interpolate Example </b>
+ *
+ * <b> Description </b>
+ * This example demonstrates usage of linear interpolate modules and fast math modules.
+ * Method 1 uses fast math sine function to calculate sine values using cubic interpolation and method 2 uses
+ * linear interpolation function and results are compared to reference output.
+ * Example shows linear interpolation function can be used to get higher precision compared to fast math sin calculation.
+ *
+ * \par Block Diagram:
+ * \par
+ * \image html linearInterpExampleMethod1.gif "Method 1: Sine caluclation using fast math"
+ * \par
+ * \image html linearInterpExampleMethod2.gif "Method 2: Sine caluclation using interpolation function"
+ *
+ * \par Variables Description:
+ * \par
+ * \li \c testInputSin_f32 points to the input values for sine calculation
+ * \li \c testRefSinOutput32_f32 points to the reference values caculated from sin() matlab function
+ * \li \c testOutput points to output buffer calculation from cubic interpolation
+ * \li \c testLinIntOutput points to output buffer calculation from linear interpolation
+ * \li \c snr1 Signal to noise ratio for reference and cubic interpolation output
+ * \li \c snr2 Signal to noise ratio for reference and linear interpolation output
+ *
+ * \par CMSIS DSP Software Library Functions Used:
+ * \par
+ * - arm_sin_f32()
+ * - arm_linear_interp_f32()
+ *
+ * <b> Refer </b>
+ * \link arm_linear_interp_example_f32.c \endlink
+ *
+ */
+
+
+/** \example arm_linear_interp_example_f32.c
+ */
+
+#include "arm_math.h"
+#include "math_helper.h"
+
+#define SNR_THRESHOLD 90
+#define TEST_LENGTH_SAMPLES 10
+#define XSPACING (0.00005f)
+
+/* ----------------------------------------------------------------------
+* Test input data for F32 SIN function
+* Generated by the MATLAB rand() function
+* randn('state', 0)
+* xi = (((1/4.18318581819710)* randn(blockSize, 1) * 2* pi));
+* --------------------------------------------------------------------*/
+float32_t testInputSin_f32[TEST_LENGTH_SAMPLES] =
+{
+ -0.649716504673081170, -2.501723745497831200,
+ 0.188250329003310100, 0.432092748487532540,
+ -1.722010988459680800, 1.788766476323060600,
+ 1.786136060975809500, -0.056525543169408797,
+ 0.491596272728153760, 0.262309671126153390
+};
+
+/*------------------------------------------------------------------------------
+* Reference out of SIN F32 function for Block Size = 10
+* Calculated from sin(testInputSin_f32)
+*------------------------------------------------------------------------------*/
+float32_t testRefSinOutput32_f32[TEST_LENGTH_SAMPLES] =
+{
+ -0.604960695383043530, -0.597090287967934840,
+ 0.187140422442966500, 0.418772124875992690,
+ -0.988588831792106880, 0.976338412038794010,
+ 0.976903856413481100, -0.056495446835214236,
+ 0.472033731854734240, 0.259311907228582830
+};
+
+/*------------------------------------------------------------------------------
+* Method 1: Test out Buffer Calculated from Cubic Interpolation
+*------------------------------------------------------------------------------*/
+float32_t testOutput[TEST_LENGTH_SAMPLES];
+
+/*------------------------------------------------------------------------------
+* Method 2: Test out buffer Calculated from Linear Interpolation
+*------------------------------------------------------------------------------*/
+float32_t testLinIntOutput[TEST_LENGTH_SAMPLES];
+
+/*------------------------------------------------------------------------------
+* External table used for linear interpolation
+*------------------------------------------------------------------------------*/
+extern float arm_linear_interep_table[188495];
+
+/* ----------------------------------------------------------------------
+* Global Variables for caluclating SNR's for Method1 & Method 2
+* ------------------------------------------------------------------- */
+float32_t snr1;
+float32_t snr2;
+
+/* ----------------------------------------------------------------------------
+* Calculation of Sine values from Cubic Interpolation and Linear interpolation
+* ---------------------------------------------------------------------------- */
+int32_t main(void)
+{
+ uint32_t i;
+ arm_status status;
+
+ arm_linear_interp_instance_f32 S = {188495, -3.141592653589793238, XSPACING, &arm_linear_interep_table[0]};
+
+ /*------------------------------------------------------------------------------
+ * Method 1: Test out Calculated from Cubic Interpolation
+ *------------------------------------------------------------------------------*/
+ for(i=0; i< TEST_LENGTH_SAMPLES; i++)
+ {
+ testOutput[i] = arm_sin_f32(testInputSin_f32[i]);
+ }
+
+ /*------------------------------------------------------------------------------
+ * Method 2: Test out Calculated from Cubic Interpolation and Linear interpolation
+ *------------------------------------------------------------------------------*/
+
+ for(i=0; i< TEST_LENGTH_SAMPLES; i++)
+ {
+ testLinIntOutput[i] = arm_linear_interp_f32(&S, testInputSin_f32[i]);
+ }
+
+ /*------------------------------------------------------------------------------
+ * SNR calculation for method 1
+ *------------------------------------------------------------------------------*/
+ snr1 = arm_snr_f32(testRefSinOutput32_f32, testOutput, 2);
+
+ /*------------------------------------------------------------------------------
+ * SNR calculation for method 2
+ *------------------------------------------------------------------------------*/
+ snr2 = arm_snr_f32(testRefSinOutput32_f32, testLinIntOutput, 2);
+
+ /*------------------------------------------------------------------------------
+ * Initialise status depending on SNR calculations
+ *------------------------------------------------------------------------------*/
+ if ( snr2 > snr1)
+ {
+ status = ARM_MATH_SUCCESS;
+ }
+ else
+ {
+ status = ARM_MATH_TEST_FAILURE;
+ }
+
+ /* ----------------------------------------------------------------------
+ ** Loop here if the signals fail the PASS check.
+ ** This denotes a test failure
+ ** ------------------------------------------------------------------- */
+ if ( status != ARM_MATH_SUCCESS)
+ {
+ while (1);
+ }
+
+ while (1); /* main function does not return */
+}
+
+ /** \endlink */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.c
new file mode 100644
index 0000000..f615e6f
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.c
@@ -0,0 +1,466 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.0 b
+*
+* Project: CMSIS DSP Library
+*
+* Title: math_helper.c
+*
+* Description: Definition of all helper functions required.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+/* ----------------------------------------------------------------------
+* Include standard header files
+* -------------------------------------------------------------------- */
+#include<math.h>
+
+/* ----------------------------------------------------------------------
+* Include project header files
+* -------------------------------------------------------------------- */
+#include "math_helper.h"
+
+/**
+ * @brief Caluclation of SNR
+ * @param[in] pRef Pointer to the reference buffer
+ * @param[in] pTest Pointer to the test buffer
+ * @param[in] buffSize total number of samples
+ * @return SNR
+ * The function Caluclates signal to noise ratio for the reference output
+ * and test output
+ */
+
+float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize)
+{
+ float EnergySignal = 0.0, EnergyError = 0.0;
+ uint32_t i;
+ float SNR;
+ int temp;
+ int *test;
+
+ for (i = 0; i < buffSize; i++)
+ {
+ /* Checking for a NAN value in pRef array */
+ test = (int *)(&pRef[i]);
+ temp = *test;
+
+ if (temp == 0x7FC00000)
+ {
+ return(0);
+ }
+
+ /* Checking for a NAN value in pTest array */
+ test = (int *)(&pTest[i]);
+ temp = *test;
+
+ if (temp == 0x7FC00000)
+ {
+ return(0);
+ }
+ EnergySignal += pRef[i] * pRef[i];
+ EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]);
+ }
+
+ /* Checking for a NAN value in EnergyError */
+ test = (int *)(&EnergyError);
+ temp = *test;
+
+ if (temp == 0x7FC00000)
+ {
+ return(0);
+ }
+
+
+ SNR = 10 * log10 (EnergySignal / EnergyError);
+
+ return (SNR);
+
+}
+
+
+/**
+ * @brief Provide guard bits for Input buffer
+ * @param[in,out] input_buf Pointer to input buffer
+ * @param[in] blockSize block Size
+ * @param[in] guard_bits guard bits
+ * @return none
+ * The function Provides the guard bits for the buffer
+ * to avoid overflow
+ */
+
+void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < blockSize; i++)
+ {
+ input_buf[i] = input_buf[i] >> guard_bits;
+ }
+}
+
+/**
+ * @brief Converts float to fixed in q12.20 format
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to outputbuffer
+ * @param[in] numSamples number of samples in the input buffer
+ * @return none
+ * The function converts floating point values to fixed point(q12.20) values
+ */
+
+void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 1048576.0f corresponds to pow(2, 20) */
+ pOut[i] = (q31_t) (pIn[i] * 1048576.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 1.0)
+ {
+ pOut[i] = 0x000FFFFF;
+ }
+ }
+}
+
+/**
+ * @brief Compare MATLAB Reference Output and ARM Test output
+ * @param[in] pIn Pointer to Ref buffer
+ * @param[in] pOut Pointer to Test buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return maximum difference
+ */
+
+uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t *pOut, uint32_t numSamples)
+{
+ uint32_t i;
+ int32_t diff, diffCrnt = 0;
+ uint32_t maxDiff = 0;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ diff = pIn[i] - pOut[i];
+ diffCrnt = (diff > 0) ? diff : -diff;
+
+ if (diffCrnt > maxDiff)
+ {
+ maxDiff = diffCrnt;
+ }
+ }
+
+ return(maxDiff);
+}
+
+/**
+ * @brief Compare MATLAB Reference Output and ARM Test output
+ * @param[in] pIn Pointer to Ref buffer
+ * @param[in] pOut Pointer to Test buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return maximum difference
+ */
+
+uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples)
+{
+ uint32_t i;
+ int32_t diff, diffCrnt = 0;
+ uint32_t maxDiff = 0;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ diff = pIn[i] - pOut[i];
+ diffCrnt = (diff > 0) ? diff : -diff;
+
+ if (diffCrnt > maxDiff)
+ {
+ maxDiff = diffCrnt;
+ }
+ }
+
+ return(maxDiff);
+}
+
+/**
+ * @brief Provide guard bits for Input buffer
+ * @param[in,out] input_buf Pointer to input buffer
+ * @param[in] blockSize block Size
+ * @param[in] guard_bits guard bits
+ * @return none
+ * The function Provides the guard bits for the buffer
+ * to avoid overflow
+ */
+
+void arm_provide_guard_bits_q31 (q31_t * input_buf,
+ uint32_t blockSize,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < blockSize; i++)
+ {
+ input_buf[i] = input_buf[i] >> guard_bits;
+ }
+}
+
+/**
+ * @brief Provide guard bits for Input buffer
+ * @param[in,out] input_buf Pointer to input buffer
+ * @param[in] blockSize block Size
+ * @param[in] guard_bits guard bits
+ * @return none
+ * The function Provides the guard bits for the buffer
+ * to avoid overflow
+ */
+
+void arm_provide_guard_bits_q7 (q7_t * input_buf,
+ uint32_t blockSize,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < blockSize; i++)
+ {
+ input_buf[i] = input_buf[i] >> guard_bits;
+ }
+}
+
+
+
+/**
+ * @brief Caluclates number of guard bits
+ * @param[in] num_adds number of additions
+ * @return guard bits
+ * The function Caluclates the number of guard bits
+ * depending on the numtaps
+ */
+
+uint32_t arm_calc_guard_bits (uint32_t num_adds)
+{
+ uint32_t i = 1, j = 0;
+
+ if (num_adds == 1)
+ {
+ return (0);
+ }
+
+ while (i < num_adds)
+ {
+ i = i * 2;
+ j++;
+ }
+
+ return (j);
+}
+
+/**
+ * @brief Apply guard bits to buffer
+ * @param[in,out] pIn pointer to input buffer
+ * @param[in] numSamples number of samples in the input buffer
+ * @param[in] guard_bits guard bits
+ * @return none
+ */
+
+void arm_apply_guard_bits (float32_t *pIn,
+ uint32_t numSamples,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ pIn[i] = pIn[i] * arm_calc_2pow(guard_bits);
+ }
+}
+
+/**
+ * @brief Calculates pow(2, numShifts)
+ * @param[in] numShifts number of shifts
+ * @return pow(2, numShifts)
+ */
+uint32_t arm_calc_2pow(uint32_t numShifts)
+{
+
+ uint32_t i, val = 1;
+
+ for (i = 0; i < numShifts; i++)
+ {
+ val = val * 2;
+ }
+
+ return(val);
+}
+
+
+
+/**
+ * @brief Converts float to fixed q14
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to output buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 16384.0f corresponds to pow(2, 14) */
+ pOut[i] = (q15_t) (pIn[i] * 16384.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 2.0)
+ {
+ pOut[i] = 0x7FFF;
+ }
+
+ }
+
+}
+
+
+/**
+ * @brief Converts float to fixed q30 format
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to output buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q30 (float *pIn, q31_t * pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 1073741824.0f corresponds to pow(2, 30) */
+ pOut[i] = (q31_t) (pIn[i] * 1073741824.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 2.0)
+ {
+ pOut[i] = 0x7FFFFFFF;
+ }
+ }
+}
+
+/**
+ * @brief Converts float to fixed q30 format
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to output buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 1073741824.0f corresponds to pow(2, 30) */
+ pOut[i] = (q31_t) (pIn[i] * 536870912.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 4.0)
+ {
+ pOut[i] = 0x7FFFFFFF;
+ }
+ }
+}
+
+
+/**
+ * @brief Converts float to fixed q28 format
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to output buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 268435456.0f corresponds to pow(2, 28) */
+ pOut[i] = (q31_t) (pIn[i] * 268435456.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 8.0)
+ {
+ pOut[i] = 0x7FFFFFFF;
+ }
+ }
+}
+
+/**
+ * @brief Clip the float values to +/- 1
+ * @param[in,out] pIn input buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_clip_f32 (float *pIn, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ if (pIn[i] > 1.0f)
+ {
+ pIn[i] = 1.0;
+ }
+ else if ( pIn[i] < -1.0f)
+ {
+ pIn[i] = -1.0;
+ }
+
+ }
+}
+
+
+
+
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.h
new file mode 100644
index 0000000..5a18734
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.h
@@ -0,0 +1,63 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.0
+*
+* Project: CMSIS DSP Library
+*
+* Title: math_helper.h
+*
+* Description: Prototypes of all helper functions required.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+#ifndef MATH_HELPER_H
+#define MATH_HELPER_H
+
+float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize);
+void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples);
+void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits);
+void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits);
+void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples);
+void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_clip_f32(float *pIn, uint32_t numSamples);
+uint32_t arm_calc_guard_bits(uint32_t num_adds);
+void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits);
+uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples);
+uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples);
+uint32_t arm_calc_2pow(uint32_t guard_bits);
+#endif
+
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_matrix_example/arm_matrix_example_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_matrix_example/arm_matrix_example_f32.c
new file mode 100644
index 0000000..3d7a505
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_matrix_example/arm_matrix_example_f32.c
@@ -0,0 +1,233 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.0
+*
+* Project: CMSIS DSP Library
+* Title: arm_matrix_example_f32.c
+*
+* Description: Example code demonstrating least square fit to data
+* using matrix functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+ * @ingroup groupExamples
+ */
+
+/**
+ * @defgroup MatrixExample Matrix Example
+ *
+ * \par Description:
+ * \par
+ * Demonstrates the use of Matrix Transpose, Matrix Muliplication, and Matrix Inverse
+ * functions to apply least squares fitting to input data. Least squares fitting is
+ * the procedure for finding the best-fitting curve that minimizes the sum of the
+ * squares of the offsets (least square error) from a given set of data.
+ *
+ * \par Algorithm:
+ * \par
+ * The linear combination of parameters considered is as follows:
+ * \par
+ * <code>A * X = B</code>, where \c X is the unknown value and can be estimated
+ * from \c A & \c B.
+ * \par
+ * The least squares estimate \c X is given by the following equation:
+ * \par
+ * <code>X = Inverse(A<sup>T</sup> * A) * A<sup>T</sup> * B</code>
+ *
+ * \par Block Diagram:
+ * \par
+ * \image html matrixExample.gif
+ *
+ * \par Variables Description:
+ * \par
+ * \li \c A_f32 input matrix in the linear combination equation
+ * \li \c B_f32 output matrix in the linear combination equation
+ * \li \c X_f32 unknown matrix estimated using \c A_f32 & \c B_f32 matrices
+ *
+ * \par CMSIS DSP Software Library Functions Used:
+ * \par
+ * - arm_mat_init_f32()
+ * - arm_mat_trans_f32()
+ * - arm_mat_mult_f32()
+ * - arm_mat_inverse_f32()
+ *
+ * <b> Refer </b>
+ * \link arm_matrix_example_f32.c \endlink
+ *
+ */
+
+
+/** \example arm_matrix_example_f32.c
+ */
+
+#include "arm_math.h"
+#include "math_helper.h"
+
+#define SNR_THRESHOLD 90
+
+/* --------------------------------------------------------------------------------
+* Test input data(Cycles) taken from FIR Q15 module for differant cases of blockSize
+* and tapSize
+* --------------------------------------------------------------------------------- */
+
+const float32_t B_f32[4] =
+{
+ 782.0, 7577.0, 470.0, 4505.0
+};
+
+/* --------------------------------------------------------------------------------
+* Formula to fit is C1 + C2 * numTaps + C3 * blockSize + C4 * numTaps * blockSize
+* -------------------------------------------------------------------------------- */
+
+const float32_t A_f32[16] =
+{
+ /* Const, numTaps, blockSize, numTaps*blockSize */
+ 1.0, 32.0, 4.0, 128.0,
+ 1.0, 32.0, 64.0, 2048.0,
+ 1.0, 16.0, 4.0, 64.0,
+ 1.0, 16.0, 64.0, 1024.0,
+};
+
+
+/* ----------------------------------------------------------------------
+* Temporary buffers for storing intermediate values
+* ------------------------------------------------------------------- */
+/* Transpose of A Buffer */
+float32_t AT_f32[16];
+/* (Transpose of A * A) Buffer */
+float32_t ATMA_f32[16];
+/* Inverse(Transpose of A * A) Buffer */
+float32_t ATMAI_f32[16];
+/* Test Output Buffer */
+float32_t X_f32[4];
+
+/* ----------------------------------------------------------------------
+* Reference ouput buffer C1, C2, C3 and C4 taken from MATLAB
+* ------------------------------------------------------------------- */
+const float32_t xRef_f32[4] = {73.0, 8.0, 21.25, 2.875};
+
+float32_t snr;
+
+
+/* ----------------------------------------------------------------------
+* Max magnitude FFT Bin test
+* ------------------------------------------------------------------- */
+
+int32_t main(void)
+{
+
+ arm_matrix_instance_f32 A; /* Matrix A Instance */
+ arm_matrix_instance_f32 AT; /* Matrix AT(A transpose) instance */
+ arm_matrix_instance_f32 ATMA; /* Matrix ATMA( AT multiply with A) instance */
+ arm_matrix_instance_f32 ATMAI; /* Matrix ATMAI(Inverse of ATMA) instance */
+ arm_matrix_instance_f32 B; /* Matrix B instance */
+ arm_matrix_instance_f32 X; /* Matrix X(Unknown Matrix) instance */
+
+ uint32_t srcRows, srcColumns; /* Temporary variables */
+ arm_status status;
+
+ /* Initialise A Matrix Instance with numRows, numCols and data array(A_f32) */
+ srcRows = 4;
+ srcColumns = 4;
+ arm_mat_init_f32(&A, srcRows, srcColumns, (float32_t *)A_f32);
+
+ /* Initialise Matrix Instance AT with numRows, numCols and data array(AT_f32) */
+ srcRows = 4;
+ srcColumns = 4;
+ arm_mat_init_f32(&AT, srcRows, srcColumns, AT_f32);
+
+ /* calculation of A transpose */
+ status = arm_mat_trans_f32(&A, &AT);
+
+
+ /* Initialise ATMA Matrix Instance with numRows, numCols and data array(ATMA_f32) */
+ srcRows = 4;
+ srcColumns = 4;
+ arm_mat_init_f32(&ATMA, srcRows, srcColumns, ATMA_f32);
+
+ /* calculation of AT Multiply with A */
+ status = arm_mat_mult_f32(&AT, &A, &ATMA);
+
+ /* Initialise ATMAI Matrix Instance with numRows, numCols and data array(ATMAI_f32) */
+ srcRows = 4;
+ srcColumns = 4;
+ arm_mat_init_f32(&ATMAI, srcRows, srcColumns, ATMAI_f32);
+
+ /* calculation of Inverse((Transpose(A) * A) */
+ status = arm_mat_inverse_f32(&ATMA, &ATMAI);
+
+ /* calculation of (Inverse((Transpose(A) * A)) * Transpose(A)) */
+ status = arm_mat_mult_f32(&ATMAI, &AT, &ATMA);
+
+ /* Initialise B Matrix Instance with numRows, numCols and data array(B_f32) */
+ srcRows = 4;
+ srcColumns = 1;
+ arm_mat_init_f32(&B, srcRows, srcColumns, (float32_t *)B_f32);
+
+ /* Initialise X Matrix Instance with numRows, numCols and data array(X_f32) */
+ srcRows = 4;
+ srcColumns = 1;
+ arm_mat_init_f32(&X, srcRows, srcColumns, X_f32);
+
+ /* calculation ((Inverse((Transpose(A) * A)) * Transpose(A)) * B) */
+ status = arm_mat_mult_f32(&ATMA, &B, &X);
+
+ /* Comparison of reference with test output */
+ snr = arm_snr_f32((float32_t *)xRef_f32, X_f32, 4);
+
+ /*------------------------------------------------------------------------------
+ * Initialise status depending on SNR calculations
+ *------------------------------------------------------------------------------*/
+ if ( snr > SNR_THRESHOLD)
+ {
+ status = ARM_MATH_SUCCESS;
+ }
+ else
+ {
+ status = ARM_MATH_TEST_FAILURE;
+ }
+
+
+ /* ----------------------------------------------------------------------
+ ** Loop here if the signals fail the PASS check.
+ ** This denotes a test failure
+ ** ------------------------------------------------------------------- */
+ if ( status != ARM_MATH_SUCCESS)
+ {
+ while (1);
+ }
+
+ while (1); /* main function does not return */
+}
+
+ /** \endlink */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.c
new file mode 100644
index 0000000..f615e6f
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.c
@@ -0,0 +1,466 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.0 b
+*
+* Project: CMSIS DSP Library
+*
+* Title: math_helper.c
+*
+* Description: Definition of all helper functions required.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+/* ----------------------------------------------------------------------
+* Include standard header files
+* -------------------------------------------------------------------- */
+#include<math.h>
+
+/* ----------------------------------------------------------------------
+* Include project header files
+* -------------------------------------------------------------------- */
+#include "math_helper.h"
+
+/**
+ * @brief Caluclation of SNR
+ * @param[in] pRef Pointer to the reference buffer
+ * @param[in] pTest Pointer to the test buffer
+ * @param[in] buffSize total number of samples
+ * @return SNR
+ * The function Caluclates signal to noise ratio for the reference output
+ * and test output
+ */
+
+float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize)
+{
+ float EnergySignal = 0.0, EnergyError = 0.0;
+ uint32_t i;
+ float SNR;
+ int temp;
+ int *test;
+
+ for (i = 0; i < buffSize; i++)
+ {
+ /* Checking for a NAN value in pRef array */
+ test = (int *)(&pRef[i]);
+ temp = *test;
+
+ if (temp == 0x7FC00000)
+ {
+ return(0);
+ }
+
+ /* Checking for a NAN value in pTest array */
+ test = (int *)(&pTest[i]);
+ temp = *test;
+
+ if (temp == 0x7FC00000)
+ {
+ return(0);
+ }
+ EnergySignal += pRef[i] * pRef[i];
+ EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]);
+ }
+
+ /* Checking for a NAN value in EnergyError */
+ test = (int *)(&EnergyError);
+ temp = *test;
+
+ if (temp == 0x7FC00000)
+ {
+ return(0);
+ }
+
+
+ SNR = 10 * log10 (EnergySignal / EnergyError);
+
+ return (SNR);
+
+}
+
+
+/**
+ * @brief Provide guard bits for Input buffer
+ * @param[in,out] input_buf Pointer to input buffer
+ * @param[in] blockSize block Size
+ * @param[in] guard_bits guard bits
+ * @return none
+ * The function Provides the guard bits for the buffer
+ * to avoid overflow
+ */
+
+void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < blockSize; i++)
+ {
+ input_buf[i] = input_buf[i] >> guard_bits;
+ }
+}
+
+/**
+ * @brief Converts float to fixed in q12.20 format
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to outputbuffer
+ * @param[in] numSamples number of samples in the input buffer
+ * @return none
+ * The function converts floating point values to fixed point(q12.20) values
+ */
+
+void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 1048576.0f corresponds to pow(2, 20) */
+ pOut[i] = (q31_t) (pIn[i] * 1048576.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 1.0)
+ {
+ pOut[i] = 0x000FFFFF;
+ }
+ }
+}
+
+/**
+ * @brief Compare MATLAB Reference Output and ARM Test output
+ * @param[in] pIn Pointer to Ref buffer
+ * @param[in] pOut Pointer to Test buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return maximum difference
+ */
+
+uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t *pOut, uint32_t numSamples)
+{
+ uint32_t i;
+ int32_t diff, diffCrnt = 0;
+ uint32_t maxDiff = 0;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ diff = pIn[i] - pOut[i];
+ diffCrnt = (diff > 0) ? diff : -diff;
+
+ if (diffCrnt > maxDiff)
+ {
+ maxDiff = diffCrnt;
+ }
+ }
+
+ return(maxDiff);
+}
+
+/**
+ * @brief Compare MATLAB Reference Output and ARM Test output
+ * @param[in] pIn Pointer to Ref buffer
+ * @param[in] pOut Pointer to Test buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return maximum difference
+ */
+
+uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples)
+{
+ uint32_t i;
+ int32_t diff, diffCrnt = 0;
+ uint32_t maxDiff = 0;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ diff = pIn[i] - pOut[i];
+ diffCrnt = (diff > 0) ? diff : -diff;
+
+ if (diffCrnt > maxDiff)
+ {
+ maxDiff = diffCrnt;
+ }
+ }
+
+ return(maxDiff);
+}
+
+/**
+ * @brief Provide guard bits for Input buffer
+ * @param[in,out] input_buf Pointer to input buffer
+ * @param[in] blockSize block Size
+ * @param[in] guard_bits guard bits
+ * @return none
+ * The function Provides the guard bits for the buffer
+ * to avoid overflow
+ */
+
+void arm_provide_guard_bits_q31 (q31_t * input_buf,
+ uint32_t blockSize,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < blockSize; i++)
+ {
+ input_buf[i] = input_buf[i] >> guard_bits;
+ }
+}
+
+/**
+ * @brief Provide guard bits for Input buffer
+ * @param[in,out] input_buf Pointer to input buffer
+ * @param[in] blockSize block Size
+ * @param[in] guard_bits guard bits
+ * @return none
+ * The function Provides the guard bits for the buffer
+ * to avoid overflow
+ */
+
+void arm_provide_guard_bits_q7 (q7_t * input_buf,
+ uint32_t blockSize,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < blockSize; i++)
+ {
+ input_buf[i] = input_buf[i] >> guard_bits;
+ }
+}
+
+
+
+/**
+ * @brief Caluclates number of guard bits
+ * @param[in] num_adds number of additions
+ * @return guard bits
+ * The function Caluclates the number of guard bits
+ * depending on the numtaps
+ */
+
+uint32_t arm_calc_guard_bits (uint32_t num_adds)
+{
+ uint32_t i = 1, j = 0;
+
+ if (num_adds == 1)
+ {
+ return (0);
+ }
+
+ while (i < num_adds)
+ {
+ i = i * 2;
+ j++;
+ }
+
+ return (j);
+}
+
+/**
+ * @brief Apply guard bits to buffer
+ * @param[in,out] pIn pointer to input buffer
+ * @param[in] numSamples number of samples in the input buffer
+ * @param[in] guard_bits guard bits
+ * @return none
+ */
+
+void arm_apply_guard_bits (float32_t *pIn,
+ uint32_t numSamples,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ pIn[i] = pIn[i] * arm_calc_2pow(guard_bits);
+ }
+}
+
+/**
+ * @brief Calculates pow(2, numShifts)
+ * @param[in] numShifts number of shifts
+ * @return pow(2, numShifts)
+ */
+uint32_t arm_calc_2pow(uint32_t numShifts)
+{
+
+ uint32_t i, val = 1;
+
+ for (i = 0; i < numShifts; i++)
+ {
+ val = val * 2;
+ }
+
+ return(val);
+}
+
+
+
+/**
+ * @brief Converts float to fixed q14
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to output buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 16384.0f corresponds to pow(2, 14) */
+ pOut[i] = (q15_t) (pIn[i] * 16384.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 2.0)
+ {
+ pOut[i] = 0x7FFF;
+ }
+
+ }
+
+}
+
+
+/**
+ * @brief Converts float to fixed q30 format
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to output buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q30 (float *pIn, q31_t * pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 1073741824.0f corresponds to pow(2, 30) */
+ pOut[i] = (q31_t) (pIn[i] * 1073741824.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 2.0)
+ {
+ pOut[i] = 0x7FFFFFFF;
+ }
+ }
+}
+
+/**
+ * @brief Converts float to fixed q30 format
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to output buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 1073741824.0f corresponds to pow(2, 30) */
+ pOut[i] = (q31_t) (pIn[i] * 536870912.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 4.0)
+ {
+ pOut[i] = 0x7FFFFFFF;
+ }
+ }
+}
+
+
+/**
+ * @brief Converts float to fixed q28 format
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to output buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 268435456.0f corresponds to pow(2, 28) */
+ pOut[i] = (q31_t) (pIn[i] * 268435456.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 8.0)
+ {
+ pOut[i] = 0x7FFFFFFF;
+ }
+ }
+}
+
+/**
+ * @brief Clip the float values to +/- 1
+ * @param[in,out] pIn input buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_clip_f32 (float *pIn, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ if (pIn[i] > 1.0f)
+ {
+ pIn[i] = 1.0;
+ }
+ else if ( pIn[i] < -1.0f)
+ {
+ pIn[i] = -1.0;
+ }
+
+ }
+}
+
+
+
+
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.h
new file mode 100644
index 0000000..5a18734
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.h
@@ -0,0 +1,63 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.0
+*
+* Project: CMSIS DSP Library
+*
+* Title: math_helper.h
+*
+* Description: Prototypes of all helper functions required.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+#ifndef MATH_HELPER_H
+#define MATH_HELPER_H
+
+float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize);
+void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples);
+void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits);
+void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits);
+void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples);
+void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_clip_f32(float *pIn, uint32_t numSamples);
+uint32_t arm_calc_guard_bits(uint32_t num_adds);
+void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits);
+uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples);
+uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples);
+uint32_t arm_calc_2pow(uint32_t guard_bits);
+#endif
+
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_data.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_data.c
new file mode 100644
index 0000000..3a2337d
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_data.c
@@ -0,0 +1,269 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.0
+*
+* Project: CMSIS DSP Library
+* Title: arm_signal_converge_data.c
+*
+* Description: Test input data for Floating point LMS Norm FIR filter
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/* ----------------------------------------------------------------------
+** Test input data for Floating point LMS Norm FIR filter
+** Generated by the MATLAB randn() function
+** ------------------------------------------------------------------- */
+
+float32_t testInput_f32[1536] =
+{
+-0.432565, -1.665584, 0.125332, 0.287676, -1.146471, 1.190915, 1.189164, -0.037633,
+0.327292, 0.174639, -0.186709, 0.725791, -0.588317, 2.183186, -0.136396, 0.113931,
+1.066768, 0.059281, -0.095648, -0.832349, 0.294411, -1.336182, 0.714325, 1.623562,
+-0.691776, 0.857997, 1.254001, -1.593730, -1.440964, 0.571148, -0.399886, 0.689997,
+0.815622, 0.711908, 1.290250, 0.668601, 1.190838, -1.202457, -0.019790, -0.156717,
+-1.604086, 0.257304, -1.056473, 1.415141, -0.805090, 0.528743, 0.219321, -0.921902,
+-2.170674, -0.059188, -1.010634, 0.614463, 0.507741, 1.692430, 0.591283, -0.643595,
+0.380337, -1.009116, -0.019511, -0.048221, 0.000043, -0.317859, 1.095004, -1.873990,
+0.428183, 0.895638, 0.730957, 0.577857, 0.040314, 0.677089, 0.568900, -0.255645,
+-0.377469, -0.295887, -1.475135, -0.234004, 0.118445, 0.314809, 1.443508, -0.350975,
+0.623234, 0.799049, 0.940890, -0.992092, 0.212035, 0.237882, -1.007763, -0.742045,
+1.082295, -0.131500, 0.389880, 0.087987, -0.635465, -0.559573, 0.443653, -0.949904,
+0.781182, 0.568961, -0.821714, -0.265607, -1.187777, -2.202321, 0.986337, -0.518635,
+0.327368, 0.234057, 0.021466, -1.003944, -0.947146, -0.374429, -1.185886, -1.055903,
+1.472480, 0.055744, -1.217317, -0.041227, -1.128344, -1.349278, -0.261102, 0.953465,
+0.128644, 0.656468, -1.167819, -0.460605, -0.262440, -1.213152, -1.319437, 0.931218,
+0.011245, -0.645146, 0.805729, 0.231626, -0.989760, 1.339586, 0.289502, 1.478917,
+1.138028, -0.684139, -1.291936, -0.072926, -0.330599, -0.843628, 0.497770, 1.488490,
+-0.546476, -0.846758, -0.246337, 0.663024, -0.854197, -1.201315, -0.119869, -0.065294,
+0.485296, -0.595491, -0.149668, -0.434752, -0.079330, 1.535152, -0.606483, -1.347363,
+0.469383, -0.903567, 0.035880, -0.627531, 0.535398, 0.552884, -0.203690, -2.054325,
+0.132561, 1.592941, 1.018412, -1.580402, -0.078662, -0.681657, -1.024553, -1.234353,
+0.288807, -0.429303, 0.055801, -0.367874, -0.464973, 0.370961, 0.728283, 2.112160,
+-1.357298, -1.022610, 1.037834, -0.389800, -1.381266, 0.315543, 1.553243, 0.707894,
+1.957385, 0.504542, 1.864529, -0.339812, -1.139779, -0.211123, 1.190245, -1.116209,
+0.635274, -0.601412, 0.551185, -1.099840, 0.085991, -2.004563, -0.493088, 0.462048,
+-0.321005, 1.236556, -0.631280, -2.325211, -1.231637, 1.055648, -0.113224, 0.379224,
+0.944200, -2.120427, -0.644679, -0.704302, -1.018137, -0.182082, 1.521013, -0.038439,
+1.227448, -0.696205, 0.007524, -0.782893, 0.586939, -0.251207, 0.480136, 0.668155,
+-0.078321, 0.889173, 2.309287, 0.524639, -0.011787, 0.913141, 0.055941, -1.107070,
+0.485498, -0.005005, -0.276218, 1.276452, 1.863401, -0.522559, 0.103424, -0.807649,
+0.680439, -2.364590, 0.990115, 0.218899, 0.261662, 1.213444, -0.274667, -0.133134,
+-1.270500, -1.663606, -0.703554, 0.280880, -0.541209, -1.333531, 1.072686, -0.712085,
+-0.011286, -0.000817, -0.249436, 0.396575, -0.264013, -1.664011, -1.028975, 0.243095,
+-1.256590, -0.347183, -0.941372, -1.174560, -1.021142, -0.401667, 0.173666, -0.116118,
+1.064119, -0.245386, -1.517539, 0.009734, 0.071373, 0.316536, 0.499826, 1.278084,
+-0.547816, 0.260808, -0.013177, -0.580264, 2.136308, -0.257617, -1.409528, 1.770101,
+0.325546, -1.119040, 0.620350, 1.269782, -0.896043, 0.135175, -0.139040, -1.163395,
+1.183720, -0.015430, 0.536219, -0.716429, -0.655559, 0.314363, 0.106814, 1.848216,
+-0.275106, 2.212554, 1.508526, -1.945079, -1.680543, -0.573534, -0.185817, 0.008934,
+0.836950, -0.722271, -0.721490, -0.201181, -0.020464, 0.278890, 1.058295, 0.621673,
+-1.750615, 0.697348, 0.811486, 0.636345, 1.310080, 0.327098, -0.672993, -0.149327,
+-2.449018, 0.473286, 0.116946, -0.591104, -0.654708, -1.080662, -0.047731, 0.379345,
+-0.330361, -0.499898, -0.035979, -0.174760, -0.957265, 1.292548, 0.440910, 1.280941,
+-0.497730, -1.118717, 0.807650, 0.041200, -0.756209, -0.089129, -2.008850, 1.083918,
+-0.981191, -0.688489, 1.339479, -0.909243, -0.412858, -0.506163, 1.619748, 0.080901,
+-1.081056, -1.124518, 1.735676, 1.937459, 1.635068, -1.255940, -0.213538, -0.198932,
+0.307499, -0.572325, -0.977648, -0.446809, 1.082092, 2.372648, 0.229288, -0.266623,
+0.701672, -0.487590, 1.862480, 1.106851, -1.227566, -0.669885, 1.340929, 0.388083,
+0.393059, -1.707334, 0.227859, 0.685633, -0.636790, -1.002606, -0.185621, -1.054033,
+-0.071539, 0.279198, 1.373275, 0.179841, -0.542017, 1.634191, 0.825215, 0.230761,
+0.671634, -0.508078, 0.856352, 0.268503, 0.624975, -1.047338, 1.535670, 0.434426,
+-1.917136, 0.469940, 1.274351, 0.638542, 1.380782, 1.319843, -0.909429, -2.305605,
+1.788730, 0.390798, 0.020324, -0.405977, -1.534895, 0.221373, -1.374479, -0.839286,
+-0.208643, 0.755913, 0.375734, -1.345413, 1.481876, 0.032736, 1.870453, -1.208991,
+-0.782632, -0.767299, -0.107200, -0.977057, -0.963988, -2.379172, -0.838188, 0.257346,
+-0.183834, -0.167615, -0.116989, 0.168488, -0.501206, -0.705076, 0.508165, -0.420922,
+0.229133, -0.959497, -0.146043, 0.744538, -0.890496, 0.139062, -0.236144, -0.075459,
+-0.358572, -2.077635, -0.143546, 1.393341, 0.651804, -0.377134, -0.661443, 0.248958,
+-0.383516, -0.528480, 0.055388, 1.253769, -2.520004, 0.584856, -1.008064, 0.944285,
+-2.423957, -0.223831, 0.058070, -0.424614, -0.202918, -1.513077, -1.126352, -0.815002,
+0.366614, -0.586107, 1.537409, 0.140072, -1.862767, -0.454193, -0.652074, 0.103318,
+-0.220632, -0.279043, -0.733662, -0.064534, -1.444004, 0.612340, -1.323503, -0.661577,
+-0.146115, 0.248085, -0.076633, 1.738170, 1.621972, 0.626436, 0.091814, -0.807607,
+-0.461337, -1.405969, -0.374530, -0.470911, 1.751296, 0.753225, 0.064989, -0.292764,
+0.082823, 0.766191, 2.236850, 0.326887, 0.863304, 0.679387, 0.554758, 1.001630,
+1.259365, 0.044151, -0.314138, 0.226708, 0.996692, 1.215912, -0.542702, 0.912228,
+-0.172141, -0.335955, 0.541487, 0.932111, -0.570253, -1.498605, -0.050346, 0.553025,
+0.083498, 1.577524, -0.330774, 0.795155, -0.784800, -1.263121, 0.666655, -1.392632,
+-1.300562, -0.605022, -1.488565, 0.558543, -0.277354, -1.293685, -0.888435, -0.986520,
+-0.071618, -2.414591, -0.694349, -1.391389, 0.329648, 0.598544, 0.147175, -0.101439,
+-2.634981, 0.028053, -0.876310, -0.265477, -0.327578, -1.158247, 0.580053, 0.239756,
+-0.350885, 0.892098, 1.578299, -1.108174, -0.025931, -1.110628, 0.750834, 0.500167,
+-0.517261, -0.559209, -0.753371, 0.925813, -0.248520, -0.149835, -1.258415, 0.312620,
+2.690277, 0.289696, -1.422803, 0.246786, -1.435773, 0.148573, -1.693073, 0.719188,
+1.141773, 1.551936, 1.383630, -0.758092, 0.442663, 0.911098, -1.074086, 0.201762,
+0.762863, -1.288187, -0.952962, 0.778175, -0.006331, 0.524487, 1.364272, 0.482039,
+-0.787066, 0.751999, -0.166888, -0.816228, 2.094065, 0.080153, -0.937295, 0.635739,
+1.682028, 0.593634, 0.790153, 0.105254, -0.158579, 0.870907, -0.194759, 0.075474,
+-0.526635, -0.685484, -0.268388, -1.188346, 0.248579, 0.102452, -0.041007, -2.247582,
+-0.510776, 0.249243, 0.369197, 0.179197, -0.037283, -1.603310, 0.339372, -0.131135,
+0.485190, 0.598751, -0.086031, 0.325292, -0.335143, -0.322449, -0.382374, -0.953371,
+0.233576, 1.235245, -0.578532, -0.501537, 0.722864, 0.039498, 1.541279, -1.701053,
+-1.033741, -0.763708, 2.176426, 0.431612, -0.443765, 0.029996, -0.315671, 0.977846,
+0.018295, 0.817963, 0.702341, -0.231271, -0.113690, 0.127941, -0.799410, -0.238612,
+-0.089463, -1.023264, 0.937538, -1.131719, -0.710702, -1.169501, 1.065437, -0.680394,
+-1.725773, 0.813200, 1.441867, 0.672272, 0.138665, -0.859534, -0.752251, 1.229615,
+1.150754, -0.608025, 0.806158, 0.217133, -0.373461, -0.832030, 0.286866, -1.818892,
+-1.573051, 2.015666, -0.071982, 2.628909, -0.243317, 0.173276, 0.923207, -0.178553,
+-0.521705, 1.431962, -0.870117, 0.807542, -0.510635, 0.743514, 0.847898, -0.829901,
+0.532994, 1.032848, -1.052024, 0.362114, -0.036787, -1.227636, -0.275099, -0.160435,
+-1.083575, -1.954213, -0.909487, -0.005579, -1.723490, 1.263077, -0.600433, -2.063925,
+0.110911, 1.487614, 0.053002, 0.161981, -0.026878, 0.173576, 0.882168, 0.182294,
+0.755295, 0.508035, 0.131880, 0.280104, -0.982848, -0.944087, -0.013058, 0.354345,
+-0.894709, 0.812111, 0.109537, 2.731644, 0.411079, -1.306862, 0.383806, 0.499504,
+-0.510786, 0.234922, -0.597825, 0.020771, 0.419443, 1.191104, 0.771214, -2.644222,
+0.285430, 0.826093, -0.008122, 0.858438, 0.774788, 1.305945, 1.231503, 0.958564,
+-1.654548, -0.990396, 0.685236, -0.974870, -0.606726, 0.686794, 0.020049, 1.063801,
+-1.341050, 0.479510, -1.633974, -1.442665, 0.293781, -0.140364, -1.130341, -0.292538,
+-0.582536, -0.896348, 0.248601, -1.489663, 0.313509, -2.025084, 0.528990, 0.343471,
+0.758193, -0.691940, 0.680179, -1.072541, 0.899772, -2.123092, 0.284712, -0.733323,
+-0.773376, 0.151842, -0.336843, 0.970761, -0.107236, 1.013492, -0.475347, 0.068948,
+0.398592, 1.116326, 0.620451, -0.287674, -1.371773, -0.685868, 0.331685, -0.997722,
+0.291418, 1.107078, 0.244959, 0.164976, 0.406231, 1.215981, 1.448424, -1.025137,
+0.205418, 0.588882, -0.264024, 2.495318, 0.855948, -0.850954, 0.811879, 0.700242,
+0.759938, -1.712909, 1.537021, -1.609847, 1.109526, -1.109704, 0.385469, 0.965231,
+0.818297, 0.037049, -0.926012, -0.111919, -0.803030, -1.665006, -0.901401, 0.588350,
+0.554159, -0.415173, 0.061795, 0.457432, 0.199014, 0.257558, 2.080730, -2.277237,
+0.339022, 0.289894, 0.662261, -0.580860, 0.887752, 0.171871, 0.848821, 0.963769,
+1.321918, -0.064345, 1.317053, 0.228017, -1.429637, -0.149701, -0.504968, -1.729141,
+-0.417472, -0.614969, 0.720777, 0.339364, 0.882845, 0.284245, -0.145541, -0.089646,
+0.289161, 1.164831, 0.805729, -1.355643, 0.120893, -0.222178, 0.571732, -0.300140,
+1.134277, -0.179356, -1.467067, 1.395346, 0.440836, 0.565384, -0.693623, 0.833869,
+-2.237378, 1.097644, -0.001617, -1.614573, -1.228727, 0.207405, 0.220942, -1.006073,
+-0.453067, 1.399453, -0.461964, 0.032716, 0.798783, 0.896816, 0.137892, -1.619146,
+-1.646606, 0.428707, -0.737231, 0.564926, -1.384167, 0.460268, 0.629384, 0.379847,
+-1.013330, -0.347243, 0.441912, -1.590240, -0.701417, -1.077601, 1.002220, 1.729481,
+0.709032, -0.747897, 0.228862, -0.223497, -0.853275, 0.345627, 0.109764, -1.133039,
+-0.683124, -0.277856, 0.654790, -1.248394, -0.597539, -0.481813, 0.983372, 1.762121,
+1.427402, 0.911763, 0.326823, 0.069619, -1.499763, -0.418223, -0.021037, 0.228425,
+-1.008196, -0.664622, 0.558177, -1.188542, -0.775481, 0.271042, 1.534976, -1.052283,
+0.625559, -0.797626, -0.313522, -0.602210, 1.259060, 0.858484, -2.105292, -0.360937,
+0.553557, -1.556384, -0.206666, -0.425568, 0.493778, -0.870908, 0.079828, -0.521619,
+-1.413861, -0.384293, -0.457922, -0.291471, -0.301224, -1.588594, 1.094287, 1.324167,
+-0.126480, -0.737164, 0.213719, -0.400529, 0.064938, -1.757996, 1.686748, 0.327400,
+0.715967, 1.598648, -2.064741, -0.743632, 0.176185, 0.527839, -0.553153, 0.298280,
+-1.226607, -0.189676, -0.301713, 0.956956, -0.533366, -0.901082, -0.892552, 0.278717,
+-0.745807, 1.603464, 0.574270, 0.320655, -0.151383, 0.315762, 1.343703, -2.237832,
+1.292906, -0.378459, 0.002521, 0.884641, 0.582450, -1.614244, -1.503666, 0.573586,
+-0.910537, -1.631277, -0.359138, -0.397616, -1.161307, -1.109838, 0.290672, -1.910239,
+1.314768, 0.665319, -0.275115, -0.023022, -0.907976, -1.043657, 0.373516, 0.901532,
+1.278539, -0.128456, 0.612821, 1.956518, 2.266326, -0.373959, 2.238039, -0.159580,
+-0.703281, 0.563477, -0.050296, 1.163593, 0.658808, -1.550089, -3.029118, 0.540578,
+-1.008998, 0.908047, 1.582303, -0.979088, 1.007902, 0.158491, -0.586927, 1.574082,
+-0.516649, 1.227800, 1.583876, -2.088950, 2.949545, 1.356125, 1.050068, -0.767170,
+-0.257653, -1.371845, -1.267656, -0.894948, 0.589089, 1.842629, 1.347967, -0.491253,
+-2.177568, 0.237000, -0.735411, -1.779419, 0.448030, 0.581214, 0.856607, -0.266263,
+-0.417470, -0.205806, -0.174323, 0.217577, 1.684295, 0.119528, 0.650667, 2.080061,
+-0.339225, 0.730113, 0.293969, -0.849109, -2.533858, -2.378941, -0.346276, -0.610937,
+-0.408192, -1.415611, 0.227122, 0.207974, -0.719718, 0.757762, -1.643135, -1.056813,
+-0.251662, -1.298441, 1.233255, 1.494625, 0.235938, -1.404359, 0.658791, -2.556613,
+-0.534945, 3.202525, 0.439198, -1.149901, 0.886765, -0.283386, 1.035336, -0.364878,
+1.341987, 1.008872, 0.213874, -0.299264, 0.255849, -0.190826, -0.079060, 0.699851,
+-0.796540, -0.801284, -0.007599, -0.726810, -1.490902, 0.870335, -0.265675, -1.566695,
+-0.394636, -0.143855, -2.334247, -1.357539, -1.815689, 1.108422, -0.142115, 1.112757,
+0.559264, 0.478370, -0.679385, 0.284967, -1.332935, -0.723980, -0.663600, 0.198443,
+-1.794868, -1.387673, 0.197768, 1.469328, 0.366493, -0.442775, -0.048563, 0.077709,
+1.957910, -0.072848, 0.938810, -0.079608, -0.800959, 0.309424, 1.051826, -1.664211,
+-1.090792, -0.191731, 0.463401, -0.924147, -0.649657, 0.622893, -1.335107, 1.047689,
+0.863327, -0.642411, 0.660010, 1.294116, 0.314579, 0.859573, 0.128670, 0.016568,
+-0.072801, -0.994310, -0.747358, -0.030814, 0.988355, -0.599017, 1.476644, -0.813801,
+0.645040, -1.309919, -0.867425, -0.474233, 0.222417, 1.871323, 0.110001, -0.411341,
+0.511242, -1.199117, -0.096361, 0.445817, -0.295825, -0.167996, 0.179543, 0.421118,
+1.677678, 1.996949, 0.696964, -1.366382, 0.363045, -0.567044, -1.044154, 0.697139,
+0.484026, -0.193751, -0.378095, -0.886374, -1.840197, -1.628195, -1.173789, -0.415411,
+0.175088, 0.229433, -1.240889, 0.700004, 0.426877, 1.454803, -0.510186, -0.006657,
+-0.525496, 0.717698, 1.088374, 0.500552, 2.771790, -0.160309, 0.429489, -1.966817,
+-0.546019, -1.888395, -0.107952, -1.316144, -0.672632, -0.902365, -0.154798, 0.947242,
+1.550375, 0.429040, -0.560795, 0.179304, -0.771509, -0.943390, -1.407569, -1.906131,
+-0.065293, 0.672149, 0.206147, -0.008124, 0.020042, -0.558447, 1.886079, -0.219975,
+-1.414395, -0.302811, -0.569574, -0.121495, -0.390171, -0.844287, -1.737757, -0.449520,
+-1.547933, -0.095776, 0.907714, 2.369602, 0.519768, 0.410525, 1.052585, 0.428784,
+1.295088, -0.186053, 0.130733, -0.657627, -0.759267, -0.595170, 0.812400, 0.069541,
+-1.833687, 1.827363, 0.654075, -1.544769, -0.375109, 0.207688, -0.765615, -0.106355,
+0.338769, 1.033461, -1.404822, -1.030570, -0.643372, 0.170787, 1.344839, 1.936273,
+0.741336, 0.811980, -0.142808, -0.099858, -0.800131, 0.493249, 1.237574, 1.295951,
+-0.278196, 0.217127, 0.630728, -0.548549, 0.229632, 0.355311, 0.521284, -0.615971,
+1.345803, 0.974922, -2.377934, -1.092319, -0.325710, -2.012228, 1.567660, 0.233337,
+0.646420, -1.129412, 0.197038, 1.696870, 0.726034, 0.792526, 0.603357, -0.058405,
+-1.108666, 2.144229, -1.352821, 0.457021, 0.391175, 2.073013, -0.323318, 1.468132,
+-0.502399, 0.209593, 0.754800, -0.948189, 0.613157, 1.760503, 0.088762, 2.595570,
+-0.675470, 2.786804, -0.016827, 0.271651, -0.914102, -1.951371, -0.317418, 0.588333,
+0.828996, -1.674851, -1.922293, -0.436662, 0.044974, 2.416609, -0.309892, 0.187583,
+0.947699, -0.525703, -1.115605, -1.592320, 1.174844, 0.485144, 1.645480, -0.454233,
+1.008768, 2.049403, 0.602020, 0.017860, -1.610426, 1.238752, 0.683587, -0.780716,
+0.530979, 2.134498, 0.354361, 0.231700, 1.287980, -0.013488, -1.333345, -0.556343,
+0.755597, -0.911854, 1.371684, 0.245580, 0.118845, 0.384690, -0.070152, -0.578309,
+0.469308, 1.299687, 1.634798, -0.702809, 0.807253, -1.027451, 1.294496, 0.014930,
+0.218705, 1.713188, -2.078805, 0.112917, -1.086491, -1.558311, 0.637406, -0.404576,
+-0.403325, 0.084076, -0.435349, -0.562623, 0.878062, -0.814650, -0.258363, 0.493299,
+-0.802694, -0.008329, 0.627571, 0.154382, 2.580735, -1.306246, 1.023526, 0.777795,
+-0.833884, -0.586663, 0.065664, -0.012342, -0.076987, -1.558587, 1.702607, -0.468984,
+0.094619, 0.287071, 0.919354, 0.510136, 0.245440, -1.400519, 0.969571, 1.593698,
+-1.437917, -1.534230, -0.074710, 0.081459, -0.843240, -0.564640, -0.028207, -1.243702,
+0.733039, 0.059580, 0.149144, 1.595857, -0.777250, 1.550277, 1.055002, -0.166654,
+0.314484, 1.419571, 0.327348, 0.475653, 0.398754, -0.072770, 1.314784, 0.978279,
+1.722114, -0.412302, 0.565133, 0.739851, 0.220138, 1.312807, 0.629152, -1.107987,
+-0.447001, -0.725993, 0.354045, -0.506772, -2.103747, -0.664684, 1.450110, -0.329805,
+2.701872, -1.634939, -0.536325, 0.547223, 1.492603, -0.455243, -0.496416, 1.235260,
+0.040926, 0.748467, 1.230764, 0.304903, 1.077771, 0.765151, -1.319580, -0.509191,
+0.555116, -1.957625, -0.760453, -2.443886, -0.659366, -0.114779, 0.300079, -0.583996,
+-3.073745, 1.551042, -0.407369, 1.428095, -1.353242, 0.903970, 0.541671, -0.465020
+};
+
+
+
+/* ----------------------------------------------------------------------
+** Coefficients for 32-tap filter for Floating point LMS FIR filter
+* FIR high pass filter with cutoff freq 9.6kHz (transition 9.6KHz to 11.52KHz)
+** ------------------------------------------------------------------- */
+float32_t lmsNormCoeff_f32[32] = {
+-0.004240, 0.002301, 0.008860, -0.000000, -0.019782, -0.010543, 0.032881, 0.034736,
+-0.037374, -0.069586, 0.022397, 0.102169, 0.014185, -0.115908, -0.061648, 0.101018,
+0.101018, -0.061648, -0.115908, 0.014185, 0.102169, 0.022397, -0.069586, -0.037374,
+0.034736, 0.032881, -0.010543, -0.019782, -0.000000, 0.008860, 0.002301, -0.004240
+
+};
+
+/* ----------------------------------------------------------------------
+** Coefficients for 32-tap filter for Floating point FIR filter
+* FIR low pass filter with cutoff freq 24Hz (transition 24Hz to 240Hz)
+** ------------------------------------------------------------------- */
+const float32_t FIRCoeff_f32[32] = {
+0.004502, 0.005074, 0.006707, 0.009356, 0.012933, 0.017303, 0.022298, 0.027717,
+0.033338, 0.038930, 0.044258, 0.049098, 0.053243, 0.056519, 0.058784, 0.059941,
+0.059941, 0.058784, 0.056519, 0.053243, 0.049098, 0.044258, 0.038930, 0.033338,
+0.027717, 0.022298, 0.017303, 0.012933, 0.009356, 0.006707, 0.005074, 0.004502
+
+};
+
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_example_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_example_f32.c
new file mode 100644
index 0000000..d984e2f
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_example_f32.c
@@ -0,0 +1,259 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.0
+*
+* Project: CMSIS DSP Library
+* Title: arm_signal_converge_example_f32.c
+*
+* Description: Example code demonstrating convergence of an adaptive
+* filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+ * @ingroup groupExamples
+ */
+
+/**
+ * @defgroup SignalConvergence Signal Convergence Example
+ *
+ * \par Description:
+ * \par
+ * Demonstrates the ability of an adaptive filter to "learn" the transfer function of
+ * a FIR lowpass filter using the Normalized LMS Filter, Finite Impulse
+ * Response (FIR) Filter, and Basic Math Functions.
+ *
+ * \par Algorithm:
+ * \par
+ * The figure below illustrates the signal flow in this example. Uniformly distributed white
+ * noise is passed through an FIR lowpass filter. The output of the FIR filter serves as the
+ * reference input of the adaptive filter (normalized LMS filter). The white noise is input
+ * to the adaptive filter. The adaptive filter learns the transfer function of the FIR filter.
+ * The filter outputs two signals: (1) the output of the internal adaptive FIR filter, and
+ * (2) the error signal which is the difference between the adaptive filter and the reference
+ * output of the FIR filter. Over time as the adaptive filter learns the transfer function
+ * of the FIR filter, the first output approaches the reference output of the FIR filter,
+ * and the error signal approaches zero.
+ * \par
+ * The adaptive filter converges properly even if the input signal has a large dynamic
+ * range (i.e., varies from small to large values). The coefficients of the adaptive filter
+ * are initially zero, and then converge over 1536 samples. The internal function test_signal_converge()
+ * implements the stopping condition. The function checks if all of the values of the error signal have a
+ * magnitude below a threshold DELTA.
+ *
+ * \par Block Diagram:
+ * \par
+ * \image html SignalFlow.gif
+ *
+ *
+ * \par Variables Description:
+ * \par
+ * \li \c testInput_f32 points to the input data
+ * \li \c firStateF32 points to FIR state buffer
+ * \li \c lmsStateF32 points to Normalised Least mean square FIR filter state buffer
+ * \li \c FIRCoeff_f32 points to coefficient buffer
+ * \li \c lmsNormCoeff_f32 points to Normalised Least mean square FIR filter coefficient buffer
+ * \li \c wire1, wir2, wire3 temporary buffers
+ * \li \c errOutput, err_signal temporary error buffers
+ *
+ * \par CMSIS DSP Software Library Functions Used:
+ * \par
+ * - arm_lms_norm_init_f32()
+ * - arm_fir_init_f32()
+ * - arm_fir_f32()
+ * - arm_lms_norm_f32()
+ * - arm_scale_f32()
+ * - arm_abs_f32()
+ * - arm_sub_f32()
+ * - arm_min_f32()
+ * - arm_copy_f32()
+ *
+ * <b> Refer </b>
+ * \link arm_signal_converge_example_f32.c \endlink
+ *
+ */
+
+
+/** \example arm_signal_converge_example_f32.c
+ */
+
+#include "arm_math.h"
+#include "math_helper.h"
+
+/* ----------------------------------------------------------------------
+** Global defines for the simulation
+* ------------------------------------------------------------------- */
+
+#define TEST_LENGTH_SAMPLES 1536
+#define NUMTAPS 32
+#define BLOCKSIZE 32
+#define DELTA_ERROR 0.000001f
+#define DELTA_COEFF 0.0001f
+#define MU 0.5f
+
+#define NUMFRAMES (TEST_LENGTH_SAMPLES / BLOCKSIZE)
+
+/* ----------------------------------------------------------------------
+* Declare FIR state buffers and structure
+* ------------------------------------------------------------------- */
+
+float32_t firStateF32[NUMTAPS + BLOCKSIZE];
+arm_fir_instance_f32 LPF_instance;
+
+/* ----------------------------------------------------------------------
+* Declare LMSNorm state buffers and structure
+* ------------------------------------------------------------------- */
+
+float32_t lmsStateF32[NUMTAPS + BLOCKSIZE];
+float32_t errOutput[TEST_LENGTH_SAMPLES];
+arm_lms_norm_instance_f32 lmsNorm_instance;
+
+
+/* ----------------------------------------------------------------------
+* Function Declarations for Signal Convergence Example
+* ------------------------------------------------------------------- */
+
+arm_status test_signal_converge_example( void );
+
+
+/* ----------------------------------------------------------------------
+* Internal functions
+* ------------------------------------------------------------------- */
+arm_status test_signal_converge(float32_t* err_signal,
+ uint32_t blockSize);
+
+void getinput(float32_t* input,
+ uint32_t fr_cnt,
+ uint32_t blockSize);
+
+/* ----------------------------------------------------------------------
+* External Declarations for FIR F32 module Test
+* ------------------------------------------------------------------- */
+extern float32_t testInput_f32[TEST_LENGTH_SAMPLES];
+extern float32_t lmsNormCoeff_f32[32];
+extern const float32_t FIRCoeff_f32[32];
+extern arm_lms_norm_instance_f32 lmsNorm_instance;
+
+/* ----------------------------------------------------------------------
+* Declare I/O buffers
+* ------------------------------------------------------------------- */
+
+float32_t wire1[BLOCKSIZE];
+float32_t wire2[BLOCKSIZE];
+float32_t wire3[BLOCKSIZE];
+float32_t err_signal[BLOCKSIZE];
+
+/* ----------------------------------------------------------------------
+* Signal converge test
+* ------------------------------------------------------------------- */
+
+int32_t main(void)
+{
+ uint32_t i;
+ arm_status status;
+ uint32_t index;
+ float32_t minValue;
+
+ /* Initialize the LMSNorm data structure */
+ arm_lms_norm_init_f32(&lmsNorm_instance, NUMTAPS, lmsNormCoeff_f32, lmsStateF32, MU, BLOCKSIZE);
+
+ /* Initialize the FIR data structure */
+ arm_fir_init_f32(&LPF_instance, NUMTAPS, (float32_t *)FIRCoeff_f32, firStateF32, BLOCKSIZE);
+
+ /* ----------------------------------------------------------------------
+ * Loop over the frames of data and execute each of the processing
+ * functions in the system.
+ * ------------------------------------------------------------------- */
+
+ for(i=0; i < NUMFRAMES; i++)
+ {
+ /* Read the input data - uniformly distributed random noise - into wire1 */
+ arm_copy_f32(testInput_f32 + (i * BLOCKSIZE), wire1, BLOCKSIZE);
+
+ /* Execute the FIR processing function. Input wire1 and output wire2 */
+ arm_fir_f32(&LPF_instance, wire1, wire2, BLOCKSIZE);
+
+ /* Execute the LMS Norm processing function*/
+
+ arm_lms_norm_f32(&lmsNorm_instance, /* LMSNorm instance */
+ wire1, /* Input signal */
+ wire2, /* Reference Signal */
+ wire3, /* Converged Signal */
+ err_signal, /* Error Signal, this will become small as the signal converges */
+ BLOCKSIZE); /* BlockSize */
+
+ /* apply overall gain */
+ arm_scale_f32(wire3, 5, wire3, BLOCKSIZE); /* in-place buffer */
+ }
+
+ status = ARM_MATH_SUCCESS;
+
+ /* -------------------------------------------------------------------------------
+ * Test whether the error signal has reached towards 0.
+ * ----------------------------------------------------------------------------- */
+
+ arm_abs_f32(err_signal, err_signal, BLOCKSIZE);
+ arm_min_f32(err_signal, BLOCKSIZE, &minValue, &index);
+
+ if (minValue > DELTA_ERROR)
+ {
+ status = ARM_MATH_TEST_FAILURE;
+ }
+
+ /* ----------------------------------------------------------------------
+ * Test whether the filter coefficients have converged.
+ * ------------------------------------------------------------------- */
+
+ arm_sub_f32((float32_t *)FIRCoeff_f32, lmsNormCoeff_f32, lmsNormCoeff_f32, NUMTAPS);
+
+ arm_abs_f32(lmsNormCoeff_f32, lmsNormCoeff_f32, NUMTAPS);
+ arm_min_f32(lmsNormCoeff_f32, NUMTAPS, &minValue, &index);
+
+ if (minValue > DELTA_COEFF)
+ {
+ status = ARM_MATH_TEST_FAILURE;
+ }
+
+ /* ----------------------------------------------------------------------
+ * Loop here if the signals did not pass the convergence check.
+ * This denotes a test failure
+ * ------------------------------------------------------------------- */
+
+ if ( status != ARM_MATH_SUCCESS)
+ {
+ while (1);
+ }
+
+ while (1); /* main function does not return */
+}
+
+ /** \endlink */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.c
new file mode 100644
index 0000000..f615e6f
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.c
@@ -0,0 +1,466 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.0 b
+*
+* Project: CMSIS DSP Library
+*
+* Title: math_helper.c
+*
+* Description: Definition of all helper functions required.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+/* ----------------------------------------------------------------------
+* Include standard header files
+* -------------------------------------------------------------------- */
+#include<math.h>
+
+/* ----------------------------------------------------------------------
+* Include project header files
+* -------------------------------------------------------------------- */
+#include "math_helper.h"
+
+/**
+ * @brief Caluclation of SNR
+ * @param[in] pRef Pointer to the reference buffer
+ * @param[in] pTest Pointer to the test buffer
+ * @param[in] buffSize total number of samples
+ * @return SNR
+ * The function Caluclates signal to noise ratio for the reference output
+ * and test output
+ */
+
+float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize)
+{
+ float EnergySignal = 0.0, EnergyError = 0.0;
+ uint32_t i;
+ float SNR;
+ int temp;
+ int *test;
+
+ for (i = 0; i < buffSize; i++)
+ {
+ /* Checking for a NAN value in pRef array */
+ test = (int *)(&pRef[i]);
+ temp = *test;
+
+ if (temp == 0x7FC00000)
+ {
+ return(0);
+ }
+
+ /* Checking for a NAN value in pTest array */
+ test = (int *)(&pTest[i]);
+ temp = *test;
+
+ if (temp == 0x7FC00000)
+ {
+ return(0);
+ }
+ EnergySignal += pRef[i] * pRef[i];
+ EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]);
+ }
+
+ /* Checking for a NAN value in EnergyError */
+ test = (int *)(&EnergyError);
+ temp = *test;
+
+ if (temp == 0x7FC00000)
+ {
+ return(0);
+ }
+
+
+ SNR = 10 * log10 (EnergySignal / EnergyError);
+
+ return (SNR);
+
+}
+
+
+/**
+ * @brief Provide guard bits for Input buffer
+ * @param[in,out] input_buf Pointer to input buffer
+ * @param[in] blockSize block Size
+ * @param[in] guard_bits guard bits
+ * @return none
+ * The function Provides the guard bits for the buffer
+ * to avoid overflow
+ */
+
+void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < blockSize; i++)
+ {
+ input_buf[i] = input_buf[i] >> guard_bits;
+ }
+}
+
+/**
+ * @brief Converts float to fixed in q12.20 format
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to outputbuffer
+ * @param[in] numSamples number of samples in the input buffer
+ * @return none
+ * The function converts floating point values to fixed point(q12.20) values
+ */
+
+void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 1048576.0f corresponds to pow(2, 20) */
+ pOut[i] = (q31_t) (pIn[i] * 1048576.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 1.0)
+ {
+ pOut[i] = 0x000FFFFF;
+ }
+ }
+}
+
+/**
+ * @brief Compare MATLAB Reference Output and ARM Test output
+ * @param[in] pIn Pointer to Ref buffer
+ * @param[in] pOut Pointer to Test buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return maximum difference
+ */
+
+uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t *pOut, uint32_t numSamples)
+{
+ uint32_t i;
+ int32_t diff, diffCrnt = 0;
+ uint32_t maxDiff = 0;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ diff = pIn[i] - pOut[i];
+ diffCrnt = (diff > 0) ? diff : -diff;
+
+ if (diffCrnt > maxDiff)
+ {
+ maxDiff = diffCrnt;
+ }
+ }
+
+ return(maxDiff);
+}
+
+/**
+ * @brief Compare MATLAB Reference Output and ARM Test output
+ * @param[in] pIn Pointer to Ref buffer
+ * @param[in] pOut Pointer to Test buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return maximum difference
+ */
+
+uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples)
+{
+ uint32_t i;
+ int32_t diff, diffCrnt = 0;
+ uint32_t maxDiff = 0;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ diff = pIn[i] - pOut[i];
+ diffCrnt = (diff > 0) ? diff : -diff;
+
+ if (diffCrnt > maxDiff)
+ {
+ maxDiff = diffCrnt;
+ }
+ }
+
+ return(maxDiff);
+}
+
+/**
+ * @brief Provide guard bits for Input buffer
+ * @param[in,out] input_buf Pointer to input buffer
+ * @param[in] blockSize block Size
+ * @param[in] guard_bits guard bits
+ * @return none
+ * The function Provides the guard bits for the buffer
+ * to avoid overflow
+ */
+
+void arm_provide_guard_bits_q31 (q31_t * input_buf,
+ uint32_t blockSize,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < blockSize; i++)
+ {
+ input_buf[i] = input_buf[i] >> guard_bits;
+ }
+}
+
+/**
+ * @brief Provide guard bits for Input buffer
+ * @param[in,out] input_buf Pointer to input buffer
+ * @param[in] blockSize block Size
+ * @param[in] guard_bits guard bits
+ * @return none
+ * The function Provides the guard bits for the buffer
+ * to avoid overflow
+ */
+
+void arm_provide_guard_bits_q7 (q7_t * input_buf,
+ uint32_t blockSize,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < blockSize; i++)
+ {
+ input_buf[i] = input_buf[i] >> guard_bits;
+ }
+}
+
+
+
+/**
+ * @brief Caluclates number of guard bits
+ * @param[in] num_adds number of additions
+ * @return guard bits
+ * The function Caluclates the number of guard bits
+ * depending on the numtaps
+ */
+
+uint32_t arm_calc_guard_bits (uint32_t num_adds)
+{
+ uint32_t i = 1, j = 0;
+
+ if (num_adds == 1)
+ {
+ return (0);
+ }
+
+ while (i < num_adds)
+ {
+ i = i * 2;
+ j++;
+ }
+
+ return (j);
+}
+
+/**
+ * @brief Apply guard bits to buffer
+ * @param[in,out] pIn pointer to input buffer
+ * @param[in] numSamples number of samples in the input buffer
+ * @param[in] guard_bits guard bits
+ * @return none
+ */
+
+void arm_apply_guard_bits (float32_t *pIn,
+ uint32_t numSamples,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ pIn[i] = pIn[i] * arm_calc_2pow(guard_bits);
+ }
+}
+
+/**
+ * @brief Calculates pow(2, numShifts)
+ * @param[in] numShifts number of shifts
+ * @return pow(2, numShifts)
+ */
+uint32_t arm_calc_2pow(uint32_t numShifts)
+{
+
+ uint32_t i, val = 1;
+
+ for (i = 0; i < numShifts; i++)
+ {
+ val = val * 2;
+ }
+
+ return(val);
+}
+
+
+
+/**
+ * @brief Converts float to fixed q14
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to output buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 16384.0f corresponds to pow(2, 14) */
+ pOut[i] = (q15_t) (pIn[i] * 16384.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 2.0)
+ {
+ pOut[i] = 0x7FFF;
+ }
+
+ }
+
+}
+
+
+/**
+ * @brief Converts float to fixed q30 format
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to output buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q30 (float *pIn, q31_t * pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 1073741824.0f corresponds to pow(2, 30) */
+ pOut[i] = (q31_t) (pIn[i] * 1073741824.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 2.0)
+ {
+ pOut[i] = 0x7FFFFFFF;
+ }
+ }
+}
+
+/**
+ * @brief Converts float to fixed q30 format
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to output buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 1073741824.0f corresponds to pow(2, 30) */
+ pOut[i] = (q31_t) (pIn[i] * 536870912.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 4.0)
+ {
+ pOut[i] = 0x7FFFFFFF;
+ }
+ }
+}
+
+
+/**
+ * @brief Converts float to fixed q28 format
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to output buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 268435456.0f corresponds to pow(2, 28) */
+ pOut[i] = (q31_t) (pIn[i] * 268435456.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 8.0)
+ {
+ pOut[i] = 0x7FFFFFFF;
+ }
+ }
+}
+
+/**
+ * @brief Clip the float values to +/- 1
+ * @param[in,out] pIn input buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_clip_f32 (float *pIn, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ if (pIn[i] > 1.0f)
+ {
+ pIn[i] = 1.0;
+ }
+ else if ( pIn[i] < -1.0f)
+ {
+ pIn[i] = -1.0;
+ }
+
+ }
+}
+
+
+
+
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.h
new file mode 100644
index 0000000..5a18734
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.h
@@ -0,0 +1,63 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.0
+*
+* Project: CMSIS DSP Library
+*
+* Title: math_helper.h
+*
+* Description: Prototypes of all helper functions required.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+#ifndef MATH_HELPER_H
+#define MATH_HELPER_H
+
+float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize);
+void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples);
+void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits);
+void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits);
+void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples);
+void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_clip_f32(float *pIn, uint32_t numSamples);
+uint32_t arm_calc_guard_bits(uint32_t num_adds);
+void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits);
+uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples);
+uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples);
+uint32_t arm_calc_2pow(uint32_t guard_bits);
+#endif
+
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/arm_sin_cos_example_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/arm_sin_cos_example_f32.c
new file mode 100644
index 0000000..7e2eb00
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/arm_sin_cos_example_f32.c
@@ -0,0 +1,161 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+*
+* $Date: 12. March 2014
+* $Revision: V1.4.3
+*
+* Project: CMSIS DSP Library
+* Title: arm_sin_cos_example_f32.c
+*
+* Description: Example code demonstrating sin and cos calculation of input signal.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+/**
+ * @ingroup groupExamples
+ */
+
+/**
+ * @defgroup SinCosExample SineCosine Example
+ *
+ * \par Description:
+ * \par
+ * Demonstrates the Pythagorean trignometric identity with the use of Cosine, Sine, Vector
+ * Multiplication, and Vector Addition functions.
+ *
+ * \par Algorithm:
+ * \par
+ * Mathematically, the Pythagorean trignometric identity is defined by the following equation:
+ * <pre>sin(x) * sin(x) + cos(x) * cos(x) = 1</pre>
+ * where \c x is the angle in radians.
+ *
+ * \par Block Diagram:
+ * \par
+ * \image html sinCos.gif
+ *
+ * \par Variables Description:
+ * \par
+ * \li \c testInput_f32 array of input angle in radians
+ * \li \c testOutput stores sum of the squares of sine and cosine values of input angle
+ *
+ * \par CMSIS DSP Software Library Functions Used:
+ * \par
+ * - arm_cos_f32()
+ * - arm_sin_f32()
+ * - arm_mult_f32()
+ * - arm_add_f32()
+ *
+ * <b> Refer </b>
+ * \link arm_sin_cos_example_f32.c \endlink
+ *
+ */
+
+
+/** \example arm_sin_cos_example_f32.c
+ */
+
+#include <math.h>
+#include "arm_math.h"
+
+/* ----------------------------------------------------------------------
+* Defines each of the tests performed
+* ------------------------------------------------------------------- */
+#define MAX_BLOCKSIZE 32
+#define DELTA (0.0001f)
+
+
+/* ----------------------------------------------------------------------
+* Test input data for Floating point sin_cos example for 32-blockSize
+* Generated by the MATLAB randn() function
+* ------------------------------------------------------------------- */
+
+const float32_t testInput_f32[MAX_BLOCKSIZE] =
+{
+ -1.244916875853235400, -4.793533929171324800, 0.360705030233248850, 0.827929644170887320, -3.299532218312426900, 3.427441903227623800, 3.422401784294607700, -0.108308165334010680,
+ 0.941943896490312180, 0.502609575000365850, -0.537345278736373500, 2.088817392965764500, -1.693168684143455700, 6.283185307179590700, -0.392545884746175080, 0.327893095115825040,
+ 3.070147440456292300, 0.170611405884662230, -0.275275082396073010, -2.395492805446796300, 0.847311163536506600, -3.845517018083148800, 2.055818378415868300, 4.672594161978930800,
+ -1.990923030266425800, 2.469305197656249500, 3.609002606064021000, -4.586736582331667500, -4.147080139136136300, 1.643756718868359500, -1.150866392366494800, 1.985805026477433800
+
+
+};
+
+const float32_t testRefOutput_f32 = 1.000000000;
+
+/* ----------------------------------------------------------------------
+* Declare Global variables
+* ------------------------------------------------------------------- */
+uint32_t blockSize = 32;
+float32_t testOutput;
+float32_t cosOutput;
+float32_t sinOutput;
+float32_t cosSquareOutput;
+float32_t sinSquareOutput;
+
+/* ----------------------------------------------------------------------
+* Max magnitude FFT Bin test
+* ------------------------------------------------------------------- */
+
+arm_status status;
+
+int32_t main(void)
+{
+ float32_t diff;
+ uint32_t i;
+
+ for(i=0; i< blockSize; i++)
+ {
+ cosOutput = arm_cos_f32(testInput_f32[i]);
+ sinOutput = arm_sin_f32(testInput_f32[i]);
+
+ arm_mult_f32(&cosOutput, &cosOutput, &cosSquareOutput, 1);
+ arm_mult_f32(&sinOutput, &sinOutput, &sinSquareOutput, 1);
+
+ arm_add_f32(&cosSquareOutput, &sinSquareOutput, &testOutput, 1);
+
+ /* absolute value of difference between ref and test */
+ diff = fabsf(testRefOutput_f32 - testOutput);
+
+ /* Comparison of sin_cos value with reference */
+ if (diff > DELTA)
+ {
+ status = ARM_MATH_TEST_FAILURE;
+ }
+
+ if ( status == ARM_MATH_TEST_FAILURE)
+ {
+ while (1);
+ }
+
+ }
+
+ while (1); /* main function does not return */
+}
+
+ /** \endlink */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_variance_example/arm_variance_example_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_variance_example/arm_variance_example_f32.c
new file mode 100644
index 0000000..78a0681
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Examples/ARM/arm_variance_example/arm_variance_example_f32.c
@@ -0,0 +1,204 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.0
+*
+* Project: CMSIS DSP Library
+* Title: arm_variance_example_f32.c
+*
+* Description: Example code demonstrating variance calculation of input sequence.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+/**
+ * @ingroup groupExamples
+ */
+
+/**
+ * @defgroup VarianceExample Variance Example
+ *
+ * \par Description:
+ * \par
+ * Demonstrates the use of Basic Math and Support Functions to calculate the variance of an
+ * input sequence with N samples. Uniformly distributed white noise is taken as input.
+ *
+ * \par Algorithm:
+ * \par
+ * The variance of a sequence is the mean of the squared deviation of the sequence from its mean.
+ * \par
+ * This is denoted by the following equation:
+ * <pre> variance = ((x[0] - x') * (x[0] - x') + (x[1] - x') * (x[1] - x') + ... + * (x[n-1] - x') * (x[n-1] - x')) / (N-1)</pre>
+ * where, <code>x[n]</code> is the input sequence, <code>N</code> is the number of input samples, and
+ * <code>x'</code> is the mean value of the input sequence, <code>x[n]</code>.
+ * \par
+ * The mean value <code>x'</code> is defined as:
+ * <pre> x' = (x[0] + x[1] + ... + x[n-1]) / N</pre>
+ *
+ * \par Block Diagram:
+ * \par
+ * \image html Variance.gif
+ *
+ *
+ * \par Variables Description:
+ * \par
+ * \li \c testInput_f32 points to the input data
+ * \li \c wire1, \c wir2, \c wire3 temporary buffers
+ * \li \c blockSize number of samples processed at a time
+ * \li \c refVarianceOut reference variance value
+ *
+ * \par CMSIS DSP Software Library Functions Used:
+ * \par
+ * - arm_dot_prod_f32()
+ * - arm_mult_f32()
+ * - arm_sub_f32()
+ * - arm_fill_f32()
+ * - arm_copy_f32()
+ *
+ * <b> Refer </b>
+ * \link arm_variance_example_f32.c \endlink
+ *
+ */
+
+
+/** \example arm_variance_example_f32.c
+ */
+#include <math.h>
+#include "arm_math.h"
+
+/* ----------------------------------------------------------------------
+* Defines each of the tests performed
+* ------------------------------------------------------------------- */
+#define MAX_BLOCKSIZE 32
+#define DELTA (0.000001f)
+
+
+/* ----------------------------------------------------------------------
+* Declare I/O buffers
+* ------------------------------------------------------------------- */
+float32_t wire1[MAX_BLOCKSIZE];
+float32_t wire2[MAX_BLOCKSIZE];
+float32_t wire3[MAX_BLOCKSIZE];
+
+/* ----------------------------------------------------------------------
+* Test input data for Floating point Variance example for 32-blockSize
+* Generated by the MATLAB randn() function
+* ------------------------------------------------------------------- */
+
+float32_t testInput_f32[32] =
+{
+ -0.432564811528221, -1.665584378238097, 0.125332306474831, 0.287676420358549,
+ -1.146471350681464, 1.190915465642999, 1.189164201652103, -0.037633276593318,
+ 0.327292361408654, 0.174639142820925, -0.186708577681439, 0.725790548293303,
+ -0.588316543014189, 2.183185818197101, -0.136395883086596, 0.113931313520810,
+ 1.066768211359189, 0.059281460523605, -0.095648405483669, -0.832349463650022,
+ 0.294410816392640, -1.336181857937804, 0.714324551818952, 1.623562064446271,
+ -0.691775701702287, 0.857996672828263, 1.254001421602532, -1.593729576447477,
+ -1.440964431901020, 0.571147623658178, -0.399885577715363, 0.689997375464345
+
+};
+
+/* ----------------------------------------------------------------------
+* Declare Global variables
+* ------------------------------------------------------------------- */
+uint32_t blockSize = 32;
+float32_t refVarianceOut = 0.903941793931839;
+
+/* ----------------------------------------------------------------------
+* Variance calculation test
+* ------------------------------------------------------------------- */
+
+int32_t main(void)
+{
+ arm_status status;
+ float32_t mean, oneByBlockSize;
+ float32_t variance;
+ float32_t diff;
+
+ status = ARM_MATH_SUCCESS;
+
+ /* Calculation of mean value of input */
+
+ /* x' = 1/blockSize * (x(0)* 1 + x(1) * 1 + ... + x(n-1) * 1) */
+
+ /* Fill wire1 buffer with 1.0 value */
+ arm_fill_f32(1.0, wire1, blockSize);
+
+ /* Calculate the dot product of wire1 and wire2 */
+ /* (x(0)* 1 + x(1) * 1 + ...+ x(n-1) * 1) */
+ arm_dot_prod_f32(testInput_f32, wire1, blockSize, &mean);
+
+ /* Calculation of 1/blockSize */
+ oneByBlockSize = 1.0 / (blockSize);
+
+ /* 1/blockSize * (x(0)* 1 + x(1) * 1 + ... + x(n-1) * 1) */
+ arm_mult_f32(&mean, &oneByBlockSize, &mean, 1);
+
+
+ /* Calculation of variance value of input */
+
+ /* (1/blockSize) * (x(0) - x') * (x(0) - x') + (x(1) - x') * (x(1) - x') + ... + (x(n-1) - x') * (x(n-1) - x') */
+
+ /* Fill wire2 with mean value x' */
+ arm_fill_f32(mean, wire2, blockSize);
+
+ /* wire3 contains (x-x') */
+ arm_sub_f32(testInput_f32, wire2, wire3, blockSize);
+
+ /* wire2 contains (x-x') */
+ arm_copy_f32(wire3, wire2, blockSize);
+
+ /* (x(0) - x') * (x(0) - x') + (x(1) - x') * (x(1) - x') + ... + (x(n-1) - x') * (x(n-1) - x') */
+ arm_dot_prod_f32(wire2, wire3, blockSize, &variance);
+
+ /* Calculation of 1/blockSize */
+ oneByBlockSize = 1.0 / (blockSize - 1);
+
+ /* Calculation of variance */
+ arm_mult_f32(&variance, &oneByBlockSize, &variance, 1);
+
+ /* absolute value of difference between ref and test */
+ diff = fabsf(refVarianceOut - variance);
+
+ /* Comparison of variance value with reference */
+ if (diff > DELTA)
+ {
+ status = ARM_MATH_TEST_FAILURE;
+ }
+
+ if ( status != ARM_MATH_SUCCESS)
+ {
+ while (1);
+ }
+
+ while (1); /* main function does not return */
+}
+
+ /** \endlink */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Include/arm_common_tables.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Include/arm_common_tables.h
new file mode 100644
index 0000000..233f623
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Include/arm_common_tables.h
@@ -0,0 +1,121 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_common_tables.h
+ * Description: Extern declaration for common tables
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
+#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
+#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
+#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
+#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
+#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
+#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
+#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /* ARM_COMMON_TABLES_H */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Include/arm_const_structs.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Include/arm_const_structs.h
new file mode 100644
index 0000000..677073e
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Include/arm_const_structs.h
@@ -0,0 +1,66 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_const_structs.h
+ * Description: Constant structs that are initialized for user convenience.
+ * For example, some can be given as arguments to the arm_cfft_f32() function.
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Include/arm_math.h b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Include/arm_math.h
new file mode 100644
index 0000000..997aeae
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Include/arm_math.h
@@ -0,0 +1,7157 @@
+/******************************************************************************
+ * @file arm_math.h
+ * @brief Public header file for CMSIS DSP LibraryU
+ * @version V1.5.3
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ \mainpage CMSIS DSP Software Library
+ *
+ * Introduction
+ * ------------
+ *
+ * This user manual describes the CMSIS DSP software library,
+ * a suite of common signal processing functions for use on Cortex-M processor based devices.
+ *
+ * The library is divided into a number of functions each covering a specific category:
+ * - Basic math functions
+ * - Fast math functions
+ * - Complex math functions
+ * - Filters
+ * - Matrix functions
+ * - Transforms
+ * - Motor control functions
+ * - Statistical functions
+ * - Support functions
+ * - Interpolation functions
+ *
+ * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+ * 32-bit integer and 32-bit floating-point values.
+ *
+ * Using the Library
+ * ------------
+ *
+ * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+ * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)
+ * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)
+ * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)
+ * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)
+ * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)
+ * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)
+ * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)
+ * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)
+ * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)
+ * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)
+ * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)
+ * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)
+ * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)
+ * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)
+ * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian)
+ * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian)
+ * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit)
+ * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions)
+ * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)
+ *
+ * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+ * public header file <code> arm_math.h</code> for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+ * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or
+ * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+ * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
+ * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions.
+ *
+ *
+ * Examples
+ * --------
+ *
+ * The library ships with a number of examples which demonstrate how to use the library functions.
+ *
+ * Toolchain Support
+ * ------------
+ *
+ * The library has been developed and tested with MDK version 5.14.0.0
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+ *
+ * Building the Library
+ * ------------
+ *
+ * The library installer contains a project file to rebuild libraries on MDK toolchain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+ * - arm_cortexM_math.uvprojx
+ *
+ *
+ * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above.
+ *
+ * Preprocessor Macros
+ * ------------
+ *
+ * Each library project have different preprocessor macros.
+ *
+ * - UNALIGNED_SUPPORT_DISABLE:
+ *
+ * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+ *
+ * - ARM_MATH_BIG_ENDIAN:
+ *
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+ *
+ * - ARM_MATH_MATRIX_CHECK:
+ *
+ * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+ *
+ * - ARM_MATH_ROUNDING:
+ *
+ * Define macro ARM_MATH_ROUNDING for rounding on support functions
+ *
+ * - ARM_MATH_CMx:
+ *
+ * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+ * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+ * ARM_MATH_CM7 for building the library on cortex-M7.
+ *
+ * - ARM_MATH_ARMV8MxL:
+ *
+ * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library
+ * on Armv8-M Mainline target.
+ *
+ * - __FPU_PRESENT:
+ *
+ * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries.
+ *
+ * - __DSP_PRESENT:
+ *
+ * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions.
+ *
+ * <hr>
+ * CMSIS-DSP in ARM::CMSIS Pack
+ * -----------------------------
+ *
+ * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
+ * |File/Folder |Content |
+ * |------------------------------|------------------------------------------------------------------------|
+ * |\b CMSIS\\Documentation\\DSP | This documentation |
+ * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) |
+ * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions |
+ * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library |
+ *
+ * <hr>
+ * Revision History of CMSIS-DSP
+ * ------------
+ * Please refer to \ref ChangeLog_pg.
+ *
+ * Copyright Notice
+ * ------------
+ *
+ * Copyright (C) 2010-2015 Arm Limited. All rights reserved.
+ */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures. For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ * typedef struct
+ * {
+ * uint16_t numRows; // number of rows of the matrix.
+ * uint16_t numCols; // number of columns of the matrix.
+ * float32_t *pData; // points to the data of the matrix.
+ * } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data. The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order. That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ * pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types, respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure. For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices. For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns. If the size check fails the functions return:
+ * <pre>
+ * ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ * ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ * ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings. By default this macro is defined
+ * and size checking is enabled. By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster. With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+/* Compiler specific diagnostic adjustment */
+#if defined ( __CC_ARM )
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+#elif defined ( __ICCARM__ )
+
+#elif defined ( __TI_ARM__ )
+
+#elif defined ( __CSMC__ )
+
+#elif defined ( __TASKING__ )
+
+#else
+ #error Unknown compiler
+#endif
+
+
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+ #include "core_cm7.h"
+ #define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM4)
+ #include "core_cm4.h"
+ #define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM3)
+ #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+ #include "core_cm0.h"
+ #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+ #include "core_cm0plus.h"
+ #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MBL)
+ #include "core_armv8mbl.h"
+ #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MML)
+ #include "core_armv8mml.h"
+ #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1))
+ #define ARM_MATH_DSP
+ #endif
+#else
+ #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML"
+#endif
+
+#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+ /**
+ * @brief Macros required for reciprocal calculation in Normalized LMS
+ */
+
+#define DELTA_Q31 (0x100)
+#define DELTA_Q15 0x5
+#define INDEX_MASK 0x0000003F
+#ifndef PI
+ #define PI 3.14159265358979f
+#endif
+
+ /**
+ * @brief Macros required for SINE and COSINE Fast math approximations
+ */
+
+#define FAST_MATH_TABLE_SIZE 512
+#define FAST_MATH_Q31_SHIFT (32 - 10)
+#define FAST_MATH_Q15_SHIFT (16 - 10)
+#define CONTROLLER_Q31_SHIFT (32 - 9)
+#define TABLE_SPACING_Q31 0x400000
+#define TABLE_SPACING_Q15 0x80
+
+ /**
+ * @brief Macros required for SINE and COSINE Controller functions
+ */
+ /* 1.31(q31) Fixed value of 2/360 */
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING 0xB60B61
+
+ /**
+ * @brief Macro for Unaligned Support
+ */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+ #define ALIGN4
+#else
+ #if defined (__GNUC__)
+ #define ALIGN4 __attribute__((aligned(4)))
+ #else
+ #define ALIGN4 __align(4)
+ #endif
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /**
+ * @brief Error status returned by some functions in the library.
+ */
+
+ typedef enum
+ {
+ ARM_MATH_SUCCESS = 0, /**< No error */
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
+ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
+ } arm_status;
+
+ /**
+ * @brief 8-bit fractional data type in 1.7 format.
+ */
+ typedef int8_t q7_t;
+
+ /**
+ * @brief 16-bit fractional data type in 1.15 format.
+ */
+ typedef int16_t q15_t;
+
+ /**
+ * @brief 32-bit fractional data type in 1.31 format.
+ */
+ typedef int32_t q31_t;
+
+ /**
+ * @brief 64-bit fractional data type in 1.63 format.
+ */
+ typedef int64_t q63_t;
+
+ /**
+ * @brief 32-bit floating-point type definition.
+ */
+ typedef float float32_t;
+
+ /**
+ * @brief 64-bit floating-point type definition.
+ */
+ typedef double float64_t;
+
+ /**
+ * @brief definition to read/write two 16 bit values.
+ */
+#if defined ( __CC_ARM )
+ #define __SIMD32_TYPE int32_t __packed
+ #define CMSIS_UNUSED __attribute__((unused))
+ #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED __attribute__((unused))
+ #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __GNUC__ )
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED __attribute__((unused))
+ #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ICCARM__ )
+ #define __SIMD32_TYPE int32_t __packed
+ #define CMSIS_UNUSED
+ #define CMSIS_INLINE
+
+#elif defined ( __TI_ARM__ )
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED __attribute__((unused))
+ #define CMSIS_INLINE
+
+#elif defined ( __CSMC__ )
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED
+ #define CMSIS_INLINE
+
+#elif defined ( __TASKING__ )
+ #define __SIMD32_TYPE __unaligned int32_t
+ #define CMSIS_UNUSED
+ #define CMSIS_INLINE
+
+#else
+ #error Unknown compiler
+#endif
+
+#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))
+#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))
+#define __SIMD64(addr) (*(int64_t **) & (addr))
+
+#if !defined (ARM_MATH_DSP)
+ /**
+ * @brief definition to pack two 16 bit values.
+ */
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
+ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
+
+#endif /* !defined (ARM_MATH_DSP) */
+
+ /**
+ * @brief definition to pack four 8 bit values.
+ */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
+
+#endif
+
+
+ /**
+ * @brief Clips Q63 to Q31 values.
+ */
+ CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+ }
+
+ /**
+ * @brief Clips Q63 to Q15 values.
+ */
+ CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+ }
+
+ /**
+ * @brief Clips Q31 to Q7 values.
+ */
+ CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+ }
+
+ /**
+ * @brief Clips Q31 to Q15 values.
+ */
+ CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+ }
+
+ /**
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+ */
+
+ CMSIS_INLINE __STATIC_INLINE q63_t mult32x64(
+ q63_t x,
+ q31_t y)
+ {
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+ (((q63_t) (x >> 32) * y)));
+ }
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+ */
+
+ CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31(
+ q31_t in,
+ q31_t * dst,
+ q31_t * pRecipTable)
+ {
+ q31_t out;
+ uint32_t tempVal;
+ uint32_t index, i;
+ uint32_t signBits;
+
+ if (in > 0)
+ {
+ signBits = ((uint32_t) (__CLZ( in) - 1));
+ }
+ else
+ {
+ signBits = ((uint32_t) (__CLZ(-in) - 1));
+ }
+
+ /* Convert input sample to 1.31 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 24);
+ index = (index & INDEX_MASK);
+
+ /* 1.31 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0U; i < 2U; i++)
+ {
+ tempVal = (uint32_t) (((q63_t) in * out) >> 31);
+ tempVal = 0x7FFFFFFFu - tempVal;
+ /* 1.31 with exp 1 */
+ /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
+ out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1U);
+ }
+
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15(
+ q15_t in,
+ q15_t * dst,
+ q15_t * pRecipTable)
+ {
+ q15_t out = 0;
+ uint32_t tempVal = 0;
+ uint32_t index = 0, i = 0;
+ uint32_t signBits = 0;
+
+ if (in > 0)
+ {
+ signBits = ((uint32_t)(__CLZ( in) - 17));
+ }
+ else
+ {
+ signBits = ((uint32_t)(__CLZ(-in) - 17));
+ }
+
+ /* Convert input sample to 1.15 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 8);
+ index = (index & INDEX_MASK);
+
+ /* 1.15 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0U; i < 2U; i++)
+ {
+ tempVal = (uint32_t) (((q31_t) in * out) >> 15);
+ tempVal = 0x7FFFu - tempVal;
+ /* 1.15 with exp 1 */
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);
+ /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1);
+ }
+
+
+/*
+ * @brief C custom defined intrinsic function for M3 and M0 processors
+ */
+#if !defined (ARM_MATH_DSP)
+
+ /*
+ * @brief C custom defined QADD8 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB8 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16(
+ uint32_t x,
+ uint32_t y)
+ {
+/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */
+ q31_t r = 0, s = 0;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHADD16 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB16 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHSUB16 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QASX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QASX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHASX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSAX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHSAX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SMUSDX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+ }
+
+ /*
+ * @brief C custom defined SMUADX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined QADD for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE int32_t __QADD(
+ int32_t x,
+ int32_t y)
+ {
+ return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE int32_t __QSUB(
+ int32_t x,
+ int32_t y)
+ {
+ return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
+ }
+
+
+ /*
+ * @brief C custom defined SMLAD for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLADX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLSDX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLALD for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+ {
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLALDX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+ {
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMUAD for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMUSD for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined SXTB16 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16(
+ uint32_t x)
+ {
+ return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
+ ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) ));
+ }
+
+ /*
+ * @brief C custom defined SMMLA for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA(
+ int32_t x,
+ int32_t y,
+ int32_t sum)
+ {
+ return (sum + (int32_t) (((int64_t) x * y) >> 32));
+ }
+
+#endif /* !defined (ARM_MATH_DSP) */
+
+
+ /**
+ * @brief Instance structure for the Q7 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q7;
+
+ /**
+ * @brief Instance structure for the Q15 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in] S points to an instance of the Q7 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q7(
+ const arm_fir_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 FIR filter.
+ * @param[in,out] S points to an instance of the Q7 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed.
+ */
+ void arm_fir_init_q7(
+ arm_fir_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] S points to an instance of the Q15 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_fast_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR filter.
+ * @param[in,out] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+ * <code>numTaps</code> is not a supported value.
+ */
+ arm_status arm_fir_init_q15(
+ arm_fir_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in] S points to an instance of the Q31 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_fast_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR filter.
+ * @param[in,out] S points to an instance of the Q31 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+ void arm_fir_init_q31(
+ arm_fir_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] S points to an instance of the floating-point FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_f32(
+ const arm_fir_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR filter.
+ * @param[in,out] S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+ void arm_fir_init_f32(
+ arm_fir_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+ } arm_biquad_casd_df1_inst_q15;
+
+ /**
+ * @brief Instance structure for the Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+ } arm_biquad_casd_df1_inst_q31;
+
+ /**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_casd_df1_inst_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift);
+
+
+ /**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift);
+
+
+ /**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float32_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f32;
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float64_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f64;
+
+ /**
+ * @brief Instance structure for the Q15 matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q15_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q31_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_q31;
+
+
+ /**
+ * @brief Floating-point matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_add_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_add_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_add_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_cmplx_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_cmplx_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Q31, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_cmplx_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_trans_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_trans_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_trans_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+
+ /**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_fast_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+
+ /**
+ * @brief Q31 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_fast_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_sub_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_sub_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_sub_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix scaling.
+ * @param[in] pSrc points to the input matrix
+ * @param[in] scale scale factor
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_scale_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_scale_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_scale_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Q31 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+ void arm_mat_init_q31(
+ arm_matrix_instance_q31 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t * pData);
+
+
+ /**
+ * @brief Q15 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+ void arm_mat_init_q15(
+ arm_matrix_instance_q15 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t * pData);
+
+
+ /**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+ void arm_mat_init_f32(
+ arm_matrix_instance_f32 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t * pData);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 PID Control.
+ */
+ typedef struct
+ {
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+#if !defined (ARM_MATH_DSP)
+ q15_t A1;
+ q15_t A2;
+#else
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+ q15_t state[3]; /**< The state array of length 3. */
+ q15_t Kp; /**< The proportional gain. */
+ q15_t Ki; /**< The integral gain. */
+ q15_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 PID Control.
+ */
+ typedef struct
+ {
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ q31_t A2; /**< The derived gain, A2 = Kd . */
+ q31_t state[3]; /**< The state array of length 3. */
+ q31_t Kp; /**< The proportional gain. */
+ q31_t Ki; /**< The integral gain. */
+ q31_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point PID Control.
+ */
+ typedef struct
+ {
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ float32_t A2; /**< The derived gain, A2 = Kd . */
+ float32_t state[3]; /**< The state array of length 3. */
+ float32_t Kp; /**< The proportional gain. */
+ float32_t Ki; /**< The integral gain. */
+ float32_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_f32;
+
+
+
+ /**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_f32(
+ arm_pid_instance_f32 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ */
+ void arm_pid_reset_f32(
+ arm_pid_instance_f32 * S);
+
+
+ /**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_q31(
+ arm_pid_instance_q31 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ */
+
+ void arm_pid_reset_q31(
+ arm_pid_instance_q31 * S);
+
+
+ /**
+ * @brief Initialization function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_q15(
+ arm_pid_instance_q15 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the q15 PID Control structure
+ */
+ void arm_pid_reset_q15(
+ arm_pid_instance_q15 * S);
+
+
+ /**
+ * @brief Instance structure for the floating-point Linear Interpolate function.
+ */
+ typedef struct
+ {
+ uint32_t nValues; /**< nValues */
+ float32_t x1; /**< x1 */
+ float32_t xSpacing; /**< xSpacing */
+ float32_t *pYData; /**< pointer to the table of Y values */
+ } arm_linear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ float32_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q31_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q15_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q7_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q7;
+
+
+ /**
+ * @brief Q7 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q15(
+ arm_cfft_radix2_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q15(
+ const arm_cfft_radix2_instance_q15 * S,
+ q15_t * pSrc);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q15(
+ arm_cfft_radix4_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q31(
+ arm_cfft_radix2_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q31(
+ const arm_cfft_radix2_instance_q31 * S,
+ q31_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+ void arm_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc);
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q31(
+ arm_cfft_radix4_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_f32(
+ arm_cfft_radix2_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_f32(
+ const arm_cfft_radix2_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_f32(
+ arm_cfft_radix4_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_f32(
+ const arm_cfft_radix4_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q15_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_q15;
+
+void arm_cfft_q15(
+ const arm_cfft_instance_q15 * S,
+ q15_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_q31;
+
+void arm_cfft_q31(
+ const arm_cfft_instance_q31 * S,
+ q31_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_f32;
+
+ void arm_cfft_f32(
+ const arm_cfft_instance_f32 * S,
+ float32_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q15;
+
+ arm_status arm_rfft_init_q15(
+ arm_rfft_instance_q15 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q15(
+ const arm_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst);
+
+ /**
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q31;
+
+ arm_status arm_rfft_init_q31(
+ arm_rfft_instance_q31 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q31(
+ const arm_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint16_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_f32;
+
+ arm_status arm_rfft_init_f32(
+ arm_rfft_instance_f32 * S,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_f32(
+ const arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+typedef struct
+ {
+ arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
+ uint16_t fftLenRFFT; /**< length of the real sequence */
+ float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */
+ } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+ arm_rfft_fast_instance_f32 * S,
+ uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+ arm_rfft_fast_instance_f32 * S,
+ float32_t * p, float32_t * pOut,
+ uint8_t ifftFlag);
+
+ /**
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ float32_t normalize; /**< normalizing factor. */
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */
+ float32_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_f32;
+
+
+ /**
+ * @brief Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+ */
+ arm_status arm_dct4_init_f32(
+ arm_dct4_instance_f32 * S,
+ arm_rfft_instance_f32 * S_RFFT,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize);
+
+
+ /**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_f32(
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer);
+
+
+ /**
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q31_t normalize; /**< normalizing factor. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ q31_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q31;
+
+
+ /**
+ * @brief Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ */
+ arm_status arm_dct4_init_q31(
+ arm_dct4_instance_q31 * S,
+ arm_rfft_instance_q31 * S_RFFT,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize);
+
+
+ /**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q31 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_q31(
+ const arm_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer);
+
+
+ /**
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q15_t normalize; /**< normalizing factor. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ q15_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ */
+ arm_status arm_dct4_init_q15(
+ arm_dct4_instance_q15 * S,
+ arm_rfft_instance_q15 * S_RFFT,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize);
+
+
+ /**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q15 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_q15(
+ const arm_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer);
+
+
+ /**
+ * @brief Floating-point vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_f32(
+ float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q7(
+ q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q15(
+ q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q31(
+ q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result);
+
+
+ /**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result);
+
+
+ /**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+ /**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+ /**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q7(
+ q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q15(
+ q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q31(
+ q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_f32(
+ float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q7(
+ q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q15(
+ q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q31(
+ q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+ void arm_conv_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+ void arm_conv_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+ void arm_conv_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+ void arm_conv_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q7 sequences
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point FIR decimator.
+ * @param[in] S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR decimator.
+ * @param[in,out] S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+ arm_status arm_fir_decimate_init_f32(
+ arm_fir_decimate_instance_f32 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR decimator.
+ * @param[in,out] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+ arm_status arm_fir_decimate_init_q15(
+ arm_fir_decimate_instance_q15 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_fast_q31(
+ arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR decimator.
+ * @param[in,out] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+ arm_status arm_fir_decimate_init_q31(
+ arm_fir_decimate_instance_q31 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+ } arm_fir_interpolate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+ arm_status arm_fir_interpolate_init_q15(
+ arm_fir_interpolate_instance_q15 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+ arm_status arm_fir_interpolate_init_q31(
+ arm_fir_interpolate_instance_q31 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+ arm_status arm_fir_interpolate_init_f32(
+ arm_fir_interpolate_instance_f32 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
+ } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+ /**
+ * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f64;
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df2T_f32(
+ const arm_biquad_cascade_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_stereo_df2T_f32(
+ const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df2T_f64(
+ const arm_biquad_cascade_df2T_instance_f64 * S,
+ float64_t * pSrc,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df2T_init_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_stereo_df2T_init_f32(
+ arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df2T_init_f64(
+ arm_biquad_cascade_df2T_instance_f64 * S,
+ uint8_t numStages,
+ float64_t * pCoeffs,
+ float64_t * pState);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_f32;
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_q15(
+ arm_fir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_q31(
+ arm_fir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_f32(
+ arm_fir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_init_f32(
+ arm_iir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pkCoeffs,
+ float32_t * pvCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_init_q31(
+ arm_iir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pkCoeffs,
+ q31_t * pvCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ */
+ void arm_iir_lattice_init_q15(
+ arm_iir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pkCoeffs,
+ q15_t * pvCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the floating-point LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that controls filter coefficient updates. */
+ } arm_lms_instance_f32;
+
+
+ /**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_f32(
+ const arm_lms_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_init_f32(
+ arm_lms_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_init_q15(
+ arm_lms_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+ /**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_q15(
+ const arm_lms_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q31;
+
+
+ /**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_q31(
+ const arm_lms_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_init_q31(
+ arm_lms_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+ /**
+ * @brief Instance structure for the floating-point normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that control filter coefficient updates. */
+ float32_t energy; /**< saves previous frame energy. */
+ float32_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_f32;
+
+
+ /**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_init_f32(
+ arm_lms_norm_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q31_t *recipTable; /**< points to the reciprocal initial value table. */
+ q31_t energy; /**< saves previous frame energy. */
+ q31_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q31;
+
+
+ /**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_q31(
+ arm_lms_norm_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_norm_init_q31(
+ arm_lms_norm_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Instance structure for the Q15 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< Number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q15_t *recipTable; /**< Points to the reciprocal initial value table. */
+ q15_t energy; /**< saves previous frame energy. */
+ q15_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q15;
+
+
+ /**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_q15(
+ arm_lms_norm_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_norm_init_q15(
+ arm_lms_norm_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ */
+ void arm_correlate_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+
+ void arm_correlate_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+
+ void arm_correlate_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ */
+ void arm_correlate_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+ void arm_correlate_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Instance structure for the floating-point sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q7 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q7;
+
+
+ /**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_f32(
+ arm_fir_sparse_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_f32(
+ arm_fir_sparse_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q31(
+ arm_fir_sparse_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q31(
+ arm_fir_sparse_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q15(
+ arm_fir_sparse_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q15(
+ arm_fir_sparse_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q7(
+ arm_fir_sparse_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ q7_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q7(
+ arm_fir_sparse_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cos output.
+ */
+ void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCosVal);
+
+
+ /**
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cosine output.
+ */
+ void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal);
+
+
+ /**
+ * @brief Floating-point complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * <code>S</code> points to an instance of the PID control data structure. <code>in</code>
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ * <pre>
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ * A0 = Kp + Ki + Kd
+ * A1 = (-Kp ) - (2 * Kd )
+ * A2 = Kd </pre>
+ *
+ * \par
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+ *
+ * \par
+ * \image html PID.gif "Proportional Integral Derivative Controller"
+ *
+ * \par
+ * The PID controller calculates an "error" value as the difference between
+ * the measured output and the reference input.
+ * The controller attempts to minimize the error by adjusting the process control inputs.
+ * The proportional value determines the reaction to the current error,
+ * the integral value determines the reaction based on the sum of recent errors,
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.
+ *
+ * \par Instance Structure
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+ * A separate instance structure must be defined for each PID Controller.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Reset Functions
+ * There is also an associated reset function for each data type which clears the state array.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+ * - Zeros out the values in the state buffer.
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ */
+ CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32(
+ arm_pid_instance_f32 * S,
+ float32_t in)
+ {
+ float32_t out;
+
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
+ out = (S->A0 * in) +
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @brief Process function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+ CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31(
+ arm_pid_instance_q31 * S,
+ q31_t in)
+ {
+ q63_t acc;
+ q31_t out;
+
+ /* acc = A0 * x[n] */
+ acc = (q63_t) S->A0 * in;
+
+ /* acc += A1 * x[n-1] */
+ acc += (q63_t) S->A1 * S->state[0];
+
+ /* acc += A2 * x[n-2] */
+ acc += (q63_t) S->A2 * S->state[1];
+
+ /* convert output to 1.31 format to add y[n-1] */
+ out = (q31_t) (acc >> 31U);
+
+ /* out += y[n-1] */
+ out += S->state[2];
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+ }
+
+
+ /**
+ * @brief Process function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+ CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15(
+ arm_pid_instance_q15 * S,
+ q15_t in)
+ {
+ q63_t acc;
+ q15_t out;
+
+#if defined (ARM_MATH_DSP)
+ __SIMD32_TYPE *vstate;
+
+ /* Implementation of PID controller */
+
+ /* acc = A0 * x[n] */
+ acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ vstate = __SIMD32_CONST(S->state);
+ acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);
+#else
+ /* acc = A0 * x[n] */
+ acc = ((q31_t) S->A0) * in;
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc += (q31_t) S->A1 * S->state[0];
+ acc += (q31_t) S->A2 * S->state[1];
+#endif
+
+ /* acc += y[n-1] */
+ acc += (q31_t) S->state[2] << 15;
+
+ /* saturate the output */
+ out = (q15_t) (__SSAT((acc >> 15), 16));
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+ }
+
+ /**
+ * @} end of PID group
+ */
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+ arm_status arm_mat_inverse_f32(
+ const arm_matrix_instance_f32 * src,
+ arm_matrix_instance_f32 * dst);
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+ arm_status arm_mat_inverse_f64(
+ const arm_matrix_instance_f64 * src,
+ arm_matrix_instance_f64 * dst);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup clarke Vector Clarke Transform
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+ * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+ * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+ * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+ * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+ * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup clarke
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point Clarke transform
+ * @param[in] Ia input three-phase coordinate <code>a</code>
+ * @param[in] Ib input three-phase coordinate <code>b</code>
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32(
+ float32_t Ia,
+ float32_t Ib,
+ float32_t * pIalpha,
+ float32_t * pIbeta)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+ *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+ }
+
+
+ /**
+ * @brief Clarke transform for Q31 version
+ * @param[in] Ia input three-phase coordinate <code>a</code>
+ * @param[in] Ib input three-phase coordinate <code>b</code>
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31(
+ q31_t Ia,
+ q31_t Ib,
+ q31_t * pIalpha,
+ q31_t * pIbeta)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+ /* pIbeta is calculated by adding the intermediate products */
+ *pIbeta = __QADD(product1, product2);
+ }
+
+ /**
+ * @} end of clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_q7_to_q31(
+ q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+ * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Clarke transform
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] pIa points to output three-phase coordinate <code>a</code>
+ * @param[out] pIb points to output three-phase coordinate <code>b</code>
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pIa,
+ float32_t * pIb)
+ {
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+ *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
+ }
+
+
+ /**
+ * @brief Inverse Clarke transform for Q31 version
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] pIa points to output three-phase coordinate <code>a</code>
+ * @param[out] pIb points to output three-phase coordinate <code>b</code>
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pIa,
+ q31_t * pIb)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+ /* pIb is calculated by subtracting the products */
+ *pIb = __QSUB(product2, product1);
+ }
+
+ /**
+ * @} end of inv_clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_q7_to_q15(
+ q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+ * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Park transform
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_park_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pId,
+ float32_t * pIq,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+ *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+ }
+
+
+ /**
+ * @brief Park transform for Q31 version
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_park_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pId,
+ q31_t * pIq,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Ialpha * cosVal) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * sinVal) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Ialpha * sinVal) */
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * cosVal) */
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+ /* Calculate pId by adding the two intermediate products 1 and 2 */
+ *pId = __QADD(product1, product2);
+
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+ *pIq = __QSUB(product4, product3);
+ }
+
+ /**
+ * @} end of park group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q7_to_float(
+ q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+ * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Park transform
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32(
+ float32_t Id,
+ float32_t Iq,
+ float32_t * pIalpha,
+ float32_t * pIbeta,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+ *pIalpha = Id * cosVal - Iq * sinVal;
+
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+ *pIbeta = Id * sinVal + Iq * cosVal;
+ }
+
+
+ /**
+ * @brief Inverse Park transform for Q31 version
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31(
+ q31_t Id,
+ q31_t Iq,
+ q31_t * pIalpha,
+ q31_t * pIbeta,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Id * cosVal) */
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * sinVal) */
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Id * sinVal) */
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * cosVal) */
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+ *pIalpha = __QSUB(product1, product2);
+
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+ *pIbeta = __QADD(product4, product3);
+ }
+
+ /**
+ * @} end of Inverse park group
+ */
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_float(
+ q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup LinearInterpolate Linear Interpolation
+ *
+ * Linear interpolation is a method of curve fitting using linear polynomials.
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+ *
+ * \par
+ * \image html LinearInterp.gif "Linear interpolation"
+ *
+ * \par
+ * A Linear Interpolate function calculates an output value(y), for the input(x)
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+ *
+ * \par Algorithm:
+ * <pre>
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ * where x0, x1 are nearest values of input x
+ * y0, y1 are nearest values to output y
+ * </pre>
+ *
+ * \par
+ * This set of functions implements Linear interpolation process
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
+ * sample of data and each call to the function returns a single processed value.
+ * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+ * <code>x</code> is the input sample value. The functions returns the output value.
+ *
+ * \par
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table
+ * if x is below input range and returns last value of table if x is above range.
+ */
+
+ /**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] S is an instance of the floating-point Linear Interpolation structure
+ * @param[in] x input sample to process
+ * @return y processed output sample.
+ *
+ */
+ CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32(
+ arm_linear_interp_instance_f32 * S,
+ float32_t x)
+ {
+ float32_t y;
+ float32_t x0, x1; /* Nearest input values */
+ float32_t y0, y1; /* Nearest output values */
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */
+ int32_t i; /* Index variable */
+ float32_t *pYData = S->pYData; /* pointer to output table */
+
+ /* Calculation of index */
+ i = (int32_t) ((x - S->x1) / xSpacing);
+
+ if (i < 0)
+ {
+ /* Iniatilize output for below specified range as least output value of table */
+ y = pYData[0];
+ }
+ else if ((uint32_t)i >= S->nValues)
+ {
+ /* Iniatilize output for above specified range as last output value of table */
+ y = pYData[S->nValues - 1];
+ }
+ else
+ {
+ /* Calculation of nearest input values */
+ x0 = S->x1 + i * xSpacing;
+ x1 = S->x1 + (i + 1) * xSpacing;
+
+ /* Read of nearest output values */
+ y0 = pYData[i];
+ y1 = pYData[i + 1];
+
+ /* Calculation of output */
+ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+ }
+
+ /* returns output value */
+ return (y);
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q31 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q31 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+ CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31(
+ q31_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q31_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (q31_t)0xFFF00000) >> 20);
+
+ if (index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if (index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* shift left by 11 to keep fract in 1.31 format */
+ fract = (x & 0x000FFFFF) << 11;
+
+ /* Read two nearest output values from the index in 1.31(q31) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+ /* Convert y to 1.31 format */
+ return (y << 1U);
+ }
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q15 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q15 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+ CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15(
+ q15_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q63_t y; /* output */
+ q15_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (int32_t)0xFFF00000) >> 20);
+
+ if (index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if (index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+ y = ((q63_t) y0 * (0xFFFFF - fract));
+
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+ y += ((q63_t) y1 * (fract));
+
+ /* convert y to 1.15 format */
+ return (q15_t) (y >> 20);
+ }
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q7 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q7 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+ CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7(
+ q7_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q7_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ uint32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ if (x < 0)
+ {
+ return (pYData[0]);
+ }
+ index = (x >> 20) & 0xfff;
+
+ if (index >= (nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index and are in 1.7(q7) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+ y = ((y0 * (0xFFFFF - fract)));
+
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+ y += (y1 * fract);
+
+ /* convert y to 1.7(q7) format */
+ return (q7_t) (y >> 20);
+ }
+ }
+
+ /**
+ * @} end of LinearInterpolate group
+ */
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+ float32_t arm_sin_f32(
+ float32_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+ q31_t arm_sin_q31(
+ q31_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+ q15_t arm_sin_q15(
+ q15_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+ float32_t arm_cos_f32(
+ float32_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+ q31_t arm_cos_q31(
+ q31_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+ q15_t arm_cos_q15(
+ q15_t x);
+
+
+ /**
+ * @ingroup groupFastMath
+ */
+
+
+ /**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ * <pre>
+ * x1 = x0 - f(x0)/f'(x0)
+ * </pre>
+ * where <code>x1</code> is the current estimate,
+ * <code>x0</code> is the previous estimate, and
+ * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+ * For the square root function, the algorithm reduces to:
+ * <pre>
+ * x0 = in/2 [initial guess]
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]
+ * </pre>
+ */
+
+
+ /**
+ * @addtogroup SQRT
+ * @{
+ */
+
+ /**
+ * @brief Floating-point square root function.
+ * @param[in] in input value.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+ CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32(
+ float32_t in,
+ float32_t * pOut)
+ {
+ if (in >= 0.0f)
+ {
+
+#if (__FPU_USED == 1) && defined ( __CC_ARM )
+ *pOut = __sqrtf(in);
+#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+ *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined(__GNUC__)
+ *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)
+ __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
+#else
+ *pOut = sqrtf(in);
+#endif
+
+ return (ARM_MATH_SUCCESS);
+ }
+ else
+ {
+ *pOut = 0.0f;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+ }
+
+
+ /**
+ * @brief Q31 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q31(
+ q31_t in,
+ q31_t * pOut);
+
+
+ /**
+ * @brief Q15 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q15(
+ q15_t in,
+ q15_t * pOut);
+
+ /**
+ * @} end of SQRT group
+ */
+
+
+ /**
+ * @brief floating-point Circular write function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const int32_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+
+ /**
+ * @brief floating-point Circular Read function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ int32_t * dst,
+ int32_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == (int32_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q15 Circular write function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q15_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+ /**
+ * @brief Q15 Circular Read function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q15_t * dst,
+ q15_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == (q15_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular write function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q7_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular Read function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q7_t * dst,
+ q7_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == (q7_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Floating-point complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult);
+
+
+ /**
+ * @brief Q31 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult);
+
+
+ /**
+ * @brief Floating-point complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult);
+
+
+ /**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_q15(
+ q15_t * pSrcCmplx,
+ q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_q31(
+ q31_t * pSrcCmplx,
+ q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_f32(
+ float32_t * pSrcCmplx,
+ float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] result is output pointer
+ * @param[in] index is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * result,
+ uint32_t * index);
+
+
+ /**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[in] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q31(
+ float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q15(
+ float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q7(
+ float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_q15(
+ q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_q7(
+ q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_float(
+ q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_q31(
+ q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_q7(
+ q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup BilinearInterpolate Bilinear Interpolation
+ *
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+ * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+ * determines values between the grid points.
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+ * Bilinear interpolation is often used in image processing to rescale images.
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+ *
+ * <b>Algorithm</b>
+ * \par
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+ * For floating-point, the instance structure is defined as:
+ * <pre>
+ * typedef struct
+ * {
+ * uint16_t numRows;
+ * uint16_t numCols;
+ * float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ * </pre>
+ *
+ * \par
+ * where <code>numRows</code> specifies the number of rows in the table;
+ * <code>numCols</code> specifies the number of columns in the table;
+ * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+ * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+ * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+ *
+ * \par
+ * Let <code>(x, y)</code> specify the desired interpolation point. Then define:
+ * <pre>
+ * XF = floor(x)
+ * YF = floor(y)
+ * </pre>
+ * \par
+ * The interpolated output point is computed as:
+ * <pre>
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ * </pre>
+ * Note that the coordinates (x, y) contain integer and fractional components.
+ * The integer components specify which portion of the table to use while the
+ * fractional components control the interpolation processor.
+ *
+ * \par
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+ */
+
+ /**
+ * @addtogroup BilinearInterpolate
+ * @{
+ */
+
+
+ /**
+ *
+ * @brief Floating-point bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate.
+ * @param[in] Y interpolation coordinate.
+ * @return out interpolated value.
+ */
+ CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32(
+ const arm_bilinear_interp_instance_f32 * S,
+ float32_t X,
+ float32_t Y)
+ {
+ float32_t out;
+ float32_t f00, f01, f10, f11;
+ float32_t *pData = S->pData;
+ int32_t xIndex, yIndex, index;
+ float32_t xdiff, ydiff;
+ float32_t b1, b2, b3, b4;
+
+ xIndex = (int32_t) X;
+ yIndex = (int32_t) Y;
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* Calculation of index for two nearest points in X-direction */
+ index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+ /* Read two nearest points in X-direction */
+ f00 = pData[index];
+ f01 = pData[index + 1];
+
+ /* Calculation of index for two nearest points in Y-direction */
+ index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+ /* Read two nearest points in Y-direction */
+ f10 = pData[index];
+ f11 = pData[index + 1];
+
+ /* Calculation of intermediate values */
+ b1 = f00;
+ b2 = f01 - f00;
+ b3 = f10 - f00;
+ b4 = f00 - f01 - f10 + f11;
+
+ /* Calculation of fractional part in X */
+ xdiff = X - xIndex;
+
+ /* Calculation of fractional part in Y */
+ ydiff = Y - yIndex;
+
+ /* Calculation of bi-linear interpolated output */
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+ /* return to application */
+ return (out);
+ }
+
+
+ /**
+ *
+ * @brief Q31 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31(
+ arm_bilinear_interp_instance_q31 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q31_t out; /* Temporary output */
+ q31_t acc = 0; /* output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q31_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q31_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* shift left xfract by 11 to keep 1.31 format */
+ xfract = (X & 0x000FFFFF) << 11U;
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + (int32_t)nCols * (cI) ];
+ x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* shift left yfract by 11 to keep 1.31 format */
+ yfract = (Y & 0x000FFFFF) << 11U;
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ];
+ y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* Convert acc to 1.31(q31) format */
+ return ((q31_t)(acc << 2));
+ }
+
+
+ /**
+ * @brief Q15 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15(
+ arm_bilinear_interp_instance_q15 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q15_t x1, x2, y1, y2; /* Nearest output values */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ int32_t rI, cI; /* Row and column indices */
+ q15_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
+ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U);
+ acc = ((q63_t) out * (0xFFFFF - yfract));
+
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U);
+ acc += ((q63_t) out * (xfract));
+
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U);
+ acc += ((q63_t) out * (yfract));
+
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U);
+ acc += ((q63_t) out * (yfract));
+
+ /* acc is in 13.51 format and down shift acc by 36 times */
+ /* Convert out to 1.15 format */
+ return ((q15_t)(acc >> 36));
+ }
+
+
+ /**
+ * @brief Q7 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7(
+ arm_bilinear_interp_instance_q7 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q7_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q7_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+ out = ((x1 * (0xFFFFF - xfract)));
+ acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
+ out = ((x2 * (0xFFFFF - yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y1 * (0xFFFFF - xfract)));
+ acc += (((q63_t) out * (yfract)));
+
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y2 * (yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+ return ((q7_t)(acc >> 40));
+ }
+
+ /**
+ * @} end of BilinearInterpolate group
+ */
+
+
+/* SMMLAR */
+#define multAcc_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMLSR */
+#define multSub_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMULR */
+#define mult_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+/* SMMLA */
+#define multAcc_32x32_keep32(a, x, y) \
+ a += (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMLS */
+#define multSub_32x32_keep32(a, x, y) \
+ a -= (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMUL */
+#define mult_32x32_keep32(a, x, y) \
+ a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM )
+ /* Enter low optimization region - place directly above function definition */
+ #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("push") \
+ _Pragma ("O1")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+ #define LOW_OPTIMIZATION_EXIT \
+ _Pragma ("pop")
+ #else
+ #define LOW_OPTIMIZATION_EXIT
+ #endif
+
+ /* Enter low optimization region - place directly above function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __GNUC__ )
+ #define LOW_OPTIMIZATION_ENTER \
+ __attribute__(( optimize("-O1") ))
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __ICCARM__ )
+ /* Enter low optimization region - place directly above function definition */
+ #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define LOW_OPTIMIZATION_EXIT
+
+ /* Enter low optimization region - place directly above function definition */
+ #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TI_ARM__ )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __CSMC__ )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TASKING__ )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/* Compiler specific diagnostic adjustment */
+#if defined ( __CC_ARM )
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+
+#elif defined ( __ICCARM__ )
+
+#elif defined ( __TI_ARM__ )
+
+#elif defined ( __CSMC__ )
+
+#elif defined ( __TASKING__ )
+
+#else
+ #error Unknown compiler
+#endif
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f32.c
new file mode 100644
index 0000000..69b2bfc
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f32.c
@@ -0,0 +1,153 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_abs_f32.c
+ * Description: Floating-point vector absolute value
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include <math.h>
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @defgroup BasicAbs Vector Absolute Value
+ *
+ * Computes the absolute value of a vector on an element-by-element basis.
+ *
+ * <pre>
+ * pDst[n] = abs(pSrc[n]), 0 <= n < blockSize.
+ * </pre>
+ *
+ * The functions support in-place computation allowing the source and
+ * destination pointers to reference the same memory buffer.
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup BasicAbs
+ * @{
+ */
+
+/**
+ * @brief Floating-point vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_abs_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t in1, in2, in3, in4; /* temporary variables */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = |A| */
+ /* Calculate absolute and then store the results in the destination buffer. */
+ /* read sample from source */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+ in3 = *(pSrc + 2);
+
+ /* find absolute value */
+ in1 = fabsf(in1);
+
+ /* read sample from source */
+ in4 = *(pSrc + 3);
+
+ /* find absolute value */
+ in2 = fabsf(in2);
+
+ /* read sample from source */
+ *pDst = in1;
+
+ /* find absolute value */
+ in3 = fabsf(in3);
+
+ /* find absolute value */
+ in4 = fabsf(in4);
+
+ /* store result to destination */
+ *(pDst + 1) = in2;
+
+ /* store result to destination */
+ *(pDst + 2) = in3;
+
+ /* store result to destination */
+ *(pDst + 3) = in4;
+
+
+ /* Update source pointer to process next sampels */
+ pSrc += 4U;
+
+ /* Update destination pointer to process next sampels */
+ pDst += 4U;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = |A| */
+ /* Calculate absolute and then store the results in the destination buffer. */
+ *pDst++ = fabsf(*pSrc++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicAbs group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.c
new file mode 100644
index 0000000..4bed8cc
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.c
@@ -0,0 +1,167 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_abs_q15.c
+ * Description: Q15 vector absolute value
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicAbs
+ * @{
+ */
+
+/**
+ * @brief Q15 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF.
+ */
+
+void arm_abs_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+ __SIMD32_TYPE *simd;
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q15_t in1; /* Input value1 */
+ q15_t in2; /* Input value2 */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ simd = __SIMD32_CONST(pDst);
+ while (blkCnt > 0U)
+ {
+ /* C = |A| */
+ /* Read two inputs */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+
+
+ /* Store the Absolute result in the destination buffer by packing the two values, in a single cycle */
+#ifndef ARM_MATH_BIG_ENDIAN
+ *simd++ =
+ __PKHBT(((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)),
+ ((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)), 16);
+
+#else
+
+
+ *simd++ =
+ __PKHBT(((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)),
+ ((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *simd++ =
+ __PKHBT(((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)),
+ ((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)), 16);
+
+#else
+
+
+ *simd++ =
+ __PKHBT(((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)),
+ ((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ pDst = (q15_t *)simd;
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = |A| */
+ /* Read the input */
+ in1 = *pSrc++;
+
+ /* Calculate absolute value of input and then store the result in the destination buffer. */
+ *pDst++ = (in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q15_t in; /* Temporary input variable */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* C = |A| */
+ /* Read the input */
+ in = *pSrc++;
+
+ /* Calculate absolute value of input and then store the result in the destination buffer. */
+ *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of BasicAbs group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.c
new file mode 100644
index 0000000..25cd036
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.c
@@ -0,0 +1,118 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_abs_q31.c
+ * Description: Q31 vector absolute value
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicAbs
+ * @{
+ */
+
+
+/**
+ * @brief Q31 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF.
+ */
+
+void arm_abs_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+ q31_t in; /* Input value */
+
+#if defined (ARM_MATH_DSP)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2, in3, in4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = |A| */
+ /* Calculate absolute of input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ in3 = *pSrc++;
+ in4 = *pSrc++;
+
+ *pDst++ = (in1 > 0) ? in1 : (q31_t)__QSUB(0, in1);
+ *pDst++ = (in2 > 0) ? in2 : (q31_t)__QSUB(0, in2);
+ *pDst++ = (in3 > 0) ? in3 : (q31_t)__QSUB(0, in3);
+ *pDst++ = (in4 > 0) ? in4 : (q31_t)__QSUB(0, in4);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = |A| */
+ /* Calculate absolute value of the input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */
+ in = *pSrc++;
+ *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ * @} end of BasicAbs group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.c
new file mode 100644
index 0000000..1ab2a1c
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.c
@@ -0,0 +1,145 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_abs_q7.c
+ * Description: Q7 vector absolute value
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicAbs
+ * @{
+ */
+
+/**
+ * @brief Q7 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * \par Conditions for optimum performance
+ * Input and output buffers should be aligned by 32-bit
+ *
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F.
+ */
+
+void arm_abs_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+ q7_t in; /* Input value1 */
+
+#if defined (ARM_MATH_DSP)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2, in3, in4; /* temporary input variables */
+ q31_t out1, out2, out3, out4; /* temporary output variables */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = |A| */
+ /* Read inputs */
+ in1 = (q31_t) * pSrc;
+ in2 = (q31_t) * (pSrc + 1);
+ in3 = (q31_t) * (pSrc + 2);
+
+ /* find absolute value */
+ out1 = (in1 > 0) ? in1 : (q31_t)__QSUB8(0, in1);
+
+ /* read input */
+ in4 = (q31_t) * (pSrc + 3);
+
+ /* find absolute value */
+ out2 = (in2 > 0) ? in2 : (q31_t)__QSUB8(0, in2);
+
+ /* store result to destination */
+ *pDst = (q7_t) out1;
+
+ /* find absolute value */
+ out3 = (in3 > 0) ? in3 : (q31_t)__QSUB8(0, in3);
+
+ /* find absolute value */
+ out4 = (in4 > 0) ? in4 : (q31_t)__QSUB8(0, in4);
+
+ /* store result to destination */
+ *(pDst + 1) = (q7_t) out2;
+
+ /* store result to destination */
+ *(pDst + 2) = (q7_t) out3;
+
+ /* store result to destination */
+ *(pDst + 3) = (q7_t) out4;
+
+ /* update pointers to process next samples */
+ pSrc += 4U;
+ pDst += 4U;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+#else
+
+ /* Run the below code for Cortex-M0 */
+ blkCnt = blockSize;
+
+#endif /* #define ARM_MATH_CM0_FAMILY */
+
+ while (blkCnt > 0U)
+ {
+ /* C = |A| */
+ /* Read the input */
+ in = *pSrc++;
+
+ /* Store the Absolute result in the destination buffer */
+ *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? 0x7f : -in);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicAbs group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.c
new file mode 100644
index 0000000..4d1ac4d
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.c
@@ -0,0 +1,138 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_add_f32.c
+ * Description: Floating-point vector addition
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @defgroup BasicAdd Vector Addition
+ *
+ * Element-by-element addition of two vectors.
+ *
+ * <pre>
+ * pDst[n] = pSrcA[n] + pSrcB[n], 0 <= n < blockSize.
+ * </pre>
+ *
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup BasicAdd
+ * @{
+ */
+
+/**
+ * @brief Floating-point vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_add_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t inA1, inA2, inA3, inA4; /* temporary input variabels */
+ float32_t inB1, inB2, inB3, inB4; /* temporary input variables */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+
+ /* read four inputs from sourceA and four inputs from sourceB */
+ inA1 = *pSrcA;
+ inB1 = *pSrcB;
+ inA2 = *(pSrcA + 1);
+ inB2 = *(pSrcB + 1);
+ inA3 = *(pSrcA + 2);
+ inB3 = *(pSrcB + 2);
+ inA4 = *(pSrcA + 3);
+ inB4 = *(pSrcB + 3);
+
+ /* C = A + B */
+ /* add and store result to destination */
+ *pDst = inA1 + inB1;
+ *(pDst + 1) = inA2 + inB2;
+ *(pDst + 2) = inA3 + inB3;
+ *(pDst + 3) = inA4 + inB4;
+
+ /* update pointers to process next samples */
+ pSrcA += 4U;
+ pSrcB += 4U;
+ pDst += 4U;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ *pDst++ = (*pSrcA++) + (*pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicAdd group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.c
new file mode 100644
index 0000000..2a14c29
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.c
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_add_q15.c
+ * Description: Q15 vector addition
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicAdd
+ * @{
+ */
+
+/**
+ * @brief Q15 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ */
+
+void arm_add_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t inA1, inA2, inB1, inB2;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ inA1 = *__SIMD32(pSrcA)++;
+ inA2 = *__SIMD32(pSrcA)++;
+ inB1 = *__SIMD32(pSrcB)++;
+ inB2 = *__SIMD32(pSrcB)++;
+
+ *__SIMD32(pDst)++ = __QADD16(inA1, inB1);
+ *__SIMD32(pDst)++ = __QADD16(inA2, inB2);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ *pDst++ = (q15_t) __QADD16(*pSrcA++, *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ *pDst++ = (q15_t) __SSAT(((q31_t) * pSrcA++ + *pSrcB++), 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+
+}
+
+/**
+ * @} end of BasicAdd group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.c
new file mode 100644
index 0000000..7503e1a
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.c
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_add_q31.c
+ * Description: Q31 vector addition
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicAdd
+ * @{
+ */
+
+
+/**
+ * @brief Q31 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.
+ */
+
+void arm_add_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t inA1, inA2, inA3, inA4;
+ q31_t inB1, inB2, inB3, inB4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ inA1 = *pSrcA++;
+ inA2 = *pSrcA++;
+ inB1 = *pSrcB++;
+ inB2 = *pSrcB++;
+
+ inA3 = *pSrcA++;
+ inA4 = *pSrcA++;
+ inB3 = *pSrcB++;
+ inB4 = *pSrcB++;
+
+ *pDst++ = __QADD(inA1, inB1);
+ *pDst++ = __QADD(inA2, inB2);
+ *pDst++ = __QADD(inA3, inB3);
+ *pDst++ = __QADD(inA4, inB4);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ *pDst++ = __QADD(*pSrcA++, *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrcA++ + *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of BasicAdd group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.c
new file mode 100644
index 0000000..fee1865
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.c
@@ -0,0 +1,122 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_add_q7.c
+ * Description: Q7 vector addition
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicAdd
+ * @{
+ */
+
+/**
+ * @brief Q7 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.
+ */
+
+void arm_add_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ *__SIMD32(pDst)++ = __QADD8(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ *pDst++ = (q7_t) __SSAT(*pSrcA++ + *pSrcB++, 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ *pDst++ = (q7_t) __SSAT((q15_t) * pSrcA++ + *pSrcB++, 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+
+}
+
+/**
+ * @} end of BasicAdd group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.c
new file mode 100644
index 0000000..6c7aae1
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.c
@@ -0,0 +1,123 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_dot_prod_f32.c
+ * Description: Floating-point dot product
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @defgroup dot_prod Vector Dot Product
+ *
+ * Computes the dot product of two vectors.
+ * The vectors are multiplied element-by-element and then summed.
+ *
+ * <pre>
+ * sum = pSrcA[0]*pSrcB[0] + pSrcA[1]*pSrcB[1] + ... + pSrcA[blockSize-1]*pSrcB[blockSize-1]
+ * </pre>
+ *
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup dot_prod
+ * @{
+ */
+
+/**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+
+void arm_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result)
+{
+ float32_t sum = 0.0f; /* Temporary result storage */
+ uint32_t blkCnt; /* loop counter */
+
+
+#if defined (ARM_MATH_DSP)
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Calculate dot product and then store the result in a temporary buffer */
+ sum += (*pSrcA++) * (*pSrcB++);
+ sum += (*pSrcA++) * (*pSrcB++);
+ sum += (*pSrcA++) * (*pSrcB++);
+ sum += (*pSrcA++) * (*pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Calculate dot product and then store the result in a temporary buffer. */
+ sum += (*pSrcA++) * (*pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ /* Store the result back in the destination buffer */
+ *result = sum;
+}
+
+/**
+ * @} end of dot_prod group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.c
new file mode 100644
index 0000000..6a48242
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.c
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_dot_prod_q15.c
+ * Description: Q15 dot product
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup dot_prod
+ * @{
+ */
+
+/**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The intermediate multiplications are in 1.15 x 1.15 = 2.30 format and these
+ * results are added to a 64-bit accumulator in 34.30 format.
+ * Nonsaturating additions are used and given that there are 33 guard bits in the accumulator
+ * there is no risk of overflow.
+ * The return result is in 34.30 format.
+ */
+
+void arm_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result)
+{
+ q63_t sum = 0; /* Temporary result storage */
+ uint32_t blkCnt; /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Calculate dot product and then store the result in a temporary buffer. */
+ sum = __SMLALD(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++, sum);
+ sum = __SMLALD(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++, sum);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Calculate dot product and then store the results in a temporary buffer. */
+ sum = __SMLALD(*pSrcA++, *pSrcB++, sum);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Calculate dot product and then store the results in a temporary buffer. */
+ sum += (q63_t) ((q31_t) * pSrcA++ * *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ /* Store the result in the destination buffer in 34.30 format */
+ *result = sum;
+
+}
+
+/**
+ * @} end of dot_prod group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.c
new file mode 100644
index 0000000..e739879
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.c
@@ -0,0 +1,131 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_dot_prod_q31.c
+ * Description: Q31 dot product
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup dot_prod
+ * @{
+ */
+
+/**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The intermediate multiplications are in 1.31 x 1.31 = 2.62 format and these
+ * are truncated to 2.48 format by discarding the lower 14 bits.
+ * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format.
+ * There are 15 guard bits in the accumulator and there is no risk of overflow as long as
+ * the length of the vectors is less than 2^16 elements.
+ * The return result is in 16.48 format.
+ */
+
+void arm_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result)
+{
+ q63_t sum = 0; /* Temporary result storage */
+ uint32_t blkCnt; /* loop counter */
+
+
+#if defined (ARM_MATH_DSP)
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t inA1, inA2, inA3, inA4;
+ q31_t inB1, inB2, inB3, inB4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Calculate dot product and then store the result in a temporary buffer. */
+ inA1 = *pSrcA++;
+ inA2 = *pSrcA++;
+ inA3 = *pSrcA++;
+ inA4 = *pSrcA++;
+ inB1 = *pSrcB++;
+ inB2 = *pSrcB++;
+ inB3 = *pSrcB++;
+ inB4 = *pSrcB++;
+
+ sum += ((q63_t) inA1 * inB1) >> 14U;
+ sum += ((q63_t) inA2 * inB2) >> 14U;
+ sum += ((q63_t) inA3 * inB3) >> 14U;
+ sum += ((q63_t) inA4 * inB4) >> 14U;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Calculate dot product and then store the result in a temporary buffer. */
+ sum += ((q63_t) * pSrcA++ * *pSrcB++) >> 14U;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Store the result in the destination buffer in 16.48 format */
+ *result = sum;
+}
+
+/**
+ * @} end of dot_prod group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.c
new file mode 100644
index 0000000..ef08038
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.c
@@ -0,0 +1,147 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_dot_prod_q7.c
+ * Description: Q7 dot product
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup dot_prod
+ * @{
+ */
+
+/**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The intermediate multiplications are in 1.7 x 1.7 = 2.14 format and these
+ * results are added to an accumulator in 18.14 format.
+ * Nonsaturating additions are used and there is no danger of wrap around as long as
+ * the vectors are less than 2^18 elements long.
+ * The return result is in 18.14 format.
+ */
+
+void arm_dot_prod_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result)
+{
+ uint32_t blkCnt; /* loop counter */
+
+ q31_t sum = 0; /* Temporary variables to store output */
+
+#if defined (ARM_MATH_DSP)
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t input1, input2; /* Temporary variables to store input */
+ q31_t inA1, inA2, inB1, inB2; /* Temporary variables to store input */
+
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* read 4 samples at a time from sourceA */
+ input1 = *__SIMD32(pSrcA)++;
+ /* read 4 samples at a time from sourceB */
+ input2 = *__SIMD32(pSrcB)++;
+
+ /* extract two q7_t samples to q15_t samples */
+ inA1 = __SXTB16(__ROR(input1, 8));
+ /* extract reminaing two samples */
+ inA2 = __SXTB16(input1);
+ /* extract two q7_t samples to q15_t samples */
+ inB1 = __SXTB16(__ROR(input2, 8));
+ /* extract reminaing two samples */
+ inB2 = __SXTB16(input2);
+
+ /* multiply and accumulate two samples at a time */
+ sum = __SMLAD(inA1, inB1, sum);
+ sum = __SMLAD(inA2, inB2, sum);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Dot product and then store the results in a temporary buffer. */
+ sum = __SMLAD(*pSrcA++, *pSrcB++, sum);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Dot product and then store the results in a temporary buffer. */
+ sum += (q31_t) ((q15_t) * pSrcA++ * *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+
+ /* Store the result in the destination buffer in 18.14 format */
+ *result = sum;
+}
+
+/**
+ * @} end of dot_prod group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.c
new file mode 100644
index 0000000..334e32b
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.c
@@ -0,0 +1,162 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_mult_f32.c
+ * Description: Floating-point vector multiplication
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @defgroup BasicMult Vector Multiplication
+ *
+ * Element-by-element multiplication of two vectors.
+ *
+ * <pre>
+ * pDst[n] = pSrcA[n] * pSrcB[n], 0 <= n < blockSize.
+ * </pre>
+ *
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup BasicMult
+ * @{
+ */
+
+/**
+ * @brief Floating-point vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_mult_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counters */
+#if defined (ARM_MATH_DSP)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t inA1, inA2, inA3, inA4; /* temporary input variables */
+ float32_t inB1, inB2, inB3, inB4; /* temporary input variables */
+ float32_t out1, out2, out3, out4; /* temporary output variables */
+
+ /* loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = A * B */
+ /* Multiply the inputs and store the results in output buffer */
+ /* read sample from sourceA */
+ inA1 = *pSrcA;
+ /* read sample from sourceB */
+ inB1 = *pSrcB;
+ /* read sample from sourceA */
+ inA2 = *(pSrcA + 1);
+ /* read sample from sourceB */
+ inB2 = *(pSrcB + 1);
+
+ /* out = sourceA * sourceB */
+ out1 = inA1 * inB1;
+
+ /* read sample from sourceA */
+ inA3 = *(pSrcA + 2);
+ /* read sample from sourceB */
+ inB3 = *(pSrcB + 2);
+
+ /* out = sourceA * sourceB */
+ out2 = inA2 * inB2;
+
+ /* read sample from sourceA */
+ inA4 = *(pSrcA + 3);
+
+ /* store result to destination buffer */
+ *pDst = out1;
+
+ /* read sample from sourceB */
+ inB4 = *(pSrcB + 3);
+
+ /* out = sourceA * sourceB */
+ out3 = inA3 * inB3;
+
+ /* store result to destination buffer */
+ *(pDst + 1) = out2;
+
+ /* out = sourceA * sourceB */
+ out4 = inA4 * inB4;
+ /* store result to destination buffer */
+ *(pDst + 2) = out3;
+ /* store result to destination buffer */
+ *(pDst + 3) = out4;
+
+
+ /* update pointers to process next samples */
+ pSrcA += 4U;
+ pSrcB += 4U;
+ pDst += 4U;
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A * B */
+ /* Multiply the inputs and store the results in output buffer */
+ *pDst++ = (*pSrcA++) * (*pSrcB++);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicMult group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.c
new file mode 100644
index 0000000..f3039d2
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.c
@@ -0,0 +1,142 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_mult_q15.c
+ * Description: Q15 vector multiplication
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicMult
+ * @{
+ */
+
+
+/**
+ * @brief Q15 vector multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ */
+
+void arm_mult_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counters */
+
+#if defined (ARM_MATH_DSP)
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t inA1, inA2, inB1, inB2; /* temporary input variables */
+ q15_t out1, out2, out3, out4; /* temporary output variables */
+ q31_t mul1, mul2, mul3, mul4; /* temporary variables */
+
+ /* loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* read two samples at a time from sourceA */
+ inA1 = *__SIMD32(pSrcA)++;
+ /* read two samples at a time from sourceB */
+ inB1 = *__SIMD32(pSrcB)++;
+ /* read two samples at a time from sourceA */
+ inA2 = *__SIMD32(pSrcA)++;
+ /* read two samples at a time from sourceB */
+ inB2 = *__SIMD32(pSrcB)++;
+
+ /* multiply mul = sourceA * sourceB */
+ mul1 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
+ mul2 = (q31_t) ((q15_t) inA1 * (q15_t) inB1);
+ mul3 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB2 >> 16));
+ mul4 = (q31_t) ((q15_t) inA2 * (q15_t) inB2);
+
+ /* saturate result to 16 bit */
+ out1 = (q15_t) __SSAT(mul1 >> 15, 16);
+ out2 = (q15_t) __SSAT(mul2 >> 15, 16);
+ out3 = (q15_t) __SSAT(mul3 >> 15, 16);
+ out4 = (q15_t) __SSAT(mul4 >> 15, 16);
+
+ /* store the result */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ = __PKHBT(out2, out1, 16);
+ *__SIMD32(pDst)++ = __PKHBT(out4, out3, 16);
+
+#else
+
+ *__SIMD32(pDst)++ = __PKHBT(out2, out1, 16);
+ *__SIMD32(pDst)++ = __PKHBT(out4, out3, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+
+ while (blkCnt > 0U)
+ {
+ /* C = A * B */
+ /* Multiply the inputs and store the result in the destination buffer */
+ *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicMult group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.c
new file mode 100644
index 0000000..93f0c73
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.c
@@ -0,0 +1,148 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_mult_q31.c
+ * Description: Q31 vector multiplication
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicMult
+ * @{
+ */
+
+/**
+ * @brief Q31 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.
+ */
+
+void arm_mult_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counters */
+
+#if defined (ARM_MATH_DSP)
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t inA1, inA2, inA3, inA4; /* temporary input variables */
+ q31_t inB1, inB2, inB3, inB4; /* temporary input variables */
+ q31_t out1, out2, out3, out4; /* temporary output variables */
+
+ /* loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = A * B */
+ /* Multiply the inputs and then store the results in the destination buffer. */
+ inA1 = *pSrcA++;
+ inA2 = *pSrcA++;
+ inA3 = *pSrcA++;
+ inA4 = *pSrcA++;
+ inB1 = *pSrcB++;
+ inB2 = *pSrcB++;
+ inB3 = *pSrcB++;
+ inB4 = *pSrcB++;
+
+ out1 = ((q63_t) inA1 * inB1) >> 32;
+ out2 = ((q63_t) inA2 * inB2) >> 32;
+ out3 = ((q63_t) inA3 * inB3) >> 32;
+ out4 = ((q63_t) inA4 * inB4) >> 32;
+
+ out1 = __SSAT(out1, 31);
+ out2 = __SSAT(out2, 31);
+ out3 = __SSAT(out3, 31);
+ out4 = __SSAT(out4, 31);
+
+ *pDst++ = out1 << 1U;
+ *pDst++ = out2 << 1U;
+ *pDst++ = out3 << 1U;
+ *pDst++ = out4 << 1U;
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A * B */
+ /* Multiply the inputs and then store the results in the destination buffer. */
+ inA1 = *pSrcA++;
+ inB1 = *pSrcB++;
+ out1 = ((q63_t) inA1 * inB1) >> 32;
+ out1 = __SSAT(out1, 31);
+ *pDst++ = out1 << 1U;
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+
+ while (blkCnt > 0U)
+ {
+ /* C = A * B */
+ /* Multiply the inputs and then store the results in the destination buffer. */
+ *pDst++ =
+ (q31_t) clip_q63_to_q31(((q63_t) (*pSrcA++) * (*pSrcB++)) >> 31);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+}
+
+/**
+ * @} end of BasicMult group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.c
new file mode 100644
index 0000000..e5a8f24
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.c
@@ -0,0 +1,115 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_mult_q7.c
+ * Description: Q7 vector multiplication
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicMult
+ * @{
+ */
+
+/**
+ * @brief Q7 vector multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.
+ */
+
+void arm_mult_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counters */
+
+#if defined (ARM_MATH_DSP)
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q7_t out1, out2, out3, out4; /* Temporary variables to store the product */
+
+ /* loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = A * B */
+ /* Multiply the inputs and store the results in temporary variables */
+ out1 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+ out2 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+ out3 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+ out4 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+
+ /* Store the results of 4 inputs in the destination buffer in single cycle by packing */
+ *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+
+ while (blkCnt > 0U)
+ {
+ /* C = A * B */
+ /* Multiply the inputs and store the result in the destination buffer */
+ *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicMult group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.c
new file mode 100644
index 0000000..d463885
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.c
@@ -0,0 +1,134 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_negate_f32.c
+ * Description: Negates floating-point vectors
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @defgroup negate Vector Negate
+ *
+ * Negates the elements of a vector.
+ *
+ * <pre>
+ * pDst[n] = -pSrc[n], 0 <= n < blockSize.
+ * </pre>
+ *
+ * The functions support in-place computation allowing the source and
+ * destination pointers to reference the same memory buffer.
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup negate
+ * @{
+ */
+
+/**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_negate_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+
+#if defined (ARM_MATH_DSP)
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t in1, in2, in3, in4; /* temporary variables */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* read inputs from source */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+ in3 = *(pSrc + 2);
+ in4 = *(pSrc + 3);
+
+ /* negate the input */
+ in1 = -in1;
+ in2 = -in2;
+ in3 = -in3;
+ in4 = -in4;
+
+ /* store the result to destination */
+ *pDst = in1;
+ *(pDst + 1) = in2;
+ *(pDst + 2) = in3;
+ *(pDst + 3) = in4;
+
+ /* update pointers to process next samples */
+ pSrc += 4U;
+ pDst += 4U;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = -A */
+ /* Negate and then store the results in the destination buffer. */
+ *pDst++ = -*pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of negate group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.c
new file mode 100644
index 0000000..0820f30
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.c
@@ -0,0 +1,131 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_negate_q15.c
+ * Description: Negates Q15 vectors
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup negate
+ * @{
+ */
+
+/**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * \par Conditions for optimum performance
+ * Input and output buffers should be aligned by 32-bit
+ *
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF.
+ */
+
+void arm_negate_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+ q15_t in;
+
+#if defined (ARM_MATH_DSP)
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t in1, in2; /* Temporary variables */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = -A */
+ /* Read two inputs at a time */
+ in1 = _SIMD32_OFFSET(pSrc);
+ in2 = _SIMD32_OFFSET(pSrc + 2);
+
+ /* negate two samples at a time */
+ in1 = __QSUB16(0, in1);
+
+ /* negate two samples at a time */
+ in2 = __QSUB16(0, in2);
+
+ /* store the result to destination 2 samples at a time */
+ _SIMD32_OFFSET(pDst) = in1;
+ /* store the result to destination 2 samples at a time */
+ _SIMD32_OFFSET(pDst + 2) = in2;
+
+
+ /* update pointers to process next samples */
+ pSrc += 4U;
+ pDst += 4U;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = -A */
+ /* Negate and then store the result in the destination buffer. */
+ in = *pSrc++;
+ *pDst++ = (in == (q15_t) 0x8000) ? 0x7fff : -in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of negate group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.c
new file mode 100644
index 0000000..ab5985a
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.c
@@ -0,0 +1,117 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_negate_q31.c
+ * Description: Negates Q31 vectors
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup negate
+ * @{
+ */
+
+/**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF.
+ */
+
+void arm_negate_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t in; /* Temporary variable */
+ uint32_t blkCnt; /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2, in3, in4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = -A */
+ /* Negate and then store the results in the destination buffer. */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ in3 = *pSrc++;
+ in4 = *pSrc++;
+
+ *pDst++ = __QSUB(0, in1);
+ *pDst++ = __QSUB(0, in2);
+ *pDst++ = __QSUB(0, in3);
+ *pDst++ = __QSUB(0, in4);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+
+ while (blkCnt > 0U)
+ {
+ /* C = -A */
+ /* Negate and then store the result in the destination buffer. */
+ in = *pSrc++;
+ *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of negate group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.c
new file mode 100644
index 0000000..b225c5e
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.c
@@ -0,0 +1,113 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_negate_q7.c
+ * Description: Negates Q7 vectors
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup negate
+ * @{
+ */
+
+/**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F.
+ */
+
+void arm_negate_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+ q7_t in;
+
+#if defined (ARM_MATH_DSP)
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t input; /* Input values1-4 */
+ q31_t zero = 0x00000000;
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = -A */
+ /* Read four inputs */
+ input = *__SIMD32(pSrc)++;
+
+ /* Store the Negated results in the destination buffer in a single cycle by packing the results */
+ *__SIMD32(pDst)++ = __QSUB8(zero, input);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = -A */
+ /* Negate and then store the results in the destination buffer. */ \
+ in = *pSrc++;
+ *pDst++ = (in == (q7_t) 0x80) ? 0x7f : -in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of negate group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.c
new file mode 100644
index 0000000..c35fe8e
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.c
@@ -0,0 +1,154 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_offset_f32.c
+ * Description: Floating-point vector offset
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @defgroup offset Vector Offset
+ *
+ * Adds a constant offset to each element of a vector.
+ *
+ * <pre>
+ * pDst[n] = pSrc[n] + offset, 0 <= n < blockSize.
+ * </pre>
+ *
+ * The functions support in-place computation allowing the source and
+ * destination pointers to reference the same memory buffer.
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup offset
+ * @{
+ */
+
+/**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+
+void arm_offset_f32(
+ float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t in1, in2, in3, in4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the results in the destination buffer. */
+ /* read samples from source */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+
+ /* add offset to input */
+ in1 = in1 + offset;
+
+ /* read samples from source */
+ in3 = *(pSrc + 2);
+
+ /* add offset to input */
+ in2 = in2 + offset;
+
+ /* read samples from source */
+ in4 = *(pSrc + 3);
+
+ /* add offset to input */
+ in3 = in3 + offset;
+
+ /* store result to destination */
+ *pDst = in1;
+
+ /* add offset to input */
+ in4 = in4 + offset;
+
+ /* store result to destination */
+ *(pDst + 1) = in2;
+
+ /* store result to destination */
+ *(pDst + 2) = in3;
+
+ /* store result to destination */
+ *(pDst + 3) = in4;
+
+ /* update pointers to process next samples */
+ pSrc += 4U;
+ pDst += 4U;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the result in the destination buffer. */
+ *pDst++ = (*pSrc++) + offset;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of offset group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.c
new file mode 100644
index 0000000..4c16224
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.c
@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_offset_q15.c
+ * Description: Q15 vector offset
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup offset
+ * @{
+ */
+
+/**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated.
+ */
+
+void arm_offset_q15(
+ q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t offset_packed; /* Offset packed to 32 bit */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+ /* Offset is packed to 32 bit in order to use SIMD32 for addition */
+ offset_packed = __PKHBT(offset, offset, 16);
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the results in the destination buffer, 2 samples at a time. */
+ *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrc)++, offset_packed);
+ *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrc)++, offset_packed);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the results in the destination buffer. */
+ *pDst++ = (q15_t) __QADD16(*pSrc++, offset);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the results in the destination buffer. */
+ *pDst++ = (q15_t) __SSAT(((q31_t) * pSrc++ + offset), 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of offset group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.c
new file mode 100644
index 0000000..0b0ee32
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.c
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_offset_q31.c
+ * Description: Q31 vector offset
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup offset
+ * @{
+ */
+
+/**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated.
+ */
+
+void arm_offset_q31(
+ q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2, in3, in4;
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the results in the destination buffer. */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ in3 = *pSrc++;
+ in4 = *pSrc++;
+
+ *pDst++ = __QADD(in1, offset);
+ *pDst++ = __QADD(in2, offset);
+ *pDst++ = __QADD(in3, offset);
+ *pDst++ = __QADD(in4, offset);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the result in the destination buffer. */
+ *pDst++ = __QADD(*pSrc++, offset);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the result in the destination buffer. */
+ *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrc++ + offset);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of offset group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.c
new file mode 100644
index 0000000..5b98951
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.c
@@ -0,0 +1,123 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_offset_q7.c
+ * Description: Q7 vector offset
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup offset
+ * @{
+ */
+
+/**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q7 range [0x80 0x7F] are saturated.
+ */
+
+void arm_offset_q7(
+ q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t offset_packed; /* Offset packed to 32 bit */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+ /* Offset is packed to 32 bit in order to use SIMD32 for addition */
+ offset_packed = __PACKq7(offset, offset, offset, offset);
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the results in the destination bufferfor 4 samples at a time. */
+ *__SIMD32(pDst)++ = __QADD8(*__SIMD32(pSrc)++, offset_packed);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the result in the destination buffer. */
+ *pDst++ = (q7_t) __SSAT(*pSrc++ + offset, 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the result in the destination buffer. */
+ *pDst++ = (q7_t) __SSAT((q15_t) * pSrc++ + offset, 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of offset group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.c
new file mode 100644
index 0000000..0fc3204
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.c
@@ -0,0 +1,157 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_scale_f32.c
+ * Description: Multiplies a floating-point vector by a scalar
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @defgroup scale Vector Scale
+ *
+ * Multiply a vector by a scalar value. For floating-point data, the algorithm used is:
+ *
+ * <pre>
+ * pDst[n] = pSrc[n] * scale, 0 <= n < blockSize.
+ * </pre>
+ *
+ * In the fixed-point Q7, Q15, and Q31 functions, <code>scale</code> is represented by
+ * a fractional multiplication <code>scaleFract</code> and an arithmetic shift <code>shift</code>.
+ * The shift allows the gain of the scaling operation to exceed 1.0.
+ * The algorithm used with fixed-point data is:
+ *
+ * <pre>
+ * pDst[n] = (pSrc[n] * scaleFract) << shift, 0 <= n < blockSize.
+ * </pre>
+ *
+ * The overall scale factor applied to the fixed-point data is
+ * <pre>
+ * scale = scaleFract * 2^shift.
+ * </pre>
+ *
+ * The functions support in-place computation allowing the source and destination
+ * pointers to reference the same memory buffer.
+ */
+
+/**
+ * @addtogroup scale
+ * @{
+ */
+
+/**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+
+void arm_scale_f32(
+ float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+#if defined (ARM_MATH_DSP)
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t in1, in2, in3, in4; /* temporary variabels */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = A * scale */
+ /* Scale the input and then store the results in the destination buffer. */
+ /* read input samples from source */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+
+ /* multiply with scaling factor */
+ in1 = in1 * scale;
+
+ /* read input sample from source */
+ in3 = *(pSrc + 2);
+
+ /* multiply with scaling factor */
+ in2 = in2 * scale;
+
+ /* read input sample from source */
+ in4 = *(pSrc + 3);
+
+ /* multiply with scaling factor */
+ in3 = in3 * scale;
+ in4 = in4 * scale;
+ /* store the result to destination */
+ *pDst = in1;
+ *(pDst + 1) = in2;
+ *(pDst + 2) = in3;
+ *(pDst + 3) = in4;
+
+ /* update pointers to process next samples */
+ pSrc += 4U;
+ pDst += 4U;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A * scale */
+ /* Scale the input and then store the result in the destination buffer. */
+ *pDst++ = (*pSrc++) * scale;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of scale group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.c
new file mode 100644
index 0000000..f1d3063
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.c
@@ -0,0 +1,150 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_scale_q15.c
+ * Description: Multiplies a Q15 vector by a scalar
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup scale
+ * @{
+ */
+
+/**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The input data <code>*pSrc</code> and <code>scaleFract</code> are in 1.15 format.
+ * These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format.
+ */
+
+
+void arm_scale_q15(
+ q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ int8_t kShift = 15 - shift; /* shift to apply after scaling */
+ uint32_t blkCnt; /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q15_t in1, in2, in3, in4;
+ q31_t inA1, inA2; /* Temporary variables */
+ q31_t out1, out2, out3, out4;
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* Reading 2 inputs from memory */
+ inA1 = *__SIMD32(pSrc)++;
+ inA2 = *__SIMD32(pSrc)++;
+
+ /* C = A * scale */
+ /* Scale the inputs and then store the 2 results in the destination buffer
+ * in single cycle by packing the outputs */
+ out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract);
+ out2 = (q31_t) ((q15_t) inA1 * scaleFract);
+ out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract);
+ out4 = (q31_t) ((q15_t) inA2 * scaleFract);
+
+ /* apply shifting */
+ out1 = out1 >> kShift;
+ out2 = out2 >> kShift;
+ out3 = out3 >> kShift;
+ out4 = out4 >> kShift;
+
+ /* saturate the output */
+ in1 = (q15_t) (__SSAT(out1, 16));
+ in2 = (q15_t) (__SSAT(out2, 16));
+ in3 = (q15_t) (__SSAT(out3, 16));
+ in4 = (q15_t) (__SSAT(out4, 16));
+
+ /* store the result to destination */
+ *__SIMD32(pDst)++ = __PKHBT(in2, in1, 16);
+ *__SIMD32(pDst)++ = __PKHBT(in4, in3, 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A * scale */
+ /* Scale the input and then store the result in the destination buffer. */
+ *pDst++ = (q15_t) (__SSAT(((*pSrc++) * scaleFract) >> kShift, 16));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A * scale */
+ /* Scale the input and then store the result in the destination buffer. */
+ *pDst++ = (q15_t) (__SSAT(((q31_t) * pSrc++ * scaleFract) >> kShift, 16));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of scale group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.c
new file mode 100644
index 0000000..dcc7bbe
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.c
@@ -0,0 +1,227 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_scale_q31.c
+ * Description: Multiplies a Q31 vector by a scalar
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup scale
+ * @{
+ */
+
+/**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The input data <code>*pSrc</code> and <code>scaleFract</code> are in 1.31 format.
+ * These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format.
+ */
+
+void arm_scale_q31(
+ q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ int8_t kShift = shift + 1; /* Shift to apply after scaling */
+ int8_t sign = (kShift & 0x80);
+ uint32_t blkCnt; /* loop counter */
+ q31_t in, out;
+
+#if defined (ARM_MATH_DSP)
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t in1, in2, in3, in4; /* temporary input variables */
+ q31_t out1, out2, out3, out4; /* temporary output variabels */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+ if (sign == 0U)
+ {
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* read four inputs from source */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+ in3 = *(pSrc + 2);
+ in4 = *(pSrc + 3);
+
+ /* multiply input with scaler value */
+ in1 = ((q63_t) in1 * scaleFract) >> 32;
+ in2 = ((q63_t) in2 * scaleFract) >> 32;
+ in3 = ((q63_t) in3 * scaleFract) >> 32;
+ in4 = ((q63_t) in4 * scaleFract) >> 32;
+
+ /* apply shifting */
+ out1 = in1 << kShift;
+ out2 = in2 << kShift;
+
+ /* saturate the results. */
+ if (in1 != (out1 >> kShift))
+ out1 = 0x7FFFFFFF ^ (in1 >> 31);
+
+ if (in2 != (out2 >> kShift))
+ out2 = 0x7FFFFFFF ^ (in2 >> 31);
+
+ out3 = in3 << kShift;
+ out4 = in4 << kShift;
+
+ *pDst = out1;
+ *(pDst + 1) = out2;
+
+ if (in3 != (out3 >> kShift))
+ out3 = 0x7FFFFFFF ^ (in3 >> 31);
+
+ if (in4 != (out4 >> kShift))
+ out4 = 0x7FFFFFFF ^ (in4 >> 31);
+
+ /* Store result destination */
+ *(pDst + 2) = out3;
+ *(pDst + 3) = out4;
+
+ /* Update pointers to process next sampels */
+ pSrc += 4U;
+ pDst += 4U;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ }
+ else
+ {
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* read four inputs from source */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+ in3 = *(pSrc + 2);
+ in4 = *(pSrc + 3);
+
+ /* multiply input with scaler value */
+ in1 = ((q63_t) in1 * scaleFract) >> 32;
+ in2 = ((q63_t) in2 * scaleFract) >> 32;
+ in3 = ((q63_t) in3 * scaleFract) >> 32;
+ in4 = ((q63_t) in4 * scaleFract) >> 32;
+
+ /* apply shifting */
+ out1 = in1 >> -kShift;
+ out2 = in2 >> -kShift;
+
+ out3 = in3 >> -kShift;
+ out4 = in4 >> -kShift;
+
+ /* Store result destination */
+ *pDst = out1;
+ *(pDst + 1) = out2;
+
+ *(pDst + 2) = out3;
+ *(pDst + 3) = out4;
+
+ /* Update pointers to process next sampels */
+ pSrc += 4U;
+ pDst += 4U;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ if (sign == 0)
+ {
+ while (blkCnt > 0U)
+ {
+ /* C = A * scale */
+ /* Scale the input and then store the result in the destination buffer. */
+ in = *pSrc++;
+ in = ((q63_t) in * scaleFract) >> 32;
+
+ out = in << kShift;
+
+ if (in != (out >> kShift))
+ out = 0x7FFFFFFF ^ (in >> 31);
+
+ *pDst++ = out;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ while (blkCnt > 0U)
+ {
+ /* C = A * scale */
+ /* Scale the input and then store the result in the destination buffer. */
+ in = *pSrc++;
+ in = ((q63_t) in * scaleFract) >> 32;
+
+ out = in >> -kShift;
+
+ *pDst++ = out;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ }
+}
+
+/**
+ * @} end of scale group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.c
new file mode 100644
index 0000000..8c90396
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.c
@@ -0,0 +1,137 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_scale_q7.c
+ * Description: Multiplies a Q7 vector by a scalar
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup scale
+ * @{
+ */
+
+/**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The input data <code>*pSrc</code> and <code>scaleFract</code> are in 1.7 format.
+ * These are multiplied to yield a 2.14 intermediate result and this is shifted with saturation to 1.7 format.
+ */
+
+void arm_scale_q7(
+ q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ int8_t kShift = 7 - shift; /* shift to apply after scaling */
+ uint32_t blkCnt; /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q7_t in1, in2, in3, in4, out1, out2, out3, out4; /* Temporary variables to store input & output */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* Reading 4 inputs from memory */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ in3 = *pSrc++;
+ in4 = *pSrc++;
+
+ /* C = A * scale */
+ /* Scale the inputs and then store the results in the temporary variables. */
+ out1 = (q7_t) (__SSAT(((in1) * scaleFract) >> kShift, 8));
+ out2 = (q7_t) (__SSAT(((in2) * scaleFract) >> kShift, 8));
+ out3 = (q7_t) (__SSAT(((in3) * scaleFract) >> kShift, 8));
+ out4 = (q7_t) (__SSAT(((in4) * scaleFract) >> kShift, 8));
+
+ /* Packing the individual outputs into 32bit and storing in
+ * destination buffer in single write */
+ *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A * scale */
+ /* Scale the input and then store the result in the destination buffer. */
+ *pDst++ = (q7_t) (__SSAT(((*pSrc++) * scaleFract) >> kShift, 8));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A * scale */
+ /* Scale the input and then store the result in the destination buffer. */
+ *pDst++ = (q7_t) (__SSAT((((q15_t) * pSrc++ * scaleFract) >> kShift), 8));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of scale group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.c
new file mode 100644
index 0000000..9462ad7
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.c
@@ -0,0 +1,236 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_shift_q15.c
+ * Description: Shifts the elements of a Q15 vector by a specified number of bits
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup shift
+ * @{
+ */
+
+/**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ */
+
+void arm_shift_q15(
+ q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+ uint8_t sign; /* Sign of shiftBits */
+
+#if defined (ARM_MATH_DSP)
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q15_t in1, in2; /* Temporary variables */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+ /* Getting the sign of shiftBits */
+ sign = (shiftBits & 0x80);
+
+ /* If the shift value is positive then do right shift else left shift */
+ if (sign == 0U)
+ {
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* Read 2 inputs */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ /* C = A << shiftBits */
+ /* Shift the inputs and then store the results in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16),
+ __SSAT((in2 << shiftBits), 16), 16);
+
+#else
+
+ *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16),
+ __SSAT((in1 << shiftBits), 16), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16),
+ __SSAT((in2 << shiftBits), 16), 16);
+
+#else
+
+ *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16),
+ __SSAT((in1 << shiftBits), 16), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A << shiftBits */
+ /* Shift and then store the results in the destination buffer. */
+ *pDst++ = __SSAT((*pSrc++ << shiftBits), 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* Read 2 inputs */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+
+ /* C = A >> shiftBits */
+ /* Shift the inputs and then store the results in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits),
+ (in2 >> -shiftBits), 16);
+
+#else
+
+ *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits),
+ (in1 >> -shiftBits), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits),
+ (in2 >> -shiftBits), 16);
+
+#else
+
+ *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits),
+ (in1 >> -shiftBits), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A >> shiftBits */
+ /* Shift the inputs and then store the results in the destination buffer. */
+ *pDst++ = (*pSrc++ >> -shiftBits);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Getting the sign of shiftBits */
+ sign = (shiftBits & 0x80);
+
+ /* If the shift value is positive then do right shift else left shift */
+ if (sign == 0U)
+ {
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A << shiftBits */
+ /* Shift and then store the results in the destination buffer. */
+ *pDst++ = __SSAT(((q31_t) * pSrc++ << shiftBits), 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A >> shiftBits */
+ /* Shift the inputs and then store the results in the destination buffer. */
+ *pDst++ = (*pSrc++ >> -shiftBits);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of shift group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q31.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q31.c
new file mode 100644
index 0000000..12490a1
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q31.c
@@ -0,0 +1,191 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_shift_q31.c
+ * Description: Shifts the elements of a Q31 vector by a specified number of bits
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+/**
+ * @defgroup shift Vector Shift
+ *
+ * Shifts the elements of a fixed-point vector by a specified number of bits.
+ * There are separate functions for Q7, Q15, and Q31 data types.
+ * The underlying algorithm used is:
+ *
+ * <pre>
+ * pDst[n] = pSrc[n] << shift, 0 <= n < blockSize.
+ * </pre>
+ *
+ * If <code>shift</code> is positive then the elements of the vector are shifted to the left.
+ * If <code>shift</code> is negative then the elements of the vector are shifted to the right.
+ *
+ * The functions support in-place computation allowing the source and destination
+ * pointers to reference the same memory buffer.
+ */
+
+/**
+ * @addtogroup shift
+ * @{
+ */
+
+/**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.
+ */
+
+void arm_shift_q31(
+ q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+ uint8_t sign = (shiftBits & 0x80); /* Sign of shiftBits */
+
+#if defined (ARM_MATH_DSP)
+
+ q31_t in1, in2, in3, in4; /* Temporary input variables */
+ q31_t out1, out2, out3, out4; /* Temporary output variables */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+
+ if (sign == 0U)
+ {
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = A << shiftBits */
+ /* Shift the input and then store the results in the destination buffer. */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+ out1 = in1 << shiftBits;
+ in3 = *(pSrc + 2);
+ out2 = in2 << shiftBits;
+ in4 = *(pSrc + 3);
+ if (in1 != (out1 >> shiftBits))
+ out1 = 0x7FFFFFFF ^ (in1 >> 31);
+
+ if (in2 != (out2 >> shiftBits))
+ out2 = 0x7FFFFFFF ^ (in2 >> 31);
+
+ *pDst = out1;
+ out3 = in3 << shiftBits;
+ *(pDst + 1) = out2;
+ out4 = in4 << shiftBits;
+
+ if (in3 != (out3 >> shiftBits))
+ out3 = 0x7FFFFFFF ^ (in3 >> 31);
+
+ if (in4 != (out4 >> shiftBits))
+ out4 = 0x7FFFFFFF ^ (in4 >> 31);
+
+ *(pDst + 2) = out3;
+ *(pDst + 3) = out4;
+
+ /* Update destination pointer to process next sampels */
+ pSrc += 4U;
+ pDst += 4U;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = A >> shiftBits */
+ /* Shift the input and then store the results in the destination buffer. */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+ in3 = *(pSrc + 2);
+ in4 = *(pSrc + 3);
+
+ *pDst = (in1 >> -shiftBits);
+ *(pDst + 1) = (in2 >> -shiftBits);
+ *(pDst + 2) = (in3 >> -shiftBits);
+ *(pDst + 3) = (in4 >> -shiftBits);
+
+
+ pSrc += 4U;
+ pDst += 4U;
+
+ blkCnt--;
+ }
+
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+
+ while (blkCnt > 0U)
+ {
+ /* C = A (>> or <<) shiftBits */
+ /* Shift the input and then store the result in the destination buffer. */
+ *pDst++ = (sign == 0U) ? clip_q63_to_q31((q63_t) * pSrc++ << shiftBits) :
+ (*pSrc++ >> -shiftBits);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+}
+
+/**
+ * @} end of shift group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.c
new file mode 100644
index 0000000..6f40431
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.c
@@ -0,0 +1,208 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_shift_q7.c
+ * Description: Processing function for the Q7 Shifting
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup shift
+ * @{
+ */
+
+
+/**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * \par Conditions for optimum performance
+ * Input and output buffers should be aligned by 32-bit
+ *
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q7 range [0x8 0x7F] will be saturated.
+ */
+
+void arm_shift_q7(
+ q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+ uint8_t sign; /* Sign of shiftBits */
+
+#if defined (ARM_MATH_DSP)
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q7_t in1; /* Input value1 */
+ q7_t in2; /* Input value2 */
+ q7_t in3; /* Input value3 */
+ q7_t in4; /* Input value4 */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+ /* Getting the sign of shiftBits */
+ sign = (shiftBits & 0x80);
+
+ /* If the shift value is positive then do right shift else left shift */
+ if (sign == 0U)
+ {
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = A << shiftBits */
+ /* Read 4 inputs */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+ in3 = *(pSrc + 2);
+ in4 = *(pSrc + 3);
+
+ /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */
+ *__SIMD32(pDst)++ = __PACKq7(__SSAT((in1 << shiftBits), 8),
+ __SSAT((in2 << shiftBits), 8),
+ __SSAT((in3 << shiftBits), 8),
+ __SSAT((in4 << shiftBits), 8));
+ /* Update source pointer to process next sampels */
+ pSrc += 4U;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A << shiftBits */
+ /* Shift the input and then store the result in the destination buffer. */
+ *pDst++ = (q7_t) __SSAT((*pSrc++ << shiftBits), 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ shiftBits = -shiftBits;
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = A >> shiftBits */
+ /* Read 4 inputs */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+ in3 = *(pSrc + 2);
+ in4 = *(pSrc + 3);
+
+ /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */
+ *__SIMD32(pDst)++ = __PACKq7((in1 >> shiftBits), (in2 >> shiftBits),
+ (in3 >> shiftBits), (in4 >> shiftBits));
+
+
+ pSrc += 4U;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A >> shiftBits */
+ /* Shift the input and then store the result in the destination buffer. */
+ in1 = *pSrc++;
+ *pDst++ = (in1 >> shiftBits);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Getting the sign of shiftBits */
+ sign = (shiftBits & 0x80);
+
+ /* If the shift value is positive then do right shift else left shift */
+ if (sign == 0U)
+ {
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A << shiftBits */
+ /* Shift the input and then store the result in the destination buffer. */
+ *pDst++ = (q7_t) __SSAT(((q15_t) * pSrc++ << shiftBits), 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A >> shiftBits */
+ /* Shift the input and then store the result in the destination buffer. */
+ *pDst++ = (*pSrc++ >> -shiftBits);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+}
+
+/**
+ * @} end of shift group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.c
new file mode 100644
index 0000000..6d56fa7
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.c
@@ -0,0 +1,138 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_sub_f32.c
+ * Description: Floating-point vector subtraction.
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @defgroup BasicSub Vector Subtraction
+ *
+ * Element-by-element subtraction of two vectors.
+ *
+ * <pre>
+ * pDst[n] = pSrcA[n] - pSrcB[n], 0 <= n < blockSize.
+ * </pre>
+ *
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup BasicSub
+ * @{
+ */
+
+
+/**
+ * @brief Floating-point vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_sub_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t inA1, inA2, inA3, inA4; /* temporary variables */
+ float32_t inB1, inB2, inB3, inB4; /* temporary variables */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = A - B */
+ /* Subtract and then store the results in the destination buffer. */
+ /* Read 4 input samples from sourceA and sourceB */
+ inA1 = *pSrcA;
+ inB1 = *pSrcB;
+ inA2 = *(pSrcA + 1);
+ inB2 = *(pSrcB + 1);
+ inA3 = *(pSrcA + 2);
+ inB3 = *(pSrcB + 2);
+ inA4 = *(pSrcA + 3);
+ inB4 = *(pSrcB + 3);
+
+ /* dst = srcA - srcB */
+ /* subtract and store the result */
+ *pDst = inA1 - inB1;
+ *(pDst + 1) = inA2 - inB2;
+ *(pDst + 2) = inA3 - inB3;
+ *(pDst + 3) = inA4 - inB4;
+
+
+ /* Update pointers to process next sampels */
+ pSrcA += 4U;
+ pSrcB += 4U;
+ pDst += 4U;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A - B */
+ /* Subtract and then store the results in the destination buffer. */
+ *pDst++ = (*pSrcA++) - (*pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicSub group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.c
new file mode 100644
index 0000000..643f933
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.c
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_sub_q15.c
+ * Description: Q15 vector subtraction
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicSub
+ * @{
+ */
+
+/**
+ * @brief Q15 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ */
+
+void arm_sub_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+
+#if defined (ARM_MATH_DSP)
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t inA1, inA2;
+ q31_t inB1, inB2;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = A - B */
+ /* Subtract and then store the results in the destination buffer two samples at a time. */
+ inA1 = *__SIMD32(pSrcA)++;
+ inA2 = *__SIMD32(pSrcA)++;
+ inB1 = *__SIMD32(pSrcB)++;
+ inB2 = *__SIMD32(pSrcB)++;
+
+ *__SIMD32(pDst)++ = __QSUB16(inA1, inB1);
+ *__SIMD32(pDst)++ = __QSUB16(inA2, inB2);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A - B */
+ /* Subtract and then store the result in the destination buffer. */
+ *pDst++ = (q15_t) __QSUB16(*pSrcA++, *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A - B */
+ /* Subtract and then store the result in the destination buffer. */
+ *pDst++ = (q15_t) __SSAT(((q31_t) * pSrcA++ - *pSrcB++), 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+
+}
+
+/**
+ * @} end of BasicSub group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.c
new file mode 100644
index 0000000..1c83aae
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.c
@@ -0,0 +1,134 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_sub_q31.c
+ * Description: Q31 vector subtraction
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicSub
+ * @{
+ */
+
+/**
+ * @brief Q31 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.
+ */
+
+void arm_sub_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+
+#if defined (ARM_MATH_DSP)
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t inA1, inA2, inA3, inA4;
+ q31_t inB1, inB2, inB3, inB4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = A - B */
+ /* Subtract and then store the results in the destination buffer. */
+ inA1 = *pSrcA++;
+ inA2 = *pSrcA++;
+ inB1 = *pSrcB++;
+ inB2 = *pSrcB++;
+
+ inA3 = *pSrcA++;
+ inA4 = *pSrcA++;
+ inB3 = *pSrcB++;
+ inB4 = *pSrcB++;
+
+ *pDst++ = __QSUB(inA1, inB1);
+ *pDst++ = __QSUB(inA2, inB2);
+ *pDst++ = __QSUB(inA3, inB3);
+ *pDst++ = __QSUB(inA4, inB4);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A - B */
+ /* Subtract and then store the result in the destination buffer. */
+ *pDst++ = __QSUB(*pSrcA++, *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A - B */
+ /* Subtract and then store the result in the destination buffer. */
+ *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrcA++ - *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of BasicSub group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.c
new file mode 100644
index 0000000..8f8e111
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.c
@@ -0,0 +1,119 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_sub_q7.c
+ * Description: Q7 vector subtraction
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicSub
+ * @{
+ */
+
+/**
+ * @brief Q7 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.
+ */
+
+void arm_sub_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = A - B */
+ /* Subtract and then store the results in the destination buffer 4 samples at a time. */
+ *__SIMD32(pDst)++ = __QSUB8(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A - B */
+ /* Subtract and then store the result in the destination buffer. */
+ *pDst++ = __SSAT(*pSrcA++ - *pSrcB++, 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A - B */
+ /* Subtract and then store the result in the destination buffer. */
+ *pDst++ = (q7_t) __SSAT((q15_t) * pSrcA++ - *pSrcB++, 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+
+}
+
+/**
+ * @} end of BasicSub group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/CommonTables/arm_common_tables.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/CommonTables/arm_common_tables.c
new file mode 100644
index 0000000..bb5c15a
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/CommonTables/arm_common_tables.c
@@ -0,0 +1,22176 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_common_tables.c
+ * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup ComplexFFT
+ */
+
+/**
+ * @addtogroup CFFT_CIFFT Complex FFT Tables
+ * @{
+ */
+
+/**
+* \par
+* Pseudo code for Generation of Bit reversal Table is
+* \par
+* <pre>for(l=1;l <= N/4;l++)
+* {
+* for(i=0;i<logN2;i++)
+* {
+* a[i]=l&(1<<i);
+* }
+* for(j=0; j<logN2; j++)
+* {
+* if (a[j]!=0)
+* y[l]+=(1<<((logN2-1)-j));
+* }
+* y[l] = y[l] >> 1;
+* } </pre>
+* \par
+* where N = 4096 logN2 = 12
+* \par
+* N is the maximum FFT Size supported
+*/
+
+/*
+* @brief Table for bit reversal process
+*/
+const uint16_t armBitRevTable[1024] = {
+ 0x400, 0x200, 0x600, 0x100, 0x500, 0x300, 0x700, 0x80, 0x480, 0x280,
+ 0x680, 0x180, 0x580, 0x380, 0x780, 0x40, 0x440, 0x240, 0x640, 0x140,
+ 0x540, 0x340, 0x740, 0xc0, 0x4c0, 0x2c0, 0x6c0, 0x1c0, 0x5c0, 0x3c0,
+ 0x7c0, 0x20, 0x420, 0x220, 0x620, 0x120, 0x520, 0x320, 0x720, 0xa0,
+ 0x4a0, 0x2a0, 0x6a0, 0x1a0, 0x5a0, 0x3a0, 0x7a0, 0x60, 0x460, 0x260,
+ 0x660, 0x160, 0x560, 0x360, 0x760, 0xe0, 0x4e0, 0x2e0, 0x6e0, 0x1e0,
+ 0x5e0, 0x3e0, 0x7e0, 0x10, 0x410, 0x210, 0x610, 0x110, 0x510, 0x310,
+ 0x710, 0x90, 0x490, 0x290, 0x690, 0x190, 0x590, 0x390, 0x790, 0x50,
+ 0x450, 0x250, 0x650, 0x150, 0x550, 0x350, 0x750, 0xd0, 0x4d0, 0x2d0,
+ 0x6d0, 0x1d0, 0x5d0, 0x3d0, 0x7d0, 0x30, 0x430, 0x230, 0x630, 0x130,
+ 0x530, 0x330, 0x730, 0xb0, 0x4b0, 0x2b0, 0x6b0, 0x1b0, 0x5b0, 0x3b0,
+ 0x7b0, 0x70, 0x470, 0x270, 0x670, 0x170, 0x570, 0x370, 0x770, 0xf0,
+ 0x4f0, 0x2f0, 0x6f0, 0x1f0, 0x5f0, 0x3f0, 0x7f0, 0x8, 0x408, 0x208,
+ 0x608, 0x108, 0x508, 0x308, 0x708, 0x88, 0x488, 0x288, 0x688, 0x188,
+ 0x588, 0x388, 0x788, 0x48, 0x448, 0x248, 0x648, 0x148, 0x548, 0x348,
+ 0x748, 0xc8, 0x4c8, 0x2c8, 0x6c8, 0x1c8, 0x5c8, 0x3c8, 0x7c8, 0x28,
+ 0x428, 0x228, 0x628, 0x128, 0x528, 0x328, 0x728, 0xa8, 0x4a8, 0x2a8,
+ 0x6a8, 0x1a8, 0x5a8, 0x3a8, 0x7a8, 0x68, 0x468, 0x268, 0x668, 0x168,
+ 0x568, 0x368, 0x768, 0xe8, 0x4e8, 0x2e8, 0x6e8, 0x1e8, 0x5e8, 0x3e8,
+ 0x7e8, 0x18, 0x418, 0x218, 0x618, 0x118, 0x518, 0x318, 0x718, 0x98,
+ 0x498, 0x298, 0x698, 0x198, 0x598, 0x398, 0x798, 0x58, 0x458, 0x258,
+ 0x658, 0x158, 0x558, 0x358, 0x758, 0xd8, 0x4d8, 0x2d8, 0x6d8, 0x1d8,
+ 0x5d8, 0x3d8, 0x7d8, 0x38, 0x438, 0x238, 0x638, 0x138, 0x538, 0x338,
+ 0x738, 0xb8, 0x4b8, 0x2b8, 0x6b8, 0x1b8, 0x5b8, 0x3b8, 0x7b8, 0x78,
+ 0x478, 0x278, 0x678, 0x178, 0x578, 0x378, 0x778, 0xf8, 0x4f8, 0x2f8,
+ 0x6f8, 0x1f8, 0x5f8, 0x3f8, 0x7f8, 0x4, 0x404, 0x204, 0x604, 0x104,
+ 0x504, 0x304, 0x704, 0x84, 0x484, 0x284, 0x684, 0x184, 0x584, 0x384,
+ 0x784, 0x44, 0x444, 0x244, 0x644, 0x144, 0x544, 0x344, 0x744, 0xc4,
+ 0x4c4, 0x2c4, 0x6c4, 0x1c4, 0x5c4, 0x3c4, 0x7c4, 0x24, 0x424, 0x224,
+ 0x624, 0x124, 0x524, 0x324, 0x724, 0xa4, 0x4a4, 0x2a4, 0x6a4, 0x1a4,
+ 0x5a4, 0x3a4, 0x7a4, 0x64, 0x464, 0x264, 0x664, 0x164, 0x564, 0x364,
+ 0x764, 0xe4, 0x4e4, 0x2e4, 0x6e4, 0x1e4, 0x5e4, 0x3e4, 0x7e4, 0x14,
+ 0x414, 0x214, 0x614, 0x114, 0x514, 0x314, 0x714, 0x94, 0x494, 0x294,
+ 0x694, 0x194, 0x594, 0x394, 0x794, 0x54, 0x454, 0x254, 0x654, 0x154,
+ 0x554, 0x354, 0x754, 0xd4, 0x4d4, 0x2d4, 0x6d4, 0x1d4, 0x5d4, 0x3d4,
+ 0x7d4, 0x34, 0x434, 0x234, 0x634, 0x134, 0x534, 0x334, 0x734, 0xb4,
+ 0x4b4, 0x2b4, 0x6b4, 0x1b4, 0x5b4, 0x3b4, 0x7b4, 0x74, 0x474, 0x274,
+ 0x674, 0x174, 0x574, 0x374, 0x774, 0xf4, 0x4f4, 0x2f4, 0x6f4, 0x1f4,
+ 0x5f4, 0x3f4, 0x7f4, 0xc, 0x40c, 0x20c, 0x60c, 0x10c, 0x50c, 0x30c,
+ 0x70c, 0x8c, 0x48c, 0x28c, 0x68c, 0x18c, 0x58c, 0x38c, 0x78c, 0x4c,
+ 0x44c, 0x24c, 0x64c, 0x14c, 0x54c, 0x34c, 0x74c, 0xcc, 0x4cc, 0x2cc,
+ 0x6cc, 0x1cc, 0x5cc, 0x3cc, 0x7cc, 0x2c, 0x42c, 0x22c, 0x62c, 0x12c,
+ 0x52c, 0x32c, 0x72c, 0xac, 0x4ac, 0x2ac, 0x6ac, 0x1ac, 0x5ac, 0x3ac,
+ 0x7ac, 0x6c, 0x46c, 0x26c, 0x66c, 0x16c, 0x56c, 0x36c, 0x76c, 0xec,
+ 0x4ec, 0x2ec, 0x6ec, 0x1ec, 0x5ec, 0x3ec, 0x7ec, 0x1c, 0x41c, 0x21c,
+ 0x61c, 0x11c, 0x51c, 0x31c, 0x71c, 0x9c, 0x49c, 0x29c, 0x69c, 0x19c,
+ 0x59c, 0x39c, 0x79c, 0x5c, 0x45c, 0x25c, 0x65c, 0x15c, 0x55c, 0x35c,
+ 0x75c, 0xdc, 0x4dc, 0x2dc, 0x6dc, 0x1dc, 0x5dc, 0x3dc, 0x7dc, 0x3c,
+ 0x43c, 0x23c, 0x63c, 0x13c, 0x53c, 0x33c, 0x73c, 0xbc, 0x4bc, 0x2bc,
+ 0x6bc, 0x1bc, 0x5bc, 0x3bc, 0x7bc, 0x7c, 0x47c, 0x27c, 0x67c, 0x17c,
+ 0x57c, 0x37c, 0x77c, 0xfc, 0x4fc, 0x2fc, 0x6fc, 0x1fc, 0x5fc, 0x3fc,
+ 0x7fc, 0x2, 0x402, 0x202, 0x602, 0x102, 0x502, 0x302, 0x702, 0x82,
+ 0x482, 0x282, 0x682, 0x182, 0x582, 0x382, 0x782, 0x42, 0x442, 0x242,
+ 0x642, 0x142, 0x542, 0x342, 0x742, 0xc2, 0x4c2, 0x2c2, 0x6c2, 0x1c2,
+ 0x5c2, 0x3c2, 0x7c2, 0x22, 0x422, 0x222, 0x622, 0x122, 0x522, 0x322,
+ 0x722, 0xa2, 0x4a2, 0x2a2, 0x6a2, 0x1a2, 0x5a2, 0x3a2, 0x7a2, 0x62,
+ 0x462, 0x262, 0x662, 0x162, 0x562, 0x362, 0x762, 0xe2, 0x4e2, 0x2e2,
+ 0x6e2, 0x1e2, 0x5e2, 0x3e2, 0x7e2, 0x12, 0x412, 0x212, 0x612, 0x112,
+ 0x512, 0x312, 0x712, 0x92, 0x492, 0x292, 0x692, 0x192, 0x592, 0x392,
+ 0x792, 0x52, 0x452, 0x252, 0x652, 0x152, 0x552, 0x352, 0x752, 0xd2,
+ 0x4d2, 0x2d2, 0x6d2, 0x1d2, 0x5d2, 0x3d2, 0x7d2, 0x32, 0x432, 0x232,
+ 0x632, 0x132, 0x532, 0x332, 0x732, 0xb2, 0x4b2, 0x2b2, 0x6b2, 0x1b2,
+ 0x5b2, 0x3b2, 0x7b2, 0x72, 0x472, 0x272, 0x672, 0x172, 0x572, 0x372,
+ 0x772, 0xf2, 0x4f2, 0x2f2, 0x6f2, 0x1f2, 0x5f2, 0x3f2, 0x7f2, 0xa,
+ 0x40a, 0x20a, 0x60a, 0x10a, 0x50a, 0x30a, 0x70a, 0x8a, 0x48a, 0x28a,
+ 0x68a, 0x18a, 0x58a, 0x38a, 0x78a, 0x4a, 0x44a, 0x24a, 0x64a, 0x14a,
+ 0x54a, 0x34a, 0x74a, 0xca, 0x4ca, 0x2ca, 0x6ca, 0x1ca, 0x5ca, 0x3ca,
+ 0x7ca, 0x2a, 0x42a, 0x22a, 0x62a, 0x12a, 0x52a, 0x32a, 0x72a, 0xaa,
+ 0x4aa, 0x2aa, 0x6aa, 0x1aa, 0x5aa, 0x3aa, 0x7aa, 0x6a, 0x46a, 0x26a,
+ 0x66a, 0x16a, 0x56a, 0x36a, 0x76a, 0xea, 0x4ea, 0x2ea, 0x6ea, 0x1ea,
+ 0x5ea, 0x3ea, 0x7ea, 0x1a, 0x41a, 0x21a, 0x61a, 0x11a, 0x51a, 0x31a,
+ 0x71a, 0x9a, 0x49a, 0x29a, 0x69a, 0x19a, 0x59a, 0x39a, 0x79a, 0x5a,
+ 0x45a, 0x25a, 0x65a, 0x15a, 0x55a, 0x35a, 0x75a, 0xda, 0x4da, 0x2da,
+ 0x6da, 0x1da, 0x5da, 0x3da, 0x7da, 0x3a, 0x43a, 0x23a, 0x63a, 0x13a,
+ 0x53a, 0x33a, 0x73a, 0xba, 0x4ba, 0x2ba, 0x6ba, 0x1ba, 0x5ba, 0x3ba,
+ 0x7ba, 0x7a, 0x47a, 0x27a, 0x67a, 0x17a, 0x57a, 0x37a, 0x77a, 0xfa,
+ 0x4fa, 0x2fa, 0x6fa, 0x1fa, 0x5fa, 0x3fa, 0x7fa, 0x6, 0x406, 0x206,
+ 0x606, 0x106, 0x506, 0x306, 0x706, 0x86, 0x486, 0x286, 0x686, 0x186,
+ 0x586, 0x386, 0x786, 0x46, 0x446, 0x246, 0x646, 0x146, 0x546, 0x346,
+ 0x746, 0xc6, 0x4c6, 0x2c6, 0x6c6, 0x1c6, 0x5c6, 0x3c6, 0x7c6, 0x26,
+ 0x426, 0x226, 0x626, 0x126, 0x526, 0x326, 0x726, 0xa6, 0x4a6, 0x2a6,
+ 0x6a6, 0x1a6, 0x5a6, 0x3a6, 0x7a6, 0x66, 0x466, 0x266, 0x666, 0x166,
+ 0x566, 0x366, 0x766, 0xe6, 0x4e6, 0x2e6, 0x6e6, 0x1e6, 0x5e6, 0x3e6,
+ 0x7e6, 0x16, 0x416, 0x216, 0x616, 0x116, 0x516, 0x316, 0x716, 0x96,
+ 0x496, 0x296, 0x696, 0x196, 0x596, 0x396, 0x796, 0x56, 0x456, 0x256,
+ 0x656, 0x156, 0x556, 0x356, 0x756, 0xd6, 0x4d6, 0x2d6, 0x6d6, 0x1d6,
+ 0x5d6, 0x3d6, 0x7d6, 0x36, 0x436, 0x236, 0x636, 0x136, 0x536, 0x336,
+ 0x736, 0xb6, 0x4b6, 0x2b6, 0x6b6, 0x1b6, 0x5b6, 0x3b6, 0x7b6, 0x76,
+ 0x476, 0x276, 0x676, 0x176, 0x576, 0x376, 0x776, 0xf6, 0x4f6, 0x2f6,
+ 0x6f6, 0x1f6, 0x5f6, 0x3f6, 0x7f6, 0xe, 0x40e, 0x20e, 0x60e, 0x10e,
+ 0x50e, 0x30e, 0x70e, 0x8e, 0x48e, 0x28e, 0x68e, 0x18e, 0x58e, 0x38e,
+ 0x78e, 0x4e, 0x44e, 0x24e, 0x64e, 0x14e, 0x54e, 0x34e, 0x74e, 0xce,
+ 0x4ce, 0x2ce, 0x6ce, 0x1ce, 0x5ce, 0x3ce, 0x7ce, 0x2e, 0x42e, 0x22e,
+ 0x62e, 0x12e, 0x52e, 0x32e, 0x72e, 0xae, 0x4ae, 0x2ae, 0x6ae, 0x1ae,
+ 0x5ae, 0x3ae, 0x7ae, 0x6e, 0x46e, 0x26e, 0x66e, 0x16e, 0x56e, 0x36e,
+ 0x76e, 0xee, 0x4ee, 0x2ee, 0x6ee, 0x1ee, 0x5ee, 0x3ee, 0x7ee, 0x1e,
+ 0x41e, 0x21e, 0x61e, 0x11e, 0x51e, 0x31e, 0x71e, 0x9e, 0x49e, 0x29e,
+ 0x69e, 0x19e, 0x59e, 0x39e, 0x79e, 0x5e, 0x45e, 0x25e, 0x65e, 0x15e,
+ 0x55e, 0x35e, 0x75e, 0xde, 0x4de, 0x2de, 0x6de, 0x1de, 0x5de, 0x3de,
+ 0x7de, 0x3e, 0x43e, 0x23e, 0x63e, 0x13e, 0x53e, 0x33e, 0x73e, 0xbe,
+ 0x4be, 0x2be, 0x6be, 0x1be, 0x5be, 0x3be, 0x7be, 0x7e, 0x47e, 0x27e,
+ 0x67e, 0x17e, 0x57e, 0x37e, 0x77e, 0xfe, 0x4fe, 0x2fe, 0x6fe, 0x1fe,
+ 0x5fe, 0x3fe, 0x7fe, 0x1
+};
+
+
+/*
+* @brief Floating-point Twiddle factors Table Generation
+*/
+
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* <pre>for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 16 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+const float32_t twiddleCoef_16[32] = {
+ 1.000000000f, 0.000000000f,
+ 0.923879533f, 0.382683432f,
+ 0.707106781f, 0.707106781f,
+ 0.382683432f, 0.923879533f,
+ 0.000000000f, 1.000000000f,
+ -0.382683432f, 0.923879533f,
+ -0.707106781f, 0.707106781f,
+ -0.923879533f, 0.382683432f,
+ -1.000000000f, 0.000000000f,
+ -0.923879533f, -0.382683432f,
+ -0.707106781f, -0.707106781f,
+ -0.382683432f, -0.923879533f,
+ -0.000000000f, -1.000000000f,
+ 0.382683432f, -0.923879533f,
+ 0.707106781f, -0.707106781f,
+ 0.923879533f, -0.382683432f
+};
+
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* <pre>for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 32 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+const float32_t twiddleCoef_32[64] = {
+ 1.000000000f, 0.000000000f,
+ 0.980785280f, 0.195090322f,
+ 0.923879533f, 0.382683432f,
+ 0.831469612f, 0.555570233f,
+ 0.707106781f, 0.707106781f,
+ 0.555570233f, 0.831469612f,
+ 0.382683432f, 0.923879533f,
+ 0.195090322f, 0.980785280f,
+ 0.000000000f, 1.000000000f,
+ -0.195090322f, 0.980785280f,
+ -0.382683432f, 0.923879533f,
+ -0.555570233f, 0.831469612f,
+ -0.707106781f, 0.707106781f,
+ -0.831469612f, 0.555570233f,
+ -0.923879533f, 0.382683432f,
+ -0.980785280f, 0.195090322f,
+ -1.000000000f, 0.000000000f,
+ -0.980785280f, -0.195090322f,
+ -0.923879533f, -0.382683432f,
+ -0.831469612f, -0.555570233f,
+ -0.707106781f, -0.707106781f,
+ -0.555570233f, -0.831469612f,
+ -0.382683432f, -0.923879533f,
+ -0.195090322f, -0.980785280f,
+ -0.000000000f, -1.000000000f,
+ 0.195090322f, -0.980785280f,
+ 0.382683432f, -0.923879533f,
+ 0.555570233f, -0.831469612f,
+ 0.707106781f, -0.707106781f,
+ 0.831469612f, -0.555570233f,
+ 0.923879533f, -0.382683432f,
+ 0.980785280f, -0.195090322f
+};
+
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* <pre>for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 64 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+const float32_t twiddleCoef_64[128] = {
+ 1.000000000f, 0.000000000f,
+ 0.995184727f, 0.098017140f,
+ 0.980785280f, 0.195090322f,
+ 0.956940336f, 0.290284677f,
+ 0.923879533f, 0.382683432f,
+ 0.881921264f, 0.471396737f,
+ 0.831469612f, 0.555570233f,
+ 0.773010453f, 0.634393284f,
+ 0.707106781f, 0.707106781f,
+ 0.634393284f, 0.773010453f,
+ 0.555570233f, 0.831469612f,
+ 0.471396737f, 0.881921264f,
+ 0.382683432f, 0.923879533f,
+ 0.290284677f, 0.956940336f,
+ 0.195090322f, 0.980785280f,
+ 0.098017140f, 0.995184727f,
+ 0.000000000f, 1.000000000f,
+ -0.098017140f, 0.995184727f,
+ -0.195090322f, 0.980785280f,
+ -0.290284677f, 0.956940336f,
+ -0.382683432f, 0.923879533f,
+ -0.471396737f, 0.881921264f,
+ -0.555570233f, 0.831469612f,
+ -0.634393284f, 0.773010453f,
+ -0.707106781f, 0.707106781f,
+ -0.773010453f, 0.634393284f,
+ -0.831469612f, 0.555570233f,
+ -0.881921264f, 0.471396737f,
+ -0.923879533f, 0.382683432f,
+ -0.956940336f, 0.290284677f,
+ -0.980785280f, 0.195090322f,
+ -0.995184727f, 0.098017140f,
+ -1.000000000f, 0.000000000f,
+ -0.995184727f, -0.098017140f,
+ -0.980785280f, -0.195090322f,
+ -0.956940336f, -0.290284677f,
+ -0.923879533f, -0.382683432f,
+ -0.881921264f, -0.471396737f,
+ -0.831469612f, -0.555570233f,
+ -0.773010453f, -0.634393284f,
+ -0.707106781f, -0.707106781f,
+ -0.634393284f, -0.773010453f,
+ -0.555570233f, -0.831469612f,
+ -0.471396737f, -0.881921264f,
+ -0.382683432f, -0.923879533f,
+ -0.290284677f, -0.956940336f,
+ -0.195090322f, -0.980785280f,
+ -0.098017140f, -0.995184727f,
+ -0.000000000f, -1.000000000f,
+ 0.098017140f, -0.995184727f,
+ 0.195090322f, -0.980785280f,
+ 0.290284677f, -0.956940336f,
+ 0.382683432f, -0.923879533f,
+ 0.471396737f, -0.881921264f,
+ 0.555570233f, -0.831469612f,
+ 0.634393284f, -0.773010453f,
+ 0.707106781f, -0.707106781f,
+ 0.773010453f, -0.634393284f,
+ 0.831469612f, -0.555570233f,
+ 0.881921264f, -0.471396737f,
+ 0.923879533f, -0.382683432f,
+ 0.956940336f, -0.290284677f,
+ 0.980785280f, -0.195090322f,
+ 0.995184727f, -0.098017140f
+};
+
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* <pre>for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 128 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+
+const float32_t twiddleCoef_128[256] = {
+ 1.000000000f, 0.000000000f,
+ 0.998795456f, 0.049067674f,
+ 0.995184727f, 0.098017140f,
+ 0.989176510f, 0.146730474f,
+ 0.980785280f, 0.195090322f,
+ 0.970031253f, 0.242980180f,
+ 0.956940336f, 0.290284677f,
+ 0.941544065f, 0.336889853f,
+ 0.923879533f, 0.382683432f,
+ 0.903989293f, 0.427555093f,
+ 0.881921264f, 0.471396737f,
+ 0.857728610f, 0.514102744f,
+ 0.831469612f, 0.555570233f,
+ 0.803207531f, 0.595699304f,
+ 0.773010453f, 0.634393284f,
+ 0.740951125f, 0.671558955f,
+ 0.707106781f, 0.707106781f,
+ 0.671558955f, 0.740951125f,
+ 0.634393284f, 0.773010453f,
+ 0.595699304f, 0.803207531f,
+ 0.555570233f, 0.831469612f,
+ 0.514102744f, 0.857728610f,
+ 0.471396737f, 0.881921264f,
+ 0.427555093f, 0.903989293f,
+ 0.382683432f, 0.923879533f,
+ 0.336889853f, 0.941544065f,
+ 0.290284677f, 0.956940336f,
+ 0.242980180f, 0.970031253f,
+ 0.195090322f, 0.980785280f,
+ 0.146730474f, 0.989176510f,
+ 0.098017140f, 0.995184727f,
+ 0.049067674f, 0.998795456f,
+ 0.000000000f, 1.000000000f,
+ -0.049067674f, 0.998795456f,
+ -0.098017140f, 0.995184727f,
+ -0.146730474f, 0.989176510f,
+ -0.195090322f, 0.980785280f,
+ -0.242980180f, 0.970031253f,
+ -0.290284677f, 0.956940336f,
+ -0.336889853f, 0.941544065f,
+ -0.382683432f, 0.923879533f,
+ -0.427555093f, 0.903989293f,
+ -0.471396737f, 0.881921264f,
+ -0.514102744f, 0.857728610f,
+ -0.555570233f, 0.831469612f,
+ -0.595699304f, 0.803207531f,
+ -0.634393284f, 0.773010453f,
+ -0.671558955f, 0.740951125f,
+ -0.707106781f, 0.707106781f,
+ -0.740951125f, 0.671558955f,
+ -0.773010453f, 0.634393284f,
+ -0.803207531f, 0.595699304f,
+ -0.831469612f, 0.555570233f,
+ -0.857728610f, 0.514102744f,
+ -0.881921264f, 0.471396737f,
+ -0.903989293f, 0.427555093f,
+ -0.923879533f, 0.382683432f,
+ -0.941544065f, 0.336889853f,
+ -0.956940336f, 0.290284677f,
+ -0.970031253f, 0.242980180f,
+ -0.980785280f, 0.195090322f,
+ -0.989176510f, 0.146730474f,
+ -0.995184727f, 0.098017140f,
+ -0.998795456f, 0.049067674f,
+ -1.000000000f, 0.000000000f,
+ -0.998795456f, -0.049067674f,
+ -0.995184727f, -0.098017140f,
+ -0.989176510f, -0.146730474f,
+ -0.980785280f, -0.195090322f,
+ -0.970031253f, -0.242980180f,
+ -0.956940336f, -0.290284677f,
+ -0.941544065f, -0.336889853f,
+ -0.923879533f, -0.382683432f,
+ -0.903989293f, -0.427555093f,
+ -0.881921264f, -0.471396737f,
+ -0.857728610f, -0.514102744f,
+ -0.831469612f, -0.555570233f,
+ -0.803207531f, -0.595699304f,
+ -0.773010453f, -0.634393284f,
+ -0.740951125f, -0.671558955f,
+ -0.707106781f, -0.707106781f,
+ -0.671558955f, -0.740951125f,
+ -0.634393284f, -0.773010453f,
+ -0.595699304f, -0.803207531f,
+ -0.555570233f, -0.831469612f,
+ -0.514102744f, -0.857728610f,
+ -0.471396737f, -0.881921264f,
+ -0.427555093f, -0.903989293f,
+ -0.382683432f, -0.923879533f,
+ -0.336889853f, -0.941544065f,
+ -0.290284677f, -0.956940336f,
+ -0.242980180f, -0.970031253f,
+ -0.195090322f, -0.980785280f,
+ -0.146730474f, -0.989176510f,
+ -0.098017140f, -0.995184727f,
+ -0.049067674f, -0.998795456f,
+ -0.000000000f, -1.000000000f,
+ 0.049067674f, -0.998795456f,
+ 0.098017140f, -0.995184727f,
+ 0.146730474f, -0.989176510f,
+ 0.195090322f, -0.980785280f,
+ 0.242980180f, -0.970031253f,
+ 0.290284677f, -0.956940336f,
+ 0.336889853f, -0.941544065f,
+ 0.382683432f, -0.923879533f,
+ 0.427555093f, -0.903989293f,
+ 0.471396737f, -0.881921264f,
+ 0.514102744f, -0.857728610f,
+ 0.555570233f, -0.831469612f,
+ 0.595699304f, -0.803207531f,
+ 0.634393284f, -0.773010453f,
+ 0.671558955f, -0.740951125f,
+ 0.707106781f, -0.707106781f,
+ 0.740951125f, -0.671558955f,
+ 0.773010453f, -0.634393284f,
+ 0.803207531f, -0.595699304f,
+ 0.831469612f, -0.555570233f,
+ 0.857728610f, -0.514102744f,
+ 0.881921264f, -0.471396737f,
+ 0.903989293f, -0.427555093f,
+ 0.923879533f, -0.382683432f,
+ 0.941544065f, -0.336889853f,
+ 0.956940336f, -0.290284677f,
+ 0.970031253f, -0.242980180f,
+ 0.980785280f, -0.195090322f,
+ 0.989176510f, -0.146730474f,
+ 0.995184727f, -0.098017140f,
+ 0.998795456f, -0.049067674f
+};
+
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* <pre>for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 256 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+const float32_t twiddleCoef_256[512] = {
+ 1.000000000f, 0.000000000f,
+ 0.999698819f, 0.024541229f,
+ 0.998795456f, 0.049067674f,
+ 0.997290457f, 0.073564564f,
+ 0.995184727f, 0.098017140f,
+ 0.992479535f, 0.122410675f,
+ 0.989176510f, 0.146730474f,
+ 0.985277642f, 0.170961889f,
+ 0.980785280f, 0.195090322f,
+ 0.975702130f, 0.219101240f,
+ 0.970031253f, 0.242980180f,
+ 0.963776066f, 0.266712757f,
+ 0.956940336f, 0.290284677f,
+ 0.949528181f, 0.313681740f,
+ 0.941544065f, 0.336889853f,
+ 0.932992799f, 0.359895037f,
+ 0.923879533f, 0.382683432f,
+ 0.914209756f, 0.405241314f,
+ 0.903989293f, 0.427555093f,
+ 0.893224301f, 0.449611330f,
+ 0.881921264f, 0.471396737f,
+ 0.870086991f, 0.492898192f,
+ 0.857728610f, 0.514102744f,
+ 0.844853565f, 0.534997620f,
+ 0.831469612f, 0.555570233f,
+ 0.817584813f, 0.575808191f,
+ 0.803207531f, 0.595699304f,
+ 0.788346428f, 0.615231591f,
+ 0.773010453f, 0.634393284f,
+ 0.757208847f, 0.653172843f,
+ 0.740951125f, 0.671558955f,
+ 0.724247083f, 0.689540545f,
+ 0.707106781f, 0.707106781f,
+ 0.689540545f, 0.724247083f,
+ 0.671558955f, 0.740951125f,
+ 0.653172843f, 0.757208847f,
+ 0.634393284f, 0.773010453f,
+ 0.615231591f, 0.788346428f,
+ 0.595699304f, 0.803207531f,
+ 0.575808191f, 0.817584813f,
+ 0.555570233f, 0.831469612f,
+ 0.534997620f, 0.844853565f,
+ 0.514102744f, 0.857728610f,
+ 0.492898192f, 0.870086991f,
+ 0.471396737f, 0.881921264f,
+ 0.449611330f, 0.893224301f,
+ 0.427555093f, 0.903989293f,
+ 0.405241314f, 0.914209756f,
+ 0.382683432f, 0.923879533f,
+ 0.359895037f, 0.932992799f,
+ 0.336889853f, 0.941544065f,
+ 0.313681740f, 0.949528181f,
+ 0.290284677f, 0.956940336f,
+ 0.266712757f, 0.963776066f,
+ 0.242980180f, 0.970031253f,
+ 0.219101240f, 0.975702130f,
+ 0.195090322f, 0.980785280f,
+ 0.170961889f, 0.985277642f,
+ 0.146730474f, 0.989176510f,
+ 0.122410675f, 0.992479535f,
+ 0.098017140f, 0.995184727f,
+ 0.073564564f, 0.997290457f,
+ 0.049067674f, 0.998795456f,
+ 0.024541229f, 0.999698819f,
+ 0.000000000f, 1.000000000f,
+ -0.024541229f, 0.999698819f,
+ -0.049067674f, 0.998795456f,
+ -0.073564564f, 0.997290457f,
+ -0.098017140f, 0.995184727f,
+ -0.122410675f, 0.992479535f,
+ -0.146730474f, 0.989176510f,
+ -0.170961889f, 0.985277642f,
+ -0.195090322f, 0.980785280f,
+ -0.219101240f, 0.975702130f,
+ -0.242980180f, 0.970031253f,
+ -0.266712757f, 0.963776066f,
+ -0.290284677f, 0.956940336f,
+ -0.313681740f, 0.949528181f,
+ -0.336889853f, 0.941544065f,
+ -0.359895037f, 0.932992799f,
+ -0.382683432f, 0.923879533f,
+ -0.405241314f, 0.914209756f,
+ -0.427555093f, 0.903989293f,
+ -0.449611330f, 0.893224301f,
+ -0.471396737f, 0.881921264f,
+ -0.492898192f, 0.870086991f,
+ -0.514102744f, 0.857728610f,
+ -0.534997620f, 0.844853565f,
+ -0.555570233f, 0.831469612f,
+ -0.575808191f, 0.817584813f,
+ -0.595699304f, 0.803207531f,
+ -0.615231591f, 0.788346428f,
+ -0.634393284f, 0.773010453f,
+ -0.653172843f, 0.757208847f,
+ -0.671558955f, 0.740951125f,
+ -0.689540545f, 0.724247083f,
+ -0.707106781f, 0.707106781f,
+ -0.724247083f, 0.689540545f,
+ -0.740951125f, 0.671558955f,
+ -0.757208847f, 0.653172843f,
+ -0.773010453f, 0.634393284f,
+ -0.788346428f, 0.615231591f,
+ -0.803207531f, 0.595699304f,
+ -0.817584813f, 0.575808191f,
+ -0.831469612f, 0.555570233f,
+ -0.844853565f, 0.534997620f,
+ -0.857728610f, 0.514102744f,
+ -0.870086991f, 0.492898192f,
+ -0.881921264f, 0.471396737f,
+ -0.893224301f, 0.449611330f,
+ -0.903989293f, 0.427555093f,
+ -0.914209756f, 0.405241314f,
+ -0.923879533f, 0.382683432f,
+ -0.932992799f, 0.359895037f,
+ -0.941544065f, 0.336889853f,
+ -0.949528181f, 0.313681740f,
+ -0.956940336f, 0.290284677f,
+ -0.963776066f, 0.266712757f,
+ -0.970031253f, 0.242980180f,
+ -0.975702130f, 0.219101240f,
+ -0.980785280f, 0.195090322f,
+ -0.985277642f, 0.170961889f,
+ -0.989176510f, 0.146730474f,
+ -0.992479535f, 0.122410675f,
+ -0.995184727f, 0.098017140f,
+ -0.997290457f, 0.073564564f,
+ -0.998795456f, 0.049067674f,
+ -0.999698819f, 0.024541229f,
+ -1.000000000f, 0.000000000f,
+ -0.999698819f, -0.024541229f,
+ -0.998795456f, -0.049067674f,
+ -0.997290457f, -0.073564564f,
+ -0.995184727f, -0.098017140f,
+ -0.992479535f, -0.122410675f,
+ -0.989176510f, -0.146730474f,
+ -0.985277642f, -0.170961889f,
+ -0.980785280f, -0.195090322f,
+ -0.975702130f, -0.219101240f,
+ -0.970031253f, -0.242980180f,
+ -0.963776066f, -0.266712757f,
+ -0.956940336f, -0.290284677f,
+ -0.949528181f, -0.313681740f,
+ -0.941544065f, -0.336889853f,
+ -0.932992799f, -0.359895037f,
+ -0.923879533f, -0.382683432f,
+ -0.914209756f, -0.405241314f,
+ -0.903989293f, -0.427555093f,
+ -0.893224301f, -0.449611330f,
+ -0.881921264f, -0.471396737f,
+ -0.870086991f, -0.492898192f,
+ -0.857728610f, -0.514102744f,
+ -0.844853565f, -0.534997620f,
+ -0.831469612f, -0.555570233f,
+ -0.817584813f, -0.575808191f,
+ -0.803207531f, -0.595699304f,
+ -0.788346428f, -0.615231591f,
+ -0.773010453f, -0.634393284f,
+ -0.757208847f, -0.653172843f,
+ -0.740951125f, -0.671558955f,
+ -0.724247083f, -0.689540545f,
+ -0.707106781f, -0.707106781f,
+ -0.689540545f, -0.724247083f,
+ -0.671558955f, -0.740951125f,
+ -0.653172843f, -0.757208847f,
+ -0.634393284f, -0.773010453f,
+ -0.615231591f, -0.788346428f,
+ -0.595699304f, -0.803207531f,
+ -0.575808191f, -0.817584813f,
+ -0.555570233f, -0.831469612f,
+ -0.534997620f, -0.844853565f,
+ -0.514102744f, -0.857728610f,
+ -0.492898192f, -0.870086991f,
+ -0.471396737f, -0.881921264f,
+ -0.449611330f, -0.893224301f,
+ -0.427555093f, -0.903989293f,
+ -0.405241314f, -0.914209756f,
+ -0.382683432f, -0.923879533f,
+ -0.359895037f, -0.932992799f,
+ -0.336889853f, -0.941544065f,
+ -0.313681740f, -0.949528181f,
+ -0.290284677f, -0.956940336f,
+ -0.266712757f, -0.963776066f,
+ -0.242980180f, -0.970031253f,
+ -0.219101240f, -0.975702130f,
+ -0.195090322f, -0.980785280f,
+ -0.170961889f, -0.985277642f,
+ -0.146730474f, -0.989176510f,
+ -0.122410675f, -0.992479535f,
+ -0.098017140f, -0.995184727f,
+ -0.073564564f, -0.997290457f,
+ -0.049067674f, -0.998795456f,
+ -0.024541229f, -0.999698819f,
+ -0.000000000f, -1.000000000f,
+ 0.024541229f, -0.999698819f,
+ 0.049067674f, -0.998795456f,
+ 0.073564564f, -0.997290457f,
+ 0.098017140f, -0.995184727f,
+ 0.122410675f, -0.992479535f,
+ 0.146730474f, -0.989176510f,
+ 0.170961889f, -0.985277642f,
+ 0.195090322f, -0.980785280f,
+ 0.219101240f, -0.975702130f,
+ 0.242980180f, -0.970031253f,
+ 0.266712757f, -0.963776066f,
+ 0.290284677f, -0.956940336f,
+ 0.313681740f, -0.949528181f,
+ 0.336889853f, -0.941544065f,
+ 0.359895037f, -0.932992799f,
+ 0.382683432f, -0.923879533f,
+ 0.405241314f, -0.914209756f,
+ 0.427555093f, -0.903989293f,
+ 0.449611330f, -0.893224301f,
+ 0.471396737f, -0.881921264f,
+ 0.492898192f, -0.870086991f,
+ 0.514102744f, -0.857728610f,
+ 0.534997620f, -0.844853565f,
+ 0.555570233f, -0.831469612f,
+ 0.575808191f, -0.817584813f,
+ 0.595699304f, -0.803207531f,
+ 0.615231591f, -0.788346428f,
+ 0.634393284f, -0.773010453f,
+ 0.653172843f, -0.757208847f,
+ 0.671558955f, -0.740951125f,
+ 0.689540545f, -0.724247083f,
+ 0.707106781f, -0.707106781f,
+ 0.724247083f, -0.689540545f,
+ 0.740951125f, -0.671558955f,
+ 0.757208847f, -0.653172843f,
+ 0.773010453f, -0.634393284f,
+ 0.788346428f, -0.615231591f,
+ 0.803207531f, -0.595699304f,
+ 0.817584813f, -0.575808191f,
+ 0.831469612f, -0.555570233f,
+ 0.844853565f, -0.534997620f,
+ 0.857728610f, -0.514102744f,
+ 0.870086991f, -0.492898192f,
+ 0.881921264f, -0.471396737f,
+ 0.893224301f, -0.449611330f,
+ 0.903989293f, -0.427555093f,
+ 0.914209756f, -0.405241314f,
+ 0.923879533f, -0.382683432f,
+ 0.932992799f, -0.359895037f,
+ 0.941544065f, -0.336889853f,
+ 0.949528181f, -0.313681740f,
+ 0.956940336f, -0.290284677f,
+ 0.963776066f, -0.266712757f,
+ 0.970031253f, -0.242980180f,
+ 0.975702130f, -0.219101240f,
+ 0.980785280f, -0.195090322f,
+ 0.985277642f, -0.170961889f,
+ 0.989176510f, -0.146730474f,
+ 0.992479535f, -0.122410675f,
+ 0.995184727f, -0.098017140f,
+ 0.997290457f, -0.073564564f,
+ 0.998795456f, -0.049067674f,
+ 0.999698819f, -0.024541229f
+};
+
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* <pre>for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 512 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+const float32_t twiddleCoef_512[1024] = {
+ 1.000000000f, 0.000000000f,
+ 0.999924702f, 0.012271538f,
+ 0.999698819f, 0.024541229f,
+ 0.999322385f, 0.036807223f,
+ 0.998795456f, 0.049067674f,
+ 0.998118113f, 0.061320736f,
+ 0.997290457f, 0.073564564f,
+ 0.996312612f, 0.085797312f,
+ 0.995184727f, 0.098017140f,
+ 0.993906970f, 0.110222207f,
+ 0.992479535f, 0.122410675f,
+ 0.990902635f, 0.134580709f,
+ 0.989176510f, 0.146730474f,
+ 0.987301418f, 0.158858143f,
+ 0.985277642f, 0.170961889f,
+ 0.983105487f, 0.183039888f,
+ 0.980785280f, 0.195090322f,
+ 0.978317371f, 0.207111376f,
+ 0.975702130f, 0.219101240f,
+ 0.972939952f, 0.231058108f,
+ 0.970031253f, 0.242980180f,
+ 0.966976471f, 0.254865660f,
+ 0.963776066f, 0.266712757f,
+ 0.960430519f, 0.278519689f,
+ 0.956940336f, 0.290284677f,
+ 0.953306040f, 0.302005949f,
+ 0.949528181f, 0.313681740f,
+ 0.945607325f, 0.325310292f,
+ 0.941544065f, 0.336889853f,
+ 0.937339012f, 0.348418680f,
+ 0.932992799f, 0.359895037f,
+ 0.928506080f, 0.371317194f,
+ 0.923879533f, 0.382683432f,
+ 0.919113852f, 0.393992040f,
+ 0.914209756f, 0.405241314f,
+ 0.909167983f, 0.416429560f,
+ 0.903989293f, 0.427555093f,
+ 0.898674466f, 0.438616239f,
+ 0.893224301f, 0.449611330f,
+ 0.887639620f, 0.460538711f,
+ 0.881921264f, 0.471396737f,
+ 0.876070094f, 0.482183772f,
+ 0.870086991f, 0.492898192f,
+ 0.863972856f, 0.503538384f,
+ 0.857728610f, 0.514102744f,
+ 0.851355193f, 0.524589683f,
+ 0.844853565f, 0.534997620f,
+ 0.838224706f, 0.545324988f,
+ 0.831469612f, 0.555570233f,
+ 0.824589303f, 0.565731811f,
+ 0.817584813f, 0.575808191f,
+ 0.810457198f, 0.585797857f,
+ 0.803207531f, 0.595699304f,
+ 0.795836905f, 0.605511041f,
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+ 0.831469612f, -0.555570233f,
+ 0.838224706f, -0.545324988f,
+ 0.844853565f, -0.534997620f,
+ 0.851355193f, -0.524589683f,
+ 0.857728610f, -0.514102744f,
+ 0.863972856f, -0.503538384f,
+ 0.870086991f, -0.492898192f,
+ 0.876070094f, -0.482183772f,
+ 0.881921264f, -0.471396737f,
+ 0.887639620f, -0.460538711f,
+ 0.893224301f, -0.449611330f,
+ 0.898674466f, -0.438616239f,
+ 0.903989293f, -0.427555093f,
+ 0.909167983f, -0.416429560f,
+ 0.914209756f, -0.405241314f,
+ 0.919113852f, -0.393992040f,
+ 0.923879533f, -0.382683432f,
+ 0.928506080f, -0.371317194f,
+ 0.932992799f, -0.359895037f,
+ 0.937339012f, -0.348418680f,
+ 0.941544065f, -0.336889853f,
+ 0.945607325f, -0.325310292f,
+ 0.949528181f, -0.313681740f,
+ 0.953306040f, -0.302005949f,
+ 0.956940336f, -0.290284677f,
+ 0.960430519f, -0.278519689f,
+ 0.963776066f, -0.266712757f,
+ 0.966976471f, -0.254865660f,
+ 0.970031253f, -0.242980180f,
+ 0.972939952f, -0.231058108f,
+ 0.975702130f, -0.219101240f,
+ 0.978317371f, -0.207111376f,
+ 0.980785280f, -0.195090322f,
+ 0.983105487f, -0.183039888f,
+ 0.985277642f, -0.170961889f,
+ 0.987301418f, -0.158858143f,
+ 0.989176510f, -0.146730474f,
+ 0.990902635f, -0.134580709f,
+ 0.992479535f, -0.122410675f,
+ 0.993906970f, -0.110222207f,
+ 0.995184727f, -0.098017140f,
+ 0.996312612f, -0.085797312f,
+ 0.997290457f, -0.073564564f,
+ 0.998118113f, -0.061320736f,
+ 0.998795456f, -0.049067674f,
+ 0.999322385f, -0.036807223f,
+ 0.999698819f, -0.024541229f,
+ 0.999924702f, -0.012271538f
+};
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* <pre>for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 1024 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+const float32_t twiddleCoef_1024[2048] = {
+ 1.000000000f, 0.000000000f,
+ 0.999981175f, 0.006135885f,
+ 0.999924702f, 0.012271538f,
+ 0.999830582f, 0.018406730f,
+ 0.999698819f, 0.024541229f,
+ 0.999529418f, 0.030674803f,
+ 0.999322385f, 0.036807223f,
+ 0.999077728f, 0.042938257f,
+ 0.998795456f, 0.049067674f,
+ 0.998475581f, 0.055195244f,
+ 0.998118113f, 0.061320736f,
+ 0.997723067f, 0.067443920f,
+ 0.997290457f, 0.073564564f,
+ 0.996820299f, 0.079682438f,
+ 0.996312612f, 0.085797312f,
+ 0.995767414f, 0.091908956f,
+ 0.995184727f, 0.098017140f,
+ 0.994564571f, 0.104121634f,
+ 0.993906970f, 0.110222207f,
+ 0.993211949f, 0.116318631f,
+ 0.992479535f, 0.122410675f,
+ 0.991709754f, 0.128498111f,
+ 0.990902635f, 0.134580709f,
+ 0.990058210f, 0.140658239f,
+ 0.989176510f, 0.146730474f,
+ 0.988257568f, 0.152797185f,
+ 0.987301418f, 0.158858143f,
+ 0.986308097f, 0.164913120f,
+ 0.985277642f, 0.170961889f,
+ 0.984210092f, 0.177004220f,
+ 0.983105487f, 0.183039888f,
+ 0.981963869f, 0.189068664f,
+ 0.980785280f, 0.195090322f,
+ 0.979569766f, 0.201104635f,
+ 0.978317371f, 0.207111376f,
+ 0.977028143f, 0.213110320f,
+ 0.975702130f, 0.219101240f,
+ 0.974339383f, 0.225083911f,
+ 0.972939952f, 0.231058108f,
+ 0.971503891f, 0.237023606f,
+ 0.970031253f, 0.242980180f,
+ 0.968522094f, 0.248927606f,
+ 0.966976471f, 0.254865660f,
+ 0.965394442f, 0.260794118f,
+ 0.963776066f, 0.266712757f,
+ 0.962121404f, 0.272621355f,
+ 0.960430519f, 0.278519689f,
+ 0.958703475f, 0.284407537f,
+ 0.956940336f, 0.290284677f,
+ 0.955141168f, 0.296150888f,
+ 0.953306040f, 0.302005949f,
+ 0.951435021f, 0.307849640f,
+ 0.949528181f, 0.313681740f,
+ 0.947585591f, 0.319502031f,
+ 0.945607325f, 0.325310292f,
+ 0.943593458f, 0.331106306f,
+ 0.941544065f, 0.336889853f,
+ 0.939459224f, 0.342660717f,
+ 0.937339012f, 0.348418680f,
+ 0.935183510f, 0.354163525f,
+ 0.932992799f, 0.359895037f,
+ 0.930766961f, 0.365612998f,
+ 0.928506080f, 0.371317194f,
+ 0.926210242f, 0.377007410f,
+ 0.923879533f, 0.382683432f,
+ 0.921514039f, 0.388345047f,
+ 0.919113852f, 0.393992040f,
+ 0.916679060f, 0.399624200f,
+ 0.914209756f, 0.405241314f,
+ 0.911706032f, 0.410843171f,
+ 0.909167983f, 0.416429560f,
+ 0.906595705f, 0.422000271f,
+ 0.903989293f, 0.427555093f,
+ 0.901348847f, 0.433093819f,
+ 0.898674466f, 0.438616239f,
+ 0.895966250f, 0.444122145f,
+ 0.893224301f, 0.449611330f,
+ 0.890448723f, 0.455083587f,
+ 0.887639620f, 0.460538711f,
+ 0.884797098f, 0.465976496f,
+ 0.881921264f, 0.471396737f,
+ 0.879012226f, 0.476799230f,
+ 0.876070094f, 0.482183772f,
+ 0.873094978f, 0.487550160f,
+ 0.870086991f, 0.492898192f,
+ 0.867046246f, 0.498227667f,
+ 0.863972856f, 0.503538384f,
+ 0.860866939f, 0.508830143f,
+ 0.857728610f, 0.514102744f,
+ 0.854557988f, 0.519355990f,
+ 0.851355193f, 0.524589683f,
+ 0.848120345f, 0.529803625f,
+ 0.844853565f, 0.534997620f,
+ 0.841554977f, 0.540171473f,
+ 0.838224706f, 0.545324988f,
+ 0.834862875f, 0.550457973f,
+ 0.831469612f, 0.555570233f,
+ 0.828045045f, 0.560661576f,
+ 0.824589303f, 0.565731811f,
+ 0.821102515f, 0.570780746f,
+ 0.817584813f, 0.575808191f,
+ 0.814036330f, 0.580813958f,
+ 0.810457198f, 0.585797857f,
+ 0.806847554f, 0.590759702f,
+ 0.803207531f, 0.595699304f,
+ 0.799537269f, 0.600616479f,
+ 0.795836905f, 0.605511041f,
+ 0.792106577f, 0.610382806f,
+ 0.788346428f, 0.615231591f,
+ 0.784556597f, 0.620057212f,
+ 0.780737229f, 0.624859488f,
+ 0.776888466f, 0.629638239f,
+ 0.773010453f, 0.634393284f,
+ 0.769103338f, 0.639124445f,
+ 0.765167266f, 0.643831543f,
+ 0.761202385f, 0.648514401f,
+ 0.757208847f, 0.653172843f,
+ 0.753186799f, 0.657806693f,
+ 0.749136395f, 0.662415778f,
+ 0.745057785f, 0.666999922f,
+ 0.740951125f, 0.671558955f,
+ 0.736816569f, 0.676092704f,
+ 0.732654272f, 0.680600998f,
+ 0.728464390f, 0.685083668f,
+ 0.724247083f, 0.689540545f,
+ 0.720002508f, 0.693971461f,
+ 0.715730825f, 0.698376249f,
+ 0.711432196f, 0.702754744f,
+ 0.707106781f, 0.707106781f,
+ 0.702754744f, 0.711432196f,
+ 0.698376249f, 0.715730825f,
+ 0.693971461f, 0.720002508f,
+ 0.689540545f, 0.724247083f,
+ 0.685083668f, 0.728464390f,
+ 0.680600998f, 0.732654272f,
+ 0.676092704f, 0.736816569f,
+ 0.671558955f, 0.740951125f,
+ 0.666999922f, 0.745057785f,
+ 0.662415778f, 0.749136395f,
+ 0.657806693f, 0.753186799f,
+ 0.653172843f, 0.757208847f,
+ 0.648514401f, 0.761202385f,
+ 0.643831543f, 0.765167266f,
+ 0.639124445f, 0.769103338f,
+ 0.634393284f, 0.773010453f,
+ 0.629638239f, 0.776888466f,
+ 0.624859488f, 0.780737229f,
+ 0.620057212f, 0.784556597f,
+ 0.615231591f, 0.788346428f,
+ 0.610382806f, 0.792106577f,
+ 0.605511041f, 0.795836905f,
+ 0.600616479f, 0.799537269f,
+ 0.595699304f, 0.803207531f,
+ 0.590759702f, 0.806847554f,
+ 0.585797857f, 0.810457198f,
+ 0.580813958f, 0.814036330f,
+ 0.575808191f, 0.817584813f,
+ 0.570780746f, 0.821102515f,
+ 0.565731811f, 0.824589303f,
+ 0.560661576f, 0.828045045f,
+ 0.555570233f, 0.831469612f,
+ 0.550457973f, 0.834862875f,
+ 0.545324988f, 0.838224706f,
+ 0.540171473f, 0.841554977f,
+ 0.534997620f, 0.844853565f,
+ 0.529803625f, 0.848120345f,
+ 0.524589683f, 0.851355193f,
+ 0.519355990f, 0.854557988f,
+ 0.514102744f, 0.857728610f,
+ 0.508830143f, 0.860866939f,
+ 0.503538384f, 0.863972856f,
+ 0.498227667f, 0.867046246f,
+ 0.492898192f, 0.870086991f,
+ 0.487550160f, 0.873094978f,
+ 0.482183772f, 0.876070094f,
+ 0.476799230f, 0.879012226f,
+ 0.471396737f, 0.881921264f,
+ 0.465976496f, 0.884797098f,
+ 0.460538711f, 0.887639620f,
+ 0.455083587f, 0.890448723f,
+ 0.449611330f, 0.893224301f,
+ 0.444122145f, 0.895966250f,
+ 0.438616239f, 0.898674466f,
+ 0.433093819f, 0.901348847f,
+ 0.427555093f, 0.903989293f,
+ 0.422000271f, 0.906595705f,
+ 0.416429560f, 0.909167983f,
+ 0.410843171f, 0.911706032f,
+ 0.405241314f, 0.914209756f,
+ 0.399624200f, 0.916679060f,
+ 0.393992040f, 0.919113852f,
+ 0.388345047f, 0.921514039f,
+ 0.382683432f, 0.923879533f,
+ 0.377007410f, 0.926210242f,
+ 0.371317194f, 0.928506080f,
+ 0.365612998f, 0.930766961f,
+ 0.359895037f, 0.932992799f,
+ 0.354163525f, 0.935183510f,
+ 0.348418680f, 0.937339012f,
+ 0.342660717f, 0.939459224f,
+ 0.336889853f, 0.941544065f,
+ 0.331106306f, 0.943593458f,
+ 0.325310292f, 0.945607325f,
+ 0.319502031f, 0.947585591f,
+ 0.313681740f, 0.949528181f,
+ 0.307849640f, 0.951435021f,
+ 0.302005949f, 0.953306040f,
+ 0.296150888f, 0.955141168f,
+ 0.290284677f, 0.956940336f,
+ 0.284407537f, 0.958703475f,
+ 0.278519689f, 0.960430519f,
+ 0.272621355f, 0.962121404f,
+ 0.266712757f, 0.963776066f,
+ 0.260794118f, 0.965394442f,
+ 0.254865660f, 0.966976471f,
+ 0.248927606f, 0.968522094f,
+ 0.242980180f, 0.970031253f,
+ 0.237023606f, 0.971503891f,
+ 0.231058108f, 0.972939952f,
+ 0.225083911f, 0.974339383f,
+ 0.219101240f, 0.975702130f,
+ 0.213110320f, 0.977028143f,
+ 0.207111376f, 0.978317371f,
+ 0.201104635f, 0.979569766f,
+ 0.195090322f, 0.980785280f,
+ 0.189068664f, 0.981963869f,
+ 0.183039888f, 0.983105487f,
+ 0.177004220f, 0.984210092f,
+ 0.170961889f, 0.985277642f,
+ 0.164913120f, 0.986308097f,
+ 0.158858143f, 0.987301418f,
+ 0.152797185f, 0.988257568f,
+ 0.146730474f, 0.989176510f,
+ 0.140658239f, 0.990058210f,
+ 0.134580709f, 0.990902635f,
+ 0.128498111f, 0.991709754f,
+ 0.122410675f, 0.992479535f,
+ 0.116318631f, 0.993211949f,
+ 0.110222207f, 0.993906970f,
+ 0.104121634f, 0.994564571f,
+ 0.098017140f, 0.995184727f,
+ 0.091908956f, 0.995767414f,
+ 0.085797312f, 0.996312612f,
+ 0.079682438f, 0.996820299f,
+ 0.073564564f, 0.997290457f,
+ 0.067443920f, 0.997723067f,
+ 0.061320736f, 0.998118113f,
+ 0.055195244f, 0.998475581f,
+ 0.049067674f, 0.998795456f,
+ 0.042938257f, 0.999077728f,
+ 0.036807223f, 0.999322385f,
+ 0.030674803f, 0.999529418f,
+ 0.024541229f, 0.999698819f,
+ 0.018406730f, 0.999830582f,
+ 0.012271538f, 0.999924702f,
+ 0.006135885f, 0.999981175f,
+ 0.000000000f, 1.000000000f,
+ -0.006135885f, 0.999981175f,
+ -0.012271538f, 0.999924702f,
+ -0.018406730f, 0.999830582f,
+ -0.024541229f, 0.999698819f,
+ -0.030674803f, 0.999529418f,
+ -0.036807223f, 0.999322385f,
+ -0.042938257f, 0.999077728f,
+ -0.049067674f, 0.998795456f,
+ -0.055195244f, 0.998475581f,
+ -0.061320736f, 0.998118113f,
+ -0.067443920f, 0.997723067f,
+ -0.073564564f, 0.997290457f,
+ -0.079682438f, 0.996820299f,
+ -0.085797312f, 0.996312612f,
+ -0.091908956f, 0.995767414f,
+ -0.098017140f, 0.995184727f,
+ -0.104121634f, 0.994564571f,
+ -0.110222207f, 0.993906970f,
+ -0.116318631f, 0.993211949f,
+ -0.122410675f, 0.992479535f,
+ -0.128498111f, 0.991709754f,
+ -0.134580709f, 0.990902635f,
+ -0.140658239f, 0.990058210f,
+ -0.146730474f, 0.989176510f,
+ -0.152797185f, 0.988257568f,
+ -0.158858143f, 0.987301418f,
+ -0.164913120f, 0.986308097f,
+ -0.170961889f, 0.985277642f,
+ -0.177004220f, 0.984210092f,
+ -0.183039888f, 0.983105487f,
+ -0.189068664f, 0.981963869f,
+ -0.195090322f, 0.980785280f,
+ -0.201104635f, 0.979569766f,
+ -0.207111376f, 0.978317371f,
+ -0.213110320f, 0.977028143f,
+ -0.219101240f, 0.975702130f,
+ -0.225083911f, 0.974339383f,
+ -0.231058108f, 0.972939952f,
+ -0.237023606f, 0.971503891f,
+ -0.242980180f, 0.970031253f,
+ -0.248927606f, 0.968522094f,
+ -0.254865660f, 0.966976471f,
+ -0.260794118f, 0.965394442f,
+ -0.266712757f, 0.963776066f,
+ -0.272621355f, 0.962121404f,
+ -0.278519689f, 0.960430519f,
+ -0.284407537f, 0.958703475f,
+ -0.290284677f, 0.956940336f,
+ -0.296150888f, 0.955141168f,
+ -0.302005949f, 0.953306040f,
+ -0.307849640f, 0.951435021f,
+ -0.313681740f, 0.949528181f,
+ -0.319502031f, 0.947585591f,
+ -0.325310292f, 0.945607325f,
+ -0.331106306f, 0.943593458f,
+ -0.336889853f, 0.941544065f,
+ -0.342660717f, 0.939459224f,
+ -0.348418680f, 0.937339012f,
+ -0.354163525f, 0.935183510f,
+ -0.359895037f, 0.932992799f,
+ -0.365612998f, 0.930766961f,
+ -0.371317194f, 0.928506080f,
+ -0.377007410f, 0.926210242f,
+ -0.382683432f, 0.923879533f,
+ -0.388345047f, 0.921514039f,
+ -0.393992040f, 0.919113852f,
+ -0.399624200f, 0.916679060f,
+ -0.405241314f, 0.914209756f,
+ -0.410843171f, 0.911706032f,
+ -0.416429560f, 0.909167983f,
+ -0.422000271f, 0.906595705f,
+ -0.427555093f, 0.903989293f,
+ -0.433093819f, 0.901348847f,
+ -0.438616239f, 0.898674466f,
+ -0.444122145f, 0.895966250f,
+ -0.449611330f, 0.893224301f,
+ -0.455083587f, 0.890448723f,
+ -0.460538711f, 0.887639620f,
+ -0.465976496f, 0.884797098f,
+ -0.471396737f, 0.881921264f,
+ -0.476799230f, 0.879012226f,
+ -0.482183772f, 0.876070094f,
+ -0.487550160f, 0.873094978f,
+ -0.492898192f, 0.870086991f,
+ -0.498227667f, 0.867046246f,
+ -0.503538384f, 0.863972856f,
+ -0.508830143f, 0.860866939f,
+ -0.514102744f, 0.857728610f,
+ -0.519355990f, 0.854557988f,
+ -0.524589683f, 0.851355193f,
+ -0.529803625f, 0.848120345f,
+ -0.534997620f, 0.844853565f,
+ -0.540171473f, 0.841554977f,
+ -0.545324988f, 0.838224706f,
+ -0.550457973f, 0.834862875f,
+ -0.555570233f, 0.831469612f,
+ -0.560661576f, 0.828045045f,
+ -0.565731811f, 0.824589303f,
+ -0.570780746f, 0.821102515f,
+ -0.575808191f, 0.817584813f,
+ -0.580813958f, 0.814036330f,
+ -0.585797857f, 0.810457198f,
+ -0.590759702f, 0.806847554f,
+ -0.595699304f, 0.803207531f,
+ -0.600616479f, 0.799537269f,
+ -0.605511041f, 0.795836905f,
+ -0.610382806f, 0.792106577f,
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+ -0.024541229f, -0.999698819f,
+ -0.018406730f, -0.999830582f,
+ -0.012271538f, -0.999924702f,
+ -0.006135885f, -0.999981175f,
+ -0.000000000f, -1.000000000f,
+ 0.006135885f, -0.999981175f,
+ 0.012271538f, -0.999924702f,
+ 0.018406730f, -0.999830582f,
+ 0.024541229f, -0.999698819f,
+ 0.030674803f, -0.999529418f,
+ 0.036807223f, -0.999322385f,
+ 0.042938257f, -0.999077728f,
+ 0.049067674f, -0.998795456f,
+ 0.055195244f, -0.998475581f,
+ 0.061320736f, -0.998118113f,
+ 0.067443920f, -0.997723067f,
+ 0.073564564f, -0.997290457f,
+ 0.079682438f, -0.996820299f,
+ 0.085797312f, -0.996312612f,
+ 0.091908956f, -0.995767414f,
+ 0.098017140f, -0.995184727f,
+ 0.104121634f, -0.994564571f,
+ 0.110222207f, -0.993906970f,
+ 0.116318631f, -0.993211949f,
+ 0.122410675f, -0.992479535f,
+ 0.128498111f, -0.991709754f,
+ 0.134580709f, -0.990902635f,
+ 0.140658239f, -0.990058210f,
+ 0.146730474f, -0.989176510f,
+ 0.152797185f, -0.988257568f,
+ 0.158858143f, -0.987301418f,
+ 0.164913120f, -0.986308097f,
+ 0.170961889f, -0.985277642f,
+ 0.177004220f, -0.984210092f,
+ 0.183039888f, -0.983105487f,
+ 0.189068664f, -0.981963869f,
+ 0.195090322f, -0.980785280f,
+ 0.201104635f, -0.979569766f,
+ 0.207111376f, -0.978317371f,
+ 0.213110320f, -0.977028143f,
+ 0.219101240f, -0.975702130f,
+ 0.225083911f, -0.974339383f,
+ 0.231058108f, -0.972939952f,
+ 0.237023606f, -0.971503891f,
+ 0.242980180f, -0.970031253f,
+ 0.248927606f, -0.968522094f,
+ 0.254865660f, -0.966976471f,
+ 0.260794118f, -0.965394442f,
+ 0.266712757f, -0.963776066f,
+ 0.272621355f, -0.962121404f,
+ 0.278519689f, -0.960430519f,
+ 0.284407537f, -0.958703475f,
+ 0.290284677f, -0.956940336f,
+ 0.296150888f, -0.955141168f,
+ 0.302005949f, -0.953306040f,
+ 0.307849640f, -0.951435021f,
+ 0.313681740f, -0.949528181f,
+ 0.319502031f, -0.947585591f,
+ 0.325310292f, -0.945607325f,
+ 0.331106306f, -0.943593458f,
+ 0.336889853f, -0.941544065f,
+ 0.342660717f, -0.939459224f,
+ 0.348418680f, -0.937339012f,
+ 0.354163525f, -0.935183510f,
+ 0.359895037f, -0.932992799f,
+ 0.365612998f, -0.930766961f,
+ 0.371317194f, -0.928506080f,
+ 0.377007410f, -0.926210242f,
+ 0.382683432f, -0.923879533f,
+ 0.388345047f, -0.921514039f,
+ 0.393992040f, -0.919113852f,
+ 0.399624200f, -0.916679060f,
+ 0.405241314f, -0.914209756f,
+ 0.410843171f, -0.911706032f,
+ 0.416429560f, -0.909167983f,
+ 0.422000271f, -0.906595705f,
+ 0.427555093f, -0.903989293f,
+ 0.433093819f, -0.901348847f,
+ 0.438616239f, -0.898674466f,
+ 0.444122145f, -0.895966250f,
+ 0.449611330f, -0.893224301f,
+ 0.455083587f, -0.890448723f,
+ 0.460538711f, -0.887639620f,
+ 0.465976496f, -0.884797098f,
+ 0.471396737f, -0.881921264f,
+ 0.476799230f, -0.879012226f,
+ 0.482183772f, -0.876070094f,
+ 0.487550160f, -0.873094978f,
+ 0.492898192f, -0.870086991f,
+ 0.498227667f, -0.867046246f,
+ 0.503538384f, -0.863972856f,
+ 0.508830143f, -0.860866939f,
+ 0.514102744f, -0.857728610f,
+ 0.519355990f, -0.854557988f,
+ 0.524589683f, -0.851355193f,
+ 0.529803625f, -0.848120345f,
+ 0.534997620f, -0.844853565f,
+ 0.540171473f, -0.841554977f,
+ 0.545324988f, -0.838224706f,
+ 0.550457973f, -0.834862875f,
+ 0.555570233f, -0.831469612f,
+ 0.560661576f, -0.828045045f,
+ 0.565731811f, -0.824589303f,
+ 0.570780746f, -0.821102515f,
+ 0.575808191f, -0.817584813f,
+ 0.580813958f, -0.814036330f,
+ 0.585797857f, -0.810457198f,
+ 0.590759702f, -0.806847554f,
+ 0.595699304f, -0.803207531f,
+ 0.600616479f, -0.799537269f,
+ 0.605511041f, -0.795836905f,
+ 0.610382806f, -0.792106577f,
+ 0.615231591f, -0.788346428f,
+ 0.620057212f, -0.784556597f,
+ 0.624859488f, -0.780737229f,
+ 0.629638239f, -0.776888466f,
+ 0.634393284f, -0.773010453f,
+ 0.639124445f, -0.769103338f,
+ 0.643831543f, -0.765167266f,
+ 0.648514401f, -0.761202385f,
+ 0.653172843f, -0.757208847f,
+ 0.657806693f, -0.753186799f,
+ 0.662415778f, -0.749136395f,
+ 0.666999922f, -0.745057785f,
+ 0.671558955f, -0.740951125f,
+ 0.676092704f, -0.736816569f,
+ 0.680600998f, -0.732654272f,
+ 0.685083668f, -0.728464390f,
+ 0.689540545f, -0.724247083f,
+ 0.693971461f, -0.720002508f,
+ 0.698376249f, -0.715730825f,
+ 0.702754744f, -0.711432196f,
+ 0.707106781f, -0.707106781f,
+ 0.711432196f, -0.702754744f,
+ 0.715730825f, -0.698376249f,
+ 0.720002508f, -0.693971461f,
+ 0.724247083f, -0.689540545f,
+ 0.728464390f, -0.685083668f,
+ 0.732654272f, -0.680600998f,
+ 0.736816569f, -0.676092704f,
+ 0.740951125f, -0.671558955f,
+ 0.745057785f, -0.666999922f,
+ 0.749136395f, -0.662415778f,
+ 0.753186799f, -0.657806693f,
+ 0.757208847f, -0.653172843f,
+ 0.761202385f, -0.648514401f,
+ 0.765167266f, -0.643831543f,
+ 0.769103338f, -0.639124445f,
+ 0.773010453f, -0.634393284f,
+ 0.776888466f, -0.629638239f,
+ 0.780737229f, -0.624859488f,
+ 0.784556597f, -0.620057212f,
+ 0.788346428f, -0.615231591f,
+ 0.792106577f, -0.610382806f,
+ 0.795836905f, -0.605511041f,
+ 0.799537269f, -0.600616479f,
+ 0.803207531f, -0.595699304f,
+ 0.806847554f, -0.590759702f,
+ 0.810457198f, -0.585797857f,
+ 0.814036330f, -0.580813958f,
+ 0.817584813f, -0.575808191f,
+ 0.821102515f, -0.570780746f,
+ 0.824589303f, -0.565731811f,
+ 0.828045045f, -0.560661576f,
+ 0.831469612f, -0.555570233f,
+ 0.834862875f, -0.550457973f,
+ 0.838224706f, -0.545324988f,
+ 0.841554977f, -0.540171473f,
+ 0.844853565f, -0.534997620f,
+ 0.848120345f, -0.529803625f,
+ 0.851355193f, -0.524589683f,
+ 0.854557988f, -0.519355990f,
+ 0.857728610f, -0.514102744f,
+ 0.860866939f, -0.508830143f,
+ 0.863972856f, -0.503538384f,
+ 0.867046246f, -0.498227667f,
+ 0.870086991f, -0.492898192f,
+ 0.873094978f, -0.487550160f,
+ 0.876070094f, -0.482183772f,
+ 0.879012226f, -0.476799230f,
+ 0.881921264f, -0.471396737f,
+ 0.884797098f, -0.465976496f,
+ 0.887639620f, -0.460538711f,
+ 0.890448723f, -0.455083587f,
+ 0.893224301f, -0.449611330f,
+ 0.895966250f, -0.444122145f,
+ 0.898674466f, -0.438616239f,
+ 0.901348847f, -0.433093819f,
+ 0.903989293f, -0.427555093f,
+ 0.906595705f, -0.422000271f,
+ 0.909167983f, -0.416429560f,
+ 0.911706032f, -0.410843171f,
+ 0.914209756f, -0.405241314f,
+ 0.916679060f, -0.399624200f,
+ 0.919113852f, -0.393992040f,
+ 0.921514039f, -0.388345047f,
+ 0.923879533f, -0.382683432f,
+ 0.926210242f, -0.377007410f,
+ 0.928506080f, -0.371317194f,
+ 0.930766961f, -0.365612998f,
+ 0.932992799f, -0.359895037f,
+ 0.935183510f, -0.354163525f,
+ 0.937339012f, -0.348418680f,
+ 0.939459224f, -0.342660717f,
+ 0.941544065f, -0.336889853f,
+ 0.943593458f, -0.331106306f,
+ 0.945607325f, -0.325310292f,
+ 0.947585591f, -0.319502031f,
+ 0.949528181f, -0.313681740f,
+ 0.951435021f, -0.307849640f,
+ 0.953306040f, -0.302005949f,
+ 0.955141168f, -0.296150888f,
+ 0.956940336f, -0.290284677f,
+ 0.958703475f, -0.284407537f,
+ 0.960430519f, -0.278519689f,
+ 0.962121404f, -0.272621355f,
+ 0.963776066f, -0.266712757f,
+ 0.965394442f, -0.260794118f,
+ 0.966976471f, -0.254865660f,
+ 0.968522094f, -0.248927606f,
+ 0.970031253f, -0.242980180f,
+ 0.971503891f, -0.237023606f,
+ 0.972939952f, -0.231058108f,
+ 0.974339383f, -0.225083911f,
+ 0.975702130f, -0.219101240f,
+ 0.977028143f, -0.213110320f,
+ 0.978317371f, -0.207111376f,
+ 0.979569766f, -0.201104635f,
+ 0.980785280f, -0.195090322f,
+ 0.981963869f, -0.189068664f,
+ 0.983105487f, -0.183039888f,
+ 0.984210092f, -0.177004220f,
+ 0.985277642f, -0.170961889f,
+ 0.986308097f, -0.164913120f,
+ 0.987301418f, -0.158858143f,
+ 0.988257568f, -0.152797185f,
+ 0.989176510f, -0.146730474f,
+ 0.990058210f, -0.140658239f,
+ 0.990902635f, -0.134580709f,
+ 0.991709754f, -0.128498111f,
+ 0.992479535f, -0.122410675f,
+ 0.993211949f, -0.116318631f,
+ 0.993906970f, -0.110222207f,
+ 0.994564571f, -0.104121634f,
+ 0.995184727f, -0.098017140f,
+ 0.995767414f, -0.091908956f,
+ 0.996312612f, -0.085797312f,
+ 0.996820299f, -0.079682438f,
+ 0.997290457f, -0.073564564f,
+ 0.997723067f, -0.067443920f,
+ 0.998118113f, -0.061320736f,
+ 0.998475581f, -0.055195244f,
+ 0.998795456f, -0.049067674f,
+ 0.999077728f, -0.042938257f,
+ 0.999322385f, -0.036807223f,
+ 0.999529418f, -0.030674803f,
+ 0.999698819f, -0.024541229f,
+ 0.999830582f, -0.018406730f,
+ 0.999924702f, -0.012271538f,
+ 0.999981175f, -0.006135885f
+};
+
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* <pre>for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 2048 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+const float32_t twiddleCoef_2048[4096] = {
+ 1.000000000f, 0.000000000f,
+ 0.999995294f, 0.003067957f,
+ 0.999981175f, 0.006135885f,
+ 0.999957645f, 0.009203755f,
+ 0.999924702f, 0.012271538f,
+ 0.999882347f, 0.015339206f,
+ 0.999830582f, 0.018406730f,
+ 0.999769405f, 0.021474080f,
+ 0.999698819f, 0.024541229f,
+ 0.999618822f, 0.027608146f,
+ 0.999529418f, 0.030674803f,
+ 0.999430605f, 0.033741172f,
+ 0.999322385f, 0.036807223f,
+ 0.999204759f, 0.039872928f,
+ 0.999077728f, 0.042938257f,
+ 0.998941293f, 0.046003182f,
+ 0.998795456f, 0.049067674f,
+ 0.998640218f, 0.052131705f,
+ 0.998475581f, 0.055195244f,
+ 0.998301545f, 0.058258265f,
+ 0.998118113f, 0.061320736f,
+ 0.997925286f, 0.064382631f,
+ 0.997723067f, 0.067443920f,
+ 0.997511456f, 0.070504573f,
+ 0.997290457f, 0.073564564f,
+ 0.997060070f, 0.076623861f,
+ 0.996820299f, 0.079682438f,
+ 0.996571146f, 0.082740265f,
+ 0.996312612f, 0.085797312f,
+ 0.996044701f, 0.088853553f,
+ 0.995767414f, 0.091908956f,
+ 0.995480755f, 0.094963495f,
+ 0.995184727f, 0.098017140f,
+ 0.994879331f, 0.101069863f,
+ 0.994564571f, 0.104121634f,
+ 0.994240449f, 0.107172425f,
+ 0.993906970f, 0.110222207f,
+ 0.993564136f, 0.113270952f,
+ 0.993211949f, 0.116318631f,
+ 0.992850414f, 0.119365215f,
+ 0.992479535f, 0.122410675f,
+ 0.992099313f, 0.125454983f,
+ 0.991709754f, 0.128498111f,
+ 0.991310860f, 0.131540029f,
+ 0.990902635f, 0.134580709f,
+ 0.990485084f, 0.137620122f,
+ 0.990058210f, 0.140658239f,
+ 0.989622017f, 0.143695033f,
+ 0.989176510f, 0.146730474f,
+ 0.988721692f, 0.149764535f,
+ 0.988257568f, 0.152797185f,
+ 0.987784142f, 0.155828398f,
+ 0.987301418f, 0.158858143f,
+ 0.986809402f, 0.161886394f,
+ 0.986308097f, 0.164913120f,
+ 0.985797509f, 0.167938295f,
+ 0.985277642f, 0.170961889f,
+ 0.984748502f, 0.173983873f,
+ 0.984210092f, 0.177004220f,
+ 0.983662419f, 0.180022901f,
+ 0.983105487f, 0.183039888f,
+ 0.982539302f, 0.186055152f,
+ 0.981963869f, 0.189068664f,
+ 0.981379193f, 0.192080397f,
+ 0.980785280f, 0.195090322f,
+ 0.980182136f, 0.198098411f,
+ 0.979569766f, 0.201104635f,
+ 0.978948175f, 0.204108966f,
+ 0.978317371f, 0.207111376f,
+ 0.977677358f, 0.210111837f,
+ 0.977028143f, 0.213110320f,
+ 0.976369731f, 0.216106797f,
+ 0.975702130f, 0.219101240f,
+ 0.975025345f, 0.222093621f,
+ 0.974339383f, 0.225083911f,
+ 0.973644250f, 0.228072083f,
+ 0.972939952f, 0.231058108f,
+ 0.972226497f, 0.234041959f,
+ 0.971503891f, 0.237023606f,
+ 0.970772141f, 0.240003022f,
+ 0.970031253f, 0.242980180f,
+ 0.969281235f, 0.245955050f,
+ 0.968522094f, 0.248927606f,
+ 0.967753837f, 0.251897818f,
+ 0.966976471f, 0.254865660f,
+ 0.966190003f, 0.257831102f,
+ 0.965394442f, 0.260794118f,
+ 0.964589793f, 0.263754679f,
+ 0.963776066f, 0.266712757f,
+ 0.962953267f, 0.269668326f,
+ 0.962121404f, 0.272621355f,
+ 0.961280486f, 0.275571819f,
+ 0.960430519f, 0.278519689f,
+ 0.959571513f, 0.281464938f,
+ 0.958703475f, 0.284407537f,
+ 0.957826413f, 0.287347460f,
+ 0.956940336f, 0.290284677f,
+ 0.956045251f, 0.293219163f,
+ 0.955141168f, 0.296150888f,
+ 0.954228095f, 0.299079826f,
+ 0.953306040f, 0.302005949f,
+ 0.952375013f, 0.304929230f,
+ 0.951435021f, 0.307849640f,
+ 0.950486074f, 0.310767153f,
+ 0.949528181f, 0.313681740f,
+ 0.948561350f, 0.316593376f,
+ 0.947585591f, 0.319502031f,
+ 0.946600913f, 0.322407679f,
+ 0.945607325f, 0.325310292f,
+ 0.944604837f, 0.328209844f,
+ 0.943593458f, 0.331106306f,
+ 0.942573198f, 0.333999651f,
+ 0.941544065f, 0.336889853f,
+ 0.940506071f, 0.339776884f,
+ 0.939459224f, 0.342660717f,
+ 0.938403534f, 0.345541325f,
+ 0.937339012f, 0.348418680f,
+ 0.936265667f, 0.351292756f,
+ 0.935183510f, 0.354163525f,
+ 0.934092550f, 0.357030961f,
+ 0.932992799f, 0.359895037f,
+ 0.931884266f, 0.362755724f,
+ 0.930766961f, 0.365612998f,
+ 0.929640896f, 0.368466830f,
+ 0.928506080f, 0.371317194f,
+ 0.927362526f, 0.374164063f,
+ 0.926210242f, 0.377007410f,
+ 0.925049241f, 0.379847209f,
+ 0.923879533f, 0.382683432f,
+ 0.922701128f, 0.385516054f,
+ 0.921514039f, 0.388345047f,
+ 0.920318277f, 0.391170384f,
+ 0.919113852f, 0.393992040f,
+ 0.917900776f, 0.396809987f,
+ 0.916679060f, 0.399624200f,
+ 0.915448716f, 0.402434651f,
+ 0.914209756f, 0.405241314f,
+ 0.912962190f, 0.408044163f,
+ 0.911706032f, 0.410843171f,
+ 0.910441292f, 0.413638312f,
+ 0.909167983f, 0.416429560f,
+ 0.907886116f, 0.419216888f,
+ 0.906595705f, 0.422000271f,
+ 0.905296759f, 0.424779681f,
+ 0.903989293f, 0.427555093f,
+ 0.902673318f, 0.430326481f,
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+ 0.696177131f, -0.717870045f,
+ 0.698376249f, -0.715730825f,
+ 0.700568794f, -0.713584869f,
+ 0.702754744f, -0.711432196f,
+ 0.704934080f, -0.709272826f,
+ 0.707106781f, -0.707106781f,
+ 0.709272826f, -0.704934080f,
+ 0.711432196f, -0.702754744f,
+ 0.713584869f, -0.700568794f,
+ 0.715730825f, -0.698376249f,
+ 0.717870045f, -0.696177131f,
+ 0.720002508f, -0.693971461f,
+ 0.722128194f, -0.691759258f,
+ 0.724247083f, -0.689540545f,
+ 0.726359155f, -0.687315341f,
+ 0.728464390f, -0.685083668f,
+ 0.730562769f, -0.682845546f,
+ 0.732654272f, -0.680600998f,
+ 0.734738878f, -0.678350043f,
+ 0.736816569f, -0.676092704f,
+ 0.738887324f, -0.673829000f,
+ 0.740951125f, -0.671558955f,
+ 0.743007952f, -0.669282588f,
+ 0.745057785f, -0.666999922f,
+ 0.747100606f, -0.664710978f,
+ 0.749136395f, -0.662415778f,
+ 0.751165132f, -0.660114342f,
+ 0.753186799f, -0.657806693f,
+ 0.755201377f, -0.655492853f,
+ 0.757208847f, -0.653172843f,
+ 0.759209189f, -0.650846685f,
+ 0.761202385f, -0.648514401f,
+ 0.763188417f, -0.646176013f,
+ 0.765167266f, -0.643831543f,
+ 0.767138912f, -0.641481013f,
+ 0.769103338f, -0.639124445f,
+ 0.771060524f, -0.636761861f,
+ 0.773010453f, -0.634393284f,
+ 0.774953107f, -0.632018736f,
+ 0.776888466f, -0.629638239f,
+ 0.778816512f, -0.627251815f,
+ 0.780737229f, -0.624859488f,
+ 0.782650596f, -0.622461279f,
+ 0.784556597f, -0.620057212f,
+ 0.786455214f, -0.617647308f,
+ 0.788346428f, -0.615231591f,
+ 0.790230221f, -0.612810082f,
+ 0.792106577f, -0.610382806f,
+ 0.793975478f, -0.607949785f,
+ 0.795836905f, -0.605511041f,
+ 0.797690841f, -0.603066599f,
+ 0.799537269f, -0.600616479f,
+ 0.801376172f, -0.598160707f,
+ 0.803207531f, -0.595699304f,
+ 0.805031331f, -0.593232295f,
+ 0.806847554f, -0.590759702f,
+ 0.808656182f, -0.588281548f,
+ 0.810457198f, -0.585797857f,
+ 0.812250587f, -0.583308653f,
+ 0.814036330f, -0.580813958f,
+ 0.815814411f, -0.578313796f,
+ 0.817584813f, -0.575808191f,
+ 0.819347520f, -0.573297167f,
+ 0.821102515f, -0.570780746f,
+ 0.822849781f, -0.568258953f,
+ 0.824589303f, -0.565731811f,
+ 0.826321063f, -0.563199344f,
+ 0.828045045f, -0.560661576f,
+ 0.829761234f, -0.558118531f,
+ 0.831469612f, -0.555570233f,
+ 0.833170165f, -0.553016706f,
+ 0.834862875f, -0.550457973f,
+ 0.836547727f, -0.547894059f,
+ 0.838224706f, -0.545324988f,
+ 0.839893794f, -0.542750785f,
+ 0.841554977f, -0.540171473f,
+ 0.843208240f, -0.537587076f,
+ 0.844853565f, -0.534997620f,
+ 0.846490939f, -0.532403128f,
+ 0.848120345f, -0.529803625f,
+ 0.849741768f, -0.527199135f,
+ 0.851355193f, -0.524589683f,
+ 0.852960605f, -0.521975293f,
+ 0.854557988f, -0.519355990f,
+ 0.856147328f, -0.516731799f,
+ 0.857728610f, -0.514102744f,
+ 0.859301818f, -0.511468850f,
+ 0.860866939f, -0.508830143f,
+ 0.862423956f, -0.506186645f,
+ 0.863972856f, -0.503538384f,
+ 0.865513624f, -0.500885383f,
+ 0.867046246f, -0.498227667f,
+ 0.868570706f, -0.495565262f,
+ 0.870086991f, -0.492898192f,
+ 0.871595087f, -0.490226483f,
+ 0.873094978f, -0.487550160f,
+ 0.874586652f, -0.484869248f,
+ 0.876070094f, -0.482183772f,
+ 0.877545290f, -0.479493758f,
+ 0.879012226f, -0.476799230f,
+ 0.880470889f, -0.474100215f,
+ 0.881921264f, -0.471396737f,
+ 0.883363339f, -0.468688822f,
+ 0.884797098f, -0.465976496f,
+ 0.886222530f, -0.463259784f,
+ 0.887639620f, -0.460538711f,
+ 0.889048356f, -0.457813304f,
+ 0.890448723f, -0.455083587f,
+ 0.891840709f, -0.452349587f,
+ 0.893224301f, -0.449611330f,
+ 0.894599486f, -0.446868840f,
+ 0.895966250f, -0.444122145f,
+ 0.897324581f, -0.441371269f,
+ 0.898674466f, -0.438616239f,
+ 0.900015892f, -0.435857080f,
+ 0.901348847f, -0.433093819f,
+ 0.902673318f, -0.430326481f,
+ 0.903989293f, -0.427555093f,
+ 0.905296759f, -0.424779681f,
+ 0.906595705f, -0.422000271f,
+ 0.907886116f, -0.419216888f,
+ 0.909167983f, -0.416429560f,
+ 0.910441292f, -0.413638312f,
+ 0.911706032f, -0.410843171f,
+ 0.912962190f, -0.408044163f,
+ 0.914209756f, -0.405241314f,
+ 0.915448716f, -0.402434651f,
+ 0.916679060f, -0.399624200f,
+ 0.917900776f, -0.396809987f,
+ 0.919113852f, -0.393992040f,
+ 0.920318277f, -0.391170384f,
+ 0.921514039f, -0.388345047f,
+ 0.922701128f, -0.385516054f,
+ 0.923879533f, -0.382683432f,
+ 0.925049241f, -0.379847209f,
+ 0.926210242f, -0.377007410f,
+ 0.927362526f, -0.374164063f,
+ 0.928506080f, -0.371317194f,
+ 0.929640896f, -0.368466830f,
+ 0.930766961f, -0.365612998f,
+ 0.931884266f, -0.362755724f,
+ 0.932992799f, -0.359895037f,
+ 0.934092550f, -0.357030961f,
+ 0.935183510f, -0.354163525f,
+ 0.936265667f, -0.351292756f,
+ 0.937339012f, -0.348418680f,
+ 0.938403534f, -0.345541325f,
+ 0.939459224f, -0.342660717f,
+ 0.940506071f, -0.339776884f,
+ 0.941544065f, -0.336889853f,
+ 0.942573198f, -0.333999651f,
+ 0.943593458f, -0.331106306f,
+ 0.944604837f, -0.328209844f,
+ 0.945607325f, -0.325310292f,
+ 0.946600913f, -0.322407679f,
+ 0.947585591f, -0.319502031f,
+ 0.948561350f, -0.316593376f,
+ 0.949528181f, -0.313681740f,
+ 0.950486074f, -0.310767153f,
+ 0.951435021f, -0.307849640f,
+ 0.952375013f, -0.304929230f,
+ 0.953306040f, -0.302005949f,
+ 0.954228095f, -0.299079826f,
+ 0.955141168f, -0.296150888f,
+ 0.956045251f, -0.293219163f,
+ 0.956940336f, -0.290284677f,
+ 0.957826413f, -0.287347460f,
+ 0.958703475f, -0.284407537f,
+ 0.959571513f, -0.281464938f,
+ 0.960430519f, -0.278519689f,
+ 0.961280486f, -0.275571819f,
+ 0.962121404f, -0.272621355f,
+ 0.962953267f, -0.269668326f,
+ 0.963776066f, -0.266712757f,
+ 0.964589793f, -0.263754679f,
+ 0.965394442f, -0.260794118f,
+ 0.966190003f, -0.257831102f,
+ 0.966976471f, -0.254865660f,
+ 0.967753837f, -0.251897818f,
+ 0.968522094f, -0.248927606f,
+ 0.969281235f, -0.245955050f,
+ 0.970031253f, -0.242980180f,
+ 0.970772141f, -0.240003022f,
+ 0.971503891f, -0.237023606f,
+ 0.972226497f, -0.234041959f,
+ 0.972939952f, -0.231058108f,
+ 0.973644250f, -0.228072083f,
+ 0.974339383f, -0.225083911f,
+ 0.975025345f, -0.222093621f,
+ 0.975702130f, -0.219101240f,
+ 0.976369731f, -0.216106797f,
+ 0.977028143f, -0.213110320f,
+ 0.977677358f, -0.210111837f,
+ 0.978317371f, -0.207111376f,
+ 0.978948175f, -0.204108966f,
+ 0.979569766f, -0.201104635f,
+ 0.980182136f, -0.198098411f,
+ 0.980785280f, -0.195090322f,
+ 0.981379193f, -0.192080397f,
+ 0.981963869f, -0.189068664f,
+ 0.982539302f, -0.186055152f,
+ 0.983105487f, -0.183039888f,
+ 0.983662419f, -0.180022901f,
+ 0.984210092f, -0.177004220f,
+ 0.984748502f, -0.173983873f,
+ 0.985277642f, -0.170961889f,
+ 0.985797509f, -0.167938295f,
+ 0.986308097f, -0.164913120f,
+ 0.986809402f, -0.161886394f,
+ 0.987301418f, -0.158858143f,
+ 0.987784142f, -0.155828398f,
+ 0.988257568f, -0.152797185f,
+ 0.988721692f, -0.149764535f,
+ 0.989176510f, -0.146730474f,
+ 0.989622017f, -0.143695033f,
+ 0.990058210f, -0.140658239f,
+ 0.990485084f, -0.137620122f,
+ 0.990902635f, -0.134580709f,
+ 0.991310860f, -0.131540029f,
+ 0.991709754f, -0.128498111f,
+ 0.992099313f, -0.125454983f,
+ 0.992479535f, -0.122410675f,
+ 0.992850414f, -0.119365215f,
+ 0.993211949f, -0.116318631f,
+ 0.993564136f, -0.113270952f,
+ 0.993906970f, -0.110222207f,
+ 0.994240449f, -0.107172425f,
+ 0.994564571f, -0.104121634f,
+ 0.994879331f, -0.101069863f,
+ 0.995184727f, -0.098017140f,
+ 0.995480755f, -0.094963495f,
+ 0.995767414f, -0.091908956f,
+ 0.996044701f, -0.088853553f,
+ 0.996312612f, -0.085797312f,
+ 0.996571146f, -0.082740265f,
+ 0.996820299f, -0.079682438f,
+ 0.997060070f, -0.076623861f,
+ 0.997290457f, -0.073564564f,
+ 0.997511456f, -0.070504573f,
+ 0.997723067f, -0.067443920f,
+ 0.997925286f, -0.064382631f,
+ 0.998118113f, -0.061320736f,
+ 0.998301545f, -0.058258265f,
+ 0.998475581f, -0.055195244f,
+ 0.998640218f, -0.052131705f,
+ 0.998795456f, -0.049067674f,
+ 0.998941293f, -0.046003182f,
+ 0.999077728f, -0.042938257f,
+ 0.999204759f, -0.039872928f,
+ 0.999322385f, -0.036807223f,
+ 0.999430605f, -0.033741172f,
+ 0.999529418f, -0.030674803f,
+ 0.999618822f, -0.027608146f,
+ 0.999698819f, -0.024541229f,
+ 0.999769405f, -0.021474080f,
+ 0.999830582f, -0.018406730f,
+ 0.999882347f, -0.015339206f,
+ 0.999924702f, -0.012271538f,
+ 0.999957645f, -0.009203755f,
+ 0.999981175f, -0.006135885f,
+ 0.999995294f, -0.003067957f
+};
+
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* <pre>for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 4096 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+const float32_t twiddleCoef_4096[8192] = {
+ 1.000000000f, 0.000000000f,
+ 0.999998823f, 0.001533980f,
+ 0.999995294f, 0.003067957f,
+ 0.999989411f, 0.004601926f,
+ 0.999981175f, 0.006135885f,
+ 0.999970586f, 0.007669829f,
+ 0.999957645f, 0.009203755f,
+ 0.999942350f, 0.010737659f,
+ 0.999924702f, 0.012271538f,
+ 0.999904701f, 0.013805389f,
+ 0.999882347f, 0.015339206f,
+ 0.999857641f, 0.016872988f,
+ 0.999830582f, 0.018406730f,
+ 0.999801170f, 0.019940429f,
+ 0.999769405f, 0.021474080f,
+ 0.999735288f, 0.023007681f,
+ 0.999698819f, 0.024541229f,
+ 0.999659997f, 0.026074718f,
+ 0.999618822f, 0.027608146f,
+ 0.999575296f, 0.029141509f,
+ 0.999529418f, 0.030674803f,
+ 0.999481187f, 0.032208025f,
+ 0.999430605f, 0.033741172f,
+ 0.999377670f, 0.035274239f,
+ 0.999322385f, 0.036807223f,
+ 0.999264747f, 0.038340120f,
+ 0.999204759f, 0.039872928f,
+ 0.999142419f, 0.041405641f,
+ 0.999077728f, 0.042938257f,
+ 0.999010686f, 0.044470772f,
+ 0.998941293f, 0.046003182f,
+ 0.998869550f, 0.047535484f,
+ 0.998795456f, 0.049067674f,
+ 0.998719012f, 0.050599749f,
+ 0.998640218f, 0.052131705f,
+ 0.998559074f, 0.053663538f,
+ 0.998475581f, 0.055195244f,
+ 0.998389737f, 0.056726821f,
+ 0.998301545f, 0.058258265f,
+ 0.998211003f, 0.059789571f,
+ 0.998118113f, 0.061320736f,
+ 0.998022874f, 0.062851758f,
+ 0.997925286f, 0.064382631f,
+ 0.997825350f, 0.065913353f,
+ 0.997723067f, 0.067443920f,
+ 0.997618435f, 0.068974328f,
+ 0.997511456f, 0.070504573f,
+ 0.997402130f, 0.072034653f,
+ 0.997290457f, 0.073564564f,
+ 0.997176437f, 0.075094301f,
+ 0.997060070f, 0.076623861f,
+ 0.996941358f, 0.078153242f,
+ 0.996820299f, 0.079682438f,
+ 0.996696895f, 0.081211447f,
+ 0.996571146f, 0.082740265f,
+ 0.996443051f, 0.084268888f,
+ 0.996312612f, 0.085797312f,
+ 0.996179829f, 0.087325535f,
+ 0.996044701f, 0.088853553f,
+ 0.995907229f, 0.090381361f,
+ 0.995767414f, 0.091908956f,
+ 0.995625256f, 0.093436336f,
+ 0.995480755f, 0.094963495f,
+ 0.995333912f, 0.096490431f,
+ 0.995184727f, 0.098017140f,
+ 0.995033199f, 0.099543619f,
+ 0.994879331f, 0.101069863f,
+ 0.994723121f, 0.102595869f,
+ 0.994564571f, 0.104121634f,
+ 0.994403680f, 0.105647154f,
+ 0.994240449f, 0.107172425f,
+ 0.994074879f, 0.108697444f,
+ 0.993906970f, 0.110222207f,
+ 0.993736722f, 0.111746711f,
+ 0.993564136f, 0.113270952f,
+ 0.993389211f, 0.114794927f,
+ 0.993211949f, 0.116318631f,
+ 0.993032350f, 0.117842062f,
+ 0.992850414f, 0.119365215f,
+ 0.992666142f, 0.120888087f,
+ 0.992479535f, 0.122410675f,
+ 0.992290591f, 0.123932975f,
+ 0.992099313f, 0.125454983f,
+ 0.991905700f, 0.126976696f,
+ 0.991709754f, 0.128498111f,
+ 0.991511473f, 0.130019223f,
+ 0.991310860f, 0.131540029f,
+ 0.991107914f, 0.133060525f,
+ 0.990902635f, 0.134580709f,
+ 0.990695025f, 0.136100575f,
+ 0.990485084f, 0.137620122f,
+ 0.990272812f, 0.139139344f,
+ 0.990058210f, 0.140658239f,
+ 0.989841278f, 0.142176804f,
+ 0.989622017f, 0.143695033f,
+ 0.989400428f, 0.145212925f,
+ 0.989176510f, 0.146730474f,
+ 0.988950265f, 0.148247679f,
+ 0.988721692f, 0.149764535f,
+ 0.988490793f, 0.151281038f,
+ 0.988257568f, 0.152797185f,
+ 0.988022017f, 0.154312973f,
+ 0.987784142f, 0.155828398f,
+ 0.987543942f, 0.157343456f,
+ 0.987301418f, 0.158858143f,
+ 0.987056571f, 0.160372457f,
+ 0.986809402f, 0.161886394f,
+ 0.986559910f, 0.163399949f,
+ 0.986308097f, 0.164913120f,
+ 0.986053963f, 0.166425904f,
+ 0.985797509f, 0.167938295f,
+ 0.985538735f, 0.169450291f,
+ 0.985277642f, 0.170961889f,
+ 0.985014231f, 0.172473084f,
+ 0.984748502f, 0.173983873f,
+ 0.984480455f, 0.175494253f,
+ 0.984210092f, 0.177004220f,
+ 0.983937413f, 0.178513771f,
+ 0.983662419f, 0.180022901f,
+ 0.983385110f, 0.181531608f,
+ 0.983105487f, 0.183039888f,
+ 0.982823551f, 0.184547737f,
+ 0.982539302f, 0.186055152f,
+ 0.982252741f, 0.187562129f,
+ 0.981963869f, 0.189068664f,
+ 0.981672686f, 0.190574755f,
+ 0.981379193f, 0.192080397f,
+ 0.981083391f, 0.193585587f,
+ 0.980785280f, 0.195090322f,
+ 0.980484862f, 0.196594598f,
+ 0.980182136f, 0.198098411f,
+ 0.979877104f, 0.199601758f,
+ 0.979569766f, 0.201104635f,
+ 0.979260123f, 0.202607039f,
+ 0.978948175f, 0.204108966f,
+ 0.978633924f, 0.205610413f,
+ 0.978317371f, 0.207111376f,
+ 0.977998515f, 0.208611852f,
+ 0.977677358f, 0.210111837f,
+ 0.977353900f, 0.211611327f,
+ 0.977028143f, 0.213110320f,
+ 0.976700086f, 0.214608811f,
+ 0.976369731f, 0.216106797f,
+ 0.976037079f, 0.217604275f,
+ 0.975702130f, 0.219101240f,
+ 0.975364885f, 0.220597690f,
+ 0.975025345f, 0.222093621f,
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+ 0.927935395f, -0.372741067f,
+ 0.928506080f, -0.371317194f,
+ 0.929074581f, -0.369892447f,
+ 0.929640896f, -0.368466830f,
+ 0.930205023f, -0.367040346f,
+ 0.930766961f, -0.365612998f,
+ 0.931326709f, -0.364184790f,
+ 0.931884266f, -0.362755724f,
+ 0.932439629f, -0.361325806f,
+ 0.932992799f, -0.359895037f,
+ 0.933543773f, -0.358463421f,
+ 0.934092550f, -0.357030961f,
+ 0.934639130f, -0.355597662f,
+ 0.935183510f, -0.354163525f,
+ 0.935725689f, -0.352728556f,
+ 0.936265667f, -0.351292756f,
+ 0.936803442f, -0.349856130f,
+ 0.937339012f, -0.348418680f,
+ 0.937872376f, -0.346980411f,
+ 0.938403534f, -0.345541325f,
+ 0.938932484f, -0.344101426f,
+ 0.939459224f, -0.342660717f,
+ 0.939983753f, -0.341219202f,
+ 0.940506071f, -0.339776884f,
+ 0.941026175f, -0.338333767f,
+ 0.941544065f, -0.336889853f,
+ 0.942059740f, -0.335445147f,
+ 0.942573198f, -0.333999651f,
+ 0.943084437f, -0.332553370f,
+ 0.943593458f, -0.331106306f,
+ 0.944100258f, -0.329658463f,
+ 0.944604837f, -0.328209844f,
+ 0.945107193f, -0.326760452f,
+ 0.945607325f, -0.325310292f,
+ 0.946105232f, -0.323859367f,
+ 0.946600913f, -0.322407679f,
+ 0.947094366f, -0.320955232f,
+ 0.947585591f, -0.319502031f,
+ 0.948074586f, -0.318048077f,
+ 0.948561350f, -0.316593376f,
+ 0.949045882f, -0.315137929f,
+ 0.949528181f, -0.313681740f,
+ 0.950008245f, -0.312224814f,
+ 0.950486074f, -0.310767153f,
+ 0.950961666f, -0.309308760f,
+ 0.951435021f, -0.307849640f,
+ 0.951906137f, -0.306389795f,
+ 0.952375013f, -0.304929230f,
+ 0.952841648f, -0.303467947f,
+ 0.953306040f, -0.302005949f,
+ 0.953768190f, -0.300543241f,
+ 0.954228095f, -0.299079826f,
+ 0.954685755f, -0.297615707f,
+ 0.955141168f, -0.296150888f,
+ 0.955594334f, -0.294685372f,
+ 0.956045251f, -0.293219163f,
+ 0.956493919f, -0.291752263f,
+ 0.956940336f, -0.290284677f,
+ 0.957384501f, -0.288816408f,
+ 0.957826413f, -0.287347460f,
+ 0.958266071f, -0.285877835f,
+ 0.958703475f, -0.284407537f,
+ 0.959138622f, -0.282936570f,
+ 0.959571513f, -0.281464938f,
+ 0.960002146f, -0.279992643f,
+ 0.960430519f, -0.278519689f,
+ 0.960856633f, -0.277046080f,
+ 0.961280486f, -0.275571819f,
+ 0.961702077f, -0.274096910f,
+ 0.962121404f, -0.272621355f,
+ 0.962538468f, -0.271145160f,
+ 0.962953267f, -0.269668326f,
+ 0.963365800f, -0.268190857f,
+ 0.963776066f, -0.266712757f,
+ 0.964184064f, -0.265234030f,
+ 0.964589793f, -0.263754679f,
+ 0.964993253f, -0.262274707f,
+ 0.965394442f, -0.260794118f,
+ 0.965793359f, -0.259312915f,
+ 0.966190003f, -0.257831102f,
+ 0.966584374f, -0.256348682f,
+ 0.966976471f, -0.254865660f,
+ 0.967366292f, -0.253382037f,
+ 0.967753837f, -0.251897818f,
+ 0.968139105f, -0.250413007f,
+ 0.968522094f, -0.248927606f,
+ 0.968902805f, -0.247441619f,
+ 0.969281235f, -0.245955050f,
+ 0.969657385f, -0.244467903f,
+ 0.970031253f, -0.242980180f,
+ 0.970402839f, -0.241491885f,
+ 0.970772141f, -0.240003022f,
+ 0.971139158f, -0.238513595f,
+ 0.971503891f, -0.237023606f,
+ 0.971866337f, -0.235533059f,
+ 0.972226497f, -0.234041959f,
+ 0.972584369f, -0.232550307f,
+ 0.972939952f, -0.231058108f,
+ 0.973293246f, -0.229565366f,
+ 0.973644250f, -0.228072083f,
+ 0.973992962f, -0.226578264f,
+ 0.974339383f, -0.225083911f,
+ 0.974683511f, -0.223589029f,
+ 0.975025345f, -0.222093621f,
+ 0.975364885f, -0.220597690f,
+ 0.975702130f, -0.219101240f,
+ 0.976037079f, -0.217604275f,
+ 0.976369731f, -0.216106797f,
+ 0.976700086f, -0.214608811f,
+ 0.977028143f, -0.213110320f,
+ 0.977353900f, -0.211611327f,
+ 0.977677358f, -0.210111837f,
+ 0.977998515f, -0.208611852f,
+ 0.978317371f, -0.207111376f,
+ 0.978633924f, -0.205610413f,
+ 0.978948175f, -0.204108966f,
+ 0.979260123f, -0.202607039f,
+ 0.979569766f, -0.201104635f,
+ 0.979877104f, -0.199601758f,
+ 0.980182136f, -0.198098411f,
+ 0.980484862f, -0.196594598f,
+ 0.980785280f, -0.195090322f,
+ 0.981083391f, -0.193585587f,
+ 0.981379193f, -0.192080397f,
+ 0.981672686f, -0.190574755f,
+ 0.981963869f, -0.189068664f,
+ 0.982252741f, -0.187562129f,
+ 0.982539302f, -0.186055152f,
+ 0.982823551f, -0.184547737f,
+ 0.983105487f, -0.183039888f,
+ 0.983385110f, -0.181531608f,
+ 0.983662419f, -0.180022901f,
+ 0.983937413f, -0.178513771f,
+ 0.984210092f, -0.177004220f,
+ 0.984480455f, -0.175494253f,
+ 0.984748502f, -0.173983873f,
+ 0.985014231f, -0.172473084f,
+ 0.985277642f, -0.170961889f,
+ 0.985538735f, -0.169450291f,
+ 0.985797509f, -0.167938295f,
+ 0.986053963f, -0.166425904f,
+ 0.986308097f, -0.164913120f,
+ 0.986559910f, -0.163399949f,
+ 0.986809402f, -0.161886394f,
+ 0.987056571f, -0.160372457f,
+ 0.987301418f, -0.158858143f,
+ 0.987543942f, -0.157343456f,
+ 0.987784142f, -0.155828398f,
+ 0.988022017f, -0.154312973f,
+ 0.988257568f, -0.152797185f,
+ 0.988490793f, -0.151281038f,
+ 0.988721692f, -0.149764535f,
+ 0.988950265f, -0.148247679f,
+ 0.989176510f, -0.146730474f,
+ 0.989400428f, -0.145212925f,
+ 0.989622017f, -0.143695033f,
+ 0.989841278f, -0.142176804f,
+ 0.990058210f, -0.140658239f,
+ 0.990272812f, -0.139139344f,
+ 0.990485084f, -0.137620122f,
+ 0.990695025f, -0.136100575f,
+ 0.990902635f, -0.134580709f,
+ 0.991107914f, -0.133060525f,
+ 0.991310860f, -0.131540029f,
+ 0.991511473f, -0.130019223f,
+ 0.991709754f, -0.128498111f,
+ 0.991905700f, -0.126976696f,
+ 0.992099313f, -0.125454983f,
+ 0.992290591f, -0.123932975f,
+ 0.992479535f, -0.122410675f,
+ 0.992666142f, -0.120888087f,
+ 0.992850414f, -0.119365215f,
+ 0.993032350f, -0.117842062f,
+ 0.993211949f, -0.116318631f,
+ 0.993389211f, -0.114794927f,
+ 0.993564136f, -0.113270952f,
+ 0.993736722f, -0.111746711f,
+ 0.993906970f, -0.110222207f,
+ 0.994074879f, -0.108697444f,
+ 0.994240449f, -0.107172425f,
+ 0.994403680f, -0.105647154f,
+ 0.994564571f, -0.104121634f,
+ 0.994723121f, -0.102595869f,
+ 0.994879331f, -0.101069863f,
+ 0.995033199f, -0.099543619f,
+ 0.995184727f, -0.098017140f,
+ 0.995333912f, -0.096490431f,
+ 0.995480755f, -0.094963495f,
+ 0.995625256f, -0.093436336f,
+ 0.995767414f, -0.091908956f,
+ 0.995907229f, -0.090381361f,
+ 0.996044701f, -0.088853553f,
+ 0.996179829f, -0.087325535f,
+ 0.996312612f, -0.085797312f,
+ 0.996443051f, -0.084268888f,
+ 0.996571146f, -0.082740265f,
+ 0.996696895f, -0.081211447f,
+ 0.996820299f, -0.079682438f,
+ 0.996941358f, -0.078153242f,
+ 0.997060070f, -0.076623861f,
+ 0.997176437f, -0.075094301f,
+ 0.997290457f, -0.073564564f,
+ 0.997402130f, -0.072034653f,
+ 0.997511456f, -0.070504573f,
+ 0.997618435f, -0.068974328f,
+ 0.997723067f, -0.067443920f,
+ 0.997825350f, -0.065913353f,
+ 0.997925286f, -0.064382631f,
+ 0.998022874f, -0.062851758f,
+ 0.998118113f, -0.061320736f,
+ 0.998211003f, -0.059789571f,
+ 0.998301545f, -0.058258265f,
+ 0.998389737f, -0.056726821f,
+ 0.998475581f, -0.055195244f,
+ 0.998559074f, -0.053663538f,
+ 0.998640218f, -0.052131705f,
+ 0.998719012f, -0.050599749f,
+ 0.998795456f, -0.049067674f,
+ 0.998869550f, -0.047535484f,
+ 0.998941293f, -0.046003182f,
+ 0.999010686f, -0.044470772f,
+ 0.999077728f, -0.042938257f,
+ 0.999142419f, -0.041405641f,
+ 0.999204759f, -0.039872928f,
+ 0.999264747f, -0.038340120f,
+ 0.999322385f, -0.036807223f,
+ 0.999377670f, -0.035274239f,
+ 0.999430605f, -0.033741172f,
+ 0.999481187f, -0.032208025f,
+ 0.999529418f, -0.030674803f,
+ 0.999575296f, -0.029141509f,
+ 0.999618822f, -0.027608146f,
+ 0.999659997f, -0.026074718f,
+ 0.999698819f, -0.024541229f,
+ 0.999735288f, -0.023007681f,
+ 0.999769405f, -0.021474080f,
+ 0.999801170f, -0.019940429f,
+ 0.999830582f, -0.018406730f,
+ 0.999857641f, -0.016872988f,
+ 0.999882347f, -0.015339206f,
+ 0.999904701f, -0.013805389f,
+ 0.999924702f, -0.012271538f,
+ 0.999942350f, -0.010737659f,
+ 0.999957645f, -0.009203755f,
+ 0.999970586f, -0.007669829f,
+ 0.999981175f, -0.006135885f,
+ 0.999989411f, -0.004601926f,
+ 0.999995294f, -0.003067957f,
+ 0.999998823f, -0.001533980f
+};
+
+/*
+* @brief Q31 Twiddle factors Table
+*/
+
+
+/**
+* \par
+* Example code for Q31 Twiddle factors Generation::
+* \par
+* <pre>for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 16 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to Q31(Fixed point 1.31):
+* round(twiddleCoefQ31(i) * pow(2, 31))
+*
+*/
+const q31_t twiddleCoef_16_q31[24] = {
+ (q31_t)0x7FFFFFFF, (q31_t)0x00000000,
+ (q31_t)0x7641AF3C, (q31_t)0x30FBC54D,
+ (q31_t)0x5A82799A, (q31_t)0x5A82799A,
+ (q31_t)0x30FBC54D, (q31_t)0x7641AF3C,
+ (q31_t)0x00000000, (q31_t)0x7FFFFFFF,
+ (q31_t)0xCF043AB2, (q31_t)0x7641AF3C,
+ (q31_t)0xA57D8666, (q31_t)0x5A82799A,
+ (q31_t)0x89BE50C3, (q31_t)0x30FBC54D,
+ (q31_t)0x80000000, (q31_t)0x00000000,
+ (q31_t)0x89BE50C3, (q31_t)0xCF043AB2,
+ (q31_t)0xA57D8666, (q31_t)0xA57D8666,
+ (q31_t)0xCF043AB2, (q31_t)0x89BE50C3
+};
+
+/**
+* \par
+* Example code for Q31 Twiddle factors Generation::
+* \par
+* <pre>for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 32 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to Q31(Fixed point 1.31):
+* round(twiddleCoefQ31(i) * pow(2, 31))
+*
+*/
+const q31_t twiddleCoef_32_q31[48] = {
+ (q31_t)0x7FFFFFFF, (q31_t)0x00000000,
+ (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C,
+ (q31_t)0x7641AF3C, (q31_t)0x30FBC54D,
+ (q31_t)0x6A6D98A4, (q31_t)0x471CECE6,
+ (q31_t)0x5A82799A, (q31_t)0x5A82799A,
+ (q31_t)0x471CECE6, (q31_t)0x6A6D98A4,
+ (q31_t)0x30FBC54D, (q31_t)0x7641AF3C,
+ (q31_t)0x18F8B83C, (q31_t)0x7D8A5F3F,
+ (q31_t)0x00000000, (q31_t)0x7FFFFFFF,
+ (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F,
+ (q31_t)0xCF043AB2, (q31_t)0x7641AF3C,
+ (q31_t)0xB8E31319, (q31_t)0x6A6D98A4,
+ (q31_t)0xA57D8666, (q31_t)0x5A82799A,
+ (q31_t)0x9592675B, (q31_t)0x471CECE6,
+ (q31_t)0x89BE50C3, (q31_t)0x30FBC54D,
+ (q31_t)0x8275A0C0, (q31_t)0x18F8B83C,
+ (q31_t)0x80000000, (q31_t)0x00000000,
+ (q31_t)0x8275A0C0, (q31_t)0xE70747C3,
+ (q31_t)0x89BE50C3, (q31_t)0xCF043AB2,
+ (q31_t)0x9592675B, (q31_t)0xB8E31319,
+ (q31_t)0xA57D8666, (q31_t)0xA57D8666,
+ (q31_t)0xB8E31319, (q31_t)0x9592675B,
+ (q31_t)0xCF043AB2, (q31_t)0x89BE50C3,
+ (q31_t)0xE70747C3, (q31_t)0x8275A0C0
+};
+
+/**
+* \par
+* Example code for Q31 Twiddle factors Generation::
+* \par
+* <pre>for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 64 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to Q31(Fixed point 1.31):
+* round(twiddleCoefQ31(i) * pow(2, 31))
+*
+*/
+const q31_t twiddleCoef_64_q31[96] = {
+ (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7F62368F,
+ (q31_t)0x0C8BD35E, (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C,
+ (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7641AF3C,
+ (q31_t)0x30FBC54D, (q31_t)0x70E2CBC6, (q31_t)0x3C56BA70,
+ (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x62F201AC,
+ (q31_t)0x5133CC94, (q31_t)0x5A82799A, (q31_t)0x5A82799A,
+ (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x471CECE6,
+ (q31_t)0x6A6D98A4, (q31_t)0x3C56BA70, (q31_t)0x70E2CBC6,
+ (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x25280C5D,
+ (q31_t)0x7A7D055B, (q31_t)0x18F8B83C, (q31_t)0x7D8A5F3F,
+ (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x00000000,
+ (q31_t)0x7FFFFFFF, (q31_t)0xF3742CA1, (q31_t)0x7F62368F,
+ (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xDAD7F3A2,
+ (q31_t)0x7A7D055B, (q31_t)0xCF043AB2, (q31_t)0x7641AF3C,
+ (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xB8E31319,
+ (q31_t)0x6A6D98A4, (q31_t)0xAECC336B, (q31_t)0x62F201AC,
+ (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0x9D0DFE53,
+ (q31_t)0x5133CC94, (q31_t)0x9592675B, (q31_t)0x471CECE6,
+ (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x89BE50C3,
+ (q31_t)0x30FBC54D, (q31_t)0x8582FAA4, (q31_t)0x25280C5D,
+ (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x809DC970,
+ (q31_t)0x0C8BD35E, (q31_t)0x80000000, (q31_t)0x00000000,
+ (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x8275A0C0,
+ (q31_t)0xE70747C3, (q31_t)0x8582FAA4, (q31_t)0xDAD7F3A2,
+ (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8F1D343A,
+ (q31_t)0xC3A9458F, (q31_t)0x9592675B, (q31_t)0xB8E31319,
+ (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0xA57D8666,
+ (q31_t)0xA57D8666, (q31_t)0xAECC336B, (q31_t)0x9D0DFE53,
+ (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xC3A9458F,
+ (q31_t)0x8F1D343A, (q31_t)0xCF043AB2, (q31_t)0x89BE50C3,
+ (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xE70747C3,
+ (q31_t)0x8275A0C0, (q31_t)0xF3742CA1, (q31_t)0x809DC970
+};
+
+/**
+* \par
+* Example code for Q31 Twiddle factors Generation::
+* \par
+* <pre>for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 128 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to Q31(Fixed point 1.31):
+* round(twiddleCoefQ31(i) * pow(2, 31))
+*
+*/
+const q31_t twiddleCoef_128_q31[192] = {
+ (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FD8878D,
+ (q31_t)0x0647D97C, (q31_t)0x7F62368F, (q31_t)0x0C8BD35E,
+ (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7D8A5F3F,
+ (q31_t)0x18F8B83C, (q31_t)0x7C29FBEE, (q31_t)0x1F19F97B,
+ (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x78848413,
+ (q31_t)0x2B1F34EB, (q31_t)0x7641AF3C, (q31_t)0x30FBC54D,
+ (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x70E2CBC6,
+ (q31_t)0x3C56BA70, (q31_t)0x6DCA0D14, (q31_t)0x41CE1E64,
+ (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x66CF811F,
+ (q31_t)0x4C3FDFF3, (q31_t)0x62F201AC, (q31_t)0x5133CC94,
+ (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5A82799A,
+ (q31_t)0x5A82799A, (q31_t)0x55F5A4D2, (q31_t)0x5ED77C89,
+ (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x4C3FDFF3,
+ (q31_t)0x66CF811F, (q31_t)0x471CECE6, (q31_t)0x6A6D98A4,
+ (q31_t)0x41CE1E64, (q31_t)0x6DCA0D14, (q31_t)0x3C56BA70,
+ (q31_t)0x70E2CBC6, (q31_t)0x36BA2013, (q31_t)0x73B5EBD0,
+ (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x2B1F34EB,
+ (q31_t)0x78848413, (q31_t)0x25280C5D, (q31_t)0x7A7D055B,
+ (q31_t)0x1F19F97B, (q31_t)0x7C29FBEE, (q31_t)0x18F8B83C,
+ (q31_t)0x7D8A5F3F, (q31_t)0x12C8106E, (q31_t)0x7E9D55FC,
+ (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x0647D97C,
+ (q31_t)0x7FD8878D, (q31_t)0x00000000, (q31_t)0x7FFFFFFF,
+ (q31_t)0xF9B82683, (q31_t)0x7FD8878D, (q31_t)0xF3742CA1,
+ (q31_t)0x7F62368F, (q31_t)0xED37EF91, (q31_t)0x7E9D55FC,
+ (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xE0E60684,
+ (q31_t)0x7C29FBEE, (q31_t)0xDAD7F3A2, (q31_t)0x7A7D055B,
+ (q31_t)0xD4E0CB14, (q31_t)0x78848413, (q31_t)0xCF043AB2,
+ (q31_t)0x7641AF3C, (q31_t)0xC945DFEC, (q31_t)0x73B5EBD0,
+ (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xBE31E19B,
+ (q31_t)0x6DCA0D14, (q31_t)0xB8E31319, (q31_t)0x6A6D98A4,
+ (q31_t)0xB3C0200C, (q31_t)0x66CF811F, (q31_t)0xAECC336B,
+ (q31_t)0x62F201AC, (q31_t)0xAA0A5B2D, (q31_t)0x5ED77C89,
+ (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0xA1288376,
+ (q31_t)0x55F5A4D2, (q31_t)0x9D0DFE53, (q31_t)0x5133CC94,
+ (q31_t)0x99307EE0, (q31_t)0x4C3FDFF3, (q31_t)0x9592675B,
+ (q31_t)0x471CECE6, (q31_t)0x9235F2EB, (q31_t)0x41CE1E64,
+ (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x8C4A142F,
+ (q31_t)0x36BA2013, (q31_t)0x89BE50C3, (q31_t)0x30FBC54D,
+ (q31_t)0x877B7BEC, (q31_t)0x2B1F34EB, (q31_t)0x8582FAA4,
+ (q31_t)0x25280C5D, (q31_t)0x83D60411, (q31_t)0x1F19F97B,
+ (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x8162AA03,
+ (q31_t)0x12C8106E, (q31_t)0x809DC970, (q31_t)0x0C8BD35E,
+ (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x80000000,
+ (q31_t)0x00000000, (q31_t)0x80277872, (q31_t)0xF9B82683,
+ (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x8162AA03,
+ (q31_t)0xED37EF91, (q31_t)0x8275A0C0, (q31_t)0xE70747C3,
+ (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x8582FAA4,
+ (q31_t)0xDAD7F3A2, (q31_t)0x877B7BEC, (q31_t)0xD4E0CB14,
+ (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8C4A142F,
+ (q31_t)0xC945DFEC, (q31_t)0x8F1D343A, (q31_t)0xC3A9458F,
+ (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x9592675B,
+ (q31_t)0xB8E31319, (q31_t)0x99307EE0, (q31_t)0xB3C0200C,
+ (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0xA1288376,
+ (q31_t)0xAA0A5B2D, (q31_t)0xA57D8666, (q31_t)0xA57D8666,
+ (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAECC336B,
+ (q31_t)0x9D0DFE53, (q31_t)0xB3C0200C, (q31_t)0x99307EE0,
+ (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xBE31E19B,
+ (q31_t)0x9235F2EB, (q31_t)0xC3A9458F, (q31_t)0x8F1D343A,
+ (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xCF043AB2,
+ (q31_t)0x89BE50C3, (q31_t)0xD4E0CB14, (q31_t)0x877B7BEC,
+ (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xE0E60684,
+ (q31_t)0x83D60411, (q31_t)0xE70747C3, (q31_t)0x8275A0C0,
+ (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xF3742CA1,
+ (q31_t)0x809DC970, (q31_t)0xF9B82683, (q31_t)0x80277872
+};
+
+/**
+* \par
+* Example code for Q31 Twiddle factors Generation::
+* \par
+* <pre>for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 256 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to Q31(Fixed point 1.31):
+* round(twiddleCoefQ31(i) * pow(2, 31))
+*
+*/
+const q31_t twiddleCoef_256_q31[384] = {
+ (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FF62182,
+ (q31_t)0x03242ABF, (q31_t)0x7FD8878D, (q31_t)0x0647D97C,
+ (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7F62368F,
+ (q31_t)0x0C8BD35E, (q31_t)0x7F0991C3, (q31_t)0x0FAB272B,
+ (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E1D93E9,
+ (q31_t)0x15E21444, (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C,
+ (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7C29FBEE,
+ (q31_t)0x1F19F97B, (q31_t)0x7B5D039D, (q31_t)0x2223A4C5,
+ (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x798A23B1,
+ (q31_t)0x2826B928, (q31_t)0x78848413, (q31_t)0x2B1F34EB,
+ (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x7641AF3C,
+ (q31_t)0x30FBC54D, (q31_t)0x7504D345, (q31_t)0x33DEF287,
+ (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x72552C84,
+ (q31_t)0x398CDD32, (q31_t)0x70E2CBC6, (q31_t)0x3C56BA70,
+ (q31_t)0x6F5F02B1, (q31_t)0x3F1749B7, (q31_t)0x6DCA0D14,
+ (q31_t)0x41CE1E64, (q31_t)0x6C242960, (q31_t)0x447ACD50,
+ (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x68A69E81,
+ (q31_t)0x49B41533, (q31_t)0x66CF811F, (q31_t)0x4C3FDFF3,
+ (q31_t)0x64E88926, (q31_t)0x4EBFE8A4, (q31_t)0x62F201AC,
+ (q31_t)0x5133CC94, (q31_t)0x60EC3830, (q31_t)0x539B2AEF,
+ (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5CB420DF,
+ (q31_t)0x5842DD54, (q31_t)0x5A82799A, (q31_t)0x5A82799A,
+ (q31_t)0x5842DD54, (q31_t)0x5CB420DF, (q31_t)0x55F5A4D2,
+ (q31_t)0x5ED77C89, (q31_t)0x539B2AEF, (q31_t)0x60EC3830,
+ (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x4EBFE8A4,
+ (q31_t)0x64E88926, (q31_t)0x4C3FDFF3, (q31_t)0x66CF811F,
+ (q31_t)0x49B41533, (q31_t)0x68A69E81, (q31_t)0x471CECE6,
+ (q31_t)0x6A6D98A4, (q31_t)0x447ACD50, (q31_t)0x6C242960,
+ (q31_t)0x41CE1E64, (q31_t)0x6DCA0D14, (q31_t)0x3F1749B7,
+ (q31_t)0x6F5F02B1, (q31_t)0x3C56BA70, (q31_t)0x70E2CBC6,
+ (q31_t)0x398CDD32, (q31_t)0x72552C84, (q31_t)0x36BA2013,
+ (q31_t)0x73B5EBD0, (q31_t)0x33DEF287, (q31_t)0x7504D345,
+ (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x2E110A62,
+ (q31_t)0x776C4EDB, (q31_t)0x2B1F34EB, (q31_t)0x78848413,
+ (q31_t)0x2826B928, (q31_t)0x798A23B1, (q31_t)0x25280C5D,
+ (q31_t)0x7A7D055B, (q31_t)0x2223A4C5, (q31_t)0x7B5D039D,
+ (q31_t)0x1F19F97B, (q31_t)0x7C29FBEE, (q31_t)0x1C0B826A,
+ (q31_t)0x7CE3CEB1, (q31_t)0x18F8B83C, (q31_t)0x7D8A5F3F,
+ (q31_t)0x15E21444, (q31_t)0x7E1D93E9, (q31_t)0x12C8106E,
+ (q31_t)0x7E9D55FC, (q31_t)0x0FAB272B, (q31_t)0x7F0991C3,
+ (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x096A9049,
+ (q31_t)0x7FA736B4, (q31_t)0x0647D97C, (q31_t)0x7FD8878D,
+ (q31_t)0x03242ABF, (q31_t)0x7FF62182, (q31_t)0x00000000,
+ (q31_t)0x7FFFFFFF, (q31_t)0xFCDBD541, (q31_t)0x7FF62182,
+ (q31_t)0xF9B82683, (q31_t)0x7FD8878D, (q31_t)0xF6956FB6,
+ (q31_t)0x7FA736B4, (q31_t)0xF3742CA1, (q31_t)0x7F62368F,
+ (q31_t)0xF054D8D4, (q31_t)0x7F0991C3, (q31_t)0xED37EF91,
+ (q31_t)0x7E9D55FC, (q31_t)0xEA1DEBBB, (q31_t)0x7E1D93E9,
+ (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xE3F47D95,
+ (q31_t)0x7CE3CEB1, (q31_t)0xE0E60684, (q31_t)0x7C29FBEE,
+ (q31_t)0xDDDC5B3A, (q31_t)0x7B5D039D, (q31_t)0xDAD7F3A2,
+ (q31_t)0x7A7D055B, (q31_t)0xD7D946D7, (q31_t)0x798A23B1,
+ (q31_t)0xD4E0CB14, (q31_t)0x78848413, (q31_t)0xD1EEF59E,
+ (q31_t)0x776C4EDB, (q31_t)0xCF043AB2, (q31_t)0x7641AF3C,
+ (q31_t)0xCC210D78, (q31_t)0x7504D345, (q31_t)0xC945DFEC,
+ (q31_t)0x73B5EBD0, (q31_t)0xC67322CD, (q31_t)0x72552C84,
+ (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xC0E8B648,
+ (q31_t)0x6F5F02B1, (q31_t)0xBE31E19B, (q31_t)0x6DCA0D14,
+ (q31_t)0xBB8532AF, (q31_t)0x6C242960, (q31_t)0xB8E31319,
+ (q31_t)0x6A6D98A4, (q31_t)0xB64BEACC, (q31_t)0x68A69E81,
+ (q31_t)0xB3C0200C, (q31_t)0x66CF811F, (q31_t)0xB140175B,
+ (q31_t)0x64E88926, (q31_t)0xAECC336B, (q31_t)0x62F201AC,
+ (q31_t)0xAC64D510, (q31_t)0x60EC3830, (q31_t)0xAA0A5B2D,
+ (q31_t)0x5ED77C89, (q31_t)0xA7BD22AB, (q31_t)0x5CB420DF,
+ (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0xA34BDF20,
+ (q31_t)0x5842DD54, (q31_t)0xA1288376, (q31_t)0x55F5A4D2,
+ (q31_t)0x9F13C7D0, (q31_t)0x539B2AEF, (q31_t)0x9D0DFE53,
+ (q31_t)0x5133CC94, (q31_t)0x9B1776D9, (q31_t)0x4EBFE8A4,
+ (q31_t)0x99307EE0, (q31_t)0x4C3FDFF3, (q31_t)0x9759617E,
+ (q31_t)0x49B41533, (q31_t)0x9592675B, (q31_t)0x471CECE6,
+ (q31_t)0x93DBD69F, (q31_t)0x447ACD50, (q31_t)0x9235F2EB,
+ (q31_t)0x41CE1E64, (q31_t)0x90A0FD4E, (q31_t)0x3F1749B7,
+ (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x8DAAD37B,
+ (q31_t)0x398CDD32, (q31_t)0x8C4A142F, (q31_t)0x36BA2013,
+ (q31_t)0x8AFB2CBA, (q31_t)0x33DEF287, (q31_t)0x89BE50C3,
+ (q31_t)0x30FBC54D, (q31_t)0x8893B124, (q31_t)0x2E110A62,
+ (q31_t)0x877B7BEC, (q31_t)0x2B1F34EB, (q31_t)0x8675DC4E,
+ (q31_t)0x2826B928, (q31_t)0x8582FAA4, (q31_t)0x25280C5D,
+ (q31_t)0x84A2FC62, (q31_t)0x2223A4C5, (q31_t)0x83D60411,
+ (q31_t)0x1F19F97B, (q31_t)0x831C314E, (q31_t)0x1C0B826A,
+ (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x81E26C16,
+ (q31_t)0x15E21444, (q31_t)0x8162AA03, (q31_t)0x12C8106E,
+ (q31_t)0x80F66E3C, (q31_t)0x0FAB272B, (q31_t)0x809DC970,
+ (q31_t)0x0C8BD35E, (q31_t)0x8058C94C, (q31_t)0x096A9049,
+ (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x8009DE7D,
+ (q31_t)0x03242ABF, (q31_t)0x80000000, (q31_t)0x00000000,
+ (q31_t)0x8009DE7D, (q31_t)0xFCDBD541, (q31_t)0x80277872,
+ (q31_t)0xF9B82683, (q31_t)0x8058C94C, (q31_t)0xF6956FB6,
+ (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x80F66E3C,
+ (q31_t)0xF054D8D4, (q31_t)0x8162AA03, (q31_t)0xED37EF91,
+ (q31_t)0x81E26C16, (q31_t)0xEA1DEBBB, (q31_t)0x8275A0C0,
+ (q31_t)0xE70747C3, (q31_t)0x831C314E, (q31_t)0xE3F47D95,
+ (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x84A2FC62,
+ (q31_t)0xDDDC5B3A, (q31_t)0x8582FAA4, (q31_t)0xDAD7F3A2,
+ (q31_t)0x8675DC4E, (q31_t)0xD7D946D7, (q31_t)0x877B7BEC,
+ (q31_t)0xD4E0CB14, (q31_t)0x8893B124, (q31_t)0xD1EEF59E,
+ (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8AFB2CBA,
+ (q31_t)0xCC210D78, (q31_t)0x8C4A142F, (q31_t)0xC945DFEC,
+ (q31_t)0x8DAAD37B, (q31_t)0xC67322CD, (q31_t)0x8F1D343A,
+ (q31_t)0xC3A9458F, (q31_t)0x90A0FD4E, (q31_t)0xC0E8B648,
+ (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x93DBD69F,
+ (q31_t)0xBB8532AF, (q31_t)0x9592675B, (q31_t)0xB8E31319,
+ (q31_t)0x9759617E, (q31_t)0xB64BEACC, (q31_t)0x99307EE0,
+ (q31_t)0xB3C0200C, (q31_t)0x9B1776D9, (q31_t)0xB140175B,
+ (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0x9F13C7D0,
+ (q31_t)0xAC64D510, (q31_t)0xA1288376, (q31_t)0xAA0A5B2D,
+ (q31_t)0xA34BDF20, (q31_t)0xA7BD22AB, (q31_t)0xA57D8666,
+ (q31_t)0xA57D8666, (q31_t)0xA7BD22AB, (q31_t)0xA34BDF20,
+ (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAC64D510,
+ (q31_t)0x9F13C7D0, (q31_t)0xAECC336B, (q31_t)0x9D0DFE53,
+ (q31_t)0xB140175B, (q31_t)0x9B1776D9, (q31_t)0xB3C0200C,
+ (q31_t)0x99307EE0, (q31_t)0xB64BEACC, (q31_t)0x9759617E,
+ (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xBB8532AF,
+ (q31_t)0x93DBD69F, (q31_t)0xBE31E19B, (q31_t)0x9235F2EB,
+ (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC3A9458F,
+ (q31_t)0x8F1D343A, (q31_t)0xC67322CD, (q31_t)0x8DAAD37B,
+ (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xCC210D78,
+ (q31_t)0x8AFB2CBA, (q31_t)0xCF043AB2, (q31_t)0x89BE50C3,
+ (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD4E0CB14,
+ (q31_t)0x877B7BEC, (q31_t)0xD7D946D7, (q31_t)0x8675DC4E,
+ (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDDDC5B3A,
+ (q31_t)0x84A2FC62, (q31_t)0xE0E60684, (q31_t)0x83D60411,
+ (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE70747C3,
+ (q31_t)0x8275A0C0, (q31_t)0xEA1DEBBB, (q31_t)0x81E26C16,
+ (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xF054D8D4,
+ (q31_t)0x80F66E3C, (q31_t)0xF3742CA1, (q31_t)0x809DC970,
+ (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF9B82683,
+ (q31_t)0x80277872, (q31_t)0xFCDBD541, (q31_t)0x8009DE7D
+};
+
+/**
+* \par
+* Example code for Q31 Twiddle factors Generation::
+* \par
+* <pre>for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 512 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to Q31(Fixed point 1.31):
+* round(twiddleCoefQ31(i) * pow(2, 31))
+*
+*/
+const q31_t twiddleCoef_512_q31[768] = {
+ (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FFD885A,
+ (q31_t)0x01921D1F, (q31_t)0x7FF62182, (q31_t)0x03242ABF,
+ (q31_t)0x7FE9CBC0, (q31_t)0x04B6195D, (q31_t)0x7FD8878D,
+ (q31_t)0x0647D97C, (q31_t)0x7FC25596, (q31_t)0x07D95B9E,
+ (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7F872BF3,
+ (q31_t)0x0AFB6805, (q31_t)0x7F62368F, (q31_t)0x0C8BD35E,
+ (q31_t)0x7F3857F5, (q31_t)0x0E1BC2E3, (q31_t)0x7F0991C3,
+ (q31_t)0x0FAB272B, (q31_t)0x7ED5E5C6, (q31_t)0x1139F0CE,
+ (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E5FE493,
+ (q31_t)0x145576B1, (q31_t)0x7E1D93E9, (q31_t)0x15E21444,
+ (q31_t)0x7DD6668E, (q31_t)0x176DD9DE, (q31_t)0x7D8A5F3F,
+ (q31_t)0x18F8B83C, (q31_t)0x7D3980EC, (q31_t)0x1A82A025,
+ (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7C894BDD,
+ (q31_t)0x1D934FE5, (q31_t)0x7C29FBEE, (q31_t)0x1F19F97B,
+ (q31_t)0x7BC5E28F, (q31_t)0x209F701C, (q31_t)0x7B5D039D,
+ (q31_t)0x2223A4C5, (q31_t)0x7AEF6323, (q31_t)0x23A6887E,
+ (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7A05EEAD,
+ (q31_t)0x26A82185, (q31_t)0x798A23B1, (q31_t)0x2826B928,
+ (q31_t)0x7909A92C, (q31_t)0x29A3C484, (q31_t)0x78848413,
+ (q31_t)0x2B1F34EB, (q31_t)0x77FAB988, (q31_t)0x2C98FBBA,
+ (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x76D94988,
+ (q31_t)0x2F875262, (q31_t)0x7641AF3C, (q31_t)0x30FBC54D,
+ (q31_t)0x75A585CF, (q31_t)0x326E54C7, (q31_t)0x7504D345,
+ (q31_t)0x33DEF287, (q31_t)0x745F9DD1, (q31_t)0x354D9056,
+ (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x7307C3D0,
+ (q31_t)0x382493B0, (q31_t)0x72552C84, (q31_t)0x398CDD32,
+ (q31_t)0x719E2CD2, (q31_t)0x3AF2EEB7, (q31_t)0x70E2CBC6,
+ (q31_t)0x3C56BA70, (q31_t)0x70231099, (q31_t)0x3DB832A5,
+ (q31_t)0x6F5F02B1, (q31_t)0x3F1749B7, (q31_t)0x6E96A99C,
+ (q31_t)0x4073F21D, (q31_t)0x6DCA0D14, (q31_t)0x41CE1E64,
+ (q31_t)0x6CF934FB, (q31_t)0x4325C135, (q31_t)0x6C242960,
+ (q31_t)0x447ACD50, (q31_t)0x6B4AF278, (q31_t)0x45CD358F,
+ (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x698C246C,
+ (q31_t)0x4869E664, (q31_t)0x68A69E81, (q31_t)0x49B41533,
+ (q31_t)0x67BD0FBC, (q31_t)0x4AFB6C97, (q31_t)0x66CF811F,
+ (q31_t)0x4C3FDFF3, (q31_t)0x65DDFBD3, (q31_t)0x4D8162C4,
+ (q31_t)0x64E88926, (q31_t)0x4EBFE8A4, (q31_t)0x63EF328F,
+ (q31_t)0x4FFB654D, (q31_t)0x62F201AC, (q31_t)0x5133CC94,
+ (q31_t)0x61F1003E, (q31_t)0x5269126E, (q31_t)0x60EC3830,
+ (q31_t)0x539B2AEF, (q31_t)0x5FE3B38D, (q31_t)0x54CA0A4A,
+ (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5DC79D7C,
+ (q31_t)0x571DEEF9, (q31_t)0x5CB420DF, (q31_t)0x5842DD54,
+ (q31_t)0x5B9D1153, (q31_t)0x59646497, (q31_t)0x5A82799A,
+ (q31_t)0x5A82799A, (q31_t)0x59646497, (q31_t)0x5B9D1153,
+ (q31_t)0x5842DD54, (q31_t)0x5CB420DF, (q31_t)0x571DEEF9,
+ (q31_t)0x5DC79D7C, (q31_t)0x55F5A4D2, (q31_t)0x5ED77C89,
+ (q31_t)0x54CA0A4A, (q31_t)0x5FE3B38D, (q31_t)0x539B2AEF,
+ (q31_t)0x60EC3830, (q31_t)0x5269126E, (q31_t)0x61F1003E,
+ (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x4FFB654D,
+ (q31_t)0x63EF328F, (q31_t)0x4EBFE8A4, (q31_t)0x64E88926,
+ (q31_t)0x4D8162C4, (q31_t)0x65DDFBD3, (q31_t)0x4C3FDFF3,
+ (q31_t)0x66CF811F, (q31_t)0x4AFB6C97, (q31_t)0x67BD0FBC,
+ (q31_t)0x49B41533, (q31_t)0x68A69E81, (q31_t)0x4869E664,
+ (q31_t)0x698C246C, (q31_t)0x471CECE6, (q31_t)0x6A6D98A4,
+ (q31_t)0x45CD358F, (q31_t)0x6B4AF278, (q31_t)0x447ACD50,
+ (q31_t)0x6C242960, (q31_t)0x4325C135, (q31_t)0x6CF934FB,
+ (q31_t)0x41CE1E64, (q31_t)0x6DCA0D14, (q31_t)0x4073F21D,
+ (q31_t)0x6E96A99C, (q31_t)0x3F1749B7, (q31_t)0x6F5F02B1,
+ (q31_t)0x3DB832A5, (q31_t)0x70231099, (q31_t)0x3C56BA70,
+ (q31_t)0x70E2CBC6, (q31_t)0x3AF2EEB7, (q31_t)0x719E2CD2,
+ (q31_t)0x398CDD32, (q31_t)0x72552C84, (q31_t)0x382493B0,
+ (q31_t)0x7307C3D0, (q31_t)0x36BA2013, (q31_t)0x73B5EBD0,
+ (q31_t)0x354D9056, (q31_t)0x745F9DD1, (q31_t)0x33DEF287,
+ (q31_t)0x7504D345, (q31_t)0x326E54C7, (q31_t)0x75A585CF,
+ (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x2F875262,
+ (q31_t)0x76D94988, (q31_t)0x2E110A62, (q31_t)0x776C4EDB,
+ (q31_t)0x2C98FBBA, (q31_t)0x77FAB988, (q31_t)0x2B1F34EB,
+ (q31_t)0x78848413, (q31_t)0x29A3C484, (q31_t)0x7909A92C,
+ (q31_t)0x2826B928, (q31_t)0x798A23B1, (q31_t)0x26A82185,
+ (q31_t)0x7A05EEAD, (q31_t)0x25280C5D, (q31_t)0x7A7D055B,
+ (q31_t)0x23A6887E, (q31_t)0x7AEF6323, (q31_t)0x2223A4C5,
+ (q31_t)0x7B5D039D, (q31_t)0x209F701C, (q31_t)0x7BC5E28F,
+ (q31_t)0x1F19F97B, (q31_t)0x7C29FBEE, (q31_t)0x1D934FE5,
+ (q31_t)0x7C894BDD, (q31_t)0x1C0B826A, (q31_t)0x7CE3CEB1,
+ (q31_t)0x1A82A025, (q31_t)0x7D3980EC, (q31_t)0x18F8B83C,
+ (q31_t)0x7D8A5F3F, (q31_t)0x176DD9DE, (q31_t)0x7DD6668E,
+ (q31_t)0x15E21444, (q31_t)0x7E1D93E9, (q31_t)0x145576B1,
+ (q31_t)0x7E5FE493, (q31_t)0x12C8106E, (q31_t)0x7E9D55FC,
+ (q31_t)0x1139F0CE, (q31_t)0x7ED5E5C6, (q31_t)0x0FAB272B,
+ (q31_t)0x7F0991C3, (q31_t)0x0E1BC2E3, (q31_t)0x7F3857F5,
+ (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x0AFB6805,
+ (q31_t)0x7F872BF3, (q31_t)0x096A9049, (q31_t)0x7FA736B4,
+ (q31_t)0x07D95B9E, (q31_t)0x7FC25596, (q31_t)0x0647D97C,
+ (q31_t)0x7FD8878D, (q31_t)0x04B6195D, (q31_t)0x7FE9CBC0,
+ (q31_t)0x03242ABF, (q31_t)0x7FF62182, (q31_t)0x01921D1F,
+ (q31_t)0x7FFD885A, (q31_t)0x00000000, (q31_t)0x7FFFFFFF,
+ (q31_t)0xFE6DE2E0, (q31_t)0x7FFD885A, (q31_t)0xFCDBD541,
+ (q31_t)0x7FF62182, (q31_t)0xFB49E6A2, (q31_t)0x7FE9CBC0,
+ (q31_t)0xF9B82683, (q31_t)0x7FD8878D, (q31_t)0xF826A461,
+ (q31_t)0x7FC25596, (q31_t)0xF6956FB6, (q31_t)0x7FA736B4,
+ (q31_t)0xF50497FA, (q31_t)0x7F872BF3, (q31_t)0xF3742CA1,
+ (q31_t)0x7F62368F, (q31_t)0xF1E43D1C, (q31_t)0x7F3857F5,
+ (q31_t)0xF054D8D4, (q31_t)0x7F0991C3, (q31_t)0xEEC60F31,
+ (q31_t)0x7ED5E5C6, (q31_t)0xED37EF91, (q31_t)0x7E9D55FC,
+ (q31_t)0xEBAA894E, (q31_t)0x7E5FE493, (q31_t)0xEA1DEBBB,
+ (q31_t)0x7E1D93E9, (q31_t)0xE8922621, (q31_t)0x7DD6668E,
+ (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xE57D5FDA,
+ (q31_t)0x7D3980EC, (q31_t)0xE3F47D95, (q31_t)0x7CE3CEB1,
+ (q31_t)0xE26CB01A, (q31_t)0x7C894BDD, (q31_t)0xE0E60684,
+ (q31_t)0x7C29FBEE, (q31_t)0xDF608FE3, (q31_t)0x7BC5E28F,
+ (q31_t)0xDDDC5B3A, (q31_t)0x7B5D039D, (q31_t)0xDC597781,
+ (q31_t)0x7AEF6323, (q31_t)0xDAD7F3A2, (q31_t)0x7A7D055B,
+ (q31_t)0xD957DE7A, (q31_t)0x7A05EEAD, (q31_t)0xD7D946D7,
+ (q31_t)0x798A23B1, (q31_t)0xD65C3B7B, (q31_t)0x7909A92C,
+ (q31_t)0xD4E0CB14, (q31_t)0x78848413, (q31_t)0xD3670445,
+ (q31_t)0x77FAB988, (q31_t)0xD1EEF59E, (q31_t)0x776C4EDB,
+ (q31_t)0xD078AD9D, (q31_t)0x76D94988, (q31_t)0xCF043AB2,
+ (q31_t)0x7641AF3C, (q31_t)0xCD91AB38, (q31_t)0x75A585CF,
+ (q31_t)0xCC210D78, (q31_t)0x7504D345, (q31_t)0xCAB26FA9,
+ (q31_t)0x745F9DD1, (q31_t)0xC945DFEC, (q31_t)0x73B5EBD0,
+ (q31_t)0xC7DB6C50, (q31_t)0x7307C3D0, (q31_t)0xC67322CD,
+ (q31_t)0x72552C84, (q31_t)0xC50D1148, (q31_t)0x719E2CD2,
+ (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xC247CD5A,
+ (q31_t)0x70231099, (q31_t)0xC0E8B648, (q31_t)0x6F5F02B1,
+ (q31_t)0xBF8C0DE2, (q31_t)0x6E96A99C, (q31_t)0xBE31E19B,
+ (q31_t)0x6DCA0D14, (q31_t)0xBCDA3ECA, (q31_t)0x6CF934FB,
+ (q31_t)0xBB8532AF, (q31_t)0x6C242960, (q31_t)0xBA32CA70,
+ (q31_t)0x6B4AF278, (q31_t)0xB8E31319, (q31_t)0x6A6D98A4,
+ (q31_t)0xB796199B, (q31_t)0x698C246C, (q31_t)0xB64BEACC,
+ (q31_t)0x68A69E81, (q31_t)0xB5049368, (q31_t)0x67BD0FBC,
+ (q31_t)0xB3C0200C, (q31_t)0x66CF811F, (q31_t)0xB27E9D3B,
+ (q31_t)0x65DDFBD3, (q31_t)0xB140175B, (q31_t)0x64E88926,
+ (q31_t)0xB0049AB2, (q31_t)0x63EF328F, (q31_t)0xAECC336B,
+ (q31_t)0x62F201AC, (q31_t)0xAD96ED91, (q31_t)0x61F1003E,
+ (q31_t)0xAC64D510, (q31_t)0x60EC3830, (q31_t)0xAB35F5B5,
+ (q31_t)0x5FE3B38D, (q31_t)0xAA0A5B2D, (q31_t)0x5ED77C89,
+ (q31_t)0xA8E21106, (q31_t)0x5DC79D7C, (q31_t)0xA7BD22AB,
+ (q31_t)0x5CB420DF, (q31_t)0xA69B9B68, (q31_t)0x5B9D1153,
+ (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0xA462EEAC,
+ (q31_t)0x59646497, (q31_t)0xA34BDF20, (q31_t)0x5842DD54,
+ (q31_t)0xA2386283, (q31_t)0x571DEEF9, (q31_t)0xA1288376,
+ (q31_t)0x55F5A4D2, (q31_t)0xA01C4C72, (q31_t)0x54CA0A4A,
+ (q31_t)0x9F13C7D0, (q31_t)0x539B2AEF, (q31_t)0x9E0EFFC1,
+ (q31_t)0x5269126E, (q31_t)0x9D0DFE53, (q31_t)0x5133CC94,
+ (q31_t)0x9C10CD70, (q31_t)0x4FFB654D, (q31_t)0x9B1776D9,
+ (q31_t)0x4EBFE8A4, (q31_t)0x9A22042C, (q31_t)0x4D8162C4,
+ (q31_t)0x99307EE0, (q31_t)0x4C3FDFF3, (q31_t)0x9842F043,
+ (q31_t)0x4AFB6C97, (q31_t)0x9759617E, (q31_t)0x49B41533,
+ (q31_t)0x9673DB94, (q31_t)0x4869E664, (q31_t)0x9592675B,
+ (q31_t)0x471CECE6, (q31_t)0x94B50D87, (q31_t)0x45CD358F,
+ (q31_t)0x93DBD69F, (q31_t)0x447ACD50, (q31_t)0x9306CB04,
+ (q31_t)0x4325C135, (q31_t)0x9235F2EB, (q31_t)0x41CE1E64,
+ (q31_t)0x91695663, (q31_t)0x4073F21D, (q31_t)0x90A0FD4E,
+ (q31_t)0x3F1749B7, (q31_t)0x8FDCEF66, (q31_t)0x3DB832A5,
+ (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x8E61D32D,
+ (q31_t)0x3AF2EEB7, (q31_t)0x8DAAD37B, (q31_t)0x398CDD32,
+ (q31_t)0x8CF83C30, (q31_t)0x382493B0, (q31_t)0x8C4A142F,
+ (q31_t)0x36BA2013, (q31_t)0x8BA0622F, (q31_t)0x354D9056,
+ (q31_t)0x8AFB2CBA, (q31_t)0x33DEF287, (q31_t)0x8A5A7A30,
+ (q31_t)0x326E54C7, (q31_t)0x89BE50C3, (q31_t)0x30FBC54D,
+ (q31_t)0x8926B677, (q31_t)0x2F875262, (q31_t)0x8893B124,
+ (q31_t)0x2E110A62, (q31_t)0x88054677, (q31_t)0x2C98FBBA,
+ (q31_t)0x877B7BEC, (q31_t)0x2B1F34EB, (q31_t)0x86F656D3,
+ (q31_t)0x29A3C484, (q31_t)0x8675DC4E, (q31_t)0x2826B928,
+ (q31_t)0x85FA1152, (q31_t)0x26A82185, (q31_t)0x8582FAA4,
+ (q31_t)0x25280C5D, (q31_t)0x85109CDC, (q31_t)0x23A6887E,
+ (q31_t)0x84A2FC62, (q31_t)0x2223A4C5, (q31_t)0x843A1D70,
+ (q31_t)0x209F701C, (q31_t)0x83D60411, (q31_t)0x1F19F97B,
+ (q31_t)0x8376B422, (q31_t)0x1D934FE5, (q31_t)0x831C314E,
+ (q31_t)0x1C0B826A, (q31_t)0x82C67F13, (q31_t)0x1A82A025,
+ (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x82299971,
+ (q31_t)0x176DD9DE, (q31_t)0x81E26C16, (q31_t)0x15E21444,
+ (q31_t)0x81A01B6C, (q31_t)0x145576B1, (q31_t)0x8162AA03,
+ (q31_t)0x12C8106E, (q31_t)0x812A1A39, (q31_t)0x1139F0CE,
+ (q31_t)0x80F66E3C, (q31_t)0x0FAB272B, (q31_t)0x80C7A80A,
+ (q31_t)0x0E1BC2E3, (q31_t)0x809DC970, (q31_t)0x0C8BD35E,
+ (q31_t)0x8078D40D, (q31_t)0x0AFB6805, (q31_t)0x8058C94C,
+ (q31_t)0x096A9049, (q31_t)0x803DAA69, (q31_t)0x07D95B9E,
+ (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x80163440,
+ (q31_t)0x04B6195D, (q31_t)0x8009DE7D, (q31_t)0x03242ABF,
+ (q31_t)0x800277A5, (q31_t)0x01921D1F, (q31_t)0x80000000,
+ (q31_t)0x00000000, (q31_t)0x800277A5, (q31_t)0xFE6DE2E0,
+ (q31_t)0x8009DE7D, (q31_t)0xFCDBD541, (q31_t)0x80163440,
+ (q31_t)0xFB49E6A2, (q31_t)0x80277872, (q31_t)0xF9B82683,
+ (q31_t)0x803DAA69, (q31_t)0xF826A461, (q31_t)0x8058C94C,
+ (q31_t)0xF6956FB6, (q31_t)0x8078D40D, (q31_t)0xF50497FA,
+ (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x80C7A80A,
+ (q31_t)0xF1E43D1C, (q31_t)0x80F66E3C, (q31_t)0xF054D8D4,
+ (q31_t)0x812A1A39, (q31_t)0xEEC60F31, (q31_t)0x8162AA03,
+ (q31_t)0xED37EF91, (q31_t)0x81A01B6C, (q31_t)0xEBAA894E,
+ (q31_t)0x81E26C16, (q31_t)0xEA1DEBBB, (q31_t)0x82299971,
+ (q31_t)0xE8922621, (q31_t)0x8275A0C0, (q31_t)0xE70747C3,
+ (q31_t)0x82C67F13, (q31_t)0xE57D5FDA, (q31_t)0x831C314E,
+ (q31_t)0xE3F47D95, (q31_t)0x8376B422, (q31_t)0xE26CB01A,
+ (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x843A1D70,
+ (q31_t)0xDF608FE3, (q31_t)0x84A2FC62, (q31_t)0xDDDC5B3A,
+ (q31_t)0x85109CDC, (q31_t)0xDC597781, (q31_t)0x8582FAA4,
+ (q31_t)0xDAD7F3A2, (q31_t)0x85FA1152, (q31_t)0xD957DE7A,
+ (q31_t)0x8675DC4E, (q31_t)0xD7D946D7, (q31_t)0x86F656D3,
+ (q31_t)0xD65C3B7B, (q31_t)0x877B7BEC, (q31_t)0xD4E0CB14,
+ (q31_t)0x88054677, (q31_t)0xD3670445, (q31_t)0x8893B124,
+ (q31_t)0xD1EEF59E, (q31_t)0x8926B677, (q31_t)0xD078AD9D,
+ (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8A5A7A30,
+ (q31_t)0xCD91AB38, (q31_t)0x8AFB2CBA, (q31_t)0xCC210D78,
+ (q31_t)0x8BA0622F, (q31_t)0xCAB26FA9, (q31_t)0x8C4A142F,
+ (q31_t)0xC945DFEC, (q31_t)0x8CF83C30, (q31_t)0xC7DB6C50,
+ (q31_t)0x8DAAD37B, (q31_t)0xC67322CD, (q31_t)0x8E61D32D,
+ (q31_t)0xC50D1148, (q31_t)0x8F1D343A, (q31_t)0xC3A9458F,
+ (q31_t)0x8FDCEF66, (q31_t)0xC247CD5A, (q31_t)0x90A0FD4E,
+ (q31_t)0xC0E8B648, (q31_t)0x91695663, (q31_t)0xBF8C0DE2,
+ (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x9306CB04,
+ (q31_t)0xBCDA3ECA, (q31_t)0x93DBD69F, (q31_t)0xBB8532AF,
+ (q31_t)0x94B50D87, (q31_t)0xBA32CA70, (q31_t)0x9592675B,
+ (q31_t)0xB8E31319, (q31_t)0x9673DB94, (q31_t)0xB796199B,
+ (q31_t)0x9759617E, (q31_t)0xB64BEACC, (q31_t)0x9842F043,
+ (q31_t)0xB5049368, (q31_t)0x99307EE0, (q31_t)0xB3C0200C,
+ (q31_t)0x9A22042C, (q31_t)0xB27E9D3B, (q31_t)0x9B1776D9,
+ (q31_t)0xB140175B, (q31_t)0x9C10CD70, (q31_t)0xB0049AB2,
+ (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0x9E0EFFC1,
+ (q31_t)0xAD96ED91, (q31_t)0x9F13C7D0, (q31_t)0xAC64D510,
+ (q31_t)0xA01C4C72, (q31_t)0xAB35F5B5, (q31_t)0xA1288376,
+ (q31_t)0xAA0A5B2D, (q31_t)0xA2386283, (q31_t)0xA8E21106,
+ (q31_t)0xA34BDF20, (q31_t)0xA7BD22AB, (q31_t)0xA462EEAC,
+ (q31_t)0xA69B9B68, (q31_t)0xA57D8666, (q31_t)0xA57D8666,
+ (q31_t)0xA69B9B68, (q31_t)0xA462EEAC, (q31_t)0xA7BD22AB,
+ (q31_t)0xA34BDF20, (q31_t)0xA8E21106, (q31_t)0xA2386283,
+ (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAB35F5B5,
+ (q31_t)0xA01C4C72, (q31_t)0xAC64D510, (q31_t)0x9F13C7D0,
+ (q31_t)0xAD96ED91, (q31_t)0x9E0EFFC1, (q31_t)0xAECC336B,
+ (q31_t)0x9D0DFE53, (q31_t)0xB0049AB2, (q31_t)0x9C10CD70,
+ (q31_t)0xB140175B, (q31_t)0x9B1776D9, (q31_t)0xB27E9D3B,
+ (q31_t)0x9A22042C, (q31_t)0xB3C0200C, (q31_t)0x99307EE0,
+ (q31_t)0xB5049368, (q31_t)0x9842F043, (q31_t)0xB64BEACC,
+ (q31_t)0x9759617E, (q31_t)0xB796199B, (q31_t)0x9673DB94,
+ (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xBA32CA70,
+ (q31_t)0x94B50D87, (q31_t)0xBB8532AF, (q31_t)0x93DBD69F,
+ (q31_t)0xBCDA3ECA, (q31_t)0x9306CB04, (q31_t)0xBE31E19B,
+ (q31_t)0x9235F2EB, (q31_t)0xBF8C0DE2, (q31_t)0x91695663,
+ (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC247CD5A,
+ (q31_t)0x8FDCEF66, (q31_t)0xC3A9458F, (q31_t)0x8F1D343A,
+ (q31_t)0xC50D1148, (q31_t)0x8E61D32D, (q31_t)0xC67322CD,
+ (q31_t)0x8DAAD37B, (q31_t)0xC7DB6C50, (q31_t)0x8CF83C30,
+ (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xCAB26FA9,
+ (q31_t)0x8BA0622F, (q31_t)0xCC210D78, (q31_t)0x8AFB2CBA,
+ (q31_t)0xCD91AB38, (q31_t)0x8A5A7A30, (q31_t)0xCF043AB2,
+ (q31_t)0x89BE50C3, (q31_t)0xD078AD9D, (q31_t)0x8926B677,
+ (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD3670445,
+ (q31_t)0x88054677, (q31_t)0xD4E0CB14, (q31_t)0x877B7BEC,
+ (q31_t)0xD65C3B7B, (q31_t)0x86F656D3, (q31_t)0xD7D946D7,
+ (q31_t)0x8675DC4E, (q31_t)0xD957DE7A, (q31_t)0x85FA1152,
+ (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDC597781,
+ (q31_t)0x85109CDC, (q31_t)0xDDDC5B3A, (q31_t)0x84A2FC62,
+ (q31_t)0xDF608FE3, (q31_t)0x843A1D70, (q31_t)0xE0E60684,
+ (q31_t)0x83D60411, (q31_t)0xE26CB01A, (q31_t)0x8376B422,
+ (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE57D5FDA,
+ (q31_t)0x82C67F13, (q31_t)0xE70747C3, (q31_t)0x8275A0C0,
+ (q31_t)0xE8922621, (q31_t)0x82299971, (q31_t)0xEA1DEBBB,
+ (q31_t)0x81E26C16, (q31_t)0xEBAA894E, (q31_t)0x81A01B6C,
+ (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xEEC60F31,
+ (q31_t)0x812A1A39, (q31_t)0xF054D8D4, (q31_t)0x80F66E3C,
+ (q31_t)0xF1E43D1C, (q31_t)0x80C7A80A, (q31_t)0xF3742CA1,
+ (q31_t)0x809DC970, (q31_t)0xF50497FA, (q31_t)0x8078D40D,
+ (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF826A461,
+ (q31_t)0x803DAA69, (q31_t)0xF9B82683, (q31_t)0x80277872,
+ (q31_t)0xFB49E6A2, (q31_t)0x80163440, (q31_t)0xFCDBD541,
+ (q31_t)0x8009DE7D, (q31_t)0xFE6DE2E0, (q31_t)0x800277A5
+};
+
+/**
+* \par
+* Example code for Q31 Twiddle factors Generation::
+* \par
+* <pre>for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 1024 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to Q31(Fixed point 1.31):
+* round(twiddleCoefQ31(i) * pow(2, 31))
+*
+*/
+const q31_t twiddleCoef_1024_q31[1536] = {
+ (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FFF6216,
+ (q31_t)0x00C90F88, (q31_t)0x7FFD885A, (q31_t)0x01921D1F,
+ (q31_t)0x7FFA72D1, (q31_t)0x025B26D7, (q31_t)0x7FF62182,
+ (q31_t)0x03242ABF, (q31_t)0x7FF09477, (q31_t)0x03ED26E6,
+ (q31_t)0x7FE9CBC0, (q31_t)0x04B6195D, (q31_t)0x7FE1C76B,
+ (q31_t)0x057F0034, (q31_t)0x7FD8878D, (q31_t)0x0647D97C,
+ (q31_t)0x7FCE0C3E, (q31_t)0x0710A344, (q31_t)0x7FC25596,
+ (q31_t)0x07D95B9E, (q31_t)0x7FB563B2, (q31_t)0x08A2009A,
+ (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7F97CEBC,
+ (q31_t)0x0A3308BC, (q31_t)0x7F872BF3, (q31_t)0x0AFB6805,
+ (q31_t)0x7F754E7F, (q31_t)0x0BC3AC35, (q31_t)0x7F62368F,
+ (q31_t)0x0C8BD35E, (q31_t)0x7F4DE450, (q31_t)0x0D53DB92,
+ (q31_t)0x7F3857F5, (q31_t)0x0E1BC2E3, (q31_t)0x7F2191B4,
+ (q31_t)0x0EE38765, (q31_t)0x7F0991C3, (q31_t)0x0FAB272B,
+ (q31_t)0x7EF0585F, (q31_t)0x1072A047, (q31_t)0x7ED5E5C6,
+ (q31_t)0x1139F0CE, (q31_t)0x7EBA3A39, (q31_t)0x120116D4,
+ (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E7F3956,
+ (q31_t)0x138EDBB0, (q31_t)0x7E5FE493, (q31_t)0x145576B1,
+ (q31_t)0x7E3F57FE, (q31_t)0x151BDF85, (q31_t)0x7E1D93E9,
+ (q31_t)0x15E21444, (q31_t)0x7DFA98A7, (q31_t)0x16A81305,
+ (q31_t)0x7DD6668E, (q31_t)0x176DD9DE, (q31_t)0x7DB0FDF7,
+ (q31_t)0x183366E8, (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C,
+ (q31_t)0x7D628AC5, (q31_t)0x19BDCBF2, (q31_t)0x7D3980EC,
+ (q31_t)0x1A82A025, (q31_t)0x7D0F4218, (q31_t)0x1B4732EF,
+ (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7CB72724,
+ (q31_t)0x1CCF8CB3, (q31_t)0x7C894BDD, (q31_t)0x1D934FE5,
+ (q31_t)0x7C5A3D4F, (q31_t)0x1E56CA1E, (q31_t)0x7C29FBEE,
+ (q31_t)0x1F19F97B, (q31_t)0x7BF88830, (q31_t)0x1FDCDC1A,
+ (q31_t)0x7BC5E28F, (q31_t)0x209F701C, (q31_t)0x7B920B89,
+ (q31_t)0x2161B39F, (q31_t)0x7B5D039D, (q31_t)0x2223A4C5,
+ (q31_t)0x7B26CB4F, (q31_t)0x22E541AE, (q31_t)0x7AEF6323,
+ (q31_t)0x23A6887E, (q31_t)0x7AB6CBA3, (q31_t)0x24677757,
+ (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7A4210D8,
+ (q31_t)0x25E845B5, (q31_t)0x7A05EEAD, (q31_t)0x26A82185,
+ (q31_t)0x79C89F6D, (q31_t)0x27679DF4, (q31_t)0x798A23B1,
+ (q31_t)0x2826B928, (q31_t)0x794A7C11, (q31_t)0x28E5714A,
+ (q31_t)0x7909A92C, (q31_t)0x29A3C484, (q31_t)0x78C7ABA1,
+ (q31_t)0x2A61B101, (q31_t)0x78848413, (q31_t)0x2B1F34EB,
+ (q31_t)0x78403328, (q31_t)0x2BDC4E6F, (q31_t)0x77FAB988,
+ (q31_t)0x2C98FBBA, (q31_t)0x77B417DF, (q31_t)0x2D553AFB,
+ (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x77235F2D,
+ (q31_t)0x2ECC681E, (q31_t)0x76D94988, (q31_t)0x2F875262,
+ (q31_t)0x768E0EA5, (q31_t)0x3041C760, (q31_t)0x7641AF3C,
+ (q31_t)0x30FBC54D, (q31_t)0x75F42C0A, (q31_t)0x31B54A5D,
+ (q31_t)0x75A585CF, (q31_t)0x326E54C7, (q31_t)0x7555BD4B,
+ (q31_t)0x3326E2C2, (q31_t)0x7504D345, (q31_t)0x33DEF287,
+ (q31_t)0x74B2C883, (q31_t)0x3496824F, (q31_t)0x745F9DD1,
+ (q31_t)0x354D9056, (q31_t)0x740B53FA, (q31_t)0x36041AD9,
+ (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x735F6626,
+ (q31_t)0x376F9E46, (q31_t)0x7307C3D0, (q31_t)0x382493B0,
+ (q31_t)0x72AF05A6, (q31_t)0x38D8FE93, (q31_t)0x72552C84,
+ (q31_t)0x398CDD32, (q31_t)0x71FA3948, (q31_t)0x3A402DD1,
+ (q31_t)0x719E2CD2, (q31_t)0x3AF2EEB7, (q31_t)0x71410804,
+ (q31_t)0x3BA51E29, (q31_t)0x70E2CBC6, (q31_t)0x3C56BA70,
+ (q31_t)0x708378FE, (q31_t)0x3D07C1D5, (q31_t)0x70231099,
+ (q31_t)0x3DB832A5, (q31_t)0x6FC19385, (q31_t)0x3E680B2C,
+ (q31_t)0x6F5F02B1, (q31_t)0x3F1749B7, (q31_t)0x6EFB5F12,
+ (q31_t)0x3FC5EC97, (q31_t)0x6E96A99C, (q31_t)0x4073F21D,
+ (q31_t)0x6E30E349, (q31_t)0x4121589A, (q31_t)0x6DCA0D14,
+ (q31_t)0x41CE1E64, (q31_t)0x6D6227FA, (q31_t)0x427A41D0,
+ (q31_t)0x6CF934FB, (q31_t)0x4325C135, (q31_t)0x6C8F351C,
+ (q31_t)0x43D09AEC, (q31_t)0x6C242960, (q31_t)0x447ACD50,
+ (q31_t)0x6BB812D0, (q31_t)0x452456BC, (q31_t)0x6B4AF278,
+ (q31_t)0x45CD358F, (q31_t)0x6ADCC964, (q31_t)0x46756827,
+ (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x69FD614A,
+ (q31_t)0x47C3C22E, (q31_t)0x698C246C, (q31_t)0x4869E664,
+ (q31_t)0x6919E320, (q31_t)0x490F57EE, (q31_t)0x68A69E81,
+ (q31_t)0x49B41533, (q31_t)0x683257AA, (q31_t)0x4A581C9D,
+ (q31_t)0x67BD0FBC, (q31_t)0x4AFB6C97, (q31_t)0x6746C7D7,
+ (q31_t)0x4B9E038F, (q31_t)0x66CF811F, (q31_t)0x4C3FDFF3,
+ (q31_t)0x66573CBB, (q31_t)0x4CE10034, (q31_t)0x65DDFBD3,
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+ (q31_t)0x8A0BD3F5, (q31_t)0x31B54A5D, (q31_t)0x89BE50C3,
+ (q31_t)0x30FBC54D, (q31_t)0x8971F15A, (q31_t)0x3041C760,
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+ (q31_t)0x2826B928, (q31_t)0x86376092, (q31_t)0x27679DF4,
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+ (q31_t)0x8549345C, (q31_t)0x24677757, (q31_t)0x85109CDC,
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+ (q31_t)0x840777CF, (q31_t)0x1FDCDC1A, (q31_t)0x83D60411,
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+ (q31_t)0x1CCF8CB3, (q31_t)0x831C314E, (q31_t)0x1C0B826A,
+ (q31_t)0x82F0BDE8, (q31_t)0x1B4732EF, (q31_t)0x82C67F13,
+ (q31_t)0x1A82A025, (q31_t)0x829D753A, (q31_t)0x19BDCBF2,
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+ (q31_t)0x80009DE9, (q31_t)0xFF36F078, (q31_t)0x800277A5,
+ (q31_t)0xFE6DE2E0, (q31_t)0x80058D2E, (q31_t)0xFDA4D928,
+ (q31_t)0x8009DE7D, (q31_t)0xFCDBD541, (q31_t)0x800F6B88,
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+ (q31_t)0x803DAA69, (q31_t)0xF826A461, (q31_t)0x804A9C4D,
+ (q31_t)0xF75DFF65, (q31_t)0x8058C94C, (q31_t)0xF6956FB6,
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+ (q31_t)0xD71A8EB5, (q31_t)0x86F656D3, (q31_t)0xD65C3B7B,
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+ (q31_t)0x8AAA42B4, (q31_t)0xCCD91D3D, (q31_t)0x8AFB2CBA,
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+ (q31_t)0xC9FBE527, (q31_t)0x8C4A142F, (q31_t)0xC945DFEC,
+ (q31_t)0x8CA099D9, (q31_t)0xC89061BA, (q31_t)0x8CF83C30,
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+ (q31_t)0xC5BFD22E, (q31_t)0x8E61D32D, (q31_t)0xC50D1148,
+ (q31_t)0x8EBEF7FB, (q31_t)0xC45AE1D7, (q31_t)0x8F1D343A,
+ (q31_t)0xC3A9458F, (q31_t)0x8F7C8701, (q31_t)0xC2F83E2A,
+ (q31_t)0x8FDCEF66, (q31_t)0xC247CD5A, (q31_t)0x903E6C7A,
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+ (q31_t)0x9104A0ED, (q31_t)0xC03A1368, (q31_t)0x91695663,
+ (q31_t)0xBF8C0DE2, (q31_t)0x91CF1CB6, (q31_t)0xBEDEA765,
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+ (q31_t)0xBD85BE2F, (q31_t)0x9306CB04, (q31_t)0xBCDA3ECA,
+ (q31_t)0x9370CAE4, (q31_t)0xBC2F6513, (q31_t)0x93DBD69F,
+ (q31_t)0xBB8532AF, (q31_t)0x9447ED2F, (q31_t)0xBADBA943,
+ (q31_t)0x94B50D87, (q31_t)0xBA32CA70, (q31_t)0x9523369B,
+ (q31_t)0xB98A97D8, (q31_t)0x9592675B, (q31_t)0xB8E31319,
+ (q31_t)0x96029EB5, (q31_t)0xB83C3DD1, (q31_t)0x9673DB94,
+ (q31_t)0xB796199B, (q31_t)0x96E61CDF, (q31_t)0xB6F0A811,
+ (q31_t)0x9759617E, (q31_t)0xB64BEACC, (q31_t)0x97CDA855,
+ (q31_t)0xB5A7E362, (q31_t)0x9842F043, (q31_t)0xB5049368,
+ (q31_t)0x98B93828, (q31_t)0xB461FC70, (q31_t)0x99307EE0,
+ (q31_t)0xB3C0200C, (q31_t)0x99A8C344, (q31_t)0xB31EFFCB,
+ (q31_t)0x9A22042C, (q31_t)0xB27E9D3B, (q31_t)0x9A9C406D,
+ (q31_t)0xB1DEF9E8, (q31_t)0x9B1776D9, (q31_t)0xB140175B,
+ (q31_t)0x9B93A640, (q31_t)0xB0A1F71C, (q31_t)0x9C10CD70,
+ (q31_t)0xB0049AB2, (q31_t)0x9C8EEB33, (q31_t)0xAF6803A1,
+ (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0x9D8E0596,
+ (q31_t)0xAE312B91, (q31_t)0x9E0EFFC1, (q31_t)0xAD96ED91,
+ (q31_t)0x9E90EB94, (q31_t)0xACFD7AE8, (q31_t)0x9F13C7D0,
+ (q31_t)0xAC64D510, (q31_t)0x9F979331, (q31_t)0xABCCFD82,
+ (q31_t)0xA01C4C72, (q31_t)0xAB35F5B5, (q31_t)0xA0A1F24C,
+ (q31_t)0xAA9FBF1D, (q31_t)0xA1288376, (q31_t)0xAA0A5B2D,
+ (q31_t)0xA1AFFEA2, (q31_t)0xA975CB56, (q31_t)0xA2386283,
+ (q31_t)0xA8E21106, (q31_t)0xA2C1ADC9, (q31_t)0xA84F2DA9,
+ (q31_t)0xA34BDF20, (q31_t)0xA7BD22AB, (q31_t)0xA3D6F533,
+ (q31_t)0xA72BF173, (q31_t)0xA462EEAC, (q31_t)0xA69B9B68,
+ (q31_t)0xA4EFCA31, (q31_t)0xA60C21ED, (q31_t)0xA57D8666,
+ (q31_t)0xA57D8666, (q31_t)0xA60C21ED, (q31_t)0xA4EFCA31,
+ (q31_t)0xA69B9B68, (q31_t)0xA462EEAC, (q31_t)0xA72BF173,
+ (q31_t)0xA3D6F533, (q31_t)0xA7BD22AB, (q31_t)0xA34BDF20,
+ (q31_t)0xA84F2DA9, (q31_t)0xA2C1ADC9, (q31_t)0xA8E21106,
+ (q31_t)0xA2386283, (q31_t)0xA975CB56, (q31_t)0xA1AFFEA2,
+ (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAA9FBF1D,
+ (q31_t)0xA0A1F24C, (q31_t)0xAB35F5B5, (q31_t)0xA01C4C72,
+ (q31_t)0xABCCFD82, (q31_t)0x9F979331, (q31_t)0xAC64D510,
+ (q31_t)0x9F13C7D0, (q31_t)0xACFD7AE8, (q31_t)0x9E90EB94,
+ (q31_t)0xAD96ED91, (q31_t)0x9E0EFFC1, (q31_t)0xAE312B91,
+ (q31_t)0x9D8E0596, (q31_t)0xAECC336B, (q31_t)0x9D0DFE53,
+ (q31_t)0xAF6803A1, (q31_t)0x9C8EEB33, (q31_t)0xB0049AB2,
+ (q31_t)0x9C10CD70, (q31_t)0xB0A1F71C, (q31_t)0x9B93A640,
+ (q31_t)0xB140175B, (q31_t)0x9B1776D9, (q31_t)0xB1DEF9E8,
+ (q31_t)0x9A9C406D, (q31_t)0xB27E9D3B, (q31_t)0x9A22042C,
+ (q31_t)0xB31EFFCB, (q31_t)0x99A8C344, (q31_t)0xB3C0200C,
+ (q31_t)0x99307EE0, (q31_t)0xB461FC70, (q31_t)0x98B93828,
+ (q31_t)0xB5049368, (q31_t)0x9842F043, (q31_t)0xB5A7E362,
+ (q31_t)0x97CDA855, (q31_t)0xB64BEACC, (q31_t)0x9759617E,
+ (q31_t)0xB6F0A811, (q31_t)0x96E61CDF, (q31_t)0xB796199B,
+ (q31_t)0x9673DB94, (q31_t)0xB83C3DD1, (q31_t)0x96029EB5,
+ (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xB98A97D8,
+ (q31_t)0x9523369B, (q31_t)0xBA32CA70, (q31_t)0x94B50D87,
+ (q31_t)0xBADBA943, (q31_t)0x9447ED2F, (q31_t)0xBB8532AF,
+ (q31_t)0x93DBD69F, (q31_t)0xBC2F6513, (q31_t)0x9370CAE4,
+ (q31_t)0xBCDA3ECA, (q31_t)0x9306CB04, (q31_t)0xBD85BE2F,
+ (q31_t)0x929DD805, (q31_t)0xBE31E19B, (q31_t)0x9235F2EB,
+ (q31_t)0xBEDEA765, (q31_t)0x91CF1CB6, (q31_t)0xBF8C0DE2,
+ (q31_t)0x91695663, (q31_t)0xC03A1368, (q31_t)0x9104A0ED,
+ (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC197F4D3,
+ (q31_t)0x903E6C7A, (q31_t)0xC247CD5A, (q31_t)0x8FDCEF66,
+ (q31_t)0xC2F83E2A, (q31_t)0x8F7C8701, (q31_t)0xC3A9458F,
+ (q31_t)0x8F1D343A, (q31_t)0xC45AE1D7, (q31_t)0x8EBEF7FB,
+ (q31_t)0xC50D1148, (q31_t)0x8E61D32D, (q31_t)0xC5BFD22E,
+ (q31_t)0x8E05C6B7, (q31_t)0xC67322CD, (q31_t)0x8DAAD37B,
+ (q31_t)0xC727016C, (q31_t)0x8D50FA59, (q31_t)0xC7DB6C50,
+ (q31_t)0x8CF83C30, (q31_t)0xC89061BA, (q31_t)0x8CA099D9,
+ (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xC9FBE527,
+ (q31_t)0x8BF4AC05, (q31_t)0xCAB26FA9, (q31_t)0x8BA0622F,
+ (q31_t)0xCB697DB0, (q31_t)0x8B4D377C, (q31_t)0xCC210D78,
+ (q31_t)0x8AFB2CBA, (q31_t)0xCCD91D3D, (q31_t)0x8AAA42B4,
+ (q31_t)0xCD91AB38, (q31_t)0x8A5A7A30, (q31_t)0xCE4AB5A2,
+ (q31_t)0x8A0BD3F5, (q31_t)0xCF043AB2, (q31_t)0x89BE50C3,
+ (q31_t)0xCFBE389F, (q31_t)0x8971F15A, (q31_t)0xD078AD9D,
+ (q31_t)0x8926B677, (q31_t)0xD13397E1, (q31_t)0x88DCA0D3,
+ (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD2AAC504,
+ (q31_t)0x884BE820, (q31_t)0xD3670445, (q31_t)0x88054677,
+ (q31_t)0xD423B190, (q31_t)0x87BFCCD7, (q31_t)0xD4E0CB14,
+ (q31_t)0x877B7BEC, (q31_t)0xD59E4EFE, (q31_t)0x8738545E,
+ (q31_t)0xD65C3B7B, (q31_t)0x86F656D3, (q31_t)0xD71A8EB5,
+ (q31_t)0x86B583EE, (q31_t)0xD7D946D7, (q31_t)0x8675DC4E,
+ (q31_t)0xD898620C, (q31_t)0x86376092, (q31_t)0xD957DE7A,
+ (q31_t)0x85FA1152, (q31_t)0xDA17BA4A, (q31_t)0x85BDEF27,
+ (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDB9888A8,
+ (q31_t)0x8549345C, (q31_t)0xDC597781, (q31_t)0x85109CDC,
+ (q31_t)0xDD1ABE51, (q31_t)0x84D934B0, (q31_t)0xDDDC5B3A,
+ (q31_t)0x84A2FC62, (q31_t)0xDE9E4C60, (q31_t)0x846DF476,
+ (q31_t)0xDF608FE3, (q31_t)0x843A1D70, (q31_t)0xE02323E5,
+ (q31_t)0x840777CF, (q31_t)0xE0E60684, (q31_t)0x83D60411,
+ (q31_t)0xE1A935E1, (q31_t)0x83A5C2B0, (q31_t)0xE26CB01A,
+ (q31_t)0x8376B422, (q31_t)0xE330734C, (q31_t)0x8348D8DB,
+ (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE4B8CD10,
+ (q31_t)0x82F0BDE8, (q31_t)0xE57D5FDA, (q31_t)0x82C67F13,
+ (q31_t)0xE642340D, (q31_t)0x829D753A, (q31_t)0xE70747C3,
+ (q31_t)0x8275A0C0, (q31_t)0xE7CC9917, (q31_t)0x824F0208,
+ (q31_t)0xE8922621, (q31_t)0x82299971, (q31_t)0xE957ECFB,
+ (q31_t)0x82056758, (q31_t)0xEA1DEBBB, (q31_t)0x81E26C16,
+ (q31_t)0xEAE4207A, (q31_t)0x81C0A801, (q31_t)0xEBAA894E,
+ (q31_t)0x81A01B6C, (q31_t)0xEC71244F, (q31_t)0x8180C6A9,
+ (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xEDFEE92B,
+ (q31_t)0x8145C5C6, (q31_t)0xEEC60F31, (q31_t)0x812A1A39,
+ (q31_t)0xEF8D5FB8, (q31_t)0x810FA7A0, (q31_t)0xF054D8D4,
+ (q31_t)0x80F66E3C, (q31_t)0xF11C789A, (q31_t)0x80DE6E4C,
+ (q31_t)0xF1E43D1C, (q31_t)0x80C7A80A, (q31_t)0xF2AC246D,
+ (q31_t)0x80B21BAF, (q31_t)0xF3742CA1, (q31_t)0x809DC970,
+ (q31_t)0xF43C53CA, (q31_t)0x808AB180, (q31_t)0xF50497FA,
+ (q31_t)0x8078D40D, (q31_t)0xF5CCF743, (q31_t)0x80683143,
+ (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF75DFF65,
+ (q31_t)0x804A9C4D, (q31_t)0xF826A461, (q31_t)0x803DAA69,
+ (q31_t)0xF8EF5CBB, (q31_t)0x8031F3C1, (q31_t)0xF9B82683,
+ (q31_t)0x80277872, (q31_t)0xFA80FFCB, (q31_t)0x801E3894,
+ (q31_t)0xFB49E6A2, (q31_t)0x80163440, (q31_t)0xFC12D919,
+ (q31_t)0x800F6B88, (q31_t)0xFCDBD541, (q31_t)0x8009DE7D,
+ (q31_t)0xFDA4D928, (q31_t)0x80058D2E, (q31_t)0xFE6DE2E0,
+ (q31_t)0x800277A5, (q31_t)0xFF36F078, (q31_t)0x80009DE9
+};
+
+/**
+* \par
+* Example code for Q31 Twiddle factors Generation::
+* \par
+* <pre>for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 2048 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to Q31(Fixed point 1.31):
+* round(twiddleCoefQ31(i) * pow(2, 31))
+*
+*/
+const q31_t twiddleCoef_2048_q31[3072] = {
+ (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FFFD885,
+ (q31_t)0x006487E3, (q31_t)0x7FFF6216, (q31_t)0x00C90F88,
+ (q31_t)0x7FFE9CB2, (q31_t)0x012D96B0, (q31_t)0x7FFD885A,
+ (q31_t)0x01921D1F, (q31_t)0x7FFC250F, (q31_t)0x01F6A296,
+ (q31_t)0x7FFA72D1, (q31_t)0x025B26D7, (q31_t)0x7FF871A1,
+ (q31_t)0x02BFA9A4, (q31_t)0x7FF62182, (q31_t)0x03242ABF,
+ (q31_t)0x7FF38273, (q31_t)0x0388A9E9, (q31_t)0x7FF09477,
+ (q31_t)0x03ED26E6, (q31_t)0x7FED5790, (q31_t)0x0451A176,
+ (q31_t)0x7FE9CBC0, (q31_t)0x04B6195D, (q31_t)0x7FE5F108,
+ (q31_t)0x051A8E5C, (q31_t)0x7FE1C76B, (q31_t)0x057F0034,
+ (q31_t)0x7FDD4EEC, (q31_t)0x05E36EA9, (q31_t)0x7FD8878D,
+ (q31_t)0x0647D97C, (q31_t)0x7FD37152, (q31_t)0x06AC406F,
+ (q31_t)0x7FCE0C3E, (q31_t)0x0710A344, (q31_t)0x7FC85853,
+ (q31_t)0x077501BE, (q31_t)0x7FC25596, (q31_t)0x07D95B9E,
+ (q31_t)0x7FBC040A, (q31_t)0x083DB0A7, (q31_t)0x7FB563B2,
+ (q31_t)0x08A2009A, (q31_t)0x7FAE7494, (q31_t)0x09064B3A,
+ (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7F9FAA15,
+ (q31_t)0x09CECF89, (q31_t)0x7F97CEBC, (q31_t)0x0A3308BC,
+ (q31_t)0x7F8FA4AF, (q31_t)0x0A973BA5, (q31_t)0x7F872BF3,
+ (q31_t)0x0AFB6805, (q31_t)0x7F7E648B, (q31_t)0x0B5F8D9F,
+ (q31_t)0x7F754E7F, (q31_t)0x0BC3AC35, (q31_t)0x7F6BE9D4,
+ (q31_t)0x0C27C389, (q31_t)0x7F62368F, (q31_t)0x0C8BD35E,
+ (q31_t)0x7F5834B6, (q31_t)0x0CEFDB75, (q31_t)0x7F4DE450,
+ (q31_t)0x0D53DB92, (q31_t)0x7F434563, (q31_t)0x0DB7D376,
+ (q31_t)0x7F3857F5, (q31_t)0x0E1BC2E3, (q31_t)0x7F2D1C0E,
+ (q31_t)0x0E7FA99D, (q31_t)0x7F2191B4, (q31_t)0x0EE38765,
+ (q31_t)0x7F15B8EE, (q31_t)0x0F475BFE, (q31_t)0x7F0991C3,
+ (q31_t)0x0FAB272B, (q31_t)0x7EFD1C3C, (q31_t)0x100EE8AD,
+ (q31_t)0x7EF0585F, (q31_t)0x1072A047, (q31_t)0x7EE34635,
+ (q31_t)0x10D64DBC, (q31_t)0x7ED5E5C6, (q31_t)0x1139F0CE,
+ (q31_t)0x7EC8371A, (q31_t)0x119D8940, (q31_t)0x7EBA3A39,
+ (q31_t)0x120116D4, (q31_t)0x7EABEF2C, (q31_t)0x1264994E,
+ (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E8E6EB1,
+ (q31_t)0x132B7BF9, (q31_t)0x7E7F3956, (q31_t)0x138EDBB0,
+ (q31_t)0x7E6FB5F3, (q31_t)0x13F22F57, (q31_t)0x7E5FE493,
+ (q31_t)0x145576B1, (q31_t)0x7E4FC53E, (q31_t)0x14B8B17F,
+ (q31_t)0x7E3F57FE, (q31_t)0x151BDF85, (q31_t)0x7E2E9CDF,
+ (q31_t)0x157F0086, (q31_t)0x7E1D93E9, (q31_t)0x15E21444,
+ (q31_t)0x7E0C3D29, (q31_t)0x16451A83, (q31_t)0x7DFA98A7,
+ (q31_t)0x16A81305, (q31_t)0x7DE8A670, (q31_t)0x170AFD8D,
+ (q31_t)0x7DD6668E, (q31_t)0x176DD9DE, (q31_t)0x7DC3D90D,
+ (q31_t)0x17D0A7BB, (q31_t)0x7DB0FDF7, (q31_t)0x183366E8,
+ (q31_t)0x7D9DD55A, (q31_t)0x18961727, (q31_t)0x7D8A5F3F,
+ (q31_t)0x18F8B83C, (q31_t)0x7D769BB5, (q31_t)0x195B49E9,
+ (q31_t)0x7D628AC5, (q31_t)0x19BDCBF2, (q31_t)0x7D4E2C7E,
+ (q31_t)0x1A203E1B, (q31_t)0x7D3980EC, (q31_t)0x1A82A025,
+ (q31_t)0x7D24881A, (q31_t)0x1AE4F1D6, (q31_t)0x7D0F4218,
+ (q31_t)0x1B4732EF, (q31_t)0x7CF9AEF0, (q31_t)0x1BA96334,
+ (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7CCDA168,
+ (q31_t)0x1C6D9053, (q31_t)0x7CB72724, (q31_t)0x1CCF8CB3,
+ (q31_t)0x7CA05FF1, (q31_t)0x1D31774D, (q31_t)0x7C894BDD,
+ (q31_t)0x1D934FE5, (q31_t)0x7C71EAF8, (q31_t)0x1DF5163F,
+ (q31_t)0x7C5A3D4F, (q31_t)0x1E56CA1E, (q31_t)0x7C4242F2,
+ (q31_t)0x1EB86B46, (q31_t)0x7C29FBEE, (q31_t)0x1F19F97B,
+ (q31_t)0x7C116853, (q31_t)0x1F7B7480, (q31_t)0x7BF88830,
+ (q31_t)0x1FDCDC1A, (q31_t)0x7BDF5B94, (q31_t)0x203E300D,
+ (q31_t)0x7BC5E28F, (q31_t)0x209F701C, (q31_t)0x7BAC1D31,
+ (q31_t)0x21009C0B, (q31_t)0x7B920B89, (q31_t)0x2161B39F,
+ (q31_t)0x7B77ADA8, (q31_t)0x21C2B69C, (q31_t)0x7B5D039D,
+ (q31_t)0x2223A4C5, (q31_t)0x7B420D7A, (q31_t)0x22847DDF,
+ (q31_t)0x7B26CB4F, (q31_t)0x22E541AE, (q31_t)0x7B0B3D2C,
+ (q31_t)0x2345EFF7, (q31_t)0x7AEF6323, (q31_t)0x23A6887E,
+ (q31_t)0x7AD33D45, (q31_t)0x24070B07, (q31_t)0x7AB6CBA3,
+ (q31_t)0x24677757, (q31_t)0x7A9A0E4F, (q31_t)0x24C7CD32,
+ (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7A5FB0D8,
+ (q31_t)0x2588349D, (q31_t)0x7A4210D8, (q31_t)0x25E845B5,
+ (q31_t)0x7A24256E, (q31_t)0x26483F6C, (q31_t)0x7A05EEAD,
+ (q31_t)0x26A82185, (q31_t)0x79E76CA6, (q31_t)0x2707EBC6,
+ (q31_t)0x79C89F6D, (q31_t)0x27679DF4, (q31_t)0x79A98715,
+ (q31_t)0x27C737D2, (q31_t)0x798A23B1, (q31_t)0x2826B928,
+ (q31_t)0x796A7554, (q31_t)0x288621B9, (q31_t)0x794A7C11,
+ (q31_t)0x28E5714A, (q31_t)0x792A37FE, (q31_t)0x2944A7A2,
+ (q31_t)0x7909A92C, (q31_t)0x29A3C484, (q31_t)0x78E8CFB1,
+ (q31_t)0x2A02C7B8, (q31_t)0x78C7ABA1, (q31_t)0x2A61B101,
+ (q31_t)0x78A63D10, (q31_t)0x2AC08025, (q31_t)0x78848413,
+ (q31_t)0x2B1F34EB, (q31_t)0x786280BF, (q31_t)0x2B7DCF17,
+ (q31_t)0x78403328, (q31_t)0x2BDC4E6F, (q31_t)0x781D9B64,
+ (q31_t)0x2C3AB2B9, (q31_t)0x77FAB988, (q31_t)0x2C98FBBA,
+ (q31_t)0x77D78DAA, (q31_t)0x2CF72939, (q31_t)0x77B417DF,
+ (q31_t)0x2D553AFB, (q31_t)0x7790583D, (q31_t)0x2DB330C7,
+ (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x7747FBCE,
+ (q31_t)0x2E6EC792, (q31_t)0x77235F2D, (q31_t)0x2ECC681E,
+ (q31_t)0x76FE790E, (q31_t)0x2F29EBCC, (q31_t)0x76D94988,
+ (q31_t)0x2F875262, (q31_t)0x76B3D0B3, (q31_t)0x2FE49BA6,
+ (q31_t)0x768E0EA5, (q31_t)0x3041C760, (q31_t)0x76680376,
+ (q31_t)0x309ED555, (q31_t)0x7641AF3C, (q31_t)0x30FBC54D,
+ (q31_t)0x761B1211, (q31_t)0x3158970D, (q31_t)0x75F42C0A,
+ (q31_t)0x31B54A5D, (q31_t)0x75CCFD42, (q31_t)0x3211DF03,
+ (q31_t)0x75A585CF, (q31_t)0x326E54C7, (q31_t)0x757DC5CA,
+ (q31_t)0x32CAAB6F, (q31_t)0x7555BD4B, (q31_t)0x3326E2C2,
+ (q31_t)0x752D6C6C, (q31_t)0x3382FA88, (q31_t)0x7504D345,
+ (q31_t)0x33DEF287, (q31_t)0x74DBF1EF, (q31_t)0x343ACA87,
+ (q31_t)0x74B2C883, (q31_t)0x3496824F, (q31_t)0x7489571B,
+ (q31_t)0x34F219A7, (q31_t)0x745F9DD1, (q31_t)0x354D9056,
+ (q31_t)0x74359CBD, (q31_t)0x35A8E624, (q31_t)0x740B53FA,
+ (q31_t)0x36041AD9, (q31_t)0x73E0C3A3, (q31_t)0x365F2E3B,
+ (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x738ACC9E,
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+ (q31_t)0x24C7CD32, (q31_t)0x7A9A0E4F, (q31_t)0x24677757,
+ (q31_t)0x7AB6CBA3, (q31_t)0x24070B07, (q31_t)0x7AD33D45,
+ (q31_t)0x23A6887E, (q31_t)0x7AEF6323, (q31_t)0x2345EFF7,
+ (q31_t)0x7B0B3D2C, (q31_t)0x22E541AE, (q31_t)0x7B26CB4F,
+ (q31_t)0x22847DDF, (q31_t)0x7B420D7A, (q31_t)0x2223A4C5,
+ (q31_t)0x7B5D039D, (q31_t)0x21C2B69C, (q31_t)0x7B77ADA8,
+ (q31_t)0x2161B39F, (q31_t)0x7B920B89, (q31_t)0x21009C0B,
+ (q31_t)0x7BAC1D31, (q31_t)0x209F701C, (q31_t)0x7BC5E28F,
+ (q31_t)0x203E300D, (q31_t)0x7BDF5B94, (q31_t)0x1FDCDC1A,
+ (q31_t)0x7BF88830, (q31_t)0x1F7B7480, (q31_t)0x7C116853,
+ (q31_t)0x1F19F97B, (q31_t)0x7C29FBEE, (q31_t)0x1EB86B46,
+ (q31_t)0x7C4242F2, (q31_t)0x1E56CA1E, (q31_t)0x7C5A3D4F,
+ (q31_t)0x1DF5163F, (q31_t)0x7C71EAF8, (q31_t)0x1D934FE5,
+ (q31_t)0x7C894BDD, (q31_t)0x1D31774D, (q31_t)0x7CA05FF1,
+ (q31_t)0x1CCF8CB3, (q31_t)0x7CB72724, (q31_t)0x1C6D9053,
+ (q31_t)0x7CCDA168, (q31_t)0x1C0B826A, (q31_t)0x7CE3CEB1,
+ (q31_t)0x1BA96334, (q31_t)0x7CF9AEF0, (q31_t)0x1B4732EF,
+ (q31_t)0x7D0F4218, (q31_t)0x1AE4F1D6, (q31_t)0x7D24881A,
+ (q31_t)0x1A82A025, (q31_t)0x7D3980EC, (q31_t)0x1A203E1B,
+ (q31_t)0x7D4E2C7E, (q31_t)0x19BDCBF2, (q31_t)0x7D628AC5,
+ (q31_t)0x195B49E9, (q31_t)0x7D769BB5, (q31_t)0x18F8B83C,
+ (q31_t)0x7D8A5F3F, (q31_t)0x18961727, (q31_t)0x7D9DD55A,
+ (q31_t)0x183366E8, (q31_t)0x7DB0FDF7, (q31_t)0x17D0A7BB,
+ (q31_t)0x7DC3D90D, (q31_t)0x176DD9DE, (q31_t)0x7DD6668E,
+ (q31_t)0x170AFD8D, (q31_t)0x7DE8A670, (q31_t)0x16A81305,
+ (q31_t)0x7DFA98A7, (q31_t)0x16451A83, (q31_t)0x7E0C3D29,
+ (q31_t)0x15E21444, (q31_t)0x7E1D93E9, (q31_t)0x157F0086,
+ (q31_t)0x7E2E9CDF, (q31_t)0x151BDF85, (q31_t)0x7E3F57FE,
+ (q31_t)0x14B8B17F, (q31_t)0x7E4FC53E, (q31_t)0x145576B1,
+ (q31_t)0x7E5FE493, (q31_t)0x13F22F57, (q31_t)0x7E6FB5F3,
+ (q31_t)0x138EDBB0, (q31_t)0x7E7F3956, (q31_t)0x132B7BF9,
+ (q31_t)0x7E8E6EB1, (q31_t)0x12C8106E, (q31_t)0x7E9D55FC,
+ (q31_t)0x1264994E, (q31_t)0x7EABEF2C, (q31_t)0x120116D4,
+ (q31_t)0x7EBA3A39, (q31_t)0x119D8940, (q31_t)0x7EC8371A,
+ (q31_t)0x1139F0CE, (q31_t)0x7ED5E5C6, (q31_t)0x10D64DBC,
+ (q31_t)0x7EE34635, (q31_t)0x1072A047, (q31_t)0x7EF0585F,
+ (q31_t)0x100EE8AD, (q31_t)0x7EFD1C3C, (q31_t)0x0FAB272B,
+ (q31_t)0x7F0991C3, (q31_t)0x0F475BFE, (q31_t)0x7F15B8EE,
+ (q31_t)0x0EE38765, (q31_t)0x7F2191B4, (q31_t)0x0E7FA99D,
+ (q31_t)0x7F2D1C0E, (q31_t)0x0E1BC2E3, (q31_t)0x7F3857F5,
+ (q31_t)0x0DB7D376, (q31_t)0x7F434563, (q31_t)0x0D53DB92,
+ (q31_t)0x7F4DE450, (q31_t)0x0CEFDB75, (q31_t)0x7F5834B6,
+ (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x0C27C389,
+ (q31_t)0x7F6BE9D4, (q31_t)0x0BC3AC35, (q31_t)0x7F754E7F,
+ (q31_t)0x0B5F8D9F, (q31_t)0x7F7E648B, (q31_t)0x0AFB6805,
+ (q31_t)0x7F872BF3, (q31_t)0x0A973BA5, (q31_t)0x7F8FA4AF,
+ (q31_t)0x0A3308BC, (q31_t)0x7F97CEBC, (q31_t)0x09CECF89,
+ (q31_t)0x7F9FAA15, (q31_t)0x096A9049, (q31_t)0x7FA736B4,
+ (q31_t)0x09064B3A, (q31_t)0x7FAE7494, (q31_t)0x08A2009A,
+ (q31_t)0x7FB563B2, (q31_t)0x083DB0A7, (q31_t)0x7FBC040A,
+ (q31_t)0x07D95B9E, (q31_t)0x7FC25596, (q31_t)0x077501BE,
+ (q31_t)0x7FC85853, (q31_t)0x0710A344, (q31_t)0x7FCE0C3E,
+ (q31_t)0x06AC406F, (q31_t)0x7FD37152, (q31_t)0x0647D97C,
+ (q31_t)0x7FD8878D, (q31_t)0x05E36EA9, (q31_t)0x7FDD4EEC,
+ (q31_t)0x057F0034, (q31_t)0x7FE1C76B, (q31_t)0x051A8E5C,
+ (q31_t)0x7FE5F108, (q31_t)0x04B6195D, (q31_t)0x7FE9CBC0,
+ (q31_t)0x0451A176, (q31_t)0x7FED5790, (q31_t)0x03ED26E6,
+ (q31_t)0x7FF09477, (q31_t)0x0388A9E9, (q31_t)0x7FF38273,
+ (q31_t)0x03242ABF, (q31_t)0x7FF62182, (q31_t)0x02BFA9A4,
+ (q31_t)0x7FF871A1, (q31_t)0x025B26D7, (q31_t)0x7FFA72D1,
+ (q31_t)0x01F6A296, (q31_t)0x7FFC250F, (q31_t)0x01921D1F,
+ (q31_t)0x7FFD885A, (q31_t)0x012D96B0, (q31_t)0x7FFE9CB2,
+ (q31_t)0x00C90F88, (q31_t)0x7FFF6216, (q31_t)0x006487E3,
+ (q31_t)0x7FFFD885, (q31_t)0x00000000, (q31_t)0x7FFFFFFF,
+ (q31_t)0xFF9B781D, (q31_t)0x7FFFD885, (q31_t)0xFF36F078,
+ (q31_t)0x7FFF6216, (q31_t)0xFED2694F, (q31_t)0x7FFE9CB2,
+ (q31_t)0xFE6DE2E0, (q31_t)0x7FFD885A, (q31_t)0xFE095D69,
+ (q31_t)0x7FFC250F, (q31_t)0xFDA4D928, (q31_t)0x7FFA72D1,
+ (q31_t)0xFD40565B, (q31_t)0x7FF871A1, (q31_t)0xFCDBD541,
+ (q31_t)0x7FF62182, (q31_t)0xFC775616, (q31_t)0x7FF38273,
+ (q31_t)0xFC12D919, (q31_t)0x7FF09477, (q31_t)0xFBAE5E89,
+ (q31_t)0x7FED5790, (q31_t)0xFB49E6A2, (q31_t)0x7FE9CBC0,
+ (q31_t)0xFAE571A4, (q31_t)0x7FE5F108, (q31_t)0xFA80FFCB,
+ (q31_t)0x7FE1C76B, (q31_t)0xFA1C9156, (q31_t)0x7FDD4EEC,
+ (q31_t)0xF9B82683, (q31_t)0x7FD8878D, (q31_t)0xF953BF90,
+ (q31_t)0x7FD37152, (q31_t)0xF8EF5CBB, (q31_t)0x7FCE0C3E,
+ (q31_t)0xF88AFE41, (q31_t)0x7FC85853, (q31_t)0xF826A461,
+ (q31_t)0x7FC25596, (q31_t)0xF7C24F58, (q31_t)0x7FBC040A,
+ (q31_t)0xF75DFF65, (q31_t)0x7FB563B2, (q31_t)0xF6F9B4C5,
+ (q31_t)0x7FAE7494, (q31_t)0xF6956FB6, (q31_t)0x7FA736B4,
+ (q31_t)0xF6313076, (q31_t)0x7F9FAA15, (q31_t)0xF5CCF743,
+ (q31_t)0x7F97CEBC, (q31_t)0xF568C45A, (q31_t)0x7F8FA4AF,
+ (q31_t)0xF50497FA, (q31_t)0x7F872BF3, (q31_t)0xF4A07260,
+ (q31_t)0x7F7E648B, (q31_t)0xF43C53CA, (q31_t)0x7F754E7F,
+ (q31_t)0xF3D83C76, (q31_t)0x7F6BE9D4, (q31_t)0xF3742CA1,
+ (q31_t)0x7F62368F, (q31_t)0xF310248A, (q31_t)0x7F5834B6,
+ (q31_t)0xF2AC246D, (q31_t)0x7F4DE450, (q31_t)0xF2482C89,
+ (q31_t)0x7F434563, (q31_t)0xF1E43D1C, (q31_t)0x7F3857F5,
+ (q31_t)0xF1805662, (q31_t)0x7F2D1C0E, (q31_t)0xF11C789A,
+ (q31_t)0x7F2191B4, (q31_t)0xF0B8A401, (q31_t)0x7F15B8EE,
+ (q31_t)0xF054D8D4, (q31_t)0x7F0991C3, (q31_t)0xEFF11752,
+ (q31_t)0x7EFD1C3C, (q31_t)0xEF8D5FB8, (q31_t)0x7EF0585F,
+ (q31_t)0xEF29B243, (q31_t)0x7EE34635, (q31_t)0xEEC60F31,
+ (q31_t)0x7ED5E5C6, (q31_t)0xEE6276BF, (q31_t)0x7EC8371A,
+ (q31_t)0xEDFEE92B, (q31_t)0x7EBA3A39, (q31_t)0xED9B66B2,
+ (q31_t)0x7EABEF2C, (q31_t)0xED37EF91, (q31_t)0x7E9D55FC,
+ (q31_t)0xECD48406, (q31_t)0x7E8E6EB1, (q31_t)0xEC71244F,
+ (q31_t)0x7E7F3956, (q31_t)0xEC0DD0A8, (q31_t)0x7E6FB5F3,
+ (q31_t)0xEBAA894E, (q31_t)0x7E5FE493, (q31_t)0xEB474E80,
+ (q31_t)0x7E4FC53E, (q31_t)0xEAE4207A, (q31_t)0x7E3F57FE,
+ (q31_t)0xEA80FF79, (q31_t)0x7E2E9CDF, (q31_t)0xEA1DEBBB,
+ (q31_t)0x7E1D93E9, (q31_t)0xE9BAE57C, (q31_t)0x7E0C3D29,
+ (q31_t)0xE957ECFB, (q31_t)0x7DFA98A7, (q31_t)0xE8F50273,
+ (q31_t)0x7DE8A670, (q31_t)0xE8922621, (q31_t)0x7DD6668E,
+ (q31_t)0xE82F5844, (q31_t)0x7DC3D90D, (q31_t)0xE7CC9917,
+ (q31_t)0x7DB0FDF7, (q31_t)0xE769E8D8, (q31_t)0x7D9DD55A,
+ (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xE6A4B616,
+ (q31_t)0x7D769BB5, (q31_t)0xE642340D, (q31_t)0x7D628AC5,
+ (q31_t)0xE5DFC1E4, (q31_t)0x7D4E2C7E, (q31_t)0xE57D5FDA,
+ (q31_t)0x7D3980EC, (q31_t)0xE51B0E2A, (q31_t)0x7D24881A,
+ (q31_t)0xE4B8CD10, (q31_t)0x7D0F4218, (q31_t)0xE4569CCB,
+ (q31_t)0x7CF9AEF0, (q31_t)0xE3F47D95, (q31_t)0x7CE3CEB1,
+ (q31_t)0xE3926FAC, (q31_t)0x7CCDA168, (q31_t)0xE330734C,
+ (q31_t)0x7CB72724, (q31_t)0xE2CE88B2, (q31_t)0x7CA05FF1,
+ (q31_t)0xE26CB01A, (q31_t)0x7C894BDD, (q31_t)0xE20AE9C1,
+ (q31_t)0x7C71EAF8, (q31_t)0xE1A935E1, (q31_t)0x7C5A3D4F,
+ (q31_t)0xE14794B9, (q31_t)0x7C4242F2, (q31_t)0xE0E60684,
+ (q31_t)0x7C29FBEE, (q31_t)0xE0848B7F, (q31_t)0x7C116853,
+ (q31_t)0xE02323E5, (q31_t)0x7BF88830, (q31_t)0xDFC1CFF2,
+ (q31_t)0x7BDF5B94, (q31_t)0xDF608FE3, (q31_t)0x7BC5E28F,
+ (q31_t)0xDEFF63F4, (q31_t)0x7BAC1D31, (q31_t)0xDE9E4C60,
+ (q31_t)0x7B920B89, (q31_t)0xDE3D4963, (q31_t)0x7B77ADA8,
+ (q31_t)0xDDDC5B3A, (q31_t)0x7B5D039D, (q31_t)0xDD7B8220,
+ (q31_t)0x7B420D7A, (q31_t)0xDD1ABE51, (q31_t)0x7B26CB4F,
+ (q31_t)0xDCBA1008, (q31_t)0x7B0B3D2C, (q31_t)0xDC597781,
+ (q31_t)0x7AEF6323, (q31_t)0xDBF8F4F8, (q31_t)0x7AD33D45,
+ (q31_t)0xDB9888A8, (q31_t)0x7AB6CBA3, (q31_t)0xDB3832CD,
+ (q31_t)0x7A9A0E4F, (q31_t)0xDAD7F3A2, (q31_t)0x7A7D055B,
+ (q31_t)0xDA77CB62, (q31_t)0x7A5FB0D8, (q31_t)0xDA17BA4A,
+ (q31_t)0x7A4210D8, (q31_t)0xD9B7C093, (q31_t)0x7A24256E,
+ (q31_t)0xD957DE7A, (q31_t)0x7A05EEAD, (q31_t)0xD8F81439,
+ (q31_t)0x79E76CA6, (q31_t)0xD898620C, (q31_t)0x79C89F6D,
+ (q31_t)0xD838C82D, (q31_t)0x79A98715, (q31_t)0xD7D946D7,
+ (q31_t)0x798A23B1, (q31_t)0xD779DE46, (q31_t)0x796A7554,
+ (q31_t)0xD71A8EB5, (q31_t)0x794A7C11, (q31_t)0xD6BB585D,
+ (q31_t)0x792A37FE, (q31_t)0xD65C3B7B, (q31_t)0x7909A92C,
+ (q31_t)0xD5FD3847, (q31_t)0x78E8CFB1, (q31_t)0xD59E4EFE,
+ (q31_t)0x78C7ABA1, (q31_t)0xD53F7FDA, (q31_t)0x78A63D10,
+ (q31_t)0xD4E0CB14, (q31_t)0x78848413, (q31_t)0xD48230E8,
+ (q31_t)0x786280BF, (q31_t)0xD423B190, (q31_t)0x78403328,
+ (q31_t)0xD3C54D46, (q31_t)0x781D9B64, (q31_t)0xD3670445,
+ (q31_t)0x77FAB988, (q31_t)0xD308D6C6, (q31_t)0x77D78DAA,
+ (q31_t)0xD2AAC504, (q31_t)0x77B417DF, (q31_t)0xD24CCF38,
+ (q31_t)0x7790583D, (q31_t)0xD1EEF59E, (q31_t)0x776C4EDB,
+ (q31_t)0xD191386D, (q31_t)0x7747FBCE, (q31_t)0xD13397E1,
+ (q31_t)0x77235F2D, (q31_t)0xD0D61433, (q31_t)0x76FE790E,
+ (q31_t)0xD078AD9D, (q31_t)0x76D94988, (q31_t)0xD01B6459,
+ (q31_t)0x76B3D0B3, (q31_t)0xCFBE389F, (q31_t)0x768E0EA5,
+ (q31_t)0xCF612AAA, (q31_t)0x76680376, (q31_t)0xCF043AB2,
+ (q31_t)0x7641AF3C, (q31_t)0xCEA768F2, (q31_t)0x761B1211,
+ (q31_t)0xCE4AB5A2, (q31_t)0x75F42C0A, (q31_t)0xCDEE20FC,
+ (q31_t)0x75CCFD42, (q31_t)0xCD91AB38, (q31_t)0x75A585CF,
+ (q31_t)0xCD355490, (q31_t)0x757DC5CA, (q31_t)0xCCD91D3D,
+ (q31_t)0x7555BD4B, (q31_t)0xCC7D0577, (q31_t)0x752D6C6C,
+ (q31_t)0xCC210D78, (q31_t)0x7504D345, (q31_t)0xCBC53578,
+ (q31_t)0x74DBF1EF, (q31_t)0xCB697DB0, (q31_t)0x74B2C883,
+ (q31_t)0xCB0DE658, (q31_t)0x7489571B, (q31_t)0xCAB26FA9,
+ (q31_t)0x745F9DD1, (q31_t)0xCA5719DB, (q31_t)0x74359CBD,
+ (q31_t)0xC9FBE527, (q31_t)0x740B53FA, (q31_t)0xC9A0D1C4,
+ (q31_t)0x73E0C3A3, (q31_t)0xC945DFEC, (q31_t)0x73B5EBD0,
+ (q31_t)0xC8EB0FD6, (q31_t)0x738ACC9E, (q31_t)0xC89061BA,
+ (q31_t)0x735F6626, (q31_t)0xC835D5D0, (q31_t)0x7333B883,
+ (q31_t)0xC7DB6C50, (q31_t)0x7307C3D0, (q31_t)0xC7812571,
+ (q31_t)0x72DB8828, (q31_t)0xC727016C, (q31_t)0x72AF05A6,
+ (q31_t)0xC6CD0079, (q31_t)0x72823C66, (q31_t)0xC67322CD,
+ (q31_t)0x72552C84, (q31_t)0xC61968A2, (q31_t)0x7227D61C,
+ (q31_t)0xC5BFD22E, (q31_t)0x71FA3948, (q31_t)0xC5665FA8,
+ (q31_t)0x71CC5626, (q31_t)0xC50D1148, (q31_t)0x719E2CD2,
+ (q31_t)0xC4B3E746, (q31_t)0x716FBD68, (q31_t)0xC45AE1D7,
+ (q31_t)0x71410804, (q31_t)0xC4020132, (q31_t)0x71120CC5,
+ (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xC350AF25,
+ (q31_t)0x70B34524, (q31_t)0xC2F83E2A, (q31_t)0x708378FE,
+ (q31_t)0xC29FF2D4, (q31_t)0x70536771, (q31_t)0xC247CD5A,
+ (q31_t)0x70231099, (q31_t)0xC1EFCDF2, (q31_t)0x6FF27496,
+ (q31_t)0xC197F4D3, (q31_t)0x6FC19385, (q31_t)0xC1404233,
+ (q31_t)0x6F906D84, (q31_t)0xC0E8B648, (q31_t)0x6F5F02B1,
+ (q31_t)0xC0915147, (q31_t)0x6F2D532C, (q31_t)0xC03A1368,
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+ (q31_t)0xBF8C0DE2, (q31_t)0x6E96A99C, (q31_t)0xBF3546A8,
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+ (q31_t)0x82F0BDE8, (q31_t)0x1B4732EF, (q31_t)0x82DB77E5,
+ (q31_t)0x1AE4F1D6, (q31_t)0x82C67F13, (q31_t)0x1A82A025,
+ (q31_t)0x82B1D381, (q31_t)0x1A203E1B, (q31_t)0x829D753A,
+ (q31_t)0x19BDCBF2, (q31_t)0x8289644A, (q31_t)0x195B49E9,
+ (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x82622AA5,
+ (q31_t)0x18961727, (q31_t)0x824F0208, (q31_t)0x183366E8,
+ (q31_t)0x823C26F2, (q31_t)0x17D0A7BB, (q31_t)0x82299971,
+ (q31_t)0x176DD9DE, (q31_t)0x8217598F, (q31_t)0x170AFD8D,
+ (q31_t)0x82056758, (q31_t)0x16A81305, (q31_t)0x81F3C2D7,
+ (q31_t)0x16451A83, (q31_t)0x81E26C16, (q31_t)0x15E21444,
+ (q31_t)0x81D16320, (q31_t)0x157F0086, (q31_t)0x81C0A801,
+ (q31_t)0x151BDF85, (q31_t)0x81B03AC1, (q31_t)0x14B8B17F,
+ (q31_t)0x81A01B6C, (q31_t)0x145576B1, (q31_t)0x81904A0C,
+ (q31_t)0x13F22F57, (q31_t)0x8180C6A9, (q31_t)0x138EDBB0,
+ (q31_t)0x8171914E, (q31_t)0x132B7BF9, (q31_t)0x8162AA03,
+ (q31_t)0x12C8106E, (q31_t)0x815410D3, (q31_t)0x1264994E,
+ (q31_t)0x8145C5C6, (q31_t)0x120116D4, (q31_t)0x8137C8E6,
+ (q31_t)0x119D8940, (q31_t)0x812A1A39, (q31_t)0x1139F0CE,
+ (q31_t)0x811CB9CA, (q31_t)0x10D64DBC, (q31_t)0x810FA7A0,
+ (q31_t)0x1072A047, (q31_t)0x8102E3C3, (q31_t)0x100EE8AD,
+ (q31_t)0x80F66E3C, (q31_t)0x0FAB272B, (q31_t)0x80EA4712,
+ (q31_t)0x0F475BFE, (q31_t)0x80DE6E4C, (q31_t)0x0EE38765,
+ (q31_t)0x80D2E3F1, (q31_t)0x0E7FA99D, (q31_t)0x80C7A80A,
+ (q31_t)0x0E1BC2E3, (q31_t)0x80BCBA9C, (q31_t)0x0DB7D376,
+ (q31_t)0x80B21BAF, (q31_t)0x0D53DB92, (q31_t)0x80A7CB49,
+ (q31_t)0x0CEFDB75, (q31_t)0x809DC970, (q31_t)0x0C8BD35E,
+ (q31_t)0x8094162B, (q31_t)0x0C27C389, (q31_t)0x808AB180,
+ (q31_t)0x0BC3AC35, (q31_t)0x80819B74, (q31_t)0x0B5F8D9F,
+ (q31_t)0x8078D40D, (q31_t)0x0AFB6805, (q31_t)0x80705B50,
+ (q31_t)0x0A973BA5, (q31_t)0x80683143, (q31_t)0x0A3308BC,
+ (q31_t)0x806055EA, (q31_t)0x09CECF89, (q31_t)0x8058C94C,
+ (q31_t)0x096A9049, (q31_t)0x80518B6B, (q31_t)0x09064B3A,
+ (q31_t)0x804A9C4D, (q31_t)0x08A2009A, (q31_t)0x8043FBF6,
+ (q31_t)0x083DB0A7, (q31_t)0x803DAA69, (q31_t)0x07D95B9E,
+ (q31_t)0x8037A7AC, (q31_t)0x077501BE, (q31_t)0x8031F3C1,
+ (q31_t)0x0710A344, (q31_t)0x802C8EAD, (q31_t)0x06AC406F,
+ (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x8022B113,
+ (q31_t)0x05E36EA9, (q31_t)0x801E3894, (q31_t)0x057F0034,
+ (q31_t)0x801A0EF7, (q31_t)0x051A8E5C, (q31_t)0x80163440,
+ (q31_t)0x04B6195D, (q31_t)0x8012A86F, (q31_t)0x0451A176,
+ (q31_t)0x800F6B88, (q31_t)0x03ED26E6, (q31_t)0x800C7D8C,
+ (q31_t)0x0388A9E9, (q31_t)0x8009DE7D, (q31_t)0x03242ABF,
+ (q31_t)0x80078E5E, (q31_t)0x02BFA9A4, (q31_t)0x80058D2E,
+ (q31_t)0x025B26D7, (q31_t)0x8003DAF0, (q31_t)0x01F6A296,
+ (q31_t)0x800277A5, (q31_t)0x01921D1F, (q31_t)0x8001634D,
+ (q31_t)0x012D96B0, (q31_t)0x80009DE9, (q31_t)0x00C90F88,
+ (q31_t)0x8000277A, (q31_t)0x006487E3, (q31_t)0x80000000,
+ (q31_t)0x00000000, (q31_t)0x8000277A, (q31_t)0xFF9B781D,
+ (q31_t)0x80009DE9, (q31_t)0xFF36F078, (q31_t)0x8001634D,
+ (q31_t)0xFED2694F, (q31_t)0x800277A5, (q31_t)0xFE6DE2E0,
+ (q31_t)0x8003DAF0, (q31_t)0xFE095D69, (q31_t)0x80058D2E,
+ (q31_t)0xFDA4D928, (q31_t)0x80078E5E, (q31_t)0xFD40565B,
+ (q31_t)0x8009DE7D, (q31_t)0xFCDBD541, (q31_t)0x800C7D8C,
+ (q31_t)0xFC775616, (q31_t)0x800F6B88, (q31_t)0xFC12D919,
+ (q31_t)0x8012A86F, (q31_t)0xFBAE5E89, (q31_t)0x80163440,
+ (q31_t)0xFB49E6A2, (q31_t)0x801A0EF7, (q31_t)0xFAE571A4,
+ (q31_t)0x801E3894, (q31_t)0xFA80FFCB, (q31_t)0x8022B113,
+ (q31_t)0xFA1C9156, (q31_t)0x80277872, (q31_t)0xF9B82683,
+ (q31_t)0x802C8EAD, (q31_t)0xF953BF90, (q31_t)0x8031F3C1,
+ (q31_t)0xF8EF5CBB, (q31_t)0x8037A7AC, (q31_t)0xF88AFE41,
+ (q31_t)0x803DAA69, (q31_t)0xF826A461, (q31_t)0x8043FBF6,
+ (q31_t)0xF7C24F58, (q31_t)0x804A9C4D, (q31_t)0xF75DFF65,
+ (q31_t)0x80518B6B, (q31_t)0xF6F9B4C5, (q31_t)0x8058C94C,
+ (q31_t)0xF6956FB6, (q31_t)0x806055EA, (q31_t)0xF6313076,
+ (q31_t)0x80683143, (q31_t)0xF5CCF743, (q31_t)0x80705B50,
+ (q31_t)0xF568C45A, (q31_t)0x8078D40D, (q31_t)0xF50497FA,
+ (q31_t)0x80819B74, (q31_t)0xF4A07260, (q31_t)0x808AB180,
+ (q31_t)0xF43C53CA, (q31_t)0x8094162B, (q31_t)0xF3D83C76,
+ (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x80A7CB49,
+ (q31_t)0xF310248A, (q31_t)0x80B21BAF, (q31_t)0xF2AC246D,
+ (q31_t)0x80BCBA9C, (q31_t)0xF2482C89, (q31_t)0x80C7A80A,
+ (q31_t)0xF1E43D1C, (q31_t)0x80D2E3F1, (q31_t)0xF1805662,
+ (q31_t)0x80DE6E4C, (q31_t)0xF11C789A, (q31_t)0x80EA4712,
+ (q31_t)0xF0B8A401, (q31_t)0x80F66E3C, (q31_t)0xF054D8D4,
+ (q31_t)0x8102E3C3, (q31_t)0xEFF11752, (q31_t)0x810FA7A0,
+ (q31_t)0xEF8D5FB8, (q31_t)0x811CB9CA, (q31_t)0xEF29B243,
+ (q31_t)0x812A1A39, (q31_t)0xEEC60F31, (q31_t)0x8137C8E6,
+ (q31_t)0xEE6276BF, (q31_t)0x8145C5C6, (q31_t)0xEDFEE92B,
+ (q31_t)0x815410D3, (q31_t)0xED9B66B2, (q31_t)0x8162AA03,
+ (q31_t)0xED37EF91, (q31_t)0x8171914E, (q31_t)0xECD48406,
+ (q31_t)0x8180C6A9, (q31_t)0xEC71244F, (q31_t)0x81904A0C,
+ (q31_t)0xEC0DD0A8, (q31_t)0x81A01B6C, (q31_t)0xEBAA894E,
+ (q31_t)0x81B03AC1, (q31_t)0xEB474E80, (q31_t)0x81C0A801,
+ (q31_t)0xEAE4207A, (q31_t)0x81D16320, (q31_t)0xEA80FF79,
+ (q31_t)0x81E26C16, (q31_t)0xEA1DEBBB, (q31_t)0x81F3C2D7,
+ (q31_t)0xE9BAE57C, (q31_t)0x82056758, (q31_t)0xE957ECFB,
+ (q31_t)0x8217598F, (q31_t)0xE8F50273, (q31_t)0x82299971,
+ (q31_t)0xE8922621, (q31_t)0x823C26F2, (q31_t)0xE82F5844,
+ (q31_t)0x824F0208, (q31_t)0xE7CC9917, (q31_t)0x82622AA5,
+ (q31_t)0xE769E8D8, (q31_t)0x8275A0C0, (q31_t)0xE70747C3,
+ (q31_t)0x8289644A, (q31_t)0xE6A4B616, (q31_t)0x829D753A,
+ (q31_t)0xE642340D, (q31_t)0x82B1D381, (q31_t)0xE5DFC1E4,
+ (q31_t)0x82C67F13, (q31_t)0xE57D5FDA, (q31_t)0x82DB77E5,
+ (q31_t)0xE51B0E2A, (q31_t)0x82F0BDE8, (q31_t)0xE4B8CD10,
+ (q31_t)0x8306510F, (q31_t)0xE4569CCB, (q31_t)0x831C314E,
+ (q31_t)0xE3F47D95, (q31_t)0x83325E97, (q31_t)0xE3926FAC,
+ (q31_t)0x8348D8DB, (q31_t)0xE330734C, (q31_t)0x835FA00E,
+ (q31_t)0xE2CE88B2, (q31_t)0x8376B422, (q31_t)0xE26CB01A,
+ (q31_t)0x838E1507, (q31_t)0xE20AE9C1, (q31_t)0x83A5C2B0,
+ (q31_t)0xE1A935E1, (q31_t)0x83BDBD0D, (q31_t)0xE14794B9,
+ (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x83EE97AC,
+ (q31_t)0xE0848B7F, (q31_t)0x840777CF, (q31_t)0xE02323E5,
+ (q31_t)0x8420A46B, (q31_t)0xDFC1CFF2, (q31_t)0x843A1D70,
+ (q31_t)0xDF608FE3, (q31_t)0x8453E2CE, (q31_t)0xDEFF63F4,
+ (q31_t)0x846DF476, (q31_t)0xDE9E4C60, (q31_t)0x84885257,
+ (q31_t)0xDE3D4963, (q31_t)0x84A2FC62, (q31_t)0xDDDC5B3A,
+ (q31_t)0x84BDF285, (q31_t)0xDD7B8220, (q31_t)0x84D934B0,
+ (q31_t)0xDD1ABE51, (q31_t)0x84F4C2D3, (q31_t)0xDCBA1008,
+ (q31_t)0x85109CDC, (q31_t)0xDC597781, (q31_t)0x852CC2BA,
+ (q31_t)0xDBF8F4F8, (q31_t)0x8549345C, (q31_t)0xDB9888A8,
+ (q31_t)0x8565F1B0, (q31_t)0xDB3832CD, (q31_t)0x8582FAA4,
+ (q31_t)0xDAD7F3A2, (q31_t)0x85A04F28, (q31_t)0xDA77CB62,
+ (q31_t)0x85BDEF27, (q31_t)0xDA17BA4A, (q31_t)0x85DBDA91,
+ (q31_t)0xD9B7C093, (q31_t)0x85FA1152, (q31_t)0xD957DE7A,
+ (q31_t)0x86189359, (q31_t)0xD8F81439, (q31_t)0x86376092,
+ (q31_t)0xD898620C, (q31_t)0x865678EA, (q31_t)0xD838C82D,
+ (q31_t)0x8675DC4E, (q31_t)0xD7D946D7, (q31_t)0x86958AAB,
+ (q31_t)0xD779DE46, (q31_t)0x86B583EE, (q31_t)0xD71A8EB5,
+ (q31_t)0x86D5C802, (q31_t)0xD6BB585D, (q31_t)0x86F656D3,
+ (q31_t)0xD65C3B7B, (q31_t)0x8717304E, (q31_t)0xD5FD3847,
+ (q31_t)0x8738545E, (q31_t)0xD59E4EFE, (q31_t)0x8759C2EF,
+ (q31_t)0xD53F7FDA, (q31_t)0x877B7BEC, (q31_t)0xD4E0CB14,
+ (q31_t)0x879D7F40, (q31_t)0xD48230E8, (q31_t)0x87BFCCD7,
+ (q31_t)0xD423B190, (q31_t)0x87E2649B, (q31_t)0xD3C54D46,
+ (q31_t)0x88054677, (q31_t)0xD3670445, (q31_t)0x88287255,
+ (q31_t)0xD308D6C6, (q31_t)0x884BE820, (q31_t)0xD2AAC504,
+ (q31_t)0x886FA7C2, (q31_t)0xD24CCF38, (q31_t)0x8893B124,
+ (q31_t)0xD1EEF59E, (q31_t)0x88B80431, (q31_t)0xD191386D,
+ (q31_t)0x88DCA0D3, (q31_t)0xD13397E1, (q31_t)0x890186F1,
+ (q31_t)0xD0D61433, (q31_t)0x8926B677, (q31_t)0xD078AD9D,
+ (q31_t)0x894C2F4C, (q31_t)0xD01B6459, (q31_t)0x8971F15A,
+ (q31_t)0xCFBE389F, (q31_t)0x8997FC89, (q31_t)0xCF612AAA,
+ (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x89E4EDEE,
+ (q31_t)0xCEA768F2, (q31_t)0x8A0BD3F5, (q31_t)0xCE4AB5A2,
+ (q31_t)0x8A3302BD, (q31_t)0xCDEE20FC, (q31_t)0x8A5A7A30,
+ (q31_t)0xCD91AB38, (q31_t)0x8A823A35, (q31_t)0xCD355490,
+ (q31_t)0x8AAA42B4, (q31_t)0xCCD91D3D, (q31_t)0x8AD29393,
+ (q31_t)0xCC7D0577, (q31_t)0x8AFB2CBA, (q31_t)0xCC210D78,
+ (q31_t)0x8B240E10, (q31_t)0xCBC53578, (q31_t)0x8B4D377C,
+ (q31_t)0xCB697DB0, (q31_t)0x8B76A8E4, (q31_t)0xCB0DE658,
+ (q31_t)0x8BA0622F, (q31_t)0xCAB26FA9, (q31_t)0x8BCA6342,
+ (q31_t)0xCA5719DB, (q31_t)0x8BF4AC05, (q31_t)0xC9FBE527,
+ (q31_t)0x8C1F3C5C, (q31_t)0xC9A0D1C4, (q31_t)0x8C4A142F,
+ (q31_t)0xC945DFEC, (q31_t)0x8C753361, (q31_t)0xC8EB0FD6,
+ (q31_t)0x8CA099D9, (q31_t)0xC89061BA, (q31_t)0x8CCC477D,
+ (q31_t)0xC835D5D0, (q31_t)0x8CF83C30, (q31_t)0xC7DB6C50,
+ (q31_t)0x8D2477D8, (q31_t)0xC7812571, (q31_t)0x8D50FA59,
+ (q31_t)0xC727016C, (q31_t)0x8D7DC399, (q31_t)0xC6CD0079,
+ (q31_t)0x8DAAD37B, (q31_t)0xC67322CD, (q31_t)0x8DD829E4,
+ (q31_t)0xC61968A2, (q31_t)0x8E05C6B7, (q31_t)0xC5BFD22E,
+ (q31_t)0x8E33A9D9, (q31_t)0xC5665FA8, (q31_t)0x8E61D32D,
+ (q31_t)0xC50D1148, (q31_t)0x8E904298, (q31_t)0xC4B3E746,
+ (q31_t)0x8EBEF7FB, (q31_t)0xC45AE1D7, (q31_t)0x8EEDF33B,
+ (q31_t)0xC4020132, (q31_t)0x8F1D343A, (q31_t)0xC3A9458F,
+ (q31_t)0x8F4CBADB, (q31_t)0xC350AF25, (q31_t)0x8F7C8701,
+ (q31_t)0xC2F83E2A, (q31_t)0x8FAC988E, (q31_t)0xC29FF2D4,
+ (q31_t)0x8FDCEF66, (q31_t)0xC247CD5A, (q31_t)0x900D8B69,
+ (q31_t)0xC1EFCDF2, (q31_t)0x903E6C7A, (q31_t)0xC197F4D3,
+ (q31_t)0x906F927B, (q31_t)0xC1404233, (q31_t)0x90A0FD4E,
+ (q31_t)0xC0E8B648, (q31_t)0x90D2ACD3, (q31_t)0xC0915147,
+ (q31_t)0x9104A0ED, (q31_t)0xC03A1368, (q31_t)0x9136D97D,
+ (q31_t)0xBFE2FCDF, (q31_t)0x91695663, (q31_t)0xBF8C0DE2,
+ (q31_t)0x919C1780, (q31_t)0xBF3546A8, (q31_t)0x91CF1CB6,
+ (q31_t)0xBEDEA765, (q31_t)0x920265E4, (q31_t)0xBE88304F,
+ (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x9269C3AC,
+ (q31_t)0xBDDBBB7F, (q31_t)0x929DD805, (q31_t)0xBD85BE2F,
+ (q31_t)0x92D22FD8, (q31_t)0xBD2FE9E1, (q31_t)0x9306CB04,
+ (q31_t)0xBCDA3ECA, (q31_t)0x933BA968, (q31_t)0xBC84BD1E,
+ (q31_t)0x9370CAE4, (q31_t)0xBC2F6513, (q31_t)0x93A62F56,
+ (q31_t)0xBBDA36DC, (q31_t)0x93DBD69F, (q31_t)0xBB8532AF,
+ (q31_t)0x9411C09D, (q31_t)0xBB3058C0, (q31_t)0x9447ED2F,
+ (q31_t)0xBADBA943, (q31_t)0x947E5C32, (q31_t)0xBA87246C,
+ (q31_t)0x94B50D87, (q31_t)0xBA32CA70, (q31_t)0x94EC010B,
+ (q31_t)0xB9DE9B83, (q31_t)0x9523369B, (q31_t)0xB98A97D8,
+ (q31_t)0x955AAE17, (q31_t)0xB936BFA3, (q31_t)0x9592675B,
+ (q31_t)0xB8E31319, (q31_t)0x95CA6246, (q31_t)0xB88F926C,
+ (q31_t)0x96029EB5, (q31_t)0xB83C3DD1, (q31_t)0x963B1C85,
+ (q31_t)0xB7E9157A, (q31_t)0x9673DB94, (q31_t)0xB796199B,
+ (q31_t)0x96ACDBBD, (q31_t)0xB7434A67, (q31_t)0x96E61CDF,
+ (q31_t)0xB6F0A811, (q31_t)0x971F9ED6, (q31_t)0xB69E32CD,
+ (q31_t)0x9759617E, (q31_t)0xB64BEACC, (q31_t)0x979364B5,
+ (q31_t)0xB5F9D042, (q31_t)0x97CDA855, (q31_t)0xB5A7E362,
+ (q31_t)0x98082C3B, (q31_t)0xB556245E, (q31_t)0x9842F043,
+ (q31_t)0xB5049368, (q31_t)0x987DF449, (q31_t)0xB4B330B2,
+ (q31_t)0x98B93828, (q31_t)0xB461FC70, (q31_t)0x98F4BBBC,
+ (q31_t)0xB410F6D2, (q31_t)0x99307EE0, (q31_t)0xB3C0200C,
+ (q31_t)0x996C816F, (q31_t)0xB36F784E, (q31_t)0x99A8C344,
+ (q31_t)0xB31EFFCB, (q31_t)0x99E5443A, (q31_t)0xB2CEB6B5,
+ (q31_t)0x9A22042C, (q31_t)0xB27E9D3B, (q31_t)0x9A5F02F5,
+ (q31_t)0xB22EB392, (q31_t)0x9A9C406D, (q31_t)0xB1DEF9E8,
+ (q31_t)0x9AD9BC71, (q31_t)0xB18F7070, (q31_t)0x9B1776D9,
+ (q31_t)0xB140175B, (q31_t)0x9B556F80, (q31_t)0xB0F0EEDA,
+ (q31_t)0x9B93A640, (q31_t)0xB0A1F71C, (q31_t)0x9BD21AF2,
+ (q31_t)0xB0533055, (q31_t)0x9C10CD70, (q31_t)0xB0049AB2,
+ (q31_t)0x9C4FBD92, (q31_t)0xAFB63667, (q31_t)0x9C8EEB33,
+ (q31_t)0xAF6803A1, (q31_t)0x9CCE562B, (q31_t)0xAF1A0293,
+ (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0x9D4DE384,
+ (q31_t)0xAE7E965B, (q31_t)0x9D8E0596, (q31_t)0xAE312B91,
+ (q31_t)0x9DCE6462, (q31_t)0xADE3F33E, (q31_t)0x9E0EFFC1,
+ (q31_t)0xAD96ED91, (q31_t)0x9E4FD789, (q31_t)0xAD4A1ABA,
+ (q31_t)0x9E90EB94, (q31_t)0xACFD7AE8, (q31_t)0x9ED23BB9,
+ (q31_t)0xACB10E4A, (q31_t)0x9F13C7D0, (q31_t)0xAC64D510,
+ (q31_t)0x9F558FB0, (q31_t)0xAC18CF68, (q31_t)0x9F979331,
+ (q31_t)0xABCCFD82, (q31_t)0x9FD9D22A, (q31_t)0xAB815F8C,
+ (q31_t)0xA01C4C72, (q31_t)0xAB35F5B5, (q31_t)0xA05F01E1,
+ (q31_t)0xAAEAC02B, (q31_t)0xA0A1F24C, (q31_t)0xAA9FBF1D,
+ (q31_t)0xA0E51D8C, (q31_t)0xAA54F2B9, (q31_t)0xA1288376,
+ (q31_t)0xAA0A5B2D, (q31_t)0xA16C23E1, (q31_t)0xA9BFF8A8,
+ (q31_t)0xA1AFFEA2, (q31_t)0xA975CB56, (q31_t)0xA1F41391,
+ (q31_t)0xA92BD366, (q31_t)0xA2386283, (q31_t)0xA8E21106,
+ (q31_t)0xA27CEB4F, (q31_t)0xA8988463, (q31_t)0xA2C1ADC9,
+ (q31_t)0xA84F2DA9, (q31_t)0xA306A9C7, (q31_t)0xA8060D08,
+ (q31_t)0xA34BDF20, (q31_t)0xA7BD22AB, (q31_t)0xA3914DA7,
+ (q31_t)0xA7746EC0, (q31_t)0xA3D6F533, (q31_t)0xA72BF173,
+ (q31_t)0xA41CD598, (q31_t)0xA6E3AAF2, (q31_t)0xA462EEAC,
+ (q31_t)0xA69B9B68, (q31_t)0xA4A94042, (q31_t)0xA653C302,
+ (q31_t)0xA4EFCA31, (q31_t)0xA60C21ED, (q31_t)0xA5368C4B,
+ (q31_t)0xA5C4B855, (q31_t)0xA57D8666, (q31_t)0xA57D8666,
+ (q31_t)0xA5C4B855, (q31_t)0xA5368C4B, (q31_t)0xA60C21ED,
+ (q31_t)0xA4EFCA31, (q31_t)0xA653C302, (q31_t)0xA4A94042,
+ (q31_t)0xA69B9B68, (q31_t)0xA462EEAC, (q31_t)0xA6E3AAF2,
+ (q31_t)0xA41CD598, (q31_t)0xA72BF173, (q31_t)0xA3D6F533,
+ (q31_t)0xA7746EC0, (q31_t)0xA3914DA7, (q31_t)0xA7BD22AB,
+ (q31_t)0xA34BDF20, (q31_t)0xA8060D08, (q31_t)0xA306A9C7,
+ (q31_t)0xA84F2DA9, (q31_t)0xA2C1ADC9, (q31_t)0xA8988463,
+ (q31_t)0xA27CEB4F, (q31_t)0xA8E21106, (q31_t)0xA2386283,
+ (q31_t)0xA92BD366, (q31_t)0xA1F41391, (q31_t)0xA975CB56,
+ (q31_t)0xA1AFFEA2, (q31_t)0xA9BFF8A8, (q31_t)0xA16C23E1,
+ (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAA54F2B9,
+ (q31_t)0xA0E51D8C, (q31_t)0xAA9FBF1D, (q31_t)0xA0A1F24C,
+ (q31_t)0xAAEAC02B, (q31_t)0xA05F01E1, (q31_t)0xAB35F5B5,
+ (q31_t)0xA01C4C72, (q31_t)0xAB815F8C, (q31_t)0x9FD9D22A,
+ (q31_t)0xABCCFD82, (q31_t)0x9F979331, (q31_t)0xAC18CF68,
+ (q31_t)0x9F558FB0, (q31_t)0xAC64D510, (q31_t)0x9F13C7D0,
+ (q31_t)0xACB10E4A, (q31_t)0x9ED23BB9, (q31_t)0xACFD7AE8,
+ (q31_t)0x9E90EB94, (q31_t)0xAD4A1ABA, (q31_t)0x9E4FD789,
+ (q31_t)0xAD96ED91, (q31_t)0x9E0EFFC1, (q31_t)0xADE3F33E,
+ (q31_t)0x9DCE6462, (q31_t)0xAE312B91, (q31_t)0x9D8E0596,
+ (q31_t)0xAE7E965B, (q31_t)0x9D4DE384, (q31_t)0xAECC336B,
+ (q31_t)0x9D0DFE53, (q31_t)0xAF1A0293, (q31_t)0x9CCE562B,
+ (q31_t)0xAF6803A1, (q31_t)0x9C8EEB33, (q31_t)0xAFB63667,
+ (q31_t)0x9C4FBD92, (q31_t)0xB0049AB2, (q31_t)0x9C10CD70,
+ (q31_t)0xB0533055, (q31_t)0x9BD21AF2, (q31_t)0xB0A1F71C,
+ (q31_t)0x9B93A640, (q31_t)0xB0F0EEDA, (q31_t)0x9B556F80,
+ (q31_t)0xB140175B, (q31_t)0x9B1776D9, (q31_t)0xB18F7070,
+ (q31_t)0x9AD9BC71, (q31_t)0xB1DEF9E8, (q31_t)0x9A9C406D,
+ (q31_t)0xB22EB392, (q31_t)0x9A5F02F5, (q31_t)0xB27E9D3B,
+ (q31_t)0x9A22042C, (q31_t)0xB2CEB6B5, (q31_t)0x99E5443A,
+ (q31_t)0xB31EFFCB, (q31_t)0x99A8C344, (q31_t)0xB36F784E,
+ (q31_t)0x996C816F, (q31_t)0xB3C0200C, (q31_t)0x99307EE0,
+ (q31_t)0xB410F6D2, (q31_t)0x98F4BBBC, (q31_t)0xB461FC70,
+ (q31_t)0x98B93828, (q31_t)0xB4B330B2, (q31_t)0x987DF449,
+ (q31_t)0xB5049368, (q31_t)0x9842F043, (q31_t)0xB556245E,
+ (q31_t)0x98082C3B, (q31_t)0xB5A7E362, (q31_t)0x97CDA855,
+ (q31_t)0xB5F9D042, (q31_t)0x979364B5, (q31_t)0xB64BEACC,
+ (q31_t)0x9759617E, (q31_t)0xB69E32CD, (q31_t)0x971F9ED6,
+ (q31_t)0xB6F0A811, (q31_t)0x96E61CDF, (q31_t)0xB7434A67,
+ (q31_t)0x96ACDBBD, (q31_t)0xB796199B, (q31_t)0x9673DB94,
+ (q31_t)0xB7E9157A, (q31_t)0x963B1C85, (q31_t)0xB83C3DD1,
+ (q31_t)0x96029EB5, (q31_t)0xB88F926C, (q31_t)0x95CA6246,
+ (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xB936BFA3,
+ (q31_t)0x955AAE17, (q31_t)0xB98A97D8, (q31_t)0x9523369B,
+ (q31_t)0xB9DE9B83, (q31_t)0x94EC010B, (q31_t)0xBA32CA70,
+ (q31_t)0x94B50D87, (q31_t)0xBA87246C, (q31_t)0x947E5C32,
+ (q31_t)0xBADBA943, (q31_t)0x9447ED2F, (q31_t)0xBB3058C0,
+ (q31_t)0x9411C09D, (q31_t)0xBB8532AF, (q31_t)0x93DBD69F,
+ (q31_t)0xBBDA36DC, (q31_t)0x93A62F56, (q31_t)0xBC2F6513,
+ (q31_t)0x9370CAE4, (q31_t)0xBC84BD1E, (q31_t)0x933BA968,
+ (q31_t)0xBCDA3ECA, (q31_t)0x9306CB04, (q31_t)0xBD2FE9E1,
+ (q31_t)0x92D22FD8, (q31_t)0xBD85BE2F, (q31_t)0x929DD805,
+ (q31_t)0xBDDBBB7F, (q31_t)0x9269C3AC, (q31_t)0xBE31E19B,
+ (q31_t)0x9235F2EB, (q31_t)0xBE88304F, (q31_t)0x920265E4,
+ (q31_t)0xBEDEA765, (q31_t)0x91CF1CB6, (q31_t)0xBF3546A8,
+ (q31_t)0x919C1780, (q31_t)0xBF8C0DE2, (q31_t)0x91695663,
+ (q31_t)0xBFE2FCDF, (q31_t)0x9136D97D, (q31_t)0xC03A1368,
+ (q31_t)0x9104A0ED, (q31_t)0xC0915147, (q31_t)0x90D2ACD3,
+ (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC1404233,
+ (q31_t)0x906F927B, (q31_t)0xC197F4D3, (q31_t)0x903E6C7A,
+ (q31_t)0xC1EFCDF2, (q31_t)0x900D8B69, (q31_t)0xC247CD5A,
+ (q31_t)0x8FDCEF66, (q31_t)0xC29FF2D4, (q31_t)0x8FAC988E,
+ (q31_t)0xC2F83E2A, (q31_t)0x8F7C8701, (q31_t)0xC350AF25,
+ (q31_t)0x8F4CBADB, (q31_t)0xC3A9458F, (q31_t)0x8F1D343A,
+ (q31_t)0xC4020132, (q31_t)0x8EEDF33B, (q31_t)0xC45AE1D7,
+ (q31_t)0x8EBEF7FB, (q31_t)0xC4B3E746, (q31_t)0x8E904298,
+ (q31_t)0xC50D1148, (q31_t)0x8E61D32D, (q31_t)0xC5665FA8,
+ (q31_t)0x8E33A9D9, (q31_t)0xC5BFD22E, (q31_t)0x8E05C6B7,
+ (q31_t)0xC61968A2, (q31_t)0x8DD829E4, (q31_t)0xC67322CD,
+ (q31_t)0x8DAAD37B, (q31_t)0xC6CD0079, (q31_t)0x8D7DC399,
+ (q31_t)0xC727016C, (q31_t)0x8D50FA59, (q31_t)0xC7812571,
+ (q31_t)0x8D2477D8, (q31_t)0xC7DB6C50, (q31_t)0x8CF83C30,
+ (q31_t)0xC835D5D0, (q31_t)0x8CCC477D, (q31_t)0xC89061BA,
+ (q31_t)0x8CA099D9, (q31_t)0xC8EB0FD6, (q31_t)0x8C753361,
+ (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xC9A0D1C4,
+ (q31_t)0x8C1F3C5C, (q31_t)0xC9FBE527, (q31_t)0x8BF4AC05,
+ (q31_t)0xCA5719DB, (q31_t)0x8BCA6342, (q31_t)0xCAB26FA9,
+ (q31_t)0x8BA0622F, (q31_t)0xCB0DE658, (q31_t)0x8B76A8E4,
+ (q31_t)0xCB697DB0, (q31_t)0x8B4D377C, (q31_t)0xCBC53578,
+ (q31_t)0x8B240E10, (q31_t)0xCC210D78, (q31_t)0x8AFB2CBA,
+ (q31_t)0xCC7D0577, (q31_t)0x8AD29393, (q31_t)0xCCD91D3D,
+ (q31_t)0x8AAA42B4, (q31_t)0xCD355490, (q31_t)0x8A823A35,
+ (q31_t)0xCD91AB38, (q31_t)0x8A5A7A30, (q31_t)0xCDEE20FC,
+ (q31_t)0x8A3302BD, (q31_t)0xCE4AB5A2, (q31_t)0x8A0BD3F5,
+ (q31_t)0xCEA768F2, (q31_t)0x89E4EDEE, (q31_t)0xCF043AB2,
+ (q31_t)0x89BE50C3, (q31_t)0xCF612AAA, (q31_t)0x8997FC89,
+ (q31_t)0xCFBE389F, (q31_t)0x8971F15A, (q31_t)0xD01B6459,
+ (q31_t)0x894C2F4C, (q31_t)0xD078AD9D, (q31_t)0x8926B677,
+ (q31_t)0xD0D61433, (q31_t)0x890186F1, (q31_t)0xD13397E1,
+ (q31_t)0x88DCA0D3, (q31_t)0xD191386D, (q31_t)0x88B80431,
+ (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD24CCF38,
+ (q31_t)0x886FA7C2, (q31_t)0xD2AAC504, (q31_t)0x884BE820,
+ (q31_t)0xD308D6C6, (q31_t)0x88287255, (q31_t)0xD3670445,
+ (q31_t)0x88054677, (q31_t)0xD3C54D46, (q31_t)0x87E2649B,
+ (q31_t)0xD423B190, (q31_t)0x87BFCCD7, (q31_t)0xD48230E8,
+ (q31_t)0x879D7F40, (q31_t)0xD4E0CB14, (q31_t)0x877B7BEC,
+ (q31_t)0xD53F7FDA, (q31_t)0x8759C2EF, (q31_t)0xD59E4EFE,
+ (q31_t)0x8738545E, (q31_t)0xD5FD3847, (q31_t)0x8717304E,
+ (q31_t)0xD65C3B7B, (q31_t)0x86F656D3, (q31_t)0xD6BB585D,
+ (q31_t)0x86D5C802, (q31_t)0xD71A8EB5, (q31_t)0x86B583EE,
+ (q31_t)0xD779DE46, (q31_t)0x86958AAB, (q31_t)0xD7D946D7,
+ (q31_t)0x8675DC4E, (q31_t)0xD838C82D, (q31_t)0x865678EA,
+ (q31_t)0xD898620C, (q31_t)0x86376092, (q31_t)0xD8F81439,
+ (q31_t)0x86189359, (q31_t)0xD957DE7A, (q31_t)0x85FA1152,
+ (q31_t)0xD9B7C093, (q31_t)0x85DBDA91, (q31_t)0xDA17BA4A,
+ (q31_t)0x85BDEF27, (q31_t)0xDA77CB62, (q31_t)0x85A04F28,
+ (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDB3832CD,
+ (q31_t)0x8565F1B0, (q31_t)0xDB9888A8, (q31_t)0x8549345C,
+ (q31_t)0xDBF8F4F8, (q31_t)0x852CC2BA, (q31_t)0xDC597781,
+ (q31_t)0x85109CDC, (q31_t)0xDCBA1008, (q31_t)0x84F4C2D3,
+ (q31_t)0xDD1ABE51, (q31_t)0x84D934B0, (q31_t)0xDD7B8220,
+ (q31_t)0x84BDF285, (q31_t)0xDDDC5B3A, (q31_t)0x84A2FC62,
+ (q31_t)0xDE3D4963, (q31_t)0x84885257, (q31_t)0xDE9E4C60,
+ (q31_t)0x846DF476, (q31_t)0xDEFF63F4, (q31_t)0x8453E2CE,
+ (q31_t)0xDF608FE3, (q31_t)0x843A1D70, (q31_t)0xDFC1CFF2,
+ (q31_t)0x8420A46B, (q31_t)0xE02323E5, (q31_t)0x840777CF,
+ (q31_t)0xE0848B7F, (q31_t)0x83EE97AC, (q31_t)0xE0E60684,
+ (q31_t)0x83D60411, (q31_t)0xE14794B9, (q31_t)0x83BDBD0D,
+ (q31_t)0xE1A935E1, (q31_t)0x83A5C2B0, (q31_t)0xE20AE9C1,
+ (q31_t)0x838E1507, (q31_t)0xE26CB01A, (q31_t)0x8376B422,
+ (q31_t)0xE2CE88B2, (q31_t)0x835FA00E, (q31_t)0xE330734C,
+ (q31_t)0x8348D8DB, (q31_t)0xE3926FAC, (q31_t)0x83325E97,
+ (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE4569CCB,
+ (q31_t)0x8306510F, (q31_t)0xE4B8CD10, (q31_t)0x82F0BDE8,
+ (q31_t)0xE51B0E2A, (q31_t)0x82DB77E5, (q31_t)0xE57D5FDA,
+ (q31_t)0x82C67F13, (q31_t)0xE5DFC1E4, (q31_t)0x82B1D381,
+ (q31_t)0xE642340D, (q31_t)0x829D753A, (q31_t)0xE6A4B616,
+ (q31_t)0x8289644A, (q31_t)0xE70747C3, (q31_t)0x8275A0C0,
+ (q31_t)0xE769E8D8, (q31_t)0x82622AA5, (q31_t)0xE7CC9917,
+ (q31_t)0x824F0208, (q31_t)0xE82F5844, (q31_t)0x823C26F2,
+ (q31_t)0xE8922621, (q31_t)0x82299971, (q31_t)0xE8F50273,
+ (q31_t)0x8217598F, (q31_t)0xE957ECFB, (q31_t)0x82056758,
+ (q31_t)0xE9BAE57C, (q31_t)0x81F3C2D7, (q31_t)0xEA1DEBBB,
+ (q31_t)0x81E26C16, (q31_t)0xEA80FF79, (q31_t)0x81D16320,
+ (q31_t)0xEAE4207A, (q31_t)0x81C0A801, (q31_t)0xEB474E80,
+ (q31_t)0x81B03AC1, (q31_t)0xEBAA894E, (q31_t)0x81A01B6C,
+ (q31_t)0xEC0DD0A8, (q31_t)0x81904A0C, (q31_t)0xEC71244F,
+ (q31_t)0x8180C6A9, (q31_t)0xECD48406, (q31_t)0x8171914E,
+ (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xED9B66B2,
+ (q31_t)0x815410D3, (q31_t)0xEDFEE92B, (q31_t)0x8145C5C6,
+ (q31_t)0xEE6276BF, (q31_t)0x8137C8E6, (q31_t)0xEEC60F31,
+ (q31_t)0x812A1A39, (q31_t)0xEF29B243, (q31_t)0x811CB9CA,
+ (q31_t)0xEF8D5FB8, (q31_t)0x810FA7A0, (q31_t)0xEFF11752,
+ (q31_t)0x8102E3C3, (q31_t)0xF054D8D4, (q31_t)0x80F66E3C,
+ (q31_t)0xF0B8A401, (q31_t)0x80EA4712, (q31_t)0xF11C789A,
+ (q31_t)0x80DE6E4C, (q31_t)0xF1805662, (q31_t)0x80D2E3F1,
+ (q31_t)0xF1E43D1C, (q31_t)0x80C7A80A, (q31_t)0xF2482C89,
+ (q31_t)0x80BCBA9C, (q31_t)0xF2AC246D, (q31_t)0x80B21BAF,
+ (q31_t)0xF310248A, (q31_t)0x80A7CB49, (q31_t)0xF3742CA1,
+ (q31_t)0x809DC970, (q31_t)0xF3D83C76, (q31_t)0x8094162B,
+ (q31_t)0xF43C53CA, (q31_t)0x808AB180, (q31_t)0xF4A07260,
+ (q31_t)0x80819B74, (q31_t)0xF50497FA, (q31_t)0x8078D40D,
+ (q31_t)0xF568C45A, (q31_t)0x80705B50, (q31_t)0xF5CCF743,
+ (q31_t)0x80683143, (q31_t)0xF6313076, (q31_t)0x806055EA,
+ (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF6F9B4C5,
+ (q31_t)0x80518B6B, (q31_t)0xF75DFF65, (q31_t)0x804A9C4D,
+ (q31_t)0xF7C24F58, (q31_t)0x8043FBF6, (q31_t)0xF826A461,
+ (q31_t)0x803DAA69, (q31_t)0xF88AFE41, (q31_t)0x8037A7AC,
+ (q31_t)0xF8EF5CBB, (q31_t)0x8031F3C1, (q31_t)0xF953BF90,
+ (q31_t)0x802C8EAD, (q31_t)0xF9B82683, (q31_t)0x80277872,
+ (q31_t)0xFA1C9156, (q31_t)0x8022B113, (q31_t)0xFA80FFCB,
+ (q31_t)0x801E3894, (q31_t)0xFAE571A4, (q31_t)0x801A0EF7,
+ (q31_t)0xFB49E6A2, (q31_t)0x80163440, (q31_t)0xFBAE5E89,
+ (q31_t)0x8012A86F, (q31_t)0xFC12D919, (q31_t)0x800F6B88,
+ (q31_t)0xFC775616, (q31_t)0x800C7D8C, (q31_t)0xFCDBD541,
+ (q31_t)0x8009DE7D, (q31_t)0xFD40565B, (q31_t)0x80078E5E,
+ (q31_t)0xFDA4D928, (q31_t)0x80058D2E, (q31_t)0xFE095D69,
+ (q31_t)0x8003DAF0, (q31_t)0xFE6DE2E0, (q31_t)0x800277A5,
+ (q31_t)0xFED2694F, (q31_t)0x8001634D, (q31_t)0xFF36F078,
+ (q31_t)0x80009DE9, (q31_t)0xFF9B781D, (q31_t)0x8000277A
+};
+
+/**
+* \par
+* Example code for Q31 Twiddle factors Generation::
+* \par
+* <pre>for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 4096 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to Q31(Fixed point 1.31):
+* round(twiddleCoefQ31(i) * pow(2, 31))
+*
+*/
+const q31_t twiddleCoef_4096_q31[6144] =
+{
+ (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FFFF621,
+ (q31_t)0x003243F5, (q31_t)0x7FFFD885, (q31_t)0x006487E3,
+ (q31_t)0x7FFFA72C, (q31_t)0x0096CBC1, (q31_t)0x7FFF6216,
+ (q31_t)0x00C90F88, (q31_t)0x7FFF0942, (q31_t)0x00FB532F,
+ (q31_t)0x7FFE9CB2, (q31_t)0x012D96B0, (q31_t)0x7FFE1C64,
+ (q31_t)0x015FDA03, (q31_t)0x7FFD885A, (q31_t)0x01921D1F,
+ (q31_t)0x7FFCE093, (q31_t)0x01C45FFE, (q31_t)0x7FFC250F,
+ (q31_t)0x01F6A296, (q31_t)0x7FFB55CE, (q31_t)0x0228E4E1,
+ (q31_t)0x7FFA72D1, (q31_t)0x025B26D7, (q31_t)0x7FF97C17,
+ (q31_t)0x028D6870, (q31_t)0x7FF871A1, (q31_t)0x02BFA9A4,
+ (q31_t)0x7FF7536F, (q31_t)0x02F1EA6B, (q31_t)0x7FF62182,
+ (q31_t)0x03242ABF, (q31_t)0x7FF4DBD8, (q31_t)0x03566A96,
+ (q31_t)0x7FF38273, (q31_t)0x0388A9E9, (q31_t)0x7FF21553,
+ (q31_t)0x03BAE8B1, (q31_t)0x7FF09477, (q31_t)0x03ED26E6,
+ (q31_t)0x7FEEFFE1, (q31_t)0x041F647F, (q31_t)0x7FED5790,
+ (q31_t)0x0451A176, (q31_t)0x7FEB9B85, (q31_t)0x0483DDC3,
+ (q31_t)0x7FE9CBC0, (q31_t)0x04B6195D, (q31_t)0x7FE7E840,
+ (q31_t)0x04E8543D, (q31_t)0x7FE5F108, (q31_t)0x051A8E5C,
+ (q31_t)0x7FE3E616, (q31_t)0x054CC7B0, (q31_t)0x7FE1C76B,
+ (q31_t)0x057F0034, (q31_t)0x7FDF9508, (q31_t)0x05B137DF,
+ (q31_t)0x7FDD4EEC, (q31_t)0x05E36EA9, (q31_t)0x7FDAF518,
+ (q31_t)0x0615A48A, (q31_t)0x7FD8878D, (q31_t)0x0647D97C,
+ (q31_t)0x7FD6064B, (q31_t)0x067A0D75, (q31_t)0x7FD37152,
+ (q31_t)0x06AC406F, (q31_t)0x7FD0C8A3, (q31_t)0x06DE7261,
+ (q31_t)0x7FCE0C3E, (q31_t)0x0710A344, (q31_t)0x7FCB3C23,
+ (q31_t)0x0742D310, (q31_t)0x7FC85853, (q31_t)0x077501BE,
+ (q31_t)0x7FC560CF, (q31_t)0x07A72F45, (q31_t)0x7FC25596,
+ (q31_t)0x07D95B9E, (q31_t)0x7FBF36A9, (q31_t)0x080B86C1,
+ (q31_t)0x7FBC040A, (q31_t)0x083DB0A7, (q31_t)0x7FB8BDB7,
+ (q31_t)0x086FD947, (q31_t)0x7FB563B2, (q31_t)0x08A2009A,
+ (q31_t)0x7FB1F5FC, (q31_t)0x08D42698, (q31_t)0x7FAE7494,
+ (q31_t)0x09064B3A, (q31_t)0x7FAADF7C, (q31_t)0x09386E77,
+ (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7FA37A3C,
+ (q31_t)0x099CB0A7, (q31_t)0x7F9FAA15, (q31_t)0x09CECF89,
+ (q31_t)0x7F9BC63F, (q31_t)0x0A00ECE8, (q31_t)0x7F97CEBC,
+ (q31_t)0x0A3308BC, (q31_t)0x7F93C38C, (q31_t)0x0A6522FE,
+ (q31_t)0x7F8FA4AF, (q31_t)0x0A973BA5, (q31_t)0x7F8B7226,
+ (q31_t)0x0AC952AA, (q31_t)0x7F872BF3, (q31_t)0x0AFB6805,
+ (q31_t)0x7F82D214, (q31_t)0x0B2D7BAE, (q31_t)0x7F7E648B,
+ (q31_t)0x0B5F8D9F, (q31_t)0x7F79E35A, (q31_t)0x0B919DCE,
+ (q31_t)0x7F754E7F, (q31_t)0x0BC3AC35, (q31_t)0x7F70A5FD,
+ (q31_t)0x0BF5B8CB, (q31_t)0x7F6BE9D4, (q31_t)0x0C27C389,
+ (q31_t)0x7F671A04, (q31_t)0x0C59CC67, (q31_t)0x7F62368F,
+ (q31_t)0x0C8BD35E, (q31_t)0x7F5D3F75, (q31_t)0x0CBDD865,
+ (q31_t)0x7F5834B6, (q31_t)0x0CEFDB75, (q31_t)0x7F531654,
+ (q31_t)0x0D21DC87, (q31_t)0x7F4DE450, (q31_t)0x0D53DB92,
+ (q31_t)0x7F489EAA, (q31_t)0x0D85D88F, (q31_t)0x7F434563,
+ (q31_t)0x0DB7D376, (q31_t)0x7F3DD87C, (q31_t)0x0DE9CC3F,
+ (q31_t)0x7F3857F5, (q31_t)0x0E1BC2E3, (q31_t)0x7F32C3D0,
+ (q31_t)0x0E4DB75B, (q31_t)0x7F2D1C0E, (q31_t)0x0E7FA99D,
+ (q31_t)0x7F2760AF, (q31_t)0x0EB199A3, (q31_t)0x7F2191B4,
+ (q31_t)0x0EE38765, (q31_t)0x7F1BAF1E, (q31_t)0x0F1572DC,
+ (q31_t)0x7F15B8EE, (q31_t)0x0F475BFE, (q31_t)0x7F0FAF24,
+ (q31_t)0x0F7942C6, (q31_t)0x7F0991C3, (q31_t)0x0FAB272B,
+ (q31_t)0x7F0360CB, (q31_t)0x0FDD0925, (q31_t)0x7EFD1C3C,
+ (q31_t)0x100EE8AD, (q31_t)0x7EF6C418, (q31_t)0x1040C5BB,
+ (q31_t)0x7EF0585F, (q31_t)0x1072A047, (q31_t)0x7EE9D913,
+ (q31_t)0x10A4784A, (q31_t)0x7EE34635, (q31_t)0x10D64DBC,
+ (q31_t)0x7EDC9FC6, (q31_t)0x11082096, (q31_t)0x7ED5E5C6,
+ (q31_t)0x1139F0CE, (q31_t)0x7ECF1837, (q31_t)0x116BBE5F,
+ (q31_t)0x7EC8371A, (q31_t)0x119D8940, (q31_t)0x7EC1426F,
+ (q31_t)0x11CF516A, (q31_t)0x7EBA3A39, (q31_t)0x120116D4,
+ (q31_t)0x7EB31E77, (q31_t)0x1232D978, (q31_t)0x7EABEF2C,
+ (q31_t)0x1264994E, (q31_t)0x7EA4AC58, (q31_t)0x1296564D,
+ (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E95EC19,
+ (q31_t)0x12F9C7AA, (q31_t)0x7E8E6EB1, (q31_t)0x132B7BF9,
+ (q31_t)0x7E86DDC5, (q31_t)0x135D2D53, (q31_t)0x7E7F3956,
+ (q31_t)0x138EDBB0, (q31_t)0x7E778165, (q31_t)0x13C0870A,
+ (q31_t)0x7E6FB5F3, (q31_t)0x13F22F57, (q31_t)0x7E67D702,
+ (q31_t)0x1423D492, (q31_t)0x7E5FE493, (q31_t)0x145576B1,
+ (q31_t)0x7E57DEA6, (q31_t)0x148715AD, (q31_t)0x7E4FC53E,
+ (q31_t)0x14B8B17F, (q31_t)0x7E47985B, (q31_t)0x14EA4A1F,
+ (q31_t)0x7E3F57FE, (q31_t)0x151BDF85, (q31_t)0x7E37042A,
+ (q31_t)0x154D71AA, (q31_t)0x7E2E9CDF, (q31_t)0x157F0086,
+ (q31_t)0x7E26221E, (q31_t)0x15B08C11, (q31_t)0x7E1D93E9,
+ (q31_t)0x15E21444, (q31_t)0x7E14F242, (q31_t)0x16139917,
+ (q31_t)0x7E0C3D29, (q31_t)0x16451A83, (q31_t)0x7E03749F,
+ (q31_t)0x1676987F, (q31_t)0x7DFA98A7, (q31_t)0x16A81305,
+ (q31_t)0x7DF1A942, (q31_t)0x16D98A0C, (q31_t)0x7DE8A670,
+ (q31_t)0x170AFD8D, (q31_t)0x7DDF9034, (q31_t)0x173C6D80,
+ (q31_t)0x7DD6668E, (q31_t)0x176DD9DE, (q31_t)0x7DCD2981,
+ (q31_t)0x179F429F, (q31_t)0x7DC3D90D, (q31_t)0x17D0A7BB,
+ (q31_t)0x7DBA7534, (q31_t)0x1802092C, (q31_t)0x7DB0FDF7,
+ (q31_t)0x183366E8, (q31_t)0x7DA77359, (q31_t)0x1864C0E9,
+ (q31_t)0x7D9DD55A, (q31_t)0x18961727, (q31_t)0x7D9423FB,
+ (q31_t)0x18C7699B, (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C,
+ (q31_t)0x7D808727, (q31_t)0x192A0303, (q31_t)0x7D769BB5,
+ (q31_t)0x195B49E9, (q31_t)0x7D6C9CE9, (q31_t)0x198C8CE6,
+ (q31_t)0x7D628AC5, (q31_t)0x19BDCBF2, (q31_t)0x7D58654C,
+ (q31_t)0x19EF0706, (q31_t)0x7D4E2C7E, (q31_t)0x1A203E1B,
+ (q31_t)0x7D43E05E, (q31_t)0x1A517127, (q31_t)0x7D3980EC,
+ (q31_t)0x1A82A025, (q31_t)0x7D2F0E2A, (q31_t)0x1AB3CB0C,
+ (q31_t)0x7D24881A, (q31_t)0x1AE4F1D6, (q31_t)0x7D19EEBE,
+ (q31_t)0x1B161479, (q31_t)0x7D0F4218, (q31_t)0x1B4732EF,
+ (q31_t)0x7D048228, (q31_t)0x1B784D30, (q31_t)0x7CF9AEF0,
+ (q31_t)0x1BA96334, (q31_t)0x7CEEC873, (q31_t)0x1BDA74F5,
+ (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7CD8C1AD,
+ (q31_t)0x1C3C8B8C, (q31_t)0x7CCDA168, (q31_t)0x1C6D9053,
+ (q31_t)0x7CC26DE5, (q31_t)0x1C9E90B8, (q31_t)0x7CB72724,
+ (q31_t)0x1CCF8CB3, (q31_t)0x7CABCD27, (q31_t)0x1D00843C,
+ (q31_t)0x7CA05FF1, (q31_t)0x1D31774D, (q31_t)0x7C94DF82,
+ (q31_t)0x1D6265DD, (q31_t)0x7C894BDD, (q31_t)0x1D934FE5,
+ (q31_t)0x7C7DA504, (q31_t)0x1DC4355D, (q31_t)0x7C71EAF8,
+ (q31_t)0x1DF5163F, (q31_t)0x7C661DBB, (q31_t)0x1E25F281,
+ (q31_t)0x7C5A3D4F, (q31_t)0x1E56CA1E, (q31_t)0x7C4E49B6,
+ (q31_t)0x1E879D0C, (q31_t)0x7C4242F2, (q31_t)0x1EB86B46,
+ (q31_t)0x7C362904, (q31_t)0x1EE934C2, (q31_t)0x7C29FBEE,
+ (q31_t)0x1F19F97B, (q31_t)0x7C1DBBB2, (q31_t)0x1F4AB967,
+ (q31_t)0x7C116853, (q31_t)0x1F7B7480, (q31_t)0x7C0501D1,
+ (q31_t)0x1FAC2ABF, (q31_t)0x7BF88830, (q31_t)0x1FDCDC1A,
+ (q31_t)0x7BEBFB70, (q31_t)0x200D888C, (q31_t)0x7BDF5B94,
+ (q31_t)0x203E300D, (q31_t)0x7BD2A89E, (q31_t)0x206ED295,
+ (q31_t)0x7BC5E28F, (q31_t)0x209F701C, (q31_t)0x7BB9096A,
+ (q31_t)0x20D0089B, (q31_t)0x7BAC1D31, (q31_t)0x21009C0B,
+ (q31_t)0x7B9F1DE5, (q31_t)0x21312A65, (q31_t)0x7B920B89,
+ (q31_t)0x2161B39F, (q31_t)0x7B84E61E, (q31_t)0x219237B4,
+ (q31_t)0x7B77ADA8, (q31_t)0x21C2B69C, (q31_t)0x7B6A6227,
+ (q31_t)0x21F3304E, (q31_t)0x7B5D039D, (q31_t)0x2223A4C5,
+ (q31_t)0x7B4F920E, (q31_t)0x225413F8, (q31_t)0x7B420D7A,
+ (q31_t)0x22847DDF, (q31_t)0x7B3475E4, (q31_t)0x22B4E274,
+ (q31_t)0x7B26CB4F, (q31_t)0x22E541AE, (q31_t)0x7B190DBB,
+ (q31_t)0x23159B87, (q31_t)0x7B0B3D2C, (q31_t)0x2345EFF7,
+ (q31_t)0x7AFD59A3, (q31_t)0x23763EF7, (q31_t)0x7AEF6323,
+ (q31_t)0x23A6887E, (q31_t)0x7AE159AE, (q31_t)0x23D6CC86,
+ (q31_t)0x7AD33D45, (q31_t)0x24070B07, (q31_t)0x7AC50DEB,
+ (q31_t)0x243743FA, (q31_t)0x7AB6CBA3, (q31_t)0x24677757,
+ (q31_t)0x7AA8766E, (q31_t)0x2497A517, (q31_t)0x7A9A0E4F,
+ (q31_t)0x24C7CD32, (q31_t)0x7A8B9348, (q31_t)0x24F7EFA1,
+ (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7A6E648A,
+ (q31_t)0x2558235E, (q31_t)0x7A5FB0D8, (q31_t)0x2588349D,
+ (q31_t)0x7A50EA46, (q31_t)0x25B84012, (q31_t)0x7A4210D8,
+ (q31_t)0x25E845B5, (q31_t)0x7A33248F, (q31_t)0x26184581,
+ (q31_t)0x7A24256E, (q31_t)0x26483F6C, (q31_t)0x7A151377,
+ (q31_t)0x26783370, (q31_t)0x7A05EEAD, (q31_t)0x26A82185,
+ (q31_t)0x79F6B711, (q31_t)0x26D809A5, (q31_t)0x79E76CA6,
+ (q31_t)0x2707EBC6, (q31_t)0x79D80F6F, (q31_t)0x2737C7E3,
+ (q31_t)0x79C89F6D, (q31_t)0x27679DF4, (q31_t)0x79B91CA4,
+ (q31_t)0x27976DF1, (q31_t)0x79A98715, (q31_t)0x27C737D2,
+ (q31_t)0x7999DEC3, (q31_t)0x27F6FB92, (q31_t)0x798A23B1,
+ (q31_t)0x2826B928, (q31_t)0x797A55E0, (q31_t)0x2856708C,
+ (q31_t)0x796A7554, (q31_t)0x288621B9, (q31_t)0x795A820E,
+ (q31_t)0x28B5CCA5, (q31_t)0x794A7C11, (q31_t)0x28E5714A,
+ (q31_t)0x793A6360, (q31_t)0x29150FA1, (q31_t)0x792A37FE,
+ (q31_t)0x2944A7A2, (q31_t)0x7919F9EB, (q31_t)0x29743945,
+ (q31_t)0x7909A92C, (q31_t)0x29A3C484, (q31_t)0x78F945C3,
+ (q31_t)0x29D34958, (q31_t)0x78E8CFB1, (q31_t)0x2A02C7B8,
+ (q31_t)0x78D846FB, (q31_t)0x2A323F9D, (q31_t)0x78C7ABA1,
+ (q31_t)0x2A61B101, (q31_t)0x78B6FDA8, (q31_t)0x2A911BDB,
+ (q31_t)0x78A63D10, (q31_t)0x2AC08025, (q31_t)0x789569DE,
+ (q31_t)0x2AEFDDD8, (q31_t)0x78848413, (q31_t)0x2B1F34EB,
+ (q31_t)0x78738BB3, (q31_t)0x2B4E8558, (q31_t)0x786280BF,
+ (q31_t)0x2B7DCF17, (q31_t)0x7851633B, (q31_t)0x2BAD1221,
+ (q31_t)0x78403328, (q31_t)0x2BDC4E6F, (q31_t)0x782EF08B,
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+ (q31_t)0x7FE9CBC0, (q31_t)0xFB17ABC2, (q31_t)0x7FE7E840,
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+ (q31_t)0xFA4EC820, (q31_t)0x7FDF9508, (q31_t)0xFA1C9156,
+ (q31_t)0x7FDD4EEC, (q31_t)0xF9EA5B75, (q31_t)0x7FDAF518,
+ (q31_t)0xF9B82683, (q31_t)0x7FD8878D, (q31_t)0xF985F28A,
+ (q31_t)0x7FD6064B, (q31_t)0xF953BF90, (q31_t)0x7FD37152,
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+ (q31_t)0x7FCE0C3E, (q31_t)0xF8BD2CEF, (q31_t)0x7FCB3C23,
+ (q31_t)0xF88AFE41, (q31_t)0x7FC85853, (q31_t)0xF858D0BA,
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+ (q31_t)0x7FBC040A, (q31_t)0xF79026B8, (q31_t)0x7FB8BDB7,
+ (q31_t)0xF75DFF65, (q31_t)0x7FB563B2, (q31_t)0xF72BD967,
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+ (q31_t)0x7FA736B4, (q31_t)0xF6634F58, (q31_t)0x7FA37A3C,
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+ (q31_t)0xF59ADD01, (q31_t)0x7F93C38C, (q31_t)0xF568C45A,
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+ (q31_t)0xF50497FA, (q31_t)0x7F872BF3, (q31_t)0xF4D28451,
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+ (q31_t)0xF46E6231, (q31_t)0x7F79E35A, (q31_t)0xF43C53CA,
+ (q31_t)0x7F754E7F, (q31_t)0xF40A4734, (q31_t)0x7F70A5FD,
+ (q31_t)0xF3D83C76, (q31_t)0x7F6BE9D4, (q31_t)0xF3A63398,
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+ (q31_t)0xF2AC246D, (q31_t)0x7F4DE450, (q31_t)0xF27A2770,
+ (q31_t)0x7F489EAA, (q31_t)0xF2482C89, (q31_t)0x7F434563,
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+ (q31_t)0x7F3857F5, (q31_t)0xF1B248A5, (q31_t)0x7F32C3D0,
+ (q31_t)0xF1805662, (q31_t)0x7F2D1C0E, (q31_t)0xF14E665C,
+ (q31_t)0x7F2760AF, (q31_t)0xF11C789A, (q31_t)0x7F2191B4,
+ (q31_t)0xF0EA8D23, (q31_t)0x7F1BAF1E, (q31_t)0xF0B8A401,
+ (q31_t)0x7F15B8EE, (q31_t)0xF086BD39, (q31_t)0x7F0FAF24,
+ (q31_t)0xF054D8D4, (q31_t)0x7F0991C3, (q31_t)0xF022F6DA,
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+ (q31_t)0x7EF0585F, (q31_t)0xEF5B87B5, (q31_t)0x7EE9D913,
+ (q31_t)0xEF29B243, (q31_t)0x7EE34635, (q31_t)0xEEF7DF6A,
+ (q31_t)0x7EDC9FC6, (q31_t)0xEEC60F31, (q31_t)0x7ED5E5C6,
+ (q31_t)0xEE9441A0, (q31_t)0x7ECF1837, (q31_t)0xEE6276BF,
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+ (q31_t)0xED69A9B2, (q31_t)0x7EA4AC58, (q31_t)0xED37EF91,
+ (q31_t)0x7E9D55FC, (q31_t)0xED063855, (q31_t)0x7E95EC19,
+ (q31_t)0xECD48406, (q31_t)0x7E8E6EB1, (q31_t)0xECA2D2AC,
+ (q31_t)0x7E86DDC5, (q31_t)0xEC71244F, (q31_t)0x7E7F3956,
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+ (q31_t)0xEBAA894E, (q31_t)0x7E5FE493, (q31_t)0xEB78EA52,
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+ (q31_t)0xEB15B5E0, (q31_t)0x7E47985B, (q31_t)0xEAE4207A,
+ (q31_t)0x7E3F57FE, (q31_t)0xEAB28E55, (q31_t)0x7E37042A,
+ (q31_t)0xEA80FF79, (q31_t)0x7E2E9CDF, (q31_t)0xEA4F73EE,
+ (q31_t)0x7E26221E, (q31_t)0xEA1DEBBB, (q31_t)0x7E1D93E9,
+ (q31_t)0xE9EC66E8, (q31_t)0x7E14F242, (q31_t)0xE9BAE57C,
+ (q31_t)0x7E0C3D29, (q31_t)0xE9896780, (q31_t)0x7E03749F,
+ (q31_t)0xE957ECFB, (q31_t)0x7DFA98A7, (q31_t)0xE92675F4,
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+ (q31_t)0x7DBA7534, (q31_t)0xE7CC9917, (q31_t)0x7DB0FDF7,
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+ (q31_t)0xE5DFC1E4, (q31_t)0x7D4E2C7E, (q31_t)0xE5AE8ED8,
+ (q31_t)0x7D43E05E, (q31_t)0xE57D5FDA, (q31_t)0x7D3980EC,
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+ (q31_t)0xE3926FAC, (q31_t)0x7CCDA168, (q31_t)0xE3616F47,
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+ (q31_t)0xE26CB01A, (q31_t)0x7C894BDD, (q31_t)0xE23BCAA2,
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+ (q31_t)0x768E0EA5, (q31_t)0xCF8FADE8, (q31_t)0x767B1230,
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+ (q31_t)0x75A585CF, (q31_t)0xCD637BFD, (q31_t)0x7591AEDD,
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+ (q31_t)0xCCAB0D65, (q31_t)0x75419DE6, (q31_t)0xCC7D0577,
+ (q31_t)0x752D6C6C, (q31_t)0xCC4F057B, (q31_t)0x751928E0,
+ (q31_t)0xCC210D78, (q31_t)0x7504D345, (q31_t)0xCBF31D75,
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+ (q31_t)0xCB975589, (q31_t)0x74C7663A, (q31_t)0xCB697DB0,
+ (q31_t)0x74B2C883, (q31_t)0xCB3BADF2, (q31_t)0x749E18CD,
+ (q31_t)0xCB0DE658, (q31_t)0x7489571B, (q31_t)0xCAE026E8,
+ (q31_t)0x74748371, (q31_t)0xCAB26FA9, (q31_t)0x745F9DD1,
+ (q31_t)0xCA84C0A2, (q31_t)0x744AA63E, (q31_t)0xCA5719DB,
+ (q31_t)0x74359CBD, (q31_t)0xCA297B5A, (q31_t)0x74208150,
+ (q31_t)0xC9FBE527, (q31_t)0x740B53FA, (q31_t)0xC9CE5748,
+ (q31_t)0x73F614C0, (q31_t)0xC9A0D1C4, (q31_t)0x73E0C3A3,
+ (q31_t)0xC97354A3, (q31_t)0x73CB60A7, (q31_t)0xC945DFEC,
+ (q31_t)0x73B5EBD0, (q31_t)0xC91873A5, (q31_t)0x73A06522,
+ (q31_t)0xC8EB0FD6, (q31_t)0x738ACC9E, (q31_t)0xC8BDB485,
+ (q31_t)0x73752249, (q31_t)0xC89061BA, (q31_t)0x735F6626,
+ (q31_t)0xC863177B, (q31_t)0x73499838, (q31_t)0xC835D5D0,
+ (q31_t)0x7333B883, (q31_t)0xC8089CBF, (q31_t)0x731DC709,
+ (q31_t)0xC7DB6C50, (q31_t)0x7307C3D0, (q31_t)0xC7AE4489,
+ (q31_t)0x72F1AED8, (q31_t)0xC7812571, (q31_t)0x72DB8828,
+ (q31_t)0xC7540F10, (q31_t)0x72C54FC0, (q31_t)0xC727016C,
+ (q31_t)0x72AF05A6, (q31_t)0xC6F9FC8D, (q31_t)0x7298A9DC,
+ (q31_t)0xC6CD0079, (q31_t)0x72823C66, (q31_t)0xC6A00D36,
+ (q31_t)0x726BBD48, (q31_t)0xC67322CD, (q31_t)0x72552C84,
+ (q31_t)0xC6464144, (q31_t)0x723E8A1F, (q31_t)0xC61968A2,
+ (q31_t)0x7227D61C, (q31_t)0xC5EC98ED, (q31_t)0x7211107D,
+ (q31_t)0xC5BFD22E, (q31_t)0x71FA3948, (q31_t)0xC593146A,
+ (q31_t)0x71E3507F, (q31_t)0xC5665FA8, (q31_t)0x71CC5626,
+ (q31_t)0xC539B3F0, (q31_t)0x71B54A40, (q31_t)0xC50D1148,
+ (q31_t)0x719E2CD2, (q31_t)0xC4E077B8, (q31_t)0x7186FDDE,
+ (q31_t)0xC4B3E746, (q31_t)0x716FBD68, (q31_t)0xC4875FF8,
+ (q31_t)0x71586B73, (q31_t)0xC45AE1D7, (q31_t)0x71410804,
+ (q31_t)0xC42E6CE8, (q31_t)0x7129931E, (q31_t)0xC4020132,
+ (q31_t)0x71120CC5, (q31_t)0xC3D59EBD, (q31_t)0x70FA74FB,
+ (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xC37CF5B0,
+ (q31_t)0x70CB1127, (q31_t)0xC350AF25, (q31_t)0x70B34524,
+ (q31_t)0xC32471F6, (q31_t)0x709B67C0, (q31_t)0xC2F83E2A,
+ (q31_t)0x708378FE, (q31_t)0xC2CC13C7, (q31_t)0x706B78E3,
+ (q31_t)0xC29FF2D4, (q31_t)0x70536771, (q31_t)0xC273DB58,
+ (q31_t)0x703B44AC, (q31_t)0xC247CD5A, (q31_t)0x70231099,
+ (q31_t)0xC21BC8E0, (q31_t)0x700ACB3B, (q31_t)0xC1EFCDF2,
+ (q31_t)0x6FF27496, (q31_t)0xC1C3DC96, (q31_t)0x6FDA0CAD,
+ (q31_t)0xC197F4D3, (q31_t)0x6FC19385, (q31_t)0xC16C16B0,
+ (q31_t)0x6FA90920, (q31_t)0xC1404233, (q31_t)0x6F906D84,
+ (q31_t)0xC1147763, (q31_t)0x6F77C0B3, (q31_t)0xC0E8B648,
+ (q31_t)0x6F5F02B1, (q31_t)0xC0BCFEE7, (q31_t)0x6F463383,
+ (q31_t)0xC0915147, (q31_t)0x6F2D532C, (q31_t)0xC065AD70,
+ (q31_t)0x6F1461AF, (q31_t)0xC03A1368, (q31_t)0x6EFB5F12,
+ (q31_t)0xC00E8335, (q31_t)0x6EE24B57, (q31_t)0xBFE2FCDF,
+ (q31_t)0x6EC92682, (q31_t)0xBFB7806C, (q31_t)0x6EAFF098,
+ (q31_t)0xBF8C0DE2, (q31_t)0x6E96A99C, (q31_t)0xBF60A54A,
+ (q31_t)0x6E7D5193, (q31_t)0xBF3546A8, (q31_t)0x6E63E87F,
+ (q31_t)0xBF09F204, (q31_t)0x6E4A6E65, (q31_t)0xBEDEA765,
+ (q31_t)0x6E30E349, (q31_t)0xBEB366D1, (q31_t)0x6E17472F,
+ (q31_t)0xBE88304F, (q31_t)0x6DFD9A1B, (q31_t)0xBE5D03E5,
+ (q31_t)0x6DE3DC11, (q31_t)0xBE31E19B, (q31_t)0x6DCA0D14,
+ (q31_t)0xBE06C977, (q31_t)0x6DB02D29, (q31_t)0xBDDBBB7F,
+ (q31_t)0x6D963C54, (q31_t)0xBDB0B7BA, (q31_t)0x6D7C3A98,
+ (q31_t)0xBD85BE2F, (q31_t)0x6D6227FA, (q31_t)0xBD5ACEE5,
+ (q31_t)0x6D48047E, (q31_t)0xBD2FE9E1, (q31_t)0x6D2DD027,
+ (q31_t)0xBD050F2C, (q31_t)0x6D138AFA, (q31_t)0xBCDA3ECA,
+ (q31_t)0x6CF934FB, (q31_t)0xBCAF78C3, (q31_t)0x6CDECE2E,
+ (q31_t)0xBC84BD1E, (q31_t)0x6CC45697, (q31_t)0xBC5A0BE1,
+ (q31_t)0x6CA9CE3A, (q31_t)0xBC2F6513, (q31_t)0x6C8F351C,
+ (q31_t)0xBC04C8BA, (q31_t)0x6C748B3F, (q31_t)0xBBDA36DC,
+ (q31_t)0x6C59D0A9, (q31_t)0xBBAFAF81, (q31_t)0x6C3F055D,
+ (q31_t)0xBB8532AF, (q31_t)0x6C242960, (q31_t)0xBB5AC06C,
+ (q31_t)0x6C093CB6, (q31_t)0xBB3058C0, (q31_t)0x6BEE3F62,
+ (q31_t)0xBB05FBB0, (q31_t)0x6BD3316A, (q31_t)0xBADBA943,
+ (q31_t)0x6BB812D0, (q31_t)0xBAB1617F, (q31_t)0x6B9CE39B,
+ (q31_t)0xBA87246C, (q31_t)0x6B81A3CD, (q31_t)0xBA5CF210,
+ (q31_t)0x6B66536A, (q31_t)0xBA32CA70, (q31_t)0x6B4AF278,
+ (q31_t)0xBA08AD94, (q31_t)0x6B2F80FA, (q31_t)0xB9DE9B83,
+ (q31_t)0x6B13FEF5, (q31_t)0xB9B49442, (q31_t)0x6AF86C6C,
+ (q31_t)0xB98A97D8, (q31_t)0x6ADCC964, (q31_t)0xB960A64B,
+ (q31_t)0x6AC115E1, (q31_t)0xB936BFA3, (q31_t)0x6AA551E8,
+ (q31_t)0xB90CE3E6, (q31_t)0x6A897D7D, (q31_t)0xB8E31319,
+ (q31_t)0x6A6D98A4, (q31_t)0xB8B94D44, (q31_t)0x6A51A361,
+ (q31_t)0xB88F926C, (q31_t)0x6A359DB9, (q31_t)0xB865E299,
+ (q31_t)0x6A1987B0, (q31_t)0xB83C3DD1, (q31_t)0x69FD614A,
+ (q31_t)0xB812A419, (q31_t)0x69E12A8C, (q31_t)0xB7E9157A,
+ (q31_t)0x69C4E37A, (q31_t)0xB7BF91F8, (q31_t)0x69A88C18,
+ (q31_t)0xB796199B, (q31_t)0x698C246C, (q31_t)0xB76CAC68,
+ (q31_t)0x696FAC78, (q31_t)0xB7434A67, (q31_t)0x69532442,
+ (q31_t)0xB719F39D, (q31_t)0x69368BCE, (q31_t)0xB6F0A811,
+ (q31_t)0x6919E320, (q31_t)0xB6C767CA, (q31_t)0x68FD2A3D,
+ (q31_t)0xB69E32CD, (q31_t)0x68E06129, (q31_t)0xB6750921,
+ (q31_t)0x68C387E9, (q31_t)0xB64BEACC, (q31_t)0x68A69E81,
+ (q31_t)0xB622D7D5, (q31_t)0x6889A4F5, (q31_t)0xB5F9D042,
+ (q31_t)0x686C9B4B, (q31_t)0xB5D0D41A, (q31_t)0x684F8186,
+ (q31_t)0xB5A7E362, (q31_t)0x683257AA, (q31_t)0xB57EFE21,
+ (q31_t)0x68151DBE, (q31_t)0xB556245E, (q31_t)0x67F7D3C4,
+ (q31_t)0xB52D561E, (q31_t)0x67DA79C2, (q31_t)0xB5049368,
+ (q31_t)0x67BD0FBC, (q31_t)0xB4DBDC42, (q31_t)0x679F95B7,
+ (q31_t)0xB4B330B2, (q31_t)0x67820BB6, (q31_t)0xB48A90C0,
+ (q31_t)0x676471C0, (q31_t)0xB461FC70, (q31_t)0x6746C7D7,
+ (q31_t)0xB43973C9, (q31_t)0x67290E02, (q31_t)0xB410F6D2,
+ (q31_t)0x670B4443, (q31_t)0xB3E88591, (q31_t)0x66ED6AA1,
+ (q31_t)0xB3C0200C, (q31_t)0x66CF811F, (q31_t)0xB397C649,
+ (q31_t)0x66B187C3, (q31_t)0xB36F784E, (q31_t)0x66937E90,
+ (q31_t)0xB3473622, (q31_t)0x6675658C, (q31_t)0xB31EFFCB,
+ (q31_t)0x66573CBB, (q31_t)0xB2F6D54F, (q31_t)0x66390422,
+ (q31_t)0xB2CEB6B5, (q31_t)0x661ABBC5, (q31_t)0xB2A6A401,
+ (q31_t)0x65FC63A9, (q31_t)0xB27E9D3B, (q31_t)0x65DDFBD3,
+ (q31_t)0xB256A26A, (q31_t)0x65BF8447, (q31_t)0xB22EB392,
+ (q31_t)0x65A0FD0B, (q31_t)0xB206D0BA, (q31_t)0x65826622,
+ (q31_t)0xB1DEF9E8, (q31_t)0x6563BF92, (q31_t)0xB1B72F23,
+ (q31_t)0x6545095F, (q31_t)0xB18F7070, (q31_t)0x6526438E,
+ (q31_t)0xB167BDD6, (q31_t)0x65076E24, (q31_t)0xB140175B,
+ (q31_t)0x64E88926, (q31_t)0xB1187D05, (q31_t)0x64C99498,
+ (q31_t)0xB0F0EEDA, (q31_t)0x64AA907F, (q31_t)0xB0C96CDF,
+ (q31_t)0x648B7CDF, (q31_t)0xB0A1F71C, (q31_t)0x646C59BF,
+ (q31_t)0xB07A8D97, (q31_t)0x644D2722, (q31_t)0xB0533055,
+ (q31_t)0x642DE50D, (q31_t)0xB02BDF5C, (q31_t)0x640E9385,
+ (q31_t)0xB0049AB2, (q31_t)0x63EF328F, (q31_t)0xAFDD625F,
+ (q31_t)0x63CFC230, (q31_t)0xAFB63667, (q31_t)0x63B0426D,
+ (q31_t)0xAF8F16D0, (q31_t)0x6390B34A, (q31_t)0xAF6803A1,
+ (q31_t)0x637114CC, (q31_t)0xAF40FCE0, (q31_t)0x635166F8,
+ (q31_t)0xAF1A0293, (q31_t)0x6331A9D4, (q31_t)0xAEF314BF,
+ (q31_t)0x6311DD63, (q31_t)0xAECC336B, (q31_t)0x62F201AC,
+ (q31_t)0xAEA55E9D, (q31_t)0x62D216B2, (q31_t)0xAE7E965B,
+ (q31_t)0x62B21C7B, (q31_t)0xAE57DAAA, (q31_t)0x6292130C,
+ (q31_t)0xAE312B91, (q31_t)0x6271FA69, (q31_t)0xAE0A8916,
+ (q31_t)0x6251D297, (q31_t)0xADE3F33E, (q31_t)0x62319B9D,
+ (q31_t)0xADBD6A10, (q31_t)0x6211557D, (q31_t)0xAD96ED91,
+ (q31_t)0x61F1003E, (q31_t)0xAD707DC8, (q31_t)0x61D09BE5,
+ (q31_t)0xAD4A1ABA, (q31_t)0x61B02876, (q31_t)0xAD23C46D,
+ (q31_t)0x618FA5F6, (q31_t)0xACFD7AE8, (q31_t)0x616F146B,
+ (q31_t)0xACD73E30, (q31_t)0x614E73D9, (q31_t)0xACB10E4A,
+ (q31_t)0x612DC446, (q31_t)0xAC8AEB3E, (q31_t)0x610D05B7,
+ (q31_t)0xAC64D510, (q31_t)0x60EC3830, (q31_t)0xAC3ECBC7,
+ (q31_t)0x60CB5BB6, (q31_t)0xAC18CF68, (q31_t)0x60AA704F,
+ (q31_t)0xABF2DFFA, (q31_t)0x60897600, (q31_t)0xABCCFD82,
+ (q31_t)0x60686CCE, (q31_t)0xABA72806, (q31_t)0x604754BE,
+ (q31_t)0xAB815F8C, (q31_t)0x60262DD5, (q31_t)0xAB5BA41A,
+ (q31_t)0x6004F818, (q31_t)0xAB35F5B5, (q31_t)0x5FE3B38D,
+ (q31_t)0xAB105464, (q31_t)0x5FC26038, (q31_t)0xAAEAC02B,
+ (q31_t)0x5FA0FE1E, (q31_t)0xAAC53912, (q31_t)0x5F7F8D46,
+ (q31_t)0xAA9FBF1D, (q31_t)0x5F5E0DB3, (q31_t)0xAA7A5253,
+ (q31_t)0x5F3C7F6B, (q31_t)0xAA54F2B9, (q31_t)0x5F1AE273,
+ (q31_t)0xAA2FA055, (q31_t)0x5EF936D1, (q31_t)0xAA0A5B2D,
+ (q31_t)0x5ED77C89, (q31_t)0xA9E52347, (q31_t)0x5EB5B3A1,
+ (q31_t)0xA9BFF8A8, (q31_t)0x5E93DC1F, (q31_t)0xA99ADB56,
+ (q31_t)0x5E71F606, (q31_t)0xA975CB56, (q31_t)0x5E50015D,
+ (q31_t)0xA950C8AF, (q31_t)0x5E2DFE28, (q31_t)0xA92BD366,
+ (q31_t)0x5E0BEC6E, (q31_t)0xA906EB81, (q31_t)0x5DE9CC32,
+ (q31_t)0xA8E21106, (q31_t)0x5DC79D7C, (q31_t)0xA8BD43FA,
+ (q31_t)0x5DA5604E, (q31_t)0xA8988463, (q31_t)0x5D8314B0,
+ (q31_t)0xA873D246, (q31_t)0x5D60BAA6, (q31_t)0xA84F2DA9,
+ (q31_t)0x5D3E5236, (q31_t)0xA82A9693, (q31_t)0x5D1BDB65,
+ (q31_t)0xA8060D08, (q31_t)0x5CF95638, (q31_t)0xA7E1910E,
+ (q31_t)0x5CD6C2B4, (q31_t)0xA7BD22AB, (q31_t)0x5CB420DF,
+ (q31_t)0xA798C1E4, (q31_t)0x5C9170BF, (q31_t)0xA7746EC0,
+ (q31_t)0x5C6EB258, (q31_t)0xA7502943, (q31_t)0x5C4BE5B0,
+ (q31_t)0xA72BF173, (q31_t)0x5C290ACC, (q31_t)0xA707C756,
+ (q31_t)0x5C0621B2, (q31_t)0xA6E3AAF2, (q31_t)0x5BE32A67,
+ (q31_t)0xA6BF9C4B, (q31_t)0x5BC024F0, (q31_t)0xA69B9B68,
+ (q31_t)0x5B9D1153, (q31_t)0xA677A84E, (q31_t)0x5B79EF96,
+ (q31_t)0xA653C302, (q31_t)0x5B56BFBD, (q31_t)0xA62FEB8B,
+ (q31_t)0x5B3381CE, (q31_t)0xA60C21ED, (q31_t)0x5B1035CF,
+ (q31_t)0xA5E8662F, (q31_t)0x5AECDBC4, (q31_t)0xA5C4B855,
+ (q31_t)0x5AC973B4, (q31_t)0xA5A11865, (q31_t)0x5AA5FDA4,
+ (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0xA55A025B,
+ (q31_t)0x5A5EE79A, (q31_t)0xA5368C4B, (q31_t)0x5A3B47AA,
+ (q31_t)0xA513243B, (q31_t)0x5A1799D0, (q31_t)0xA4EFCA31,
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+ (q31_t)0xA4A94042, (q31_t)0x59AC3CFD, (q31_t)0xA4861069,
+ (q31_t)0x598857B1, (q31_t)0xA462EEAC, (q31_t)0x59646497,
+ (q31_t)0xA43FDB0F, (q31_t)0x594063B4, (q31_t)0xA41CD598,
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+ (q31_t)0xA3D6F533, (q31_t)0x58D40E8C, (q31_t)0xA3B41A4F,
+ (q31_t)0x58AFD6BC, (q31_t)0xA3914DA7, (q31_t)0x588B913F,
+ (q31_t)0xA36E8F40, (q31_t)0x58673E1B, (q31_t)0xA34BDF20,
+ (q31_t)0x5842DD54, (q31_t)0xA3293D4B, (q31_t)0x581E6EF1,
+ (q31_t)0xA306A9C7, (q31_t)0x57F9F2F7, (q31_t)0xA2E4249A,
+ (q31_t)0x57D5696C, (q31_t)0xA2C1ADC9, (q31_t)0x57B0D256,
+ (q31_t)0xA29F4559, (q31_t)0x578C2DB9, (q31_t)0xA27CEB4F,
+ (q31_t)0x57677B9D, (q31_t)0xA25A9FB1, (q31_t)0x5742BC05,
+ (q31_t)0xA2386283, (q31_t)0x571DEEF9, (q31_t)0xA21633CD,
+ (q31_t)0x56F9147E, (q31_t)0xA1F41391, (q31_t)0x56D42C99,
+ (q31_t)0xA1D201D7, (q31_t)0x56AF3750, (q31_t)0xA1AFFEA2,
+ (q31_t)0x568A34A9, (q31_t)0xA18E09F9, (q31_t)0x566524AA,
+ (q31_t)0xA16C23E1, (q31_t)0x56400757, (q31_t)0xA14A4C5E,
+ (q31_t)0x561ADCB8, (q31_t)0xA1288376, (q31_t)0x55F5A4D2,
+ (q31_t)0xA106C92E, (q31_t)0x55D05FAA, (q31_t)0xA0E51D8C,
+ (q31_t)0x55AB0D46, (q31_t)0xA0C38094, (q31_t)0x5585ADAC,
+ (q31_t)0xA0A1F24C, (q31_t)0x556040E2, (q31_t)0xA08072BA,
+ (q31_t)0x553AC6ED, (q31_t)0xA05F01E1, (q31_t)0x55153FD4,
+ (q31_t)0xA03D9FC7, (q31_t)0x54EFAB9C, (q31_t)0xA01C4C72,
+ (q31_t)0x54CA0A4A, (q31_t)0x9FFB07E7, (q31_t)0x54A45BE5,
+ (q31_t)0x9FD9D22A, (q31_t)0x547EA073, (q31_t)0x9FB8AB41,
+ (q31_t)0x5458D7F9, (q31_t)0x9F979331, (q31_t)0x5433027D,
+ (q31_t)0x9F7689FF, (q31_t)0x540D2005, (q31_t)0x9F558FB0,
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+ (q31_t)0x2558235E, (q31_t)0x8582FAA4, (q31_t)0x25280C5D,
+ (q31_t)0x85746CB7, (q31_t)0x24F7EFA1, (q31_t)0x8565F1B0,
+ (q31_t)0x24C7CD32, (q31_t)0x85578991, (q31_t)0x2497A517,
+ (q31_t)0x8549345C, (q31_t)0x24677757, (q31_t)0x853AF214,
+ (q31_t)0x243743FA, (q31_t)0x852CC2BA, (q31_t)0x24070B07,
+ (q31_t)0x851EA652, (q31_t)0x23D6CC86, (q31_t)0x85109CDC,
+ (q31_t)0x23A6887E, (q31_t)0x8502A65C, (q31_t)0x23763EF7,
+ (q31_t)0x84F4C2D3, (q31_t)0x2345EFF7, (q31_t)0x84E6F244,
+ (q31_t)0x23159B87, (q31_t)0x84D934B0, (q31_t)0x22E541AE,
+ (q31_t)0x84CB8A1B, (q31_t)0x22B4E274, (q31_t)0x84BDF285,
+ (q31_t)0x22847DDF, (q31_t)0x84B06DF1, (q31_t)0x225413F8,
+ (q31_t)0x84A2FC62, (q31_t)0x2223A4C5, (q31_t)0x84959DD9,
+ (q31_t)0x21F3304E, (q31_t)0x84885257, (q31_t)0x21C2B69C,
+ (q31_t)0x847B19E1, (q31_t)0x219237B4, (q31_t)0x846DF476,
+ (q31_t)0x2161B39F, (q31_t)0x8460E21A, (q31_t)0x21312A65,
+ (q31_t)0x8453E2CE, (q31_t)0x21009C0B, (q31_t)0x8446F695,
+ (q31_t)0x20D0089B, (q31_t)0x843A1D70, (q31_t)0x209F701C,
+ (q31_t)0x842D5761, (q31_t)0x206ED295, (q31_t)0x8420A46B,
+ (q31_t)0x203E300D, (q31_t)0x8414048F, (q31_t)0x200D888C,
+ (q31_t)0x840777CF, (q31_t)0x1FDCDC1A, (q31_t)0x83FAFE2E,
+ (q31_t)0x1FAC2ABF, (q31_t)0x83EE97AC, (q31_t)0x1F7B7480,
+ (q31_t)0x83E2444D, (q31_t)0x1F4AB967, (q31_t)0x83D60411,
+ (q31_t)0x1F19F97B, (q31_t)0x83C9D6FB, (q31_t)0x1EE934C2,
+ (q31_t)0x83BDBD0D, (q31_t)0x1EB86B46, (q31_t)0x83B1B649,
+ (q31_t)0x1E879D0C, (q31_t)0x83A5C2B0, (q31_t)0x1E56CA1E,
+ (q31_t)0x8399E244, (q31_t)0x1E25F281, (q31_t)0x838E1507,
+ (q31_t)0x1DF5163F, (q31_t)0x83825AFB, (q31_t)0x1DC4355D,
+ (q31_t)0x8376B422, (q31_t)0x1D934FE5, (q31_t)0x836B207D,
+ (q31_t)0x1D6265DD, (q31_t)0x835FA00E, (q31_t)0x1D31774D,
+ (q31_t)0x835432D8, (q31_t)0x1D00843C, (q31_t)0x8348D8DB,
+ (q31_t)0x1CCF8CB3, (q31_t)0x833D921A, (q31_t)0x1C9E90B8,
+ (q31_t)0x83325E97, (q31_t)0x1C6D9053, (q31_t)0x83273E52,
+ (q31_t)0x1C3C8B8C, (q31_t)0x831C314E, (q31_t)0x1C0B826A,
+ (q31_t)0x8311378C, (q31_t)0x1BDA74F5, (q31_t)0x8306510F,
+ (q31_t)0x1BA96334, (q31_t)0x82FB7DD8, (q31_t)0x1B784D30,
+ (q31_t)0x82F0BDE8, (q31_t)0x1B4732EF, (q31_t)0x82E61141,
+ (q31_t)0x1B161479, (q31_t)0x82DB77E5, (q31_t)0x1AE4F1D6,
+ (q31_t)0x82D0F1D5, (q31_t)0x1AB3CB0C, (q31_t)0x82C67F13,
+ (q31_t)0x1A82A025, (q31_t)0x82BC1FA1, (q31_t)0x1A517127,
+ (q31_t)0x82B1D381, (q31_t)0x1A203E1B, (q31_t)0x82A79AB3,
+ (q31_t)0x19EF0706, (q31_t)0x829D753A, (q31_t)0x19BDCBF2,
+ (q31_t)0x82936316, (q31_t)0x198C8CE6, (q31_t)0x8289644A,
+ (q31_t)0x195B49E9, (q31_t)0x827F78D8, (q31_t)0x192A0303,
+ (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x826BDC04,
+ (q31_t)0x18C7699B, (q31_t)0x82622AA5, (q31_t)0x18961727,
+ (q31_t)0x82588CA6, (q31_t)0x1864C0E9, (q31_t)0x824F0208,
+ (q31_t)0x183366E8, (q31_t)0x82458ACB, (q31_t)0x1802092C,
+ (q31_t)0x823C26F2, (q31_t)0x17D0A7BB, (q31_t)0x8232D67E,
+ (q31_t)0x179F429F, (q31_t)0x82299971, (q31_t)0x176DD9DE,
+ (q31_t)0x82206FCB, (q31_t)0x173C6D80, (q31_t)0x8217598F,
+ (q31_t)0x170AFD8D, (q31_t)0x820E56BE, (q31_t)0x16D98A0C,
+ (q31_t)0x82056758, (q31_t)0x16A81305, (q31_t)0x81FC8B60,
+ (q31_t)0x1676987F, (q31_t)0x81F3C2D7, (q31_t)0x16451A83,
+ (q31_t)0x81EB0DBD, (q31_t)0x16139917, (q31_t)0x81E26C16,
+ (q31_t)0x15E21444, (q31_t)0x81D9DDE1, (q31_t)0x15B08C11,
+ (q31_t)0x81D16320, (q31_t)0x157F0086, (q31_t)0x81C8FBD5,
+ (q31_t)0x154D71AA, (q31_t)0x81C0A801, (q31_t)0x151BDF85,
+ (q31_t)0x81B867A4, (q31_t)0x14EA4A1F, (q31_t)0x81B03AC1,
+ (q31_t)0x14B8B17F, (q31_t)0x81A82159, (q31_t)0x148715AD,
+ (q31_t)0x81A01B6C, (q31_t)0x145576B1, (q31_t)0x819828FD,
+ (q31_t)0x1423D492, (q31_t)0x81904A0C, (q31_t)0x13F22F57,
+ (q31_t)0x81887E9A, (q31_t)0x13C0870A, (q31_t)0x8180C6A9,
+ (q31_t)0x138EDBB0, (q31_t)0x8179223A, (q31_t)0x135D2D53,
+ (q31_t)0x8171914E, (q31_t)0x132B7BF9, (q31_t)0x816A13E6,
+ (q31_t)0x12F9C7AA, (q31_t)0x8162AA03, (q31_t)0x12C8106E,
+ (q31_t)0x815B53A8, (q31_t)0x1296564D, (q31_t)0x815410D3,
+ (q31_t)0x1264994E, (q31_t)0x814CE188, (q31_t)0x1232D978,
+ (q31_t)0x8145C5C6, (q31_t)0x120116D4, (q31_t)0x813EBD90,
+ (q31_t)0x11CF516A, (q31_t)0x8137C8E6, (q31_t)0x119D8940,
+ (q31_t)0x8130E7C8, (q31_t)0x116BBE5F, (q31_t)0x812A1A39,
+ (q31_t)0x1139F0CE, (q31_t)0x81236039, (q31_t)0x11082096,
+ (q31_t)0x811CB9CA, (q31_t)0x10D64DBC, (q31_t)0x811626EC,
+ (q31_t)0x10A4784A, (q31_t)0x810FA7A0, (q31_t)0x1072A047,
+ (q31_t)0x81093BE8, (q31_t)0x1040C5BB, (q31_t)0x8102E3C3,
+ (q31_t)0x100EE8AD, (q31_t)0x80FC9F35, (q31_t)0x0FDD0925,
+ (q31_t)0x80F66E3C, (q31_t)0x0FAB272B, (q31_t)0x80F050DB,
+ (q31_t)0x0F7942C6, (q31_t)0x80EA4712, (q31_t)0x0F475BFE,
+ (q31_t)0x80E450E2, (q31_t)0x0F1572DC, (q31_t)0x80DE6E4C,
+ (q31_t)0x0EE38765, (q31_t)0x80D89F51, (q31_t)0x0EB199A3,
+ (q31_t)0x80D2E3F1, (q31_t)0x0E7FA99D, (q31_t)0x80CD3C2F,
+ (q31_t)0x0E4DB75B, (q31_t)0x80C7A80A, (q31_t)0x0E1BC2E3,
+ (q31_t)0x80C22783, (q31_t)0x0DE9CC3F, (q31_t)0x80BCBA9C,
+ (q31_t)0x0DB7D376, (q31_t)0x80B76155, (q31_t)0x0D85D88F,
+ (q31_t)0x80B21BAF, (q31_t)0x0D53DB92, (q31_t)0x80ACE9AB,
+ (q31_t)0x0D21DC87, (q31_t)0x80A7CB49, (q31_t)0x0CEFDB75,
+ (q31_t)0x80A2C08B, (q31_t)0x0CBDD865, (q31_t)0x809DC970,
+ (q31_t)0x0C8BD35E, (q31_t)0x8098E5FB, (q31_t)0x0C59CC67,
+ (q31_t)0x8094162B, (q31_t)0x0C27C389, (q31_t)0x808F5A02,
+ (q31_t)0x0BF5B8CB, (q31_t)0x808AB180, (q31_t)0x0BC3AC35,
+ (q31_t)0x80861CA5, (q31_t)0x0B919DCE, (q31_t)0x80819B74,
+ (q31_t)0x0B5F8D9F, (q31_t)0x807D2DEB, (q31_t)0x0B2D7BAE,
+ (q31_t)0x8078D40D, (q31_t)0x0AFB6805, (q31_t)0x80748DD9,
+ (q31_t)0x0AC952AA, (q31_t)0x80705B50, (q31_t)0x0A973BA5,
+ (q31_t)0x806C3C73, (q31_t)0x0A6522FE, (q31_t)0x80683143,
+ (q31_t)0x0A3308BC, (q31_t)0x806439C0, (q31_t)0x0A00ECE8,
+ (q31_t)0x806055EA, (q31_t)0x09CECF89, (q31_t)0x805C85C3,
+ (q31_t)0x099CB0A7, (q31_t)0x8058C94C, (q31_t)0x096A9049,
+ (q31_t)0x80552083, (q31_t)0x09386E77, (q31_t)0x80518B6B,
+ (q31_t)0x09064B3A, (q31_t)0x804E0A03, (q31_t)0x08D42698,
+ (q31_t)0x804A9C4D, (q31_t)0x08A2009A, (q31_t)0x80474248,
+ (q31_t)0x086FD947, (q31_t)0x8043FBF6, (q31_t)0x083DB0A7,
+ (q31_t)0x8040C956, (q31_t)0x080B86C1, (q31_t)0x803DAA69,
+ (q31_t)0x07D95B9E, (q31_t)0x803A9F31, (q31_t)0x07A72F45,
+ (q31_t)0x8037A7AC, (q31_t)0x077501BE, (q31_t)0x8034C3DC,
+ (q31_t)0x0742D310, (q31_t)0x8031F3C1, (q31_t)0x0710A344,
+ (q31_t)0x802F375C, (q31_t)0x06DE7261, (q31_t)0x802C8EAD,
+ (q31_t)0x06AC406F, (q31_t)0x8029F9B4, (q31_t)0x067A0D75,
+ (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x80250AE7,
+ (q31_t)0x0615A48A, (q31_t)0x8022B113, (q31_t)0x05E36EA9,
+ (q31_t)0x80206AF8, (q31_t)0x05B137DF, (q31_t)0x801E3894,
+ (q31_t)0x057F0034, (q31_t)0x801C19E9, (q31_t)0x054CC7B0,
+ (q31_t)0x801A0EF7, (q31_t)0x051A8E5C, (q31_t)0x801817BF,
+ (q31_t)0x04E8543D, (q31_t)0x80163440, (q31_t)0x04B6195D,
+ (q31_t)0x8014647A, (q31_t)0x0483DDC3, (q31_t)0x8012A86F,
+ (q31_t)0x0451A176, (q31_t)0x8011001E, (q31_t)0x041F647F,
+ (q31_t)0x800F6B88, (q31_t)0x03ED26E6, (q31_t)0x800DEAAC,
+ (q31_t)0x03BAE8B1, (q31_t)0x800C7D8C, (q31_t)0x0388A9E9,
+ (q31_t)0x800B2427, (q31_t)0x03566A96, (q31_t)0x8009DE7D,
+ (q31_t)0x03242ABF, (q31_t)0x8008AC90, (q31_t)0x02F1EA6B,
+ (q31_t)0x80078E5E, (q31_t)0x02BFA9A4, (q31_t)0x800683E8,
+ (q31_t)0x028D6870, (q31_t)0x80058D2E, (q31_t)0x025B26D7,
+ (q31_t)0x8004AA31, (q31_t)0x0228E4E1, (q31_t)0x8003DAF0,
+ (q31_t)0x01F6A296, (q31_t)0x80031F6C, (q31_t)0x01C45FFE,
+ (q31_t)0x800277A5, (q31_t)0x01921D1F, (q31_t)0x8001E39B,
+ (q31_t)0x015FDA03, (q31_t)0x8001634D, (q31_t)0x012D96B0,
+ (q31_t)0x8000F6BD, (q31_t)0x00FB532F, (q31_t)0x80009DE9,
+ (q31_t)0x00C90F88, (q31_t)0x800058D3, (q31_t)0x0096CBC1,
+ (q31_t)0x8000277A, (q31_t)0x006487E3, (q31_t)0x800009DE,
+ (q31_t)0x003243F5, (q31_t)0x80000000, (q31_t)0x00000000,
+ (q31_t)0x800009DE, (q31_t)0xFFCDBC0A, (q31_t)0x8000277A,
+ (q31_t)0xFF9B781D, (q31_t)0x800058D3, (q31_t)0xFF69343E,
+ (q31_t)0x80009DE9, (q31_t)0xFF36F078, (q31_t)0x8000F6BD,
+ (q31_t)0xFF04ACD0, (q31_t)0x8001634D, (q31_t)0xFED2694F,
+ (q31_t)0x8001E39B, (q31_t)0xFEA025FC, (q31_t)0x800277A5,
+ (q31_t)0xFE6DE2E0, (q31_t)0x80031F6C, (q31_t)0xFE3BA001,
+ (q31_t)0x8003DAF0, (q31_t)0xFE095D69, (q31_t)0x8004AA31,
+ (q31_t)0xFDD71B1E, (q31_t)0x80058D2E, (q31_t)0xFDA4D928,
+ (q31_t)0x800683E8, (q31_t)0xFD72978F, (q31_t)0x80078E5E,
+ (q31_t)0xFD40565B, (q31_t)0x8008AC90, (q31_t)0xFD0E1594,
+ (q31_t)0x8009DE7D, (q31_t)0xFCDBD541, (q31_t)0x800B2427,
+ (q31_t)0xFCA99569, (q31_t)0x800C7D8C, (q31_t)0xFC775616,
+ (q31_t)0x800DEAAC, (q31_t)0xFC45174E, (q31_t)0x800F6B88,
+ (q31_t)0xFC12D919, (q31_t)0x8011001E, (q31_t)0xFBE09B80,
+ (q31_t)0x8012A86F, (q31_t)0xFBAE5E89, (q31_t)0x8014647A,
+ (q31_t)0xFB7C223C, (q31_t)0x80163440, (q31_t)0xFB49E6A2,
+ (q31_t)0x801817BF, (q31_t)0xFB17ABC2, (q31_t)0x801A0EF7,
+ (q31_t)0xFAE571A4, (q31_t)0x801C19E9, (q31_t)0xFAB3384F,
+ (q31_t)0x801E3894, (q31_t)0xFA80FFCB, (q31_t)0x80206AF8,
+ (q31_t)0xFA4EC820, (q31_t)0x8022B113, (q31_t)0xFA1C9156,
+ (q31_t)0x80250AE7, (q31_t)0xF9EA5B75, (q31_t)0x80277872,
+ (q31_t)0xF9B82683, (q31_t)0x8029F9B4, (q31_t)0xF985F28A,
+ (q31_t)0x802C8EAD, (q31_t)0xF953BF90, (q31_t)0x802F375C,
+ (q31_t)0xF9218D9E, (q31_t)0x8031F3C1, (q31_t)0xF8EF5CBB,
+ (q31_t)0x8034C3DC, (q31_t)0xF8BD2CEF, (q31_t)0x8037A7AC,
+ (q31_t)0xF88AFE41, (q31_t)0x803A9F31, (q31_t)0xF858D0BA,
+ (q31_t)0x803DAA69, (q31_t)0xF826A461, (q31_t)0x8040C956,
+ (q31_t)0xF7F4793E, (q31_t)0x8043FBF6, (q31_t)0xF7C24F58,
+ (q31_t)0x80474248, (q31_t)0xF79026B8, (q31_t)0x804A9C4D,
+ (q31_t)0xF75DFF65, (q31_t)0x804E0A03, (q31_t)0xF72BD967,
+ (q31_t)0x80518B6B, (q31_t)0xF6F9B4C5, (q31_t)0x80552083,
+ (q31_t)0xF6C79188, (q31_t)0x8058C94C, (q31_t)0xF6956FB6,
+ (q31_t)0x805C85C3, (q31_t)0xF6634F58, (q31_t)0x806055EA,
+ (q31_t)0xF6313076, (q31_t)0x806439C0, (q31_t)0xF5FF1317,
+ (q31_t)0x80683143, (q31_t)0xF5CCF743, (q31_t)0x806C3C73,
+ (q31_t)0xF59ADD01, (q31_t)0x80705B50, (q31_t)0xF568C45A,
+ (q31_t)0x80748DD9, (q31_t)0xF536AD55, (q31_t)0x8078D40D,
+ (q31_t)0xF50497FA, (q31_t)0x807D2DEB, (q31_t)0xF4D28451,
+ (q31_t)0x80819B74, (q31_t)0xF4A07260, (q31_t)0x80861CA5,
+ (q31_t)0xF46E6231, (q31_t)0x808AB180, (q31_t)0xF43C53CA,
+ (q31_t)0x808F5A02, (q31_t)0xF40A4734, (q31_t)0x8094162B,
+ (q31_t)0xF3D83C76, (q31_t)0x8098E5FB, (q31_t)0xF3A63398,
+ (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x80A2C08B,
+ (q31_t)0xF342279A, (q31_t)0x80A7CB49, (q31_t)0xF310248A,
+ (q31_t)0x80ACE9AB, (q31_t)0xF2DE2378, (q31_t)0x80B21BAF,
+ (q31_t)0xF2AC246D, (q31_t)0x80B76155, (q31_t)0xF27A2770,
+ (q31_t)0x80BCBA9C, (q31_t)0xF2482C89, (q31_t)0x80C22783,
+ (q31_t)0xF21633C0, (q31_t)0x80C7A80A, (q31_t)0xF1E43D1C,
+ (q31_t)0x80CD3C2F, (q31_t)0xF1B248A5, (q31_t)0x80D2E3F1,
+ (q31_t)0xF1805662, (q31_t)0x80D89F51, (q31_t)0xF14E665C,
+ (q31_t)0x80DE6E4C, (q31_t)0xF11C789A, (q31_t)0x80E450E2,
+ (q31_t)0xF0EA8D23, (q31_t)0x80EA4712, (q31_t)0xF0B8A401,
+ (q31_t)0x80F050DB, (q31_t)0xF086BD39, (q31_t)0x80F66E3C,
+ (q31_t)0xF054D8D4, (q31_t)0x80FC9F35, (q31_t)0xF022F6DA,
+ (q31_t)0x8102E3C3, (q31_t)0xEFF11752, (q31_t)0x81093BE8,
+ (q31_t)0xEFBF3A44, (q31_t)0x810FA7A0, (q31_t)0xEF8D5FB8,
+ (q31_t)0x811626EC, (q31_t)0xEF5B87B5, (q31_t)0x811CB9CA,
+ (q31_t)0xEF29B243, (q31_t)0x81236039, (q31_t)0xEEF7DF6A,
+ (q31_t)0x812A1A39, (q31_t)0xEEC60F31, (q31_t)0x8130E7C8,
+ (q31_t)0xEE9441A0, (q31_t)0x8137C8E6, (q31_t)0xEE6276BF,
+ (q31_t)0x813EBD90, (q31_t)0xEE30AE95, (q31_t)0x8145C5C6,
+ (q31_t)0xEDFEE92B, (q31_t)0x814CE188, (q31_t)0xEDCD2687,
+ (q31_t)0x815410D3, (q31_t)0xED9B66B2, (q31_t)0x815B53A8,
+ (q31_t)0xED69A9B2, (q31_t)0x8162AA03, (q31_t)0xED37EF91,
+ (q31_t)0x816A13E6, (q31_t)0xED063855, (q31_t)0x8171914E,
+ (q31_t)0xECD48406, (q31_t)0x8179223A, (q31_t)0xECA2D2AC,
+ (q31_t)0x8180C6A9, (q31_t)0xEC71244F, (q31_t)0x81887E9A,
+ (q31_t)0xEC3F78F5, (q31_t)0x81904A0C, (q31_t)0xEC0DD0A8,
+ (q31_t)0x819828FD, (q31_t)0xEBDC2B6D, (q31_t)0x81A01B6C,
+ (q31_t)0xEBAA894E, (q31_t)0x81A82159, (q31_t)0xEB78EA52,
+ (q31_t)0x81B03AC1, (q31_t)0xEB474E80, (q31_t)0x81B867A4,
+ (q31_t)0xEB15B5E0, (q31_t)0x81C0A801, (q31_t)0xEAE4207A,
+ (q31_t)0x81C8FBD5, (q31_t)0xEAB28E55, (q31_t)0x81D16320,
+ (q31_t)0xEA80FF79, (q31_t)0x81D9DDE1, (q31_t)0xEA4F73EE,
+ (q31_t)0x81E26C16, (q31_t)0xEA1DEBBB, (q31_t)0x81EB0DBD,
+ (q31_t)0xE9EC66E8, (q31_t)0x81F3C2D7, (q31_t)0xE9BAE57C,
+ (q31_t)0x81FC8B60, (q31_t)0xE9896780, (q31_t)0x82056758,
+ (q31_t)0xE957ECFB, (q31_t)0x820E56BE, (q31_t)0xE92675F4,
+ (q31_t)0x8217598F, (q31_t)0xE8F50273, (q31_t)0x82206FCB,
+ (q31_t)0xE8C3927F, (q31_t)0x82299971, (q31_t)0xE8922621,
+ (q31_t)0x8232D67E, (q31_t)0xE860BD60, (q31_t)0x823C26F2,
+ (q31_t)0xE82F5844, (q31_t)0x82458ACB, (q31_t)0xE7FDF6D3,
+ (q31_t)0x824F0208, (q31_t)0xE7CC9917, (q31_t)0x82588CA6,
+ (q31_t)0xE79B3F16, (q31_t)0x82622AA5, (q31_t)0xE769E8D8,
+ (q31_t)0x826BDC04, (q31_t)0xE7389664, (q31_t)0x8275A0C0,
+ (q31_t)0xE70747C3, (q31_t)0x827F78D8, (q31_t)0xE6D5FCFC,
+ (q31_t)0x8289644A, (q31_t)0xE6A4B616, (q31_t)0x82936316,
+ (q31_t)0xE6737319, (q31_t)0x829D753A, (q31_t)0xE642340D,
+ (q31_t)0x82A79AB3, (q31_t)0xE610F8F9, (q31_t)0x82B1D381,
+ (q31_t)0xE5DFC1E4, (q31_t)0x82BC1FA1, (q31_t)0xE5AE8ED8,
+ (q31_t)0x82C67F13, (q31_t)0xE57D5FDA, (q31_t)0x82D0F1D5,
+ (q31_t)0xE54C34F3, (q31_t)0x82DB77E5, (q31_t)0xE51B0E2A,
+ (q31_t)0x82E61141, (q31_t)0xE4E9EB86, (q31_t)0x82F0BDE8,
+ (q31_t)0xE4B8CD10, (q31_t)0x82FB7DD8, (q31_t)0xE487B2CF,
+ (q31_t)0x8306510F, (q31_t)0xE4569CCB, (q31_t)0x8311378C,
+ (q31_t)0xE4258B0A, (q31_t)0x831C314E, (q31_t)0xE3F47D95,
+ (q31_t)0x83273E52, (q31_t)0xE3C37473, (q31_t)0x83325E97,
+ (q31_t)0xE3926FAC, (q31_t)0x833D921A, (q31_t)0xE3616F47,
+ (q31_t)0x8348D8DB, (q31_t)0xE330734C, (q31_t)0x835432D8,
+ (q31_t)0xE2FF7BC3, (q31_t)0x835FA00E, (q31_t)0xE2CE88B2,
+ (q31_t)0x836B207D, (q31_t)0xE29D9A22, (q31_t)0x8376B422,
+ (q31_t)0xE26CB01A, (q31_t)0x83825AFB, (q31_t)0xE23BCAA2,
+ (q31_t)0x838E1507, (q31_t)0xE20AE9C1, (q31_t)0x8399E244,
+ (q31_t)0xE1DA0D7E, (q31_t)0x83A5C2B0, (q31_t)0xE1A935E1,
+ (q31_t)0x83B1B649, (q31_t)0xE17862F3, (q31_t)0x83BDBD0D,
+ (q31_t)0xE14794B9, (q31_t)0x83C9D6FB, (q31_t)0xE116CB3D,
+ (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x83E2444D,
+ (q31_t)0xE0B54698, (q31_t)0x83EE97AC, (q31_t)0xE0848B7F,
+ (q31_t)0x83FAFE2E, (q31_t)0xE053D541, (q31_t)0x840777CF,
+ (q31_t)0xE02323E5, (q31_t)0x8414048F, (q31_t)0xDFF27773,
+ (q31_t)0x8420A46B, (q31_t)0xDFC1CFF2, (q31_t)0x842D5761,
+ (q31_t)0xDF912D6A, (q31_t)0x843A1D70, (q31_t)0xDF608FE3,
+ (q31_t)0x8446F695, (q31_t)0xDF2FF764, (q31_t)0x8453E2CE,
+ (q31_t)0xDEFF63F4, (q31_t)0x8460E21A, (q31_t)0xDECED59B,
+ (q31_t)0x846DF476, (q31_t)0xDE9E4C60, (q31_t)0x847B19E1,
+ (q31_t)0xDE6DC84B, (q31_t)0x84885257, (q31_t)0xDE3D4963,
+ (q31_t)0x84959DD9, (q31_t)0xDE0CCFB1, (q31_t)0x84A2FC62,
+ (q31_t)0xDDDC5B3A, (q31_t)0x84B06DF1, (q31_t)0xDDABEC07,
+ (q31_t)0x84BDF285, (q31_t)0xDD7B8220, (q31_t)0x84CB8A1B,
+ (q31_t)0xDD4B1D8B, (q31_t)0x84D934B0, (q31_t)0xDD1ABE51,
+ (q31_t)0x84E6F244, (q31_t)0xDCEA6478, (q31_t)0x84F4C2D3,
+ (q31_t)0xDCBA1008, (q31_t)0x8502A65C, (q31_t)0xDC89C108,
+ (q31_t)0x85109CDC, (q31_t)0xDC597781, (q31_t)0x851EA652,
+ (q31_t)0xDC293379, (q31_t)0x852CC2BA, (q31_t)0xDBF8F4F8,
+ (q31_t)0x853AF214, (q31_t)0xDBC8BC05, (q31_t)0x8549345C,
+ (q31_t)0xDB9888A8, (q31_t)0x85578991, (q31_t)0xDB685AE8,
+ (q31_t)0x8565F1B0, (q31_t)0xDB3832CD, (q31_t)0x85746CB7,
+ (q31_t)0xDB08105E, (q31_t)0x8582FAA4, (q31_t)0xDAD7F3A2,
+ (q31_t)0x85919B75, (q31_t)0xDAA7DCA1, (q31_t)0x85A04F28,
+ (q31_t)0xDA77CB62, (q31_t)0x85AF15B9, (q31_t)0xDA47BFED,
+ (q31_t)0x85BDEF27, (q31_t)0xDA17BA4A, (q31_t)0x85CCDB70,
+ (q31_t)0xD9E7BA7E, (q31_t)0x85DBDA91, (q31_t)0xD9B7C093,
+ (q31_t)0x85EAEC88, (q31_t)0xD987CC8F, (q31_t)0x85FA1152,
+ (q31_t)0xD957DE7A, (q31_t)0x860948EE, (q31_t)0xD927F65B,
+ (q31_t)0x86189359, (q31_t)0xD8F81439, (q31_t)0x8627F090,
+ (q31_t)0xD8C8381C, (q31_t)0x86376092, (q31_t)0xD898620C,
+ (q31_t)0x8646E35B, (q31_t)0xD868920F, (q31_t)0x865678EA,
+ (q31_t)0xD838C82D, (q31_t)0x8666213C, (q31_t)0xD809046D,
+ (q31_t)0x8675DC4E, (q31_t)0xD7D946D7, (q31_t)0x8685AA1F,
+ (q31_t)0xD7A98F73, (q31_t)0x86958AAB, (q31_t)0xD779DE46,
+ (q31_t)0x86A57DF1, (q31_t)0xD74A335A, (q31_t)0x86B583EE,
+ (q31_t)0xD71A8EB5, (q31_t)0x86C59C9F, (q31_t)0xD6EAF05E,
+ (q31_t)0x86D5C802, (q31_t)0xD6BB585D, (q31_t)0x86E60614,
+ (q31_t)0xD68BC6BA, (q31_t)0x86F656D3, (q31_t)0xD65C3B7B,
+ (q31_t)0x8706BA3C, (q31_t)0xD62CB6A7, (q31_t)0x8717304E,
+ (q31_t)0xD5FD3847, (q31_t)0x8727B904, (q31_t)0xD5CDC062,
+ (q31_t)0x8738545E, (q31_t)0xD59E4EFE, (q31_t)0x87490257,
+ (q31_t)0xD56EE424, (q31_t)0x8759C2EF, (q31_t)0xD53F7FDA,
+ (q31_t)0x876A9621, (q31_t)0xD5102227, (q31_t)0x877B7BEC,
+ (q31_t)0xD4E0CB14, (q31_t)0x878C744C, (q31_t)0xD4B17AA7,
+ (q31_t)0x879D7F40, (q31_t)0xD48230E8, (q31_t)0x87AE9CC5,
+ (q31_t)0xD452EDDE, (q31_t)0x87BFCCD7, (q31_t)0xD423B190,
+ (q31_t)0x87D10F75, (q31_t)0xD3F47C06, (q31_t)0x87E2649B,
+ (q31_t)0xD3C54D46, (q31_t)0x87F3CC47, (q31_t)0xD3962559,
+ (q31_t)0x88054677, (q31_t)0xD3670445, (q31_t)0x8816D327,
+ (q31_t)0xD337EA12, (q31_t)0x88287255, (q31_t)0xD308D6C6,
+ (q31_t)0x883A23FE, (q31_t)0xD2D9CA6A, (q31_t)0x884BE820,
+ (q31_t)0xD2AAC504, (q31_t)0x885DBEB7, (q31_t)0xD27BC69C,
+ (q31_t)0x886FA7C2, (q31_t)0xD24CCF38, (q31_t)0x8881A33C,
+ (q31_t)0xD21DDEE1, (q31_t)0x8893B124, (q31_t)0xD1EEF59E,
+ (q31_t)0x88A5D177, (q31_t)0xD1C01374, (q31_t)0x88B80431,
+ (q31_t)0xD191386D, (q31_t)0x88CA4951, (q31_t)0xD162648F,
+ (q31_t)0x88DCA0D3, (q31_t)0xD13397E1, (q31_t)0x88EF0AB4,
+ (q31_t)0xD104D26B, (q31_t)0x890186F1, (q31_t)0xD0D61433,
+ (q31_t)0x89141589, (q31_t)0xD0A75D42, (q31_t)0x8926B677,
+ (q31_t)0xD078AD9D, (q31_t)0x893969B9, (q31_t)0xD04A054D,
+ (q31_t)0x894C2F4C, (q31_t)0xD01B6459, (q31_t)0x895F072D,
+ (q31_t)0xCFECCAC7, (q31_t)0x8971F15A, (q31_t)0xCFBE389F,
+ (q31_t)0x8984EDCF, (q31_t)0xCF8FADE8, (q31_t)0x8997FC89,
+ (q31_t)0xCF612AAA, (q31_t)0x89AB1D86, (q31_t)0xCF32AEEB,
+ (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x89D1963C,
+ (q31_t)0xCED5CE08, (q31_t)0x89E4EDEE, (q31_t)0xCEA768F2,
+ (q31_t)0x89F857D8, (q31_t)0xCE790B78, (q31_t)0x8A0BD3F5,
+ (q31_t)0xCE4AB5A2, (q31_t)0x8A1F6242, (q31_t)0xCE1C6776,
+ (q31_t)0x8A3302BD, (q31_t)0xCDEE20FC, (q31_t)0x8A46B563,
+ (q31_t)0xCDBFE23A, (q31_t)0x8A5A7A30, (q31_t)0xCD91AB38,
+ (q31_t)0x8A6E5122, (q31_t)0xCD637BFD, (q31_t)0x8A823A35,
+ (q31_t)0xCD355490, (q31_t)0x8A963567, (q31_t)0xCD0734F8,
+ (q31_t)0x8AAA42B4, (q31_t)0xCCD91D3D, (q31_t)0x8ABE6219,
+ (q31_t)0xCCAB0D65, (q31_t)0x8AD29393, (q31_t)0xCC7D0577,
+ (q31_t)0x8AE6D71F, (q31_t)0xCC4F057B, (q31_t)0x8AFB2CBA,
+ (q31_t)0xCC210D78, (q31_t)0x8B0F9461, (q31_t)0xCBF31D75,
+ (q31_t)0x8B240E10, (q31_t)0xCBC53578, (q31_t)0x8B3899C5,
+ (q31_t)0xCB975589, (q31_t)0x8B4D377C, (q31_t)0xCB697DB0,
+ (q31_t)0x8B61E732, (q31_t)0xCB3BADF2, (q31_t)0x8B76A8E4,
+ (q31_t)0xCB0DE658, (q31_t)0x8B8B7C8F, (q31_t)0xCAE026E8,
+ (q31_t)0x8BA0622F, (q31_t)0xCAB26FA9, (q31_t)0x8BB559C1,
+ (q31_t)0xCA84C0A2, (q31_t)0x8BCA6342, (q31_t)0xCA5719DB,
+ (q31_t)0x8BDF7EAF, (q31_t)0xCA297B5A, (q31_t)0x8BF4AC05,
+ (q31_t)0xC9FBE527, (q31_t)0x8C09EB40, (q31_t)0xC9CE5748,
+ (q31_t)0x8C1F3C5C, (q31_t)0xC9A0D1C4, (q31_t)0x8C349F58,
+ (q31_t)0xC97354A3, (q31_t)0x8C4A142F, (q31_t)0xC945DFEC,
+ (q31_t)0x8C5F9ADD, (q31_t)0xC91873A5, (q31_t)0x8C753361,
+ (q31_t)0xC8EB0FD6, (q31_t)0x8C8ADDB6, (q31_t)0xC8BDB485,
+ (q31_t)0x8CA099D9, (q31_t)0xC89061BA, (q31_t)0x8CB667C7,
+ (q31_t)0xC863177B, (q31_t)0x8CCC477D, (q31_t)0xC835D5D0,
+ (q31_t)0x8CE238F6, (q31_t)0xC8089CBF, (q31_t)0x8CF83C30,
+ (q31_t)0xC7DB6C50, (q31_t)0x8D0E5127, (q31_t)0xC7AE4489,
+ (q31_t)0x8D2477D8, (q31_t)0xC7812571, (q31_t)0x8D3AB03F,
+ (q31_t)0xC7540F10, (q31_t)0x8D50FA59, (q31_t)0xC727016C,
+ (q31_t)0x8D675623, (q31_t)0xC6F9FC8D, (q31_t)0x8D7DC399,
+ (q31_t)0xC6CD0079, (q31_t)0x8D9442B7, (q31_t)0xC6A00D36,
+ (q31_t)0x8DAAD37B, (q31_t)0xC67322CD, (q31_t)0x8DC175E0,
+ (q31_t)0xC6464144, (q31_t)0x8DD829E4, (q31_t)0xC61968A2,
+ (q31_t)0x8DEEEF82, (q31_t)0xC5EC98ED, (q31_t)0x8E05C6B7,
+ (q31_t)0xC5BFD22E, (q31_t)0x8E1CAF80, (q31_t)0xC593146A,
+ (q31_t)0x8E33A9D9, (q31_t)0xC5665FA8, (q31_t)0x8E4AB5BF,
+ (q31_t)0xC539B3F0, (q31_t)0x8E61D32D, (q31_t)0xC50D1148,
+ (q31_t)0x8E790222, (q31_t)0xC4E077B8, (q31_t)0x8E904298,
+ (q31_t)0xC4B3E746, (q31_t)0x8EA7948C, (q31_t)0xC4875FF8,
+ (q31_t)0x8EBEF7FB, (q31_t)0xC45AE1D7, (q31_t)0x8ED66CE1,
+ (q31_t)0xC42E6CE8, (q31_t)0x8EEDF33B, (q31_t)0xC4020132,
+ (q31_t)0x8F058B04, (q31_t)0xC3D59EBD, (q31_t)0x8F1D343A,
+ (q31_t)0xC3A9458F, (q31_t)0x8F34EED8, (q31_t)0xC37CF5B0,
+ (q31_t)0x8F4CBADB, (q31_t)0xC350AF25, (q31_t)0x8F64983F,
+ (q31_t)0xC32471F6, (q31_t)0x8F7C8701, (q31_t)0xC2F83E2A,
+ (q31_t)0x8F94871D, (q31_t)0xC2CC13C7, (q31_t)0x8FAC988E,
+ (q31_t)0xC29FF2D4, (q31_t)0x8FC4BB53, (q31_t)0xC273DB58,
+ (q31_t)0x8FDCEF66, (q31_t)0xC247CD5A, (q31_t)0x8FF534C4,
+ (q31_t)0xC21BC8E0, (q31_t)0x900D8B69, (q31_t)0xC1EFCDF2,
+ (q31_t)0x9025F352, (q31_t)0xC1C3DC96, (q31_t)0x903E6C7A,
+ (q31_t)0xC197F4D3, (q31_t)0x9056F6DF, (q31_t)0xC16C16B0,
+ (q31_t)0x906F927B, (q31_t)0xC1404233, (q31_t)0x90883F4C,
+ (q31_t)0xC1147763, (q31_t)0x90A0FD4E, (q31_t)0xC0E8B648,
+ (q31_t)0x90B9CC7C, (q31_t)0xC0BCFEE7, (q31_t)0x90D2ACD3,
+ (q31_t)0xC0915147, (q31_t)0x90EB9E50, (q31_t)0xC065AD70,
+ (q31_t)0x9104A0ED, (q31_t)0xC03A1368, (q31_t)0x911DB4A8,
+ (q31_t)0xC00E8335, (q31_t)0x9136D97D, (q31_t)0xBFE2FCDF,
+ (q31_t)0x91500F67, (q31_t)0xBFB7806C, (q31_t)0x91695663,
+ (q31_t)0xBF8C0DE2, (q31_t)0x9182AE6C, (q31_t)0xBF60A54A,
+ (q31_t)0x919C1780, (q31_t)0xBF3546A8, (q31_t)0x91B5919A,
+ (q31_t)0xBF09F204, (q31_t)0x91CF1CB6, (q31_t)0xBEDEA765,
+ (q31_t)0x91E8B8D0, (q31_t)0xBEB366D1, (q31_t)0x920265E4,
+ (q31_t)0xBE88304F, (q31_t)0x921C23EE, (q31_t)0xBE5D03E5,
+ (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x924FD2D6,
+ (q31_t)0xBE06C977, (q31_t)0x9269C3AC, (q31_t)0xBDDBBB7F,
+ (q31_t)0x9283C567, (q31_t)0xBDB0B7BA, (q31_t)0x929DD805,
+ (q31_t)0xBD85BE2F, (q31_t)0x92B7FB82, (q31_t)0xBD5ACEE5,
+ (q31_t)0x92D22FD8, (q31_t)0xBD2FE9E1, (q31_t)0x92EC7505,
+ (q31_t)0xBD050F2C, (q31_t)0x9306CB04, (q31_t)0xBCDA3ECA,
+ (q31_t)0x932131D1, (q31_t)0xBCAF78C3, (q31_t)0x933BA968,
+ (q31_t)0xBC84BD1E, (q31_t)0x935631C5, (q31_t)0xBC5A0BE1,
+ (q31_t)0x9370CAE4, (q31_t)0xBC2F6513, (q31_t)0x938B74C0,
+ (q31_t)0xBC04C8BA, (q31_t)0x93A62F56, (q31_t)0xBBDA36DC,
+ (q31_t)0x93C0FAA2, (q31_t)0xBBAFAF81, (q31_t)0x93DBD69F,
+ (q31_t)0xBB8532AF, (q31_t)0x93F6C34A, (q31_t)0xBB5AC06C,
+ (q31_t)0x9411C09D, (q31_t)0xBB3058C0, (q31_t)0x942CCE95,
+ (q31_t)0xBB05FBB0, (q31_t)0x9447ED2F, (q31_t)0xBADBA943,
+ (q31_t)0x94631C64, (q31_t)0xBAB1617F, (q31_t)0x947E5C32,
+ (q31_t)0xBA87246C, (q31_t)0x9499AC95, (q31_t)0xBA5CF210,
+ (q31_t)0x94B50D87, (q31_t)0xBA32CA70, (q31_t)0x94D07F05,
+ (q31_t)0xBA08AD94, (q31_t)0x94EC010B, (q31_t)0xB9DE9B83,
+ (q31_t)0x95079393, (q31_t)0xB9B49442, (q31_t)0x9523369B,
+ (q31_t)0xB98A97D8, (q31_t)0x953EEA1E, (q31_t)0xB960A64B,
+ (q31_t)0x955AAE17, (q31_t)0xB936BFA3, (q31_t)0x95768282,
+ (q31_t)0xB90CE3E6, (q31_t)0x9592675B, (q31_t)0xB8E31319,
+ (q31_t)0x95AE5C9E, (q31_t)0xB8B94D44, (q31_t)0x95CA6246,
+ (q31_t)0xB88F926C, (q31_t)0x95E6784F, (q31_t)0xB865E299,
+ (q31_t)0x96029EB5, (q31_t)0xB83C3DD1, (q31_t)0x961ED573,
+ (q31_t)0xB812A419, (q31_t)0x963B1C85, (q31_t)0xB7E9157A,
+ (q31_t)0x965773E7, (q31_t)0xB7BF91F8, (q31_t)0x9673DB94,
+ (q31_t)0xB796199B, (q31_t)0x96905387, (q31_t)0xB76CAC68,
+ (q31_t)0x96ACDBBD, (q31_t)0xB7434A67, (q31_t)0x96C97431,
+ (q31_t)0xB719F39D, (q31_t)0x96E61CDF, (q31_t)0xB6F0A811,
+ (q31_t)0x9702D5C2, (q31_t)0xB6C767CA, (q31_t)0x971F9ED6,
+ (q31_t)0xB69E32CD, (q31_t)0x973C7816, (q31_t)0xB6750921,
+ (q31_t)0x9759617E, (q31_t)0xB64BEACC, (q31_t)0x97765B0A,
+ (q31_t)0xB622D7D5, (q31_t)0x979364B5, (q31_t)0xB5F9D042,
+ (q31_t)0x97B07E7A, (q31_t)0xB5D0D41A, (q31_t)0x97CDA855,
+ (q31_t)0xB5A7E362, (q31_t)0x97EAE241, (q31_t)0xB57EFE21,
+ (q31_t)0x98082C3B, (q31_t)0xB556245E, (q31_t)0x9825863D,
+ (q31_t)0xB52D561E, (q31_t)0x9842F043, (q31_t)0xB5049368,
+ (q31_t)0x98606A48, (q31_t)0xB4DBDC42, (q31_t)0x987DF449,
+ (q31_t)0xB4B330B2, (q31_t)0x989B8E3F, (q31_t)0xB48A90C0,
+ (q31_t)0x98B93828, (q31_t)0xB461FC70, (q31_t)0x98D6F1FE,
+ (q31_t)0xB43973C9, (q31_t)0x98F4BBBC, (q31_t)0xB410F6D2,
+ (q31_t)0x9912955E, (q31_t)0xB3E88591, (q31_t)0x99307EE0,
+ (q31_t)0xB3C0200C, (q31_t)0x994E783C, (q31_t)0xB397C649,
+ (q31_t)0x996C816F, (q31_t)0xB36F784E, (q31_t)0x998A9A73,
+ (q31_t)0xB3473622, (q31_t)0x99A8C344, (q31_t)0xB31EFFCB,
+ (q31_t)0x99C6FBDE, (q31_t)0xB2F6D54F, (q31_t)0x99E5443A,
+ (q31_t)0xB2CEB6B5, (q31_t)0x9A039C56, (q31_t)0xB2A6A401,
+ (q31_t)0x9A22042C, (q31_t)0xB27E9D3B, (q31_t)0x9A407BB8,
+ (q31_t)0xB256A26A, (q31_t)0x9A5F02F5, (q31_t)0xB22EB392,
+ (q31_t)0x9A7D99DD, (q31_t)0xB206D0BA, (q31_t)0x9A9C406D,
+ (q31_t)0xB1DEF9E8, (q31_t)0x9ABAF6A0, (q31_t)0xB1B72F23,
+ (q31_t)0x9AD9BC71, (q31_t)0xB18F7070, (q31_t)0x9AF891DB,
+ (q31_t)0xB167BDD6, (q31_t)0x9B1776D9, (q31_t)0xB140175B,
+ (q31_t)0x9B366B67, (q31_t)0xB1187D05, (q31_t)0x9B556F80,
+ (q31_t)0xB0F0EEDA, (q31_t)0x9B748320, (q31_t)0xB0C96CDF,
+ (q31_t)0x9B93A640, (q31_t)0xB0A1F71C, (q31_t)0x9BB2D8DD,
+ (q31_t)0xB07A8D97, (q31_t)0x9BD21AF2, (q31_t)0xB0533055,
+ (q31_t)0x9BF16C7A, (q31_t)0xB02BDF5C, (q31_t)0x9C10CD70,
+ (q31_t)0xB0049AB2, (q31_t)0x9C303DCF, (q31_t)0xAFDD625F,
+ (q31_t)0x9C4FBD92, (q31_t)0xAFB63667, (q31_t)0x9C6F4CB5,
+ (q31_t)0xAF8F16D0, (q31_t)0x9C8EEB33, (q31_t)0xAF6803A1,
+ (q31_t)0x9CAE9907, (q31_t)0xAF40FCE0, (q31_t)0x9CCE562B,
+ (q31_t)0xAF1A0293, (q31_t)0x9CEE229C, (q31_t)0xAEF314BF,
+ (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0x9D2DE94D,
+ (q31_t)0xAEA55E9D, (q31_t)0x9D4DE384, (q31_t)0xAE7E965B,
+ (q31_t)0x9D6DECF4, (q31_t)0xAE57DAAA, (q31_t)0x9D8E0596,
+ (q31_t)0xAE312B91, (q31_t)0x9DAE2D68, (q31_t)0xAE0A8916,
+ (q31_t)0x9DCE6462, (q31_t)0xADE3F33E, (q31_t)0x9DEEAA82,
+ (q31_t)0xADBD6A10, (q31_t)0x9E0EFFC1, (q31_t)0xAD96ED91,
+ (q31_t)0x9E2F641A, (q31_t)0xAD707DC8, (q31_t)0x9E4FD789,
+ (q31_t)0xAD4A1ABA, (q31_t)0x9E705A09, (q31_t)0xAD23C46D,
+ (q31_t)0x9E90EB94, (q31_t)0xACFD7AE8, (q31_t)0x9EB18C26,
+ (q31_t)0xACD73E30, (q31_t)0x9ED23BB9, (q31_t)0xACB10E4A,
+ (q31_t)0x9EF2FA48, (q31_t)0xAC8AEB3E, (q31_t)0x9F13C7D0,
+ (q31_t)0xAC64D510, (q31_t)0x9F34A449, (q31_t)0xAC3ECBC7,
+ (q31_t)0x9F558FB0, (q31_t)0xAC18CF68, (q31_t)0x9F7689FF,
+ (q31_t)0xABF2DFFA, (q31_t)0x9F979331, (q31_t)0xABCCFD82,
+ (q31_t)0x9FB8AB41, (q31_t)0xABA72806, (q31_t)0x9FD9D22A,
+ (q31_t)0xAB815F8C, (q31_t)0x9FFB07E7, (q31_t)0xAB5BA41A,
+ (q31_t)0xA01C4C72, (q31_t)0xAB35F5B5, (q31_t)0xA03D9FC7,
+ (q31_t)0xAB105464, (q31_t)0xA05F01E1, (q31_t)0xAAEAC02B,
+ (q31_t)0xA08072BA, (q31_t)0xAAC53912, (q31_t)0xA0A1F24C,
+ (q31_t)0xAA9FBF1D, (q31_t)0xA0C38094, (q31_t)0xAA7A5253,
+ (q31_t)0xA0E51D8C, (q31_t)0xAA54F2B9, (q31_t)0xA106C92E,
+ (q31_t)0xAA2FA055, (q31_t)0xA1288376, (q31_t)0xAA0A5B2D,
+ (q31_t)0xA14A4C5E, (q31_t)0xA9E52347, (q31_t)0xA16C23E1,
+ (q31_t)0xA9BFF8A8, (q31_t)0xA18E09F9, (q31_t)0xA99ADB56,
+ (q31_t)0xA1AFFEA2, (q31_t)0xA975CB56, (q31_t)0xA1D201D7,
+ (q31_t)0xA950C8AF, (q31_t)0xA1F41391, (q31_t)0xA92BD366,
+ (q31_t)0xA21633CD, (q31_t)0xA906EB81, (q31_t)0xA2386283,
+ (q31_t)0xA8E21106, (q31_t)0xA25A9FB1, (q31_t)0xA8BD43FA,
+ (q31_t)0xA27CEB4F, (q31_t)0xA8988463, (q31_t)0xA29F4559,
+ (q31_t)0xA873D246, (q31_t)0xA2C1ADC9, (q31_t)0xA84F2DA9,
+ (q31_t)0xA2E4249A, (q31_t)0xA82A9693, (q31_t)0xA306A9C7,
+ (q31_t)0xA8060D08, (q31_t)0xA3293D4B, (q31_t)0xA7E1910E,
+ (q31_t)0xA34BDF20, (q31_t)0xA7BD22AB, (q31_t)0xA36E8F40,
+ (q31_t)0xA798C1E4, (q31_t)0xA3914DA7, (q31_t)0xA7746EC0,
+ (q31_t)0xA3B41A4F, (q31_t)0xA7502943, (q31_t)0xA3D6F533,
+ (q31_t)0xA72BF173, (q31_t)0xA3F9DE4D, (q31_t)0xA707C756,
+ (q31_t)0xA41CD598, (q31_t)0xA6E3AAF2, (q31_t)0xA43FDB0F,
+ (q31_t)0xA6BF9C4B, (q31_t)0xA462EEAC, (q31_t)0xA69B9B68,
+ (q31_t)0xA4861069, (q31_t)0xA677A84E, (q31_t)0xA4A94042,
+ (q31_t)0xA653C302, (q31_t)0xA4CC7E31, (q31_t)0xA62FEB8B,
+ (q31_t)0xA4EFCA31, (q31_t)0xA60C21ED, (q31_t)0xA513243B,
+ (q31_t)0xA5E8662F, (q31_t)0xA5368C4B, (q31_t)0xA5C4B855,
+ (q31_t)0xA55A025B, (q31_t)0xA5A11865, (q31_t)0xA57D8666,
+ (q31_t)0xA57D8666, (q31_t)0xA5A11865, (q31_t)0xA55A025B,
+ (q31_t)0xA5C4B855, (q31_t)0xA5368C4B, (q31_t)0xA5E8662F,
+ (q31_t)0xA513243B, (q31_t)0xA60C21ED, (q31_t)0xA4EFCA31,
+ (q31_t)0xA62FEB8B, (q31_t)0xA4CC7E31, (q31_t)0xA653C302,
+ (q31_t)0xA4A94042, (q31_t)0xA677A84E, (q31_t)0xA4861069,
+ (q31_t)0xA69B9B68, (q31_t)0xA462EEAC, (q31_t)0xA6BF9C4B,
+ (q31_t)0xA43FDB0F, (q31_t)0xA6E3AAF2, (q31_t)0xA41CD598,
+ (q31_t)0xA707C756, (q31_t)0xA3F9DE4D, (q31_t)0xA72BF173,
+ (q31_t)0xA3D6F533, (q31_t)0xA7502943, (q31_t)0xA3B41A4F,
+ (q31_t)0xA7746EC0, (q31_t)0xA3914DA7, (q31_t)0xA798C1E4,
+ (q31_t)0xA36E8F40, (q31_t)0xA7BD22AB, (q31_t)0xA34BDF20,
+ (q31_t)0xA7E1910E, (q31_t)0xA3293D4B, (q31_t)0xA8060D08,
+ (q31_t)0xA306A9C7, (q31_t)0xA82A9693, (q31_t)0xA2E4249A,
+ (q31_t)0xA84F2DA9, (q31_t)0xA2C1ADC9, (q31_t)0xA873D246,
+ (q31_t)0xA29F4559, (q31_t)0xA8988463, (q31_t)0xA27CEB4F,
+ (q31_t)0xA8BD43FA, (q31_t)0xA25A9FB1, (q31_t)0xA8E21106,
+ (q31_t)0xA2386283, (q31_t)0xA906EB81, (q31_t)0xA21633CD,
+ (q31_t)0xA92BD366, (q31_t)0xA1F41391, (q31_t)0xA950C8AF,
+ (q31_t)0xA1D201D7, (q31_t)0xA975CB56, (q31_t)0xA1AFFEA2,
+ (q31_t)0xA99ADB56, (q31_t)0xA18E09F9, (q31_t)0xA9BFF8A8,
+ (q31_t)0xA16C23E1, (q31_t)0xA9E52347, (q31_t)0xA14A4C5E,
+ (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAA2FA055,
+ (q31_t)0xA106C92E, (q31_t)0xAA54F2B9, (q31_t)0xA0E51D8C,
+ (q31_t)0xAA7A5253, (q31_t)0xA0C38094, (q31_t)0xAA9FBF1D,
+ (q31_t)0xA0A1F24C, (q31_t)0xAAC53912, (q31_t)0xA08072BA,
+ (q31_t)0xAAEAC02B, (q31_t)0xA05F01E1, (q31_t)0xAB105464,
+ (q31_t)0xA03D9FC7, (q31_t)0xAB35F5B5, (q31_t)0xA01C4C72,
+ (q31_t)0xAB5BA41A, (q31_t)0x9FFB07E7, (q31_t)0xAB815F8C,
+ (q31_t)0x9FD9D22A, (q31_t)0xABA72806, (q31_t)0x9FB8AB41,
+ (q31_t)0xABCCFD82, (q31_t)0x9F979331, (q31_t)0xABF2DFFA,
+ (q31_t)0x9F7689FF, (q31_t)0xAC18CF68, (q31_t)0x9F558FB0,
+ (q31_t)0xAC3ECBC7, (q31_t)0x9F34A449, (q31_t)0xAC64D510,
+ (q31_t)0x9F13C7D0, (q31_t)0xAC8AEB3E, (q31_t)0x9EF2FA48,
+ (q31_t)0xACB10E4A, (q31_t)0x9ED23BB9, (q31_t)0xACD73E30,
+ (q31_t)0x9EB18C26, (q31_t)0xACFD7AE8, (q31_t)0x9E90EB94,
+ (q31_t)0xAD23C46D, (q31_t)0x9E705A09, (q31_t)0xAD4A1ABA,
+ (q31_t)0x9E4FD789, (q31_t)0xAD707DC8, (q31_t)0x9E2F641A,
+ (q31_t)0xAD96ED91, (q31_t)0x9E0EFFC1, (q31_t)0xADBD6A10,
+ (q31_t)0x9DEEAA82, (q31_t)0xADE3F33E, (q31_t)0x9DCE6462,
+ (q31_t)0xAE0A8916, (q31_t)0x9DAE2D68, (q31_t)0xAE312B91,
+ (q31_t)0x9D8E0596, (q31_t)0xAE57DAAA, (q31_t)0x9D6DECF4,
+ (q31_t)0xAE7E965B, (q31_t)0x9D4DE384, (q31_t)0xAEA55E9D,
+ (q31_t)0x9D2DE94D, (q31_t)0xAECC336B, (q31_t)0x9D0DFE53,
+ (q31_t)0xAEF314BF, (q31_t)0x9CEE229C, (q31_t)0xAF1A0293,
+ (q31_t)0x9CCE562B, (q31_t)0xAF40FCE0, (q31_t)0x9CAE9907,
+ (q31_t)0xAF6803A1, (q31_t)0x9C8EEB33, (q31_t)0xAF8F16D0,
+ (q31_t)0x9C6F4CB5, (q31_t)0xAFB63667, (q31_t)0x9C4FBD92,
+ (q31_t)0xAFDD625F, (q31_t)0x9C303DCF, (q31_t)0xB0049AB2,
+ (q31_t)0x9C10CD70, (q31_t)0xB02BDF5C, (q31_t)0x9BF16C7A,
+ (q31_t)0xB0533055, (q31_t)0x9BD21AF2, (q31_t)0xB07A8D97,
+ (q31_t)0x9BB2D8DD, (q31_t)0xB0A1F71C, (q31_t)0x9B93A640,
+ (q31_t)0xB0C96CDF, (q31_t)0x9B748320, (q31_t)0xB0F0EEDA,
+ (q31_t)0x9B556F80, (q31_t)0xB1187D05, (q31_t)0x9B366B67,
+ (q31_t)0xB140175B, (q31_t)0x9B1776D9, (q31_t)0xB167BDD6,
+ (q31_t)0x9AF891DB, (q31_t)0xB18F7070, (q31_t)0x9AD9BC71,
+ (q31_t)0xB1B72F23, (q31_t)0x9ABAF6A0, (q31_t)0xB1DEF9E8,
+ (q31_t)0x9A9C406D, (q31_t)0xB206D0BA, (q31_t)0x9A7D99DD,
+ (q31_t)0xB22EB392, (q31_t)0x9A5F02F5, (q31_t)0xB256A26A,
+ (q31_t)0x9A407BB8, (q31_t)0xB27E9D3B, (q31_t)0x9A22042C,
+ (q31_t)0xB2A6A401, (q31_t)0x9A039C56, (q31_t)0xB2CEB6B5,
+ (q31_t)0x99E5443A, (q31_t)0xB2F6D54F, (q31_t)0x99C6FBDE,
+ (q31_t)0xB31EFFCB, (q31_t)0x99A8C344, (q31_t)0xB3473622,
+ (q31_t)0x998A9A73, (q31_t)0xB36F784E, (q31_t)0x996C816F,
+ (q31_t)0xB397C649, (q31_t)0x994E783C, (q31_t)0xB3C0200C,
+ (q31_t)0x99307EE0, (q31_t)0xB3E88591, (q31_t)0x9912955E,
+ (q31_t)0xB410F6D2, (q31_t)0x98F4BBBC, (q31_t)0xB43973C9,
+ (q31_t)0x98D6F1FE, (q31_t)0xB461FC70, (q31_t)0x98B93828,
+ (q31_t)0xB48A90C0, (q31_t)0x989B8E3F, (q31_t)0xB4B330B2,
+ (q31_t)0x987DF449, (q31_t)0xB4DBDC42, (q31_t)0x98606A48,
+ (q31_t)0xB5049368, (q31_t)0x9842F043, (q31_t)0xB52D561E,
+ (q31_t)0x9825863D, (q31_t)0xB556245E, (q31_t)0x98082C3B,
+ (q31_t)0xB57EFE21, (q31_t)0x97EAE241, (q31_t)0xB5A7E362,
+ (q31_t)0x97CDA855, (q31_t)0xB5D0D41A, (q31_t)0x97B07E7A,
+ (q31_t)0xB5F9D042, (q31_t)0x979364B5, (q31_t)0xB622D7D5,
+ (q31_t)0x97765B0A, (q31_t)0xB64BEACC, (q31_t)0x9759617E,
+ (q31_t)0xB6750921, (q31_t)0x973C7816, (q31_t)0xB69E32CD,
+ (q31_t)0x971F9ED6, (q31_t)0xB6C767CA, (q31_t)0x9702D5C2,
+ (q31_t)0xB6F0A811, (q31_t)0x96E61CDF, (q31_t)0xB719F39D,
+ (q31_t)0x96C97431, (q31_t)0xB7434A67, (q31_t)0x96ACDBBD,
+ (q31_t)0xB76CAC68, (q31_t)0x96905387, (q31_t)0xB796199B,
+ (q31_t)0x9673DB94, (q31_t)0xB7BF91F8, (q31_t)0x965773E7,
+ (q31_t)0xB7E9157A, (q31_t)0x963B1C85, (q31_t)0xB812A419,
+ (q31_t)0x961ED573, (q31_t)0xB83C3DD1, (q31_t)0x96029EB5,
+ (q31_t)0xB865E299, (q31_t)0x95E6784F, (q31_t)0xB88F926C,
+ (q31_t)0x95CA6246, (q31_t)0xB8B94D44, (q31_t)0x95AE5C9E,
+ (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xB90CE3E6,
+ (q31_t)0x95768282, (q31_t)0xB936BFA3, (q31_t)0x955AAE17,
+ (q31_t)0xB960A64B, (q31_t)0x953EEA1E, (q31_t)0xB98A97D8,
+ (q31_t)0x9523369B, (q31_t)0xB9B49442, (q31_t)0x95079393,
+ (q31_t)0xB9DE9B83, (q31_t)0x94EC010B, (q31_t)0xBA08AD94,
+ (q31_t)0x94D07F05, (q31_t)0xBA32CA70, (q31_t)0x94B50D87,
+ (q31_t)0xBA5CF210, (q31_t)0x9499AC95, (q31_t)0xBA87246C,
+ (q31_t)0x947E5C32, (q31_t)0xBAB1617F, (q31_t)0x94631C64,
+ (q31_t)0xBADBA943, (q31_t)0x9447ED2F, (q31_t)0xBB05FBB0,
+ (q31_t)0x942CCE95, (q31_t)0xBB3058C0, (q31_t)0x9411C09D,
+ (q31_t)0xBB5AC06C, (q31_t)0x93F6C34A, (q31_t)0xBB8532AF,
+ (q31_t)0x93DBD69F, (q31_t)0xBBAFAF81, (q31_t)0x93C0FAA2,
+ (q31_t)0xBBDA36DC, (q31_t)0x93A62F56, (q31_t)0xBC04C8BA,
+ (q31_t)0x938B74C0, (q31_t)0xBC2F6513, (q31_t)0x9370CAE4,
+ (q31_t)0xBC5A0BE1, (q31_t)0x935631C5, (q31_t)0xBC84BD1E,
+ (q31_t)0x933BA968, (q31_t)0xBCAF78C3, (q31_t)0x932131D1,
+ (q31_t)0xBCDA3ECA, (q31_t)0x9306CB04, (q31_t)0xBD050F2C,
+ (q31_t)0x92EC7505, (q31_t)0xBD2FE9E1, (q31_t)0x92D22FD8,
+ (q31_t)0xBD5ACEE5, (q31_t)0x92B7FB82, (q31_t)0xBD85BE2F,
+ (q31_t)0x929DD805, (q31_t)0xBDB0B7BA, (q31_t)0x9283C567,
+ (q31_t)0xBDDBBB7F, (q31_t)0x9269C3AC, (q31_t)0xBE06C977,
+ (q31_t)0x924FD2D6, (q31_t)0xBE31E19B, (q31_t)0x9235F2EB,
+ (q31_t)0xBE5D03E5, (q31_t)0x921C23EE, (q31_t)0xBE88304F,
+ (q31_t)0x920265E4, (q31_t)0xBEB366D1, (q31_t)0x91E8B8D0,
+ (q31_t)0xBEDEA765, (q31_t)0x91CF1CB6, (q31_t)0xBF09F204,
+ (q31_t)0x91B5919A, (q31_t)0xBF3546A8, (q31_t)0x919C1780,
+ (q31_t)0xBF60A54A, (q31_t)0x9182AE6C, (q31_t)0xBF8C0DE2,
+ (q31_t)0x91695663, (q31_t)0xBFB7806C, (q31_t)0x91500F67,
+ (q31_t)0xBFE2FCDF, (q31_t)0x9136D97D, (q31_t)0xC00E8335,
+ (q31_t)0x911DB4A8, (q31_t)0xC03A1368, (q31_t)0x9104A0ED,
+ (q31_t)0xC065AD70, (q31_t)0x90EB9E50, (q31_t)0xC0915147,
+ (q31_t)0x90D2ACD3, (q31_t)0xC0BCFEE7, (q31_t)0x90B9CC7C,
+ (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC1147763,
+ (q31_t)0x90883F4C, (q31_t)0xC1404233, (q31_t)0x906F927B,
+ (q31_t)0xC16C16B0, (q31_t)0x9056F6DF, (q31_t)0xC197F4D3,
+ (q31_t)0x903E6C7A, (q31_t)0xC1C3DC96, (q31_t)0x9025F352,
+ (q31_t)0xC1EFCDF2, (q31_t)0x900D8B69, (q31_t)0xC21BC8E0,
+ (q31_t)0x8FF534C4, (q31_t)0xC247CD5A, (q31_t)0x8FDCEF66,
+ (q31_t)0xC273DB58, (q31_t)0x8FC4BB53, (q31_t)0xC29FF2D4,
+ (q31_t)0x8FAC988E, (q31_t)0xC2CC13C7, (q31_t)0x8F94871D,
+ (q31_t)0xC2F83E2A, (q31_t)0x8F7C8701, (q31_t)0xC32471F6,
+ (q31_t)0x8F64983F, (q31_t)0xC350AF25, (q31_t)0x8F4CBADB,
+ (q31_t)0xC37CF5B0, (q31_t)0x8F34EED8, (q31_t)0xC3A9458F,
+ (q31_t)0x8F1D343A, (q31_t)0xC3D59EBD, (q31_t)0x8F058B04,
+ (q31_t)0xC4020132, (q31_t)0x8EEDF33B, (q31_t)0xC42E6CE8,
+ (q31_t)0x8ED66CE1, (q31_t)0xC45AE1D7, (q31_t)0x8EBEF7FB,
+ (q31_t)0xC4875FF8, (q31_t)0x8EA7948C, (q31_t)0xC4B3E746,
+ (q31_t)0x8E904298, (q31_t)0xC4E077B8, (q31_t)0x8E790222,
+ (q31_t)0xC50D1148, (q31_t)0x8E61D32D, (q31_t)0xC539B3F0,
+ (q31_t)0x8E4AB5BF, (q31_t)0xC5665FA8, (q31_t)0x8E33A9D9,
+ (q31_t)0xC593146A, (q31_t)0x8E1CAF80, (q31_t)0xC5BFD22E,
+ (q31_t)0x8E05C6B7, (q31_t)0xC5EC98ED, (q31_t)0x8DEEEF82,
+ (q31_t)0xC61968A2, (q31_t)0x8DD829E4, (q31_t)0xC6464144,
+ (q31_t)0x8DC175E0, (q31_t)0xC67322CD, (q31_t)0x8DAAD37B,
+ (q31_t)0xC6A00D36, (q31_t)0x8D9442B7, (q31_t)0xC6CD0079,
+ (q31_t)0x8D7DC399, (q31_t)0xC6F9FC8D, (q31_t)0x8D675623,
+ (q31_t)0xC727016C, (q31_t)0x8D50FA59, (q31_t)0xC7540F10,
+ (q31_t)0x8D3AB03F, (q31_t)0xC7812571, (q31_t)0x8D2477D8,
+ (q31_t)0xC7AE4489, (q31_t)0x8D0E5127, (q31_t)0xC7DB6C50,
+ (q31_t)0x8CF83C30, (q31_t)0xC8089CBF, (q31_t)0x8CE238F6,
+ (q31_t)0xC835D5D0, (q31_t)0x8CCC477D, (q31_t)0xC863177B,
+ (q31_t)0x8CB667C7, (q31_t)0xC89061BA, (q31_t)0x8CA099D9,
+ (q31_t)0xC8BDB485, (q31_t)0x8C8ADDB6, (q31_t)0xC8EB0FD6,
+ (q31_t)0x8C753361, (q31_t)0xC91873A5, (q31_t)0x8C5F9ADD,
+ (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xC97354A3,
+ (q31_t)0x8C349F58, (q31_t)0xC9A0D1C4, (q31_t)0x8C1F3C5C,
+ (q31_t)0xC9CE5748, (q31_t)0x8C09EB40, (q31_t)0xC9FBE527,
+ (q31_t)0x8BF4AC05, (q31_t)0xCA297B5A, (q31_t)0x8BDF7EAF,
+ (q31_t)0xCA5719DB, (q31_t)0x8BCA6342, (q31_t)0xCA84C0A2,
+ (q31_t)0x8BB559C1, (q31_t)0xCAB26FA9, (q31_t)0x8BA0622F,
+ (q31_t)0xCAE026E8, (q31_t)0x8B8B7C8F, (q31_t)0xCB0DE658,
+ (q31_t)0x8B76A8E4, (q31_t)0xCB3BADF2, (q31_t)0x8B61E732,
+ (q31_t)0xCB697DB0, (q31_t)0x8B4D377C, (q31_t)0xCB975589,
+ (q31_t)0x8B3899C5, (q31_t)0xCBC53578, (q31_t)0x8B240E10,
+ (q31_t)0xCBF31D75, (q31_t)0x8B0F9461, (q31_t)0xCC210D78,
+ (q31_t)0x8AFB2CBA, (q31_t)0xCC4F057B, (q31_t)0x8AE6D71F,
+ (q31_t)0xCC7D0577, (q31_t)0x8AD29393, (q31_t)0xCCAB0D65,
+ (q31_t)0x8ABE6219, (q31_t)0xCCD91D3D, (q31_t)0x8AAA42B4,
+ (q31_t)0xCD0734F8, (q31_t)0x8A963567, (q31_t)0xCD355490,
+ (q31_t)0x8A823A35, (q31_t)0xCD637BFD, (q31_t)0x8A6E5122,
+ (q31_t)0xCD91AB38, (q31_t)0x8A5A7A30, (q31_t)0xCDBFE23A,
+ (q31_t)0x8A46B563, (q31_t)0xCDEE20FC, (q31_t)0x8A3302BD,
+ (q31_t)0xCE1C6776, (q31_t)0x8A1F6242, (q31_t)0xCE4AB5A2,
+ (q31_t)0x8A0BD3F5, (q31_t)0xCE790B78, (q31_t)0x89F857D8,
+ (q31_t)0xCEA768F2, (q31_t)0x89E4EDEE, (q31_t)0xCED5CE08,
+ (q31_t)0x89D1963C, (q31_t)0xCF043AB2, (q31_t)0x89BE50C3,
+ (q31_t)0xCF32AEEB, (q31_t)0x89AB1D86, (q31_t)0xCF612AAA,
+ (q31_t)0x8997FC89, (q31_t)0xCF8FADE8, (q31_t)0x8984EDCF,
+ (q31_t)0xCFBE389F, (q31_t)0x8971F15A, (q31_t)0xCFECCAC7,
+ (q31_t)0x895F072D, (q31_t)0xD01B6459, (q31_t)0x894C2F4C,
+ (q31_t)0xD04A054D, (q31_t)0x893969B9, (q31_t)0xD078AD9D,
+ (q31_t)0x8926B677, (q31_t)0xD0A75D42, (q31_t)0x89141589,
+ (q31_t)0xD0D61433, (q31_t)0x890186F1, (q31_t)0xD104D26B,
+ (q31_t)0x88EF0AB4, (q31_t)0xD13397E1, (q31_t)0x88DCA0D3,
+ (q31_t)0xD162648F, (q31_t)0x88CA4951, (q31_t)0xD191386D,
+ (q31_t)0x88B80431, (q31_t)0xD1C01374, (q31_t)0x88A5D177,
+ (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD21DDEE1,
+ (q31_t)0x8881A33C, (q31_t)0xD24CCF38, (q31_t)0x886FA7C2,
+ (q31_t)0xD27BC69C, (q31_t)0x885DBEB7, (q31_t)0xD2AAC504,
+ (q31_t)0x884BE820, (q31_t)0xD2D9CA6A, (q31_t)0x883A23FE,
+ (q31_t)0xD308D6C6, (q31_t)0x88287255, (q31_t)0xD337EA12,
+ (q31_t)0x8816D327, (q31_t)0xD3670445, (q31_t)0x88054677,
+ (q31_t)0xD3962559, (q31_t)0x87F3CC47, (q31_t)0xD3C54D46,
+ (q31_t)0x87E2649B, (q31_t)0xD3F47C06, (q31_t)0x87D10F75,
+ (q31_t)0xD423B190, (q31_t)0x87BFCCD7, (q31_t)0xD452EDDE,
+ (q31_t)0x87AE9CC5, (q31_t)0xD48230E8, (q31_t)0x879D7F40,
+ (q31_t)0xD4B17AA7, (q31_t)0x878C744C, (q31_t)0xD4E0CB14,
+ (q31_t)0x877B7BEC, (q31_t)0xD5102227, (q31_t)0x876A9621,
+ (q31_t)0xD53F7FDA, (q31_t)0x8759C2EF, (q31_t)0xD56EE424,
+ (q31_t)0x87490257, (q31_t)0xD59E4EFE, (q31_t)0x8738545E,
+ (q31_t)0xD5CDC062, (q31_t)0x8727B904, (q31_t)0xD5FD3847,
+ (q31_t)0x8717304E, (q31_t)0xD62CB6A7, (q31_t)0x8706BA3C,
+ (q31_t)0xD65C3B7B, (q31_t)0x86F656D3, (q31_t)0xD68BC6BA,
+ (q31_t)0x86E60614, (q31_t)0xD6BB585D, (q31_t)0x86D5C802,
+ (q31_t)0xD6EAF05E, (q31_t)0x86C59C9F, (q31_t)0xD71A8EB5,
+ (q31_t)0x86B583EE, (q31_t)0xD74A335A, (q31_t)0x86A57DF1,
+ (q31_t)0xD779DE46, (q31_t)0x86958AAB, (q31_t)0xD7A98F73,
+ (q31_t)0x8685AA1F, (q31_t)0xD7D946D7, (q31_t)0x8675DC4E,
+ (q31_t)0xD809046D, (q31_t)0x8666213C, (q31_t)0xD838C82D,
+ (q31_t)0x865678EA, (q31_t)0xD868920F, (q31_t)0x8646E35B,
+ (q31_t)0xD898620C, (q31_t)0x86376092, (q31_t)0xD8C8381C,
+ (q31_t)0x8627F090, (q31_t)0xD8F81439, (q31_t)0x86189359,
+ (q31_t)0xD927F65B, (q31_t)0x860948EE, (q31_t)0xD957DE7A,
+ (q31_t)0x85FA1152, (q31_t)0xD987CC8F, (q31_t)0x85EAEC88,
+ (q31_t)0xD9B7C093, (q31_t)0x85DBDA91, (q31_t)0xD9E7BA7E,
+ (q31_t)0x85CCDB70, (q31_t)0xDA17BA4A, (q31_t)0x85BDEF27,
+ (q31_t)0xDA47BFED, (q31_t)0x85AF15B9, (q31_t)0xDA77CB62,
+ (q31_t)0x85A04F28, (q31_t)0xDAA7DCA1, (q31_t)0x85919B75,
+ (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDB08105E,
+ (q31_t)0x85746CB7, (q31_t)0xDB3832CD, (q31_t)0x8565F1B0,
+ (q31_t)0xDB685AE8, (q31_t)0x85578991, (q31_t)0xDB9888A8,
+ (q31_t)0x8549345C, (q31_t)0xDBC8BC05, (q31_t)0x853AF214,
+ (q31_t)0xDBF8F4F8, (q31_t)0x852CC2BA, (q31_t)0xDC293379,
+ (q31_t)0x851EA652, (q31_t)0xDC597781, (q31_t)0x85109CDC,
+ (q31_t)0xDC89C108, (q31_t)0x8502A65C, (q31_t)0xDCBA1008,
+ (q31_t)0x84F4C2D3, (q31_t)0xDCEA6478, (q31_t)0x84E6F244,
+ (q31_t)0xDD1ABE51, (q31_t)0x84D934B0, (q31_t)0xDD4B1D8B,
+ (q31_t)0x84CB8A1B, (q31_t)0xDD7B8220, (q31_t)0x84BDF285,
+ (q31_t)0xDDABEC07, (q31_t)0x84B06DF1, (q31_t)0xDDDC5B3A,
+ (q31_t)0x84A2FC62, (q31_t)0xDE0CCFB1, (q31_t)0x84959DD9,
+ (q31_t)0xDE3D4963, (q31_t)0x84885257, (q31_t)0xDE6DC84B,
+ (q31_t)0x847B19E1, (q31_t)0xDE9E4C60, (q31_t)0x846DF476,
+ (q31_t)0xDECED59B, (q31_t)0x8460E21A, (q31_t)0xDEFF63F4,
+ (q31_t)0x8453E2CE, (q31_t)0xDF2FF764, (q31_t)0x8446F695,
+ (q31_t)0xDF608FE3, (q31_t)0x843A1D70, (q31_t)0xDF912D6A,
+ (q31_t)0x842D5761, (q31_t)0xDFC1CFF2, (q31_t)0x8420A46B,
+ (q31_t)0xDFF27773, (q31_t)0x8414048F, (q31_t)0xE02323E5,
+ (q31_t)0x840777CF, (q31_t)0xE053D541, (q31_t)0x83FAFE2E,
+ (q31_t)0xE0848B7F, (q31_t)0x83EE97AC, (q31_t)0xE0B54698,
+ (q31_t)0x83E2444D, (q31_t)0xE0E60684, (q31_t)0x83D60411,
+ (q31_t)0xE116CB3D, (q31_t)0x83C9D6FB, (q31_t)0xE14794B9,
+ (q31_t)0x83BDBD0D, (q31_t)0xE17862F3, (q31_t)0x83B1B649,
+ (q31_t)0xE1A935E1, (q31_t)0x83A5C2B0, (q31_t)0xE1DA0D7E,
+ (q31_t)0x8399E244, (q31_t)0xE20AE9C1, (q31_t)0x838E1507,
+ (q31_t)0xE23BCAA2, (q31_t)0x83825AFB, (q31_t)0xE26CB01A,
+ (q31_t)0x8376B422, (q31_t)0xE29D9A22, (q31_t)0x836B207D,
+ (q31_t)0xE2CE88B2, (q31_t)0x835FA00E, (q31_t)0xE2FF7BC3,
+ (q31_t)0x835432D8, (q31_t)0xE330734C, (q31_t)0x8348D8DB,
+ (q31_t)0xE3616F47, (q31_t)0x833D921A, (q31_t)0xE3926FAC,
+ (q31_t)0x83325E97, (q31_t)0xE3C37473, (q31_t)0x83273E52,
+ (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE4258B0A,
+ (q31_t)0x8311378C, (q31_t)0xE4569CCB, (q31_t)0x8306510F,
+ (q31_t)0xE487B2CF, (q31_t)0x82FB7DD8, (q31_t)0xE4B8CD10,
+ (q31_t)0x82F0BDE8, (q31_t)0xE4E9EB86, (q31_t)0x82E61141,
+ (q31_t)0xE51B0E2A, (q31_t)0x82DB77E5, (q31_t)0xE54C34F3,
+ (q31_t)0x82D0F1D5, (q31_t)0xE57D5FDA, (q31_t)0x82C67F13,
+ (q31_t)0xE5AE8ED8, (q31_t)0x82BC1FA1, (q31_t)0xE5DFC1E4,
+ (q31_t)0x82B1D381, (q31_t)0xE610F8F9, (q31_t)0x82A79AB3,
+ (q31_t)0xE642340D, (q31_t)0x829D753A, (q31_t)0xE6737319,
+ (q31_t)0x82936316, (q31_t)0xE6A4B616, (q31_t)0x8289644A,
+ (q31_t)0xE6D5FCFC, (q31_t)0x827F78D8, (q31_t)0xE70747C3,
+ (q31_t)0x8275A0C0, (q31_t)0xE7389664, (q31_t)0x826BDC04,
+ (q31_t)0xE769E8D8, (q31_t)0x82622AA5, (q31_t)0xE79B3F16,
+ (q31_t)0x82588CA6, (q31_t)0xE7CC9917, (q31_t)0x824F0208,
+ (q31_t)0xE7FDF6D3, (q31_t)0x82458ACB, (q31_t)0xE82F5844,
+ (q31_t)0x823C26F2, (q31_t)0xE860BD60, (q31_t)0x8232D67E,
+ (q31_t)0xE8922621, (q31_t)0x82299971, (q31_t)0xE8C3927F,
+ (q31_t)0x82206FCB, (q31_t)0xE8F50273, (q31_t)0x8217598F,
+ (q31_t)0xE92675F4, (q31_t)0x820E56BE, (q31_t)0xE957ECFB,
+ (q31_t)0x82056758, (q31_t)0xE9896780, (q31_t)0x81FC8B60,
+ (q31_t)0xE9BAE57C, (q31_t)0x81F3C2D7, (q31_t)0xE9EC66E8,
+ (q31_t)0x81EB0DBD, (q31_t)0xEA1DEBBB, (q31_t)0x81E26C16,
+ (q31_t)0xEA4F73EE, (q31_t)0x81D9DDE1, (q31_t)0xEA80FF79,
+ (q31_t)0x81D16320, (q31_t)0xEAB28E55, (q31_t)0x81C8FBD5,
+ (q31_t)0xEAE4207A, (q31_t)0x81C0A801, (q31_t)0xEB15B5E0,
+ (q31_t)0x81B867A4, (q31_t)0xEB474E80, (q31_t)0x81B03AC1,
+ (q31_t)0xEB78EA52, (q31_t)0x81A82159, (q31_t)0xEBAA894E,
+ (q31_t)0x81A01B6C, (q31_t)0xEBDC2B6D, (q31_t)0x819828FD,
+ (q31_t)0xEC0DD0A8, (q31_t)0x81904A0C, (q31_t)0xEC3F78F5,
+ (q31_t)0x81887E9A, (q31_t)0xEC71244F, (q31_t)0x8180C6A9,
+ (q31_t)0xECA2D2AC, (q31_t)0x8179223A, (q31_t)0xECD48406,
+ (q31_t)0x8171914E, (q31_t)0xED063855, (q31_t)0x816A13E6,
+ (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xED69A9B2,
+ (q31_t)0x815B53A8, (q31_t)0xED9B66B2, (q31_t)0x815410D3,
+ (q31_t)0xEDCD2687, (q31_t)0x814CE188, (q31_t)0xEDFEE92B,
+ (q31_t)0x8145C5C6, (q31_t)0xEE30AE95, (q31_t)0x813EBD90,
+ (q31_t)0xEE6276BF, (q31_t)0x8137C8E6, (q31_t)0xEE9441A0,
+ (q31_t)0x8130E7C8, (q31_t)0xEEC60F31, (q31_t)0x812A1A39,
+ (q31_t)0xEEF7DF6A, (q31_t)0x81236039, (q31_t)0xEF29B243,
+ (q31_t)0x811CB9CA, (q31_t)0xEF5B87B5, (q31_t)0x811626EC,
+ (q31_t)0xEF8D5FB8, (q31_t)0x810FA7A0, (q31_t)0xEFBF3A44,
+ (q31_t)0x81093BE8, (q31_t)0xEFF11752, (q31_t)0x8102E3C3,
+ (q31_t)0xF022F6DA, (q31_t)0x80FC9F35, (q31_t)0xF054D8D4,
+ (q31_t)0x80F66E3C, (q31_t)0xF086BD39, (q31_t)0x80F050DB,
+ (q31_t)0xF0B8A401, (q31_t)0x80EA4712, (q31_t)0xF0EA8D23,
+ (q31_t)0x80E450E2, (q31_t)0xF11C789A, (q31_t)0x80DE6E4C,
+ (q31_t)0xF14E665C, (q31_t)0x80D89F51, (q31_t)0xF1805662,
+ (q31_t)0x80D2E3F1, (q31_t)0xF1B248A5, (q31_t)0x80CD3C2F,
+ (q31_t)0xF1E43D1C, (q31_t)0x80C7A80A, (q31_t)0xF21633C0,
+ (q31_t)0x80C22783, (q31_t)0xF2482C89, (q31_t)0x80BCBA9C,
+ (q31_t)0xF27A2770, (q31_t)0x80B76155, (q31_t)0xF2AC246D,
+ (q31_t)0x80B21BAF, (q31_t)0xF2DE2378, (q31_t)0x80ACE9AB,
+ (q31_t)0xF310248A, (q31_t)0x80A7CB49, (q31_t)0xF342279A,
+ (q31_t)0x80A2C08B, (q31_t)0xF3742CA1, (q31_t)0x809DC970,
+ (q31_t)0xF3A63398, (q31_t)0x8098E5FB, (q31_t)0xF3D83C76,
+ (q31_t)0x8094162B, (q31_t)0xF40A4734, (q31_t)0x808F5A02,
+ (q31_t)0xF43C53CA, (q31_t)0x808AB180, (q31_t)0xF46E6231,
+ (q31_t)0x80861CA5, (q31_t)0xF4A07260, (q31_t)0x80819B74,
+ (q31_t)0xF4D28451, (q31_t)0x807D2DEB, (q31_t)0xF50497FA,
+ (q31_t)0x8078D40D, (q31_t)0xF536AD55, (q31_t)0x80748DD9,
+ (q31_t)0xF568C45A, (q31_t)0x80705B50, (q31_t)0xF59ADD01,
+ (q31_t)0x806C3C73, (q31_t)0xF5CCF743, (q31_t)0x80683143,
+ (q31_t)0xF5FF1317, (q31_t)0x806439C0, (q31_t)0xF6313076,
+ (q31_t)0x806055EA, (q31_t)0xF6634F58, (q31_t)0x805C85C3,
+ (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF6C79188,
+ (q31_t)0x80552083, (q31_t)0xF6F9B4C5, (q31_t)0x80518B6B,
+ (q31_t)0xF72BD967, (q31_t)0x804E0A03, (q31_t)0xF75DFF65,
+ (q31_t)0x804A9C4D, (q31_t)0xF79026B8, (q31_t)0x80474248,
+ (q31_t)0xF7C24F58, (q31_t)0x8043FBF6, (q31_t)0xF7F4793E,
+ (q31_t)0x8040C956, (q31_t)0xF826A461, (q31_t)0x803DAA69,
+ (q31_t)0xF858D0BA, (q31_t)0x803A9F31, (q31_t)0xF88AFE41,
+ (q31_t)0x8037A7AC, (q31_t)0xF8BD2CEF, (q31_t)0x8034C3DC,
+ (q31_t)0xF8EF5CBB, (q31_t)0x8031F3C1, (q31_t)0xF9218D9E,
+ (q31_t)0x802F375C, (q31_t)0xF953BF90, (q31_t)0x802C8EAD,
+ (q31_t)0xF985F28A, (q31_t)0x8029F9B4, (q31_t)0xF9B82683,
+ (q31_t)0x80277872, (q31_t)0xF9EA5B75, (q31_t)0x80250AE7,
+ (q31_t)0xFA1C9156, (q31_t)0x8022B113, (q31_t)0xFA4EC820,
+ (q31_t)0x80206AF8, (q31_t)0xFA80FFCB, (q31_t)0x801E3894,
+ (q31_t)0xFAB3384F, (q31_t)0x801C19E9, (q31_t)0xFAE571A4,
+ (q31_t)0x801A0EF7, (q31_t)0xFB17ABC2, (q31_t)0x801817BF,
+ (q31_t)0xFB49E6A2, (q31_t)0x80163440, (q31_t)0xFB7C223C,
+ (q31_t)0x8014647A, (q31_t)0xFBAE5E89, (q31_t)0x8012A86F,
+ (q31_t)0xFBE09B80, (q31_t)0x8011001E, (q31_t)0xFC12D919,
+ (q31_t)0x800F6B88, (q31_t)0xFC45174E, (q31_t)0x800DEAAC,
+ (q31_t)0xFC775616, (q31_t)0x800C7D8C, (q31_t)0xFCA99569,
+ (q31_t)0x800B2427, (q31_t)0xFCDBD541, (q31_t)0x8009DE7D,
+ (q31_t)0xFD0E1594, (q31_t)0x8008AC90, (q31_t)0xFD40565B,
+ (q31_t)0x80078E5E, (q31_t)0xFD72978F, (q31_t)0x800683E8,
+ (q31_t)0xFDA4D928, (q31_t)0x80058D2E, (q31_t)0xFDD71B1E,
+ (q31_t)0x8004AA31, (q31_t)0xFE095D69, (q31_t)0x8003DAF0,
+ (q31_t)0xFE3BA001, (q31_t)0x80031F6C, (q31_t)0xFE6DE2E0,
+ (q31_t)0x800277A5, (q31_t)0xFEA025FC, (q31_t)0x8001E39B,
+ (q31_t)0xFED2694F, (q31_t)0x8001634D, (q31_t)0xFF04ACD0,
+ (q31_t)0x8000F6BD, (q31_t)0xFF36F078, (q31_t)0x80009DE9,
+ (q31_t)0xFF69343E, (q31_t)0x800058D3, (q31_t)0xFF9B781D,
+ (q31_t)0x8000277A, (q31_t)0xFFCDBC0A, (q31_t)0x800009DE
+};
+
+
+
+/*
+* @brief q15 Twiddle factors Table
+*/
+
+
+/**
+* \par
+* Example code for q15 Twiddle factors Generation::
+* \par
+* <pre>for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 16 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to q15(Fixed point 1.15):
+* round(twiddleCoefq15(i) * pow(2, 15))
+*
+*/
+const q15_t twiddleCoef_16_q15[24] = {
+ (q15_t)0x7FFF, (q15_t)0x0000,
+ (q15_t)0x7641, (q15_t)0x30FB,
+ (q15_t)0x5A82, (q15_t)0x5A82,
+ (q15_t)0x30FB, (q15_t)0x7641,
+ (q15_t)0x0000, (q15_t)0x7FFF,
+ (q15_t)0xCF04, (q15_t)0x7641,
+ (q15_t)0xA57D, (q15_t)0x5A82,
+ (q15_t)0x89BE, (q15_t)0x30FB,
+ (q15_t)0x8000, (q15_t)0x0000,
+ (q15_t)0x89BE, (q15_t)0xCF04,
+ (q15_t)0xA57D, (q15_t)0xA57D,
+ (q15_t)0xCF04, (q15_t)0x89BE
+};
+
+/**
+* \par
+* Example code for q15 Twiddle factors Generation::
+* \par
+* <pre>for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 32 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to q15(Fixed point 1.15):
+* round(twiddleCoefq15(i) * pow(2, 15))
+*
+*/
+const q15_t twiddleCoef_32_q15[48] = {
+ (q15_t)0x7FFF, (q15_t)0x0000,
+ (q15_t)0x7D8A, (q15_t)0x18F8,
+ (q15_t)0x7641, (q15_t)0x30FB,
+ (q15_t)0x6A6D, (q15_t)0x471C,
+ (q15_t)0x5A82, (q15_t)0x5A82,
+ (q15_t)0x471C, (q15_t)0x6A6D,
+ (q15_t)0x30FB, (q15_t)0x7641,
+ (q15_t)0x18F8, (q15_t)0x7D8A,
+ (q15_t)0x0000, (q15_t)0x7FFF,
+ (q15_t)0xE707, (q15_t)0x7D8A,
+ (q15_t)0xCF04, (q15_t)0x7641,
+ (q15_t)0xB8E3, (q15_t)0x6A6D,
+ (q15_t)0xA57D, (q15_t)0x5A82,
+ (q15_t)0x9592, (q15_t)0x471C,
+ (q15_t)0x89BE, (q15_t)0x30FB,
+ (q15_t)0x8275, (q15_t)0x18F8,
+ (q15_t)0x8000, (q15_t)0x0000,
+ (q15_t)0x8275, (q15_t)0xE707,
+ (q15_t)0x89BE, (q15_t)0xCF04,
+ (q15_t)0x9592, (q15_t)0xB8E3,
+ (q15_t)0xA57D, (q15_t)0xA57D,
+ (q15_t)0xB8E3, (q15_t)0x9592,
+ (q15_t)0xCF04, (q15_t)0x89BE,
+ (q15_t)0xE707, (q15_t)0x8275
+};
+
+/**
+* \par
+* Example code for q15 Twiddle factors Generation::
+* \par
+* <pre>for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 64 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to q15(Fixed point 1.15):
+* round(twiddleCoefq15(i) * pow(2, 15))
+*
+*/
+const q15_t twiddleCoef_64_q15[96] = {
+ (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7F62, (q15_t)0x0C8B,
+ (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7A7D, (q15_t)0x2528,
+ (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x70E2, (q15_t)0x3C56,
+ (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x62F2, (q15_t)0x5133,
+ (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x5133, (q15_t)0x62F2,
+ (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x3C56, (q15_t)0x70E2,
+ (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x2528, (q15_t)0x7A7D,
+ (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x0C8B, (q15_t)0x7F62,
+ (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xF374, (q15_t)0x7F62,
+ (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xDAD7, (q15_t)0x7A7D,
+ (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xC3A9, (q15_t)0x70E2,
+ (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xAECC, (q15_t)0x62F2,
+ (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0x9D0D, (q15_t)0x5133,
+ (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x8F1D, (q15_t)0x3C56,
+ (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x8582, (q15_t)0x2528,
+ (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x809D, (q15_t)0x0C8B,
+ (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x809D, (q15_t)0xF374,
+ (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x8582, (q15_t)0xDAD7,
+ (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8F1D, (q15_t)0xC3A9,
+ (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9D0D, (q15_t)0xAECC,
+ (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xAECC, (q15_t)0x9D0D,
+ (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xC3A9, (q15_t)0x8F1D,
+ (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xDAD7, (q15_t)0x8582,
+ (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xF374, (q15_t)0x809D
+};
+
+/**
+* \par
+* Example code for q15 Twiddle factors Generation::
+* \par
+* <pre>for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 128 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to q15(Fixed point 1.15):
+* round(twiddleCoefq15(i) * pow(2, 15))
+*
+*/
+const q15_t twiddleCoef_128_q15[192] = {
+ (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FD8, (q15_t)0x0647,
+ (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7E9D, (q15_t)0x12C8,
+ (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7C29, (q15_t)0x1F19,
+ (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7884, (q15_t)0x2B1F,
+ (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x73B5, (q15_t)0x36BA,
+ (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x6DCA, (q15_t)0x41CE,
+ (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x66CF, (q15_t)0x4C3F,
+ (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x5ED7, (q15_t)0x55F5,
+ (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x55F5, (q15_t)0x5ED7,
+ (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x4C3F, (q15_t)0x66CF,
+ (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x41CE, (q15_t)0x6DCA,
+ (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x36BA, (q15_t)0x73B5,
+ (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x2B1F, (q15_t)0x7884,
+ (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x1F19, (q15_t)0x7C29,
+ (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x12C8, (q15_t)0x7E9D,
+ (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x0647, (q15_t)0x7FD8,
+ (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xF9B8, (q15_t)0x7FD8,
+ (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xED37, (q15_t)0x7E9D,
+ (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE0E6, (q15_t)0x7C29,
+ (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xD4E0, (q15_t)0x7884,
+ (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xC945, (q15_t)0x73B5,
+ (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xBE31, (q15_t)0x6DCA,
+ (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB3C0, (q15_t)0x66CF,
+ (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAA0A, (q15_t)0x5ED7,
+ (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA128, (q15_t)0x55F5,
+ (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9930, (q15_t)0x4C3F,
+ (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x9235, (q15_t)0x41CE,
+ (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8C4A, (q15_t)0x36BA,
+ (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x877B, (q15_t)0x2B1F,
+ (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x83D6, (q15_t)0x1F19,
+ (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x8162, (q15_t)0x12C8,
+ (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x8027, (q15_t)0x0647,
+ (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8027, (q15_t)0xF9B8,
+ (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x8162, (q15_t)0xED37,
+ (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x83D6, (q15_t)0xE0E6,
+ (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x877B, (q15_t)0xD4E0,
+ (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8C4A, (q15_t)0xC945,
+ (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x9235, (q15_t)0xBE31,
+ (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9930, (q15_t)0xB3C0,
+ (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0xA128, (q15_t)0xAA0A,
+ (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xAA0A, (q15_t)0xA128,
+ (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xB3C0, (q15_t)0x9930,
+ (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xBE31, (q15_t)0x9235,
+ (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC945, (q15_t)0x8C4A,
+ (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xD4E0, (q15_t)0x877B,
+ (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xE0E6, (q15_t)0x83D6,
+ (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xED37, (q15_t)0x8162,
+ (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF9B8, (q15_t)0x8027
+};
+
+/**
+* \par
+* Example code for q15 Twiddle factors Generation::
+* \par
+* <pre>for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 256 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to q15(Fixed point 1.15):
+* round(twiddleCoefq15(i) * pow(2, 15))
+*
+*/
+const q15_t twiddleCoef_256_q15[384] = {
+ (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FF6, (q15_t)0x0324,
+ (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FA7, (q15_t)0x096A,
+ (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F09, (q15_t)0x0FAB,
+ (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E1D, (q15_t)0x15E2,
+ (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7CE3, (q15_t)0x1C0B,
+ (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7B5D, (q15_t)0x2223,
+ (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x798A, (q15_t)0x2826,
+ (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x776C, (q15_t)0x2E11,
+ (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x7504, (q15_t)0x33DE,
+ (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x7255, (q15_t)0x398C,
+ (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x6F5F, (q15_t)0x3F17,
+ (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6C24, (q15_t)0x447A,
+ (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x68A6, (q15_t)0x49B4,
+ (q15_t)0x66CF, (q15_t)0x4C3F, (q15_t)0x64E8, (q15_t)0x4EBF,
+ (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x60EC, (q15_t)0x539B,
+ (q15_t)0x5ED7, (q15_t)0x55F5, (q15_t)0x5CB4, (q15_t)0x5842,
+ (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x5842, (q15_t)0x5CB4,
+ (q15_t)0x55F5, (q15_t)0x5ED7, (q15_t)0x539B, (q15_t)0x60EC,
+ (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x4EBF, (q15_t)0x64E8,
+ (q15_t)0x4C3F, (q15_t)0x66CF, (q15_t)0x49B4, (q15_t)0x68A6,
+ (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x447A, (q15_t)0x6C24,
+ (q15_t)0x41CE, (q15_t)0x6DCA, (q15_t)0x3F17, (q15_t)0x6F5F,
+ (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x398C, (q15_t)0x7255,
+ (q15_t)0x36BA, (q15_t)0x73B5, (q15_t)0x33DE, (q15_t)0x7504,
+ (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x2E11, (q15_t)0x776C,
+ (q15_t)0x2B1F, (q15_t)0x7884, (q15_t)0x2826, (q15_t)0x798A,
+ (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x2223, (q15_t)0x7B5D,
+ (q15_t)0x1F19, (q15_t)0x7C29, (q15_t)0x1C0B, (q15_t)0x7CE3,
+ (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x15E2, (q15_t)0x7E1D,
+ (q15_t)0x12C8, (q15_t)0x7E9D, (q15_t)0x0FAB, (q15_t)0x7F09,
+ (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x096A, (q15_t)0x7FA7,
+ (q15_t)0x0647, (q15_t)0x7FD8, (q15_t)0x0324, (q15_t)0x7FF6,
+ (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xFCDB, (q15_t)0x7FF6,
+ (q15_t)0xF9B8, (q15_t)0x7FD8, (q15_t)0xF695, (q15_t)0x7FA7,
+ (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xF054, (q15_t)0x7F09,
+ (q15_t)0xED37, (q15_t)0x7E9D, (q15_t)0xEA1D, (q15_t)0x7E1D,
+ (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE3F4, (q15_t)0x7CE3,
+ (q15_t)0xE0E6, (q15_t)0x7C29, (q15_t)0xDDDC, (q15_t)0x7B5D,
+ (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xD7D9, (q15_t)0x798A,
+ (q15_t)0xD4E0, (q15_t)0x7884, (q15_t)0xD1EE, (q15_t)0x776C,
+ (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xCC21, (q15_t)0x7504,
+ (q15_t)0xC945, (q15_t)0x73B5, (q15_t)0xC673, (q15_t)0x7255,
+ (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xC0E8, (q15_t)0x6F5F,
+ (q15_t)0xBE31, (q15_t)0x6DCA, (q15_t)0xBB85, (q15_t)0x6C24,
+ (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB64B, (q15_t)0x68A6,
+ (q15_t)0xB3C0, (q15_t)0x66CF, (q15_t)0xB140, (q15_t)0x64E8,
+ (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAC64, (q15_t)0x60EC,
+ (q15_t)0xAA0A, (q15_t)0x5ED7, (q15_t)0xA7BD, (q15_t)0x5CB4,
+ (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA34B, (q15_t)0x5842,
+ (q15_t)0xA128, (q15_t)0x55F5, (q15_t)0x9F13, (q15_t)0x539B,
+ (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9B17, (q15_t)0x4EBF,
+ (q15_t)0x9930, (q15_t)0x4C3F, (q15_t)0x9759, (q15_t)0x49B4,
+ (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x93DB, (q15_t)0x447A,
+ (q15_t)0x9235, (q15_t)0x41CE, (q15_t)0x90A0, (q15_t)0x3F17,
+ (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8DAA, (q15_t)0x398C,
+ (q15_t)0x8C4A, (q15_t)0x36BA, (q15_t)0x8AFB, (q15_t)0x33DE,
+ (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x8893, (q15_t)0x2E11,
+ (q15_t)0x877B, (q15_t)0x2B1F, (q15_t)0x8675, (q15_t)0x2826,
+ (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x84A2, (q15_t)0x2223,
+ (q15_t)0x83D6, (q15_t)0x1F19, (q15_t)0x831C, (q15_t)0x1C0B,
+ (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x81E2, (q15_t)0x15E2,
+ (q15_t)0x8162, (q15_t)0x12C8, (q15_t)0x80F6, (q15_t)0x0FAB,
+ (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x8058, (q15_t)0x096A,
+ (q15_t)0x8027, (q15_t)0x0647, (q15_t)0x8009, (q15_t)0x0324,
+ (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8009, (q15_t)0xFCDB,
+ (q15_t)0x8027, (q15_t)0xF9B8, (q15_t)0x8058, (q15_t)0xF695,
+ (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x80F6, (q15_t)0xF054,
+ (q15_t)0x8162, (q15_t)0xED37, (q15_t)0x81E2, (q15_t)0xEA1D,
+ (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x831C, (q15_t)0xE3F4,
+ (q15_t)0x83D6, (q15_t)0xE0E6, (q15_t)0x84A2, (q15_t)0xDDDC,
+ (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x8675, (q15_t)0xD7D9,
+ (q15_t)0x877B, (q15_t)0xD4E0, (q15_t)0x8893, (q15_t)0xD1EE,
+ (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8AFB, (q15_t)0xCC21,
+ (q15_t)0x8C4A, (q15_t)0xC945, (q15_t)0x8DAA, (q15_t)0xC673,
+ (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x90A0, (q15_t)0xC0E8,
+ (q15_t)0x9235, (q15_t)0xBE31, (q15_t)0x93DB, (q15_t)0xBB85,
+ (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9759, (q15_t)0xB64B,
+ (q15_t)0x9930, (q15_t)0xB3C0, (q15_t)0x9B17, (q15_t)0xB140,
+ (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0x9F13, (q15_t)0xAC64,
+ (q15_t)0xA128, (q15_t)0xAA0A, (q15_t)0xA34B, (q15_t)0xA7BD,
+ (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xA7BD, (q15_t)0xA34B,
+ (q15_t)0xAA0A, (q15_t)0xA128, (q15_t)0xAC64, (q15_t)0x9F13,
+ (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xB140, (q15_t)0x9B17,
+ (q15_t)0xB3C0, (q15_t)0x9930, (q15_t)0xB64B, (q15_t)0x9759,
+ (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xBB85, (q15_t)0x93DB,
+ (q15_t)0xBE31, (q15_t)0x9235, (q15_t)0xC0E8, (q15_t)0x90A0,
+ (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC673, (q15_t)0x8DAA,
+ (q15_t)0xC945, (q15_t)0x8C4A, (q15_t)0xCC21, (q15_t)0x8AFB,
+ (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xD1EE, (q15_t)0x8893,
+ (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD7D9, (q15_t)0x8675,
+ (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDDDC, (q15_t)0x84A2,
+ (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE3F4, (q15_t)0x831C,
+ (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xEA1D, (q15_t)0x81E2,
+ (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xF054, (q15_t)0x80F6,
+ (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF695, (q15_t)0x8058,
+ (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xFCDB, (q15_t)0x8009
+};
+
+/**
+* \par
+* Example code for q15 Twiddle factors Generation::
+* \par
+* <pre>for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 512 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to q15(Fixed point 1.15):
+* round(twiddleCoefq15(i) * pow(2, 15))
+*
+*/
+const q15_t twiddleCoef_512_q15[768] = {
+ (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FFD, (q15_t)0x0192,
+ (q15_t)0x7FF6, (q15_t)0x0324, (q15_t)0x7FE9, (q15_t)0x04B6,
+ (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FC2, (q15_t)0x07D9,
+ (q15_t)0x7FA7, (q15_t)0x096A, (q15_t)0x7F87, (q15_t)0x0AFB,
+ (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F38, (q15_t)0x0E1B,
+ (q15_t)0x7F09, (q15_t)0x0FAB, (q15_t)0x7ED5, (q15_t)0x1139,
+ (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E5F, (q15_t)0x1455,
+ (q15_t)0x7E1D, (q15_t)0x15E2, (q15_t)0x7DD6, (q15_t)0x176D,
+ (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7D39, (q15_t)0x1A82,
+ (q15_t)0x7CE3, (q15_t)0x1C0B, (q15_t)0x7C89, (q15_t)0x1D93,
+ (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7BC5, (q15_t)0x209F,
+ (q15_t)0x7B5D, (q15_t)0x2223, (q15_t)0x7AEF, (q15_t)0x23A6,
+ (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7A05, (q15_t)0x26A8,
+ (q15_t)0x798A, (q15_t)0x2826, (q15_t)0x7909, (q15_t)0x29A3,
+ (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x77FA, (q15_t)0x2C98,
+ (q15_t)0x776C, (q15_t)0x2E11, (q15_t)0x76D9, (q15_t)0x2F87,
+ (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x75A5, (q15_t)0x326E,
+ (q15_t)0x7504, (q15_t)0x33DE, (q15_t)0x745F, (q15_t)0x354D,
+ (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x7307, (q15_t)0x3824,
+ (q15_t)0x7255, (q15_t)0x398C, (q15_t)0x719E, (q15_t)0x3AF2,
+ (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x7023, (q15_t)0x3DB8,
+ (q15_t)0x6F5F, (q15_t)0x3F17, (q15_t)0x6E96, (q15_t)0x4073,
+ (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6CF9, (q15_t)0x4325,
+ (q15_t)0x6C24, (q15_t)0x447A, (q15_t)0x6B4A, (q15_t)0x45CD,
+ (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x698C, (q15_t)0x4869,
+ (q15_t)0x68A6, (q15_t)0x49B4, (q15_t)0x67BD, (q15_t)0x4AFB,
+ (q15_t)0x66CF, (q15_t)0x4C3F, (q15_t)0x65DD, (q15_t)0x4D81,
+ (q15_t)0x64E8, (q15_t)0x4EBF, (q15_t)0x63EF, (q15_t)0x4FFB,
+ (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x61F1, (q15_t)0x5269,
+ (q15_t)0x60EC, (q15_t)0x539B, (q15_t)0x5FE3, (q15_t)0x54CA,
+ (q15_t)0x5ED7, (q15_t)0x55F5, (q15_t)0x5DC7, (q15_t)0x571D,
+ (q15_t)0x5CB4, (q15_t)0x5842, (q15_t)0x5B9D, (q15_t)0x5964,
+ (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x5964, (q15_t)0x5B9D,
+ (q15_t)0x5842, (q15_t)0x5CB4, (q15_t)0x571D, (q15_t)0x5DC7,
+ (q15_t)0x55F5, (q15_t)0x5ED7, (q15_t)0x54CA, (q15_t)0x5FE3,
+ (q15_t)0x539B, (q15_t)0x60EC, (q15_t)0x5269, (q15_t)0x61F1,
+ (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x4FFB, (q15_t)0x63EF,
+ (q15_t)0x4EBF, (q15_t)0x64E8, (q15_t)0x4D81, (q15_t)0x65DD,
+ (q15_t)0x4C3F, (q15_t)0x66CF, (q15_t)0x4AFB, (q15_t)0x67BD,
+ (q15_t)0x49B4, (q15_t)0x68A6, (q15_t)0x4869, (q15_t)0x698C,
+ (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x45CD, (q15_t)0x6B4A,
+ (q15_t)0x447A, (q15_t)0x6C24, (q15_t)0x4325, (q15_t)0x6CF9,
+ (q15_t)0x41CE, (q15_t)0x6DCA, (q15_t)0x4073, (q15_t)0x6E96,
+ (q15_t)0x3F17, (q15_t)0x6F5F, (q15_t)0x3DB8, (q15_t)0x7023,
+ (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x3AF2, (q15_t)0x719E,
+ (q15_t)0x398C, (q15_t)0x7255, (q15_t)0x3824, (q15_t)0x7307,
+ (q15_t)0x36BA, (q15_t)0x73B5, (q15_t)0x354D, (q15_t)0x745F,
+ (q15_t)0x33DE, (q15_t)0x7504, (q15_t)0x326E, (q15_t)0x75A5,
+ (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x2F87, (q15_t)0x76D9,
+ (q15_t)0x2E11, (q15_t)0x776C, (q15_t)0x2C98, (q15_t)0x77FA,
+ (q15_t)0x2B1F, (q15_t)0x7884, (q15_t)0x29A3, (q15_t)0x7909,
+ (q15_t)0x2826, (q15_t)0x798A, (q15_t)0x26A8, (q15_t)0x7A05,
+ (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x23A6, (q15_t)0x7AEF,
+ (q15_t)0x2223, (q15_t)0x7B5D, (q15_t)0x209F, (q15_t)0x7BC5,
+ (q15_t)0x1F19, (q15_t)0x7C29, (q15_t)0x1D93, (q15_t)0x7C89,
+ (q15_t)0x1C0B, (q15_t)0x7CE3, (q15_t)0x1A82, (q15_t)0x7D39,
+ (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x176D, (q15_t)0x7DD6,
+ (q15_t)0x15E2, (q15_t)0x7E1D, (q15_t)0x1455, (q15_t)0x7E5F,
+ (q15_t)0x12C8, (q15_t)0x7E9D, (q15_t)0x1139, (q15_t)0x7ED5,
+ (q15_t)0x0FAB, (q15_t)0x7F09, (q15_t)0x0E1B, (q15_t)0x7F38,
+ (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x0AFB, (q15_t)0x7F87,
+ (q15_t)0x096A, (q15_t)0x7FA7, (q15_t)0x07D9, (q15_t)0x7FC2,
+ (q15_t)0x0647, (q15_t)0x7FD8, (q15_t)0x04B6, (q15_t)0x7FE9,
+ (q15_t)0x0324, (q15_t)0x7FF6, (q15_t)0x0192, (q15_t)0x7FFD,
+ (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xFE6D, (q15_t)0x7FFD,
+ (q15_t)0xFCDB, (q15_t)0x7FF6, (q15_t)0xFB49, (q15_t)0x7FE9,
+ (q15_t)0xF9B8, (q15_t)0x7FD8, (q15_t)0xF826, (q15_t)0x7FC2,
+ (q15_t)0xF695, (q15_t)0x7FA7, (q15_t)0xF504, (q15_t)0x7F87,
+ (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xF1E4, (q15_t)0x7F38,
+ (q15_t)0xF054, (q15_t)0x7F09, (q15_t)0xEEC6, (q15_t)0x7ED5,
+ (q15_t)0xED37, (q15_t)0x7E9D, (q15_t)0xEBAA, (q15_t)0x7E5F,
+ (q15_t)0xEA1D, (q15_t)0x7E1D, (q15_t)0xE892, (q15_t)0x7DD6,
+ (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE57D, (q15_t)0x7D39,
+ (q15_t)0xE3F4, (q15_t)0x7CE3, (q15_t)0xE26C, (q15_t)0x7C89,
+ (q15_t)0xE0E6, (q15_t)0x7C29, (q15_t)0xDF60, (q15_t)0x7BC5,
+ (q15_t)0xDDDC, (q15_t)0x7B5D, (q15_t)0xDC59, (q15_t)0x7AEF,
+ (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xD957, (q15_t)0x7A05,
+ (q15_t)0xD7D9, (q15_t)0x798A, (q15_t)0xD65C, (q15_t)0x7909,
+ (q15_t)0xD4E0, (q15_t)0x7884, (q15_t)0xD367, (q15_t)0x77FA,
+ (q15_t)0xD1EE, (q15_t)0x776C, (q15_t)0xD078, (q15_t)0x76D9,
+ (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xCD91, (q15_t)0x75A5,
+ (q15_t)0xCC21, (q15_t)0x7504, (q15_t)0xCAB2, (q15_t)0x745F,
+ (q15_t)0xC945, (q15_t)0x73B5, (q15_t)0xC7DB, (q15_t)0x7307,
+ (q15_t)0xC673, (q15_t)0x7255, (q15_t)0xC50D, (q15_t)0x719E,
+ (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xC247, (q15_t)0x7023,
+ (q15_t)0xC0E8, (q15_t)0x6F5F, (q15_t)0xBF8C, (q15_t)0x6E96,
+ (q15_t)0xBE31, (q15_t)0x6DCA, (q15_t)0xBCDA, (q15_t)0x6CF9,
+ (q15_t)0xBB85, (q15_t)0x6C24, (q15_t)0xBA32, (q15_t)0x6B4A,
+ (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB796, (q15_t)0x698C,
+ (q15_t)0xB64B, (q15_t)0x68A6, (q15_t)0xB504, (q15_t)0x67BD,
+ (q15_t)0xB3C0, (q15_t)0x66CF, (q15_t)0xB27E, (q15_t)0x65DD,
+ (q15_t)0xB140, (q15_t)0x64E8, (q15_t)0xB004, (q15_t)0x63EF,
+ (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAD96, (q15_t)0x61F1,
+ (q15_t)0xAC64, (q15_t)0x60EC, (q15_t)0xAB35, (q15_t)0x5FE3,
+ (q15_t)0xAA0A, (q15_t)0x5ED7, (q15_t)0xA8E2, (q15_t)0x5DC7,
+ (q15_t)0xA7BD, (q15_t)0x5CB4, (q15_t)0xA69B, (q15_t)0x5B9D,
+ (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA462, (q15_t)0x5964,
+ (q15_t)0xA34B, (q15_t)0x5842, (q15_t)0xA238, (q15_t)0x571D,
+ (q15_t)0xA128, (q15_t)0x55F5, (q15_t)0xA01C, (q15_t)0x54CA,
+ (q15_t)0x9F13, (q15_t)0x539B, (q15_t)0x9E0E, (q15_t)0x5269,
+ (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9C10, (q15_t)0x4FFB,
+ (q15_t)0x9B17, (q15_t)0x4EBF, (q15_t)0x9A22, (q15_t)0x4D81,
+ (q15_t)0x9930, (q15_t)0x4C3F, (q15_t)0x9842, (q15_t)0x4AFB,
+ (q15_t)0x9759, (q15_t)0x49B4, (q15_t)0x9673, (q15_t)0x4869,
+ (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x94B5, (q15_t)0x45CD,
+ (q15_t)0x93DB, (q15_t)0x447A, (q15_t)0x9306, (q15_t)0x4325,
+ (q15_t)0x9235, (q15_t)0x41CE, (q15_t)0x9169, (q15_t)0x4073,
+ (q15_t)0x90A0, (q15_t)0x3F17, (q15_t)0x8FDC, (q15_t)0x3DB8,
+ (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8E61, (q15_t)0x3AF2,
+ (q15_t)0x8DAA, (q15_t)0x398C, (q15_t)0x8CF8, (q15_t)0x3824,
+ (q15_t)0x8C4A, (q15_t)0x36BA, (q15_t)0x8BA0, (q15_t)0x354D,
+ (q15_t)0x8AFB, (q15_t)0x33DE, (q15_t)0x8A5A, (q15_t)0x326E,
+ (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x8926, (q15_t)0x2F87,
+ (q15_t)0x8893, (q15_t)0x2E11, (q15_t)0x8805, (q15_t)0x2C98,
+ (q15_t)0x877B, (q15_t)0x2B1F, (q15_t)0x86F6, (q15_t)0x29A3,
+ (q15_t)0x8675, (q15_t)0x2826, (q15_t)0x85FA, (q15_t)0x26A8,
+ (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x8510, (q15_t)0x23A6,
+ (q15_t)0x84A2, (q15_t)0x2223, (q15_t)0x843A, (q15_t)0x209F,
+ (q15_t)0x83D6, (q15_t)0x1F19, (q15_t)0x8376, (q15_t)0x1D93,
+ (q15_t)0x831C, (q15_t)0x1C0B, (q15_t)0x82C6, (q15_t)0x1A82,
+ (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x8229, (q15_t)0x176D,
+ (q15_t)0x81E2, (q15_t)0x15E2, (q15_t)0x81A0, (q15_t)0x1455,
+ (q15_t)0x8162, (q15_t)0x12C8, (q15_t)0x812A, (q15_t)0x1139,
+ (q15_t)0x80F6, (q15_t)0x0FAB, (q15_t)0x80C7, (q15_t)0x0E1B,
+ (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x8078, (q15_t)0x0AFB,
+ (q15_t)0x8058, (q15_t)0x096A, (q15_t)0x803D, (q15_t)0x07D9,
+ (q15_t)0x8027, (q15_t)0x0647, (q15_t)0x8016, (q15_t)0x04B6,
+ (q15_t)0x8009, (q15_t)0x0324, (q15_t)0x8002, (q15_t)0x0192,
+ (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8002, (q15_t)0xFE6D,
+ (q15_t)0x8009, (q15_t)0xFCDB, (q15_t)0x8016, (q15_t)0xFB49,
+ (q15_t)0x8027, (q15_t)0xF9B8, (q15_t)0x803D, (q15_t)0xF826,
+ (q15_t)0x8058, (q15_t)0xF695, (q15_t)0x8078, (q15_t)0xF504,
+ (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x80C7, (q15_t)0xF1E4,
+ (q15_t)0x80F6, (q15_t)0xF054, (q15_t)0x812A, (q15_t)0xEEC6,
+ (q15_t)0x8162, (q15_t)0xED37, (q15_t)0x81A0, (q15_t)0xEBAA,
+ (q15_t)0x81E2, (q15_t)0xEA1D, (q15_t)0x8229, (q15_t)0xE892,
+ (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x82C6, (q15_t)0xE57D,
+ (q15_t)0x831C, (q15_t)0xE3F4, (q15_t)0x8376, (q15_t)0xE26C,
+ (q15_t)0x83D6, (q15_t)0xE0E6, (q15_t)0x843A, (q15_t)0xDF60,
+ (q15_t)0x84A2, (q15_t)0xDDDC, (q15_t)0x8510, (q15_t)0xDC59,
+ (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x85FA, (q15_t)0xD957,
+ (q15_t)0x8675, (q15_t)0xD7D9, (q15_t)0x86F6, (q15_t)0xD65C,
+ (q15_t)0x877B, (q15_t)0xD4E0, (q15_t)0x8805, (q15_t)0xD367,
+ (q15_t)0x8893, (q15_t)0xD1EE, (q15_t)0x8926, (q15_t)0xD078,
+ (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8A5A, (q15_t)0xCD91,
+ (q15_t)0x8AFB, (q15_t)0xCC21, (q15_t)0x8BA0, (q15_t)0xCAB2,
+ (q15_t)0x8C4A, (q15_t)0xC945, (q15_t)0x8CF8, (q15_t)0xC7DB,
+ (q15_t)0x8DAA, (q15_t)0xC673, (q15_t)0x8E61, (q15_t)0xC50D,
+ (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x8FDC, (q15_t)0xC247,
+ (q15_t)0x90A0, (q15_t)0xC0E8, (q15_t)0x9169, (q15_t)0xBF8C,
+ (q15_t)0x9235, (q15_t)0xBE31, (q15_t)0x9306, (q15_t)0xBCDA,
+ (q15_t)0x93DB, (q15_t)0xBB85, (q15_t)0x94B5, (q15_t)0xBA32,
+ (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9673, (q15_t)0xB796,
+ (q15_t)0x9759, (q15_t)0xB64B, (q15_t)0x9842, (q15_t)0xB504,
+ (q15_t)0x9930, (q15_t)0xB3C0, (q15_t)0x9A22, (q15_t)0xB27E,
+ (q15_t)0x9B17, (q15_t)0xB140, (q15_t)0x9C10, (q15_t)0xB004,
+ (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0x9E0E, (q15_t)0xAD96,
+ (q15_t)0x9F13, (q15_t)0xAC64, (q15_t)0xA01C, (q15_t)0xAB35,
+ (q15_t)0xA128, (q15_t)0xAA0A, (q15_t)0xA238, (q15_t)0xA8E2,
+ (q15_t)0xA34B, (q15_t)0xA7BD, (q15_t)0xA462, (q15_t)0xA69B,
+ (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xA69B, (q15_t)0xA462,
+ (q15_t)0xA7BD, (q15_t)0xA34B, (q15_t)0xA8E2, (q15_t)0xA238,
+ (q15_t)0xAA0A, (q15_t)0xA128, (q15_t)0xAB35, (q15_t)0xA01C,
+ (q15_t)0xAC64, (q15_t)0x9F13, (q15_t)0xAD96, (q15_t)0x9E0E,
+ (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xB004, (q15_t)0x9C10,
+ (q15_t)0xB140, (q15_t)0x9B17, (q15_t)0xB27E, (q15_t)0x9A22,
+ (q15_t)0xB3C0, (q15_t)0x9930, (q15_t)0xB504, (q15_t)0x9842,
+ (q15_t)0xB64B, (q15_t)0x9759, (q15_t)0xB796, (q15_t)0x9673,
+ (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xBA32, (q15_t)0x94B5,
+ (q15_t)0xBB85, (q15_t)0x93DB, (q15_t)0xBCDA, (q15_t)0x9306,
+ (q15_t)0xBE31, (q15_t)0x9235, (q15_t)0xBF8C, (q15_t)0x9169,
+ (q15_t)0xC0E8, (q15_t)0x90A0, (q15_t)0xC247, (q15_t)0x8FDC,
+ (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC50D, (q15_t)0x8E61,
+ (q15_t)0xC673, (q15_t)0x8DAA, (q15_t)0xC7DB, (q15_t)0x8CF8,
+ (q15_t)0xC945, (q15_t)0x8C4A, (q15_t)0xCAB2, (q15_t)0x8BA0,
+ (q15_t)0xCC21, (q15_t)0x8AFB, (q15_t)0xCD91, (q15_t)0x8A5A,
+ (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xD078, (q15_t)0x8926,
+ (q15_t)0xD1EE, (q15_t)0x8893, (q15_t)0xD367, (q15_t)0x8805,
+ (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD65C, (q15_t)0x86F6,
+ (q15_t)0xD7D9, (q15_t)0x8675, (q15_t)0xD957, (q15_t)0x85FA,
+ (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDC59, (q15_t)0x8510,
+ (q15_t)0xDDDC, (q15_t)0x84A2, (q15_t)0xDF60, (q15_t)0x843A,
+ (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE26C, (q15_t)0x8376,
+ (q15_t)0xE3F4, (q15_t)0x831C, (q15_t)0xE57D, (q15_t)0x82C6,
+ (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xE892, (q15_t)0x8229,
+ (q15_t)0xEA1D, (q15_t)0x81E2, (q15_t)0xEBAA, (q15_t)0x81A0,
+ (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xEEC6, (q15_t)0x812A,
+ (q15_t)0xF054, (q15_t)0x80F6, (q15_t)0xF1E4, (q15_t)0x80C7,
+ (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF504, (q15_t)0x8078,
+ (q15_t)0xF695, (q15_t)0x8058, (q15_t)0xF826, (q15_t)0x803D,
+ (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xFB49, (q15_t)0x8016,
+ (q15_t)0xFCDB, (q15_t)0x8009, (q15_t)0xFE6D, (q15_t)0x8002
+};
+
+/**
+* \par
+* Example code for q15 Twiddle factors Generation::
+* \par
+* <pre>for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 1024 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to q15(Fixed point 1.15):
+* round(twiddleCoefq15(i) * pow(2, 15))
+*
+*/
+const q15_t twiddleCoef_1024_q15[1536] = {
+ (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0x00C9,
+ (q15_t)0x7FFD, (q15_t)0x0192, (q15_t)0x7FFA, (q15_t)0x025B,
+ (q15_t)0x7FF6, (q15_t)0x0324, (q15_t)0x7FF0, (q15_t)0x03ED,
+ (q15_t)0x7FE9, (q15_t)0x04B6, (q15_t)0x7FE1, (q15_t)0x057F,
+ (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FCE, (q15_t)0x0710,
+ (q15_t)0x7FC2, (q15_t)0x07D9, (q15_t)0x7FB5, (q15_t)0x08A2,
+ (q15_t)0x7FA7, (q15_t)0x096A, (q15_t)0x7F97, (q15_t)0x0A33,
+ (q15_t)0x7F87, (q15_t)0x0AFB, (q15_t)0x7F75, (q15_t)0x0BC3,
+ (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F4D, (q15_t)0x0D53,
+ (q15_t)0x7F38, (q15_t)0x0E1B, (q15_t)0x7F21, (q15_t)0x0EE3,
+ (q15_t)0x7F09, (q15_t)0x0FAB, (q15_t)0x7EF0, (q15_t)0x1072,
+ (q15_t)0x7ED5, (q15_t)0x1139, (q15_t)0x7EBA, (q15_t)0x1201,
+ (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E7F, (q15_t)0x138E,
+ (q15_t)0x7E5F, (q15_t)0x1455, (q15_t)0x7E3F, (q15_t)0x151B,
+ (q15_t)0x7E1D, (q15_t)0x15E2, (q15_t)0x7DFA, (q15_t)0x16A8,
+ (q15_t)0x7DD6, (q15_t)0x176D, (q15_t)0x7DB0, (q15_t)0x1833,
+ (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7D62, (q15_t)0x19BD,
+ (q15_t)0x7D39, (q15_t)0x1A82, (q15_t)0x7D0F, (q15_t)0x1B47,
+ (q15_t)0x7CE3, (q15_t)0x1C0B, (q15_t)0x7CB7, (q15_t)0x1CCF,
+ (q15_t)0x7C89, (q15_t)0x1D93, (q15_t)0x7C5A, (q15_t)0x1E56,
+ (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7BF8, (q15_t)0x1FDC,
+ (q15_t)0x7BC5, (q15_t)0x209F, (q15_t)0x7B92, (q15_t)0x2161,
+ (q15_t)0x7B5D, (q15_t)0x2223, (q15_t)0x7B26, (q15_t)0x22E5,
+ (q15_t)0x7AEF, (q15_t)0x23A6, (q15_t)0x7AB6, (q15_t)0x2467,
+ (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7A42, (q15_t)0x25E8,
+ (q15_t)0x7A05, (q15_t)0x26A8, (q15_t)0x79C8, (q15_t)0x2767,
+ (q15_t)0x798A, (q15_t)0x2826, (q15_t)0x794A, (q15_t)0x28E5,
+ (q15_t)0x7909, (q15_t)0x29A3, (q15_t)0x78C7, (q15_t)0x2A61,
+ (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x7840, (q15_t)0x2BDC,
+ (q15_t)0x77FA, (q15_t)0x2C98, (q15_t)0x77B4, (q15_t)0x2D55,
+ (q15_t)0x776C, (q15_t)0x2E11, (q15_t)0x7723, (q15_t)0x2ECC,
+ (q15_t)0x76D9, (q15_t)0x2F87, (q15_t)0x768E, (q15_t)0x3041,
+ (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x75F4, (q15_t)0x31B5,
+ (q15_t)0x75A5, (q15_t)0x326E, (q15_t)0x7555, (q15_t)0x3326,
+ (q15_t)0x7504, (q15_t)0x33DE, (q15_t)0x74B2, (q15_t)0x3496,
+ (q15_t)0x745F, (q15_t)0x354D, (q15_t)0x740B, (q15_t)0x3604,
+ (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x735F, (q15_t)0x376F,
+ (q15_t)0x7307, (q15_t)0x3824, (q15_t)0x72AF, (q15_t)0x38D8,
+ (q15_t)0x7255, (q15_t)0x398C, (q15_t)0x71FA, (q15_t)0x3A40,
+ (q15_t)0x719E, (q15_t)0x3AF2, (q15_t)0x7141, (q15_t)0x3BA5,
+ (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x7083, (q15_t)0x3D07,
+ (q15_t)0x7023, (q15_t)0x3DB8, (q15_t)0x6FC1, (q15_t)0x3E68,
+ (q15_t)0x6F5F, (q15_t)0x3F17, (q15_t)0x6EFB, (q15_t)0x3FC5,
+ (q15_t)0x6E96, (q15_t)0x4073, (q15_t)0x6E30, (q15_t)0x4121,
+ (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6D62, (q15_t)0x427A,
+ (q15_t)0x6CF9, (q15_t)0x4325, (q15_t)0x6C8F, (q15_t)0x43D0,
+ (q15_t)0x6C24, (q15_t)0x447A, (q15_t)0x6BB8, (q15_t)0x4524,
+ (q15_t)0x6B4A, (q15_t)0x45CD, (q15_t)0x6ADC, (q15_t)0x4675,
+ (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x69FD, (q15_t)0x47C3,
+ (q15_t)0x698C, (q15_t)0x4869, (q15_t)0x6919, (q15_t)0x490F,
+ (q15_t)0x68A6, (q15_t)0x49B4, (q15_t)0x6832, (q15_t)0x4A58,
+ (q15_t)0x67BD, (q15_t)0x4AFB, (q15_t)0x6746, (q15_t)0x4B9E,
+ (q15_t)0x66CF, (q15_t)0x4C3F, (q15_t)0x6657, (q15_t)0x4CE1,
+ (q15_t)0x65DD, (q15_t)0x4D81, (q15_t)0x6563, (q15_t)0x4E21,
+ (q15_t)0x64E8, (q15_t)0x4EBF, (q15_t)0x646C, (q15_t)0x4F5E,
+ (q15_t)0x63EF, (q15_t)0x4FFB, (q15_t)0x6371, (q15_t)0x5097,
+ (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x6271, (q15_t)0x51CE,
+ (q15_t)0x61F1, (q15_t)0x5269, (q15_t)0x616F, (q15_t)0x5302,
+ (q15_t)0x60EC, (q15_t)0x539B, (q15_t)0x6068, (q15_t)0x5433,
+ (q15_t)0x5FE3, (q15_t)0x54CA, (q15_t)0x5F5E, (q15_t)0x5560,
+ (q15_t)0x5ED7, (q15_t)0x55F5, (q15_t)0x5E50, (q15_t)0x568A,
+ (q15_t)0x5DC7, (q15_t)0x571D, (q15_t)0x5D3E, (q15_t)0x57B0,
+ (q15_t)0x5CB4, (q15_t)0x5842, (q15_t)0x5C29, (q15_t)0x58D4,
+ (q15_t)0x5B9D, (q15_t)0x5964, (q15_t)0x5B10, (q15_t)0x59F3,
+ (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x59F3, (q15_t)0x5B10,
+ (q15_t)0x5964, (q15_t)0x5B9D, (q15_t)0x58D4, (q15_t)0x5C29,
+ (q15_t)0x5842, (q15_t)0x5CB4, (q15_t)0x57B0, (q15_t)0x5D3E,
+ (q15_t)0x571D, (q15_t)0x5DC7, (q15_t)0x568A, (q15_t)0x5E50,
+ (q15_t)0x55F5, (q15_t)0x5ED7, (q15_t)0x5560, (q15_t)0x5F5E,
+ (q15_t)0x54CA, (q15_t)0x5FE3, (q15_t)0x5433, (q15_t)0x6068,
+ (q15_t)0x539B, (q15_t)0x60EC, (q15_t)0x5302, (q15_t)0x616F,
+ (q15_t)0x5269, (q15_t)0x61F1, (q15_t)0x51CE, (q15_t)0x6271,
+ (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x5097, (q15_t)0x6371,
+ (q15_t)0x4FFB, (q15_t)0x63EF, (q15_t)0x4F5E, (q15_t)0x646C,
+ (q15_t)0x4EBF, (q15_t)0x64E8, (q15_t)0x4E21, (q15_t)0x6563,
+ (q15_t)0x4D81, (q15_t)0x65DD, (q15_t)0x4CE1, (q15_t)0x6657,
+ (q15_t)0x4C3F, (q15_t)0x66CF, (q15_t)0x4B9E, (q15_t)0x6746,
+ (q15_t)0x4AFB, (q15_t)0x67BD, (q15_t)0x4A58, (q15_t)0x6832,
+ (q15_t)0x49B4, (q15_t)0x68A6, (q15_t)0x490F, (q15_t)0x6919,
+ (q15_t)0x4869, (q15_t)0x698C, (q15_t)0x47C3, (q15_t)0x69FD,
+ (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x4675, (q15_t)0x6ADC,
+ (q15_t)0x45CD, (q15_t)0x6B4A, (q15_t)0x4524, (q15_t)0x6BB8,
+ (q15_t)0x447A, (q15_t)0x6C24, (q15_t)0x43D0, (q15_t)0x6C8F,
+ (q15_t)0x4325, (q15_t)0x6CF9, (q15_t)0x427A, (q15_t)0x6D62,
+ (q15_t)0x41CE, (q15_t)0x6DCA, (q15_t)0x4121, (q15_t)0x6E30,
+ (q15_t)0x4073, (q15_t)0x6E96, (q15_t)0x3FC5, (q15_t)0x6EFB,
+ (q15_t)0x3F17, (q15_t)0x6F5F, (q15_t)0x3E68, (q15_t)0x6FC1,
+ (q15_t)0x3DB8, (q15_t)0x7023, (q15_t)0x3D07, (q15_t)0x7083,
+ (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x3BA5, (q15_t)0x7141,
+ (q15_t)0x3AF2, (q15_t)0x719E, (q15_t)0x3A40, (q15_t)0x71FA,
+ (q15_t)0x398C, (q15_t)0x7255, (q15_t)0x38D8, (q15_t)0x72AF,
+ (q15_t)0x3824, (q15_t)0x7307, (q15_t)0x376F, (q15_t)0x735F,
+ (q15_t)0x36BA, (q15_t)0x73B5, (q15_t)0x3604, (q15_t)0x740B,
+ (q15_t)0x354D, (q15_t)0x745F, (q15_t)0x3496, (q15_t)0x74B2,
+ (q15_t)0x33DE, (q15_t)0x7504, (q15_t)0x3326, (q15_t)0x7555,
+ (q15_t)0x326E, (q15_t)0x75A5, (q15_t)0x31B5, (q15_t)0x75F4,
+ (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x3041, (q15_t)0x768E,
+ (q15_t)0x2F87, (q15_t)0x76D9, (q15_t)0x2ECC, (q15_t)0x7723,
+ (q15_t)0x2E11, (q15_t)0x776C, (q15_t)0x2D55, (q15_t)0x77B4,
+ (q15_t)0x2C98, (q15_t)0x77FA, (q15_t)0x2BDC, (q15_t)0x7840,
+ (q15_t)0x2B1F, (q15_t)0x7884, (q15_t)0x2A61, (q15_t)0x78C7,
+ (q15_t)0x29A3, (q15_t)0x7909, (q15_t)0x28E5, (q15_t)0x794A,
+ (q15_t)0x2826, (q15_t)0x798A, (q15_t)0x2767, (q15_t)0x79C8,
+ (q15_t)0x26A8, (q15_t)0x7A05, (q15_t)0x25E8, (q15_t)0x7A42,
+ (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x2467, (q15_t)0x7AB6,
+ (q15_t)0x23A6, (q15_t)0x7AEF, (q15_t)0x22E5, (q15_t)0x7B26,
+ (q15_t)0x2223, (q15_t)0x7B5D, (q15_t)0x2161, (q15_t)0x7B92,
+ (q15_t)0x209F, (q15_t)0x7BC5, (q15_t)0x1FDC, (q15_t)0x7BF8,
+ (q15_t)0x1F19, (q15_t)0x7C29, (q15_t)0x1E56, (q15_t)0x7C5A,
+ (q15_t)0x1D93, (q15_t)0x7C89, (q15_t)0x1CCF, (q15_t)0x7CB7,
+ (q15_t)0x1C0B, (q15_t)0x7CE3, (q15_t)0x1B47, (q15_t)0x7D0F,
+ (q15_t)0x1A82, (q15_t)0x7D39, (q15_t)0x19BD, (q15_t)0x7D62,
+ (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x1833, (q15_t)0x7DB0,
+ (q15_t)0x176D, (q15_t)0x7DD6, (q15_t)0x16A8, (q15_t)0x7DFA,
+ (q15_t)0x15E2, (q15_t)0x7E1D, (q15_t)0x151B, (q15_t)0x7E3F,
+ (q15_t)0x1455, (q15_t)0x7E5F, (q15_t)0x138E, (q15_t)0x7E7F,
+ (q15_t)0x12C8, (q15_t)0x7E9D, (q15_t)0x1201, (q15_t)0x7EBA,
+ (q15_t)0x1139, (q15_t)0x7ED5, (q15_t)0x1072, (q15_t)0x7EF0,
+ (q15_t)0x0FAB, (q15_t)0x7F09, (q15_t)0x0EE3, (q15_t)0x7F21,
+ (q15_t)0x0E1B, (q15_t)0x7F38, (q15_t)0x0D53, (q15_t)0x7F4D,
+ (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x0BC3, (q15_t)0x7F75,
+ (q15_t)0x0AFB, (q15_t)0x7F87, (q15_t)0x0A33, (q15_t)0x7F97,
+ (q15_t)0x096A, (q15_t)0x7FA7, (q15_t)0x08A2, (q15_t)0x7FB5,
+ (q15_t)0x07D9, (q15_t)0x7FC2, (q15_t)0x0710, (q15_t)0x7FCE,
+ (q15_t)0x0647, (q15_t)0x7FD8, (q15_t)0x057F, (q15_t)0x7FE1,
+ (q15_t)0x04B6, (q15_t)0x7FE9, (q15_t)0x03ED, (q15_t)0x7FF0,
+ (q15_t)0x0324, (q15_t)0x7FF6, (q15_t)0x025B, (q15_t)0x7FFA,
+ (q15_t)0x0192, (q15_t)0x7FFD, (q15_t)0x00C9, (q15_t)0x7FFF,
+ (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xFF36, (q15_t)0x7FFF,
+ (q15_t)0xFE6D, (q15_t)0x7FFD, (q15_t)0xFDA4, (q15_t)0x7FFA,
+ (q15_t)0xFCDB, (q15_t)0x7FF6, (q15_t)0xFC12, (q15_t)0x7FF0,
+ (q15_t)0xFB49, (q15_t)0x7FE9, (q15_t)0xFA80, (q15_t)0x7FE1,
+ (q15_t)0xF9B8, (q15_t)0x7FD8, (q15_t)0xF8EF, (q15_t)0x7FCE,
+ (q15_t)0xF826, (q15_t)0x7FC2, (q15_t)0xF75D, (q15_t)0x7FB5,
+ (q15_t)0xF695, (q15_t)0x7FA7, (q15_t)0xF5CC, (q15_t)0x7F97,
+ (q15_t)0xF504, (q15_t)0x7F87, (q15_t)0xF43C, (q15_t)0x7F75,
+ (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xF2AC, (q15_t)0x7F4D,
+ (q15_t)0xF1E4, (q15_t)0x7F38, (q15_t)0xF11C, (q15_t)0x7F21,
+ (q15_t)0xF054, (q15_t)0x7F09, (q15_t)0xEF8D, (q15_t)0x7EF0,
+ (q15_t)0xEEC6, (q15_t)0x7ED5, (q15_t)0xEDFE, (q15_t)0x7EBA,
+ (q15_t)0xED37, (q15_t)0x7E9D, (q15_t)0xEC71, (q15_t)0x7E7F,
+ (q15_t)0xEBAA, (q15_t)0x7E5F, (q15_t)0xEAE4, (q15_t)0x7E3F,
+ (q15_t)0xEA1D, (q15_t)0x7E1D, (q15_t)0xE957, (q15_t)0x7DFA,
+ (q15_t)0xE892, (q15_t)0x7DD6, (q15_t)0xE7CC, (q15_t)0x7DB0,
+ (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE642, (q15_t)0x7D62,
+ (q15_t)0xE57D, (q15_t)0x7D39, (q15_t)0xE4B8, (q15_t)0x7D0F,
+ (q15_t)0xE3F4, (q15_t)0x7CE3, (q15_t)0xE330, (q15_t)0x7CB7,
+ (q15_t)0xE26C, (q15_t)0x7C89, (q15_t)0xE1A9, (q15_t)0x7C5A,
+ (q15_t)0xE0E6, (q15_t)0x7C29, (q15_t)0xE023, (q15_t)0x7BF8,
+ (q15_t)0xDF60, (q15_t)0x7BC5, (q15_t)0xDE9E, (q15_t)0x7B92,
+ (q15_t)0xDDDC, (q15_t)0x7B5D, (q15_t)0xDD1A, (q15_t)0x7B26,
+ (q15_t)0xDC59, (q15_t)0x7AEF, (q15_t)0xDB98, (q15_t)0x7AB6,
+ (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xDA17, (q15_t)0x7A42,
+ (q15_t)0xD957, (q15_t)0x7A05, (q15_t)0xD898, (q15_t)0x79C8,
+ (q15_t)0xD7D9, (q15_t)0x798A, (q15_t)0xD71A, (q15_t)0x794A,
+ (q15_t)0xD65C, (q15_t)0x7909, (q15_t)0xD59E, (q15_t)0x78C7,
+ (q15_t)0xD4E0, (q15_t)0x7884, (q15_t)0xD423, (q15_t)0x7840,
+ (q15_t)0xD367, (q15_t)0x77FA, (q15_t)0xD2AA, (q15_t)0x77B4,
+ (q15_t)0xD1EE, (q15_t)0x776C, (q15_t)0xD133, (q15_t)0x7723,
+ (q15_t)0xD078, (q15_t)0x76D9, (q15_t)0xCFBE, (q15_t)0x768E,
+ (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xCE4A, (q15_t)0x75F4,
+ (q15_t)0xCD91, (q15_t)0x75A5, (q15_t)0xCCD9, (q15_t)0x7555,
+ (q15_t)0xCC21, (q15_t)0x7504, (q15_t)0xCB69, (q15_t)0x74B2,
+ (q15_t)0xCAB2, (q15_t)0x745F, (q15_t)0xC9FB, (q15_t)0x740B,
+ (q15_t)0xC945, (q15_t)0x73B5, (q15_t)0xC890, (q15_t)0x735F,
+ (q15_t)0xC7DB, (q15_t)0x7307, (q15_t)0xC727, (q15_t)0x72AF,
+ (q15_t)0xC673, (q15_t)0x7255, (q15_t)0xC5BF, (q15_t)0x71FA,
+ (q15_t)0xC50D, (q15_t)0x719E, (q15_t)0xC45A, (q15_t)0x7141,
+ (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xC2F8, (q15_t)0x7083,
+ (q15_t)0xC247, (q15_t)0x7023, (q15_t)0xC197, (q15_t)0x6FC1,
+ (q15_t)0xC0E8, (q15_t)0x6F5F, (q15_t)0xC03A, (q15_t)0x6EFB,
+ (q15_t)0xBF8C, (q15_t)0x6E96, (q15_t)0xBEDE, (q15_t)0x6E30,
+ (q15_t)0xBE31, (q15_t)0x6DCA, (q15_t)0xBD85, (q15_t)0x6D62,
+ (q15_t)0xBCDA, (q15_t)0x6CF9, (q15_t)0xBC2F, (q15_t)0x6C8F,
+ (q15_t)0xBB85, (q15_t)0x6C24, (q15_t)0xBADB, (q15_t)0x6BB8,
+ (q15_t)0xBA32, (q15_t)0x6B4A, (q15_t)0xB98A, (q15_t)0x6ADC,
+ (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB83C, (q15_t)0x69FD,
+ (q15_t)0xB796, (q15_t)0x698C, (q15_t)0xB6F0, (q15_t)0x6919,
+ (q15_t)0xB64B, (q15_t)0x68A6, (q15_t)0xB5A7, (q15_t)0x6832,
+ (q15_t)0xB504, (q15_t)0x67BD, (q15_t)0xB461, (q15_t)0x6746,
+ (q15_t)0xB3C0, (q15_t)0x66CF, (q15_t)0xB31E, (q15_t)0x6657,
+ (q15_t)0xB27E, (q15_t)0x65DD, (q15_t)0xB1DE, (q15_t)0x6563,
+ (q15_t)0xB140, (q15_t)0x64E8, (q15_t)0xB0A1, (q15_t)0x646C,
+ (q15_t)0xB004, (q15_t)0x63EF, (q15_t)0xAF68, (q15_t)0x6371,
+ (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAE31, (q15_t)0x6271,
+ (q15_t)0xAD96, (q15_t)0x61F1, (q15_t)0xACFD, (q15_t)0x616F,
+ (q15_t)0xAC64, (q15_t)0x60EC, (q15_t)0xABCC, (q15_t)0x6068,
+ (q15_t)0xAB35, (q15_t)0x5FE3, (q15_t)0xAA9F, (q15_t)0x5F5E,
+ (q15_t)0xAA0A, (q15_t)0x5ED7, (q15_t)0xA975, (q15_t)0x5E50,
+ (q15_t)0xA8E2, (q15_t)0x5DC7, (q15_t)0xA84F, (q15_t)0x5D3E,
+ (q15_t)0xA7BD, (q15_t)0x5CB4, (q15_t)0xA72B, (q15_t)0x5C29,
+ (q15_t)0xA69B, (q15_t)0x5B9D, (q15_t)0xA60C, (q15_t)0x5B10,
+ (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA4EF, (q15_t)0x59F3,
+ (q15_t)0xA462, (q15_t)0x5964, (q15_t)0xA3D6, (q15_t)0x58D4,
+ (q15_t)0xA34B, (q15_t)0x5842, (q15_t)0xA2C1, (q15_t)0x57B0,
+ (q15_t)0xA238, (q15_t)0x571D, (q15_t)0xA1AF, (q15_t)0x568A,
+ (q15_t)0xA128, (q15_t)0x55F5, (q15_t)0xA0A1, (q15_t)0x5560,
+ (q15_t)0xA01C, (q15_t)0x54CA, (q15_t)0x9F97, (q15_t)0x5433,
+ (q15_t)0x9F13, (q15_t)0x539B, (q15_t)0x9E90, (q15_t)0x5302,
+ (q15_t)0x9E0E, (q15_t)0x5269, (q15_t)0x9D8E, (q15_t)0x51CE,
+ (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9C8E, (q15_t)0x5097,
+ (q15_t)0x9C10, (q15_t)0x4FFB, (q15_t)0x9B93, (q15_t)0x4F5E,
+ (q15_t)0x9B17, (q15_t)0x4EBF, (q15_t)0x9A9C, (q15_t)0x4E21,
+ (q15_t)0x9A22, (q15_t)0x4D81, (q15_t)0x99A8, (q15_t)0x4CE1,
+ (q15_t)0x9930, (q15_t)0x4C3F, (q15_t)0x98B9, (q15_t)0x4B9E,
+ (q15_t)0x9842, (q15_t)0x4AFB, (q15_t)0x97CD, (q15_t)0x4A58,
+ (q15_t)0x9759, (q15_t)0x49B4, (q15_t)0x96E6, (q15_t)0x490F,
+ (q15_t)0x9673, (q15_t)0x4869, (q15_t)0x9602, (q15_t)0x47C3,
+ (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x9523, (q15_t)0x4675,
+ (q15_t)0x94B5, (q15_t)0x45CD, (q15_t)0x9447, (q15_t)0x4524,
+ (q15_t)0x93DB, (q15_t)0x447A, (q15_t)0x9370, (q15_t)0x43D0,
+ (q15_t)0x9306, (q15_t)0x4325, (q15_t)0x929D, (q15_t)0x427A,
+ (q15_t)0x9235, (q15_t)0x41CE, (q15_t)0x91CF, (q15_t)0x4121,
+ (q15_t)0x9169, (q15_t)0x4073, (q15_t)0x9104, (q15_t)0x3FC5,
+ (q15_t)0x90A0, (q15_t)0x3F17, (q15_t)0x903E, (q15_t)0x3E68,
+ (q15_t)0x8FDC, (q15_t)0x3DB8, (q15_t)0x8F7C, (q15_t)0x3D07,
+ (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8EBE, (q15_t)0x3BA5,
+ (q15_t)0x8E61, (q15_t)0x3AF2, (q15_t)0x8E05, (q15_t)0x3A40,
+ (q15_t)0x8DAA, (q15_t)0x398C, (q15_t)0x8D50, (q15_t)0x38D8,
+ (q15_t)0x8CF8, (q15_t)0x3824, (q15_t)0x8CA0, (q15_t)0x376F,
+ (q15_t)0x8C4A, (q15_t)0x36BA, (q15_t)0x8BF4, (q15_t)0x3604,
+ (q15_t)0x8BA0, (q15_t)0x354D, (q15_t)0x8B4D, (q15_t)0x3496,
+ (q15_t)0x8AFB, (q15_t)0x33DE, (q15_t)0x8AAA, (q15_t)0x3326,
+ (q15_t)0x8A5A, (q15_t)0x326E, (q15_t)0x8A0B, (q15_t)0x31B5,
+ (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x8971, (q15_t)0x3041,
+ (q15_t)0x8926, (q15_t)0x2F87, (q15_t)0x88DC, (q15_t)0x2ECC,
+ (q15_t)0x8893, (q15_t)0x2E11, (q15_t)0x884B, (q15_t)0x2D55,
+ (q15_t)0x8805, (q15_t)0x2C98, (q15_t)0x87BF, (q15_t)0x2BDC,
+ (q15_t)0x877B, (q15_t)0x2B1F, (q15_t)0x8738, (q15_t)0x2A61,
+ (q15_t)0x86F6, (q15_t)0x29A3, (q15_t)0x86B5, (q15_t)0x28E5,
+ (q15_t)0x8675, (q15_t)0x2826, (q15_t)0x8637, (q15_t)0x2767,
+ (q15_t)0x85FA, (q15_t)0x26A8, (q15_t)0x85BD, (q15_t)0x25E8,
+ (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x8549, (q15_t)0x2467,
+ (q15_t)0x8510, (q15_t)0x23A6, (q15_t)0x84D9, (q15_t)0x22E5,
+ (q15_t)0x84A2, (q15_t)0x2223, (q15_t)0x846D, (q15_t)0x2161,
+ (q15_t)0x843A, (q15_t)0x209F, (q15_t)0x8407, (q15_t)0x1FDC,
+ (q15_t)0x83D6, (q15_t)0x1F19, (q15_t)0x83A5, (q15_t)0x1E56,
+ (q15_t)0x8376, (q15_t)0x1D93, (q15_t)0x8348, (q15_t)0x1CCF,
+ (q15_t)0x831C, (q15_t)0x1C0B, (q15_t)0x82F0, (q15_t)0x1B47,
+ (q15_t)0x82C6, (q15_t)0x1A82, (q15_t)0x829D, (q15_t)0x19BD,
+ (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x824F, (q15_t)0x1833,
+ (q15_t)0x8229, (q15_t)0x176D, (q15_t)0x8205, (q15_t)0x16A8,
+ (q15_t)0x81E2, (q15_t)0x15E2, (q15_t)0x81C0, (q15_t)0x151B,
+ (q15_t)0x81A0, (q15_t)0x1455, (q15_t)0x8180, (q15_t)0x138E,
+ (q15_t)0x8162, (q15_t)0x12C8, (q15_t)0x8145, (q15_t)0x1201,
+ (q15_t)0x812A, (q15_t)0x1139, (q15_t)0x810F, (q15_t)0x1072,
+ (q15_t)0x80F6, (q15_t)0x0FAB, (q15_t)0x80DE, (q15_t)0x0EE3,
+ (q15_t)0x80C7, (q15_t)0x0E1B, (q15_t)0x80B2, (q15_t)0x0D53,
+ (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x808A, (q15_t)0x0BC3,
+ (q15_t)0x8078, (q15_t)0x0AFB, (q15_t)0x8068, (q15_t)0x0A33,
+ (q15_t)0x8058, (q15_t)0x096A, (q15_t)0x804A, (q15_t)0x08A2,
+ (q15_t)0x803D, (q15_t)0x07D9, (q15_t)0x8031, (q15_t)0x0710,
+ (q15_t)0x8027, (q15_t)0x0647, (q15_t)0x801E, (q15_t)0x057F,
+ (q15_t)0x8016, (q15_t)0x04B6, (q15_t)0x800F, (q15_t)0x03ED,
+ (q15_t)0x8009, (q15_t)0x0324, (q15_t)0x8005, (q15_t)0x025B,
+ (q15_t)0x8002, (q15_t)0x0192, (q15_t)0x8000, (q15_t)0x00C9,
+ (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8000, (q15_t)0xFF36,
+ (q15_t)0x8002, (q15_t)0xFE6D, (q15_t)0x8005, (q15_t)0xFDA4,
+ (q15_t)0x8009, (q15_t)0xFCDB, (q15_t)0x800F, (q15_t)0xFC12,
+ (q15_t)0x8016, (q15_t)0xFB49, (q15_t)0x801E, (q15_t)0xFA80,
+ (q15_t)0x8027, (q15_t)0xF9B8, (q15_t)0x8031, (q15_t)0xF8EF,
+ (q15_t)0x803D, (q15_t)0xF826, (q15_t)0x804A, (q15_t)0xF75D,
+ (q15_t)0x8058, (q15_t)0xF695, (q15_t)0x8068, (q15_t)0xF5CC,
+ (q15_t)0x8078, (q15_t)0xF504, (q15_t)0x808A, (q15_t)0xF43C,
+ (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x80B2, (q15_t)0xF2AC,
+ (q15_t)0x80C7, (q15_t)0xF1E4, (q15_t)0x80DE, (q15_t)0xF11C,
+ (q15_t)0x80F6, (q15_t)0xF054, (q15_t)0x810F, (q15_t)0xEF8D,
+ (q15_t)0x812A, (q15_t)0xEEC6, (q15_t)0x8145, (q15_t)0xEDFE,
+ (q15_t)0x8162, (q15_t)0xED37, (q15_t)0x8180, (q15_t)0xEC71,
+ (q15_t)0x81A0, (q15_t)0xEBAA, (q15_t)0x81C0, (q15_t)0xEAE4,
+ (q15_t)0x81E2, (q15_t)0xEA1D, (q15_t)0x8205, (q15_t)0xE957,
+ (q15_t)0x8229, (q15_t)0xE892, (q15_t)0x824F, (q15_t)0xE7CC,
+ (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x829D, (q15_t)0xE642,
+ (q15_t)0x82C6, (q15_t)0xE57D, (q15_t)0x82F0, (q15_t)0xE4B8,
+ (q15_t)0x831C, (q15_t)0xE3F4, (q15_t)0x8348, (q15_t)0xE330,
+ (q15_t)0x8376, (q15_t)0xE26C, (q15_t)0x83A5, (q15_t)0xE1A9,
+ (q15_t)0x83D6, (q15_t)0xE0E6, (q15_t)0x8407, (q15_t)0xE023,
+ (q15_t)0x843A, (q15_t)0xDF60, (q15_t)0x846D, (q15_t)0xDE9E,
+ (q15_t)0x84A2, (q15_t)0xDDDC, (q15_t)0x84D9, (q15_t)0xDD1A,
+ (q15_t)0x8510, (q15_t)0xDC59, (q15_t)0x8549, (q15_t)0xDB98,
+ (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x85BD, (q15_t)0xDA17,
+ (q15_t)0x85FA, (q15_t)0xD957, (q15_t)0x8637, (q15_t)0xD898,
+ (q15_t)0x8675, (q15_t)0xD7D9, (q15_t)0x86B5, (q15_t)0xD71A,
+ (q15_t)0x86F6, (q15_t)0xD65C, (q15_t)0x8738, (q15_t)0xD59E,
+ (q15_t)0x877B, (q15_t)0xD4E0, (q15_t)0x87BF, (q15_t)0xD423,
+ (q15_t)0x8805, (q15_t)0xD367, (q15_t)0x884B, (q15_t)0xD2AA,
+ (q15_t)0x8893, (q15_t)0xD1EE, (q15_t)0x88DC, (q15_t)0xD133,
+ (q15_t)0x8926, (q15_t)0xD078, (q15_t)0x8971, (q15_t)0xCFBE,
+ (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8A0B, (q15_t)0xCE4A,
+ (q15_t)0x8A5A, (q15_t)0xCD91, (q15_t)0x8AAA, (q15_t)0xCCD9,
+ (q15_t)0x8AFB, (q15_t)0xCC21, (q15_t)0x8B4D, (q15_t)0xCB69,
+ (q15_t)0x8BA0, (q15_t)0xCAB2, (q15_t)0x8BF4, (q15_t)0xC9FB,
+ (q15_t)0x8C4A, (q15_t)0xC945, (q15_t)0x8CA0, (q15_t)0xC890,
+ (q15_t)0x8CF8, (q15_t)0xC7DB, (q15_t)0x8D50, (q15_t)0xC727,
+ (q15_t)0x8DAA, (q15_t)0xC673, (q15_t)0x8E05, (q15_t)0xC5BF,
+ (q15_t)0x8E61, (q15_t)0xC50D, (q15_t)0x8EBE, (q15_t)0xC45A,
+ (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x8F7C, (q15_t)0xC2F8,
+ (q15_t)0x8FDC, (q15_t)0xC247, (q15_t)0x903E, (q15_t)0xC197,
+ (q15_t)0x90A0, (q15_t)0xC0E8, (q15_t)0x9104, (q15_t)0xC03A,
+ (q15_t)0x9169, (q15_t)0xBF8C, (q15_t)0x91CF, (q15_t)0xBEDE,
+ (q15_t)0x9235, (q15_t)0xBE31, (q15_t)0x929D, (q15_t)0xBD85,
+ (q15_t)0x9306, (q15_t)0xBCDA, (q15_t)0x9370, (q15_t)0xBC2F,
+ (q15_t)0x93DB, (q15_t)0xBB85, (q15_t)0x9447, (q15_t)0xBADB,
+ (q15_t)0x94B5, (q15_t)0xBA32, (q15_t)0x9523, (q15_t)0xB98A,
+ (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9602, (q15_t)0xB83C,
+ (q15_t)0x9673, (q15_t)0xB796, (q15_t)0x96E6, (q15_t)0xB6F0,
+ (q15_t)0x9759, (q15_t)0xB64B, (q15_t)0x97CD, (q15_t)0xB5A7,
+ (q15_t)0x9842, (q15_t)0xB504, (q15_t)0x98B9, (q15_t)0xB461,
+ (q15_t)0x9930, (q15_t)0xB3C0, (q15_t)0x99A8, (q15_t)0xB31E,
+ (q15_t)0x9A22, (q15_t)0xB27E, (q15_t)0x9A9C, (q15_t)0xB1DE,
+ (q15_t)0x9B17, (q15_t)0xB140, (q15_t)0x9B93, (q15_t)0xB0A1,
+ (q15_t)0x9C10, (q15_t)0xB004, (q15_t)0x9C8E, (q15_t)0xAF68,
+ (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0x9D8E, (q15_t)0xAE31,
+ (q15_t)0x9E0E, (q15_t)0xAD96, (q15_t)0x9E90, (q15_t)0xACFD,
+ (q15_t)0x9F13, (q15_t)0xAC64, (q15_t)0x9F97, (q15_t)0xABCC,
+ (q15_t)0xA01C, (q15_t)0xAB35, (q15_t)0xA0A1, (q15_t)0xAA9F,
+ (q15_t)0xA128, (q15_t)0xAA0A, (q15_t)0xA1AF, (q15_t)0xA975,
+ (q15_t)0xA238, (q15_t)0xA8E2, (q15_t)0xA2C1, (q15_t)0xA84F,
+ (q15_t)0xA34B, (q15_t)0xA7BD, (q15_t)0xA3D6, (q15_t)0xA72B,
+ (q15_t)0xA462, (q15_t)0xA69B, (q15_t)0xA4EF, (q15_t)0xA60C,
+ (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xA60C, (q15_t)0xA4EF,
+ (q15_t)0xA69B, (q15_t)0xA462, (q15_t)0xA72B, (q15_t)0xA3D6,
+ (q15_t)0xA7BD, (q15_t)0xA34B, (q15_t)0xA84F, (q15_t)0xA2C1,
+ (q15_t)0xA8E2, (q15_t)0xA238, (q15_t)0xA975, (q15_t)0xA1AF,
+ (q15_t)0xAA0A, (q15_t)0xA128, (q15_t)0xAA9F, (q15_t)0xA0A1,
+ (q15_t)0xAB35, (q15_t)0xA01C, (q15_t)0xABCC, (q15_t)0x9F97,
+ (q15_t)0xAC64, (q15_t)0x9F13, (q15_t)0xACFD, (q15_t)0x9E90,
+ (q15_t)0xAD96, (q15_t)0x9E0E, (q15_t)0xAE31, (q15_t)0x9D8E,
+ (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xAF68, (q15_t)0x9C8E,
+ (q15_t)0xB004, (q15_t)0x9C10, (q15_t)0xB0A1, (q15_t)0x9B93,
+ (q15_t)0xB140, (q15_t)0x9B17, (q15_t)0xB1DE, (q15_t)0x9A9C,
+ (q15_t)0xB27E, (q15_t)0x9A22, (q15_t)0xB31E, (q15_t)0x99A8,
+ (q15_t)0xB3C0, (q15_t)0x9930, (q15_t)0xB461, (q15_t)0x98B9,
+ (q15_t)0xB504, (q15_t)0x9842, (q15_t)0xB5A7, (q15_t)0x97CD,
+ (q15_t)0xB64B, (q15_t)0x9759, (q15_t)0xB6F0, (q15_t)0x96E6,
+ (q15_t)0xB796, (q15_t)0x9673, (q15_t)0xB83C, (q15_t)0x9602,
+ (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xB98A, (q15_t)0x9523,
+ (q15_t)0xBA32, (q15_t)0x94B5, (q15_t)0xBADB, (q15_t)0x9447,
+ (q15_t)0xBB85, (q15_t)0x93DB, (q15_t)0xBC2F, (q15_t)0x9370,
+ (q15_t)0xBCDA, (q15_t)0x9306, (q15_t)0xBD85, (q15_t)0x929D,
+ (q15_t)0xBE31, (q15_t)0x9235, (q15_t)0xBEDE, (q15_t)0x91CF,
+ (q15_t)0xBF8C, (q15_t)0x9169, (q15_t)0xC03A, (q15_t)0x9104,
+ (q15_t)0xC0E8, (q15_t)0x90A0, (q15_t)0xC197, (q15_t)0x903E,
+ (q15_t)0xC247, (q15_t)0x8FDC, (q15_t)0xC2F8, (q15_t)0x8F7C,
+ (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC45A, (q15_t)0x8EBE,
+ (q15_t)0xC50D, (q15_t)0x8E61, (q15_t)0xC5BF, (q15_t)0x8E05,
+ (q15_t)0xC673, (q15_t)0x8DAA, (q15_t)0xC727, (q15_t)0x8D50,
+ (q15_t)0xC7DB, (q15_t)0x8CF8, (q15_t)0xC890, (q15_t)0x8CA0,
+ (q15_t)0xC945, (q15_t)0x8C4A, (q15_t)0xC9FB, (q15_t)0x8BF4,
+ (q15_t)0xCAB2, (q15_t)0x8BA0, (q15_t)0xCB69, (q15_t)0x8B4D,
+ (q15_t)0xCC21, (q15_t)0x8AFB, (q15_t)0xCCD9, (q15_t)0x8AAA,
+ (q15_t)0xCD91, (q15_t)0x8A5A, (q15_t)0xCE4A, (q15_t)0x8A0B,
+ (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xCFBE, (q15_t)0x8971,
+ (q15_t)0xD078, (q15_t)0x8926, (q15_t)0xD133, (q15_t)0x88DC,
+ (q15_t)0xD1EE, (q15_t)0x8893, (q15_t)0xD2AA, (q15_t)0x884B,
+ (q15_t)0xD367, (q15_t)0x8805, (q15_t)0xD423, (q15_t)0x87BF,
+ (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD59E, (q15_t)0x8738,
+ (q15_t)0xD65C, (q15_t)0x86F6, (q15_t)0xD71A, (q15_t)0x86B5,
+ (q15_t)0xD7D9, (q15_t)0x8675, (q15_t)0xD898, (q15_t)0x8637,
+ (q15_t)0xD957, (q15_t)0x85FA, (q15_t)0xDA17, (q15_t)0x85BD,
+ (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDB98, (q15_t)0x8549,
+ (q15_t)0xDC59, (q15_t)0x8510, (q15_t)0xDD1A, (q15_t)0x84D9,
+ (q15_t)0xDDDC, (q15_t)0x84A2, (q15_t)0xDE9E, (q15_t)0x846D,
+ (q15_t)0xDF60, (q15_t)0x843A, (q15_t)0xE023, (q15_t)0x8407,
+ (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE1A9, (q15_t)0x83A5,
+ (q15_t)0xE26C, (q15_t)0x8376, (q15_t)0xE330, (q15_t)0x8348,
+ (q15_t)0xE3F4, (q15_t)0x831C, (q15_t)0xE4B8, (q15_t)0x82F0,
+ (q15_t)0xE57D, (q15_t)0x82C6, (q15_t)0xE642, (q15_t)0x829D,
+ (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xE7CC, (q15_t)0x824F,
+ (q15_t)0xE892, (q15_t)0x8229, (q15_t)0xE957, (q15_t)0x8205,
+ (q15_t)0xEA1D, (q15_t)0x81E2, (q15_t)0xEAE4, (q15_t)0x81C0,
+ (q15_t)0xEBAA, (q15_t)0x81A0, (q15_t)0xEC71, (q15_t)0x8180,
+ (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xEDFE, (q15_t)0x8145,
+ (q15_t)0xEEC6, (q15_t)0x812A, (q15_t)0xEF8D, (q15_t)0x810F,
+ (q15_t)0xF054, (q15_t)0x80F6, (q15_t)0xF11C, (q15_t)0x80DE,
+ (q15_t)0xF1E4, (q15_t)0x80C7, (q15_t)0xF2AC, (q15_t)0x80B2,
+ (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF43C, (q15_t)0x808A,
+ (q15_t)0xF504, (q15_t)0x8078, (q15_t)0xF5CC, (q15_t)0x8068,
+ (q15_t)0xF695, (q15_t)0x8058, (q15_t)0xF75D, (q15_t)0x804A,
+ (q15_t)0xF826, (q15_t)0x803D, (q15_t)0xF8EF, (q15_t)0x8031,
+ (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xFA80, (q15_t)0x801E,
+ (q15_t)0xFB49, (q15_t)0x8016, (q15_t)0xFC12, (q15_t)0x800F,
+ (q15_t)0xFCDB, (q15_t)0x8009, (q15_t)0xFDA4, (q15_t)0x8005,
+ (q15_t)0xFE6D, (q15_t)0x8002, (q15_t)0xFF36, (q15_t)0x8000
+};
+
+/**
+* \par
+* Example code for q15 Twiddle factors Generation::
+* \par
+* <pre>for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 2048 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to q15(Fixed point 1.15):
+* round(twiddleCoefq15(i) * pow(2, 15))
+*
+*/
+const q15_t twiddleCoef_2048_q15[3072] = {
+ (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0x0064,
+ (q15_t)0x7FFF, (q15_t)0x00C9, (q15_t)0x7FFE, (q15_t)0x012D,
+ (q15_t)0x7FFD, (q15_t)0x0192, (q15_t)0x7FFC, (q15_t)0x01F6,
+ (q15_t)0x7FFA, (q15_t)0x025B, (q15_t)0x7FF8, (q15_t)0x02BF,
+ (q15_t)0x7FF6, (q15_t)0x0324, (q15_t)0x7FF3, (q15_t)0x0388,
+ (q15_t)0x7FF0, (q15_t)0x03ED, (q15_t)0x7FED, (q15_t)0x0451,
+ (q15_t)0x7FE9, (q15_t)0x04B6, (q15_t)0x7FE5, (q15_t)0x051A,
+ (q15_t)0x7FE1, (q15_t)0x057F, (q15_t)0x7FDD, (q15_t)0x05E3,
+ (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FD3, (q15_t)0x06AC,
+ (q15_t)0x7FCE, (q15_t)0x0710, (q15_t)0x7FC8, (q15_t)0x0775,
+ (q15_t)0x7FC2, (q15_t)0x07D9, (q15_t)0x7FBC, (q15_t)0x083D,
+ (q15_t)0x7FB5, (q15_t)0x08A2, (q15_t)0x7FAE, (q15_t)0x0906,
+ (q15_t)0x7FA7, (q15_t)0x096A, (q15_t)0x7F9F, (q15_t)0x09CE,
+ (q15_t)0x7F97, (q15_t)0x0A33, (q15_t)0x7F8F, (q15_t)0x0A97,
+ (q15_t)0x7F87, (q15_t)0x0AFB, (q15_t)0x7F7E, (q15_t)0x0B5F,
+ (q15_t)0x7F75, (q15_t)0x0BC3, (q15_t)0x7F6B, (q15_t)0x0C27,
+ (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F58, (q15_t)0x0CEF,
+ (q15_t)0x7F4D, (q15_t)0x0D53, (q15_t)0x7F43, (q15_t)0x0DB7,
+ (q15_t)0x7F38, (q15_t)0x0E1B, (q15_t)0x7F2D, (q15_t)0x0E7F,
+ (q15_t)0x7F21, (q15_t)0x0EE3, (q15_t)0x7F15, (q15_t)0x0F47,
+ (q15_t)0x7F09, (q15_t)0x0FAB, (q15_t)0x7EFD, (q15_t)0x100E,
+ (q15_t)0x7EF0, (q15_t)0x1072, (q15_t)0x7EE3, (q15_t)0x10D6,
+ (q15_t)0x7ED5, (q15_t)0x1139, (q15_t)0x7EC8, (q15_t)0x119D,
+ (q15_t)0x7EBA, (q15_t)0x1201, (q15_t)0x7EAB, (q15_t)0x1264,
+ (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E8E, (q15_t)0x132B,
+ (q15_t)0x7E7F, (q15_t)0x138E, (q15_t)0x7E6F, (q15_t)0x13F2,
+ (q15_t)0x7E5F, (q15_t)0x1455, (q15_t)0x7E4F, (q15_t)0x14B8,
+ (q15_t)0x7E3F, (q15_t)0x151B, (q15_t)0x7E2E, (q15_t)0x157F,
+ (q15_t)0x7E1D, (q15_t)0x15E2, (q15_t)0x7E0C, (q15_t)0x1645,
+ (q15_t)0x7DFA, (q15_t)0x16A8, (q15_t)0x7DE8, (q15_t)0x170A,
+ (q15_t)0x7DD6, (q15_t)0x176D, (q15_t)0x7DC3, (q15_t)0x17D0,
+ (q15_t)0x7DB0, (q15_t)0x1833, (q15_t)0x7D9D, (q15_t)0x1896,
+ (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7D76, (q15_t)0x195B,
+ (q15_t)0x7D62, (q15_t)0x19BD, (q15_t)0x7D4E, (q15_t)0x1A20,
+ (q15_t)0x7D39, (q15_t)0x1A82, (q15_t)0x7D24, (q15_t)0x1AE4,
+ (q15_t)0x7D0F, (q15_t)0x1B47, (q15_t)0x7CF9, (q15_t)0x1BA9,
+ (q15_t)0x7CE3, (q15_t)0x1C0B, (q15_t)0x7CCD, (q15_t)0x1C6D,
+ (q15_t)0x7CB7, (q15_t)0x1CCF, (q15_t)0x7CA0, (q15_t)0x1D31,
+ (q15_t)0x7C89, (q15_t)0x1D93, (q15_t)0x7C71, (q15_t)0x1DF5,
+ (q15_t)0x7C5A, (q15_t)0x1E56, (q15_t)0x7C42, (q15_t)0x1EB8,
+ (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7C11, (q15_t)0x1F7B,
+ (q15_t)0x7BF8, (q15_t)0x1FDC, (q15_t)0x7BDF, (q15_t)0x203E,
+ (q15_t)0x7BC5, (q15_t)0x209F, (q15_t)0x7BAC, (q15_t)0x2100,
+ (q15_t)0x7B92, (q15_t)0x2161, (q15_t)0x7B77, (q15_t)0x21C2,
+ (q15_t)0x7B5D, (q15_t)0x2223, (q15_t)0x7B42, (q15_t)0x2284,
+ (q15_t)0x7B26, (q15_t)0x22E5, (q15_t)0x7B0B, (q15_t)0x2345,
+ (q15_t)0x7AEF, (q15_t)0x23A6, (q15_t)0x7AD3, (q15_t)0x2407,
+ (q15_t)0x7AB6, (q15_t)0x2467, (q15_t)0x7A9A, (q15_t)0x24C7,
+ (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7A5F, (q15_t)0x2588,
+ (q15_t)0x7A42, (q15_t)0x25E8, (q15_t)0x7A24, (q15_t)0x2648,
+ (q15_t)0x7A05, (q15_t)0x26A8, (q15_t)0x79E7, (q15_t)0x2707,
+ (q15_t)0x79C8, (q15_t)0x2767, (q15_t)0x79A9, (q15_t)0x27C7,
+ (q15_t)0x798A, (q15_t)0x2826, (q15_t)0x796A, (q15_t)0x2886,
+ (q15_t)0x794A, (q15_t)0x28E5, (q15_t)0x792A, (q15_t)0x2944,
+ (q15_t)0x7909, (q15_t)0x29A3, (q15_t)0x78E8, (q15_t)0x2A02,
+ (q15_t)0x78C7, (q15_t)0x2A61, (q15_t)0x78A6, (q15_t)0x2AC0,
+ (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x7862, (q15_t)0x2B7D,
+ (q15_t)0x7840, (q15_t)0x2BDC, (q15_t)0x781D, (q15_t)0x2C3A,
+ (q15_t)0x77FA, (q15_t)0x2C98, (q15_t)0x77D7, (q15_t)0x2CF7,
+ (q15_t)0x77B4, (q15_t)0x2D55, (q15_t)0x7790, (q15_t)0x2DB3,
+ (q15_t)0x776C, (q15_t)0x2E11, (q15_t)0x7747, (q15_t)0x2E6E,
+ (q15_t)0x7723, (q15_t)0x2ECC, (q15_t)0x76FE, (q15_t)0x2F29,
+ (q15_t)0x76D9, (q15_t)0x2F87, (q15_t)0x76B3, (q15_t)0x2FE4,
+ (q15_t)0x768E, (q15_t)0x3041, (q15_t)0x7668, (q15_t)0x309E,
+ (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x761B, (q15_t)0x3158,
+ (q15_t)0x75F4, (q15_t)0x31B5, (q15_t)0x75CC, (q15_t)0x3211,
+ (q15_t)0x75A5, (q15_t)0x326E, (q15_t)0x757D, (q15_t)0x32CA,
+ (q15_t)0x7555, (q15_t)0x3326, (q15_t)0x752D, (q15_t)0x3382,
+ (q15_t)0x7504, (q15_t)0x33DE, (q15_t)0x74DB, (q15_t)0x343A,
+ (q15_t)0x74B2, (q15_t)0x3496, (q15_t)0x7489, (q15_t)0x34F2,
+ (q15_t)0x745F, (q15_t)0x354D, (q15_t)0x7435, (q15_t)0x35A8,
+ (q15_t)0x740B, (q15_t)0x3604, (q15_t)0x73E0, (q15_t)0x365F,
+ (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x738A, (q15_t)0x3714,
+ (q15_t)0x735F, (q15_t)0x376F, (q15_t)0x7333, (q15_t)0x37CA,
+ (q15_t)0x7307, (q15_t)0x3824, (q15_t)0x72DB, (q15_t)0x387E,
+ (q15_t)0x72AF, (q15_t)0x38D8, (q15_t)0x7282, (q15_t)0x3932,
+ (q15_t)0x7255, (q15_t)0x398C, (q15_t)0x7227, (q15_t)0x39E6,
+ (q15_t)0x71FA, (q15_t)0x3A40, (q15_t)0x71CC, (q15_t)0x3A99,
+ (q15_t)0x719E, (q15_t)0x3AF2, (q15_t)0x716F, (q15_t)0x3B4C,
+ (q15_t)0x7141, (q15_t)0x3BA5, (q15_t)0x7112, (q15_t)0x3BFD,
+ (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x70B3, (q15_t)0x3CAF,
+ (q15_t)0x7083, (q15_t)0x3D07, (q15_t)0x7053, (q15_t)0x3D60,
+ (q15_t)0x7023, (q15_t)0x3DB8, (q15_t)0x6FF2, (q15_t)0x3E10,
+ (q15_t)0x6FC1, (q15_t)0x3E68, (q15_t)0x6F90, (q15_t)0x3EBF,
+ (q15_t)0x6F5F, (q15_t)0x3F17, (q15_t)0x6F2D, (q15_t)0x3F6E,
+ (q15_t)0x6EFB, (q15_t)0x3FC5, (q15_t)0x6EC9, (q15_t)0x401D,
+ (q15_t)0x6E96, (q15_t)0x4073, (q15_t)0x6E63, (q15_t)0x40CA,
+ (q15_t)0x6E30, (q15_t)0x4121, (q15_t)0x6DFD, (q15_t)0x4177,
+ (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6D96, (q15_t)0x4224,
+ (q15_t)0x6D62, (q15_t)0x427A, (q15_t)0x6D2D, (q15_t)0x42D0,
+ (q15_t)0x6CF9, (q15_t)0x4325, (q15_t)0x6CC4, (q15_t)0x437B,
+ (q15_t)0x6C8F, (q15_t)0x43D0, (q15_t)0x6C59, (q15_t)0x4425,
+ (q15_t)0x6C24, (q15_t)0x447A, (q15_t)0x6BEE, (q15_t)0x44CF,
+ (q15_t)0x6BB8, (q15_t)0x4524, (q15_t)0x6B81, (q15_t)0x4578,
+ (q15_t)0x6B4A, (q15_t)0x45CD, (q15_t)0x6B13, (q15_t)0x4621,
+ (q15_t)0x6ADC, (q15_t)0x4675, (q15_t)0x6AA5, (q15_t)0x46C9,
+ (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x6A35, (q15_t)0x4770,
+ (q15_t)0x69FD, (q15_t)0x47C3, (q15_t)0x69C4, (q15_t)0x4816,
+ (q15_t)0x698C, (q15_t)0x4869, (q15_t)0x6953, (q15_t)0x48BC,
+ (q15_t)0x6919, (q15_t)0x490F, (q15_t)0x68E0, (q15_t)0x4961,
+ (q15_t)0x68A6, (q15_t)0x49B4, (q15_t)0x686C, (q15_t)0x4A06,
+ (q15_t)0x6832, (q15_t)0x4A58, (q15_t)0x67F7, (q15_t)0x4AA9,
+ (q15_t)0x67BD, (q15_t)0x4AFB, (q15_t)0x6782, (q15_t)0x4B4C,
+ (q15_t)0x6746, (q15_t)0x4B9E, (q15_t)0x670B, (q15_t)0x4BEF,
+ (q15_t)0x66CF, (q15_t)0x4C3F, (q15_t)0x6693, (q15_t)0x4C90,
+ (q15_t)0x6657, (q15_t)0x4CE1, (q15_t)0x661A, (q15_t)0x4D31,
+ (q15_t)0x65DD, (q15_t)0x4D81, (q15_t)0x65A0, (q15_t)0x4DD1,
+ (q15_t)0x6563, (q15_t)0x4E21, (q15_t)0x6526, (q15_t)0x4E70,
+ (q15_t)0x64E8, (q15_t)0x4EBF, (q15_t)0x64AA, (q15_t)0x4F0F,
+ (q15_t)0x646C, (q15_t)0x4F5E, (q15_t)0x642D, (q15_t)0x4FAC,
+ (q15_t)0x63EF, (q15_t)0x4FFB, (q15_t)0x63B0, (q15_t)0x5049,
+ (q15_t)0x6371, (q15_t)0x5097, (q15_t)0x6331, (q15_t)0x50E5,
+ (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x62B2, (q15_t)0x5181,
+ (q15_t)0x6271, (q15_t)0x51CE, (q15_t)0x6231, (q15_t)0x521C,
+ (q15_t)0x61F1, (q15_t)0x5269, (q15_t)0x61B0, (q15_t)0x52B5,
+ (q15_t)0x616F, (q15_t)0x5302, (q15_t)0x612D, (q15_t)0x534E,
+ (q15_t)0x60EC, (q15_t)0x539B, (q15_t)0x60AA, (q15_t)0x53E7,
+ (q15_t)0x6068, (q15_t)0x5433, (q15_t)0x6026, (q15_t)0x547E,
+ (q15_t)0x5FE3, (q15_t)0x54CA, (q15_t)0x5FA0, (q15_t)0x5515,
+ (q15_t)0x5F5E, (q15_t)0x5560, (q15_t)0x5F1A, (q15_t)0x55AB,
+ (q15_t)0x5ED7, (q15_t)0x55F5, (q15_t)0x5E93, (q15_t)0x5640,
+ (q15_t)0x5E50, (q15_t)0x568A, (q15_t)0x5E0B, (q15_t)0x56D4,
+ (q15_t)0x5DC7, (q15_t)0x571D, (q15_t)0x5D83, (q15_t)0x5767,
+ (q15_t)0x5D3E, (q15_t)0x57B0, (q15_t)0x5CF9, (q15_t)0x57F9,
+ (q15_t)0x5CB4, (q15_t)0x5842, (q15_t)0x5C6E, (q15_t)0x588B,
+ (q15_t)0x5C29, (q15_t)0x58D4, (q15_t)0x5BE3, (q15_t)0x591C,
+ (q15_t)0x5B9D, (q15_t)0x5964, (q15_t)0x5B56, (q15_t)0x59AC,
+ (q15_t)0x5B10, (q15_t)0x59F3, (q15_t)0x5AC9, (q15_t)0x5A3B,
+ (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x5A3B, (q15_t)0x5AC9,
+ (q15_t)0x59F3, (q15_t)0x5B10, (q15_t)0x59AC, (q15_t)0x5B56,
+ (q15_t)0x5964, (q15_t)0x5B9D, (q15_t)0x591C, (q15_t)0x5BE3,
+ (q15_t)0x58D4, (q15_t)0x5C29, (q15_t)0x588B, (q15_t)0x5C6E,
+ (q15_t)0x5842, (q15_t)0x5CB4, (q15_t)0x57F9, (q15_t)0x5CF9,
+ (q15_t)0x57B0, (q15_t)0x5D3E, (q15_t)0x5767, (q15_t)0x5D83,
+ (q15_t)0x571D, (q15_t)0x5DC7, (q15_t)0x56D4, (q15_t)0x5E0B,
+ (q15_t)0x568A, (q15_t)0x5E50, (q15_t)0x5640, (q15_t)0x5E93,
+ (q15_t)0x55F5, (q15_t)0x5ED7, (q15_t)0x55AB, (q15_t)0x5F1A,
+ (q15_t)0x5560, (q15_t)0x5F5E, (q15_t)0x5515, (q15_t)0x5FA0,
+ (q15_t)0x54CA, (q15_t)0x5FE3, (q15_t)0x547E, (q15_t)0x6026,
+ (q15_t)0x5433, (q15_t)0x6068, (q15_t)0x53E7, (q15_t)0x60AA,
+ (q15_t)0x539B, (q15_t)0x60EC, (q15_t)0x534E, (q15_t)0x612D,
+ (q15_t)0x5302, (q15_t)0x616F, (q15_t)0x52B5, (q15_t)0x61B0,
+ (q15_t)0x5269, (q15_t)0x61F1, (q15_t)0x521C, (q15_t)0x6231,
+ (q15_t)0x51CE, (q15_t)0x6271, (q15_t)0x5181, (q15_t)0x62B2,
+ (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x50E5, (q15_t)0x6331,
+ (q15_t)0x5097, (q15_t)0x6371, (q15_t)0x5049, (q15_t)0x63B0,
+ (q15_t)0x4FFB, (q15_t)0x63EF, (q15_t)0x4FAC, (q15_t)0x642D,
+ (q15_t)0x4F5E, (q15_t)0x646C, (q15_t)0x4F0F, (q15_t)0x64AA,
+ (q15_t)0x4EBF, (q15_t)0x64E8, (q15_t)0x4E70, (q15_t)0x6526,
+ (q15_t)0x4E21, (q15_t)0x6563, (q15_t)0x4DD1, (q15_t)0x65A0,
+ (q15_t)0x4D81, (q15_t)0x65DD, (q15_t)0x4D31, (q15_t)0x661A,
+ (q15_t)0x4CE1, (q15_t)0x6657, (q15_t)0x4C90, (q15_t)0x6693,
+ (q15_t)0x4C3F, (q15_t)0x66CF, (q15_t)0x4BEF, (q15_t)0x670B,
+ (q15_t)0x4B9E, (q15_t)0x6746, (q15_t)0x4B4C, (q15_t)0x6782,
+ (q15_t)0x4AFB, (q15_t)0x67BD, (q15_t)0x4AA9, (q15_t)0x67F7,
+ (q15_t)0x4A58, (q15_t)0x6832, (q15_t)0x4A06, (q15_t)0x686C,
+ (q15_t)0x49B4, (q15_t)0x68A6, (q15_t)0x4961, (q15_t)0x68E0,
+ (q15_t)0x490F, (q15_t)0x6919, (q15_t)0x48BC, (q15_t)0x6953,
+ (q15_t)0x4869, (q15_t)0x698C, (q15_t)0x4816, (q15_t)0x69C4,
+ (q15_t)0x47C3, (q15_t)0x69FD, (q15_t)0x4770, (q15_t)0x6A35,
+ (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x46C9, (q15_t)0x6AA5,
+ (q15_t)0x4675, (q15_t)0x6ADC, (q15_t)0x4621, (q15_t)0x6B13,
+ (q15_t)0x45CD, (q15_t)0x6B4A, (q15_t)0x4578, (q15_t)0x6B81,
+ (q15_t)0x4524, (q15_t)0x6BB8, (q15_t)0x44CF, (q15_t)0x6BEE,
+ (q15_t)0x447A, (q15_t)0x6C24, (q15_t)0x4425, (q15_t)0x6C59,
+ (q15_t)0x43D0, (q15_t)0x6C8F, (q15_t)0x437B, (q15_t)0x6CC4,
+ (q15_t)0x4325, (q15_t)0x6CF9, (q15_t)0x42D0, (q15_t)0x6D2D,
+ (q15_t)0x427A, (q15_t)0x6D62, (q15_t)0x4224, (q15_t)0x6D96,
+ (q15_t)0x41CE, (q15_t)0x6DCA, (q15_t)0x4177, (q15_t)0x6DFD,
+ (q15_t)0x4121, (q15_t)0x6E30, (q15_t)0x40CA, (q15_t)0x6E63,
+ (q15_t)0x4073, (q15_t)0x6E96, (q15_t)0x401D, (q15_t)0x6EC9,
+ (q15_t)0x3FC5, (q15_t)0x6EFB, (q15_t)0x3F6E, (q15_t)0x6F2D,
+ (q15_t)0x3F17, (q15_t)0x6F5F, (q15_t)0x3EBF, (q15_t)0x6F90,
+ (q15_t)0x3E68, (q15_t)0x6FC1, (q15_t)0x3E10, (q15_t)0x6FF2,
+ (q15_t)0x3DB8, (q15_t)0x7023, (q15_t)0x3D60, (q15_t)0x7053,
+ (q15_t)0x3D07, (q15_t)0x7083, (q15_t)0x3CAF, (q15_t)0x70B3,
+ (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x3BFD, (q15_t)0x7112,
+ (q15_t)0x3BA5, (q15_t)0x7141, (q15_t)0x3B4C, (q15_t)0x716F,
+ (q15_t)0x3AF2, (q15_t)0x719E, (q15_t)0x3A99, (q15_t)0x71CC,
+ (q15_t)0x3A40, (q15_t)0x71FA, (q15_t)0x39E6, (q15_t)0x7227,
+ (q15_t)0x398C, (q15_t)0x7255, (q15_t)0x3932, (q15_t)0x7282,
+ (q15_t)0x38D8, (q15_t)0x72AF, (q15_t)0x387E, (q15_t)0x72DB,
+ (q15_t)0x3824, (q15_t)0x7307, (q15_t)0x37CA, (q15_t)0x7333,
+ (q15_t)0x376F, (q15_t)0x735F, (q15_t)0x3714, (q15_t)0x738A,
+ (q15_t)0x36BA, (q15_t)0x73B5, (q15_t)0x365F, (q15_t)0x73E0,
+ (q15_t)0x3604, (q15_t)0x740B, (q15_t)0x35A8, (q15_t)0x7435,
+ (q15_t)0x354D, (q15_t)0x745F, (q15_t)0x34F2, (q15_t)0x7489,
+ (q15_t)0x3496, (q15_t)0x74B2, (q15_t)0x343A, (q15_t)0x74DB,
+ (q15_t)0x33DE, (q15_t)0x7504, (q15_t)0x3382, (q15_t)0x752D,
+ (q15_t)0x3326, (q15_t)0x7555, (q15_t)0x32CA, (q15_t)0x757D,
+ (q15_t)0x326E, (q15_t)0x75A5, (q15_t)0x3211, (q15_t)0x75CC,
+ (q15_t)0x31B5, (q15_t)0x75F4, (q15_t)0x3158, (q15_t)0x761B,
+ (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x309E, (q15_t)0x7668,
+ (q15_t)0x3041, (q15_t)0x768E, (q15_t)0x2FE4, (q15_t)0x76B3,
+ (q15_t)0x2F87, (q15_t)0x76D9, (q15_t)0x2F29, (q15_t)0x76FE,
+ (q15_t)0x2ECC, (q15_t)0x7723, (q15_t)0x2E6E, (q15_t)0x7747,
+ (q15_t)0x2E11, (q15_t)0x776C, (q15_t)0x2DB3, (q15_t)0x7790,
+ (q15_t)0x2D55, (q15_t)0x77B4, (q15_t)0x2CF7, (q15_t)0x77D7,
+ (q15_t)0x2C98, (q15_t)0x77FA, (q15_t)0x2C3A, (q15_t)0x781D,
+ (q15_t)0x2BDC, (q15_t)0x7840, (q15_t)0x2B7D, (q15_t)0x7862,
+ (q15_t)0x2B1F, (q15_t)0x7884, (q15_t)0x2AC0, (q15_t)0x78A6,
+ (q15_t)0x2A61, (q15_t)0x78C7, (q15_t)0x2A02, (q15_t)0x78E8,
+ (q15_t)0x29A3, (q15_t)0x7909, (q15_t)0x2944, (q15_t)0x792A,
+ (q15_t)0x28E5, (q15_t)0x794A, (q15_t)0x2886, (q15_t)0x796A,
+ (q15_t)0x2826, (q15_t)0x798A, (q15_t)0x27C7, (q15_t)0x79A9,
+ (q15_t)0x2767, (q15_t)0x79C8, (q15_t)0x2707, (q15_t)0x79E7,
+ (q15_t)0x26A8, (q15_t)0x7A05, (q15_t)0x2648, (q15_t)0x7A24,
+ (q15_t)0x25E8, (q15_t)0x7A42, (q15_t)0x2588, (q15_t)0x7A5F,
+ (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x24C7, (q15_t)0x7A9A,
+ (q15_t)0x2467, (q15_t)0x7AB6, (q15_t)0x2407, (q15_t)0x7AD3,
+ (q15_t)0x23A6, (q15_t)0x7AEF, (q15_t)0x2345, (q15_t)0x7B0B,
+ (q15_t)0x22E5, (q15_t)0x7B26, (q15_t)0x2284, (q15_t)0x7B42,
+ (q15_t)0x2223, (q15_t)0x7B5D, (q15_t)0x21C2, (q15_t)0x7B77,
+ (q15_t)0x2161, (q15_t)0x7B92, (q15_t)0x2100, (q15_t)0x7BAC,
+ (q15_t)0x209F, (q15_t)0x7BC5, (q15_t)0x203E, (q15_t)0x7BDF,
+ (q15_t)0x1FDC, (q15_t)0x7BF8, (q15_t)0x1F7B, (q15_t)0x7C11,
+ (q15_t)0x1F19, (q15_t)0x7C29, (q15_t)0x1EB8, (q15_t)0x7C42,
+ (q15_t)0x1E56, (q15_t)0x7C5A, (q15_t)0x1DF5, (q15_t)0x7C71,
+ (q15_t)0x1D93, (q15_t)0x7C89, (q15_t)0x1D31, (q15_t)0x7CA0,
+ (q15_t)0x1CCF, (q15_t)0x7CB7, (q15_t)0x1C6D, (q15_t)0x7CCD,
+ (q15_t)0x1C0B, (q15_t)0x7CE3, (q15_t)0x1BA9, (q15_t)0x7CF9,
+ (q15_t)0x1B47, (q15_t)0x7D0F, (q15_t)0x1AE4, (q15_t)0x7D24,
+ (q15_t)0x1A82, (q15_t)0x7D39, (q15_t)0x1A20, (q15_t)0x7D4E,
+ (q15_t)0x19BD, (q15_t)0x7D62, (q15_t)0x195B, (q15_t)0x7D76,
+ (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x1896, (q15_t)0x7D9D,
+ (q15_t)0x1833, (q15_t)0x7DB0, (q15_t)0x17D0, (q15_t)0x7DC3,
+ (q15_t)0x176D, (q15_t)0x7DD6, (q15_t)0x170A, (q15_t)0x7DE8,
+ (q15_t)0x16A8, (q15_t)0x7DFA, (q15_t)0x1645, (q15_t)0x7E0C,
+ (q15_t)0x15E2, (q15_t)0x7E1D, (q15_t)0x157F, (q15_t)0x7E2E,
+ (q15_t)0x151B, (q15_t)0x7E3F, (q15_t)0x14B8, (q15_t)0x7E4F,
+ (q15_t)0x1455, (q15_t)0x7E5F, (q15_t)0x13F2, (q15_t)0x7E6F,
+ (q15_t)0x138E, (q15_t)0x7E7F, (q15_t)0x132B, (q15_t)0x7E8E,
+ (q15_t)0x12C8, (q15_t)0x7E9D, (q15_t)0x1264, (q15_t)0x7EAB,
+ (q15_t)0x1201, (q15_t)0x7EBA, (q15_t)0x119D, (q15_t)0x7EC8,
+ (q15_t)0x1139, (q15_t)0x7ED5, (q15_t)0x10D6, (q15_t)0x7EE3,
+ (q15_t)0x1072, (q15_t)0x7EF0, (q15_t)0x100E, (q15_t)0x7EFD,
+ (q15_t)0x0FAB, (q15_t)0x7F09, (q15_t)0x0F47, (q15_t)0x7F15,
+ (q15_t)0x0EE3, (q15_t)0x7F21, (q15_t)0x0E7F, (q15_t)0x7F2D,
+ (q15_t)0x0E1B, (q15_t)0x7F38, (q15_t)0x0DB7, (q15_t)0x7F43,
+ (q15_t)0x0D53, (q15_t)0x7F4D, (q15_t)0x0CEF, (q15_t)0x7F58,
+ (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x0C27, (q15_t)0x7F6B,
+ (q15_t)0x0BC3, (q15_t)0x7F75, (q15_t)0x0B5F, (q15_t)0x7F7E,
+ (q15_t)0x0AFB, (q15_t)0x7F87, (q15_t)0x0A97, (q15_t)0x7F8F,
+ (q15_t)0x0A33, (q15_t)0x7F97, (q15_t)0x09CE, (q15_t)0x7F9F,
+ (q15_t)0x096A, (q15_t)0x7FA7, (q15_t)0x0906, (q15_t)0x7FAE,
+ (q15_t)0x08A2, (q15_t)0x7FB5, (q15_t)0x083D, (q15_t)0x7FBC,
+ (q15_t)0x07D9, (q15_t)0x7FC2, (q15_t)0x0775, (q15_t)0x7FC8,
+ (q15_t)0x0710, (q15_t)0x7FCE, (q15_t)0x06AC, (q15_t)0x7FD3,
+ (q15_t)0x0647, (q15_t)0x7FD8, (q15_t)0x05E3, (q15_t)0x7FDD,
+ (q15_t)0x057F, (q15_t)0x7FE1, (q15_t)0x051A, (q15_t)0x7FE5,
+ (q15_t)0x04B6, (q15_t)0x7FE9, (q15_t)0x0451, (q15_t)0x7FED,
+ (q15_t)0x03ED, (q15_t)0x7FF0, (q15_t)0x0388, (q15_t)0x7FF3,
+ (q15_t)0x0324, (q15_t)0x7FF6, (q15_t)0x02BF, (q15_t)0x7FF8,
+ (q15_t)0x025B, (q15_t)0x7FFA, (q15_t)0x01F6, (q15_t)0x7FFC,
+ (q15_t)0x0192, (q15_t)0x7FFD, (q15_t)0x012D, (q15_t)0x7FFE,
+ (q15_t)0x00C9, (q15_t)0x7FFF, (q15_t)0x0064, (q15_t)0x7FFF,
+ (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xFF9B, (q15_t)0x7FFF,
+ (q15_t)0xFF36, (q15_t)0x7FFF, (q15_t)0xFED2, (q15_t)0x7FFE,
+ (q15_t)0xFE6D, (q15_t)0x7FFD, (q15_t)0xFE09, (q15_t)0x7FFC,
+ (q15_t)0xFDA4, (q15_t)0x7FFA, (q15_t)0xFD40, (q15_t)0x7FF8,
+ (q15_t)0xFCDB, (q15_t)0x7FF6, (q15_t)0xFC77, (q15_t)0x7FF3,
+ (q15_t)0xFC12, (q15_t)0x7FF0, (q15_t)0xFBAE, (q15_t)0x7FED,
+ (q15_t)0xFB49, (q15_t)0x7FE9, (q15_t)0xFAE5, (q15_t)0x7FE5,
+ (q15_t)0xFA80, (q15_t)0x7FE1, (q15_t)0xFA1C, (q15_t)0x7FDD,
+ (q15_t)0xF9B8, (q15_t)0x7FD8, (q15_t)0xF953, (q15_t)0x7FD3,
+ (q15_t)0xF8EF, (q15_t)0x7FCE, (q15_t)0xF88A, (q15_t)0x7FC8,
+ (q15_t)0xF826, (q15_t)0x7FC2, (q15_t)0xF7C2, (q15_t)0x7FBC,
+ (q15_t)0xF75D, (q15_t)0x7FB5, (q15_t)0xF6F9, (q15_t)0x7FAE,
+ (q15_t)0xF695, (q15_t)0x7FA7, (q15_t)0xF631, (q15_t)0x7F9F,
+ (q15_t)0xF5CC, (q15_t)0x7F97, (q15_t)0xF568, (q15_t)0x7F8F,
+ (q15_t)0xF504, (q15_t)0x7F87, (q15_t)0xF4A0, (q15_t)0x7F7E,
+ (q15_t)0xF43C, (q15_t)0x7F75, (q15_t)0xF3D8, (q15_t)0x7F6B,
+ (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xF310, (q15_t)0x7F58,
+ (q15_t)0xF2AC, (q15_t)0x7F4D, (q15_t)0xF248, (q15_t)0x7F43,
+ (q15_t)0xF1E4, (q15_t)0x7F38, (q15_t)0xF180, (q15_t)0x7F2D,
+ (q15_t)0xF11C, (q15_t)0x7F21, (q15_t)0xF0B8, (q15_t)0x7F15,
+ (q15_t)0xF054, (q15_t)0x7F09, (q15_t)0xEFF1, (q15_t)0x7EFD,
+ (q15_t)0xEF8D, (q15_t)0x7EF0, (q15_t)0xEF29, (q15_t)0x7EE3,
+ (q15_t)0xEEC6, (q15_t)0x7ED5, (q15_t)0xEE62, (q15_t)0x7EC8,
+ (q15_t)0xEDFE, (q15_t)0x7EBA, (q15_t)0xED9B, (q15_t)0x7EAB,
+ (q15_t)0xED37, (q15_t)0x7E9D, (q15_t)0xECD4, (q15_t)0x7E8E,
+ (q15_t)0xEC71, (q15_t)0x7E7F, (q15_t)0xEC0D, (q15_t)0x7E6F,
+ (q15_t)0xEBAA, (q15_t)0x7E5F, (q15_t)0xEB47, (q15_t)0x7E4F,
+ (q15_t)0xEAE4, (q15_t)0x7E3F, (q15_t)0xEA80, (q15_t)0x7E2E,
+ (q15_t)0xEA1D, (q15_t)0x7E1D, (q15_t)0xE9BA, (q15_t)0x7E0C,
+ (q15_t)0xE957, (q15_t)0x7DFA, (q15_t)0xE8F5, (q15_t)0x7DE8,
+ (q15_t)0xE892, (q15_t)0x7DD6, (q15_t)0xE82F, (q15_t)0x7DC3,
+ (q15_t)0xE7CC, (q15_t)0x7DB0, (q15_t)0xE769, (q15_t)0x7D9D,
+ (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE6A4, (q15_t)0x7D76,
+ (q15_t)0xE642, (q15_t)0x7D62, (q15_t)0xE5DF, (q15_t)0x7D4E,
+ (q15_t)0xE57D, (q15_t)0x7D39, (q15_t)0xE51B, (q15_t)0x7D24,
+ (q15_t)0xE4B8, (q15_t)0x7D0F, (q15_t)0xE456, (q15_t)0x7CF9,
+ (q15_t)0xE3F4, (q15_t)0x7CE3, (q15_t)0xE392, (q15_t)0x7CCD,
+ (q15_t)0xE330, (q15_t)0x7CB7, (q15_t)0xE2CE, (q15_t)0x7CA0,
+ (q15_t)0xE26C, (q15_t)0x7C89, (q15_t)0xE20A, (q15_t)0x7C71,
+ (q15_t)0xE1A9, (q15_t)0x7C5A, (q15_t)0xE147, (q15_t)0x7C42,
+ (q15_t)0xE0E6, (q15_t)0x7C29, (q15_t)0xE084, (q15_t)0x7C11,
+ (q15_t)0xE023, (q15_t)0x7BF8, (q15_t)0xDFC1, (q15_t)0x7BDF,
+ (q15_t)0xDF60, (q15_t)0x7BC5, (q15_t)0xDEFF, (q15_t)0x7BAC,
+ (q15_t)0xDE9E, (q15_t)0x7B92, (q15_t)0xDE3D, (q15_t)0x7B77,
+ (q15_t)0xDDDC, (q15_t)0x7B5D, (q15_t)0xDD7B, (q15_t)0x7B42,
+ (q15_t)0xDD1A, (q15_t)0x7B26, (q15_t)0xDCBA, (q15_t)0x7B0B,
+ (q15_t)0xDC59, (q15_t)0x7AEF, (q15_t)0xDBF8, (q15_t)0x7AD3,
+ (q15_t)0xDB98, (q15_t)0x7AB6, (q15_t)0xDB38, (q15_t)0x7A9A,
+ (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xDA77, (q15_t)0x7A5F,
+ (q15_t)0xDA17, (q15_t)0x7A42, (q15_t)0xD9B7, (q15_t)0x7A24,
+ (q15_t)0xD957, (q15_t)0x7A05, (q15_t)0xD8F8, (q15_t)0x79E7,
+ (q15_t)0xD898, (q15_t)0x79C8, (q15_t)0xD838, (q15_t)0x79A9,
+ (q15_t)0xD7D9, (q15_t)0x798A, (q15_t)0xD779, (q15_t)0x796A,
+ (q15_t)0xD71A, (q15_t)0x794A, (q15_t)0xD6BB, (q15_t)0x792A,
+ (q15_t)0xD65C, (q15_t)0x7909, (q15_t)0xD5FD, (q15_t)0x78E8,
+ (q15_t)0xD59E, (q15_t)0x78C7, (q15_t)0xD53F, (q15_t)0x78A6,
+ (q15_t)0xD4E0, (q15_t)0x7884, (q15_t)0xD482, (q15_t)0x7862,
+ (q15_t)0xD423, (q15_t)0x7840, (q15_t)0xD3C5, (q15_t)0x781D,
+ (q15_t)0xD367, (q15_t)0x77FA, (q15_t)0xD308, (q15_t)0x77D7,
+ (q15_t)0xD2AA, (q15_t)0x77B4, (q15_t)0xD24C, (q15_t)0x7790,
+ (q15_t)0xD1EE, (q15_t)0x776C, (q15_t)0xD191, (q15_t)0x7747,
+ (q15_t)0xD133, (q15_t)0x7723, (q15_t)0xD0D6, (q15_t)0x76FE,
+ (q15_t)0xD078, (q15_t)0x76D9, (q15_t)0xD01B, (q15_t)0x76B3,
+ (q15_t)0xCFBE, (q15_t)0x768E, (q15_t)0xCF61, (q15_t)0x7668,
+ (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xCEA7, (q15_t)0x761B,
+ (q15_t)0xCE4A, (q15_t)0x75F4, (q15_t)0xCDEE, (q15_t)0x75CC,
+ (q15_t)0xCD91, (q15_t)0x75A5, (q15_t)0xCD35, (q15_t)0x757D,
+ (q15_t)0xCCD9, (q15_t)0x7555, (q15_t)0xCC7D, (q15_t)0x752D,
+ (q15_t)0xCC21, (q15_t)0x7504, (q15_t)0xCBC5, (q15_t)0x74DB,
+ (q15_t)0xCB69, (q15_t)0x74B2, (q15_t)0xCB0D, (q15_t)0x7489,
+ (q15_t)0xCAB2, (q15_t)0x745F, (q15_t)0xCA57, (q15_t)0x7435,
+ (q15_t)0xC9FB, (q15_t)0x740B, (q15_t)0xC9A0, (q15_t)0x73E0,
+ (q15_t)0xC945, (q15_t)0x73B5, (q15_t)0xC8EB, (q15_t)0x738A,
+ (q15_t)0xC890, (q15_t)0x735F, (q15_t)0xC835, (q15_t)0x7333,
+ (q15_t)0xC7DB, (q15_t)0x7307, (q15_t)0xC781, (q15_t)0x72DB,
+ (q15_t)0xC727, (q15_t)0x72AF, (q15_t)0xC6CD, (q15_t)0x7282,
+ (q15_t)0xC673, (q15_t)0x7255, (q15_t)0xC619, (q15_t)0x7227,
+ (q15_t)0xC5BF, (q15_t)0x71FA, (q15_t)0xC566, (q15_t)0x71CC,
+ (q15_t)0xC50D, (q15_t)0x719E, (q15_t)0xC4B3, (q15_t)0x716F,
+ (q15_t)0xC45A, (q15_t)0x7141, (q15_t)0xC402, (q15_t)0x7112,
+ (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xC350, (q15_t)0x70B3,
+ (q15_t)0xC2F8, (q15_t)0x7083, (q15_t)0xC29F, (q15_t)0x7053,
+ (q15_t)0xC247, (q15_t)0x7023, (q15_t)0xC1EF, (q15_t)0x6FF2,
+ (q15_t)0xC197, (q15_t)0x6FC1, (q15_t)0xC140, (q15_t)0x6F90,
+ (q15_t)0xC0E8, (q15_t)0x6F5F, (q15_t)0xC091, (q15_t)0x6F2D,
+ (q15_t)0xC03A, (q15_t)0x6EFB, (q15_t)0xBFE2, (q15_t)0x6EC9,
+ (q15_t)0xBF8C, (q15_t)0x6E96, (q15_t)0xBF35, (q15_t)0x6E63,
+ (q15_t)0xBEDE, (q15_t)0x6E30, (q15_t)0xBE88, (q15_t)0x6DFD,
+ (q15_t)0xBE31, (q15_t)0x6DCA, (q15_t)0xBDDB, (q15_t)0x6D96,
+ (q15_t)0xBD85, (q15_t)0x6D62, (q15_t)0xBD2F, (q15_t)0x6D2D,
+ (q15_t)0xBCDA, (q15_t)0x6CF9, (q15_t)0xBC84, (q15_t)0x6CC4,
+ (q15_t)0xBC2F, (q15_t)0x6C8F, (q15_t)0xBBDA, (q15_t)0x6C59,
+ (q15_t)0xBB85, (q15_t)0x6C24, (q15_t)0xBB30, (q15_t)0x6BEE,
+ (q15_t)0xBADB, (q15_t)0x6BB8, (q15_t)0xBA87, (q15_t)0x6B81,
+ (q15_t)0xBA32, (q15_t)0x6B4A, (q15_t)0xB9DE, (q15_t)0x6B13,
+ (q15_t)0xB98A, (q15_t)0x6ADC, (q15_t)0xB936, (q15_t)0x6AA5,
+ (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB88F, (q15_t)0x6A35,
+ (q15_t)0xB83C, (q15_t)0x69FD, (q15_t)0xB7E9, (q15_t)0x69C4,
+ (q15_t)0xB796, (q15_t)0x698C, (q15_t)0xB743, (q15_t)0x6953,
+ (q15_t)0xB6F0, (q15_t)0x6919, (q15_t)0xB69E, (q15_t)0x68E0,
+ (q15_t)0xB64B, (q15_t)0x68A6, (q15_t)0xB5F9, (q15_t)0x686C,
+ (q15_t)0xB5A7, (q15_t)0x6832, (q15_t)0xB556, (q15_t)0x67F7,
+ (q15_t)0xB504, (q15_t)0x67BD, (q15_t)0xB4B3, (q15_t)0x6782,
+ (q15_t)0xB461, (q15_t)0x6746, (q15_t)0xB410, (q15_t)0x670B,
+ (q15_t)0xB3C0, (q15_t)0x66CF, (q15_t)0xB36F, (q15_t)0x6693,
+ (q15_t)0xB31E, (q15_t)0x6657, (q15_t)0xB2CE, (q15_t)0x661A,
+ (q15_t)0xB27E, (q15_t)0x65DD, (q15_t)0xB22E, (q15_t)0x65A0,
+ (q15_t)0xB1DE, (q15_t)0x6563, (q15_t)0xB18F, (q15_t)0x6526,
+ (q15_t)0xB140, (q15_t)0x64E8, (q15_t)0xB0F0, (q15_t)0x64AA,
+ (q15_t)0xB0A1, (q15_t)0x646C, (q15_t)0xB053, (q15_t)0x642D,
+ (q15_t)0xB004, (q15_t)0x63EF, (q15_t)0xAFB6, (q15_t)0x63B0,
+ (q15_t)0xAF68, (q15_t)0x6371, (q15_t)0xAF1A, (q15_t)0x6331,
+ (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAE7E, (q15_t)0x62B2,
+ (q15_t)0xAE31, (q15_t)0x6271, (q15_t)0xADE3, (q15_t)0x6231,
+ (q15_t)0xAD96, (q15_t)0x61F1, (q15_t)0xAD4A, (q15_t)0x61B0,
+ (q15_t)0xACFD, (q15_t)0x616F, (q15_t)0xACB1, (q15_t)0x612D,
+ (q15_t)0xAC64, (q15_t)0x60EC, (q15_t)0xAC18, (q15_t)0x60AA,
+ (q15_t)0xABCC, (q15_t)0x6068, (q15_t)0xAB81, (q15_t)0x6026,
+ (q15_t)0xAB35, (q15_t)0x5FE3, (q15_t)0xAAEA, (q15_t)0x5FA0,
+ (q15_t)0xAA9F, (q15_t)0x5F5E, (q15_t)0xAA54, (q15_t)0x5F1A,
+ (q15_t)0xAA0A, (q15_t)0x5ED7, (q15_t)0xA9BF, (q15_t)0x5E93,
+ (q15_t)0xA975, (q15_t)0x5E50, (q15_t)0xA92B, (q15_t)0x5E0B,
+ (q15_t)0xA8E2, (q15_t)0x5DC7, (q15_t)0xA898, (q15_t)0x5D83,
+ (q15_t)0xA84F, (q15_t)0x5D3E, (q15_t)0xA806, (q15_t)0x5CF9,
+ (q15_t)0xA7BD, (q15_t)0x5CB4, (q15_t)0xA774, (q15_t)0x5C6E,
+ (q15_t)0xA72B, (q15_t)0x5C29, (q15_t)0xA6E3, (q15_t)0x5BE3,
+ (q15_t)0xA69B, (q15_t)0x5B9D, (q15_t)0xA653, (q15_t)0x5B56,
+ (q15_t)0xA60C, (q15_t)0x5B10, (q15_t)0xA5C4, (q15_t)0x5AC9,
+ (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA536, (q15_t)0x5A3B,
+ (q15_t)0xA4EF, (q15_t)0x59F3, (q15_t)0xA4A9, (q15_t)0x59AC,
+ (q15_t)0xA462, (q15_t)0x5964, (q15_t)0xA41C, (q15_t)0x591C,
+ (q15_t)0xA3D6, (q15_t)0x58D4, (q15_t)0xA391, (q15_t)0x588B,
+ (q15_t)0xA34B, (q15_t)0x5842, (q15_t)0xA306, (q15_t)0x57F9,
+ (q15_t)0xA2C1, (q15_t)0x57B0, (q15_t)0xA27C, (q15_t)0x5767,
+ (q15_t)0xA238, (q15_t)0x571D, (q15_t)0xA1F4, (q15_t)0x56D4,
+ (q15_t)0xA1AF, (q15_t)0x568A, (q15_t)0xA16C, (q15_t)0x5640,
+ (q15_t)0xA128, (q15_t)0x55F5, (q15_t)0xA0E5, (q15_t)0x55AB,
+ (q15_t)0xA0A1, (q15_t)0x5560, (q15_t)0xA05F, (q15_t)0x5515,
+ (q15_t)0xA01C, (q15_t)0x54CA, (q15_t)0x9FD9, (q15_t)0x547E,
+ (q15_t)0x9F97, (q15_t)0x5433, (q15_t)0x9F55, (q15_t)0x53E7,
+ (q15_t)0x9F13, (q15_t)0x539B, (q15_t)0x9ED2, (q15_t)0x534E,
+ (q15_t)0x9E90, (q15_t)0x5302, (q15_t)0x9E4F, (q15_t)0x52B5,
+ (q15_t)0x9E0E, (q15_t)0x5269, (q15_t)0x9DCE, (q15_t)0x521C,
+ (q15_t)0x9D8E, (q15_t)0x51CE, (q15_t)0x9D4D, (q15_t)0x5181,
+ (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9CCE, (q15_t)0x50E5,
+ (q15_t)0x9C8E, (q15_t)0x5097, (q15_t)0x9C4F, (q15_t)0x5049,
+ (q15_t)0x9C10, (q15_t)0x4FFB, (q15_t)0x9BD2, (q15_t)0x4FAC,
+ (q15_t)0x9B93, (q15_t)0x4F5E, (q15_t)0x9B55, (q15_t)0x4F0F,
+ (q15_t)0x9B17, (q15_t)0x4EBF, (q15_t)0x9AD9, (q15_t)0x4E70,
+ (q15_t)0x9A9C, (q15_t)0x4E21, (q15_t)0x9A5F, (q15_t)0x4DD1,
+ (q15_t)0x9A22, (q15_t)0x4D81, (q15_t)0x99E5, (q15_t)0x4D31,
+ (q15_t)0x99A8, (q15_t)0x4CE1, (q15_t)0x996C, (q15_t)0x4C90,
+ (q15_t)0x9930, (q15_t)0x4C3F, (q15_t)0x98F4, (q15_t)0x4BEF,
+ (q15_t)0x98B9, (q15_t)0x4B9E, (q15_t)0x987D, (q15_t)0x4B4C,
+ (q15_t)0x9842, (q15_t)0x4AFB, (q15_t)0x9808, (q15_t)0x4AA9,
+ (q15_t)0x97CD, (q15_t)0x4A58, (q15_t)0x9793, (q15_t)0x4A06,
+ (q15_t)0x9759, (q15_t)0x49B4, (q15_t)0x971F, (q15_t)0x4961,
+ (q15_t)0x96E6, (q15_t)0x490F, (q15_t)0x96AC, (q15_t)0x48BC,
+ (q15_t)0x9673, (q15_t)0x4869, (q15_t)0x963B, (q15_t)0x4816,
+ (q15_t)0x9602, (q15_t)0x47C3, (q15_t)0x95CA, (q15_t)0x4770,
+ (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x955A, (q15_t)0x46C9,
+ (q15_t)0x9523, (q15_t)0x4675, (q15_t)0x94EC, (q15_t)0x4621,
+ (q15_t)0x94B5, (q15_t)0x45CD, (q15_t)0x947E, (q15_t)0x4578,
+ (q15_t)0x9447, (q15_t)0x4524, (q15_t)0x9411, (q15_t)0x44CF,
+ (q15_t)0x93DB, (q15_t)0x447A, (q15_t)0x93A6, (q15_t)0x4425,
+ (q15_t)0x9370, (q15_t)0x43D0, (q15_t)0x933B, (q15_t)0x437B,
+ (q15_t)0x9306, (q15_t)0x4325, (q15_t)0x92D2, (q15_t)0x42D0,
+ (q15_t)0x929D, (q15_t)0x427A, (q15_t)0x9269, (q15_t)0x4224,
+ (q15_t)0x9235, (q15_t)0x41CE, (q15_t)0x9202, (q15_t)0x4177,
+ (q15_t)0x91CF, (q15_t)0x4121, (q15_t)0x919C, (q15_t)0x40CA,
+ (q15_t)0x9169, (q15_t)0x4073, (q15_t)0x9136, (q15_t)0x401D,
+ (q15_t)0x9104, (q15_t)0x3FC5, (q15_t)0x90D2, (q15_t)0x3F6E,
+ (q15_t)0x90A0, (q15_t)0x3F17, (q15_t)0x906F, (q15_t)0x3EBF,
+ (q15_t)0x903E, (q15_t)0x3E68, (q15_t)0x900D, (q15_t)0x3E10,
+ (q15_t)0x8FDC, (q15_t)0x3DB8, (q15_t)0x8FAC, (q15_t)0x3D60,
+ (q15_t)0x8F7C, (q15_t)0x3D07, (q15_t)0x8F4C, (q15_t)0x3CAF,
+ (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8EED, (q15_t)0x3BFD,
+ (q15_t)0x8EBE, (q15_t)0x3BA5, (q15_t)0x8E90, (q15_t)0x3B4C,
+ (q15_t)0x8E61, (q15_t)0x3AF2, (q15_t)0x8E33, (q15_t)0x3A99,
+ (q15_t)0x8E05, (q15_t)0x3A40, (q15_t)0x8DD8, (q15_t)0x39E6,
+ (q15_t)0x8DAA, (q15_t)0x398C, (q15_t)0x8D7D, (q15_t)0x3932,
+ (q15_t)0x8D50, (q15_t)0x38D8, (q15_t)0x8D24, (q15_t)0x387E,
+ (q15_t)0x8CF8, (q15_t)0x3824, (q15_t)0x8CCC, (q15_t)0x37CA,
+ (q15_t)0x8CA0, (q15_t)0x376F, (q15_t)0x8C75, (q15_t)0x3714,
+ (q15_t)0x8C4A, (q15_t)0x36BA, (q15_t)0x8C1F, (q15_t)0x365F,
+ (q15_t)0x8BF4, (q15_t)0x3604, (q15_t)0x8BCA, (q15_t)0x35A8,
+ (q15_t)0x8BA0, (q15_t)0x354D, (q15_t)0x8B76, (q15_t)0x34F2,
+ (q15_t)0x8B4D, (q15_t)0x3496, (q15_t)0x8B24, (q15_t)0x343A,
+ (q15_t)0x8AFB, (q15_t)0x33DE, (q15_t)0x8AD2, (q15_t)0x3382,
+ (q15_t)0x8AAA, (q15_t)0x3326, (q15_t)0x8A82, (q15_t)0x32CA,
+ (q15_t)0x8A5A, (q15_t)0x326E, (q15_t)0x8A33, (q15_t)0x3211,
+ (q15_t)0x8A0B, (q15_t)0x31B5, (q15_t)0x89E4, (q15_t)0x3158,
+ (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x8997, (q15_t)0x309E,
+ (q15_t)0x8971, (q15_t)0x3041, (q15_t)0x894C, (q15_t)0x2FE4,
+ (q15_t)0x8926, (q15_t)0x2F87, (q15_t)0x8901, (q15_t)0x2F29,
+ (q15_t)0x88DC, (q15_t)0x2ECC, (q15_t)0x88B8, (q15_t)0x2E6E,
+ (q15_t)0x8893, (q15_t)0x2E11, (q15_t)0x886F, (q15_t)0x2DB3,
+ (q15_t)0x884B, (q15_t)0x2D55, (q15_t)0x8828, (q15_t)0x2CF7,
+ (q15_t)0x8805, (q15_t)0x2C98, (q15_t)0x87E2, (q15_t)0x2C3A,
+ (q15_t)0x87BF, (q15_t)0x2BDC, (q15_t)0x879D, (q15_t)0x2B7D,
+ (q15_t)0x877B, (q15_t)0x2B1F, (q15_t)0x8759, (q15_t)0x2AC0,
+ (q15_t)0x8738, (q15_t)0x2A61, (q15_t)0x8717, (q15_t)0x2A02,
+ (q15_t)0x86F6, (q15_t)0x29A3, (q15_t)0x86D5, (q15_t)0x2944,
+ (q15_t)0x86B5, (q15_t)0x28E5, (q15_t)0x8695, (q15_t)0x2886,
+ (q15_t)0x8675, (q15_t)0x2826, (q15_t)0x8656, (q15_t)0x27C7,
+ (q15_t)0x8637, (q15_t)0x2767, (q15_t)0x8618, (q15_t)0x2707,
+ (q15_t)0x85FA, (q15_t)0x26A8, (q15_t)0x85DB, (q15_t)0x2648,
+ (q15_t)0x85BD, (q15_t)0x25E8, (q15_t)0x85A0, (q15_t)0x2588,
+ (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x8565, (q15_t)0x24C7,
+ (q15_t)0x8549, (q15_t)0x2467, (q15_t)0x852C, (q15_t)0x2407,
+ (q15_t)0x8510, (q15_t)0x23A6, (q15_t)0x84F4, (q15_t)0x2345,
+ (q15_t)0x84D9, (q15_t)0x22E5, (q15_t)0x84BD, (q15_t)0x2284,
+ (q15_t)0x84A2, (q15_t)0x2223, (q15_t)0x8488, (q15_t)0x21C2,
+ (q15_t)0x846D, (q15_t)0x2161, (q15_t)0x8453, (q15_t)0x2100,
+ (q15_t)0x843A, (q15_t)0x209F, (q15_t)0x8420, (q15_t)0x203E,
+ (q15_t)0x8407, (q15_t)0x1FDC, (q15_t)0x83EE, (q15_t)0x1F7B,
+ (q15_t)0x83D6, (q15_t)0x1F19, (q15_t)0x83BD, (q15_t)0x1EB8,
+ (q15_t)0x83A5, (q15_t)0x1E56, (q15_t)0x838E, (q15_t)0x1DF5,
+ (q15_t)0x8376, (q15_t)0x1D93, (q15_t)0x835F, (q15_t)0x1D31,
+ (q15_t)0x8348, (q15_t)0x1CCF, (q15_t)0x8332, (q15_t)0x1C6D,
+ (q15_t)0x831C, (q15_t)0x1C0B, (q15_t)0x8306, (q15_t)0x1BA9,
+ (q15_t)0x82F0, (q15_t)0x1B47, (q15_t)0x82DB, (q15_t)0x1AE4,
+ (q15_t)0x82C6, (q15_t)0x1A82, (q15_t)0x82B1, (q15_t)0x1A20,
+ (q15_t)0x829D, (q15_t)0x19BD, (q15_t)0x8289, (q15_t)0x195B,
+ (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x8262, (q15_t)0x1896,
+ (q15_t)0x824F, (q15_t)0x1833, (q15_t)0x823C, (q15_t)0x17D0,
+ (q15_t)0x8229, (q15_t)0x176D, (q15_t)0x8217, (q15_t)0x170A,
+ (q15_t)0x8205, (q15_t)0x16A8, (q15_t)0x81F3, (q15_t)0x1645,
+ (q15_t)0x81E2, (q15_t)0x15E2, (q15_t)0x81D1, (q15_t)0x157F,
+ (q15_t)0x81C0, (q15_t)0x151B, (q15_t)0x81B0, (q15_t)0x14B8,
+ (q15_t)0x81A0, (q15_t)0x1455, (q15_t)0x8190, (q15_t)0x13F2,
+ (q15_t)0x8180, (q15_t)0x138E, (q15_t)0x8171, (q15_t)0x132B,
+ (q15_t)0x8162, (q15_t)0x12C8, (q15_t)0x8154, (q15_t)0x1264,
+ (q15_t)0x8145, (q15_t)0x1201, (q15_t)0x8137, (q15_t)0x119D,
+ (q15_t)0x812A, (q15_t)0x1139, (q15_t)0x811C, (q15_t)0x10D6,
+ (q15_t)0x810F, (q15_t)0x1072, (q15_t)0x8102, (q15_t)0x100E,
+ (q15_t)0x80F6, (q15_t)0x0FAB, (q15_t)0x80EA, (q15_t)0x0F47,
+ (q15_t)0x80DE, (q15_t)0x0EE3, (q15_t)0x80D2, (q15_t)0x0E7F,
+ (q15_t)0x80C7, (q15_t)0x0E1B, (q15_t)0x80BC, (q15_t)0x0DB7,
+ (q15_t)0x80B2, (q15_t)0x0D53, (q15_t)0x80A7, (q15_t)0x0CEF,
+ (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x8094, (q15_t)0x0C27,
+ (q15_t)0x808A, (q15_t)0x0BC3, (q15_t)0x8081, (q15_t)0x0B5F,
+ (q15_t)0x8078, (q15_t)0x0AFB, (q15_t)0x8070, (q15_t)0x0A97,
+ (q15_t)0x8068, (q15_t)0x0A33, (q15_t)0x8060, (q15_t)0x09CE,
+ (q15_t)0x8058, (q15_t)0x096A, (q15_t)0x8051, (q15_t)0x0906,
+ (q15_t)0x804A, (q15_t)0x08A2, (q15_t)0x8043, (q15_t)0x083D,
+ (q15_t)0x803D, (q15_t)0x07D9, (q15_t)0x8037, (q15_t)0x0775,
+ (q15_t)0x8031, (q15_t)0x0710, (q15_t)0x802C, (q15_t)0x06AC,
+ (q15_t)0x8027, (q15_t)0x0647, (q15_t)0x8022, (q15_t)0x05E3,
+ (q15_t)0x801E, (q15_t)0x057F, (q15_t)0x801A, (q15_t)0x051A,
+ (q15_t)0x8016, (q15_t)0x04B6, (q15_t)0x8012, (q15_t)0x0451,
+ (q15_t)0x800F, (q15_t)0x03ED, (q15_t)0x800C, (q15_t)0x0388,
+ (q15_t)0x8009, (q15_t)0x0324, (q15_t)0x8007, (q15_t)0x02BF,
+ (q15_t)0x8005, (q15_t)0x025B, (q15_t)0x8003, (q15_t)0x01F6,
+ (q15_t)0x8002, (q15_t)0x0192, (q15_t)0x8001, (q15_t)0x012D,
+ (q15_t)0x8000, (q15_t)0x00C9, (q15_t)0x8000, (q15_t)0x0064,
+ (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8000, (q15_t)0xFF9B,
+ (q15_t)0x8000, (q15_t)0xFF36, (q15_t)0x8001, (q15_t)0xFED2,
+ (q15_t)0x8002, (q15_t)0xFE6D, (q15_t)0x8003, (q15_t)0xFE09,
+ (q15_t)0x8005, (q15_t)0xFDA4, (q15_t)0x8007, (q15_t)0xFD40,
+ (q15_t)0x8009, (q15_t)0xFCDB, (q15_t)0x800C, (q15_t)0xFC77,
+ (q15_t)0x800F, (q15_t)0xFC12, (q15_t)0x8012, (q15_t)0xFBAE,
+ (q15_t)0x8016, (q15_t)0xFB49, (q15_t)0x801A, (q15_t)0xFAE5,
+ (q15_t)0x801E, (q15_t)0xFA80, (q15_t)0x8022, (q15_t)0xFA1C,
+ (q15_t)0x8027, (q15_t)0xF9B8, (q15_t)0x802C, (q15_t)0xF953,
+ (q15_t)0x8031, (q15_t)0xF8EF, (q15_t)0x8037, (q15_t)0xF88A,
+ (q15_t)0x803D, (q15_t)0xF826, (q15_t)0x8043, (q15_t)0xF7C2,
+ (q15_t)0x804A, (q15_t)0xF75D, (q15_t)0x8051, (q15_t)0xF6F9,
+ (q15_t)0x8058, (q15_t)0xF695, (q15_t)0x8060, (q15_t)0xF631,
+ (q15_t)0x8068, (q15_t)0xF5CC, (q15_t)0x8070, (q15_t)0xF568,
+ (q15_t)0x8078, (q15_t)0xF504, (q15_t)0x8081, (q15_t)0xF4A0,
+ (q15_t)0x808A, (q15_t)0xF43C, (q15_t)0x8094, (q15_t)0xF3D8,
+ (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x80A7, (q15_t)0xF310,
+ (q15_t)0x80B2, (q15_t)0xF2AC, (q15_t)0x80BC, (q15_t)0xF248,
+ (q15_t)0x80C7, (q15_t)0xF1E4, (q15_t)0x80D2, (q15_t)0xF180,
+ (q15_t)0x80DE, (q15_t)0xF11C, (q15_t)0x80EA, (q15_t)0xF0B8,
+ (q15_t)0x80F6, (q15_t)0xF054, (q15_t)0x8102, (q15_t)0xEFF1,
+ (q15_t)0x810F, (q15_t)0xEF8D, (q15_t)0x811C, (q15_t)0xEF29,
+ (q15_t)0x812A, (q15_t)0xEEC6, (q15_t)0x8137, (q15_t)0xEE62,
+ (q15_t)0x8145, (q15_t)0xEDFE, (q15_t)0x8154, (q15_t)0xED9B,
+ (q15_t)0x8162, (q15_t)0xED37, (q15_t)0x8171, (q15_t)0xECD4,
+ (q15_t)0x8180, (q15_t)0xEC71, (q15_t)0x8190, (q15_t)0xEC0D,
+ (q15_t)0x81A0, (q15_t)0xEBAA, (q15_t)0x81B0, (q15_t)0xEB47,
+ (q15_t)0x81C0, (q15_t)0xEAE4, (q15_t)0x81D1, (q15_t)0xEA80,
+ (q15_t)0x81E2, (q15_t)0xEA1D, (q15_t)0x81F3, (q15_t)0xE9BA,
+ (q15_t)0x8205, (q15_t)0xE957, (q15_t)0x8217, (q15_t)0xE8F5,
+ (q15_t)0x8229, (q15_t)0xE892, (q15_t)0x823C, (q15_t)0xE82F,
+ (q15_t)0x824F, (q15_t)0xE7CC, (q15_t)0x8262, (q15_t)0xE769,
+ (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x8289, (q15_t)0xE6A4,
+ (q15_t)0x829D, (q15_t)0xE642, (q15_t)0x82B1, (q15_t)0xE5DF,
+ (q15_t)0x82C6, (q15_t)0xE57D, (q15_t)0x82DB, (q15_t)0xE51B,
+ (q15_t)0x82F0, (q15_t)0xE4B8, (q15_t)0x8306, (q15_t)0xE456,
+ (q15_t)0x831C, (q15_t)0xE3F4, (q15_t)0x8332, (q15_t)0xE392,
+ (q15_t)0x8348, (q15_t)0xE330, (q15_t)0x835F, (q15_t)0xE2CE,
+ (q15_t)0x8376, (q15_t)0xE26C, (q15_t)0x838E, (q15_t)0xE20A,
+ (q15_t)0x83A5, (q15_t)0xE1A9, (q15_t)0x83BD, (q15_t)0xE147,
+ (q15_t)0x83D6, (q15_t)0xE0E6, (q15_t)0x83EE, (q15_t)0xE084,
+ (q15_t)0x8407, (q15_t)0xE023, (q15_t)0x8420, (q15_t)0xDFC1,
+ (q15_t)0x843A, (q15_t)0xDF60, (q15_t)0x8453, (q15_t)0xDEFF,
+ (q15_t)0x846D, (q15_t)0xDE9E, (q15_t)0x8488, (q15_t)0xDE3D,
+ (q15_t)0x84A2, (q15_t)0xDDDC, (q15_t)0x84BD, (q15_t)0xDD7B,
+ (q15_t)0x84D9, (q15_t)0xDD1A, (q15_t)0x84F4, (q15_t)0xDCBA,
+ (q15_t)0x8510, (q15_t)0xDC59, (q15_t)0x852C, (q15_t)0xDBF8,
+ (q15_t)0x8549, (q15_t)0xDB98, (q15_t)0x8565, (q15_t)0xDB38,
+ (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x85A0, (q15_t)0xDA77,
+ (q15_t)0x85BD, (q15_t)0xDA17, (q15_t)0x85DB, (q15_t)0xD9B7,
+ (q15_t)0x85FA, (q15_t)0xD957, (q15_t)0x8618, (q15_t)0xD8F8,
+ (q15_t)0x8637, (q15_t)0xD898, (q15_t)0x8656, (q15_t)0xD838,
+ (q15_t)0x8675, (q15_t)0xD7D9, (q15_t)0x8695, (q15_t)0xD779,
+ (q15_t)0x86B5, (q15_t)0xD71A, (q15_t)0x86D5, (q15_t)0xD6BB,
+ (q15_t)0x86F6, (q15_t)0xD65C, (q15_t)0x8717, (q15_t)0xD5FD,
+ (q15_t)0x8738, (q15_t)0xD59E, (q15_t)0x8759, (q15_t)0xD53F,
+ (q15_t)0x877B, (q15_t)0xD4E0, (q15_t)0x879D, (q15_t)0xD482,
+ (q15_t)0x87BF, (q15_t)0xD423, (q15_t)0x87E2, (q15_t)0xD3C5,
+ (q15_t)0x8805, (q15_t)0xD367, (q15_t)0x8828, (q15_t)0xD308,
+ (q15_t)0x884B, (q15_t)0xD2AA, (q15_t)0x886F, (q15_t)0xD24C,
+ (q15_t)0x8893, (q15_t)0xD1EE, (q15_t)0x88B8, (q15_t)0xD191,
+ (q15_t)0x88DC, (q15_t)0xD133, (q15_t)0x8901, (q15_t)0xD0D6,
+ (q15_t)0x8926, (q15_t)0xD078, (q15_t)0x894C, (q15_t)0xD01B,
+ (q15_t)0x8971, (q15_t)0xCFBE, (q15_t)0x8997, (q15_t)0xCF61,
+ (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x89E4, (q15_t)0xCEA7,
+ (q15_t)0x8A0B, (q15_t)0xCE4A, (q15_t)0x8A33, (q15_t)0xCDEE,
+ (q15_t)0x8A5A, (q15_t)0xCD91, (q15_t)0x8A82, (q15_t)0xCD35,
+ (q15_t)0x8AAA, (q15_t)0xCCD9, (q15_t)0x8AD2, (q15_t)0xCC7D,
+ (q15_t)0x8AFB, (q15_t)0xCC21, (q15_t)0x8B24, (q15_t)0xCBC5,
+ (q15_t)0x8B4D, (q15_t)0xCB69, (q15_t)0x8B76, (q15_t)0xCB0D,
+ (q15_t)0x8BA0, (q15_t)0xCAB2, (q15_t)0x8BCA, (q15_t)0xCA57,
+ (q15_t)0x8BF4, (q15_t)0xC9FB, (q15_t)0x8C1F, (q15_t)0xC9A0,
+ (q15_t)0x8C4A, (q15_t)0xC945, (q15_t)0x8C75, (q15_t)0xC8EB,
+ (q15_t)0x8CA0, (q15_t)0xC890, (q15_t)0x8CCC, (q15_t)0xC835,
+ (q15_t)0x8CF8, (q15_t)0xC7DB, (q15_t)0x8D24, (q15_t)0xC781,
+ (q15_t)0x8D50, (q15_t)0xC727, (q15_t)0x8D7D, (q15_t)0xC6CD,
+ (q15_t)0x8DAA, (q15_t)0xC673, (q15_t)0x8DD8, (q15_t)0xC619,
+ (q15_t)0x8E05, (q15_t)0xC5BF, (q15_t)0x8E33, (q15_t)0xC566,
+ (q15_t)0x8E61, (q15_t)0xC50D, (q15_t)0x8E90, (q15_t)0xC4B3,
+ (q15_t)0x8EBE, (q15_t)0xC45A, (q15_t)0x8EED, (q15_t)0xC402,
+ (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x8F4C, (q15_t)0xC350,
+ (q15_t)0x8F7C, (q15_t)0xC2F8, (q15_t)0x8FAC, (q15_t)0xC29F,
+ (q15_t)0x8FDC, (q15_t)0xC247, (q15_t)0x900D, (q15_t)0xC1EF,
+ (q15_t)0x903E, (q15_t)0xC197, (q15_t)0x906F, (q15_t)0xC140,
+ (q15_t)0x90A0, (q15_t)0xC0E8, (q15_t)0x90D2, (q15_t)0xC091,
+ (q15_t)0x9104, (q15_t)0xC03A, (q15_t)0x9136, (q15_t)0xBFE2,
+ (q15_t)0x9169, (q15_t)0xBF8C, (q15_t)0x919C, (q15_t)0xBF35,
+ (q15_t)0x91CF, (q15_t)0xBEDE, (q15_t)0x9202, (q15_t)0xBE88,
+ (q15_t)0x9235, (q15_t)0xBE31, (q15_t)0x9269, (q15_t)0xBDDB,
+ (q15_t)0x929D, (q15_t)0xBD85, (q15_t)0x92D2, (q15_t)0xBD2F,
+ (q15_t)0x9306, (q15_t)0xBCDA, (q15_t)0x933B, (q15_t)0xBC84,
+ (q15_t)0x9370, (q15_t)0xBC2F, (q15_t)0x93A6, (q15_t)0xBBDA,
+ (q15_t)0x93DB, (q15_t)0xBB85, (q15_t)0x9411, (q15_t)0xBB30,
+ (q15_t)0x9447, (q15_t)0xBADB, (q15_t)0x947E, (q15_t)0xBA87,
+ (q15_t)0x94B5, (q15_t)0xBA32, (q15_t)0x94EC, (q15_t)0xB9DE,
+ (q15_t)0x9523, (q15_t)0xB98A, (q15_t)0x955A, (q15_t)0xB936,
+ (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x95CA, (q15_t)0xB88F,
+ (q15_t)0x9602, (q15_t)0xB83C, (q15_t)0x963B, (q15_t)0xB7E9,
+ (q15_t)0x9673, (q15_t)0xB796, (q15_t)0x96AC, (q15_t)0xB743,
+ (q15_t)0x96E6, (q15_t)0xB6F0, (q15_t)0x971F, (q15_t)0xB69E,
+ (q15_t)0x9759, (q15_t)0xB64B, (q15_t)0x9793, (q15_t)0xB5F9,
+ (q15_t)0x97CD, (q15_t)0xB5A7, (q15_t)0x9808, (q15_t)0xB556,
+ (q15_t)0x9842, (q15_t)0xB504, (q15_t)0x987D, (q15_t)0xB4B3,
+ (q15_t)0x98B9, (q15_t)0xB461, (q15_t)0x98F4, (q15_t)0xB410,
+ (q15_t)0x9930, (q15_t)0xB3C0, (q15_t)0x996C, (q15_t)0xB36F,
+ (q15_t)0x99A8, (q15_t)0xB31E, (q15_t)0x99E5, (q15_t)0xB2CE,
+ (q15_t)0x9A22, (q15_t)0xB27E, (q15_t)0x9A5F, (q15_t)0xB22E,
+ (q15_t)0x9A9C, (q15_t)0xB1DE, (q15_t)0x9AD9, (q15_t)0xB18F,
+ (q15_t)0x9B17, (q15_t)0xB140, (q15_t)0x9B55, (q15_t)0xB0F0,
+ (q15_t)0x9B93, (q15_t)0xB0A1, (q15_t)0x9BD2, (q15_t)0xB053,
+ (q15_t)0x9C10, (q15_t)0xB004, (q15_t)0x9C4F, (q15_t)0xAFB6,
+ (q15_t)0x9C8E, (q15_t)0xAF68, (q15_t)0x9CCE, (q15_t)0xAF1A,
+ (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0x9D4D, (q15_t)0xAE7E,
+ (q15_t)0x9D8E, (q15_t)0xAE31, (q15_t)0x9DCE, (q15_t)0xADE3,
+ (q15_t)0x9E0E, (q15_t)0xAD96, (q15_t)0x9E4F, (q15_t)0xAD4A,
+ (q15_t)0x9E90, (q15_t)0xACFD, (q15_t)0x9ED2, (q15_t)0xACB1,
+ (q15_t)0x9F13, (q15_t)0xAC64, (q15_t)0x9F55, (q15_t)0xAC18,
+ (q15_t)0x9F97, (q15_t)0xABCC, (q15_t)0x9FD9, (q15_t)0xAB81,
+ (q15_t)0xA01C, (q15_t)0xAB35, (q15_t)0xA05F, (q15_t)0xAAEA,
+ (q15_t)0xA0A1, (q15_t)0xAA9F, (q15_t)0xA0E5, (q15_t)0xAA54,
+ (q15_t)0xA128, (q15_t)0xAA0A, (q15_t)0xA16C, (q15_t)0xA9BF,
+ (q15_t)0xA1AF, (q15_t)0xA975, (q15_t)0xA1F4, (q15_t)0xA92B,
+ (q15_t)0xA238, (q15_t)0xA8E2, (q15_t)0xA27C, (q15_t)0xA898,
+ (q15_t)0xA2C1, (q15_t)0xA84F, (q15_t)0xA306, (q15_t)0xA806,
+ (q15_t)0xA34B, (q15_t)0xA7BD, (q15_t)0xA391, (q15_t)0xA774,
+ (q15_t)0xA3D6, (q15_t)0xA72B, (q15_t)0xA41C, (q15_t)0xA6E3,
+ (q15_t)0xA462, (q15_t)0xA69B, (q15_t)0xA4A9, (q15_t)0xA653,
+ (q15_t)0xA4EF, (q15_t)0xA60C, (q15_t)0xA536, (q15_t)0xA5C4,
+ (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xA5C4, (q15_t)0xA536,
+ (q15_t)0xA60C, (q15_t)0xA4EF, (q15_t)0xA653, (q15_t)0xA4A9,
+ (q15_t)0xA69B, (q15_t)0xA462, (q15_t)0xA6E3, (q15_t)0xA41C,
+ (q15_t)0xA72B, (q15_t)0xA3D6, (q15_t)0xA774, (q15_t)0xA391,
+ (q15_t)0xA7BD, (q15_t)0xA34B, (q15_t)0xA806, (q15_t)0xA306,
+ (q15_t)0xA84F, (q15_t)0xA2C1, (q15_t)0xA898, (q15_t)0xA27C,
+ (q15_t)0xA8E2, (q15_t)0xA238, (q15_t)0xA92B, (q15_t)0xA1F4,
+ (q15_t)0xA975, (q15_t)0xA1AF, (q15_t)0xA9BF, (q15_t)0xA16C,
+ (q15_t)0xAA0A, (q15_t)0xA128, (q15_t)0xAA54, (q15_t)0xA0E5,
+ (q15_t)0xAA9F, (q15_t)0xA0A1, (q15_t)0xAAEA, (q15_t)0xA05F,
+ (q15_t)0xAB35, (q15_t)0xA01C, (q15_t)0xAB81, (q15_t)0x9FD9,
+ (q15_t)0xABCC, (q15_t)0x9F97, (q15_t)0xAC18, (q15_t)0x9F55,
+ (q15_t)0xAC64, (q15_t)0x9F13, (q15_t)0xACB1, (q15_t)0x9ED2,
+ (q15_t)0xACFD, (q15_t)0x9E90, (q15_t)0xAD4A, (q15_t)0x9E4F,
+ (q15_t)0xAD96, (q15_t)0x9E0E, (q15_t)0xADE3, (q15_t)0x9DCE,
+ (q15_t)0xAE31, (q15_t)0x9D8E, (q15_t)0xAE7E, (q15_t)0x9D4D,
+ (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xAF1A, (q15_t)0x9CCE,
+ (q15_t)0xAF68, (q15_t)0x9C8E, (q15_t)0xAFB6, (q15_t)0x9C4F,
+ (q15_t)0xB004, (q15_t)0x9C10, (q15_t)0xB053, (q15_t)0x9BD2,
+ (q15_t)0xB0A1, (q15_t)0x9B93, (q15_t)0xB0F0, (q15_t)0x9B55,
+ (q15_t)0xB140, (q15_t)0x9B17, (q15_t)0xB18F, (q15_t)0x9AD9,
+ (q15_t)0xB1DE, (q15_t)0x9A9C, (q15_t)0xB22E, (q15_t)0x9A5F,
+ (q15_t)0xB27E, (q15_t)0x9A22, (q15_t)0xB2CE, (q15_t)0x99E5,
+ (q15_t)0xB31E, (q15_t)0x99A8, (q15_t)0xB36F, (q15_t)0x996C,
+ (q15_t)0xB3C0, (q15_t)0x9930, (q15_t)0xB410, (q15_t)0x98F4,
+ (q15_t)0xB461, (q15_t)0x98B9, (q15_t)0xB4B3, (q15_t)0x987D,
+ (q15_t)0xB504, (q15_t)0x9842, (q15_t)0xB556, (q15_t)0x9808,
+ (q15_t)0xB5A7, (q15_t)0x97CD, (q15_t)0xB5F9, (q15_t)0x9793,
+ (q15_t)0xB64B, (q15_t)0x9759, (q15_t)0xB69E, (q15_t)0x971F,
+ (q15_t)0xB6F0, (q15_t)0x96E6, (q15_t)0xB743, (q15_t)0x96AC,
+ (q15_t)0xB796, (q15_t)0x9673, (q15_t)0xB7E9, (q15_t)0x963B,
+ (q15_t)0xB83C, (q15_t)0x9602, (q15_t)0xB88F, (q15_t)0x95CA,
+ (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xB936, (q15_t)0x955A,
+ (q15_t)0xB98A, (q15_t)0x9523, (q15_t)0xB9DE, (q15_t)0x94EC,
+ (q15_t)0xBA32, (q15_t)0x94B5, (q15_t)0xBA87, (q15_t)0x947E,
+ (q15_t)0xBADB, (q15_t)0x9447, (q15_t)0xBB30, (q15_t)0x9411,
+ (q15_t)0xBB85, (q15_t)0x93DB, (q15_t)0xBBDA, (q15_t)0x93A6,
+ (q15_t)0xBC2F, (q15_t)0x9370, (q15_t)0xBC84, (q15_t)0x933B,
+ (q15_t)0xBCDA, (q15_t)0x9306, (q15_t)0xBD2F, (q15_t)0x92D2,
+ (q15_t)0xBD85, (q15_t)0x929D, (q15_t)0xBDDB, (q15_t)0x9269,
+ (q15_t)0xBE31, (q15_t)0x9235, (q15_t)0xBE88, (q15_t)0x9202,
+ (q15_t)0xBEDE, (q15_t)0x91CF, (q15_t)0xBF35, (q15_t)0x919C,
+ (q15_t)0xBF8C, (q15_t)0x9169, (q15_t)0xBFE2, (q15_t)0x9136,
+ (q15_t)0xC03A, (q15_t)0x9104, (q15_t)0xC091, (q15_t)0x90D2,
+ (q15_t)0xC0E8, (q15_t)0x90A0, (q15_t)0xC140, (q15_t)0x906F,
+ (q15_t)0xC197, (q15_t)0x903E, (q15_t)0xC1EF, (q15_t)0x900D,
+ (q15_t)0xC247, (q15_t)0x8FDC, (q15_t)0xC29F, (q15_t)0x8FAC,
+ (q15_t)0xC2F8, (q15_t)0x8F7C, (q15_t)0xC350, (q15_t)0x8F4C,
+ (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC402, (q15_t)0x8EED,
+ (q15_t)0xC45A, (q15_t)0x8EBE, (q15_t)0xC4B3, (q15_t)0x8E90,
+ (q15_t)0xC50D, (q15_t)0x8E61, (q15_t)0xC566, (q15_t)0x8E33,
+ (q15_t)0xC5BF, (q15_t)0x8E05, (q15_t)0xC619, (q15_t)0x8DD8,
+ (q15_t)0xC673, (q15_t)0x8DAA, (q15_t)0xC6CD, (q15_t)0x8D7D,
+ (q15_t)0xC727, (q15_t)0x8D50, (q15_t)0xC781, (q15_t)0x8D24,
+ (q15_t)0xC7DB, (q15_t)0x8CF8, (q15_t)0xC835, (q15_t)0x8CCC,
+ (q15_t)0xC890, (q15_t)0x8CA0, (q15_t)0xC8EB, (q15_t)0x8C75,
+ (q15_t)0xC945, (q15_t)0x8C4A, (q15_t)0xC9A0, (q15_t)0x8C1F,
+ (q15_t)0xC9FB, (q15_t)0x8BF4, (q15_t)0xCA57, (q15_t)0x8BCA,
+ (q15_t)0xCAB2, (q15_t)0x8BA0, (q15_t)0xCB0D, (q15_t)0x8B76,
+ (q15_t)0xCB69, (q15_t)0x8B4D, (q15_t)0xCBC5, (q15_t)0x8B24,
+ (q15_t)0xCC21, (q15_t)0x8AFB, (q15_t)0xCC7D, (q15_t)0x8AD2,
+ (q15_t)0xCCD9, (q15_t)0x8AAA, (q15_t)0xCD35, (q15_t)0x8A82,
+ (q15_t)0xCD91, (q15_t)0x8A5A, (q15_t)0xCDEE, (q15_t)0x8A33,
+ (q15_t)0xCE4A, (q15_t)0x8A0B, (q15_t)0xCEA7, (q15_t)0x89E4,
+ (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xCF61, (q15_t)0x8997,
+ (q15_t)0xCFBE, (q15_t)0x8971, (q15_t)0xD01B, (q15_t)0x894C,
+ (q15_t)0xD078, (q15_t)0x8926, (q15_t)0xD0D6, (q15_t)0x8901,
+ (q15_t)0xD133, (q15_t)0x88DC, (q15_t)0xD191, (q15_t)0x88B8,
+ (q15_t)0xD1EE, (q15_t)0x8893, (q15_t)0xD24C, (q15_t)0x886F,
+ (q15_t)0xD2AA, (q15_t)0x884B, (q15_t)0xD308, (q15_t)0x8828,
+ (q15_t)0xD367, (q15_t)0x8805, (q15_t)0xD3C5, (q15_t)0x87E2,
+ (q15_t)0xD423, (q15_t)0x87BF, (q15_t)0xD482, (q15_t)0x879D,
+ (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD53F, (q15_t)0x8759,
+ (q15_t)0xD59E, (q15_t)0x8738, (q15_t)0xD5FD, (q15_t)0x8717,
+ (q15_t)0xD65C, (q15_t)0x86F6, (q15_t)0xD6BB, (q15_t)0x86D5,
+ (q15_t)0xD71A, (q15_t)0x86B5, (q15_t)0xD779, (q15_t)0x8695,
+ (q15_t)0xD7D9, (q15_t)0x8675, (q15_t)0xD838, (q15_t)0x8656,
+ (q15_t)0xD898, (q15_t)0x8637, (q15_t)0xD8F8, (q15_t)0x8618,
+ (q15_t)0xD957, (q15_t)0x85FA, (q15_t)0xD9B7, (q15_t)0x85DB,
+ (q15_t)0xDA17, (q15_t)0x85BD, (q15_t)0xDA77, (q15_t)0x85A0,
+ (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDB38, (q15_t)0x8565,
+ (q15_t)0xDB98, (q15_t)0x8549, (q15_t)0xDBF8, (q15_t)0x852C,
+ (q15_t)0xDC59, (q15_t)0x8510, (q15_t)0xDCBA, (q15_t)0x84F4,
+ (q15_t)0xDD1A, (q15_t)0x84D9, (q15_t)0xDD7B, (q15_t)0x84BD,
+ (q15_t)0xDDDC, (q15_t)0x84A2, (q15_t)0xDE3D, (q15_t)0x8488,
+ (q15_t)0xDE9E, (q15_t)0x846D, (q15_t)0xDEFF, (q15_t)0x8453,
+ (q15_t)0xDF60, (q15_t)0x843A, (q15_t)0xDFC1, (q15_t)0x8420,
+ (q15_t)0xE023, (q15_t)0x8407, (q15_t)0xE084, (q15_t)0x83EE,
+ (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE147, (q15_t)0x83BD,
+ (q15_t)0xE1A9, (q15_t)0x83A5, (q15_t)0xE20A, (q15_t)0x838E,
+ (q15_t)0xE26C, (q15_t)0x8376, (q15_t)0xE2CE, (q15_t)0x835F,
+ (q15_t)0xE330, (q15_t)0x8348, (q15_t)0xE392, (q15_t)0x8332,
+ (q15_t)0xE3F4, (q15_t)0x831C, (q15_t)0xE456, (q15_t)0x8306,
+ (q15_t)0xE4B8, (q15_t)0x82F0, (q15_t)0xE51B, (q15_t)0x82DB,
+ (q15_t)0xE57D, (q15_t)0x82C6, (q15_t)0xE5DF, (q15_t)0x82B1,
+ (q15_t)0xE642, (q15_t)0x829D, (q15_t)0xE6A4, (q15_t)0x8289,
+ (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xE769, (q15_t)0x8262,
+ (q15_t)0xE7CC, (q15_t)0x824F, (q15_t)0xE82F, (q15_t)0x823C,
+ (q15_t)0xE892, (q15_t)0x8229, (q15_t)0xE8F5, (q15_t)0x8217,
+ (q15_t)0xE957, (q15_t)0x8205, (q15_t)0xE9BA, (q15_t)0x81F3,
+ (q15_t)0xEA1D, (q15_t)0x81E2, (q15_t)0xEA80, (q15_t)0x81D1,
+ (q15_t)0xEAE4, (q15_t)0x81C0, (q15_t)0xEB47, (q15_t)0x81B0,
+ (q15_t)0xEBAA, (q15_t)0x81A0, (q15_t)0xEC0D, (q15_t)0x8190,
+ (q15_t)0xEC71, (q15_t)0x8180, (q15_t)0xECD4, (q15_t)0x8171,
+ (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xED9B, (q15_t)0x8154,
+ (q15_t)0xEDFE, (q15_t)0x8145, (q15_t)0xEE62, (q15_t)0x8137,
+ (q15_t)0xEEC6, (q15_t)0x812A, (q15_t)0xEF29, (q15_t)0x811C,
+ (q15_t)0xEF8D, (q15_t)0x810F, (q15_t)0xEFF1, (q15_t)0x8102,
+ (q15_t)0xF054, (q15_t)0x80F6, (q15_t)0xF0B8, (q15_t)0x80EA,
+ (q15_t)0xF11C, (q15_t)0x80DE, (q15_t)0xF180, (q15_t)0x80D2,
+ (q15_t)0xF1E4, (q15_t)0x80C7, (q15_t)0xF248, (q15_t)0x80BC,
+ (q15_t)0xF2AC, (q15_t)0x80B2, (q15_t)0xF310, (q15_t)0x80A7,
+ (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF3D8, (q15_t)0x8094,
+ (q15_t)0xF43C, (q15_t)0x808A, (q15_t)0xF4A0, (q15_t)0x8081,
+ (q15_t)0xF504, (q15_t)0x8078, (q15_t)0xF568, (q15_t)0x8070,
+ (q15_t)0xF5CC, (q15_t)0x8068, (q15_t)0xF631, (q15_t)0x8060,
+ (q15_t)0xF695, (q15_t)0x8058, (q15_t)0xF6F9, (q15_t)0x8051,
+ (q15_t)0xF75D, (q15_t)0x804A, (q15_t)0xF7C2, (q15_t)0x8043,
+ (q15_t)0xF826, (q15_t)0x803D, (q15_t)0xF88A, (q15_t)0x8037,
+ (q15_t)0xF8EF, (q15_t)0x8031, (q15_t)0xF953, (q15_t)0x802C,
+ (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xFA1C, (q15_t)0x8022,
+ (q15_t)0xFA80, (q15_t)0x801E, (q15_t)0xFAE5, (q15_t)0x801A,
+ (q15_t)0xFB49, (q15_t)0x8016, (q15_t)0xFBAE, (q15_t)0x8012,
+ (q15_t)0xFC12, (q15_t)0x800F, (q15_t)0xFC77, (q15_t)0x800C,
+ (q15_t)0xFCDB, (q15_t)0x8009, (q15_t)0xFD40, (q15_t)0x8007,
+ (q15_t)0xFDA4, (q15_t)0x8005, (q15_t)0xFE09, (q15_t)0x8003,
+ (q15_t)0xFE6D, (q15_t)0x8002, (q15_t)0xFED2, (q15_t)0x8001,
+ (q15_t)0xFF36, (q15_t)0x8000, (q15_t)0xFF9B, (q15_t)0x8000
+};
+
+/**
+* \par
+* Example code for q15 Twiddle factors Generation::
+* \par
+* <pre>for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 4096 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to q15(Fixed point 1.15):
+* round(twiddleCoefq15(i) * pow(2, 15))
+*
+*/
+const q15_t twiddleCoef_4096_q15[6144] =
+{
+ (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0x0032,
+ (q15_t)0x7FFF, (q15_t)0x0064, (q15_t)0x7FFF, (q15_t)0x0096,
+ (q15_t)0x7FFF, (q15_t)0x00C9, (q15_t)0x7FFF, (q15_t)0x00FB,
+ (q15_t)0x7FFE, (q15_t)0x012D, (q15_t)0x7FFE, (q15_t)0x015F,
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+ (q15_t)0x09CE, (q15_t)0x7F9F, (q15_t)0x099C, (q15_t)0x7FA3,
+ (q15_t)0x096A, (q15_t)0x7FA7, (q15_t)0x0938, (q15_t)0x7FAA,
+ (q15_t)0x0906, (q15_t)0x7FAE, (q15_t)0x08D4, (q15_t)0x7FB1,
+ (q15_t)0x08A2, (q15_t)0x7FB5, (q15_t)0x086F, (q15_t)0x7FB8,
+ (q15_t)0x083D, (q15_t)0x7FBC, (q15_t)0x080B, (q15_t)0x7FBF,
+ (q15_t)0x07D9, (q15_t)0x7FC2, (q15_t)0x07A7, (q15_t)0x7FC5,
+ (q15_t)0x0775, (q15_t)0x7FC8, (q15_t)0x0742, (q15_t)0x7FCB,
+ (q15_t)0x0710, (q15_t)0x7FCE, (q15_t)0x06DE, (q15_t)0x7FD0,
+ (q15_t)0x06AC, (q15_t)0x7FD3, (q15_t)0x067A, (q15_t)0x7FD6,
+ (q15_t)0x0647, (q15_t)0x7FD8, (q15_t)0x0615, (q15_t)0x7FDA,
+ (q15_t)0x05E3, (q15_t)0x7FDD, (q15_t)0x05B1, (q15_t)0x7FDF,
+ (q15_t)0x057F, (q15_t)0x7FE1, (q15_t)0x054C, (q15_t)0x7FE3,
+ (q15_t)0x051A, (q15_t)0x7FE5, (q15_t)0x04E8, (q15_t)0x7FE7,
+ (q15_t)0x04B6, (q15_t)0x7FE9, (q15_t)0x0483, (q15_t)0x7FEB,
+ (q15_t)0x0451, (q15_t)0x7FED, (q15_t)0x041F, (q15_t)0x7FEE,
+ (q15_t)0x03ED, (q15_t)0x7FF0, (q15_t)0x03BA, (q15_t)0x7FF2,
+ (q15_t)0x0388, (q15_t)0x7FF3, (q15_t)0x0356, (q15_t)0x7FF4,
+ (q15_t)0x0324, (q15_t)0x7FF6, (q15_t)0x02F1, (q15_t)0x7FF7,
+ (q15_t)0x02BF, (q15_t)0x7FF8, (q15_t)0x028D, (q15_t)0x7FF9,
+ (q15_t)0x025B, (q15_t)0x7FFA, (q15_t)0x0228, (q15_t)0x7FFB,
+ (q15_t)0x01F6, (q15_t)0x7FFC, (q15_t)0x01C4, (q15_t)0x7FFC,
+ (q15_t)0x0192, (q15_t)0x7FFD, (q15_t)0x015F, (q15_t)0x7FFE,
+ (q15_t)0x012D, (q15_t)0x7FFE, (q15_t)0x00FB, (q15_t)0x7FFF,
+ (q15_t)0x00C9, (q15_t)0x7FFF, (q15_t)0x0096, (q15_t)0x7FFF,
+ (q15_t)0x0064, (q15_t)0x7FFF, (q15_t)0x0032, (q15_t)0x7FFF,
+ (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xFFCD, (q15_t)0x7FFF,
+ (q15_t)0xFF9B, (q15_t)0x7FFF, (q15_t)0xFF69, (q15_t)0x7FFF,
+ (q15_t)0xFF36, (q15_t)0x7FFF, (q15_t)0xFF04, (q15_t)0x7FFF,
+ (q15_t)0xFED2, (q15_t)0x7FFE, (q15_t)0xFEA0, (q15_t)0x7FFE,
+ (q15_t)0xFE6D, (q15_t)0x7FFD, (q15_t)0xFE3B, (q15_t)0x7FFC,
+ (q15_t)0xFE09, (q15_t)0x7FFC, (q15_t)0xFDD7, (q15_t)0x7FFB,
+ (q15_t)0xFDA4, (q15_t)0x7FFA, (q15_t)0xFD72, (q15_t)0x7FF9,
+ (q15_t)0xFD40, (q15_t)0x7FF8, (q15_t)0xFD0E, (q15_t)0x7FF7,
+ (q15_t)0xFCDB, (q15_t)0x7FF6, (q15_t)0xFCA9, (q15_t)0x7FF4,
+ (q15_t)0xFC77, (q15_t)0x7FF3, (q15_t)0xFC45, (q15_t)0x7FF2,
+ (q15_t)0xFC12, (q15_t)0x7FF0, (q15_t)0xFBE0, (q15_t)0x7FEE,
+ (q15_t)0xFBAE, (q15_t)0x7FED, (q15_t)0xFB7C, (q15_t)0x7FEB,
+ (q15_t)0xFB49, (q15_t)0x7FE9, (q15_t)0xFB17, (q15_t)0x7FE7,
+ (q15_t)0xFAE5, (q15_t)0x7FE5, (q15_t)0xFAB3, (q15_t)0x7FE3,
+ (q15_t)0xFA80, (q15_t)0x7FE1, (q15_t)0xFA4E, (q15_t)0x7FDF,
+ (q15_t)0xFA1C, (q15_t)0x7FDD, (q15_t)0xF9EA, (q15_t)0x7FDA,
+ (q15_t)0xF9B8, (q15_t)0x7FD8, (q15_t)0xF985, (q15_t)0x7FD6,
+ (q15_t)0xF953, (q15_t)0x7FD3, (q15_t)0xF921, (q15_t)0x7FD0,
+ (q15_t)0xF8EF, (q15_t)0x7FCE, (q15_t)0xF8BD, (q15_t)0x7FCB,
+ (q15_t)0xF88A, (q15_t)0x7FC8, (q15_t)0xF858, (q15_t)0x7FC5,
+ (q15_t)0xF826, (q15_t)0x7FC2, (q15_t)0xF7F4, (q15_t)0x7FBF,
+ (q15_t)0xF7C2, (q15_t)0x7FBC, (q15_t)0xF790, (q15_t)0x7FB8,
+ (q15_t)0xF75D, (q15_t)0x7FB5, (q15_t)0xF72B, (q15_t)0x7FB1,
+ (q15_t)0xF6F9, (q15_t)0x7FAE, (q15_t)0xF6C7, (q15_t)0x7FAA,
+ (q15_t)0xF695, (q15_t)0x7FA7, (q15_t)0xF663, (q15_t)0x7FA3,
+ (q15_t)0xF631, (q15_t)0x7F9F, (q15_t)0xF5FF, (q15_t)0x7F9B,
+ (q15_t)0xF5CC, (q15_t)0x7F97, (q15_t)0xF59A, (q15_t)0x7F93,
+ (q15_t)0xF568, (q15_t)0x7F8F, (q15_t)0xF536, (q15_t)0x7F8B,
+ (q15_t)0xF504, (q15_t)0x7F87, (q15_t)0xF4D2, (q15_t)0x7F82,
+ (q15_t)0xF4A0, (q15_t)0x7F7E, (q15_t)0xF46E, (q15_t)0x7F79,
+ (q15_t)0xF43C, (q15_t)0x7F75, (q15_t)0xF40A, (q15_t)0x7F70,
+ (q15_t)0xF3D8, (q15_t)0x7F6B, (q15_t)0xF3A6, (q15_t)0x7F67,
+ (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xF342, (q15_t)0x7F5D,
+ (q15_t)0xF310, (q15_t)0x7F58, (q15_t)0xF2DE, (q15_t)0x7F53,
+ (q15_t)0xF2AC, (q15_t)0x7F4D, (q15_t)0xF27A, (q15_t)0x7F48,
+ (q15_t)0xF248, (q15_t)0x7F43, (q15_t)0xF216, (q15_t)0x7F3D,
+ (q15_t)0xF1E4, (q15_t)0x7F38, (q15_t)0xF1B2, (q15_t)0x7F32,
+ (q15_t)0xF180, (q15_t)0x7F2D, (q15_t)0xF14E, (q15_t)0x7F27,
+ (q15_t)0xF11C, (q15_t)0x7F21, (q15_t)0xF0EA, (q15_t)0x7F1B,
+ (q15_t)0xF0B8, (q15_t)0x7F15, (q15_t)0xF086, (q15_t)0x7F0F,
+ (q15_t)0xF054, (q15_t)0x7F09, (q15_t)0xF022, (q15_t)0x7F03,
+ (q15_t)0xEFF1, (q15_t)0x7EFD, (q15_t)0xEFBF, (q15_t)0x7EF6,
+ (q15_t)0xEF8D, (q15_t)0x7EF0, (q15_t)0xEF5B, (q15_t)0x7EE9,
+ (q15_t)0xEF29, (q15_t)0x7EE3, (q15_t)0xEEF7, (q15_t)0x7EDC,
+ (q15_t)0xEEC6, (q15_t)0x7ED5, (q15_t)0xEE94, (q15_t)0x7ECF,
+ (q15_t)0xEE62, (q15_t)0x7EC8, (q15_t)0xEE30, (q15_t)0x7EC1,
+ (q15_t)0xEDFE, (q15_t)0x7EBA, (q15_t)0xEDCD, (q15_t)0x7EB3,
+ (q15_t)0xED9B, (q15_t)0x7EAB, (q15_t)0xED69, (q15_t)0x7EA4,
+ (q15_t)0xED37, (q15_t)0x7E9D, (q15_t)0xED06, (q15_t)0x7E95,
+ (q15_t)0xECD4, (q15_t)0x7E8E, (q15_t)0xECA2, (q15_t)0x7E86,
+ (q15_t)0xEC71, (q15_t)0x7E7F, (q15_t)0xEC3F, (q15_t)0x7E77,
+ (q15_t)0xEC0D, (q15_t)0x7E6F, (q15_t)0xEBDC, (q15_t)0x7E67,
+ (q15_t)0xEBAA, (q15_t)0x7E5F, (q15_t)0xEB78, (q15_t)0x7E57,
+ (q15_t)0xEB47, (q15_t)0x7E4F, (q15_t)0xEB15, (q15_t)0x7E47,
+ (q15_t)0xEAE4, (q15_t)0x7E3F, (q15_t)0xEAB2, (q15_t)0x7E37,
+ (q15_t)0xEA80, (q15_t)0x7E2E, (q15_t)0xEA4F, (q15_t)0x7E26,
+ (q15_t)0xEA1D, (q15_t)0x7E1D, (q15_t)0xE9EC, (q15_t)0x7E14,
+ (q15_t)0xE9BA, (q15_t)0x7E0C, (q15_t)0xE989, (q15_t)0x7E03,
+ (q15_t)0xE957, (q15_t)0x7DFA, (q15_t)0xE926, (q15_t)0x7DF1,
+ (q15_t)0xE8F5, (q15_t)0x7DE8, (q15_t)0xE8C3, (q15_t)0x7DDF,
+ (q15_t)0xE892, (q15_t)0x7DD6, (q15_t)0xE860, (q15_t)0x7DCD,
+ (q15_t)0xE82F, (q15_t)0x7DC3, (q15_t)0xE7FD, (q15_t)0x7DBA,
+ (q15_t)0xE7CC, (q15_t)0x7DB0, (q15_t)0xE79B, (q15_t)0x7DA7,
+ (q15_t)0xE769, (q15_t)0x7D9D, (q15_t)0xE738, (q15_t)0x7D94,
+ (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE6D5, (q15_t)0x7D80,
+ (q15_t)0xE6A4, (q15_t)0x7D76, (q15_t)0xE673, (q15_t)0x7D6C,
+ (q15_t)0xE642, (q15_t)0x7D62, (q15_t)0xE610, (q15_t)0x7D58,
+ (q15_t)0xE5DF, (q15_t)0x7D4E, (q15_t)0xE5AE, (q15_t)0x7D43,
+ (q15_t)0xE57D, (q15_t)0x7D39, (q15_t)0xE54C, (q15_t)0x7D2F,
+ (q15_t)0xE51B, (q15_t)0x7D24, (q15_t)0xE4E9, (q15_t)0x7D19,
+ (q15_t)0xE4B8, (q15_t)0x7D0F, (q15_t)0xE487, (q15_t)0x7D04,
+ (q15_t)0xE456, (q15_t)0x7CF9, (q15_t)0xE425, (q15_t)0x7CEE,
+ (q15_t)0xE3F4, (q15_t)0x7CE3, (q15_t)0xE3C3, (q15_t)0x7CD8,
+ (q15_t)0xE392, (q15_t)0x7CCD, (q15_t)0xE361, (q15_t)0x7CC2,
+ (q15_t)0xE330, (q15_t)0x7CB7, (q15_t)0xE2FF, (q15_t)0x7CAB,
+ (q15_t)0xE2CE, (q15_t)0x7CA0, (q15_t)0xE29D, (q15_t)0x7C94,
+ (q15_t)0xE26C, (q15_t)0x7C89, (q15_t)0xE23B, (q15_t)0x7C7D,
+ (q15_t)0xE20A, (q15_t)0x7C71, (q15_t)0xE1DA, (q15_t)0x7C66,
+ (q15_t)0xE1A9, (q15_t)0x7C5A, (q15_t)0xE178, (q15_t)0x7C4E,
+ (q15_t)0xE147, (q15_t)0x7C42, (q15_t)0xE116, (q15_t)0x7C36,
+ (q15_t)0xE0E6, (q15_t)0x7C29, (q15_t)0xE0B5, (q15_t)0x7C1D,
+ (q15_t)0xE084, (q15_t)0x7C11, (q15_t)0xE053, (q15_t)0x7C05,
+ (q15_t)0xE023, (q15_t)0x7BF8, (q15_t)0xDFF2, (q15_t)0x7BEB,
+ (q15_t)0xDFC1, (q15_t)0x7BDF, (q15_t)0xDF91, (q15_t)0x7BD2,
+ (q15_t)0xDF60, (q15_t)0x7BC5, (q15_t)0xDF2F, (q15_t)0x7BB9,
+ (q15_t)0xDEFF, (q15_t)0x7BAC, (q15_t)0xDECE, (q15_t)0x7B9F,
+ (q15_t)0xDE9E, (q15_t)0x7B92, (q15_t)0xDE6D, (q15_t)0x7B84,
+ (q15_t)0xDE3D, (q15_t)0x7B77, (q15_t)0xDE0C, (q15_t)0x7B6A,
+ (q15_t)0xDDDC, (q15_t)0x7B5D, (q15_t)0xDDAB, (q15_t)0x7B4F,
+ (q15_t)0xDD7B, (q15_t)0x7B42, (q15_t)0xDD4B, (q15_t)0x7B34,
+ (q15_t)0xDD1A, (q15_t)0x7B26, (q15_t)0xDCEA, (q15_t)0x7B19,
+ (q15_t)0xDCBA, (q15_t)0x7B0B, (q15_t)0xDC89, (q15_t)0x7AFD,
+ (q15_t)0xDC59, (q15_t)0x7AEF, (q15_t)0xDC29, (q15_t)0x7AE1,
+ (q15_t)0xDBF8, (q15_t)0x7AD3, (q15_t)0xDBC8, (q15_t)0x7AC5,
+ (q15_t)0xDB98, (q15_t)0x7AB6, (q15_t)0xDB68, (q15_t)0x7AA8,
+ (q15_t)0xDB38, (q15_t)0x7A9A, (q15_t)0xDB08, (q15_t)0x7A8B,
+ (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xDAA7, (q15_t)0x7A6E,
+ (q15_t)0xDA77, (q15_t)0x7A5F, (q15_t)0xDA47, (q15_t)0x7A50,
+ (q15_t)0xDA17, (q15_t)0x7A42, (q15_t)0xD9E7, (q15_t)0x7A33,
+ (q15_t)0xD9B7, (q15_t)0x7A24, (q15_t)0xD987, (q15_t)0x7A15,
+ (q15_t)0xD957, (q15_t)0x7A05, (q15_t)0xD927, (q15_t)0x79F6,
+ (q15_t)0xD8F8, (q15_t)0x79E7, (q15_t)0xD8C8, (q15_t)0x79D8,
+ (q15_t)0xD898, (q15_t)0x79C8, (q15_t)0xD868, (q15_t)0x79B9,
+ (q15_t)0xD838, (q15_t)0x79A9, (q15_t)0xD809, (q15_t)0x7999,
+ (q15_t)0xD7D9, (q15_t)0x798A, (q15_t)0xD7A9, (q15_t)0x797A,
+ (q15_t)0xD779, (q15_t)0x796A, (q15_t)0xD74A, (q15_t)0x795A,
+ (q15_t)0xD71A, (q15_t)0x794A, (q15_t)0xD6EA, (q15_t)0x793A,
+ (q15_t)0xD6BB, (q15_t)0x792A, (q15_t)0xD68B, (q15_t)0x7919,
+ (q15_t)0xD65C, (q15_t)0x7909, (q15_t)0xD62C, (q15_t)0x78F9,
+ (q15_t)0xD5FD, (q15_t)0x78E8, (q15_t)0xD5CD, (q15_t)0x78D8,
+ (q15_t)0xD59E, (q15_t)0x78C7, (q15_t)0xD56E, (q15_t)0x78B6,
+ (q15_t)0xD53F, (q15_t)0x78A6, (q15_t)0xD510, (q15_t)0x7895,
+ (q15_t)0xD4E0, (q15_t)0x7884, (q15_t)0xD4B1, (q15_t)0x7873,
+ (q15_t)0xD482, (q15_t)0x7862, (q15_t)0xD452, (q15_t)0x7851,
+ (q15_t)0xD423, (q15_t)0x7840, (q15_t)0xD3F4, (q15_t)0x782E,
+ (q15_t)0xD3C5, (q15_t)0x781D, (q15_t)0xD396, (q15_t)0x780C,
+ (q15_t)0xD367, (q15_t)0x77FA, (q15_t)0xD337, (q15_t)0x77E9,
+ (q15_t)0xD308, (q15_t)0x77D7, (q15_t)0xD2D9, (q15_t)0x77C5,
+ (q15_t)0xD2AA, (q15_t)0x77B4, (q15_t)0xD27B, (q15_t)0x77A2,
+ (q15_t)0xD24C, (q15_t)0x7790, (q15_t)0xD21D, (q15_t)0x777E,
+ (q15_t)0xD1EE, (q15_t)0x776C, (q15_t)0xD1C0, (q15_t)0x775A,
+ (q15_t)0xD191, (q15_t)0x7747, (q15_t)0xD162, (q15_t)0x7735,
+ (q15_t)0xD133, (q15_t)0x7723, (q15_t)0xD104, (q15_t)0x7710,
+ (q15_t)0xD0D6, (q15_t)0x76FE, (q15_t)0xD0A7, (q15_t)0x76EB,
+ (q15_t)0xD078, (q15_t)0x76D9, (q15_t)0xD04A, (q15_t)0x76C6,
+ (q15_t)0xD01B, (q15_t)0x76B3, (q15_t)0xCFEC, (q15_t)0x76A0,
+ (q15_t)0xCFBE, (q15_t)0x768E, (q15_t)0xCF8F, (q15_t)0x767B,
+ (q15_t)0xCF61, (q15_t)0x7668, (q15_t)0xCF32, (q15_t)0x7654,
+ (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xCED5, (q15_t)0x762E,
+ (q15_t)0xCEA7, (q15_t)0x761B, (q15_t)0xCE79, (q15_t)0x7607,
+ (q15_t)0xCE4A, (q15_t)0x75F4, (q15_t)0xCE1C, (q15_t)0x75E0,
+ (q15_t)0xCDEE, (q15_t)0x75CC, (q15_t)0xCDBF, (q15_t)0x75B9,
+ (q15_t)0xCD91, (q15_t)0x75A5, (q15_t)0xCD63, (q15_t)0x7591,
+ (q15_t)0xCD35, (q15_t)0x757D, (q15_t)0xCD07, (q15_t)0x7569,
+ (q15_t)0xCCD9, (q15_t)0x7555, (q15_t)0xCCAB, (q15_t)0x7541,
+ (q15_t)0xCC7D, (q15_t)0x752D, (q15_t)0xCC4F, (q15_t)0x7519,
+ (q15_t)0xCC21, (q15_t)0x7504, (q15_t)0xCBF3, (q15_t)0x74F0,
+ (q15_t)0xCBC5, (q15_t)0x74DB, (q15_t)0xCB97, (q15_t)0x74C7,
+ (q15_t)0xCB69, (q15_t)0x74B2, (q15_t)0xCB3B, (q15_t)0x749E,
+ (q15_t)0xCB0D, (q15_t)0x7489, (q15_t)0xCAE0, (q15_t)0x7474,
+ (q15_t)0xCAB2, (q15_t)0x745F, (q15_t)0xCA84, (q15_t)0x744A,
+ (q15_t)0xCA57, (q15_t)0x7435, (q15_t)0xCA29, (q15_t)0x7420,
+ (q15_t)0xC9FB, (q15_t)0x740B, (q15_t)0xC9CE, (q15_t)0x73F6,
+ (q15_t)0xC9A0, (q15_t)0x73E0, (q15_t)0xC973, (q15_t)0x73CB,
+ (q15_t)0xC945, (q15_t)0x73B5, (q15_t)0xC918, (q15_t)0x73A0,
+ (q15_t)0xC8EB, (q15_t)0x738A, (q15_t)0xC8BD, (q15_t)0x7375,
+ (q15_t)0xC890, (q15_t)0x735F, (q15_t)0xC863, (q15_t)0x7349,
+ (q15_t)0xC835, (q15_t)0x7333, (q15_t)0xC808, (q15_t)0x731D,
+ (q15_t)0xC7DB, (q15_t)0x7307, (q15_t)0xC7AE, (q15_t)0x72F1,
+ (q15_t)0xC781, (q15_t)0x72DB, (q15_t)0xC754, (q15_t)0x72C5,
+ (q15_t)0xC727, (q15_t)0x72AF, (q15_t)0xC6F9, (q15_t)0x7298,
+ (q15_t)0xC6CD, (q15_t)0x7282, (q15_t)0xC6A0, (q15_t)0x726B,
+ (q15_t)0xC673, (q15_t)0x7255, (q15_t)0xC646, (q15_t)0x723E,
+ (q15_t)0xC619, (q15_t)0x7227, (q15_t)0xC5EC, (q15_t)0x7211,
+ (q15_t)0xC5BF, (q15_t)0x71FA, (q15_t)0xC593, (q15_t)0x71E3,
+ (q15_t)0xC566, (q15_t)0x71CC, (q15_t)0xC539, (q15_t)0x71B5,
+ (q15_t)0xC50D, (q15_t)0x719E, (q15_t)0xC4E0, (q15_t)0x7186,
+ (q15_t)0xC4B3, (q15_t)0x716F, (q15_t)0xC487, (q15_t)0x7158,
+ (q15_t)0xC45A, (q15_t)0x7141, (q15_t)0xC42E, (q15_t)0x7129,
+ (q15_t)0xC402, (q15_t)0x7112, (q15_t)0xC3D5, (q15_t)0x70FA,
+ (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xC37C, (q15_t)0x70CB,
+ (q15_t)0xC350, (q15_t)0x70B3, (q15_t)0xC324, (q15_t)0x709B,
+ (q15_t)0xC2F8, (q15_t)0x7083, (q15_t)0xC2CC, (q15_t)0x706B,
+ (q15_t)0xC29F, (q15_t)0x7053, (q15_t)0xC273, (q15_t)0x703B,
+ (q15_t)0xC247, (q15_t)0x7023, (q15_t)0xC21B, (q15_t)0x700A,
+ (q15_t)0xC1EF, (q15_t)0x6FF2, (q15_t)0xC1C3, (q15_t)0x6FDA,
+ (q15_t)0xC197, (q15_t)0x6FC1, (q15_t)0xC16C, (q15_t)0x6FA9,
+ (q15_t)0xC140, (q15_t)0x6F90, (q15_t)0xC114, (q15_t)0x6F77,
+ (q15_t)0xC0E8, (q15_t)0x6F5F, (q15_t)0xC0BC, (q15_t)0x6F46,
+ (q15_t)0xC091, (q15_t)0x6F2D, (q15_t)0xC065, (q15_t)0x6F14,
+ (q15_t)0xC03A, (q15_t)0x6EFB, (q15_t)0xC00E, (q15_t)0x6EE2,
+ (q15_t)0xBFE2, (q15_t)0x6EC9, (q15_t)0xBFB7, (q15_t)0x6EAF,
+ (q15_t)0xBF8C, (q15_t)0x6E96, (q15_t)0xBF60, (q15_t)0x6E7D,
+ (q15_t)0xBF35, (q15_t)0x6E63, (q15_t)0xBF09, (q15_t)0x6E4A,
+ (q15_t)0xBEDE, (q15_t)0x6E30, (q15_t)0xBEB3, (q15_t)0x6E17,
+ (q15_t)0xBE88, (q15_t)0x6DFD, (q15_t)0xBE5D, (q15_t)0x6DE3,
+ (q15_t)0xBE31, (q15_t)0x6DCA, (q15_t)0xBE06, (q15_t)0x6DB0,
+ (q15_t)0xBDDB, (q15_t)0x6D96, (q15_t)0xBDB0, (q15_t)0x6D7C,
+ (q15_t)0xBD85, (q15_t)0x6D62, (q15_t)0xBD5A, (q15_t)0x6D48,
+ (q15_t)0xBD2F, (q15_t)0x6D2D, (q15_t)0xBD05, (q15_t)0x6D13,
+ (q15_t)0xBCDA, (q15_t)0x6CF9, (q15_t)0xBCAF, (q15_t)0x6CDE,
+ (q15_t)0xBC84, (q15_t)0x6CC4, (q15_t)0xBC5A, (q15_t)0x6CA9,
+ (q15_t)0xBC2F, (q15_t)0x6C8F, (q15_t)0xBC04, (q15_t)0x6C74,
+ (q15_t)0xBBDA, (q15_t)0x6C59, (q15_t)0xBBAF, (q15_t)0x6C3F,
+ (q15_t)0xBB85, (q15_t)0x6C24, (q15_t)0xBB5A, (q15_t)0x6C09,
+ (q15_t)0xBB30, (q15_t)0x6BEE, (q15_t)0xBB05, (q15_t)0x6BD3,
+ (q15_t)0xBADB, (q15_t)0x6BB8, (q15_t)0xBAB1, (q15_t)0x6B9C,
+ (q15_t)0xBA87, (q15_t)0x6B81, (q15_t)0xBA5C, (q15_t)0x6B66,
+ (q15_t)0xBA32, (q15_t)0x6B4A, (q15_t)0xBA08, (q15_t)0x6B2F,
+ (q15_t)0xB9DE, (q15_t)0x6B13, (q15_t)0xB9B4, (q15_t)0x6AF8,
+ (q15_t)0xB98A, (q15_t)0x6ADC, (q15_t)0xB960, (q15_t)0x6AC1,
+ (q15_t)0xB936, (q15_t)0x6AA5, (q15_t)0xB90C, (q15_t)0x6A89,
+ (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB8B9, (q15_t)0x6A51,
+ (q15_t)0xB88F, (q15_t)0x6A35, (q15_t)0xB865, (q15_t)0x6A19,
+ (q15_t)0xB83C, (q15_t)0x69FD, (q15_t)0xB812, (q15_t)0x69E1,
+ (q15_t)0xB7E9, (q15_t)0x69C4, (q15_t)0xB7BF, (q15_t)0x69A8,
+ (q15_t)0xB796, (q15_t)0x698C, (q15_t)0xB76C, (q15_t)0x696F,
+ (q15_t)0xB743, (q15_t)0x6953, (q15_t)0xB719, (q15_t)0x6936,
+ (q15_t)0xB6F0, (q15_t)0x6919, (q15_t)0xB6C7, (q15_t)0x68FD,
+ (q15_t)0xB69E, (q15_t)0x68E0, (q15_t)0xB675, (q15_t)0x68C3,
+ (q15_t)0xB64B, (q15_t)0x68A6, (q15_t)0xB622, (q15_t)0x6889,
+ (q15_t)0xB5F9, (q15_t)0x686C, (q15_t)0xB5D0, (q15_t)0x684F,
+ (q15_t)0xB5A7, (q15_t)0x6832, (q15_t)0xB57E, (q15_t)0x6815,
+ (q15_t)0xB556, (q15_t)0x67F7, (q15_t)0xB52D, (q15_t)0x67DA,
+ (q15_t)0xB504, (q15_t)0x67BD, (q15_t)0xB4DB, (q15_t)0x679F,
+ (q15_t)0xB4B3, (q15_t)0x6782, (q15_t)0xB48A, (q15_t)0x6764,
+ (q15_t)0xB461, (q15_t)0x6746, (q15_t)0xB439, (q15_t)0x6729,
+ (q15_t)0xB410, (q15_t)0x670B, (q15_t)0xB3E8, (q15_t)0x66ED,
+ (q15_t)0xB3C0, (q15_t)0x66CF, (q15_t)0xB397, (q15_t)0x66B1,
+ (q15_t)0xB36F, (q15_t)0x6693, (q15_t)0xB347, (q15_t)0x6675,
+ (q15_t)0xB31E, (q15_t)0x6657, (q15_t)0xB2F6, (q15_t)0x6639,
+ (q15_t)0xB2CE, (q15_t)0x661A, (q15_t)0xB2A6, (q15_t)0x65FC,
+ (q15_t)0xB27E, (q15_t)0x65DD, (q15_t)0xB256, (q15_t)0x65BF,
+ (q15_t)0xB22E, (q15_t)0x65A0, (q15_t)0xB206, (q15_t)0x6582,
+ (q15_t)0xB1DE, (q15_t)0x6563, (q15_t)0xB1B7, (q15_t)0x6545,
+ (q15_t)0xB18F, (q15_t)0x6526, (q15_t)0xB167, (q15_t)0x6507,
+ (q15_t)0xB140, (q15_t)0x64E8, (q15_t)0xB118, (q15_t)0x64C9,
+ (q15_t)0xB0F0, (q15_t)0x64AA, (q15_t)0xB0C9, (q15_t)0x648B,
+ (q15_t)0xB0A1, (q15_t)0x646C, (q15_t)0xB07A, (q15_t)0x644D,
+ (q15_t)0xB053, (q15_t)0x642D, (q15_t)0xB02B, (q15_t)0x640E,
+ (q15_t)0xB004, (q15_t)0x63EF, (q15_t)0xAFDD, (q15_t)0x63CF,
+ (q15_t)0xAFB6, (q15_t)0x63B0, (q15_t)0xAF8F, (q15_t)0x6390,
+ (q15_t)0xAF68, (q15_t)0x6371, (q15_t)0xAF40, (q15_t)0x6351,
+ (q15_t)0xAF1A, (q15_t)0x6331, (q15_t)0xAEF3, (q15_t)0x6311,
+ (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAEA5, (q15_t)0x62D2,
+ (q15_t)0xAE7E, (q15_t)0x62B2, (q15_t)0xAE57, (q15_t)0x6292,
+ (q15_t)0xAE31, (q15_t)0x6271, (q15_t)0xAE0A, (q15_t)0x6251,
+ (q15_t)0xADE3, (q15_t)0x6231, (q15_t)0xADBD, (q15_t)0x6211,
+ (q15_t)0xAD96, (q15_t)0x61F1, (q15_t)0xAD70, (q15_t)0x61D0,
+ (q15_t)0xAD4A, (q15_t)0x61B0, (q15_t)0xAD23, (q15_t)0x618F,
+ (q15_t)0xACFD, (q15_t)0x616F, (q15_t)0xACD7, (q15_t)0x614E,
+ (q15_t)0xACB1, (q15_t)0x612D, (q15_t)0xAC8A, (q15_t)0x610D,
+ (q15_t)0xAC64, (q15_t)0x60EC, (q15_t)0xAC3E, (q15_t)0x60CB,
+ (q15_t)0xAC18, (q15_t)0x60AA, (q15_t)0xABF2, (q15_t)0x6089,
+ (q15_t)0xABCC, (q15_t)0x6068, (q15_t)0xABA7, (q15_t)0x6047,
+ (q15_t)0xAB81, (q15_t)0x6026, (q15_t)0xAB5B, (q15_t)0x6004,
+ (q15_t)0xAB35, (q15_t)0x5FE3, (q15_t)0xAB10, (q15_t)0x5FC2,
+ (q15_t)0xAAEA, (q15_t)0x5FA0, (q15_t)0xAAC5, (q15_t)0x5F7F,
+ (q15_t)0xAA9F, (q15_t)0x5F5E, (q15_t)0xAA7A, (q15_t)0x5F3C,
+ (q15_t)0xAA54, (q15_t)0x5F1A, (q15_t)0xAA2F, (q15_t)0x5EF9,
+ (q15_t)0xAA0A, (q15_t)0x5ED7, (q15_t)0xA9E5, (q15_t)0x5EB5,
+ (q15_t)0xA9BF, (q15_t)0x5E93, (q15_t)0xA99A, (q15_t)0x5E71,
+ (q15_t)0xA975, (q15_t)0x5E50, (q15_t)0xA950, (q15_t)0x5E2D,
+ (q15_t)0xA92B, (q15_t)0x5E0B, (q15_t)0xA906, (q15_t)0x5DE9,
+ (q15_t)0xA8E2, (q15_t)0x5DC7, (q15_t)0xA8BD, (q15_t)0x5DA5,
+ (q15_t)0xA898, (q15_t)0x5D83, (q15_t)0xA873, (q15_t)0x5D60,
+ (q15_t)0xA84F, (q15_t)0x5D3E, (q15_t)0xA82A, (q15_t)0x5D1B,
+ (q15_t)0xA806, (q15_t)0x5CF9, (q15_t)0xA7E1, (q15_t)0x5CD6,
+ (q15_t)0xA7BD, (q15_t)0x5CB4, (q15_t)0xA798, (q15_t)0x5C91,
+ (q15_t)0xA774, (q15_t)0x5C6E, (q15_t)0xA750, (q15_t)0x5C4B,
+ (q15_t)0xA72B, (q15_t)0x5C29, (q15_t)0xA707, (q15_t)0x5C06,
+ (q15_t)0xA6E3, (q15_t)0x5BE3, (q15_t)0xA6BF, (q15_t)0x5BC0,
+ (q15_t)0xA69B, (q15_t)0x5B9D, (q15_t)0xA677, (q15_t)0x5B79,
+ (q15_t)0xA653, (q15_t)0x5B56, (q15_t)0xA62F, (q15_t)0x5B33,
+ (q15_t)0xA60C, (q15_t)0x5B10, (q15_t)0xA5E8, (q15_t)0x5AEC,
+ (q15_t)0xA5C4, (q15_t)0x5AC9, (q15_t)0xA5A1, (q15_t)0x5AA5,
+ (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA55A, (q15_t)0x5A5E,
+ (q15_t)0xA536, (q15_t)0x5A3B, (q15_t)0xA513, (q15_t)0x5A17,
+ (q15_t)0xA4EF, (q15_t)0x59F3, (q15_t)0xA4CC, (q15_t)0x59D0,
+ (q15_t)0xA4A9, (q15_t)0x59AC, (q15_t)0xA486, (q15_t)0x5988,
+ (q15_t)0xA462, (q15_t)0x5964, (q15_t)0xA43F, (q15_t)0x5940,
+ (q15_t)0xA41C, (q15_t)0x591C, (q15_t)0xA3F9, (q15_t)0x58F8,
+ (q15_t)0xA3D6, (q15_t)0x58D4, (q15_t)0xA3B4, (q15_t)0x58AF,
+ (q15_t)0xA391, (q15_t)0x588B, (q15_t)0xA36E, (q15_t)0x5867,
+ (q15_t)0xA34B, (q15_t)0x5842, (q15_t)0xA329, (q15_t)0x581E,
+ (q15_t)0xA306, (q15_t)0x57F9, (q15_t)0xA2E4, (q15_t)0x57D5,
+ (q15_t)0xA2C1, (q15_t)0x57B0, (q15_t)0xA29F, (q15_t)0x578C,
+ (q15_t)0xA27C, (q15_t)0x5767, (q15_t)0xA25A, (q15_t)0x5742,
+ (q15_t)0xA238, (q15_t)0x571D, (q15_t)0xA216, (q15_t)0x56F9,
+ (q15_t)0xA1F4, (q15_t)0x56D4, (q15_t)0xA1D2, (q15_t)0x56AF,
+ (q15_t)0xA1AF, (q15_t)0x568A, (q15_t)0xA18E, (q15_t)0x5665,
+ (q15_t)0xA16C, (q15_t)0x5640, (q15_t)0xA14A, (q15_t)0x561A,
+ (q15_t)0xA128, (q15_t)0x55F5, (q15_t)0xA106, (q15_t)0x55D0,
+ (q15_t)0xA0E5, (q15_t)0x55AB, (q15_t)0xA0C3, (q15_t)0x5585,
+ (q15_t)0xA0A1, (q15_t)0x5560, (q15_t)0xA080, (q15_t)0x553A,
+ (q15_t)0xA05F, (q15_t)0x5515, (q15_t)0xA03D, (q15_t)0x54EF,
+ (q15_t)0xA01C, (q15_t)0x54CA, (q15_t)0x9FFB, (q15_t)0x54A4,
+ (q15_t)0x9FD9, (q15_t)0x547E, (q15_t)0x9FB8, (q15_t)0x5458,
+ (q15_t)0x9F97, (q15_t)0x5433, (q15_t)0x9F76, (q15_t)0x540D,
+ (q15_t)0x9F55, (q15_t)0x53E7, (q15_t)0x9F34, (q15_t)0x53C1,
+ (q15_t)0x9F13, (q15_t)0x539B, (q15_t)0x9EF2, (q15_t)0x5375,
+ (q15_t)0x9ED2, (q15_t)0x534E, (q15_t)0x9EB1, (q15_t)0x5328,
+ (q15_t)0x9E90, (q15_t)0x5302, (q15_t)0x9E70, (q15_t)0x52DC,
+ (q15_t)0x9E4F, (q15_t)0x52B5, (q15_t)0x9E2F, (q15_t)0x528F,
+ (q15_t)0x9E0E, (q15_t)0x5269, (q15_t)0x9DEE, (q15_t)0x5242,
+ (q15_t)0x9DCE, (q15_t)0x521C, (q15_t)0x9DAE, (q15_t)0x51F5,
+ (q15_t)0x9D8E, (q15_t)0x51CE, (q15_t)0x9D6D, (q15_t)0x51A8,
+ (q15_t)0x9D4D, (q15_t)0x5181, (q15_t)0x9D2D, (q15_t)0x515A,
+ (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9CEE, (q15_t)0x510C,
+ (q15_t)0x9CCE, (q15_t)0x50E5, (q15_t)0x9CAE, (q15_t)0x50BF,
+ (q15_t)0x9C8E, (q15_t)0x5097, (q15_t)0x9C6F, (q15_t)0x5070,
+ (q15_t)0x9C4F, (q15_t)0x5049, (q15_t)0x9C30, (q15_t)0x5022,
+ (q15_t)0x9C10, (q15_t)0x4FFB, (q15_t)0x9BF1, (q15_t)0x4FD4,
+ (q15_t)0x9BD2, (q15_t)0x4FAC, (q15_t)0x9BB2, (q15_t)0x4F85,
+ (q15_t)0x9B93, (q15_t)0x4F5E, (q15_t)0x9B74, (q15_t)0x4F36,
+ (q15_t)0x9B55, (q15_t)0x4F0F, (q15_t)0x9B36, (q15_t)0x4EE7,
+ (q15_t)0x9B17, (q15_t)0x4EBF, (q15_t)0x9AF8, (q15_t)0x4E98,
+ (q15_t)0x9AD9, (q15_t)0x4E70, (q15_t)0x9ABA, (q15_t)0x4E48,
+ (q15_t)0x9A9C, (q15_t)0x4E21, (q15_t)0x9A7D, (q15_t)0x4DF9,
+ (q15_t)0x9A5F, (q15_t)0x4DD1, (q15_t)0x9A40, (q15_t)0x4DA9,
+ (q15_t)0x9A22, (q15_t)0x4D81, (q15_t)0x9A03, (q15_t)0x4D59,
+ (q15_t)0x99E5, (q15_t)0x4D31, (q15_t)0x99C6, (q15_t)0x4D09,
+ (q15_t)0x99A8, (q15_t)0x4CE1, (q15_t)0x998A, (q15_t)0x4CB8,
+ (q15_t)0x996C, (q15_t)0x4C90, (q15_t)0x994E, (q15_t)0x4C68,
+ (q15_t)0x9930, (q15_t)0x4C3F, (q15_t)0x9912, (q15_t)0x4C17,
+ (q15_t)0x98F4, (q15_t)0x4BEF, (q15_t)0x98D6, (q15_t)0x4BC6,
+ (q15_t)0x98B9, (q15_t)0x4B9E, (q15_t)0x989B, (q15_t)0x4B75,
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+ (q15_t)0x811C, (q15_t)0x10D6, (q15_t)0x8116, (q15_t)0x10A4,
+ (q15_t)0x810F, (q15_t)0x1072, (q15_t)0x8109, (q15_t)0x1040,
+ (q15_t)0x8102, (q15_t)0x100E, (q15_t)0x80FC, (q15_t)0x0FDD,
+ (q15_t)0x80F6, (q15_t)0x0FAB, (q15_t)0x80F0, (q15_t)0x0F79,
+ (q15_t)0x80EA, (q15_t)0x0F47, (q15_t)0x80E4, (q15_t)0x0F15,
+ (q15_t)0x80DE, (q15_t)0x0EE3, (q15_t)0x80D8, (q15_t)0x0EB1,
+ (q15_t)0x80D2, (q15_t)0x0E7F, (q15_t)0x80CD, (q15_t)0x0E4D,
+ (q15_t)0x80C7, (q15_t)0x0E1B, (q15_t)0x80C2, (q15_t)0x0DE9,
+ (q15_t)0x80BC, (q15_t)0x0DB7, (q15_t)0x80B7, (q15_t)0x0D85,
+ (q15_t)0x80B2, (q15_t)0x0D53, (q15_t)0x80AC, (q15_t)0x0D21,
+ (q15_t)0x80A7, (q15_t)0x0CEF, (q15_t)0x80A2, (q15_t)0x0CBD,
+ (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x8098, (q15_t)0x0C59,
+ (q15_t)0x8094, (q15_t)0x0C27, (q15_t)0x808F, (q15_t)0x0BF5,
+ (q15_t)0x808A, (q15_t)0x0BC3, (q15_t)0x8086, (q15_t)0x0B91,
+ (q15_t)0x8081, (q15_t)0x0B5F, (q15_t)0x807D, (q15_t)0x0B2D,
+ (q15_t)0x8078, (q15_t)0x0AFB, (q15_t)0x8074, (q15_t)0x0AC9,
+ (q15_t)0x8070, (q15_t)0x0A97, (q15_t)0x806C, (q15_t)0x0A65,
+ (q15_t)0x8068, (q15_t)0x0A33, (q15_t)0x8064, (q15_t)0x0A00,
+ (q15_t)0x8060, (q15_t)0x09CE, (q15_t)0x805C, (q15_t)0x099C,
+ (q15_t)0x8058, (q15_t)0x096A, (q15_t)0x8055, (q15_t)0x0938,
+ (q15_t)0x8051, (q15_t)0x0906, (q15_t)0x804E, (q15_t)0x08D4,
+ (q15_t)0x804A, (q15_t)0x08A2, (q15_t)0x8047, (q15_t)0x086F,
+ (q15_t)0x8043, (q15_t)0x083D, (q15_t)0x8040, (q15_t)0x080B,
+ (q15_t)0x803D, (q15_t)0x07D9, (q15_t)0x803A, (q15_t)0x07A7,
+ (q15_t)0x8037, (q15_t)0x0775, (q15_t)0x8034, (q15_t)0x0742,
+ (q15_t)0x8031, (q15_t)0x0710, (q15_t)0x802F, (q15_t)0x06DE,
+ (q15_t)0x802C, (q15_t)0x06AC, (q15_t)0x8029, (q15_t)0x067A,
+ (q15_t)0x8027, (q15_t)0x0647, (q15_t)0x8025, (q15_t)0x0615,
+ (q15_t)0x8022, (q15_t)0x05E3, (q15_t)0x8020, (q15_t)0x05B1,
+ (q15_t)0x801E, (q15_t)0x057F, (q15_t)0x801C, (q15_t)0x054C,
+ (q15_t)0x801A, (q15_t)0x051A, (q15_t)0x8018, (q15_t)0x04E8,
+ (q15_t)0x8016, (q15_t)0x04B6, (q15_t)0x8014, (q15_t)0x0483,
+ (q15_t)0x8012, (q15_t)0x0451, (q15_t)0x8011, (q15_t)0x041F,
+ (q15_t)0x800F, (q15_t)0x03ED, (q15_t)0x800D, (q15_t)0x03BA,
+ (q15_t)0x800C, (q15_t)0x0388, (q15_t)0x800B, (q15_t)0x0356,
+ (q15_t)0x8009, (q15_t)0x0324, (q15_t)0x8008, (q15_t)0x02F1,
+ (q15_t)0x8007, (q15_t)0x02BF, (q15_t)0x8006, (q15_t)0x028D,
+ (q15_t)0x8005, (q15_t)0x025B, (q15_t)0x8004, (q15_t)0x0228,
+ (q15_t)0x8003, (q15_t)0x01F6, (q15_t)0x8003, (q15_t)0x01C4,
+ (q15_t)0x8002, (q15_t)0x0192, (q15_t)0x8001, (q15_t)0x015F,
+ (q15_t)0x8001, (q15_t)0x012D, (q15_t)0x8000, (q15_t)0x00FB,
+ (q15_t)0x8000, (q15_t)0x00C9, (q15_t)0x8000, (q15_t)0x0096,
+ (q15_t)0x8000, (q15_t)0x0064, (q15_t)0x8000, (q15_t)0x0032,
+ (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8000, (q15_t)0xFFCD,
+ (q15_t)0x8000, (q15_t)0xFF9B, (q15_t)0x8000, (q15_t)0xFF69,
+ (q15_t)0x8000, (q15_t)0xFF36, (q15_t)0x8000, (q15_t)0xFF04,
+ (q15_t)0x8001, (q15_t)0xFED2, (q15_t)0x8001, (q15_t)0xFEA0,
+ (q15_t)0x8002, (q15_t)0xFE6D, (q15_t)0x8003, (q15_t)0xFE3B,
+ (q15_t)0x8003, (q15_t)0xFE09, (q15_t)0x8004, (q15_t)0xFDD7,
+ (q15_t)0x8005, (q15_t)0xFDA4, (q15_t)0x8006, (q15_t)0xFD72,
+ (q15_t)0x8007, (q15_t)0xFD40, (q15_t)0x8008, (q15_t)0xFD0E,
+ (q15_t)0x8009, (q15_t)0xFCDB, (q15_t)0x800B, (q15_t)0xFCA9,
+ (q15_t)0x800C, (q15_t)0xFC77, (q15_t)0x800D, (q15_t)0xFC45,
+ (q15_t)0x800F, (q15_t)0xFC12, (q15_t)0x8011, (q15_t)0xFBE0,
+ (q15_t)0x8012, (q15_t)0xFBAE, (q15_t)0x8014, (q15_t)0xFB7C,
+ (q15_t)0x8016, (q15_t)0xFB49, (q15_t)0x8018, (q15_t)0xFB17,
+ (q15_t)0x801A, (q15_t)0xFAE5, (q15_t)0x801C, (q15_t)0xFAB3,
+ (q15_t)0x801E, (q15_t)0xFA80, (q15_t)0x8020, (q15_t)0xFA4E,
+ (q15_t)0x8022, (q15_t)0xFA1C, (q15_t)0x8025, (q15_t)0xF9EA,
+ (q15_t)0x8027, (q15_t)0xF9B8, (q15_t)0x8029, (q15_t)0xF985,
+ (q15_t)0x802C, (q15_t)0xF953, (q15_t)0x802F, (q15_t)0xF921,
+ (q15_t)0x8031, (q15_t)0xF8EF, (q15_t)0x8034, (q15_t)0xF8BD,
+ (q15_t)0x8037, (q15_t)0xF88A, (q15_t)0x803A, (q15_t)0xF858,
+ (q15_t)0x803D, (q15_t)0xF826, (q15_t)0x8040, (q15_t)0xF7F4,
+ (q15_t)0x8043, (q15_t)0xF7C2, (q15_t)0x8047, (q15_t)0xF790,
+ (q15_t)0x804A, (q15_t)0xF75D, (q15_t)0x804E, (q15_t)0xF72B,
+ (q15_t)0x8051, (q15_t)0xF6F9, (q15_t)0x8055, (q15_t)0xF6C7,
+ (q15_t)0x8058, (q15_t)0xF695, (q15_t)0x805C, (q15_t)0xF663,
+ (q15_t)0x8060, (q15_t)0xF631, (q15_t)0x8064, (q15_t)0xF5FF,
+ (q15_t)0x8068, (q15_t)0xF5CC, (q15_t)0x806C, (q15_t)0xF59A,
+ (q15_t)0x8070, (q15_t)0xF568, (q15_t)0x8074, (q15_t)0xF536,
+ (q15_t)0x8078, (q15_t)0xF504, (q15_t)0x807D, (q15_t)0xF4D2,
+ (q15_t)0x8081, (q15_t)0xF4A0, (q15_t)0x8086, (q15_t)0xF46E,
+ (q15_t)0x808A, (q15_t)0xF43C, (q15_t)0x808F, (q15_t)0xF40A,
+ (q15_t)0x8094, (q15_t)0xF3D8, (q15_t)0x8098, (q15_t)0xF3A6,
+ (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x80A2, (q15_t)0xF342,
+ (q15_t)0x80A7, (q15_t)0xF310, (q15_t)0x80AC, (q15_t)0xF2DE,
+ (q15_t)0x80B2, (q15_t)0xF2AC, (q15_t)0x80B7, (q15_t)0xF27A,
+ (q15_t)0x80BC, (q15_t)0xF248, (q15_t)0x80C2, (q15_t)0xF216,
+ (q15_t)0x80C7, (q15_t)0xF1E4, (q15_t)0x80CD, (q15_t)0xF1B2,
+ (q15_t)0x80D2, (q15_t)0xF180, (q15_t)0x80D8, (q15_t)0xF14E,
+ (q15_t)0x80DE, (q15_t)0xF11C, (q15_t)0x80E4, (q15_t)0xF0EA,
+ (q15_t)0x80EA, (q15_t)0xF0B8, (q15_t)0x80F0, (q15_t)0xF086,
+ (q15_t)0x80F6, (q15_t)0xF054, (q15_t)0x80FC, (q15_t)0xF022,
+ (q15_t)0x8102, (q15_t)0xEFF1, (q15_t)0x8109, (q15_t)0xEFBF,
+ (q15_t)0x810F, (q15_t)0xEF8D, (q15_t)0x8116, (q15_t)0xEF5B,
+ (q15_t)0x811C, (q15_t)0xEF29, (q15_t)0x8123, (q15_t)0xEEF7,
+ (q15_t)0x812A, (q15_t)0xEEC6, (q15_t)0x8130, (q15_t)0xEE94,
+ (q15_t)0x8137, (q15_t)0xEE62, (q15_t)0x813E, (q15_t)0xEE30,
+ (q15_t)0x8145, (q15_t)0xEDFE, (q15_t)0x814C, (q15_t)0xEDCD,
+ (q15_t)0x8154, (q15_t)0xED9B, (q15_t)0x815B, (q15_t)0xED69,
+ (q15_t)0x8162, (q15_t)0xED37, (q15_t)0x816A, (q15_t)0xED06,
+ (q15_t)0x8171, (q15_t)0xECD4, (q15_t)0x8179, (q15_t)0xECA2,
+ (q15_t)0x8180, (q15_t)0xEC71, (q15_t)0x8188, (q15_t)0xEC3F,
+ (q15_t)0x8190, (q15_t)0xEC0D, (q15_t)0x8198, (q15_t)0xEBDC,
+ (q15_t)0x81A0, (q15_t)0xEBAA, (q15_t)0x81A8, (q15_t)0xEB78,
+ (q15_t)0x81B0, (q15_t)0xEB47, (q15_t)0x81B8, (q15_t)0xEB15,
+ (q15_t)0x81C0, (q15_t)0xEAE4, (q15_t)0x81C8, (q15_t)0xEAB2,
+ (q15_t)0x81D1, (q15_t)0xEA80, (q15_t)0x81D9, (q15_t)0xEA4F,
+ (q15_t)0x81E2, (q15_t)0xEA1D, (q15_t)0x81EB, (q15_t)0xE9EC,
+ (q15_t)0x81F3, (q15_t)0xE9BA, (q15_t)0x81FC, (q15_t)0xE989,
+ (q15_t)0x8205, (q15_t)0xE957, (q15_t)0x820E, (q15_t)0xE926,
+ (q15_t)0x8217, (q15_t)0xE8F5, (q15_t)0x8220, (q15_t)0xE8C3,
+ (q15_t)0x8229, (q15_t)0xE892, (q15_t)0x8232, (q15_t)0xE860,
+ (q15_t)0x823C, (q15_t)0xE82F, (q15_t)0x8245, (q15_t)0xE7FD,
+ (q15_t)0x824F, (q15_t)0xE7CC, (q15_t)0x8258, (q15_t)0xE79B,
+ (q15_t)0x8262, (q15_t)0xE769, (q15_t)0x826B, (q15_t)0xE738,
+ (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x827F, (q15_t)0xE6D5,
+ (q15_t)0x8289, (q15_t)0xE6A4, (q15_t)0x8293, (q15_t)0xE673,
+ (q15_t)0x829D, (q15_t)0xE642, (q15_t)0x82A7, (q15_t)0xE610,
+ (q15_t)0x82B1, (q15_t)0xE5DF, (q15_t)0x82BC, (q15_t)0xE5AE,
+ (q15_t)0x82C6, (q15_t)0xE57D, (q15_t)0x82D0, (q15_t)0xE54C,
+ (q15_t)0x82DB, (q15_t)0xE51B, (q15_t)0x82E6, (q15_t)0xE4E9,
+ (q15_t)0x82F0, (q15_t)0xE4B8, (q15_t)0x82FB, (q15_t)0xE487,
+ (q15_t)0x8306, (q15_t)0xE456, (q15_t)0x8311, (q15_t)0xE425,
+ (q15_t)0x831C, (q15_t)0xE3F4, (q15_t)0x8327, (q15_t)0xE3C3,
+ (q15_t)0x8332, (q15_t)0xE392, (q15_t)0x833D, (q15_t)0xE361,
+ (q15_t)0x8348, (q15_t)0xE330, (q15_t)0x8354, (q15_t)0xE2FF,
+ (q15_t)0x835F, (q15_t)0xE2CE, (q15_t)0x836B, (q15_t)0xE29D,
+ (q15_t)0x8376, (q15_t)0xE26C, (q15_t)0x8382, (q15_t)0xE23B,
+ (q15_t)0x838E, (q15_t)0xE20A, (q15_t)0x8399, (q15_t)0xE1DA,
+ (q15_t)0x83A5, (q15_t)0xE1A9, (q15_t)0x83B1, (q15_t)0xE178,
+ (q15_t)0x83BD, (q15_t)0xE147, (q15_t)0x83C9, (q15_t)0xE116,
+ (q15_t)0x83D6, (q15_t)0xE0E6, (q15_t)0x83E2, (q15_t)0xE0B5,
+ (q15_t)0x83EE, (q15_t)0xE084, (q15_t)0x83FA, (q15_t)0xE053,
+ (q15_t)0x8407, (q15_t)0xE023, (q15_t)0x8414, (q15_t)0xDFF2,
+ (q15_t)0x8420, (q15_t)0xDFC1, (q15_t)0x842D, (q15_t)0xDF91,
+ (q15_t)0x843A, (q15_t)0xDF60, (q15_t)0x8446, (q15_t)0xDF2F,
+ (q15_t)0x8453, (q15_t)0xDEFF, (q15_t)0x8460, (q15_t)0xDECE,
+ (q15_t)0x846D, (q15_t)0xDE9E, (q15_t)0x847B, (q15_t)0xDE6D,
+ (q15_t)0x8488, (q15_t)0xDE3D, (q15_t)0x8495, (q15_t)0xDE0C,
+ (q15_t)0x84A2, (q15_t)0xDDDC, (q15_t)0x84B0, (q15_t)0xDDAB,
+ (q15_t)0x84BD, (q15_t)0xDD7B, (q15_t)0x84CB, (q15_t)0xDD4B,
+ (q15_t)0x84D9, (q15_t)0xDD1A, (q15_t)0x84E6, (q15_t)0xDCEA,
+ (q15_t)0x84F4, (q15_t)0xDCBA, (q15_t)0x8502, (q15_t)0xDC89,
+ (q15_t)0x8510, (q15_t)0xDC59, (q15_t)0x851E, (q15_t)0xDC29,
+ (q15_t)0x852C, (q15_t)0xDBF8, (q15_t)0x853A, (q15_t)0xDBC8,
+ (q15_t)0x8549, (q15_t)0xDB98, (q15_t)0x8557, (q15_t)0xDB68,
+ (q15_t)0x8565, (q15_t)0xDB38, (q15_t)0x8574, (q15_t)0xDB08,
+ (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x8591, (q15_t)0xDAA7,
+ (q15_t)0x85A0, (q15_t)0xDA77, (q15_t)0x85AF, (q15_t)0xDA47,
+ (q15_t)0x85BD, (q15_t)0xDA17, (q15_t)0x85CC, (q15_t)0xD9E7,
+ (q15_t)0x85DB, (q15_t)0xD9B7, (q15_t)0x85EA, (q15_t)0xD987,
+ (q15_t)0x85FA, (q15_t)0xD957, (q15_t)0x8609, (q15_t)0xD927,
+ (q15_t)0x8618, (q15_t)0xD8F8, (q15_t)0x8627, (q15_t)0xD8C8,
+ (q15_t)0x8637, (q15_t)0xD898, (q15_t)0x8646, (q15_t)0xD868,
+ (q15_t)0x8656, (q15_t)0xD838, (q15_t)0x8666, (q15_t)0xD809,
+ (q15_t)0x8675, (q15_t)0xD7D9, (q15_t)0x8685, (q15_t)0xD7A9,
+ (q15_t)0x8695, (q15_t)0xD779, (q15_t)0x86A5, (q15_t)0xD74A,
+ (q15_t)0x86B5, (q15_t)0xD71A, (q15_t)0x86C5, (q15_t)0xD6EA,
+ (q15_t)0x86D5, (q15_t)0xD6BB, (q15_t)0x86E6, (q15_t)0xD68B,
+ (q15_t)0x86F6, (q15_t)0xD65C, (q15_t)0x8706, (q15_t)0xD62C,
+ (q15_t)0x8717, (q15_t)0xD5FD, (q15_t)0x8727, (q15_t)0xD5CD,
+ (q15_t)0x8738, (q15_t)0xD59E, (q15_t)0x8749, (q15_t)0xD56E,
+ (q15_t)0x8759, (q15_t)0xD53F, (q15_t)0x876A, (q15_t)0xD510,
+ (q15_t)0x877B, (q15_t)0xD4E0, (q15_t)0x878C, (q15_t)0xD4B1,
+ (q15_t)0x879D, (q15_t)0xD482, (q15_t)0x87AE, (q15_t)0xD452,
+ (q15_t)0x87BF, (q15_t)0xD423, (q15_t)0x87D1, (q15_t)0xD3F4,
+ (q15_t)0x87E2, (q15_t)0xD3C5, (q15_t)0x87F3, (q15_t)0xD396,
+ (q15_t)0x8805, (q15_t)0xD367, (q15_t)0x8816, (q15_t)0xD337,
+ (q15_t)0x8828, (q15_t)0xD308, (q15_t)0x883A, (q15_t)0xD2D9,
+ (q15_t)0x884B, (q15_t)0xD2AA, (q15_t)0x885D, (q15_t)0xD27B,
+ (q15_t)0x886F, (q15_t)0xD24C, (q15_t)0x8881, (q15_t)0xD21D,
+ (q15_t)0x8893, (q15_t)0xD1EE, (q15_t)0x88A5, (q15_t)0xD1C0,
+ (q15_t)0x88B8, (q15_t)0xD191, (q15_t)0x88CA, (q15_t)0xD162,
+ (q15_t)0x88DC, (q15_t)0xD133, (q15_t)0x88EF, (q15_t)0xD104,
+ (q15_t)0x8901, (q15_t)0xD0D6, (q15_t)0x8914, (q15_t)0xD0A7,
+ (q15_t)0x8926, (q15_t)0xD078, (q15_t)0x8939, (q15_t)0xD04A,
+ (q15_t)0x894C, (q15_t)0xD01B, (q15_t)0x895F, (q15_t)0xCFEC,
+ (q15_t)0x8971, (q15_t)0xCFBE, (q15_t)0x8984, (q15_t)0xCF8F,
+ (q15_t)0x8997, (q15_t)0xCF61, (q15_t)0x89AB, (q15_t)0xCF32,
+ (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x89D1, (q15_t)0xCED5,
+ (q15_t)0x89E4, (q15_t)0xCEA7, (q15_t)0x89F8, (q15_t)0xCE79,
+ (q15_t)0x8A0B, (q15_t)0xCE4A, (q15_t)0x8A1F, (q15_t)0xCE1C,
+ (q15_t)0x8A33, (q15_t)0xCDEE, (q15_t)0x8A46, (q15_t)0xCDBF,
+ (q15_t)0x8A5A, (q15_t)0xCD91, (q15_t)0x8A6E, (q15_t)0xCD63,
+ (q15_t)0x8A82, (q15_t)0xCD35, (q15_t)0x8A96, (q15_t)0xCD07,
+ (q15_t)0x8AAA, (q15_t)0xCCD9, (q15_t)0x8ABE, (q15_t)0xCCAB,
+ (q15_t)0x8AD2, (q15_t)0xCC7D, (q15_t)0x8AE6, (q15_t)0xCC4F,
+ (q15_t)0x8AFB, (q15_t)0xCC21, (q15_t)0x8B0F, (q15_t)0xCBF3,
+ (q15_t)0x8B24, (q15_t)0xCBC5, (q15_t)0x8B38, (q15_t)0xCB97,
+ (q15_t)0x8B4D, (q15_t)0xCB69, (q15_t)0x8B61, (q15_t)0xCB3B,
+ (q15_t)0x8B76, (q15_t)0xCB0D, (q15_t)0x8B8B, (q15_t)0xCAE0,
+ (q15_t)0x8BA0, (q15_t)0xCAB2, (q15_t)0x8BB5, (q15_t)0xCA84,
+ (q15_t)0x8BCA, (q15_t)0xCA57, (q15_t)0x8BDF, (q15_t)0xCA29,
+ (q15_t)0x8BF4, (q15_t)0xC9FB, (q15_t)0x8C09, (q15_t)0xC9CE,
+ (q15_t)0x8C1F, (q15_t)0xC9A0, (q15_t)0x8C34, (q15_t)0xC973,
+ (q15_t)0x8C4A, (q15_t)0xC945, (q15_t)0x8C5F, (q15_t)0xC918,
+ (q15_t)0x8C75, (q15_t)0xC8EB, (q15_t)0x8C8A, (q15_t)0xC8BD,
+ (q15_t)0x8CA0, (q15_t)0xC890, (q15_t)0x8CB6, (q15_t)0xC863,
+ (q15_t)0x8CCC, (q15_t)0xC835, (q15_t)0x8CE2, (q15_t)0xC808,
+ (q15_t)0x8CF8, (q15_t)0xC7DB, (q15_t)0x8D0E, (q15_t)0xC7AE,
+ (q15_t)0x8D24, (q15_t)0xC781, (q15_t)0x8D3A, (q15_t)0xC754,
+ (q15_t)0x8D50, (q15_t)0xC727, (q15_t)0x8D67, (q15_t)0xC6F9,
+ (q15_t)0x8D7D, (q15_t)0xC6CD, (q15_t)0x8D94, (q15_t)0xC6A0,
+ (q15_t)0x8DAA, (q15_t)0xC673, (q15_t)0x8DC1, (q15_t)0xC646,
+ (q15_t)0x8DD8, (q15_t)0xC619, (q15_t)0x8DEE, (q15_t)0xC5EC,
+ (q15_t)0x8E05, (q15_t)0xC5BF, (q15_t)0x8E1C, (q15_t)0xC593,
+ (q15_t)0x8E33, (q15_t)0xC566, (q15_t)0x8E4A, (q15_t)0xC539,
+ (q15_t)0x8E61, (q15_t)0xC50D, (q15_t)0x8E79, (q15_t)0xC4E0,
+ (q15_t)0x8E90, (q15_t)0xC4B3, (q15_t)0x8EA7, (q15_t)0xC487,
+ (q15_t)0x8EBE, (q15_t)0xC45A, (q15_t)0x8ED6, (q15_t)0xC42E,
+ (q15_t)0x8EED, (q15_t)0xC402, (q15_t)0x8F05, (q15_t)0xC3D5,
+ (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x8F34, (q15_t)0xC37C,
+ (q15_t)0x8F4C, (q15_t)0xC350, (q15_t)0x8F64, (q15_t)0xC324,
+ (q15_t)0x8F7C, (q15_t)0xC2F8, (q15_t)0x8F94, (q15_t)0xC2CC,
+ (q15_t)0x8FAC, (q15_t)0xC29F, (q15_t)0x8FC4, (q15_t)0xC273,
+ (q15_t)0x8FDC, (q15_t)0xC247, (q15_t)0x8FF5, (q15_t)0xC21B,
+ (q15_t)0x900D, (q15_t)0xC1EF, (q15_t)0x9025, (q15_t)0xC1C3,
+ (q15_t)0x903E, (q15_t)0xC197, (q15_t)0x9056, (q15_t)0xC16C,
+ (q15_t)0x906F, (q15_t)0xC140, (q15_t)0x9088, (q15_t)0xC114,
+ (q15_t)0x90A0, (q15_t)0xC0E8, (q15_t)0x90B9, (q15_t)0xC0BC,
+ (q15_t)0x90D2, (q15_t)0xC091, (q15_t)0x90EB, (q15_t)0xC065,
+ (q15_t)0x9104, (q15_t)0xC03A, (q15_t)0x911D, (q15_t)0xC00E,
+ (q15_t)0x9136, (q15_t)0xBFE2, (q15_t)0x9150, (q15_t)0xBFB7,
+ (q15_t)0x9169, (q15_t)0xBF8C, (q15_t)0x9182, (q15_t)0xBF60,
+ (q15_t)0x919C, (q15_t)0xBF35, (q15_t)0x91B5, (q15_t)0xBF09,
+ (q15_t)0x91CF, (q15_t)0xBEDE, (q15_t)0x91E8, (q15_t)0xBEB3,
+ (q15_t)0x9202, (q15_t)0xBE88, (q15_t)0x921C, (q15_t)0xBE5D,
+ (q15_t)0x9235, (q15_t)0xBE31, (q15_t)0x924F, (q15_t)0xBE06,
+ (q15_t)0x9269, (q15_t)0xBDDB, (q15_t)0x9283, (q15_t)0xBDB0,
+ (q15_t)0x929D, (q15_t)0xBD85, (q15_t)0x92B7, (q15_t)0xBD5A,
+ (q15_t)0x92D2, (q15_t)0xBD2F, (q15_t)0x92EC, (q15_t)0xBD05,
+ (q15_t)0x9306, (q15_t)0xBCDA, (q15_t)0x9321, (q15_t)0xBCAF,
+ (q15_t)0x933B, (q15_t)0xBC84, (q15_t)0x9356, (q15_t)0xBC5A,
+ (q15_t)0x9370, (q15_t)0xBC2F, (q15_t)0x938B, (q15_t)0xBC04,
+ (q15_t)0x93A6, (q15_t)0xBBDA, (q15_t)0x93C0, (q15_t)0xBBAF,
+ (q15_t)0x93DB, (q15_t)0xBB85, (q15_t)0x93F6, (q15_t)0xBB5A,
+ (q15_t)0x9411, (q15_t)0xBB30, (q15_t)0x942C, (q15_t)0xBB05,
+ (q15_t)0x9447, (q15_t)0xBADB, (q15_t)0x9463, (q15_t)0xBAB1,
+ (q15_t)0x947E, (q15_t)0xBA87, (q15_t)0x9499, (q15_t)0xBA5C,
+ (q15_t)0x94B5, (q15_t)0xBA32, (q15_t)0x94D0, (q15_t)0xBA08,
+ (q15_t)0x94EC, (q15_t)0xB9DE, (q15_t)0x9507, (q15_t)0xB9B4,
+ (q15_t)0x9523, (q15_t)0xB98A, (q15_t)0x953E, (q15_t)0xB960,
+ (q15_t)0x955A, (q15_t)0xB936, (q15_t)0x9576, (q15_t)0xB90C,
+ (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x95AE, (q15_t)0xB8B9,
+ (q15_t)0x95CA, (q15_t)0xB88F, (q15_t)0x95E6, (q15_t)0xB865,
+ (q15_t)0x9602, (q15_t)0xB83C, (q15_t)0x961E, (q15_t)0xB812,
+ (q15_t)0x963B, (q15_t)0xB7E9, (q15_t)0x9657, (q15_t)0xB7BF,
+ (q15_t)0x9673, (q15_t)0xB796, (q15_t)0x9690, (q15_t)0xB76C,
+ (q15_t)0x96AC, (q15_t)0xB743, (q15_t)0x96C9, (q15_t)0xB719,
+ (q15_t)0x96E6, (q15_t)0xB6F0, (q15_t)0x9702, (q15_t)0xB6C7,
+ (q15_t)0x971F, (q15_t)0xB69E, (q15_t)0x973C, (q15_t)0xB675,
+ (q15_t)0x9759, (q15_t)0xB64B, (q15_t)0x9776, (q15_t)0xB622,
+ (q15_t)0x9793, (q15_t)0xB5F9, (q15_t)0x97B0, (q15_t)0xB5D0,
+ (q15_t)0x97CD, (q15_t)0xB5A7, (q15_t)0x97EA, (q15_t)0xB57E,
+ (q15_t)0x9808, (q15_t)0xB556, (q15_t)0x9825, (q15_t)0xB52D,
+ (q15_t)0x9842, (q15_t)0xB504, (q15_t)0x9860, (q15_t)0xB4DB,
+ (q15_t)0x987D, (q15_t)0xB4B3, (q15_t)0x989B, (q15_t)0xB48A,
+ (q15_t)0x98B9, (q15_t)0xB461, (q15_t)0x98D6, (q15_t)0xB439,
+ (q15_t)0x98F4, (q15_t)0xB410, (q15_t)0x9912, (q15_t)0xB3E8,
+ (q15_t)0x9930, (q15_t)0xB3C0, (q15_t)0x994E, (q15_t)0xB397,
+ (q15_t)0x996C, (q15_t)0xB36F, (q15_t)0x998A, (q15_t)0xB347,
+ (q15_t)0x99A8, (q15_t)0xB31E, (q15_t)0x99C6, (q15_t)0xB2F6,
+ (q15_t)0x99E5, (q15_t)0xB2CE, (q15_t)0x9A03, (q15_t)0xB2A6,
+ (q15_t)0x9A22, (q15_t)0xB27E, (q15_t)0x9A40, (q15_t)0xB256,
+ (q15_t)0x9A5F, (q15_t)0xB22E, (q15_t)0x9A7D, (q15_t)0xB206,
+ (q15_t)0x9A9C, (q15_t)0xB1DE, (q15_t)0x9ABA, (q15_t)0xB1B7,
+ (q15_t)0x9AD9, (q15_t)0xB18F, (q15_t)0x9AF8, (q15_t)0xB167,
+ (q15_t)0x9B17, (q15_t)0xB140, (q15_t)0x9B36, (q15_t)0xB118,
+ (q15_t)0x9B55, (q15_t)0xB0F0, (q15_t)0x9B74, (q15_t)0xB0C9,
+ (q15_t)0x9B93, (q15_t)0xB0A1, (q15_t)0x9BB2, (q15_t)0xB07A,
+ (q15_t)0x9BD2, (q15_t)0xB053, (q15_t)0x9BF1, (q15_t)0xB02B,
+ (q15_t)0x9C10, (q15_t)0xB004, (q15_t)0x9C30, (q15_t)0xAFDD,
+ (q15_t)0x9C4F, (q15_t)0xAFB6, (q15_t)0x9C6F, (q15_t)0xAF8F,
+ (q15_t)0x9C8E, (q15_t)0xAF68, (q15_t)0x9CAE, (q15_t)0xAF40,
+ (q15_t)0x9CCE, (q15_t)0xAF1A, (q15_t)0x9CEE, (q15_t)0xAEF3,
+ (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0x9D2D, (q15_t)0xAEA5,
+ (q15_t)0x9D4D, (q15_t)0xAE7E, (q15_t)0x9D6D, (q15_t)0xAE57,
+ (q15_t)0x9D8E, (q15_t)0xAE31, (q15_t)0x9DAE, (q15_t)0xAE0A,
+ (q15_t)0x9DCE, (q15_t)0xADE3, (q15_t)0x9DEE, (q15_t)0xADBD,
+ (q15_t)0x9E0E, (q15_t)0xAD96, (q15_t)0x9E2F, (q15_t)0xAD70,
+ (q15_t)0x9E4F, (q15_t)0xAD4A, (q15_t)0x9E70, (q15_t)0xAD23,
+ (q15_t)0x9E90, (q15_t)0xACFD, (q15_t)0x9EB1, (q15_t)0xACD7,
+ (q15_t)0x9ED2, (q15_t)0xACB1, (q15_t)0x9EF2, (q15_t)0xAC8A,
+ (q15_t)0x9F13, (q15_t)0xAC64, (q15_t)0x9F34, (q15_t)0xAC3E,
+ (q15_t)0x9F55, (q15_t)0xAC18, (q15_t)0x9F76, (q15_t)0xABF2,
+ (q15_t)0x9F97, (q15_t)0xABCC, (q15_t)0x9FB8, (q15_t)0xABA7,
+ (q15_t)0x9FD9, (q15_t)0xAB81, (q15_t)0x9FFB, (q15_t)0xAB5B,
+ (q15_t)0xA01C, (q15_t)0xAB35, (q15_t)0xA03D, (q15_t)0xAB10,
+ (q15_t)0xA05F, (q15_t)0xAAEA, (q15_t)0xA080, (q15_t)0xAAC5,
+ (q15_t)0xA0A1, (q15_t)0xAA9F, (q15_t)0xA0C3, (q15_t)0xAA7A,
+ (q15_t)0xA0E5, (q15_t)0xAA54, (q15_t)0xA106, (q15_t)0xAA2F,
+ (q15_t)0xA128, (q15_t)0xAA0A, (q15_t)0xA14A, (q15_t)0xA9E5,
+ (q15_t)0xA16C, (q15_t)0xA9BF, (q15_t)0xA18E, (q15_t)0xA99A,
+ (q15_t)0xA1AF, (q15_t)0xA975, (q15_t)0xA1D2, (q15_t)0xA950,
+ (q15_t)0xA1F4, (q15_t)0xA92B, (q15_t)0xA216, (q15_t)0xA906,
+ (q15_t)0xA238, (q15_t)0xA8E2, (q15_t)0xA25A, (q15_t)0xA8BD,
+ (q15_t)0xA27C, (q15_t)0xA898, (q15_t)0xA29F, (q15_t)0xA873,
+ (q15_t)0xA2C1, (q15_t)0xA84F, (q15_t)0xA2E4, (q15_t)0xA82A,
+ (q15_t)0xA306, (q15_t)0xA806, (q15_t)0xA329, (q15_t)0xA7E1,
+ (q15_t)0xA34B, (q15_t)0xA7BD, (q15_t)0xA36E, (q15_t)0xA798,
+ (q15_t)0xA391, (q15_t)0xA774, (q15_t)0xA3B4, (q15_t)0xA750,
+ (q15_t)0xA3D6, (q15_t)0xA72B, (q15_t)0xA3F9, (q15_t)0xA707,
+ (q15_t)0xA41C, (q15_t)0xA6E3, (q15_t)0xA43F, (q15_t)0xA6BF,
+ (q15_t)0xA462, (q15_t)0xA69B, (q15_t)0xA486, (q15_t)0xA677,
+ (q15_t)0xA4A9, (q15_t)0xA653, (q15_t)0xA4CC, (q15_t)0xA62F,
+ (q15_t)0xA4EF, (q15_t)0xA60C, (q15_t)0xA513, (q15_t)0xA5E8,
+ (q15_t)0xA536, (q15_t)0xA5C4, (q15_t)0xA55A, (q15_t)0xA5A1,
+ (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xA5A1, (q15_t)0xA55A,
+ (q15_t)0xA5C4, (q15_t)0xA536, (q15_t)0xA5E8, (q15_t)0xA513,
+ (q15_t)0xA60C, (q15_t)0xA4EF, (q15_t)0xA62F, (q15_t)0xA4CC,
+ (q15_t)0xA653, (q15_t)0xA4A9, (q15_t)0xA677, (q15_t)0xA486,
+ (q15_t)0xA69B, (q15_t)0xA462, (q15_t)0xA6BF, (q15_t)0xA43F,
+ (q15_t)0xA6E3, (q15_t)0xA41C, (q15_t)0xA707, (q15_t)0xA3F9,
+ (q15_t)0xA72B, (q15_t)0xA3D6, (q15_t)0xA750, (q15_t)0xA3B4,
+ (q15_t)0xA774, (q15_t)0xA391, (q15_t)0xA798, (q15_t)0xA36E,
+ (q15_t)0xA7BD, (q15_t)0xA34B, (q15_t)0xA7E1, (q15_t)0xA329,
+ (q15_t)0xA806, (q15_t)0xA306, (q15_t)0xA82A, (q15_t)0xA2E4,
+ (q15_t)0xA84F, (q15_t)0xA2C1, (q15_t)0xA873, (q15_t)0xA29F,
+ (q15_t)0xA898, (q15_t)0xA27C, (q15_t)0xA8BD, (q15_t)0xA25A,
+ (q15_t)0xA8E2, (q15_t)0xA238, (q15_t)0xA906, (q15_t)0xA216,
+ (q15_t)0xA92B, (q15_t)0xA1F4, (q15_t)0xA950, (q15_t)0xA1D2,
+ (q15_t)0xA975, (q15_t)0xA1AF, (q15_t)0xA99A, (q15_t)0xA18E,
+ (q15_t)0xA9BF, (q15_t)0xA16C, (q15_t)0xA9E5, (q15_t)0xA14A,
+ (q15_t)0xAA0A, (q15_t)0xA128, (q15_t)0xAA2F, (q15_t)0xA106,
+ (q15_t)0xAA54, (q15_t)0xA0E5, (q15_t)0xAA7A, (q15_t)0xA0C3,
+ (q15_t)0xAA9F, (q15_t)0xA0A1, (q15_t)0xAAC5, (q15_t)0xA080,
+ (q15_t)0xAAEA, (q15_t)0xA05F, (q15_t)0xAB10, (q15_t)0xA03D,
+ (q15_t)0xAB35, (q15_t)0xA01C, (q15_t)0xAB5B, (q15_t)0x9FFB,
+ (q15_t)0xAB81, (q15_t)0x9FD9, (q15_t)0xABA7, (q15_t)0x9FB8,
+ (q15_t)0xABCC, (q15_t)0x9F97, (q15_t)0xABF2, (q15_t)0x9F76,
+ (q15_t)0xAC18, (q15_t)0x9F55, (q15_t)0xAC3E, (q15_t)0x9F34,
+ (q15_t)0xAC64, (q15_t)0x9F13, (q15_t)0xAC8A, (q15_t)0x9EF2,
+ (q15_t)0xACB1, (q15_t)0x9ED2, (q15_t)0xACD7, (q15_t)0x9EB1,
+ (q15_t)0xACFD, (q15_t)0x9E90, (q15_t)0xAD23, (q15_t)0x9E70,
+ (q15_t)0xAD4A, (q15_t)0x9E4F, (q15_t)0xAD70, (q15_t)0x9E2F,
+ (q15_t)0xAD96, (q15_t)0x9E0E, (q15_t)0xADBD, (q15_t)0x9DEE,
+ (q15_t)0xADE3, (q15_t)0x9DCE, (q15_t)0xAE0A, (q15_t)0x9DAE,
+ (q15_t)0xAE31, (q15_t)0x9D8E, (q15_t)0xAE57, (q15_t)0x9D6D,
+ (q15_t)0xAE7E, (q15_t)0x9D4D, (q15_t)0xAEA5, (q15_t)0x9D2D,
+ (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xAEF3, (q15_t)0x9CEE,
+ (q15_t)0xAF1A, (q15_t)0x9CCE, (q15_t)0xAF40, (q15_t)0x9CAE,
+ (q15_t)0xAF68, (q15_t)0x9C8E, (q15_t)0xAF8F, (q15_t)0x9C6F,
+ (q15_t)0xAFB6, (q15_t)0x9C4F, (q15_t)0xAFDD, (q15_t)0x9C30,
+ (q15_t)0xB004, (q15_t)0x9C10, (q15_t)0xB02B, (q15_t)0x9BF1,
+ (q15_t)0xB053, (q15_t)0x9BD2, (q15_t)0xB07A, (q15_t)0x9BB2,
+ (q15_t)0xB0A1, (q15_t)0x9B93, (q15_t)0xB0C9, (q15_t)0x9B74,
+ (q15_t)0xB0F0, (q15_t)0x9B55, (q15_t)0xB118, (q15_t)0x9B36,
+ (q15_t)0xB140, (q15_t)0x9B17, (q15_t)0xB167, (q15_t)0x9AF8,
+ (q15_t)0xB18F, (q15_t)0x9AD9, (q15_t)0xB1B7, (q15_t)0x9ABA,
+ (q15_t)0xB1DE, (q15_t)0x9A9C, (q15_t)0xB206, (q15_t)0x9A7D,
+ (q15_t)0xB22E, (q15_t)0x9A5F, (q15_t)0xB256, (q15_t)0x9A40,
+ (q15_t)0xB27E, (q15_t)0x9A22, (q15_t)0xB2A6, (q15_t)0x9A03,
+ (q15_t)0xB2CE, (q15_t)0x99E5, (q15_t)0xB2F6, (q15_t)0x99C6,
+ (q15_t)0xB31E, (q15_t)0x99A8, (q15_t)0xB347, (q15_t)0x998A,
+ (q15_t)0xB36F, (q15_t)0x996C, (q15_t)0xB397, (q15_t)0x994E,
+ (q15_t)0xB3C0, (q15_t)0x9930, (q15_t)0xB3E8, (q15_t)0x9912,
+ (q15_t)0xB410, (q15_t)0x98F4, (q15_t)0xB439, (q15_t)0x98D6,
+ (q15_t)0xB461, (q15_t)0x98B9, (q15_t)0xB48A, (q15_t)0x989B,
+ (q15_t)0xB4B3, (q15_t)0x987D, (q15_t)0xB4DB, (q15_t)0x9860,
+ (q15_t)0xB504, (q15_t)0x9842, (q15_t)0xB52D, (q15_t)0x9825,
+ (q15_t)0xB556, (q15_t)0x9808, (q15_t)0xB57E, (q15_t)0x97EA,
+ (q15_t)0xB5A7, (q15_t)0x97CD, (q15_t)0xB5D0, (q15_t)0x97B0,
+ (q15_t)0xB5F9, (q15_t)0x9793, (q15_t)0xB622, (q15_t)0x9776,
+ (q15_t)0xB64B, (q15_t)0x9759, (q15_t)0xB675, (q15_t)0x973C,
+ (q15_t)0xB69E, (q15_t)0x971F, (q15_t)0xB6C7, (q15_t)0x9702,
+ (q15_t)0xB6F0, (q15_t)0x96E6, (q15_t)0xB719, (q15_t)0x96C9,
+ (q15_t)0xB743, (q15_t)0x96AC, (q15_t)0xB76C, (q15_t)0x9690,
+ (q15_t)0xB796, (q15_t)0x9673, (q15_t)0xB7BF, (q15_t)0x9657,
+ (q15_t)0xB7E9, (q15_t)0x963B, (q15_t)0xB812, (q15_t)0x961E,
+ (q15_t)0xB83C, (q15_t)0x9602, (q15_t)0xB865, (q15_t)0x95E6,
+ (q15_t)0xB88F, (q15_t)0x95CA, (q15_t)0xB8B9, (q15_t)0x95AE,
+ (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xB90C, (q15_t)0x9576,
+ (q15_t)0xB936, (q15_t)0x955A, (q15_t)0xB960, (q15_t)0x953E,
+ (q15_t)0xB98A, (q15_t)0x9523, (q15_t)0xB9B4, (q15_t)0x9507,
+ (q15_t)0xB9DE, (q15_t)0x94EC, (q15_t)0xBA08, (q15_t)0x94D0,
+ (q15_t)0xBA32, (q15_t)0x94B5, (q15_t)0xBA5C, (q15_t)0x9499,
+ (q15_t)0xBA87, (q15_t)0x947E, (q15_t)0xBAB1, (q15_t)0x9463,
+ (q15_t)0xBADB, (q15_t)0x9447, (q15_t)0xBB05, (q15_t)0x942C,
+ (q15_t)0xBB30, (q15_t)0x9411, (q15_t)0xBB5A, (q15_t)0x93F6,
+ (q15_t)0xBB85, (q15_t)0x93DB, (q15_t)0xBBAF, (q15_t)0x93C0,
+ (q15_t)0xBBDA, (q15_t)0x93A6, (q15_t)0xBC04, (q15_t)0x938B,
+ (q15_t)0xBC2F, (q15_t)0x9370, (q15_t)0xBC5A, (q15_t)0x9356,
+ (q15_t)0xBC84, (q15_t)0x933B, (q15_t)0xBCAF, (q15_t)0x9321,
+ (q15_t)0xBCDA, (q15_t)0x9306, (q15_t)0xBD05, (q15_t)0x92EC,
+ (q15_t)0xBD2F, (q15_t)0x92D2, (q15_t)0xBD5A, (q15_t)0x92B7,
+ (q15_t)0xBD85, (q15_t)0x929D, (q15_t)0xBDB0, (q15_t)0x9283,
+ (q15_t)0xBDDB, (q15_t)0x9269, (q15_t)0xBE06, (q15_t)0x924F,
+ (q15_t)0xBE31, (q15_t)0x9235, (q15_t)0xBE5D, (q15_t)0x921C,
+ (q15_t)0xBE88, (q15_t)0x9202, (q15_t)0xBEB3, (q15_t)0x91E8,
+ (q15_t)0xBEDE, (q15_t)0x91CF, (q15_t)0xBF09, (q15_t)0x91B5,
+ (q15_t)0xBF35, (q15_t)0x919C, (q15_t)0xBF60, (q15_t)0x9182,
+ (q15_t)0xBF8C, (q15_t)0x9169, (q15_t)0xBFB7, (q15_t)0x9150,
+ (q15_t)0xBFE2, (q15_t)0x9136, (q15_t)0xC00E, (q15_t)0x911D,
+ (q15_t)0xC03A, (q15_t)0x9104, (q15_t)0xC065, (q15_t)0x90EB,
+ (q15_t)0xC091, (q15_t)0x90D2, (q15_t)0xC0BC, (q15_t)0x90B9,
+ (q15_t)0xC0E8, (q15_t)0x90A0, (q15_t)0xC114, (q15_t)0x9088,
+ (q15_t)0xC140, (q15_t)0x906F, (q15_t)0xC16C, (q15_t)0x9056,
+ (q15_t)0xC197, (q15_t)0x903E, (q15_t)0xC1C3, (q15_t)0x9025,
+ (q15_t)0xC1EF, (q15_t)0x900D, (q15_t)0xC21B, (q15_t)0x8FF5,
+ (q15_t)0xC247, (q15_t)0x8FDC, (q15_t)0xC273, (q15_t)0x8FC4,
+ (q15_t)0xC29F, (q15_t)0x8FAC, (q15_t)0xC2CC, (q15_t)0x8F94,
+ (q15_t)0xC2F8, (q15_t)0x8F7C, (q15_t)0xC324, (q15_t)0x8F64,
+ (q15_t)0xC350, (q15_t)0x8F4C, (q15_t)0xC37C, (q15_t)0x8F34,
+ (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC3D5, (q15_t)0x8F05,
+ (q15_t)0xC402, (q15_t)0x8EED, (q15_t)0xC42E, (q15_t)0x8ED6,
+ (q15_t)0xC45A, (q15_t)0x8EBE, (q15_t)0xC487, (q15_t)0x8EA7,
+ (q15_t)0xC4B3, (q15_t)0x8E90, (q15_t)0xC4E0, (q15_t)0x8E79,
+ (q15_t)0xC50D, (q15_t)0x8E61, (q15_t)0xC539, (q15_t)0x8E4A,
+ (q15_t)0xC566, (q15_t)0x8E33, (q15_t)0xC593, (q15_t)0x8E1C,
+ (q15_t)0xC5BF, (q15_t)0x8E05, (q15_t)0xC5EC, (q15_t)0x8DEE,
+ (q15_t)0xC619, (q15_t)0x8DD8, (q15_t)0xC646, (q15_t)0x8DC1,
+ (q15_t)0xC673, (q15_t)0x8DAA, (q15_t)0xC6A0, (q15_t)0x8D94,
+ (q15_t)0xC6CD, (q15_t)0x8D7D, (q15_t)0xC6F9, (q15_t)0x8D67,
+ (q15_t)0xC727, (q15_t)0x8D50, (q15_t)0xC754, (q15_t)0x8D3A,
+ (q15_t)0xC781, (q15_t)0x8D24, (q15_t)0xC7AE, (q15_t)0x8D0E,
+ (q15_t)0xC7DB, (q15_t)0x8CF8, (q15_t)0xC808, (q15_t)0x8CE2,
+ (q15_t)0xC835, (q15_t)0x8CCC, (q15_t)0xC863, (q15_t)0x8CB6,
+ (q15_t)0xC890, (q15_t)0x8CA0, (q15_t)0xC8BD, (q15_t)0x8C8A,
+ (q15_t)0xC8EB, (q15_t)0x8C75, (q15_t)0xC918, (q15_t)0x8C5F,
+ (q15_t)0xC945, (q15_t)0x8C4A, (q15_t)0xC973, (q15_t)0x8C34,
+ (q15_t)0xC9A0, (q15_t)0x8C1F, (q15_t)0xC9CE, (q15_t)0x8C09,
+ (q15_t)0xC9FB, (q15_t)0x8BF4, (q15_t)0xCA29, (q15_t)0x8BDF,
+ (q15_t)0xCA57, (q15_t)0x8BCA, (q15_t)0xCA84, (q15_t)0x8BB5,
+ (q15_t)0xCAB2, (q15_t)0x8BA0, (q15_t)0xCAE0, (q15_t)0x8B8B,
+ (q15_t)0xCB0D, (q15_t)0x8B76, (q15_t)0xCB3B, (q15_t)0x8B61,
+ (q15_t)0xCB69, (q15_t)0x8B4D, (q15_t)0xCB97, (q15_t)0x8B38,
+ (q15_t)0xCBC5, (q15_t)0x8B24, (q15_t)0xCBF3, (q15_t)0x8B0F,
+ (q15_t)0xCC21, (q15_t)0x8AFB, (q15_t)0xCC4F, (q15_t)0x8AE6,
+ (q15_t)0xCC7D, (q15_t)0x8AD2, (q15_t)0xCCAB, (q15_t)0x8ABE,
+ (q15_t)0xCCD9, (q15_t)0x8AAA, (q15_t)0xCD07, (q15_t)0x8A96,
+ (q15_t)0xCD35, (q15_t)0x8A82, (q15_t)0xCD63, (q15_t)0x8A6E,
+ (q15_t)0xCD91, (q15_t)0x8A5A, (q15_t)0xCDBF, (q15_t)0x8A46,
+ (q15_t)0xCDEE, (q15_t)0x8A33, (q15_t)0xCE1C, (q15_t)0x8A1F,
+ (q15_t)0xCE4A, (q15_t)0x8A0B, (q15_t)0xCE79, (q15_t)0x89F8,
+ (q15_t)0xCEA7, (q15_t)0x89E4, (q15_t)0xCED5, (q15_t)0x89D1,
+ (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xCF32, (q15_t)0x89AB,
+ (q15_t)0xCF61, (q15_t)0x8997, (q15_t)0xCF8F, (q15_t)0x8984,
+ (q15_t)0xCFBE, (q15_t)0x8971, (q15_t)0xCFEC, (q15_t)0x895F,
+ (q15_t)0xD01B, (q15_t)0x894C, (q15_t)0xD04A, (q15_t)0x8939,
+ (q15_t)0xD078, (q15_t)0x8926, (q15_t)0xD0A7, (q15_t)0x8914,
+ (q15_t)0xD0D6, (q15_t)0x8901, (q15_t)0xD104, (q15_t)0x88EF,
+ (q15_t)0xD133, (q15_t)0x88DC, (q15_t)0xD162, (q15_t)0x88CA,
+ (q15_t)0xD191, (q15_t)0x88B8, (q15_t)0xD1C0, (q15_t)0x88A5,
+ (q15_t)0xD1EE, (q15_t)0x8893, (q15_t)0xD21D, (q15_t)0x8881,
+ (q15_t)0xD24C, (q15_t)0x886F, (q15_t)0xD27B, (q15_t)0x885D,
+ (q15_t)0xD2AA, (q15_t)0x884B, (q15_t)0xD2D9, (q15_t)0x883A,
+ (q15_t)0xD308, (q15_t)0x8828, (q15_t)0xD337, (q15_t)0x8816,
+ (q15_t)0xD367, (q15_t)0x8805, (q15_t)0xD396, (q15_t)0x87F3,
+ (q15_t)0xD3C5, (q15_t)0x87E2, (q15_t)0xD3F4, (q15_t)0x87D1,
+ (q15_t)0xD423, (q15_t)0x87BF, (q15_t)0xD452, (q15_t)0x87AE,
+ (q15_t)0xD482, (q15_t)0x879D, (q15_t)0xD4B1, (q15_t)0x878C,
+ (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD510, (q15_t)0x876A,
+ (q15_t)0xD53F, (q15_t)0x8759, (q15_t)0xD56E, (q15_t)0x8749,
+ (q15_t)0xD59E, (q15_t)0x8738, (q15_t)0xD5CD, (q15_t)0x8727,
+ (q15_t)0xD5FD, (q15_t)0x8717, (q15_t)0xD62C, (q15_t)0x8706,
+ (q15_t)0xD65C, (q15_t)0x86F6, (q15_t)0xD68B, (q15_t)0x86E6,
+ (q15_t)0xD6BB, (q15_t)0x86D5, (q15_t)0xD6EA, (q15_t)0x86C5,
+ (q15_t)0xD71A, (q15_t)0x86B5, (q15_t)0xD74A, (q15_t)0x86A5,
+ (q15_t)0xD779, (q15_t)0x8695, (q15_t)0xD7A9, (q15_t)0x8685,
+ (q15_t)0xD7D9, (q15_t)0x8675, (q15_t)0xD809, (q15_t)0x8666,
+ (q15_t)0xD838, (q15_t)0x8656, (q15_t)0xD868, (q15_t)0x8646,
+ (q15_t)0xD898, (q15_t)0x8637, (q15_t)0xD8C8, (q15_t)0x8627,
+ (q15_t)0xD8F8, (q15_t)0x8618, (q15_t)0xD927, (q15_t)0x8609,
+ (q15_t)0xD957, (q15_t)0x85FA, (q15_t)0xD987, (q15_t)0x85EA,
+ (q15_t)0xD9B7, (q15_t)0x85DB, (q15_t)0xD9E7, (q15_t)0x85CC,
+ (q15_t)0xDA17, (q15_t)0x85BD, (q15_t)0xDA47, (q15_t)0x85AF,
+ (q15_t)0xDA77, (q15_t)0x85A0, (q15_t)0xDAA7, (q15_t)0x8591,
+ (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDB08, (q15_t)0x8574,
+ (q15_t)0xDB38, (q15_t)0x8565, (q15_t)0xDB68, (q15_t)0x8557,
+ (q15_t)0xDB98, (q15_t)0x8549, (q15_t)0xDBC8, (q15_t)0x853A,
+ (q15_t)0xDBF8, (q15_t)0x852C, (q15_t)0xDC29, (q15_t)0x851E,
+ (q15_t)0xDC59, (q15_t)0x8510, (q15_t)0xDC89, (q15_t)0x8502,
+ (q15_t)0xDCBA, (q15_t)0x84F4, (q15_t)0xDCEA, (q15_t)0x84E6,
+ (q15_t)0xDD1A, (q15_t)0x84D9, (q15_t)0xDD4B, (q15_t)0x84CB,
+ (q15_t)0xDD7B, (q15_t)0x84BD, (q15_t)0xDDAB, (q15_t)0x84B0,
+ (q15_t)0xDDDC, (q15_t)0x84A2, (q15_t)0xDE0C, (q15_t)0x8495,
+ (q15_t)0xDE3D, (q15_t)0x8488, (q15_t)0xDE6D, (q15_t)0x847B,
+ (q15_t)0xDE9E, (q15_t)0x846D, (q15_t)0xDECE, (q15_t)0x8460,
+ (q15_t)0xDEFF, (q15_t)0x8453, (q15_t)0xDF2F, (q15_t)0x8446,
+ (q15_t)0xDF60, (q15_t)0x843A, (q15_t)0xDF91, (q15_t)0x842D,
+ (q15_t)0xDFC1, (q15_t)0x8420, (q15_t)0xDFF2, (q15_t)0x8414,
+ (q15_t)0xE023, (q15_t)0x8407, (q15_t)0xE053, (q15_t)0x83FA,
+ (q15_t)0xE084, (q15_t)0x83EE, (q15_t)0xE0B5, (q15_t)0x83E2,
+ (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE116, (q15_t)0x83C9,
+ (q15_t)0xE147, (q15_t)0x83BD, (q15_t)0xE178, (q15_t)0x83B1,
+ (q15_t)0xE1A9, (q15_t)0x83A5, (q15_t)0xE1DA, (q15_t)0x8399,
+ (q15_t)0xE20A, (q15_t)0x838E, (q15_t)0xE23B, (q15_t)0x8382,
+ (q15_t)0xE26C, (q15_t)0x8376, (q15_t)0xE29D, (q15_t)0x836B,
+ (q15_t)0xE2CE, (q15_t)0x835F, (q15_t)0xE2FF, (q15_t)0x8354,
+ (q15_t)0xE330, (q15_t)0x8348, (q15_t)0xE361, (q15_t)0x833D,
+ (q15_t)0xE392, (q15_t)0x8332, (q15_t)0xE3C3, (q15_t)0x8327,
+ (q15_t)0xE3F4, (q15_t)0x831C, (q15_t)0xE425, (q15_t)0x8311,
+ (q15_t)0xE456, (q15_t)0x8306, (q15_t)0xE487, (q15_t)0x82FB,
+ (q15_t)0xE4B8, (q15_t)0x82F0, (q15_t)0xE4E9, (q15_t)0x82E6,
+ (q15_t)0xE51B, (q15_t)0x82DB, (q15_t)0xE54C, (q15_t)0x82D0,
+ (q15_t)0xE57D, (q15_t)0x82C6, (q15_t)0xE5AE, (q15_t)0x82BC,
+ (q15_t)0xE5DF, (q15_t)0x82B1, (q15_t)0xE610, (q15_t)0x82A7,
+ (q15_t)0xE642, (q15_t)0x829D, (q15_t)0xE673, (q15_t)0x8293,
+ (q15_t)0xE6A4, (q15_t)0x8289, (q15_t)0xE6D5, (q15_t)0x827F,
+ (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xE738, (q15_t)0x826B,
+ (q15_t)0xE769, (q15_t)0x8262, (q15_t)0xE79B, (q15_t)0x8258,
+ (q15_t)0xE7CC, (q15_t)0x824F, (q15_t)0xE7FD, (q15_t)0x8245,
+ (q15_t)0xE82F, (q15_t)0x823C, (q15_t)0xE860, (q15_t)0x8232,
+ (q15_t)0xE892, (q15_t)0x8229, (q15_t)0xE8C3, (q15_t)0x8220,
+ (q15_t)0xE8F5, (q15_t)0x8217, (q15_t)0xE926, (q15_t)0x820E,
+ (q15_t)0xE957, (q15_t)0x8205, (q15_t)0xE989, (q15_t)0x81FC,
+ (q15_t)0xE9BA, (q15_t)0x81F3, (q15_t)0xE9EC, (q15_t)0x81EB,
+ (q15_t)0xEA1D, (q15_t)0x81E2, (q15_t)0xEA4F, (q15_t)0x81D9,
+ (q15_t)0xEA80, (q15_t)0x81D1, (q15_t)0xEAB2, (q15_t)0x81C8,
+ (q15_t)0xEAE4, (q15_t)0x81C0, (q15_t)0xEB15, (q15_t)0x81B8,
+ (q15_t)0xEB47, (q15_t)0x81B0, (q15_t)0xEB78, (q15_t)0x81A8,
+ (q15_t)0xEBAA, (q15_t)0x81A0, (q15_t)0xEBDC, (q15_t)0x8198,
+ (q15_t)0xEC0D, (q15_t)0x8190, (q15_t)0xEC3F, (q15_t)0x8188,
+ (q15_t)0xEC71, (q15_t)0x8180, (q15_t)0xECA2, (q15_t)0x8179,
+ (q15_t)0xECD4, (q15_t)0x8171, (q15_t)0xED06, (q15_t)0x816A,
+ (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xED69, (q15_t)0x815B,
+ (q15_t)0xED9B, (q15_t)0x8154, (q15_t)0xEDCD, (q15_t)0x814C,
+ (q15_t)0xEDFE, (q15_t)0x8145, (q15_t)0xEE30, (q15_t)0x813E,
+ (q15_t)0xEE62, (q15_t)0x8137, (q15_t)0xEE94, (q15_t)0x8130,
+ (q15_t)0xEEC6, (q15_t)0x812A, (q15_t)0xEEF7, (q15_t)0x8123,
+ (q15_t)0xEF29, (q15_t)0x811C, (q15_t)0xEF5B, (q15_t)0x8116,
+ (q15_t)0xEF8D, (q15_t)0x810F, (q15_t)0xEFBF, (q15_t)0x8109,
+ (q15_t)0xEFF1, (q15_t)0x8102, (q15_t)0xF022, (q15_t)0x80FC,
+ (q15_t)0xF054, (q15_t)0x80F6, (q15_t)0xF086, (q15_t)0x80F0,
+ (q15_t)0xF0B8, (q15_t)0x80EA, (q15_t)0xF0EA, (q15_t)0x80E4,
+ (q15_t)0xF11C, (q15_t)0x80DE, (q15_t)0xF14E, (q15_t)0x80D8,
+ (q15_t)0xF180, (q15_t)0x80D2, (q15_t)0xF1B2, (q15_t)0x80CD,
+ (q15_t)0xF1E4, (q15_t)0x80C7, (q15_t)0xF216, (q15_t)0x80C2,
+ (q15_t)0xF248, (q15_t)0x80BC, (q15_t)0xF27A, (q15_t)0x80B7,
+ (q15_t)0xF2AC, (q15_t)0x80B2, (q15_t)0xF2DE, (q15_t)0x80AC,
+ (q15_t)0xF310, (q15_t)0x80A7, (q15_t)0xF342, (q15_t)0x80A2,
+ (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF3A6, (q15_t)0x8098,
+ (q15_t)0xF3D8, (q15_t)0x8094, (q15_t)0xF40A, (q15_t)0x808F,
+ (q15_t)0xF43C, (q15_t)0x808A, (q15_t)0xF46E, (q15_t)0x8086,
+ (q15_t)0xF4A0, (q15_t)0x8081, (q15_t)0xF4D2, (q15_t)0x807D,
+ (q15_t)0xF504, (q15_t)0x8078, (q15_t)0xF536, (q15_t)0x8074,
+ (q15_t)0xF568, (q15_t)0x8070, (q15_t)0xF59A, (q15_t)0x806C,
+ (q15_t)0xF5CC, (q15_t)0x8068, (q15_t)0xF5FF, (q15_t)0x8064,
+ (q15_t)0xF631, (q15_t)0x8060, (q15_t)0xF663, (q15_t)0x805C,
+ (q15_t)0xF695, (q15_t)0x8058, (q15_t)0xF6C7, (q15_t)0x8055,
+ (q15_t)0xF6F9, (q15_t)0x8051, (q15_t)0xF72B, (q15_t)0x804E,
+ (q15_t)0xF75D, (q15_t)0x804A, (q15_t)0xF790, (q15_t)0x8047,
+ (q15_t)0xF7C2, (q15_t)0x8043, (q15_t)0xF7F4, (q15_t)0x8040,
+ (q15_t)0xF826, (q15_t)0x803D, (q15_t)0xF858, (q15_t)0x803A,
+ (q15_t)0xF88A, (q15_t)0x8037, (q15_t)0xF8BD, (q15_t)0x8034,
+ (q15_t)0xF8EF, (q15_t)0x8031, (q15_t)0xF921, (q15_t)0x802F,
+ (q15_t)0xF953, (q15_t)0x802C, (q15_t)0xF985, (q15_t)0x8029,
+ (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xF9EA, (q15_t)0x8025,
+ (q15_t)0xFA1C, (q15_t)0x8022, (q15_t)0xFA4E, (q15_t)0x8020,
+ (q15_t)0xFA80, (q15_t)0x801E, (q15_t)0xFAB3, (q15_t)0x801C,
+ (q15_t)0xFAE5, (q15_t)0x801A, (q15_t)0xFB17, (q15_t)0x8018,
+ (q15_t)0xFB49, (q15_t)0x8016, (q15_t)0xFB7C, (q15_t)0x8014,
+ (q15_t)0xFBAE, (q15_t)0x8012, (q15_t)0xFBE0, (q15_t)0x8011,
+ (q15_t)0xFC12, (q15_t)0x800F, (q15_t)0xFC45, (q15_t)0x800D,
+ (q15_t)0xFC77, (q15_t)0x800C, (q15_t)0xFCA9, (q15_t)0x800B,
+ (q15_t)0xFCDB, (q15_t)0x8009, (q15_t)0xFD0E, (q15_t)0x8008,
+ (q15_t)0xFD40, (q15_t)0x8007, (q15_t)0xFD72, (q15_t)0x8006,
+ (q15_t)0xFDA4, (q15_t)0x8005, (q15_t)0xFDD7, (q15_t)0x8004,
+ (q15_t)0xFE09, (q15_t)0x8003, (q15_t)0xFE3B, (q15_t)0x8003,
+ (q15_t)0xFE6D, (q15_t)0x8002, (q15_t)0xFEA0, (q15_t)0x8001,
+ (q15_t)0xFED2, (q15_t)0x8001, (q15_t)0xFF04, (q15_t)0x8000,
+ (q15_t)0xFF36, (q15_t)0x8000, (q15_t)0xFF69, (q15_t)0x8000,
+ (q15_t)0xFF9B, (q15_t)0x8000, (q15_t)0xFFCD, (q15_t)0x8000
+};
+
+
+/**
+* @} end of CFFT_CIFFT group
+*/
+
+/*
+* @brief Q15 table for reciprocal
+*/
+const q15_t ALIGN4 armRecipTableQ15[64] = {
+ 0x7F03, 0x7D13, 0x7B31, 0x795E, 0x7798, 0x75E0,
+ 0x7434, 0x7294, 0x70FF, 0x6F76, 0x6DF6, 0x6C82,
+ 0x6B16, 0x69B5, 0x685C, 0x670C, 0x65C4, 0x6484,
+ 0x634C, 0x621C, 0x60F3, 0x5FD0, 0x5EB5, 0x5DA0,
+ 0x5C91, 0x5B88, 0x5A85, 0x5988, 0x5890, 0x579E,
+ 0x56B0, 0x55C8, 0x54E4, 0x5405, 0x532B, 0x5255,
+ 0x5183, 0x50B6, 0x4FEC, 0x4F26, 0x4E64, 0x4DA6,
+ 0x4CEC, 0x4C34, 0x4B81, 0x4AD0, 0x4A23, 0x4978,
+ 0x48D1, 0x482D, 0x478C, 0x46ED, 0x4651, 0x45B8,
+ 0x4521, 0x448D, 0x43FC, 0x436C, 0x42DF, 0x4255,
+ 0x41CC, 0x4146, 0x40C2, 0x4040
+};
+
+/*
+* @brief Q31 table for reciprocal
+*/
+const q31_t armRecipTableQ31[64] = {
+ 0x7F03F03F, 0x7D137420, 0x7B31E739, 0x795E9F94, 0x7798FD29, 0x75E06928,
+ 0x7434554D, 0x72943B4B, 0x70FF9C40, 0x6F760031, 0x6DF6F593, 0x6C8210E3,
+ 0x6B16EC3A, 0x69B526F6, 0x685C655F, 0x670C505D, 0x65C4952D, 0x6484E519,
+ 0x634CF53E, 0x621C7E4F, 0x60F33C61, 0x5FD0EEB3, 0x5EB55785, 0x5DA03BEB,
+ 0x5C9163A1, 0x5B8898E6, 0x5A85A85A, 0x598860DF, 0x58909373, 0x579E1318,
+ 0x56B0B4B8, 0x55C84F0B, 0x54E4BA80, 0x5405D124, 0x532B6E8F, 0x52556FD0,
+ 0x5183B35A, 0x50B618F3, 0x4FEC81A2, 0x4F26CFA2, 0x4E64E64E, 0x4DA6AA1D,
+ 0x4CEC008B, 0x4C34D010, 0x4B810016, 0x4AD078EF, 0x4A2323C4, 0x4978EA96,
+ 0x48D1B827, 0x482D77FE, 0x478C1657, 0x46ED801D, 0x4651A2E5, 0x45B86CE2,
+ 0x4521CCE1, 0x448DB244, 0x43FC0CFA, 0x436CCD78, 0x42DFE4B4, 0x42554426,
+ 0x41CCDDB6, 0x4146A3C6, 0x40C28923, 0x40408102
+};
+
+const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH] =
+{
+ /* 8x2, size 20 */
+ 8,64, 24,72, 16,64, 40,80, 32,64, 56,88, 48,72, 88,104, 72,96, 104,112
+};
+
+const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH] =
+{
+ /* 8x4, size 48 */
+ 8,64, 16,128, 24,192, 32,64, 40,72, 48,136, 56,200, 64,128, 72,80, 88,208,
+ 80,144, 96,192, 104,208, 112,152, 120,216, 136,192, 144,160, 168,208,
+ 152,224, 176,208, 184,232, 216,240, 200,224, 232,240
+};
+
+const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH] =
+{
+ /* radix 8, size 56 */
+ 8,64, 16,128, 24,192, 32,256, 40,320, 48,384, 56,448, 80,136, 88,200,
+ 96,264, 104,328, 112,392, 120,456, 152,208, 160,272, 168,336, 176,400,
+ 184,464, 224,280, 232,344, 240,408, 248,472, 296,352, 304,416, 312,480,
+ 368,424, 376,488, 440,496
+};
+
+const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH] =
+{
+ /* 8x2, size 208 */
+ 8,512, 16,64, 24,576, 32,128, 40,640, 48,192, 56,704, 64,256, 72,768,
+ 80,320, 88,832, 96,384, 104,896, 112,448, 120,960, 128,512, 136,520,
+ 144,768, 152,584, 160,520, 168,648, 176,200, 184,712, 192,264, 200,776,
+ 208,328, 216,840, 224,392, 232,904, 240,456, 248,968, 264,528, 272,320,
+ 280,592, 288,768, 296,656, 304,328, 312,720, 328,784, 344,848, 352,400,
+ 360,912, 368,464, 376,976, 384,576, 392,536, 400,832, 408,600, 416,584,
+ 424,664, 432,840, 440,728, 448,592, 456,792, 464,848, 472,856, 480,600,
+ 488,920, 496,856, 504,984, 520,544, 528,576, 536,608, 552,672, 560,608,
+ 568,736, 576,768, 584,800, 592,832, 600,864, 608,800, 616,928, 624,864,
+ 632,992, 648,672, 656,896, 664,928, 688,904, 696,744, 704,896, 712,808,
+ 720,912, 728,872, 736,928, 744,936, 752,920, 760,1000, 776,800, 784,832,
+ 792,864, 808,904, 816,864, 824,920, 840,864, 856,880, 872,944, 888,1008,
+ 904,928, 912,960, 920,992, 944,968, 952,1000, 968,992, 984,1008
+};
+
+const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH] =
+{
+ /* 8x4, size 440 */
+ 8,512, 16,1024, 24,1536, 32,64, 40,576, 48,1088, 56,1600, 64,128, 72,640,
+ 80,1152, 88,1664, 96,192, 104,704, 112,1216, 120,1728, 128,256, 136,768,
+ 144,1280, 152,1792, 160,320, 168,832, 176,1344, 184,1856, 192,384,
+ 200,896, 208,1408, 216,1920, 224,448, 232,960, 240,1472, 248,1984,
+ 256,512, 264,520, 272,1032, 280,1544, 288,640, 296,584, 304,1096, 312,1608,
+ 320,768, 328,648, 336,1160, 344,1672, 352,896, 360,712, 368,1224, 376,1736,
+ 384,520, 392,776, 400,1288, 408,1800, 416,648, 424,840, 432,1352, 440,1864,
+ 448,776, 456,904, 464,1416, 472,1928, 480,904, 488,968, 496,1480, 504,1992,
+ 520,528, 512,1024, 528,1040, 536,1552, 544,1152, 552,592, 560,1104,
+ 568,1616, 576,1280, 584,656, 592,1168, 600,1680, 608,1408, 616,720,
+ 624,1232, 632,1744, 640,1032, 648,784, 656,1296, 664,1808, 672,1160,
+ 680,848, 688,1360, 696,1872, 704,1288, 712,912, 720,1424, 728,1936,
+ 736,1416, 744,976, 752,1488, 760,2000, 768,1536, 776,1552, 784,1048,
+ 792,1560, 800,1664, 808,1680, 816,1112, 824,1624, 832,1792, 840,1808,
+ 848,1176, 856,1688, 864,1920, 872,1936, 880,1240, 888,1752, 896,1544,
+ 904,1560, 912,1304, 920,1816, 928,1672, 936,1688, 944,1368, 952,1880,
+ 960,1800, 968,1816, 976,1432, 984,1944, 992,1928, 1000,1944, 1008,1496,
+ 1016,2008, 1032,1152, 1040,1056, 1048,1568, 1064,1408, 1072,1120,
+ 1080,1632, 1088,1536, 1096,1160, 1104,1184, 1112,1696, 1120,1552,
+ 1128,1416, 1136,1248, 1144,1760, 1160,1664, 1168,1312, 1176,1824,
+ 1184,1544, 1192,1920, 1200,1376, 1208,1888, 1216,1568, 1224,1672,
+ 1232,1440, 1240,1952, 1248,1560, 1256,1928, 1264,1504, 1272,2016,
+ 1288,1312, 1296,1408, 1304,1576, 1320,1424, 1328,1416, 1336,1640,
+ 1344,1792, 1352,1824, 1360,1920, 1368,1704, 1376,1800, 1384,1432,
+ 1392,1928, 1400,1768, 1416,1680, 1432,1832, 1440,1576, 1448,1936,
+ 1456,1832, 1464,1896, 1472,1808, 1480,1688, 1488,1936, 1496,1960,
+ 1504,1816, 1512,1944, 1520,1944, 1528,2024, 1560,1584, 1592,1648,
+ 1600,1792, 1608,1920, 1616,1800, 1624,1712, 1632,1808, 1640,1936,
+ 1648,1816, 1656,1776, 1672,1696, 1688,1840, 1704,1952, 1712,1928,
+ 1720,1904, 1728,1824, 1736,1952, 1744,1832, 1752,1968, 1760,1840,
+ 1768,1960, 1776,1944, 1784,2032, 1864,1872, 1848,1944, 1872,1888,
+ 1880,1904, 1888,1984, 1896,2000, 1912,2032, 1904,2016, 1976,2032,
+ 1960,1968, 2008,2032, 1992,2016, 2024,2032
+};
+
+const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH] =
+{
+ /* radix 8, size 448 */
+ 8,512, 16,1024, 24,1536, 32,2048, 40,2560, 48,3072, 56,3584, 72,576,
+ 80,1088, 88,1600, 96,2112, 104,2624, 112,3136, 120,3648, 136,640, 144,1152,
+ 152,1664, 160,2176, 168,2688, 176,3200, 184,3712, 200,704, 208,1216,
+ 216,1728, 224,2240, 232,2752, 240,3264, 248,3776, 264,768, 272,1280,
+ 280,1792, 288,2304, 296,2816, 304,3328, 312,3840, 328,832, 336,1344,
+ 344,1856, 352,2368, 360,2880, 368,3392, 376,3904, 392,896, 400,1408,
+ 408,1920, 416,2432, 424,2944, 432,3456, 440,3968, 456,960, 464,1472,
+ 472,1984, 480,2496, 488,3008, 496,3520, 504,4032, 528,1032, 536,1544,
+ 544,2056, 552,2568, 560,3080, 568,3592, 592,1096, 600,1608, 608,2120,
+ 616,2632, 624,3144, 632,3656, 656,1160, 664,1672, 672,2184, 680,2696,
+ 688,3208, 696,3720, 720,1224, 728,1736, 736,2248, 744,2760, 752,3272,
+ 760,3784, 784,1288, 792,1800, 800,2312, 808,2824, 816,3336, 824,3848,
+ 848,1352, 856,1864, 864,2376, 872,2888, 880,3400, 888,3912, 912,1416,
+ 920,1928, 928,2440, 936,2952, 944,3464, 952,3976, 976,1480, 984,1992,
+ 992,2504, 1000,3016, 1008,3528, 1016,4040, 1048,1552, 1056,2064, 1064,2576,
+ 1072,3088, 1080,3600, 1112,1616, 1120,2128, 1128,2640, 1136,3152,
+ 1144,3664, 1176,1680, 1184,2192, 1192,2704, 1200,3216, 1208,3728,
+ 1240,1744, 1248,2256, 1256,2768, 1264,3280, 1272,3792, 1304,1808,
+ 1312,2320, 1320,2832, 1328,3344, 1336,3856, 1368,1872, 1376,2384,
+ 1384,2896, 1392,3408, 1400,3920, 1432,1936, 1440,2448, 1448,2960,
+ 1456,3472, 1464,3984, 1496,2000, 1504,2512, 1512,3024, 1520,3536,
+ 1528,4048, 1568,2072, 1576,2584, 1584,3096, 1592,3608, 1632,2136,
+ 1640,2648, 1648,3160, 1656,3672, 1696,2200, 1704,2712, 1712,3224,
+ 1720,3736, 1760,2264, 1768,2776, 1776,3288, 1784,3800, 1824,2328,
+ 1832,2840, 1840,3352, 1848,3864, 1888,2392, 1896,2904, 1904,3416,
+ 1912,3928, 1952,2456, 1960,2968, 1968,3480, 1976,3992, 2016,2520,
+ 2024,3032, 2032,3544, 2040,4056, 2088,2592, 2096,3104, 2104,3616,
+ 2152,2656, 2160,3168, 2168,3680, 2216,2720, 2224,3232, 2232,3744,
+ 2280,2784, 2288,3296, 2296,3808, 2344,2848, 2352,3360, 2360,3872,
+ 2408,2912, 2416,3424, 2424,3936, 2472,2976, 2480,3488, 2488,4000,
+ 2536,3040, 2544,3552, 2552,4064, 2608,3112, 2616,3624, 2672,3176,
+ 2680,3688, 2736,3240, 2744,3752, 2800,3304, 2808,3816, 2864,3368,
+ 2872,3880, 2928,3432, 2936,3944, 2992,3496, 3000,4008, 3056,3560,
+ 3064,4072, 3128,3632, 3192,3696, 3256,3760, 3320,3824, 3384,3888,
+ 3448,3952, 3512,4016, 3576,4080
+};
+
+const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH] =
+{
+ /* 8x2, size 1800 */
+ 8,4096, 16,512, 24,4608, 32,1024, 40,5120, 48,1536, 56,5632, 64,2048,
+ 72,6144, 80,2560, 88,6656, 96,3072, 104,7168, 112,3584, 120,7680, 128,2048,
+ 136,4160, 144,576, 152,4672, 160,1088, 168,5184, 176,1600, 184,5696,
+ 192,2112, 200,6208, 208,2624, 216,6720, 224,3136, 232,7232, 240,3648,
+ 248,7744, 256,2048, 264,4224, 272,640, 280,4736, 288,1152, 296,5248,
+ 304,1664, 312,5760, 320,2176, 328,6272, 336,2688, 344,6784, 352,3200,
+ 360,7296, 368,3712, 376,7808, 384,2112, 392,4288, 400,704, 408,4800,
+ 416,1216, 424,5312, 432,1728, 440,5824, 448,2240, 456,6336, 464,2752,
+ 472,6848, 480,3264, 488,7360, 496,3776, 504,7872, 512,2048, 520,4352,
+ 528,768, 536,4864, 544,1280, 552,5376, 560,1792, 568,5888, 576,2304,
+ 584,6400, 592,2816, 600,6912, 608,3328, 616,7424, 624,3840, 632,7936,
+ 640,2176, 648,4416, 656,832, 664,4928, 672,1344, 680,5440, 688,1856,
+ 696,5952, 704,2368, 712,6464, 720,2880, 728,6976, 736,3392, 744,7488,
+ 752,3904, 760,8000, 768,2112, 776,4480, 784,896, 792,4992, 800,1408,
+ 808,5504, 816,1920, 824,6016, 832,2432, 840,6528, 848,2944, 856,7040,
+ 864,3456, 872,7552, 880,3968, 888,8064, 896,2240, 904,4544, 912,960,
+ 920,5056, 928,1472, 936,5568, 944,1984, 952,6080, 960,2496, 968,6592,
+ 976,3008, 984,7104, 992,3520, 1000,7616, 1008,4032, 1016,8128, 1024,4096,
+ 1032,4104, 1040,4352, 1048,4616, 1056,4104, 1064,5128, 1072,1544,
+ 1080,5640, 1088,2056, 1096,6152, 1104,2568, 1112,6664, 1120,3080,
+ 1128,7176, 1136,3592, 1144,7688, 1152,6144, 1160,4168, 1168,6400,
+ 1176,4680, 1184,6152, 1192,5192, 1200,1608, 1208,5704, 1216,2120,
+ 1224,6216, 1232,2632, 1240,6728, 1248,3144, 1256,7240, 1264,3656,
+ 1272,7752, 1280,4160, 1288,4232, 1296,4416, 1304,4744, 1312,4168,
+ 1320,5256, 1328,1672, 1336,5768, 1344,2184, 1352,6280, 1360,2696,
+ 1368,6792, 1376,3208, 1384,7304, 1392,3720, 1400,7816, 1408,6208,
+ 1416,4296, 1424,6464, 1432,4808, 1440,6216, 1448,5320, 1456,1736,
+ 1464,5832, 1472,2248, 1480,6344, 1488,2760, 1496,6856, 1504,3272,
+ 1512,7368, 1520,3784, 1528,7880, 1536,4224, 1544,4360, 1552,4480,
+ 1560,4872, 1568,4232, 1576,5384, 1584,1800, 1592,5896, 1600,2312,
+ 1608,6408, 1616,2824, 1624,6920, 1632,3336, 1640,7432, 1648,3848,
+ 1656,7944, 1664,6272, 1672,4424, 1680,6528, 1688,4936, 1696,6280,
+ 1704,5448, 1712,1864, 1720,5960, 1728,2376, 1736,6472, 1744,2888,
+ 1752,6984, 1760,3400, 1768,7496, 1776,3912, 1784,8008, 1792,4288,
+ 1800,4488, 1808,4544, 1816,5000, 1824,4296, 1832,5512, 1840,1928,
+ 1848,6024, 1856,2440, 1864,6536, 1872,2952, 1880,7048, 1888,3464,
+ 1896,7560, 1904,3976, 1912,8072, 1920,6336, 1928,4552, 1936,6592,
+ 1944,5064, 1952,6344, 1960,5576, 1968,1992, 1976,6088, 1984,2504,
+ 1992,6600, 2000,3016, 2008,7112, 2016,3528, 2024,7624, 2032,4040,
+ 2040,8136, 2056,4112, 2064,2112, 2072,4624, 2080,4352, 2088,5136,
+ 2096,4480, 2104,5648, 2120,6160, 2128,2576, 2136,6672, 2144,3088,
+ 2152,7184, 2160,3600, 2168,7696, 2176,2560, 2184,4176, 2192,2816,
+ 2200,4688, 2208,2568, 2216,5200, 2224,2824, 2232,5712, 2240,2576,
+ 2248,6224, 2256,2640, 2264,6736, 2272,3152, 2280,7248, 2288,3664,
+ 2296,7760, 2312,4240, 2320,2432, 2328,4752, 2336,6400, 2344,5264,
+ 2352,6528, 2360,5776, 2368,2816, 2376,6288, 2384,2704, 2392,6800,
+ 2400,3216, 2408,7312, 2416,3728, 2424,7824, 2432,2624, 2440,4304,
+ 2448,2880, 2456,4816, 2464,2632, 2472,5328, 2480,2888, 2488,5840,
+ 2496,2640, 2504,6352, 2512,2768, 2520,6864, 2528,3280, 2536,7376,
+ 2544,3792, 2552,7888, 2568,4368, 2584,4880, 2592,4416, 2600,5392,
+ 2608,4544, 2616,5904, 2632,6416, 2640,2832, 2648,6928, 2656,3344,
+ 2664,7440, 2672,3856, 2680,7952, 2696,4432, 2704,2944, 2712,4944,
+ 2720,4432, 2728,5456, 2736,2952, 2744,5968, 2752,2944, 2760,6480,
+ 2768,2896, 2776,6992, 2784,3408, 2792,7504, 2800,3920, 2808,8016,
+ 2824,4496, 2840,5008, 2848,6464, 2856,5520, 2864,6592, 2872,6032,
+ 2888,6544, 2896,2960, 2904,7056, 2912,3472, 2920,7568, 2928,3984,
+ 2936,8080, 2952,4560, 2960,3008, 2968,5072, 2976,6480, 2984,5584,
+ 2992,3016, 3000,6096, 3016,6608, 3032,7120, 3040,3536, 3048,7632,
+ 3056,4048, 3064,8144, 3072,4608, 3080,4120, 3088,4864, 3096,4632,
+ 3104,4616, 3112,5144, 3120,4872, 3128,5656, 3136,4624, 3144,6168,
+ 3152,4880, 3160,6680, 3168,4632, 3176,7192, 3184,3608, 3192,7704,
+ 3200,6656, 3208,4184, 3216,6912, 3224,4696, 3232,6664, 3240,5208,
+ 3248,6920, 3256,5720, 3264,6672, 3272,6232, 3280,6928, 3288,6744,
+ 3296,6680, 3304,7256, 3312,3672, 3320,7768, 3328,4672, 3336,4248,
+ 3344,4928, 3352,4760, 3360,4680, 3368,5272, 3376,4936, 3384,5784,
+ 3392,4688, 3400,6296, 3408,4944, 3416,6808, 3424,4696, 3432,7320,
+ 3440,3736, 3448,7832, 3456,6720, 3464,4312, 3472,6976, 3480,4824,
+ 3488,6728, 3496,5336, 3504,6984, 3512,5848, 3520,6736, 3528,6360,
+ 3536,6992, 3544,6872, 3552,6744, 3560,7384, 3568,3800, 3576,7896,
+ 3584,4736, 3592,4376, 3600,4992, 3608,4888, 3616,4744, 3624,5400,
+ 3632,5000, 3640,5912, 3648,4752, 3656,6424, 3664,5008, 3672,6936,
+ 3680,4760, 3688,7448, 3696,3864, 3704,7960, 3712,6784, 3720,4440,
+ 3728,7040, 3736,4952, 3744,6792, 3752,5464, 3760,7048, 3768,5976,
+ 3776,6800, 3784,6488, 3792,7056, 3800,7000, 3808,6808, 3816,7512,
+ 3824,3928, 3832,8024, 3840,4800, 3848,4504, 3856,5056, 3864,5016,
+ 3872,4808, 3880,5528, 3888,5064, 3896,6040, 3904,4816, 3912,6552,
+ 3920,5072, 3928,7064, 3936,4824, 3944,7576, 3952,3992, 3960,8088,
+ 3968,6848, 3976,4568, 3984,7104, 3992,5080, 4000,6856, 4008,5592,
+ 4016,7112, 4024,6104, 4032,6864, 4040,6616, 4048,7120, 4056,7128,
+ 4064,6872, 4072,7640, 4080,7128, 4088,8152, 4104,4128, 4112,4160,
+ 4120,4640, 4136,5152, 4144,4232, 4152,5664, 4160,4352, 4168,6176,
+ 4176,4416, 4184,6688, 4192,4616, 4200,7200, 4208,4744, 4216,7712,
+ 4224,4608, 4232,4616, 4240,4672, 4248,4704, 4256,4640, 4264,5216,
+ 4272,4704, 4280,5728, 4288,4864, 4296,6240, 4304,4928, 4312,6752,
+ 4320,4632, 4328,7264, 4336,4760, 4344,7776, 4360,4640, 4368,4416,
+ 4376,4768, 4384,6152, 4392,5280, 4400,6280, 4408,5792, 4424,6304,
+ 4440,6816, 4448,6664, 4456,7328, 4464,6792, 4472,7840, 4480,4624,
+ 4488,4632, 4496,4688, 4504,4832, 4512,6168, 4520,5344, 4528,6296,
+ 4536,5856, 4544,4880, 4552,6368, 4560,4944, 4568,6880, 4576,6680,
+ 4584,7392, 4592,6808, 4600,7904, 4608,6144, 4616,6152, 4624,6208,
+ 4632,4896, 4640,6176, 4648,5408, 4656,6240, 4664,5920, 4672,6400,
+ 4680,6432, 4688,6464, 4696,6944, 4704,6432, 4712,7456, 4720,4808,
+ 4728,7968, 4736,6656, 4744,6664, 4752,6720, 4760,4960, 4768,6688,
+ 4776,5472, 4784,6752, 4792,5984, 4800,6912, 4808,6496, 4816,6976,
+ 4824,7008, 4832,6944, 4840,7520, 4848,7008, 4856,8032, 4864,6160,
+ 4872,6168, 4880,6224, 4888,5024, 4896,6216, 4904,5536, 4912,6344,
+ 4920,6048, 4928,6416, 4936,6560, 4944,6480, 4952,7072, 4960,6728,
+ 4968,7584, 4976,6856, 4984,8096, 4992,6672, 5000,6680, 5008,6736,
+ 5016,5088, 5024,6232, 5032,5600, 5040,6360, 5048,6112, 5056,6928,
+ 5064,6624, 5072,6992, 5080,7136, 5088,6744, 5096,7648, 5104,6872,
+ 5112,8160, 5128,5152, 5136,5376, 5144,5408, 5168,5384, 5176,5672,
+ 5184,5376, 5192,6184, 5200,5392, 5208,6696, 5216,5408, 5224,7208,
+ 5232,5400, 5240,7720, 5248,7168, 5256,7200, 5264,7424, 5272,7456,
+ 5280,7176, 5288,7208, 5296,7432, 5304,5736, 5312,7184, 5320,6248,
+ 5328,7440, 5336,6760, 5344,7192, 5352,7272, 5360,7448, 5368,7784,
+ 5384,5408, 5392,5440, 5400,5472, 5408,6184, 5416,7208, 5424,5448,
+ 5432,5800, 5448,6312, 5464,6824, 5472,6696, 5480,7336, 5488,6824,
+ 5496,7848, 5504,7232, 5512,7264, 5520,7488, 5528,7520, 5536,7240,
+ 5544,7272, 5552,7496, 5560,5864, 5568,7248, 5576,6376, 5584,7504,
+ 5592,6888, 5600,7256, 5608,7400, 5616,7512, 5624,7912, 5632,7168,
+ 5640,7176, 5648,7232, 5656,7240, 5664,7200, 5672,7208, 5680,7264,
+ 5688,5928, 5696,7424, 5704,6440, 5712,7488, 5720,6952, 5728,7456,
+ 5736,7464, 5744,7520, 5752,7976, 5760,7296, 5768,7328, 5776,7552,
+ 5784,7584, 5792,7304, 5800,7336, 5808,7560, 5816,5992, 5824,7312,
+ 5832,6504, 5840,7568, 5848,7016, 5856,7320, 5864,7528, 5872,7576,
+ 5880,8040, 5888,7184, 5896,7192, 5904,7248, 5912,7256, 5920,6248,
+ 5928,7272, 5936,6376, 5944,6056, 5952,7440, 5960,6568, 5968,7504,
+ 5976,7080, 5984,6760, 5992,7592, 6000,6888, 6008,8104, 6016,7360,
+ 6024,7392, 6032,7616, 6040,7648, 6048,7368, 6056,7400, 6064,7624,
+ 6072,6120, 6080,7376, 6088,6632, 6096,7632, 6104,7144, 6112,7384,
+ 6120,7656, 6128,7640, 6136,8168, 6168,6240, 6192,6216, 6200,7264,
+ 6232,6704, 6248,7216, 6256,6680, 6264,7728, 6272,6656, 6280,6664,
+ 6288,6912, 6296,6496, 6304,6688, 6312,6696, 6320,6944, 6328,7520,
+ 6336,6672, 6344,6680, 6352,6928, 6360,6768, 6368,6704, 6376,7280,
+ 6384,6744, 6392,7792, 6408,6432, 6424,6752, 6440,7432, 6448,6536,
+ 6456,7560, 6472,6944, 6488,6832, 6496,6920, 6504,7344, 6512,7048,
+ 6520,7856, 6528,6720, 6536,6728, 6544,6976, 6552,7008, 6560,6752,
+ 6568,7448, 6576,7008, 6584,7576, 6592,6736, 6600,6744, 6608,6992,
+ 6616,6896, 6624,6936, 6632,7408, 6640,7064, 6648,7920, 6712,7280,
+ 6744,6960, 6760,7472, 6768,6936, 6776,7984, 6800,6848, 6808,6856,
+ 6832,6880, 6840,6888, 6848,7040, 6856,7048, 6864,7104, 6872,7024,
+ 6880,7072, 6888,7536, 6896,7136, 6904,8048, 6952,7496, 6968,7624,
+ 6984,7008, 7000,7088, 7016,7600, 7024,7112, 7032,8112, 7056,7104,
+ 7064,7112, 7080,7512, 7088,7136, 7096,7640, 7128,7152, 7144,7664,
+ 7160,8176, 7176,7200, 7192,7216, 7224,7272, 7240,7264, 7256,7280,
+ 7288,7736, 7296,7680, 7304,7712, 7312,7936, 7320,7968, 7328,7688,
+ 7336,7720, 7344,7944, 7352,7976, 7360,7696, 7368,7728, 7376,7952,
+ 7384,7984, 7392,7704, 7400,7736, 7408,7960, 7416,7800, 7432,7456,
+ 7448,7472, 7480,7592, 7496,7520, 7512,7536, 7528,7976, 7544,7864,
+ 7552,7744, 7560,7776, 7568,8000, 7576,8032, 7584,7752, 7592,7784,
+ 7600,8008, 7608,8040, 7616,7760, 7624,7792, 7632,8016, 7640,8048,
+ 7648,7768, 7656,7800, 7664,8024, 7672,7928, 7688,7712, 7704,7728,
+ 7752,7776, 7768,7792, 7800,7992, 7816,7840, 7824,8064, 7832,8096,
+ 7856,8072, 7864,8104, 7872,8064, 7880,8072, 7888,8080, 7896,8112,
+ 7904,8096, 7912,8104, 7920,8088, 7928,8056, 7944,7968, 7960,7984,
+ 8008,8032, 8024,8048, 8056,8120, 8072,8096, 8080,8128, 8088,8160,
+ 8112,8136, 8120,8168, 8136,8160, 8152,8176
+};
+
+const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH] =
+{
+ /* 8x2, size 3808 */
+ 8,4096, 16,8192, 24,12288, 32,512, 40,4608, 48,8704, 56,12800, 64,1024,
+ 72,5120, 80,9216, 88,13312, 96,1536, 104,5632, 112,9728, 120,13824,
+ 128,2048, 136,6144, 144,10240, 152,14336, 160,2560, 168,6656, 176,10752,
+ 184,14848, 192,3072, 200,7168, 208,11264, 216,15360, 224,3584, 232,7680,
+ 240,11776, 248,15872, 256,1024, 264,4160, 272,8256, 280,12352, 288,576,
+ 296,4672, 304,8768, 312,12864, 320,1088, 328,5184, 336,9280, 344,13376,
+ 352,1600, 360,5696, 368,9792, 376,13888, 384,2112, 392,6208, 400,10304,
+ 408,14400, 416,2624, 424,6720, 432,10816, 440,14912, 448,3136, 456,7232,
+ 464,11328, 472,15424, 480,3648, 488,7744, 496,11840, 504,15936, 512,2048,
+ 520,4224, 528,8320, 536,12416, 544,640, 552,4736, 560,8832, 568,12928,
+ 576,1152, 584,5248, 592,9344, 600,13440, 608,1664, 616,5760, 624,9856,
+ 632,13952, 640,2176, 648,6272, 656,10368, 664,14464, 672,2688, 680,6784,
+ 688,10880, 696,14976, 704,3200, 712,7296, 720,11392, 728,15488, 736,3712,
+ 744,7808, 752,11904, 760,16000, 768,3072, 776,4288, 784,8384, 792,12480,
+ 800,3200, 808,4800, 816,8896, 824,12992, 832,1216, 840,5312, 848,9408,
+ 856,13504, 864,1728, 872,5824, 880,9920, 888,14016, 896,2240, 904,6336,
+ 912,10432, 920,14528, 928,2752, 936,6848, 944,10944, 952,15040, 960,3264,
+ 968,7360, 976,11456, 984,15552, 992,3776, 1000,7872, 1008,11968, 1016,16064,
+ 1032,4352, 1040,8448, 1048,12544, 1056,3072, 1064,4864, 1072,8960,
+ 1080,13056, 1088,1280, 1096,5376, 1104,9472, 1112,13568, 1120,1792,
+ 1128,5888, 1136,9984, 1144,14080, 1152,2304, 1160,6400, 1168,10496,
+ 1176,14592, 1184,2816, 1192,6912, 1200,11008, 1208,15104, 1216,3328,
+ 1224,7424, 1232,11520, 1240,15616, 1248,3840, 1256,7936, 1264,12032,
+ 1272,16128, 1288,4416, 1296,8512, 1304,12608, 1312,3328, 1320,4928,
+ 1328,9024, 1336,13120, 1352,5440, 1360,9536, 1368,13632, 1376,1856,
+ 1384,5952, 1392,10048, 1400,14144, 1408,2368, 1416,6464, 1424,10560,
+ 1432,14656, 1440,2880, 1448,6976, 1456,11072, 1464,15168, 1472,3392,
+ 1480,7488, 1488,11584, 1496,15680, 1504,3904, 1512,8000, 1520,12096,
+ 1528,16192, 1536,2112, 1544,4480, 1552,8576, 1560,12672, 1568,2240,
+ 1576,4992, 1584,9088, 1592,13184, 1600,2368, 1608,5504, 1616,9600,
+ 1624,13696, 1632,1920, 1640,6016, 1648,10112, 1656,14208, 1664,2432,
+ 1672,6528, 1680,10624, 1688,14720, 1696,2944, 1704,7040, 1712,11136,
+ 1720,15232, 1728,3456, 1736,7552, 1744,11648, 1752,15744, 1760,3968,
+ 1768,8064, 1776,12160, 1784,16256, 1792,3136, 1800,4544, 1808,8640,
+ 1816,12736, 1824,3264, 1832,5056, 1840,9152, 1848,13248, 1856,3392,
+ 1864,5568, 1872,9664, 1880,13760, 1888,1984, 1896,6080, 1904,10176,
+ 1912,14272, 1920,2496, 1928,6592, 1936,10688, 1944,14784, 1952,3008,
+ 1960,7104, 1968,11200, 1976,15296, 1984,3520, 1992,7616, 2000,11712,
+ 2008,15808, 2016,4032, 2024,8128, 2032,12224, 2040,16320, 2048,4096,
+ 2056,4104, 2064,8200, 2072,12296, 2080,4224, 2088,4616, 2096,8712,
+ 2104,12808, 2112,4352, 2120,5128, 2128,9224, 2136,13320, 2144,4480,
+ 2152,5640, 2160,9736, 2168,13832, 2176,4104, 2184,6152, 2192,10248,
+ 2200,14344, 2208,2568, 2216,6664, 2224,10760, 2232,14856, 2240,3080,
+ 2248,7176, 2256,11272, 2264,15368, 2272,3592, 2280,7688, 2288,11784,
+ 2296,15880, 2304,5120, 2312,4168, 2320,8264, 2328,12360, 2336,5248,
+ 2344,4680, 2352,8776, 2360,12872, 2368,5376, 2376,5192, 2384,9288,
+ 2392,13384, 2400,5504, 2408,5704, 2416,9800, 2424,13896, 2432,5128,
+ 2440,6216, 2448,10312, 2456,14408, 2464,2632, 2472,6728, 2480,10824,
+ 2488,14920, 2496,3144, 2504,7240, 2512,11336, 2520,15432, 2528,3656,
+ 2536,7752, 2544,11848, 2552,15944, 2560,6144, 2568,4232, 2576,8328,
+ 2584,12424, 2592,6272, 2600,4744, 2608,8840, 2616,12936, 2624,6400,
+ 2632,5256, 2640,9352, 2648,13448, 2656,6528, 2664,5768, 2672,9864,
+ 2680,13960, 2688,6152, 2696,6280, 2704,10376, 2712,14472, 2720,6280,
+ 2728,6792, 2736,10888, 2744,14984, 2752,3208, 2760,7304, 2768,11400,
+ 2776,15496, 2784,3720, 2792,7816, 2800,11912, 2808,16008, 2816,7168,
+ 2824,4296, 2832,8392, 2840,12488, 2848,7296, 2856,4808, 2864,8904,
+ 2872,13000, 2880,7424, 2888,5320, 2896,9416, 2904,13512, 2912,7552,
+ 2920,5832, 2928,9928, 2936,14024, 2944,7176, 2952,6344, 2960,10440,
+ 2968,14536, 2976,7304, 2984,6856, 2992,10952, 3000,15048, 3008,3272,
+ 3016,7368, 3024,11464, 3032,15560, 3040,3784, 3048,7880, 3056,11976,
+ 3064,16072, 3072,4160, 3080,4360, 3088,8456, 3096,12552, 3104,4288,
+ 3112,4872, 3120,8968, 3128,13064, 3136,4416, 3144,5384, 3152,9480,
+ 3160,13576, 3168,4544, 3176,5896, 3184,9992, 3192,14088, 3200,4168,
+ 3208,6408, 3216,10504, 3224,14600, 3232,4296, 3240,6920, 3248,11016,
+ 3256,15112, 3264,3336, 3272,7432, 3280,11528, 3288,15624, 3296,3848,
+ 3304,7944, 3312,12040, 3320,16136, 3328,5184, 3336,4424, 3344,8520,
+ 3352,12616, 3360,5312, 3368,4936, 3376,9032, 3384,13128, 3392,5440,
+ 3400,5448, 3408,9544, 3416,13640, 3424,5568, 3432,5960, 3440,10056,
+ 3448,14152, 3456,5192, 3464,6472, 3472,10568, 3480,14664, 3488,5320,
+ 3496,6984, 3504,11080, 3512,15176, 3520,5448, 3528,7496, 3536,11592,
+ 3544,15688, 3552,3912, 3560,8008, 3568,12104, 3576,16200, 3584,6208,
+ 3592,4488, 3600,8584, 3608,12680, 3616,6336, 3624,5000, 3632,9096,
+ 3640,13192, 3648,6464, 3656,5512, 3664,9608, 3672,13704, 3680,6592,
+ 3688,6024, 3696,10120, 3704,14216, 3712,6216, 3720,6536, 3728,10632,
+ 3736,14728, 3744,6344, 3752,7048, 3760,11144, 3768,15240, 3776,6472,
+ 3784,7560, 3792,11656, 3800,15752, 3808,3976, 3816,8072, 3824,12168,
+ 3832,16264, 3840,7232, 3848,4552, 3856,8648, 3864,12744, 3872,7360,
+ 3880,5064, 3888,9160, 3896,13256, 3904,7488, 3912,5576, 3920,9672,
+ 3928,13768, 3936,7616, 3944,6088, 3952,10184, 3960,14280, 3968,7240,
+ 3976,6600, 3984,10696, 3992,14792, 4000,7368, 4008,7112, 4016,11208,
+ 4024,15304, 4032,7496, 4040,7624, 4048,11720, 4056,15816, 4064,7624,
+ 4072,8136, 4080,12232, 4088,16328, 4096,8192, 4104,4112, 4112,8208,
+ 4120,12304, 4128,8320, 4136,4624, 4144,8720, 4152,12816, 4160,8448,
+ 4168,5136, 4176,9232, 4184,13328, 4192,8576, 4200,5648, 4208,9744,
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+ 14664,15624, 14672,15632, 14680,15640, 14688,15648, 14696,15656,
+ 14704,15664, 14712,15576, 14720,15488, 14728,15496, 14736,15504,
+ 14744,15512, 14752,15520, 14760,14768, 14776,14968, 14768,15528,
+ 14784,15744, 14792,15752, 14800,15760, 14808,15480, 14816,15776,
+ 14824,14832, 14840,15992, 14832,15784, 14856,14864, 14864,14880,
+ 14872,14896, 14880,14976, 14888,14992, 14896,15008, 14904,15024,
+ 14912,15104, 14920,15120, 14928,15136, 14936,15152, 14944,15232,
+ 14952,15248, 14960,15264, 14968,15280, 14984,15008, 15000,15024,
+ 15016,15024, 15040,15112, 15048,15128, 15056,15144, 15064,15544,
+ 15072,15240, 15080,15256, 15088,15272, 15096,16056, 15104,15872,
+ 15112,15888, 15120,15904, 15128,15920, 15136,16000, 15144,16016,
+ 15152,16032, 15160,16048, 15168,16128, 15176,16144, 15184,16160,
+ 15192,16176, 15200,16256, 15208,16272, 15216,16288, 15224,16304,
+ 15232,15880, 15240,15896, 15248,15912, 15256,15928, 15264,16008,
+ 15272,16024, 15280,16040, 15288,16056, 15296,16136, 15304,16152,
+ 15312,16168, 15320,15608, 15328,16264, 15336,16280, 15344,16296,
+ 15352,16120, 15416,15512, 15424,15616, 15432,15624, 15440,15632,
+ 15448,15640, 15456,15648, 15464,15656, 15472,15664, 15480,15768,
+ 15528,15536, 15544,16048, 15552,15744, 15560,15752, 15568,15760,
+ 15576,15672, 15584,15776, 15592,15600, 15600,15784, 15608,16184,
+ 15672,15768, 15736,15832, 15784,15792, 15800,16304, 15848,15856,
+ 15880,16000, 15864,16248, 15888,16000, 15896,16008, 15904,16000,
+ 15912,16016, 15920,16008, 15928,16024, 15936,16128, 15944,16160,
+ 15952,16256, 15960,16288, 15968,16136, 15976,16168, 15984,16264,
+ 15992,16296, 16008,16032, 16024,16040, 16064,16144, 16040,16048,
+ 16072,16176, 16080,16272, 16088,16304, 16096,16152, 16104,16184,
+ 16112,16280, 16136,16256, 16120,16312, 16144,16256, 16152,16264,
+ 16160,16256, 16168,16272, 16176,16264, 16184,16280, 16200,16208,
+ 16208,16224, 16216,16240, 16224,16320, 16232,16336, 16240,16352,
+ 16248,16368, 16264,16288, 16280,16296, 16296,16304, 16344,16368,
+ 16328,16352, 16360,16368
+};
+
+const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH] =
+{
+ /* radix 8, size 4032 */
+ 8,4096, 16,8192, 24,12288, 32,16384, 40,20480, 48,24576, 56,28672, 64,512,
+ 72,4608, 80,8704, 88,12800, 96,16896, 104,20992, 112,25088, 120,29184,
+ 128,1024, 136,5120, 144,9216, 152,13312, 160,17408, 168,21504, 176,25600,
+ 184,29696, 192,1536, 200,5632, 208,9728, 216,13824, 224,17920, 232,22016,
+ 240,26112, 248,30208, 256,2048, 264,6144, 272,10240, 280,14336, 288,18432,
+ 296,22528, 304,26624, 312,30720, 320,2560, 328,6656, 336,10752, 344,14848,
+ 352,18944, 360,23040, 368,27136, 376,31232, 384,3072, 392,7168, 400,11264,
+ 408,15360, 416,19456, 424,23552, 432,27648, 440,31744, 448,3584, 456,7680,
+ 464,11776, 472,15872, 480,19968, 488,24064, 496,28160, 504,32256, 520,4160,
+ 528,8256, 536,12352, 544,16448, 552,20544, 560,24640, 568,28736, 584,4672,
+ 592,8768, 600,12864, 608,16960, 616,21056, 624,25152, 632,29248, 640,1088,
+ 648,5184, 656,9280, 664,13376, 672,17472, 680,21568, 688,25664, 696,29760,
+ 704,1600, 712,5696, 720,9792, 728,13888, 736,17984, 744,22080, 752,26176,
+ 760,30272, 768,2112, 776,6208, 784,10304, 792,14400, 800,18496, 808,22592,
+ 816,26688, 824,30784, 832,2624, 840,6720, 848,10816, 856,14912, 864,19008,
+ 872,23104, 880,27200, 888,31296, 896,3136, 904,7232, 912,11328, 920,15424,
+ 928,19520, 936,23616, 944,27712, 952,31808, 960,3648, 968,7744, 976,11840,
+ 984,15936, 992,20032, 1000,24128, 1008,28224, 1016,32320, 1032,4224,
+ 1040,8320, 1048,12416, 1056,16512, 1064,20608, 1072,24704, 1080,28800,
+ 1096,4736, 1104,8832, 1112,12928, 1120,17024, 1128,21120, 1136,25216,
+ 1144,29312, 1160,5248, 1168,9344, 1176,13440, 1184,17536, 1192,21632,
+ 1200,25728, 1208,29824, 1216,1664, 1224,5760, 1232,9856, 1240,13952,
+ 1248,18048, 1256,22144, 1264,26240, 1272,30336, 1280,2176, 1288,6272,
+ 1296,10368, 1304,14464, 1312,18560, 1320,22656, 1328,26752, 1336,30848,
+ 1344,2688, 1352,6784, 1360,10880, 1368,14976, 1376,19072, 1384,23168,
+ 1392,27264, 1400,31360, 1408,3200, 1416,7296, 1424,11392, 1432,15488,
+ 1440,19584, 1448,23680, 1456,27776, 1464,31872, 1472,3712, 1480,7808,
+ 1488,11904, 1496,16000, 1504,20096, 1512,24192, 1520,28288, 1528,32384,
+ 1544,4288, 1552,8384, 1560,12480, 1568,16576, 1576,20672, 1584,24768,
+ 1592,28864, 1608,4800, 1616,8896, 1624,12992, 1632,17088, 1640,21184,
+ 1648,25280, 1656,29376, 1672,5312, 1680,9408, 1688,13504, 1696,17600,
+ 1704,21696, 1712,25792, 1720,29888, 1736,5824, 1744,9920, 1752,14016,
+ 1760,18112, 1768,22208, 1776,26304, 1784,30400, 1792,2240, 1800,6336,
+ 1808,10432, 1816,14528, 1824,18624, 1832,22720, 1840,26816, 1848,30912,
+ 1856,2752, 1864,6848, 1872,10944, 1880,15040, 1888,19136, 1896,23232,
+ 1904,27328, 1912,31424, 1920,3264, 1928,7360, 1936,11456, 1944,15552,
+ 1952,19648, 1960,23744, 1968,27840, 1976,31936, 1984,3776, 1992,7872,
+ 2000,11968, 2008,16064, 2016,20160, 2024,24256, 2032,28352, 2040,32448,
+ 2056,4352, 2064,8448, 2072,12544, 2080,16640, 2088,20736, 2096,24832,
+ 2104,28928, 2120,4864, 2128,8960, 2136,13056, 2144,17152, 2152,21248,
+ 2160,25344, 2168,29440, 2184,5376, 2192,9472, 2200,13568, 2208,17664,
+ 2216,21760, 2224,25856, 2232,29952, 2248,5888, 2256,9984, 2264,14080,
+ 2272,18176, 2280,22272, 2288,26368, 2296,30464, 2312,6400, 2320,10496,
+ 2328,14592, 2336,18688, 2344,22784, 2352,26880, 2360,30976, 2368,2816,
+ 2376,6912, 2384,11008, 2392,15104, 2400,19200, 2408,23296, 2416,27392,
+ 2424,31488, 2432,3328, 2440,7424, 2448,11520, 2456,15616, 2464,19712,
+ 2472,23808, 2480,27904, 2488,32000, 2496,3840, 2504,7936, 2512,12032,
+ 2520,16128, 2528,20224, 2536,24320, 2544,28416, 2552,32512, 2568,4416,
+ 2576,8512, 2584,12608, 2592,16704, 2600,20800, 2608,24896, 2616,28992,
+ 2632,4928, 2640,9024, 2648,13120, 2656,17216, 2664,21312, 2672,25408,
+ 2680,29504, 2696,5440, 2704,9536, 2712,13632, 2720,17728, 2728,21824,
+ 2736,25920, 2744,30016, 2760,5952, 2768,10048, 2776,14144, 2784,18240,
+ 2792,22336, 2800,26432, 2808,30528, 2824,6464, 2832,10560, 2840,14656,
+ 2848,18752, 2856,22848, 2864,26944, 2872,31040, 2888,6976, 2896,11072,
+ 2904,15168, 2912,19264, 2920,23360, 2928,27456, 2936,31552, 2944,3392,
+ 2952,7488, 2960,11584, 2968,15680, 2976,19776, 2984,23872, 2992,27968,
+ 3000,32064, 3008,3904, 3016,8000, 3024,12096, 3032,16192, 3040,20288,
+ 3048,24384, 3056,28480, 3064,32576, 3080,4480, 3088,8576, 3096,12672,
+ 3104,16768, 3112,20864, 3120,24960, 3128,29056, 3144,4992, 3152,9088,
+ 3160,13184, 3168,17280, 3176,21376, 3184,25472, 3192,29568, 3208,5504,
+ 3216,9600, 3224,13696, 3232,17792, 3240,21888, 3248,25984, 3256,30080,
+ 3272,6016, 3280,10112, 3288,14208, 3296,18304, 3304,22400, 3312,26496,
+ 3320,30592, 3336,6528, 3344,10624, 3352,14720, 3360,18816, 3368,22912,
+ 3376,27008, 3384,31104, 3400,7040, 3408,11136, 3416,15232, 3424,19328,
+ 3432,23424, 3440,27520, 3448,31616, 3464,7552, 3472,11648, 3480,15744,
+ 3488,19840, 3496,23936, 3504,28032, 3512,32128, 3520,3968, 3528,8064,
+ 3536,12160, 3544,16256, 3552,20352, 3560,24448, 3568,28544, 3576,32640,
+ 3592,4544, 3600,8640, 3608,12736, 3616,16832, 3624,20928, 3632,25024,
+ 3640,29120, 3656,5056, 3664,9152, 3672,13248, 3680,17344, 3688,21440,
+ 3696,25536, 3704,29632, 3720,5568, 3728,9664, 3736,13760, 3744,17856,
+ 3752,21952, 3760,26048, 3768,30144, 3784,6080, 3792,10176, 3800,14272,
+ 3808,18368, 3816,22464, 3824,26560, 3832,30656, 3848,6592, 3856,10688,
+ 3864,14784, 3872,18880, 3880,22976, 3888,27072, 3896,31168, 3912,7104,
+ 3920,11200, 3928,15296, 3936,19392, 3944,23488, 3952,27584, 3960,31680,
+ 3976,7616, 3984,11712, 3992,15808, 4000,19904, 4008,24000, 4016,28096,
+ 4024,32192, 4040,8128, 4048,12224, 4056,16320, 4064,20416, 4072,24512,
+ 4080,28608, 4088,32704, 4112,8200, 4120,12296, 4128,16392, 4136,20488,
+ 4144,24584, 4152,28680, 4168,4616, 4176,8712, 4184,12808, 4192,16904,
+ 4200,21000, 4208,25096, 4216,29192, 4232,5128, 4240,9224, 4248,13320,
+ 4256,17416, 4264,21512, 4272,25608, 4280,29704, 4296,5640, 4304,9736,
+ 4312,13832, 4320,17928, 4328,22024, 4336,26120, 4344,30216, 4360,6152,
+ 4368,10248, 4376,14344, 4384,18440, 4392,22536, 4400,26632, 4408,30728,
+ 4424,6664, 4432,10760, 4440,14856, 4448,18952, 4456,23048, 4464,27144,
+ 4472,31240, 4488,7176, 4496,11272, 4504,15368, 4512,19464, 4520,23560,
+ 4528,27656, 4536,31752, 4552,7688, 4560,11784, 4568,15880, 4576,19976,
+ 4584,24072, 4592,28168, 4600,32264, 4624,8264, 4632,12360, 4640,16456,
+ 4648,20552, 4656,24648, 4664,28744, 4688,8776, 4696,12872, 4704,16968,
+ 4712,21064, 4720,25160, 4728,29256, 4744,5192, 4752,9288, 4760,13384,
+ 4768,17480, 4776,21576, 4784,25672, 4792,29768, 4808,5704, 4816,9800,
+ 4824,13896, 4832,17992, 4840,22088, 4848,26184, 4856,30280, 4872,6216,
+ 4880,10312, 4888,14408, 4896,18504, 4904,22600, 4912,26696, 4920,30792,
+ 4936,6728, 4944,10824, 4952,14920, 4960,19016, 4968,23112, 4976,27208,
+ 4984,31304, 5000,7240, 5008,11336, 5016,15432, 5024,19528, 5032,23624,
+ 5040,27720, 5048,31816, 5064,7752, 5072,11848, 5080,15944, 5088,20040,
+ 5096,24136, 5104,28232, 5112,32328, 5136,8328, 5144,12424, 5152,16520,
+ 5160,20616, 5168,24712, 5176,28808, 5200,8840, 5208,12936, 5216,17032,
+ 5224,21128, 5232,25224, 5240,29320, 5264,9352, 5272,13448, 5280,17544,
+ 5288,21640, 5296,25736, 5304,29832, 5320,5768, 5328,9864, 5336,13960,
+ 5344,18056, 5352,22152, 5360,26248, 5368,30344, 5384,6280, 5392,10376,
+ 5400,14472, 5408,18568, 5416,22664, 5424,26760, 5432,30856, 5448,6792,
+ 5456,10888, 5464,14984, 5472,19080, 5480,23176, 5488,27272, 5496,31368,
+ 5512,7304, 5520,11400, 5528,15496, 5536,19592, 5544,23688, 5552,27784,
+ 5560,31880, 5576,7816, 5584,11912, 5592,16008, 5600,20104, 5608,24200,
+ 5616,28296, 5624,32392, 5648,8392, 5656,12488, 5664,16584, 5672,20680,
+ 5680,24776, 5688,28872, 5712,8904, 5720,13000, 5728,17096, 5736,21192,
+ 5744,25288, 5752,29384, 5776,9416, 5784,13512, 5792,17608, 5800,21704,
+ 5808,25800, 5816,29896, 5840,9928, 5848,14024, 5856,18120, 5864,22216,
+ 5872,26312, 5880,30408, 5896,6344, 5904,10440, 5912,14536, 5920,18632,
+ 5928,22728, 5936,26824, 5944,30920, 5960,6856, 5968,10952, 5976,15048,
+ 5984,19144, 5992,23240, 6000,27336, 6008,31432, 6024,7368, 6032,11464,
+ 6040,15560, 6048,19656, 6056,23752, 6064,27848, 6072,31944, 6088,7880,
+ 6096,11976, 6104,16072, 6112,20168, 6120,24264, 6128,28360, 6136,32456,
+ 6160,8456, 6168,12552, 6176,16648, 6184,20744, 6192,24840, 6200,28936,
+ 6224,8968, 6232,13064, 6240,17160, 6248,21256, 6256,25352, 6264,29448,
+ 6288,9480, 6296,13576, 6304,17672, 6312,21768, 6320,25864, 6328,29960,
+ 6352,9992, 6360,14088, 6368,18184, 6376,22280, 6384,26376, 6392,30472,
+ 6416,10504, 6424,14600, 6432,18696, 6440,22792, 6448,26888, 6456,30984,
+ 6472,6920, 6480,11016, 6488,15112, 6496,19208, 6504,23304, 6512,27400,
+ 6520,31496, 6536,7432, 6544,11528, 6552,15624, 6560,19720, 6568,23816,
+ 6576,27912, 6584,32008, 6600,7944, 6608,12040, 6616,16136, 6624,20232,
+ 6632,24328, 6640,28424, 6648,32520, 6672,8520, 6680,12616, 6688,16712,
+ 6696,20808, 6704,24904, 6712,29000, 6736,9032, 6744,13128, 6752,17224,
+ 6760,21320, 6768,25416, 6776,29512, 6800,9544, 6808,13640, 6816,17736,
+ 6824,21832, 6832,25928, 6840,30024, 6864,10056, 6872,14152, 6880,18248,
+ 6888,22344, 6896,26440, 6904,30536, 6928,10568, 6936,14664, 6944,18760,
+ 6952,22856, 6960,26952, 6968,31048, 6992,11080, 7000,15176, 7008,19272,
+ 7016,23368, 7024,27464, 7032,31560, 7048,7496, 7056,11592, 7064,15688,
+ 7072,19784, 7080,23880, 7088,27976, 7096,32072, 7112,8008, 7120,12104,
+ 7128,16200, 7136,20296, 7144,24392, 7152,28488, 7160,32584, 7184,8584,
+ 7192,12680, 7200,16776, 7208,20872, 7216,24968, 7224,29064, 7248,9096,
+ 7256,13192, 7264,17288, 7272,21384, 7280,25480, 7288,29576, 7312,9608,
+ 7320,13704, 7328,17800, 7336,21896, 7344,25992, 7352,30088, 7376,10120,
+ 7384,14216, 7392,18312, 7400,22408, 7408,26504, 7416,30600, 7440,10632,
+ 7448,14728, 7456,18824, 7464,22920, 7472,27016, 7480,31112, 7504,11144,
+ 7512,15240, 7520,19336, 7528,23432, 7536,27528, 7544,31624, 7568,11656,
+ 7576,15752, 7584,19848, 7592,23944, 7600,28040, 7608,32136, 7624,8072,
+ 7632,12168, 7640,16264, 7648,20360, 7656,24456, 7664,28552, 7672,32648,
+ 7696,8648, 7704,12744, 7712,16840, 7720,20936, 7728,25032, 7736,29128,
+ 7760,9160, 7768,13256, 7776,17352, 7784,21448, 7792,25544, 7800,29640,
+ 7824,9672, 7832,13768, 7840,17864, 7848,21960, 7856,26056, 7864,30152,
+ 7888,10184, 7896,14280, 7904,18376, 7912,22472, 7920,26568, 7928,30664,
+ 7952,10696, 7960,14792, 7968,18888, 7976,22984, 7984,27080, 7992,31176,
+ 8016,11208, 8024,15304, 8032,19400, 8040,23496, 8048,27592, 8056,31688,
+ 8080,11720, 8088,15816, 8096,19912, 8104,24008, 8112,28104, 8120,32200,
+ 8144,12232, 8152,16328, 8160,20424, 8168,24520, 8176,28616, 8184,32712,
+ 8216,12304, 8224,16400, 8232,20496, 8240,24592, 8248,28688, 8272,8720,
+ 8280,12816, 8288,16912, 8296,21008, 8304,25104, 8312,29200, 8336,9232,
+ 8344,13328, 8352,17424, 8360,21520, 8368,25616, 8376,29712, 8400,9744,
+ 8408,13840, 8416,17936, 8424,22032, 8432,26128, 8440,30224, 8464,10256,
+ 8472,14352, 8480,18448, 8488,22544, 8496,26640, 8504,30736, 8528,10768,
+ 8536,14864, 8544,18960, 8552,23056, 8560,27152, 8568,31248, 8592,11280,
+ 8600,15376, 8608,19472, 8616,23568, 8624,27664, 8632,31760, 8656,11792,
+ 8664,15888, 8672,19984, 8680,24080, 8688,28176, 8696,32272, 8728,12368,
+ 8736,16464, 8744,20560, 8752,24656, 8760,28752, 8792,12880, 8800,16976,
+ 8808,21072, 8816,25168, 8824,29264, 8848,9296, 8856,13392, 8864,17488,
+ 8872,21584, 8880,25680, 8888,29776, 8912,9808, 8920,13904, 8928,18000,
+ 8936,22096, 8944,26192, 8952,30288, 8976,10320, 8984,14416, 8992,18512,
+ 9000,22608, 9008,26704, 9016,30800, 9040,10832, 9048,14928, 9056,19024,
+ 9064,23120, 9072,27216, 9080,31312, 9104,11344, 9112,15440, 9120,19536,
+ 9128,23632, 9136,27728, 9144,31824, 9168,11856, 9176,15952, 9184,20048,
+ 9192,24144, 9200,28240, 9208,32336, 9240,12432, 9248,16528, 9256,20624,
+ 9264,24720, 9272,28816, 9304,12944, 9312,17040, 9320,21136, 9328,25232,
+ 9336,29328, 9368,13456, 9376,17552, 9384,21648, 9392,25744, 9400,29840,
+ 9424,9872, 9432,13968, 9440,18064, 9448,22160, 9456,26256, 9464,30352,
+ 9488,10384, 9496,14480, 9504,18576, 9512,22672, 9520,26768, 9528,30864,
+ 9552,10896, 9560,14992, 9568,19088, 9576,23184, 9584,27280, 9592,31376,
+ 9616,11408, 9624,15504, 9632,19600, 9640,23696, 9648,27792, 9656,31888,
+ 9680,11920, 9688,16016, 9696,20112, 9704,24208, 9712,28304, 9720,32400,
+ 9752,12496, 9760,16592, 9768,20688, 9776,24784, 9784,28880, 9816,13008,
+ 9824,17104, 9832,21200, 9840,25296, 9848,29392, 9880,13520, 9888,17616,
+ 9896,21712, 9904,25808, 9912,29904, 9944,14032, 9952,18128, 9960,22224,
+ 9968,26320, 9976,30416, 10000,10448, 10008,14544, 10016,18640, 10024,22736,
+ 10032,26832, 10040,30928, 10064,10960, 10072,15056, 10080,19152,
+ 10088,23248, 10096,27344, 10104,31440, 10128,11472, 10136,15568,
+ 10144,19664, 10152,23760, 10160,27856, 10168,31952, 10192,11984,
+ 10200,16080, 10208,20176, 10216,24272, 10224,28368, 10232,32464,
+ 10264,12560, 10272,16656, 10280,20752, 10288,24848, 10296,28944,
+ 10328,13072, 10336,17168, 10344,21264, 10352,25360, 10360,29456,
+ 10392,13584, 10400,17680, 10408,21776, 10416,25872, 10424,29968,
+ 10456,14096, 10464,18192, 10472,22288, 10480,26384, 10488,30480,
+ 10520,14608, 10528,18704, 10536,22800, 10544,26896, 10552,30992,
+ 10576,11024, 10584,15120, 10592,19216, 10600,23312, 10608,27408,
+ 10616,31504, 10640,11536, 10648,15632, 10656,19728, 10664,23824,
+ 10672,27920, 10680,32016, 10704,12048, 10712,16144, 10720,20240,
+ 10728,24336, 10736,28432, 10744,32528, 10776,12624, 10784,16720,
+ 10792,20816, 10800,24912, 10808,29008, 10840,13136, 10848,17232,
+ 10856,21328, 10864,25424, 10872,29520, 10904,13648, 10912,17744,
+ 10920,21840, 10928,25936, 10936,30032, 10968,14160, 10976,18256,
+ 10984,22352, 10992,26448, 11000,30544, 11032,14672, 11040,18768,
+ 11048,22864, 11056,26960, 11064,31056, 11096,15184, 11104,19280,
+ 11112,23376, 11120,27472, 11128,31568, 11152,11600, 11160,15696,
+ 11168,19792, 11176,23888, 11184,27984, 11192,32080, 11216,12112,
+ 11224,16208, 11232,20304, 11240,24400, 11248,28496, 11256,32592,
+ 11288,12688, 11296,16784, 11304,20880, 11312,24976, 11320,29072,
+ 11352,13200, 11360,17296, 11368,21392, 11376,25488, 11384,29584,
+ 11416,13712, 11424,17808, 11432,21904, 11440,26000, 11448,30096,
+ 11480,14224, 11488,18320, 11496,22416, 11504,26512, 11512,30608,
+ 11544,14736, 11552,18832, 11560,22928, 11568,27024, 11576,31120,
+ 11608,15248, 11616,19344, 11624,23440, 11632,27536, 11640,31632,
+ 11672,15760, 11680,19856, 11688,23952, 11696,28048, 11704,32144,
+ 11728,12176, 11736,16272, 11744,20368, 11752,24464, 11760,28560,
+ 11768,32656, 11800,12752, 11808,16848, 11816,20944, 11824,25040,
+ 11832,29136, 11864,13264, 11872,17360, 11880,21456, 11888,25552,
+ 11896,29648, 11928,13776, 11936,17872, 11944,21968, 11952,26064,
+ 11960,30160, 11992,14288, 12000,18384, 12008,22480, 12016,26576,
+ 12024,30672, 12056,14800, 12064,18896, 12072,22992, 12080,27088,
+ 12088,31184, 12120,15312, 12128,19408, 12136,23504, 12144,27600,
+ 12152,31696, 12184,15824, 12192,19920, 12200,24016, 12208,28112,
+ 12216,32208, 12248,16336, 12256,20432, 12264,24528, 12272,28624,
+ 12280,32720, 12320,16408, 12328,20504, 12336,24600, 12344,28696,
+ 12376,12824, 12384,16920, 12392,21016, 12400,25112, 12408,29208,
+ 12440,13336, 12448,17432, 12456,21528, 12464,25624, 12472,29720,
+ 12504,13848, 12512,17944, 12520,22040, 12528,26136, 12536,30232,
+ 12568,14360, 12576,18456, 12584,22552, 12592,26648, 12600,30744,
+ 12632,14872, 12640,18968, 12648,23064, 12656,27160, 12664,31256,
+ 12696,15384, 12704,19480, 12712,23576, 12720,27672, 12728,31768,
+ 12760,15896, 12768,19992, 12776,24088, 12784,28184, 12792,32280,
+ 12832,16472, 12840,20568, 12848,24664, 12856,28760, 12896,16984,
+ 12904,21080, 12912,25176, 12920,29272, 12952,13400, 12960,17496,
+ 12968,21592, 12976,25688, 12984,29784, 13016,13912, 13024,18008,
+ 13032,22104, 13040,26200, 13048,30296, 13080,14424, 13088,18520,
+ 13096,22616, 13104,26712, 13112,30808, 13144,14936, 13152,19032,
+ 13160,23128, 13168,27224, 13176,31320, 13208,15448, 13216,19544,
+ 13224,23640, 13232,27736, 13240,31832, 13272,15960, 13280,20056,
+ 13288,24152, 13296,28248, 13304,32344, 13344,16536, 13352,20632,
+ 13360,24728, 13368,28824, 13408,17048, 13416,21144, 13424,25240,
+ 13432,29336, 13472,17560, 13480,21656, 13488,25752, 13496,29848,
+ 13528,13976, 13536,18072, 13544,22168, 13552,26264, 13560,30360,
+ 13592,14488, 13600,18584, 13608,22680, 13616,26776, 13624,30872,
+ 13656,15000, 13664,19096, 13672,23192, 13680,27288, 13688,31384,
+ 13720,15512, 13728,19608, 13736,23704, 13744,27800, 13752,31896,
+ 13784,16024, 13792,20120, 13800,24216, 13808,28312, 13816,32408,
+ 13856,16600, 13864,20696, 13872,24792, 13880,28888, 13920,17112,
+ 13928,21208, 13936,25304, 13944,29400, 13984,17624, 13992,21720,
+ 14000,25816, 14008,29912, 14048,18136, 14056,22232, 14064,26328,
+ 14072,30424, 14104,14552, 14112,18648, 14120,22744, 14128,26840,
+ 14136,30936, 14168,15064, 14176,19160, 14184,23256, 14192,27352,
+ 14200,31448, 14232,15576, 14240,19672, 14248,23768, 14256,27864,
+ 14264,31960, 14296,16088, 14304,20184, 14312,24280, 14320,28376,
+ 14328,32472, 14368,16664, 14376,20760, 14384,24856, 14392,28952,
+ 14432,17176, 14440,21272, 14448,25368, 14456,29464, 14496,17688,
+ 14504,21784, 14512,25880, 14520,29976, 14560,18200, 14568,22296,
+ 14576,26392, 14584,30488, 14624,18712, 14632,22808, 14640,26904,
+ 14648,31000, 14680,15128, 14688,19224, 14696,23320, 14704,27416,
+ 14712,31512, 14744,15640, 14752,19736, 14760,23832, 14768,27928,
+ 14776,32024, 14808,16152, 14816,20248, 14824,24344, 14832,28440,
+ 14840,32536, 14880,16728, 14888,20824, 14896,24920, 14904,29016,
+ 14944,17240, 14952,21336, 14960,25432, 14968,29528, 15008,17752,
+ 15016,21848, 15024,25944, 15032,30040, 15072,18264, 15080,22360,
+ 15088,26456, 15096,30552, 15136,18776, 15144,22872, 15152,26968,
+ 15160,31064, 15200,19288, 15208,23384, 15216,27480, 15224,31576,
+ 15256,15704, 15264,19800, 15272,23896, 15280,27992, 15288,32088,
+ 15320,16216, 15328,20312, 15336,24408, 15344,28504, 15352,32600,
+ 15392,16792, 15400,20888, 15408,24984, 15416,29080, 15456,17304,
+ 15464,21400, 15472,25496, 15480,29592, 15520,17816, 15528,21912,
+ 15536,26008, 15544,30104, 15584,18328, 15592,22424, 15600,26520,
+ 15608,30616, 15648,18840, 15656,22936, 15664,27032, 15672,31128,
+ 15712,19352, 15720,23448, 15728,27544, 15736,31640, 15776,19864,
+ 15784,23960, 15792,28056, 15800,32152, 15832,16280, 15840,20376,
+ 15848,24472, 15856,28568, 15864,32664, 15904,16856, 15912,20952,
+ 15920,25048, 15928,29144, 15968,17368, 15976,21464, 15984,25560,
+ 15992,29656, 16032,17880, 16040,21976, 16048,26072, 16056,30168,
+ 16096,18392, 16104,22488, 16112,26584, 16120,30680, 16160,18904,
+ 16168,23000, 16176,27096, 16184,31192, 16224,19416, 16232,23512,
+ 16240,27608, 16248,31704, 16288,19928, 16296,24024, 16304,28120,
+ 16312,32216, 16352,20440, 16360,24536, 16368,28632, 16376,32728,
+ 16424,20512, 16432,24608, 16440,28704, 16480,16928, 16488,21024,
+ 16496,25120, 16504,29216, 16544,17440, 16552,21536, 16560,25632,
+ 16568,29728, 16608,17952, 16616,22048, 16624,26144, 16632,30240,
+ 16672,18464, 16680,22560, 16688,26656, 16696,30752, 16736,18976,
+ 16744,23072, 16752,27168, 16760,31264, 16800,19488, 16808,23584,
+ 16816,27680, 16824,31776, 16864,20000, 16872,24096, 16880,28192,
+ 16888,32288, 16936,20576, 16944,24672, 16952,28768, 17000,21088,
+ 17008,25184, 17016,29280, 17056,17504, 17064,21600, 17072,25696,
+ 17080,29792, 17120,18016, 17128,22112, 17136,26208, 17144,30304,
+ 17184,18528, 17192,22624, 17200,26720, 17208,30816, 17248,19040,
+ 17256,23136, 17264,27232, 17272,31328, 17312,19552, 17320,23648,
+ 17328,27744, 17336,31840, 17376,20064, 17384,24160, 17392,28256,
+ 17400,32352, 17448,20640, 17456,24736, 17464,28832, 17512,21152,
+ 17520,25248, 17528,29344, 17576,21664, 17584,25760, 17592,29856,
+ 17632,18080, 17640,22176, 17648,26272, 17656,30368, 17696,18592,
+ 17704,22688, 17712,26784, 17720,30880, 17760,19104, 17768,23200,
+ 17776,27296, 17784,31392, 17824,19616, 17832,23712, 17840,27808,
+ 17848,31904, 17888,20128, 17896,24224, 17904,28320, 17912,32416,
+ 17960,20704, 17968,24800, 17976,28896, 18024,21216, 18032,25312,
+ 18040,29408, 18088,21728, 18096,25824, 18104,29920, 18152,22240,
+ 18160,26336, 18168,30432, 18208,18656, 18216,22752, 18224,26848,
+ 18232,30944, 18272,19168, 18280,23264, 18288,27360, 18296,31456,
+ 18336,19680, 18344,23776, 18352,27872, 18360,31968, 18400,20192,
+ 18408,24288, 18416,28384, 18424,32480, 18472,20768, 18480,24864,
+ 18488,28960, 18536,21280, 18544,25376, 18552,29472, 18600,21792,
+ 18608,25888, 18616,29984, 18664,22304, 18672,26400, 18680,30496,
+ 18728,22816, 18736,26912, 18744,31008, 18784,19232, 18792,23328,
+ 18800,27424, 18808,31520, 18848,19744, 18856,23840, 18864,27936,
+ 18872,32032, 18912,20256, 18920,24352, 18928,28448, 18936,32544,
+ 18984,20832, 18992,24928, 19000,29024, 19048,21344, 19056,25440,
+ 19064,29536, 19112,21856, 19120,25952, 19128,30048, 19176,22368,
+ 19184,26464, 19192,30560, 19240,22880, 19248,26976, 19256,31072,
+ 19304,23392, 19312,27488, 19320,31584, 19360,19808, 19368,23904,
+ 19376,28000, 19384,32096, 19424,20320, 19432,24416, 19440,28512,
+ 19448,32608, 19496,20896, 19504,24992, 19512,29088, 19560,21408,
+ 19568,25504, 19576,29600, 19624,21920, 19632,26016, 19640,30112,
+ 19688,22432, 19696,26528, 19704,30624, 19752,22944, 19760,27040,
+ 19768,31136, 19816,23456, 19824,27552, 19832,31648, 19880,23968,
+ 19888,28064, 19896,32160, 19936,20384, 19944,24480, 19952,28576,
+ 19960,32672, 20008,20960, 20016,25056, 20024,29152, 20072,21472,
+ 20080,25568, 20088,29664, 20136,21984, 20144,26080, 20152,30176,
+ 20200,22496, 20208,26592, 20216,30688, 20264,23008, 20272,27104,
+ 20280,31200, 20328,23520, 20336,27616, 20344,31712, 20392,24032,
+ 20400,28128, 20408,32224, 20456,24544, 20464,28640, 20472,32736,
+ 20528,24616, 20536,28712, 20584,21032, 20592,25128, 20600,29224,
+ 20648,21544, 20656,25640, 20664,29736, 20712,22056, 20720,26152,
+ 20728,30248, 20776,22568, 20784,26664, 20792,30760, 20840,23080,
+ 20848,27176, 20856,31272, 20904,23592, 20912,27688, 20920,31784,
+ 20968,24104, 20976,28200, 20984,32296, 21040,24680, 21048,28776,
+ 21104,25192, 21112,29288, 21160,21608, 21168,25704, 21176,29800,
+ 21224,22120, 21232,26216, 21240,30312, 21288,22632, 21296,26728,
+ 21304,30824, 21352,23144, 21360,27240, 21368,31336, 21416,23656,
+ 21424,27752, 21432,31848, 21480,24168, 21488,28264, 21496,32360,
+ 21552,24744, 21560,28840, 21616,25256, 21624,29352, 21680,25768,
+ 21688,29864, 21736,22184, 21744,26280, 21752,30376, 21800,22696,
+ 21808,26792, 21816,30888, 21864,23208, 21872,27304, 21880,31400,
+ 21928,23720, 21936,27816, 21944,31912, 21992,24232, 22000,28328,
+ 22008,32424, 22064,24808, 22072,28904, 22128,25320, 22136,29416,
+ 22192,25832, 22200,29928, 22256,26344, 22264,30440, 22312,22760,
+ 22320,26856, 22328,30952, 22376,23272, 22384,27368, 22392,31464,
+ 22440,23784, 22448,27880, 22456,31976, 22504,24296, 22512,28392,
+ 22520,32488, 22576,24872, 22584,28968, 22640,25384, 22648,29480,
+ 22704,25896, 22712,29992, 22768,26408, 22776,30504, 22832,26920,
+ 22840,31016, 22888,23336, 22896,27432, 22904,31528, 22952,23848,
+ 22960,27944, 22968,32040, 23016,24360, 23024,28456, 23032,32552,
+ 23088,24936, 23096,29032, 23152,25448, 23160,29544, 23216,25960,
+ 23224,30056, 23280,26472, 23288,30568, 23344,26984, 23352,31080,
+ 23408,27496, 23416,31592, 23464,23912, 23472,28008, 23480,32104,
+ 23528,24424, 23536,28520, 23544,32616, 23600,25000, 23608,29096,
+ 23664,25512, 23672,29608, 23728,26024, 23736,30120, 23792,26536,
+ 23800,30632, 23856,27048, 23864,31144, 23920,27560, 23928,31656,
+ 23984,28072, 23992,32168, 24040,24488, 24048,28584, 24056,32680,
+ 24112,25064, 24120,29160, 24176,25576, 24184,29672, 24240,26088,
+ 24248,30184, 24304,26600, 24312,30696, 24368,27112, 24376,31208,
+ 24432,27624, 24440,31720, 24496,28136, 24504,32232, 24560,28648,
+ 24568,32744, 24632,28720, 24688,25136, 24696,29232, 24752,25648,
+ 24760,29744, 24816,26160, 24824,30256, 24880,26672, 24888,30768,
+ 24944,27184, 24952,31280, 25008,27696, 25016,31792, 25072,28208,
+ 25080,32304, 25144,28784, 25208,29296, 25264,25712, 25272,29808,
+ 25328,26224, 25336,30320, 25392,26736, 25400,30832, 25456,27248,
+ 25464,31344, 25520,27760, 25528,31856, 25584,28272, 25592,32368,
+ 25656,28848, 25720,29360, 25784,29872, 25840,26288, 25848,30384,
+ 25904,26800, 25912,30896, 25968,27312, 25976,31408, 26032,27824,
+ 26040,31920, 26096,28336, 26104,32432, 26168,28912, 26232,29424,
+ 26296,29936, 26360,30448, 26416,26864, 26424,30960, 26480,27376,
+ 26488,31472, 26544,27888, 26552,31984, 26608,28400, 26616,32496,
+ 26680,28976, 26744,29488, 26808,30000, 26872,30512, 26936,31024,
+ 26992,27440, 27000,31536, 27056,27952, 27064,32048, 27120,28464,
+ 27128,32560, 27192,29040, 27256,29552, 27320,30064, 27384,30576,
+ 27448,31088, 27512,31600, 27568,28016, 27576,32112, 27632,28528,
+ 27640,32624, 27704,29104, 27768,29616, 27832,30128, 27896,30640,
+ 27960,31152, 28024,31664, 28088,32176, 28144,28592, 28152,32688,
+ 28216,29168, 28280,29680, 28344,30192, 28408,30704, 28472,31216,
+ 28536,31728, 28600,32240, 28664,32752, 28792,29240, 28856,29752,
+ 28920,30264, 28984,30776, 29048,31288, 29112,31800, 29176,32312,
+ 29368,29816, 29432,30328, 29496,30840, 29560,31352, 29624,31864,
+ 29688,32376, 29944,30392, 30008,30904, 30072,31416, 30136,31928,
+ 30200,32440, 30520,30968, 30584,31480, 30648,31992, 30712,32504,
+ 31096,31544, 31160,32056, 31224,32568, 31672,32120, 31736,32632,
+ 32248,32696
+};
+
+
+const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH] =
+{
+ /* radix 4, size 12 */
+ 8,64, 16,32, 24,96, 40,80, 56,112, 88,104
+};
+
+const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH] =
+{
+ /* 4x2, size 24 */
+ 8,128, 16,64, 24,192, 40,160, 48,96, 56,224, 72,144,
+ 88,208, 104,176, 120,240, 152,200, 184,232
+};
+
+const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH] =
+{
+ /* radix 4, size 56 */
+ 8,256, 16,128, 24,384, 32,64, 40,320, 48,192, 56,448, 72,288, 80,160, 88,416, 104,352,
+ 112,224, 120,480, 136,272, 152,400, 168,336, 176,208, 184,464, 200,304, 216,432,
+ 232,368, 248,496, 280,392, 296,328, 312,456, 344,424, 376,488, 440,472
+};
+
+const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH] =
+{
+ /* 4x2, size 112 */
+ 8,512, 16,256, 24,768, 32,128, 40,640, 48,384, 56,896, 72,576, 80,320, 88,832, 96,192,
+ 104,704, 112,448, 120,960, 136,544, 144,288, 152,800, 168,672, 176,416, 184,928, 200,608,
+ 208,352, 216,864, 232,736, 240,480, 248,992, 264,528, 280,784, 296,656, 304,400, 312,912,
+ 328,592, 344,848, 360,720, 368,464, 376,976, 392,560, 408,816, 424,688, 440,944, 456,624,
+ 472,880, 488,752, 504,1008, 536,776, 552,648, 568,904, 600,840, 616,712, 632,968,
+ 664,808, 696,936, 728,872, 760,1000, 824,920, 888,984
+};
+
+const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH] =
+{
+ /* radix 4, size 240 */
+ 8,1024, 16,512, 24,1536, 32,256, 40,1280, 48,768, 56,1792, 64,128, 72,1152, 80,640,
+ 88,1664, 96,384, 104,1408, 112,896, 120,1920, 136,1088, 144,576, 152,1600, 160,320,
+ 168,1344, 176,832, 184,1856, 200,1216, 208,704, 216,1728, 224,448, 232,1472, 240,960,
+ 248,1984, 264,1056, 272,544, 280,1568, 296,1312, 304,800, 312,1824, 328,1184, 336,672,
+ 344,1696, 352,416, 360,1440, 368,928, 376,1952, 392,1120, 400,608, 408,1632, 424,1376,
+ 432,864, 440,1888, 456,1248, 464,736, 472,1760, 488,1504, 496,992, 504,2016, 520,1040,
+ 536,1552, 552,1296, 560,784, 568,1808, 584,1168, 592,656, 600,1680, 616,1424, 624,912,
+ 632,1936, 648,1104, 664,1616, 680,1360, 688,848, 696,1872, 712,1232, 728,1744, 744,1488,
+ 752,976, 760,2000, 776,1072, 792,1584, 808,1328, 824,1840, 840,1200, 856,1712, 872,1456,
+ 880,944, 888,1968, 904,1136, 920,1648, 936,1392, 952,1904, 968,1264, 984,1776, 1000,1520,
+ 1016,2032, 1048,1544, 1064,1288, 1080,1800, 1096,1160, 1112,1672, 1128,1416, 1144,1928,
+ 1176,1608, 1192,1352, 1208,1864, 1240,1736, 1256,1480, 1272,1992, 1304,1576, 1336,1832,
+ 1368,1704, 1384,1448, 1400,1960, 1432,1640, 1464,1896, 1496,1768, 1528,2024, 1592,1816,
+ 1624,1688, 1656,1944, 1720,1880, 1784,2008, 1912,1976
+};
+
+const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH] =
+{
+ /* 4x2, size 480 */
+ 8,2048, 16,1024, 24,3072, 32,512, 40,2560, 48,1536, 56,3584, 64,256, 72,2304, 80,1280,
+ 88,3328, 96,768, 104,2816, 112,1792, 120,3840, 136,2176, 144,1152, 152,3200, 160,640,
+ 168,2688, 176,1664, 184,3712, 192,384, 200,2432, 208,1408, 216,3456, 224,896, 232,2944,
+ 240,1920, 248,3968, 264,2112, 272,1088, 280,3136, 288,576, 296,2624, 304,1600, 312,3648,
+ 328,2368, 336,1344, 344,3392, 352,832, 360,2880, 368,1856, 376,3904, 392,2240, 400,1216,
+ 408,3264, 416,704, 424,2752, 432,1728, 440,3776, 456,2496, 464,1472, 472,3520, 480,960,
+ 488,3008, 496,1984, 504,4032, 520,2080, 528,1056, 536,3104, 552,2592, 560,1568, 568,3616,
+ 584,2336, 592,1312, 600,3360, 608,800, 616,2848, 624,1824, 632,3872, 648,2208, 656,1184,
+ 664,3232, 680,2720, 688,1696, 696,3744, 712,2464, 720,1440, 728,3488, 736,928, 744,2976,
+ 752,1952, 760,4000, 776,2144, 784,1120, 792,3168, 808,2656, 816,1632, 824,3680, 840,2400,
+ 848,1376, 856,3424, 872,2912, 880,1888, 888,3936, 904,2272, 912,1248, 920,3296, 936,2784,
+ 944,1760, 952,3808, 968,2528, 976,1504, 984,3552, 1000,3040, 1008,2016, 1016,4064,
+ 1032,2064, 1048,3088, 1064,2576, 1072,1552, 1080,3600, 1096,2320, 1104,1296, 1112,3344,
+ 1128,2832, 1136,1808, 1144,3856, 1160,2192, 1176,3216, 1192,2704, 1200,1680, 1208,3728,
+ 1224,2448, 1232,1424, 1240,3472, 1256,2960, 1264,1936, 1272,3984, 1288,2128, 1304,3152,
+ 1320,2640, 1328,1616, 1336,3664, 1352,2384, 1368,3408, 1384,2896, 1392,1872, 1400,3920,
+ 1416,2256, 1432,3280, 1448,2768, 1456,1744, 1464,3792, 1480,2512, 1496,3536, 1512,3024,
+ 1520,2000, 1528,4048, 1544,2096, 1560,3120, 1576,2608, 1592,3632, 1608,2352, 1624,3376,
+ 1640,2864, 1648,1840, 1656,3888, 1672,2224, 1688,3248, 1704,2736, 1720,3760, 1736,2480,
+ 1752,3504, 1768,2992, 1776,1968, 1784,4016, 1800,2160, 1816,3184, 1832,2672, 1848,3696,
+ 1864,2416, 1880,3440, 1896,2928, 1912,3952, 1928,2288, 1944,3312, 1960,2800, 1976,3824,
+ 1992,2544, 2008,3568, 2024,3056, 2040,4080, 2072,3080, 2088,2568, 2104,3592, 2120,2312,
+ 2136,3336, 2152,2824, 2168,3848, 2200,3208, 2216,2696, 2232,3720, 2248,2440, 2264,3464,
+ 2280,2952, 2296,3976, 2328,3144, 2344,2632, 2360,3656, 2392,3400, 2408,2888, 2424,3912,
+ 2456,3272, 2472,2760, 2488,3784, 2520,3528, 2536,3016, 2552,4040, 2584,3112, 2616,3624,
+ 2648,3368, 2664,2856, 2680,3880, 2712,3240, 2744,3752, 2776,3496, 2792,2984, 2808,4008,
+ 2840,3176, 2872,3688, 2904,3432, 2936,3944, 2968,3304, 3000,3816, 3032,3560, 3064,4072,
+ 3128,3608, 3160,3352, 3192,3864, 3256,3736, 3288,3480, 3320,3992, 3384,3672, 3448,3928,
+ 3512,3800, 3576,4056, 3704,3896, 3832,4024
+};
+
+const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH] =
+{
+ /* radix 4, size 992 */
+ 8,4096, 16,2048, 24,6144, 32,1024, 40,5120, 48,3072, 56,7168, 64,512, 72,4608,
+ 80,2560, 88,6656, 96,1536, 104,5632, 112,3584, 120,7680, 128,256, 136,4352,
+ 144,2304, 152,6400, 160,1280, 168,5376, 176,3328, 184,7424, 192,768, 200,4864,
+ 208,2816, 216,6912, 224,1792, 232,5888, 240,3840, 248,7936, 264,4224, 272,2176,
+ 280,6272, 288,1152, 296,5248, 304,3200, 312,7296, 320,640, 328,4736, 336,2688,
+ 344,6784, 352,1664, 360,5760, 368,3712, 376,7808, 392,4480, 400,2432, 408,6528,
+ 416,1408, 424,5504, 432,3456, 440,7552, 448,896, 456,4992, 464,2944, 472,7040,
+ 480,1920, 488,6016, 496,3968, 504,8064, 520,4160, 528,2112, 536,6208, 544,1088,
+ 552,5184, 560,3136, 568,7232, 584,4672, 592,2624, 600,6720, 608,1600, 616,5696,
+ 624,3648, 632,7744, 648,4416, 656,2368, 664,6464, 672,1344, 680,5440, 688,3392,
+ 696,7488, 704,832, 712,4928, 720,2880, 728,6976, 736,1856, 744,5952, 752,3904,
+ 760,8000, 776,4288, 784,2240, 792,6336, 800,1216, 808,5312, 816,3264, 824,7360,
+ 840,4800, 848,2752, 856,6848, 864,1728, 872,5824, 880,3776, 888,7872, 904,4544,
+ 912,2496, 920,6592, 928,1472, 936,5568, 944,3520, 952,7616, 968,5056, 976,3008,
+ 984,7104, 992,1984, 1000,6080, 1008,4032, 1016,8128, 1032,4128, 1040,2080,
+ 1048,6176, 1064,5152, 1072,3104, 1080,7200, 1096,4640, 1104,2592, 1112,6688,
+ 1120,1568, 1128,5664, 1136,3616, 1144,7712, 1160,4384, 1168,2336, 1176,6432,
+ 1184,1312, 1192,5408, 1200,3360, 1208,7456, 1224,4896, 1232,2848, 1240,6944,
+ 1248,1824, 1256,5920, 1264,3872, 1272,7968, 1288,4256, 1296,2208, 1304,6304,
+ 1320,5280, 1328,3232, 1336,7328, 1352,4768, 1360,2720, 1368,6816, 1376,1696,
+ 1384,5792, 1392,3744, 1400,7840, 1416,4512, 1424,2464, 1432,6560, 1448,5536,
+ 1456,3488, 1464,7584, 1480,5024, 1488,2976, 1496,7072, 1504,1952, 1512,6048,
+ 1520,4000, 1528,8096, 1544,4192, 1552,2144, 1560,6240, 1576,5216, 1584,3168,
+ 1592,7264, 1608,4704, 1616,2656, 1624,6752, 1640,5728, 1648,3680, 1656,7776,
+ 1672,4448, 1680,2400, 1688,6496, 1704,5472, 1712,3424, 1720,7520, 1736,4960,
+ 1744,2912, 1752,7008, 1760,1888, 1768,5984, 1776,3936, 1784,8032, 1800,4320,
+ 1808,2272, 1816,6368, 1832,5344, 1840,3296, 1848,7392, 1864,4832, 1872,2784,
+ 1880,6880, 1896,5856, 1904,3808, 1912,7904, 1928,4576, 1936,2528, 1944,6624,
+ 1960,5600, 1968,3552, 1976,7648, 1992,5088, 2000,3040, 2008,7136, 2024,6112,
+ 2032,4064, 2040,8160, 2056,4112, 2072,6160, 2088,5136, 2096,3088, 2104,7184,
+ 2120,4624, 2128,2576, 2136,6672, 2152,5648, 2160,3600, 2168,7696, 2184,4368,
+ 2192,2320, 2200,6416, 2216,5392, 2224,3344, 2232,7440, 2248,4880, 2256,2832,
+ 2264,6928, 2280,5904, 2288,3856, 2296,7952, 2312,4240, 2328,6288, 2344,5264,
+ 2352,3216, 2360,7312, 2376,4752, 2384,2704, 2392,6800, 2408,5776, 2416,3728,
+ 2424,7824, 2440,4496, 2456,6544, 2472,5520, 2480,3472, 2488,7568, 2504,5008,
+ 2512,2960, 2520,7056, 2536,6032, 2544,3984, 2552,8080, 2568,4176, 2584,6224,
+ 2600,5200, 2608,3152, 2616,7248, 2632,4688, 2648,6736, 2664,5712, 2672,3664,
+ 2680,7760, 2696,4432, 2712,6480, 2728,5456, 2736,3408, 2744,7504, 2760,4944,
+ 2768,2896, 2776,6992, 2792,5968, 2800,3920, 2808,8016, 2824,4304, 2840,6352,
+ 2856,5328, 2864,3280, 2872,7376, 2888,4816, 2904,6864, 2920,5840, 2928,3792,
+ 2936,7888, 2952,4560, 2968,6608, 2984,5584, 2992,3536, 3000,7632, 3016,5072,
+ 3032,7120, 3048,6096, 3056,4048, 3064,8144, 3080,4144, 3096,6192, 3112,5168,
+ 3128,7216, 3144,4656, 3160,6704, 3176,5680, 3184,3632, 3192,7728, 3208,4400,
+ 3224,6448, 3240,5424, 3248,3376, 3256,7472, 3272,4912, 3288,6960, 3304,5936,
+ 3312,3888, 3320,7984, 3336,4272, 3352,6320, 3368,5296, 3384,7344, 3400,4784,
+ 3416,6832, 3432,5808, 3440,3760, 3448,7856, 3464,4528, 3480,6576, 3496,5552,
+ 3512,7600, 3528,5040, 3544,7088, 3560,6064, 3568,4016, 3576,8112, 3592,4208,
+ 3608,6256, 3624,5232, 3640,7280, 3656,4720, 3672,6768, 3688,5744, 3704,7792,
+ 3720,4464, 3736,6512, 3752,5488, 3768,7536, 3784,4976, 3800,7024, 3816,6000,
+ 3824,3952, 3832,8048, 3848,4336, 3864,6384, 3880,5360, 3896,7408, 3912,4848,
+ 3928,6896, 3944,5872, 3960,7920, 3976,4592, 3992,6640, 4008,5616, 4024,7664,
+ 4040,5104, 4056,7152, 4072,6128, 4088,8176, 4120,6152, 4136,5128, 4152,7176,
+ 4168,4616, 4184,6664, 4200,5640, 4216,7688, 4232,4360, 4248,6408, 4264,5384,
+ 4280,7432, 4296,4872, 4312,6920, 4328,5896, 4344,7944, 4376,6280, 4392,5256,
+ 4408,7304, 4424,4744, 4440,6792, 4456,5768, 4472,7816, 4504,6536, 4520,5512,
+ 4536,7560, 4552,5000, 4568,7048, 4584,6024, 4600,8072, 4632,6216, 4648,5192,
+ 4664,7240, 4696,6728, 4712,5704, 4728,7752, 4760,6472, 4776,5448, 4792,7496,
+ 4808,4936, 4824,6984, 4840,5960, 4856,8008, 4888,6344, 4904,5320, 4920,7368,
+ 4952,6856, 4968,5832, 4984,7880, 5016,6600, 5032,5576, 5048,7624, 5080,7112,
+ 5096,6088, 5112,8136, 5144,6184, 5176,7208, 5208,6696, 5224,5672, 5240,7720,
+ 5272,6440, 5288,5416, 5304,7464, 5336,6952, 5352,5928, 5368,7976, 5400,6312,
+ 5432,7336, 5464,6824, 5480,5800, 5496,7848, 5528,6568, 5560,7592, 5592,7080,
+ 5608,6056, 5624,8104, 5656,6248, 5688,7272, 5720,6760, 5752,7784, 5784,6504,
+ 5816,7528, 5848,7016, 5864,5992, 5880,8040, 5912,6376, 5944,7400, 5976,6888,
+ 6008,7912, 6040,6632, 6072,7656, 6104,7144, 6136,8168, 6200,7192, 6232,6680,
+ 6264,7704, 6296,6424, 6328,7448, 6360,6936, 6392,7960, 6456,7320, 6488,6808,
+ 6520,7832, 6584,7576, 6616,7064, 6648,8088, 6712,7256, 6776,7768, 6840,7512,
+ 6872,7000, 6904,8024, 6968,7384, 7032,7896, 7096,7640, 7160,8152, 7288,7736,
+ 7352,7480, 7416,7992, 7544,7864, 7672,8120, 7928,8056
+};
+
+const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH] =
+{
+ /* 4x2, size 1984 */
+ 8,8192, 16,4096, 24,12288, 32,2048, 40,10240, 48,6144, 56,14336, 64,1024,
+ 72,9216, 80,5120, 88,13312, 96,3072, 104,11264, 112,7168, 120,15360, 128,512,
+ 136,8704, 144,4608, 152,12800, 160,2560, 168,10752, 176,6656, 184,14848,
+ 192,1536, 200,9728, 208,5632, 216,13824, 224,3584, 232,11776, 240,7680,
+ 248,15872, 264,8448, 272,4352, 280,12544, 288,2304, 296,10496, 304,6400,
+ 312,14592, 320,1280, 328,9472, 336,5376, 344,13568, 352,3328, 360,11520,
+ 368,7424, 376,15616, 384,768, 392,8960, 400,4864, 408,13056, 416,2816,
+ 424,11008, 432,6912, 440,15104, 448,1792, 456,9984, 464,5888, 472,14080,
+ 480,3840, 488,12032, 496,7936, 504,16128, 520,8320, 528,4224, 536,12416,
+ 544,2176, 552,10368, 560,6272, 568,14464, 576,1152, 584,9344, 592,5248,
+ 600,13440, 608,3200, 616,11392, 624,7296, 632,15488, 648,8832, 656,4736,
+ 664,12928, 672,2688, 680,10880, 688,6784, 696,14976, 704,1664, 712,9856,
+ 720,5760, 728,13952, 736,3712, 744,11904, 752,7808, 760,16000, 776,8576,
+ 784,4480, 792,12672, 800,2432, 808,10624, 816,6528, 824,14720, 832,1408,
+ 840,9600, 848,5504, 856,13696, 864,3456, 872,11648, 880,7552, 888,15744,
+ 904,9088, 912,4992, 920,13184, 928,2944, 936,11136, 944,7040, 952,15232,
+ 960,1920, 968,10112, 976,6016, 984,14208, 992,3968, 1000,12160, 1008,8064,
+ 1016,16256, 1032,8256, 1040,4160, 1048,12352, 1056,2112, 1064,10304, 1072,6208,
+ 1080,14400, 1096,9280, 1104,5184, 1112,13376, 1120,3136, 1128,11328, 1136,7232,
+ 1144,15424, 1160,8768, 1168,4672, 1176,12864, 1184,2624, 1192,10816, 1200,6720,
+ 1208,14912, 1216,1600, 1224,9792, 1232,5696, 1240,13888, 1248,3648, 1256,11840,
+ 1264,7744, 1272,15936, 1288,8512, 1296,4416, 1304,12608, 1312,2368, 1320,10560,
+ 1328,6464, 1336,14656, 1352,9536, 1360,5440, 1368,13632, 1376,3392, 1384,11584,
+ 1392,7488, 1400,15680, 1416,9024, 1424,4928, 1432,13120, 1440,2880, 1448,11072,
+ 1456,6976, 1464,15168, 1472,1856, 1480,10048, 1488,5952, 1496,14144, 1504,3904,
+ 1512,12096, 1520,8000, 1528,16192, 1544,8384, 1552,4288, 1560,12480, 1568,2240,
+ 1576,10432, 1584,6336, 1592,14528, 1608,9408, 1616,5312, 1624,13504, 1632,3264,
+ 1640,11456, 1648,7360, 1656,15552, 1672,8896, 1680,4800, 1688,12992, 1696,2752,
+ 1704,10944, 1712,6848, 1720,15040, 1736,9920, 1744,5824, 1752,14016, 1760,3776,
+ 1768,11968, 1776,7872, 1784,16064, 1800,8640, 1808,4544, 1816,12736, 1824,2496,
+ 1832,10688, 1840,6592, 1848,14784, 1864,9664, 1872,5568, 1880,13760, 1888,3520,
+ 1896,11712, 1904,7616, 1912,15808, 1928,9152, 1936,5056, 1944,13248, 1952,3008,
+ 1960,11200, 1968,7104, 1976,15296, 1992,10176, 2000,6080, 2008,14272, 2016,4032,
+ 2024,12224, 2032,8128, 2040,16320, 2056,8224, 2064,4128, 2072,12320, 2088,10272,
+ 2096,6176, 2104,14368, 2120,9248, 2128,5152, 2136,13344, 2144,3104, 2152,11296,
+ 2160,7200, 2168,15392, 2184,8736, 2192,4640, 2200,12832, 2208,2592, 2216,10784,
+ 2224,6688, 2232,14880, 2248,9760, 2256,5664, 2264,13856, 2272,3616, 2280,11808,
+ 2288,7712, 2296,15904, 2312,8480, 2320,4384, 2328,12576, 2344,10528, 2352,6432,
+ 2360,14624, 2376,9504, 2384,5408, 2392,13600, 2400,3360, 2408,11552, 2416,7456,
+ 2424,15648, 2440,8992, 2448,4896, 2456,13088, 2464,2848, 2472,11040, 2480,6944,
+ 2488,15136, 2504,10016, 2512,5920, 2520,14112, 2528,3872, 2536,12064, 2544,7968,
+ 2552,16160, 2568,8352, 2576,4256, 2584,12448, 2600,10400, 2608,6304, 2616,14496,
+ 2632,9376, 2640,5280, 2648,13472, 2656,3232, 2664,11424, 2672,7328, 2680,15520,
+ 2696,8864, 2704,4768, 2712,12960, 2728,10912, 2736,6816, 2744,15008, 2760,9888,
+ 2768,5792, 2776,13984, 2784,3744, 2792,11936, 2800,7840, 2808,16032, 2824,8608,
+ 2832,4512, 2840,12704, 2856,10656, 2864,6560, 2872,14752, 2888,9632, 2896,5536,
+ 2904,13728, 2912,3488, 2920,11680, 2928,7584, 2936,15776, 2952,9120, 2960,5024,
+ 2968,13216, 2984,11168, 2992,7072, 3000,15264, 3016,10144, 3024,6048,
+ 3032,14240, 3040,4000, 3048,12192, 3056,8096, 3064,16288, 3080,8288, 3088,4192,
+ 3096,12384, 3112,10336, 3120,6240, 3128,14432, 3144,9312, 3152,5216, 3160,13408,
+ 3176,11360, 3184,7264, 3192,15456, 3208,8800, 3216,4704, 3224,12896, 3240,10848,
+ 3248,6752, 3256,14944, 3272,9824, 3280,5728, 3288,13920, 3296,3680, 3304,11872,
+ 3312,7776, 3320,15968, 3336,8544, 3344,4448, 3352,12640, 3368,10592, 3376,6496,
+ 3384,14688, 3400,9568, 3408,5472, 3416,13664, 3432,11616, 3440,7520, 3448,15712,
+ 3464,9056, 3472,4960, 3480,13152, 3496,11104, 3504,7008, 3512,15200, 3528,10080,
+ 3536,5984, 3544,14176, 3552,3936, 3560,12128, 3568,8032, 3576,16224, 3592,8416,
+ 3600,4320, 3608,12512, 3624,10464, 3632,6368, 3640,14560, 3656,9440, 3664,5344,
+ 3672,13536, 3688,11488, 3696,7392, 3704,15584, 3720,8928, 3728,4832, 3736,13024,
+ 3752,10976, 3760,6880, 3768,15072, 3784,9952, 3792,5856, 3800,14048, 3816,12000,
+ 3824,7904, 3832,16096, 3848,8672, 3856,4576, 3864,12768, 3880,10720, 3888,6624,
+ 3896,14816, 3912,9696, 3920,5600, 3928,13792, 3944,11744, 3952,7648, 3960,15840,
+ 3976,9184, 3984,5088, 3992,13280, 4008,11232, 4016,7136, 4024,15328, 4040,10208,
+ 4048,6112, 4056,14304, 4072,12256, 4080,8160, 4088,16352, 4104,8208, 4120,12304,
+ 4136,10256, 4144,6160, 4152,14352, 4168,9232, 4176,5136, 4184,13328, 4200,11280,
+ 4208,7184, 4216,15376, 4232,8720, 4240,4624, 4248,12816, 4264,10768, 4272,6672,
+ 4280,14864, 4296,9744, 4304,5648, 4312,13840, 4328,11792, 4336,7696, 4344,15888,
+ 4360,8464, 4376,12560, 4392,10512, 4400,6416, 4408,14608, 4424,9488, 4432,5392,
+ 4440,13584, 4456,11536, 4464,7440, 4472,15632, 4488,8976, 4496,4880, 4504,13072,
+ 4520,11024, 4528,6928, 4536,15120, 4552,10000, 4560,5904, 4568,14096,
+ 4584,12048, 4592,7952, 4600,16144, 4616,8336, 4632,12432, 4648,10384, 4656,6288,
+ 4664,14480, 4680,9360, 4688,5264, 4696,13456, 4712,11408, 4720,7312, 4728,15504,
+ 4744,8848, 4760,12944, 4776,10896, 4784,6800, 4792,14992, 4808,9872, 4816,5776,
+ 4824,13968, 4840,11920, 4848,7824, 4856,16016, 4872,8592, 4888,12688,
+ 4904,10640, 4912,6544, 4920,14736, 4936,9616, 4944,5520, 4952,13712, 4968,11664,
+ 4976,7568, 4984,15760, 5000,9104, 5016,13200, 5032,11152, 5040,7056, 5048,15248,
+ 5064,10128, 5072,6032, 5080,14224, 5096,12176, 5104,8080, 5112,16272, 5128,8272,
+ 5144,12368, 5160,10320, 5168,6224, 5176,14416, 5192,9296, 5208,13392,
+ 5224,11344, 5232,7248, 5240,15440, 5256,8784, 5272,12880, 5288,10832, 5296,6736,
+ 5304,14928, 5320,9808, 5328,5712, 5336,13904, 5352,11856, 5360,7760, 5368,15952,
+ 5384,8528, 5400,12624, 5416,10576, 5424,6480, 5432,14672, 5448,9552, 5464,13648,
+ 5480,11600, 5488,7504, 5496,15696, 5512,9040, 5528,13136, 5544,11088, 5552,6992,
+ 5560,15184, 5576,10064, 5584,5968, 5592,14160, 5608,12112, 5616,8016,
+ 5624,16208, 5640,8400, 5656,12496, 5672,10448, 5680,6352, 5688,14544, 5704,9424,
+ 5720,13520, 5736,11472, 5744,7376, 5752,15568, 5768,8912, 5784,13008,
+ 5800,10960, 5808,6864, 5816,15056, 5832,9936, 5848,14032, 5864,11984, 5872,7888,
+ 5880,16080, 5896,8656, 5912,12752, 5928,10704, 5936,6608, 5944,14800, 5960,9680,
+ 5976,13776, 5992,11728, 6000,7632, 6008,15824, 6024,9168, 6040,13264,
+ 6056,11216, 6064,7120, 6072,15312, 6088,10192, 6104,14288, 6120,12240,
+ 6128,8144, 6136,16336, 6152,8240, 6168,12336, 6184,10288, 6200,14384, 6216,9264,
+ 6232,13360, 6248,11312, 6256,7216, 6264,15408, 6280,8752, 6296,12848,
+ 6312,10800, 6320,6704, 6328,14896, 6344,9776, 6360,13872, 6376,11824, 6384,7728,
+ 6392,15920, 6408,8496, 6424,12592, 6440,10544, 6456,14640, 6472,9520,
+ 6488,13616, 6504,11568, 6512,7472, 6520,15664, 6536,9008, 6552,13104,
+ 6568,11056, 6576,6960, 6584,15152, 6600,10032, 6616,14128, 6632,12080,
+ 6640,7984, 6648,16176, 6664,8368, 6680,12464, 6696,10416, 6712,14512, 6728,9392,
+ 6744,13488, 6760,11440, 6768,7344, 6776,15536, 6792,8880, 6808,12976,
+ 6824,10928, 6840,15024, 6856,9904, 6872,14000, 6888,11952, 6896,7856,
+ 6904,16048, 6920,8624, 6936,12720, 6952,10672, 6968,14768, 6984,9648,
+ 7000,13744, 7016,11696, 7024,7600, 7032,15792, 7048,9136, 7064,13232,
+ 7080,11184, 7096,15280, 7112,10160, 7128,14256, 7144,12208, 7152,8112,
+ 7160,16304, 7176,8304, 7192,12400, 7208,10352, 7224,14448, 7240,9328,
+ 7256,13424, 7272,11376, 7288,15472, 7304,8816, 7320,12912, 7336,10864,
+ 7352,14960, 7368,9840, 7384,13936, 7400,11888, 7408,7792, 7416,15984, 7432,8560,
+ 7448,12656, 7464,10608, 7480,14704, 7496,9584, 7512,13680, 7528,11632,
+ 7544,15728, 7560,9072, 7576,13168, 7592,11120, 7608,15216, 7624,10096,
+ 7640,14192, 7656,12144, 7664,8048, 7672,16240, 7688,8432, 7704,12528,
+ 7720,10480, 7736,14576, 7752,9456, 7768,13552, 7784,11504, 7800,15600,
+ 7816,8944, 7832,13040, 7848,10992, 7864,15088, 7880,9968, 7896,14064,
+ 7912,12016, 7928,16112, 7944,8688, 7960,12784, 7976,10736, 7992,14832,
+ 8008,9712, 8024,13808, 8040,11760, 8056,15856, 8072,9200, 8088,13296,
+ 8104,11248, 8120,15344, 8136,10224, 8152,14320, 8168,12272, 8184,16368,
+ 8216,12296, 8232,10248, 8248,14344, 8264,9224, 8280,13320, 8296,11272,
+ 8312,15368, 8328,8712, 8344,12808, 8360,10760, 8376,14856, 8392,9736,
+ 8408,13832, 8424,11784, 8440,15880, 8472,12552, 8488,10504, 8504,14600,
+ 8520,9480, 8536,13576, 8552,11528, 8568,15624, 8584,8968, 8600,13064,
+ 8616,11016, 8632,15112, 8648,9992, 8664,14088, 8680,12040, 8696,16136,
+ 8728,12424, 8744,10376, 8760,14472, 8776,9352, 8792,13448, 8808,11400,
+ 8824,15496, 8856,12936, 8872,10888, 8888,14984, 8904,9864, 8920,13960,
+ 8936,11912, 8952,16008, 8984,12680, 9000,10632, 9016,14728, 9032,9608,
+ 9048,13704, 9064,11656, 9080,15752, 9112,13192, 9128,11144, 9144,15240,
+ 9160,10120, 9176,14216, 9192,12168, 9208,16264, 9240,12360, 9256,10312,
+ 9272,14408, 9304,13384, 9320,11336, 9336,15432, 9368,12872, 9384,10824,
+ 9400,14920, 9416,9800, 9432,13896, 9448,11848, 9464,15944, 9496,12616,
+ 9512,10568, 9528,14664, 9560,13640, 9576,11592, 9592,15688, 9624,13128,
+ 9640,11080, 9656,15176, 9672,10056, 9688,14152, 9704,12104, 9720,16200,
+ 9752,12488, 9768,10440, 9784,14536, 9816,13512, 9832,11464, 9848,15560,
+ 9880,13000, 9896,10952, 9912,15048, 9944,14024, 9960,11976, 9976,16072,
+ 10008,12744, 10024,10696, 10040,14792, 10072,13768, 10088,11720, 10104,15816,
+ 10136,13256, 10152,11208, 10168,15304, 10200,14280, 10216,12232, 10232,16328,
+ 10264,12328, 10296,14376, 10328,13352, 10344,11304, 10360,15400, 10392,12840,
+ 10408,10792, 10424,14888, 10456,13864, 10472,11816, 10488,15912, 10520,12584,
+ 10552,14632, 10584,13608, 10600,11560, 10616,15656, 10648,13096, 10664,11048,
+ 10680,15144, 10712,14120, 10728,12072, 10744,16168, 10776,12456, 10808,14504,
+ 10840,13480, 10856,11432, 10872,15528, 10904,12968, 10936,15016, 10968,13992,
+ 10984,11944, 11000,16040, 11032,12712, 11064,14760, 11096,13736, 11112,11688,
+ 11128,15784, 11160,13224, 11192,15272, 11224,14248, 11240,12200, 11256,16296,
+ 11288,12392, 11320,14440, 11352,13416, 11384,15464, 11416,12904, 11448,14952,
+ 11480,13928, 11496,11880, 11512,15976, 11544,12648, 11576,14696, 11608,13672,
+ 11640,15720, 11672,13160, 11704,15208, 11736,14184, 11752,12136, 11768,16232,
+ 11800,12520, 11832,14568, 11864,13544, 11896,15592, 11928,13032, 11960,15080,
+ 11992,14056, 12024,16104, 12056,12776, 12088,14824, 12120,13800, 12152,15848,
+ 12184,13288, 12216,15336, 12248,14312, 12280,16360, 12344,14360, 12376,13336,
+ 12408,15384, 12440,12824, 12472,14872, 12504,13848, 12536,15896, 12600,14616,
+ 12632,13592, 12664,15640, 12696,13080, 12728,15128, 12760,14104, 12792,16152,
+ 12856,14488, 12888,13464, 12920,15512, 12984,15000, 13016,13976, 13048,16024,
+ 13112,14744, 13144,13720, 13176,15768, 13240,15256, 13272,14232, 13304,16280,
+ 13368,14424, 13432,15448, 13496,14936, 13528,13912, 13560,15960, 13624,14680,
+ 13688,15704, 13752,15192, 13784,14168, 13816,16216, 13880,14552, 13944,15576,
+ 14008,15064, 14072,16088, 14136,14808, 14200,15832, 14264,15320, 14328,16344,
+ 14456,15416, 14520,14904, 14584,15928, 14712,15672, 14776,15160, 14840,16184,
+ 14968,15544, 15096,16056, 15224,15800, 15352,16312, 15608,15992, 15864,16248
+};
+
+const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH] =
+{
+ /* radix 4, size 4032 */
+ 8,16384, 16,8192, 24,24576, 32,4096, 40,20480, 48,12288, 56,28672, 64,2048,
+ 72,18432, 80,10240, 88,26624, 96,6144, 104,22528, 112,14336, 120,30720,
+ 128,1024, 136,17408, 144,9216, 152,25600, 160,5120, 168,21504, 176,13312,
+ 184,29696, 192,3072, 200,19456, 208,11264, 216,27648, 224,7168, 232,23552,
+ 240,15360, 248,31744, 256,512, 264,16896, 272,8704, 280,25088, 288,4608,
+ 296,20992, 304,12800, 312,29184, 320,2560, 328,18944, 336,10752, 344,27136,
+ 352,6656, 360,23040, 368,14848, 376,31232, 384,1536, 392,17920, 400,9728,
+ 408,26112, 416,5632, 424,22016, 432,13824, 440,30208, 448,3584, 456,19968,
+ 464,11776, 472,28160, 480,7680, 488,24064, 496,15872, 504,32256, 520,16640,
+ 528,8448, 536,24832, 544,4352, 552,20736, 560,12544, 568,28928, 576,2304,
+ 584,18688, 592,10496, 600,26880, 608,6400, 616,22784, 624,14592, 632,30976,
+ 640,1280, 648,17664, 656,9472, 664,25856, 672,5376, 680,21760, 688,13568,
+ 696,29952, 704,3328, 712,19712, 720,11520, 728,27904, 736,7424, 744,23808,
+ 752,15616, 760,32000, 776,17152, 784,8960, 792,25344, 800,4864, 808,21248,
+ 816,13056, 824,29440, 832,2816, 840,19200, 848,11008, 856,27392, 864,6912,
+ 872,23296, 880,15104, 888,31488, 896,1792, 904,18176, 912,9984, 920,26368,
+ 928,5888, 936,22272, 944,14080, 952,30464, 960,3840, 968,20224, 976,12032,
+ 984,28416, 992,7936, 1000,24320, 1008,16128, 1016,32512, 1032,16512, 1040,8320,
+ 1048,24704, 1056,4224, 1064,20608, 1072,12416, 1080,28800, 1088,2176,
+ 1096,18560, 1104,10368, 1112,26752, 1120,6272, 1128,22656, 1136,14464,
+ 1144,30848, 1160,17536, 1168,9344, 1176,25728, 1184,5248, 1192,21632,
+ 1200,13440, 1208,29824, 1216,3200, 1224,19584, 1232,11392, 1240,27776,
+ 1248,7296, 1256,23680, 1264,15488, 1272,31872, 1288,17024, 1296,8832,
+ 1304,25216, 1312,4736, 1320,21120, 1328,12928, 1336,29312, 1344,2688,
+ 1352,19072, 1360,10880, 1368,27264, 1376,6784, 1384,23168, 1392,14976,
+ 1400,31360, 1408,1664, 1416,18048, 1424,9856, 1432,26240, 1440,5760, 1448,22144,
+ 1456,13952, 1464,30336, 1472,3712, 1480,20096, 1488,11904, 1496,28288,
+ 1504,7808, 1512,24192, 1520,16000, 1528,32384, 1544,16768, 1552,8576,
+ 1560,24960, 1568,4480, 1576,20864, 1584,12672, 1592,29056, 1600,2432,
+ 1608,18816, 1616,10624, 1624,27008, 1632,6528, 1640,22912, 1648,14720,
+ 1656,31104, 1672,17792, 1680,9600, 1688,25984, 1696,5504, 1704,21888,
+ 1712,13696, 1720,30080, 1728,3456, 1736,19840, 1744,11648, 1752,28032,
+ 1760,7552, 1768,23936, 1776,15744, 1784,32128, 1800,17280, 1808,9088,
+ 1816,25472, 1824,4992, 1832,21376, 1840,13184, 1848,29568, 1856,2944,
+ 1864,19328, 1872,11136, 1880,27520, 1888,7040, 1896,23424, 1904,15232,
+ 1912,31616, 1928,18304, 1936,10112, 1944,26496, 1952,6016, 1960,22400,
+ 1968,14208, 1976,30592, 1984,3968, 1992,20352, 2000,12160, 2008,28544,
+ 2016,8064, 2024,24448, 2032,16256, 2040,32640, 2056,16448, 2064,8256,
+ 2072,24640, 2080,4160, 2088,20544, 2096,12352, 2104,28736, 2120,18496,
+ 2128,10304, 2136,26688, 2144,6208, 2152,22592, 2160,14400, 2168,30784,
+ 2184,17472, 2192,9280, 2200,25664, 2208,5184, 2216,21568, 2224,13376,
+ 2232,29760, 2240,3136, 2248,19520, 2256,11328, 2264,27712, 2272,7232,
+ 2280,23616, 2288,15424, 2296,31808, 2312,16960, 2320,8768, 2328,25152,
+ 2336,4672, 2344,21056, 2352,12864, 2360,29248, 2368,2624, 2376,19008,
+ 2384,10816, 2392,27200, 2400,6720, 2408,23104, 2416,14912, 2424,31296,
+ 2440,17984, 2448,9792, 2456,26176, 2464,5696, 2472,22080, 2480,13888,
+ 2488,30272, 2496,3648, 2504,20032, 2512,11840, 2520,28224, 2528,7744,
+ 2536,24128, 2544,15936, 2552,32320, 2568,16704, 2576,8512, 2584,24896,
+ 2592,4416, 2600,20800, 2608,12608, 2616,28992, 2632,18752, 2640,10560,
+ 2648,26944, 2656,6464, 2664,22848, 2672,14656, 2680,31040, 2696,17728,
+ 2704,9536, 2712,25920, 2720,5440, 2728,21824, 2736,13632, 2744,30016, 2752,3392,
+ 2760,19776, 2768,11584, 2776,27968, 2784,7488, 2792,23872, 2800,15680,
+ 2808,32064, 2824,17216, 2832,9024, 2840,25408, 2848,4928, 2856,21312,
+ 2864,13120, 2872,29504, 2888,19264, 2896,11072, 2904,27456, 2912,6976,
+ 2920,23360, 2928,15168, 2936,31552, 2952,18240, 2960,10048, 2968,26432,
+ 2976,5952, 2984,22336, 2992,14144, 3000,30528, 3008,3904, 3016,20288,
+ 3024,12096, 3032,28480, 3040,8000, 3048,24384, 3056,16192, 3064,32576,
+ 3080,16576, 3088,8384, 3096,24768, 3104,4288, 3112,20672, 3120,12480,
+ 3128,28864, 3144,18624, 3152,10432, 3160,26816, 3168,6336, 3176,22720,
+ 3184,14528, 3192,30912, 3208,17600, 3216,9408, 3224,25792, 3232,5312,
+ 3240,21696, 3248,13504, 3256,29888, 3272,19648, 3280,11456, 3288,27840,
+ 3296,7360, 3304,23744, 3312,15552, 3320,31936, 3336,17088, 3344,8896,
+ 3352,25280, 3360,4800, 3368,21184, 3376,12992, 3384,29376, 3400,19136,
+ 3408,10944, 3416,27328, 3424,6848, 3432,23232, 3440,15040, 3448,31424,
+ 3464,18112, 3472,9920, 3480,26304, 3488,5824, 3496,22208, 3504,14016,
+ 3512,30400, 3520,3776, 3528,20160, 3536,11968, 3544,28352, 3552,7872,
+ 3560,24256, 3568,16064, 3576,32448, 3592,16832, 3600,8640, 3608,25024,
+ 3616,4544, 3624,20928, 3632,12736, 3640,29120, 3656,18880, 3664,10688,
+ 3672,27072, 3680,6592, 3688,22976, 3696,14784, 3704,31168, 3720,17856,
+ 3728,9664, 3736,26048, 3744,5568, 3752,21952, 3760,13760, 3768,30144,
+ 3784,19904, 3792,11712, 3800,28096, 3808,7616, 3816,24000, 3824,15808,
+ 3832,32192, 3848,17344, 3856,9152, 3864,25536, 3872,5056, 3880,21440,
+ 3888,13248, 3896,29632, 3912,19392, 3920,11200, 3928,27584, 3936,7104,
+ 3944,23488, 3952,15296, 3960,31680, 3976,18368, 3984,10176, 3992,26560,
+ 4000,6080, 4008,22464, 4016,14272, 4024,30656, 4040,20416, 4048,12224,
+ 4056,28608, 4064,8128, 4072,24512, 4080,16320, 4088,32704, 4104,16416,
+ 4112,8224, 4120,24608, 4136,20512, 4144,12320, 4152,28704, 4168,18464,
+ 4176,10272, 4184,26656, 4192,6176, 4200,22560, 4208,14368, 4216,30752,
+ 4232,17440, 4240,9248, 4248,25632, 4256,5152, 4264,21536, 4272,13344,
+ 4280,29728, 4296,19488, 4304,11296, 4312,27680, 4320,7200, 4328,23584,
+ 4336,15392, 4344,31776, 4360,16928, 4368,8736, 4376,25120, 4384,4640,
+ 4392,21024, 4400,12832, 4408,29216, 4424,18976, 4432,10784, 4440,27168,
+ 4448,6688, 4456,23072, 4464,14880, 4472,31264, 4488,17952, 4496,9760,
+ 4504,26144, 4512,5664, 4520,22048, 4528,13856, 4536,30240, 4552,20000,
+ 4560,11808, 4568,28192, 4576,7712, 4584,24096, 4592,15904, 4600,32288,
+ 4616,16672, 4624,8480, 4632,24864, 4648,20768, 4656,12576, 4664,28960,
+ 4680,18720, 4688,10528, 4696,26912, 4704,6432, 4712,22816, 4720,14624,
+ 4728,31008, 4744,17696, 4752,9504, 4760,25888, 4768,5408, 4776,21792,
+ 4784,13600, 4792,29984, 4808,19744, 4816,11552, 4824,27936, 4832,7456,
+ 4840,23840, 4848,15648, 4856,32032, 4872,17184, 4880,8992, 4888,25376,
+ 4904,21280, 4912,13088, 4920,29472, 4936,19232, 4944,11040, 4952,27424,
+ 4960,6944, 4968,23328, 4976,15136, 4984,31520, 5000,18208, 5008,10016,
+ 5016,26400, 5024,5920, 5032,22304, 5040,14112, 5048,30496, 5064,20256,
+ 5072,12064, 5080,28448, 5088,7968, 5096,24352, 5104,16160, 5112,32544,
+ 5128,16544, 5136,8352, 5144,24736, 5160,20640, 5168,12448, 5176,28832,
+ 5192,18592, 5200,10400, 5208,26784, 5216,6304, 5224,22688, 5232,14496,
+ 5240,30880, 5256,17568, 5264,9376, 5272,25760, 5288,21664, 5296,13472,
+ 5304,29856, 5320,19616, 5328,11424, 5336,27808, 5344,7328, 5352,23712,
+ 5360,15520, 5368,31904, 5384,17056, 5392,8864, 5400,25248, 5416,21152,
+ 5424,12960, 5432,29344, 5448,19104, 5456,10912, 5464,27296, 5472,6816,
+ 5480,23200, 5488,15008, 5496,31392, 5512,18080, 5520,9888, 5528,26272,
+ 5536,5792, 5544,22176, 5552,13984, 5560,30368, 5576,20128, 5584,11936,
+ 5592,28320, 5600,7840, 5608,24224, 5616,16032, 5624,32416, 5640,16800,
+ 5648,8608, 5656,24992, 5672,20896, 5680,12704, 5688,29088, 5704,18848,
+ 5712,10656, 5720,27040, 5728,6560, 5736,22944, 5744,14752, 5752,31136,
+ 5768,17824, 5776,9632, 5784,26016, 5800,21920, 5808,13728, 5816,30112,
+ 5832,19872, 5840,11680, 5848,28064, 5856,7584, 5864,23968, 5872,15776,
+ 5880,32160, 5896,17312, 5904,9120, 5912,25504, 5928,21408, 5936,13216,
+ 5944,29600, 5960,19360, 5968,11168, 5976,27552, 5984,7072, 5992,23456,
+ 6000,15264, 6008,31648, 6024,18336, 6032,10144, 6040,26528, 6056,22432,
+ 6064,14240, 6072,30624, 6088,20384, 6096,12192, 6104,28576, 6112,8096,
+ 6120,24480, 6128,16288, 6136,32672, 6152,16480, 6160,8288, 6168,24672,
+ 6184,20576, 6192,12384, 6200,28768, 6216,18528, 6224,10336, 6232,26720,
+ 6248,22624, 6256,14432, 6264,30816, 6280,17504, 6288,9312, 6296,25696,
+ 6312,21600, 6320,13408, 6328,29792, 6344,19552, 6352,11360, 6360,27744,
+ 6368,7264, 6376,23648, 6384,15456, 6392,31840, 6408,16992, 6416,8800,
+ 6424,25184, 6440,21088, 6448,12896, 6456,29280, 6472,19040, 6480,10848,
+ 6488,27232, 6496,6752, 6504,23136, 6512,14944, 6520,31328, 6536,18016,
+ 6544,9824, 6552,26208, 6568,22112, 6576,13920, 6584,30304, 6600,20064,
+ 6608,11872, 6616,28256, 6624,7776, 6632,24160, 6640,15968, 6648,32352,
+ 6664,16736, 6672,8544, 6680,24928, 6696,20832, 6704,12640, 6712,29024,
+ 6728,18784, 6736,10592, 6744,26976, 6760,22880, 6768,14688, 6776,31072,
+ 6792,17760, 6800,9568, 6808,25952, 6824,21856, 6832,13664, 6840,30048,
+ 6856,19808, 6864,11616, 6872,28000, 6880,7520, 6888,23904, 6896,15712,
+ 6904,32096, 6920,17248, 6928,9056, 6936,25440, 6952,21344, 6960,13152,
+ 6968,29536, 6984,19296, 6992,11104, 7000,27488, 7016,23392, 7024,15200,
+ 7032,31584, 7048,18272, 7056,10080, 7064,26464, 7080,22368, 7088,14176,
+ 7096,30560, 7112,20320, 7120,12128, 7128,28512, 7136,8032, 7144,24416,
+ 7152,16224, 7160,32608, 7176,16608, 7184,8416, 7192,24800, 7208,20704,
+ 7216,12512, 7224,28896, 7240,18656, 7248,10464, 7256,26848, 7272,22752,
+ 7280,14560, 7288,30944, 7304,17632, 7312,9440, 7320,25824, 7336,21728,
+ 7344,13536, 7352,29920, 7368,19680, 7376,11488, 7384,27872, 7400,23776,
+ 7408,15584, 7416,31968, 7432,17120, 7440,8928, 7448,25312, 7464,21216,
+ 7472,13024, 7480,29408, 7496,19168, 7504,10976, 7512,27360, 7528,23264,
+ 7536,15072, 7544,31456, 7560,18144, 7568,9952, 7576,26336, 7592,22240,
+ 7600,14048, 7608,30432, 7624,20192, 7632,12000, 7640,28384, 7648,7904,
+ 7656,24288, 7664,16096, 7672,32480, 7688,16864, 7696,8672, 7704,25056,
+ 7720,20960, 7728,12768, 7736,29152, 7752,18912, 7760,10720, 7768,27104,
+ 7784,23008, 7792,14816, 7800,31200, 7816,17888, 7824,9696, 7832,26080,
+ 7848,21984, 7856,13792, 7864,30176, 7880,19936, 7888,11744, 7896,28128,
+ 7912,24032, 7920,15840, 7928,32224, 7944,17376, 7952,9184, 7960,25568,
+ 7976,21472, 7984,13280, 7992,29664, 8008,19424, 8016,11232, 8024,27616,
+ 8040,23520, 8048,15328, 8056,31712, 8072,18400, 8080,10208, 8088,26592,
+ 8104,22496, 8112,14304, 8120,30688, 8136,20448, 8144,12256, 8152,28640,
+ 8168,24544, 8176,16352, 8184,32736, 8200,16400, 8216,24592, 8232,20496,
+ 8240,12304, 8248,28688, 8264,18448, 8272,10256, 8280,26640, 8296,22544,
+ 8304,14352, 8312,30736, 8328,17424, 8336,9232, 8344,25616, 8360,21520,
+ 8368,13328, 8376,29712, 8392,19472, 8400,11280, 8408,27664, 8424,23568,
+ 8432,15376, 8440,31760, 8456,16912, 8464,8720, 8472,25104, 8488,21008,
+ 8496,12816, 8504,29200, 8520,18960, 8528,10768, 8536,27152, 8552,23056,
+ 8560,14864, 8568,31248, 8584,17936, 8592,9744, 8600,26128, 8616,22032,
+ 8624,13840, 8632,30224, 8648,19984, 8656,11792, 8664,28176, 8680,24080,
+ 8688,15888, 8696,32272, 8712,16656, 8728,24848, 8744,20752, 8752,12560,
+ 8760,28944, 8776,18704, 8784,10512, 8792,26896, 8808,22800, 8816,14608,
+ 8824,30992, 8840,17680, 8848,9488, 8856,25872, 8872,21776, 8880,13584,
+ 8888,29968, 8904,19728, 8912,11536, 8920,27920, 8936,23824, 8944,15632,
+ 8952,32016, 8968,17168, 8984,25360, 9000,21264, 9008,13072, 9016,29456,
+ 9032,19216, 9040,11024, 9048,27408, 9064,23312, 9072,15120, 9080,31504,
+ 9096,18192, 9104,10000, 9112,26384, 9128,22288, 9136,14096, 9144,30480,
+ 9160,20240, 9168,12048, 9176,28432, 9192,24336, 9200,16144, 9208,32528,
+ 9224,16528, 9240,24720, 9256,20624, 9264,12432, 9272,28816, 9288,18576,
+ 9296,10384, 9304,26768, 9320,22672, 9328,14480, 9336,30864, 9352,17552,
+ 9368,25744, 9384,21648, 9392,13456, 9400,29840, 9416,19600, 9424,11408,
+ 9432,27792, 9448,23696, 9456,15504, 9464,31888, 9480,17040, 9496,25232,
+ 9512,21136, 9520,12944, 9528,29328, 9544,19088, 9552,10896, 9560,27280,
+ 9576,23184, 9584,14992, 9592,31376, 9608,18064, 9616,9872, 9624,26256,
+ 9640,22160, 9648,13968, 9656,30352, 9672,20112, 9680,11920, 9688,28304,
+ 9704,24208, 9712,16016, 9720,32400, 9736,16784, 9752,24976, 9768,20880,
+ 9776,12688, 9784,29072, 9800,18832, 9808,10640, 9816,27024, 9832,22928,
+ 9840,14736, 9848,31120, 9864,17808, 9880,26000, 9896,21904, 9904,13712,
+ 9912,30096, 9928,19856, 9936,11664, 9944,28048, 9960,23952, 9968,15760,
+ 9976,32144, 9992,17296, 10008,25488, 10024,21392, 10032,13200, 10040,29584,
+ 10056,19344, 10064,11152, 10072,27536, 10088,23440, 10096,15248, 10104,31632,
+ 10120,18320, 10136,26512, 10152,22416, 10160,14224, 10168,30608, 10184,20368,
+ 10192,12176, 10200,28560, 10216,24464, 10224,16272, 10232,32656, 10248,16464,
+ 10264,24656, 10280,20560, 10288,12368, 10296,28752, 10312,18512, 10328,26704,
+ 10344,22608, 10352,14416, 10360,30800, 10376,17488, 10392,25680, 10408,21584,
+ 10416,13392, 10424,29776, 10440,19536, 10448,11344, 10456,27728, 10472,23632,
+ 10480,15440, 10488,31824, 10504,16976, 10520,25168, 10536,21072, 10544,12880,
+ 10552,29264, 10568,19024, 10576,10832, 10584,27216, 10600,23120, 10608,14928,
+ 10616,31312, 10632,18000, 10648,26192, 10664,22096, 10672,13904, 10680,30288,
+ 10696,20048, 10704,11856, 10712,28240, 10728,24144, 10736,15952, 10744,32336,
+ 10760,16720, 10776,24912, 10792,20816, 10800,12624, 10808,29008, 10824,18768,
+ 10840,26960, 10856,22864, 10864,14672, 10872,31056, 10888,17744, 10904,25936,
+ 10920,21840, 10928,13648, 10936,30032, 10952,19792, 10960,11600, 10968,27984,
+ 10984,23888, 10992,15696, 11000,32080, 11016,17232, 11032,25424, 11048,21328,
+ 11056,13136, 11064,29520, 11080,19280, 11096,27472, 11112,23376, 11120,15184,
+ 11128,31568, 11144,18256, 11160,26448, 11176,22352, 11184,14160, 11192,30544,
+ 11208,20304, 11216,12112, 11224,28496, 11240,24400, 11248,16208, 11256,32592,
+ 11272,16592, 11288,24784, 11304,20688, 11312,12496, 11320,28880, 11336,18640,
+ 11352,26832, 11368,22736, 11376,14544, 11384,30928, 11400,17616, 11416,25808,
+ 11432,21712, 11440,13520, 11448,29904, 11464,19664, 11480,27856, 11496,23760,
+ 11504,15568, 11512,31952, 11528,17104, 11544,25296, 11560,21200, 11568,13008,
+ 11576,29392, 11592,19152, 11608,27344, 11624,23248, 11632,15056, 11640,31440,
+ 11656,18128, 11672,26320, 11688,22224, 11696,14032, 11704,30416, 11720,20176,
+ 11728,11984, 11736,28368, 11752,24272, 11760,16080, 11768,32464, 11784,16848,
+ 11800,25040, 11816,20944, 11824,12752, 11832,29136, 11848,18896, 11864,27088,
+ 11880,22992, 11888,14800, 11896,31184, 11912,17872, 11928,26064, 11944,21968,
+ 11952,13776, 11960,30160, 11976,19920, 11992,28112, 12008,24016, 12016,15824,
+ 12024,32208, 12040,17360, 12056,25552, 12072,21456, 12080,13264, 12088,29648,
+ 12104,19408, 12120,27600, 12136,23504, 12144,15312, 12152,31696, 12168,18384,
+ 12184,26576, 12200,22480, 12208,14288, 12216,30672, 12232,20432, 12248,28624,
+ 12264,24528, 12272,16336, 12280,32720, 12296,16432, 12312,24624, 12328,20528,
+ 12344,28720, 12360,18480, 12376,26672, 12392,22576, 12400,14384, 12408,30768,
+ 12424,17456, 12440,25648, 12456,21552, 12464,13360, 12472,29744, 12488,19504,
+ 12504,27696, 12520,23600, 12528,15408, 12536,31792, 12552,16944, 12568,25136,
+ 12584,21040, 12592,12848, 12600,29232, 12616,18992, 12632,27184, 12648,23088,
+ 12656,14896, 12664,31280, 12680,17968, 12696,26160, 12712,22064, 12720,13872,
+ 12728,30256, 12744,20016, 12760,28208, 12776,24112, 12784,15920, 12792,32304,
+ 12808,16688, 12824,24880, 12840,20784, 12856,28976, 12872,18736, 12888,26928,
+ 12904,22832, 12912,14640, 12920,31024, 12936,17712, 12952,25904, 12968,21808,
+ 12976,13616, 12984,30000, 13000,19760, 13016,27952, 13032,23856, 13040,15664,
+ 13048,32048, 13064,17200, 13080,25392, 13096,21296, 13112,29488, 13128,19248,
+ 13144,27440, 13160,23344, 13168,15152, 13176,31536, 13192,18224, 13208,26416,
+ 13224,22320, 13232,14128, 13240,30512, 13256,20272, 13272,28464, 13288,24368,
+ 13296,16176, 13304,32560, 13320,16560, 13336,24752, 13352,20656, 13368,28848,
+ 13384,18608, 13400,26800, 13416,22704, 13424,14512, 13432,30896, 13448,17584,
+ 13464,25776, 13480,21680, 13496,29872, 13512,19632, 13528,27824, 13544,23728,
+ 13552,15536, 13560,31920, 13576,17072, 13592,25264, 13608,21168, 13624,29360,
+ 13640,19120, 13656,27312, 13672,23216, 13680,15024, 13688,31408, 13704,18096,
+ 13720,26288, 13736,22192, 13744,14000, 13752,30384, 13768,20144, 13784,28336,
+ 13800,24240, 13808,16048, 13816,32432, 13832,16816, 13848,25008, 13864,20912,
+ 13880,29104, 13896,18864, 13912,27056, 13928,22960, 13936,14768, 13944,31152,
+ 13960,17840, 13976,26032, 13992,21936, 14008,30128, 14024,19888, 14040,28080,
+ 14056,23984, 14064,15792, 14072,32176, 14088,17328, 14104,25520, 14120,21424,
+ 14136,29616, 14152,19376, 14168,27568, 14184,23472, 14192,15280, 14200,31664,
+ 14216,18352, 14232,26544, 14248,22448, 14264,30640, 14280,20400, 14296,28592,
+ 14312,24496, 14320,16304, 14328,32688, 14344,16496, 14360,24688, 14376,20592,
+ 14392,28784, 14408,18544, 14424,26736, 14440,22640, 14456,30832, 14472,17520,
+ 14488,25712, 14504,21616, 14520,29808, 14536,19568, 14552,27760, 14568,23664,
+ 14576,15472, 14584,31856, 14600,17008, 14616,25200, 14632,21104, 14648,29296,
+ 14664,19056, 14680,27248, 14696,23152, 14704,14960, 14712,31344, 14728,18032,
+ 14744,26224, 14760,22128, 14776,30320, 14792,20080, 14808,28272, 14824,24176,
+ 14832,15984, 14840,32368, 14856,16752, 14872,24944, 14888,20848, 14904,29040,
+ 14920,18800, 14936,26992, 14952,22896, 14968,31088, 14984,17776, 15000,25968,
+ 15016,21872, 15032,30064, 15048,19824, 15064,28016, 15080,23920, 15088,15728,
+ 15096,32112, 15112,17264, 15128,25456, 15144,21360, 15160,29552, 15176,19312,
+ 15192,27504, 15208,23408, 15224,31600, 15240,18288, 15256,26480, 15272,22384,
+ 15288,30576, 15304,20336, 15320,28528, 15336,24432, 15344,16240, 15352,32624,
+ 15368,16624, 15384,24816, 15400,20720, 15416,28912, 15432,18672, 15448,26864,
+ 15464,22768, 15480,30960, 15496,17648, 15512,25840, 15528,21744, 15544,29936,
+ 15560,19696, 15576,27888, 15592,23792, 15608,31984, 15624,17136, 15640,25328,
+ 15656,21232, 15672,29424, 15688,19184, 15704,27376, 15720,23280, 15736,31472,
+ 15752,18160, 15768,26352, 15784,22256, 15800,30448, 15816,20208, 15832,28400,
+ 15848,24304, 15856,16112, 15864,32496, 15880,16880, 15896,25072, 15912,20976,
+ 15928,29168, 15944,18928, 15960,27120, 15976,23024, 15992,31216, 16008,17904,
+ 16024,26096, 16040,22000, 16056,30192, 16072,19952, 16088,28144, 16104,24048,
+ 16120,32240, 16136,17392, 16152,25584, 16168,21488, 16184,29680, 16200,19440,
+ 16216,27632, 16232,23536, 16248,31728, 16264,18416, 16280,26608, 16296,22512,
+ 16312,30704, 16328,20464, 16344,28656, 16360,24560, 16376,32752, 16408,24584,
+ 16424,20488, 16440,28680, 16456,18440, 16472,26632, 16488,22536, 16504,30728,
+ 16520,17416, 16536,25608, 16552,21512, 16568,29704, 16584,19464, 16600,27656,
+ 16616,23560, 16632,31752, 16648,16904, 16664,25096, 16680,21000, 16696,29192,
+ 16712,18952, 16728,27144, 16744,23048, 16760,31240, 16776,17928, 16792,26120,
+ 16808,22024, 16824,30216, 16840,19976, 16856,28168, 16872,24072, 16888,32264,
+ 16920,24840, 16936,20744, 16952,28936, 16968,18696, 16984,26888, 17000,22792,
+ 17016,30984, 17032,17672, 17048,25864, 17064,21768, 17080,29960, 17096,19720,
+ 17112,27912, 17128,23816, 17144,32008, 17176,25352, 17192,21256, 17208,29448,
+ 17224,19208, 17240,27400, 17256,23304, 17272,31496, 17288,18184, 17304,26376,
+ 17320,22280, 17336,30472, 17352,20232, 17368,28424, 17384,24328, 17400,32520,
+ 17432,24712, 17448,20616, 17464,28808, 17480,18568, 17496,26760, 17512,22664,
+ 17528,30856, 17560,25736, 17576,21640, 17592,29832, 17608,19592, 17624,27784,
+ 17640,23688, 17656,31880, 17688,25224, 17704,21128, 17720,29320, 17736,19080,
+ 17752,27272, 17768,23176, 17784,31368, 17800,18056, 17816,26248, 17832,22152,
+ 17848,30344, 17864,20104, 17880,28296, 17896,24200, 17912,32392, 17944,24968,
+ 17960,20872, 17976,29064, 17992,18824, 18008,27016, 18024,22920, 18040,31112,
+ 18072,25992, 18088,21896, 18104,30088, 18120,19848, 18136,28040, 18152,23944,
+ 18168,32136, 18200,25480, 18216,21384, 18232,29576, 18248,19336, 18264,27528,
+ 18280,23432, 18296,31624, 18328,26504, 18344,22408, 18360,30600, 18376,20360,
+ 18392,28552, 18408,24456, 18424,32648, 18456,24648, 18472,20552, 18488,28744,
+ 18520,26696, 18536,22600, 18552,30792, 18584,25672, 18600,21576, 18616,29768,
+ 18632,19528, 18648,27720, 18664,23624, 18680,31816, 18712,25160, 18728,21064,
+ 18744,29256, 18760,19016, 18776,27208, 18792,23112, 18808,31304, 18840,26184,
+ 18856,22088, 18872,30280, 18888,20040, 18904,28232, 18920,24136, 18936,32328,
+ 18968,24904, 18984,20808, 19000,29000, 19032,26952, 19048,22856, 19064,31048,
+ 19096,25928, 19112,21832, 19128,30024, 19144,19784, 19160,27976, 19176,23880,
+ 19192,32072, 19224,25416, 19240,21320, 19256,29512, 19288,27464, 19304,23368,
+ 19320,31560, 19352,26440, 19368,22344, 19384,30536, 19400,20296, 19416,28488,
+ 19432,24392, 19448,32584, 19480,24776, 19496,20680, 19512,28872, 19544,26824,
+ 19560,22728, 19576,30920, 19608,25800, 19624,21704, 19640,29896, 19672,27848,
+ 19688,23752, 19704,31944, 19736,25288, 19752,21192, 19768,29384, 19800,27336,
+ 19816,23240, 19832,31432, 19864,26312, 19880,22216, 19896,30408, 19912,20168,
+ 19928,28360, 19944,24264, 19960,32456, 19992,25032, 20008,20936, 20024,29128,
+ 20056,27080, 20072,22984, 20088,31176, 20120,26056, 20136,21960, 20152,30152,
+ 20184,28104, 20200,24008, 20216,32200, 20248,25544, 20264,21448, 20280,29640,
+ 20312,27592, 20328,23496, 20344,31688, 20376,26568, 20392,22472, 20408,30664,
+ 20440,28616, 20456,24520, 20472,32712, 20504,24616, 20536,28712, 20568,26664,
+ 20584,22568, 20600,30760, 20632,25640, 20648,21544, 20664,29736, 20696,27688,
+ 20712,23592, 20728,31784, 20760,25128, 20776,21032, 20792,29224, 20824,27176,
+ 20840,23080, 20856,31272, 20888,26152, 20904,22056, 20920,30248, 20952,28200,
+ 20968,24104, 20984,32296, 21016,24872, 21048,28968, 21080,26920, 21096,22824,
+ 21112,31016, 21144,25896, 21160,21800, 21176,29992, 21208,27944, 21224,23848,
+ 21240,32040, 21272,25384, 21304,29480, 21336,27432, 21352,23336, 21368,31528,
+ 21400,26408, 21416,22312, 21432,30504, 21464,28456, 21480,24360, 21496,32552,
+ 21528,24744, 21560,28840, 21592,26792, 21608,22696, 21624,30888, 21656,25768,
+ 21688,29864, 21720,27816, 21736,23720, 21752,31912, 21784,25256, 21816,29352,
+ 21848,27304, 21864,23208, 21880,31400, 21912,26280, 21928,22184, 21944,30376,
+ 21976,28328, 21992,24232, 22008,32424, 22040,25000, 22072,29096, 22104,27048,
+ 22120,22952, 22136,31144, 22168,26024, 22200,30120, 22232,28072, 22248,23976,
+ 22264,32168, 22296,25512, 22328,29608, 22360,27560, 22376,23464, 22392,31656,
+ 22424,26536, 22456,30632, 22488,28584, 22504,24488, 22520,32680, 22552,24680,
+ 22584,28776, 22616,26728, 22648,30824, 22680,25704, 22712,29800, 22744,27752,
+ 22760,23656, 22776,31848, 22808,25192, 22840,29288, 22872,27240, 22888,23144,
+ 22904,31336, 22936,26216, 22968,30312, 23000,28264, 23016,24168, 23032,32360,
+ 23064,24936, 23096,29032, 23128,26984, 23160,31080, 23192,25960, 23224,30056,
+ 23256,28008, 23272,23912, 23288,32104, 23320,25448, 23352,29544, 23384,27496,
+ 23416,31592, 23448,26472, 23480,30568, 23512,28520, 23528,24424, 23544,32616,
+ 23576,24808, 23608,28904, 23640,26856, 23672,30952, 23704,25832, 23736,29928,
+ 23768,27880, 23800,31976, 23832,25320, 23864,29416, 23896,27368, 23928,31464,
+ 23960,26344, 23992,30440, 24024,28392, 24040,24296, 24056,32488, 24088,25064,
+ 24120,29160, 24152,27112, 24184,31208, 24216,26088, 24248,30184, 24280,28136,
+ 24312,32232, 24344,25576, 24376,29672, 24408,27624, 24440,31720, 24472,26600,
+ 24504,30696, 24536,28648, 24568,32744, 24632,28696, 24664,26648, 24696,30744,
+ 24728,25624, 24760,29720, 24792,27672, 24824,31768, 24856,25112, 24888,29208,
+ 24920,27160, 24952,31256, 24984,26136, 25016,30232, 25048,28184, 25080,32280,
+ 25144,28952, 25176,26904, 25208,31000, 25240,25880, 25272,29976, 25304,27928,
+ 25336,32024, 25400,29464, 25432,27416, 25464,31512, 25496,26392, 25528,30488,
+ 25560,28440, 25592,32536, 25656,28824, 25688,26776, 25720,30872, 25784,29848,
+ 25816,27800, 25848,31896, 25912,29336, 25944,27288, 25976,31384, 26008,26264,
+ 26040,30360, 26072,28312, 26104,32408, 26168,29080, 26200,27032, 26232,31128,
+ 26296,30104, 26328,28056, 26360,32152, 26424,29592, 26456,27544, 26488,31640,
+ 26552,30616, 26584,28568, 26616,32664, 26680,28760, 26744,30808, 26808,29784,
+ 26840,27736, 26872,31832, 26936,29272, 26968,27224, 27000,31320, 27064,30296,
+ 27096,28248, 27128,32344, 27192,29016, 27256,31064, 27320,30040, 27352,27992,
+ 27384,32088, 27448,29528, 27512,31576, 27576,30552, 27608,28504, 27640,32600,
+ 27704,28888, 27768,30936, 27832,29912, 27896,31960, 27960,29400, 28024,31448,
+ 28088,30424, 28120,28376, 28152,32472, 28216,29144, 28280,31192, 28344,30168,
+ 28408,32216, 28472,29656, 28536,31704, 28600,30680, 28664,32728, 28792,30776,
+ 28856,29752, 28920,31800, 28984,29240, 29048,31288, 29112,30264, 29176,32312,
+ 29304,31032, 29368,30008, 29432,32056, 29560,31544, 29624,30520, 29688,32568,
+ 29816,30904, 29944,31928, 30072,31416, 30136,30392, 30200,32440, 30328,31160,
+ 30456,32184, 30584,31672, 30712,32696, 30968,31864, 31096,31352, 31224,32376,
+ 31480,32120, 31736,32632, 32248,32504
+};
+
+/**
+* \par
+* Example code for Floating-point RFFT Twiddle factors Generation:
+* \par
+* <pre>TW = exp(2*pi*i*[0:L/2-1]/L - pi/2*i).' </pre>
+* \par
+* Real and Imag values are in interleaved fashion
+*/
+const float32_t twiddleCoef_rfft_32[32] = {
+ 0.000000000f, 1.000000000f,
+ 0.195090322f, 0.980785280f,
+ 0.382683432f, 0.923879533f,
+ 0.555570233f, 0.831469612f,
+ 0.707106781f, 0.707106781f,
+ 0.831469612f, 0.555570233f,
+ 0.923879533f, 0.382683432f,
+ 0.980785280f, 0.195090322f,
+ 1.000000000f, 0.000000000f,
+ 0.980785280f, -0.195090322f,
+ 0.923879533f, -0.382683432f,
+ 0.831469612f, -0.555570233f,
+ 0.707106781f, -0.707106781f,
+ 0.555570233f, -0.831469612f,
+ 0.382683432f, -0.923879533f,
+ 0.195090322f, -0.980785280f
+};
+
+const float32_t twiddleCoef_rfft_64[64] = {
+ 0.000000000000000f, 1.000000000000000f,
+ 0.098017140329561f, 0.995184726672197f,
+ 0.195090322016128f, 0.980785280403230f,
+ 0.290284677254462f, 0.956940335732209f,
+ 0.382683432365090f, 0.923879532511287f,
+ 0.471396736825998f, 0.881921264348355f,
+ 0.555570233019602f, 0.831469612302545f,
+ 0.634393284163645f, 0.773010453362737f,
+ 0.707106781186547f, 0.707106781186548f,
+ 0.773010453362737f, 0.634393284163645f,
+ 0.831469612302545f, 0.555570233019602f,
+ 0.881921264348355f, 0.471396736825998f,
+ 0.923879532511287f, 0.382683432365090f,
+ 0.956940335732209f, 0.290284677254462f,
+ 0.980785280403230f, 0.195090322016128f,
+ 0.995184726672197f, 0.098017140329561f,
+ 1.000000000000000f, 0.000000000000000f,
+ 0.995184726672197f, -0.098017140329561f,
+ 0.980785280403230f, -0.195090322016128f,
+ 0.956940335732209f, -0.290284677254462f,
+ 0.923879532511287f, -0.382683432365090f,
+ 0.881921264348355f, -0.471396736825998f,
+ 0.831469612302545f, -0.555570233019602f,
+ 0.773010453362737f, -0.634393284163645f,
+ 0.707106781186548f, -0.707106781186547f,
+ 0.634393284163645f, -0.773010453362737f,
+ 0.555570233019602f, -0.831469612302545f,
+ 0.471396736825998f, -0.881921264348355f,
+ 0.382683432365090f, -0.923879532511287f,
+ 0.290284677254462f, -0.956940335732209f,
+ 0.195090322016129f, -0.980785280403230f,
+ 0.098017140329561f, -0.995184726672197f
+};
+
+const float32_t twiddleCoef_rfft_128[128] = {
+ 0.000000000f, 1.000000000f,
+ 0.049067674f, 0.998795456f,
+ 0.098017140f, 0.995184727f,
+ 0.146730474f, 0.989176510f,
+ 0.195090322f, 0.980785280f,
+ 0.242980180f, 0.970031253f,
+ 0.290284677f, 0.956940336f,
+ 0.336889853f, 0.941544065f,
+ 0.382683432f, 0.923879533f,
+ 0.427555093f, 0.903989293f,
+ 0.471396737f, 0.881921264f,
+ 0.514102744f, 0.857728610f,
+ 0.555570233f, 0.831469612f,
+ 0.595699304f, 0.803207531f,
+ 0.634393284f, 0.773010453f,
+ 0.671558955f, 0.740951125f,
+ 0.707106781f, 0.707106781f,
+ 0.740951125f, 0.671558955f,
+ 0.773010453f, 0.634393284f,
+ 0.803207531f, 0.595699304f,
+ 0.831469612f, 0.555570233f,
+ 0.857728610f, 0.514102744f,
+ 0.881921264f, 0.471396737f,
+ 0.903989293f, 0.427555093f,
+ 0.923879533f, 0.382683432f,
+ 0.941544065f, 0.336889853f,
+ 0.956940336f, 0.290284677f,
+ 0.970031253f, 0.242980180f,
+ 0.980785280f, 0.195090322f,
+ 0.989176510f, 0.146730474f,
+ 0.995184727f, 0.098017140f,
+ 0.998795456f, 0.049067674f,
+ 1.000000000f, 0.000000000f,
+ 0.998795456f, -0.049067674f,
+ 0.995184727f, -0.098017140f,
+ 0.989176510f, -0.146730474f,
+ 0.980785280f, -0.195090322f,
+ 0.970031253f, -0.242980180f,
+ 0.956940336f, -0.290284677f,
+ 0.941544065f, -0.336889853f,
+ 0.923879533f, -0.382683432f,
+ 0.903989293f, -0.427555093f,
+ 0.881921264f, -0.471396737f,
+ 0.857728610f, -0.514102744f,
+ 0.831469612f, -0.555570233f,
+ 0.803207531f, -0.595699304f,
+ 0.773010453f, -0.634393284f,
+ 0.740951125f, -0.671558955f,
+ 0.707106781f, -0.707106781f,
+ 0.671558955f, -0.740951125f,
+ 0.634393284f, -0.773010453f,
+ 0.595699304f, -0.803207531f,
+ 0.555570233f, -0.831469612f,
+ 0.514102744f, -0.857728610f,
+ 0.471396737f, -0.881921264f,
+ 0.427555093f, -0.903989293f,
+ 0.382683432f, -0.923879533f,
+ 0.336889853f, -0.941544065f,
+ 0.290284677f, -0.956940336f,
+ 0.242980180f, -0.970031253f,
+ 0.195090322f, -0.980785280f,
+ 0.146730474f, -0.989176510f,
+ 0.098017140f, -0.995184727f,
+ 0.049067674f, -0.998795456f
+};
+
+const float32_t twiddleCoef_rfft_256[256] = {
+ 0.000000000f, 1.000000000f,
+ 0.024541229f, 0.999698819f,
+ 0.049067674f, 0.998795456f,
+ 0.073564564f, 0.997290457f,
+ 0.098017140f, 0.995184727f,
+ 0.122410675f, 0.992479535f,
+ 0.146730474f, 0.989176510f,
+ 0.170961889f, 0.985277642f,
+ 0.195090322f, 0.980785280f,
+ 0.219101240f, 0.975702130f,
+ 0.242980180f, 0.970031253f,
+ 0.266712757f, 0.963776066f,
+ 0.290284677f, 0.956940336f,
+ 0.313681740f, 0.949528181f,
+ 0.336889853f, 0.941544065f,
+ 0.359895037f, 0.932992799f,
+ 0.382683432f, 0.923879533f,
+ 0.405241314f, 0.914209756f,
+ 0.427555093f, 0.903989293f,
+ 0.449611330f, 0.893224301f,
+ 0.471396737f, 0.881921264f,
+ 0.492898192f, 0.870086991f,
+ 0.514102744f, 0.857728610f,
+ 0.534997620f, 0.844853565f,
+ 0.555570233f, 0.831469612f,
+ 0.575808191f, 0.817584813f,
+ 0.595699304f, 0.803207531f,
+ 0.615231591f, 0.788346428f,
+ 0.634393284f, 0.773010453f,
+ 0.653172843f, 0.757208847f,
+ 0.671558955f, 0.740951125f,
+ 0.689540545f, 0.724247083f,
+ 0.707106781f, 0.707106781f,
+ 0.724247083f, 0.689540545f,
+ 0.740951125f, 0.671558955f,
+ 0.757208847f, 0.653172843f,
+ 0.773010453f, 0.634393284f,
+ 0.788346428f, 0.615231591f,
+ 0.803207531f, 0.595699304f,
+ 0.817584813f, 0.575808191f,
+ 0.831469612f, 0.555570233f,
+ 0.844853565f, 0.534997620f,
+ 0.857728610f, 0.514102744f,
+ 0.870086991f, 0.492898192f,
+ 0.881921264f, 0.471396737f,
+ 0.893224301f, 0.449611330f,
+ 0.903989293f, 0.427555093f,
+ 0.914209756f, 0.405241314f,
+ 0.923879533f, 0.382683432f,
+ 0.932992799f, 0.359895037f,
+ 0.941544065f, 0.336889853f,
+ 0.949528181f, 0.313681740f,
+ 0.956940336f, 0.290284677f,
+ 0.963776066f, 0.266712757f,
+ 0.970031253f, 0.242980180f,
+ 0.975702130f, 0.219101240f,
+ 0.980785280f, 0.195090322f,
+ 0.985277642f, 0.170961889f,
+ 0.989176510f, 0.146730474f,
+ 0.992479535f, 0.122410675f,
+ 0.995184727f, 0.098017140f,
+ 0.997290457f, 0.073564564f,
+ 0.998795456f, 0.049067674f,
+ 0.999698819f, 0.024541229f,
+ 1.000000000f, 0.000000000f,
+ 0.999698819f, -0.024541229f,
+ 0.998795456f, -0.049067674f,
+ 0.997290457f, -0.073564564f,
+ 0.995184727f, -0.098017140f,
+ 0.992479535f, -0.122410675f,
+ 0.989176510f, -0.146730474f,
+ 0.985277642f, -0.170961889f,
+ 0.980785280f, -0.195090322f,
+ 0.975702130f, -0.219101240f,
+ 0.970031253f, -0.242980180f,
+ 0.963776066f, -0.266712757f,
+ 0.956940336f, -0.290284677f,
+ 0.949528181f, -0.313681740f,
+ 0.941544065f, -0.336889853f,
+ 0.932992799f, -0.359895037f,
+ 0.923879533f, -0.382683432f,
+ 0.914209756f, -0.405241314f,
+ 0.903989293f, -0.427555093f,
+ 0.893224301f, -0.449611330f,
+ 0.881921264f, -0.471396737f,
+ 0.870086991f, -0.492898192f,
+ 0.857728610f, -0.514102744f,
+ 0.844853565f, -0.534997620f,
+ 0.831469612f, -0.555570233f,
+ 0.817584813f, -0.575808191f,
+ 0.803207531f, -0.595699304f,
+ 0.788346428f, -0.615231591f,
+ 0.773010453f, -0.634393284f,
+ 0.757208847f, -0.653172843f,
+ 0.740951125f, -0.671558955f,
+ 0.724247083f, -0.689540545f,
+ 0.707106781f, -0.707106781f,
+ 0.689540545f, -0.724247083f,
+ 0.671558955f, -0.740951125f,
+ 0.653172843f, -0.757208847f,
+ 0.634393284f, -0.773010453f,
+ 0.615231591f, -0.788346428f,
+ 0.595699304f, -0.803207531f,
+ 0.575808191f, -0.817584813f,
+ 0.555570233f, -0.831469612f,
+ 0.534997620f, -0.844853565f,
+ 0.514102744f, -0.857728610f,
+ 0.492898192f, -0.870086991f,
+ 0.471396737f, -0.881921264f,
+ 0.449611330f, -0.893224301f,
+ 0.427555093f, -0.903989293f,
+ 0.405241314f, -0.914209756f,
+ 0.382683432f, -0.923879533f,
+ 0.359895037f, -0.932992799f,
+ 0.336889853f, -0.941544065f,
+ 0.313681740f, -0.949528181f,
+ 0.290284677f, -0.956940336f,
+ 0.266712757f, -0.963776066f,
+ 0.242980180f, -0.970031253f,
+ 0.219101240f, -0.975702130f,
+ 0.195090322f, -0.980785280f,
+ 0.170961889f, -0.985277642f,
+ 0.146730474f, -0.989176510f,
+ 0.122410675f, -0.992479535f,
+ 0.098017140f, -0.995184727f,
+ 0.073564564f, -0.997290457f,
+ 0.049067674f, -0.998795456f,
+ 0.024541229f, -0.999698819f
+};
+
+const float32_t twiddleCoef_rfft_512[512] = {
+ 0.000000000f, 1.000000000f,
+ 0.012271538f, 0.999924702f,
+ 0.024541229f, 0.999698819f,
+ 0.036807223f, 0.999322385f,
+ 0.049067674f, 0.998795456f,
+ 0.061320736f, 0.998118113f,
+ 0.073564564f, 0.997290457f,
+ 0.085797312f, 0.996312612f,
+ 0.098017140f, 0.995184727f,
+ 0.110222207f, 0.993906970f,
+ 0.122410675f, 0.992479535f,
+ 0.134580709f, 0.990902635f,
+ 0.146730474f, 0.989176510f,
+ 0.158858143f, 0.987301418f,
+ 0.170961889f, 0.985277642f,
+ 0.183039888f, 0.983105487f,
+ 0.195090322f, 0.980785280f,
+ 0.207111376f, 0.978317371f,
+ 0.219101240f, 0.975702130f,
+ 0.231058108f, 0.972939952f,
+ 0.242980180f, 0.970031253f,
+ 0.254865660f, 0.966976471f,
+ 0.266712757f, 0.963776066f,
+ 0.278519689f, 0.960430519f,
+ 0.290284677f, 0.956940336f,
+ 0.302005949f, 0.953306040f,
+ 0.313681740f, 0.949528181f,
+ 0.325310292f, 0.945607325f,
+ 0.336889853f, 0.941544065f,
+ 0.348418680f, 0.937339012f,
+ 0.359895037f, 0.932992799f,
+ 0.371317194f, 0.928506080f,
+ 0.382683432f, 0.923879533f,
+ 0.393992040f, 0.919113852f,
+ 0.405241314f, 0.914209756f,
+ 0.416429560f, 0.909167983f,
+ 0.427555093f, 0.903989293f,
+ 0.438616239f, 0.898674466f,
+ 0.449611330f, 0.893224301f,
+ 0.460538711f, 0.887639620f,
+ 0.471396737f, 0.881921264f,
+ 0.482183772f, 0.876070094f,
+ 0.492898192f, 0.870086991f,
+ 0.503538384f, 0.863972856f,
+ 0.514102744f, 0.857728610f,
+ 0.524589683f, 0.851355193f,
+ 0.534997620f, 0.844853565f,
+ 0.545324988f, 0.838224706f,
+ 0.555570233f, 0.831469612f,
+ 0.565731811f, 0.824589303f,
+ 0.575808191f, 0.817584813f,
+ 0.585797857f, 0.810457198f,
+ 0.595699304f, 0.803207531f,
+ 0.605511041f, 0.795836905f,
+ 0.615231591f, 0.788346428f,
+ 0.624859488f, 0.780737229f,
+ 0.634393284f, 0.773010453f,
+ 0.643831543f, 0.765167266f,
+ 0.653172843f, 0.757208847f,
+ 0.662415778f, 0.749136395f,
+ 0.671558955f, 0.740951125f,
+ 0.680600998f, 0.732654272f,
+ 0.689540545f, 0.724247083f,
+ 0.698376249f, 0.715730825f,
+ 0.707106781f, 0.707106781f,
+ 0.715730825f, 0.698376249f,
+ 0.724247083f, 0.689540545f,
+ 0.732654272f, 0.680600998f,
+ 0.740951125f, 0.671558955f,
+ 0.749136395f, 0.662415778f,
+ 0.757208847f, 0.653172843f,
+ 0.765167266f, 0.643831543f,
+ 0.773010453f, 0.634393284f,
+ 0.780737229f, 0.624859488f,
+ 0.788346428f, 0.615231591f,
+ 0.795836905f, 0.605511041f,
+ 0.803207531f, 0.595699304f,
+ 0.810457198f, 0.585797857f,
+ 0.817584813f, 0.575808191f,
+ 0.824589303f, 0.565731811f,
+ 0.831469612f, 0.555570233f,
+ 0.838224706f, 0.545324988f,
+ 0.844853565f, 0.534997620f,
+ 0.851355193f, 0.524589683f,
+ 0.857728610f, 0.514102744f,
+ 0.863972856f, 0.503538384f,
+ 0.870086991f, 0.492898192f,
+ 0.876070094f, 0.482183772f,
+ 0.881921264f, 0.471396737f,
+ 0.887639620f, 0.460538711f,
+ 0.893224301f, 0.449611330f,
+ 0.898674466f, 0.438616239f,
+ 0.903989293f, 0.427555093f,
+ 0.909167983f, 0.416429560f,
+ 0.914209756f, 0.405241314f,
+ 0.919113852f, 0.393992040f,
+ 0.923879533f, 0.382683432f,
+ 0.928506080f, 0.371317194f,
+ 0.932992799f, 0.359895037f,
+ 0.937339012f, 0.348418680f,
+ 0.941544065f, 0.336889853f,
+ 0.945607325f, 0.325310292f,
+ 0.949528181f, 0.313681740f,
+ 0.953306040f, 0.302005949f,
+ 0.956940336f, 0.290284677f,
+ 0.960430519f, 0.278519689f,
+ 0.963776066f, 0.266712757f,
+ 0.966976471f, 0.254865660f,
+ 0.970031253f, 0.242980180f,
+ 0.972939952f, 0.231058108f,
+ 0.975702130f, 0.219101240f,
+ 0.978317371f, 0.207111376f,
+ 0.980785280f, 0.195090322f,
+ 0.983105487f, 0.183039888f,
+ 0.985277642f, 0.170961889f,
+ 0.987301418f, 0.158858143f,
+ 0.989176510f, 0.146730474f,
+ 0.990902635f, 0.134580709f,
+ 0.992479535f, 0.122410675f,
+ 0.993906970f, 0.110222207f,
+ 0.995184727f, 0.098017140f,
+ 0.996312612f, 0.085797312f,
+ 0.997290457f, 0.073564564f,
+ 0.998118113f, 0.061320736f,
+ 0.998795456f, 0.049067674f,
+ 0.999322385f, 0.036807223f,
+ 0.999698819f, 0.024541229f,
+ 0.999924702f, 0.012271538f,
+ 1.000000000f, 0.000000000f,
+ 0.999924702f, -0.012271538f,
+ 0.999698819f, -0.024541229f,
+ 0.999322385f, -0.036807223f,
+ 0.998795456f, -0.049067674f,
+ 0.998118113f, -0.061320736f,
+ 0.997290457f, -0.073564564f,
+ 0.996312612f, -0.085797312f,
+ 0.995184727f, -0.098017140f,
+ 0.993906970f, -0.110222207f,
+ 0.992479535f, -0.122410675f,
+ 0.990902635f, -0.134580709f,
+ 0.989176510f, -0.146730474f,
+ 0.987301418f, -0.158858143f,
+ 0.985277642f, -0.170961889f,
+ 0.983105487f, -0.183039888f,
+ 0.980785280f, -0.195090322f,
+ 0.978317371f, -0.207111376f,
+ 0.975702130f, -0.219101240f,
+ 0.972939952f, -0.231058108f,
+ 0.970031253f, -0.242980180f,
+ 0.966976471f, -0.254865660f,
+ 0.963776066f, -0.266712757f,
+ 0.960430519f, -0.278519689f,
+ 0.956940336f, -0.290284677f,
+ 0.953306040f, -0.302005949f,
+ 0.949528181f, -0.313681740f,
+ 0.945607325f, -0.325310292f,
+ 0.941544065f, -0.336889853f,
+ 0.937339012f, -0.348418680f,
+ 0.932992799f, -0.359895037f,
+ 0.928506080f, -0.371317194f,
+ 0.923879533f, -0.382683432f,
+ 0.919113852f, -0.393992040f,
+ 0.914209756f, -0.405241314f,
+ 0.909167983f, -0.416429560f,
+ 0.903989293f, -0.427555093f,
+ 0.898674466f, -0.438616239f,
+ 0.893224301f, -0.449611330f,
+ 0.887639620f, -0.460538711f,
+ 0.881921264f, -0.471396737f,
+ 0.876070094f, -0.482183772f,
+ 0.870086991f, -0.492898192f,
+ 0.863972856f, -0.503538384f,
+ 0.857728610f, -0.514102744f,
+ 0.851355193f, -0.524589683f,
+ 0.844853565f, -0.534997620f,
+ 0.838224706f, -0.545324988f,
+ 0.831469612f, -0.555570233f,
+ 0.824589303f, -0.565731811f,
+ 0.817584813f, -0.575808191f,
+ 0.810457198f, -0.585797857f,
+ 0.803207531f, -0.595699304f,
+ 0.795836905f, -0.605511041f,
+ 0.788346428f, -0.615231591f,
+ 0.780737229f, -0.624859488f,
+ 0.773010453f, -0.634393284f,
+ 0.765167266f, -0.643831543f,
+ 0.757208847f, -0.653172843f,
+ 0.749136395f, -0.662415778f,
+ 0.740951125f, -0.671558955f,
+ 0.732654272f, -0.680600998f,
+ 0.724247083f, -0.689540545f,
+ 0.715730825f, -0.698376249f,
+ 0.707106781f, -0.707106781f,
+ 0.698376249f, -0.715730825f,
+ 0.689540545f, -0.724247083f,
+ 0.680600998f, -0.732654272f,
+ 0.671558955f, -0.740951125f,
+ 0.662415778f, -0.749136395f,
+ 0.653172843f, -0.757208847f,
+ 0.643831543f, -0.765167266f,
+ 0.634393284f, -0.773010453f,
+ 0.624859488f, -0.780737229f,
+ 0.615231591f, -0.788346428f,
+ 0.605511041f, -0.795836905f,
+ 0.595699304f, -0.803207531f,
+ 0.585797857f, -0.810457198f,
+ 0.575808191f, -0.817584813f,
+ 0.565731811f, -0.824589303f,
+ 0.555570233f, -0.831469612f,
+ 0.545324988f, -0.838224706f,
+ 0.534997620f, -0.844853565f,
+ 0.524589683f, -0.851355193f,
+ 0.514102744f, -0.857728610f,
+ 0.503538384f, -0.863972856f,
+ 0.492898192f, -0.870086991f,
+ 0.482183772f, -0.876070094f,
+ 0.471396737f, -0.881921264f,
+ 0.460538711f, -0.887639620f,
+ 0.449611330f, -0.893224301f,
+ 0.438616239f, -0.898674466f,
+ 0.427555093f, -0.903989293f,
+ 0.416429560f, -0.909167983f,
+ 0.405241314f, -0.914209756f,
+ 0.393992040f, -0.919113852f,
+ 0.382683432f, -0.923879533f,
+ 0.371317194f, -0.928506080f,
+ 0.359895037f, -0.932992799f,
+ 0.348418680f, -0.937339012f,
+ 0.336889853f, -0.941544065f,
+ 0.325310292f, -0.945607325f,
+ 0.313681740f, -0.949528181f,
+ 0.302005949f, -0.953306040f,
+ 0.290284677f, -0.956940336f,
+ 0.278519689f, -0.960430519f,
+ 0.266712757f, -0.963776066f,
+ 0.254865660f, -0.966976471f,
+ 0.242980180f, -0.970031253f,
+ 0.231058108f, -0.972939952f,
+ 0.219101240f, -0.975702130f,
+ 0.207111376f, -0.978317371f,
+ 0.195090322f, -0.980785280f,
+ 0.183039888f, -0.983105487f,
+ 0.170961889f, -0.985277642f,
+ 0.158858143f, -0.987301418f,
+ 0.146730474f, -0.989176510f,
+ 0.134580709f, -0.990902635f,
+ 0.122410675f, -0.992479535f,
+ 0.110222207f, -0.993906970f,
+ 0.098017140f, -0.995184727f,
+ 0.085797312f, -0.996312612f,
+ 0.073564564f, -0.997290457f,
+ 0.061320736f, -0.998118113f,
+ 0.049067674f, -0.998795456f,
+ 0.036807223f, -0.999322385f,
+ 0.024541229f, -0.999698819f,
+ 0.012271538f, -0.999924702f
+};
+
+const float32_t twiddleCoef_rfft_1024[1024] = {
+ 0.000000000f, 1.000000000f,
+ 0.006135885f, 0.999981175f,
+ 0.012271538f, 0.999924702f,
+ 0.018406730f, 0.999830582f,
+ 0.024541229f, 0.999698819f,
+ 0.030674803f, 0.999529418f,
+ 0.036807223f, 0.999322385f,
+ 0.042938257f, 0.999077728f,
+ 0.049067674f, 0.998795456f,
+ 0.055195244f, 0.998475581f,
+ 0.061320736f, 0.998118113f,
+ 0.067443920f, 0.997723067f,
+ 0.073564564f, 0.997290457f,
+ 0.079682438f, 0.996820299f,
+ 0.085797312f, 0.996312612f,
+ 0.091908956f, 0.995767414f,
+ 0.098017140f, 0.995184727f,
+ 0.104121634f, 0.994564571f,
+ 0.110222207f, 0.993906970f,
+ 0.116318631f, 0.993211949f,
+ 0.122410675f, 0.992479535f,
+ 0.128498111f, 0.991709754f,
+ 0.134580709f, 0.990902635f,
+ 0.140658239f, 0.990058210f,
+ 0.146730474f, 0.989176510f,
+ 0.152797185f, 0.988257568f,
+ 0.158858143f, 0.987301418f,
+ 0.164913120f, 0.986308097f,
+ 0.170961889f, 0.985277642f,
+ 0.177004220f, 0.984210092f,
+ 0.183039888f, 0.983105487f,
+ 0.189068664f, 0.981963869f,
+ 0.195090322f, 0.980785280f,
+ 0.201104635f, 0.979569766f,
+ 0.207111376f, 0.978317371f,
+ 0.213110320f, 0.977028143f,
+ 0.219101240f, 0.975702130f,
+ 0.225083911f, 0.974339383f,
+ 0.231058108f, 0.972939952f,
+ 0.237023606f, 0.971503891f,
+ 0.242980180f, 0.970031253f,
+ 0.248927606f, 0.968522094f,
+ 0.254865660f, 0.966976471f,
+ 0.260794118f, 0.965394442f,
+ 0.266712757f, 0.963776066f,
+ 0.272621355f, 0.962121404f,
+ 0.278519689f, 0.960430519f,
+ 0.284407537f, 0.958703475f,
+ 0.290284677f, 0.956940336f,
+ 0.296150888f, 0.955141168f,
+ 0.302005949f, 0.953306040f,
+ 0.307849640f, 0.951435021f,
+ 0.313681740f, 0.949528181f,
+ 0.319502031f, 0.947585591f,
+ 0.325310292f, 0.945607325f,
+ 0.331106306f, 0.943593458f,
+ 0.336889853f, 0.941544065f,
+ 0.342660717f, 0.939459224f,
+ 0.348418680f, 0.937339012f,
+ 0.354163525f, 0.935183510f,
+ 0.359895037f, 0.932992799f,
+ 0.365612998f, 0.930766961f,
+ 0.371317194f, 0.928506080f,
+ 0.377007410f, 0.926210242f,
+ 0.382683432f, 0.923879533f,
+ 0.388345047f, 0.921514039f,
+ 0.393992040f, 0.919113852f,
+ 0.399624200f, 0.916679060f,
+ 0.405241314f, 0.914209756f,
+ 0.410843171f, 0.911706032f,
+ 0.416429560f, 0.909167983f,
+ 0.422000271f, 0.906595705f,
+ 0.427555093f, 0.903989293f,
+ 0.433093819f, 0.901348847f,
+ 0.438616239f, 0.898674466f,
+ 0.444122145f, 0.895966250f,
+ 0.449611330f, 0.893224301f,
+ 0.455083587f, 0.890448723f,
+ 0.460538711f, 0.887639620f,
+ 0.465976496f, 0.884797098f,
+ 0.471396737f, 0.881921264f,
+ 0.476799230f, 0.879012226f,
+ 0.482183772f, 0.876070094f,
+ 0.487550160f, 0.873094978f,
+ 0.492898192f, 0.870086991f,
+ 0.498227667f, 0.867046246f,
+ 0.503538384f, 0.863972856f,
+ 0.508830143f, 0.860866939f,
+ 0.514102744f, 0.857728610f,
+ 0.519355990f, 0.854557988f,
+ 0.524589683f, 0.851355193f,
+ 0.529803625f, 0.848120345f,
+ 0.534997620f, 0.844853565f,
+ 0.540171473f, 0.841554977f,
+ 0.545324988f, 0.838224706f,
+ 0.550457973f, 0.834862875f,
+ 0.555570233f, 0.831469612f,
+ 0.560661576f, 0.828045045f,
+ 0.565731811f, 0.824589303f,
+ 0.570780746f, 0.821102515f,
+ 0.575808191f, 0.817584813f,
+ 0.580813958f, 0.814036330f,
+ 0.585797857f, 0.810457198f,
+ 0.590759702f, 0.806847554f,
+ 0.595699304f, 0.803207531f,
+ 0.600616479f, 0.799537269f,
+ 0.605511041f, 0.795836905f,
+ 0.610382806f, 0.792106577f,
+ 0.615231591f, 0.788346428f,
+ 0.620057212f, 0.784556597f,
+ 0.624859488f, 0.780737229f,
+ 0.629638239f, 0.776888466f,
+ 0.634393284f, 0.773010453f,
+ 0.639124445f, 0.769103338f,
+ 0.643831543f, 0.765167266f,
+ 0.648514401f, 0.761202385f,
+ 0.653172843f, 0.757208847f,
+ 0.657806693f, 0.753186799f,
+ 0.662415778f, 0.749136395f,
+ 0.666999922f, 0.745057785f,
+ 0.671558955f, 0.740951125f,
+ 0.676092704f, 0.736816569f,
+ 0.680600998f, 0.732654272f,
+ 0.685083668f, 0.728464390f,
+ 0.689540545f, 0.724247083f,
+ 0.693971461f, 0.720002508f,
+ 0.698376249f, 0.715730825f,
+ 0.702754744f, 0.711432196f,
+ 0.707106781f, 0.707106781f,
+ 0.711432196f, 0.702754744f,
+ 0.715730825f, 0.698376249f,
+ 0.720002508f, 0.693971461f,
+ 0.724247083f, 0.689540545f,
+ 0.728464390f, 0.685083668f,
+ 0.732654272f, 0.680600998f,
+ 0.736816569f, 0.676092704f,
+ 0.740951125f, 0.671558955f,
+ 0.745057785f, 0.666999922f,
+ 0.749136395f, 0.662415778f,
+ 0.753186799f, 0.657806693f,
+ 0.757208847f, 0.653172843f,
+ 0.761202385f, 0.648514401f,
+ 0.765167266f, 0.643831543f,
+ 0.769103338f, 0.639124445f,
+ 0.773010453f, 0.634393284f,
+ 0.776888466f, 0.629638239f,
+ 0.780737229f, 0.624859488f,
+ 0.784556597f, 0.620057212f,
+ 0.788346428f, 0.615231591f,
+ 0.792106577f, 0.610382806f,
+ 0.795836905f, 0.605511041f,
+ 0.799537269f, 0.600616479f,
+ 0.803207531f, 0.595699304f,
+ 0.806847554f, 0.590759702f,
+ 0.810457198f, 0.585797857f,
+ 0.814036330f, 0.580813958f,
+ 0.817584813f, 0.575808191f,
+ 0.821102515f, 0.570780746f,
+ 0.824589303f, 0.565731811f,
+ 0.828045045f, 0.560661576f,
+ 0.831469612f, 0.555570233f,
+ 0.834862875f, 0.550457973f,
+ 0.838224706f, 0.545324988f,
+ 0.841554977f, 0.540171473f,
+ 0.844853565f, 0.534997620f,
+ 0.848120345f, 0.529803625f,
+ 0.851355193f, 0.524589683f,
+ 0.854557988f, 0.519355990f,
+ 0.857728610f, 0.514102744f,
+ 0.860866939f, 0.508830143f,
+ 0.863972856f, 0.503538384f,
+ 0.867046246f, 0.498227667f,
+ 0.870086991f, 0.492898192f,
+ 0.873094978f, 0.487550160f,
+ 0.876070094f, 0.482183772f,
+ 0.879012226f, 0.476799230f,
+ 0.881921264f, 0.471396737f,
+ 0.884797098f, 0.465976496f,
+ 0.887639620f, 0.460538711f,
+ 0.890448723f, 0.455083587f,
+ 0.893224301f, 0.449611330f,
+ 0.895966250f, 0.444122145f,
+ 0.898674466f, 0.438616239f,
+ 0.901348847f, 0.433093819f,
+ 0.903989293f, 0.427555093f,
+ 0.906595705f, 0.422000271f,
+ 0.909167983f, 0.416429560f,
+ 0.911706032f, 0.410843171f,
+ 0.914209756f, 0.405241314f,
+ 0.916679060f, 0.399624200f,
+ 0.919113852f, 0.393992040f,
+ 0.921514039f, 0.388345047f,
+ 0.923879533f, 0.382683432f,
+ 0.926210242f, 0.377007410f,
+ 0.928506080f, 0.371317194f,
+ 0.930766961f, 0.365612998f,
+ 0.932992799f, 0.359895037f,
+ 0.935183510f, 0.354163525f,
+ 0.937339012f, 0.348418680f,
+ 0.939459224f, 0.342660717f,
+ 0.941544065f, 0.336889853f,
+ 0.943593458f, 0.331106306f,
+ 0.945607325f, 0.325310292f,
+ 0.947585591f, 0.319502031f,
+ 0.949528181f, 0.313681740f,
+ 0.951435021f, 0.307849640f,
+ 0.953306040f, 0.302005949f,
+ 0.955141168f, 0.296150888f,
+ 0.956940336f, 0.290284677f,
+ 0.958703475f, 0.284407537f,
+ 0.960430519f, 0.278519689f,
+ 0.962121404f, 0.272621355f,
+ 0.963776066f, 0.266712757f,
+ 0.965394442f, 0.260794118f,
+ 0.966976471f, 0.254865660f,
+ 0.968522094f, 0.248927606f,
+ 0.970031253f, 0.242980180f,
+ 0.971503891f, 0.237023606f,
+ 0.972939952f, 0.231058108f,
+ 0.974339383f, 0.225083911f,
+ 0.975702130f, 0.219101240f,
+ 0.977028143f, 0.213110320f,
+ 0.978317371f, 0.207111376f,
+ 0.979569766f, 0.201104635f,
+ 0.980785280f, 0.195090322f,
+ 0.981963869f, 0.189068664f,
+ 0.983105487f, 0.183039888f,
+ 0.984210092f, 0.177004220f,
+ 0.985277642f, 0.170961889f,
+ 0.986308097f, 0.164913120f,
+ 0.987301418f, 0.158858143f,
+ 0.988257568f, 0.152797185f,
+ 0.989176510f, 0.146730474f,
+ 0.990058210f, 0.140658239f,
+ 0.990902635f, 0.134580709f,
+ 0.991709754f, 0.128498111f,
+ 0.992479535f, 0.122410675f,
+ 0.993211949f, 0.116318631f,
+ 0.993906970f, 0.110222207f,
+ 0.994564571f, 0.104121634f,
+ 0.995184727f, 0.098017140f,
+ 0.995767414f, 0.091908956f,
+ 0.996312612f, 0.085797312f,
+ 0.996820299f, 0.079682438f,
+ 0.997290457f, 0.073564564f,
+ 0.997723067f, 0.067443920f,
+ 0.998118113f, 0.061320736f,
+ 0.998475581f, 0.055195244f,
+ 0.998795456f, 0.049067674f,
+ 0.999077728f, 0.042938257f,
+ 0.999322385f, 0.036807223f,
+ 0.999529418f, 0.030674803f,
+ 0.999698819f, 0.024541229f,
+ 0.999830582f, 0.018406730f,
+ 0.999924702f, 0.012271538f,
+ 0.999981175f, 0.006135885f,
+ 1.000000000f, 0.000000000f,
+ 0.999981175f, -0.006135885f,
+ 0.999924702f, -0.012271538f,
+ 0.999830582f, -0.018406730f,
+ 0.999698819f, -0.024541229f,
+ 0.999529418f, -0.030674803f,
+ 0.999322385f, -0.036807223f,
+ 0.999077728f, -0.042938257f,
+ 0.998795456f, -0.049067674f,
+ 0.998475581f, -0.055195244f,
+ 0.998118113f, -0.061320736f,
+ 0.997723067f, -0.067443920f,
+ 0.997290457f, -0.073564564f,
+ 0.996820299f, -0.079682438f,
+ 0.996312612f, -0.085797312f,
+ 0.995767414f, -0.091908956f,
+ 0.995184727f, -0.098017140f,
+ 0.994564571f, -0.104121634f,
+ 0.993906970f, -0.110222207f,
+ 0.993211949f, -0.116318631f,
+ 0.992479535f, -0.122410675f,
+ 0.991709754f, -0.128498111f,
+ 0.990902635f, -0.134580709f,
+ 0.990058210f, -0.140658239f,
+ 0.989176510f, -0.146730474f,
+ 0.988257568f, -0.152797185f,
+ 0.987301418f, -0.158858143f,
+ 0.986308097f, -0.164913120f,
+ 0.985277642f, -0.170961889f,
+ 0.984210092f, -0.177004220f,
+ 0.983105487f, -0.183039888f,
+ 0.981963869f, -0.189068664f,
+ 0.980785280f, -0.195090322f,
+ 0.979569766f, -0.201104635f,
+ 0.978317371f, -0.207111376f,
+ 0.977028143f, -0.213110320f,
+ 0.975702130f, -0.219101240f,
+ 0.974339383f, -0.225083911f,
+ 0.972939952f, -0.231058108f,
+ 0.971503891f, -0.237023606f,
+ 0.970031253f, -0.242980180f,
+ 0.968522094f, -0.248927606f,
+ 0.966976471f, -0.254865660f,
+ 0.965394442f, -0.260794118f,
+ 0.963776066f, -0.266712757f,
+ 0.962121404f, -0.272621355f,
+ 0.960430519f, -0.278519689f,
+ 0.958703475f, -0.284407537f,
+ 0.956940336f, -0.290284677f,
+ 0.955141168f, -0.296150888f,
+ 0.953306040f, -0.302005949f,
+ 0.951435021f, -0.307849640f,
+ 0.949528181f, -0.313681740f,
+ 0.947585591f, -0.319502031f,
+ 0.945607325f, -0.325310292f,
+ 0.943593458f, -0.331106306f,
+ 0.941544065f, -0.336889853f,
+ 0.939459224f, -0.342660717f,
+ 0.937339012f, -0.348418680f,
+ 0.935183510f, -0.354163525f,
+ 0.932992799f, -0.359895037f,
+ 0.930766961f, -0.365612998f,
+ 0.928506080f, -0.371317194f,
+ 0.926210242f, -0.377007410f,
+ 0.923879533f, -0.382683432f,
+ 0.921514039f, -0.388345047f,
+ 0.919113852f, -0.393992040f,
+ 0.916679060f, -0.399624200f,
+ 0.914209756f, -0.405241314f,
+ 0.911706032f, -0.410843171f,
+ 0.909167983f, -0.416429560f,
+ 0.906595705f, -0.422000271f,
+ 0.903989293f, -0.427555093f,
+ 0.901348847f, -0.433093819f,
+ 0.898674466f, -0.438616239f,
+ 0.895966250f, -0.444122145f,
+ 0.893224301f, -0.449611330f,
+ 0.890448723f, -0.455083587f,
+ 0.887639620f, -0.460538711f,
+ 0.884797098f, -0.465976496f,
+ 0.881921264f, -0.471396737f,
+ 0.879012226f, -0.476799230f,
+ 0.876070094f, -0.482183772f,
+ 0.873094978f, -0.487550160f,
+ 0.870086991f, -0.492898192f,
+ 0.867046246f, -0.498227667f,
+ 0.863972856f, -0.503538384f,
+ 0.860866939f, -0.508830143f,
+ 0.857728610f, -0.514102744f,
+ 0.854557988f, -0.519355990f,
+ 0.851355193f, -0.524589683f,
+ 0.848120345f, -0.529803625f,
+ 0.844853565f, -0.534997620f,
+ 0.841554977f, -0.540171473f,
+ 0.838224706f, -0.545324988f,
+ 0.834862875f, -0.550457973f,
+ 0.831469612f, -0.555570233f,
+ 0.828045045f, -0.560661576f,
+ 0.824589303f, -0.565731811f,
+ 0.821102515f, -0.570780746f,
+ 0.817584813f, -0.575808191f,
+ 0.814036330f, -0.580813958f,
+ 0.810457198f, -0.585797857f,
+ 0.806847554f, -0.590759702f,
+ 0.803207531f, -0.595699304f,
+ 0.799537269f, -0.600616479f,
+ 0.795836905f, -0.605511041f,
+ 0.792106577f, -0.610382806f,
+ 0.788346428f, -0.615231591f,
+ 0.784556597f, -0.620057212f,
+ 0.780737229f, -0.624859488f,
+ 0.776888466f, -0.629638239f,
+ 0.773010453f, -0.634393284f,
+ 0.769103338f, -0.639124445f,
+ 0.765167266f, -0.643831543f,
+ 0.761202385f, -0.648514401f,
+ 0.757208847f, -0.653172843f,
+ 0.753186799f, -0.657806693f,
+ 0.749136395f, -0.662415778f,
+ 0.745057785f, -0.666999922f,
+ 0.740951125f, -0.671558955f,
+ 0.736816569f, -0.676092704f,
+ 0.732654272f, -0.680600998f,
+ 0.728464390f, -0.685083668f,
+ 0.724247083f, -0.689540545f,
+ 0.720002508f, -0.693971461f,
+ 0.715730825f, -0.698376249f,
+ 0.711432196f, -0.702754744f,
+ 0.707106781f, -0.707106781f,
+ 0.702754744f, -0.711432196f,
+ 0.698376249f, -0.715730825f,
+ 0.693971461f, -0.720002508f,
+ 0.689540545f, -0.724247083f,
+ 0.685083668f, -0.728464390f,
+ 0.680600998f, -0.732654272f,
+ 0.676092704f, -0.736816569f,
+ 0.671558955f, -0.740951125f,
+ 0.666999922f, -0.745057785f,
+ 0.662415778f, -0.749136395f,
+ 0.657806693f, -0.753186799f,
+ 0.653172843f, -0.757208847f,
+ 0.648514401f, -0.761202385f,
+ 0.643831543f, -0.765167266f,
+ 0.639124445f, -0.769103338f,
+ 0.634393284f, -0.773010453f,
+ 0.629638239f, -0.776888466f,
+ 0.624859488f, -0.780737229f,
+ 0.620057212f, -0.784556597f,
+ 0.615231591f, -0.788346428f,
+ 0.610382806f, -0.792106577f,
+ 0.605511041f, -0.795836905f,
+ 0.600616479f, -0.799537269f,
+ 0.595699304f, -0.803207531f,
+ 0.590759702f, -0.806847554f,
+ 0.585797857f, -0.810457198f,
+ 0.580813958f, -0.814036330f,
+ 0.575808191f, -0.817584813f,
+ 0.570780746f, -0.821102515f,
+ 0.565731811f, -0.824589303f,
+ 0.560661576f, -0.828045045f,
+ 0.555570233f, -0.831469612f,
+ 0.550457973f, -0.834862875f,
+ 0.545324988f, -0.838224706f,
+ 0.540171473f, -0.841554977f,
+ 0.534997620f, -0.844853565f,
+ 0.529803625f, -0.848120345f,
+ 0.524589683f, -0.851355193f,
+ 0.519355990f, -0.854557988f,
+ 0.514102744f, -0.857728610f,
+ 0.508830143f, -0.860866939f,
+ 0.503538384f, -0.863972856f,
+ 0.498227667f, -0.867046246f,
+ 0.492898192f, -0.870086991f,
+ 0.487550160f, -0.873094978f,
+ 0.482183772f, -0.876070094f,
+ 0.476799230f, -0.879012226f,
+ 0.471396737f, -0.881921264f,
+ 0.465976496f, -0.884797098f,
+ 0.460538711f, -0.887639620f,
+ 0.455083587f, -0.890448723f,
+ 0.449611330f, -0.893224301f,
+ 0.444122145f, -0.895966250f,
+ 0.438616239f, -0.898674466f,
+ 0.433093819f, -0.901348847f,
+ 0.427555093f, -0.903989293f,
+ 0.422000271f, -0.906595705f,
+ 0.416429560f, -0.909167983f,
+ 0.410843171f, -0.911706032f,
+ 0.405241314f, -0.914209756f,
+ 0.399624200f, -0.916679060f,
+ 0.393992040f, -0.919113852f,
+ 0.388345047f, -0.921514039f,
+ 0.382683432f, -0.923879533f,
+ 0.377007410f, -0.926210242f,
+ 0.371317194f, -0.928506080f,
+ 0.365612998f, -0.930766961f,
+ 0.359895037f, -0.932992799f,
+ 0.354163525f, -0.935183510f,
+ 0.348418680f, -0.937339012f,
+ 0.342660717f, -0.939459224f,
+ 0.336889853f, -0.941544065f,
+ 0.331106306f, -0.943593458f,
+ 0.325310292f, -0.945607325f,
+ 0.319502031f, -0.947585591f,
+ 0.313681740f, -0.949528181f,
+ 0.307849640f, -0.951435021f,
+ 0.302005949f, -0.953306040f,
+ 0.296150888f, -0.955141168f,
+ 0.290284677f, -0.956940336f,
+ 0.284407537f, -0.958703475f,
+ 0.278519689f, -0.960430519f,
+ 0.272621355f, -0.962121404f,
+ 0.266712757f, -0.963776066f,
+ 0.260794118f, -0.965394442f,
+ 0.254865660f, -0.966976471f,
+ 0.248927606f, -0.968522094f,
+ 0.242980180f, -0.970031253f,
+ 0.237023606f, -0.971503891f,
+ 0.231058108f, -0.972939952f,
+ 0.225083911f, -0.974339383f,
+ 0.219101240f, -0.975702130f,
+ 0.213110320f, -0.977028143f,
+ 0.207111376f, -0.978317371f,
+ 0.201104635f, -0.979569766f,
+ 0.195090322f, -0.980785280f,
+ 0.189068664f, -0.981963869f,
+ 0.183039888f, -0.983105487f,
+ 0.177004220f, -0.984210092f,
+ 0.170961889f, -0.985277642f,
+ 0.164913120f, -0.986308097f,
+ 0.158858143f, -0.987301418f,
+ 0.152797185f, -0.988257568f,
+ 0.146730474f, -0.989176510f,
+ 0.140658239f, -0.990058210f,
+ 0.134580709f, -0.990902635f,
+ 0.128498111f, -0.991709754f,
+ 0.122410675f, -0.992479535f,
+ 0.116318631f, -0.993211949f,
+ 0.110222207f, -0.993906970f,
+ 0.104121634f, -0.994564571f,
+ 0.098017140f, -0.995184727f,
+ 0.091908956f, -0.995767414f,
+ 0.085797312f, -0.996312612f,
+ 0.079682438f, -0.996820299f,
+ 0.073564564f, -0.997290457f,
+ 0.067443920f, -0.997723067f,
+ 0.061320736f, -0.998118113f,
+ 0.055195244f, -0.998475581f,
+ 0.049067674f, -0.998795456f,
+ 0.042938257f, -0.999077728f,
+ 0.036807223f, -0.999322385f,
+ 0.030674803f, -0.999529418f,
+ 0.024541229f, -0.999698819f,
+ 0.018406730f, -0.999830582f,
+ 0.012271538f, -0.999924702f,
+ 0.006135885f, -0.999981175f
+};
+
+const float32_t twiddleCoef_rfft_2048[2048] = {
+ 0.000000000f, 1.000000000f,
+ 0.003067957f, 0.999995294f,
+ 0.006135885f, 0.999981175f,
+ 0.009203755f, 0.999957645f,
+ 0.012271538f, 0.999924702f,
+ 0.015339206f, 0.999882347f,
+ 0.018406730f, 0.999830582f,
+ 0.021474080f, 0.999769405f,
+ 0.024541229f, 0.999698819f,
+ 0.027608146f, 0.999618822f,
+ 0.030674803f, 0.999529418f,
+ 0.033741172f, 0.999430605f,
+ 0.036807223f, 0.999322385f,
+ 0.039872928f, 0.999204759f,
+ 0.042938257f, 0.999077728f,
+ 0.046003182f, 0.998941293f,
+ 0.049067674f, 0.998795456f,
+ 0.052131705f, 0.998640218f,
+ 0.055195244f, 0.998475581f,
+ 0.058258265f, 0.998301545f,
+ 0.061320736f, 0.998118113f,
+ 0.064382631f, 0.997925286f,
+ 0.067443920f, 0.997723067f,
+ 0.070504573f, 0.997511456f,
+ 0.073564564f, 0.997290457f,
+ 0.076623861f, 0.997060070f,
+ 0.079682438f, 0.996820299f,
+ 0.082740265f, 0.996571146f,
+ 0.085797312f, 0.996312612f,
+ 0.088853553f, 0.996044701f,
+ 0.091908956f, 0.995767414f,
+ 0.094963495f, 0.995480755f,
+ 0.098017140f, 0.995184727f,
+ 0.101069863f, 0.994879331f,
+ 0.104121634f, 0.994564571f,
+ 0.107172425f, 0.994240449f,
+ 0.110222207f, 0.993906970f,
+ 0.113270952f, 0.993564136f,
+ 0.116318631f, 0.993211949f,
+ 0.119365215f, 0.992850414f,
+ 0.122410675f, 0.992479535f,
+ 0.125454983f, 0.992099313f,
+ 0.128498111f, 0.991709754f,
+ 0.131540029f, 0.991310860f,
+ 0.134580709f, 0.990902635f,
+ 0.137620122f, 0.990485084f,
+ 0.140658239f, 0.990058210f,
+ 0.143695033f, 0.989622017f,
+ 0.146730474f, 0.989176510f,
+ 0.149764535f, 0.988721692f,
+ 0.152797185f, 0.988257568f,
+ 0.155828398f, 0.987784142f,
+ 0.158858143f, 0.987301418f,
+ 0.161886394f, 0.986809402f,
+ 0.164913120f, 0.986308097f,
+ 0.167938295f, 0.985797509f,
+ 0.170961889f, 0.985277642f,
+ 0.173983873f, 0.984748502f,
+ 0.177004220f, 0.984210092f,
+ 0.180022901f, 0.983662419f,
+ 0.183039888f, 0.983105487f,
+ 0.186055152f, 0.982539302f,
+ 0.189068664f, 0.981963869f,
+ 0.192080397f, 0.981379193f,
+ 0.195090322f, 0.980785280f,
+ 0.198098411f, 0.980182136f,
+ 0.201104635f, 0.979569766f,
+ 0.204108966f, 0.978948175f,
+ 0.207111376f, 0.978317371f,
+ 0.210111837f, 0.977677358f,
+ 0.213110320f, 0.977028143f,
+ 0.216106797f, 0.976369731f,
+ 0.219101240f, 0.975702130f,
+ 0.222093621f, 0.975025345f,
+ 0.225083911f, 0.974339383f,
+ 0.228072083f, 0.973644250f,
+ 0.231058108f, 0.972939952f,
+ 0.234041959f, 0.972226497f,
+ 0.237023606f, 0.971503891f,
+ 0.240003022f, 0.970772141f,
+ 0.242980180f, 0.970031253f,
+ 0.245955050f, 0.969281235f,
+ 0.248927606f, 0.968522094f,
+ 0.251897818f, 0.967753837f,
+ 0.254865660f, 0.966976471f,
+ 0.257831102f, 0.966190003f,
+ 0.260794118f, 0.965394442f,
+ 0.263754679f, 0.964589793f,
+ 0.266712757f, 0.963776066f,
+ 0.269668326f, 0.962953267f,
+ 0.272621355f, 0.962121404f,
+ 0.275571819f, 0.961280486f,
+ 0.278519689f, 0.960430519f,
+ 0.281464938f, 0.959571513f,
+ 0.284407537f, 0.958703475f,
+ 0.287347460f, 0.957826413f,
+ 0.290284677f, 0.956940336f,
+ 0.293219163f, 0.956045251f,
+ 0.296150888f, 0.955141168f,
+ 0.299079826f, 0.954228095f,
+ 0.302005949f, 0.953306040f,
+ 0.304929230f, 0.952375013f,
+ 0.307849640f, 0.951435021f,
+ 0.310767153f, 0.950486074f,
+ 0.313681740f, 0.949528181f,
+ 0.316593376f, 0.948561350f,
+ 0.319502031f, 0.947585591f,
+ 0.322407679f, 0.946600913f,
+ 0.325310292f, 0.945607325f,
+ 0.328209844f, 0.944604837f,
+ 0.331106306f, 0.943593458f,
+ 0.333999651f, 0.942573198f,
+ 0.336889853f, 0.941544065f,
+ 0.339776884f, 0.940506071f,
+ 0.342660717f, 0.939459224f,
+ 0.345541325f, 0.938403534f,
+ 0.348418680f, 0.937339012f,
+ 0.351292756f, 0.936265667f,
+ 0.354163525f, 0.935183510f,
+ 0.357030961f, 0.934092550f,
+ 0.359895037f, 0.932992799f,
+ 0.362755724f, 0.931884266f,
+ 0.365612998f, 0.930766961f,
+ 0.368466830f, 0.929640896f,
+ 0.371317194f, 0.928506080f,
+ 0.374164063f, 0.927362526f,
+ 0.377007410f, 0.926210242f,
+ 0.379847209f, 0.925049241f,
+ 0.382683432f, 0.923879533f,
+ 0.385516054f, 0.922701128f,
+ 0.388345047f, 0.921514039f,
+ 0.391170384f, 0.920318277f,
+ 0.393992040f, 0.919113852f,
+ 0.396809987f, 0.917900776f,
+ 0.399624200f, 0.916679060f,
+ 0.402434651f, 0.915448716f,
+ 0.405241314f, 0.914209756f,
+ 0.408044163f, 0.912962190f,
+ 0.410843171f, 0.911706032f,
+ 0.413638312f, 0.910441292f,
+ 0.416429560f, 0.909167983f,
+ 0.419216888f, 0.907886116f,
+ 0.422000271f, 0.906595705f,
+ 0.424779681f, 0.905296759f,
+ 0.427555093f, 0.903989293f,
+ 0.430326481f, 0.902673318f,
+ 0.433093819f, 0.901348847f,
+ 0.435857080f, 0.900015892f,
+ 0.438616239f, 0.898674466f,
+ 0.441371269f, 0.897324581f,
+ 0.444122145f, 0.895966250f,
+ 0.446868840f, 0.894599486f,
+ 0.449611330f, 0.893224301f,
+ 0.452349587f, 0.891840709f,
+ 0.455083587f, 0.890448723f,
+ 0.457813304f, 0.889048356f,
+ 0.460538711f, 0.887639620f,
+ 0.463259784f, 0.886222530f,
+ 0.465976496f, 0.884797098f,
+ 0.468688822f, 0.883363339f,
+ 0.471396737f, 0.881921264f,
+ 0.474100215f, 0.880470889f,
+ 0.476799230f, 0.879012226f,
+ 0.479493758f, 0.877545290f,
+ 0.482183772f, 0.876070094f,
+ 0.484869248f, 0.874586652f,
+ 0.487550160f, 0.873094978f,
+ 0.490226483f, 0.871595087f,
+ 0.492898192f, 0.870086991f,
+ 0.495565262f, 0.868570706f,
+ 0.498227667f, 0.867046246f,
+ 0.500885383f, 0.865513624f,
+ 0.503538384f, 0.863972856f,
+ 0.506186645f, 0.862423956f,
+ 0.508830143f, 0.860866939f,
+ 0.511468850f, 0.859301818f,
+ 0.514102744f, 0.857728610f,
+ 0.516731799f, 0.856147328f,
+ 0.519355990f, 0.854557988f,
+ 0.521975293f, 0.852960605f,
+ 0.524589683f, 0.851355193f,
+ 0.527199135f, 0.849741768f,
+ 0.529803625f, 0.848120345f,
+ 0.532403128f, 0.846490939f,
+ 0.534997620f, 0.844853565f,
+ 0.537587076f, 0.843208240f,
+ 0.540171473f, 0.841554977f,
+ 0.542750785f, 0.839893794f,
+ 0.545324988f, 0.838224706f,
+ 0.547894059f, 0.836547727f,
+ 0.550457973f, 0.834862875f,
+ 0.553016706f, 0.833170165f,
+ 0.555570233f, 0.831469612f,
+ 0.558118531f, 0.829761234f,
+ 0.560661576f, 0.828045045f,
+ 0.563199344f, 0.826321063f,
+ 0.565731811f, 0.824589303f,
+ 0.568258953f, 0.822849781f,
+ 0.570780746f, 0.821102515f,
+ 0.573297167f, 0.819347520f,
+ 0.575808191f, 0.817584813f,
+ 0.578313796f, 0.815814411f,
+ 0.580813958f, 0.814036330f,
+ 0.583308653f, 0.812250587f,
+ 0.585797857f, 0.810457198f,
+ 0.588281548f, 0.808656182f,
+ 0.590759702f, 0.806847554f,
+ 0.593232295f, 0.805031331f,
+ 0.595699304f, 0.803207531f,
+ 0.598160707f, 0.801376172f,
+ 0.600616479f, 0.799537269f,
+ 0.603066599f, 0.797690841f,
+ 0.605511041f, 0.795836905f,
+ 0.607949785f, 0.793975478f,
+ 0.610382806f, 0.792106577f,
+ 0.612810082f, 0.790230221f,
+ 0.615231591f, 0.788346428f,
+ 0.617647308f, 0.786455214f,
+ 0.620057212f, 0.784556597f,
+ 0.622461279f, 0.782650596f,
+ 0.624859488f, 0.780737229f,
+ 0.627251815f, 0.778816512f,
+ 0.629638239f, 0.776888466f,
+ 0.632018736f, 0.774953107f,
+ 0.634393284f, 0.773010453f,
+ 0.636761861f, 0.771060524f,
+ 0.639124445f, 0.769103338f,
+ 0.641481013f, 0.767138912f,
+ 0.643831543f, 0.765167266f,
+ 0.646176013f, 0.763188417f,
+ 0.648514401f, 0.761202385f,
+ 0.650846685f, 0.759209189f,
+ 0.653172843f, 0.757208847f,
+ 0.655492853f, 0.755201377f,
+ 0.657806693f, 0.753186799f,
+ 0.660114342f, 0.751165132f,
+ 0.662415778f, 0.749136395f,
+ 0.664710978f, 0.747100606f,
+ 0.666999922f, 0.745057785f,
+ 0.669282588f, 0.743007952f,
+ 0.671558955f, 0.740951125f,
+ 0.673829000f, 0.738887324f,
+ 0.676092704f, 0.736816569f,
+ 0.678350043f, 0.734738878f,
+ 0.680600998f, 0.732654272f,
+ 0.682845546f, 0.730562769f,
+ 0.685083668f, 0.728464390f,
+ 0.687315341f, 0.726359155f,
+ 0.689540545f, 0.724247083f,
+ 0.691759258f, 0.722128194f,
+ 0.693971461f, 0.720002508f,
+ 0.696177131f, 0.717870045f,
+ 0.698376249f, 0.715730825f,
+ 0.700568794f, 0.713584869f,
+ 0.702754744f, 0.711432196f,
+ 0.704934080f, 0.709272826f,
+ 0.707106781f, 0.707106781f,
+ 0.709272826f, 0.704934080f,
+ 0.711432196f, 0.702754744f,
+ 0.713584869f, 0.700568794f,
+ 0.715730825f, 0.698376249f,
+ 0.717870045f, 0.696177131f,
+ 0.720002508f, 0.693971461f,
+ 0.722128194f, 0.691759258f,
+ 0.724247083f, 0.689540545f,
+ 0.726359155f, 0.687315341f,
+ 0.728464390f, 0.685083668f,
+ 0.730562769f, 0.682845546f,
+ 0.732654272f, 0.680600998f,
+ 0.734738878f, 0.678350043f,
+ 0.736816569f, 0.676092704f,
+ 0.738887324f, 0.673829000f,
+ 0.740951125f, 0.671558955f,
+ 0.743007952f, 0.669282588f,
+ 0.745057785f, 0.666999922f,
+ 0.747100606f, 0.664710978f,
+ 0.749136395f, 0.662415778f,
+ 0.751165132f, 0.660114342f,
+ 0.753186799f, 0.657806693f,
+ 0.755201377f, 0.655492853f,
+ 0.757208847f, 0.653172843f,
+ 0.759209189f, 0.650846685f,
+ 0.761202385f, 0.648514401f,
+ 0.763188417f, 0.646176013f,
+ 0.765167266f, 0.643831543f,
+ 0.767138912f, 0.641481013f,
+ 0.769103338f, 0.639124445f,
+ 0.771060524f, 0.636761861f,
+ 0.773010453f, 0.634393284f,
+ 0.774953107f, 0.632018736f,
+ 0.776888466f, 0.629638239f,
+ 0.778816512f, 0.627251815f,
+ 0.780737229f, 0.624859488f,
+ 0.782650596f, 0.622461279f,
+ 0.784556597f, 0.620057212f,
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+ 0.207111376f, -0.978317371f,
+ 0.204108966f, -0.978948175f,
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+ 0.152797185f, -0.988257568f,
+ 0.149764535f, -0.988721692f,
+ 0.146730474f, -0.989176510f,
+ 0.143695033f, -0.989622017f,
+ 0.140658239f, -0.990058210f,
+ 0.137620122f, -0.990485084f,
+ 0.134580709f, -0.990902635f,
+ 0.131540029f, -0.991310860f,
+ 0.128498111f, -0.991709754f,
+ 0.125454983f, -0.992099313f,
+ 0.122410675f, -0.992479535f,
+ 0.119365215f, -0.992850414f,
+ 0.116318631f, -0.993211949f,
+ 0.113270952f, -0.993564136f,
+ 0.110222207f, -0.993906970f,
+ 0.107172425f, -0.994240449f,
+ 0.104121634f, -0.994564571f,
+ 0.101069863f, -0.994879331f,
+ 0.098017140f, -0.995184727f,
+ 0.094963495f, -0.995480755f,
+ 0.091908956f, -0.995767414f,
+ 0.088853553f, -0.996044701f,
+ 0.085797312f, -0.996312612f,
+ 0.082740265f, -0.996571146f,
+ 0.079682438f, -0.996820299f,
+ 0.076623861f, -0.997060070f,
+ 0.073564564f, -0.997290457f,
+ 0.070504573f, -0.997511456f,
+ 0.067443920f, -0.997723067f,
+ 0.064382631f, -0.997925286f,
+ 0.061320736f, -0.998118113f,
+ 0.058258265f, -0.998301545f,
+ 0.055195244f, -0.998475581f,
+ 0.052131705f, -0.998640218f,
+ 0.049067674f, -0.998795456f,
+ 0.046003182f, -0.998941293f,
+ 0.042938257f, -0.999077728f,
+ 0.039872928f, -0.999204759f,
+ 0.036807223f, -0.999322385f,
+ 0.033741172f, -0.999430605f,
+ 0.030674803f, -0.999529418f,
+ 0.027608146f, -0.999618822f,
+ 0.024541229f, -0.999698819f,
+ 0.021474080f, -0.999769405f,
+ 0.018406730f, -0.999830582f,
+ 0.015339206f, -0.999882347f,
+ 0.012271538f, -0.999924702f,
+ 0.009203755f, -0.999957645f,
+ 0.006135885f, -0.999981175f,
+ 0.003067957f, -0.999995294f
+};
+
+const float32_t twiddleCoef_rfft_4096[4096] = {
+ 0.000000000f, 1.000000000f,
+ 0.001533980f, 0.999998823f,
+ 0.003067957f, 0.999995294f,
+ 0.004601926f, 0.999989411f,
+ 0.006135885f, 0.999981175f,
+ 0.007669829f, 0.999970586f,
+ 0.009203755f, 0.999957645f,
+ 0.010737659f, 0.999942350f,
+ 0.012271538f, 0.999924702f,
+ 0.013805389f, 0.999904701f,
+ 0.015339206f, 0.999882347f,
+ 0.016872988f, 0.999857641f,
+ 0.018406730f, 0.999830582f,
+ 0.019940429f, 0.999801170f,
+ 0.021474080f, 0.999769405f,
+ 0.023007681f, 0.999735288f,
+ 0.024541229f, 0.999698819f,
+ 0.026074718f, 0.999659997f,
+ 0.027608146f, 0.999618822f,
+ 0.029141509f, 0.999575296f,
+ 0.030674803f, 0.999529418f,
+ 0.032208025f, 0.999481187f,
+ 0.033741172f, 0.999430605f,
+ 0.035274239f, 0.999377670f,
+ 0.036807223f, 0.999322385f,
+ 0.038340120f, 0.999264747f,
+ 0.039872928f, 0.999204759f,
+ 0.041405641f, 0.999142419f,
+ 0.042938257f, 0.999077728f,
+ 0.044470772f, 0.999010686f,
+ 0.046003182f, 0.998941293f,
+ 0.047535484f, 0.998869550f,
+ 0.049067674f, 0.998795456f,
+ 0.050599749f, 0.998719012f,
+ 0.052131705f, 0.998640218f,
+ 0.053663538f, 0.998559074f,
+ 0.055195244f, 0.998475581f,
+ 0.056726821f, 0.998389737f,
+ 0.058258265f, 0.998301545f,
+ 0.059789571f, 0.998211003f,
+ 0.061320736f, 0.998118113f,
+ 0.062851758f, 0.998022874f,
+ 0.064382631f, 0.997925286f,
+ 0.065913353f, 0.997825350f,
+ 0.067443920f, 0.997723067f,
+ 0.068974328f, 0.997618435f,
+ 0.070504573f, 0.997511456f,
+ 0.072034653f, 0.997402130f,
+ 0.073564564f, 0.997290457f,
+ 0.075094301f, 0.997176437f,
+ 0.076623861f, 0.997060070f,
+ 0.078153242f, 0.996941358f,
+ 0.079682438f, 0.996820299f,
+ 0.081211447f, 0.996696895f,
+ 0.082740265f, 0.996571146f,
+ 0.084268888f, 0.996443051f,
+ 0.085797312f, 0.996312612f,
+ 0.087325535f, 0.996179829f,
+ 0.088853553f, 0.996044701f,
+ 0.090381361f, 0.995907229f,
+ 0.091908956f, 0.995767414f,
+ 0.093436336f, 0.995625256f,
+ 0.094963495f, 0.995480755f,
+ 0.096490431f, 0.995333912f,
+ 0.098017140f, 0.995184727f,
+ 0.099543619f, 0.995033199f,
+ 0.101069863f, 0.994879331f,
+ 0.102595869f, 0.994723121f,
+ 0.104121634f, 0.994564571f,
+ 0.105647154f, 0.994403680f,
+ 0.107172425f, 0.994240449f,
+ 0.108697444f, 0.994074879f,
+ 0.110222207f, 0.993906970f,
+ 0.111746711f, 0.993736722f,
+ 0.113270952f, 0.993564136f,
+ 0.114794927f, 0.993389211f,
+ 0.116318631f, 0.993211949f,
+ 0.117842062f, 0.993032350f,
+ 0.119365215f, 0.992850414f,
+ 0.120888087f, 0.992666142f,
+ 0.122410675f, 0.992479535f,
+ 0.123932975f, 0.992290591f,
+ 0.125454983f, 0.992099313f,
+ 0.126976696f, 0.991905700f,
+ 0.128498111f, 0.991709754f,
+ 0.130019223f, 0.991511473f,
+ 0.131540029f, 0.991310860f,
+ 0.133060525f, 0.991107914f,
+ 0.134580709f, 0.990902635f,
+ 0.136100575f, 0.990695025f,
+ 0.137620122f, 0.990485084f,
+ 0.139139344f, 0.990272812f,
+ 0.140658239f, 0.990058210f,
+ 0.142176804f, 0.989841278f,
+ 0.143695033f, 0.989622017f,
+ 0.145212925f, 0.989400428f,
+ 0.146730474f, 0.989176510f,
+ 0.148247679f, 0.988950265f,
+ 0.149764535f, 0.988721692f,
+ 0.151281038f, 0.988490793f,
+ 0.152797185f, 0.988257568f,
+ 0.154312973f, 0.988022017f,
+ 0.155828398f, 0.987784142f,
+ 0.157343456f, 0.987543942f,
+ 0.158858143f, 0.987301418f,
+ 0.160372457f, 0.987056571f,
+ 0.161886394f, 0.986809402f,
+ 0.163399949f, 0.986559910f,
+ 0.164913120f, 0.986308097f,
+ 0.166425904f, 0.986053963f,
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+ 0.364184790f, -0.931326709f,
+ 0.362755724f, -0.931884266f,
+ 0.361325806f, -0.932439629f,
+ 0.359895037f, -0.932992799f,
+ 0.358463421f, -0.933543773f,
+ 0.357030961f, -0.934092550f,
+ 0.355597662f, -0.934639130f,
+ 0.354163525f, -0.935183510f,
+ 0.352728556f, -0.935725689f,
+ 0.351292756f, -0.936265667f,
+ 0.349856130f, -0.936803442f,
+ 0.348418680f, -0.937339012f,
+ 0.346980411f, -0.937872376f,
+ 0.345541325f, -0.938403534f,
+ 0.344101426f, -0.938932484f,
+ 0.342660717f, -0.939459224f,
+ 0.341219202f, -0.939983753f,
+ 0.339776884f, -0.940506071f,
+ 0.338333767f, -0.941026175f,
+ 0.336889853f, -0.941544065f,
+ 0.335445147f, -0.942059740f,
+ 0.333999651f, -0.942573198f,
+ 0.332553370f, -0.943084437f,
+ 0.331106306f, -0.943593458f,
+ 0.329658463f, -0.944100258f,
+ 0.328209844f, -0.944604837f,
+ 0.326760452f, -0.945107193f,
+ 0.325310292f, -0.945607325f,
+ 0.323859367f, -0.946105232f,
+ 0.322407679f, -0.946600913f,
+ 0.320955232f, -0.947094366f,
+ 0.319502031f, -0.947585591f,
+ 0.318048077f, -0.948074586f,
+ 0.316593376f, -0.948561350f,
+ 0.315137929f, -0.949045882f,
+ 0.313681740f, -0.949528181f,
+ 0.312224814f, -0.950008245f,
+ 0.310767153f, -0.950486074f,
+ 0.309308760f, -0.950961666f,
+ 0.307849640f, -0.951435021f,
+ 0.306389795f, -0.951906137f,
+ 0.304929230f, -0.952375013f,
+ 0.303467947f, -0.952841648f,
+ 0.302005949f, -0.953306040f,
+ 0.300543241f, -0.953768190f,
+ 0.299079826f, -0.954228095f,
+ 0.297615707f, -0.954685755f,
+ 0.296150888f, -0.955141168f,
+ 0.294685372f, -0.955594334f,
+ 0.293219163f, -0.956045251f,
+ 0.291752263f, -0.956493919f,
+ 0.290284677f, -0.956940336f,
+ 0.288816408f, -0.957384501f,
+ 0.287347460f, -0.957826413f,
+ 0.285877835f, -0.958266071f,
+ 0.284407537f, -0.958703475f,
+ 0.282936570f, -0.959138622f,
+ 0.281464938f, -0.959571513f,
+ 0.279992643f, -0.960002146f,
+ 0.278519689f, -0.960430519f,
+ 0.277046080f, -0.960856633f,
+ 0.275571819f, -0.961280486f,
+ 0.274096910f, -0.961702077f,
+ 0.272621355f, -0.962121404f,
+ 0.271145160f, -0.962538468f,
+ 0.269668326f, -0.962953267f,
+ 0.268190857f, -0.963365800f,
+ 0.266712757f, -0.963776066f,
+ 0.265234030f, -0.964184064f,
+ 0.263754679f, -0.964589793f,
+ 0.262274707f, -0.964993253f,
+ 0.260794118f, -0.965394442f,
+ 0.259312915f, -0.965793359f,
+ 0.257831102f, -0.966190003f,
+ 0.256348682f, -0.966584374f,
+ 0.254865660f, -0.966976471f,
+ 0.253382037f, -0.967366292f,
+ 0.251897818f, -0.967753837f,
+ 0.250413007f, -0.968139105f,
+ 0.248927606f, -0.968522094f,
+ 0.247441619f, -0.968902805f,
+ 0.245955050f, -0.969281235f,
+ 0.244467903f, -0.969657385f,
+ 0.242980180f, -0.970031253f,
+ 0.241491885f, -0.970402839f,
+ 0.240003022f, -0.970772141f,
+ 0.238513595f, -0.971139158f,
+ 0.237023606f, -0.971503891f,
+ 0.235533059f, -0.971866337f,
+ 0.234041959f, -0.972226497f,
+ 0.232550307f, -0.972584369f,
+ 0.231058108f, -0.972939952f,
+ 0.229565366f, -0.973293246f,
+ 0.228072083f, -0.973644250f,
+ 0.226578264f, -0.973992962f,
+ 0.225083911f, -0.974339383f,
+ 0.223589029f, -0.974683511f,
+ 0.222093621f, -0.975025345f,
+ 0.220597690f, -0.975364885f,
+ 0.219101240f, -0.975702130f,
+ 0.217604275f, -0.976037079f,
+ 0.216106797f, -0.976369731f,
+ 0.214608811f, -0.976700086f,
+ 0.213110320f, -0.977028143f,
+ 0.211611327f, -0.977353900f,
+ 0.210111837f, -0.977677358f,
+ 0.208611852f, -0.977998515f,
+ 0.207111376f, -0.978317371f,
+ 0.205610413f, -0.978633924f,
+ 0.204108966f, -0.978948175f,
+ 0.202607039f, -0.979260123f,
+ 0.201104635f, -0.979569766f,
+ 0.199601758f, -0.979877104f,
+ 0.198098411f, -0.980182136f,
+ 0.196594598f, -0.980484862f,
+ 0.195090322f, -0.980785280f,
+ 0.193585587f, -0.981083391f,
+ 0.192080397f, -0.981379193f,
+ 0.190574755f, -0.981672686f,
+ 0.189068664f, -0.981963869f,
+ 0.187562129f, -0.982252741f,
+ 0.186055152f, -0.982539302f,
+ 0.184547737f, -0.982823551f,
+ 0.183039888f, -0.983105487f,
+ 0.181531608f, -0.983385110f,
+ 0.180022901f, -0.983662419f,
+ 0.178513771f, -0.983937413f,
+ 0.177004220f, -0.984210092f,
+ 0.175494253f, -0.984480455f,
+ 0.173983873f, -0.984748502f,
+ 0.172473084f, -0.985014231f,
+ 0.170961889f, -0.985277642f,
+ 0.169450291f, -0.985538735f,
+ 0.167938295f, -0.985797509f,
+ 0.166425904f, -0.986053963f,
+ 0.164913120f, -0.986308097f,
+ 0.163399949f, -0.986559910f,
+ 0.161886394f, -0.986809402f,
+ 0.160372457f, -0.987056571f,
+ 0.158858143f, -0.987301418f,
+ 0.157343456f, -0.987543942f,
+ 0.155828398f, -0.987784142f,
+ 0.154312973f, -0.988022017f,
+ 0.152797185f, -0.988257568f,
+ 0.151281038f, -0.988490793f,
+ 0.149764535f, -0.988721692f,
+ 0.148247679f, -0.988950265f,
+ 0.146730474f, -0.989176510f,
+ 0.145212925f, -0.989400428f,
+ 0.143695033f, -0.989622017f,
+ 0.142176804f, -0.989841278f,
+ 0.140658239f, -0.990058210f,
+ 0.139139344f, -0.990272812f,
+ 0.137620122f, -0.990485084f,
+ 0.136100575f, -0.990695025f,
+ 0.134580709f, -0.990902635f,
+ 0.133060525f, -0.991107914f,
+ 0.131540029f, -0.991310860f,
+ 0.130019223f, -0.991511473f,
+ 0.128498111f, -0.991709754f,
+ 0.126976696f, -0.991905700f,
+ 0.125454983f, -0.992099313f,
+ 0.123932975f, -0.992290591f,
+ 0.122410675f, -0.992479535f,
+ 0.120888087f, -0.992666142f,
+ 0.119365215f, -0.992850414f,
+ 0.117842062f, -0.993032350f,
+ 0.116318631f, -0.993211949f,
+ 0.114794927f, -0.993389211f,
+ 0.113270952f, -0.993564136f,
+ 0.111746711f, -0.993736722f,
+ 0.110222207f, -0.993906970f,
+ 0.108697444f, -0.994074879f,
+ 0.107172425f, -0.994240449f,
+ 0.105647154f, -0.994403680f,
+ 0.104121634f, -0.994564571f,
+ 0.102595869f, -0.994723121f,
+ 0.101069863f, -0.994879331f,
+ 0.099543619f, -0.995033199f,
+ 0.098017140f, -0.995184727f,
+ 0.096490431f, -0.995333912f,
+ 0.094963495f, -0.995480755f,
+ 0.093436336f, -0.995625256f,
+ 0.091908956f, -0.995767414f,
+ 0.090381361f, -0.995907229f,
+ 0.088853553f, -0.996044701f,
+ 0.087325535f, -0.996179829f,
+ 0.085797312f, -0.996312612f,
+ 0.084268888f, -0.996443051f,
+ 0.082740265f, -0.996571146f,
+ 0.081211447f, -0.996696895f,
+ 0.079682438f, -0.996820299f,
+ 0.078153242f, -0.996941358f,
+ 0.076623861f, -0.997060070f,
+ 0.075094301f, -0.997176437f,
+ 0.073564564f, -0.997290457f,
+ 0.072034653f, -0.997402130f,
+ 0.070504573f, -0.997511456f,
+ 0.068974328f, -0.997618435f,
+ 0.067443920f, -0.997723067f,
+ 0.065913353f, -0.997825350f,
+ 0.064382631f, -0.997925286f,
+ 0.062851758f, -0.998022874f,
+ 0.061320736f, -0.998118113f,
+ 0.059789571f, -0.998211003f,
+ 0.058258265f, -0.998301545f,
+ 0.056726821f, -0.998389737f,
+ 0.055195244f, -0.998475581f,
+ 0.053663538f, -0.998559074f,
+ 0.052131705f, -0.998640218f,
+ 0.050599749f, -0.998719012f,
+ 0.049067674f, -0.998795456f,
+ 0.047535484f, -0.998869550f,
+ 0.046003182f, -0.998941293f,
+ 0.044470772f, -0.999010686f,
+ 0.042938257f, -0.999077728f,
+ 0.041405641f, -0.999142419f,
+ 0.039872928f, -0.999204759f,
+ 0.038340120f, -0.999264747f,
+ 0.036807223f, -0.999322385f,
+ 0.035274239f, -0.999377670f,
+ 0.033741172f, -0.999430605f,
+ 0.032208025f, -0.999481187f,
+ 0.030674803f, -0.999529418f,
+ 0.029141509f, -0.999575296f,
+ 0.027608146f, -0.999618822f,
+ 0.026074718f, -0.999659997f,
+ 0.024541229f, -0.999698819f,
+ 0.023007681f, -0.999735288f,
+ 0.021474080f, -0.999769405f,
+ 0.019940429f, -0.999801170f,
+ 0.018406730f, -0.999830582f,
+ 0.016872988f, -0.999857641f,
+ 0.015339206f, -0.999882347f,
+ 0.013805389f, -0.999904701f,
+ 0.012271538f, -0.999924702f,
+ 0.010737659f, -0.999942350f,
+ 0.009203755f, -0.999957645f,
+ 0.007669829f, -0.999970586f,
+ 0.006135885f, -0.999981175f,
+ 0.004601926f, -0.999989411f,
+ 0.003067957f, -0.999995294f,
+ 0.001533980f, -0.999998823f
+};
+
+
+/**
+ * \par
+ * Example code for the generation of the floating-point sine table:
+ * <pre>
+ * tableSize = 512;
+ * for(n = 0; n < (tableSize + 1); n++)
+ * {
+ * sinTable[n]=sin(2*pi*n/tableSize);
+ * }</pre>
+ * \par
+ * where pi value is 3.14159265358979
+ */
+
+const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1] = {
+ 0.00000000f, 0.01227154f, 0.02454123f, 0.03680722f, 0.04906767f, 0.06132074f,
+ 0.07356456f, 0.08579731f, 0.09801714f, 0.11022221f, 0.12241068f, 0.13458071f,
+ 0.14673047f, 0.15885814f, 0.17096189f, 0.18303989f, 0.19509032f, 0.20711138f,
+ 0.21910124f, 0.23105811f, 0.24298018f, 0.25486566f, 0.26671276f, 0.27851969f,
+ 0.29028468f, 0.30200595f, 0.31368174f, 0.32531029f, 0.33688985f, 0.34841868f,
+ 0.35989504f, 0.37131719f, 0.38268343f, 0.39399204f, 0.40524131f, 0.41642956f,
+ 0.42755509f, 0.43861624f, 0.44961133f, 0.46053871f, 0.47139674f, 0.48218377f,
+ 0.49289819f, 0.50353838f, 0.51410274f, 0.52458968f, 0.53499762f, 0.54532499f,
+ 0.55557023f, 0.56573181f, 0.57580819f, 0.58579786f, 0.59569930f, 0.60551104f,
+ 0.61523159f, 0.62485949f, 0.63439328f, 0.64383154f, 0.65317284f, 0.66241578f,
+ 0.67155895f, 0.68060100f, 0.68954054f, 0.69837625f, 0.70710678f, 0.71573083f,
+ 0.72424708f, 0.73265427f, 0.74095113f, 0.74913639f, 0.75720885f, 0.76516727f,
+ 0.77301045f, 0.78073723f, 0.78834643f, 0.79583690f, 0.80320753f, 0.81045720f,
+ 0.81758481f, 0.82458930f, 0.83146961f, 0.83822471f, 0.84485357f, 0.85135519f,
+ 0.85772861f, 0.86397286f, 0.87008699f, 0.87607009f, 0.88192126f, 0.88763962f,
+ 0.89322430f, 0.89867447f, 0.90398929f, 0.90916798f, 0.91420976f, 0.91911385f,
+ 0.92387953f, 0.92850608f, 0.93299280f, 0.93733901f, 0.94154407f, 0.94560733f,
+ 0.94952818f, 0.95330604f, 0.95694034f, 0.96043052f, 0.96377607f, 0.96697647f,
+ 0.97003125f, 0.97293995f, 0.97570213f, 0.97831737f, 0.98078528f, 0.98310549f,
+ 0.98527764f, 0.98730142f, 0.98917651f, 0.99090264f, 0.99247953f, 0.99390697f,
+ 0.99518473f, 0.99631261f, 0.99729046f, 0.99811811f, 0.99879546f, 0.99932238f,
+ 0.99969882f, 0.99992470f, 1.00000000f, 0.99992470f, 0.99969882f, 0.99932238f,
+ 0.99879546f, 0.99811811f, 0.99729046f, 0.99631261f, 0.99518473f, 0.99390697f,
+ 0.99247953f, 0.99090264f, 0.98917651f, 0.98730142f, 0.98527764f, 0.98310549f,
+ 0.98078528f, 0.97831737f, 0.97570213f, 0.97293995f, 0.97003125f, 0.96697647f,
+ 0.96377607f, 0.96043052f, 0.95694034f, 0.95330604f, 0.94952818f, 0.94560733f,
+ 0.94154407f, 0.93733901f, 0.93299280f, 0.92850608f, 0.92387953f, 0.91911385f,
+ 0.91420976f, 0.90916798f, 0.90398929f, 0.89867447f, 0.89322430f, 0.88763962f,
+ 0.88192126f, 0.87607009f, 0.87008699f, 0.86397286f, 0.85772861f, 0.85135519f,
+ 0.84485357f, 0.83822471f, 0.83146961f, 0.82458930f, 0.81758481f, 0.81045720f,
+ 0.80320753f, 0.79583690f, 0.78834643f, 0.78073723f, 0.77301045f, 0.76516727f,
+ 0.75720885f, 0.74913639f, 0.74095113f, 0.73265427f, 0.72424708f, 0.71573083f,
+ 0.70710678f, 0.69837625f, 0.68954054f, 0.68060100f, 0.67155895f, 0.66241578f,
+ 0.65317284f, 0.64383154f, 0.63439328f, 0.62485949f, 0.61523159f, 0.60551104f,
+ 0.59569930f, 0.58579786f, 0.57580819f, 0.56573181f, 0.55557023f, 0.54532499f,
+ 0.53499762f, 0.52458968f, 0.51410274f, 0.50353838f, 0.49289819f, 0.48218377f,
+ 0.47139674f, 0.46053871f, 0.44961133f, 0.43861624f, 0.42755509f, 0.41642956f,
+ 0.40524131f, 0.39399204f, 0.38268343f, 0.37131719f, 0.35989504f, 0.34841868f,
+ 0.33688985f, 0.32531029f, 0.31368174f, 0.30200595f, 0.29028468f, 0.27851969f,
+ 0.26671276f, 0.25486566f, 0.24298018f, 0.23105811f, 0.21910124f, 0.20711138f,
+ 0.19509032f, 0.18303989f, 0.17096189f, 0.15885814f, 0.14673047f, 0.13458071f,
+ 0.12241068f, 0.11022221f, 0.09801714f, 0.08579731f, 0.07356456f, 0.06132074f,
+ 0.04906767f, 0.03680722f, 0.02454123f, 0.01227154f, 0.00000000f, -0.01227154f,
+ -0.02454123f, -0.03680722f, -0.04906767f, -0.06132074f, -0.07356456f,
+ -0.08579731f, -0.09801714f, -0.11022221f, -0.12241068f, -0.13458071f,
+ -0.14673047f, -0.15885814f, -0.17096189f, -0.18303989f, -0.19509032f,
+ -0.20711138f, -0.21910124f, -0.23105811f, -0.24298018f, -0.25486566f,
+ -0.26671276f, -0.27851969f, -0.29028468f, -0.30200595f, -0.31368174f,
+ -0.32531029f, -0.33688985f, -0.34841868f, -0.35989504f, -0.37131719f,
+ -0.38268343f, -0.39399204f, -0.40524131f, -0.41642956f, -0.42755509f,
+ -0.43861624f, -0.44961133f, -0.46053871f, -0.47139674f, -0.48218377f,
+ -0.49289819f, -0.50353838f, -0.51410274f, -0.52458968f, -0.53499762f,
+ -0.54532499f, -0.55557023f, -0.56573181f, -0.57580819f, -0.58579786f,
+ -0.59569930f, -0.60551104f, -0.61523159f, -0.62485949f, -0.63439328f,
+ -0.64383154f, -0.65317284f, -0.66241578f, -0.67155895f, -0.68060100f,
+ -0.68954054f, -0.69837625f, -0.70710678f, -0.71573083f, -0.72424708f,
+ -0.73265427f, -0.74095113f, -0.74913639f, -0.75720885f, -0.76516727f,
+ -0.77301045f, -0.78073723f, -0.78834643f, -0.79583690f, -0.80320753f,
+ -0.81045720f, -0.81758481f, -0.82458930f, -0.83146961f, -0.83822471f,
+ -0.84485357f, -0.85135519f, -0.85772861f, -0.86397286f, -0.87008699f,
+ -0.87607009f, -0.88192126f, -0.88763962f, -0.89322430f, -0.89867447f,
+ -0.90398929f, -0.90916798f, -0.91420976f, -0.91911385f, -0.92387953f,
+ -0.92850608f, -0.93299280f, -0.93733901f, -0.94154407f, -0.94560733f,
+ -0.94952818f, -0.95330604f, -0.95694034f, -0.96043052f, -0.96377607f,
+ -0.96697647f, -0.97003125f, -0.97293995f, -0.97570213f, -0.97831737f,
+ -0.98078528f, -0.98310549f, -0.98527764f, -0.98730142f, -0.98917651f,
+ -0.99090264f, -0.99247953f, -0.99390697f, -0.99518473f, -0.99631261f,
+ -0.99729046f, -0.99811811f, -0.99879546f, -0.99932238f, -0.99969882f,
+ -0.99992470f, -1.00000000f, -0.99992470f, -0.99969882f, -0.99932238f,
+ -0.99879546f, -0.99811811f, -0.99729046f, -0.99631261f, -0.99518473f,
+ -0.99390697f, -0.99247953f, -0.99090264f, -0.98917651f, -0.98730142f,
+ -0.98527764f, -0.98310549f, -0.98078528f, -0.97831737f, -0.97570213f,
+ -0.97293995f, -0.97003125f, -0.96697647f, -0.96377607f, -0.96043052f,
+ -0.95694034f, -0.95330604f, -0.94952818f, -0.94560733f, -0.94154407f,
+ -0.93733901f, -0.93299280f, -0.92850608f, -0.92387953f, -0.91911385f,
+ -0.91420976f, -0.90916798f, -0.90398929f, -0.89867447f, -0.89322430f,
+ -0.88763962f, -0.88192126f, -0.87607009f, -0.87008699f, -0.86397286f,
+ -0.85772861f, -0.85135519f, -0.84485357f, -0.83822471f, -0.83146961f,
+ -0.82458930f, -0.81758481f, -0.81045720f, -0.80320753f, -0.79583690f,
+ -0.78834643f, -0.78073723f, -0.77301045f, -0.76516727f, -0.75720885f,
+ -0.74913639f, -0.74095113f, -0.73265427f, -0.72424708f, -0.71573083f,
+ -0.70710678f, -0.69837625f, -0.68954054f, -0.68060100f, -0.67155895f,
+ -0.66241578f, -0.65317284f, -0.64383154f, -0.63439328f, -0.62485949f,
+ -0.61523159f, -0.60551104f, -0.59569930f, -0.58579786f, -0.57580819f,
+ -0.56573181f, -0.55557023f, -0.54532499f, -0.53499762f, -0.52458968f,
+ -0.51410274f, -0.50353838f, -0.49289819f, -0.48218377f, -0.47139674f,
+ -0.46053871f, -0.44961133f, -0.43861624f, -0.42755509f, -0.41642956f,
+ -0.40524131f, -0.39399204f, -0.38268343f, -0.37131719f, -0.35989504f,
+ -0.34841868f, -0.33688985f, -0.32531029f, -0.31368174f, -0.30200595f,
+ -0.29028468f, -0.27851969f, -0.26671276f, -0.25486566f, -0.24298018f,
+ -0.23105811f, -0.21910124f, -0.20711138f, -0.19509032f, -0.18303989f,
+ -0.17096189f, -0.15885814f, -0.14673047f, -0.13458071f, -0.12241068f,
+ -0.11022221f, -0.09801714f, -0.08579731f, -0.07356456f, -0.06132074f,
+ -0.04906767f, -0.03680722f, -0.02454123f, -0.01227154f, -0.00000000f
+};
+
+/**
+ * \par
+ * Table values are in Q31 (1.31 fixed-point format) and generation is done in
+ * three steps. First, generate sin values in floating point:
+ * <pre>
+ * tableSize = 512;
+ * for(n = 0; n < (tableSize + 1); n++)
+ * {
+ * sinTable[n]= sin(2*pi*n/tableSize);
+ * } </pre>
+ * where pi value is 3.14159265358979
+ * \par
+ * Second, convert floating-point to Q31 (Fixed point):
+ * (sinTable[i] * pow(2, 31))
+ * \par
+ * Finally, round to the nearest integer value:
+ * sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5);
+ */
+const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1] = {
+ 0L, 26352928L, 52701887L, 79042909L, 105372028L, 131685278L, 157978697L,
+ 184248325L, 210490206L, 236700388L, 262874923L, 289009871L, 315101295L,
+ 341145265L, 367137861L, 393075166L, 418953276L, 444768294L, 470516330L,
+ 496193509L, 521795963L, 547319836L, 572761285L, 598116479L, 623381598L,
+ 648552838L, 673626408L, 698598533L, 723465451L, 748223418L, 772868706L,
+ 797397602L, 821806413L, 846091463L, 870249095L, 894275671L, 918167572L,
+ 941921200L, 965532978L, 988999351L, 1012316784L, 1035481766L, 1058490808L,
+ 1081340445L, 1104027237L, 1126547765L, 1148898640L, 1171076495L, 1193077991L,
+ 1214899813L, 1236538675L, 1257991320L, 1279254516L, 1300325060L, 1321199781L,
+ 1341875533L, 1362349204L, 1382617710L, 1402678000L, 1422527051L, 1442161874L,
+ 1461579514L, 1480777044L, 1499751576L, 1518500250L, 1537020244L, 1555308768L,
+ 1573363068L, 1591180426L, 1608758157L, 1626093616L, 1643184191L, 1660027308L,
+ 1676620432L, 1692961062L, 1709046739L, 1724875040L, 1740443581L, 1755750017L,
+ 1770792044L, 1785567396L, 1800073849L, 1814309216L, 1828271356L, 1841958164L,
+ 1855367581L, 1868497586L, 1881346202L, 1893911494L, 1906191570L, 1918184581L,
+ 1929888720L, 1941302225L, 1952423377L, 1963250501L, 1973781967L, 1984016189L,
+ 1993951625L, 2003586779L, 2012920201L, 2021950484L, 2030676269L, 2039096241L,
+ 2047209133L, 2055013723L, 2062508835L, 2069693342L, 2076566160L, 2083126254L,
+ 2089372638L, 2095304370L, 2100920556L, 2106220352L, 2111202959L, 2115867626L,
+ 2120213651L, 2124240380L, 2127947206L, 2131333572L, 2134398966L, 2137142927L,
+ 2139565043L, 2141664948L, 2143442326L, 2144896910L, 2146028480L, 2146836866L,
+ 2147321946L, 2147483647L, 2147321946L, 2146836866L, 2146028480L, 2144896910L,
+ 2143442326L, 2141664948L, 2139565043L, 2137142927L, 2134398966L, 2131333572L,
+ 2127947206L, 2124240380L, 2120213651L, 2115867626L, 2111202959L, 2106220352L,
+ 2100920556L, 2095304370L, 2089372638L, 2083126254L, 2076566160L, 2069693342L,
+ 2062508835L, 2055013723L, 2047209133L, 2039096241L, 2030676269L, 2021950484L,
+ 2012920201L, 2003586779L, 1993951625L, 1984016189L, 1973781967L, 1963250501L,
+ 1952423377L, 1941302225L, 1929888720L, 1918184581L, 1906191570L, 1893911494L,
+ 1881346202L, 1868497586L, 1855367581L, 1841958164L, 1828271356L, 1814309216L,
+ 1800073849L, 1785567396L, 1770792044L, 1755750017L, 1740443581L, 1724875040L,
+ 1709046739L, 1692961062L, 1676620432L, 1660027308L, 1643184191L, 1626093616L,
+ 1608758157L, 1591180426L, 1573363068L, 1555308768L, 1537020244L, 1518500250L,
+ 1499751576L, 1480777044L, 1461579514L, 1442161874L, 1422527051L, 1402678000L,
+ 1382617710L, 1362349204L, 1341875533L, 1321199781L, 1300325060L, 1279254516L,
+ 1257991320L, 1236538675L, 1214899813L, 1193077991L, 1171076495L, 1148898640L,
+ 1126547765L, 1104027237L, 1081340445L, 1058490808L, 1035481766L, 1012316784L,
+ 988999351L, 965532978L, 941921200L, 918167572L, 894275671L, 870249095L,
+ 846091463L, 821806413L, 797397602L, 772868706L, 748223418L, 723465451L,
+ 698598533L, 673626408L, 648552838L, 623381598L, 598116479L, 572761285L,
+ 547319836L, 521795963L, 496193509L, 470516330L, 444768294L, 418953276L,
+ 393075166L, 367137861L, 341145265L, 315101295L, 289009871L, 262874923L,
+ 236700388L, 210490206L, 184248325L, 157978697L, 131685278L, 105372028L,
+ 79042909L, 52701887L, 26352928L, 0L, -26352928L, -52701887L, -79042909L,
+ -105372028L, -131685278L, -157978697L, -184248325L, -210490206L, -236700388L,
+ -262874923L, -289009871L, -315101295L, -341145265L, -367137861L, -393075166L,
+ -418953276L, -444768294L, -470516330L, -496193509L, -521795963L, -547319836L,
+ -572761285L, -598116479L, -623381598L, -648552838L, -673626408L, -698598533L,
+ -723465451L, -748223418L, -772868706L, -797397602L, -821806413L, -846091463L,
+ -870249095L, -894275671L, -918167572L, -941921200L, -965532978L, -988999351L,
+ -1012316784L, -1035481766L, -1058490808L, -1081340445L, -1104027237L,
+ -1126547765L, -1148898640L, -1171076495L, -1193077991L, -1214899813L,
+ -1236538675L, -1257991320L, -1279254516L, -1300325060L, -1321199781L,
+ -1341875533L, -1362349204L, -1382617710L, -1402678000L, -1422527051L,
+ -1442161874L, -1461579514L, -1480777044L, -1499751576L, -1518500250L,
+ -1537020244L, -1555308768L, -1573363068L, -1591180426L, -1608758157L,
+ -1626093616L, -1643184191L, -1660027308L, -1676620432L, -1692961062L,
+ -1709046739L, -1724875040L, -1740443581L, -1755750017L, -1770792044L,
+ -1785567396L, -1800073849L, -1814309216L, -1828271356L, -1841958164L,
+ -1855367581L, -1868497586L, -1881346202L, -1893911494L, -1906191570L,
+ -1918184581L, -1929888720L, -1941302225L, -1952423377L, -1963250501L,
+ -1973781967L, -1984016189L, -1993951625L, -2003586779L, -2012920201L,
+ -2021950484L, -2030676269L, -2039096241L, -2047209133L, -2055013723L,
+ -2062508835L, -2069693342L, -2076566160L, -2083126254L, -2089372638L,
+ -2095304370L, -2100920556L, -2106220352L, -2111202959L, -2115867626L,
+ -2120213651L, -2124240380L, -2127947206L, -2131333572L, -2134398966L,
+ -2137142927L, -2139565043L, -2141664948L, -2143442326L, -2144896910L,
+ -2146028480L, -2146836866L, -2147321946L, (q31_t)0x80000000, -2147321946L,
+ -2146836866L, -2146028480L, -2144896910L, -2143442326L, -2141664948L,
+ -2139565043L, -2137142927L, -2134398966L, -2131333572L, -2127947206L,
+ -2124240380L, -2120213651L, -2115867626L, -2111202959L, -2106220352L,
+ -2100920556L, -2095304370L, -2089372638L, -2083126254L, -2076566160L,
+ -2069693342L, -2062508835L, -2055013723L, -2047209133L, -2039096241L,
+ -2030676269L, -2021950484L, -2012920201L, -2003586779L, -1993951625L,
+ -1984016189L, -1973781967L, -1963250501L, -1952423377L, -1941302225L,
+ -1929888720L, -1918184581L, -1906191570L, -1893911494L, -1881346202L,
+ -1868497586L, -1855367581L, -1841958164L, -1828271356L, -1814309216L,
+ -1800073849L, -1785567396L, -1770792044L, -1755750017L, -1740443581L,
+ -1724875040L, -1709046739L, -1692961062L, -1676620432L, -1660027308L,
+ -1643184191L, -1626093616L, -1608758157L, -1591180426L, -1573363068L,
+ -1555308768L, -1537020244L, -1518500250L, -1499751576L, -1480777044L,
+ -1461579514L, -1442161874L, -1422527051L, -1402678000L, -1382617710L,
+ -1362349204L, -1341875533L, -1321199781L, -1300325060L, -1279254516L,
+ -1257991320L, -1236538675L, -1214899813L, -1193077991L, -1171076495L,
+ -1148898640L, -1126547765L, -1104027237L, -1081340445L, -1058490808L,
+ -1035481766L, -1012316784L, -988999351L, -965532978L, -941921200L,
+ -918167572L, -894275671L, -870249095L, -846091463L, -821806413L, -797397602L,
+ -772868706L, -748223418L, -723465451L, -698598533L, -673626408L, -648552838L,
+ -623381598L, -598116479L, -572761285L, -547319836L, -521795963L, -496193509L,
+ -470516330L, -444768294L, -418953276L, -393075166L, -367137861L, -341145265L,
+ -315101295L, -289009871L, -262874923L, -236700388L, -210490206L, -184248325L,
+ -157978697L, -131685278L, -105372028L, -79042909L, -52701887L, -26352928L, 0
+};
+
+/**
+ * \par
+ * Table values are in Q15 (1.15 fixed-point format) and generation is done in
+ * three steps. First, generate sin values in floating point:
+ * <pre>
+ * tableSize = 512;
+ * for(n = 0; n < (tableSize + 1); n++)
+ * {
+ * sinTable[n]= sin(2*pi*n/tableSize);
+ * } </pre>
+ * where pi value is 3.14159265358979
+ * \par
+ * Second, convert floating-point to Q15 (Fixed point):
+ * (sinTable[i] * pow(2, 15))
+ * \par
+ * Finally, round to the nearest integer value:
+ * sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5);
+ */
+const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1] = {
+ 0, 402, 804, 1206, 1608, 2009, 2411, 2811, 3212, 3612, 4011, 4410, 4808,
+ 5205, 5602, 5998, 6393, 6787, 7180, 7571, 7962, 8351, 8740, 9127, 9512,
+ 9896, 10279, 10660, 11039, 11417, 11793, 12167, 12540, 12910, 13279,
+ 13646, 14010, 14373, 14733, 15091, 15447, 15800, 16151, 16500, 16846,
+ 17190, 17531, 17869, 18205, 18538, 18868, 19195, 19520, 19841, 20160,
+ 20475, 20788, 21097, 21403, 21706, 22006, 22302, 22595, 22884, 23170,
+ 23453, 23732, 24008, 24279, 24548, 24812, 25073, 25330, 25583, 25833,
+ 26078, 26320, 26557, 26791, 27020, 27246, 27467, 27684, 27897, 28106,
+ 28311, 28511, 28707, 28899, 29086, 29269, 29448, 29622, 29792, 29957,
+ 30118, 30274, 30425, 30572, 30715, 30853, 30986, 31114, 31238, 31357,
+ 31471, 31581, 31686, 31786, 31881, 31972, 32058, 32138, 32214, 32286,
+ 32352, 32413, 32470, 32522, 32568, 32610, 32647, 32679, 32706, 32729,
+ 32746, 32758, 32766, 32767, 32766, 32758, 32746, 32729, 32706, 32679,
+ 32647, 32610, 32568, 32522, 32470, 32413, 32352, 32286, 32214, 32138,
+ 32058, 31972, 31881, 31786, 31686, 31581, 31471, 31357, 31238, 31114,
+ 30986, 30853, 30715, 30572, 30425, 30274, 30118, 29957, 29792, 29622,
+ 29448, 29269, 29086, 28899, 28707, 28511, 28311, 28106, 27897, 27684,
+ 27467, 27246, 27020, 26791, 26557, 26320, 26078, 25833, 25583, 25330,
+ 25073, 24812, 24548, 24279, 24008, 23732, 23453, 23170, 22884, 22595,
+ 22302, 22006, 21706, 21403, 21097, 20788, 20475, 20160, 19841, 19520,
+ 19195, 18868, 18538, 18205, 17869, 17531, 17190, 16846, 16500, 16151,
+ 15800, 15447, 15091, 14733, 14373, 14010, 13646, 13279, 12910, 12540,
+ 12167, 11793, 11417, 11039, 10660, 10279, 9896, 9512, 9127, 8740, 8351,
+ 7962, 7571, 7180, 6787, 6393, 5998, 5602, 5205, 4808, 4410, 4011, 3612,
+ 3212, 2811, 2411, 2009, 1608, 1206, 804, 402, 0, -402, -804, -1206,
+ -1608, -2009, -2411, -2811, -3212, -3612, -4011, -4410, -4808, -5205,
+ -5602, -5998, -6393, -6787, -7180, -7571, -7962, -8351, -8740, -9127,
+ -9512, -9896, -10279, -10660, -11039, -11417, -11793, -12167, -12540,
+ -12910, -13279, -13646, -14010, -14373, -14733, -15091, -15447, -15800,
+ -16151, -16500, -16846, -17190, -17531, -17869, -18205, -18538, -18868,
+ -19195, -19520, -19841, -20160, -20475, -20788, -21097, -21403, -21706,
+ -22006, -22302, -22595, -22884, -23170, -23453, -23732, -24008, -24279,
+ -24548, -24812, -25073, -25330, -25583, -25833, -26078, -26320, -26557,
+ -26791, -27020, -27246, -27467, -27684, -27897, -28106, -28311, -28511,
+ -28707, -28899, -29086, -29269, -29448, -29622, -29792, -29957, -30118,
+ -30274, -30425, -30572, -30715, -30853, -30986, -31114, -31238, -31357,
+ -31471, -31581, -31686, -31786, -31881, -31972, -32058, -32138, -32214,
+ -32286, -32352, -32413, -32470, -32522, -32568, -32610, -32647, -32679,
+ -32706, -32729, -32746, -32758, -32766, -32768, -32766, -32758, -32746,
+ -32729, -32706, -32679, -32647, -32610, -32568, -32522, -32470, -32413,
+ -32352, -32286, -32214, -32138, -32058, -31972, -31881, -31786, -31686,
+ -31581, -31471, -31357, -31238, -31114, -30986, -30853, -30715, -30572,
+ -30425, -30274, -30118, -29957, -29792, -29622, -29448, -29269, -29086,
+ -28899, -28707, -28511, -28311, -28106, -27897, -27684, -27467, -27246,
+ -27020, -26791, -26557, -26320, -26078, -25833, -25583, -25330, -25073,
+ -24812, -24548, -24279, -24008, -23732, -23453, -23170, -22884, -22595,
+ -22302, -22006, -21706, -21403, -21097, -20788, -20475, -20160, -19841,
+ -19520, -19195, -18868, -18538, -18205, -17869, -17531, -17190, -16846,
+ -16500, -16151, -15800, -15447, -15091, -14733, -14373, -14010, -13646,
+ -13279, -12910, -12540, -12167, -11793, -11417, -11039, -10660, -10279,
+ -9896, -9512, -9127, -8740, -8351, -7962, -7571, -7180, -6787, -6393,
+ -5998, -5602, -5205, -4808, -4410, -4011, -3612, -3212, -2811, -2411,
+ -2009, -1608, -1206, -804, -402, 0
+};
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/CommonTables/arm_const_structs.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/CommonTables/arm_const_structs.c
new file mode 100644
index 0000000..96808d3
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/CommonTables/arm_const_structs.c
@@ -0,0 +1,379 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_const_structs.c
+ * Description: Constant structs that are initialized for user convenience.
+ * For example, some can be given as arguments to the arm_cfft_f32() or arm_rfft_f32() functions.
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_const_structs.h"
+
+/* Floating-point structs */
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = {
+ 16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE_16_TABLE_LENGTH
+};
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = {
+ 32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE_32_TABLE_LENGTH
+};
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = {
+ 64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE_64_TABLE_LENGTH
+};
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = {
+ 128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH
+};
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = {
+ 256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH
+};
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = {
+ 512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH
+};
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = {
+ 1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE_1024_TABLE_LENGTH
+};
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = {
+ 2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE_2048_TABLE_LENGTH
+};
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = {
+ 4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE_4096_TABLE_LENGTH
+};
+
+/* Fixed-point structs */
+const arm_cfft_instance_q31 arm_cfft_sR_q31_len16 = {
+ 16, twiddleCoef_16_q31, armBitRevIndexTable_fixed_16, ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q31 arm_cfft_sR_q31_len32 = {
+ 32, twiddleCoef_32_q31, armBitRevIndexTable_fixed_32, ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q31 arm_cfft_sR_q31_len64 = {
+ 64, twiddleCoef_64_q31, armBitRevIndexTable_fixed_64, ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q31 arm_cfft_sR_q31_len128 = {
+ 128, twiddleCoef_128_q31, armBitRevIndexTable_fixed_128, ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q31 arm_cfft_sR_q31_len256 = {
+ 256, twiddleCoef_256_q31, armBitRevIndexTable_fixed_256, ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q31 arm_cfft_sR_q31_len512 = {
+ 512, twiddleCoef_512_q31, armBitRevIndexTable_fixed_512, ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024 = {
+ 1024, twiddleCoef_1024_q31, armBitRevIndexTable_fixed_1024, ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048 = {
+ 2048, twiddleCoef_2048_q31, armBitRevIndexTable_fixed_2048, ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096 = {
+ 4096, twiddleCoef_4096_q31, armBitRevIndexTable_fixed_4096, ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q15 arm_cfft_sR_q15_len16 = {
+ 16, twiddleCoef_16_q15, armBitRevIndexTable_fixed_16, ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q15 arm_cfft_sR_q15_len32 = {
+ 32, twiddleCoef_32_q15, armBitRevIndexTable_fixed_32, ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q15 arm_cfft_sR_q15_len64 = {
+ 64, twiddleCoef_64_q15, armBitRevIndexTable_fixed_64, ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q15 arm_cfft_sR_q15_len128 = {
+ 128, twiddleCoef_128_q15, armBitRevIndexTable_fixed_128, ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q15 arm_cfft_sR_q15_len256 = {
+ 256, twiddleCoef_256_q15, armBitRevIndexTable_fixed_256, ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q15 arm_cfft_sR_q15_len512 = {
+ 512, twiddleCoef_512_q15, armBitRevIndexTable_fixed_512, ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024 = {
+ 1024, twiddleCoef_1024_q15, armBitRevIndexTable_fixed_1024, ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048 = {
+ 2048, twiddleCoef_2048_q15, armBitRevIndexTable_fixed_2048, ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096 = {
+ 4096, twiddleCoef_4096_q15, armBitRevIndexTable_fixed_4096, ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH
+};
+
+/* Structure for real-value inputs */
+/* Floating-point structs */
+const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len32 = {
+ { 16, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE_16_TABLE_LENGTH },
+ 32U,
+ (float32_t *)twiddleCoef_rfft_32
+};
+
+const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len64 = {
+ { 32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE_32_TABLE_LENGTH },
+ 64U,
+ (float32_t *)twiddleCoef_rfft_64
+};
+
+const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len128 = {
+ { 64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE_64_TABLE_LENGTH },
+ 128U,
+ (float32_t *)twiddleCoef_rfft_128
+};
+
+const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len256 = {
+ { 128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH },
+ 256U,
+ (float32_t *)twiddleCoef_rfft_256
+};
+
+const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len512 = {
+ { 256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH },
+ 512U,
+ (float32_t *)twiddleCoef_rfft_512
+};
+
+const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len1024 = {
+ { 512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH },
+ 1024U,
+ (float32_t *)twiddleCoef_rfft_1024
+};
+
+const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len2048 = {
+ { 1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE_1024_TABLE_LENGTH },
+ 2048U,
+ (float32_t *)twiddleCoef_rfft_2048
+};
+
+const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len4096 = {
+ { 2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE_2048_TABLE_LENGTH },
+ 4096U,
+ (float32_t *)twiddleCoef_rfft_4096
+};
+
+/* Fixed-point structs */
+/* q31_t */
+extern const q31_t realCoefAQ31[8192];
+extern const q31_t realCoefBQ31[8192];
+
+const arm_rfft_instance_q31 arm_rfft_sR_q31_len32 = {
+ 32U,
+ 0,
+ 1,
+ 256U,
+ (q31_t*)realCoefAQ31,
+ (q31_t*)realCoefBQ31,
+ &arm_cfft_sR_q31_len16
+};
+
+const arm_rfft_instance_q31 arm_rfft_sR_q31_len64 = {
+ 64U,
+ 0,
+ 1,
+ 128U,
+ (q31_t*)realCoefAQ31,
+ (q31_t*)realCoefBQ31,
+ &arm_cfft_sR_q31_len32
+};
+
+const arm_rfft_instance_q31 arm_rfft_sR_q31_len128 = {
+ 128U,
+ 0,
+ 1,
+ 64U,
+ (q31_t*)realCoefAQ31,
+ (q31_t*)realCoefBQ31,
+ &arm_cfft_sR_q31_len64
+};
+
+const arm_rfft_instance_q31 arm_rfft_sR_q31_len256 = {
+ 256U,
+ 0,
+ 1,
+ 32U,
+ (q31_t*)realCoefAQ31,
+ (q31_t*)realCoefBQ31,
+ &arm_cfft_sR_q31_len128
+};
+
+const arm_rfft_instance_q31 arm_rfft_sR_q31_len512 = {
+ 512U,
+ 0,
+ 1,
+ 16U,
+ (q31_t*)realCoefAQ31,
+ (q31_t*)realCoefBQ31,
+ &arm_cfft_sR_q31_len256
+};
+
+const arm_rfft_instance_q31 arm_rfft_sR_q31_len1024 = {
+ 1024U,
+ 0,
+ 1,
+ 8U,
+ (q31_t*)realCoefAQ31,
+ (q31_t*)realCoefBQ31,
+ &arm_cfft_sR_q31_len512
+};
+
+const arm_rfft_instance_q31 arm_rfft_sR_q31_len2048 = {
+ 2048U,
+ 0,
+ 1,
+ 4U,
+ (q31_t*)realCoefAQ31,
+ (q31_t*)realCoefBQ31,
+ &arm_cfft_sR_q31_len1024
+};
+
+const arm_rfft_instance_q31 arm_rfft_sR_q31_len4096 = {
+ 4096U,
+ 0,
+ 1,
+ 2U,
+ (q31_t*)realCoefAQ31,
+ (q31_t*)realCoefBQ31,
+ &arm_cfft_sR_q31_len2048
+};
+
+const arm_rfft_instance_q31 arm_rfft_sR_q31_len8192 = {
+ 8192U,
+ 0,
+ 1,
+ 1U,
+ (q31_t*)realCoefAQ31,
+ (q31_t*)realCoefBQ31,
+ &arm_cfft_sR_q31_len4096
+};
+
+/* q15_t */
+extern const q15_t realCoefAQ15[8192];
+extern const q15_t realCoefBQ15[8192];
+
+const arm_rfft_instance_q15 arm_rfft_sR_q15_len32 = {
+ 32U,
+ 0,
+ 1,
+ 256U,
+ (q15_t*)realCoefAQ15,
+ (q15_t*)realCoefBQ15,
+ &arm_cfft_sR_q15_len16
+};
+
+const arm_rfft_instance_q15 arm_rfft_sR_q15_len64 = {
+ 64U,
+ 0,
+ 1,
+ 128U,
+ (q15_t*)realCoefAQ15,
+ (q15_t*)realCoefBQ15,
+ &arm_cfft_sR_q15_len32
+};
+
+const arm_rfft_instance_q15 arm_rfft_sR_q15_len128 = {
+ 128U,
+ 0,
+ 1,
+ 64U,
+ (q15_t*)realCoefAQ15,
+ (q15_t*)realCoefBQ15,
+ &arm_cfft_sR_q15_len64
+};
+
+const arm_rfft_instance_q15 arm_rfft_sR_q15_len256 = {
+ 256U,
+ 0,
+ 1,
+ 32U,
+ (q15_t*)realCoefAQ15,
+ (q15_t*)realCoefBQ15,
+ &arm_cfft_sR_q15_len128
+};
+
+const arm_rfft_instance_q15 arm_rfft_sR_q15_len512 = {
+ 512U,
+ 0,
+ 1,
+ 16U,
+ (q15_t*)realCoefAQ15,
+ (q15_t*)realCoefBQ15,
+ &arm_cfft_sR_q15_len256
+};
+
+const arm_rfft_instance_q15 arm_rfft_sR_q15_len1024 = {
+ 1024U,
+ 0,
+ 1,
+ 8U,
+ (q15_t*)realCoefAQ15,
+ (q15_t*)realCoefBQ15,
+ &arm_cfft_sR_q15_len512
+};
+
+const arm_rfft_instance_q15 arm_rfft_sR_q15_len2048 = {
+ 2048U,
+ 0,
+ 1,
+ 4U,
+ (q15_t*)realCoefAQ15,
+ (q15_t*)realCoefBQ15,
+ &arm_cfft_sR_q15_len1024
+};
+
+const arm_rfft_instance_q15 arm_rfft_sR_q15_len4096 = {
+ 4096U,
+ 0,
+ 1,
+ 2U,
+ (q15_t*)realCoefAQ15,
+ (q15_t*)realCoefBQ15,
+ &arm_cfft_sR_q15_len2048
+};
+
+const arm_rfft_instance_q15 arm_rfft_sR_q15_len8192 = {
+ 8192U,
+ 0,
+ 1,
+ 1U,
+ (q15_t*)realCoefAQ15,
+ (q15_t*)realCoefBQ15,
+ &arm_cfft_sR_q15_len4096
+};
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c
new file mode 100644
index 0000000..29e74bc
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c
@@ -0,0 +1,171 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_conj_f32.c
+ * Description: Floating-point complex conjugate
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @defgroup cmplx_conj Complex Conjugate
+ *
+ * Conjugates the elements of a complex data vector.
+ *
+ * The <code>pSrc</code> points to the source data and
+ * <code>pDst</code> points to the where the result should be written.
+ * <code>numSamples</code> specifies the number of complex samples
+ * and the data in each array is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * Each array has a total of <code>2*numSamples</code> values.
+ * The underlying algorithm is used:
+ *
+ * <pre>
+ * for(n=0; n<numSamples; n++) {
+ * pDst[(2*n)+0)] = pSrc[(2*n)+0]; // real part
+ * pDst[(2*n)+1)] = -pSrc[(2*n)+1]; // imag part
+ * }
+ * </pre>
+ *
+ * There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup cmplx_conj
+ * @{
+ */
+
+/**
+ * @brief Floating-point complex conjugate.
+ * @param *pSrc points to the input vector
+ * @param *pDst points to the output vector
+ * @param numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+void arm_cmplx_conj_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t inR1, inR2, inR3, inR4;
+ float32_t inI1, inI2, inI3, inI4;
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+ /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+ /* read real input samples */
+ inR1 = pSrc[0];
+ /* store real samples to destination */
+ pDst[0] = inR1;
+ inR2 = pSrc[2];
+ pDst[2] = inR2;
+ inR3 = pSrc[4];
+ pDst[4] = inR3;
+ inR4 = pSrc[6];
+ pDst[6] = inR4;
+
+ /* read imaginary input samples */
+ inI1 = pSrc[1];
+ inI2 = pSrc[3];
+
+ /* conjugate input */
+ inI1 = -inI1;
+
+ /* read imaginary input samples */
+ inI3 = pSrc[5];
+
+ /* conjugate input */
+ inI2 = -inI2;
+
+ /* read imaginary input samples */
+ inI4 = pSrc[7];
+
+ /* conjugate input */
+ inI3 = -inI3;
+
+ /* store imaginary samples to destination */
+ pDst[1] = inI1;
+ pDst[3] = inI2;
+
+ /* conjugate input */
+ inI4 = -inI4;
+
+ /* store imaginary samples to destination */
+ pDst[5] = inI3;
+
+ /* increment source pointer by 8 to process next sampels */
+ pSrc += 8U;
+
+ /* store imaginary sample to destination */
+ pDst[7] = inI4;
+
+ /* increment destination pointer by 8 to store next samples */
+ pDst += 8U;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4U;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ blkCnt = numSamples;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ while (blkCnt > 0U)
+ {
+ /* realOut + j (imagOut) = realIn + j (-1) imagIn */
+ /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+ *pDst++ = *pSrc++;
+ *pDst++ = -*pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of cmplx_conj group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c
new file mode 100644
index 0000000..1e371bd
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c
@@ -0,0 +1,149 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_conj_q15.c
+ * Description: Q15 complex conjugate
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_conj
+ * @{
+ */
+
+/**
+ * @brief Q15 complex conjugate.
+ * @param *pSrc points to the input vector
+ * @param *pDst points to the output vector
+ * @param numSamples number of complex samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF.
+ */
+
+void arm_cmplx_conj_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples)
+{
+
+#if defined (ARM_MATH_DSP)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counter */
+ q31_t in1, in2, in3, in4;
+ q31_t zero = 0;
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+ /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+ in1 = *__SIMD32(pSrc)++;
+ in2 = *__SIMD32(pSrc)++;
+ in3 = *__SIMD32(pSrc)++;
+ in4 = *__SIMD32(pSrc)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ in1 = __QASX(zero, in1);
+ in2 = __QASX(zero, in2);
+ in3 = __QASX(zero, in3);
+ in4 = __QASX(zero, in4);
+
+#else
+
+ in1 = __QSAX(zero, in1);
+ in2 = __QSAX(zero, in2);
+ in3 = __QSAX(zero, in3);
+ in4 = __QSAX(zero, in4);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ in1 = ((uint32_t) in1 >> 16) | ((uint32_t) in1 << 16);
+ in2 = ((uint32_t) in2 >> 16) | ((uint32_t) in2 << 16);
+ in3 = ((uint32_t) in3 >> 16) | ((uint32_t) in3 << 16);
+ in4 = ((uint32_t) in4 >> 16) | ((uint32_t) in4 << 16);
+
+ *__SIMD32(pDst)++ = in1;
+ *__SIMD32(pDst)++ = in2;
+ *__SIMD32(pDst)++ = in3;
+ *__SIMD32(pDst)++ = in4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+ /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+ *pDst++ = *pSrc++;
+ *pDst++ = __SSAT(-*pSrc++, 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ q15_t in;
+
+ /* Run the below code for Cortex-M0 */
+
+ while (numSamples > 0U)
+ {
+ /* realOut + j (imagOut) = realIn+ j (-1) imagIn */
+ /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+ *pDst++ = *pSrc++;
+ in = *pSrc++;
+ *pDst++ = (in == (q15_t) 0x8000) ? 0x7fff : -in;
+
+ /* Decrement the loop counter */
+ numSamples--;
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of cmplx_conj group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c
new file mode 100644
index 0000000..af14414
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c
@@ -0,0 +1,169 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_conj_q31.c
+ * Description: Q31 complex conjugate
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_conj
+ * @{
+ */
+
+/**
+ * @brief Q31 complex conjugate.
+ * @param *pSrc points to the input vector
+ * @param *pDst points to the output vector
+ * @param numSamples number of complex samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF.
+ */
+
+void arm_cmplx_conj_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples)
+{
+ uint32_t blkCnt; /* loop counter */
+ q31_t in; /* Input value */
+
+#if defined (ARM_MATH_DSP)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t inR1, inR2, inR3, inR4; /* Temporary real variables */
+ q31_t inI1, inI2, inI3, inI4; /* Temporary imaginary variables */
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+ /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+ /* Saturated to 0x7fffffff if the input is -1(0x80000000) */
+ /* read real input sample */
+ inR1 = pSrc[0];
+ /* store real input sample */
+ pDst[0] = inR1;
+
+ /* read imaginary input sample */
+ inI1 = pSrc[1];
+
+ /* read real input sample */
+ inR2 = pSrc[2];
+ /* store real input sample */
+ pDst[2] = inR2;
+
+ /* read imaginary input sample */
+ inI2 = pSrc[3];
+
+ /* negate imaginary input sample */
+ inI1 = __QSUB(0, inI1);
+
+ /* read real input sample */
+ inR3 = pSrc[4];
+ /* store real input sample */
+ pDst[4] = inR3;
+
+ /* read imaginary input sample */
+ inI3 = pSrc[5];
+
+ /* negate imaginary input sample */
+ inI2 = __QSUB(0, inI2);
+
+ /* read real input sample */
+ inR4 = pSrc[6];
+ /* store real input sample */
+ pDst[6] = inR4;
+
+ /* negate imaginary input sample */
+ inI3 = __QSUB(0, inI3);
+
+ /* store imaginary input sample */
+ inI4 = pSrc[7];
+
+ /* store imaginary input samples */
+ pDst[1] = inI1;
+
+ /* negate imaginary input sample */
+ inI4 = __QSUB(0, inI4);
+
+ /* store imaginary input samples */
+ pDst[3] = inI2;
+
+ /* increment source pointer by 8 to proecess next samples */
+ pSrc += 8U;
+
+ /* store imaginary input samples */
+ pDst[5] = inI3;
+ pDst[7] = inI4;
+
+ /* increment destination pointer by 8 to process next samples */
+ pDst += 8U;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4U;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ blkCnt = numSamples;
+
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ while (blkCnt > 0U)
+ {
+ /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+ /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+ /* Saturated to 0x7fffffff if the input is -1(0x80000000) */
+ *pDst++ = *pSrc++;
+ in = *pSrc++;
+ *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of cmplx_conj group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
new file mode 100644
index 0000000..aac177f
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
@@ -0,0 +1,191 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_dot_prod_f32.c
+ * Description: Floating-point complex dot product
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @defgroup cmplx_dot_prod Complex Dot Product
+ *
+ * Computes the dot product of two complex vectors.
+ * The vectors are multiplied element-by-element and then summed.
+ *
+ * The <code>pSrcA</code> points to the first complex input vector and
+ * <code>pSrcB</code> points to the second complex input vector.
+ * <code>numSamples</code> specifies the number of complex samples
+ * and the data in each array is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * Each array has a total of <code>2*numSamples</code> values.
+ *
+ * The underlying algorithm is used:
+ * <pre>
+ * realResult=0;
+ * imagResult=0;
+ * for(n=0; n<numSamples; n++) {
+ * realResult += pSrcA[(2*n)+0]*pSrcB[(2*n)+0] - pSrcA[(2*n)+1]*pSrcB[(2*n)+1];
+ * imagResult += pSrcA[(2*n)+0]*pSrcB[(2*n)+1] + pSrcA[(2*n)+1]*pSrcB[(2*n)+0];
+ * }
+ * </pre>
+ *
+ * There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup cmplx_dot_prod
+ * @{
+ */
+
+/**
+ * @brief Floating-point complex dot product
+ * @param *pSrcA points to the first input vector
+ * @param *pSrcB points to the second input vector
+ * @param numSamples number of complex samples in each vector
+ * @param *realResult real part of the result returned here
+ * @param *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+void arm_cmplx_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult)
+{
+ float32_t real_sum = 0.0f, imag_sum = 0.0f; /* Temporary result storage */
+ float32_t a0,b0,c0,d0;
+
+#if defined (ARM_MATH_DSP)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counter */
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += a0 * c0;
+ imag_sum += a0 * d0;
+ real_sum -= b0 * d0;
+ imag_sum += b0 * c0;
+
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += a0 * c0;
+ imag_sum += a0 * d0;
+ real_sum -= b0 * d0;
+ imag_sum += b0 * c0;
+
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += a0 * c0;
+ imag_sum += a0 * d0;
+ real_sum -= b0 * d0;
+ imag_sum += b0 * c0;
+
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += a0 * c0;
+ imag_sum += a0 * d0;
+ real_sum -= b0 * d0;
+ imag_sum += b0 * c0;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples & 0x3U;
+
+ while (blkCnt > 0U)
+ {
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += a0 * c0;
+ imag_sum += a0 * d0;
+ real_sum -= b0 * d0;
+ imag_sum += b0 * c0;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while (numSamples > 0U)
+ {
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += a0 * c0;
+ imag_sum += a0 * d0;
+ real_sum -= b0 * d0;
+ imag_sum += b0 * c0;
+
+ /* Decrement the loop counter */
+ numSamples--;
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ /* Store the real and imaginary results in the destination buffers */
+ *realResult = real_sum;
+ *imagResult = imag_sum;
+}
+
+/**
+ * @} end of cmplx_dot_prod group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
new file mode 100644
index 0000000..efe72a2
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
@@ -0,0 +1,177 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_dot_prod_q15.c
+ * Description: Processing function for the Q15 Complex Dot product
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_dot_prod
+ * @{
+ */
+
+/**
+ * @brief Q15 complex dot product
+ * @param *pSrcA points to the first input vector
+ * @param *pSrcB points to the second input vector
+ * @param numSamples number of complex samples in each vector
+ * @param *realResult real part of the result returned here
+ * @param *imagResult imaginary part of the result returned here
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The intermediate 1.15 by 1.15 multiplications are performed with full precision and yield a 2.30 result.
+ * These are accumulated in a 64-bit accumulator with 34.30 precision.
+ * As a final step, the accumulators are converted to 8.24 format.
+ * The return results <code>realResult</code> and <code>imagResult</code> are in 8.24 format.
+ */
+
+void arm_cmplx_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult)
+{
+ q63_t real_sum = 0, imag_sum = 0; /* Temporary result storage */
+ q15_t a0,b0,c0,d0;
+
+#if defined (ARM_MATH_DSP)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counter */
+
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += (q31_t)a0 * c0;
+ imag_sum += (q31_t)a0 * d0;
+ real_sum -= (q31_t)b0 * d0;
+ imag_sum += (q31_t)b0 * c0;
+
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += (q31_t)a0 * c0;
+ imag_sum += (q31_t)a0 * d0;
+ real_sum -= (q31_t)b0 * d0;
+ imag_sum += (q31_t)b0 * c0;
+
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += (q31_t)a0 * c0;
+ imag_sum += (q31_t)a0 * d0;
+ real_sum -= (q31_t)b0 * d0;
+ imag_sum += (q31_t)b0 * c0;
+
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += (q31_t)a0 * c0;
+ imag_sum += (q31_t)a0 * d0;
+ real_sum -= (q31_t)b0 * d0;
+ imag_sum += (q31_t)b0 * c0;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += (q31_t)a0 * c0;
+ imag_sum += (q31_t)a0 * d0;
+ real_sum -= (q31_t)b0 * d0;
+ imag_sum += (q31_t)b0 * c0;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while (numSamples > 0U)
+ {
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += a0 * c0;
+ imag_sum += a0 * d0;
+ real_sum -= b0 * d0;
+ imag_sum += b0 * c0;
+
+
+ /* Decrement the loop counter */
+ numSamples--;
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ /* Store the real and imaginary results in 8.24 format */
+ /* Convert real data in 34.30 to 8.24 by 6 right shifts */
+ *realResult = (q31_t) (real_sum >> 6);
+ /* Convert imaginary data in 34.30 to 8.24 by 6 right shifts */
+ *imagResult = (q31_t) (imag_sum >> 6);
+}
+
+/**
+ * @} end of cmplx_dot_prod group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
new file mode 100644
index 0000000..dfd3a4b
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
@@ -0,0 +1,175 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_dot_prod_q31.c
+ * Description: Q31 complex dot product
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_dot_prod
+ * @{
+ */
+
+/**
+ * @brief Q31 complex dot product
+ * @param *pSrcA points to the first input vector
+ * @param *pSrcB points to the second input vector
+ * @param numSamples number of complex samples in each vector
+ * @param *realResult real part of the result returned here
+ * @param *imagResult imaginary part of the result returned here
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The intermediate 1.31 by 1.31 multiplications are performed with 64-bit precision and then shifted to 16.48 format.
+ * The internal real and imaginary accumulators are in 16.48 format and provide 15 guard bits.
+ * Additions are nonsaturating and no overflow will occur as long as <code>numSamples</code> is less than 32768.
+ * The return results <code>realResult</code> and <code>imagResult</code> are in 16.48 format.
+ * Input down scaling is not required.
+ */
+
+void arm_cmplx_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult)
+{
+ q63_t real_sum = 0, imag_sum = 0; /* Temporary result storage */
+ q31_t a0,b0,c0,d0;
+
+#if defined (ARM_MATH_DSP)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counter */
+
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += ((q63_t)a0 * c0) >> 14;
+ imag_sum += ((q63_t)a0 * d0) >> 14;
+ real_sum -= ((q63_t)b0 * d0) >> 14;
+ imag_sum += ((q63_t)b0 * c0) >> 14;
+
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += ((q63_t)a0 * c0) >> 14;
+ imag_sum += ((q63_t)a0 * d0) >> 14;
+ real_sum -= ((q63_t)b0 * d0) >> 14;
+ imag_sum += ((q63_t)b0 * c0) >> 14;
+
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += ((q63_t)a0 * c0) >> 14;
+ imag_sum += ((q63_t)a0 * d0) >> 14;
+ real_sum -= ((q63_t)b0 * d0) >> 14;
+ imag_sum += ((q63_t)b0 * c0) >> 14;
+
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += ((q63_t)a0 * c0) >> 14;
+ imag_sum += ((q63_t)a0 * d0) >> 14;
+ real_sum -= ((q63_t)b0 * d0) >> 14;
+ imag_sum += ((q63_t)b0 * c0) >> 14;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += ((q63_t)a0 * c0) >> 14;
+ imag_sum += ((q63_t)a0 * d0) >> 14;
+ real_sum -= ((q63_t)b0 * d0) >> 14;
+ imag_sum += ((q63_t)b0 * c0) >> 14;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while (numSamples > 0U)
+ {
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += ((q63_t)a0 * c0) >> 14;
+ imag_sum += ((q63_t)a0 * d0) >> 14;
+ real_sum -= ((q63_t)b0 * d0) >> 14;
+ imag_sum += ((q63_t)b0 * c0) >> 14;
+
+ /* Decrement the loop counter */
+ numSamples--;
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ /* Store the real and imaginary results in 16.48 format */
+ *realResult = real_sum;
+ *imagResult = imag_sum;
+}
+
+/**
+ * @} end of cmplx_dot_prod group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c
new file mode 100644
index 0000000..6c8be8f
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c
@@ -0,0 +1,153 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_mag_f32.c
+ * Description: Floating-point complex magnitude
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @defgroup cmplx_mag Complex Magnitude
+ *
+ * Computes the magnitude of the elements of a complex data vector.
+ *
+ * The <code>pSrc</code> points to the source data and
+ * <code>pDst</code> points to the where the result should be written.
+ * <code>numSamples</code> specifies the number of complex samples
+ * in the input array and the data is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * The input array has a total of <code>2*numSamples</code> values;
+ * the output array has a total of <code>numSamples</code> values.
+ * The underlying algorithm is used:
+ *
+ * <pre>
+ * for(n=0; n<numSamples; n++) {
+ * pDst[n] = sqrt(pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2);
+ * }
+ * </pre>
+ *
+ * There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup cmplx_mag
+ * @{
+ */
+/**
+ * @brief Floating-point complex magnitude.
+ * @param[in] *pSrc points to complex input buffer
+ * @param[out] *pDst points to real output buffer
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ *
+ */
+
+
+void arm_cmplx_mag_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples)
+{
+ float32_t realIn, imagIn; /* Temporary variables to hold input values */
+
+#if defined (ARM_MATH_DSP)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counter */
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+
+ /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+ realIn = *pSrc++;
+ imagIn = *pSrc++;
+ /* store the result in the destination buffer. */
+ arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+ realIn = *pSrc++;
+ imagIn = *pSrc++;
+ arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+ realIn = *pSrc++;
+ imagIn = *pSrc++;
+ arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+ realIn = *pSrc++;
+ imagIn = *pSrc++;
+ arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+ realIn = *pSrc++;
+ imagIn = *pSrc++;
+ /* store the result in the destination buffer. */
+ arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while (numSamples > 0U)
+ {
+ /* out = sqrt((real * real) + (imag * imag)) */
+ realIn = *pSrc++;
+ imagIn = *pSrc++;
+ /* store the result in the destination buffer. */
+ arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+ /* Decrement the loop counter */
+ numSamples--;
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of cmplx_mag group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c
new file mode 100644
index 0000000..445c996
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c
@@ -0,0 +1,141 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_mag_q15.c
+ * Description: Q15 complex magnitude
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_mag
+ * @{
+ */
+
+
+/**
+ * @brief Q15 complex magnitude
+ * @param *pSrc points to the complex input vector
+ * @param *pDst points to the real output vector
+ * @param numSamples number of complex samples in the input vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function implements 1.15 by 1.15 multiplications and finally output is converted into 2.14 format.
+ */
+
+void arm_cmplx_mag_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples)
+{
+ q31_t acc0, acc1; /* Accumulators */
+
+#if defined (ARM_MATH_DSP)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counter */
+ q31_t in1, in2, in3, in4;
+ q31_t acc2, acc3;
+
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+
+ /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+ in1 = *__SIMD32(pSrc)++;
+ in2 = *__SIMD32(pSrc)++;
+ in3 = *__SIMD32(pSrc)++;
+ in4 = *__SIMD32(pSrc)++;
+
+ acc0 = __SMUAD(in1, in1);
+ acc1 = __SMUAD(in2, in2);
+ acc2 = __SMUAD(in3, in3);
+ acc3 = __SMUAD(in4, in4);
+
+ /* store the result in 2.14 format in the destination buffer. */
+ arm_sqrt_q15((q15_t) ((acc0) >> 17), pDst++);
+ arm_sqrt_q15((q15_t) ((acc1) >> 17), pDst++);
+ arm_sqrt_q15((q15_t) ((acc2) >> 17), pDst++);
+ arm_sqrt_q15((q15_t) ((acc3) >> 17), pDst++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+ in1 = *__SIMD32(pSrc)++;
+ acc0 = __SMUAD(in1, in1);
+
+ /* store the result in 2.14 format in the destination buffer. */
+ arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ q15_t real, imag; /* Temporary variables to hold input values */
+
+ while (numSamples > 0U)
+ {
+ /* out = sqrt(real * real + imag * imag) */
+ real = *pSrc++;
+ imag = *pSrc++;
+
+ acc0 = (real * real);
+ acc1 = (imag * imag);
+
+ /* store the result in 2.14 format in the destination buffer. */
+ arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
+
+ /* Decrement the loop counter */
+ numSamples--;
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of cmplx_mag group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c
new file mode 100644
index 0000000..c1fdfdf
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c
@@ -0,0 +1,173 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_mag_q31.c
+ * Description: Q31 complex magnitude
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_mag
+ * @{
+ */
+
+/**
+ * @brief Q31 complex magnitude
+ * @param *pSrc points to the complex input vector
+ * @param *pDst points to the real output vector
+ * @param numSamples number of complex samples in the input vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function implements 1.31 by 1.31 multiplications and finally output is converted into 2.30 format.
+ * Input down scaling is not required.
+ */
+
+void arm_cmplx_mag_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples)
+{
+ q31_t real, imag; /* Temporary variables to hold input values */
+ q31_t acc0, acc1; /* Accumulators */
+ uint32_t blkCnt; /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t real1, real2, imag1, imag2; /* Temporary variables to hold input values */
+ q31_t out1, out2, out3, out4; /* Accumulators */
+ q63_t mul1, mul2, mul3, mul4; /* Temporary variables */
+
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* read complex input from source buffer */
+ real1 = pSrc[0];
+ imag1 = pSrc[1];
+ real2 = pSrc[2];
+ imag2 = pSrc[3];
+
+ /* calculate power of input values */
+ mul1 = (q63_t) real1 *real1;
+ mul2 = (q63_t) imag1 *imag1;
+ mul3 = (q63_t) real2 *real2;
+ mul4 = (q63_t) imag2 *imag2;
+
+ /* get the result to 3.29 format */
+ out1 = (q31_t) (mul1 >> 33);
+ out2 = (q31_t) (mul2 >> 33);
+ out3 = (q31_t) (mul3 >> 33);
+ out4 = (q31_t) (mul4 >> 33);
+
+ /* add real and imaginary accumulators */
+ out1 = out1 + out2;
+ out3 = out3 + out4;
+
+ /* read complex input from source buffer */
+ real1 = pSrc[4];
+ imag1 = pSrc[5];
+ real2 = pSrc[6];
+ imag2 = pSrc[7];
+
+ /* calculate square root */
+ arm_sqrt_q31(out1, &pDst[0]);
+
+ /* calculate power of input values */
+ mul1 = (q63_t) real1 *real1;
+
+ /* calculate square root */
+ arm_sqrt_q31(out3, &pDst[1]);
+
+ /* calculate power of input values */
+ mul2 = (q63_t) imag1 *imag1;
+ mul3 = (q63_t) real2 *real2;
+ mul4 = (q63_t) imag2 *imag2;
+
+ /* get the result to 3.29 format */
+ out1 = (q31_t) (mul1 >> 33);
+ out2 = (q31_t) (mul2 >> 33);
+ out3 = (q31_t) (mul3 >> 33);
+ out4 = (q31_t) (mul4 >> 33);
+
+ /* add real and imaginary accumulators */
+ out1 = out1 + out2;
+ out3 = out3 + out4;
+
+ /* calculate square root */
+ arm_sqrt_q31(out1, &pDst[2]);
+
+ /* increment destination by 8 to process next samples */
+ pSrc += 8U;
+
+ /* calculate square root */
+ arm_sqrt_q31(out3, &pDst[3]);
+
+ /* increment destination by 4 to process next samples */
+ pDst += 4U;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4U;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ blkCnt = numSamples;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ while (blkCnt > 0U)
+ {
+ /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ /* store the result in 2.30 format in the destination buffer. */
+ arm_sqrt_q31(acc0 + acc1, pDst++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of cmplx_mag group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
new file mode 100644
index 0000000..a7a34a3
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
@@ -0,0 +1,204 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_mag_squared_f32.c
+ * Description: Floating-point complex magnitude squared
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @defgroup cmplx_mag_squared Complex Magnitude Squared
+ *
+ * Computes the magnitude squared of the elements of a complex data vector.
+ *
+ * The <code>pSrc</code> points to the source data and
+ * <code>pDst</code> points to the where the result should be written.
+ * <code>numSamples</code> specifies the number of complex samples
+ * in the input array and the data is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * The input array has a total of <code>2*numSamples</code> values;
+ * the output array has a total of <code>numSamples</code> values.
+ *
+ * The underlying algorithm is used:
+ *
+ * <pre>
+ * for(n=0; n<numSamples; n++) {
+ * pDst[n] = pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2;
+ * }
+ * </pre>
+ *
+ * There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup cmplx_mag_squared
+ * @{
+ */
+
+
+/**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+void arm_cmplx_mag_squared_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples)
+{
+ float32_t real, imag; /* Temporary variables to store real and imaginary values */
+ uint32_t blkCnt; /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+ float32_t real1, real2, real3, real4; /* Temporary variables to hold real values */
+ float32_t imag1, imag2, imag3, imag4; /* Temporary variables to hold imaginary values */
+ float32_t mul1, mul2, mul3, mul4; /* Temporary variables */
+ float32_t mul5, mul6, mul7, mul8; /* Temporary variables */
+ float32_t out1, out2, out3, out4; /* Temporary variables to hold output values */
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+ /* read real input sample from source buffer */
+ real1 = pSrc[0];
+ /* read imaginary input sample from source buffer */
+ imag1 = pSrc[1];
+
+ /* calculate power of real value */
+ mul1 = real1 * real1;
+
+ /* read real input sample from source buffer */
+ real2 = pSrc[2];
+
+ /* calculate power of imaginary value */
+ mul2 = imag1 * imag1;
+
+ /* read imaginary input sample from source buffer */
+ imag2 = pSrc[3];
+
+ /* calculate power of real value */
+ mul3 = real2 * real2;
+
+ /* read real input sample from source buffer */
+ real3 = pSrc[4];
+
+ /* calculate power of imaginary value */
+ mul4 = imag2 * imag2;
+
+ /* read imaginary input sample from source buffer */
+ imag3 = pSrc[5];
+
+ /* calculate power of real value */
+ mul5 = real3 * real3;
+ /* calculate power of imaginary value */
+ mul6 = imag3 * imag3;
+
+ /* read real input sample from source buffer */
+ real4 = pSrc[6];
+
+ /* accumulate real and imaginary powers */
+ out1 = mul1 + mul2;
+
+ /* read imaginary input sample from source buffer */
+ imag4 = pSrc[7];
+
+ /* accumulate real and imaginary powers */
+ out2 = mul3 + mul4;
+
+ /* calculate power of real value */
+ mul7 = real4 * real4;
+ /* calculate power of imaginary value */
+ mul8 = imag4 * imag4;
+
+ /* store output to destination */
+ pDst[0] = out1;
+
+ /* accumulate real and imaginary powers */
+ out3 = mul5 + mul6;
+
+ /* store output to destination */
+ pDst[1] = out2;
+
+ /* accumulate real and imaginary powers */
+ out4 = mul7 + mul8;
+
+ /* store output to destination */
+ pDst[2] = out3;
+
+ /* increment destination pointer by 8 to process next samples */
+ pSrc += 8U;
+
+ /* store output to destination */
+ pDst[3] = out4;
+
+ /* increment destination pointer by 4 to process next samples */
+ pDst += 4U;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4U;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ blkCnt = numSamples;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ while (blkCnt > 0U)
+ {
+ /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+ real = *pSrc++;
+ imag = *pSrc++;
+
+ /* out = (real * real) + (imag * imag) */
+ /* store the result in the destination buffer. */
+ *pDst++ = (real * real) + (imag * imag);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of cmplx_mag_squared group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
new file mode 100644
index 0000000..7876cdc
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_mag_squared_q15.c
+ * Description: Q15 complex magnitude squared
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_mag_squared
+ * @{
+ */
+
+/**
+ * @brief Q15 complex magnitude squared
+ * @param *pSrc points to the complex input vector
+ * @param *pDst points to the real output vector
+ * @param numSamples number of complex samples in the input vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format.
+ */
+
+void arm_cmplx_mag_squared_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples)
+{
+ q31_t acc0, acc1; /* Accumulators */
+
+#if defined (ARM_MATH_DSP)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counter */
+ q31_t in1, in2, in3, in4;
+ q31_t acc2, acc3;
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+ in1 = *__SIMD32(pSrc)++;
+ in2 = *__SIMD32(pSrc)++;
+ in3 = *__SIMD32(pSrc)++;
+ in4 = *__SIMD32(pSrc)++;
+
+ acc0 = __SMUAD(in1, in1);
+ acc1 = __SMUAD(in2, in2);
+ acc2 = __SMUAD(in3, in3);
+ acc3 = __SMUAD(in4, in4);
+
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ = (q15_t) (acc0 >> 17);
+ *pDst++ = (q15_t) (acc1 >> 17);
+ *pDst++ = (q15_t) (acc2 >> 17);
+ *pDst++ = (q15_t) (acc3 >> 17);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+ in1 = *__SIMD32(pSrc)++;
+ acc0 = __SMUAD(in1, in1);
+
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ = (q15_t) (acc0 >> 17);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ q15_t real, imag; /* Temporary variables to store real and imaginary values */
+
+ while (numSamples > 0U)
+ {
+ /* out = ((real * real) + (imag * imag)) */
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (real * real);
+ acc1 = (imag * imag);
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
+
+ /* Decrement the loop counter */
+ numSamples--;
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of cmplx_mag_squared group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
new file mode 100644
index 0000000..b9c0c0c
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
@@ -0,0 +1,149 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_mag_squared_q31.c
+ * Description: Q31 complex magnitude squared
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_mag_squared
+ * @{
+ */
+
+
+/**
+ * @brief Q31 complex magnitude squared
+ * @param *pSrc points to the complex input vector
+ * @param *pDst points to the real output vector
+ * @param numSamples number of complex samples in the input vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format.
+ * Input down scaling is not required.
+ */
+
+void arm_cmplx_mag_squared_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples)
+{
+ q31_t real, imag; /* Temporary variables to store real and imaginary values */
+ q31_t acc0, acc1; /* Accumulators */
+
+#if defined (ARM_MATH_DSP)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counter */
+
+ /* loop Unrolling */
+ blkCnt = numSamples >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ /* store the result in 3.29 format in the destination buffer. */
+ *pDst++ = acc0 + acc1;
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ /* store the result in 3.29 format in the destination buffer. */
+ *pDst++ = acc0 + acc1;
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ /* store the result in 3.29 format in the destination buffer. */
+ *pDst++ = acc0 + acc1;
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ /* store the result in 3.29 format in the destination buffer. */
+ *pDst++ = acc0 + acc1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ /* store the result in 3.29 format in the destination buffer. */
+ *pDst++ = acc0 + acc1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while (numSamples > 0U)
+ {
+ /* out = ((real * real) + (imag * imag)) */
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ /* store the result in 3.29 format in the destination buffer. */
+ *pDst++ = acc0 + acc1;
+
+ /* Decrement the loop counter */
+ numSamples--;
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of cmplx_mag_squared group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
new file mode 100644
index 0000000..90af35a
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
@@ -0,0 +1,196 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_mult_cmplx_f32.c
+ * Description: Floating-point complex-by-complex multiplication
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @defgroup CmplxByCmplxMult Complex-by-Complex Multiplication
+ *
+ * Multiplies a complex vector by another complex vector and generates a complex result.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * The parameter <code>numSamples</code> represents the number of complex
+ * samples processed. The complex arrays have a total of <code>2*numSamples</code>
+ * real values.
+ *
+ * The underlying algorithm is used:
+ *
+ * <pre>
+ * for(n=0; n<numSamples; n++) {
+ * pDst[(2*n)+0] = pSrcA[(2*n)+0] * pSrcB[(2*n)+0] - pSrcA[(2*n)+1] * pSrcB[(2*n)+1];
+ * pDst[(2*n)+1] = pSrcA[(2*n)+0] * pSrcB[(2*n)+1] + pSrcA[(2*n)+1] * pSrcB[(2*n)+0];
+ * }
+ * </pre>
+ *
+ * There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup CmplxByCmplxMult
+ * @{
+ */
+
+
+/**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+void arm_cmplx_mult_cmplx_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples)
+{
+ float32_t a1, b1, c1, d1; /* Temporary variables to store real and imaginary values */
+ uint32_t blkCnt; /* loop counters */
+
+#if defined (ARM_MATH_DSP)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t a2, b2, c2, d2; /* Temporary variables to store real and imaginary values */
+ float32_t acc1, acc2, acc3, acc4;
+
+
+ /* loop Unrolling */
+ blkCnt = numSamples >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a1 = *pSrcA; /* A[2 * i] */
+ c1 = *pSrcB; /* B[2 * i] */
+
+ b1 = *(pSrcA + 1); /* A[2 * i + 1] */
+ acc1 = a1 * c1; /* acc1 = A[2 * i] * B[2 * i] */
+
+ a2 = *(pSrcA + 2); /* A[2 * i + 2] */
+ acc2 = (b1 * c1); /* acc2 = A[2 * i + 1] * B[2 * i] */
+
+ d1 = *(pSrcB + 1); /* B[2 * i + 1] */
+ c2 = *(pSrcB + 2); /* B[2 * i + 2] */
+ acc1 -= b1 * d1; /* acc1 = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1] */
+
+ d2 = *(pSrcB + 3); /* B[2 * i + 3] */
+ acc3 = a2 * c2; /* acc3 = A[2 * i + 2] * B[2 * i + 2] */
+
+ b2 = *(pSrcA + 3); /* A[2 * i + 3] */
+ acc2 += (a1 * d1); /* acc2 = A[2 * i + 1] * B[2 * i] + A[2 * i] * B[2 * i + 1] */
+
+ a1 = *(pSrcA + 4); /* A[2 * i + 4] */
+ acc4 = (a2 * d2); /* acc4 = A[2 * i + 2] * B[2 * i + 3] */
+
+ c1 = *(pSrcB + 4); /* B[2 * i + 4] */
+ acc3 -= (b2 * d2); /* acc3 = A[2 * i + 2] * B[2 * i + 2] - A[2 * i + 3] * B[2 * i + 3] */
+ *pDst = acc1; /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1] */
+
+ b1 = *(pSrcA + 5); /* A[2 * i + 5] */
+ acc4 += b2 * c2; /* acc4 = A[2 * i + 2] * B[2 * i + 3] + A[2 * i + 3] * B[2 * i + 2] */
+
+ *(pDst + 1) = acc2; /* C[2 * i + 1] = A[2 * i + 1] * B[2 * i] + A[2 * i] * B[2 * i + 1] */
+ acc1 = (a1 * c1);
+
+ d1 = *(pSrcB + 5);
+ acc2 = (b1 * c1);
+
+ *(pDst + 2) = acc3;
+ *(pDst + 3) = acc4;
+
+ a2 = *(pSrcA + 6);
+ acc1 -= (b1 * d1);
+
+ c2 = *(pSrcB + 6);
+ acc2 += (a1 * d1);
+
+ b2 = *(pSrcA + 7);
+ acc3 = (a2 * c2);
+
+ d2 = *(pSrcB + 7);
+ acc4 = (b2 * c2);
+
+ *(pDst + 4) = acc1;
+ pSrcA += 8U;
+
+ acc3 -= (b2 * d2);
+ acc4 += (a2 * d2);
+
+ *(pDst + 5) = acc2;
+ pSrcB += 8U;
+
+ *(pDst + 6) = acc3;
+ *(pDst + 7) = acc4;
+
+ pDst += 8U;
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4U;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ blkCnt = numSamples;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ while (blkCnt > 0U)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a1 = *pSrcA++;
+ b1 = *pSrcA++;
+ c1 = *pSrcB++;
+ d1 = *pSrcB++;
+
+ /* store the result in the destination buffer. */
+ *pDst++ = (a1 * c1) - (b1 * d1);
+ *pDst++ = (a1 * d1) + (b1 * c1);
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of CmplxByCmplxMult group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
new file mode 100644
index 0000000..1dce470
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
@@ -0,0 +1,181 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_mult_cmplx_q15.c
+ * Description: Q15 complex-by-complex multiplication
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup CmplxByCmplxMult
+ * @{
+ */
+
+/**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format.
+ */
+
+void arm_cmplx_mult_cmplx_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples)
+{
+ q15_t a, b, c, d; /* Temporary variables to store real and imaginary values */
+
+#if defined (ARM_MATH_DSP)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counters */
+
+ /* loop Unrolling */
+ blkCnt = numSamples >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while (numSamples > 0U)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+ /* Decrement the blockSize loop counter */
+ numSamples--;
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of CmplxByCmplxMult group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
new file mode 100644
index 0000000..2eed4e8
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
@@ -0,0 +1,314 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_mult_cmplx_q31.c
+ * Description: Q31 complex-by-complex multiplication
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup CmplxByCmplxMult
+ * @{
+ */
+
+
+/**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format.
+ * Input down scaling is not required.
+ */
+
+void arm_cmplx_mult_cmplx_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples)
+{
+ q31_t a, b, c, d; /* Temporary variables to store real and imaginary values */
+ uint32_t blkCnt; /* loop counters */
+ q31_t mul1, mul2, mul3, mul4;
+ q31_t out1, out2;
+
+#if defined (ARM_MATH_DSP)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* loop Unrolling */
+ blkCnt = numSamples >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ mul1 = (q31_t) (((q63_t) a * c) >> 32);
+ mul2 = (q31_t) (((q63_t) b * d) >> 32);
+ mul3 = (q31_t) (((q63_t) a * d) >> 32);
+ mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+ mul1 = (mul1 >> 1);
+ mul2 = (mul2 >> 1);
+ mul3 = (mul3 >> 1);
+ mul4 = (mul4 >> 1);
+
+ out1 = mul1 - mul2;
+ out2 = mul3 + mul4;
+
+ /* store the real result in 3.29 format in the destination buffer. */
+ *pDst++ = out1;
+ /* store the imag result in 3.29 format in the destination buffer. */
+ *pDst++ = out2;
+
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ mul1 = (q31_t) (((q63_t) a * c) >> 32);
+ mul2 = (q31_t) (((q63_t) b * d) >> 32);
+ mul3 = (q31_t) (((q63_t) a * d) >> 32);
+ mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+ mul1 = (mul1 >> 1);
+ mul2 = (mul2 >> 1);
+ mul3 = (mul3 >> 1);
+ mul4 = (mul4 >> 1);
+
+ out1 = mul1 - mul2;
+ out2 = mul3 + mul4;
+
+ /* store the real result in 3.29 format in the destination buffer. */
+ *pDst++ = out1;
+ /* store the imag result in 3.29 format in the destination buffer. */
+ *pDst++ = out2;
+
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ mul1 = (q31_t) (((q63_t) a * c) >> 32);
+ mul2 = (q31_t) (((q63_t) b * d) >> 32);
+ mul3 = (q31_t) (((q63_t) a * d) >> 32);
+ mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+ mul1 = (mul1 >> 1);
+ mul2 = (mul2 >> 1);
+ mul3 = (mul3 >> 1);
+ mul4 = (mul4 >> 1);
+
+ out1 = mul1 - mul2;
+ out2 = mul3 + mul4;
+
+ /* store the real result in 3.29 format in the destination buffer. */
+ *pDst++ = out1;
+ /* store the imag result in 3.29 format in the destination buffer. */
+ *pDst++ = out2;
+
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ mul1 = (q31_t) (((q63_t) a * c) >> 32);
+ mul2 = (q31_t) (((q63_t) b * d) >> 32);
+ mul3 = (q31_t) (((q63_t) a * d) >> 32);
+ mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+ mul1 = (mul1 >> 1);
+ mul2 = (mul2 >> 1);
+ mul3 = (mul3 >> 1);
+ mul4 = (mul4 >> 1);
+
+ out1 = mul1 - mul2;
+ out2 = mul3 + mul4;
+
+ /* store the real result in 3.29 format in the destination buffer. */
+ *pDst++ = out1;
+ /* store the imag result in 3.29 format in the destination buffer. */
+ *pDst++ = out2;
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ mul1 = (q31_t) (((q63_t) a * c) >> 32);
+ mul2 = (q31_t) (((q63_t) b * d) >> 32);
+ mul3 = (q31_t) (((q63_t) a * d) >> 32);
+ mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+ mul1 = (mul1 >> 1);
+ mul2 = (mul2 >> 1);
+ mul3 = (mul3 >> 1);
+ mul4 = (mul4 >> 1);
+
+ out1 = mul1 - mul2;
+ out2 = mul3 + mul4;
+
+ /* store the real result in 3.29 format in the destination buffer. */
+ *pDst++ = out1;
+ /* store the imag result in 3.29 format in the destination buffer. */
+ *pDst++ = out2;
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* loop Unrolling */
+ blkCnt = numSamples >> 1U;
+
+ /* First part of the processing with loop unrolling. Compute 2 outputs at a time.
+ ** a second loop below computes the remaining 1 sample. */
+ while (blkCnt > 0U)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ mul1 = (q31_t) (((q63_t) a * c) >> 32);
+ mul2 = (q31_t) (((q63_t) b * d) >> 32);
+ mul3 = (q31_t) (((q63_t) a * d) >> 32);
+ mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+ mul1 = (mul1 >> 1);
+ mul2 = (mul2 >> 1);
+ mul3 = (mul3 >> 1);
+ mul4 = (mul4 >> 1);
+
+ out1 = mul1 - mul2;
+ out2 = mul3 + mul4;
+
+ /* store the real result in 3.29 format in the destination buffer. */
+ *pDst++ = out1;
+ /* store the imag result in 3.29 format in the destination buffer. */
+ *pDst++ = out2;
+
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ mul1 = (q31_t) (((q63_t) a * c) >> 32);
+ mul2 = (q31_t) (((q63_t) b * d) >> 32);
+ mul3 = (q31_t) (((q63_t) a * d) >> 32);
+ mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+ mul1 = (mul1 >> 1);
+ mul2 = (mul2 >> 1);
+ mul3 = (mul3 >> 1);
+ mul4 = (mul4 >> 1);
+
+ out1 = mul1 - mul2;
+ out2 = mul3 + mul4;
+
+ /* store the real result in 3.29 format in the destination buffer. */
+ *pDst++ = out1;
+ /* store the imag result in 3.29 format in the destination buffer. */
+ *pDst++ = out2;
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 2, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ mul1 = (q31_t) (((q63_t) a * c) >> 32);
+ mul2 = (q31_t) (((q63_t) b * d) >> 32);
+ mul3 = (q31_t) (((q63_t) a * d) >> 32);
+ mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+ mul1 = (mul1 >> 1);
+ mul2 = (mul2 >> 1);
+ mul3 = (mul3 >> 1);
+ mul4 = (mul4 >> 1);
+
+ out1 = mul1 - mul2;
+ out2 = mul3 + mul4;
+
+ /* store the real result in 3.29 format in the destination buffer. */
+ *pDst++ = out1;
+ /* store the imag result in 3.29 format in the destination buffer. */
+ *pDst++ = out2;
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of CmplxByCmplxMult group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c
new file mode 100644
index 0000000..6f45804
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c
@@ -0,0 +1,213 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_mult_real_f32.c
+ * Description: Floating-point complex by real multiplication
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @defgroup CmplxByRealMult Complex-by-Real Multiplication
+ *
+ * Multiplies a complex vector by a real vector and generates a complex result.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * The parameter <code>numSamples</code> represents the number of complex
+ * samples processed. The complex arrays have a total of <code>2*numSamples</code>
+ * real values while the real array has a total of <code>numSamples</code>
+ * real values.
+ *
+ * The underlying algorithm is used:
+ *
+ * <pre>
+ * for(n=0; n<numSamples; n++) {
+ * pCmplxDst[(2*n)+0] = pSrcCmplx[(2*n)+0] * pSrcReal[n];
+ * pCmplxDst[(2*n)+1] = pSrcCmplx[(2*n)+1] * pSrcReal[n];
+ * }
+ * </pre>
+ *
+ * There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup CmplxByRealMult
+ * @{
+ */
+
+
+/**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+void arm_cmplx_mult_real_f32(
+ float32_t * pSrcCmplx,
+ float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples)
+{
+ float32_t in; /* Temporary variable to store input value */
+ uint32_t blkCnt; /* loop counters */
+
+#if defined (ARM_MATH_DSP)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t inA1, inA2, inA3, inA4; /* Temporary variables to hold input data */
+ float32_t inA5, inA6, inA7, inA8; /* Temporary variables to hold input data */
+ float32_t inB1, inB2, inB3, inB4; /* Temporary variables to hold input data */
+ float32_t out1, out2, out3, out4; /* Temporary variables to hold output data */
+ float32_t out5, out6, out7, out8; /* Temporary variables to hold output data */
+
+ /* loop Unrolling */
+ blkCnt = numSamples >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C[2 * i] = A[2 * i] * B[i]. */
+ /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
+ /* read input from complex input buffer */
+ inA1 = pSrcCmplx[0];
+ inA2 = pSrcCmplx[1];
+ /* read input from real input buffer */
+ inB1 = pSrcReal[0];
+
+ /* read input from complex input buffer */
+ inA3 = pSrcCmplx[2];
+
+ /* multiply complex buffer real input with real buffer input */
+ out1 = inA1 * inB1;
+
+ /* read input from complex input buffer */
+ inA4 = pSrcCmplx[3];
+
+ /* multiply complex buffer imaginary input with real buffer input */
+ out2 = inA2 * inB1;
+
+ /* read input from real input buffer */
+ inB2 = pSrcReal[1];
+ /* read input from complex input buffer */
+ inA5 = pSrcCmplx[4];
+
+ /* multiply complex buffer real input with real buffer input */
+ out3 = inA3 * inB2;
+
+ /* read input from complex input buffer */
+ inA6 = pSrcCmplx[5];
+ /* read input from real input buffer */
+ inB3 = pSrcReal[2];
+
+ /* multiply complex buffer imaginary input with real buffer input */
+ out4 = inA4 * inB2;
+
+ /* read input from complex input buffer */
+ inA7 = pSrcCmplx[6];
+
+ /* multiply complex buffer real input with real buffer input */
+ out5 = inA5 * inB3;
+
+ /* read input from complex input buffer */
+ inA8 = pSrcCmplx[7];
+
+ /* multiply complex buffer imaginary input with real buffer input */
+ out6 = inA6 * inB3;
+
+ /* read input from real input buffer */
+ inB4 = pSrcReal[3];
+
+ /* store result to destination bufer */
+ pCmplxDst[0] = out1;
+
+ /* multiply complex buffer real input with real buffer input */
+ out7 = inA7 * inB4;
+
+ /* store result to destination bufer */
+ pCmplxDst[1] = out2;
+
+ /* multiply complex buffer imaginary input with real buffer input */
+ out8 = inA8 * inB4;
+
+ /* store result to destination bufer */
+ pCmplxDst[2] = out3;
+ pCmplxDst[3] = out4;
+ pCmplxDst[4] = out5;
+
+ /* incremnet complex input buffer by 8 to process next samples */
+ pSrcCmplx += 8U;
+
+ /* store result to destination bufer */
+ pCmplxDst[5] = out6;
+
+ /* increment real input buffer by 4 to process next samples */
+ pSrcReal += 4U;
+
+ /* store result to destination bufer */
+ pCmplxDst[6] = out7;
+ pCmplxDst[7] = out8;
+
+ /* increment destination buffer by 8 to process next sampels */
+ pCmplxDst += 8U;
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4U;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ blkCnt = numSamples;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ while (blkCnt > 0U)
+ {
+ /* C[2 * i] = A[2 * i] * B[i]. */
+ /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
+ in = *pSrcReal++;
+ /* store the result in the destination buffer. */
+ *pCmplxDst++ = (*pSrcCmplx++) * (in);
+ *pCmplxDst++ = (*pSrcCmplx++) * (in);
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of CmplxByRealMult group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c
new file mode 100644
index 0000000..abafc3b
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c
@@ -0,0 +1,191 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_mult_real_q15.c
+ * Description: Q15 complex by real multiplication
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup CmplxByRealMult
+ * @{
+ */
+
+
+/**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ */
+
+void arm_cmplx_mult_real_q15(
+ q15_t * pSrcCmplx,
+ q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples)
+{
+ q15_t in; /* Temporary variable to store input value */
+
+#if defined (ARM_MATH_DSP)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counters */
+ q31_t inA1, inA2; /* Temporary variables to hold input data */
+ q31_t inB1; /* Temporary variables to hold input data */
+ q15_t out1, out2, out3, out4; /* Temporary variables to hold output data */
+ q31_t mul1, mul2, mul3, mul4; /* Temporary variables to hold intermediate data */
+
+ /* loop Unrolling */
+ blkCnt = numSamples >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C[2 * i] = A[2 * i] * B[i]. */
+ /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
+ /* read complex number both real and imaginary from complex input buffer */
+ inA1 = *__SIMD32(pSrcCmplx)++;
+ /* read two real values at a time from real input buffer */
+ inB1 = *__SIMD32(pSrcReal)++;
+ /* read complex number both real and imaginary from complex input buffer */
+ inA2 = *__SIMD32(pSrcCmplx)++;
+
+ /* multiply complex number with real numbers */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1));
+ mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1));
+ mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16));
+ mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16));
+
+#else
+
+ mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
+ mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16));
+ mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1);
+ mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* saturate the result */
+ out1 = (q15_t) __SSAT(mul1 >> 15U, 16);
+ out2 = (q15_t) __SSAT(mul2 >> 15U, 16);
+ out3 = (q15_t) __SSAT(mul3 >> 15U, 16);
+ out4 = (q15_t) __SSAT(mul4 >> 15U, 16);
+
+ /* pack real and imaginary outputs and store them to destination */
+ *__SIMD32(pCmplxDst)++ = __PKHBT(out1, out2, 16);
+ *__SIMD32(pCmplxDst)++ = __PKHBT(out3, out4, 16);
+
+ inA1 = *__SIMD32(pSrcCmplx)++;
+ inB1 = *__SIMD32(pSrcReal)++;
+ inA2 = *__SIMD32(pSrcCmplx)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1));
+ mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1));
+ mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16));
+ mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16));
+
+#else
+
+ mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
+ mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16));
+ mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1);
+ mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ out1 = (q15_t) __SSAT(mul1 >> 15U, 16);
+ out2 = (q15_t) __SSAT(mul2 >> 15U, 16);
+ out3 = (q15_t) __SSAT(mul3 >> 15U, 16);
+ out4 = (q15_t) __SSAT(mul4 >> 15U, 16);
+
+ *__SIMD32(pCmplxDst)++ = __PKHBT(out1, out2, 16);
+ *__SIMD32(pCmplxDst)++ = __PKHBT(out3, out4, 16);
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* C[2 * i] = A[2 * i] * B[i]. */
+ /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
+ in = *pSrcReal++;
+ /* store the result in the destination buffer. */
+ *pCmplxDst++ =
+ (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+ *pCmplxDst++ =
+ (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while (numSamples > 0U)
+ {
+ /* realOut = realA * realB. */
+ /* imagOut = imagA * realB. */
+ in = *pSrcReal++;
+ /* store the result in the destination buffer. */
+ *pCmplxDst++ =
+ (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+ *pCmplxDst++ =
+ (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+
+ /* Decrement the numSamples loop counter */
+ numSamples--;
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of CmplxByRealMult group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c
new file mode 100644
index 0000000..aaa3ec0
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c
@@ -0,0 +1,211 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_mult_real_q31.c
+ * Description: Q31 complex by real multiplication
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup CmplxByRealMult
+ * @{
+ */
+
+
+/**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.
+ */
+
+void arm_cmplx_mult_real_q31(
+ q31_t * pSrcCmplx,
+ q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples)
+{
+ q31_t inA1; /* Temporary variable to store input value */
+
+#if defined (ARM_MATH_DSP)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counters */
+ q31_t inA2, inA3, inA4; /* Temporary variables to hold input data */
+ q31_t inB1, inB2; /* Temporary variabels to hold input data */
+ q31_t out1, out2, out3, out4; /* Temporary variables to hold output data */
+
+ /* loop Unrolling */
+ blkCnt = numSamples >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C[2 * i] = A[2 * i] * B[i]. */
+ /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
+ /* read real input from complex input buffer */
+ inA1 = *pSrcCmplx++;
+ inA2 = *pSrcCmplx++;
+ /* read input from real input bufer */
+ inB1 = *pSrcReal++;
+ inB2 = *pSrcReal++;
+ /* read imaginary input from complex input buffer */
+ inA3 = *pSrcCmplx++;
+ inA4 = *pSrcCmplx++;
+
+ /* multiply complex input with real input */
+ out1 = ((q63_t) inA1 * inB1) >> 32;
+ out2 = ((q63_t) inA2 * inB1) >> 32;
+ out3 = ((q63_t) inA3 * inB2) >> 32;
+ out4 = ((q63_t) inA4 * inB2) >> 32;
+
+ /* sature the result */
+ out1 = __SSAT(out1, 31);
+ out2 = __SSAT(out2, 31);
+ out3 = __SSAT(out3, 31);
+ out4 = __SSAT(out4, 31);
+
+ /* get result in 1.31 format */
+ out1 = out1 << 1;
+ out2 = out2 << 1;
+ out3 = out3 << 1;
+ out4 = out4 << 1;
+
+ /* store the result to destination buffer */
+ *pCmplxDst++ = out1;
+ *pCmplxDst++ = out2;
+ *pCmplxDst++ = out3;
+ *pCmplxDst++ = out4;
+
+ /* read real input from complex input buffer */
+ inA1 = *pSrcCmplx++;
+ inA2 = *pSrcCmplx++;
+ /* read input from real input bufer */
+ inB1 = *pSrcReal++;
+ inB2 = *pSrcReal++;
+ /* read imaginary input from complex input buffer */
+ inA3 = *pSrcCmplx++;
+ inA4 = *pSrcCmplx++;
+
+ /* multiply complex input with real input */
+ out1 = ((q63_t) inA1 * inB1) >> 32;
+ out2 = ((q63_t) inA2 * inB1) >> 32;
+ out3 = ((q63_t) inA3 * inB2) >> 32;
+ out4 = ((q63_t) inA4 * inB2) >> 32;
+
+ /* sature the result */
+ out1 = __SSAT(out1, 31);
+ out2 = __SSAT(out2, 31);
+ out3 = __SSAT(out3, 31);
+ out4 = __SSAT(out4, 31);
+
+ /* get result in 1.31 format */
+ out1 = out1 << 1;
+ out2 = out2 << 1;
+ out3 = out3 << 1;
+ out4 = out4 << 1;
+
+ /* store the result to destination buffer */
+ *pCmplxDst++ = out1;
+ *pCmplxDst++ = out2;
+ *pCmplxDst++ = out3;
+ *pCmplxDst++ = out4;
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* C[2 * i] = A[2 * i] * B[i]. */
+ /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
+ /* read real input from complex input buffer */
+ inA1 = *pSrcCmplx++;
+ inA2 = *pSrcCmplx++;
+ /* read input from real input bufer */
+ inB1 = *pSrcReal++;
+
+ /* multiply complex input with real input */
+ out1 = ((q63_t) inA1 * inB1) >> 32;
+ out2 = ((q63_t) inA2 * inB1) >> 32;
+
+ /* sature the result */
+ out1 = __SSAT(out1, 31);
+ out2 = __SSAT(out2, 31);
+
+ /* get result in 1.31 format */
+ out1 = out1 << 1;
+ out2 = out2 << 1;
+
+ /* store the result to destination buffer */
+ *pCmplxDst++ = out1;
+ *pCmplxDst++ = out2;
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while (numSamples > 0U)
+ {
+ /* realOut = realA * realB. */
+ /* imagReal = imagA * realB. */
+ inA1 = *pSrcReal++;
+ /* store the result in the destination buffer. */
+ *pCmplxDst++ =
+ (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * inA1) >> 31);
+ *pCmplxDst++ =
+ (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * inA1) >> 31);
+
+ /* Decrement the numSamples loop counter */
+ numSamples--;
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of CmplxByRealMult group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.c
new file mode 100644
index 0000000..e729500
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.c
@@ -0,0 +1,74 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_pid_init_f32.c
+ * Description: Floating-point PID Control initialization function
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] *S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state & 1 = reset the state.
+ * @return none.
+ * \par Description:
+ * \par
+ * The <code>resetStateFlag</code> specifies whether to set state to zero or not. \n
+ * The function computes the structure fields: <code>A0</code>, <code>A1</code> <code>A2</code>
+ * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)
+ * also sets the state variables to all zeros.
+ */
+
+void arm_pid_init_f32(
+ arm_pid_instance_f32 * S,
+ int32_t resetStateFlag)
+{
+
+ /* Derived coefficient A0 */
+ S->A0 = S->Kp + S->Ki + S->Kd;
+
+ /* Derived coefficient A1 */
+ S->A1 = (-S->Kp) - ((float32_t) 2.0 * S->Kd);
+
+ /* Derived coefficient A2 */
+ S->A2 = S->Kd;
+
+ /* Check whether state needs reset or not */
+ if (resetStateFlag)
+ {
+ /* Clear the state buffer. The size will be always 3 samples */
+ memset(S->state, 0, 3U * sizeof(float32_t));
+ }
+
+}
+
+/**
+ * @} end of PID group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.c
new file mode 100644
index 0000000..0f83f35
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.c
@@ -0,0 +1,110 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_pid_init_q15.c
+ * Description: Q15 PID Control initialization function
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+ * @details
+ * @param[in,out] *S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ * \par Description:
+ * \par
+ * The <code>resetStateFlag</code> specifies whether to set state to zero or not. \n
+ * The function computes the structure fields: <code>A0</code>, <code>A1</code> <code>A2</code>
+ * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)
+ * also sets the state variables to all zeros.
+ */
+
+void arm_pid_init_q15(
+ arm_pid_instance_q15 * S,
+ int32_t resetStateFlag)
+{
+
+#if defined (ARM_MATH_DSP)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Derived coefficient A0 */
+ S->A0 = __QADD16(__QADD16(S->Kp, S->Ki), S->Kd);
+
+ /* Derived coefficients and pack into A1 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ S->A1 = __PKHBT(-__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), S->Kd, 16);
+
+#else
+
+ S->A1 = __PKHBT(S->Kd, -__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Check whether state needs reset or not */
+ if (resetStateFlag)
+ {
+ /* Clear the state buffer. The size will be always 3 samples */
+ memset(S->state, 0, 3U * sizeof(q15_t));
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q31_t temp; /*to store the sum */
+
+ /* Derived coefficient A0 */
+ temp = S->Kp + S->Ki + S->Kd;
+ S->A0 = (q15_t) __SSAT(temp, 16);
+
+ /* Derived coefficients and pack into A1 */
+ temp = -(S->Kd + S->Kd + S->Kp);
+ S->A1 = (q15_t) __SSAT(temp, 16);
+ S->A2 = S->Kd;
+
+
+
+ /* Check whether state needs reset or not */
+ if (resetStateFlag)
+ {
+ /* Clear the state buffer. The size will be always 3 samples */
+ memset(S->state, 0, 3U * sizeof(q15_t));
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of PID group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.c
new file mode 100644
index 0000000..ce2936e
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.c
@@ -0,0 +1,95 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_pid_init_q31.c
+ * Description: Q31 PID Control initialization function
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q31 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ * \par Description:
+ * \par
+ * The <code>resetStateFlag</code> specifies whether to set state to zero or not. \n
+ * The function computes the structure fields: <code>A0</code>, <code>A1</code> <code>A2</code>
+ * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)
+ * also sets the state variables to all zeros.
+ */
+
+void arm_pid_init_q31(
+ arm_pid_instance_q31 * S,
+ int32_t resetStateFlag)
+{
+
+#if defined (ARM_MATH_DSP)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Derived coefficient A0 */
+ S->A0 = __QADD(__QADD(S->Kp, S->Ki), S->Kd);
+
+ /* Derived coefficient A1 */
+ S->A1 = -__QADD(__QADD(S->Kd, S->Kd), S->Kp);
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q31_t temp;
+
+ /* Derived coefficient A0 */
+ temp = clip_q63_to_q31((q63_t) S->Kp + S->Ki);
+ S->A0 = clip_q63_to_q31((q63_t) temp + S->Kd);
+
+ /* Derived coefficient A1 */
+ temp = clip_q63_to_q31((q63_t) S->Kd + S->Kd);
+ S->A1 = -clip_q63_to_q31((q63_t) temp + S->Kp);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ /* Derived coefficient A2 */
+ S->A2 = S->Kd;
+
+ /* Check whether state needs reset or not */
+ if (resetStateFlag)
+ {
+ /* Clear the state buffer. The size will be always 3 samples */
+ memset(S->state, 0, 3U * sizeof(q31_t));
+ }
+
+}
+
+/**
+ * @} end of PID group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.c
new file mode 100644
index 0000000..acc1709
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.c
@@ -0,0 +1,53 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_pid_reset_f32.c
+ * Description: Floating-point PID Control reset function
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+* @brief Reset function for the floating-point PID Control.
+* @param[in] *S Instance pointer of PID control data structure.
+* @return none.
+* \par Description:
+* The function resets the state buffer to zeros.
+*/
+void arm_pid_reset_f32(
+ arm_pid_instance_f32 * S)
+{
+
+ /* Clear the state buffer. The size will be always 3 samples */
+ memset(S->state, 0, 3U * sizeof(float32_t));
+}
+
+/**
+ * @} end of PID group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q15.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q15.c
new file mode 100644
index 0000000..59c4416
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q15.c
@@ -0,0 +1,52 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_pid_reset_q15.c
+ * Description: Q15 PID Control reset function
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+* @brief Reset function for the Q15 PID Control.
+* @param[in] *S Instance pointer of PID control data structure.
+* @return none.
+* \par Description:
+* The function resets the state buffer to zeros.
+*/
+void arm_pid_reset_q15(
+ arm_pid_instance_q15 * S)
+{
+ /* Reset state to zero, The size will be always 3 samples */
+ memset(S->state, 0, 3U * sizeof(q15_t));
+}
+
+/**
+ * @} end of PID group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q31.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q31.c
new file mode 100644
index 0000000..7112a77
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q31.c
@@ -0,0 +1,53 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_pid_reset_q31.c
+ * Description: Q31 PID Control reset function
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+* @brief Reset function for the Q31 PID Control.
+* @param[in] *S Instance pointer of PID control data structure.
+* @return none.
+* \par Description:
+* The function resets the state buffer to zeros.
+*/
+void arm_pid_reset_q31(
+ arm_pid_instance_q31 * S)
+{
+
+ /* Clear the state buffer. The size will be always 3 samples */
+ memset(S->state, 0, 3U * sizeof(q31_t));
+}
+
+/**
+ * @} end of PID group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_f32.c
new file mode 100644
index 0000000..2aff091
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_f32.c
@@ -0,0 +1,144 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_sin_cos_f32.c
+ * Description: Sine and Cosine calculation for floating-point values
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup SinCos Sine Cosine
+ *
+ * Computes the trigonometric sine and cosine values using a combination of table lookup
+ * and linear interpolation.
+ * There are separate functions for Q31 and floating-point data types.
+ * The input to the floating-point version is in degrees while the
+ * fixed-point Q31 have a scaled input with the range
+ * [-1 0.9999] mapping to [-180 +180] degrees.
+ *
+ * The floating point function also allows values that are out of the usual range. When this happens, the function will
+ * take extra time to adjust the input value to the range of [-180 180].
+ *
+ * The result is accurate to 5 digits after the decimal point.
+ *
+ * The implementation is based on table lookup using 360 values together with linear interpolation.
+ * The steps used are:
+ * -# Calculation of the nearest integer table index.
+ * -# Compute the fractional portion (fract) of the input.
+ * -# Fetch the value corresponding to \c index from sine table to \c y0 and also value from \c index+1 to \c y1.
+ * -# Sine value is computed as <code> *psinVal = y0 + (fract * (y1 - y0))</code>.
+ * -# Fetch the value corresponding to \c index from cosine table to \c y0 and also value from \c index+1 to \c y1.
+ * -# Cosine value is computed as <code> *pcosVal = y0 + (fract * (y1 - y0))</code>.
+ */
+
+ /**
+ * @addtogroup SinCos
+ * @{
+ */
+
+/**
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cos output.
+ * @return none.
+ */
+
+void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCosVal)
+{
+ float32_t fract, in; /* Temporary variables for input, output */
+ uint16_t indexS, indexC; /* Index variable */
+ float32_t f1, f2, d1, d2; /* Two nearest output values */
+ float32_t findex, Dn, Df, temp;
+
+ /* input x is in degrees */
+ /* Scale the input, divide input by 360, for cosine add 0.25 (pi/2) to read sine table */
+ in = theta * 0.00277777777778f;
+
+ if (in < 0.0f)
+ {
+ in = -in;
+ }
+
+ in = in - (int32_t)in;
+
+ /* Calculation of index of the table */
+ findex = (float32_t) FAST_MATH_TABLE_SIZE * in;
+ indexS = ((uint16_t)findex) & 0x1ff;
+ indexC = (indexS + (FAST_MATH_TABLE_SIZE / 4)) & 0x1ff;
+
+ /* fractional value calculation */
+ fract = findex - (float32_t) indexS;
+
+ /* Read two nearest values of input value from the cos & sin tables */
+ f1 = sinTable_f32[indexC+0];
+ f2 = sinTable_f32[indexC+1];
+ d1 = -sinTable_f32[indexS+0];
+ d2 = -sinTable_f32[indexS+1];
+
+ temp = (1.0f - fract) * f1 + fract * f2;
+
+ Dn = 0.0122718463030f; // delta between the two points (fixed), in this case 2*pi/FAST_MATH_TABLE_SIZE
+ Df = f2 - f1; // delta between the values of the functions
+
+ temp = Dn *(d1 + d2) - 2 * Df;
+ temp = fract * temp + (3 * Df - (d2 + 2 * d1) * Dn);
+ temp = fract * temp + d1 * Dn;
+
+ /* Calculation of cosine value */
+ *pCosVal = fract * temp + f1;
+
+ /* Read two nearest values of input value from the cos & sin tables */
+ f1 = sinTable_f32[indexS+0];
+ f2 = sinTable_f32[indexS+1];
+ d1 = sinTable_f32[indexC+0];
+ d2 = sinTable_f32[indexC+1];
+
+ temp = (1.0f - fract) * f1 + fract * f2;
+
+ Df = f2 - f1; // delta between the values of the functions
+ temp = Dn*(d1 + d2) - 2*Df;
+ temp = fract*temp + (3*Df - (d2 + 2*d1)*Dn);
+ temp = fract*temp + d1*Dn;
+
+ /* Calculation of sine value */
+ *pSinVal = fract*temp + f1;
+
+ if (theta < 0.0f)
+ {
+ *pSinVal = -*pSinVal;
+ }
+}
+/**
+ * @} end of SinCos group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_q31.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_q31.c
new file mode 100644
index 0000000..c1c33ec
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_q31.c
@@ -0,0 +1,110 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_sin_cos_q31.c
+ * Description: Cosine & Sine calculation for Q31 values
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupController
+ */
+
+ /**
+ * @addtogroup SinCos
+ * @{
+ */
+
+/**
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cosine output.
+ * @return none.
+ *
+ * The Q31 input value is in the range [-1 0.999999] and is mapped to a degree value in the range [-180 179].
+ *
+ */
+
+void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal)
+{
+ q31_t fract; /* Temporary variables for input, output */
+ uint16_t indexS, indexC; /* Index variable */
+ q31_t f1, f2, d1, d2; /* Two nearest output values */
+ q31_t Dn, Df;
+ q63_t temp;
+
+ /* Calculate the nearest index */
+ indexS = (uint32_t)theta >> CONTROLLER_Q31_SHIFT;
+ indexC = (indexS + 128) & 0x1ff;
+
+ /* Calculation of fractional value */
+ fract = (theta - (indexS << CONTROLLER_Q31_SHIFT)) << 8;
+
+ /* Read two nearest values of input value from the cos & sin tables */
+ f1 = sinTable_q31[indexC+0];
+ f2 = sinTable_q31[indexC+1];
+ d1 = -sinTable_q31[indexS+0];
+ d2 = -sinTable_q31[indexS+1];
+
+ Dn = 0x1921FB5; // delta between the two points (fixed), in this case 2*pi/FAST_MATH_TABLE_SIZE
+ Df = f2 - f1; // delta between the values of the functions
+ temp = Dn*((q63_t)d1 + d2);
+ temp = temp - ((q63_t)Df << 32);
+ temp = (q63_t)fract*(temp >> 31);
+ temp = temp + ((3*(q63_t)Df << 31) - (d2 + ((q63_t)d1 << 1))*Dn);
+ temp = (q63_t)fract*(temp >> 31);
+ temp = temp + (q63_t)d1*Dn;
+ temp = (q63_t)fract*(temp >> 31);
+
+ /* Calculation of cosine value */
+ *pCosVal = clip_q63_to_q31((temp >> 31) + (q63_t)f1);
+
+ /* Read two nearest values of input value from the cos & sin tables */
+ f1 = sinTable_q31[indexS+0];
+ f2 = sinTable_q31[indexS+1];
+ d1 = sinTable_q31[indexC+0];
+ d2 = sinTable_q31[indexC+1];
+
+ Df = f2 - f1; // delta between the values of the functions
+ temp = Dn*((q63_t)d1 + d2);
+ temp = temp - ((q63_t)Df << 32);
+ temp = (q63_t)fract*(temp >> 31);
+ temp = temp + ((3*(q63_t)Df << 31) - (d2 + ((q63_t)d1 << 1))*Dn);
+ temp = (q63_t)fract*(temp >> 31);
+ temp = temp + (q63_t)d1*Dn;
+ temp = (q63_t)fract*(temp >> 31);
+
+ /* Calculation of sine value */
+ *pSinVal = clip_q63_to_q31((temp >> 31) + (q63_t)f1);
+}
+
+/**
+ * @} end of SinCos group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FastMathFunctions/arm_cos_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FastMathFunctions/arm_cos_f32.c
new file mode 100644
index 0000000..44efbd5
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FastMathFunctions/arm_cos_f32.c
@@ -0,0 +1,115 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cos_f32.c
+ * Description: Fast cosine calculation for floating-point values
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+/**
+ * @ingroup groupFastMath
+ */
+
+/**
+ * @defgroup cos Cosine
+ *
+ * Computes the trigonometric cosine function using a combination of table lookup
+ * and linear interpolation. There are separate functions for
+ * Q15, Q31, and floating-point data types.
+ * The input to the floating-point version is in radians and in the range [0 2*pi) while the
+ * fixed-point Q15 and Q31 have a scaled input with the range
+ * [0 +0.9999] mapping to [0 2*pi). The fixed-point range is chosen so that a
+ * value of 2*pi wraps around to 0.
+ *
+ * The implementation is based on table lookup using 256 values together with linear interpolation.
+ * The steps used are:
+ * -# Calculation of the nearest integer table index
+ * -# Compute the fractional portion (fract) of the table index.
+ * -# The final result equals <code>(1.0f-fract)*a + fract*b;</code>
+ *
+ * where
+ * <pre>
+ * b=Table[index+0];
+ * c=Table[index+1];
+ * </pre>
+ */
+
+ /**
+ * @addtogroup cos
+ * @{
+ */
+
+/**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+
+float32_t arm_cos_f32(
+ float32_t x)
+{
+ float32_t cosVal, fract, in; /* Temporary variables for input, output */
+ uint16_t index; /* Index variable */
+ float32_t a, b; /* Two nearest output values */
+ int32_t n;
+ float32_t findex;
+
+ /* input x is in radians */
+ /* Scale the input to [0 1] range from [0 2*PI] , divide input by 2*pi, add 0.25 (pi/2) to read sine table */
+ in = x * 0.159154943092f + 0.25f;
+
+ /* Calculation of floor value of input */
+ n = (int32_t) in;
+
+ /* Make negative values towards -infinity */
+ if (in < 0.0f)
+ {
+ n--;
+ }
+
+ /* Map input value to [0 1] */
+ in = in - (float32_t) n;
+
+ /* Calculation of index of the table */
+ findex = (float32_t) FAST_MATH_TABLE_SIZE * in;
+ index = ((uint16_t)findex) & 0x1ff;
+
+ /* fractional value calculation */
+ fract = findex - (float32_t) index;
+
+ /* Read two nearest values of input value from the cos table */
+ a = sinTable_f32[index];
+ b = sinTable_f32[index+1];
+
+ /* Linear interpolation process */
+ cosVal = (1.0f-fract)*a + fract*b;
+
+ /* Return the output value */
+ return (cosVal);
+}
+
+/**
+ * @} end of cos group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q15.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q15.c
new file mode 100644
index 0000000..036c5d7
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q15.c
@@ -0,0 +1,84 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cos_q15.c
+ * Description: Fast cosine calculation for Q15 values
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupFastMath
+ */
+
+ /**
+ * @addtogroup cos
+ * @{
+ */
+
+/**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ *
+ * The Q15 input value is in the range [0 +0.9999] and is mapped to a radian
+ * value in the range [0 2*pi).
+ */
+
+q15_t arm_cos_q15(
+ q15_t x)
+{
+ q15_t cosVal; /* Temporary variables for input, output */
+ int32_t index; /* Index variables */
+ q15_t a, b; /* Four nearest output values */
+ q15_t fract; /* Temporary values for fractional values */
+
+ /* add 0.25 (pi/2) to read sine table */
+ x = (uint16_t)x + 0x2000;
+ if (x < 0)
+ { /* convert negative numbers to corresponding positive ones */
+ x = (uint16_t)x + 0x8000;
+ }
+
+ /* Calculate the nearest index */
+ index = (uint32_t)x >> FAST_MATH_Q15_SHIFT;
+
+ /* Calculation of fractional value */
+ fract = (x - (index << FAST_MATH_Q15_SHIFT)) << 9;
+
+ /* Read two nearest values of input value from the sin table */
+ a = sinTable_q15[index];
+ b = sinTable_q15[index+1];
+
+ /* Linear interpolation process */
+ cosVal = (q31_t)(0x8000-fract)*a >> 16;
+ cosVal = (q15_t)((((q31_t)cosVal << 16) + ((q31_t)fract*b)) >> 16);
+
+ return cosVal << 1;
+}
+
+/**
+ * @} end of cos group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q31.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q31.c
new file mode 100644
index 0000000..105addb
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q31.c
@@ -0,0 +1,84 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cos_q31.c
+ * Description: Fast cosine calculation for Q31 values
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupFastMath
+ */
+
+ /**
+ * @addtogroup cos
+ * @{
+ */
+
+/**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ *
+ * The Q31 input value is in the range [0 +0.9999] and is mapped to a radian
+ * value in the range [0 2*pi).
+ */
+
+q31_t arm_cos_q31(
+ q31_t x)
+{
+ q31_t cosVal; /* Temporary variables for input, output */
+ int32_t index; /* Index variables */
+ q31_t a, b; /* Four nearest output values */
+ q31_t fract; /* Temporary values for fractional values */
+
+ /* add 0.25 (pi/2) to read sine table */
+ x = (uint32_t)x + 0x20000000;
+ if (x < 0)
+ { /* convert negative numbers to corresponding positive ones */
+ x = (uint32_t)x + 0x80000000;
+ }
+
+ /* Calculate the nearest index */
+ index = (uint32_t)x >> FAST_MATH_Q31_SHIFT;
+
+ /* Calculation of fractional value */
+ fract = (x - (index << FAST_MATH_Q31_SHIFT)) << 9;
+
+ /* Read two nearest values of input value from the sin table */
+ a = sinTable_q31[index];
+ b = sinTable_q31[index+1];
+
+ /* Linear interpolation process */
+ cosVal = (q63_t)(0x80000000-fract)*a >> 32;
+ cosVal = (q31_t)((((q63_t)cosVal << 32) + ((q63_t)fract*b)) >> 32);
+
+ return cosVal << 1;
+}
+
+/**
+ * @} end of cos group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FastMathFunctions/arm_sin_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FastMathFunctions/arm_sin_f32.c
new file mode 100644
index 0000000..3fb5153
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FastMathFunctions/arm_sin_f32.c
@@ -0,0 +1,123 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_sin_f32.c
+ * Description: Fast sine calculation for floating-point values
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+#include <math.h>
+
+/**
+ * @ingroup groupFastMath
+ */
+
+/**
+ * @defgroup sin Sine
+ *
+ * Computes the trigonometric sine function using a combination of table lookup
+ * and linear interpolation. There are separate functions for
+ * Q15, Q31, and floating-point data types.
+ * The input to the floating-point version is in radians and in the range [0 2*pi) while the
+ * fixed-point Q15 and Q31 have a scaled input with the range
+ * [0 +0.9999] mapping to [0 2*pi). The fixed-point range is chosen so that a
+ * value of 2*pi wraps around to 0.
+ *
+ * The implementation is based on table lookup using 256 values together with linear interpolation.
+ * The steps used are:
+ * -# Calculation of the nearest integer table index
+ * -# Compute the fractional portion (fract) of the table index.
+ * -# The final result equals <code>(1.0f-fract)*a + fract*b;</code>
+ *
+ * where
+ * <pre>
+ * b=Table[index+0];
+ * c=Table[index+1];
+ * </pre>
+ */
+
+/**
+ * @addtogroup sin
+ * @{
+ */
+
+/**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+
+float32_t arm_sin_f32(
+ float32_t x)
+{
+ float32_t sinVal, fract, in; /* Temporary variables for input, output */
+ uint16_t index; /* Index variable */
+ float32_t a, b; /* Two nearest output values */
+ int32_t n;
+ float32_t findex;
+
+ /* Special case for small negative inputs */
+ if ((x < 0.0f) && (x >= -1.9e-7f)) {
+ return x;
+ }
+
+ /* input x is in radians */
+ /* Scale the input to [0 1] range from [0 2*PI] , divide input by 2*pi */
+ in = x * 0.159154943092f;
+
+ /* Calculation of floor value of input */
+ n = (int32_t) in;
+
+ /* Make negative values towards -infinity */
+ if (x < 0.0f)
+ {
+ n--;
+ }
+
+ /* Map input value to [0 1] */
+ in = in - (float32_t) n;
+
+ /* Calculation of index of the table */
+ findex = (float32_t) FAST_MATH_TABLE_SIZE * in;
+
+ index = ((uint16_t)findex) & 0x1ff;
+
+ /* fractional value calculation */
+ fract = findex - (float32_t) index;
+
+ /* Read two nearest values of input value from the sin table */
+ a = sinTable_f32[index];
+ b = sinTable_f32[index+1];
+
+ /* Linear interpolation process */
+ sinVal = (1.0f-fract)*a + fract*b;
+
+ /* Return the output value */
+ return (sinVal);
+}
+
+/**
+ * @} end of sin group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.c
new file mode 100644
index 0000000..9eecaa9
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.c
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_sin_q15.c
+ * Description: Fast sine calculation for Q15 values
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupFastMath
+ */
+
+ /**
+ * @addtogroup sin
+ * @{
+ */
+
+/**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ *
+ * The Q15 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi).
+ */
+
+q15_t arm_sin_q15(
+ q15_t x)
+{
+ q15_t sinVal; /* Temporary variables for input, output */
+ int32_t index; /* Index variables */
+ q15_t a, b; /* Four nearest output values */
+ q15_t fract; /* Temporary values for fractional values */
+
+ /* Calculate the nearest index */
+ index = (uint32_t)x >> FAST_MATH_Q15_SHIFT;
+
+ /* Calculation of fractional value */
+ fract = (x - (index << FAST_MATH_Q15_SHIFT)) << 9;
+
+ /* Read two nearest values of input value from the sin table */
+ a = sinTable_q15[index];
+ b = sinTable_q15[index+1];
+
+ /* Linear interpolation process */
+ sinVal = (q31_t)(0x8000-fract)*a >> 16;
+ sinVal = (q15_t)((((q31_t)sinVal << 16) + ((q31_t)fract*b)) >> 16);
+
+ return sinVal << 1;
+}
+
+/**
+ * @} end of sin group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q31.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q31.c
new file mode 100644
index 0000000..2119016
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q31.c
@@ -0,0 +1,75 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_sin_q31.c
+ * Description: Fast sine calculation for Q31 values
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupFastMath
+ */
+
+ /**
+ * @addtogroup sin
+ * @{
+ */
+
+/**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ *
+ * The Q31 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi). */
+
+q31_t arm_sin_q31(
+ q31_t x)
+{
+ q31_t sinVal; /* Temporary variables for input, output */
+ int32_t index; /* Index variables */
+ q31_t a, b; /* Four nearest output values */
+ q31_t fract; /* Temporary values for fractional values */
+
+ /* Calculate the nearest index */
+ index = (uint32_t)x >> FAST_MATH_Q31_SHIFT;
+
+ /* Calculation of fractional value */
+ fract = (x - (index << FAST_MATH_Q31_SHIFT)) << 9;
+
+ /* Read two nearest values of input value from the sin table */
+ a = sinTable_q31[index];
+ b = sinTable_q31[index+1];
+
+ /* Linear interpolation process */
+ sinVal = (q63_t)(0x80000000-fract)*a >> 32;
+ sinVal = (q31_t)((((q63_t)sinVal << 32) + ((q63_t)fract*b)) >> 32);
+
+ return sinVal << 1;
+}
+
+/**
+ * @} end of sin group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q15.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q15.c
new file mode 100644
index 0000000..83e4ddd
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q15.c
@@ -0,0 +1,144 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_sqrt_q15.c
+ * Description: Q15 square root function
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+
+/**
+ * @ingroup groupFastMath
+ */
+
+/**
+ * @addtogroup SQRT
+ * @{
+ */
+
+ /**
+ * @brief Q15 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if the input value is positive
+ * and ARM_MATH_ARGUMENT_ERROR if the input is negative. For
+ * negative inputs, the function returns *pOut = 0.
+ */
+
+arm_status arm_sqrt_q15(
+ q15_t in,
+ q15_t * pOut)
+{
+ q15_t number, temp1, var1, signBits1, half;
+ q31_t bits_val1;
+ float32_t temp_float1;
+ union
+ {
+ q31_t fracval;
+ float32_t floatval;
+ } tempconv;
+
+ number = in;
+
+ /* If the input is a positive number then compute the signBits. */
+ if (number > 0)
+ {
+ signBits1 = __CLZ(number) - 17;
+
+ /* Shift by the number of signBits1 */
+ if ((signBits1 % 2) == 0)
+ {
+ number = number << signBits1;
+ }
+ else
+ {
+ number = number << (signBits1 - 1);
+ }
+
+ /* Calculate half value of the number */
+ half = number >> 1;
+ /* Store the number for later use */
+ temp1 = number;
+
+ /* Convert to float */
+ temp_float1 = number * 3.051757812500000e-005f;
+ /*Store as integer */
+ tempconv.floatval = temp_float1;
+ bits_val1 = tempconv.fracval;
+ /* Subtract the shifted value from the magic number to give intial guess */
+ bits_val1 = 0x5f3759df - (bits_val1 >> 1); /* gives initial guess */
+ /* Store as float */
+ tempconv.fracval = bits_val1;
+ temp_float1 = tempconv.floatval;
+ /* Convert to integer format */
+ var1 = (q31_t) (temp_float1 * 16384);
+
+ /* 1st iteration */
+ var1 = ((q15_t) ((q31_t) var1 * (0x3000 -
+ ((q15_t)
+ ((((q15_t)
+ (((q31_t) var1 * var1) >> 15)) *
+ (q31_t) half) >> 15))) >> 15)) << 2;
+ /* 2nd iteration */
+ var1 = ((q15_t) ((q31_t) var1 * (0x3000 -
+ ((q15_t)
+ ((((q15_t)
+ (((q31_t) var1 * var1) >> 15)) *
+ (q31_t) half) >> 15))) >> 15)) << 2;
+ /* 3rd iteration */
+ var1 = ((q15_t) ((q31_t) var1 * (0x3000 -
+ ((q15_t)
+ ((((q15_t)
+ (((q31_t) var1 * var1) >> 15)) *
+ (q31_t) half) >> 15))) >> 15)) << 2;
+
+ /* Multiply the inverse square root with the original value */
+ var1 = ((q15_t) (((q31_t) temp1 * var1) >> 15)) << 1;
+
+ /* Shift the output down accordingly */
+ if ((signBits1 % 2) == 0)
+ {
+ var1 = var1 >> (signBits1 / 2);
+ }
+ else
+ {
+ var1 = var1 >> ((signBits1 - 1) / 2);
+ }
+ *pOut = var1;
+
+ return (ARM_MATH_SUCCESS);
+ }
+ /* If the number is a negative number then store zero as its square root value */
+ else
+ {
+ *pOut = 0;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+}
+
+/**
+ * @} end of SQRT group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q31.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q31.c
new file mode 100644
index 0000000..de8c35f
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q31.c
@@ -0,0 +1,142 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_sqrt_q31.c
+ * Description: Q31 square root function
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupFastMath
+ */
+
+/**
+ * @addtogroup SQRT
+ * @{
+ */
+
+/**
+ * @brief Q31 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if the input value is positive
+ * and ARM_MATH_ARGUMENT_ERROR if the input is negative. For
+ * negative inputs, the function returns *pOut = 0.
+ */
+
+arm_status arm_sqrt_q31(
+ q31_t in,
+ q31_t * pOut)
+{
+ q31_t number, temp1, bits_val1, var1, signBits1, half;
+ float32_t temp_float1;
+ union
+ {
+ q31_t fracval;
+ float32_t floatval;
+ } tempconv;
+
+ number = in;
+
+ /* If the input is a positive number then compute the signBits. */
+ if (number > 0)
+ {
+ signBits1 = __CLZ(number) - 1;
+
+ /* Shift by the number of signBits1 */
+ if ((signBits1 % 2) == 0)
+ {
+ number = number << signBits1;
+ }
+ else
+ {
+ number = number << (signBits1 - 1);
+ }
+
+ /* Calculate half value of the number */
+ half = number >> 1;
+ /* Store the number for later use */
+ temp1 = number;
+
+ /*Convert to float */
+ temp_float1 = number * 4.6566128731e-010f;
+ /*Store as integer */
+ tempconv.floatval = temp_float1;
+ bits_val1 = tempconv.fracval;
+ /* Subtract the shifted value from the magic number to give intial guess */
+ bits_val1 = 0x5f3759df - (bits_val1 >> 1); /* gives initial guess */
+ /* Store as float */
+ tempconv.fracval = bits_val1;
+ temp_float1 = tempconv.floatval;
+ /* Convert to integer format */
+ var1 = (q31_t) (temp_float1 * 1073741824);
+
+ /* 1st iteration */
+ var1 = ((q31_t) ((q63_t) var1 * (0x30000000 -
+ ((q31_t)
+ ((((q31_t)
+ (((q63_t) var1 * var1) >> 31)) *
+ (q63_t) half) >> 31))) >> 31)) << 2;
+ /* 2nd iteration */
+ var1 = ((q31_t) ((q63_t) var1 * (0x30000000 -
+ ((q31_t)
+ ((((q31_t)
+ (((q63_t) var1 * var1) >> 31)) *
+ (q63_t) half) >> 31))) >> 31)) << 2;
+ /* 3rd iteration */
+ var1 = ((q31_t) ((q63_t) var1 * (0x30000000 -
+ ((q31_t)
+ ((((q31_t)
+ (((q63_t) var1 * var1) >> 31)) *
+ (q63_t) half) >> 31))) >> 31)) << 2;
+
+ /* Multiply the inverse square root with the original value */
+ var1 = ((q31_t) (((q63_t) temp1 * var1) >> 31)) << 1;
+
+ /* Shift the output down accordingly */
+ if ((signBits1 % 2) == 0)
+ {
+ var1 = var1 >> (signBits1 / 2);
+ }
+ else
+ {
+ var1 = var1 >> ((signBits1 - 1) / 2);
+ }
+ *pOut = var1;
+
+ return (ARM_MATH_SUCCESS);
+ }
+ /* If the number is a negative number then store zero as its square root value */
+ else
+ {
+ *pOut = 0;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+}
+
+/**
+ * @} end of SQRT group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
new file mode 100644
index 0000000..8a29213
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
@@ -0,0 +1,98 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_biquad_cascade_df1_32x64_init_q31.c
+ * Description: High precision Q31 Biquad cascade filter initialization function
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1_32x64
+ * @{
+ */
+
+/**
+ * @details
+ *
+ * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift Shift to be applied after the accumulator. Varies according to the coefficients format.
+ * @return none
+ *
+ * <b>Coefficient and State Ordering:</b>
+ *
+ * \par
+ * The coefficients are stored in the array <code>pCoeffs</code> in the following order:
+ * <pre>
+ * {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+ * </pre>
+ * where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage,
+ * <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage,
+ * and so on. The <code>pCoeffs</code> array contains a total of <code>5*numStages</code> values.
+ *
+ * \par
+ * The <code>pState</code> points to state variables array and size of each state variable is 1.63 format.
+ * Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code>.
+ * The state variables are arranged in the state array as:
+ * <pre>
+ * {x[n-1], x[n-2], y[n-1], y[n-2]}
+ * </pre>
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ * The state array has a total length of <code>4*numStages</code> values.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ */
+
+void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift)
+{
+ /* Assign filter stages */
+ S->numStages = numStages;
+
+ /* Assign postShift to be applied to the output */
+ S->postShift = postShift;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always 4 * numStages */
+ memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(q63_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ * @} end of BiquadCascadeDF1_32x64 group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
new file mode 100644
index 0000000..d241f76
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
@@ -0,0 +1,549 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_biquad_cascade_df1_32x64_q31.c
+ * Description: High precision Q31 Biquad cascade filter processing function
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup BiquadCascadeDF1_32x64 High Precision Q31 Biquad Cascade Filter
+ *
+ * This function implements a high precision Biquad cascade filter which operates on
+ * Q31 data values. The filter coefficients are in 1.31 format and the state variables
+ * are in 1.63 format. The double precision state variables reduce quantization noise
+ * in the filter and provide a cleaner output.
+ * These filters are particularly useful when implementing filters in which the
+ * singularities are close to the unit circle. This is common for low pass or high
+ * pass filters with very low cutoff frequencies.
+ *
+ * The function operates on blocks of input and output data
+ * and each call to the function processes <code>blockSize</code> samples through
+ * the filter. <code>pSrc</code> and <code>pDst</code> points to input and output arrays
+ * containing <code>blockSize</code> Q31 values.
+ *
+ * \par Algorithm
+ * Each Biquad stage implements a second order filter using the difference equation:
+ * <pre>
+ * y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * </pre>
+ * A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage.
+ * \image html Biquad.gif "Single Biquad filter stage"
+ * Coefficients <code>b0, b1, and b2 </code> multiply the input signal <code>x[n]</code> and are referred to as the feedforward coefficients.
+ * Coefficients <code>a1</code> and <code>a2</code> multiply the output signal <code>y[n]</code> and are referred to as the feedback coefficients.
+ * Pay careful attention to the sign of the feedback coefficients.
+ * Some design tools use the difference equation
+ * <pre>
+ * y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]
+ * </pre>
+ * In this case the feedback coefficients <code>a1</code> and <code>a2</code> must be negated when used with the CMSIS DSP Library.
+ *
+ * \par
+ * Higher order filters are realized as a cascade of second order sections.
+ * <code>numStages</code> refers to the number of second order stages used.
+ * For example, an 8th order filter would be realized with <code>numStages=4</code> second order stages.
+ * \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages"
+ * A 9th order filter would be realized with <code>numStages=5</code> second order stages with the coefficients for one of the stages configured as a first order filter (<code>b2=0</code> and <code>a2=0</code>).
+ *
+ * \par
+ * The <code>pState</code> points to state variables array .
+ * Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code> and each state variable in 1.63 format to improve precision.
+ * The state variables are arranged in the array as:
+ * <pre>
+ * {x[n-1], x[n-2], y[n-1], y[n-2]}
+ * </pre>
+ *
+ * \par
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ * The state array has a total length of <code>4*numStages</code> values of data in 1.63 format.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ *
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter.
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+ *
+ * \par Init Function
+ * There is also an associated initialization function which performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numStages, pCoeffs, postShift, pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * Set the values in the state buffer to zeros before static initialization.
+ * For example, to statically initialize the filter instance structure use
+ * <pre>
+ * arm_biquad_cas_df1_32x64_ins_q31 S1 = {numStages, pState, pCoeffs, postShift};
+ * </pre>
+ * where <code>numStages</code> is the number of Biquad stages in the filter; <code>pState</code> is the address of the state buffer;
+ * <code>pCoeffs</code> is the address of the coefficient buffer; <code>postShift</code> shift to be applied which is described in detail below.
+ * \par Fixed-Point Behavior
+ * Care must be taken while using Biquad Cascade 32x64 filter function.
+ * Following issues must be considered:
+ * - Scaling of coefficients
+ * - Filter gain
+ * - Overflow and saturation
+ *
+ * \par
+ * Filter coefficients are represented as fractional values and
+ * restricted to lie in the range <code>[-1 +1)</code>.
+ * The processing function has an additional scaling parameter <code>postShift</code>
+ * which allows the filter coefficients to exceed the range <code>[+1 -1)</code>.
+ * At the output of the filter's accumulator is a shift register which shifts the result by <code>postShift</code> bits.
+ * \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator"
+ * This essentially scales the filter coefficients by <code>2^postShift</code>.
+ * For example, to realize the coefficients
+ * <pre>
+ * {1.5, -0.8, 1.2, 1.6, -0.9}
+ * </pre>
+ * set the Coefficient array to:
+ * <pre>
+ * {0.75, -0.4, 0.6, 0.8, -0.45}
+ * </pre>
+ * and set <code>postShift=1</code>
+ *
+ * \par
+ * The second thing to keep in mind is the gain through the filter.
+ * The frequency response of a Biquad filter is a function of its coefficients.
+ * It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies.
+ * This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter.
+ * To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.
+ *
+ * \par
+ * The third item to consider is the overflow and saturation behavior of the fixed-point Q31 version.
+ * This is described in the function specific documentation below.
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1_32x64
+ * @{
+ */
+
+/**
+ * @details
+
+ * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ *
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25).
+ * After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by <code>postShift</code> bits and the result truncated to
+ * 1.31 format by discarding the low 32 bits.
+ *
+ * \par
+ * Two related functions are provided in the CMSIS DSP library.
+ * <code>arm_biquad_cascade_df1_q31()</code> implements a Biquad cascade with 32-bit coefficients and state variables with a Q63 accumulator.
+ * <code>arm_biquad_cascade_df1_fast_q31()</code> implements a Biquad cascade with 32-bit coefficients and state variables with a Q31 accumulator.
+ */
+
+void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pIn = pSrc; /* input pointer initialization */
+ q31_t *pOut = pDst; /* output pointer initialization */
+ q63_t *pState = S->pState; /* state pointer initialization */
+ q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */
+ q63_t acc; /* accumulator */
+ q31_t Xn1, Xn2; /* Input Filter state variables */
+ q63_t Yn1, Yn2; /* Output Filter state variables */
+ q31_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ q31_t Xn; /* temporary input */
+ int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */
+ uint32_t sample, stage = S->numStages; /* loop counters */
+ q31_t acc_l, acc_h; /* temporary output */
+ uint32_t uShift = ((uint32_t) S->postShift + 1U);
+ uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */
+
+
+#if defined (ARM_MATH_DSP)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the state values */
+ Xn1 = (q31_t) (pState[0]);
+ Xn2 = (q31_t) (pState[1]);
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* Apply loop unrolling and compute 4 output values simultaneously. */
+ /* The variable acc hold output value that is being computed and
+ * stored in the destination buffer
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (sample > 0U)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) Xn *b0;
+
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) Xn1 *b1;
+
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) Xn2 *b2;
+
+ /* acc += a1 * y[n-1] */
+ acc += mult32x64(Yn1, a1);
+
+ /* acc += a2 * y[n-2] */
+ acc += mult32x64(Yn2, a2);
+
+ /* The result is converted to 1.63 , Yn2 variable is reused */
+ Yn2 = acc << shift;
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer in 1.31 format. */
+ *pOut = acc_h;
+
+ /* Read the second input into Xn2, to reuse the value */
+ Xn2 = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc += b1 * x[n-1] */
+ acc = (q63_t) Xn *b1;
+
+ /* acc = b0 * x[n] */
+ acc += (q63_t) Xn2 *b0;
+
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) Xn1 *b2;
+
+ /* acc += a1 * y[n-1] */
+ acc += mult32x64(Yn2, a1);
+
+ /* acc += a2 * y[n-2] */
+ acc += mult32x64(Yn1, a2);
+
+ /* The result is converted to 1.63, Yn1 variable is reused */
+ Yn1 = acc << shift;
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Read the third input into Xn1, to reuse the value */
+ Xn1 = *pIn++;
+
+ /* The result is converted to 1.31 */
+ /* Store the output in the destination buffer. */
+ *(pOut + 1U) = acc_h;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) Xn1 *b0;
+
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) Xn2 *b1;
+
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) Xn *b2;
+
+ /* acc += a1 * y[n-1] */
+ acc += mult32x64(Yn1, a1);
+
+ /* acc += a2 * y[n-2] */
+ acc += mult32x64(Yn2, a2);
+
+ /* The result is converted to 1.63, Yn2 variable is reused */
+ Yn2 = acc << shift;
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer in 1.31 format. */
+ *(pOut + 2U) = acc_h;
+
+ /* Read the fourth input into Xn, to reuse the value */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ acc = (q63_t) Xn *b0;
+
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) Xn1 *b1;
+
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) Xn2 *b2;
+
+ /* acc += a1 * y[n-1] */
+ acc += mult32x64(Yn2, a1);
+
+ /* acc += a2 * y[n-2] */
+ acc += mult32x64(Yn1, a2);
+
+ /* The result is converted to 1.63, Yn1 variable is reused */
+ Yn1 = acc << shift;
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer in 1.31 format. */
+ *(pOut + 3U) = acc_h;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+
+ /* update output pointer */
+ pOut += 4U;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ sample = (blockSize & 0x3U);
+
+ while (sample > 0U)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) Xn *b0;
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) Xn1 *b1;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) Xn2 *b2;
+ /* acc += a1 * y[n-1] */
+ acc += mult32x64(Yn1, a1);
+ /* acc += a2 * y[n-2] */
+ acc += mult32x64(Yn2, a2);
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ /* The result is converted to 1.63, Yn1 variable is reused */
+ Yn1 = acc << shift;
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer in 1.31 format. */
+ *pOut++ = acc_h;
+ /* Yn1 = acc << shift; */
+
+ /* Store the output in the destination buffer in 1.31 format. */
+/* *pOut++ = (q31_t) (acc >> (32 - shift)); */
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* The first stage output is given as input to the second stage. */
+ pIn = pDst;
+
+ /* Reset to destination buffer working pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the pState array */
+ /* Store the updated state variables back into the pState array */
+ *pState++ = (q63_t) Xn1;
+ *pState++ = (q63_t) Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ } while (--stage);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the state values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* The variable acc hold output value that is being computed and
+ * stored in the destination buffer
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize;
+
+ while (sample > 0U)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ acc = (q63_t) Xn *b0;
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) Xn1 *b1;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) Xn2 *b2;
+ /* acc += a1 * y[n-1] */
+ acc += mult32x64(Yn1, a1);
+ /* acc += a2 * y[n-2] */
+ acc += mult32x64(Yn2, a2);
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+
+ /* The result is converted to 1.63, Yn1 variable is reused */
+ Yn1 = acc << shift;
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer in 1.31 format. */
+ *pOut++ = acc_h;
+
+ /* Yn1 = acc << shift; */
+
+ /* Store the output in the destination buffer in 1.31 format. */
+ /* *pOut++ = (q31_t) (acc >> (32 - shift)); */
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* The first stage output is given as input to the second stage. */
+ pIn = pDst;
+
+ /* Reset to destination buffer working pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = (q63_t) Xn1;
+ *pState++ = (q63_t) Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ } while (--stage);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+}
+
+ /**
+ * @} end of BiquadCascadeDF1_32x64 group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c
new file mode 100644
index 0000000..658e395
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c
@@ -0,0 +1,412 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_biquad_cascade_df1_f32.c
+ * Description: Processing function for the floating-point Biquad cascade DirectFormI(DF1) filter
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup BiquadCascadeDF1 Biquad Cascade IIR Filters Using Direct Form I Structure
+ *
+ * This set of functions implements arbitrary order recursive (IIR) filters.
+ * The filters are implemented as a cascade of second order Biquad sections.
+ * The functions support Q15, Q31 and floating-point data types.
+ * Fast version of Q15 and Q31 also supported on CortexM4 and Cortex-M3.
+ *
+ * The functions operate on blocks of input and output data and each call to the function
+ * processes <code>blockSize</code> samples through the filter.
+ * <code>pSrc</code> points to the array of input data and
+ * <code>pDst</code> points to the array of output data.
+ * Both arrays contain <code>blockSize</code> values.
+ *
+ * \par Algorithm
+ * Each Biquad stage implements a second order filter using the difference equation:
+ * <pre>
+ * y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * </pre>
+ * A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage.
+ * \image html Biquad.gif "Single Biquad filter stage"
+ * Coefficients <code>b0, b1 and b2 </code> multiply the input signal <code>x[n]</code> and are referred to as the feedforward coefficients.
+ * Coefficients <code>a1</code> and <code>a2</code> multiply the output signal <code>y[n]</code> and are referred to as the feedback coefficients.
+ * Pay careful attention to the sign of the feedback coefficients.
+ * Some design tools use the difference equation
+ * <pre>
+ * y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]
+ * </pre>
+ * In this case the feedback coefficients <code>a1</code> and <code>a2</code> must be negated when used with the CMSIS DSP Library.
+ *
+ * \par
+ * Higher order filters are realized as a cascade of second order sections.
+ * <code>numStages</code> refers to the number of second order stages used.
+ * For example, an 8th order filter would be realized with <code>numStages=4</code> second order stages.
+ * \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages"
+ * A 9th order filter would be realized with <code>numStages=5</code> second order stages with the coefficients for one of the stages configured as a first order filter (<code>b2=0</code> and <code>a2=0</code>).
+ *
+ * \par
+ * The <code>pState</code> points to state variables array.
+ * Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code>.
+ * The state variables are arranged in the <code>pState</code> array as:
+ * <pre>
+ * {x[n-1], x[n-2], y[n-1], y[n-2]}
+ * </pre>
+ *
+ * \par
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ * The state array has a total length of <code>4*numStages</code> values.
+ * The state variables are updated after each block of data is processed, the coefficients are untouched.
+ *
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter.
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Init Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numStages, pCoeffs, pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * Set the values in the state buffer to zeros before static initialization.
+ * The code below statically initializes each of the 3 different data type filter instance structures
+ * <pre>
+ * arm_biquad_casd_df1_inst_f32 S1 = {numStages, pState, pCoeffs};
+ * arm_biquad_casd_df1_inst_q15 S2 = {numStages, pState, pCoeffs, postShift};
+ * arm_biquad_casd_df1_inst_q31 S3 = {numStages, pState, pCoeffs, postShift};
+ * </pre>
+ * where <code>numStages</code> is the number of Biquad stages in the filter; <code>pState</code> is the address of the state buffer;
+ * <code>pCoeffs</code> is the address of the coefficient buffer; <code>postShift</code> shift to be applied.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q15 and Q31 versions of the Biquad Cascade filter functions.
+ * Following issues must be considered:
+ * - Scaling of coefficients
+ * - Filter gain
+ * - Overflow and saturation
+ *
+ * \par
+ * <b>Scaling of coefficients: </b>
+ * Filter coefficients are represented as fractional values and
+ * coefficients are restricted to lie in the range <code>[-1 +1)</code>.
+ * The fixed-point functions have an additional scaling parameter <code>postShift</code>
+ * which allow the filter coefficients to exceed the range <code>[+1 -1)</code>.
+ * At the output of the filter's accumulator is a shift register which shifts the result by <code>postShift</code> bits.
+ * \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator"
+ * This essentially scales the filter coefficients by <code>2^postShift</code>.
+ * For example, to realize the coefficients
+ * <pre>
+ * {1.5, -0.8, 1.2, 1.6, -0.9}
+ * </pre>
+ * set the pCoeffs array to:
+ * <pre>
+ * {0.75, -0.4, 0.6, 0.8, -0.45}
+ * </pre>
+ * and set <code>postShift=1</code>
+ *
+ * \par
+ * <b>Filter gain: </b>
+ * The frequency response of a Biquad filter is a function of its coefficients.
+ * It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies.
+ * This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter.
+ * To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.
+ *
+ * \par
+ * <b>Overflow and saturation: </b>
+ * For Q15 and Q31 versions, it is described separately as part of the function specific documentation below.
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @param[in] *S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ */
+
+void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pIn = pSrc; /* source pointer */
+ float32_t *pOut = pDst; /* destination pointer */
+ float32_t *pState = S->pState; /* pState pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */
+ float32_t acc; /* Simulates the accumulator */
+ float32_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ float32_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */
+ float32_t Xn; /* temporary input */
+ uint32_t sample, stage = S->numStages; /* loop counters */
+
+
+#if defined (ARM_MATH_DSP)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the pState values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* Apply loop unrolling and compute 4 output values simultaneously. */
+ /* The variable acc hold output values that are being computed:
+ *
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (sample > 0U)
+ {
+ /* Read the first input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ Yn2 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = Yn2;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+
+ /* Read the second input */
+ Xn2 = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ Yn1 = (b0 * Xn2) + (b1 * Xn) + (b2 * Xn1) + (a1 * Yn2) + (a2 * Yn1);
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = Yn1;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+
+ /* Read the third input */
+ Xn1 = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ Yn2 = (b0 * Xn1) + (b1 * Xn2) + (b2 * Xn) + (a1 * Yn1) + (a2 * Yn2);
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = Yn2;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+
+ /* Read the forth input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ Yn1 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn2) + (a2 * Yn1);
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = Yn1;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+
+ /* decrement the loop counter */
+ sample--;
+
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ sample = blockSize & 0x3U;
+
+ while (sample > 0U)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = acc;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ Yn1 = acc;
+
+ /* decrement the loop counter */
+ sample--;
+
+ }
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = Xn1;
+ *pState++ = Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent numStages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset the output pointer */
+ pOut = pDst;
+
+ /* decrement the loop counter */
+ stage--;
+
+ } while (stage > 0U);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the pState values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* The variables acc holds the output value that is computed:
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize;
+
+ while (sample > 0U)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = acc;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ Yn1 = acc;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = Xn1;
+ *pState++ = Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent numStages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset the output pointer */
+ pOut = pDst;
+
+ /* decrement the loop counter */
+ stage--;
+
+ } while (stage > 0U);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+
+ /**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
new file mode 100644
index 0000000..2a08968
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
@@ -0,0 +1,273 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_biquad_cascade_df1_fast_q15.c
+ * Description: Fast processing function for the Q15 Biquad cascade filter
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @details
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * This fast version uses a 32-bit accumulator with 2.30 format.
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around and distorts the result.
+ * In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25).
+ * The 2.30 accumulator is then shifted by <code>postShift</code> bits and the result truncated to 1.15 format by discarding the low 16 bits.
+ *
+ * \par
+ * Refer to the function <code>arm_biquad_cascade_df1_q15()</code> for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. Both the slow and the fast versions use the same instance structure.
+ * Use the function <code>arm_biquad_cascade_df1_init_q15()</code> to initialize the filter structure.
+ *
+ */
+
+void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pIn = pSrc; /* Source pointer */
+ q15_t *pOut = pDst; /* Destination pointer */
+ q31_t in; /* Temporary variable to hold input value */
+ q31_t out; /* Temporary variable to hold output value */
+ q31_t b0; /* Temporary variable to hold bo value */
+ q31_t b1, a1; /* Filter coefficients */
+ q31_t state_in, state_out; /* Filter state variables */
+ q31_t acc; /* Accumulator */
+ int32_t shift = (int32_t) (15 - S->postShift); /* Post shift */
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ uint32_t sample, stage = S->numStages; /* Stage loop counter */
+
+
+
+ do
+ {
+
+ /* Read the b0 and 0 coefficients using SIMD */
+ b0 = *__SIMD32(pCoeffs)++;
+
+ /* Read the b1 and b2 coefficients using SIMD */
+ b1 = *__SIMD32(pCoeffs)++;
+
+ /* Read the a1 and a2 coefficients using SIMD */
+ a1 = *__SIMD32(pCoeffs)++;
+
+ /* Read the input state values from the state buffer: x[n-1], x[n-2] */
+ state_in = *__SIMD32(pState)++;
+
+ /* Read the output state values from the state buffer: y[n-1], y[n-2] */
+ state_out = *__SIMD32(pState)--;
+
+ /* Apply loop unrolling and compute 2 output values simultaneously. */
+ /* The variable acc hold output values that are being computed:
+ *
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+ sample = blockSize >> 1U;
+
+ /* First part of the processing with loop unrolling. Compute 2 outputs at a time.
+ ** a second loop below computes the remaining 1 sample. */
+ while (sample > 0U)
+ {
+
+ /* Read the input */
+ in = *__SIMD32(pIn)++;
+
+ /* out = b0 * x[n] + 0 * 0 */
+ out = __SMUAD(b0, in);
+ /* acc = b1 * x[n-1] + acc += b2 * x[n-2] + out */
+ acc = __SMLAD(b1, state_in, out);
+ /* acc += a1 * y[n-1] + acc += a2 * y[n-2] */
+ acc = __SMLAD(a1, state_out, acc);
+
+ /* The result is converted from 3.29 to 1.31 and then saturation is applied */
+ out = __SSAT((acc >> shift), 16);
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+ /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ state_in = __PKHBT(in, state_in, 16);
+ state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+ state_in = __PKHBT(state_in >> 16, (in >> 16), 16);
+ state_out = __PKHBT(state_out >> 16, (out), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* out = b0 * x[n] + 0 * 0 */
+ out = __SMUADX(b0, in);
+ /* acc0 = b1 * x[n-1] , acc0 += b2 * x[n-2] + out */
+ acc = __SMLAD(b1, state_in, out);
+ /* acc += a1 * y[n-1] + acc += a2 * y[n-2] */
+ acc = __SMLAD(a1, state_out, acc);
+
+ /* The result is converted from 3.29 to 1.31 and then saturation is applied */
+ out = __SSAT((acc >> shift), 16);
+
+
+ /* Store the output in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ = __PKHBT(state_out, out, 16);
+
+#else
+
+ *__SIMD32(pOut)++ = __PKHBT(out, state_out >> 16, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+ /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ state_in = __PKHBT(in >> 16, state_in, 16);
+ state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+ state_in = __PKHBT(state_in >> 16, in, 16);
+ state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+
+ /* Decrement the loop counter */
+ sample--;
+
+ }
+
+ /* If the blockSize is not a multiple of 2, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+
+ if ((blockSize & 0x1U) != 0U)
+ {
+ /* Read the input */
+ in = *pIn++;
+
+ /* out = b0 * x[n] + 0 * 0 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out = __SMUAD(b0, in);
+
+#else
+
+ out = __SMUADX(b0, in);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc = b1 * x[n-1], acc += b2 * x[n-2] + out */
+ acc = __SMLAD(b1, state_in, out);
+ /* acc += a1 * y[n-1] + acc += a2 * y[n-2] */
+ acc = __SMLAD(a1, state_out, acc);
+
+ /* The result is converted from 3.29 to 1.31 and then saturation is applied */
+ out = __SSAT((acc >> shift), 16);
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = (q15_t) out;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+ /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ state_in = __PKHBT(in, state_in, 16);
+ state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+ state_in = __PKHBT(state_in >> 16, in, 16);
+ state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ }
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent (numStages - 1) occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset the output pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the state array */
+ *__SIMD32(pState)++ = state_in;
+ *__SIMD32(pState)++ = state_out;
+
+
+ /* Decrement the loop counter */
+ stage--;
+
+ } while (stage > 0U);
+}
+
+
+/**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
new file mode 100644
index 0000000..5e41faa
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
@@ -0,0 +1,292 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_biquad_cascade_df1_fast_q31.c
+ * Description: Processing function for the Q31 Fast Biquad cascade DirectFormI(DF1) filter
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @details
+ *
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.
+ * These intermediate results are added to a 2.30 accumulator.
+ * Finally, the accumulator is saturated and converted to a 1.31 result.
+ * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.
+ * In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25). Use the intialization function
+ * arm_biquad_cascade_df1_init_q31() to initialize filter structure.
+ *
+ * \par
+ * Refer to the function <code>arm_biquad_cascade_df1_q31()</code> for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. Both the slow and the fast versions use the same instance structure.
+ * Use the function <code>arm_biquad_cascade_df1_init_q31()</code> to initialize the filter structure.
+ */
+
+void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t acc = 0; /* accumulator */
+ q31_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */
+ q31_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ q31_t *pIn = pSrc; /* input pointer initialization */
+ q31_t *pOut = pDst; /* output pointer initialization */
+ q31_t *pState = S->pState; /* pState pointer initialization */
+ q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */
+ q31_t Xn; /* temporary input */
+ int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */
+ uint32_t sample, stage = S->numStages; /* loop counters */
+
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the state values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* Apply loop unrolling and compute 4 output values simultaneously. */
+ /* The variables acc ... acc3 hold output values that are being computed:
+ *
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (sample > 0U)
+ {
+ /* Read the input */
+ Xn = *pIn;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ /*acc = (q31_t) (((q63_t) b1 * Xn1) >> 32);*/
+ mult_32x32_keep32_R(acc, b1, Xn1);
+ /* acc += b1 * x[n-1] */
+ /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b0 * (Xn))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, b0, Xn);
+ /* acc += b[2] * x[n-2] */
+ /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, b2, Xn2);
+ /* acc += a1 * y[n-1] */
+ /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, a1, Yn1);
+ /* acc += a2 * y[n-2] */
+ /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, a2, Yn2);
+
+ /* The result is converted to 1.31 , Yn2 variable is reused */
+ Yn2 = acc << shift;
+
+ /* Read the second input */
+ Xn2 = *(pIn + 1U);
+
+ /* Store the output in the destination buffer. */
+ *pOut = Yn2;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ /*acc = (q31_t) (((q63_t) b0 * (Xn2)) >> 32);*/
+ mult_32x32_keep32_R(acc, b0, Xn2);
+ /* acc += b1 * x[n-1] */
+ /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, b1, Xn);
+ /* acc += b[2] * x[n-2] */
+ /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn1))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, b2, Xn1);
+ /* acc += a1 * y[n-1] */
+ /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, a1, Yn2);
+ /* acc += a2 * y[n-2] */
+ /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, a2, Yn1);
+
+ /* The result is converted to 1.31, Yn1 variable is reused */
+ Yn1 = acc << shift;
+
+ /* Read the third input */
+ Xn1 = *(pIn + 2U);
+
+ /* Store the output in the destination buffer. */
+ *(pOut + 1U) = Yn1;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ /*acc = (q31_t) (((q63_t) b0 * (Xn1)) >> 32);*/
+ mult_32x32_keep32_R(acc, b0, Xn1);
+ /* acc += b1 * x[n-1] */
+ /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn2))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, b1, Xn2);
+ /* acc += b[2] * x[n-2] */
+ /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, b2, Xn);
+ /* acc += a1 * y[n-1] */
+ /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, a1, Yn1);
+ /* acc += a2 * y[n-2] */
+ /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, a2, Yn2);
+
+ /* The result is converted to 1.31, Yn2 variable is reused */
+ Yn2 = acc << shift;
+
+ /* Read the forth input */
+ Xn = *(pIn + 3U);
+
+ /* Store the output in the destination buffer. */
+ *(pOut + 2U) = Yn2;
+ pIn += 4U;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ /*acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);*/
+ mult_32x32_keep32_R(acc, b0, Xn);
+ /* acc += b1 * x[n-1] */
+ /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, b1, Xn1);
+ /* acc += b[2] * x[n-2] */
+ /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, b2, Xn2);
+ /* acc += a1 * y[n-1] */
+ /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, a1, Yn2);
+ /* acc += a2 * y[n-2] */
+ /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, a2, Yn1);
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ Xn2 = Xn1;
+
+ /* The result is converted to 1.31, Yn1 variable is reused */
+ Yn1 = acc << shift;
+
+ /* Xn1 = Xn */
+ Xn1 = Xn;
+
+ /* Store the output in the destination buffer. */
+ *(pOut + 3U) = Yn1;
+ pOut += 4U;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ sample = (blockSize & 0x3U);
+
+ while (sample > 0U)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ /*acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);*/
+ mult_32x32_keep32_R(acc, b0, Xn);
+ /* acc += b1 * x[n-1] */
+ /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, b1, Xn1);
+ /* acc += b[2] * x[n-2] */
+ /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, b2, Xn2);
+ /* acc += a1 * y[n-1] */
+ /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, a1, Yn1);
+ /* acc += a2 * y[n-2] */
+ /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, a2, Yn2);
+
+ /* The result is converted to 1.31 */
+ acc = acc << shift;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ Yn1 = acc;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = acc;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent stages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset to destination pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = Xn1;
+ *pState++ = Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ } while (--stage);
+}
+
+/**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
new file mode 100644
index 0000000..147c8c5
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
@@ -0,0 +1,97 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_biquad_cascade_df1_init_f32.c
+ * Description: Floating-point Biquad cascade DirectFormI(DF1) filter initialization function
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @details
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients array.
+ * @param[in] *pState points to the state array.
+ * @return none
+ *
+ *
+ * <b>Coefficient and State Ordering:</b>
+ *
+ * \par
+ * The coefficients are stored in the array <code>pCoeffs</code> in the following order:
+ * <pre>
+ * {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+ * </pre>
+ *
+ * \par
+ * where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage,
+ * <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage,
+ * and so on. The <code>pCoeffs</code> array contains a total of <code>5*numStages</code> values.
+ *
+ * \par
+ * The <code>pState</code> is a pointer to state array.
+ * Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code>.
+ * The state variables are arranged in the <code>pState</code> array as:
+ * <pre>
+ * {x[n-1], x[n-2], y[n-1], y[n-2]}
+ * </pre>
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ * The state array has a total length of <code>4*numStages</code> values.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ *
+ */
+
+void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState)
+{
+ /* Assign filter stages */
+ S->numStages = numStages;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always 4 * numStages */
+ memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
new file mode 100644
index 0000000..dd46fb4
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
@@ -0,0 +1,99 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_biquad_cascade_df1_init_q15.c
+ * Description: Q15 Biquad cascade DirectFormI(DF1) filter initialization function
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @details
+ *
+ * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the accumulator result. Varies according to the coefficients format
+ * @return none
+ *
+ * <b>Coefficient and State Ordering:</b>
+ *
+ * \par
+ * The coefficients are stored in the array <code>pCoeffs</code> in the following order:
+ * <pre>
+ * {b10, 0, b11, b12, a11, a12, b20, 0, b21, b22, a21, a22, ...}
+ * </pre>
+ * where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage,
+ * <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage,
+ * and so on. The <code>pCoeffs</code> array contains a total of <code>6*numStages</code> values.
+ * The zero coefficient between <code>b1</code> and <code>b2</code> facilities use of 16-bit SIMD instructions on the Cortex-M4.
+ *
+ * \par
+ * The state variables are stored in the array <code>pState</code>.
+ * Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code>.
+ * The state variables are arranged in the <code>pState</code> array as:
+ * <pre>
+ * {x[n-1], x[n-2], y[n-1], y[n-2]}
+ * </pre>
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ * The state array has a total length of <code>4*numStages</code> values.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ */
+
+void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift)
+{
+ /* Assign filter stages */
+ S->numStages = numStages;
+
+ /* Assign postShift to be applied to the output */
+ S->postShift = postShift;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always 4 * numStages */
+ memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
new file mode 100644
index 0000000..10fb6bc
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
@@ -0,0 +1,98 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_biquad_cascade_df1_init_q31.c
+ * Description: Q31 Biquad cascade DirectFormI(DF1) filter initialization function
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @details
+ *
+ * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift Shift to be applied after the accumulator. Varies according to the coefficients format
+ * @return none
+ *
+ * <b>Coefficient and State Ordering:</b>
+ *
+ * \par
+ * The coefficients are stored in the array <code>pCoeffs</code> in the following order:
+ * <pre>
+ * {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+ * </pre>
+ * where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage,
+ * <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage,
+ * and so on. The <code>pCoeffs</code> array contains a total of <code>5*numStages</code> values.
+ *
+ * \par
+ * The <code>pState</code> points to state variables array.
+ * Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code>.
+ * The state variables are arranged in the <code>pState</code> array as:
+ * <pre>
+ * {x[n-1], x[n-2], y[n-1], y[n-2]}
+ * </pre>
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ * The state array has a total length of <code>4*numStages</code> values.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ */
+
+void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift)
+{
+ /* Assign filter stages */
+ S->numStages = numStages;
+
+ /* Assign postShift to be applied to the output */
+ S->postShift = postShift;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always 4 * numStages */
+ memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(q31_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c
new file mode 100644
index 0000000..c524756
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c
@@ -0,0 +1,398 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_biquad_cascade_df1_q15.c
+ * Description: Processing function for the Q15 Biquad cascade DirectFormI(DF1) filter
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * The accumulator is then shifted by <code>postShift</code> bits to truncate the result to 1.15 format by discarding the low 16 bits.
+ * Finally, the result is saturated to 1.15 format.
+ *
+ * \par
+ * Refer to the function <code>arm_biquad_cascade_df1_fast_q15()</code> for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.
+ */
+
+void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+
+
+#if defined (ARM_MATH_DSP)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q15_t *pIn = pSrc; /* Source pointer */
+ q15_t *pOut = pDst; /* Destination pointer */
+ q31_t in; /* Temporary variable to hold input value */
+ q31_t out; /* Temporary variable to hold output value */
+ q31_t b0; /* Temporary variable to hold bo value */
+ q31_t b1, a1; /* Filter coefficients */
+ q31_t state_in, state_out; /* Filter state variables */
+ q31_t acc_l, acc_h;
+ q63_t acc; /* Accumulator */
+ int32_t lShift = (15 - (int32_t) S->postShift); /* Post shift */
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ uint32_t sample, stage = (uint32_t) S->numStages; /* Stage loop counter */
+ int32_t uShift = (32 - lShift);
+
+ do
+ {
+ /* Read the b0 and 0 coefficients using SIMD */
+ b0 = *__SIMD32(pCoeffs)++;
+
+ /* Read the b1 and b2 coefficients using SIMD */
+ b1 = *__SIMD32(pCoeffs)++;
+
+ /* Read the a1 and a2 coefficients using SIMD */
+ a1 = *__SIMD32(pCoeffs)++;
+
+ /* Read the input state values from the state buffer: x[n-1], x[n-2] */
+ state_in = *__SIMD32(pState)++;
+
+ /* Read the output state values from the state buffer: y[n-1], y[n-2] */
+ state_out = *__SIMD32(pState)--;
+
+ /* Apply loop unrolling and compute 2 output values simultaneously. */
+ /* The variable acc hold output values that are being computed:
+ *
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+ sample = blockSize >> 1U;
+
+ /* First part of the processing with loop unrolling. Compute 2 outputs at a time.
+ ** a second loop below computes the remaining 1 sample. */
+ while (sample > 0U)
+ {
+
+ /* Read the input */
+ in = *__SIMD32(pIn)++;
+
+ /* out = b0 * x[n] + 0 * 0 */
+ out = __SMUAD(b0, in);
+
+ /* acc += b1 * x[n-1] + b2 * x[n-2] + out */
+ acc = __SMLALD(b1, state_in, out);
+ /* acc += a1 * y[n-1] + a2 * y[n-2] */
+ acc = __SMLALD(a1, state_out, acc);
+
+ /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ out = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ out = __SSAT(out, 16);
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+ /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ state_in = __PKHBT(in, state_in, 16);
+ state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+ state_in = __PKHBT(state_in >> 16, (in >> 16), 16);
+ state_out = __PKHBT(state_out >> 16, (out), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* out = b0 * x[n] + 0 * 0 */
+ out = __SMUADX(b0, in);
+ /* acc += b1 * x[n-1] + b2 * x[n-2] + out */
+ acc = __SMLALD(b1, state_in, out);
+ /* acc += a1 * y[n-1] + a2 * y[n-2] */
+ acc = __SMLALD(a1, state_out, acc);
+
+ /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ out = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ out = __SSAT(out, 16);
+
+ /* Store the output in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ = __PKHBT(state_out, out, 16);
+
+#else
+
+ *__SIMD32(pOut)++ = __PKHBT(out, state_out >> 16, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+ /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ state_in = __PKHBT(in >> 16, state_in, 16);
+ state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+ state_in = __PKHBT(state_in >> 16, in, 16);
+ state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+
+ /* Decrement the loop counter */
+ sample--;
+
+ }
+
+ /* If the blockSize is not a multiple of 2, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+
+ if ((blockSize & 0x1U) != 0U)
+ {
+ /* Read the input */
+ in = *pIn++;
+
+ /* out = b0 * x[n] + 0 * 0 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out = __SMUAD(b0, in);
+
+#else
+
+ out = __SMUADX(b0, in);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc = b1 * x[n-1] + b2 * x[n-2] + out */
+ acc = __SMLALD(b1, state_in, out);
+ /* acc += a1 * y[n-1] + a2 * y[n-2] */
+ acc = __SMLALD(a1, state_out, acc);
+
+ /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ out = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ out = __SSAT(out, 16);
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = (q15_t) out;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+ /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ state_in = __PKHBT(in, state_in, 16);
+ state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+ state_in = __PKHBT(state_in >> 16, in, 16);
+ state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ }
+
+ /* The first stage goes from the input wire to the output wire. */
+ /* Subsequent numStages occur in-place in the output wire */
+ pIn = pDst;
+
+ /* Reset the output pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the state array */
+ *__SIMD32(pState)++ = state_in;
+ *__SIMD32(pState)++ = state_out;
+
+
+ /* Decrement the loop counter */
+ stage--;
+
+ } while (stage > 0U);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q15_t *pIn = pSrc; /* Source pointer */
+ q15_t *pOut = pDst; /* Destination pointer */
+ q15_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ q15_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */
+ q15_t Xn; /* temporary input */
+ q63_t acc; /* Accumulator */
+ int32_t shift = (15 - (int32_t) S->postShift); /* Post shift */
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ uint32_t sample, stage = (uint32_t) S->numStages; /* Stage loop counter */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ pCoeffs++; // skip the 0 coefficient
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the state values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* The variables acc holds the output value that is computed:
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize;
+
+ while (sample > 0U)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ acc = (q31_t) b0 *Xn;
+
+ /* acc += b1 * x[n-1] */
+ acc += (q31_t) b1 *Xn1;
+ /* acc += b[2] * x[n-2] */
+ acc += (q31_t) b2 *Xn2;
+ /* acc += a1 * y[n-1] */
+ acc += (q31_t) a1 *Yn1;
+ /* acc += a2 * y[n-2] */
+ acc += (q31_t) a2 *Yn2;
+
+ /* The result is converted to 1.31 */
+ acc = __SSAT((acc >> shift), 16);
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ Yn1 = (q15_t) acc;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = (q15_t) acc;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent stages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset to destination pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = Xn1;
+ *pState++ = Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ } while (--stage);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+
+/**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c
new file mode 100644
index 0000000..da367ec
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c
@@ -0,0 +1,392 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_biquad_cascade_df1_q31.c
+ * Description: Processing function for the Q31 Biquad cascade filter
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q31 Biquad cascade filter.
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25).
+ * After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by <code>postShift</code> bits and the result truncated to
+ * 1.31 format by discarding the low 32 bits.
+ *
+ * \par
+ * Refer to the function <code>arm_biquad_cascade_df1_fast_q31()</code> for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.
+ */
+
+void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q63_t acc; /* accumulator */
+ uint32_t uShift = ((uint32_t) S->postShift + 1U);
+ uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */
+ q31_t *pIn = pSrc; /* input pointer initialization */
+ q31_t *pOut = pDst; /* output pointer initialization */
+ q31_t *pState = S->pState; /* pState pointer initialization */
+ q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */
+ q31_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */
+ q31_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ q31_t Xn; /* temporary input */
+ uint32_t sample, stage = S->numStages; /* loop counters */
+
+
+#if defined (ARM_MATH_DSP)
+
+ q31_t acc_l, acc_h; /* temporary output variables */
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the state values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* Apply loop unrolling and compute 4 output values simultaneously. */
+ /* The variable acc hold output values that are being computed:
+ *
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (sample > 0U)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) b0 *Xn;
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) b1 *Xn1;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) b2 *Xn2;
+ /* acc += a1 * y[n-1] */
+ acc += (q63_t) a1 *Yn1;
+ /* acc += a2 * y[n-2] */
+ acc += (q63_t) a2 *Yn2;
+
+ /* The result is converted to 1.31 , Yn2 variable is reused */
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = Yn2;
+
+ /* Read the second input */
+ Xn2 = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) b0 *Xn2;
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) b1 *Xn;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) b2 *Xn1;
+ /* acc += a1 * y[n-1] */
+ acc += (q63_t) a1 *Yn2;
+ /* acc += a2 * y[n-2] */
+ acc += (q63_t) a2 *Yn1;
+
+
+ /* The result is converted to 1.31, Yn1 variable is reused */
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = Yn1;
+
+ /* Read the third input */
+ Xn1 = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) b0 *Xn1;
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) b1 *Xn2;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) b2 *Xn;
+ /* acc += a1 * y[n-1] */
+ acc += (q63_t) a1 *Yn1;
+ /* acc += a2 * y[n-2] */
+ acc += (q63_t) a2 *Yn2;
+
+ /* The result is converted to 1.31, Yn2 variable is reused */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = Yn2;
+
+ /* Read the forth input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) b0 *Xn;
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) b1 *Xn1;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) b2 *Xn2;
+ /* acc += a1 * y[n-1] */
+ acc += (q63_t) a1 *Yn2;
+ /* acc += a2 * y[n-2] */
+ acc += (q63_t) a2 *Yn1;
+
+ /* The result is converted to 1.31, Yn1 variable is reused */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = Yn1;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ sample = (blockSize & 0x3U);
+
+ while (sample > 0U)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) b0 *Xn;
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) b1 *Xn1;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) b2 *Xn2;
+ /* acc += a1 * y[n-1] */
+ acc += (q63_t) a1 *Yn1;
+ /* acc += a2 * y[n-2] */
+ acc += (q63_t) a2 *Yn2;
+
+ /* The result is converted to 1.31 */
+ acc = acc >> lShift;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ Yn1 = (q31_t) acc;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = (q31_t) acc;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent stages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset to destination pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = Xn1;
+ *pState++ = Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ } while (--stage);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the state values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* The variables acc holds the output value that is computed:
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize;
+
+ while (sample > 0U)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ acc = (q63_t) b0 *Xn;
+
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) b1 *Xn1;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) b2 *Xn2;
+ /* acc += a1 * y[n-1] */
+ acc += (q63_t) a1 *Yn1;
+ /* acc += a2 * y[n-2] */
+ acc += (q63_t) a2 *Yn2;
+
+ /* The result is converted to 1.31 */
+ acc = acc >> lShift;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ Yn1 = (q31_t) acc;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = (q31_t) acc;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent stages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset to destination pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = Xn1;
+ *pState++ = Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ } while (--stage);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+}
+
+
+
+
+/**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c
new file mode 100644
index 0000000..3f1ce03
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c
@@ -0,0 +1,590 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_biquad_cascade_df2T_f32.c
+ * Description: Processing function for floating-point transposed direct form II Biquad cascade filter
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+* @ingroup groupFilters
+*/
+
+/**
+* @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure
+*
+* This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure.
+* The filters are implemented as a cascade of second order Biquad sections.
+* These functions provide a slight memory savings as compared to the direct form I Biquad filter functions.
+* Only floating-point data is supported.
+*
+* This function operate on blocks of input and output data and each call to the function
+* processes <code>blockSize</code> samples through the filter.
+* <code>pSrc</code> points to the array of input data and
+* <code>pDst</code> points to the array of output data.
+* Both arrays contain <code>blockSize</code> values.
+*
+* \par Algorithm
+* Each Biquad stage implements a second order filter using the difference equation:
+* <pre>
+* y[n] = b0 * x[n] + d1
+* d1 = b1 * x[n] + a1 * y[n] + d2
+* d2 = b2 * x[n] + a2 * y[n]
+* </pre>
+* where d1 and d2 represent the two state values.
+*
+* \par
+* A Biquad filter using a transposed Direct Form II structure is shown below.
+* \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad"
+* Coefficients <code>b0, b1, and b2 </code> multiply the input signal <code>x[n]</code> and are referred to as the feedforward coefficients.
+* Coefficients <code>a1</code> and <code>a2</code> multiply the output signal <code>y[n]</code> and are referred to as the feedback coefficients.
+* Pay careful attention to the sign of the feedback coefficients.
+* Some design tools flip the sign of the feedback coefficients:
+* <pre>
+* y[n] = b0 * x[n] + d1;
+* d1 = b1 * x[n] - a1 * y[n] + d2;
+* d2 = b2 * x[n] - a2 * y[n];
+* </pre>
+* In this case the feedback coefficients <code>a1</code> and <code>a2</code> must be negated when used with the CMSIS DSP Library.
+*
+* \par
+* Higher order filters are realized as a cascade of second order sections.
+* <code>numStages</code> refers to the number of second order stages used.
+* For example, an 8th order filter would be realized with <code>numStages=4</code> second order stages.
+* A 9th order filter would be realized with <code>numStages=5</code> second order stages with the
+* coefficients for one of the stages configured as a first order filter (<code>b2=0</code> and <code>a2=0</code>).
+*
+* \par
+* <code>pState</code> points to the state variable array.
+* Each Biquad stage has 2 state variables <code>d1</code> and <code>d2</code>.
+* The state variables are arranged in the <code>pState</code> array as:
+* <pre>
+* {d11, d12, d21, d22, ...}
+* </pre>
+* where <code>d1x</code> refers to the state variables for the first Biquad and
+* <code>d2x</code> refers to the state variables for the second Biquad.
+* The state array has a total length of <code>2*numStages</code> values.
+* The state variables are updated after each block of data is processed; the coefficients are untouched.
+*
+* \par
+* The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II.
+* The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types.
+* That is why the Direct Form I structure supports Q15 and Q31 data types.
+* The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables <code>d1</code> and <code>d2</code>.
+* Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad.
+* The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.
+*
+* \par Instance Structure
+* The coefficients and state variables for a filter are stored together in an instance data structure.
+* A separate instance structure must be defined for each filter.
+* Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+*
+* \par Init Functions
+* There is also an associated initialization function.
+* The initialization function performs following operations:
+* - Sets the values of the internal structure fields.
+* - Zeros out the values in the state buffer.
+* To do this manually without calling the init function, assign the follow subfields of the instance structure:
+* numStages, pCoeffs, pState. Also set all of the values in pState to zero.
+*
+* \par
+* Use of the initialization function is optional.
+* However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+* To place an instance structure into a const data section, the instance structure must be manually initialized.
+* Set the values in the state buffer to zeros before static initialization.
+* For example, to statically initialize the instance structure use
+* <pre>
+* arm_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs};
+* </pre>
+* where <code>numStages</code> is the number of Biquad stages in the filter; <code>pState</code> is the address of the state buffer.
+* <code>pCoeffs</code> is the address of the coefficient buffer;
+*
+*/
+
+/**
+* @addtogroup BiquadCascadeDF2T
+* @{
+*/
+
+/**
+* @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+* @param[in] *S points to an instance of the filter data structure.
+* @param[in] *pSrc points to the block of input data.
+* @param[out] *pDst points to the block of output data
+* @param[in] blockSize number of samples to process.
+* @return none.
+*/
+
+
+LOW_OPTIMIZATION_ENTER
+void arm_biquad_cascade_df2T_f32(
+const arm_biquad_cascade_df2T_instance_f32 * S,
+float32_t * pSrc,
+float32_t * pDst,
+uint32_t blockSize)
+{
+
+ float32_t *pIn = pSrc; /* source pointer */
+ float32_t *pOut = pDst; /* destination pointer */
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */
+ float32_t acc1; /* accumulator */
+ float32_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ float32_t Xn1; /* temporary input */
+ float32_t d1, d2; /* state variables */
+ uint32_t sample, stage = S->numStages; /* loop counters */
+
+#if defined(ARM_MATH_CM7)
+
+ float32_t Xn2, Xn3, Xn4, Xn5, Xn6, Xn7, Xn8; /* Input State variables */
+ float32_t Xn9, Xn10, Xn11, Xn12, Xn13, Xn14, Xn15, Xn16;
+ float32_t acc2, acc3, acc4, acc5, acc6, acc7; /* Simulates the accumulator */
+ float32_t acc8, acc9, acc10, acc11, acc12, acc13, acc14, acc15, acc16;
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = pCoeffs[0];
+ b1 = pCoeffs[1];
+ b2 = pCoeffs[2];
+ a1 = pCoeffs[3];
+ /* Apply loop unrolling and compute 16 output values simultaneously. */
+ sample = blockSize >> 4U;
+ a2 = pCoeffs[4];
+
+ /*Reading the state values */
+ d1 = pState[0];
+ d2 = pState[1];
+
+ pCoeffs += 5U;
+
+
+ /* First part of the processing with loop unrolling. Compute 16 outputs at a time.
+ ** a second loop below computes the remaining 1 to 15 samples. */
+ while (sample > 0U) {
+
+ /* y[n] = b0 * x[n] + d1 */
+ /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+ /* d2 = b2 * x[n] + a2 * y[n] */
+
+ /* Read the first 2 inputs. 2 cycles */
+ Xn1 = pIn[0 ];
+ Xn2 = pIn[1 ];
+
+ /* Sample 1. 5 cycles */
+ Xn3 = pIn[2 ];
+ acc1 = b0 * Xn1 + d1;
+
+ Xn4 = pIn[3 ];
+ d1 = b1 * Xn1 + d2;
+
+ Xn5 = pIn[4 ];
+ d2 = b2 * Xn1;
+
+ Xn6 = pIn[5 ];
+ d1 += a1 * acc1;
+
+ Xn7 = pIn[6 ];
+ d2 += a2 * acc1;
+
+ /* Sample 2. 5 cycles */
+ Xn8 = pIn[7 ];
+ acc2 = b0 * Xn2 + d1;
+
+ Xn9 = pIn[8 ];
+ d1 = b1 * Xn2 + d2;
+
+ Xn10 = pIn[9 ];
+ d2 = b2 * Xn2;
+
+ Xn11 = pIn[10];
+ d1 += a1 * acc2;
+
+ Xn12 = pIn[11];
+ d2 += a2 * acc2;
+
+ /* Sample 3. 5 cycles */
+ Xn13 = pIn[12];
+ acc3 = b0 * Xn3 + d1;
+
+ Xn14 = pIn[13];
+ d1 = b1 * Xn3 + d2;
+
+ Xn15 = pIn[14];
+ d2 = b2 * Xn3;
+
+ Xn16 = pIn[15];
+ d1 += a1 * acc3;
+
+ pIn += 16;
+ d2 += a2 * acc3;
+
+ /* Sample 4. 5 cycles */
+ acc4 = b0 * Xn4 + d1;
+ d1 = b1 * Xn4 + d2;
+ d2 = b2 * Xn4;
+ d1 += a1 * acc4;
+ d2 += a2 * acc4;
+
+ /* Sample 5. 5 cycles */
+ acc5 = b0 * Xn5 + d1;
+ d1 = b1 * Xn5 + d2;
+ d2 = b2 * Xn5;
+ d1 += a1 * acc5;
+ d2 += a2 * acc5;
+
+ /* Sample 6. 5 cycles */
+ acc6 = b0 * Xn6 + d1;
+ d1 = b1 * Xn6 + d2;
+ d2 = b2 * Xn6;
+ d1 += a1 * acc6;
+ d2 += a2 * acc6;
+
+ /* Sample 7. 5 cycles */
+ acc7 = b0 * Xn7 + d1;
+ d1 = b1 * Xn7 + d2;
+ d2 = b2 * Xn7;
+ d1 += a1 * acc7;
+ d2 += a2 * acc7;
+
+ /* Sample 8. 5 cycles */
+ acc8 = b0 * Xn8 + d1;
+ d1 = b1 * Xn8 + d2;
+ d2 = b2 * Xn8;
+ d1 += a1 * acc8;
+ d2 += a2 * acc8;
+
+ /* Sample 9. 5 cycles */
+ acc9 = b0 * Xn9 + d1;
+ d1 = b1 * Xn9 + d2;
+ d2 = b2 * Xn9;
+ d1 += a1 * acc9;
+ d2 += a2 * acc9;
+
+ /* Sample 10. 5 cycles */
+ acc10 = b0 * Xn10 + d1;
+ d1 = b1 * Xn10 + d2;
+ d2 = b2 * Xn10;
+ d1 += a1 * acc10;
+ d2 += a2 * acc10;
+
+ /* Sample 11. 5 cycles */
+ acc11 = b0 * Xn11 + d1;
+ d1 = b1 * Xn11 + d2;
+ d2 = b2 * Xn11;
+ d1 += a1 * acc11;
+ d2 += a2 * acc11;
+
+ /* Sample 12. 5 cycles */
+ acc12 = b0 * Xn12 + d1;
+ d1 = b1 * Xn12 + d2;
+ d2 = b2 * Xn12;
+ d1 += a1 * acc12;
+ d2 += a2 * acc12;
+
+ /* Sample 13. 5 cycles */
+ acc13 = b0 * Xn13 + d1;
+ d1 = b1 * Xn13 + d2;
+ d2 = b2 * Xn13;
+
+ pOut[0 ] = acc1 ;
+ d1 += a1 * acc13;
+
+ pOut[1 ] = acc2 ;
+ d2 += a2 * acc13;
+
+ /* Sample 14. 5 cycles */
+ pOut[2 ] = acc3 ;
+ acc14 = b0 * Xn14 + d1;
+
+ pOut[3 ] = acc4 ;
+ d1 = b1 * Xn14 + d2;
+
+ pOut[4 ] = acc5 ;
+ d2 = b2 * Xn14;
+
+ pOut[5 ] = acc6 ;
+ d1 += a1 * acc14;
+
+ pOut[6 ] = acc7 ;
+ d2 += a2 * acc14;
+
+ /* Sample 15. 5 cycles */
+ pOut[7 ] = acc8 ;
+ pOut[8 ] = acc9 ;
+ acc15 = b0 * Xn15 + d1;
+
+ pOut[9 ] = acc10;
+ d1 = b1 * Xn15 + d2;
+
+ pOut[10] = acc11;
+ d2 = b2 * Xn15;
+
+ pOut[11] = acc12;
+ d1 += a1 * acc15;
+
+ pOut[12] = acc13;
+ d2 += a2 * acc15;
+
+ /* Sample 16. 5 cycles */
+ pOut[13] = acc14;
+ acc16 = b0 * Xn16 + d1;
+
+ pOut[14] = acc15;
+ d1 = b1 * Xn16 + d2;
+
+ pOut[15] = acc16;
+ d2 = b2 * Xn16;
+
+ sample--;
+ d1 += a1 * acc16;
+
+ pOut += 16;
+ d2 += a2 * acc16;
+ }
+
+ sample = blockSize & 0xFu;
+ while (sample > 0U) {
+ Xn1 = *pIn;
+ acc1 = b0 * Xn1 + d1;
+
+ pIn++;
+ d1 = b1 * Xn1 + d2;
+
+ *pOut = acc1;
+ d2 = b2 * Xn1;
+
+ pOut++;
+ d1 += a1 * acc1;
+
+ sample--;
+ d2 += a2 * acc1;
+ }
+
+ /* Store the updated state variables back into the state array */
+ pState[0] = d1;
+ /* The current stage input is given as the output to the next stage */
+ pIn = pDst;
+
+ pState[1] = d2;
+ /* decrement the loop counter */
+ stage--;
+
+ pState += 2U;
+
+ /*Reset the output working pointer */
+ pOut = pDst;
+
+ } while (stage > 0U);
+
+#elif defined(ARM_MATH_CM0_FAMILY)
+
+ /* Run the below code for Cortex-M0 */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /*Reading the state values */
+ d1 = pState[0];
+ d2 = pState[1];
+
+
+ sample = blockSize;
+
+ while (sample > 0U)
+ {
+ /* Read the input */
+ Xn1 = *pIn++;
+
+ /* y[n] = b0 * x[n] + d1 */
+ acc1 = (b0 * Xn1) + d1;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = acc1;
+
+ /* Every time after the output is computed state should be updated. */
+ /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+ d1 = ((b1 * Xn1) + (a1 * acc1)) + d2;
+
+ /* d2 = b2 * x[n] + a2 * y[n] */
+ d2 = (b2 * Xn1) + (a2 * acc1);
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* Store the updated state variables back into the state array */
+ *pState++ = d1;
+ *pState++ = d2;
+
+ /* The current stage input is given as the output to the next stage */
+ pIn = pDst;
+
+ /*Reset the output working pointer */
+ pOut = pDst;
+
+ /* decrement the loop counter */
+ stage--;
+
+ } while (stage > 0U);
+
+#else
+
+ float32_t Xn2, Xn3, Xn4; /* Input State variables */
+ float32_t acc2, acc3, acc4; /* accumulator */
+
+
+ float32_t p0, p1, p2, p3, p4, A1;
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+
+ /*Reading the state values */
+ d1 = pState[0];
+ d2 = pState[1];
+
+ /* Apply loop unrolling and compute 4 output values simultaneously. */
+ sample = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (sample > 0U) {
+
+ /* y[n] = b0 * x[n] + d1 */
+ /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+ /* d2 = b2 * x[n] + a2 * y[n] */
+
+ /* Read the four inputs */
+ Xn1 = pIn[0];
+ Xn2 = pIn[1];
+ Xn3 = pIn[2];
+ Xn4 = pIn[3];
+ pIn += 4;
+
+ p0 = b0 * Xn1;
+ p1 = b1 * Xn1;
+ acc1 = p0 + d1;
+ p0 = b0 * Xn2;
+ p3 = a1 * acc1;
+ p2 = b2 * Xn1;
+ A1 = p1 + p3;
+ p4 = a2 * acc1;
+ d1 = A1 + d2;
+ d2 = p2 + p4;
+
+ p1 = b1 * Xn2;
+ acc2 = p0 + d1;
+ p0 = b0 * Xn3;
+ p3 = a1 * acc2;
+ p2 = b2 * Xn2;
+ A1 = p1 + p3;
+ p4 = a2 * acc2;
+ d1 = A1 + d2;
+ d2 = p2 + p4;
+
+ p1 = b1 * Xn3;
+ acc3 = p0 + d1;
+ p0 = b0 * Xn4;
+ p3 = a1 * acc3;
+ p2 = b2 * Xn3;
+ A1 = p1 + p3;
+ p4 = a2 * acc3;
+ d1 = A1 + d2;
+ d2 = p2 + p4;
+
+ acc4 = p0 + d1;
+ p1 = b1 * Xn4;
+ p3 = a1 * acc4;
+ p2 = b2 * Xn4;
+ A1 = p1 + p3;
+ p4 = a2 * acc4;
+ d1 = A1 + d2;
+ d2 = p2 + p4;
+
+ pOut[0] = acc1;
+ pOut[1] = acc2;
+ pOut[2] = acc3;
+ pOut[3] = acc4;
+ pOut += 4;
+
+ sample--;
+ }
+
+ sample = blockSize & 0x3U;
+ while (sample > 0U) {
+ Xn1 = *pIn++;
+
+ p0 = b0 * Xn1;
+ p1 = b1 * Xn1;
+ acc1 = p0 + d1;
+ p3 = a1 * acc1;
+ p2 = b2 * Xn1;
+ A1 = p1 + p3;
+ p4 = a2 * acc1;
+ d1 = A1 + d2;
+ d2 = p2 + p4;
+
+ *pOut++ = acc1;
+
+ sample--;
+ }
+
+ /* Store the updated state variables back into the state array */
+ *pState++ = d1;
+ *pState++ = d2;
+
+ /* The current stage input is given as the output to the next stage */
+ pIn = pDst;
+
+ /*Reset the output working pointer */
+ pOut = pDst;
+
+ /* decrement the loop counter */
+ stage--;
+
+ } while (stage > 0U);
+
+#endif
+
+}
+LOW_OPTIMIZATION_EXIT
+
+/**
+ * @} end of BiquadCascadeDF2T group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c
new file mode 100644
index 0000000..8f8a830
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c
@@ -0,0 +1,590 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_biquad_cascade_df2T_f64.c
+ * Description: Processing function for floating-point transposed direct form II Biquad cascade filter
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+* @ingroup groupFilters
+*/
+
+/**
+* @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure
+*
+* This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure.
+* The filters are implemented as a cascade of second order Biquad sections.
+* These functions provide a slight memory savings as compared to the direct form I Biquad filter functions.
+* Only floating-point data is supported.
+*
+* This function operate on blocks of input and output data and each call to the function
+* processes <code>blockSize</code> samples through the filter.
+* <code>pSrc</code> points to the array of input data and
+* <code>pDst</code> points to the array of output data.
+* Both arrays contain <code>blockSize</code> values.
+*
+* \par Algorithm
+* Each Biquad stage implements a second order filter using the difference equation:
+* <pre>
+* y[n] = b0 * x[n] + d1
+* d1 = b1 * x[n] + a1 * y[n] + d2
+* d2 = b2 * x[n] + a2 * y[n]
+* </pre>
+* where d1 and d2 represent the two state values.
+*
+* \par
+* A Biquad filter using a transposed Direct Form II structure is shown below.
+* \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad"
+* Coefficients <code>b0, b1, and b2 </code> multiply the input signal <code>x[n]</code> and are referred to as the feedforward coefficients.
+* Coefficients <code>a1</code> and <code>a2</code> multiply the output signal <code>y[n]</code> and are referred to as the feedback coefficients.
+* Pay careful attention to the sign of the feedback coefficients.
+* Some design tools flip the sign of the feedback coefficients:
+* <pre>
+* y[n] = b0 * x[n] + d1;
+* d1 = b1 * x[n] - a1 * y[n] + d2;
+* d2 = b2 * x[n] - a2 * y[n];
+* </pre>
+* In this case the feedback coefficients <code>a1</code> and <code>a2</code> must be negated when used with the CMSIS DSP Library.
+*
+* \par
+* Higher order filters are realized as a cascade of second order sections.
+* <code>numStages</code> refers to the number of second order stages used.
+* For example, an 8th order filter would be realized with <code>numStages=4</code> second order stages.
+* A 9th order filter would be realized with <code>numStages=5</code> second order stages with the
+* coefficients for one of the stages configured as a first order filter (<code>b2=0</code> and <code>a2=0</code>).
+*
+* \par
+* <code>pState</code> points to the state variable array.
+* Each Biquad stage has 2 state variables <code>d1</code> and <code>d2</code>.
+* The state variables are arranged in the <code>pState</code> array as:
+* <pre>
+* {d11, d12, d21, d22, ...}
+* </pre>
+* where <code>d1x</code> refers to the state variables for the first Biquad and
+* <code>d2x</code> refers to the state variables for the second Biquad.
+* The state array has a total length of <code>2*numStages</code> values.
+* The state variables are updated after each block of data is processed; the coefficients are untouched.
+*
+* \par
+* The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II.
+* The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types.
+* That is why the Direct Form I structure supports Q15 and Q31 data types.
+* The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables <code>d1</code> and <code>d2</code>.
+* Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad.
+* The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.
+*
+* \par Instance Structure
+* The coefficients and state variables for a filter are stored together in an instance data structure.
+* A separate instance structure must be defined for each filter.
+* Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+*
+* \par Init Functions
+* There is also an associated initialization function.
+* The initialization function performs following operations:
+* - Sets the values of the internal structure fields.
+* - Zeros out the values in the state buffer.
+* To do this manually without calling the init function, assign the follow subfields of the instance structure:
+* numStages, pCoeffs, pState. Also set all of the values in pState to zero.
+*
+* \par
+* Use of the initialization function is optional.
+* However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+* To place an instance structure into a const data section, the instance structure must be manually initialized.
+* Set the values in the state buffer to zeros before static initialization.
+* For example, to statically initialize the instance structure use
+* <pre>
+* arm_biquad_cascade_df2T_instance_f64 S1 = {numStages, pState, pCoeffs};
+* </pre>
+* where <code>numStages</code> is the number of Biquad stages in the filter; <code>pState</code> is the address of the state buffer.
+* <code>pCoeffs</code> is the address of the coefficient buffer;
+*
+*/
+
+/**
+* @addtogroup BiquadCascadeDF2T
+* @{
+*/
+
+/**
+* @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+* @param[in] *S points to an instance of the filter data structure.
+* @param[in] *pSrc points to the block of input data.
+* @param[out] *pDst points to the block of output data
+* @param[in] blockSize number of samples to process.
+* @return none.
+*/
+
+
+LOW_OPTIMIZATION_ENTER
+void arm_biquad_cascade_df2T_f64(
+const arm_biquad_cascade_df2T_instance_f64 * S,
+float64_t * pSrc,
+float64_t * pDst,
+uint32_t blockSize)
+{
+
+ float64_t *pIn = pSrc; /* source pointer */
+ float64_t *pOut = pDst; /* destination pointer */
+ float64_t *pState = S->pState; /* State pointer */
+ float64_t *pCoeffs = S->pCoeffs; /* coefficient pointer */
+ float64_t acc1; /* accumulator */
+ float64_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ float64_t Xn1; /* temporary input */
+ float64_t d1, d2; /* state variables */
+ uint32_t sample, stage = S->numStages; /* loop counters */
+
+#if defined(ARM_MATH_CM7)
+
+ float64_t Xn2, Xn3, Xn4, Xn5, Xn6, Xn7, Xn8; /* Input State variables */
+ float64_t Xn9, Xn10, Xn11, Xn12, Xn13, Xn14, Xn15, Xn16;
+ float64_t acc2, acc3, acc4, acc5, acc6, acc7; /* Simulates the accumulator */
+ float64_t acc8, acc9, acc10, acc11, acc12, acc13, acc14, acc15, acc16;
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = pCoeffs[0];
+ b1 = pCoeffs[1];
+ b2 = pCoeffs[2];
+ a1 = pCoeffs[3];
+ /* Apply loop unrolling and compute 16 output values simultaneously. */
+ sample = blockSize >> 4U;
+ a2 = pCoeffs[4];
+
+ /*Reading the state values */
+ d1 = pState[0];
+ d2 = pState[1];
+
+ pCoeffs += 5U;
+
+
+ /* First part of the processing with loop unrolling. Compute 16 outputs at a time.
+ ** a second loop below computes the remaining 1 to 15 samples. */
+ while (sample > 0U) {
+
+ /* y[n] = b0 * x[n] + d1 */
+ /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+ /* d2 = b2 * x[n] + a2 * y[n] */
+
+ /* Read the first 2 inputs. 2 cycles */
+ Xn1 = pIn[0 ];
+ Xn2 = pIn[1 ];
+
+ /* Sample 1. 5 cycles */
+ Xn3 = pIn[2 ];
+ acc1 = b0 * Xn1 + d1;
+
+ Xn4 = pIn[3 ];
+ d1 = b1 * Xn1 + d2;
+
+ Xn5 = pIn[4 ];
+ d2 = b2 * Xn1;
+
+ Xn6 = pIn[5 ];
+ d1 += a1 * acc1;
+
+ Xn7 = pIn[6 ];
+ d2 += a2 * acc1;
+
+ /* Sample 2. 5 cycles */
+ Xn8 = pIn[7 ];
+ acc2 = b0 * Xn2 + d1;
+
+ Xn9 = pIn[8 ];
+ d1 = b1 * Xn2 + d2;
+
+ Xn10 = pIn[9 ];
+ d2 = b2 * Xn2;
+
+ Xn11 = pIn[10];
+ d1 += a1 * acc2;
+
+ Xn12 = pIn[11];
+ d2 += a2 * acc2;
+
+ /* Sample 3. 5 cycles */
+ Xn13 = pIn[12];
+ acc3 = b0 * Xn3 + d1;
+
+ Xn14 = pIn[13];
+ d1 = b1 * Xn3 + d2;
+
+ Xn15 = pIn[14];
+ d2 = b2 * Xn3;
+
+ Xn16 = pIn[15];
+ d1 += a1 * acc3;
+
+ pIn += 16;
+ d2 += a2 * acc3;
+
+ /* Sample 4. 5 cycles */
+ acc4 = b0 * Xn4 + d1;
+ d1 = b1 * Xn4 + d2;
+ d2 = b2 * Xn4;
+ d1 += a1 * acc4;
+ d2 += a2 * acc4;
+
+ /* Sample 5. 5 cycles */
+ acc5 = b0 * Xn5 + d1;
+ d1 = b1 * Xn5 + d2;
+ d2 = b2 * Xn5;
+ d1 += a1 * acc5;
+ d2 += a2 * acc5;
+
+ /* Sample 6. 5 cycles */
+ acc6 = b0 * Xn6 + d1;
+ d1 = b1 * Xn6 + d2;
+ d2 = b2 * Xn6;
+ d1 += a1 * acc6;
+ d2 += a2 * acc6;
+
+ /* Sample 7. 5 cycles */
+ acc7 = b0 * Xn7 + d1;
+ d1 = b1 * Xn7 + d2;
+ d2 = b2 * Xn7;
+ d1 += a1 * acc7;
+ d2 += a2 * acc7;
+
+ /* Sample 8. 5 cycles */
+ acc8 = b0 * Xn8 + d1;
+ d1 = b1 * Xn8 + d2;
+ d2 = b2 * Xn8;
+ d1 += a1 * acc8;
+ d2 += a2 * acc8;
+
+ /* Sample 9. 5 cycles */
+ acc9 = b0 * Xn9 + d1;
+ d1 = b1 * Xn9 + d2;
+ d2 = b2 * Xn9;
+ d1 += a1 * acc9;
+ d2 += a2 * acc9;
+
+ /* Sample 10. 5 cycles */
+ acc10 = b0 * Xn10 + d1;
+ d1 = b1 * Xn10 + d2;
+ d2 = b2 * Xn10;
+ d1 += a1 * acc10;
+ d2 += a2 * acc10;
+
+ /* Sample 11. 5 cycles */
+ acc11 = b0 * Xn11 + d1;
+ d1 = b1 * Xn11 + d2;
+ d2 = b2 * Xn11;
+ d1 += a1 * acc11;
+ d2 += a2 * acc11;
+
+ /* Sample 12. 5 cycles */
+ acc12 = b0 * Xn12 + d1;
+ d1 = b1 * Xn12 + d2;
+ d2 = b2 * Xn12;
+ d1 += a1 * acc12;
+ d2 += a2 * acc12;
+
+ /* Sample 13. 5 cycles */
+ acc13 = b0 * Xn13 + d1;
+ d1 = b1 * Xn13 + d2;
+ d2 = b2 * Xn13;
+
+ pOut[0 ] = acc1 ;
+ d1 += a1 * acc13;
+
+ pOut[1 ] = acc2 ;
+ d2 += a2 * acc13;
+
+ /* Sample 14. 5 cycles */
+ pOut[2 ] = acc3 ;
+ acc14 = b0 * Xn14 + d1;
+
+ pOut[3 ] = acc4 ;
+ d1 = b1 * Xn14 + d2;
+
+ pOut[4 ] = acc5 ;
+ d2 = b2 * Xn14;
+
+ pOut[5 ] = acc6 ;
+ d1 += a1 * acc14;
+
+ pOut[6 ] = acc7 ;
+ d2 += a2 * acc14;
+
+ /* Sample 15. 5 cycles */
+ pOut[7 ] = acc8 ;
+ pOut[8 ] = acc9 ;
+ acc15 = b0 * Xn15 + d1;
+
+ pOut[9 ] = acc10;
+ d1 = b1 * Xn15 + d2;
+
+ pOut[10] = acc11;
+ d2 = b2 * Xn15;
+
+ pOut[11] = acc12;
+ d1 += a1 * acc15;
+
+ pOut[12] = acc13;
+ d2 += a2 * acc15;
+
+ /* Sample 16. 5 cycles */
+ pOut[13] = acc14;
+ acc16 = b0 * Xn16 + d1;
+
+ pOut[14] = acc15;
+ d1 = b1 * Xn16 + d2;
+
+ pOut[15] = acc16;
+ d2 = b2 * Xn16;
+
+ sample--;
+ d1 += a1 * acc16;
+
+ pOut += 16;
+ d2 += a2 * acc16;
+ }
+
+ sample = blockSize & 0xFu;
+ while (sample > 0U) {
+ Xn1 = *pIn;
+ acc1 = b0 * Xn1 + d1;
+
+ pIn++;
+ d1 = b1 * Xn1 + d2;
+
+ *pOut = acc1;
+ d2 = b2 * Xn1;
+
+ pOut++;
+ d1 += a1 * acc1;
+
+ sample--;
+ d2 += a2 * acc1;
+ }
+
+ /* Store the updated state variables back into the state array */
+ pState[0] = d1;
+ /* The current stage input is given as the output to the next stage */
+ pIn = pDst;
+
+ pState[1] = d2;
+ /* decrement the loop counter */
+ stage--;
+
+ pState += 2U;
+
+ /*Reset the output working pointer */
+ pOut = pDst;
+
+ } while (stage > 0U);
+
+#elif defined(ARM_MATH_CM0_FAMILY)
+
+ /* Run the below code for Cortex-M0 */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /*Reading the state values */
+ d1 = pState[0];
+ d2 = pState[1];
+
+
+ sample = blockSize;
+
+ while (sample > 0U)
+ {
+ /* Read the input */
+ Xn1 = *pIn++;
+
+ /* y[n] = b0 * x[n] + d1 */
+ acc1 = (b0 * Xn1) + d1;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = acc1;
+
+ /* Every time after the output is computed state should be updated. */
+ /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+ d1 = ((b1 * Xn1) + (a1 * acc1)) + d2;
+
+ /* d2 = b2 * x[n] + a2 * y[n] */
+ d2 = (b2 * Xn1) + (a2 * acc1);
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* Store the updated state variables back into the state array */
+ *pState++ = d1;
+ *pState++ = d2;
+
+ /* The current stage input is given as the output to the next stage */
+ pIn = pDst;
+
+ /*Reset the output working pointer */
+ pOut = pDst;
+
+ /* decrement the loop counter */
+ stage--;
+
+ } while (stage > 0U);
+
+#else
+
+ float64_t Xn2, Xn3, Xn4; /* Input State variables */
+ float64_t acc2, acc3, acc4; /* accumulator */
+
+
+ float64_t p0, p1, p2, p3, p4, A1;
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+
+ /*Reading the state values */
+ d1 = pState[0];
+ d2 = pState[1];
+
+ /* Apply loop unrolling and compute 4 output values simultaneously. */
+ sample = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (sample > 0U) {
+
+ /* y[n] = b0 * x[n] + d1 */
+ /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+ /* d2 = b2 * x[n] + a2 * y[n] */
+
+ /* Read the four inputs */
+ Xn1 = pIn[0];
+ Xn2 = pIn[1];
+ Xn3 = pIn[2];
+ Xn4 = pIn[3];
+ pIn += 4;
+
+ p0 = b0 * Xn1;
+ p1 = b1 * Xn1;
+ acc1 = p0 + d1;
+ p0 = b0 * Xn2;
+ p3 = a1 * acc1;
+ p2 = b2 * Xn1;
+ A1 = p1 + p3;
+ p4 = a2 * acc1;
+ d1 = A1 + d2;
+ d2 = p2 + p4;
+
+ p1 = b1 * Xn2;
+ acc2 = p0 + d1;
+ p0 = b0 * Xn3;
+ p3 = a1 * acc2;
+ p2 = b2 * Xn2;
+ A1 = p1 + p3;
+ p4 = a2 * acc2;
+ d1 = A1 + d2;
+ d2 = p2 + p4;
+
+ p1 = b1 * Xn3;
+ acc3 = p0 + d1;
+ p0 = b0 * Xn4;
+ p3 = a1 * acc3;
+ p2 = b2 * Xn3;
+ A1 = p1 + p3;
+ p4 = a2 * acc3;
+ d1 = A1 + d2;
+ d2 = p2 + p4;
+
+ acc4 = p0 + d1;
+ p1 = b1 * Xn4;
+ p3 = a1 * acc4;
+ p2 = b2 * Xn4;
+ A1 = p1 + p3;
+ p4 = a2 * acc4;
+ d1 = A1 + d2;
+ d2 = p2 + p4;
+
+ pOut[0] = acc1;
+ pOut[1] = acc2;
+ pOut[2] = acc3;
+ pOut[3] = acc4;
+ pOut += 4;
+
+ sample--;
+ }
+
+ sample = blockSize & 0x3U;
+ while (sample > 0U) {
+ Xn1 = *pIn++;
+
+ p0 = b0 * Xn1;
+ p1 = b1 * Xn1;
+ acc1 = p0 + d1;
+ p3 = a1 * acc1;
+ p2 = b2 * Xn1;
+ A1 = p1 + p3;
+ p4 = a2 * acc1;
+ d1 = A1 + d2;
+ d2 = p2 + p4;
+
+ *pOut++ = acc1;
+
+ sample--;
+ }
+
+ /* Store the updated state variables back into the state array */
+ *pState++ = d1;
+ *pState++ = d2;
+
+ /* The current stage input is given as the output to the next stage */
+ pIn = pDst;
+
+ /*Reset the output working pointer */
+ pOut = pDst;
+
+ /* decrement the loop counter */
+ stage--;
+
+ } while (stage > 0U);
+
+#endif
+
+}
+LOW_OPTIMIZATION_EXIT
+
+/**
+ * @} end of BiquadCascadeDF2T group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
new file mode 100644
index 0000000..6dfc985
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
@@ -0,0 +1,89 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_biquad_cascade_df2T_init_f32.c
+ * Description: Initialization function for floating-point transposed direct form II Biquad cascade filter
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF2T
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ *
+ * <b>Coefficient and State Ordering:</b>
+ * \par
+ * The coefficients are stored in the array <code>pCoeffs</code> in the following order:
+ * <pre>
+ * {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+ * </pre>
+ *
+ * \par
+ * where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage,
+ * <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage,
+ * and so on. The <code>pCoeffs</code> array contains a total of <code>5*numStages</code> values.
+ *
+ * \par
+ * The <code>pState</code> is a pointer to state array.
+ * Each Biquad stage has 2 state variables <code>d1,</code> and <code>d2</code>.
+ * The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on.
+ * The state array has a total length of <code>2*numStages</code> values.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ */
+
+void arm_biquad_cascade_df2T_init_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState)
+{
+ /* Assign filter stages */
+ S->numStages = numStages;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always 2 * numStages */
+ memset(pState, 0, (2U * (uint32_t) numStages) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ * @} end of BiquadCascadeDF2T group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c
new file mode 100644
index 0000000..8141da5
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c
@@ -0,0 +1,89 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_biquad_cascade_df2T_init_f64.c
+ * Description: Initialization function for floating-point transposed direct form II Biquad cascade filter
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF2T
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ *
+ * <b>Coefficient and State Ordering:</b>
+ * \par
+ * The coefficients are stored in the array <code>pCoeffs</code> in the following order:
+ * <pre>
+ * {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+ * </pre>
+ *
+ * \par
+ * where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage,
+ * <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage,
+ * and so on. The <code>pCoeffs</code> array contains a total of <code>5*numStages</code> values.
+ *
+ * \par
+ * The <code>pState</code> is a pointer to state array.
+ * Each Biquad stage has 2 state variables <code>d1,</code> and <code>d2</code>.
+ * The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on.
+ * The state array has a total length of <code>2*numStages</code> values.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ */
+
+void arm_biquad_cascade_df2T_init_f64(
+ arm_biquad_cascade_df2T_instance_f64 * S,
+ uint8_t numStages,
+ float64_t * pCoeffs,
+ float64_t * pState)
+{
+ /* Assign filter stages */
+ S->numStages = numStages;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always 2 * numStages */
+ memset(pState, 0, (2U * (uint32_t) numStages) * sizeof(float64_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ * @} end of BiquadCascadeDF2T group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c
new file mode 100644
index 0000000..36084e5
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c
@@ -0,0 +1,670 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_biquad_cascade_stereo_df2T_f32.c
+ * Description: Processing function for floating-point transposed direct form II Biquad cascade filter. 2 channels
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+* @ingroup groupFilters
+*/
+
+/**
+* @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure
+*
+* This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure.
+* The filters are implemented as a cascade of second order Biquad sections.
+* These functions provide a slight memory savings as compared to the direct form I Biquad filter functions.
+* Only floating-point data is supported.
+*
+* This function operate on blocks of input and output data and each call to the function
+* processes <code>blockSize</code> samples through the filter.
+* <code>pSrc</code> points to the array of input data and
+* <code>pDst</code> points to the array of output data.
+* Both arrays contain <code>blockSize</code> values.
+*
+* \par Algorithm
+* Each Biquad stage implements a second order filter using the difference equation:
+* <pre>
+* y[n] = b0 * x[n] + d1
+* d1 = b1 * x[n] + a1 * y[n] + d2
+* d2 = b2 * x[n] + a2 * y[n]
+* </pre>
+* where d1 and d2 represent the two state values.
+*
+* \par
+* A Biquad filter using a transposed Direct Form II structure is shown below.
+* \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad"
+* Coefficients <code>b0, b1, and b2 </code> multiply the input signal <code>x[n]</code> and are referred to as the feedforward coefficients.
+* Coefficients <code>a1</code> and <code>a2</code> multiply the output signal <code>y[n]</code> and are referred to as the feedback coefficients.
+* Pay careful attention to the sign of the feedback coefficients.
+* Some design tools flip the sign of the feedback coefficients:
+* <pre>
+* y[n] = b0 * x[n] + d1;
+* d1 = b1 * x[n] - a1 * y[n] + d2;
+* d2 = b2 * x[n] - a2 * y[n];
+* </pre>
+* In this case the feedback coefficients <code>a1</code> and <code>a2</code> must be negated when used with the CMSIS DSP Library.
+*
+* \par
+* Higher order filters are realized as a cascade of second order sections.
+* <code>numStages</code> refers to the number of second order stages used.
+* For example, an 8th order filter would be realized with <code>numStages=4</code> second order stages.
+* A 9th order filter would be realized with <code>numStages=5</code> second order stages with the
+* coefficients for one of the stages configured as a first order filter (<code>b2=0</code> and <code>a2=0</code>).
+*
+* \par
+* <code>pState</code> points to the state variable array.
+* Each Biquad stage has 2 state variables <code>d1</code> and <code>d2</code>.
+* The state variables are arranged in the <code>pState</code> array as:
+* <pre>
+* {d11, d12, d21, d22, ...}
+* </pre>
+* where <code>d1x</code> refers to the state variables for the first Biquad and
+* <code>d2x</code> refers to the state variables for the second Biquad.
+* The state array has a total length of <code>2*numStages</code> values.
+* The state variables are updated after each block of data is processed; the coefficients are untouched.
+*
+* \par
+* The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II.
+* The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types.
+* That is why the Direct Form I structure supports Q15 and Q31 data types.
+* The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables <code>d1</code> and <code>d2</code>.
+* Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad.
+* The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.
+*
+* \par Instance Structure
+* The coefficients and state variables for a filter are stored together in an instance data structure.
+* A separate instance structure must be defined for each filter.
+* Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+*
+* \par Init Functions
+* There is also an associated initialization function.
+* The initialization function performs following operations:
+* - Sets the values of the internal structure fields.
+* - Zeros out the values in the state buffer.
+* To do this manually without calling the init function, assign the follow subfields of the instance structure:
+* numStages, pCoeffs, pState. Also set all of the values in pState to zero.
+*
+* \par
+* Use of the initialization function is optional.
+* However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+* To place an instance structure into a const data section, the instance structure must be manually initialized.
+* Set the values in the state buffer to zeros before static initialization.
+* For example, to statically initialize the instance structure use
+* <pre>
+* arm_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs};
+* </pre>
+* where <code>numStages</code> is the number of Biquad stages in the filter; <code>pState</code> is the address of the state buffer.
+* <code>pCoeffs</code> is the address of the coefficient buffer;
+*
+*/
+
+/**
+* @addtogroup BiquadCascadeDF2T
+* @{
+*/
+
+/**
+* @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+* @param[in] *S points to an instance of the filter data structure.
+* @param[in] *pSrc points to the block of input data.
+* @param[out] *pDst points to the block of output data
+* @param[in] blockSize number of samples to process.
+* @return none.
+*/
+
+
+LOW_OPTIMIZATION_ENTER
+void arm_biquad_cascade_stereo_df2T_f32(
+const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+float32_t * pSrc,
+float32_t * pDst,
+uint32_t blockSize)
+{
+
+ float32_t *pIn = pSrc; /* source pointer */
+ float32_t *pOut = pDst; /* destination pointer */
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */
+ float32_t acc1a, acc1b; /* accumulator */
+ float32_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ float32_t Xn1a, Xn1b; /* temporary input */
+ float32_t d1a, d2a, d1b, d2b; /* state variables */
+ uint32_t sample, stage = S->numStages; /* loop counters */
+
+#if defined(ARM_MATH_CM7)
+
+ float32_t Xn2a, Xn3a, Xn4a, Xn5a, Xn6a, Xn7a, Xn8a; /* Input State variables */
+ float32_t Xn2b, Xn3b, Xn4b, Xn5b, Xn6b, Xn7b, Xn8b; /* Input State variables */
+ float32_t acc2a, acc3a, acc4a, acc5a, acc6a, acc7a, acc8a; /* Simulates the accumulator */
+ float32_t acc2b, acc3b, acc4b, acc5b, acc6b, acc7b, acc8b; /* Simulates the accumulator */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = pCoeffs[0];
+ b1 = pCoeffs[1];
+ b2 = pCoeffs[2];
+ a1 = pCoeffs[3];
+ /* Apply loop unrolling and compute 8 output values simultaneously. */
+ sample = blockSize >> 3U;
+ a2 = pCoeffs[4];
+
+ /*Reading the state values */
+ d1a = pState[0];
+ d2a = pState[1];
+ d1b = pState[2];
+ d2b = pState[3];
+
+ pCoeffs += 5U;
+
+ /* First part of the processing with loop unrolling. Compute 8 outputs at a time.
+ ** a second loop below computes the remaining 1 to 7 samples. */
+ while (sample > 0U) {
+
+ /* y[n] = b0 * x[n] + d1 */
+ /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+ /* d2 = b2 * x[n] + a2 * y[n] */
+
+ /* Read the first 2 inputs. 2 cycles */
+ Xn1a = pIn[0 ];
+ Xn1b = pIn[1 ];
+
+ /* Sample 1. 5 cycles */
+ Xn2a = pIn[2 ];
+ acc1a = b0 * Xn1a + d1a;
+
+ Xn2b = pIn[3 ];
+ d1a = b1 * Xn1a + d2a;
+
+ Xn3a = pIn[4 ];
+ d2a = b2 * Xn1a;
+
+ Xn3b = pIn[5 ];
+ d1a += a1 * acc1a;
+
+ Xn4a = pIn[6 ];
+ d2a += a2 * acc1a;
+
+ /* Sample 2. 5 cycles */
+ Xn4b = pIn[7 ];
+ acc1b = b0 * Xn1b + d1b;
+
+ Xn5a = pIn[8 ];
+ d1b = b1 * Xn1b + d2b;
+
+ Xn5b = pIn[9 ];
+ d2b = b2 * Xn1b;
+
+ Xn6a = pIn[10];
+ d1b += a1 * acc1b;
+
+ Xn6b = pIn[11];
+ d2b += a2 * acc1b;
+
+ /* Sample 3. 5 cycles */
+ Xn7a = pIn[12];
+ acc2a = b0 * Xn2a + d1a;
+
+ Xn7b = pIn[13];
+ d1a = b1 * Xn2a + d2a;
+
+ Xn8a = pIn[14];
+ d2a = b2 * Xn2a;
+
+ Xn8b = pIn[15];
+ d1a += a1 * acc2a;
+
+ pIn += 16;
+ d2a += a2 * acc2a;
+
+ /* Sample 4. 5 cycles */
+ acc2b = b0 * Xn2b + d1b;
+ d1b = b1 * Xn2b + d2b;
+ d2b = b2 * Xn2b;
+ d1b += a1 * acc2b;
+ d2b += a2 * acc2b;
+
+ /* Sample 5. 5 cycles */
+ acc3a = b0 * Xn3a + d1a;
+ d1a = b1 * Xn3a + d2a;
+ d2a = b2 * Xn3a;
+ d1a += a1 * acc3a;
+ d2a += a2 * acc3a;
+
+ /* Sample 6. 5 cycles */
+ acc3b = b0 * Xn3b + d1b;
+ d1b = b1 * Xn3b + d2b;
+ d2b = b2 * Xn3b;
+ d1b += a1 * acc3b;
+ d2b += a2 * acc3b;
+
+ /* Sample 7. 5 cycles */
+ acc4a = b0 * Xn4a + d1a;
+ d1a = b1 * Xn4a + d2a;
+ d2a = b2 * Xn4a;
+ d1a += a1 * acc4a;
+ d2a += a2 * acc4a;
+
+ /* Sample 8. 5 cycles */
+ acc4b = b0 * Xn4b + d1b;
+ d1b = b1 * Xn4b + d2b;
+ d2b = b2 * Xn4b;
+ d1b += a1 * acc4b;
+ d2b += a2 * acc4b;
+
+ /* Sample 9. 5 cycles */
+ acc5a = b0 * Xn5a + d1a;
+ d1a = b1 * Xn5a + d2a;
+ d2a = b2 * Xn5a;
+ d1a += a1 * acc5a;
+ d2a += a2 * acc5a;
+
+ /* Sample 10. 5 cycles */
+ acc5b = b0 * Xn5b + d1b;
+ d1b = b1 * Xn5b + d2b;
+ d2b = b2 * Xn5b;
+ d1b += a1 * acc5b;
+ d2b += a2 * acc5b;
+
+ /* Sample 11. 5 cycles */
+ acc6a = b0 * Xn6a + d1a;
+ d1a = b1 * Xn6a + d2a;
+ d2a = b2 * Xn6a;
+ d1a += a1 * acc6a;
+ d2a += a2 * acc6a;
+
+ /* Sample 12. 5 cycles */
+ acc6b = b0 * Xn6b + d1b;
+ d1b = b1 * Xn6b + d2b;
+ d2b = b2 * Xn6b;
+ d1b += a1 * acc6b;
+ d2b += a2 * acc6b;
+
+ /* Sample 13. 5 cycles */
+ acc7a = b0 * Xn7a + d1a;
+ d1a = b1 * Xn7a + d2a;
+
+ pOut[0 ] = acc1a ;
+ d2a = b2 * Xn7a;
+
+ pOut[1 ] = acc1b ;
+ d1a += a1 * acc7a;
+
+ pOut[2 ] = acc2a ;
+ d2a += a2 * acc7a;
+
+ /* Sample 14. 5 cycles */
+ pOut[3 ] = acc2b ;
+ acc7b = b0 * Xn7b + d1b;
+
+ pOut[4 ] = acc3a ;
+ d1b = b1 * Xn7b + d2b;
+
+ pOut[5 ] = acc3b ;
+ d2b = b2 * Xn7b;
+
+ pOut[6 ] = acc4a ;
+ d1b += a1 * acc7b;
+
+ pOut[7 ] = acc4b ;
+ d2b += a2 * acc7b;
+
+ /* Sample 15. 5 cycles */
+ pOut[8 ] = acc5a ;
+ acc8a = b0 * Xn8a + d1a;
+
+ pOut[9 ] = acc5b;
+ d1a = b1 * Xn8a + d2a;
+
+ pOut[10] = acc6a;
+ d2a = b2 * Xn8a;
+
+ pOut[11] = acc6b;
+ d1a += a1 * acc8a;
+
+ pOut[12] = acc7a;
+ d2a += a2 * acc8a;
+
+ /* Sample 16. 5 cycles */
+ pOut[13] = acc7b;
+ acc8b = b0 * Xn8b + d1b;
+
+ pOut[14] = acc8a;
+ d1b = b1 * Xn8b + d2b;
+
+ pOut[15] = acc8b;
+ d2b = b2 * Xn8b;
+
+ sample--;
+ d1b += a1 * acc8b;
+
+ pOut += 16;
+ d2b += a2 * acc8b;
+ }
+
+ sample = blockSize & 0x7U;
+ while (sample > 0U) {
+ /* Read the input */
+ Xn1a = *pIn++; //Channel a
+ Xn1b = *pIn++; //Channel b
+
+ /* y[n] = b0 * x[n] + d1 */
+ acc1a = (b0 * Xn1a) + d1a;
+ acc1b = (b0 * Xn1b) + d1b;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = acc1a;
+ *pOut++ = acc1b;
+
+ /* Every time after the output is computed state should be updated. */
+ /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+ d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a;
+ d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b;
+
+ /* d2 = b2 * x[n] + a2 * y[n] */
+ d2a = (b2 * Xn1a) + (a2 * acc1a);
+ d2b = (b2 * Xn1b) + (a2 * acc1b);
+
+ sample--;
+ }
+
+ /* Store the updated state variables back into the state array */
+ pState[0] = d1a;
+ pState[1] = d2a;
+
+ pState[2] = d1b;
+ pState[3] = d2b;
+
+ /* The current stage input is given as the output to the next stage */
+ pIn = pDst;
+ /* decrement the loop counter */
+ stage--;
+
+ pState += 4U;
+ /*Reset the output working pointer */
+ pOut = pDst;
+
+ } while (stage > 0U);
+
+#elif defined(ARM_MATH_CM0_FAMILY)
+
+ /* Run the below code for Cortex-M0 */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /*Reading the state values */
+ d1a = pState[0];
+ d2a = pState[1];
+ d1b = pState[2];
+ d2b = pState[3];
+
+
+ sample = blockSize;
+
+ while (sample > 0U)
+ {
+ /* Read the input */
+ Xn1a = *pIn++; //Channel a
+ Xn1b = *pIn++; //Channel b
+
+ /* y[n] = b0 * x[n] + d1 */
+ acc1a = (b0 * Xn1a) + d1a;
+ acc1b = (b0 * Xn1b) + d1b;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = acc1a;
+ *pOut++ = acc1b;
+
+ /* Every time after the output is computed state should be updated. */
+ /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+ d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a;
+ d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b;
+
+ /* d2 = b2 * x[n] + a2 * y[n] */
+ d2a = (b2 * Xn1a) + (a2 * acc1a);
+ d2b = (b2 * Xn1b) + (a2 * acc1b);
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* Store the updated state variables back into the state array */
+ *pState++ = d1a;
+ *pState++ = d2a;
+ *pState++ = d1b;
+ *pState++ = d2b;
+
+ /* The current stage input is given as the output to the next stage */
+ pIn = pDst;
+
+ /*Reset the output working pointer */
+ pOut = pDst;
+
+ /* decrement the loop counter */
+ stage--;
+
+ } while (stage > 0U);
+
+#else
+
+ float32_t Xn2a, Xn3a, Xn4a; /* Input State variables */
+ float32_t Xn2b, Xn3b, Xn4b; /* Input State variables */
+ float32_t acc2a, acc3a, acc4a; /* accumulator */
+ float32_t acc2b, acc3b, acc4b; /* accumulator */
+ float32_t p0a, p1a, p2a, p3a, p4a, A1a;
+ float32_t p0b, p1b, p2b, p3b, p4b, A1b;
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /*Reading the state values */
+ d1a = pState[0];
+ d2a = pState[1];
+ d1b = pState[2];
+ d2b = pState[3];
+
+ /* Apply loop unrolling and compute 4 output values simultaneously. */
+ sample = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (sample > 0U) {
+
+ /* y[n] = b0 * x[n] + d1 */
+ /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+ /* d2 = b2 * x[n] + a2 * y[n] */
+
+ /* Read the four inputs */
+ Xn1a = pIn[0];
+ Xn1b = pIn[1];
+ Xn2a = pIn[2];
+ Xn2b = pIn[3];
+ Xn3a = pIn[4];
+ Xn3b = pIn[5];
+ Xn4a = pIn[6];
+ Xn4b = pIn[7];
+ pIn += 8;
+
+ p0a = b0 * Xn1a;
+ p0b = b0 * Xn1b;
+ p1a = b1 * Xn1a;
+ p1b = b1 * Xn1b;
+ acc1a = p0a + d1a;
+ acc1b = p0b + d1b;
+ p0a = b0 * Xn2a;
+ p0b = b0 * Xn2b;
+ p3a = a1 * acc1a;
+ p3b = a1 * acc1b;
+ p2a = b2 * Xn1a;
+ p2b = b2 * Xn1b;
+ A1a = p1a + p3a;
+ A1b = p1b + p3b;
+ p4a = a2 * acc1a;
+ p4b = a2 * acc1b;
+ d1a = A1a + d2a;
+ d1b = A1b + d2b;
+ d2a = p2a + p4a;
+ d2b = p2b + p4b;
+
+ p1a = b1 * Xn2a;
+ p1b = b1 * Xn2b;
+ acc2a = p0a + d1a;
+ acc2b = p0b + d1b;
+ p0a = b0 * Xn3a;
+ p0b = b0 * Xn3b;
+ p3a = a1 * acc2a;
+ p3b = a1 * acc2b;
+ p2a = b2 * Xn2a;
+ p2b = b2 * Xn2b;
+ A1a = p1a + p3a;
+ A1b = p1b + p3b;
+ p4a = a2 * acc2a;
+ p4b = a2 * acc2b;
+ d1a = A1a + d2a;
+ d1b = A1b + d2b;
+ d2a = p2a + p4a;
+ d2b = p2b + p4b;
+
+ p1a = b1 * Xn3a;
+ p1b = b1 * Xn3b;
+ acc3a = p0a + d1a;
+ acc3b = p0b + d1b;
+ p0a = b0 * Xn4a;
+ p0b = b0 * Xn4b;
+ p3a = a1 * acc3a;
+ p3b = a1 * acc3b;
+ p2a = b2 * Xn3a;
+ p2b = b2 * Xn3b;
+ A1a = p1a + p3a;
+ A1b = p1b + p3b;
+ p4a = a2 * acc3a;
+ p4b = a2 * acc3b;
+ d1a = A1a + d2a;
+ d1b = A1b + d2b;
+ d2a = p2a + p4a;
+ d2b = p2b + p4b;
+
+ acc4a = p0a + d1a;
+ acc4b = p0b + d1b;
+ p1a = b1 * Xn4a;
+ p1b = b1 * Xn4b;
+ p3a = a1 * acc4a;
+ p3b = a1 * acc4b;
+ p2a = b2 * Xn4a;
+ p2b = b2 * Xn4b;
+ A1a = p1a + p3a;
+ A1b = p1b + p3b;
+ p4a = a2 * acc4a;
+ p4b = a2 * acc4b;
+ d1a = A1a + d2a;
+ d1b = A1b + d2b;
+ d2a = p2a + p4a;
+ d2b = p2b + p4b;
+
+ pOut[0] = acc1a;
+ pOut[1] = acc1b;
+ pOut[2] = acc2a;
+ pOut[3] = acc2b;
+ pOut[4] = acc3a;
+ pOut[5] = acc3b;
+ pOut[6] = acc4a;
+ pOut[7] = acc4b;
+ pOut += 8;
+
+ sample--;
+ }
+
+ sample = blockSize & 0x3U;
+ while (sample > 0U) {
+ Xn1a = *pIn++;
+ Xn1b = *pIn++;
+
+ p0a = b0 * Xn1a;
+ p0b = b0 * Xn1b;
+ p1a = b1 * Xn1a;
+ p1b = b1 * Xn1b;
+ acc1a = p0a + d1a;
+ acc1b = p0b + d1b;
+ p3a = a1 * acc1a;
+ p3b = a1 * acc1b;
+ p2a = b2 * Xn1a;
+ p2b = b2 * Xn1b;
+ A1a = p1a + p3a;
+ A1b = p1b + p3b;
+ p4a = a2 * acc1a;
+ p4b = a2 * acc1b;
+ d1a = A1a + d2a;
+ d1b = A1b + d2b;
+ d2a = p2a + p4a;
+ d2b = p2b + p4b;
+
+ *pOut++ = acc1a;
+ *pOut++ = acc1b;
+
+ sample--;
+ }
+
+ /* Store the updated state variables back into the state array */
+ *pState++ = d1a;
+ *pState++ = d2a;
+ *pState++ = d1b;
+ *pState++ = d2b;
+
+ /* The current stage input is given as the output to the next stage */
+ pIn = pDst;
+
+ /*Reset the output working pointer */
+ pOut = pDst;
+
+ /* decrement the loop counter */
+ stage--;
+
+ } while (stage > 0U);
+
+#endif
+
+}
+LOW_OPTIMIZATION_EXIT
+
+/**
+ * @} end of BiquadCascadeDF2T group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c
new file mode 100644
index 0000000..b847c6e
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c
@@ -0,0 +1,89 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_biquad_cascade_stereo_df2T_init_f32.c
+ * Description: Initialization function for floating-point transposed direct form II Biquad cascade filter
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF2T
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ *
+ * <b>Coefficient and State Ordering:</b>
+ * \par
+ * The coefficients are stored in the array <code>pCoeffs</code> in the following order:
+ * <pre>
+ * {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+ * </pre>
+ *
+ * \par
+ * where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage,
+ * <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage,
+ * and so on. The <code>pCoeffs</code> array contains a total of <code>5*numStages</code> values.
+ *
+ * \par
+ * The <code>pState</code> is a pointer to state array.
+ * Each Biquad stage has 2 state variables <code>d1,</code> and <code>d2</code> for each channel.
+ * The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on.
+ * The state array has a total length of <code>2*numStages</code> values.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ */
+
+void arm_biquad_cascade_stereo_df2T_init_f32(
+ arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState)
+{
+ /* Assign filter stages */
+ S->numStages = numStages;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always 4 * numStages */
+ memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ * @} end of BiquadCascadeDF2T group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_f32.c
new file mode 100644
index 0000000..906f7ab
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_f32.c
@@ -0,0 +1,635 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_conv_f32.c
+ * Description: Convolution of floating-point sequences
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup Conv Convolution
+ *
+ * Convolution is a mathematical operation that operates on two finite length vectors to generate a finite length output vector.
+ * Convolution is similar to correlation and is frequently used in filtering and data analysis.
+ * The CMSIS DSP library contains functions for convolving Q7, Q15, Q31, and floating-point data types.
+ * The library also provides fast versions of the Q15 and Q31 functions on Cortex-M4 and Cortex-M3.
+ *
+ * \par Algorithm
+ * Let <code>a[n]</code> and <code>b[n]</code> be sequences of length <code>srcALen</code> and <code>srcBLen</code> samples respectively.
+ * Then the convolution
+ *
+ * <pre>
+ * c[n] = a[n] * b[n]
+ * </pre>
+ *
+ * \par
+ * is defined as
+ * \image html ConvolutionEquation.gif
+ * \par
+ * Note that <code>c[n]</code> is of length <code>srcALen + srcBLen - 1</code> and is defined over the interval <code>n=0, 1, 2, ..., srcALen + srcBLen - 2</code>.
+ * <code>pSrcA</code> points to the first input vector of length <code>srcALen</code> and
+ * <code>pSrcB</code> points to the second input vector of length <code>srcBLen</code>.
+ * The output result is written to <code>pDst</code> and the calling function must allocate <code>srcALen+srcBLen-1</code> words for the result.
+ *
+ * \par
+ * Conceptually, when two signals <code>a[n]</code> and <code>b[n]</code> are convolved,
+ * the signal <code>b[n]</code> slides over <code>a[n]</code>.
+ * For each offset \c n, the overlapping portions of a[n] and b[n] are multiplied and summed together.
+ *
+ * \par
+ * Note that convolution is a commutative operation:
+ *
+ * <pre>
+ * a[n] * b[n] = b[n] * a[n].
+ * </pre>
+ *
+ * \par
+ * This means that switching the A and B arguments to the convolution functions has no effect.
+ *
+ * <b>Fixed-Point Behavior</b>
+ *
+ * \par
+ * Convolution requires summing up a large number of intermediate products.
+ * As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation.
+ * Refer to the function specific documentation below for further details of the particular algorithm used.
+ *
+ *
+ * <b>Fast Versions</b>
+ *
+ * \par
+ * Fast versions are supported for Q31 and Q15. Cycles for Fast versions are less compared to Q31 and Q15 of conv and the design requires
+ * the input signals should be scaled down to avoid intermediate overflows.
+ *
+ *
+ * <b>Opt Versions</b>
+ *
+ * \par
+ * Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation.
+ * These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+void arm_conv_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst)
+{
+
+
+#if defined (ARM_MATH_DSP)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float32_t *pIn1; /* inputA pointer */
+ float32_t *pIn2; /* inputB pointer */
+ float32_t *pOut = pDst; /* output pointer */
+ float32_t *px; /* Intermediate inputA pointer */
+ float32_t *py; /* Intermediate inputB pointer */
+ float32_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ float32_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ float32_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3; /* loop counters */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1U;
+ blockSize2 = srcALen - (srcBLen - 1U);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1U;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while (blockSize1 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* x[0] * y[srcBLen - 1] */
+ sum += *px++ * *py--;
+
+ /* x[1] * y[srcBLen - 2] */
+ sum += *px++ * *py--;
+
+ /* x[2] * y[srcBLen - 3] */
+ sum += *px++ * *py--;
+
+ /* x[3] * y[srcBLen - 4] */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0U;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if (srcBLen >= 4U)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0.0f;
+ acc1 = 0.0f;
+ acc2 = 0.0f;
+ acc3 = 0.0f;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *(py--);
+
+ /* Read x[3] sample */
+ x3 = *(px);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[0] * y[srcBLen - 1] */
+ acc0 += x0 * c0;
+
+ /* acc1 += x[1] * y[srcBLen - 1] */
+ acc1 += x1 * c0;
+
+ /* acc2 += x[2] * y[srcBLen - 1] */
+ acc2 += x2 * c0;
+
+ /* acc3 += x[3] * y[srcBLen - 1] */
+ acc3 += x3 * c0;
+
+ /* Read y[srcBLen - 2] sample */
+ c0 = *(py--);
+
+ /* Read x[4] sample */
+ x0 = *(px + 1U);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[1] * y[srcBLen - 2] */
+ acc0 += x1 * c0;
+ /* acc1 += x[2] * y[srcBLen - 2] */
+ acc1 += x2 * c0;
+ /* acc2 += x[3] * y[srcBLen - 2] */
+ acc2 += x3 * c0;
+ /* acc3 += x[4] * y[srcBLen - 2] */
+ acc3 += x0 * c0;
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *(py--);
+
+ /* Read x[5] sample */
+ x1 = *(px + 2U);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[srcBLen - 3] */
+ acc0 += x2 * c0;
+ /* acc1 += x[3] * y[srcBLen - 2] */
+ acc1 += x3 * c0;
+ /* acc2 += x[4] * y[srcBLen - 2] */
+ acc2 += x0 * c0;
+ /* acc3 += x[5] * y[srcBLen - 2] */
+ acc3 += x1 * c0;
+
+ /* Read y[srcBLen - 4] sample */
+ c0 = *(py--);
+
+ /* Read x[6] sample */
+ x2 = *(px + 3U);
+ px += 4U;
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[3] * y[srcBLen - 4] */
+ acc0 += x3 * c0;
+ /* acc1 += x[4] * y[srcBLen - 4] */
+ acc1 += x0 * c0;
+ /* acc2 += x[5] * y[srcBLen - 4] */
+ acc2 += x1 * c0;
+ /* acc3 += x[6] * y[srcBLen - 4] */
+ acc3 += x2 * c0;
+
+
+ } while (--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *(py--);
+
+ /* Read x[7] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 += x0 * c0;
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 += x1 * c0;
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 += x2 * c0;
+ /* acc3 += x[7] * y[srcBLen - 5] */
+ acc3 += x3 * c0;
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = acc0;
+ *pOut++ = acc1;
+ *pOut++ = acc2;
+ *pOut++ = acc3;
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4U;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += *px++ * *py--;
+ sum += *px++ * *py--;
+ sum += *px++ * *py--;
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while (blockSize3 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3 >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ sum += *px++ * *py--;
+
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum += *px++ * *py--;
+
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ sum += *px++ * *py--;
+
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = blockSize3 % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ float32_t *pIn1 = pSrcA; /* inputA pointer */
+ float32_t *pIn2 = pSrcB; /* inputB pointer */
+ float32_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counters */
+
+ /* Loop to calculate convolution for output length number of times */
+ for (i = 0U; i < ((srcALen + srcBLen) - 1U); i++)
+ {
+ /* Initialize sum with zero to carry out MAC operations */
+ sum = 0.0f;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0U; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if ((((i - j) < srcBLen) && (j < srcALen)))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += pIn1[j] * pIn2[i - j];
+ }
+ }
+ /* Store the output in the destination buffer */
+ pDst[i] = sum;
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_opt_q15.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_opt_q15.c
new file mode 100644
index 0000000..26c37f0
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_opt_q15.c
@@ -0,0 +1,531 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_conv_fast_opt_q15.c
+ * Description: Fast Q15 Convolution
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return none.
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * This fast version uses a 32-bit accumulator with 2.30 format.
+ * The accumulator maintains full precision of the intermediate multiplication results
+ * but provides only a single guard bit. There is no saturation on intermediate additions.
+ * Thus, if the accumulator overflows it wraps around and distorts the result.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
+ *
+ * \par
+ * See <code>arm_conv_q15()</code> for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.
+ */
+
+void arm_conv_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+ q31_t acc0, acc1, acc2, acc3; /* Accumulators */
+ q31_t x1, x2, x3; /* Temporary variables to hold state and coefficient values */
+ q31_t y1, y2; /* State variables */
+ q15_t *pOut = pDst; /* output pointer */
+ q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
+ q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ uint32_t j, k, blkCnt; /* loop counter */
+ uint32_t tapCnt; /* loop count */
+#ifdef UNALIGNED_SUPPORT_DISABLE
+
+ q15_t a, b;
+
+#endif /* #ifdef UNALIGNED_SUPPORT_DISABLE */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2 + srcBLen - 1;
+
+ /* points to smaller length sequence */
+ px = pIn2;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+
+ /* Copy smaller length input sequence in reverse order into second scratch buffer */
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Assuming scratch1 buffer is aligned by 32-bit */
+ /* Fill (srcBLen - 1U) zeros in scratch1 buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1U);
+
+ /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Copy (srcALen) samples in scratch buffer */
+ arm_copy_q15(pIn1, pScr1, srcALen);
+
+ /* Update pointers */
+ pScr1 += srcALen;
+
+#else
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcALen >> 2U;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcALen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Fill (srcBLen - 1U) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1U);
+
+#else
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = (srcBLen - 1U) >> 2U;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = (srcBLen - 1U) % 0x4U;
+
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = py;
+
+ /* First part of the processing with loop unrolling process 4 data points at a time.
+ ** a second loop below process for the remaining 1 to 3 samples. */
+
+ /* Actual convolution process starts here */
+ blkCnt = (srcALen + srcBLen - 1U) >> 2;
+
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr1)++;
+
+ tapCnt = (srcBLen) >> 2U;
+
+ while (tapCnt > 0U)
+ {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pIn2);
+ y2 = _SIMD32_OFFSET(pIn2 + 2U);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x1, y1, acc0);
+ acc2 = __SMLAD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = _SIMD32_OFFSET(pScr1);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x2, y2, acc0);
+ acc2 = __SMLAD(x1, y2, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+ acc1 = __SMLADX(x3, y2, acc1);
+
+ x2 = _SIMD32_OFFSET(pScr1 + 2U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y2, acc3);
+
+#else
+
+ /* Read four samples from smaller buffer */
+ a = *pIn2;
+ b = *(pIn2 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ y1 = __PKHBT(a, b, 16);
+#else
+ y1 = __PKHBT(b, a, 16);
+#endif
+
+ a = *(pIn2 + 2);
+ b = *(pIn2 + 3);
+#ifndef ARM_MATH_BIG_ENDIAN
+ y2 = __PKHBT(a, b, 16);
+#else
+ y2 = __PKHBT(b, a, 16);
+#endif
+
+ acc0 = __SMLAD(x1, y1, acc0);
+
+ acc2 = __SMLAD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ a = *pScr1;
+ b = *(pScr1 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(a, b, 16);
+#else
+ x1 = __PKHBT(b, a, 16);
+#endif
+
+ acc0 = __SMLAD(x2, y2, acc0);
+
+ acc2 = __SMLAD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ acc1 = __SMLADX(x3, y2, acc1);
+
+ a = *(pScr1 + 2);
+ b = *(pScr1 + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x2 = __PKHBT(a, b, 16);
+#else
+ x2 = __PKHBT(b, a, 16);
+#endif
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y2, acc3);
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* update scratch pointers */
+ pIn2 += 4U;
+ pScr1 += 4U;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3U;
+
+ while (tapCnt > 0U)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2);
+ acc1 += (*pScr1++ * *pIn2);
+ acc2 += (*pScr1++ * *pIn2);
+ acc3 += (*pScr1++ * *pIn2++);
+
+ pScr1 -= 3U;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+
+#else
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 4U;
+
+ }
+
+
+ blkCnt = (srcALen + srcBLen - 1U) & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1U;
+
+ while (tapCnt > 0U)
+ {
+
+ acc0 += (*pScr1++ * *pIn2++);
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while (tapCnt > 0U)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* The result is in 2.30 format. Convert to 1.15 with saturation.
+ ** Then store the output in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 1U;
+
+ }
+
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q15.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q15.c
new file mode 100644
index 0000000..16b0424
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q15.c
@@ -0,0 +1,1398 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_conv_fast_q15.c
+ * Description: Fast Q15 Convolution
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * This fast version uses a 32-bit accumulator with 2.30 format.
+ * The accumulator maintains full precision of the intermediate multiplication results
+ * but provides only a single guard bit. There is no saturation on intermediate additions.
+ * Thus, if the accumulator overflows it wraps around and distorts the result.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
+ *
+ * \par
+ * See <code>arm_conv_q15()</code> for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.
+ */
+
+void arm_conv_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst)
+{
+#ifndef UNALIGNED_SUPPORT_DISABLE
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt; /* loop counter */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1U;
+ blockSize2 = srcALen - (srcBLen - 1U);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1U;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations less than 4 */
+ /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ while ((count < 4U) && (blockSize1 > 0U))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over number of MAC operations between
+ * inputA samples and inputB samples */
+ k = count;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* The second part of the stage starts here */
+ /* The internal loop, over count, is unrolled by 4 */
+ /* To, read the last two inputB samples using SIMD:
+ * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+ py = py - 1;
+
+ while (blockSize1 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+ /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1U;
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + (count - 1U);
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* count is the index by which the pointer pIn1 to be incremented */
+ count = 0U;
+
+
+ /* --------------------
+ * Stage2 process
+ * -------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if (srcBLen >= 4U)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ py = py - 1U;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+
+ /* read x[0], x[1] samples */
+ x0 = *__SIMD32(px);
+ /* read x[1], x[2] samples */
+ x1 = _SIMD32_OFFSET(px+1);
+ px+= 2U;
+
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the last two inputB samples using SIMD:
+ * y[srcBLen - 1] and y[srcBLen - 2] */
+ c0 = *__SIMD32(py)--;
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLADX(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLADX(x1, c0, acc1);
+
+ /* Read x[2], x[3] */
+ x2 = *__SIMD32(px);
+
+ /* Read x[3], x[4] */
+ x3 = _SIMD32_OFFSET(px+1);
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLADX(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLADX(x3, c0, acc3);
+
+ /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+ c0 = *__SIMD32(py)--;
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLADX(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLADX(x3, c0, acc1);
+
+ /* Read x[4], x[5] */
+ x0 = _SIMD32_OFFSET(px+2);
+
+ /* Read x[5], x[6] */
+ x1 = _SIMD32_OFFSET(px+3);
+ px += 4U;
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLADX(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLADX(x1, c0, acc3);
+
+ } while (--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ if (k == 1U)
+ {
+ /* Read y[srcBLen - 5] */
+ c0 = *(py+1);
+
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16U;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7] */
+ x3 = *__SIMD32(px);
+ px++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLADX(x1, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ if (k == 2U)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = _SIMD32_OFFSET(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px+1);
+ px += 2U;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+ }
+
+ if (k == 3U)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = _SIMD32_OFFSET(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px+1);
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+
+ /* Read y[srcBLen - 7] */
+ c0 = *(py-1);
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16U;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[10] */
+ x3 = _SIMD32_OFFSET(px+2);
+ px += 3U;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x1, c0, acc0);
+ acc1 = __SMLAD(x2, c0, acc1);
+ acc2 = __SMLADX(x2, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ /* Store the results in the accumulators in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ = __PKHBT((acc0 >> 15), (acc1 >> 15), 16);
+ *__SIMD32(pOut)++ = __PKHBT((acc2 >> 15), (acc3 >> 15), 16);
+
+#else
+
+ *__SIMD32(pOut)++ = __PKHBT((acc1 >> 15), (acc0 >> 15), 16);
+ *__SIMD32(pOut)++ = __PKHBT((acc3 >> 15), (acc2 >> 15), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4U;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ pIn2 = pSrc2 - 1U;
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations greater than 4 */
+ /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ j = blockSize3 >> 2U;
+
+ while ((j > 0U) && (blockSize3 > 0U))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3 >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied
+ * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+ /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied
+ * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1U;
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = blockSize3 % 0x4U;
+
+ while (k > 0U)
+ {
+ /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ j--;
+ }
+
+ /* The second part of the stage starts here */
+ /* SIMD is not used for the next MAC operations,
+ * so pointer py is updated to read only one sample at a time */
+ py = py + 1U;
+
+ while (blockSize3 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt; /* loop counter */
+ q15_t a, b;
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1U;
+ blockSize2 = srcALen - (srcBLen - 1U);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1U;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations less than 4 */
+ /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ while ((count < 4U) && (blockSize1 > 0U))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over number of MAC operations between
+ * inputA samples and inputB samples */
+ k = count;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* The second part of the stage starts here */
+ /* The internal loop, over count, is unrolled by 4 */
+ /* To, read the last two inputB samples using SIMD:
+ * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+ py = py - 1;
+
+ while (blockSize1 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ py++;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + (count - 1U);
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* count is the index by which the pointer pIn1 to be incremented */
+ count = 0U;
+
+
+ /* --------------------
+ * Stage2 process
+ * -------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if (srcBLen >= 4U)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ py = py - 1U;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1] samples */
+ a = *px++;
+ b = *px++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x0 = __PKHBT(a, b, 16);
+ a = *px;
+ x1 = __PKHBT(b, a, 16);
+
+#else
+
+ x0 = __PKHBT(b, a, 16);
+ a = *px;
+ x1 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the last two inputB samples using SIMD:
+ * y[srcBLen - 1] and y[srcBLen - 2] */
+ a = *py;
+ b = *(py+1);
+ py -= 2;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLADX(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLADX(x1, c0, acc1);
+
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x2 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x3 = __PKHBT(b, a, 16);
+
+#else
+
+ x2 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x3 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLADX(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLADX(x3, c0, acc3);
+
+ /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+ a = *py;
+ b = *(py+1);
+ py -= 2;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLADX(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLADX(x3, c0, acc1);
+
+ /* Read x[4], x[5], x[6] */
+ a = *(px + 2);
+ b = *(px + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x0 = __PKHBT(a, b, 16);
+ a = *(px + 4);
+ x1 = __PKHBT(b, a, 16);
+
+#else
+
+ x0 = __PKHBT(b, a, 16);
+ a = *(px + 4);
+ x1 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px += 4U;
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLADX(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLADX(x1, c0, acc3);
+
+ } while (--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ if (k == 1U)
+ {
+ /* Read y[srcBLen - 5] */
+ c0 = *(py+1);
+
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16U;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7] */
+ a = *px;
+ b = *(px+1);
+ px++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLADX(x1, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ if (k == 2U)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ a = *py;
+ b = *(py+1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7], x[8], x[9] */
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(b, a, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+ px += 2U;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+ }
+
+ if (k == 3U)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ a = *py;
+ b = *(py+1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7], x[8], x[9] */
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(b, a, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+
+ /* Read y[srcBLen - 7] */
+ c0 = *(py-1);
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16U;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[10] */
+ a = *(px+2);
+ b = *(px+3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px += 3U;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x1, c0, acc0);
+ acc1 = __SMLAD(x2, c0, acc1);
+ acc2 = __SMLADX(x2, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ /* Store the results in the accumulators in the destination buffer. */
+ *pOut++ = (q15_t)(acc0 >> 15);
+ *pOut++ = (q15_t)(acc1 >> 15);
+ *pOut++ = (q15_t)(acc2 >> 15);
+ *pOut++ = (q15_t)(acc3 >> 15);
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4U;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ pIn2 = pSrc2 - 1U;
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations greater than 4 */
+ /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ j = blockSize3 >> 2U;
+
+ while ((j > 0U) && (blockSize3 > 0U))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3 >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ py++;
+
+ while (k > 0U)
+ {
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = blockSize3 % 0x4U;
+
+ while (k > 0U)
+ {
+ /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ j--;
+ }
+
+ /* The second part of the stage starts here */
+ /* SIMD is not used for the next MAC operations,
+ * so pointer py is updated to read only one sample at a time */
+ py = py + 1U;
+
+ while (blockSize3 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q31.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q31.c
new file mode 100644
index 0000000..bc57221
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q31.c
@@ -0,0 +1,565 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_conv_fast_q31.c
+ * Description: Fast Q31 Convolution
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.
+ * These intermediate results are accumulated in a 32-bit register in 2.30 format.
+ * Finally, the accumulator is saturated and converted to a 1.31 result.
+ *
+ * \par
+ * The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result.
+ * In order to avoid overflows completely the input signals must be scaled down.
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.
+ *
+ * \par
+ * See <code>arm_conv_q31()</code> for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.
+ */
+
+void arm_conv_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst)
+{
+ q31_t *pIn1; /* inputA pointer */
+ q31_t *pIn2; /* inputB pointer */
+ q31_t *pOut = pDst; /* output pointer */
+ q31_t *px; /* Intermediate inputA pointer */
+ q31_t *py; /* Intermediate inputB pointer */
+ q31_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3; /* loop counter */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1U;
+ blockSize2 = srcALen - (srcBLen - 1U);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1U;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while (blockSize1 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* x[0] * y[srcBLen - 1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* x[1] * y[srcBLen - 2] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* x[2] * y[srcBLen - 3] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* x[3] * y[srcBLen - 4] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0U;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if (srcBLen >= 4U)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *(py--);
+
+ /* Read x[3] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[0] * y[srcBLen - 1] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* acc1 += x[1] * y[srcBLen - 1] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* acc2 += x[2] * y[srcBLen - 1] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+ /* acc3 += x[3] * y[srcBLen - 1] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+ /* Read y[srcBLen - 2] sample */
+ c0 = *(py--);
+
+ /* Read x[4] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[1] * y[srcBLen - 2] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc1 += x[2] * y[srcBLen - 2] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc2 += x[3] * y[srcBLen - 2] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc3 += x[4] * y[srcBLen - 2] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *(py--);
+
+ /* Read x[5] sample */
+ x1 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[srcBLen - 3] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc1 += x[3] * y[srcBLen - 3] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc2 += x[4] * y[srcBLen - 3] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc3 += x[5] * y[srcBLen - 3] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* Read y[srcBLen - 4] sample */
+ c0 = *(py--);
+
+ /* Read x[6] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[3] * y[srcBLen - 4] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc1 += x[4] * y[srcBLen - 4] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc2 += x[5] * y[srcBLen - 4] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc3 += x[6] * y[srcBLen - 4] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+
+ } while (--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *(py--);
+
+ /* Read x[7] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc3 += x[7] * y[srcBLen - 5] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the results in the accumulators in the destination buffer. */
+ *pOut++ = (q31_t) (acc0 << 1);
+ *pOut++ = (q31_t) (acc1 << 1);
+ *pOut++ = (q31_t) (acc2 << 1);
+ *pOut++ = (q31_t) (acc3 << 1);
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4U;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while (blockSize3 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3 >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = blockSize3 % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q15.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q15.c
new file mode 100644
index 0000000..47f6f84
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q15.c
@@ -0,0 +1,533 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_conv_opt_q15.c
+ * Description: Convolution of Q15 sequences
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return none.
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
+ *
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both inputs are in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * This approach provides 33 guard bits and there is no risk of overflow.
+ * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.
+ *
+ *
+ * \par
+ * Refer to <code>arm_conv_fast_q15()</code> for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
+ *
+ *
+ */
+
+void arm_conv_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+ q63_t acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t x1, x2, x3; /* Temporary variables to hold state and coefficient values */
+ q31_t y1, y2; /* State variables */
+ q15_t *pOut = pDst; /* output pointer */
+ q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
+ q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ uint32_t j, k, blkCnt; /* loop counter */
+ uint32_t tapCnt; /* loop count */
+#ifdef UNALIGNED_SUPPORT_DISABLE
+
+ q15_t a, b;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2 + srcBLen - 1;
+
+ /* points to smaller length sequence */
+ px = pIn2;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ /* Copy smaller length input sequence in reverse order into second scratch buffer */
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Assuming scratch1 buffer is aligned by 32-bit */
+ /* Fill (srcBLen - 1U) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1U);
+
+ /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Copy (srcALen) samples in scratch buffer */
+ arm_copy_q15(pIn1, pScr1, srcALen);
+
+ /* Update pointers */
+ pScr1 += srcALen;
+
+#else
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcALen >> 2U;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcALen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+#endif
+
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Fill (srcBLen - 1U) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1U);
+
+#else
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = (srcBLen - 1U) >> 2U;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = (srcBLen - 1U) % 0x4U;
+
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+#endif
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = py;
+
+ /* First part of the processing with loop unrolling process 4 data points at a time.
+ ** a second loop below process for the remaining 1 to 3 samples. */
+
+ /* Actual convolution process starts here */
+ blkCnt = (srcALen + srcBLen - 1U) >> 2;
+
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr1)++;
+
+ tapCnt = (srcBLen) >> 2U;
+
+ while (tapCnt > 0U)
+ {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pIn2);
+ y2 = _SIMD32_OFFSET(pIn2 + 2U);
+
+ /* multiply and accumlate */
+ acc0 = __SMLALD(x1, y1, acc0);
+ acc2 = __SMLALD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLALDX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = _SIMD32_OFFSET(pScr1);
+
+ /* multiply and accumlate */
+ acc0 = __SMLALD(x2, y2, acc0);
+ acc2 = __SMLALD(x1, y2, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y1, acc3);
+ acc1 = __SMLALDX(x3, y2, acc1);
+
+ x2 = _SIMD32_OFFSET(pScr1 + 2U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y2, acc3);
+
+#else
+
+ /* Read four samples from smaller buffer */
+ a = *pIn2;
+ b = *(pIn2 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ y1 = __PKHBT(a, b, 16);
+#else
+ y1 = __PKHBT(b, a, 16);
+#endif
+
+ a = *(pIn2 + 2);
+ b = *(pIn2 + 3);
+#ifndef ARM_MATH_BIG_ENDIAN
+ y2 = __PKHBT(a, b, 16);
+#else
+ y2 = __PKHBT(b, a, 16);
+#endif
+
+ acc0 = __SMLALD(x1, y1, acc0);
+
+ acc2 = __SMLALD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc1 = __SMLALDX(x3, y1, acc1);
+
+ a = *pScr1;
+ b = *(pScr1 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(a, b, 16);
+#else
+ x1 = __PKHBT(b, a, 16);
+#endif
+
+ acc0 = __SMLALD(x2, y2, acc0);
+
+ acc2 = __SMLALD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y1, acc3);
+
+ acc1 = __SMLALDX(x3, y2, acc1);
+
+ a = *(pScr1 + 2);
+ b = *(pScr1 + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x2 = __PKHBT(a, b, 16);
+#else
+ x2 = __PKHBT(b, a, 16);
+#endif
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y2, acc3);
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ pIn2 += 4U;
+ pScr1 += 4U;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3U;
+
+ while (tapCnt > 0U)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2);
+ acc1 += (*pScr1++ * *pIn2);
+ acc2 += (*pScr1++ * *pIn2);
+ acc3 += (*pScr1++ * *pIn2++);
+
+ pScr1 -= 3U;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 4U;
+
+ }
+
+
+ blkCnt = (srcALen + srcBLen - 1U) & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1U;
+
+ while (tapCnt > 0U)
+ {
+
+ /* Read next two samples from scratch1 buffer */
+ acc0 += (*pScr1++ * *pIn2++);
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while (tapCnt > 0U)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* The result is in 2.30 format. Convert to 1.15 with saturation.
+ ** Then store the output in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 1U;
+
+ }
+
+}
+
+
+/**
+ * @} end of Conv group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q7.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q7.c
new file mode 100644
index 0000000..1dc2e49
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q7.c
@@ -0,0 +1,423 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_conv_opt_q7.c
+ * Description: Convolution of Q7 sequences
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return none.
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
+ * This approach provides 17 guard bits and there is no risk of overflow as long as <code>max(srcALen, srcBLen)<131072</code>.
+ * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format.
+ *
+ */
+
+void arm_conv_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+
+ q15_t *pScr2, *pScr1; /* Intermediate pointers for scratch pointers */
+ q15_t x4; /* Temporary input variable */
+ q7_t *pIn1, *pIn2; /* inputA and inputB pointer */
+ uint32_t j, k, blkCnt, tapCnt; /* loop counter */
+ q7_t *px; /* Temporary input1 pointer */
+ q15_t *py; /* Temporary input2 pointer */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t x1, x2, x3, y1; /* Temporary input variables */
+ q7_t *pOut = pDst; /* output pointer */
+ q7_t out0, out1, out2, out3; /* temporary variables */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2;
+
+ /* points to smaller length sequence */
+ px = pIn2 + srcBLen - 1;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Fill (srcBLen - 1U) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1U);
+
+ /* Copy (srcALen) samples in scratch buffer */
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcALen >> 2U;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcALen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Fill (srcBLen - 1U) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1U);
+
+#else
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = (srcBLen - 1U) >> 2U;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = (srcBLen - 1U) % 0x4U;
+
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+#endif
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = (q7_t *) py;
+
+ pScr2 = py;
+
+ /* Actual convolution process starts here */
+ blkCnt = (srcALen + srcBLen - 1U) >> 2;
+
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr1)++;
+
+ tapCnt = (srcBLen) >> 2U;
+
+ while (tapCnt > 0U)
+ {
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pScr2);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x1, y1, acc0);
+ acc2 = __SMLAD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pScr2 + 2U);
+
+ acc0 = __SMLAD(x2, y1, acc0);
+
+ acc2 = __SMLAD(x1, y1, acc2);
+
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ x2 = *__SIMD32(pScr1)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ pScr2 += 4U;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4U;
+
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3U;
+
+ while (tapCnt > 0U)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2);
+ acc1 += (*pScr1++ * *pScr2);
+ acc2 += (*pScr1++ * *pScr2);
+ acc3 += (*pScr1++ * *pScr2++);
+
+ pScr1 -= 3U;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ out0 = (q7_t) (__SSAT(acc0 >> 7U, 8));
+ out1 = (q7_t) (__SSAT(acc1 >> 7U, 8));
+ out2 = (q7_t) (__SSAT(acc2 >> 7U, 8));
+ out3 = (q7_t) (__SSAT(acc3 >> 7U, 8));
+
+ *__SIMD32(pOut)++ = __PACKq7(out0, out1, out2, out3);
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 4U;
+
+ }
+
+
+ blkCnt = (srcALen + srcBLen - 1U) & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1U;
+
+ while (tapCnt > 0U)
+ {
+ acc0 += (*pScr1++ * *pScr2++);
+ acc0 += (*pScr1++ * *pScr2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while (tapCnt > 0U)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(acc0 >> 7U, 8));
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 1U;
+
+ }
+
+}
+
+
+/**
+ * @} end of Conv group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_f32.c
new file mode 100644
index 0000000..9eae124
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_f32.c
@@ -0,0 +1,678 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_conv_partial_f32.c
+ * Description: Partial convolution of floating-point sequences
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup PartialConv Partial Convolution
+ *
+ * Partial Convolution is equivalent to Convolution except that a subset of the output samples is generated.
+ * Each function has two additional arguments.
+ * <code>firstIndex</code> specifies the starting index of the subset of output samples.
+ * <code>numPoints</code> is the number of output samples to compute.
+ * The function computes the output in the range
+ * <code>[firstIndex, ..., firstIndex+numPoints-1]</code>.
+ * The output array <code>pDst</code> contains <code>numPoints</code> values.
+ *
+ * The allowable range of output indices is [0 srcALen+srcBLen-2].
+ * If the requested subset does not fall in this range then the functions return ARM_MATH_ARGUMENT_ERROR.
+ * Otherwise the functions return ARM_MATH_SUCCESS.
+ * \note Refer arm_conv_f32() for details on fixed point behavior.
+ *
+ *
+ * <b>Fast Versions</b>
+ *
+ * \par
+ * Fast versions are supported for Q31 and Q15 of partial convolution. Cycles for Fast versions are less compared to Q31 and Q15 of partial conv and the design requires
+ * the input signals should be scaled down to avoid intermediate overflows.
+ *
+ *
+ * <b>Opt Versions</b>
+ *
+ * \par
+ * Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation.
+ * These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions of partial convolution
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+arm_status arm_conv_partial_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+
+
+#if defined (ARM_MATH_DSP)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float32_t *pIn1 = pSrcA; /* inputA pointer */
+ float32_t *pIn2 = pSrcB; /* inputB pointer */
+ float32_t *pOut = pDst; /* output pointer */
+ float32_t *px; /* Intermediate inputA pointer */
+ float32_t *py; /* Intermediate inputB pointer */
+ float32_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ float32_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ float32_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t j, k, count = 0U, blkCnt, check;
+ int32_t blockSize1, blockSize2, blockSize3; /* loop counters */
+ arm_status status; /* status of Partial convolution */
+
+
+ /* Check for range of output samples to be calculated */
+ if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+ blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+ blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex;
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 :
+ (int32_t) numPoints) : 0;
+ blockSize2 = ((int32_t) check - blockSize3) -
+ (blockSize1 + (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1U + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc1 = pIn2 + firstIndex;
+ py = pSrc1;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while (blockSize1 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* x[0] * y[srcBLen - 1] */
+ sum += *px++ * *py--;
+
+ /* x[1] * y[srcBLen - 2] */
+ sum += *px++ * *py--;
+
+ /* x[2] * y[srcBLen - 3] */
+ sum += *px++ * *py--;
+
+ /* x[3] * y[srcBLen - 4] */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc1;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ px = pIn1 + firstIndex - srcBLen + 1;
+ }
+ else
+ {
+ px = pIn1;
+ }
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0U;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if (srcBLen >= 4U)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = ((uint32_t) blockSize2 >> 2U);
+
+ while (blkCnt > 0U)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0.0f;
+ acc1 = 0.0f;
+ acc2 = 0.0f;
+ acc3 = 0.0f;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *(py--);
+
+ /* Read x[3] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[0] * y[srcBLen - 1] */
+ acc0 += x0 * c0;
+
+ /* acc1 += x[1] * y[srcBLen - 1] */
+ acc1 += x1 * c0;
+
+ /* acc2 += x[2] * y[srcBLen - 1] */
+ acc2 += x2 * c0;
+
+ /* acc3 += x[3] * y[srcBLen - 1] */
+ acc3 += x3 * c0;
+
+ /* Read y[srcBLen - 2] sample */
+ c0 = *(py--);
+
+ /* Read x[4] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[1] * y[srcBLen - 2] */
+ acc0 += x1 * c0;
+ /* acc1 += x[2] * y[srcBLen - 2] */
+ acc1 += x2 * c0;
+ /* acc2 += x[3] * y[srcBLen - 2] */
+ acc2 += x3 * c0;
+ /* acc3 += x[4] * y[srcBLen - 2] */
+ acc3 += x0 * c0;
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *(py--);
+
+ /* Read x[5] sample */
+ x1 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[srcBLen - 3] */
+ acc0 += x2 * c0;
+ /* acc1 += x[3] * y[srcBLen - 2] */
+ acc1 += x3 * c0;
+ /* acc2 += x[4] * y[srcBLen - 2] */
+ acc2 += x0 * c0;
+ /* acc3 += x[5] * y[srcBLen - 2] */
+ acc3 += x1 * c0;
+
+ /* Read y[srcBLen - 4] sample */
+ c0 = *(py--);
+
+ /* Read x[6] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[3] * y[srcBLen - 4] */
+ acc0 += x3 * c0;
+ /* acc1 += x[4] * y[srcBLen - 4] */
+ acc1 += x0 * c0;
+ /* acc2 += x[5] * y[srcBLen - 4] */
+ acc2 += x1 * c0;
+ /* acc3 += x[6] * y[srcBLen - 4] */
+ acc3 += x2 * c0;
+
+
+ } while (--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *(py--);
+
+ /* Read x[7] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 += x0 * c0;
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 += x1 * c0;
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 += x2 * c0;
+ /* acc3 += x[7] * y[srcBLen - 5] */
+ acc3 += x3 * c0;
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = acc0;
+ *pOut++ = acc1;
+ *pOut++ = acc2;
+ *pOut++ = acc3;
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count += 4U;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ px = pIn1 + firstIndex - srcBLen + 1 + count;
+ }
+ else
+ {
+ px = pIn1 + count;
+ }
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = (uint32_t) blockSize2 % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += *px++ * *py--;
+ sum += *px++ * *py--;
+ sum += *px++ * *py--;
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ px = pIn1 + firstIndex - srcBLen + 1 + count;
+ }
+ else
+ {
+ px = pIn1 + count;
+ }
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ px = pIn1 + firstIndex - srcBLen + 1 + count;
+ }
+ else
+ {
+ px = pIn1 + count;
+ }
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1U;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ while (blockSize3 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ sum += *px++ * *py--;
+
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum += *px++ * *py--;
+
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ sum += *px++ * *py--;
+
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ float32_t *pIn1 = pSrcA; /* inputA pointer */
+ float32_t *pIn2 = pSrcB; /* inputB pointer */
+ float32_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counters */
+ arm_status status; /* status of Partial convolution */
+
+ /* Check for range of output samples to be calculated */
+ if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+ {
+ /* Set status as ARM_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+ /* Loop to calculate convolution for output length number of values */
+ for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0.0f;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0U; j <= i; j++)
+ {
+ /* Check the array limitations for inputs */
+ if ((((i - j) < srcBLen) && (j < srcALen)))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += pIn1[j] * pIn2[i - j];
+ }
+ }
+ /* Store the output in the destination buffer */
+ pDst[i] = sum;
+ }
+ /* set status as ARM_SUCCESS as there are no argument errors */
+ status = ARM_MATH_SUCCESS;
+ }
+ return (status);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c
new file mode 100644
index 0000000..f469d1f
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c
@@ -0,0 +1,756 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_conv_partial_fast_opt_q15.c
+ * Description: Fast Q15 Partial convolution
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * See <code>arm_conv_partial_q15()</code> for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
+ *
+ */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+arm_status arm_conv_partial_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+
+ q15_t *pOut = pDst; /* output pointer */
+ q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
+ q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t x1, x2, x3; /* Temporary variables to hold state and coefficient values */
+ q31_t y1, y2; /* State variables */
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ uint32_t j, k, blkCnt; /* loop counter */
+ arm_status status;
+
+ uint32_t tapCnt; /* loop count */
+
+ /* Check for range of output samples to be calculated */
+ if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2 + srcBLen - 1;
+
+ /* points to smaller length sequence */
+ px = pIn2;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+
+ /* Copy smaller length input sequence in reverse order into second scratch buffer */
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Assuming scratch1 buffer is aligned by 32-bit */
+ /* Fill (srcBLen - 1U) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1U);
+
+ /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+ /* Copy (srcALen) samples in scratch buffer */
+ arm_copy_q15(pIn1, pScr1, srcALen);
+
+ /* Update pointers */
+ pScr1 += srcALen;
+
+ /* Fill (srcBLen - 1U) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1U);
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = py;
+
+ pScratch1 += firstIndex;
+
+ pOut = pDst + firstIndex;
+
+ /* First part of the processing with loop unrolling process 4 data points at a time.
+ ** a second loop below process for the remaining 1 to 3 samples. */
+
+ /* Actual convolution process starts here */
+ blkCnt = (numPoints) >> 2;
+
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr1)++;
+
+ tapCnt = (srcBLen) >> 2U;
+
+ while (tapCnt > 0U)
+ {
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pIn2);
+ y2 = _SIMD32_OFFSET(pIn2 + 2U);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x1, y1, acc0);
+ acc2 = __SMLAD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = _SIMD32_OFFSET(pScr1);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x2, y2, acc0);
+
+ acc2 = __SMLAD(x1, y2, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+ acc1 = __SMLADX(x3, y2, acc1);
+
+ x2 = _SIMD32_OFFSET(pScr1 + 2U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y2, acc3);
+
+ /* update scratch pointers */
+ pIn2 += 4U;
+ pScr1 += 4U;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3U;
+
+ while (tapCnt > 0U)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2);
+ acc1 += (*pScr1++ * *pIn2);
+ acc2 += (*pScr1++ * *pIn2);
+ acc3 += (*pScr1++ * *pIn2++);
+
+ pScr1 -= 3U;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 4U;
+
+ }
+
+
+ blkCnt = numPoints & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1U;
+
+ while (tapCnt > 0U)
+ {
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read two samples from smaller buffer */
+ y1 = *__SIMD32(pIn2)++;
+
+ acc0 = __SMLAD(x1, y1, acc0);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while (tapCnt > 0U)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* The result is in 2.30 format. Convert to 1.15 with saturation.
+ ** Then store the output in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 1U;
+
+ }
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+ /* Return to application */
+ return (status);
+}
+
+#else
+
+arm_status arm_conv_partial_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+
+ q15_t *pOut = pDst; /* output pointer */
+ q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
+ q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulator */
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ uint32_t j, k, blkCnt; /* loop counter */
+ arm_status status; /* Status variable */
+ uint32_t tapCnt; /* loop count */
+ q15_t x10, x11, x20, x21; /* Temporary variables to hold srcA buffer */
+ q15_t y10, y11; /* Temporary variables to hold srcB buffer */
+
+
+ /* Check for range of output samples to be calculated */
+ if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2 + srcBLen - 1;
+
+ /* points to smaller length sequence */
+ px = pIn2;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Fill (srcBLen - 1U) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1U);
+
+ /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcALen >> 2U;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcALen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = (srcBLen - 1U) >> 2U;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = (srcBLen - 1U) % 0x4U;
+
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = py;
+
+ pScratch1 += firstIndex;
+
+ pOut = pDst + firstIndex;
+
+ /* Actual convolution process starts here */
+ blkCnt = (numPoints) >> 2;
+
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x10 = *pScr1++;
+ x11 = *pScr1++;
+
+ /* Read next two samples from scratch1 buffer */
+ x20 = *pScr1++;
+ x21 = *pScr1++;
+
+ tapCnt = (srcBLen) >> 2U;
+
+ while (tapCnt > 0U)
+ {
+
+ /* Read two samples from smaller buffer */
+ y10 = *pIn2;
+ y11 = *(pIn2 + 1U);
+
+ /* multiply and accumlate */
+ acc0 += (q31_t) x10 *y10;
+ acc0 += (q31_t) x11 *y11;
+ acc2 += (q31_t) x20 *y10;
+ acc2 += (q31_t) x21 *y11;
+
+ /* multiply and accumlate */
+ acc1 += (q31_t) x11 *y10;
+ acc1 += (q31_t) x20 *y11;
+
+ /* Read next two samples from scratch1 buffer */
+ x10 = *pScr1;
+ x11 = *(pScr1 + 1U);
+
+ /* multiply and accumlate */
+ acc3 += (q31_t) x21 *y10;
+ acc3 += (q31_t) x10 *y11;
+
+ /* Read next two samples from scratch2 buffer */
+ y10 = *(pIn2 + 2U);
+ y11 = *(pIn2 + 3U);
+
+ /* multiply and accumlate */
+ acc0 += (q31_t) x20 *y10;
+ acc0 += (q31_t) x21 *y11;
+ acc2 += (q31_t) x10 *y10;
+ acc2 += (q31_t) x11 *y11;
+ acc1 += (q31_t) x21 *y10;
+ acc1 += (q31_t) x10 *y11;
+
+ /* Read next two samples from scratch1 buffer */
+ x20 = *(pScr1 + 2);
+ x21 = *(pScr1 + 3);
+
+ /* multiply and accumlate */
+ acc3 += (q31_t) x11 *y10;
+ acc3 += (q31_t) x20 *y11;
+
+ /* update scratch pointers */
+ pIn2 += 4U;
+ pScr1 += 4U;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3U;
+
+ while (tapCnt > 0U)
+ {
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2);
+ acc1 += (*pScr1++ * *pIn2);
+ acc2 += (*pScr1++ * *pIn2);
+ acc3 += (*pScr1++ * *pIn2++);
+
+ pScr1 -= 3U;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+ *pOut++ = __SSAT((acc0 >> 15), 16);
+ *pOut++ = __SSAT((acc1 >> 15), 16);
+ *pOut++ = __SSAT((acc2 >> 15), 16);
+ *pOut++ = __SSAT((acc3 >> 15), 16);
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 4U;
+
+ }
+
+
+ blkCnt = numPoints & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1U;
+
+ while (tapCnt > 0U)
+ {
+
+ /* Read next two samples from scratch1 buffer */
+ x10 = *pScr1++;
+ x11 = *pScr1++;
+
+ /* Read two samples from smaller buffer */
+ y10 = *pIn2++;
+ y11 = *pIn2++;
+
+ /* multiply and accumlate */
+ acc0 += (q31_t) x10 *y10;
+ acc0 += (q31_t) x11 *y11;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while (tapCnt > 0U)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 1U;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q15.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q15.c
new file mode 100644
index 0000000..0d4486a
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q15.c
@@ -0,0 +1,1494 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_conv_partial_fast_q15.c
+ * Description: Fast Q15 Partial convolution
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * See <code>arm_conv_partial_q15()</code> for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.
+ */
+
+
+arm_status arm_conv_partial_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0;
+ uint32_t j, k, count, check, blkCnt;
+ int32_t blockSize1, blockSize2, blockSize3; /* loop counters */
+ arm_status status; /* status of Partial convolution */
+
+ /* Check for range of output samples to be calculated */
+ if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >=srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+ blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+ blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 :
+ (int32_t) numPoints) : 0;
+ blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+ (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1U + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + firstIndex;
+ py = pSrc2;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations less than 4 */
+ /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ while ((count < 4U) && (blockSize1 > 0))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over number of MAC operations between
+ * inputA samples and inputB samples */
+ k = count;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* The second part of the stage starts here */
+ /* The internal loop, over count, is unrolled by 4 */
+ /* To, read the last two inputB samples using SIMD:
+ * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+ py = py - 1;
+
+ while (blockSize1 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+ /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1U;
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2 - 1U;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ px = pIn1 + firstIndex - srcBLen + 1;
+ }
+ else
+ {
+ px = pIn1;
+ }
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* count is the index by which the pointer pIn1 to be incremented */
+ count = 0U;
+
+
+ /* --------------------
+ * Stage2 process
+ * -------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if (srcBLen >= 4U)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = ((uint32_t) blockSize2 >> 2U);
+
+ while (blkCnt > 0U)
+ {
+ py = py - 1U;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+
+ /* read x[0], x[1] samples */
+ x0 = *__SIMD32(px);
+ /* read x[1], x[2] samples */
+ x1 = _SIMD32_OFFSET(px+1);
+ px+= 2U;
+
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the last two inputB samples using SIMD:
+ * y[srcBLen - 1] and y[srcBLen - 2] */
+ c0 = *__SIMD32(py)--;
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLADX(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLADX(x1, c0, acc1);
+
+ /* Read x[2], x[3] */
+ x2 = *__SIMD32(px);
+
+ /* Read x[3], x[4] */
+ x3 = _SIMD32_OFFSET(px+1);
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLADX(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLADX(x3, c0, acc3);
+
+ /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+ c0 = *__SIMD32(py)--;
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLADX(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLADX(x3, c0, acc1);
+
+ /* Read x[4], x[5] */
+ x0 = _SIMD32_OFFSET(px+2);
+
+ /* Read x[5], x[6] */
+ x1 = _SIMD32_OFFSET(px+3);
+ px += 4U;
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLADX(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLADX(x1, c0, acc3);
+
+ } while (--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ if (k == 1U)
+ {
+ /* Read y[srcBLen - 5] */
+ c0 = *(py+1);
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16U;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7] */
+ x3 = *__SIMD32(px);
+ px++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLADX(x1, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ if (k == 2U)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = _SIMD32_OFFSET(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px+1);
+ px += 2U;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+ }
+
+ if (k == 3U)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = _SIMD32_OFFSET(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px+1);
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+
+ c0 = *(py-1);
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16U;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[10] */
+ x3 = _SIMD32_OFFSET(px+2);
+ px += 3U;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x1, c0, acc0);
+ acc1 = __SMLAD(x2, c0, acc1);
+ acc2 = __SMLADX(x2, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ /* Store the results in the accumulators in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ = __PKHBT(acc0 >> 15, acc1 >> 15, 16);
+ *__SIMD32(pOut)++ = __PKHBT(acc2 >> 15, acc3 >> 15, 16);
+
+#else
+
+ *__SIMD32(pOut)++ = __PKHBT(acc1 >> 15, acc0 >> 15, 16);
+ *__SIMD32(pOut)++ = __PKHBT(acc3 >> 15, acc2 >> 15, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4U;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = (uint32_t) blockSize2 % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ px = pIn1 + firstIndex - srcBLen + 1 + count;
+ }
+ else
+ {
+ px = pIn1 + count;
+ }
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ px = pIn1 + firstIndex - srcBLen + 1 + count;
+ }
+ else
+ {
+ px = pIn1 + count;
+ }
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1U;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ pIn2 = pSrc2 - 1U;
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations greater than 4 */
+ /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ j = count >> 2U;
+
+ while ((j > 0U) && (blockSize3 > 0))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied
+ * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+ /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied
+ * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1U;
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ j--;
+ }
+
+ /* The second part of the stage starts here */
+ /* SIMD is not used for the next MAC operations,
+ * so pointer py is updated to read only one sample at a time */
+ py = py + 1U;
+
+ while (blockSize3 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+#else
+
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0;
+ uint32_t j, k, count, check, blkCnt;
+ int32_t blockSize1, blockSize2, blockSize3; /* loop counters */
+ arm_status status; /* status of Partial convolution */
+ q15_t a, b;
+
+ /* Check for range of output samples to be calculated */
+ if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >=srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+ blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+ blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex;
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 :
+ (int32_t) numPoints) : 0;
+ blockSize2 = ((int32_t) check - blockSize3) -
+ (blockSize1 + (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1U + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + firstIndex;
+ py = pSrc2;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations less than 4 */
+ /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ while ((count < 4U) && (blockSize1 > 0))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over number of MAC operations between
+ * inputA samples and inputB samples */
+ k = count;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* The second part of the stage starts here */
+ /* The internal loop, over count, is unrolled by 4 */
+ /* To, read the last two inputB samples using SIMD:
+ * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+ py = py - 1;
+
+ while (blockSize1 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ py++;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2 - 1U;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ px = pIn1 + firstIndex - srcBLen + 1;
+ }
+ else
+ {
+ px = pIn1;
+ }
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* count is the index by which the pointer pIn1 to be incremented */
+ count = 0U;
+
+
+ /* --------------------
+ * Stage2 process
+ * -------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if (srcBLen >= 4U)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = ((uint32_t) blockSize2 >> 2U);
+
+ while (blkCnt > 0U)
+ {
+ py = py - 1U;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1] samples */
+ a = *px++;
+ b = *px++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x0 = __PKHBT(a, b, 16);
+ a = *px;
+ x1 = __PKHBT(b, a, 16);
+
+#else
+
+ x0 = __PKHBT(b, a, 16);
+ a = *px;
+ x1 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the last two inputB samples using SIMD:
+ * y[srcBLen - 1] and y[srcBLen - 2] */
+ a = *py;
+ b = *(py+1);
+ py -= 2;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLADX(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLADX(x1, c0, acc1);
+
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x2 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x3 = __PKHBT(b, a, 16);
+
+#else
+
+ x2 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x3 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLADX(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLADX(x3, c0, acc3);
+
+ /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+ a = *py;
+ b = *(py+1);
+ py -= 2;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLADX(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLADX(x3, c0, acc1);
+
+ /* Read x[4], x[5], x[6] */
+ a = *(px + 2);
+ b = *(px + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x0 = __PKHBT(a, b, 16);
+ a = *(px + 4);
+ x1 = __PKHBT(b, a, 16);
+
+#else
+
+ x0 = __PKHBT(b, a, 16);
+ a = *(px + 4);
+ x1 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px += 4U;
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLADX(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLADX(x1, c0, acc3);
+
+ } while (--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ if (k == 1U)
+ {
+ /* Read y[srcBLen - 5] */
+ c0 = *(py+1);
+
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16U;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7] */
+ a = *px;
+ b = *(px+1);
+ px++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLADX(x1, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ if (k == 2U)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ a = *py;
+ b = *(py+1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7], x[8], x[9] */
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(b, a, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+ px += 2U;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+ }
+
+ if (k == 3U)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ a = *py;
+ b = *(py+1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7], x[8], x[9] */
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(b, a, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+
+ /* Read y[srcBLen - 7] */
+ c0 = *(py-1);
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16U;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[10] */
+ a = *(px+2);
+ b = *(px+3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px += 3U;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x1, c0, acc0);
+ acc1 = __SMLAD(x2, c0, acc1);
+ acc2 = __SMLADX(x2, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ /* Store the results in the accumulators in the destination buffer. */
+ *pOut++ = (q15_t)(acc0 >> 15);
+ *pOut++ = (q15_t)(acc1 >> 15);
+ *pOut++ = (q15_t)(acc2 >> 15);
+ *pOut++ = (q15_t)(acc3 >> 15);
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4U;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = (uint32_t) blockSize2 % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1U;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ pIn2 = pSrc2 - 1U;
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations greater than 4 */
+ /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ j = count >> 2U;
+
+ while ((j > 0U) && (blockSize3 > 0))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ py++;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ /* Decrement the loop counter */
+ k--;
+ }
+
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ j--;
+ }
+
+ /* The second part of the stage starts here */
+ /* SIMD is not used for the next MAC operations,
+ * so pointer py is updated to read only one sample at a time */
+ py = py + 1U;
+
+ while (blockSize3 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+}
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q31.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q31.c
new file mode 100644
index 0000000..e845947
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q31.c
@@ -0,0 +1,620 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_conv_partial_fast_q31.c
+ * Description: Fast Q31 Partial convolution
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * \par
+ * See <code>arm_conv_partial_q31()</code> for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.
+ */
+
+arm_status arm_conv_partial_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+ q31_t *pIn1; /* inputA pointer */
+ q31_t *pIn2; /* inputB pointer */
+ q31_t *pOut = pDst; /* output pointer */
+ q31_t *px; /* Intermediate inputA pointer */
+ q31_t *py; /* Intermediate inputB pointer */
+ q31_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
+ q31_t x0, x1, x2, x3, c0;
+ uint32_t j, k, count, check, blkCnt;
+ int32_t blockSize1, blockSize2, blockSize3; /* loop counters */
+ arm_status status; /* status of Partial convolution */
+
+
+ /* Check for range of output samples to be calculated */
+ if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+ blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+ blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 :
+ (int32_t) numPoints) : 0;
+ blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+ (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1U + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + firstIndex;
+ py = pSrc2;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first loop starts here */
+ while (blockSize1 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* x[0] * y[srcBLen - 1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* x[1] * y[srcBLen - 2] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* x[2] * y[srcBLen - 3] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* x[3] * y[srcBLen - 4] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ px = pIn1 + firstIndex - srcBLen + 1;
+ }
+ else
+ {
+ px = pIn1;
+ }
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0U;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if (srcBLen >= 4U)
+ {
+ /* Loop unroll over blockSize2 */
+ blkCnt = ((uint32_t) blockSize2 >> 2U);
+
+ while (blkCnt > 0U)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *(py--);
+
+ /* Read x[3] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[0] * y[srcBLen - 1] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* acc1 += x[1] * y[srcBLen - 1] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* acc2 += x[2] * y[srcBLen - 1] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+ /* acc3 += x[3] * y[srcBLen - 1] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+ /* Read y[srcBLen - 2] sample */
+ c0 = *(py--);
+
+ /* Read x[4] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[1] * y[srcBLen - 2] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc1 += x[2] * y[srcBLen - 2] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc2 += x[3] * y[srcBLen - 2] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc3 += x[4] * y[srcBLen - 2] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *(py--);
+
+ /* Read x[5] sample */
+ x1 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[srcBLen - 3] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc1 += x[3] * y[srcBLen - 2] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc2 += x[4] * y[srcBLen - 2] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc3 += x[5] * y[srcBLen - 2] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* Read y[srcBLen - 4] sample */
+ c0 = *(py--);
+
+ /* Read x[6] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[3] * y[srcBLen - 4] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc1 += x[4] * y[srcBLen - 4] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc2 += x[5] * y[srcBLen - 4] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc3 += x[6] * y[srcBLen - 4] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+
+ } while (--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *(py--);
+
+ /* Read x[7] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc3 += x[7] * y[srcBLen - 5] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (acc0 << 1);
+ *pOut++ = (q31_t) (acc1 << 1);
+ *pOut++ = (q31_t) (acc2 << 1);
+ *pOut++ = (q31_t) (acc3 << 1);
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4U;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ px = pIn1 + firstIndex - srcBLen + 1 + count;
+ }
+ else
+ {
+ px = pIn1 + count;
+ }
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = (uint32_t) blockSize2 % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ px = pIn1 + firstIndex - srcBLen + 1 + count;
+ }
+ else
+ {
+ px = pIn1 + count;
+ }
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ px = pIn1 + firstIndex - srcBLen + 1 + count;
+ }
+ else
+ {
+ px = pIn1 + count;
+ }
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1U;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while (blockSize3 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+}
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q15.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q15.c
new file mode 100644
index 0000000..78dd548
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q15.c
@@ -0,0 +1,753 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_conv_partial_opt_q15.c
+ * Description: Partial convolution of Q15 sequences
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, state buffers should be aligned by 32-bit
+ *
+ * Refer to <code>arm_conv_partial_fast_q15()</code> for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
+ *
+ *
+ */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+arm_status arm_conv_partial_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+
+ q15_t *pOut = pDst; /* output pointer */
+ q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
+ q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
+ q63_t acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t x1, x2, x3; /* Temporary variables to hold state and coefficient values */
+ q31_t y1, y2; /* State variables */
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ uint32_t j, k, blkCnt; /* loop counter */
+ arm_status status; /* Status variable */
+ uint32_t tapCnt; /* loop count */
+
+ /* Check for range of output samples to be calculated */
+ if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2 + srcBLen - 1;
+
+ /* points to smaller length sequence */
+ px = pIn2;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Fill (srcBLen - 1U) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1U);
+
+ /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+ /* Copy (srcALen) samples in scratch buffer */
+ arm_copy_q15(pIn1, pScr1, srcALen);
+
+ /* Update pointers */
+ pScr1 += srcALen;
+
+ /* Fill (srcBLen - 1U) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1U);
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = py;
+
+ pScratch1 += firstIndex;
+
+ pOut = pDst + firstIndex;
+
+ /* Actual convolution process starts here */
+ blkCnt = (numPoints) >> 2;
+
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr1)++;
+
+ tapCnt = (srcBLen) >> 2U;
+
+ while (tapCnt > 0U)
+ {
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pIn2);
+ y2 = _SIMD32_OFFSET(pIn2 + 2U);
+
+ /* multiply and accumlate */
+ acc0 = __SMLALD(x1, y1, acc0);
+ acc2 = __SMLALD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLALDX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = _SIMD32_OFFSET(pScr1);
+
+ /* multiply and accumlate */
+ acc0 = __SMLALD(x2, y2, acc0);
+ acc2 = __SMLALD(x1, y2, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y1, acc3);
+ acc1 = __SMLALDX(x3, y2, acc1);
+
+ x2 = _SIMD32_OFFSET(pScr1 + 2U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y2, acc3);
+
+ /* update scratch pointers */
+ pIn2 += 4U;
+ pScr1 += 4U;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3U;
+
+ while (tapCnt > 0U)
+ {
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2);
+ acc1 += (*pScr1++ * *pIn2);
+ acc2 += (*pScr1++ * *pIn2);
+ acc3 += (*pScr1++ * *pIn2++);
+
+ pScr1 -= 3U;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 4U;
+
+ }
+
+
+ blkCnt = numPoints & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1U;
+
+ while (tapCnt > 0U)
+ {
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read two samples from smaller buffer */
+ y1 = *__SIMD32(pIn2)++;
+
+ acc0 = __SMLALD(x1, y1, acc0);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while (tapCnt > 0U)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 1U;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+#else
+
+arm_status arm_conv_partial_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+
+ q15_t *pOut = pDst; /* output pointer */
+ q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
+ q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
+ q63_t acc0, acc1, acc2, acc3; /* Accumulator */
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ uint32_t j, k, blkCnt; /* loop counter */
+ arm_status status; /* Status variable */
+ uint32_t tapCnt; /* loop count */
+ q15_t x10, x11, x20, x21; /* Temporary variables to hold srcA buffer */
+ q15_t y10, y11; /* Temporary variables to hold srcB buffer */
+
+
+ /* Check for range of output samples to be calculated */
+ if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2 + srcBLen - 1;
+
+ /* points to smaller length sequence */
+ px = pIn2;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Fill (srcBLen - 1U) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1U);
+
+ /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcALen >> 2U;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcALen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = (srcBLen - 1U) >> 2U;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = (srcBLen - 1U) % 0x4U;
+
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = py;
+
+ pScratch1 += firstIndex;
+
+ pOut = pDst + firstIndex;
+
+ /* Actual convolution process starts here */
+ blkCnt = (numPoints) >> 2;
+
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x10 = *pScr1++;
+ x11 = *pScr1++;
+
+ /* Read next two samples from scratch1 buffer */
+ x20 = *pScr1++;
+ x21 = *pScr1++;
+
+ tapCnt = (srcBLen) >> 2U;
+
+ while (tapCnt > 0U)
+ {
+
+ /* Read two samples from smaller buffer */
+ y10 = *pIn2;
+ y11 = *(pIn2 + 1U);
+
+ /* multiply and accumlate */
+ acc0 += (q63_t) x10 *y10;
+ acc0 += (q63_t) x11 *y11;
+ acc2 += (q63_t) x20 *y10;
+ acc2 += (q63_t) x21 *y11;
+
+ /* multiply and accumlate */
+ acc1 += (q63_t) x11 *y10;
+ acc1 += (q63_t) x20 *y11;
+
+ /* Read next two samples from scratch1 buffer */
+ x10 = *pScr1;
+ x11 = *(pScr1 + 1U);
+
+ /* multiply and accumlate */
+ acc3 += (q63_t) x21 *y10;
+ acc3 += (q63_t) x10 *y11;
+
+ /* Read next two samples from scratch2 buffer */
+ y10 = *(pIn2 + 2U);
+ y11 = *(pIn2 + 3U);
+
+ /* multiply and accumlate */
+ acc0 += (q63_t) x20 *y10;
+ acc0 += (q63_t) x21 *y11;
+ acc2 += (q63_t) x10 *y10;
+ acc2 += (q63_t) x11 *y11;
+ acc1 += (q63_t) x21 *y10;
+ acc1 += (q63_t) x10 *y11;
+
+ /* Read next two samples from scratch1 buffer */
+ x20 = *(pScr1 + 2);
+ x21 = *(pScr1 + 3);
+
+ /* multiply and accumlate */
+ acc3 += (q63_t) x11 *y10;
+ acc3 += (q63_t) x20 *y11;
+
+ /* update scratch pointers */
+ pIn2 += 4U;
+ pScr1 += 4U;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3U;
+
+ while (tapCnt > 0U)
+ {
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2);
+ acc1 += (*pScr1++ * *pIn2);
+ acc2 += (*pScr1++ * *pIn2);
+ acc3 += (*pScr1++ * *pIn2++);
+
+ pScr1 -= 3U;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+ *pOut++ = __SSAT((acc0 >> 15), 16);
+ *pOut++ = __SSAT((acc1 >> 15), 16);
+ *pOut++ = __SSAT((acc2 >> 15), 16);
+ *pOut++ = __SSAT((acc3 >> 15), 16);
+
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 4U;
+
+ }
+
+
+ blkCnt = numPoints & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1U;
+
+ while (tapCnt > 0U)
+ {
+
+ /* Read next two samples from scratch1 buffer */
+ x10 = *pScr1++;
+ x11 = *pScr1++;
+
+ /* Read two samples from smaller buffer */
+ y10 = *pIn2++;
+ y11 = *pIn2++;
+
+ /* multiply and accumlate */
+ acc0 += (q63_t) x10 *y10;
+ acc0 += (q63_t) x11 *y11;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while (tapCnt > 0U)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 1U;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q7.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q7.c
new file mode 100644
index 0000000..351c290
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q7.c
@@ -0,0 +1,791 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_conv_partial_opt_q7.c
+ * Description: Partial convolution of Q7 sequences
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
+ *
+ *
+ *
+ */
+
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+arm_status arm_conv_partial_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+
+ q15_t *pScr2, *pScr1; /* Intermediate pointers for scratch pointers */
+ q15_t x4; /* Temporary input variable */
+ q7_t *pIn1, *pIn2; /* inputA and inputB pointer */
+ uint32_t j, k, blkCnt, tapCnt; /* loop counter */
+ q7_t *px; /* Temporary input1 pointer */
+ q15_t *py; /* Temporary input2 pointer */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t x1, x2, x3, y1; /* Temporary input variables */
+ arm_status status;
+ q7_t *pOut = pDst; /* output pointer */
+ q7_t out0, out1, out2, out3; /* temporary variables */
+
+ /* Check for range of output samples to be calculated */
+ if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2;
+
+ /* points to smaller length sequence */
+ px = pIn2 + srcBLen - 1;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Fill (srcBLen - 1U) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1U);
+
+ /* Copy (srcALen) samples in scratch buffer */
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcALen >> 2U;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcALen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Fill (srcBLen - 1U) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1U);
+
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = (q7_t *) py;
+
+ pScr2 = py;
+
+ pOut = pDst + firstIndex;
+
+ pScratch1 += firstIndex;
+
+ /* Actual convolution process starts here */
+ blkCnt = (numPoints) >> 2;
+
+
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr1)++;
+
+ tapCnt = (srcBLen) >> 2U;
+
+ while (tapCnt > 0U)
+ {
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pScr2);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x1, y1, acc0);
+ acc2 = __SMLAD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pScr2 + 2U);
+
+ acc0 = __SMLAD(x2, y1, acc0);
+
+ acc2 = __SMLAD(x1, y1, acc2);
+
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ x2 = *__SIMD32(pScr1)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ pScr2 += 4U;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4U;
+
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3U;
+
+ while (tapCnt > 0U)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2);
+ acc1 += (*pScr1++ * *pScr2);
+ acc2 += (*pScr1++ * *pScr2);
+ acc3 += (*pScr1++ * *pScr2++);
+
+ pScr1 -= 3U;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ out0 = (q7_t) (__SSAT(acc0 >> 7U, 8));
+ out1 = (q7_t) (__SSAT(acc1 >> 7U, 8));
+ out2 = (q7_t) (__SSAT(acc2 >> 7U, 8));
+ out3 = (q7_t) (__SSAT(acc3 >> 7U, 8));
+
+ *__SIMD32(pOut)++ = __PACKq7(out0, out1, out2, out3);
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 4U;
+
+ }
+
+ blkCnt = (numPoints) & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1U;
+
+ while (tapCnt > 0U)
+ {
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read two samples from smaller buffer */
+ y1 = *__SIMD32(pScr2)++;
+
+ acc0 = __SMLAD(x1, y1, acc0);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while (tapCnt > 0U)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(acc0 >> 7U, 8));
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 1U;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+
+
+ }
+
+ return (status);
+
+}
+
+#else
+
+arm_status arm_conv_partial_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+
+ q15_t *pScr2, *pScr1; /* Intermediate pointers for scratch pointers */
+ q15_t x4; /* Temporary input variable */
+ q7_t *pIn1, *pIn2; /* inputA and inputB pointer */
+ uint32_t j, k, blkCnt, tapCnt; /* loop counter */
+ q7_t *px; /* Temporary input1 pointer */
+ q15_t *py; /* Temporary input2 pointer */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulator */
+ arm_status status;
+ q7_t *pOut = pDst; /* output pointer */
+ q15_t x10, x11, x20, x21; /* Temporary input variables */
+ q15_t y10, y11; /* Temporary input variables */
+
+ /* Check for range of output samples to be calculated */
+ if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2;
+
+ /* points to smaller length sequence */
+ px = pIn2 + srcBLen - 1;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Fill (srcBLen - 1U) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1U);
+
+ /* Copy (srcALen) samples in scratch buffer */
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcALen >> 2U;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcALen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = (srcBLen - 1U) >> 2U;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = (srcBLen - 1U) % 0x4U;
+
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = (q7_t *) py;
+
+ pScr2 = py;
+
+ pOut = pDst + firstIndex;
+
+ pScratch1 += firstIndex;
+
+ /* Actual convolution process starts here */
+ blkCnt = (numPoints) >> 2;
+
+
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x10 = *pScr1++;
+ x11 = *pScr1++;
+
+ /* Read next two samples from scratch1 buffer */
+ x20 = *pScr1++;
+ x21 = *pScr1++;
+
+ tapCnt = (srcBLen) >> 2U;
+
+ while (tapCnt > 0U)
+ {
+
+ /* Read four samples from smaller buffer */
+ y10 = *pScr2;
+ y11 = *(pScr2 + 1U);
+
+ /* multiply and accumlate */
+ acc0 += (q31_t) x10 *y10;
+ acc0 += (q31_t) x11 *y11;
+ acc2 += (q31_t) x20 *y10;
+ acc2 += (q31_t) x21 *y11;
+
+
+ acc1 += (q31_t) x11 *y10;
+ acc1 += (q31_t) x20 *y11;
+
+ /* Read next two samples from scratch1 buffer */
+ x10 = *pScr1;
+ x11 = *(pScr1 + 1U);
+
+ /* multiply and accumlate */
+ acc3 += (q31_t) x21 *y10;
+ acc3 += (q31_t) x10 *y11;
+
+ /* Read next two samples from scratch2 buffer */
+ y10 = *(pScr2 + 2U);
+ y11 = *(pScr2 + 3U);
+
+ /* multiply and accumlate */
+ acc0 += (q31_t) x20 *y10;
+ acc0 += (q31_t) x21 *y11;
+ acc2 += (q31_t) x10 *y10;
+ acc2 += (q31_t) x11 *y11;
+ acc1 += (q31_t) x21 *y10;
+ acc1 += (q31_t) x10 *y11;
+
+ /* Read next two samples from scratch1 buffer */
+ x20 = *(pScr1 + 2);
+ x21 = *(pScr1 + 3);
+
+ /* multiply and accumlate */
+ acc3 += (q31_t) x11 *y10;
+ acc3 += (q31_t) x20 *y11;
+
+ /* update scratch pointers */
+
+ pScr1 += 4U;
+ pScr2 += 4U;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4U;
+
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3U;
+
+ while (tapCnt > 0U)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2);
+ acc1 += (*pScr1++ * *pScr2);
+ acc2 += (*pScr1++ * *pScr2);
+ acc3 += (*pScr1++ * *pScr2++);
+
+ pScr1 -= 3U;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(acc0 >> 7U, 8));
+ *pOut++ = (q7_t) (__SSAT(acc1 >> 7U, 8));
+ *pOut++ = (q7_t) (__SSAT(acc2 >> 7U, 8));
+ *pOut++ = (q7_t) (__SSAT(acc3 >> 7U, 8));
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 4U;
+
+ }
+
+ blkCnt = (numPoints) & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1U;
+
+ while (tapCnt > 0U)
+ {
+
+ /* Read next two samples from scratch1 buffer */
+ x10 = *pScr1++;
+ x11 = *pScr1++;
+
+ /* Read two samples from smaller buffer */
+ y10 = *pScr2++;
+ y11 = *pScr2++;
+
+ /* multiply and accumlate */
+ acc0 += (q31_t) x10 *y10;
+ acc0 += (q31_t) x11 *y11;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while (tapCnt > 0U)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(acc0 >> 7U, 8));
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 1U;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+
+ }
+
+ return (status);
+
+}
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q15.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q15.c
new file mode 100644
index 0000000..43d2b35
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q15.c
@@ -0,0 +1,795 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_conv_partial_q15.c
+ * Description: Partial convolution of Q15 sequences
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * Refer to <code>arm_conv_partial_fast_q15()</code> for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
+ *
+ * \par
+ * Refer the function <code>arm_conv_partial_opt_q15()</code> for a faster implementation of this function using scratch buffers.
+ *
+ */
+
+arm_status arm_conv_partial_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+
+
+#if (defined(ARM_MATH_CM7) || defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q63_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0; /* Temporary input variables */
+ uint32_t j, k, count, check, blkCnt;
+ int32_t blockSize1, blockSize2, blockSize3; /* loop counter */
+ arm_status status; /* status of Partial convolution */
+
+ /* Check for range of output samples to be calculated */
+ if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+ blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+ blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 :
+ (int32_t) numPoints) : 0;
+ blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+ (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1U + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + firstIndex;
+ py = pSrc2;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations less than 4 */
+ /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ while ((count < 4U) && (blockSize1 > 0))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over number of MAC operations between
+ * inputA samples and inputB samples */
+ k = count;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* The second part of the stage starts here */
+ /* The internal loop, over count, is unrolled by 4 */
+ /* To, read the last two inputB samples using SIMD:
+ * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+ py = py - 1;
+
+ while (blockSize1 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+ /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1U;
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2 - 1U;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ px = pIn1 + firstIndex - srcBLen + 1;
+ }
+ else
+ {
+ px = pIn1;
+ }
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* count is the index by which the pointer pIn1 to be incremented */
+ count = 0U;
+
+
+ /* --------------------
+ * Stage2 process
+ * -------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if (srcBLen >= 4U)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ py = py - 1U;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+
+ /* read x[0], x[1] samples */
+ x0 = *__SIMD32(px);
+ /* read x[1], x[2] samples */
+ x1 = _SIMD32_OFFSET(px+1);
+ px+= 2U;
+
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the last two inputB samples using SIMD:
+ * y[srcBLen - 1] and y[srcBLen - 2] */
+ c0 = *__SIMD32(py)--;
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLALDX(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLALDX(x1, c0, acc1);
+
+ /* Read x[2], x[3] */
+ x2 = *__SIMD32(px);
+
+ /* Read x[3], x[4] */
+ x3 = _SIMD32_OFFSET(px+1);
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLALDX(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLALDX(x3, c0, acc3);
+
+ /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+ c0 = *__SIMD32(py)--;
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLALDX(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLALDX(x3, c0, acc1);
+
+ /* Read x[4], x[5] */
+ x0 = _SIMD32_OFFSET(px+2);
+
+ /* Read x[5], x[6] */
+ x1 = _SIMD32_OFFSET(px+3);
+ px += 4U;
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLALDX(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLALDX(x1, c0, acc3);
+
+ } while (--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ if (k == 1U)
+ {
+ /* Read y[srcBLen - 5] */
+ c0 = *(py+1);
+
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16U;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7] */
+ x3 = *__SIMD32(px);
+ px++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALD(x0, c0, acc0);
+ acc1 = __SMLALD(x1, c0, acc1);
+ acc2 = __SMLALDX(x1, c0, acc2);
+ acc3 = __SMLALDX(x3, c0, acc3);
+ }
+
+ if (k == 2U)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = _SIMD32_OFFSET(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px+1);
+ px += 2U;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALDX(x0, c0, acc0);
+ acc1 = __SMLALDX(x1, c0, acc1);
+ acc2 = __SMLALDX(x3, c0, acc2);
+ acc3 = __SMLALDX(x2, c0, acc3);
+ }
+
+ if (k == 3U)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = _SIMD32_OFFSET(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px+1);
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALDX(x0, c0, acc0);
+ acc1 = __SMLALDX(x1, c0, acc1);
+ acc2 = __SMLALDX(x3, c0, acc2);
+ acc3 = __SMLALDX(x2, c0, acc3);
+
+ c0 = *(py-1);
+
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16U;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[10] */
+ x3 = _SIMD32_OFFSET(px+2);
+ px += 3U;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALDX(x1, c0, acc0);
+ acc1 = __SMLALD(x2, c0, acc1);
+ acc2 = __SMLALDX(x2, c0, acc2);
+ acc3 = __SMLALDX(x3, c0, acc3);
+ }
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4U;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ px = pIn1 + firstIndex - srcBLen + 1 + count;
+ }
+ else
+ {
+ px = pIn1 + count;
+ }
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = (uint32_t) blockSize2 % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ px = pIn1 + firstIndex - srcBLen + 1 + count;
+ }
+ else
+ {
+ px = pIn1 + count;
+ }
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ px = pIn1 + firstIndex - srcBLen + 1 + count;
+ }
+ else
+ {
+ px = pIn1 + count;
+ }
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1U;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ pIn2 = pSrc2 - 1U;
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations greater than 4 */
+ /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ j = count >> 2U;
+
+ while ((j > 0U) && (blockSize3 > 0))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied
+ * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+ /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied
+ * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1U;
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ j--;
+ }
+
+ /* The second part of the stage starts here */
+ /* SIMD is not used for the next MAC operations,
+ * so pointer py is updated to read only one sample at a time */
+ py = py + 1U;
+
+ while (blockSize3 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q15_t *pIn1 = pSrcA; /* inputA pointer */
+ q15_t *pIn2 = pSrcB; /* inputB pointer */
+ q63_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counters */
+ arm_status status; /* status of Partial convolution */
+
+ /* Check for range of output samples to be calculated */
+ if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+ {
+ /* Set status as ARM_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+ /* Loop to calculate convolution for output length number of values */
+ for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if (((i - j) < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q31_t) pIn1[j] * (pIn2[i - j]));
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = (q15_t) __SSAT((sum >> 15U), 16U);
+ }
+ /* set status as ARM_SUCCESS as there are no argument errors */
+ status = ARM_MATH_SUCCESS;
+ }
+ return (status);
+
+#endif /* #if (defined(ARM_MATH_CM7) || defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE) */
+
+}
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q31.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q31.c
new file mode 100644
index 0000000..3a108e0
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q31.c
@@ -0,0 +1,616 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_conv_partial_q31.c
+ * Description: Partial convolution of Q31 sequences
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * See <code>arm_conv_partial_fast_q31()</code> for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.
+ */
+
+arm_status arm_conv_partial_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+
+
+#if defined (ARM_MATH_DSP)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t *pIn1; /* inputA pointer */
+ q31_t *pIn2; /* inputB pointer */
+ q31_t *pOut = pDst; /* output pointer */
+ q31_t *px; /* Intermediate inputA pointer */
+ q31_t *py; /* Intermediate inputB pointer */
+ q31_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q63_t sum, acc0, acc1, acc2; /* Accumulator */
+ q31_t x0, x1, x2, c0;
+ uint32_t j, k, count, check, blkCnt;
+ int32_t blockSize1, blockSize2, blockSize3; /* loop counter */
+ arm_status status; /* status of Partial convolution */
+
+
+ /* Check for range of output samples to be calculated */
+ if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+ blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+ blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 :
+ (int32_t) numPoints) : 0;
+ blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+ (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1U + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + firstIndex;
+ py = pSrc2;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first loop starts here */
+ while (blockSize1 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* x[0] * y[srcBLen - 1] */
+ sum += (q63_t) * px++ * (*py--);
+ /* x[1] * y[srcBLen - 2] */
+ sum += (q63_t) * px++ * (*py--);
+ /* x[2] * y[srcBLen - 3] */
+ sum += (q63_t) * px++ * (*py--);
+ /* x[3] * y[srcBLen - 4] */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ px = pIn1 + firstIndex - srcBLen + 1;
+ }
+ else
+ {
+ px = pIn1;
+ }
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0U;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if (srcBLen >= 4U)
+ {
+ /* Loop unroll over blkCnt */
+
+ blkCnt = blockSize2 / 3;
+ while (blkCnt > 0U)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+
+ /* read x[0], x[1] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+
+ /* Apply loop unrolling and compute 3 MACs simultaneously. */
+ k = srcBLen / 3;
+
+ /* First part of the processing with loop unrolling. Compute 3 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 2 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *(py);
+
+ /* Read x[2] sample */
+ x2 = *(px);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[0] * y[srcBLen - 1] */
+ acc0 += (q63_t) x0 *c0;
+ /* acc1 += x[1] * y[srcBLen - 1] */
+ acc1 += (q63_t) x1 *c0;
+ /* acc2 += x[2] * y[srcBLen - 1] */
+ acc2 += (q63_t) x2 *c0;
+
+ /* Read y[srcBLen - 2] sample */
+ c0 = *(py - 1U);
+
+ /* Read x[3] sample */
+ x0 = *(px + 1U);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[1] * y[srcBLen - 2] */
+ acc0 += (q63_t) x1 *c0;
+ /* acc1 += x[2] * y[srcBLen - 2] */
+ acc1 += (q63_t) x2 *c0;
+ /* acc2 += x[3] * y[srcBLen - 2] */
+ acc2 += (q63_t) x0 *c0;
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *(py - 2U);
+
+ /* Read x[4] sample */
+ x1 = *(px + 2U);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[srcBLen - 3] */
+ acc0 += (q63_t) x2 *c0;
+ /* acc1 += x[3] * y[srcBLen - 2] */
+ acc1 += (q63_t) x0 *c0;
+ /* acc2 += x[4] * y[srcBLen - 2] */
+ acc2 += (q63_t) x1 *c0;
+
+
+ px += 3U;
+
+ py -= 3U;
+
+ } while (--k);
+
+ /* If the srcBLen is not a multiple of 3, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen - (3 * (srcBLen / 3));
+
+ while (k > 0U)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *(py--);
+
+ /* Read x[7] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 += (q63_t) x0 *c0;
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 += (q63_t) x1 *c0;
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 += (q63_t) x2 *c0;
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (acc0 >> 31);
+ *pOut++ = (q31_t) (acc1 >> 31);
+ *pOut++ = (q31_t) (acc2 >> 31);
+
+ /* Increment the pointer pIn1 index, count by 3 */
+ count += 3U;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ px = pIn1 + firstIndex - srcBLen + 1 + count;
+ }
+ else
+ {
+ px = pIn1 + count;
+ }
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 3, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 - 3 * (blockSize2 / 3);
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ px = pIn1 + firstIndex - srcBLen + 1 + count;
+ }
+ else
+ {
+ px = pIn1 + count;
+ }
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ px = pIn1 + firstIndex - srcBLen + 1 + count;
+ }
+ else
+ {
+ px = pIn1 + count;
+ }
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+ count = srcBLen - 1U;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while (blockSize3 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q31_t *pIn1 = pSrcA; /* inputA pointer */
+ q31_t *pIn2 = pSrcB; /* inputB pointer */
+ q63_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counters */
+ arm_status status; /* status of Partial convolution */
+
+ /* Check for range of output samples to be calculated */
+ if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+ {
+ /* Set status as ARM_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+ /* Loop to calculate convolution for output length number of values */
+ for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if (((i - j) < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q63_t) pIn1[j] * (pIn2[i - j]));
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = (q31_t) (sum >> 31U);
+ }
+ /* set status as ARM_SUCCESS as there are no argument errors */
+ status = ARM_MATH_SUCCESS;
+ }
+ return (status);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q7.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q7.c
new file mode 100644
index 0000000..cb4c562
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q7.c
@@ -0,0 +1,750 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_conv_partial_q7.c
+ * Description: Partial convolution of Q7 sequences
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * \par
+ * Refer the function <code>arm_conv_partial_opt_q7()</code> for a faster implementation of this function.
+ *
+ */
+
+arm_status arm_conv_partial_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+
+
+#if defined (ARM_MATH_DSP)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q7_t *pIn1; /* inputA pointer */
+ q7_t *pIn2; /* inputB pointer */
+ q7_t *pOut = pDst; /* output pointer */
+ q7_t *px; /* Intermediate inputA pointer */
+ q7_t *py; /* Intermediate inputB pointer */
+ q7_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t input1, input2;
+ q15_t in1, in2;
+ q7_t x0, x1, x2, x3, c0, c1;
+ uint32_t j, k, count, check, blkCnt;
+ int32_t blockSize1, blockSize2, blockSize3; /* loop counter */
+ arm_status status;
+
+
+ /* Check for range of output samples to be calculated */
+ if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+ blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+ blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 :
+ (int32_t) numPoints) : 0;
+ blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+ (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1U + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + firstIndex;
+ py = pSrc2;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while (blockSize1 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* x[0] , x[1] */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[srcBLen - 1] , y[srcBLen - 2] */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* x[0] * y[srcBLen - 1] */
+ /* x[1] * y[srcBLen - 2] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* x[2] , x[3] */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[srcBLen - 3] , y[srcBLen - 4] */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* x[2] * y[srcBLen - 3] */
+ /* x[3] * y[srcBLen - 4] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ px = pIn1 + firstIndex - srcBLen + 1;
+ }
+ else
+ {
+ px = pIn1;
+ }
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0U;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if (srcBLen >= 4U)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = ((uint32_t) blockSize2 >> 2U);
+
+ while (blkCnt > 0U)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *(py--);
+ /* Read y[srcBLen - 2] sample */
+ c1 = *(py--);
+
+ /* Read x[3] sample */
+ x3 = *(px++);
+
+ /* x[0] and x[1] are packed */
+ in1 = (q15_t) x0;
+ in2 = (q15_t) x1;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[srcBLen - 1] and y[srcBLen - 2] are packed */
+ in1 = (q15_t) c0;
+ in2 = (q15_t) c1;
+
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLAD(input1, input2, acc0);
+
+ /* x[1] and x[2] are packed */
+ in1 = (q15_t) x1;
+ in2 = (q15_t) x2;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLAD(input1, input2, acc1);
+
+ /* x[2] and x[3] are packed */
+ in1 = (q15_t) x2;
+ in2 = (q15_t) x3;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLAD(input1, input2, acc2);
+
+ /* Read x[4] sample */
+ x0 = *(px++);
+
+ /* x[3] and x[4] are packed */
+ in1 = (q15_t) x3;
+ in2 = (q15_t) x0;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLAD(input1, input2, acc3);
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *(py--);
+ /* Read y[srcBLen - 4] sample */
+ c1 = *(py--);
+
+ /* Read x[5] sample */
+ x1 = *(px++);
+
+ /* x[2] and x[3] are packed */
+ in1 = (q15_t) x2;
+ in2 = (q15_t) x3;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[srcBLen - 3] and y[srcBLen - 4] are packed */
+ in1 = (q15_t) c0;
+ in2 = (q15_t) c1;
+
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLAD(input1, input2, acc0);
+
+ /* x[3] and x[4] are packed */
+ in1 = (q15_t) x3;
+ in2 = (q15_t) x0;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLAD(input1, input2, acc1);
+
+ /* x[4] and x[5] are packed */
+ in1 = (q15_t) x0;
+ in2 = (q15_t) x1;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLAD(input1, input2, acc2);
+
+ /* Read x[6] sample */
+ x2 = *(px++);
+
+ /* x[5] and x[6] are packed */
+ in1 = (q15_t) x1;
+ in2 = (q15_t) x2;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLAD(input1, input2, acc3);
+
+ } while (--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *(py--);
+
+ /* Read x[7] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 += ((q31_t) x0 * c0);
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 += ((q31_t) x1 * c0);
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 += ((q31_t) x2 * c0);
+ /* acc3 += x[7] * y[srcBLen - 5] */
+ acc3 += ((q31_t) x3 * c0);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(acc0 >> 7, 8));
+ *pOut++ = (q7_t) (__SSAT(acc1 >> 7, 8));
+ *pOut++ = (q7_t) (__SSAT(acc2 >> 7, 8));
+ *pOut++ = (q7_t) (__SSAT(acc3 >> 7, 8));
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4U;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ px = pIn1 + firstIndex - srcBLen + 1 + count;
+ }
+ else
+ {
+ px = pIn1 + count;
+ }
+ py = pSrc2;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = (uint32_t) blockSize2 % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+
+ /* Reading two inputs of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Reading two inputs of SrcB buffer and packing */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Reading two inputs of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Reading two inputs of SrcB buffer and packing */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ px = pIn1 + firstIndex - srcBLen + 1 + count;
+ }
+ else
+ {
+ px = pIn1 + count;
+ }
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ px = pIn1 + firstIndex - srcBLen + 1 + count;
+ }
+ else
+ {
+ px = pIn1 + count;
+ }
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1U;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while (blockSize3 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q7_t *pIn1 = pSrcA; /* inputA pointer */
+ q7_t *pIn2 = pSrcB; /* inputB pointer */
+ q31_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counters */
+ arm_status status; /* status of Partial convolution */
+
+ /* Check for range of output samples to be calculated */
+ if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+ {
+ /* Set status as ARM_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+ /* Loop to calculate convolution for output length number of values */
+ for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if (((i - j) < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q15_t) pIn1[j] * (pIn2[i - j]));
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = (q7_t) __SSAT((sum >> 7U), 8U);
+ }
+ /* set status as ARM_SUCCESS as there are no argument errors */
+ status = ARM_MATH_SUCCESS;
+ }
+ return (status);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q15.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q15.c
new file mode 100644
index 0000000..c6721e0
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q15.c
@@ -0,0 +1,722 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_conv_q15.c
+ * Description: Convolution of Q15 sequences
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both inputs are in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * This approach provides 33 guard bits and there is no risk of overflow.
+ * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.
+ *
+ * \par
+ * Refer to <code>arm_conv_fast_q15()</code> for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
+ *
+ * \par
+ * Refer the function <code>arm_conv_opt_q15()</code> for a faster implementation of this function using scratch buffers.
+ *
+ */
+
+void arm_conv_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst)
+{
+
+#if (defined(ARM_MATH_CM7) || defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q63_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt; /* loop counter */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1U;
+ blockSize2 = srcALen - (srcBLen - 1U);
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1U;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations less than 4 */
+ /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ while ((count < 4U) && (blockSize1 > 0U))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over number of MAC operations between
+ * inputA samples and inputB samples */
+ k = count;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* The second part of the stage starts here */
+ /* The internal loop, over count, is unrolled by 4 */
+ /* To, read the last two inputB samples using SIMD:
+ * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+ py = py - 1;
+
+ while (blockSize1 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+ /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1U;
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + (count - 1U);
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* count is the index by which the pointer pIn1 to be incremented */
+ count = 0U;
+
+
+ /* --------------------
+ * Stage2 process
+ * -------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if (srcBLen >= 4U)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ py = py - 1U;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+
+ /* read x[0], x[1] samples */
+ x0 = *__SIMD32(px);
+ /* read x[1], x[2] samples */
+ x1 = _SIMD32_OFFSET(px+1);
+ px+= 2U;
+
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the last two inputB samples using SIMD:
+ * y[srcBLen - 1] and y[srcBLen - 2] */
+ c0 = *__SIMD32(py)--;
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLALDX(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLALDX(x1, c0, acc1);
+
+ /* Read x[2], x[3] */
+ x2 = *__SIMD32(px);
+
+ /* Read x[3], x[4] */
+ x3 = _SIMD32_OFFSET(px+1);
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLALDX(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLALDX(x3, c0, acc3);
+
+ /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+ c0 = *__SIMD32(py)--;
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLALDX(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLALDX(x3, c0, acc1);
+
+ /* Read x[4], x[5] */
+ x0 = _SIMD32_OFFSET(px+2);
+
+ /* Read x[5], x[6] */
+ x1 = _SIMD32_OFFSET(px+3);
+ px += 4U;
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLALDX(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLALDX(x1, c0, acc3);
+
+ } while (--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ if (k == 1U)
+ {
+ /* Read y[srcBLen - 5] */
+ c0 = *(py+1);
+
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16U;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+ /* Read x[7] */
+ x3 = *__SIMD32(px);
+ px++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALD(x0, c0, acc0);
+ acc1 = __SMLALD(x1, c0, acc1);
+ acc2 = __SMLALDX(x1, c0, acc2);
+ acc3 = __SMLALDX(x3, c0, acc3);
+ }
+
+ if (k == 2U)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = _SIMD32_OFFSET(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px+1);
+ px += 2U;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALDX(x0, c0, acc0);
+ acc1 = __SMLALDX(x1, c0, acc1);
+ acc2 = __SMLALDX(x3, c0, acc2);
+ acc3 = __SMLALDX(x2, c0, acc3);
+ }
+
+ if (k == 3U)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = _SIMD32_OFFSET(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px+1);
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALDX(x0, c0, acc0);
+ acc1 = __SMLALDX(x1, c0, acc1);
+ acc2 = __SMLALDX(x3, c0, acc2);
+ acc3 = __SMLALDX(x2, c0, acc3);
+
+ c0 = *(py-1);
+
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16U;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+ /* Read x[10] */
+ x3 = _SIMD32_OFFSET(px+2);
+ px += 3U;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALDX(x1, c0, acc0);
+ acc1 = __SMLALD(x2, c0, acc1);
+ acc2 = __SMLALDX(x2, c0, acc2);
+ acc3 = __SMLALDX(x3, c0, acc3);
+ }
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4U;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+
+ blockSize3 = srcBLen - 1U;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ pIn2 = pSrc2 - 1U;
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations greater than 4 */
+ /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ j = blockSize3 >> 2U;
+
+ while ((j > 0U) && (blockSize3 > 0U))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3 >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied
+ * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+ /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied
+ * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1U;
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = blockSize3 % 0x4U;
+
+ while (k > 0U)
+ {
+ /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ j--;
+ }
+
+ /* The second part of the stage starts here */
+ /* SIMD is not used for the next MAC operations,
+ * so pointer py is updated to read only one sample at a time */
+ py = py + 1U;
+
+ while (blockSize3 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+ q15_t *pIn1 = pSrcA; /* input pointer */
+ q15_t *pIn2 = pSrcB; /* coefficient pointer */
+ q63_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counter */
+
+ /* Loop to calculate output of convolution for output length number of times */
+ for (i = 0; i < (srcALen + srcBLen - 1); i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if (((i - j) < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += (q31_t) pIn1[j] * (pIn2[i - j]);
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = (q15_t) __SSAT((sum >> 15U), 16U);
+ }
+
+#endif /* #if (defined(ARM_MATH_CM7) || defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE) */
+
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q31.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q31.c
new file mode 100644
index 0000000..14e5f86
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q31.c
@@ -0,0 +1,553 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_conv_q31.c
+ * Description: Convolution of Q31 sequences
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * There is no saturation on intermediate additions.
+ * Thus, if the accumulator overflows it wraps around and distorts the result.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.
+ * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.
+ *
+ * \par
+ * See <code>arm_conv_fast_q31()</code> for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.
+ */
+
+void arm_conv_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst)
+{
+
+
+#if defined (ARM_MATH_DSP)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t *pIn1; /* inputA pointer */
+ q31_t *pIn2; /* inputB pointer */
+ q31_t *pOut = pDst; /* output pointer */
+ q31_t *px; /* Intermediate inputA pointer */
+ q31_t *py; /* Intermediate inputB pointer */
+ q31_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q63_t sum; /* Accumulator */
+ q63_t acc0, acc1, acc2; /* Accumulator */
+ q31_t x0, x1, x2, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3; /* loop counter */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (q31_t *) pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = (q31_t *) pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1U;
+ blockSize2 = srcALen - (srcBLen - 1U);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1U;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while (blockSize1 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* x[0] * y[srcBLen - 1] */
+ sum += (q63_t) * px++ * (*py--);
+ /* x[1] * y[srcBLen - 2] */
+ sum += (q63_t) * px++ * (*py--);
+ /* x[2] * y[srcBLen - 3] */
+ sum += (q63_t) * px++ * (*py--);
+ /* x[3] * y[srcBLen - 4] */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0U;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if (srcBLen >= 4U)
+ {
+ /* Loop unroll by 3 */
+ blkCnt = blockSize2 / 3;
+
+ while (blkCnt > 0U)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+
+ /* Apply loop unrolling and compute 3 MACs simultaneously. */
+ k = srcBLen / 3;
+
+ /* First part of the processing with loop unrolling. Compute 3 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 2 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *(py);
+
+ /* Read x[3] sample */
+ x2 = *(px);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[0] * y[srcBLen - 1] */
+ acc0 += ((q63_t) x0 * c0);
+ /* acc1 += x[1] * y[srcBLen - 1] */
+ acc1 += ((q63_t) x1 * c0);
+ /* acc2 += x[2] * y[srcBLen - 1] */
+ acc2 += ((q63_t) x2 * c0);
+
+ /* Read y[srcBLen - 2] sample */
+ c0 = *(py - 1U);
+
+ /* Read x[4] sample */
+ x0 = *(px + 1U);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[1] * y[srcBLen - 2] */
+ acc0 += ((q63_t) x1 * c0);
+ /* acc1 += x[2] * y[srcBLen - 2] */
+ acc1 += ((q63_t) x2 * c0);
+ /* acc2 += x[3] * y[srcBLen - 2] */
+ acc2 += ((q63_t) x0 * c0);
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *(py - 2U);
+
+ /* Read x[5] sample */
+ x1 = *(px + 2U);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[srcBLen - 3] */
+ acc0 += ((q63_t) x2 * c0);
+ /* acc1 += x[3] * y[srcBLen - 2] */
+ acc1 += ((q63_t) x0 * c0);
+ /* acc2 += x[4] * y[srcBLen - 2] */
+ acc2 += ((q63_t) x1 * c0);
+
+ /* update scratch pointers */
+ px += 3U;
+ py -= 3U;
+
+ } while (--k);
+
+ /* If the srcBLen is not a multiple of 3, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen - (3 * (srcBLen / 3));
+
+ while (k > 0U)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *(py--);
+
+ /* Read x[7] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 += ((q63_t) x0 * c0);
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 += ((q63_t) x1 * c0);
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 += ((q63_t) x2 * c0);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the results in the accumulators in the destination buffer. */
+ *pOut++ = (q31_t) (acc0 >> 31);
+ *pOut++ = (q31_t) (acc1 >> 31);
+ *pOut++ = (q31_t) (acc2 >> 31);
+
+ /* Increment the pointer pIn1 index, count by 3 */
+ count += 3U;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 3, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 - 3 * (blockSize2 / 3);
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while (blockSize3 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3 >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ sum += (q63_t) * px++ * (*py--);
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum += (q63_t) * px++ * (*py--);
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ sum += (q63_t) * px++ * (*py--);
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = blockSize3 % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q31_t *pIn1 = pSrcA; /* input pointer */
+ q31_t *pIn2 = pSrcB; /* coefficient pointer */
+ q63_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counter */
+
+ /* Loop to calculate output of convolution for output length number of times */
+ for (i = 0; i < (srcALen + srcBLen - 1); i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if (((i - j) < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q63_t) pIn1[j] * (pIn2[i - j]));
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = (q31_t) (sum >> 31U);
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q7.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q7.c
new file mode 100644
index 0000000..6c4dd3c
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q7.c
@@ -0,0 +1,678 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_conv_q7.c
+ * Description: Convolution of Q7 sequences
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
+ * This approach provides 17 guard bits and there is no risk of overflow as long as <code>max(srcALen, srcBLen)<131072</code>.
+ * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format.
+ *
+ * \par
+ * Refer the function <code>arm_conv_opt_q7()</code> for a faster implementation of this function.
+ *
+ */
+
+void arm_conv_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst)
+{
+
+
+#if defined (ARM_MATH_DSP)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q7_t *pIn1; /* inputA pointer */
+ q7_t *pIn2; /* inputB pointer */
+ q7_t *pOut = pDst; /* output pointer */
+ q7_t *px; /* Intermediate inputA pointer */
+ q7_t *py; /* Intermediate inputB pointer */
+ q7_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q7_t x0, x1, x2, x3, c0, c1; /* Temporary variables to hold state and coefficient values */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t input1, input2; /* Temporary input variables */
+ q15_t in1, in2; /* Temporary input variables */
+ uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3; /* loop counter */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1U;
+ blockSize2 = (srcALen - srcBLen) + 1U;
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1U;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while (blockSize1 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* x[0] , x[1] */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* y[srcBLen - 1] , y[srcBLen - 2] */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* x[0] * y[srcBLen - 1] */
+ /* x[1] * y[srcBLen - 2] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* x[2] , x[3] */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* y[srcBLen - 3] , y[srcBLen - 4] */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* x[2] * y[srcBLen - 3] */
+ /* x[3] * y[srcBLen - 4] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q15_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0U;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if (srcBLen >= 4U)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *(py--);
+ /* Read y[srcBLen - 2] sample */
+ c1 = *(py--);
+
+ /* Read x[3] sample */
+ x3 = *(px++);
+
+ /* x[0] and x[1] are packed */
+ in1 = (q15_t) x0;
+ in2 = (q15_t) x1;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* y[srcBLen - 1] and y[srcBLen - 2] are packed */
+ in1 = (q15_t) c0;
+ in2 = (q15_t) c1;
+
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLAD(input1, input2, acc0);
+
+ /* x[1] and x[2] are packed */
+ in1 = (q15_t) x1;
+ in2 = (q15_t) x2;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLAD(input1, input2, acc1);
+
+ /* x[2] and x[3] are packed */
+ in1 = (q15_t) x2;
+ in2 = (q15_t) x3;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLAD(input1, input2, acc2);
+
+ /* Read x[4] sample */
+ x0 = *(px++);
+
+ /* x[3] and x[4] are packed */
+ in1 = (q15_t) x3;
+ in2 = (q15_t) x0;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLAD(input1, input2, acc3);
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *(py--);
+ /* Read y[srcBLen - 4] sample */
+ c1 = *(py--);
+
+ /* Read x[5] sample */
+ x1 = *(px++);
+
+ /* x[2] and x[3] are packed */
+ in1 = (q15_t) x2;
+ in2 = (q15_t) x3;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* y[srcBLen - 3] and y[srcBLen - 4] are packed */
+ in1 = (q15_t) c0;
+ in2 = (q15_t) c1;
+
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLAD(input1, input2, acc0);
+
+ /* x[3] and x[4] are packed */
+ in1 = (q15_t) x3;
+ in2 = (q15_t) x0;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLAD(input1, input2, acc1);
+
+ /* x[4] and x[5] are packed */
+ in1 = (q15_t) x0;
+ in2 = (q15_t) x1;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLAD(input1, input2, acc2);
+
+ /* Read x[6] sample */
+ x2 = *(px++);
+
+ /* x[5] and x[6] are packed */
+ in1 = (q15_t) x1;
+ in2 = (q15_t) x2;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLAD(input1, input2, acc3);
+
+ } while (--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *(py--);
+
+ /* Read x[7] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 += ((q15_t) x0 * c0);
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 += ((q15_t) x1 * c0);
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 += ((q15_t) x2 * c0);
+ /* acc3 += x[7] * y[srcBLen - 5] */
+ acc3 += ((q15_t) x3 * c0);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(acc0 >> 7U, 8));
+ *pOut++ = (q7_t) (__SSAT(acc1 >> 7U, 8));
+ *pOut++ = (q7_t) (__SSAT(acc2 >> 7U, 8));
+ *pOut++ = (q7_t) (__SSAT(acc3 >> 7U, 8));
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4U;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+
+ /* Reading two inputs of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* Reading two inputs of SrcB buffer and packing */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Reading two inputs of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* Reading two inputs of SrcB buffer and packing */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q15_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8));
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q15_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8));
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+
+ /* Working pointer of inputA */
+ pSrc1 = pIn1 + (srcALen - (srcBLen - 1U));
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while (blockSize3 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3 >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = blockSize3 % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q15_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q7_t *pIn1 = pSrcA; /* input pointer */
+ q7_t *pIn2 = pSrcB; /* coefficient pointer */
+ q31_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counter */
+
+ /* Loop to calculate output of convolution for output length number of times */
+ for (i = 0; i < (srcALen + srcBLen - 1); i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if (((i - j) < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += (q15_t) pIn1[j] * (pIn2[i - j]);
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = (q7_t) __SSAT((sum >> 7U), 8U);
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f32.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f32.c
new file mode 100644
index 0000000..9451887
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f32.c
@@ -0,0 +1,727 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_correlate_f32.c
+ * Description: Correlation of floating-point sequences
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup Corr Correlation
+ *
+ * Correlation is a mathematical operation that is similar to convolution.
+ * As with convolution, correlation uses two signals to produce a third signal.
+ * The underlying algorithms in correlation and convolution are identical except that one of the inputs is flipped in convolution.
+ * Correlation is commonly used to measure the similarity between two signals.
+ * It has applications in pattern recognition, cryptanalysis, and searching.
+ * The CMSIS library provides correlation functions for Q7, Q15, Q31 and floating-point data types.
+ * Fast versions of the Q15 and Q31 functions are also provided.
+ *
+ * \par Algorithm
+ * Let <code>a[n]</code> and <code>b[n]</code> be sequences of length <code>srcALen</code> and <code>srcBLen</code> samples respectively.
+ * The convolution of the two signals is denoted by
+ * <pre>
+ * c[n] = a[n] * b[n]
+ * </pre>
+ * In correlation, one of the signals is flipped in time
+ * <pre>
+ * c[n] = a[n] * b[-n]
+ * </pre>
+ *
+ * \par
+ * and this is mathematically defined as
+ * \image html CorrelateEquation.gif
+ * \par
+ * The <code>pSrcA</code> points to the first input vector of length <code>srcALen</code> and <code>pSrcB</code> points to the second input vector of length <code>srcBLen</code>.
+ * The result <code>c[n]</code> is of length <code>2 * max(srcALen, srcBLen) - 1</code> and is defined over the interval <code>n=0, 1, 2, ..., (2 * max(srcALen, srcBLen) - 2)</code>.
+ * The output result is written to <code>pDst</code> and the calling function must allocate <code>2 * max(srcALen, srcBLen) - 1</code> words for the result.
+ *
+ * <b>Note</b>
+ * \par
+ * The <code>pDst</code> should be initialized to all zeros before being used.
+ *
+ * <b>Fixed-Point Behavior</b>
+ * \par
+ * Correlation requires summing up a large number of intermediate products.
+ * As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation.
+ * Refer to the function specific documentation below for further details of the particular algorithm used.
+ *
+ *
+ * <b>Fast Versions</b>
+ *
+ * \par
+ * Fast versions are supported for Q31 and Q15. Cycles for Fast versions are less compared to Q31 and Q15 of correlate and the design requires
+ * the input signals should be scaled down to avoid intermediate overflows.
+ *
+ *
+ * <b>Opt Versions</b>
+ *
+ * \par
+ * Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation.
+ * These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions of correlate
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+/**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+void arm_correlate_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst)
+{
+
+
+#if defined (ARM_MATH_DSP)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float32_t *pIn1; /* inputA pointer */
+ float32_t *pIn2; /* inputB pointer */
+ float32_t *pOut = pDst; /* output pointer */
+ float32_t *px; /* Intermediate inputA pointer */
+ float32_t *py; /* Intermediate inputB pointer */
+ float32_t *pSrc1; /* Intermediate pointers */
+ float32_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
+ float32_t x0, x1, x2, x3, c0; /* temporary variables for holding input and coefficient values */
+ uint32_t j, k = 0U, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3; /* loop counters */
+ int32_t inc = 1; /* Destination address modifier */
+
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we assume zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2U * srcALen) - 1U;
+
+ /* When srcALen > srcBLen, zero padding has to be done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1U));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ //while (j > 0U)
+ //{
+ // /* Zero is stored in the destination buffer */
+ // *pOut++ = 0.0f;
+
+ // /* Decrement the loop counter */
+ // j--;
+ //}
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2U);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ /* The function is internally
+ * divided into three parts according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first part of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second part of the algorithm, srcBLen number of multiplications are done.
+ * In the third part of the algorithm, the multiplications decrease by one
+ * for every iteration.*/
+ /* The algorithm is implemented in three stages.
+ * The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1U;
+ blockSize2 = srcALen - (srcBLen - 1U);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[srcBlen - 1]
+ * sum = x[0] * y[srcBlen-2] + x[1] * y[srcBlen - 1]
+ * ....
+ * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1U;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc1 = pIn2 + (srcBLen - 1U);
+ py = pSrc1;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while (blockSize1 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* x[0] * y[srcBLen - 4] */
+ sum += *px++ * *py++;
+ /* x[1] * y[srcBLen - 3] */
+ sum += *px++ * *py++;
+ /* x[2] * y[srcBLen - 2] */
+ sum += *px++ * *py++;
+ /* x[3] * y[srcBLen - 1] */
+ sum += *px++ * *py++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ /* x[0] * y[srcBLen - 1] */
+ sum += *px++ * *py++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = sum;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pSrc1 - count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+ * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0U;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+ if (srcBLen >= 4U)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0.0f;
+ acc1 = 0.0f;
+ acc2 = 0.0f;
+ acc3 = 0.0f;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[0] sample */
+ c0 = *(py++);
+
+ /* Read x[3] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[0] * y[0] */
+ acc0 += x0 * c0;
+ /* acc1 += x[1] * y[0] */
+ acc1 += x1 * c0;
+ /* acc2 += x[2] * y[0] */
+ acc2 += x2 * c0;
+ /* acc3 += x[3] * y[0] */
+ acc3 += x3 * c0;
+
+ /* Read y[1] sample */
+ c0 = *(py++);
+
+ /* Read x[4] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[1] * y[1] */
+ acc0 += x1 * c0;
+ /* acc1 += x[2] * y[1] */
+ acc1 += x2 * c0;
+ /* acc2 += x[3] * y[1] */
+ acc2 += x3 * c0;
+ /* acc3 += x[4] * y[1] */
+ acc3 += x0 * c0;
+
+ /* Read y[2] sample */
+ c0 = *(py++);
+
+ /* Read x[5] sample */
+ x1 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[2] */
+ acc0 += x2 * c0;
+ /* acc1 += x[3] * y[2] */
+ acc1 += x3 * c0;
+ /* acc2 += x[4] * y[2] */
+ acc2 += x0 * c0;
+ /* acc3 += x[5] * y[2] */
+ acc3 += x1 * c0;
+
+ /* Read y[3] sample */
+ c0 = *(py++);
+
+ /* Read x[6] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[3] * y[3] */
+ acc0 += x3 * c0;
+ /* acc1 += x[4] * y[3] */
+ acc1 += x0 * c0;
+ /* acc2 += x[5] * y[3] */
+ acc2 += x1 * c0;
+ /* acc3 += x[6] * y[3] */
+ acc3 += x2 * c0;
+
+
+ } while (--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Read y[4] sample */
+ c0 = *(py++);
+
+ /* Read x[7] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[4] */
+ acc0 += x0 * c0;
+ /* acc1 += x[5] * y[4] */
+ acc1 += x1 * c0;
+ /* acc2 += x[6] * y[4] */
+ acc2 += x2 * c0;
+ /* acc3 += x[7] * y[4] */
+ acc3 += x3 * c0;
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = acc0;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ *pOut = acc1;
+ pOut += inc;
+
+ *pOut = acc2;
+ pOut += inc;
+
+ *pOut = acc3;
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4U;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += *px++ * *py++;
+ sum += *px++ * *py++;
+ sum += *px++ * *py++;
+ sum += *px++ * *py++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *px++ * *py++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = sum;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Loop over srcBLen */
+ k = srcBLen;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *px++ * *py++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = sum;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * ....
+ * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+ * sum += x[srcALen-1] * y[0]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1U;
+
+ /* Working pointer of inputA */
+ pSrc1 = pIn1 + (srcALen - (srcBLen - 1U));
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while (blockSize3 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen - srcBLen + 4] * y[3] */
+ sum += *px++ * *py++;
+ /* sum += x[srcALen - srcBLen + 3] * y[2] */
+ sum += *px++ * *py++;
+ /* sum += x[srcALen - srcBLen + 2] * y[1] */
+ sum += *px++ * *py++;
+ /* sum += x[srcALen - srcBLen + 1] * y[0] */
+ sum += *px++ * *py++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += *px++ * *py++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = sum;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ float32_t *pIn1 = pSrcA; /* inputA pointer */
+ float32_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */
+ float32_t sum; /* Accumulator */
+ uint32_t i = 0U, j; /* loop counters */
+ uint32_t inv = 0U; /* Reverse order flag */
+ uint32_t tot = 0U; /* Length */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and a varaible, inv is set to 1 */
+ /* If lengths are not equal then zero pad has to be done to make the two
+ * inputs of same length. But to improve the performance, we assume zeroes
+ * in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the
+ * starting of the output buffer */
+ /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the
+ * ending of the output buffer */
+ /* Once the zero padding is done the remaining of the output is calcualted
+ * using convolution but with the shorter signal time shifted. */
+
+ /* Calculate the length of the remaining sequence */
+ tot = ((srcALen + srcBLen) - 2U);
+
+ if (srcALen > srcBLen)
+ {
+ /* Calculating the number of zeros to be padded to the output */
+ j = srcALen - srcBLen;
+
+ /* Initialise the pointer after zero padding */
+ pDst += j;
+ }
+
+ else if (srcALen < srcBLen)
+ {
+ /* Initialization to inputB pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization to the end of inputA pointer */
+ pIn2 = pSrcA + (srcALen - 1U);
+
+ /* Initialisation of the pointer after zero padding */
+ pDst = pDst + tot;
+
+ /* Swapping the lengths */
+ j = srcALen;
+ srcALen = srcBLen;
+ srcBLen = j;
+
+ /* Setting the reverse flag */
+ inv = 1;
+
+ }
+
+ /* Loop to calculate convolution for output length number of times */
+ for (i = 0U; i <= tot; i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0.0f;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0U; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if ((((i - j) < srcBLen) && (j < srcALen)))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += pIn1[j] * pIn2[-((int32_t) i - j)];
+ }
+ }
+ /* Store the output in the destination buffer */
+ if (inv == 1)
+ *pDst-- = sum;
+ else
+ *pDst++ = sum;
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c
new file mode 100644
index 0000000..baebc49
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c
@@ -0,0 +1,500 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_correlate_fast_opt_q15.c
+ * Description: Fast Q15 Correlation
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @return none.
+ *
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, scratch buffers should be aligned by 32-bit
+ *
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * This fast version uses a 32-bit accumulator with 2.30 format.
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * There is no saturation on intermediate additions.
+ * Thus, if the accumulator overflows it wraps around and distorts the result.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
+ *
+ * \par
+ * See <code>arm_correlate_q15()</code> for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.
+ */
+
+void arm_correlate_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch)
+{
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulators */
+ q15_t *py; /* Intermediate inputB pointer */
+ q31_t x1, x2, x3; /* temporary variables for holding input and coefficient values */
+ uint32_t j, blkCnt, outBlockSize; /* loop counter */
+ int32_t inc = 1; /* Destination address modifier */
+ uint32_t tapCnt;
+ q31_t y1, y2;
+ q15_t *pScr; /* Intermediate pointers */
+ q15_t *pOut = pDst; /* output pointer */
+#ifdef UNALIGNED_SUPPORT_DISABLE
+
+ q15_t a, b;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcA);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcB);
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2U * srcALen) - 1U;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1U));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcB);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcA);
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2U);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ pScr = pScratch;
+
+ /* Fill (srcBLen - 1U) zeros in scratch buffer */
+ arm_fill_q15(0, pScr, (srcBLen - 1U));
+
+ /* Update temporary scratch pointer */
+ pScr += (srcBLen - 1U);
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Copy (srcALen) samples in scratch buffer */
+ arm_copy_q15(pIn1, pScr, srcALen);
+
+ /* Update pointers */
+ pScr += srcALen;
+
+#else
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ j = srcALen >> 2U;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while (j > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr++ = *pIn1++;
+ *pScr++ = *pIn1++;
+ *pScr++ = *pIn1++;
+ *pScr++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ j = srcALen % 0x4U;
+
+ while (j > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Fill (srcBLen - 1U) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr, (srcBLen - 1U));
+
+ /* Update pointer */
+ pScr += (srcBLen - 1U);
+
+#else
+
+/* Apply loop unrolling and do 4 Copies simultaneously. */
+ j = (srcBLen - 1U) >> 2U;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while (j > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr++ = 0;
+ *pScr++ = 0;
+ *pScr++ = 0;
+ *pScr++ = 0;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ j = (srcBLen - 1U) % 0x4U;
+
+ while (j > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr++ = 0;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Temporary pointer for scratch2 */
+ py = pIn2;
+
+
+ /* Actual correlation process starts here */
+ blkCnt = (srcALen + srcBLen - 1U) >> 2;
+
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr = pScratch;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read four samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr)++;
+
+ /* Read next four samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr)++;
+
+ tapCnt = (srcBLen) >> 2U;
+
+ while (tapCnt > 0U)
+ {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pIn2);
+ y2 = _SIMD32_OFFSET(pIn2 + 2U);
+
+ acc0 = __SMLAD(x1, y1, acc0);
+
+ acc2 = __SMLAD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ x1 = _SIMD32_OFFSET(pScr);
+
+ acc0 = __SMLAD(x2, y2, acc0);
+
+ acc2 = __SMLAD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ acc1 = __SMLADX(x3, y2, acc1);
+
+ x2 = _SIMD32_OFFSET(pScr + 2U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y2, acc3);
+#else
+
+ /* Read four samples from smaller buffer */
+ a = *pIn2;
+ b = *(pIn2 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ y1 = __PKHBT(a, b, 16);
+#else
+ y1 = __PKHBT(b, a, 16);
+#endif
+
+ a = *(pIn2 + 2);
+ b = *(pIn2 + 3);
+#ifndef ARM_MATH_BIG_ENDIAN
+ y2 = __PKHBT(a, b, 16);
+#else
+ y2 = __PKHBT(b, a, 16);
+#endif
+
+ acc0 = __SMLAD(x1, y1, acc0);
+
+ acc2 = __SMLAD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ a = *pScr;
+ b = *(pScr + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(a, b, 16);
+#else
+ x1 = __PKHBT(b, a, 16);
+#endif
+
+ acc0 = __SMLAD(x2, y2, acc0);
+
+ acc2 = __SMLAD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ acc1 = __SMLADX(x3, y2, acc1);
+
+ a = *(pScr + 2);
+ b = *(pScr + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x2 = __PKHBT(a, b, 16);
+#else
+ x2 = __PKHBT(b, a, 16);
+#endif
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y2, acc3);
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ pIn2 += 4U;
+
+ pScr += 4U;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr -= 4U;
+
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3U;
+
+ while (tapCnt > 0U)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr++ * *pIn2);
+ acc1 += (*pScr++ * *pIn2);
+ acc2 += (*pScr++ * *pIn2);
+ acc3 += (*pScr++ * *pIn2++);
+
+ pScr -= 3U;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+ *pOut = (__SSAT(acc0 >> 15U, 16));
+ pOut += inc;
+ *pOut = (__SSAT(acc1 >> 15U, 16));
+ pOut += inc;
+ *pOut = (__SSAT(acc2 >> 15U, 16));
+ pOut += inc;
+ *pOut = (__SSAT(acc3 >> 15U, 16));
+ pOut += inc;
+
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch += 4U;
+
+ }
+
+
+ blkCnt = (srcALen + srcBLen - 1U) & 0x3;
+
+ /* Calculate correlation for remaining samples of Bigger length sequence */
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr = pScratch;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1U;
+
+ while (tapCnt > 0U)
+ {
+
+ acc0 += (*pScr++ * *pIn2++);
+ acc0 += (*pScr++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while (tapCnt > 0U)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+
+ *pOut = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ pOut += inc;
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch += 1U;
+
+ }
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q15.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q15.c
new file mode 100644
index 0000000..7b676d0
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q15.c
@@ -0,0 +1,1307 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_correlate_fast_q15.c
+ * Description: Fast Q15 Correlation
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * This fast version uses a 32-bit accumulator with 2.30 format.
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * There is no saturation on intermediate additions.
+ * Thus, if the accumulator overflows it wraps around and distorts the result.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
+ *
+ * \par
+ * See <code>arm_correlate_q15()</code> for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.
+ */
+
+void arm_correlate_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst)
+{
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0; /* temporary variables for holding input and coefficient values */
+ uint32_t j, k = 0U, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3; /* loop counter */
+ int32_t inc = 1; /* Destination address modifier */
+
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcA);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcB);
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2U * srcALen) - 1U;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1U));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcB);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcA);
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2U);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ /* The function is internally
+ * divided into three parts according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first part of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second part of the algorithm, srcBLen number of multiplications are done.
+ * In the third part of the algorithm, the multiplications decrease by one
+ * for every iteration.*/
+ /* The algorithm is implemented in three stages.
+ * The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1U;
+ blockSize2 = srcALen - (srcBLen - 1U);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[srcBlen - 1]
+ * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
+ * ....
+ * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1U;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc1 = pIn2 + (srcBLen - 1U);
+ py = pSrc1;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first loop starts here */
+ while (blockSize1 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
+ sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+ /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */
+ sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0] * y[srcBLen - 1] */
+ sum = __SMLAD(*px++, *py++, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pSrc1 - count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+ * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0U;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+ if (srcBLen >= 4U)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1] samples */
+ x0 = *__SIMD32(px);
+ /* read x[1], x[2] samples */
+ x1 = _SIMD32_OFFSET(px + 1);
+ px += 2U;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the first two inputB samples using SIMD:
+ * y[0] and y[1] */
+ c0 = *__SIMD32(py)++;
+
+ /* acc0 += x[0] * y[0] + x[1] * y[1] */
+ acc0 = __SMLAD(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[0] + x[2] * y[1] */
+ acc1 = __SMLAD(x1, c0, acc1);
+
+ /* Read x[2], x[3] */
+ x2 = *__SIMD32(px);
+
+ /* Read x[3], x[4] */
+ x3 = _SIMD32_OFFSET(px + 1);
+
+ /* acc2 += x[2] * y[0] + x[3] * y[1] */
+ acc2 = __SMLAD(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[0] + x[4] * y[1] */
+ acc3 = __SMLAD(x3, c0, acc3);
+
+ /* Read y[2] and y[3] */
+ c0 = *__SIMD32(py)++;
+
+ /* acc0 += x[2] * y[2] + x[3] * y[3] */
+ acc0 = __SMLAD(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[2] + x[4] * y[3] */
+ acc1 = __SMLAD(x3, c0, acc1);
+
+ /* Read x[4], x[5] */
+ x0 = _SIMD32_OFFSET(px + 2);
+
+ /* Read x[5], x[6] */
+ x1 = _SIMD32_OFFSET(px + 3);
+ px += 4U;
+
+ /* acc2 += x[4] * y[2] + x[5] * y[3] */
+ acc2 = __SMLAD(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[2] + x[6] * y[3] */
+ acc3 = __SMLAD(x1, c0, acc3);
+
+ } while (--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ if (k == 1U)
+ {
+ /* Read y[4] */
+ c0 = *py;
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16U;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7] */
+ x3 = *__SIMD32(px);
+ px++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLADX(x1, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ if (k == 2U)
+ {
+ /* Read y[4], y[5] */
+ c0 = *__SIMD32(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px + 1);
+ px += 2U;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLAD(x3, c0, acc2);
+ acc3 = __SMLAD(x2, c0, acc3);
+ }
+
+ if (k == 3U)
+ {
+ /* Read y[4], y[5] */
+ c0 = *__SIMD32(py)++;
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px + 1);
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLAD(x3, c0, acc2);
+ acc3 = __SMLAD(x2, c0, acc3);
+
+ c0 = (*py);
+ /* Read y[6] */
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16U;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[10] */
+ x3 = _SIMD32_OFFSET(px + 2);
+ px += 3U;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x1, c0, acc0);
+ acc1 = __SMLAD(x2, c0, acc1);
+ acc2 = __SMLADX(x2, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (acc0 >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ *pOut = (q15_t) (acc1 >> 15);
+ pOut += inc;
+
+ *pOut = (q15_t) (acc2 >> 15);
+ pOut += inc;
+
+ *pOut = (q15_t) (acc3 >> 15);
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count += 4U;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over srcBLen */
+ k = srcBLen;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * ....
+ * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+ * sum += x[srcALen-1] * y[0]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1U;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while (blockSize3 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */
+ sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+ /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */
+ sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(*px++, *py++, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0; /* temporary variables for holding input and coefficient values */
+ uint32_t j, k = 0U, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3; /* loop counter */
+ int32_t inc = 1; /* Destination address modifier */
+ q15_t a, b;
+
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcA);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcB);
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2U * srcALen) - 1U;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1U));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcB);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcA);
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2U);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ /* The function is internally
+ * divided into three parts according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first part of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second part of the algorithm, srcBLen number of multiplications are done.
+ * In the third part of the algorithm, the multiplications decrease by one
+ * for every iteration.*/
+ /* The algorithm is implemented in three stages.
+ * The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1U;
+ blockSize2 = srcALen - (srcBLen - 1U);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[srcBlen - 1]
+ * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
+ * ....
+ * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1U;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc1 = pIn2 + (srcBLen - 1U);
+ py = pSrc1;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first loop starts here */
+ while (blockSize1 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0] * y[srcBLen - 1] */
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pSrc1 - count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+ * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0U;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+ if (srcBLen >= 4U)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x0 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x1 = __PKHBT(b, a, 16);
+
+#else
+
+ x0 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x1 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px += 2U;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the first two inputB samples using SIMD:
+ * y[0] and y[1] */
+ a = *py;
+ b = *(py + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc0 += x[0] * y[0] + x[1] * y[1] */
+ acc0 = __SMLAD(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[0] + x[2] * y[1] */
+ acc1 = __SMLAD(x1, c0, acc1);
+
+ /* Read x[2], x[3], x[4] */
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x2 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x3 = __PKHBT(b, a, 16);
+
+#else
+
+ x2 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x3 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc2 += x[2] * y[0] + x[3] * y[1] */
+ acc2 = __SMLAD(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[0] + x[4] * y[1] */
+ acc3 = __SMLAD(x3, c0, acc3);
+
+ /* Read y[2] and y[3] */
+ a = *(py + 2);
+ b = *(py + 3);
+
+ py += 4U;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc0 += x[2] * y[2] + x[3] * y[3] */
+ acc0 = __SMLAD(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[2] + x[4] * y[3] */
+ acc1 = __SMLAD(x3, c0, acc1);
+
+ /* Read x[4], x[5], x[6] */
+ a = *(px + 2);
+ b = *(px + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x0 = __PKHBT(a, b, 16);
+ a = *(px + 4);
+ x1 = __PKHBT(b, a, 16);
+
+#else
+
+ x0 = __PKHBT(b, a, 16);
+ a = *(px + 4);
+ x1 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px += 4U;
+
+ /* acc2 += x[4] * y[2] + x[5] * y[3] */
+ acc2 = __SMLAD(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[2] + x[6] * y[3] */
+ acc3 = __SMLAD(x1, c0, acc3);
+
+ } while (--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ if (k == 1U)
+ {
+ /* Read y[4] */
+ c0 = *py;
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16U;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7] */
+ a = *px;
+ b = *(px + 1);
+
+ px++;;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLADX(x1, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ if (k == 2U)
+ {
+ /* Read y[4], y[5] */
+ a = *py;
+ b = *(py + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7], x[8], x[9] */
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(b, a, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px += 2U;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLAD(x3, c0, acc2);
+ acc3 = __SMLAD(x2, c0, acc3);
+ }
+
+ if (k == 3U)
+ {
+ /* Read y[4], y[5] */
+ a = *py;
+ b = *(py + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ py += 2U;
+
+ /* Read x[7], x[8], x[9] */
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(b, a, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLAD(x3, c0, acc2);
+ acc3 = __SMLAD(x2, c0, acc3);
+
+ c0 = (*py);
+ /* Read y[6] */
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16U;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[10] */
+ b = *(px + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px += 3U;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x1, c0, acc0);
+ acc1 = __SMLAD(x2, c0, acc1);
+ acc2 = __SMLADX(x2, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (acc0 >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ *pOut = (q15_t) (acc1 >> 15);
+ pOut += inc;
+
+ *pOut = (q15_t) (acc2 >> 15);
+ pOut += inc;
+
+ *pOut = (q15_t) (acc3 >> 15);
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count += 4U;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over srcBLen */
+ k = srcBLen;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * ....
+ * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+ * sum += x[srcALen-1] * y[0]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1U;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while (blockSize3 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q31.c b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q31.c
new file mode 100644
index 0000000..53373ac
--- /dev/null
+++ b/mcu_sdk/gd32f103/rk_eFire/Board/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q31.c
@@ -0,0 +1,600 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_correlate_fast_q31.c
+ * Description: Fast Q31 Correlation
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.
+ * These intermediate results are accumulated in a 32-bit register in 2.30 format.
+ * Finally, the accumulator is saturated and converted to a 1.31 result.
+ *
+ * \par
+ * The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result.
+ * In order to avoid overflows completely the input signals must be scaled down.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.
+ *
+ * \par
+ * See <code>arm_correlate_q31()</code> for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.
+ */
+
+void arm_correlate_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst)
+{
+ q31_t *pIn1; /* inputA pointer */
+ q31_t *pIn2; /* inputB pointer */
+ q31_t *pOut = pDst; /* output pointer */
+ q31_t *px; /* Intermediate inputA pointer */
+ q31_t *py; /* Intermediate inputB pointer */
+ q31_t *pSrc1; /* Intermediate pointers */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
+ q31_t x0, x1, x2, x3, c0; /* temporary variables for holding input and coefficient values */
+ uint32_t j, k = 0U, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3; /* loop counter */
+ int32_t inc = 1; /* Destination address modifier */
+
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcA);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcB);
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2U * srcALen) - 1U;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1U));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcB);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcA);
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2U);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ /* The function is internally
+ * divided into three parts according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first part of the