From 80686e6bc4cb17e9d856647084725203fa63ebe6 Mon Sep 17 00:00:00 2001
From: guowenxue <guowenxue@gmail.com>
Date: Mon, 19 Aug 2024 16:47:42 +0800
Subject: [PATCH] Add LCD API examples
---
hal/modules/w25qflash.c | 831 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 831 insertions(+), 0 deletions(-)
diff --git a/hal/modules/w25qflash.c b/hal/modules/w25qflash.c
new file mode 100644
index 0000000..5623718
--- /dev/null
+++ b/hal/modules/w25qflash.c
@@ -0,0 +1,831 @@
+/*********************************************************************************
+ * Copyright: (C) 2023 LingYun IoT System Studio
+ * All rights reserved.
+ *
+ * Filename: at24c.c
+ * Description: This file is AT24Cxx EEPROM code
+ *
+ * Version: 1.0.0(10/08/23)
+ * Author: Guo Wenxue <guowenxue@gmail.com>
+ * ChangeLog: 1, Release initial version on "10/08/23 17:52:00"
+ *
+ * Pin connection:
+ * W25QXX Raspberry Pi 40Pin
+ * VCC <---> Pin#1 (3.3V)
+ * CS <---> Pin#24(CS)
+ * DO <---> Pin#21(MISO)
+ * GND <---> Pin#9 (GND)
+ * CLK <---> Pin#23(SCLK)
+ * DI <---> Pin#19(MOSI)
+ *
+ * /boot/config.txt:
+ * dtparam=spi=on
+ *
+ ********************************************************************************/
+
+
+
+#include <stdint.h>
+#include <unistd.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <errno.h>
+#include <getopt.h>
+#include <fcntl.h>
+#include <time.h>
+#include <sys/ioctl.h>
+#include <linux/ioctl.h>
+#include <sys/stat.h>
+#include <linux/types.h>
+#include <linux/spi/spidev.h>
+
+#include "w25qflash.h"
+
+#ifdef _W25QXX_DEBUG
+#define spinor_print(format,args...) printf(format, ##args)
+#else
+#define spinor_print(format,args...) do{} while(0)
+#endif
+
+#define spinor_Delay(delay) usleep(delay*1000)
+
+/*+-----------------------+
+ *| Entry Functions |
+ *+-----------------------+*/
+
+void dump_buf(const char *prompt, char *buf, size_t len);
+
+int main (int argc, char **argv)
+{
+ spinor_test();
+
+ return 0;
+}
+
+
+/*+-----------------------+
+ *| SPI API Functions |
+ *+-----------------------+*/
+
+#define SPI_DEV "/dev/spidev0" /* SPI device 0 */
+#define SPI_CS0 0 /* SPI CS0 */
+#define SPI_CS1 1 /* SPI CS1 */
+#define SPI_BITS 8
+#define SPI_MODE 0 /* (SPI_CPHA|SPI_CPOL) */
+#define SPI_SPEED 500000
+
+#define SPI_DUMMY_BYTE 0xA5
+
+int spi_lowlevel_init(spi_bus_t *spi)
+{
+ uint8_t bits = SPI_BITS;
+ uint32_t speed = SPI_SPEED;
+ uint32_t mode = SPI_MODE;
+ uint32_t request;
+ char dev[32];
+ int rv = 0;
+
+ snprintf(dev, sizeof(dev), "%s.%d", SPI_DEV, spi->cs);
+
+ spi->hspi = open(dev, O_RDWR);
+ if (spi->hspi < 0)
+ {
+ printf("ERROR: open device %s failure: %s\r\n", dev, strerror(errno));
+ return -2;
+ }
+ printf("Open '%s' for W25Q SPI norflash\n", dev);
+
+ /*
+ * spi mode
+ */
+ request = mode;
+ if( ioctl(spi->hspi, SPI_IOC_WR_MODE32, &mode) < 0 )
+ {
+ printf("ERROR: can't set spi mode\n");
+ rv = -3;
+ goto cleanup;
+ }
+
+ if( ioctl(spi->hspi, SPI_IOC_RD_MODE32, &mode) < 0 )
+ {
+ printf("ERROR: can't get spi mode\n");
+ rv = -3;
+ goto cleanup;
+ }
+
+ if (request != mode)
+ {
+ printf("WARNING: device does not support requested mode 0x%x\n", request);
+ }
+
+ /*
+ * bits per word
+ */
+ if( ioctl(spi->hspi, SPI_IOC_WR_BITS_PER_WORD, &bits) < 0 )
+ {
+ printf("ERROR: can't set bits per word\n");
+ rv = -3;
+ goto cleanup;
+ }
+
+ if( ioctl(spi->hspi, SPI_IOC_RD_BITS_PER_WORD, &bits) < 0 )
+ {
+ printf("ERROR: can't get bits per word\n");
+ rv = -3;
+ goto cleanup;
+ }
+
+ /*
+ * max speed hz
+ */
+ if( ioctl(spi->hspi, SPI_IOC_WR_MAX_SPEED_HZ, &speed) < 0 )
+ {
+ printf("ERROR: can't set max speed hz\n");
+ rv = -3;
+ goto cleanup;
+ }
+
+ if( ioctl(spi->hspi, SPI_IOC_RD_MAX_SPEED_HZ, &speed) < 0 )
+ {
+ printf("ERROR: can't get max speed hz\n");
+ rv = -3;
+ goto cleanup;
+ }
+
+ printf("spi mode: 0x%x\n", mode);
+ printf("bits per word: %u\n", bits);
+ printf("max speed: %u Hz (%u kHz)\n", speed, speed/1000);
+
+cleanup:
+ if( rv < 0 )
+ {
+ close(spi->hspi);
+ spi->hspi = -1;
+ }
+
+ return rv;
+}
+
+void spi_cs_enable(spi_bus_t *spi)
+{
+ /*
+ * No need set CS in Linux because the device name /dev/spi0.0
+ * will choose the first slave device, second slave is spi0.1
+ */
+ (void)0;
+}
+
+void spi_cs_disable(spi_bus_t *spi)
+{
+ (void)0;
+}
+
+void spi_xcmd(spi_bus_t *spi, uint8_t command)
+{
+ uint8_t rxbyte;
+ struct spi_ioc_transfer tr = {
+ .tx_buf = (unsigned long)&command,
+ .rx_buf = (unsigned long)&rxbyte,
+ .len = 1,
+ .delay_usecs = 0,
+ .speed_hz = SPI_SPEED,
+ .bits_per_word = SPI_BITS,
+ };
+
+ if( ioctl(spi->hspi, SPI_IOC_MESSAGE(1), &tr) < 0 )
+ {
+ printf("ERROR: can't send spi message:%s\n", strerror(errno));
+ }
+
+ return;
+}
+
+void spi_xfer(spi_bus_t *spi, uint8_t *send_buf, uint8_t *recv_buf, int bytes)
+{
+ struct spi_ioc_transfer tr = {
+ .tx_buf = (unsigned long)send_buf,
+ .rx_buf = (unsigned long)recv_buf,
+ .len = bytes,
+ .delay_usecs = 0,
+ .speed_hz = SPI_SPEED,
+ .bits_per_word = SPI_BITS,
+ };
+
+ if( ioctl(spi->hspi, SPI_IOC_MESSAGE(1), &tr) < 0 )
+ {
+ printf("ERROR: can't send spi message:%s\n", strerror(errno));
+ }
+
+ return;
+}
+
+#define SPI_INFO(_hspi, _cs) {\
+ .hspi = _hspi, \
+ .hspi = _cs, \
+ .select = spi_cs_enable, \
+ .deselect = spi_cs_disable, \
+ .xcmd = spi_xcmd, \
+ .xfer = spi_xfer, \
+}
+
+static spi_bus_t spinor_spi = SPI_INFO(-1, SPI_CS0);
+
+
+/*+-----------------------+
+ *| W25Q SPI Norflash ID |
+ *+-----------------------+*/
+
+#define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0]))
+
+/* JEDEC ID the 3rd bytes is the storage capacity */
+#pragma GCC diagnostic ignored "-Wshift-count-overflow"
+#define CAPCITY_ID(id) (1UL<<(id&0xFF))
+#define NOR_INFO(_name, _jedec_id) \
+ .name = _name, \
+.jedec_id = _jedec_id, \
+.block_size = W25Q_BLKSIZE, \
+.sector_size= W25Q_SECSIZE, \
+.page_size = W25Q_PAGSIZE, \
+.capacity = CAPCITY_ID(_jedec_id), \
+.n_blocks = CAPCITY_ID(_jedec_id)/W25Q_BLKSIZE, \
+.n_sectors = CAPCITY_ID(_jedec_id)/W25Q_SECSIZE, \
+.n_pages = CAPCITY_ID(_jedec_id)/W25Q_PAGSIZE, \
+
+static flash_t flash_ids[] = {
+ { NOR_INFO("W25Q512", 0xef4020) },
+ { NOR_INFO("W25Q256", 0xef4019) },
+ { NOR_INFO("W25Q128", 0xef4018) },
+ { NOR_INFO("W25Q64", 0xef4017) },
+ { NOR_INFO("W25Q32", 0xef4016) },
+ { NOR_INFO("W25Q16", 0xef4015) },
+ { NOR_INFO("W25Q80", 0xef4014) },
+ { NOR_INFO("W25Q40", 0xef4013) },
+ { NOR_INFO("W25Q20", 0xef4012) },
+ { NOR_INFO("W25Q10", 0xef4011) },
+};
+
+/*+-------------------------------+
+ *| SPI Norflash HighLevel API |
+ *+-------------------------------+*/
+
+/* SPI Norflash API test function */
+void spinor_test(void)
+{
+ spinor_t spinor;
+ int i;
+ uint8_t buf[W25Q_PAGSIZE*2];
+
+ if( spinor_init(&spinor) < 0 )
+ return ;
+
+ //spinor_erase_chip(&spinor);
+ //spinor_erase_block(&spinor, 1, W25Q_BLKSIZE);
+ spinor_erase_sector(&spinor, 1, W25Q_SECSIZE);
+
+ memset(buf, 0, sizeof(buf));
+ spinor_read(&spinor, 0, buf, sizeof(buf));
+ dump_buf("<<<Read data after erase:\n", (char *)buf, sizeof(buf));
+
+ /* Read/Write data test on address not page align */
+ for(i=0; i<sizeof(buf); i++)
+ buf[i] = i;
+ spinor_write(&spinor, 16, buf, W25Q_PAGSIZE);
+
+ memset(buf, 0, sizeof(buf));
+ spinor_read(&spinor, 0, buf, W25Q_PAGSIZE*2);
+ dump_buf("<<<Read data after write:\n", (char *)buf, sizeof(buf));
+
+ return ;
+}
+
+/* Initial SPI and detect the flash chip */
+int spinor_init(spinor_t *spinor)
+{
+ int i, found = 0;
+ uint32_t jedec_id;
+
+ spinor->lock = 0;
+ spinor->spi = &spinor_spi;
+
+ /* Initial SPI bus */
+ if( spi_lowlevel_init(spinor->spi) < 0 )
+ {
+ printf("ERROR: SPI lowlevel init failed\r\n");
+ return -2;
+ }
+
+ /* Read JEDEC ID to find the flash */
+ jedec_id = spinor_read_jedecid(spinor->spi);
+ for(i=0; i<ARRAY_SIZE(flash_ids); i++)
+ {
+ if(flash_ids[i].jedec_id == jedec_id)
+ {
+ found = 1;
+ spinor->flash = &flash_ids[i];
+ break;
+ }
+ }
+
+ if( !found )
+ {
+ printf("ERROR: W25Q Norflash JEDEC ID detect failed!\r\n");
+ return -3;
+ }
+
+ printf("Norflash %s ID[0x%x] detected, capacity %llu KB, %u blocks, %u pages.\r\n",
+ spinor->flash->name, jedec_id, spinor->flash->capacity>>10,
+ spinor->flash->n_blocks, spinor->flash->n_pages);
+
+ return 0;
+}
+
+/* Description: Erase whole flash chip.
+ * Reference : P60, 8.2.32 Chip Erase (C7h / 60h)
+ */
+int spinor_erase_chip(spinor_t *spinor)
+{
+ spi_bus_t *spi = spinor->spi;
+ uint32_t timeout;
+ uint8_t regval;
+
+ while (spinor->lock == 1)
+ spinor_Delay(1);
+
+ spinor->lock = 1;
+ spi->select(spi);
+
+ spinor_print("Norflash EraseChip Begin...\r\n");
+
+ /* Wait for flash ready */
+ spinor_WaitForReady(spi);
+
+ /* Write Enable */
+ spinor_write_enable(spi);
+
+ /* Entire flash erase */
+ spi->xcmd(spi, SPINOR_OP_CHIP_ERASE);
+
+ /* Wait for erase finish */
+ timeout = 0;
+ while (1)
+ {
+ if (timeout == 300)
+ {
+ spinor_print("\r\nErase entire flash timeout\r\n");
+ break;
+ }
+
+ regval = spinor_read_status_reg(spi, SPINOR_OP_RDSR1);
+ if( !(regval&0x1) )
+ {
+ spinor_print("\r\nNorflash EraseChip done.\r\n");
+ break;
+ }
+
+#ifdef _W25QXX_DEBUG
+ printf(".");
+ spinor_Delay(1000);
+#endif
+ }
+
+ printf("\n");
+
+ spi->deselect(spi);
+ spinor->lock = 0;
+
+ return 0;
+}
+
+/* Description: Erase blocks by 64KiB,
+ * Reference : P59, 8.2.31 64KB Block Erase with 4-Byte Address (DCh)
+ * @address is the erase start physical address, which can be not block alignment such as 0x10001.
+ * @size is the erase size, which can be larger than a block such as 4097, and it will erase 2 blocks;
+ */
+int spinor_erase_block(spinor_t *spinor, uint32_t address, uint32_t size)
+{
+ spi_bus_t *spi = spinor->spi;
+ flash_t *flash = spinor->flash;
+ uint32_t block, first, last;
+ uint32_t addr;
+ uint8_t buf[5];
+ int bytes = 0;
+
+ while (spinor->lock == 1)
+ spinor_Delay(1);
+
+ spinor->lock = 1;
+ spi->select(spi);
+
+ spinor_print("Norflash Erase %d Bytes Block@0x%x Begin...\r\n", size, address);
+
+ /* find first and last erase block */
+ first = address / flash->block_size;
+ last = (address+size-1) / flash->block_size;
+
+ /* start erase all the blocks */
+ for( block=first; block<=last; block++)
+ {
+ addr = block * flash->sector_size;
+ spinor_print("Norflash Erase Block@%x ...\r\n", addr);
+
+ spinor_WaitForReady(spi);
+ spinor_write_enable(spi);
+
+ if (spinor->flash->n_blocks >= 512 ) /* larger than W25Q256 */
+ {
+ buf[bytes++] = SPINOR_OP_BE_4K_4B;
+ buf[bytes++] = (addr & 0xFF000000) >> 24;
+ }
+ else
+ {
+ buf[bytes++] = SPINOR_OP_BE_4K;
+ }
+ buf[bytes++] = (addr & 0xFF0000) >> 16 ;
+ buf[bytes++] = (addr & 0xFF00) >> 8 ;
+ buf[bytes++] = (addr & 0xFF);
+
+ spi->xfer(spi, buf, NULL, bytes);
+
+ spinor_WaitForReady(spi);
+ }
+
+ spinor_print("Norflash EraseBlock@0x%x done.\r\n", address);
+
+ spi->deselect(spi);
+ spinor->lock = 0;
+
+ return 0;
+}
+
+/* Description: Erase sectors by 4KiB
+ * Reference : P56, 8.2.28 Sector Erase with 4-Byte Address (21h)
+ * @address is the erase start physical address, which can be not sector alignment such as 0x1001.
+ * @size is the erase size, which can be larger than a sector such as 4097, and it will erase 2 sectors;
+ */
+int spinor_erase_sector(spinor_t *spinor, uint32_t address, uint32_t size)
+{
+ spi_bus_t *spi = spinor->spi;
+ flash_t *flash = spinor->flash;
+ uint32_t sector, first, last;
+ uint32_t addr;
+ uint8_t buf[5];
+ int bytes = 0;
+
+ while (spinor->lock == 1)
+ spinor_Delay(1);
+
+ spinor->lock = 1;
+ spi->select(spi);
+
+ spinor_print("Norflash Erase %d Bytes Sector@0x%x Begin...\r\n", size, address);
+
+ /* find first and last erase sector */
+ first = address / flash->sector_size;
+ last = (address+size-1) / flash->sector_size;
+
+ /* start erase all the sectors */
+ for( sector=first; sector<=last; sector++)
+ {
+ addr = sector * flash->sector_size;
+ spinor_print("Norflash Erase Sector@%x ...\r\n", addr);
+
+ spinor_WaitForReady(spi);
+ spinor_write_enable(spi);
+
+ if (spinor->flash->n_blocks >= 512 ) /* larger than W25Q256 */
+ {
+ buf[bytes++] = SPINOR_OP_SE_4B;
+ buf[bytes++] = (addr & 0xFF000000) >> 24;
+ }
+ else
+ {
+ buf[bytes++] = SPINOR_OP_SE;
+ }
+ buf[bytes++] = (addr & 0xFF0000) >> 16 ;
+ buf[bytes++] = (addr & 0xFF00) >> 8 ;
+ buf[bytes++] = (addr & 0xFF);
+
+ spi->xfer(spi, buf, NULL, bytes);
+
+ spinor_WaitForReady(spi);
+ }
+
+ spinor_print("Norflash EraseSector@0x%x done.\r\n", address);
+
+ spi->deselect(spi);
+ spinor->lock = 0;
+
+ return 0;
+}
+
+/* Description: Page random write by 256B
+ * @addr is the write start physical address, which can be not page alignment such as 0x101.
+ * @size is the write size, which can be larger than a page such as 257, and it will write 2 pages;
+ */
+int spinor_write(spinor_t *spinor, uint32_t address, uint8_t *data, uint32_t size)
+{
+ spi_bus_t *spi = spinor->spi;
+ flash_t *flash = spinor->flash;
+ uint32_t page, first, last;
+ uint32_t addr, ofset, len;
+ uint8_t buf[W25Q_PAGSIZE+OVERHEAD_SIZE];
+ int bytes = 0;
+
+ if( address+size > spinor->flash->capacity )
+ return -1;
+
+ while (spinor->lock == 1)
+ spinor_Delay(1);
+
+ spinor->lock = 1;
+ spi->select(spi);
+
+ spinor_print("Norflash Write %d Bytes to addr@0x%x Begin...\r\n", size, address);
+
+ /* find first and last write page */
+ first = address / flash->page_size;
+ last = (address+size-1) / flash->page_size;
+
+ /* address in page and offset in buffer */
+ addr = address;
+ ofset = 0;
+
+ /* start write all the pages */
+ for( page=first; page<=last; page++)
+ {
+ len = flash->page_size - (addr%flash->page_size);
+ len = len > size ? size : len;
+
+ spinor_print("Norflash write addr@0x%x, %u bytes\r\n", addr, len);
+
+ spinor_WaitForReady(spi);
+ spinor_write_enable(spi);
+
+ bytes = 0;
+ if (spinor->flash->n_blocks >= 512 )
+ {
+ buf[bytes++] = SPINOR_OP_PP_4B;
+ buf[bytes++] = (addr & 0xFF000000) >> 24;
+ }
+ else
+ {
+ buf[bytes++] = SPINOR_OP_PP;
+ }
+ buf[bytes++] = (addr & 0xFF0000) >> 16 ;
+ buf[bytes++] = (addr & 0xFF00) >> 8 ;
+ buf[bytes++] = (addr & 0xFF);
+
+ /* send command and data */
+ memcpy(&buf[bytes], data+ofset, len);
+ bytes += len;
+
+ spi->xfer(spi, buf, NULL, bytes);
+
+ spinor_WaitForReady(spi);
+
+ addr += len;
+ ofset += len;
+ size -= len;
+ }
+
+ spinor_print("Norflash WriteByte@0x%x done.\r\n", address);
+
+ spi->deselect(spi);
+ spinor->lock = 0;
+
+ return 0;
+}
+
+/* Description: The Fast Read instruction can read the entire memory chip.
+ * Reference : P41, 8.2.13 Fast Read with 4-Byte Address (0Ch)
+ * @address is the read start physical address, which can be not page alignment such as 0x101.
+ * @size is the read size, which can be larger than a page such as 257, and it will read 2 pages;
+ */
+int spinor_read(spinor_t *spinor, uint32_t address, uint8_t *data, uint32_t size)
+{
+ spi_bus_t *spi = spinor->spi;
+ uint8_t buf[W25Q_PAGSIZE+OVERHEAD_SIZE];
+ int bytes = 0;
+ int ofset;
+ uint32_t addr = address;
+
+ if( address+size > spinor->flash->capacity )
+ return -1;
+
+ while (spinor->lock == 1)
+ spinor_Delay(1);
+
+ spinor->lock = 1;
+ spi->select(spi);
+
+ spinor_print("Norflash Read %d Bytes from addr@0x%x Begin...\r\n", size, address);
+
+ while( size > 0 )
+ {
+ bytes = size>W25Q_PAGSIZE ? W25Q_PAGSIZE : size;
+ memset(buf, SPI_DUMMY_BYTE, sizeof(buf));
+
+ spinor_print("Norflash read addr@0x%x, %d bytes\r\n", addr, bytes);
+
+ /* send instruction and address */
+ ofset = 0;
+ if (spinor->flash->n_blocks >= 512 )
+ {
+ buf[ofset++] = SPINOR_OP_READ_FAST_4B;
+ buf[ofset++] = (addr & 0xFF000000) >> 24;
+ }
+ else
+ {
+ buf[ofset++] = SPINOR_OP_READ_FAST;
+ }
+ buf[ofset++] = (addr & 0xFF0000) >> 16 ;
+ buf[ofset++] = (addr & 0xFF00) >> 8 ;
+ buf[ofset++] = (addr & 0xFF);
+
+ ofset += 1; /* Skip first dummy byte */
+
+ /* Send command and read data out */
+ spi->xfer(spi, buf, buf, ofset+bytes);
+
+ memcpy(data, &buf[ofset], bytes);
+ size -= bytes;
+ addr += bytes;
+ data += bytes;
+ }
+
+ spinor_print("Norflash ReadBytes@0x%x done.\r\n", address);
+
+ spi->deselect(spi);
+ spinor->lock = 0;
+
+ return 0;
+}
+
+/*+-------------------------------+
+ *| SPI Norflash LowLevel API |
+ *+-------------------------------+*/
+
+/* Description: Read the chipset UNIQUE ID.
+ * Reference : P68, 8.2.40 Read Unique ID Number (4Bh)
+ */
+int spinor_read_uniqid(spi_bus_t *spi, uint8_t *uniq_id)
+{
+ uint8_t i;
+ uint8_t buf[13]; /* Instruction(1B) + Dummy(4B) + UID(8B)*/
+
+ if( !uniq_id )
+ return -1;
+
+ /* Enable SPI chip select */
+ spi->select(spi);
+
+ /* Wait for flash ready */
+ spinor_WaitForReady(spi);
+
+ buf[0] = SPINOR_OP_RDUID;
+ spi->xfer(spi, buf, buf, sizeof(buf));
+
+ /* Skip 4 bytes dummy bytes */
+ for (i=0; i<8; i++)
+ {
+ uniq_id[i] = buf[5+i];
+ }
+
+ /* Disable SPI chip select */
+ spi->deselect(spi);
+
+ return 0;
+}
+
+/* Description: Read the chipset JEDEC ID.
+ * Reference : P69, 8.2.41 Read JEDEC ID (9Fh)
+ */
+uint32_t spinor_read_jedecid(spi_bus_t *spi)
+{
+ uint32_t jedec_id = 0x0;
+ uint8_t buf[4];
+
+ /* Enable SPI chip select */
+ spi->select(spi);
+
+ /* Wait for flash ready */
+ spinor_WaitForReady(spi);
+
+ /* Send Read JEDEC ID command 0x9F */
+ buf[0] = SPINOR_OP_RDID;
+ spi->xfer(spi, buf, buf, sizeof(buf));
+ jedec_id = (buf[1] << 16) | (buf[2] << 8) | buf[3];
+
+ /* Disable SPI chip select */
+ spi->deselect(spi);
+
+ return jedec_id;
+}
+
+/* Description: Write Enable
+ * Reference : P31, 8.2.1 Write Enable (06h)
+ */
+void spinor_write_enable(spi_bus_t *spi)
+{
+ spi->xcmd(spi, SPINOR_OP_WREN);
+
+ spinor_WaitForReady(spi);
+}
+
+/* Description: Write Disable
+ * Reference : P32, 8.2.3 Write Disable (04h)
+ */
+void spinor_write_disable(spi_bus_t *spi)
+{
+ spi->xcmd(spi, SPINOR_OP_WRDI);
+
+ spinor_WaitForReady(spi);
+}
+
+/* Description: Read Status Register
+ * Reference : P32, 8.2.4 Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h)
+ */
+uint8_t spinor_read_status_reg(spi_bus_t *spi, uint8_t reg)
+{
+ uint8_t buf[2];
+
+ buf[0] = reg;
+ spi->xfer(spi, buf, buf, sizeof(buf));
+
+ return buf[1];
+}
+
+/* Description: Write Status Register
+ * Reference : P33, 8.2.5 Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h)
+ */
+void spinor_write_status_reg(spi_bus_t *spi, uint8_t reg, uint8_t value)
+{
+ uint8_t buf[2];
+
+ buf[0] = reg;
+ buf[1] = value;
+ spi->xfer(spi, buf, buf, sizeof(buf));
+}
+
+/* Description: Wait flash program/erase finished by read Status Register for BUSY bit
+ * Reference : P15, 7.1 Status Registers
+ */
+void spinor_WaitForReady(spi_bus_t *spi)
+{
+ uint8_t regval;
+
+ do
+ {
+ regval = spinor_read_status_reg(spi, SPINOR_OP_RDSR1);
+ } while ((regval & 0x01) == 0x01);
+}
+
+/*+----------------------+
+ *| Misc functions |
+ *+----------------------+*/
+
+void dump_buf(const char *prompt, char *buf, size_t len)
+{
+ char line[256];
+ size_t i, j;
+ int offset;
+
+ if( prompt )
+ {
+ printf("%s", prompt);
+ }
+
+ for(i = 0; i < len; i += 16)
+ {
+ offset = snprintf(line, sizeof(line), "%08zx: ", i);
+
+ /* Print hex representation */
+ for (j = 0; j < 16; j++)
+ {
+ if (i + j < len)
+ offset += snprintf(line + offset, sizeof(line) - offset, "%02x ", buf[i + j]);
+ else
+ offset += snprintf(line + offset, sizeof(line) - offset, " ");
+ }
+
+ offset += snprintf(line + offset, sizeof(line) - offset, " ");
+
+ /* Print ASCII representation */
+ for (j = 0; j < 16; j++)
+ {
+ if (i + j < len)
+ {
+ unsigned char c = buf[i + j];
+ offset += snprintf(line + offset, sizeof(line) - offset, "%c", (c >= 32 && c <= 126) ? c : '.');
+ }
+ else
+ {
+ offset += snprintf(line + offset, sizeof(line) - offset, " ");
+ }
+ }
+
+ /* Print the line */
+ printf("%s\n", line);
+ }
+}
--
Gitblit v1.9.1