From 7800e82e4b6b59a46e648c93f488636b0a1555fc Mon Sep 17 00:00:00 2001
From: guowenxue <guowenxue@gmail.com>
Date: Thu, 30 Mar 2023 10:57:37 +0800
Subject: [PATCH] Add lf-5.15.71-2.2.0 patch for u-boot and linux
---
bsp/bootloader/patch/uboot-imx-lf-5.10.52-2.1.0.patch | 62 +++++++++++++++---------------
1 files changed, 31 insertions(+), 31 deletions(-)
diff --git a/bsp/bootloader/patch/uboot-imx-lf-5.10.52-2.1.0.patch b/bsp/bootloader/patch/uboot-imx-lf-5.10.52-2.1.0.patch
index 7444044..140def7 100644
--- a/bsp/bootloader/patch/uboot-imx-lf-5.10.52-2.1.0.patch
+++ b/bsp/bootloader/patch/uboot-imx-lf-5.10.52-2.1.0.patch
@@ -41,7 +41,7 @@
+ phy-reset-post-delay = <15>;
status = "okay";
};
-
+
@@ -91,14 +93,17 @@
pinctrl-0 = <&pinctrl_enet2>;
phy-mode = "rmii";
@@ -50,11 +50,11 @@
+ phy-reset-duration = <50>;
+ phy-reset-post-delay = <15>;
status = "okay";
-
+
mdio {
#address-cells = <1>;
#size-cells = <0>;
-
+
- ethphy0: ethernet-phy@2 {
- reg = <2>;
+ ethphy0: ethernet-phy@0 {
@@ -68,16 +68,16 @@
pinctrl-0 = <&pinctrl_lcdif_dat
- &pinctrl_lcdif_ctrl>;
+ &pinctrl_lcdif_ctrl>;
-
+
display = <&display0>;
status = "okay";
-
+
display0: display@0 {
- bits-per-pixel = <24>;
- bus-width = <24>;
+ bits-per-pixel = <16>;
+ bus-width = <16>;
-
+
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
@@ -99,11 +99,11 @@
+ vback-porch = <32>;
+ vfront-porch = <13>;
+ vsync-len = <3>;
-
+
hsync-active = <0>;
vsync-active = <0>;
@@ -284,6 +289,40 @@
-
+
&iomuxc {
pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_extgpio>;
@@ -140,7 +140,7 @@
+ MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x17059 /* 40# GPIO */
+ >;
+ };
-
+
pinctrl_csi1: csi1grp {
fsl,pins = <
@@ -306,12 +345,13 @@
@@ -160,7 +160,7 @@
+ MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x10B0 /* ENET1 RESET */
>;
};
-
+
@@ -321,12 +361,13 @@
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
@@ -178,9 +178,9 @@
+ MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x10B0 /* ENET2 RESET */
>;
};
-
+
@@ -367,41 +408,33 @@
-
+
pinctrl_lcdif_dat: lcdifdatgrp {
fsl,pins = <
- MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
@@ -225,7 +225,7 @@
+ MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
>;
};
-
+
pinctrl_lcdif_ctrl: lcdifctrlgrp {
fsl,pins = <
- MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
@@ -241,7 +241,7 @@
+ MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
>;
};
-
+
@@ -409,8 +442,8 @@
fsl,pins = <
MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
@@ -264,14 +264,14 @@
- MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059
>;
};
-
+
pinctrl_pwm1: pwm1grp {
fsl,pins = <
- MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
+ MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
>;
};
-
+
@@ -448,7 +480,6 @@
fsl,pins = <
MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1
@@ -281,7 +281,7 @@
>;
};
@@ -486,22 +517,20 @@
-
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
@@ -301,7 +301,7 @@
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
>;
};
-
+
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
@@ -312,7 +312,7 @@
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
@@ -512,8 +541,8 @@
-
+
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
@@ -323,7 +323,7 @@
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
@@ -523,8 +552,8 @@
-
+
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
@@ -334,7 +334,7 @@
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
@@ -534,8 +563,8 @@
-
+
pinctrl_usdhc2_8bit: usdhc2grp_8bit {
fsl,pins = <
- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
@@ -345,7 +345,7 @@
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
@@ -549,8 +578,8 @@
-
+
pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz {
fsl,pins = <
- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
@@ -356,7 +356,7 @@
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
@@ -564,8 +593,8 @@
-
+
pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz {
fsl,pins = <
- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
@@ -371,7 +371,7 @@
+++ uboot-imx-lf-5.10.52-2.1.0/arch/arm/dts/Makefile 2022-06-30 20:28:15.839187950 +0800
@@ -779,6 +779,7 @@
imx6ul-pico-pi.dtb
-
+
dtb-$(CONFIG_MX6ULL) += \
+ igkboard.dtb \
imx6ull-14x14-ddr3-val.dtb \
@@ -383,7 +383,7 @@
@@ -158,6 +158,16 @@
prompt "MX6 board select"
optional
-
+
+config TARGET_LINGYUN_IGKBOARD
+ bool "LingYun IoT Gateway Kits Board(IGKBoard)"
+ depends on MX6ULL
@@ -401,8 +401,8 @@
source "board/wandboard/Kconfig"
source "board/warp/Kconfig"
source "board/BuR/brppt2/Kconfig"
-+source "board/lingyun/igkboard/Kconfig"
-
++source "board/lingyun/igkboard/Kconfig"
+
endif
diff -Nuar -x lingyun.bmp uboot-imx/board/lingyun/igkboard/igkboard.c uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/igkboard.c
--- uboot-imx/board/lingyun/igkboard/igkboard.c 1970-01-01 08:00:00.000000000 +0800
@@ -1459,13 +1459,13 @@
@@ -182,6 +182,9 @@
{
int result;
-
+
+ /* add Soft Reset the PHY by guowenxue, 2021.11.14 */
+ phy_reset(phydev);
+
if (phydev->autoneg != AUTONEG_ENABLE)
return genphy_setup_forced(phydev);
-
+
diff -Nuar -x lingyun.bmp uboot-imx/include/configs/igkboard.h uboot-imx-lf-5.10.52-2.1.0/include/configs/igkboard.h
--- uboot-imx/include/configs/igkboard.h 1970-01-01 08:00:00.000000000 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/include/configs/igkboard.h 2022-06-30 20:28:15.839187950 +0800
@@ -1768,10 +1768,10 @@
@@ -263,6 +263,9 @@
CROSS_COMPILE ?=
endif
-
+
+ARCH=arm
+CROSS_COMPILE?=/opt/buildroot/cortexA7/bin/arm-linux-
+
KCONFIG_CONFIG ?= .config
export KCONFIG_CONFIG
-
+
--
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