From ddb843b28a032e43d7f88171ddbac30432022846 Mon Sep 17 00:00:00 2001
From: guowenxue <guowenxue@gmail.com>
Date: Thu, 06 Oct 2022 14:46:21 +0800
Subject: [PATCH] update meta-igkboard for honister and test okay
---
yocto/honister/meta-igkboard/recipes-bsp/u-boot/files/uboot-imx-igkboard.patch | 1727 +++++++++++++++++++++++++++++++++++++++++++++++++++++------
1 files changed, 1,543 insertions(+), 184 deletions(-)
diff --git a/yocto/honister/meta-igkboard/recipes-bsp/u-boot/files/uboot-imx-igkboard.patch b/yocto/honister/meta-igkboard/recipes-bsp/u-boot/files/uboot-imx-igkboard.patch
index 3c02384..7444044 100644
--- a/yocto/honister/meta-igkboard/recipes-bsp/u-boot/files/uboot-imx-igkboard.patch
+++ b/yocto/honister/meta-igkboard/recipes-bsp/u-boot/files/uboot-imx-igkboard.patch
@@ -1,6 +1,29 @@
-diff -Nuar uboot-imx/arch/arm/dts/imx6ul-14x14-evk.dtsi uboot-imx-igkboard/arch/arm/dts/imx6ul-14x14-evk.dtsi
+diff -Nuar -x lingyun.bmp uboot-imx/arch/arm/dts/igkboard.dts uboot-imx-lf-5.10.52-2.1.0/arch/arm/dts/igkboard.dts
+--- uboot-imx/arch/arm/dts/igkboard.dts 1970-01-01 08:00:00.000000000 +0800
++++ uboot-imx-lf-5.10.52-2.1.0/arch/arm/dts/igkboard.dts 2022-06-30 20:28:15.839187950 +0800
+@@ -0,0 +1,19 @@
++// SPDX-License-Identifier: (GPL-2.0 OR MIT)
++//
++// Copyright (C) 2016 Freescale Semiconductor, Inc.
++
++/dts-v1/;
++
++#include "imx6ull.dtsi"
++#include "imx6ul-14x14-evk.dtsi"
++#include "imx6ul-14x14-evk-u-boot.dtsi"
++
++/ {
++ model = "LingYun IoT Gateway Board";
++ compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
++};
++
++&clks {
++ assigned-clocks = <&clks IMX6UL_CLK_PLL3_PFD2>;
++ assigned-clock-rates = <320000000>;
++};
+diff -Nuar -x lingyun.bmp uboot-imx/arch/arm/dts/imx6ul-14x14-evk.dtsi uboot-imx-lf-5.10.52-2.1.0/arch/arm/dts/imx6ul-14x14-evk.dtsi
--- uboot-imx/arch/arm/dts/imx6ul-14x14-evk.dtsi 2021-09-06 16:48:23.000000000 +0800
-+++ uboot-imx-igkboard/arch/arm/dts/imx6ul-14x14-evk.dtsi 2021-12-18 19:24:57.848022011 +0800
++++ uboot-imx-lf-5.10.52-2.1.0/arch/arm/dts/imx6ul-14x14-evk.dtsi 2022-06-30 20:28:15.839187950 +0800
@@ -21,7 +21,6 @@
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
@@ -13,9 +36,9 @@
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rmii";
phy-handle = <ðphy0>;
-+ phy-reset-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>;
-+ phy-reset-duration = <50>;
-+ phy-reset-post-delay = <15>;
++ phy-reset-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>;
++ phy-reset-duration = <50>;
++ phy-reset-post-delay = <15>;
status = "okay";
};
@@ -23,9 +46,9 @@
pinctrl-0 = <&pinctrl_enet2>;
phy-mode = "rmii";
phy-handle = <ðphy1>;
-+ phy-reset-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
-+ phy-reset-duration = <50>;
-+ phy-reset-post-delay = <15>;
++ phy-reset-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
++ phy-reset-duration = <50>;
++ phy-reset-post-delay = <15>;
status = "okay";
mdio {
@@ -39,7 +62,14 @@
micrel,led-mode = <1>;
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
-@@ -151,21 +156,21 @@
+@@ -145,27 +150,27 @@
+ &lcdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcdif_dat
+- &pinctrl_lcdif_ctrl>;
++ &pinctrl_lcdif_ctrl>;
+
+ display = <&display0>;
status = "okay";
display0: display@0 {
@@ -72,31 +102,177 @@
hsync-active = <0>;
vsync-active = <0>;
-@@ -312,6 +317,7 @@
- MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
- MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+@@ -284,6 +289,40 @@
+
+ &iomuxc {
+ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_extgpio>;
++
++ pinctrl_extgpio: extgpiogrp {
++ fsl,pins = <
++ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x17059 /* 3# I2C1_SDA */
++ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x17059 /* 5# I2C1_SCL */
++ MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x17059 /* 7# GPIO */
++ MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x17059 /* 11# UART3_TX */
++ MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x17059 /* 13# UART4_TX */
++ MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x17059 /* 15# UART4_RX */
++ MX6UL_PAD_LCD_DATA22__GPIO3_IO27 0x17059 /* 19# SPI1_MOSI*/
++ MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0x17059 /* 21# SPI1_MISO*/
++ MX6UL_PAD_LCD_DATA20__GPIO3_IO25 0x17059 /* 23# SPI1_SCLK*/
++ MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x17059 /* 27# CAN1_TX */
++ MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x17059 /* 29# CAN1_RX */
++ MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x17059 /* 31# CAN2_TX */
++ MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x17059 /* 33# CAN2_RX */
++ MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 /* 35# GPIO */
++ MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x17059 /* 37# GPIO */
++ MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x17059 /* 8# UART2_TX */
++ MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x17059 /* 10# UART2_RX */
++ MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x17059 /* 12# UART3_RX */
++ MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x17059 /* 16# UART7_TX */
++ MX6UL_PAD_LCD_DATA17__GPIO3_IO22 0x17059 /* 18# UART7_RX */
++ MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x17059 /* 22# GPIO */
++ MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x17059 /* 24# SPI1_SS0 */
++ MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x17059 /* 26# GPIO */
++ MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x17059 /* 28# PWM8 */
++ MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x17059 /* 32# PWM7 */
++ MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x17059 /* 36# GPIO */
++ MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x17059 /* 38# GPIO */
++ MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x17059 /* 40# GPIO */
++ >;
++ };
+
+ pinctrl_csi1: csi1grp {
+ fsl,pins = <
+@@ -306,12 +345,13 @@
+ fsl,pins = <
+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
+- MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+- MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
++ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
++ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
+- MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+- MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
++ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
++ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
-+ MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x10B0 /* ENET1 RESET */
++ MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x10B0 /* ENET1 RESET */
>;
};
-@@ -327,6 +333,7 @@
- MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
- MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
+@@ -321,12 +361,13 @@
+ MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
+ MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
+- MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
+- MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
++ MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
++ MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
+- MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
+- MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
++ MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
++ MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
-+ MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x10B0 /* ENET2 RESET */
++ MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x10B0 /* ENET2 RESET */
>;
};
-@@ -423,7 +430,6 @@
- MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
+@@ -367,41 +408,33 @@
+
+ pinctrl_lcdif_dat: lcdifdatgrp {
+ fsl,pins = <
+- MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
+- MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
+- MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
+- MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
+- MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
+- MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
+- MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
+- MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
+- MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
+- MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
+- MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
+- MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
+- MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
+- MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
+- MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
+- MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
+- MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
+- MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
+- MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
+- MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
+- MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
+- MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
+- MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
+- MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
++ MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
++ MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
++ MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
++ MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
++ MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
++ MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
++ MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
++ MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
++ MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
++ MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
++ MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
++ MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
++ MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
++ MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
++ MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
++ MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
+ >;
+ };
+
+ pinctrl_lcdif_ctrl: lcdifctrlgrp {
+ fsl,pins = <
+- MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
+- MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
+- MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
+- MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
++ MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
++ MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
++ MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
++ MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
+ /* used for lcd reset */
+- MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
++ MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
+ >;
+ };
+
+@@ -409,8 +442,8 @@
+ fsl,pins = <
+ MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
+ MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
+- MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
+- MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
++ MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
++ MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
+ MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
+ MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
+ >;
+@@ -420,16 +453,15 @@
+ fsl,pins = <
+ MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
+ MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
+- MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
++ MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
- MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059
>;
};
-@@ -448,7 +454,6 @@
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+- MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
++ MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
+ >;
+ };
+
+@@ -448,7 +480,6 @@
fsl,pins = <
MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1
MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1
@@ -104,21 +280,1066 @@
MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000
>;
};
-@@ -492,9 +497,7 @@
- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+@@ -486,22 +517,20 @@
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
++ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071
+- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
- MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
- MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
- MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
-+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
++ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
++ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
++ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
++ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
++ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
>;
};
-diff -Nuar uboot-imx/configs/igkboard_defconfig uboot-imx-igkboard/configs/igkboard_defconfig
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ fsl,pins = <
+- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
+- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
++ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
++ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
+@@ -512,8 +541,8 @@
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ fsl,pins = <
+- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
+- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
++ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
++ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
+@@ -523,8 +552,8 @@
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
+- MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
++ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
++ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+@@ -534,8 +563,8 @@
+
+ pinctrl_usdhc2_8bit: usdhc2grp_8bit {
+ fsl,pins = <
+- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
+- MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
++ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
++ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+@@ -549,8 +578,8 @@
+
+ pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz {
+ fsl,pins = <
+- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
+- MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
++ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
++ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
+@@ -564,8 +593,8 @@
+
+ pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz {
+ fsl,pins = <
+- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
+- MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
++ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
++ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
+diff -Nuar -x lingyun.bmp uboot-imx/arch/arm/dts/Makefile uboot-imx-lf-5.10.52-2.1.0/arch/arm/dts/Makefile
+--- uboot-imx/arch/arm/dts/Makefile 2021-09-06 16:48:23.000000000 +0800
++++ uboot-imx-lf-5.10.52-2.1.0/arch/arm/dts/Makefile 2022-06-30 20:28:15.839187950 +0800
+@@ -779,6 +779,7 @@
+ imx6ul-pico-pi.dtb
+
+ dtb-$(CONFIG_MX6ULL) += \
++ igkboard.dtb \
+ imx6ull-14x14-ddr3-val.dtb \
+ imx6ull-14x14-ddr3-val-epdc.dtb \
+ imx6ull-14x14-ddr3-val-emmc.dtb \
+diff -Nuar -x lingyun.bmp uboot-imx/arch/arm/mach-imx/mx6/Kconfig uboot-imx-lf-5.10.52-2.1.0/arch/arm/mach-imx/mx6/Kconfig
+--- uboot-imx/arch/arm/mach-imx/mx6/Kconfig 2021-09-06 16:48:23.000000000 +0800
++++ uboot-imx-lf-5.10.52-2.1.0/arch/arm/mach-imx/mx6/Kconfig 2022-06-30 20:28:15.839187950 +0800
+@@ -158,6 +158,16 @@
+ prompt "MX6 board select"
+ optional
+
++config TARGET_LINGYUN_IGKBOARD
++ bool "LingYun IoT Gateway Kits Board(IGKBoard)"
++ depends on MX6ULL
++ select BOARD_LATE_INIT
++ select DM
++ select DM_THERMAL
++ select IMX_MODULE_FUSE
++ select OF_SYSTEM_SETUP
++ imply CMD_DM
++
+ config TARGET_ADVANTECH_DMS_BA16
+ bool "Advantech dms-ba16"
+ depends on MX6Q
+@@ -973,5 +983,6 @@
+ source "board/wandboard/Kconfig"
+ source "board/warp/Kconfig"
+ source "board/BuR/brppt2/Kconfig"
++source "board/lingyun/igkboard/Kconfig"
+
+ endif
+diff -Nuar -x lingyun.bmp uboot-imx/board/lingyun/igkboard/igkboard.c uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/igkboard.c
+--- uboot-imx/board/lingyun/igkboard/igkboard.c 1970-01-01 08:00:00.000000000 +0800
++++ uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/igkboard.c 2022-06-30 20:28:15.839187950 +0800
+@@ -0,0 +1,369 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright (C) 2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#include <init.h>
++#include <asm/arch/clock.h>
++#include <asm/arch/iomux.h>
++#include <asm/arch/imx-regs.h>
++#include <asm/arch/crm_regs.h>
++#include <asm/arch/mx6-pins.h>
++#include <asm/arch/sys_proto.h>
++#include <asm/global_data.h>
++#include <asm/gpio.h>
++#include <asm/mach-imx/iomux-v3.h>
++#include <asm/mach-imx/boot_mode.h>
++#include <asm/mach-imx/mxc_i2c.h>
++#include <asm/io.h>
++#include <common.h>
++#include <env.h>
++#include <fsl_esdhc_imx.h>
++#include <i2c.h>
++#include <miiphy.h>
++#include <linux/sizes.h>
++#include <linux/delay.h>
++#include <mmc.h>
++#include <miiphy.h>
++#include <power/pmic.h>
++#include <power/pfuze3000_pmic.h>
++#include "../../freescale/common/pfuze.h"
++
++DECLARE_GLOBAL_DATA_PTR;
++
++#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
++ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
++ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
++
++#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
++ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
++ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
++ PAD_CTL_ODE)
++
++#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
++ PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
++
++#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
++#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
++ PAD_CTL_SRE_FAST)
++#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
++
++
++#ifdef CONFIG_DM_PMIC
++int power_init_board(void)
++{
++ struct udevice *dev;
++ int ret, dev_id, rev_id;
++ unsigned int reg;
++
++ ret = pmic_get("pfuze3000@8", &dev);
++ if (ret == -ENODEV)
++ return 0;
++ if (ret != 0)
++ return ret;
++
++ dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
++ rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
++ printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
++
++ /* disable Low Power Mode during standby mode */
++ reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
++ reg |= 0x1;
++ pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
++
++ /* SW1B step ramp up time from 2us to 4us/25mV */
++ pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40);
++
++ /* SW1B mode to APS/PFM */
++ pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc);
++
++ /* SW1B standby voltage set to 0.975V */
++ pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb);
++
++ return 0;
++}
++
++#ifdef CONFIG_LDO_BYPASS_CHECK
++void ldo_mode_set(int ldo_bypass)
++{
++ unsigned int value;
++ u32 vddarm;
++ struct udevice *dev;
++ int ret;
++
++ ret = pmic_get("pfuze3000@8", &dev);
++ if (ret == -ENODEV) {
++ printf("No PMIC found!\n");
++ return;
++ }
++
++ /* switch to ldo_bypass mode */
++ if (ldo_bypass) {
++ prep_anatop_bypass();
++ /* decrease VDDARM to 1.275V */
++ value = pmic_reg_read(dev, PFUZE3000_SW1BVOLT);
++ value &= ~0x1f;
++ value |= PFUZE3000_SW1AB_SETP(12750);
++ pmic_reg_write(dev, PFUZE3000_SW1BVOLT, value);
++
++ set_anatop_bypass(1);
++ vddarm = PFUZE3000_SW1AB_SETP(11750);
++
++ value = pmic_reg_read(dev, PFUZE3000_SW1BVOLT);
++ value &= ~0x1f;
++ value |= vddarm;
++ pmic_reg_write(dev, PFUZE3000_SW1BVOLT, value);
++
++ finish_anatop_bypass();
++
++ printf("switch to ldo_bypass mode!\n");
++ }
++}
++#endif
++#endif
++
++int dram_init(void)
++{
++ gd->ram_size = imx_ddr_size();
++
++ return 0;
++}
++
++static iomux_v3_cfg_t const uart1_pads[] = {
++ MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
++ MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
++};
++
++static void setup_iomux_uart(void)
++{
++ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
++}
++
++#ifdef CONFIG_FSL_QSPI
++
++#ifndef CONFIG_DM_SPI
++#define QSPI_PAD_CTRL1 \
++ (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
++ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm)
++
++static iomux_v3_cfg_t const quadspi_pads[] = {
++ MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
++ MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
++ MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
++ MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
++ MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
++ MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
++};
++#endif
++
++static int board_qspi_init(void)
++{
++#ifndef CONFIG_DM_SPI
++ /* Set the iomux */
++ imx_iomux_v3_setup_multiple_pads(quadspi_pads,
++ ARRAY_SIZE(quadspi_pads));
++#endif
++ /* Set the clock */
++ enable_qspi_clk(0);
++
++ return 0;
++}
++#endif
++
++#ifdef CONFIG_NAND_MXS
++static iomux_v3_cfg_t const nand_pads[] = {
++ MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
++ MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
++ MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
++ MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
++ MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
++ MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
++ MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
++ MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
++ MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
++ MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
++ MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
++ MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
++ MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
++ MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
++ MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
++ MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
++ MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
++};
++
++static void setup_gpmi_nand(void)
++{
++ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
++
++ /* config gpmi nand iomux */
++ imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
++
++ setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
++ MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
++ MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
++
++ /* enable apbh clock gating */
++ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
++}
++#endif
++
++#ifdef CONFIG_FEC_MXC
++static int setup_fec(void)
++{
++ struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
++ int ret;
++
++ /*
++ * Use 50M anatop loopback REF_CLK1 for ENET1,
++ * clear gpr1[13], set gpr1[17].
++ */
++ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
++ IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
++ /*
++ * Use 50M anatop loopback REF_CLK2 for ENET2,
++ * clear gpr1[14], set gpr1[18].
++ */
++ if (!check_module_fused(MODULE_ENET2)) {
++ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
++ IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
++ }
++
++ ret = enable_fec_anatop_clock(0, ENET_50MHZ);
++ if (ret)
++ return ret;
++
++ if (!check_module_fused(MODULE_ENET2)) {
++ ret = enable_fec_anatop_clock(1, ENET_50MHZ);
++ if (ret)
++ return ret;
++ }
++
++ enable_enet_clk(1);
++
++ return 0;
++}
++
++int board_phy_config(struct phy_device *phydev)
++{
++ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
++
++ if (phydev->drv->config)
++ phydev->drv->config(phydev);
++
++ return 0;
++}
++#endif
++
++#ifdef CONFIG_DM_VIDEO
++static iomux_v3_cfg_t const lcd_pads[] = {
++ /* Use GPIO for Brightness adjustment, duty cycle = period. */
++ MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
++};
++
++static int setup_lcd(void)
++{
++ enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
++
++ imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
++
++ /* Reset the LCD */
++ gpio_request(IMX_GPIO_NR(5, 9), "lcd reset");
++ gpio_direction_output(IMX_GPIO_NR(5, 9) , 0);
++ udelay(500);
++ gpio_direction_output(IMX_GPIO_NR(5, 9) , 1);
++
++ /* Set Brightness to high */
++ gpio_request(IMX_GPIO_NR(1, 8), "backlight");
++ gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);
++
++ return 0;
++}
++#else
++static inline int setup_lcd(void) { return 0; }
++#endif
++
++int board_early_init_f(void)
++{
++ setup_iomux_uart();
++
++ return 0;
++}
++
++int board_init(void)
++{
++ /* Address of boot parameters */
++ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
++
++#ifdef CONFIG_FEC_MXC
++ setup_fec();
++#endif
++
++#ifdef CONFIG_FSL_QSPI
++ board_qspi_init();
++#endif
++
++#ifdef CONFIG_NAND_MXS
++ setup_gpmi_nand();
++#endif
++
++ return 0;
++}
++
++#ifdef CONFIG_CMD_BMODE
++static const struct boot_mode board_boot_modes[] = {
++ /* 4 bit bus width */
++ {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
++ {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
++ {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
++ {NULL, 0},
++};
++#endif
++
++int board_late_init(void)
++{
++#ifdef CONFIG_CMD_BMODE
++ add_board_boot_modes(board_boot_modes);
++#endif
++
++ env_set("tee", "no");
++#ifdef CONFIG_IMX_OPTEE
++ env_set("tee", "yes");
++#endif
++
++#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
++ env_set("board_name", "EVK");
++
++ if (is_mx6ull_9x9_evk())
++ env_set("board_rev", "9X9");
++ else
++ env_set("board_rev", "14X14");
++
++ if (is_cpu_type(MXC_CPU_MX6ULZ)) {
++ env_set("board_name", "ULZ-EVK");
++ env_set("usb_net_cmd", "usb start");
++ }
++#endif
++
++ setup_lcd();
++
++#ifdef CONFIG_ENV_IS_IN_MMC
++ board_late_mmc_env_init();
++#endif
++
++ set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
++
++ return 0;
++}
++
++int checkboard(void)
++{
++ if (is_mx6ull_9x9_evk())
++ puts("Board: MX6ULL 9x9 EVK\n");
++ else if (is_cpu_type(MXC_CPU_MX6ULZ))
++ puts("Board: MX6ULZ 14x14 EVK\n");
++ else
++ puts("Board: IGKBoard\n");
++
++ return 0;
++}
+diff -Nuar -x lingyun.bmp uboot-imx/board/lingyun/igkboard/imximage.cfg uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/imximage.cfg
+--- uboot-imx/board/lingyun/igkboard/imximage.cfg 1970-01-01 08:00:00.000000000 +0800
++++ uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/imximage.cfg 2022-06-30 20:28:15.839187950 +0800
+@@ -0,0 +1,121 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright (C) 2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ *
++ * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
++ * and create imximage boot image
++ *
++ * The syntax is taken as close as possible with the kwbimage
++ */
++
++#define __ASSEMBLY__
++#include <config.h>
++
++/* image version */
++
++IMAGE_VERSION 2
++
++/*
++ * Boot Device : one of
++ * spi/sd/nand/onenand, qspi/nor
++ */
++
++#ifdef CONFIG_QSPI_BOOT
++BOOT_FROM qspi
++#elif defined(CONFIG_NOR_BOOT)
++BOOT_FROM nor
++#else
++BOOT_FROM sd
++#endif
++
++#ifdef CONFIG_USE_IMXIMG_PLUGIN
++/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
++PLUGIN board/lingyun/igkboard/plugin.bin 0x00907000
++#else
++
++#ifdef CONFIG_IMX_HAB
++CSF CONFIG_CSF_SIZE
++#endif
++
++/*
++ * Device Configuration Data (DCD)
++ *
++ * Each entry must have the format:
++ * Addr-type Address Value
++ *
++ * where:
++ * Addr-type register length (1,2 or 4 bytes)
++ * Address absolute address of the register
++ * value value to be stored in the register
++ */
++
++/* Enable all clocks */
++DATA 4 0x020c4068 0xffffffff
++DATA 4 0x020c406c 0xffffffff
++DATA 4 0x020c4070 0xffffffff
++DATA 4 0x020c4074 0xffffffff
++DATA 4 0x020c4078 0xffffffff
++DATA 4 0x020c407c 0xffffffff
++DATA 4 0x020c4080 0xffffffff
++
++#ifdef CONFIG_IMX_OPTEE
++DATA 4 0x20e4024 0x00000001
++CHECK_BITS_SET 4 0x20e4024 0x1
++#endif
++
++DATA 4 0x020E04B4 0x000C0000
++DATA 4 0x020E04AC 0x00000000
++DATA 4 0x020E027C 0x00000030
++DATA 4 0x020E0250 0x00000030
++DATA 4 0x020E024C 0x00000030
++DATA 4 0x020E0490 0x00000030
++DATA 4 0x020E0288 0x000C0030
++DATA 4 0x020E0270 0x00000000
++DATA 4 0x020E0260 0x00000030
++DATA 4 0x020E0264 0x00000030
++DATA 4 0x020E04A0 0x00000030
++DATA 4 0x020E0494 0x00020000
++DATA 4 0x020E0280 0x00000030
++DATA 4 0x020E0284 0x00000030
++DATA 4 0x020E04B0 0x00020000
++DATA 4 0x020E0498 0x00000030
++DATA 4 0x020E04A4 0x00000030
++DATA 4 0x020E0244 0x00000030
++DATA 4 0x020E0248 0x00000030
++DATA 4 0x021B001C 0x00008000
++DATA 4 0x021B0800 0xA1390003
++DATA 4 0x021B080C 0x00000004
++DATA 4 0x021B083C 0x41640158
++DATA 4 0x021B0848 0x40403237
++DATA 4 0x021B0850 0x40403C33
++DATA 4 0x021B081C 0x33333333
++DATA 4 0x021B0820 0x33333333
++DATA 4 0x021B082C 0xf3333333
++DATA 4 0x021B0830 0xf3333333
++DATA 4 0x021B08C0 0x00944009
++DATA 4 0x021B08b8 0x00000800
++DATA 4 0x021B0004 0x0002002D
++DATA 4 0x021B0008 0x1B333030
++DATA 4 0x021B000C 0x676B52F3
++DATA 4 0x021B0010 0xB66D0B63
++DATA 4 0x021B0014 0x01FF00DB
++DATA 4 0x021B0018 0x00201740
++DATA 4 0x021B001C 0x00008000
++DATA 4 0x021B002C 0x000026D2
++DATA 4 0x021B0030 0x006B1023
++DATA 4 0x021B0040 0x0000004F
++DATA 4 0x021B0000 0x84180000
++DATA 4 0x021B0890 0x00400000
++DATA 4 0x021B001C 0x02008032
++DATA 4 0x021B001C 0x00008033
++DATA 4 0x021B001C 0x00048031
++DATA 4 0x021B001C 0x15208030
++DATA 4 0x021B001C 0x04008040
++DATA 4 0x021B0020 0x00000800
++DATA 4 0x021B0818 0x00000227
++DATA 4 0x021B0004 0x0002552D
++DATA 4 0x021B0404 0x00011006
++DATA 4 0x021B001C 0x00000000
++
++#endif
+diff -Nuar -x lingyun.bmp uboot-imx/board/lingyun/igkboard/imximage_lpddr2.cfg uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/imximage_lpddr2.cfg
+--- uboot-imx/board/lingyun/igkboard/imximage_lpddr2.cfg 1970-01-01 08:00:00.000000000 +0800
++++ uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/imximage_lpddr2.cfg 2022-06-30 20:28:15.839187950 +0800
+@@ -0,0 +1,126 @@
++/*
++ * Copyright (C) 2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ *
++ * Refer docs/README.imxmage for more details about how-to configure
++ * and create imximage boot image
++ *
++ * The syntax is taken as close as possible with the kwbimage
++ */
++
++#define __ASSEMBLY__
++#include <config.h>
++
++/* image version */
++
++IMAGE_VERSION 2
++
++/*
++ * Boot Device : one of
++ * spi/sd/nand/onenand, qspi/nor
++ */
++
++#ifdef CONFIG_QSPI_BOOT
++BOOT_FROM qspi
++#elif defined(CONFIG_NOR_BOOT)
++BOOT_FROM nor
++#else
++BOOT_FROM sd
++#endif
++
++#ifdef CONFIG_USE_IMXIMG_PLUGIN
++/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
++PLUGIN board/freescale/mx6ullevk/plugin.bin 0x00907000
++#else
++
++#ifdef CONFIG_IMX_HAB
++CSF CONFIG_CSF_SIZE
++#endif
++
++/*
++ * Device Configuration Data (DCD)
++ *
++ * Each entry must have the format:
++ * Addr-type Address Value
++ *
++ * where:
++ * Addr-type register length (1,2 or 4 bytes)
++ * Address absolute address of the register
++ * value value to be stored in the register
++ */
++
++DATA 4 0x020c4068 0xffffffff
++DATA 4 0x020c406c 0xffffffff
++DATA 4 0x020c4070 0xffffffff
++DATA 4 0x020c4074 0xffffffff
++DATA 4 0x020c4078 0xffffffff
++DATA 4 0x020c407c 0xffffffff
++DATA 4 0x020c4080 0xffffffff
++
++#ifdef CONFIG_IMX_OPTEE
++DATA 4 0x20e4024 0x00000001
++CHECK_BITS_SET 4 0x20e4024 0x1
++#endif
++
++DATA 4 0x020E04B4 0x00080000
++DATA 4 0x020E04AC 0x00000000
++DATA 4 0x020E027C 0x00000030
++DATA 4 0x020E0250 0x00000030
++DATA 4 0x020E024C 0x00000030
++DATA 4 0x020E0490 0x00000030
++DATA 4 0x020E0288 0x00000030
++DATA 4 0x020E0270 0x00000000
++DATA 4 0x020E0260 0x00000000
++DATA 4 0x020E0264 0x00000000
++DATA 4 0x020E04A0 0x00000030
++DATA 4 0x020E0494 0x00020000
++DATA 4 0x020E0280 0x00003030
++DATA 4 0x020E0284 0x00003030
++DATA 4 0x020E04B0 0x00020000
++DATA 4 0x020E0498 0x00000030
++DATA 4 0x020E04A4 0x00000030
++DATA 4 0x020E0244 0x00000030
++DATA 4 0x020E0248 0x00000030
++
++DATA 4 0x021B001C 0x00008000
++DATA 4 0x021B085C 0x1b4700c7
++DATA 4 0x021B0800 0xA1390003
++DATA 4 0x021B0890 0x23400A38
++DATA 4 0x021B08b8 0x00000800
++
++DATA 4 0x021B081C 0x33333333
++DATA 4 0x021B0820 0x33333333
++DATA 4 0x021B082C 0xf3333333
++DATA 4 0x021B0830 0xf3333333
++DATA 4 0x021B083C 0x20000000
++DATA 4 0x021B0848 0x40403439
++DATA 4 0x021B0850 0x4040342D
++DATA 4 0x021B08C0 0x00921012
++DATA 4 0x021B08b8 0x00000800
++
++DATA 4 0x021B0004 0x00020052
++DATA 4 0x021B0008 0x00000000
++DATA 4 0x021B000C 0x33374133
++DATA 4 0x021B0010 0x00100A82
++DATA 4 0x021B0038 0x00170557
++DATA 4 0x021B0014 0x00000093
++DATA 4 0x021B0018 0x00201748
++DATA 4 0x021B002C 0x0F9F26D2
++DATA 4 0x021B0030 0x009F0010
++DATA 4 0x021B0040 0x00000047
++DATA 4 0x021B0000 0x83100000
++DATA 4 0x021B001C 0x00008010
++DATA 4 0x021B001C 0x003F8030
++DATA 4 0x021B001C 0xFF0A8030
++DATA 4 0x021B001C 0x82018030
++DATA 4 0x021B001C 0x04028030
++DATA 4 0x021B001C 0x01038030
++DATA 4 0x021B0020 0x00001800
++DATA 4 0x021B0818 0x00000000
++DATA 4 0x021B0800 0xA1310003
++DATA 4 0x021B0004 0x00025552
++DATA 4 0x021B0404 0x00011006
++DATA 4 0x021B001C 0x00000000
++#endif
+diff -Nuar -x lingyun.bmp uboot-imx/board/lingyun/igkboard/Kconfig uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/Kconfig
+--- uboot-imx/board/lingyun/igkboard/Kconfig 1970-01-01 08:00:00.000000000 +0800
++++ uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/Kconfig 2022-06-30 20:28:15.839187950 +0800
+@@ -0,0 +1,14 @@
++if TARGET_LINGYUN_IGKBOARD
++
++config SYS_BOARD
++ default "igkboard"
++
++config SYS_VENDOR
++ default "lingyun"
++
++config SYS_CONFIG_NAME
++ default "igkboard"
++
++config SYS_TEXT_BASE
++ default 0x87800000
++endif
+diff -Nuar -x lingyun.bmp uboot-imx/board/lingyun/igkboard/MAINTAINERS uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/MAINTAINERS
+--- uboot-imx/board/lingyun/igkboard/MAINTAINERS 1970-01-01 08:00:00.000000000 +0800
++++ uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/MAINTAINERS 2022-06-30 20:28:15.839187950 +0800
+@@ -0,0 +1,6 @@
++LingYun IoT Gateway Board(IGKBoard)
++M: Guo Wenxue <guowenxue@gmail.com>
++S: Maintained
++F: board/lingyun/igkboard/
++F: include/configs/igkboard.h
++F: configs/igkboard_defconfig
+diff -Nuar -x lingyun.bmp uboot-imx/board/lingyun/igkboard/Makefile uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/Makefile
+--- uboot-imx/board/lingyun/igkboard/Makefile 1970-01-01 08:00:00.000000000 +0800
++++ uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/Makefile 2022-06-30 20:28:15.839187950 +0800
+@@ -0,0 +1,5 @@
++# SPDX-License-Identifier: GPL-2.0+
++# (C) Copyright 2016 Freescale Semiconductor, Inc.
++
++obj-y := igkboard.o
++obj-y += ../../freescale/common/mmc.o
+diff -Nuar -x lingyun.bmp uboot-imx/board/lingyun/igkboard/plugin.S uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/plugin.S
+--- uboot-imx/board/lingyun/igkboard/plugin.S 1970-01-01 08:00:00.000000000 +0800
++++ uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/plugin.S 2022-06-30 20:28:15.839187950 +0800
+@@ -0,0 +1,263 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright (C) 2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#include <config.h>
++
++/* DDR script */
++.macro imx6ull_ddr3_evk_setting
++ ldr r0, =IOMUXC_BASE_ADDR
++ ldr r1, =0x000C0000
++ str r1, [r0, #0x4B4]
++ ldr r1, =0x00000000
++ str r1, [r0, #0x4AC]
++ ldr r1, =0x00000030
++ str r1, [r0, #0x27C]
++ ldr r1, =0x00000030
++ str r1, [r0, #0x250]
++ str r1, [r0, #0x24C]
++ str r1, [r0, #0x490]
++ ldr r1, =0x000C0030
++ str r1, [r0, #0x288]
++
++ ldr r1, =0x00000000
++ str r1, [r0, #0x270]
++
++ ldr r1, =0x00000030
++ str r1, [r0, #0x260]
++ str r1, [r0, #0x264]
++ str r1, [r0, #0x4A0]
++
++ ldr r1, =0x00020000
++ str r1, [r0, #0x494]
++
++ ldr r1, =0x00000030
++ str r1, [r0, #0x280]
++ ldr r1, =0x00000030
++ str r1, [r0, #0x284]
++
++ ldr r1, =0x00020000
++ str r1, [r0, #0x4B0]
++
++ ldr r1, =0x00000030
++ str r1, [r0, #0x498]
++ str r1, [r0, #0x4A4]
++ str r1, [r0, #0x244]
++ str r1, [r0, #0x248]
++
++ ldr r0, =MMDC_P0_BASE_ADDR
++ ldr r1, =0x00008000
++ str r1, [r0, #0x1C]
++ ldr r1, =0xA1390003
++ str r1, [r0, #0x800]
++ ldr r1, =0x00000004
++ str r1, [r0, #0x80C]
++ ldr r1, =0x41640158
++ str r1, [r0, #0x83C]
++ ldr r1, =0x40403237
++ str r1, [r0, #0x848]
++ ldr r1, =0x40403C33
++ str r1, [r0, #0x850]
++ ldr r1, =0x33333333
++ str r1, [r0, #0x81C]
++ str r1, [r0, #0x820]
++ ldr r1, =0xF3333333
++ str r1, [r0, #0x82C]
++ str r1, [r0, #0x830]
++ ldr r1, =0x00944009
++ str r1, [r0, #0x8C0]
++ ldr r1, =0x00000800
++ str r1, [r0, #0x8B8]
++ ldr r1, =0x0002002D
++ str r1, [r0, #0x004]
++ ldr r1, =0x1B333030
++ str r1, [r0, #0x008]
++ ldr r1, =0x676B52F3
++ str r1, [r0, #0x00C]
++ ldr r1, =0xB66D0B63
++ str r1, [r0, #0x010]
++ ldr r1, =0x01FF00DB
++ str r1, [r0, #0x014]
++ ldr r1, =0x00201740
++ str r1, [r0, #0x018]
++ ldr r1, =0x00008000
++ str r1, [r0, #0x01C]
++ ldr r1, =0x000026D2
++ str r1, [r0, #0x02C]
++ ldr r1, =0x006B1023
++ str r1, [r0, #0x030]
++ ldr r1, =0x0000004F
++ str r1, [r0, #0x040]
++ ldr r1, =0x84180000
++ str r1, [r0, #0x000]
++ ldr r1, =0x00400000
++ str r1, [r0, #0x890]
++ ldr r1, =0x02008032
++ str r1, [r0, #0x01C]
++ ldr r1, =0x00008033
++ str r1, [r0, #0x01C]
++ ldr r1, =0x00048031
++ str r1, [r0, #0x01C]
++ ldr r1, =0x15208030
++ str r1, [r0, #0x01C]
++ ldr r1, =0x04008040
++ str r1, [r0, #0x01C]
++ ldr r1, =0x00000800
++ str r1, [r0, #0x020]
++ ldr r1, =0x00000227
++ str r1, [r0, #0x818]
++ ldr r1, =0x0002552D
++ str r1, [r0, #0x004]
++ ldr r1, =0x00011006
++ str r1, [r0, #0x404]
++ ldr r1, =0x00000000
++ str r1, [r0, #0x01C]
++.endm
++
++.macro imx6ull_lpddr2_evk_setting
++ ldr r0, =IOMUXC_BASE_ADDR
++ ldr r1, =0x00080000
++ str r1, [r0, #0x4B4]
++ ldr r1, =0x00000000
++ str r1, [r0, #0x4AC]
++ ldr r1, =0x00000030
++ str r1, [r0, #0x27C]
++ str r1, [r0, #0x250]
++ str r1, [r0, #0x24C]
++ str r1, [r0, #0x490]
++ str r1, [r0, #0x288]
++
++ ldr r1, =0x00000000
++ str r1, [r0, #0x270]
++ str r1, [r0, #0x260]
++ str r1, [r0, #0x264]
++
++ ldr r1, =0x00000030
++ str r1, [r0, #0x4A0]
++
++ ldr r1, =0x00020000
++ str r1, [r0, #0x494]
++
++ ldr r1, =0x00003030
++ str r1, [r0, #0x280]
++ ldr r1, =0x00003030
++ str r1, [r0, #0x284]
++
++ ldr r1, =0x00020000
++ str r1, [r0, #0x4B0]
++
++ ldr r1, =0x00000030
++ str r1, [r0, #0x498]
++ str r1, [r0, #0x4A4]
++ str r1, [r0, #0x244]
++ str r1, [r0, #0x248]
++
++ ldr r0, =MMDC_P0_BASE_ADDR
++ ldr r1, =0x00008000
++ str r1, [r0, #0x1C]
++ ldr r1, =0x1b4700c7
++ str r1, [r0, #0x85c]
++ ldr r1, =0xA1390003
++ str r1, [r0, #0x800]
++ ldr r1, =0x23400A38
++ str r1, [r0, #0x890]
++ ldr r1, =0x00000800
++ str r1, [r0, #0x8b8]
++ ldr r1, =0x33333333
++ str r1, [r0, #0x81C]
++ str r1, [r0, #0x820]
++ ldr r1, =0xF3333333
++ str r1, [r0, #0x82C]
++ str r1, [r0, #0x830]
++ ldr r1, =0x20000000
++ str r1, [r0, #0x83C]
++ ldr r1, =0x40403439
++ str r1, [r0, #0x848]
++ ldr r1, =0x4040342D
++ str r1, [r0, #0x850]
++ ldr r1, =0x00921012
++ str r1, [r0, #0x8C0]
++ ldr r1, =0x00000800
++ str r1, [r0, #0x8B8]
++
++ ldr r1, =0x00020052
++ str r1, [r0, #0x004]
++ ldr r1, =0x00000000
++ str r1, [r0, #0x008]
++ ldr r1, =0x33374133
++ str r1, [r0, #0x00C]
++ ldr r1, =0x00100A82
++ str r1, [r0, #0x010]
++ ldr r1, =0x00170557
++ str r1, [r0, #0x038]
++ ldr r1, =0x00000093
++ str r1, [r0, #0x014]
++ ldr r1, =0x00201748
++ str r1, [r0, #0x018]
++ ldr r1, =0x0F9F26D2
++ str r1, [r0, #0x02C]
++ ldr r1, =0x009F0010
++ str r1, [r0, #0x030]
++ ldr r1, =0x00000047
++ str r1, [r0, #0x040]
++ ldr r1, =0x83100000
++ str r1, [r0, #0x000]
++ ldr r1, =0x00008010
++ str r1, [r0, #0x01C]
++ ldr r1, =0x003F8030
++ str r1, [r0, #0x01C]
++ ldr r1, =0xFF0A8030
++ str r1, [r0, #0x01C]
++ ldr r1, =0x82018030
++ str r1, [r0, #0x01C]
++ ldr r1, =0x04028030
++ str r1, [r0, #0x01C]
++ ldr r1, =0x01038030
++ str r1, [r0, #0x01C]
++ ldr r1, =0x00001800
++ str r1, [r0, #0x020]
++ ldr r1, =0x00000000
++ str r1, [r0, #0x818]
++ ldr r1, =0xA1310003
++ str r1, [r0, #0x800]
++ ldr r1, =0x00025552
++ str r1, [r0, #0x004]
++ ldr r1, =0x00011006
++ str r1, [r0, #0x404]
++ ldr r1, =0x00000000
++ str r1, [r0, #0x01C]
++.endm
++
++.macro imx6_clock_gating
++ ldr r0, =CCM_BASE_ADDR
++ ldr r1, =0xFFFFFFFF
++ str r1, [r0, #0x68]
++ str r1, [r0, #0x6C]
++ str r1, [r0, #0x70]
++ str r1, [r0, #0x74]
++ str r1, [r0, #0x78]
++ str r1, [r0, #0x7C]
++ str r1, [r0, #0x80]
++
++#ifdef CONFIG_IMX_OPTEE
++ ldr r0, =0x20e4024
++ ldr r1, =0x1
++ str r1, [r0]
++#endif
++.endm
++
++.macro imx6_qos_setting
++.endm
++
++.macro imx6_ddr_setting
++#if defined (CONFIG_TARGET_MX6ULL_9X9_EVK)
++ imx6ull_lpddr2_evk_setting
++#else
++ imx6ull_ddr3_evk_setting
++#endif
++.endm
++
++/* include the common plugin code here */
++#include <asm/arch/mx6_plugin.S>
+diff -Nuar -x lingyun.bmp uboot-imx/configs/igkboard_defconfig uboot-imx-lf-5.10.52-2.1.0/configs/igkboard_defconfig
--- uboot-imx/configs/igkboard_defconfig 1970-01-01 08:00:00.000000000 +0800
-+++ uboot-imx-igkboard/configs/igkboard_defconfig 2021-12-26 19:59:10.026382816 +0800
-@@ -0,0 +1,96 @@
++++ uboot-imx-lf-5.10.52-2.1.0/configs/igkboard_defconfig 2022-06-30 20:28:15.839187950 +0800
+@@ -0,0 +1,97 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_NR_DRAM_BANKS=1
@@ -127,13 +1348,13 @@
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6ULL=y
-+CONFIG_TARGET_MX6ULL_14X14_EVK=y
++CONFIG_TARGET_LINGYUN_IGKBOARD=y
+CONFIG_DM_GPIO=y
+# CONFIG_CMD_QSPIHDR is not set
-+CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk"
++CONFIG_DEFAULT_DEVICE_TREE="igkboard"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SUPPORT_RAW_INITRD=y
-+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg"
++CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/lingyun/igkboard/imximage.cfg"
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
@@ -215,10 +1436,11 @@
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
-diff -Nuar uboot-imx/drivers/fastboot/fb_fsl/fb_fsl_partitions.c uboot-imx-igkboard/drivers/fastboot/fb_fsl/fb_fsl_partitions.c
++CONFIG_OF_LIBFDT_OVERLAY=y
+diff -Nuar -x lingyun.bmp uboot-imx/drivers/fastboot/fb_fsl/fb_fsl_partitions.c uboot-imx-lf-5.10.52-2.1.0/drivers/fastboot/fb_fsl/fb_fsl_partitions.c
--- uboot-imx/drivers/fastboot/fb_fsl/fb_fsl_partitions.c 2021-09-06 16:48:23.000000000 +0800
-+++ uboot-imx-igkboard/drivers/fastboot/fb_fsl/fb_fsl_partitions.c 2021-12-26 19:34:18.512291074 +0800
-@@ -185,6 +185,10 @@
++++ uboot-imx-lf-5.10.52-2.1.0/drivers/fastboot/fb_fsl/fb_fsl_partitions.c 2022-06-30 20:28:15.839187950 +0800
+@@ -185,6 +185,12 @@
boot_partition = FASTBOOT_MMC_BOOT_PARTITION_ID;
user_partition = FASTBOOT_MMC_USER_PARTITION_ID;
}
@@ -226,12 +1448,14 @@
+ /* add by guowenxue to export mmc_no env */
+ env_set_ulong("mmc_no", mmc_no);
+ env_set_ulong("mmcdev", mmc_no);
++ env_set_ulong("emmc_dev", mmc_no);
++ env_set_ulong("emmc_ack", mmc_no);
} else {
printf("Can't setup partition table on this device %d\n",
fastboot_devinfo.type);
-diff -Nuar uboot-imx/drivers/net/phy/phy.c uboot-imx-igkboard/drivers/net/phy/phy.c
+diff -Nuar -x lingyun.bmp uboot-imx/drivers/net/phy/phy.c uboot-imx-lf-5.10.52-2.1.0/drivers/net/phy/phy.c
--- uboot-imx/drivers/net/phy/phy.c 2021-09-06 16:48:23.000000000 +0800
-+++ uboot-imx-igkboard/drivers/net/phy/phy.c 2021-12-18 19:24:57.848022011 +0800
++++ uboot-imx-lf-5.10.52-2.1.0/drivers/net/phy/phy.c 2022-06-30 20:28:15.839187950 +0800
@@ -182,6 +182,9 @@
{
int result;
@@ -242,170 +1466,305 @@
if (phydev->autoneg != AUTONEG_ENABLE)
return genphy_setup_forced(phydev);
-diff -Nuar uboot-imx/include/configs/mx6ullevk.h uboot-imx-igkboard/include/configs/mx6ullevk.h
---- uboot-imx/include/configs/mx6ullevk.h 2021-09-06 16:48:23.000000000 +0800
-+++ uboot-imx-igkboard/include/configs/mx6ullevk.h 2021-12-26 19:43:02.601118471 +0800
-@@ -100,124 +100,38 @@
-
- #else
- #define CONFIG_EXTRA_ENV_SETTINGS \
-- CONFIG_MFG_ENV_SETTINGS \
-- TEE_ENV \
-+ "emmc_dev=${mmc_no}\0"\
-+ "emmc_ack=${mmc_no}\0"\
- "script=boot.scr\0" \
- "image=zImage\0" \
- "console=ttymxc0\0" \
-- "fdt_high=0xffffffff\0" \
-- "initrd_high=0xffffffff\0" \
-- "fdt_file=undefined\0" \
-+ "fdt_file=igkboard-emmc.dtb\0" \
- "fdt_addr=0x83000000\0" \
-- "tee_addr=0x84000000\0" \
-- "tee_file=undefined\0" \
-- "boot_fdt=try\0" \
-- "ip_dyn=yes\0" \
- "splashimage=0x8c000000\0" \
-- "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
-- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
-- "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
-- "mmcautodetect=yes\0" \
-- "mmcargs=setenv bootargs console=${console},${baudrate} " \
-- BOOTARGS_CMA_SIZE \
-- "root=${mmcroot}\0" \
-- "loadbootscript=" \
-- "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
-- "bootscript=echo Running bootscript from mmc ...; " \
-- "source\0" \
+diff -Nuar -x lingyun.bmp uboot-imx/include/configs/igkboard.h uboot-imx-lf-5.10.52-2.1.0/include/configs/igkboard.h
+--- uboot-imx/include/configs/igkboard.h 1970-01-01 08:00:00.000000000 +0800
++++ uboot-imx-lf-5.10.52-2.1.0/include/configs/igkboard.h 2022-06-30 20:28:15.839187950 +0800
+@@ -0,0 +1,200 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright (C) 2022 LingYun IoT System Studio
++ *
++ * Configuration settings for the LingYun IoT Gateway Board.
++ */
++#ifndef __IGKBOARD_CONFIG_H
++#define __IGKBOARD_CONFIG_H
++
++#include <asm/arch/imx-regs.h>
++#include <linux/sizes.h>
++#include <linux/stringify.h>
++#include "mx6_common.h"
++#include <asm/mach-imx/gpio.h>
++#include "imx_env.h"
++
++#define is_mx6ull_9x9_evk() CONFIG_IS_ENABLED(TARGET_MX6ULL_9X9_EVK)
++
++#ifdef CONFIG_TARGET_MX6ULL_9X9_EVK
++#define PHYS_SDRAM_SIZE SZ_256M
++#define BOOTARGS_CMA_SIZE "cma=96M "
++#else
++#define PHYS_SDRAM_SIZE SZ_512M
++#define BOOTARGS_CMA_SIZE ""
++/* DCDC used on 14x14 EVK, no PMIC */
++#undef CONFIG_LDO_BYPASS_CHECK
++#endif
++
++/* Size of malloc() pool */
++#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
++
++#define CONFIG_MXC_UART_BASE UART1_BASE
++
++/* MMC Configs */
++#ifdef CONFIG_FSL_USDHC
++#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
++
++/* NAND pin conflicts with usdhc2 */
++#ifdef CONFIG_NAND_MXS
++#define CONFIG_SYS_FSL_USDHC_NUM 1
++#else
++#define CONFIG_SYS_FSL_USDHC_NUM 2
++#endif
++#endif
++
++/* I2C configs */
++#ifdef CONFIG_CMD_I2C
++#define CONFIG_SYS_I2C_MXC
++#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
++#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
++#define CONFIG_SYS_I2C_SPEED 100000
++#endif
++
++#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
++
++#ifdef CONFIG_NAND_BOOT
++#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandkernel),16m(nanddtb),16m(nandtee),-(nandrootfs)"
++#else
++#define MFG_NAND_PARTITION ""
++#endif
++
++#define CONFIG_CMD_READ
++#define CONFIG_SERIAL_TAG
++#define CONFIG_FASTBOOT_USB_DEV 0
++
++#define CONFIG_MFG_ENV_SETTINGS \
++ CONFIG_MFG_ENV_SETTINGS_DEFAULT \
++ "initrd_addr=0x86800000\0" \
++ "initrd_high=0xffffffff\0" \
++ "emmc_dev=1\0"\
++ "emmc_ack=1\0"\
++ "sd_dev=1\0" \
++ "mtdparts=" MFG_NAND_PARTITION \
++ "\0"\
++
++#if defined(CONFIG_NAND_BOOT)
++#define CONFIG_EXTRA_ENV_SETTINGS \
++ CONFIG_MFG_ENV_SETTINGS \
++ TEE_ENV \
++ "splashimage=0x8c000000\0" \
++ "fdt_addr=0x83000000\0" \
++ "fdt_high=0xffffffff\0" \
++ "tee_addr=0x84000000\0" \
++ "console=ttymxc0\0" \
++ "bootargs=console=ttymxc0,115200 ubi.mtd=nandrootfs " \
++ "root=ubi0:rootfs rootfstype=ubifs " \
++ BOOTARGS_CMA_SIZE \
++ MFG_NAND_PARTITION \
++ "\0" \
++ "bootcmd=nand read ${loadaddr} 0x4000000 0xc00000;"\
++ "nand read ${fdt_addr} 0x5000000 0x100000;"\
++ "if test ${tee} = yes; then " \
++ "nand read ${tee_addr} 0x6000000 0x400000;"\
++ "bootm ${tee_addr} - ${fdt_addr};" \
++ "else " \
++ "bootz ${loadaddr} - ${fdt_addr};" \
++ "fi\0"
++
++#else
++#include "igkboard_overlay.h"
++
++#define CONFIG_EXTRA_ENV_SETTINGS \
++ "env_conf=config.txt\0" \
++ "image=zImage\0" \
++ "console=ttymxc0\0" \
++ "fdt_file=igkboard.dtb\0" \
++ "fdt_addr=0x83000000\0" \
++ "splashimage=0x8c000000\0" \
+ "ipaddr=192.168.2.22\0" \
+ "serverip=192.168.2.2\0" \
+ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
-+ "mmcargs=setenv bootargs console=${console},${baudrate} root=/dev/mmcblk${mmc_no}p2 rootwait rw\0" \
-+ "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
-+ "bootscript=echo Running bootscript from mmc ...; source\0" \
- "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
- "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
-- "loadtee=fatload mmc ${mmcdev}:${mmcpart} ${tee_addr} ${tee_file}\0" \
++ "mmcargs=setenv bootargs console=${console},${baudrate} root=/dev/mmcblk${mmc_no}p2 rootwait rw net.ifnames=0\0" \
++ "loadenvconf=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${env_conf};env import -t ${loadaddr} ${filesize}\0" \
++ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
++ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "bdtb=tftp $fdt_addr $fdt_file && fatwrite mmc 1:1 $fdt_addr $fdt_file $filesize\0" \
+ "bker=tftp $loadaddr $image&& fatwrite mmc 1:1 $loadaddr $image $filesize\0" \
+ "bsys=run bdtb && run bker\0" \
- "mmcboot=echo Booting from mmc ...; " \
++ "mmcboot=echo Booting from mmc ...; " \
+ "mmc dev ${mmcdev}; " \
++ "run mmcargs; run loadenvconf;" \
+ "run loadimage; run loadfdt; " \
- "run mmcargs; " \
-- "if test ${tee} = yes; then " \
-- "run loadfdt; run loadtee; bootm ${tee_addr} - ${fdt_addr}; " \
-- "else " \
-- "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-- "if run loadfdt; then " \
-- "bootz ${loadaddr} - ${fdt_addr}; " \
-- "else " \
-- "if test ${boot_fdt} = try; then " \
-- "bootz; " \
-- "else " \
-- "echo WARN: Cannot load the DT; " \
-- "fi; " \
-- "fi; " \
-- "else " \
-- "bootz; " \
-- "fi; " \
-- "fi;\0" \
-- "netargs=setenv bootargs console=${console},${baudrate} " \
-- BOOTARGS_CMA_SIZE \
-- "root=/dev/nfs " \
-- "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
-- "netboot=echo Booting from net ...; " \
-- "${usb_net_cmd}; " \
-- "run netargs; " \
-- "if test ${ip_dyn} = yes; then " \
-- "setenv get_cmd dhcp; " \
-- "else " \
-- "setenv get_cmd tftp; " \
-- "fi; " \
-- "${get_cmd} ${image}; " \
-- "if test ${tee} = yes; then " \
-- "${get_cmd} ${tee_addr} ${tee_file}; " \
-- "${get_cmd} ${fdt_addr} ${fdt_file}; " \
-- "bootm ${tee_addr} - ${fdt_addr}; " \
-- "else " \
-- "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-- "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-- "bootz ${loadaddr} - ${fdt_addr}; " \
-- "else " \
-- "if test ${boot_fdt} = try; then " \
-- "bootz; " \
-- "else " \
-- "echo WARN: Cannot load the DT; " \
-- "fi; " \
-- "fi; " \
-- "else " \
-- "bootz; " \
-- "fi; " \
-- "fi;\0" \
-- "findfdt="\
-- "if test $fdt_file = undefined; then " \
-- "if test $board_name = ULZ-EVK && test $board_rev = 14X14; then " \
-- "setenv fdt_file imx6ulz-14x14-evk.dtb; fi; " \
-- "if test $board_name = EVK && test $board_rev = 9X9; then " \
-- "setenv fdt_file imx6ull-9x9-evk.dtb; fi; " \
-- "if test $board_name = EVK && test $board_rev = 14X14; then " \
-- "setenv fdt_file imx6ull-14x14-evk.dtb; fi; " \
-- "if test $fdt_file = undefined; then " \
-- "echo WARNING: Could not determine dtb to use; " \
-- "fi; " \
-- "fi;\0" \
-- "findtee="\
-- "if test $tee_file = undefined; then " \
-- "if test $board_name = ULZ-EVK && test $board_rev = 14X14; then " \
-- "setenv tee_file uTee-6ulzevk; fi; " \
-- "if test $board_name = EVK && test $board_rev = 9X9; then " \
-- "setenv tee_file uTee-6ullevk; fi; " \
-- "if test $board_name = EVK && test $board_rev = 14X14; then " \
-- "setenv tee_file uTee-6ullevk; fi; " \
-- "if test $tee_file = undefined; then " \
-- "echo WARNING: Could not determine tee to use; " \
-- "fi; " \
-- "fi;\0" \
--
--#define CONFIG_BOOTCOMMAND \
-- "run findfdt;" \
-- "run findtee;" \
-- "mmc dev ${mmcdev};" \
-- "mmc dev ${mmcdev}; if mmc rescan; then " \
-- "if run loadbootscript; then " \
-- "run bootscript; " \
-- "else " \
-- "if run loadimage; then " \
-- "run mmcboot; " \
-- "else run netboot; " \
-- "fi; " \
-- "fi; " \
-- "else run netboot; fi"
-+ "run loadbootscript; run bootscript; " \
+ "bootz ${loadaddr} - ${fdt_addr}\0" \
+ "netboot=echo Booting from net ...; " \
+ "tftp $loadaddr $image; tftp $fdt_addr ${fdt_file};" \
+ "run mmcargs; " \
+ "bootz ${loadaddr} - ${fdt_addr}\0" \
-+ "bootcmd=run mmcboot\0" \
+ "upmode=fastboot 0\0" \
-+ "bbl=tftp ${loadaddr} u-boot-igkboard-emmc.imx && mmc dev ${mmcdev} 1 && mmc write ${loadaddr} 2 0x500\0"
- #endif
-
- /* Miscellaneous configurable options */
-@@ -238,7 +152,9 @@
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
- /* environment organization */
-+#ifndef CONFIG_SYS_MMC_ENV_DEV
- #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
++ "bbl=tftp ${loadaddr} u-boot-igkboard.imx && mmc dev ${mmcdev} 1 && mmc write ${loadaddr} 2 0x500\0" \
++ MMC_FDT_OVERLAY_SETTING \
++ "bootcmd=run mmcbootdto\0"
+#endif
- #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
-
- #define CONFIG_IOMUX_LPSR
-diff -Nuar uboot-imx/Makefile uboot-imx-igkboard/Makefile
++
++
++/* Miscellaneous configurable options */
++
++#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
++#define CONFIG_SYS_HZ 1000
++
++/* Physical Memory Map */
++#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
++
++#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
++#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
++#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
++
++#define CONFIG_SYS_INIT_SP_OFFSET \
++ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
++#define CONFIG_SYS_INIT_SP_ADDR \
++ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
++
++/* environment organization */
++#ifndef CONFIG_SYS_MMC_ENV_DEV
++#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
++#endif
++#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
++
++#define CONFIG_IOMUX_LPSR
++
++/* NAND stuff */
++#ifdef CONFIG_NAND_MXS
++#define CONFIG_SYS_MAX_NAND_DEVICE 1
++#define CONFIG_SYS_NAND_BASE 0x40000000
++#define CONFIG_SYS_NAND_5_ADDR_CYCLE
++#define CONFIG_SYS_NAND_ONFI_DETECTION
++#define CONFIG_SYS_NAND_USE_FLASH_BBT
++
++/* DMA stuff, needed for GPMI/MXS NAND support */
++#endif
++
++#if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
++#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
++#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
++#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
++#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
++#endif
++
++/* USB Configs */
++#ifdef CONFIG_CMD_USB
++#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
++#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
++#define CONFIG_MXC_USB_FLAGS 0
++#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
++#endif
++
++#define CONFIG_FEC_XCV_TYPE RMII
++#define CONFIG_ETHPRIME "eth1"
++
++#ifndef CONFIG_SPL_BUILD
++#if defined(CONFIG_DM_VIDEO)
++#define CONFIG_VIDEO_MXS
++#define CONFIG_VIDEO_LINK
++#define CONFIG_VIDEO_LOGO
++#define CONFIG_BMP_16BPP
++#define CONFIG_VIDEO_BMP_RLE8
++#define CONFIG_VIDEO_BMP_LOGO
++#endif
++#endif
++
++#endif
+diff -Nuar -x lingyun.bmp uboot-imx/include/configs/igkboard_overlay.h uboot-imx-lf-5.10.52-2.1.0/include/configs/igkboard_overlay.h
+--- uboot-imx/include/configs/igkboard_overlay.h 1970-01-01 08:00:00.000000000 +0800
++++ uboot-imx-lf-5.10.52-2.1.0/include/configs/igkboard_overlay.h 2022-06-30 20:28:15.843187892 +0800
+@@ -0,0 +1,88 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright (C) 2022 LingYun IoT System Studio
++ *
++ * Device Tree overlay env for the LingYun IoT Gateway Board.
++ */
++#ifndef __IGKBOARD_OVERLAY_H
++#define __IGKBOARD_OVERLAY_H
++
++#if 0
++ dtoverlay_xxx is set in uEnv.txt, then load the corresponding dtbo file
++
++ if env exists dtoverlay_lcd && test ${dtoverlay_lcd} = 1 -o ${dtoverlay_lcd} = yes ; then
++ dtbo_file=lcd.dtbo;
++ echo "Applying DT overlay: $dtbo_file";
++ fatload mmc ${mmcdev}:${mmcpart} ${dtbo_addr} ${dtbo_dir}/${dtbo_file};
++ fdt addr ${fdt_addr};
++ fdt resize ${fdt_size};
++ fdt apply ${dtbo_addr};
++ fi;
++
++
++ if env exists dtoverlay_uart ; then
++ for i in ${dtoverlay_uart};
++ do
++ dtbo_file=uart$i.dtbo;
++ echo "Applying DT overlay: $dtbo_file";
++ fatload mmc ${mmcdev}:${mmcpart} ${dtbo_addr} ${dtbo_dir}/${dtbo_file};
++ fdt addr ${fdt_addr};
++ fdt apply ${dtbo_addr};
++ done;
++ fi;
++
++#endif
++
++
++#define FDT_APPLY_OVERLAY() \
++ "echo Applying DT overlay ==> ${dtbo_file}; " \
++ "fatload mmc ${mmcdev}:${mmcpart} ${dtbo_addr} ${dtbo_dir}/${dtbo_file}; " \
++ "fdt addr ${fdt_addr}; " \
++ "fdt resize ${fdt_size}; " \
++ "fdt apply ${dtbo_addr}; "
++
++#define CHECK_APPLY_OVERLAY( name ) \
++ "if env exists dtoverlay_" name " && test ${dtoverlay_" name "} = 1 -o ${dtoverlay_" name "} = yes ; then " \
++ "setenv dtbo_file " name ".dtbo; " \
++ FDT_APPLY_OVERLAY() \
++ "fi; "
++
++#define CHECK_APPLY_OVERLAYS_IDX( name ) \
++ "if env exists dtoverlay_" name "; then " \
++ "for i in ${dtoverlay_" name "}; do " \
++ "setenv dtbo_file " name "$i.dtbo; " \
++ FDT_APPLY_OVERLAY() \
++ " done;" \
++ "fi; "
++
++#define CHECK_APPLY_OVERLAYS_DTBO( name ) \
++ "if env exists dtoverlay_" name "; then " \
++ "for f in ${dtoverlay_" name "}; do " \
++ "setenv dtbo_file $f.dtbo; " \
++ FDT_APPLY_OVERLAY() \
++ " done;" \
++ "fi; "
++
++#define FDT_ENTRY_DEF_SETTINGS \
++ CHECK_APPLY_OVERLAY("lcd") \
++ CHECK_APPLY_OVERLAY("cam") \
++ CHECK_APPLY_OVERLAY("i2c1") \
++ CHECK_APPLY_OVERLAY("spi1") \
++ CHECK_APPLY_OVERLAYS_IDX("uart") \
++ CHECK_APPLY_OVERLAYS_IDX("can") \
++ CHECK_APPLY_OVERLAYS_IDX("pwm") \
++ CHECK_APPLY_OVERLAYS_DTBO("extra") \
++
++#define MMC_FDT_OVERLAY_SETTING \
++ "fdt_size=0x10000\0" \
++ "dtbo_addr=0x83010000\0" \
++ "dtbo_dir=overlays\0" \
++ "mmcbootdto=echo Booting from mmc with overlay...; " \
++ "mmc dev ${mmcdev}; run mmcargs; run loadenvconf; " \
++ "run loadimage; run loadfdt; " \
++ FDT_ENTRY_DEF_SETTINGS \
++ "bootz ${loadaddr} - ${fdt_addr}\0"
++
++#define ENABLE_UENV_FDTO_SUPPORT
++
++#endif
+diff -Nuar -x lingyun.bmp uboot-imx/Makefile uboot-imx-lf-5.10.52-2.1.0/Makefile
--- uboot-imx/Makefile 2021-09-06 16:48:23.000000000 +0800
-+++ uboot-imx-igkboard/Makefile 2021-12-26 19:58:58.142407641 +0800
++++ uboot-imx-lf-5.10.52-2.1.0/Makefile 2022-06-30 20:28:15.855187718 +0800
@@ -263,6 +263,9 @@
CROSS_COMPILE ?=
endif
--
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