From e77618540841b570ae6688e5f9469c77c0619112 Mon Sep 17 00:00:00 2001
From: guowenxue <guowenxue@gmail.com>
Date: Thu, 06 Oct 2022 16:12:01 +0800
Subject: [PATCH] update uboot,linux kernel patch to remove space
---
yocto/honister/meta-igkboard/recipes-bsp/u-boot/files/uboot-imx-lf-5.10.52-2.1.0.patch | 62 ++++++++++----------
bsp/bootloader/patch/uboot-imx-lf-5.10.52-2.1.0.patch | 62 ++++++++++----------
yocto/honister/meta-igkboard/recipes-bsp/u-boot/u-boot-imx_2021.04.bbappend | 4
bsp/bootloader/patch/uboot-imx-lf-5.15.32-2.0.0.patch | 38 ++++++------
bsp/kernel/patch/linux-imx-lf-5.10.52-2.1.0.patch | 14 ++--
5 files changed, 90 insertions(+), 90 deletions(-)
diff --git a/bsp/bootloader/patch/uboot-imx-lf-5.10.52-2.1.0.patch b/bsp/bootloader/patch/uboot-imx-lf-5.10.52-2.1.0.patch
index 7444044..140def7 100644
--- a/bsp/bootloader/patch/uboot-imx-lf-5.10.52-2.1.0.patch
+++ b/bsp/bootloader/patch/uboot-imx-lf-5.10.52-2.1.0.patch
@@ -41,7 +41,7 @@
+ phy-reset-post-delay = <15>;
status = "okay";
};
-
+
@@ -91,14 +93,17 @@
pinctrl-0 = <&pinctrl_enet2>;
phy-mode = "rmii";
@@ -50,11 +50,11 @@
+ phy-reset-duration = <50>;
+ phy-reset-post-delay = <15>;
status = "okay";
-
+
mdio {
#address-cells = <1>;
#size-cells = <0>;
-
+
- ethphy0: ethernet-phy@2 {
- reg = <2>;
+ ethphy0: ethernet-phy@0 {
@@ -68,16 +68,16 @@
pinctrl-0 = <&pinctrl_lcdif_dat
- &pinctrl_lcdif_ctrl>;
+ &pinctrl_lcdif_ctrl>;
-
+
display = <&display0>;
status = "okay";
-
+
display0: display@0 {
- bits-per-pixel = <24>;
- bus-width = <24>;
+ bits-per-pixel = <16>;
+ bus-width = <16>;
-
+
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
@@ -99,11 +99,11 @@
+ vback-porch = <32>;
+ vfront-porch = <13>;
+ vsync-len = <3>;
-
+
hsync-active = <0>;
vsync-active = <0>;
@@ -284,6 +289,40 @@
-
+
&iomuxc {
pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_extgpio>;
@@ -140,7 +140,7 @@
+ MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x17059 /* 40# GPIO */
+ >;
+ };
-
+
pinctrl_csi1: csi1grp {
fsl,pins = <
@@ -306,12 +345,13 @@
@@ -160,7 +160,7 @@
+ MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x10B0 /* ENET1 RESET */
>;
};
-
+
@@ -321,12 +361,13 @@
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
@@ -178,9 +178,9 @@
+ MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x10B0 /* ENET2 RESET */
>;
};
-
+
@@ -367,41 +408,33 @@
-
+
pinctrl_lcdif_dat: lcdifdatgrp {
fsl,pins = <
- MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
@@ -225,7 +225,7 @@
+ MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
>;
};
-
+
pinctrl_lcdif_ctrl: lcdifctrlgrp {
fsl,pins = <
- MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
@@ -241,7 +241,7 @@
+ MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
>;
};
-
+
@@ -409,8 +442,8 @@
fsl,pins = <
MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
@@ -264,14 +264,14 @@
- MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059
>;
};
-
+
pinctrl_pwm1: pwm1grp {
fsl,pins = <
- MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
+ MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
>;
};
-
+
@@ -448,7 +480,6 @@
fsl,pins = <
MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1
@@ -281,7 +281,7 @@
>;
};
@@ -486,22 +517,20 @@
-
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
@@ -301,7 +301,7 @@
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
>;
};
-
+
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
@@ -312,7 +312,7 @@
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
@@ -512,8 +541,8 @@
-
+
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
@@ -323,7 +323,7 @@
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
@@ -523,8 +552,8 @@
-
+
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
@@ -334,7 +334,7 @@
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
@@ -534,8 +563,8 @@
-
+
pinctrl_usdhc2_8bit: usdhc2grp_8bit {
fsl,pins = <
- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
@@ -345,7 +345,7 @@
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
@@ -549,8 +578,8 @@
-
+
pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz {
fsl,pins = <
- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
@@ -356,7 +356,7 @@
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
@@ -564,8 +593,8 @@
-
+
pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz {
fsl,pins = <
- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
@@ -371,7 +371,7 @@
+++ uboot-imx-lf-5.10.52-2.1.0/arch/arm/dts/Makefile 2022-06-30 20:28:15.839187950 +0800
@@ -779,6 +779,7 @@
imx6ul-pico-pi.dtb
-
+
dtb-$(CONFIG_MX6ULL) += \
+ igkboard.dtb \
imx6ull-14x14-ddr3-val.dtb \
@@ -383,7 +383,7 @@
@@ -158,6 +158,16 @@
prompt "MX6 board select"
optional
-
+
+config TARGET_LINGYUN_IGKBOARD
+ bool "LingYun IoT Gateway Kits Board(IGKBoard)"
+ depends on MX6ULL
@@ -401,8 +401,8 @@
source "board/wandboard/Kconfig"
source "board/warp/Kconfig"
source "board/BuR/brppt2/Kconfig"
-+source "board/lingyun/igkboard/Kconfig"
-
++source "board/lingyun/igkboard/Kconfig"
+
endif
diff -Nuar -x lingyun.bmp uboot-imx/board/lingyun/igkboard/igkboard.c uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/igkboard.c
--- uboot-imx/board/lingyun/igkboard/igkboard.c 1970-01-01 08:00:00.000000000 +0800
@@ -1459,13 +1459,13 @@
@@ -182,6 +182,9 @@
{
int result;
-
+
+ /* add Soft Reset the PHY by guowenxue, 2021.11.14 */
+ phy_reset(phydev);
+
if (phydev->autoneg != AUTONEG_ENABLE)
return genphy_setup_forced(phydev);
-
+
diff -Nuar -x lingyun.bmp uboot-imx/include/configs/igkboard.h uboot-imx-lf-5.10.52-2.1.0/include/configs/igkboard.h
--- uboot-imx/include/configs/igkboard.h 1970-01-01 08:00:00.000000000 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/include/configs/igkboard.h 2022-06-30 20:28:15.839187950 +0800
@@ -1768,10 +1768,10 @@
@@ -263,6 +263,9 @@
CROSS_COMPILE ?=
endif
-
+
+ARCH=arm
+CROSS_COMPILE?=/opt/buildroot/cortexA7/bin/arm-linux-
+
KCONFIG_CONFIG ?= .config
export KCONFIG_CONFIG
-
+
diff --git a/bsp/bootloader/patch/uboot-imx-lf-5.15.32-2.0.0.patch b/bsp/bootloader/patch/uboot-imx-lf-5.15.32-2.0.0.patch
index 83a1463..eeb654e 100644
--- a/bsp/bootloader/patch/uboot-imx-lf-5.15.32-2.0.0.patch
+++ b/bsp/bootloader/patch/uboot-imx-lf-5.15.32-2.0.0.patch
@@ -33,7 +33,7 @@
+ phy-reset-post-delay = <15>;
status = "okay";
};
-
+
@@ -91,14 +94,17 @@
pinctrl-0 = <&pinctrl_enet2>;
phy-mode = "rmii";
@@ -42,11 +42,11 @@
+ phy-reset-duration = <50>;
+ phy-reset-post-delay = <15>;
status = "okay";
-
+
mdio {
#address-cells = <1>;
#size-cells = <0>;
-
+
- ethphy0: ethernet-phy@2 {
- reg = <2>;
+ ethphy0: ethernet-phy@0 {
@@ -56,13 +56,13 @@
clock-names = "rmii-ref";
@@ -151,21 +157,21 @@
status = "okay";
-
+
display0: display@0 {
- bits-per-pixel = <24>;
- bus-width = <24>;
+ bits-per-pixel = <16>;
+ bus-width = <16>;
-
+
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
@@ -84,11 +84,11 @@
+ vback-porch = <32>;
+ vfront-porch = <13>;
+ vsync-len = <3>;
-
+
hsync-active = <0>;
vsync-active = <0>;
@@ -284,6 +290,40 @@
-
+
&iomuxc {
pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_extgpio>;
@@ -125,7 +125,7 @@
+ MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x17059 /* 40# GPIO */
+ >;
+ };
-
+
pinctrl_csi1: csi1grp {
fsl,pins = <
@@ -312,6 +352,7 @@
@@ -135,7 +135,7 @@
+ MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x10B0 /* ENET1 RESET */
>;
};
-
+
@@ -327,6 +368,7 @@
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
@@ -143,7 +143,7 @@
+ MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x10B0 /* ENET2 RESET */
>;
};
-
+
@@ -384,13 +426,6 @@
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
@@ -157,7 +157,7 @@
- MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
>;
};
-
+
@@ -423,7 +458,6 @@
MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
@@ -165,7 +165,7 @@
- MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059
>;
};
-
+
@@ -448,7 +482,6 @@
fsl,pins = <
MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1
@@ -179,7 +179,7 @@
+++ uboot-imx-lf-5.15.32-2.0.0/arch/arm/dts/Makefile 2022-09-04 15:05:50.936174546 +0800
@@ -871,6 +871,7 @@
imx6ull-kontron-n641x-s.dtb
-
+
dtb-$(CONFIG_MX6ULL) += \
+ igkboard.dtb \
imx6ull-14x14-ddr3-val.dtb \
@@ -191,7 +191,7 @@
@@ -157,6 +157,16 @@
prompt "MX6 board select"
optional
-
+
+config TARGET_LINGYUN_IGKBOARD
+ bool "LingYun IoT Gateway Kits Board(IGKBoard)"
+ depends on MX6ULL
@@ -210,7 +210,7 @@
source "board/BuR/brppt2/Kconfig"
source "board/out4/o4-imx6ull-nano/Kconfig"
+source "board/lingyun/igkboard/Kconfig"
-
+
endif
diff -Nuar -x lingyun.bmp uboot-imx/board/lingyun/igkboard/igkboard.c uboot-imx-lf-5.15.32-2.0.0/board/lingyun/igkboard/igkboard.c
--- uboot-imx/board/lingyun/igkboard/igkboard.c 1970-01-01 08:00:00.000000000 +0800
@@ -1257,12 +1257,12 @@
@@ -182,6 +182,8 @@
{
int result;
-
+
+ phy_reset(phydev);
+
if (phydev->autoneg != AUTONEG_ENABLE)
return genphy_setup_forced(phydev);
-
+
diff -Nuar -x lingyun.bmp uboot-imx/include/configs/igkboard.h uboot-imx-lf-5.15.32-2.0.0/include/configs/igkboard.h
--- uboot-imx/include/configs/igkboard.h 1970-01-01 08:00:00.000000000 +0800
+++ uboot-imx-lf-5.15.32-2.0.0/include/configs/igkboard.h 2022-09-04 15:05:50.940174512 +0800
@@ -1538,13 +1538,13 @@
@@ -273,6 +273,9 @@
CROSS_COMPILE ?=
endif
-
+
+ARCH = arm
+CROSS_COMPILE ?= /opt/buildroot/cortexA7/bin/arm-linux-
+
KCONFIG_CONFIG ?= .config
export KCONFIG_CONFIG
-
+
diff -Nuar -x lingyun.bmp uboot-imx/tools/boot/bootm.c uboot-imx-lf-5.15.32-2.0.0/tools/boot/bootm.c
--- uboot-imx/tools/boot/bootm.c 1970-01-01 08:00:00.000000000 +0800
+++ uboot-imx-lf-5.15.32-2.0.0/tools/boot/bootm.c 2022-09-04 15:05:57.424118419 +0800
diff --git a/bsp/kernel/patch/linux-imx-lf-5.10.52-2.1.0.patch b/bsp/kernel/patch/linux-imx-lf-5.10.52-2.1.0.patch
index 167bb23..0e14b5c 100644
--- a/bsp/kernel/patch/linux-imx-lf-5.10.52-2.1.0.patch
+++ b/bsp/kernel/patch/linux-imx-lf-5.10.52-2.1.0.patch
@@ -1900,7 +1900,7 @@
@@ -136,12 +136,12 @@
.fw_name = "rtl_bt/rtl8761a_fw.bin",
.cfg_name = "rtl_bt/rtl8761a_config" },
-
+
- /* 8761B */
+ /* 8761BU */
{ IC_INFO(RTL_ROM_LMP_8761A, 0xb),
@@ -1910,7 +1910,7 @@
- .cfg_name = "rtl_bt/rtl8761b_config" },
+ .fw_name = "rtl_bt/rtl8761bu_fw.bin",
+ .cfg_name = "rtl_bt/rtl8761bu_config" },
-
+
/* 8822C with UART interface */
{ .match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_HCIREV |
diff -Nuar --no-dereference -x logo_linux_clut224.ppm linux-imx/drivers/bluetooth/btusb.c linux-imx-lf-5.10.52-2.1.0/drivers/bluetooth/btusb.c
@@ -1919,7 +1919,7 @@
@@ -419,6 +419,9 @@
{ USB_DEVICE(0x0bda, 0xb009), .driver_info = BTUSB_REALTEK },
{ USB_DEVICE(0x2ff8, 0xb011), .driver_info = BTUSB_REALTEK },
-
+
+ /* Additional Realtek 8761B Bluetooth devices */
+ { USB_DEVICE(0x2357, 0x0604), .driver_info = BTUSB_REALTEK },
+
@@ -1932,7 +1932,7 @@
@@ -558,6 +558,7 @@
if (!state.period && (data->pwm_period_ns > 0))
state.period = data->pwm_period_ns;
-
+
+ state.enabled = true; /* Add by guowenxue to enalbe backlight as default */
ret = pwm_apply_state(pb->pwm, &state);
if (ret) {
@@ -1947,7 +1947,7 @@
-ARCH ?= $(SUBARCH)
+ARCH ?= arm
+CROSS_COMPILE?=/opt/buildroot/cortexA7/bin/arm-linux-
-
+
# Architecture as present in compile.h
UTS_MACHINE := $(ARCH)
@@ -1833,6 +1834,7 @@
@@ -1964,7 +1964,7 @@
@@ -325,6 +325,16 @@
$(obj)/%.dtb: $(src)/%.dts $(DTC) FORCE
$(call if_changed_dep,dtc)
-
+
+quiet_cmd_dtco = DTCO $@
+cmd_dtco = $(HOSTCC) -E $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \
+ $(DTC) -O dtb -o $@ -b 0 \
@@ -1984,7 +1984,7 @@
@@ -1349,7 +1349,7 @@
sai->bus_clk = NULL;
}
-
+
- for (i = 0; i < FSL_SAI_MCLK_MAX; i++) {
+ for (i = 1; i < FSL_SAI_MCLK_MAX; i++) {
sprintf(tmp, "mclk%d", i);
diff --git a/yocto/honister/meta-igkboard/recipes-bsp/u-boot/files/uboot-imx-lf-5.10.52-2.1.0.patch b/yocto/honister/meta-igkboard/recipes-bsp/u-boot/files/uboot-imx-lf-5.10.52-2.1.0.patch
index 7444044..140def7 100644
--- a/yocto/honister/meta-igkboard/recipes-bsp/u-boot/files/uboot-imx-lf-5.10.52-2.1.0.patch
+++ b/yocto/honister/meta-igkboard/recipes-bsp/u-boot/files/uboot-imx-lf-5.10.52-2.1.0.patch
@@ -41,7 +41,7 @@
+ phy-reset-post-delay = <15>;
status = "okay";
};
-
+
@@ -91,14 +93,17 @@
pinctrl-0 = <&pinctrl_enet2>;
phy-mode = "rmii";
@@ -50,11 +50,11 @@
+ phy-reset-duration = <50>;
+ phy-reset-post-delay = <15>;
status = "okay";
-
+
mdio {
#address-cells = <1>;
#size-cells = <0>;
-
+
- ethphy0: ethernet-phy@2 {
- reg = <2>;
+ ethphy0: ethernet-phy@0 {
@@ -68,16 +68,16 @@
pinctrl-0 = <&pinctrl_lcdif_dat
- &pinctrl_lcdif_ctrl>;
+ &pinctrl_lcdif_ctrl>;
-
+
display = <&display0>;
status = "okay";
-
+
display0: display@0 {
- bits-per-pixel = <24>;
- bus-width = <24>;
+ bits-per-pixel = <16>;
+ bus-width = <16>;
-
+
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
@@ -99,11 +99,11 @@
+ vback-porch = <32>;
+ vfront-porch = <13>;
+ vsync-len = <3>;
-
+
hsync-active = <0>;
vsync-active = <0>;
@@ -284,6 +289,40 @@
-
+
&iomuxc {
pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_extgpio>;
@@ -140,7 +140,7 @@
+ MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x17059 /* 40# GPIO */
+ >;
+ };
-
+
pinctrl_csi1: csi1grp {
fsl,pins = <
@@ -306,12 +345,13 @@
@@ -160,7 +160,7 @@
+ MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x10B0 /* ENET1 RESET */
>;
};
-
+
@@ -321,12 +361,13 @@
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
@@ -178,9 +178,9 @@
+ MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x10B0 /* ENET2 RESET */
>;
};
-
+
@@ -367,41 +408,33 @@
-
+
pinctrl_lcdif_dat: lcdifdatgrp {
fsl,pins = <
- MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
@@ -225,7 +225,7 @@
+ MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
>;
};
-
+
pinctrl_lcdif_ctrl: lcdifctrlgrp {
fsl,pins = <
- MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
@@ -241,7 +241,7 @@
+ MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
>;
};
-
+
@@ -409,8 +442,8 @@
fsl,pins = <
MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
@@ -264,14 +264,14 @@
- MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059
>;
};
-
+
pinctrl_pwm1: pwm1grp {
fsl,pins = <
- MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
+ MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
>;
};
-
+
@@ -448,7 +480,6 @@
fsl,pins = <
MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1
@@ -281,7 +281,7 @@
>;
};
@@ -486,22 +517,20 @@
-
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
@@ -301,7 +301,7 @@
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
>;
};
-
+
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
@@ -312,7 +312,7 @@
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
@@ -512,8 +541,8 @@
-
+
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
@@ -323,7 +323,7 @@
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
@@ -523,8 +552,8 @@
-
+
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
@@ -334,7 +334,7 @@
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
@@ -534,8 +563,8 @@
-
+
pinctrl_usdhc2_8bit: usdhc2grp_8bit {
fsl,pins = <
- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
@@ -345,7 +345,7 @@
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
@@ -549,8 +578,8 @@
-
+
pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz {
fsl,pins = <
- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
@@ -356,7 +356,7 @@
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
@@ -564,8 +593,8 @@
-
+
pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz {
fsl,pins = <
- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
@@ -371,7 +371,7 @@
+++ uboot-imx-lf-5.10.52-2.1.0/arch/arm/dts/Makefile 2022-06-30 20:28:15.839187950 +0800
@@ -779,6 +779,7 @@
imx6ul-pico-pi.dtb
-
+
dtb-$(CONFIG_MX6ULL) += \
+ igkboard.dtb \
imx6ull-14x14-ddr3-val.dtb \
@@ -383,7 +383,7 @@
@@ -158,6 +158,16 @@
prompt "MX6 board select"
optional
-
+
+config TARGET_LINGYUN_IGKBOARD
+ bool "LingYun IoT Gateway Kits Board(IGKBoard)"
+ depends on MX6ULL
@@ -401,8 +401,8 @@
source "board/wandboard/Kconfig"
source "board/warp/Kconfig"
source "board/BuR/brppt2/Kconfig"
-+source "board/lingyun/igkboard/Kconfig"
-
++source "board/lingyun/igkboard/Kconfig"
+
endif
diff -Nuar -x lingyun.bmp uboot-imx/board/lingyun/igkboard/igkboard.c uboot-imx-lf-5.10.52-2.1.0/board/lingyun/igkboard/igkboard.c
--- uboot-imx/board/lingyun/igkboard/igkboard.c 1970-01-01 08:00:00.000000000 +0800
@@ -1459,13 +1459,13 @@
@@ -182,6 +182,9 @@
{
int result;
-
+
+ /* add Soft Reset the PHY by guowenxue, 2021.11.14 */
+ phy_reset(phydev);
+
if (phydev->autoneg != AUTONEG_ENABLE)
return genphy_setup_forced(phydev);
-
+
diff -Nuar -x lingyun.bmp uboot-imx/include/configs/igkboard.h uboot-imx-lf-5.10.52-2.1.0/include/configs/igkboard.h
--- uboot-imx/include/configs/igkboard.h 1970-01-01 08:00:00.000000000 +0800
+++ uboot-imx-lf-5.10.52-2.1.0/include/configs/igkboard.h 2022-06-30 20:28:15.839187950 +0800
@@ -1768,10 +1768,10 @@
@@ -263,6 +263,9 @@
CROSS_COMPILE ?=
endif
-
+
+ARCH=arm
+CROSS_COMPILE?=/opt/buildroot/cortexA7/bin/arm-linux-
+
KCONFIG_CONFIG ?= .config
export KCONFIG_CONFIG
-
+
diff --git a/yocto/honister/meta-igkboard/recipes-bsp/u-boot/u-boot-imx_2021.04.bbappend b/yocto/honister/meta-igkboard/recipes-bsp/u-boot/u-boot-imx_2021.04.bbappend
index 9aabc69..0fb12d6 100644
--- a/yocto/honister/meta-igkboard/recipes-bsp/u-boot/u-boot-imx_2021.04.bbappend
+++ b/yocto/honister/meta-igkboard/recipes-bsp/u-boot/u-boot-imx_2021.04.bbappend
@@ -1,5 +1,5 @@
# Copyright (C) 2022 LingYun IoT System Studio
-# Released under the GPLv2 license
+# Released under the GPLv2 license
#
# SPDX-License-Identifier: GPLv2
#
@@ -8,7 +8,7 @@
DESCRIPTION = "Linux Kernel provided and supported by LingYun with focus on IGKBoard"
COMPATIBLE_MACHINE = "(mx6)"
-
+
LICENSE = "GPLv2"
LIC_FILES_CHKSUM = "file://${COREBASE}/meta/files/common-licenses/GPL-2.0-only;md5=801f80980d171dd6425610833a22dbe6"
--
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