STM8S/A Standard Peripherals Drivers: STM8S/A Standard Peripherals Library

STM8S/A Standard Peripherals Drivers
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STM8S/A Standard Peripherals Library
STM8S/A Standard Peripherals Drivers

Copyright 2014 STMicroelectronics

The STM8S/A Standard Peripheral Drivers package, consists of device drivers for all of the standard device peripherals, for the STM8S/A 8-bit Flash microcontrollers.

These drivers contain a collection of routines, data structures and macros covering the features of STM8S/A peripherals. They allow any device to be used in the user application without the need for in-depth study of each peripheral’s specifications.

Using the Standard Peripherals drivers has two advantages: it saves significant time that would otherwise be spent in coding, while simultaneously reduces application development and integration costs.

The manual is structured as follows:

Standard Peripheral Drivers

Overview

MISRA-C 2004 Compliance

Run-time Checking

Coding rules and conventions

Acronyms

Naming conventions

Coding rules

Description of Peripherals drivers

Architecture

STM8S/A Standard Peripheral's Drivers

Supported STM8S/A devices and toolchains

Manual tab sheets description:

Modules: Lists the different modules that compose this Library.

Data Structures: Lists the variables, defines, structures, ...

Files: Lists all the files and global.

Directories: List of directories.

Release Notes for STM8S/A Standard Peripherals Drivers

License

censed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.
For complete documentation on STM8S 8-bit microcontrollers platform visit www.st.com

STM8 Standard Peripherals Library: Footer

For complete documentation on STM8 8-bit Microcontrollers platform visit www.st.com


STM8S/A Standard Peripherals Drivers: STM8S/A Standard Peripheral's Drivers

  • Modules
  • Data Structures
  • Files
  • Directories
STM8S/A Standard Peripheral's Drivers

src

  • stm8s_adc1.c
  • stm8s_adc2.c
  • stm8s_awu.c
  • stm8s_beep.c
  • stm8s_can.c
  • stm8s_clk.c
  • stm8s_exti.c
  • stm8s_flash.c
  • stm8s_gpio.c
  • stm8s_i2c.c
  • stm8s_itc.c
  • stm8s_iwdg.c
  • stm8s_rst.c
  • stm8s_spi.c
  • stm8s_tim1.c
  • stm8s_tim2.c
  • stm8s_tim3.c
  • stm8s_tim4.c
  • stm8s_tim5.c
  • stm8s_tim6.c
  • stm8s_uart1.c
  • stm8s_uart2.c
  • stm8s_uart3.c
  • stm8s_uart4.c
  • stm8s_wwdg.c

inc

  • stm8s.h
  • stm8s_adc1.h
  • stm8s_adc2.h
  • stm8s_awu.h
  • stm8s_beep.h
  • stm8s_can.h
  • stm8s_clk.h
  • stm8s_exti.h
  • stm8s_flash.h
  • stm8s_gpio.h
  • stm8s_i2c.h
  • stm8s_itc.h
  • stm8s_iwdg.h
  • stm8s_rst.h
  • stm8s_spi.h
  • stm8s_tim1.h
  • stm8s_tim2.h
  • stm8s_tim3.h
  • stm8s_tim4.h
  • stm8s_tim5.h
  • stm8s_tim6.h
  • stm8s_uart1.h
  • stm8s_uart3.h
  • stm8s_uart2.h
  • stm8s_uart4.h
  • stm8s_wwdg.h


STM8S/A Standard Peripherals Drivers: Exported_types

  • Directories
Defines | Typedefs | Enumerations
Exported_types
STM8S_StdPeriph_Driver

Defines

#define | __I volatile const
IO definitions.
#define | __IO volatile
#define | __O volatile
#define | IS_FUNCTIONALSTATE_OK(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
#define | S16_MAX (32767)
#define | S16_MIN (-32768)
#define | S32_MAX (2147483647)
#define | S32_MIN (-2147483648uL)
#define | S8_MAX (127)
#define | S8_MIN (-128)
#define | U16_MAX (65535u)
#define | U32_MAX (4294967295uL)
#define | U8_MAX (255)

Typedefs

typedef enum FlagStatus | BitAction
typedef enum FlagStatus | BitStatus
typedef signed short | int16_t
typedef signed long | int32_t
typedef signed char | int8_t
typedef enum FlagStatus | ITStatus
typedef int16_t | s16
typedef int32_t | s32
typedef int8_t | s8
typedef uint16_t | u16
typedef uint32_t | u32
typedef uint8_t | u8
typedef unsigned short | uint16_t
typedef unsigned long | uint32_t
typedef unsigned char | uint8_t

Enumerations

enum | bool { FALSE = 0, TRUE = !FALSE }
enum | ErrorStatus { ERROR = 0, SUCCESS = !ERROR }
enum | FlagStatus { RESET = 0, SET = !RESET }
enum | FunctionalState { DISABLE = 0, ENABLE = !DISABLE }

Define Documentation

#define __I volatile const

IO definitions.

define access restrictions to peripheral registers defines 'read only' permissions

Definition at line 206 of file stm8s.h.

#define __IO volatile

defines 'read / write' permissions Signed integer types

Definition at line 208 of file stm8s.h.

Referenced by I2C_CheckEvent(), I2C_GetITStatus(), and I2C_GetLastEvent().

#define __O volatile

defines 'write only' permissions

Definition at line 207 of file stm8s.h.

#define IS_FUNCTIONALSTATE_OK ( STATE ) (((STATE) == DISABLE) || ((STATE) == ENABLE))

Definition at line 236 of file stm8s.h.

Referenced by ADC1_AWDChannelConfig(), ADC1_Cmd(), ADC1_DataBufferCmd(), ADC1_ExternalTriggerConfig(), ADC1_Init(), ADC1_ITConfig(), ADC1_ScanModeCmd(), ADC1_SchmittTriggerConfig(), ADC2_Cmd(), ADC2_ExternalTriggerConfig(), ADC2_Init(), ADC2_ITConfig(), ADC2_SchmittTriggerConfig(), CAN_FilterInit(), CAN_ITConfig(), CAN_TTComModeCmd(), CLK_CCOCmd(), CLK_ClockSwitchCmd(), CLK_ClockSwitchConfig(), CLK_FastHaltWakeUpCmd(), CLK_HSECmd(), CLK_HSICmd(), CLK_ITConfig(), CLK_LSICmd(), CLK_PeripheralClockConfig(), CLK_SlowActiveHaltWakeUpCmd(), FLASH_ITConfig(), GPIO_ExternalPullUpConfig(), I2C_Cmd(), I2C_GeneralCallCmd(), I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_ITConfig(), I2C_SoftwareResetCmd(), I2C_StretchClockCmd(), SPI_CalculateCRCCmd(), SPI_Cmd(), SPI_ITConfig(), SPI_NSSInternalSoftwareCmd(), TIM1_ARRPreloadConfig(), TIM1_CCPreloadControl(), TIM1_CCxCmd(), TIM1_CCxNCmd(), TIM1_Cmd(), TIM1_CtrlPWMOutputs(), TIM1_ITConfig(), TIM1_OC1FastConfig(), TIM1_OC1PreloadConfig(), TIM1_OC2FastConfig(), TIM1_OC2PreloadConfig(), TIM1_OC3FastConfig(), TIM1_OC3PreloadConfig(), TIM1_OC4FastConfig(), TIM1_OC4PreloadConfig(), TIM1_SelectCOM(), TIM1_SelectHallSensor(), TIM1_SelectMasterSlaveMode(), TIM1_UpdateDisableConfig(), TIM2_ARRPreloadConfig(), TIM2_CCxCmd(), TIM2_Cmd(), TIM2_ITConfig(), TIM2_OC1PreloadConfig(), TIM2_OC2PreloadConfig(), TIM2_OC3PreloadConfig(), TIM2_UpdateDisableConfig(), TIM3_ARRPreloadConfig(), TIM3_CCxCmd(), TIM3_Cmd(), TIM3_ITConfig(), TIM3_OC1PreloadConfig(), TIM3_OC2PreloadConfig(), TIM3_UpdateDisableConfig(), TIM4_ARRPreloadConfig(), TIM4_Cmd(), TIM4_ITConfig(), TIM4_UpdateDisableConfig(), TIM5_ARRPreloadConfig(), TIM5_CCxCmd(), TIM5_Cmd(), TIM5_ITConfig(), TIM5_OC1PreloadConfig(), TIM5_OC2PreloadConfig(), TIM5_OC3PreloadConfig(), TIM5_UpdateDisableConfig(), TIM6_ARRPreloadConfig(), TIM6_Cmd(), TIM6_ITConfig(), TIM6_SelectMasterSlaveMode(), TIM6_UpdateDisableConfig(), UART1_HalfDuplexCmd(), UART1_IrDACmd(), UART1_ITConfig(), UART1_LINCmd(), UART1_ReceiverWakeUpCmd(), UART1_SmartCardCmd(), UART1_SmartCardNACKCmd(), UART2_IrDACmd(), UART2_ITConfig(), UART2_LINCmd(), UART2_ReceiverWakeUpCmd(), UART2_SmartCardCmd(), UART2_SmartCardNACKCmd(), UART3_ITConfig(), UART3_LINCmd(), UART3_ReceiverWakeUpCmd(), UART4_HalfDuplexCmd(), UART4_IrDACmd(), UART4_ITConfig(), UART4_LINCmd(), UART4_ReceiverWakeUpCmd(), UART4_SmartCardCmd(), and UART4_SmartCardNACKCmd().

#define S16_MAX (32767)

Definition at line 244 of file stm8s.h.

#define S16_MIN (-32768)

Definition at line 245 of file stm8s.h.

#define S32_MAX (2147483647)

Definition at line 247 of file stm8s.h.

#define S32_MIN (-2147483648uL)

Definition at line 248 of file stm8s.h.

#define S8_MAX (127)

Definition at line 241 of file stm8s.h.

#define S8_MIN (-128)

Definition at line 242 of file stm8s.h.

#define U16_MAX (65535u)

Definition at line 243 of file stm8s.h.

#define U32_MAX (4294967295uL)

Definition at line 246 of file stm8s.h.

#define U8_MAX (255)

Definition at line 240 of file stm8s.h.

Typedef Documentation

typedef enum FlagStatus BitAction
typedef enum FlagStatus BitStatus
typedef signed short int16_t

Definition at line 212 of file stm8s.h.

typedef signed long int32_t

Unsigned integer types

Definition at line 215 of file stm8s.h.

typedef signed char int8_t

Definition at line 211 of file stm8s.h.

typedef enum FlagStatus ITStatus
typedef int16_t s16

Definition at line 223 of file stm8s.h.

typedef int32_t s32

Definition at line 222 of file stm8s.h.

typedef int8_t s8

Definition at line 224 of file stm8s.h.

typedef uint16_t u16

Definition at line 227 of file stm8s.h.

typedef uint32_t u32

Definition at line 226 of file stm8s.h.

typedef uint8_t u8

Definition at line 228 of file stm8s.h.

typedef unsigned short uint16_t

Definition at line 217 of file stm8s.h.

typedef unsigned long uint32_t

STM8 Standard Peripheral Library old types (maintained for legacy purpose)

Definition at line 220 of file stm8s.h.

typedef unsigned char uint8_t

Definition at line 216 of file stm8s.h.

Enumeration Type Documentation

enum bool
Enumerator:
FALSE
TRUE

Definition at line 231 of file stm8s.h.

enum ErrorStatus
Enumerator:
ERROR
SUCCESS

Definition at line 238 of file stm8s.h.

enum FlagStatus
Enumerator:
RESET
SET

Definition at line 233 of file stm8s.h.

enum FunctionalState
Enumerator:
DISABLE
ENABLE

Definition at line 235 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: MAP_FILE_Exported_Types_and_Constants

Data Structures | Typedefs
MAP_FILE_Exported_Types_and_Constants
STM8S_StdPeriph_Driver

Data Structures

struct | GPIO_struct
General Purpose I/Os (GPIO) More...

Typedefs

typedef struct GPIO_struct | GPIO_TypeDef
General Purpose I/Os (GPIO)

Typedef Documentation

typedef struct GPIO_struct GPIO_TypeDef

General Purpose I/Os (GPIO)


STM8S/A Standard Peripherals Drivers: GPIO_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
GPIO_struct Struct Reference
MAP_FILE_Exported_Types_and_Constants

General Purpose I/Os (GPIO) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | CR1
__IO uint8_t | CR2
__IO uint8_t | DDR
__IO uint8_t | IDR
__IO uint8_t | ODR

Detailed Description

General Purpose I/Os (GPIO)

Definition at line 265 of file stm8s.h.

Field Documentation

__IO uint8_t GPIO_struct::CR1

Configuration Register 1

Definition at line 270 of file stm8s.h.

Referenced by GPIO_DeInit(), GPIO_ExternalPullUpConfig(), and GPIO_Init().

__IO uint8_t GPIO_struct::CR2

Configuration Register 2

Definition at line 271 of file stm8s.h.

Referenced by GPIO_DeInit(), and GPIO_Init().

__IO uint8_t GPIO_struct::DDR

Data Direction Register

Definition at line 269 of file stm8s.h.

Referenced by GPIO_DeInit(), and GPIO_Init().

__IO uint8_t GPIO_struct::IDR

Input Data Register

Definition at line 268 of file stm8s.h.

Referenced by GPIO_ReadInputData(), and GPIO_ReadInputPin().

__IO uint8_t GPIO_struct::ODR

Output Data Register

Definition at line 267 of file stm8s.h.

Referenced by GPIO_DeInit(), GPIO_Init(), GPIO_ReadOutputData(), GPIO_Write(), GPIO_WriteHigh(), GPIO_WriteLow(), and GPIO_WriteReverse().

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: GPIO_Registers_Reset_Value

Defines
GPIO_Registers_Reset_Value
STM8S_StdPeriph_Driver

Defines

#define | GPIO_CR1_RESET_VALUE ((uint8_t)0x00)
#define | GPIO_CR2_RESET_VALUE ((uint8_t)0x00)
#define | GPIO_DDR_RESET_VALUE ((uint8_t)0x00)
#define | GPIO_ODR_RESET_VALUE ((uint8_t)0x00)

Define Documentation

#define GPIO_CR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 285 of file stm8s.h.

Referenced by GPIO_DeInit().

#define GPIO_CR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 286 of file stm8s.h.

Referenced by GPIO_DeInit().

#define GPIO_DDR_RESET_VALUE ((uint8_t)0x00)

Definition at line 284 of file stm8s.h.

Referenced by GPIO_DeInit().

#define GPIO_ODR_RESET_VALUE ((uint8_t)0x00)

Definition at line 283 of file stm8s.h.

Referenced by GPIO_DeInit().


STM8S/A Standard Peripherals Drivers: IWDG_Private_Define

Defines
IWDG_Private_Define
STM8S_StdPeriph_Driver

Defines

#define | IWDG_KEY_ENABLE ((uint8_t)0xCC)
Define used to start the watchdog counter down.
#define | IWDG_KEY_REFRESH ((uint8_t)0xAA)
Define used to prevent watchdog reset.

Define Documentation

#define IWDG_KEY_ENABLE ((uint8_t)0xCC)

Define used to start the watchdog counter down.

This value written in the Key register start the watchdog counting down

Definition at line 51 of file stm8s_iwdg.h.

Referenced by IWDG_Enable().

#define IWDG_KEY_REFRESH ((uint8_t)0xAA)

Define used to prevent watchdog reset.

This value written in the Key register prevent the watchdog reset

Definition at line 46 of file stm8s_iwdg.h.

Referenced by IWDG_ReloadCounter().


STM8S/A Standard Peripherals Drivers: IWDG_Private_Macros

Defines
IWDG_Private_Macros
STM8S_StdPeriph_Driver

Defines

#define | IS_IWDG_PRESCALER_OK(VALUE)
Macro used by the assert function in order to check the different values of the prescaler.
#define | IS_IWDG_WRITEACCESS_MODE_OK(MODE) (((MODE) == IWDG_WriteAccess_Enable) || ((MODE) == IWDG_WriteAccess_Disable))
Macro used by the assert function in order to check the different values of the counter register.

Define Documentation

#define IS_IWDG_PRESCALER_OK ( VALUE )
Value:
(((VALUE) == IWDG_Prescaler_4   ) || \
                                     ((VALUE) == IWDG_Prescaler_8   ) || \
                                     ((VALUE) == IWDG_Prescaler_16  ) || \
                                     ((VALUE) == IWDG_Prescaler_32  ) || \
                                     ((VALUE) == IWDG_Prescaler_64  ) || \
                                     ((VALUE) == IWDG_Prescaler_128 ) || \
                                     ((VALUE) == IWDG_Prescaler_256))

Macro used by the assert function in order to check the different values of the prescaler.

Definition at line 65 of file stm8s_iwdg.h.

Referenced by IWDG_SetPrescaler().

#define IS_IWDG_WRITEACCESS_MODE_OK ( MODE ) (((MODE) == IWDG_WriteAccess_Enable) || ((MODE) == IWDG_WriteAccess_Disable))

Macro used by the assert function in order to check the different values of the counter register.

Definition at line 77 of file stm8s_iwdg.h.

Referenced by IWDG_WriteAccessCmd().


STM8S/A Standard Peripherals Drivers: IWDG_Exported_Types

Enumerations
IWDG_Exported_Types
STM8S_StdPeriph_Driver

Enumerations

enum IWDG_Prescaler_TypeDef {
IWDG_Prescaler_4 = (uint8_t)0x00, IWDG_Prescaler_8 = (uint8_t)0x01, IWDG_Prescaler_16 = (uint8_t)0x02, IWDG_Prescaler_32 = (uint8_t)0x03,
IWDG_Prescaler_64 = (uint8_t)0x04, IWDG_Prescaler_128 = (uint8_t)0x05, IWDG_Prescaler_256 = (uint8_t)0x06
}
IWDG prescaler enumaration. More...
enum IWDG_WriteAccess_TypeDef { IWDG_WriteAccess_Enable = (uint8_t)0x55, IWDG_WriteAccess_Disable = (uint8_t)0x00 }
IWDG write access enumeration. More...

Enumeration Type Documentation

enum IWDG_Prescaler_TypeDef

IWDG prescaler enumaration.

Enumerator:
IWDG_Prescaler_4

Used to set prescaler register to 4

IWDG_Prescaler_8

Used to set prescaler register to 8

IWDG_Prescaler_16

Used to set prescaler register to 16

IWDG_Prescaler_32

Used to set prescaler register to 32

IWDG_Prescaler_64

Used to set prescaler register to 64

IWDG_Prescaler_128

Used to set prescaler register to 128

IWDG_Prescaler_256

Used to set prescaler register to 256

Definition at line 95 of file stm8s_iwdg.h.

enum IWDG_WriteAccess_TypeDef

IWDG write access enumeration.

Enumerator:
IWDG_WriteAccess_Enable

Code 0x55 in Key register, allow write access to Prescaler and Reload registers

IWDG_WriteAccess_Disable

Code 0x00 in Key register, not allow write access to Prescaler and Reload registers

Definition at line 88 of file stm8s_iwdg.h.


STM8S/A Standard Peripherals Drivers: IWDG_Exported_Functions

Functions
IWDG_Exported_Functions
STM8S_StdPeriph_Driver

Functions

void | IWDG_Enable (void)
Enables IWDG.
void | IWDG_ReloadCounter (void)
Reloads IWDG counter.
void | IWDG_SetPrescaler (IWDG_Prescaler_TypeDef IWDG_Prescaler)
Sets IWDG Prescaler value.
void | IWDG_SetReload (uint8_t IWDG_Reload)
Sets IWDG Reload value.
void | IWDG_WriteAccessCmd (IWDG_WriteAccess_TypeDef IWDG_WriteAccess)
Enables or disables write access to Prescaler and Reload registers.

Function Documentation

void IWDG_Enable ( void )

Enables IWDG.

Parameters:
None
Return values:
None

Definition at line 99 of file stm8s_iwdg.c.

References IWDG, and IWDG_KEY_ENABLE.

void IWDG_ReloadCounter ( void )

Reloads IWDG counter.

Note:
Write access should be enabled
Parameters:
None
Return values:
None

Definition at line 89 of file stm8s_iwdg.c.

References IWDG, and IWDG_KEY_REFRESH.

void IWDG_SetPrescaler ( IWDG_Prescaler_TypeDef IWDG_Prescaler )

Sets IWDG Prescaler value.

Note:
Write access should be enabled
Parameters:
IWDG_Prescaler : Specifies the IWDG Prescaler value. This parameter can be a value of IWDG_Prescaler_TypeDef.
Return values:
None

Definition at line 63 of file stm8s_iwdg.c.

References IS_IWDG_PRESCALER_OK, and IWDG.

void IWDG_SetReload ( uint8_t IWDG_Reload )

Sets IWDG Reload value.

Note:
Write access should be enabled
Parameters:
IWDG_Reload : Reload register value. This parameter must be a number between 0 and 0xFF.
Return values:
None

Definition at line 78 of file stm8s_iwdg.c.

References IWDG.

void IWDG_WriteAccessCmd ( IWDG_WriteAccess_TypeDef IWDG_WriteAccess )

Enables or disables write access to Prescaler and Reload registers.

Parameters:
IWDG_WriteAccess : New state of write access to Prescaler and Reload registers. This parameter can be a value of IWDG_WriteAccess_TypeDef.
Return values:
None

Definition at line 48 of file stm8s_iwdg.c.

References IS_IWDG_WRITEACCESS_MODE_OK, and IWDG.


STM8S/A Standard Peripherals Drivers: RST_Exported_Types

Enumerations
RST_Exported_Types
STM8S_StdPeriph_Driver

Enumerations

enum RST_Flag_TypeDef {
RST_FLAG_EMCF = (uint8_t)0x10, RST_FLAG_SWIMF = (uint8_t)0x08, RST_FLAG_ILLOPF = (uint8_t)0x04, RST_FLAG_IWDGF = (uint8_t)0x02,
RST_FLAG_WWDGF = (uint8_t)0x01
}

Enumeration Type Documentation

enum RST_Flag_TypeDef
Enumerator:
RST_FLAG_EMCF

EMC reset flag

RST_FLAG_SWIMF

SWIM reset flag

RST_FLAG_ILLOPF

Illigal opcode reset flag

RST_FLAG_IWDGF

Independent watchdog reset flag

RST_FLAG_WWDGF

Window watchdog reset flag

Definition at line 41 of file stm8s_rst.h.


STM8S/A Standard Peripherals Drivers: RST_Private_Macros

Defines
RST_Private_Macros
STM8S_StdPeriph_Driver

Defines

#define IS_RST_FLAG_OK(FLAG)
Macro used by the assert function to check the different functions parameters.

Define Documentation

#define IS_RST_FLAG_OK ( FLAG )
Value:
(((FLAG) == RST_FLAG_EMCF) || \
                              ((FLAG) == RST_FLAG_SWIMF)  ||\
                              ((FLAG) == RST_FLAG_ILLOPF) ||\
                              ((FLAG) == RST_FLAG_IWDGF)  ||\
                              ((FLAG) == RST_FLAG_WWDGF))

Macro used by the assert function to check the different functions parameters.

Macro used by the assert function to check the different RST flags.

Definition at line 66 of file stm8s_rst.h.

Referenced by RST_ClearFlag(), and RST_GetFlagStatus().


STM8S/A Standard Peripherals Drivers: RST_Exported_functions

Functions
RST_Exported_functions
STM8S_StdPeriph_Driver

Functions

void | RST_ClearFlag (RST_Flag_TypeDef RST_Flag)
Clears the specified RST flag.
FlagStatus | RST_GetFlagStatus (RST_Flag_TypeDef RST_Flag)
Checks whether the specified RST flag is set or not.

Function Documentation

void RST_ClearFlag ( RST_Flag_TypeDef RST_Flag )

Clears the specified RST flag.

Parameters:
RST_Flag : specify the reset flag to clear. This parameter can be a value of RST_Flag_TypeDef.
Return values:
None

Definition at line 69 of file stm8s_rst.c.

References IS_RST_FLAG_OK, and RST.

FlagStatus RST_GetFlagStatus ( RST_Flag_TypeDef RST_Flag )

Checks whether the specified RST flag is set or not.

Parameters:
RST_Flag : specify the reset flag to check. This parameter can be a value of RST_Flag_TypeDef.
Return values:
FlagStatus,: status of the given RST flag.

Definition at line 54 of file stm8s_rst.c.

References IS_RST_FLAG_OK, RESET, RST, and SET.


STM8S/A Standard Peripherals Drivers: SPI_Exported_Types

Enumerations
SPI_Exported_Types
STM8S_StdPeriph_Driver

Enumerations

enum SPI_BaudRatePrescaler_TypeDef {
SPI_BAUDRATEPRESCALER_2 = (uint8_t)0x00, SPI_BAUDRATEPRESCALER_4 = (uint8_t)0x08, SPI_BAUDRATEPRESCALER_8 = (uint8_t)0x10, SPI_BAUDRATEPRESCALER_16 = (uint8_t)0x18,
SPI_BAUDRATEPRESCALER_32 = (uint8_t)0x20, SPI_BAUDRATEPRESCALER_64 = (uint8_t)0x28, SPI_BAUDRATEPRESCALER_128 = (uint8_t)0x30, SPI_BAUDRATEPRESCALER_256 = (uint8_t)0x38
}
SPI BaudRate Prescaler Warning: element values correspond to BR bits position. More...
enum | SPI_ClockPhase_TypeDef { SPI_CLOCKPHASE_1EDGE = (uint8_t)0x00, SPI_CLOCKPHASE_2EDGE = (uint8_t)0x01 }
SPI Clock Phase Warning: element values correspond to CPHA bit position. More...
enum | SPI_ClockPolarity_TypeDef { SPI_CLOCKPOLARITY_LOW = (uint8_t)0x00, SPI_CLOCKPOLARITY_HIGH = (uint8_t)0x02 }
SPI Clock Polarity Warning: element values correspond to CPOL bit position. More...
enum | SPI_CRC_TypeDef { SPI_CRC_RX = (uint8_t)0x00, SPI_CRC_TX = (uint8_t)0x01 }
SPI CRC Transmit/Receive. More...
enum | SPI_DataDirection_TypeDef { SPI_DATADIRECTION_2LINES_FULLDUPLEX = (uint8_t)0x00, SPI_DATADIRECTION_2LINES_RXONLY = (uint8_t)0x04, SPI_DATADIRECTION_1LINE_RX = (uint8_t)0x80, SPI_DATADIRECTION_1LINE_TX = (uint8_t)0xC0 }
SPI data direction mode Warning: element values correspond to BDM, BDOE, RXONLY bits position. More...
enum | SPI_Direction_TypeDef { SPI_DIRECTION_RX = (uint8_t)0x00, SPI_DIRECTION_TX = (uint8_t)0x01 }
SPI direction transmit/receive. More...
enum | SPI_FirstBit_TypeDef { SPI_FIRSTBIT_MSB = (uint8_t)0x00, SPI_FIRSTBIT_LSB = (uint8_t)0x80 }
SPI Frame Format: MSB or LSB transmitted first Warning: element values correspond to LSBFIRST bit position. More...
enum SPI_Flag_TypeDef {
SPI_FLAG_BSY = (uint8_t)0x80, SPI_FLAG_OVR = (uint8_t)0x40, SPI_FLAG_MODF = (uint8_t)0x20, SPI_FLAG_CRCERR = (uint8_t)0x10,
SPI_FLAG_WKUP = (uint8_t)0x08, SPI_FLAG_TXE = (uint8_t)0x02, SPI_FLAG_RXNE = (uint8_t)0x01
}
SPI flags definition - Warning : FLAG value = mapping position register. More...
enum SPI_IT_TypeDef {
SPI_IT_WKUP = (uint8_t)0x34, SPI_IT_OVR = (uint8_t)0x65, SPI_IT_MODF = (uint8_t)0x55, SPI_IT_CRCERR = (uint8_t)0x45,
SPI_IT_TXE = (uint8_t)0x17, SPI_IT_RXNE = (uint8_t)0x06, SPI_IT_ERR = (uint8_t)0x05
}
SPI_IT possible values Elements values convention: 0xYX X: Position of the corresponding Interrupt Y: ITPENDINGBIT position. More...
enum | SPI_Mode_TypeDef { SPI_MODE_MASTER = (uint8_t)0x04, SPI_MODE_SLAVE = (uint8_t)0x00 }
SPI master/slave mode Warning: element values correspond to MSTR bit position. More...
enum | SPI_NSS_TypeDef { SPI_NSS_SOFT = (uint8_t)0x02, SPI_NSS_HARD = (uint8_t)0x00 }
SPI Slave Select management Warning: element values correspond to LSBFIRST bit position. More...

Enumeration Type Documentation

enum SPI_BaudRatePrescaler_TypeDef

SPI BaudRate Prescaler Warning: element values correspond to BR bits position.

Enumerator:
SPI_BAUDRATEPRESCALER_2

SPI frequency = frequency(CPU)/2

SPI_BAUDRATEPRESCALER_4

SPI frequency = frequency(CPU)/4

SPI_BAUDRATEPRESCALER_8

SPI frequency = frequency(CPU)/8

SPI_BAUDRATEPRESCALER_16

SPI frequency = frequency(CPU)/16

SPI_BAUDRATEPRESCALER_32

SPI frequency = frequency(CPU)/32

SPI_BAUDRATEPRESCALER_64

SPI frequency = frequency(CPU)/64

SPI_BAUDRATEPRESCALER_128

SPI frequency = frequency(CPU)/128

SPI_BAUDRATEPRESCALER_256

SPI frequency = frequency(CPU)/256

Definition at line 87 of file stm8s_spi.h.

enum SPI_ClockPhase_TypeDef

SPI Clock Phase Warning: element values correspond to CPHA bit position.

Enumerator:
SPI_CLOCKPHASE_1EDGE

The first clock transition is the first data capture edge

SPI_CLOCKPHASE_2EDGE

The second clock transition is the first data capture edge

Definition at line 111 of file stm8s_spi.h.

enum SPI_ClockPolarity_TypeDef

SPI Clock Polarity Warning: element values correspond to CPOL bit position.

Enumerator:
SPI_CLOCKPOLARITY_LOW

Clock to 0 when idle

SPI_CLOCKPOLARITY_HIGH

Clock to 1 when idle

Definition at line 102 of file stm8s_spi.h.

enum SPI_CRC_TypeDef

SPI CRC Transmit/Receive.

Enumerator:
SPI_CRC_RX

Select Tx CRC register

SPI_CRC_TX

Select Rx CRC register

Definition at line 128 of file stm8s_spi.h.

enum SPI_DataDirection_TypeDef

SPI data direction mode Warning: element values correspond to BDM, BDOE, RXONLY bits position.

Enumerator:
SPI_DATADIRECTION_2LINES_FULLDUPLEX

2-line uni-directional data mode enable

SPI_DATADIRECTION_2LINES_RXONLY

Receiver only in 2 line uni-directional data mode

SPI_DATADIRECTION_1LINE_RX

Receiver only in 1 line bi-directional data mode

SPI_DATADIRECTION_1LINE_TX

Transmit only in 1 line bi-directional data mode

Definition at line 47 of file stm8s_spi.h.

enum SPI_Direction_TypeDef

SPI direction transmit/receive.

Enumerator:
SPI_DIRECTION_RX

Selects Rx receive direction in bi-directional mode

SPI_DIRECTION_TX

Selects Tx transmission direction in bi-directional mode

Definition at line 69 of file stm8s_spi.h.

enum SPI_FirstBit_TypeDef

SPI Frame Format: MSB or LSB transmitted first Warning: element values correspond to LSBFIRST bit position.

Enumerator:
SPI_FIRSTBIT_MSB

MSB bit will be transmitted first

SPI_FIRSTBIT_LSB

LSB bit will be transmitted first

Definition at line 120 of file stm8s_spi.h.

enum SPI_Flag_TypeDef

SPI flags definition - Warning : FLAG value = mapping position register.

Enumerator:
SPI_FLAG_BSY

Busy flag

SPI_FLAG_OVR

Overrun flag

SPI_FLAG_MODF

Mode fault

SPI_FLAG_CRCERR

CRC error flag

SPI_FLAG_WKUP

Wake-up flag

SPI_FLAG_TXE

Transmit buffer empty

SPI_FLAG_RXNE

Receive buffer empty

Definition at line 136 of file stm8s_spi.h.

enum SPI_IT_TypeDef

SPI_IT possible values Elements values convention: 0xYX X: Position of the corresponding Interrupt Y: ITPENDINGBIT position.

Enumerator:
SPI_IT_WKUP

Wake-up interrupt

SPI_IT_OVR

Overrun interrupt

SPI_IT_MODF

Mode fault interrupt

SPI_IT_CRCERR

CRC error interrupt

SPI_IT_TXE

Transmit buffer empty interrupt

SPI_IT_RXNE

Receive buffer not empty interrupt

SPI_IT_ERR

Error interrupt

Definition at line 152 of file stm8s_spi.h.

enum SPI_Mode_TypeDef

SPI master/slave mode Warning: element values correspond to MSTR bit position.

Enumerator:
SPI_MODE_MASTER

SPI Master configuration

SPI_MODE_SLAVE

SPI Slave configuration

Definition at line 78 of file stm8s_spi.h.

enum SPI_NSS_TypeDef

SPI Slave Select management Warning: element values correspond to LSBFIRST bit position.

Enumerator:
SPI_NSS_SOFT

Software slave management disabled

SPI_NSS_HARD

Software slave management enabled

Definition at line 58 of file stm8s_spi.h.


STM8S/A Standard Peripherals Drivers: SPI_Private_Macros

Defines
SPI_Private_Macros
STM8S_StdPeriph_Driver

Macros used by the assert_param function to check the different functions parameters. More...

Defines

#define | IS_SPI_BAUDRATE_PRESCALER_OK(PRESCALER)
Macro used by the assert_param function in order to check the baudrate values.
#define | IS_SPI_CLEAR_FLAGS_OK(FLAG)
Macro used by the assert_param function in order to check the different sensitivity values for the flag that can be cleared by writing 0.
#define | IS_SPI_CLEAR_IT_OK(ITPendingBit)
Macro used by the assert_param function in order to check the different sensitivity values for the pending bit that can be cleared by writing 0.
#define | IS_SPI_CONFIG_IT_OK(Interrupt)
Macro used by the assert_param function in order to check the different sensitivity values for the Interrupts.
#define | IS_SPI_CRC_OK(CRC)
Macro used by the assert_param function in order to check the CRC Transmit/Receive.
#define | IS_SPI_CRC_POLYNOMIAL_OK(POLYNOMIAL) ((POLYNOMIAL) > (uint8_t)0x00)
Macro used by the assert_param function in order to check the different sensitivity values for the CRC polynomial.
#define | IS_SPI_DATA_DIRECTION_OK(MODE)
Macro used by the assert_param function in order to check the data direction mode values.
#define | IS_SPI_DIRECTION_OK(DIRECTION)
Macro used by the assert_param function in order to check the mode half duplex data direction values.
#define | IS_SPI_FIRSTBIT_OK(BIT)
Macro used by the assert_param function in order to check the first bit to be transmited values.
#define | IS_SPI_FLAGS_OK(FLAG)
Macro used by the assert_param function in order to check the different flags values.
#define | IS_SPI_GET_IT_OK(ITPendingBit)
Macro used by the assert_param function in order to check the different sensitivity values for the pending bit.
#define | IS_SPI_MODE_OK(MODE)
Macro used by the assert_param function in order to check the SPI Mode values.
#define | IS_SPI_PHASE_OK(CLKPHA)
Macro used by the assert_param function in order to check the phase values.
#define | IS_SPI_POLARITY_OK(CLKPOL)
Macro used by the assert_param function in order to check the polarity values.
#define | IS_SPI_SLAVEMANAGEMENT_OK(NSS)
Macro used by the assert_param function in order to check the NSS management values.

Detailed Description

Macros used by the assert_param function to check the different functions parameters.

Define Documentation

#define IS_SPI_BAUDRATE_PRESCALER_OK ( PRESCALER )
Value:
(((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
    ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
    ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
    ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
    ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
    ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
    ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
    ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))

Macro used by the assert_param function in order to check the baudrate values.

Definition at line 212 of file stm8s_spi.h.

Referenced by SPI_Init().

#define IS_SPI_CLEAR_FLAGS_OK ( FLAG )
Value:
(((FLAG) == SPI_FLAG_CRCERR) || \
                                     ((FLAG) == SPI_FLAG_WKUP))

Macro used by the assert_param function in order to check the different sensitivity values for the flag that can be cleared by writing 0.

Definition at line 264 of file stm8s_spi.h.

Referenced by SPI_ClearFlag().

#define IS_SPI_CLEAR_IT_OK ( ITPendingBit )
Value:
(((ITPendingBit) == SPI_IT_CRCERR) || \
    ((ITPendingBit) == SPI_IT_WKUP))

Macro used by the assert_param function in order to check the different sensitivity values for the pending bit that can be cleared by writing 0.

Definition at line 292 of file stm8s_spi.h.

Referenced by SPI_ClearITPendingBit().

#define IS_SPI_CONFIG_IT_OK ( Interrupt )
Value:
(((Interrupt) == SPI_IT_TXE)  || \
                                        ((Interrupt) == SPI_IT_RXNE)  || \
                                        ((Interrupt) == SPI_IT_ERR) || \
                                        ((Interrupt) == SPI_IT_WKUP))

Macro used by the assert_param function in order to check the different sensitivity values for the Interrupts.

Definition at line 271 of file stm8s_spi.h.

Referenced by SPI_ITConfig().

#define IS_SPI_CRC_OK ( CRC )
Value:
(((CRC) == SPI_CRC_TX) || \
                            ((CRC) == SPI_CRC_RX))

Macro used by the assert_param function in order to check the CRC Transmit/Receive.

Definition at line 244 of file stm8s_spi.h.

Referenced by SPI_GetCRC().

#define IS_SPI_CRC_POLYNOMIAL_OK ( POLYNOMIAL ) ((POLYNOMIAL) > (uint8_t)0x00)

Macro used by the assert_param function in order to check the different sensitivity values for the CRC polynomial.

Definition at line 201 of file stm8s_spi.h.

Referenced by SPI_Init().

#define IS_SPI_DATA_DIRECTION_OK ( MODE )
Value:
(((MODE) == SPI_DATADIRECTION_2LINES_FULLDUPLEX) || \
                                        ((MODE) == SPI_DATADIRECTION_2LINES_RXONLY) || \
                                        ((MODE) == SPI_DATADIRECTION_1LINE_RX) || \
                                        ((MODE) == SPI_DATADIRECTION_1LINE_TX))

Macro used by the assert_param function in order to check the data direction mode values.

Definition at line 177 of file stm8s_spi.h.

Referenced by SPI_Init().

#define IS_SPI_DIRECTION_OK ( DIRECTION )
Value:
(((DIRECTION) == SPI_DIRECTION_RX) || \
                                        ((DIRECTION) == SPI_DIRECTION_TX))

Macro used by the assert_param function in order to check the mode half duplex data direction values.

Definition at line 186 of file stm8s_spi.h.

Referenced by SPI_BiDirectionalLineConfig().

#define IS_SPI_FIRSTBIT_OK ( BIT )
Value:
(((BIT) == SPI_FIRSTBIT_MSB) || \
                                 ((BIT) == SPI_FIRSTBIT_LSB))

Macro used by the assert_param function in order to check the first bit to be transmited values.

Definition at line 237 of file stm8s_spi.h.

Referenced by SPI_Init().

#define IS_SPI_FLAGS_OK ( FLAG )
Value:
(((FLAG) == SPI_FLAG_OVR) || \
                               ((FLAG) == SPI_FLAG_MODF) || \
                               ((FLAG) == SPI_FLAG_CRCERR) || \
                               ((FLAG) == SPI_FLAG_WKUP) || \
                               ((FLAG) == SPI_FLAG_TXE) || \
                               ((FLAG) == SPI_FLAG_RXNE) || \
                               ((FLAG) == SPI_FLAG_BSY))

Macro used by the assert_param function in order to check the different flags values.

Definition at line 251 of file stm8s_spi.h.

Referenced by SPI_GetFlagStatus().

#define IS_SPI_GET_IT_OK ( ITPendingBit )
Value:
(((ITPendingBit) == SPI_IT_OVR)  || \
                                        ((ITPendingBit) == SPI_IT_MODF) || \
                                        ((ITPendingBit) == SPI_IT_CRCERR) || \
                                        ((ITPendingBit) == SPI_IT_WKUP) || \
                                        ((ITPendingBit) == SPI_IT_TXE)  || \
                                        ((ITPendingBit) == SPI_IT_RXNE))

Macro used by the assert_param function in order to check the different sensitivity values for the pending bit.

Definition at line 280 of file stm8s_spi.h.

Referenced by SPI_GetITStatus().

#define IS_SPI_MODE_OK ( MODE )
Value:
(((MODE) == SPI_MODE_MASTER) || \
                              ((MODE) == SPI_MODE_SLAVE))

Macro used by the assert_param function in order to check the SPI Mode values.

Definition at line 206 of file stm8s_spi.h.

Referenced by SPI_Init().

#define IS_SPI_PHASE_OK ( CLKPHA )
Value:
(((CLKPHA) == SPI_CLOCKPHASE_1EDGE) || \
                                 ((CLKPHA) == SPI_CLOCKPHASE_2EDGE))

Macro used by the assert_param function in order to check the phase values.

Definition at line 230 of file stm8s_spi.h.

Referenced by SPI_Init().

#define IS_SPI_POLARITY_OK ( CLKPOL )
Value:
(((CLKPOL) == SPI_CLOCKPOLARITY_LOW) || \
                                    ((CLKPOL) == SPI_CLOCKPOLARITY_HIGH))

Macro used by the assert_param function in order to check the polarity values.

Definition at line 224 of file stm8s_spi.h.

Referenced by SPI_Init().

#define IS_SPI_SLAVEMANAGEMENT_OK ( NSS )
Value:
(((NSS) == SPI_NSS_SOFT) || \
                                        ((NSS) == SPI_NSS_HARD))

Macro used by the assert_param function in order to check the NSS management values.

Definition at line 193 of file stm8s_spi.h.

Referenced by SPI_Init().


STM8S/A Standard Peripherals Drivers: SPI_Exported_Functions

Functions
SPI_Exported_Functions
STM8S_StdPeriph_Driver

Functions

void | SPI_BiDirectionalLineConfig (SPI_Direction_TypeDef SPI_Direction)
Selects the data transfer direction in bi-directional mode.
void | SPI_CalculateCRCCmd (FunctionalState NewState)
Enables or disables the CRC value calculation of the transferred bytes.
void | SPI_ClearFlag (SPI_Flag_TypeDef SPI_FLAG)
Clears the SPI flags.
void | SPI_ClearITPendingBit (SPI_IT_TypeDef SPI_IT)
Clears the interrupt pending bits.
void | SPI_Cmd (FunctionalState NewState)
Enables or disables the SPI peripheral.
void | SPI_DeInit (void)
Deinitializes the SPI peripheral registers to their default reset values.
uint8_t | SPI_GetCRC (SPI_CRC_TypeDef SPI_CRC)
Returns the transmit or the receive CRC register value.
uint8_t | SPI_GetCRCPolynomial (void)
Returns the CRC Polynomial register value.
FlagStatus | SPI_GetFlagStatus (SPI_Flag_TypeDef SPI_FLAG)
Checks whether the specified SPI flag is set or not.
ITStatus | SPI_GetITStatus (SPI_IT_TypeDef SPI_IT)
Checks whether the specified interrupt has occurred or not.
void | SPI_Init (SPI_FirstBit_TypeDef FirstBit, SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, SPI_Mode_TypeDef Mode, SPI_ClockPolarity_TypeDef ClockPolarity, SPI_ClockPhase_TypeDef ClockPhase, SPI_DataDirection_TypeDef Data_Direction, SPI_NSS_TypeDef Slave_Management, uint8_t CRCPolynomial)
Initializes the SPI according to the specified parameters.
void | SPI_ITConfig (SPI_IT_TypeDef SPI_IT, FunctionalState NewState)
Enables or disables the specified interrupts.
void | SPI_NSSInternalSoftwareCmd (FunctionalState NewState)
Configures internally by software the NSS pin.
uint8_t | SPI_ReceiveData (void)
Returns the most recent received data by the SPI peripheral.
void | SPI_ResetCRC (void)
Reset the Rx CRCR and Tx CRCR registers.
void | SPI_SendData (uint8_t Data)
Transmits a Data through the SPI peripheral.
void | SPI_TransmitCRC (void)
Enables the transmit of the CRC value.

Function Documentation

void SPI_BiDirectionalLineConfig ( SPI_Direction_TypeDef SPI_Direction )

Selects the data transfer direction in bi-directional mode.

Parameters:
SPI_Direction Specifies the data transfer direction in bi-directional mode.
Return values:
None

Definition at line 288 of file stm8s_spi.c.

References IS_SPI_DIRECTION_OK, SPI, SPI_CR2_BDOE, and SPI_DIRECTION_RX.

void SPI_CalculateCRCCmd ( FunctionalState NewState )

Enables or disables the CRC value calculation of the transferred bytes.

Parameters:
NewState Indicates the new state of the SPI CRC value calculation. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 218 of file stm8s_spi.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, SPI, and SPI_CR2_CRCEN.

Referenced by SPI_ResetCRC().

void SPI_ClearFlag ( SPI_Flag_TypeDef SPI_FLAG )

Clears the SPI flags.

Parameters:
SPI_FLAG : Specifies the flag to clear. This parameter can be one of the following values:
  • SPI_FLAG_CRCERR
  • SPI_FLAG_WKUP
Note:
- OVR (OverRun Error) interrupt pending bit is cleared by software sequence: a read operation to SPI_DR register (SPI_ReceiveData()) followed by a read operation to SPI_SR register (SPI_GetFlagStatus()).
  • MODF (Mode Fault) interrupt pending bit is cleared by software sequence: a read/write operation to SPI_SR register (SPI_GetFlagStatus()) followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
Return values:
None

Definition at line 346 of file stm8s_spi.c.

References IS_SPI_CLEAR_FLAGS_OK, and SPI.

void SPI_ClearITPendingBit ( SPI_IT_TypeDef SPI_IT )

Clears the interrupt pending bits.

Parameters:
SPI_IT,: Specifies the interrupt pending bit to clear. This parameter can be one of the following values:
  • SPI_IT_CRCERR
  • SPI_IT_WKUP
Note:
- OVR (OverRun Error) interrupt pending bit is cleared by software sequence: a read operation to SPI_DR register (SPI_ReceiveData()) followed by a read operation to SPI_SR register (SPI_GetITStatus()).
  • MODF (Mode Fault) interrupt pending bit is cleared by software sequence: a read/write operation to SPI_SR register (SPI_GetITStatus()) followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
Return values:
None

Definition at line 412 of file stm8s_spi.c.

References IS_SPI_CLEAR_IT_OK, and SPI.

void SPI_Cmd ( FunctionalState NewState )

Enables or disables the SPI peripheral.

Parameters:
NewState New state of the SPI peripheral. This parameter can be: ENABLE or DISABLE
Return values:
None

Definition at line 119 of file stm8s_spi.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, SPI, and SPI_CR1_SPE.

Referenced by SPI_ResetCRC().

void SPI_DeInit ( void )

Deinitializes the SPI peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 50 of file stm8s_spi.c.

References SPI, SPI_CR1_RESET_VALUE, SPI_CR2_RESET_VALUE, SPI_CRCPR_RESET_VALUE, SPI_ICR_RESET_VALUE, and SPI_SR_RESET_VALUE.

uint8_t SPI_GetCRC ( SPI_CRC_TypeDef SPI_CRC )

Returns the transmit or the receive CRC register value.

Parameters:
SPI_CRC Specifies the CRC register to be read.
Return values:
The selected CRC register value.

Definition at line 238 of file stm8s_spi.c.

References IS_SPI_CRC_OK, SPI, and SPI_CRC_RX.

uint8_t SPI_GetCRCPolynomial ( void )

Returns the CRC Polynomial register value.

Parameters:
None
Return values:
The CRC Polynomial register value.

Definition at line 278 of file stm8s_spi.c.

References SPI.

FlagStatus SPI_GetFlagStatus ( SPI_Flag_TypeDef SPI_FLAG )

Checks whether the specified SPI flag is set or not.

Parameters:
SPI_FLAG : Specifies the flag to check. This parameter can be any of the SPI_Flag_TypeDef enumeration.
Return values:
FlagStatus : Indicates the state of SPI_FLAG. This parameter can be any of the FlagStatus enumeration.

Definition at line 311 of file stm8s_spi.c.

References IS_SPI_FLAGS_OK, RESET, SET, and SPI.

ITStatus SPI_GetITStatus ( SPI_IT_TypeDef SPI_IT )

Checks whether the specified interrupt has occurred or not.

Parameters:
SPI_IT,: Specifies the SPI interrupt pending bit to check. This parameter can be one of the following values:
  • SPI_IT_CRCERR
  • SPI_IT_WKUP
  • SPI_IT_OVR
  • SPI_IT_MODF
  • SPI_IT_RXNE
  • SPI_IT_TXE
Return values:
ITStatus : Indicates the state of the SPI_IT. This parameter can be any of the ITStatus enumeration.

Definition at line 366 of file stm8s_spi.c.

References IS_SPI_GET_IT_OK, RESET, SET, and SPI.

void SPI_Init | ( | SPI_FirstBit_TypeDef | FirstBit,
 |  | SPI_BaudRatePrescaler_TypeDef | BaudRatePrescaler,
 |  | SPI_Mode_TypeDef | Mode,
 |  | SPI_ClockPolarity_TypeDef | ClockPolarity,
 |  | SPI_ClockPhase_TypeDef | ClockPhase,
 |  | SPI_DataDirection_TypeDef | Data_Direction,
 |  | SPI_NSS_TypeDef | Slave_Management,
 |  | uint8_t | CRCPolynomial
 | ) |  |

Initializes the SPI according to the specified parameters.

Parameters:
FirstBit | : This parameter can be any of the SPI_FirstBit_TypeDef enumeration.
BaudRatePrescaler | : This parameter can be any of the SPI_BaudRatePrescaler_TypeDef enumeration.
Mode | : This parameter can be any of the SPI_Mode_TypeDef enumeration.
ClockPolarity | : This parameter can be any of the SPI_ClockPolarity_TypeDef enumeration.
ClockPhase | : This parameter can be any of the SPI_ClockPhase_TypeDef enumeration.
Data_Direction | : This parameter can be any of the SPI_DataDirection_TypeDef enumeration.
Slave_Management | : This parameter can be any of the SPI_NSS_TypeDef enumeration.
CRCPolynomial | : Configures the CRC polynomial.
Return values:
None

Definition at line 78 of file stm8s_spi.c.

References IS_SPI_BAUDRATE_PRESCALER_OK, IS_SPI_CRC_POLYNOMIAL_OK, IS_SPI_DATA_DIRECTION_OK, IS_SPI_FIRSTBIT_OK, IS_SPI_MODE_OK, IS_SPI_PHASE_OK, IS_SPI_POLARITY_OK, IS_SPI_SLAVEMANAGEMENT_OK, SPI, SPI_CR2_SSI, and SPI_MODE_MASTER.

void SPI_ITConfig | ( | SPI_IT_TypeDef | SPI_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified interrupts.

Parameters:
SPI_IT Specifies the SPI interrupts sources to be enabled or disabled.
NewState,: The new state of the specified SPI interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 141 of file stm8s_spi.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, IS_SPI_CONFIG_IT_OK, and SPI.

void SPI_NSSInternalSoftwareCmd ( FunctionalState NewState )

Configures internally by software the NSS pin.

Parameters:
NewState Indicates the new state of the SPI Software slave management. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 187 of file stm8s_spi.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, SPI, and SPI_CR2_SSI.

uint8_t SPI_ReceiveData ( void )

Returns the most recent received data by the SPI peripheral.

Parameters:
None
Return values:
The value of the received data.

Definition at line 176 of file stm8s_spi.c.

References SPI.

void SPI_ResetCRC ( void )

Reset the Rx CRCR and Tx CRCR registers.

Parameters:
None
Return values:
None

Definition at line 263 of file stm8s_spi.c.

References ENABLE, SPI_CalculateCRCCmd(), and SPI_Cmd().

void SPI_SendData ( uint8_t Data )

Transmits a Data through the SPI peripheral.

Parameters:
Data : Byte to be transmitted.
Return values:
None

Definition at line 166 of file stm8s_spi.c.

References SPI.

void SPI_TransmitCRC ( void )

Enables the transmit of the CRC value.

Parameters:
None
Return values:
None

Definition at line 207 of file stm8s_spi.c.

References SPI, and SPI_CR2_CRCNEXT.


STM8S/A Standard Peripherals Drivers: TIM1_Exported_Types

Defines | Enumerations
TIM1_Exported_Types
STM8S_StdPeriph_Driver

Defines

#define | IS_TIM1_AUTOMATIC_OUTPUT_STATE_OK(STATE)
#define | IS_TIM1_BREAK_POLARITY_OK(POLARITY)
#define | IS_TIM1_BREAK_STATE_OK(STATE)
#define | IS_TIM1_CHANNEL_OK(CHANNEL)
#define | IS_TIM1_CLEAR_FLAG_OK(FLAG) ((((uint16_t)(FLAG) & (uint16_t)0xE100) == 0x0000) && ((FLAG) != 0x0000))
#define | IS_TIM1_COMPLEMENTARY_CHANNEL_OK(CHANNEL)
#define | IS_TIM1_COUNTER_MODE_OK(MODE)
#define | IS_TIM1_ENCODER_MODE_OK(MODE)
#define | IS_TIM1_EVENT_SOURCE_OK(SOURCE) ((SOURCE) != 0x00)
#define | IS_TIM1_EXT_POLARITY_OK(POLARITY)
#define | IS_TIM1_EXT_PRESCALER_OK(PRESCALER)
#define | IS_TIM1_EXT_TRG_FILTER_OK(FILTER) ((FILTER) <= 0x0F)
TIM1 External Trigger Filer Value.
#define | IS_TIM1_FORCED_ACTION_OK(ACTION)
#define | IS_TIM1_GET_FLAG_OK(FLAG)
#define | IS_TIM1_GET_IT_OK(IT)
#define | IS_TIM1_IC_FILTER_OK(ICFILTER) ((ICFILTER) <= 0x0F)
TIM1 Input Capture Filer Value.
#define | IS_TIM1_IC_POLARITY_OK(POLARITY)
#define | IS_TIM1_IC_PRESCALER_OK(PRESCALER)
#define | IS_TIM1_IC_SELECTION_OK(SELECTION)
#define | IS_TIM1_IT_OK(IT) ((IT) != 0x00)
#define | IS_TIM1_LOCK_LEVEL_OK(LEVEL)
#define | IS_TIM1_OC_MODE_OK(MODE)
#define | IS_TIM1_OC_POLARITY_OK(POLARITY)
#define | IS_TIM1_OCIDLE_STATE_OK(STATE)
#define | IS_TIM1_OCM_OK(MODE)
#define | IS_TIM1_OCN_POLARITY_OK(POLARITY)
#define | IS_TIM1_OCNIDLE_STATE_OK(STATE)
#define | IS_TIM1_OPM_MODE_OK(MODE)
#define | IS_TIM1_OSSI_STATE_OK(STATE)
#define | IS_TIM1_OUTPUT_STATE_OK(STATE)
#define | IS_TIM1_OUTPUTN_STATE_OK(STATE)
#define | IS_TIM1_PRESCALER_RELOAD_OK(RELOAD)
#define | IS_TIM1_PWMI_CHANNEL_OK(CHANNEL)
#define | IS_TIM1_SLAVE_MODE_OK(MODE)
#define | IS_TIM1_TIX_TRIGGER_SELECTION_OK(SELECTION)
#define | IS_TIM1_TIXCLK_SOURCE_OK(SOURCE)
#define | IS_TIM1_TRGO_SOURCE_OK(SOURCE)
#define | IS_TIM1_TRIGGER_SELECTION_OK(SELECTION)
#define | IS_TIM1_UPDATE_SOURCE_OK(SOURCE)

Enumerations

enum | TIM1_AutomaticOutput_TypeDef { TIM1_AUTOMATICOUTPUT_ENABLE = ((uint8_t)0x40), TIM1_AUTOMATICOUTPUT_DISABLE = ((uint8_t)0x00) }
TIM1 AOE Bit Set/Reset. More...
enum | TIM1_BreakPolarity_TypeDef { TIM1_BREAKPOLARITY_LOW = ((uint8_t)0x00), TIM1_BREAKPOLARITY_HIGH = ((uint8_t)0x20) }
TIM1 Break Polarity. More...
enum | TIM1_BreakState_TypeDef { TIM1_BREAK_ENABLE = ((uint8_t)0x10), TIM1_BREAK_DISABLE = ((uint8_t)0x00) }
TIM1 Break Input enable/disable. More...
enum | TIM1_Channel_TypeDef { TIM1_CHANNEL_1 = ((uint8_t)0x00), TIM1_CHANNEL_2 = ((uint8_t)0x01), TIM1_CHANNEL_3 = ((uint8_t)0x02), TIM1_CHANNEL_4 = ((uint8_t)0x03) }
TIM1 Channel. More...
enum TIM1_CounterMode_TypeDef {
TIM1_COUNTERMODE_UP = ((uint8_t)0x00), TIM1_COUNTERMODE_DOWN = ((uint8_t)0x10), TIM1_COUNTERMODE_CENTERALIGNED1 = ((uint8_t)0x20), TIM1_COUNTERMODE_CENTERALIGNED2 = ((uint8_t)0x40),
TIM1_COUNTERMODE_CENTERALIGNED3 = ((uint8_t)0x60)
}
TIM1 Counter Mode. More...
enum | TIM1_EncoderMode_TypeDef { TIM1_ENCODERMODE_TI1 = ((uint8_t)0x01), TIM1_ENCODERMODE_TI2 = ((uint8_t)0x02), TIM1_ENCODERMODE_TI12 = ((uint8_t)0x03) }
TIM1 Encoder Mode. More...
enum TIM1_EventSource_TypeDef {
TIM1_EVENTSOURCE_UPDATE = ((uint8_t)0x01), TIM1_EVENTSOURCE_CC1 = ((uint8_t)0x02), TIM1_EVENTSOURCE_CC2 = ((uint8_t)0x04), TIM1_EVENTSOURCE_CC3 = ((uint8_t)0x08),
TIM1_EVENTSOURCE_CC4 = ((uint8_t)0x10), TIM1_EVENTSOURCE_COM = ((uint8_t)0x20), TIM1_EVENTSOURCE_TRIGGER = ((uint8_t)0x40), TIM1_EVENTSOURCE_BREAK = ((uint8_t)0x80)
}
TIM1 Event Source. More...
enum | TIM1_ExtTRGPolarity_TypeDef { TIM1_EXTTRGPOLARITY_INVERTED = ((uint8_t)0x80), TIM1_EXTTRGPOLARITY_NONINVERTED = ((uint8_t)0x00) }
TIM1 External Trigger Polarity. More...
enum | TIM1_ExtTRGPSC_TypeDef { TIM1_EXTTRGPSC_OFF = ((uint8_t)0x00), TIM1_EXTTRGPSC_DIV2 = ((uint8_t)0x10), TIM1_EXTTRGPSC_DIV4 = ((uint8_t)0x20), TIM1_EXTTRGPSC_DIV8 = ((uint8_t)0x30) }
TIM1 External Trigger Prescaler. More...
enum TIM1_FLAG_TypeDef {
TIM1_FLAG_UPDATE = ((uint16_t)0x0001), TIM1_FLAG_CC1 = ((uint16_t)0x0002), TIM1_FLAG_CC2 = ((uint16_t)0x0004), TIM1_FLAG_CC3 = ((uint16_t)0x0008),
TIM1_FLAG_CC4 = ((uint16_t)0x0010), TIM1_FLAG_COM = ((uint16_t)0x0020), TIM1_FLAG_TRIGGER = ((uint16_t)0x0040), TIM1_FLAG_BREAK = ((uint16_t)0x0080),
TIM1_FLAG_CC1OF = ((uint16_t)0x0200), TIM1_FLAG_CC2OF = ((uint16_t)0x0400), TIM1_FLAG_CC3OF = ((uint16_t)0x0800), TIM1_FLAG_CC4OF = ((uint16_t)0x1000)
}
TIM1 Flags. More...
enum | TIM1_ForcedAction_TypeDef { TIM1_FORCEDACTION_ACTIVE = ((uint8_t)0x50), TIM1_FORCEDACTION_INACTIVE = ((uint8_t)0x40) }
TIM1 Forced Action. More...
enum | TIM1_ICPolarity_TypeDef { TIM1_ICPOLARITY_RISING = ((uint8_t)0x00), TIM1_ICPOLARITY_FALLING = ((uint8_t)0x01) }
TIM1 Input Capture Polarity. More...
enum | TIM1_ICPSC_TypeDef { TIM1_ICPSC_DIV1 = ((uint8_t)0x00), TIM1_ICPSC_DIV2 = ((uint8_t)0x04), TIM1_ICPSC_DIV4 = ((uint8_t)0x08), TIM1_ICPSC_DIV8 = ((uint8_t)0x0C) }
TIM1 Input Capture Prescaler. More...
enum | TIM1_ICSelection_TypeDef { TIM1_ICSELECTION_DIRECTTI = ((uint8_t)0x01), TIM1_ICSELECTION_INDIRECTTI = ((uint8_t)0x02), TIM1_ICSELECTION_TRGI = ((uint8_t)0x03) }
TIM1 Input Capture Selection. More...
enum TIM1_IT_TypeDef {
TIM1_IT_UPDATE = ((uint8_t)0x01), TIM1_IT_CC1 = ((uint8_t)0x02), TIM1_IT_CC2 = ((uint8_t)0x04), TIM1_IT_CC3 = ((uint8_t)0x08),
TIM1_IT_CC4 = ((uint8_t)0x10), TIM1_IT_COM = ((uint8_t)0x20), TIM1_IT_TRIGGER = ((uint8_t)0x40), TIM1_IT_BREAK = ((uint8_t)0x80)
}
TIM1 interrupt sources. More...
enum | TIM1_LockLevel_TypeDef { TIM1_LOCKLEVEL_OFF = ((uint8_t)0x00), TIM1_LOCKLEVEL_1 = ((uint8_t)0x01), TIM1_LOCKLEVEL_2 = ((uint8_t)0x02), TIM1_LOCKLEVEL_3 = ((uint8_t)0x03) }
TIM1 Lock levels. More...
enum | TIM1_OCIdleState_TypeDef { TIM1_OCIDLESTATE_SET = ((uint8_t)0x55), TIM1_OCIDLESTATE_RESET = ((uint8_t)0x00) }
TIM1 Output Compare Idle State. More...
enum TIM1_OCMode_TypeDef {
TIM1_OCMODE_TIMING = ((uint8_t)0x00), TIM1_OCMODE_ACTIVE = ((uint8_t)0x10), TIM1_OCMODE_INACTIVE = ((uint8_t)0x20), TIM1_OCMODE_TOGGLE = ((uint8_t)0x30),
TIM1_OCMODE_PWM1 = ((uint8_t)0x60), TIM1_OCMODE_PWM2 = ((uint8_t)0x70)
}
TIM1 Output Compare and PWM modes. More...
enum | TIM1_OCNIdleState_TypeDef { TIM1_OCNIDLESTATE_SET = ((uint8_t)0x2A), TIM1_OCNIDLESTATE_RESET = ((uint8_t)0x00) }
TIM1 Output Compare N Idle State. More...
enum | TIM1_OCNPolarity_TypeDef { TIM1_OCNPOLARITY_HIGH = ((uint8_t)0x00), TIM1_OCNPOLARITY_LOW = ((uint8_t)0x88) }
TIM1 Output Compare N Polarity. More...
enum | TIM1_OCPolarity_TypeDef { TIM1_OCPOLARITY_HIGH = ((uint8_t)0x00), TIM1_OCPOLARITY_LOW = ((uint8_t)0x22) }
TIM1 Output Compare Polarity. More...
enum | TIM1_OPMode_TypeDef { TIM1_OPMODE_SINGLE = ((uint8_t)0x01), TIM1_OPMODE_REPETITIVE = ((uint8_t)0x00) }
TIM1 One Pulse Mode. More...
enum | TIM1_OSSIState_TypeDef { TIM1_OSSISTATE_ENABLE = ((uint8_t)0x04), TIM1_OSSISTATE_DISABLE = ((uint8_t)0x00) }
TIM1 OSSI: Off-State Selection for Idle mode states. More...
enum | TIM1_OutputNState_TypeDef { TIM1_OUTPUTNSTATE_DISABLE = ((uint8_t)0x00), TIM1_OUTPUTNSTATE_ENABLE = ((uint8_t)0x44) }
TIM1 Output Compare N States. More...
enum | TIM1_OutputState_TypeDef { TIM1_OUTPUTSTATE_DISABLE = ((uint8_t)0x00), TIM1_OUTPUTSTATE_ENABLE = ((uint8_t)0x11) }
TIM1 Output Compare states. More...
enum | TIM1_PSCReloadMode_TypeDef { TIM1_PSCRELOADMODE_UPDATE = ((uint8_t)0x00), TIM1_PSCRELOADMODE_IMMEDIATE = ((uint8_t)0x01) }
TIM1 Prescaler Reload Mode. More...
enum | TIM1_SlaveMode_TypeDef { TIM1_SLAVEMODE_RESET = ((uint8_t)0x04), TIM1_SLAVEMODE_GATED = ((uint8_t)0x05), TIM1_SLAVEMODE_TRIGGER = ((uint8_t)0x06), TIM1_SLAVEMODE_EXTERNAL1 = ((uint8_t)0x07) }
TIM1 Slave Mode. More...
enum | TIM1_TIxExternalCLK1Source_TypeDef { TIM1_TIXEXTERNALCLK1SOURCE_TI1ED = ((uint8_t)0x40), TIM1_TIXEXTERNALCLK1SOURCE_TI1 = ((uint8_t)0x50), TIM1_TIXEXTERNALCLK1SOURCE_TI2 = ((uint8_t)0x60) }
TIM1 TIx External Clock Source. More...
enum TIM1_TRGOSource_TypeDef {
TIM1_TRGOSOURCE_RESET = ((uint8_t)0x00), TIM1_TRGOSOURCE_ENABLE = ((uint8_t)0x10), TIM1_TRGOSOURCE_UPDATE = ((uint8_t)0x20), TIM1_TRGOSource_OC1 = ((uint8_t)0x30),
TIM1_TRGOSOURCE_OC1REF = ((uint8_t)0x40), TIM1_TRGOSOURCE_OC2REF = ((uint8_t)0x50), TIM1_TRGOSOURCE_OC3REF = ((uint8_t)0x60)
}
TIM1 Trigger Output Source. More...
enum TIM1_TS_TypeDef {
TIM1_TS_TIM6 = ((uint8_t)0x00), TIM1_TS_TIM5 = ((uint8_t)0x30), TIM1_TS_TI1F_ED = ((uint8_t)0x40), TIM1_TS_TI1FP1 = ((uint8_t)0x50),
TIM1_TS_TI2FP2 = ((uint8_t)0x60), TIM1_TS_ETRF = ((uint8_t)0x70)
}
TIM1 Internal Trigger Selection. More...
enum | TIM1_UpdateSource_TypeDef { TIM1_UPDATESOURCE_GLOBAL = ((uint8_t)0x00), TIM1_UPDATESOURCE_REGULAR = ((uint8_t)0x01) }
TIM1 Update Source. More...

Define Documentation

#define IS_TIM1_AUTOMATIC_OUTPUT_STATE_OK ( STATE )
Value:
(((STATE) == TIM1_AUTOMATICOUTPUT_ENABLE) || \
    ((STATE) == TIM1_AUTOMATICOUTPUT_DISABLE))

Definition at line 186 of file stm8s_tim1.h.

Referenced by TIM1_BDTRConfig().

#define IS_TIM1_BREAK_POLARITY_OK ( POLARITY )
Value:
(((POLARITY) == TIM1_BREAKPOLARITY_LOW) || \
    ((POLARITY) == TIM1_BREAKPOLARITY_HIGH))

Definition at line 176 of file stm8s_tim1.h.

Referenced by TIM1_BDTRConfig().

#define IS_TIM1_BREAK_STATE_OK ( STATE )
Value:
(((STATE) == TIM1_BREAK_ENABLE) || \
                                       ((STATE) == TIM1_BREAK_DISABLE))

Definition at line 167 of file stm8s_tim1.h.

Referenced by TIM1_BDTRConfig().

#define IS_TIM1_CHANNEL_OK ( CHANNEL )
Value:
(((CHANNEL) == TIM1_CHANNEL_1) || \
                                     ((CHANNEL) == TIM1_CHANNEL_2) || \
                                     ((CHANNEL) == TIM1_CHANNEL_3) || \
                                     ((CHANNEL) == TIM1_CHANNEL_4))

Definition at line 92 of file stm8s_tim1.h.

Referenced by TIM1_CCxCmd(), TIM1_ICInit(), and TIM1_SelectOCxM().

#define IS_TIM1_CLEAR_FLAG_OK ( FLAG ) ((((uint16_t)(FLAG) & (uint16_t)0xE100) == 0x0000) && ((FLAG) != 0x0000))

Definition at line 471 of file stm8s_tim1.h.

Referenced by TIM1_ClearFlag().

#define IS_TIM1_COMPLEMENTARY_CHANNEL_OK ( CHANNEL )
Value:
(((CHANNEL) == TIM1_CHANNEL_1) || \
    ((CHANNEL) == TIM1_CHANNEL_2) || \
    ((CHANNEL) == TIM1_CHANNEL_3))

Definition at line 100 of file stm8s_tim1.h.

Referenced by TIM1_CCxNCmd().

#define IS_TIM1_COUNTER_MODE_OK ( MODE )
Value:
(((MODE) == TIM1_COUNTERMODE_UP) || \
                                       ((MODE) == TIM1_COUNTERMODE_DOWN) || \
                                       ((MODE) == TIM1_COUNTERMODE_CENTERALIGNED1) || \
                                       ((MODE) == TIM1_COUNTERMODE_CENTERALIGNED2) || \
                                       ((MODE) == TIM1_COUNTERMODE_CENTERALIGNED3))

Definition at line 115 of file stm8s_tim1.h.

Referenced by TIM1_CounterModeConfig(), and TIM1_TimeBaseInit().

#define IS_TIM1_ENCODER_MODE_OK ( MODE )
Value:
(((MODE) == TIM1_ENCODERMODE_TI1) || \
                                       ((MODE) == TIM1_ENCODERMODE_TI2) || \
                                       ((MODE) == TIM1_ENCODERMODE_TI12))

Definition at line 378 of file stm8s_tim1.h.

Referenced by TIM1_EncoderInterfaceConfig().

#define IS_TIM1_EVENT_SOURCE_OK ( SOURCE ) ((SOURCE) != 0x00)

Definition at line 395 of file stm8s_tim1.h.

Referenced by TIM1_GenerateEvent().

#define IS_TIM1_EXT_POLARITY_OK ( POLARITY )
Value:
(((POLARITY) == TIM1_EXTTRGPOLARITY_INVERTED) || \
    ((POLARITY) == TIM1_EXTTRGPOLARITY_NONINVERTED))

Definition at line 357 of file stm8s_tim1.h.

Referenced by TIM1_ETRClockMode1Config(), and TIM1_ETRClockMode2Config().

#define IS_TIM1_EXT_PRESCALER_OK ( PRESCALER )
Value:
(((PRESCALER) == TIM1_EXTTRGPSC_OFF) || \
    ((PRESCALER) == TIM1_EXTTRGPSC_DIV2) || \
    ((PRESCALER) == TIM1_EXTTRGPSC_DIV4) || \
    ((PRESCALER) == TIM1_EXTTRGPSC_DIV8))

Definition at line 310 of file stm8s_tim1.h.

Referenced by TIM1_ETRClockMode1Config(), and TIM1_ETRClockMode2Config().

#define IS_TIM1_EXT_TRG_FILTER_OK ( FILTER ) ((FILTER) <= 0x0F)

TIM1 External Trigger Filer Value.

Definition at line 274 of file stm8s_tim1.h.

Referenced by TIM1_ETRConfig().

#define IS_TIM1_FORCED_ACTION_OK ( ACTION )
Value:
(((ACTION) == TIM1_FORCEDACTION_ACTIVE) || \
    ((ACTION) == TIM1_FORCEDACTION_INACTIVE))

Definition at line 480 of file stm8s_tim1.h.

Referenced by TIM1_ForcedOC1Config(), TIM1_ForcedOC2Config(), TIM1_ForcedOC3Config(), and TIM1_ForcedOC4Config().

#define IS_TIM1_GET_FLAG_OK ( FLAG )
Value:
(((FLAG) == TIM1_FLAG_UPDATE) || \
                                   ((FLAG) == TIM1_FLAG_CC1) || \
                                   ((FLAG) == TIM1_FLAG_CC2) || \
                                   ((FLAG) == TIM1_FLAG_CC3) || \
                                   ((FLAG) == TIM1_FLAG_CC4) || \
                                   ((FLAG) == TIM1_FLAG_COM) || \
                                   ((FLAG) == TIM1_FLAG_TRIGGER) || \
                                   ((FLAG) == TIM1_FLAG_BREAK) || \
                                   ((FLAG) == TIM1_FLAG_CC1OF) || \
                                   ((FLAG) == TIM1_FLAG_CC2OF) || \
                                   ((FLAG) == TIM1_FLAG_CC3OF) || \
                                   ((FLAG) == TIM1_FLAG_CC4OF))

Definition at line 458 of file stm8s_tim1.h.

Referenced by TIM1_GetFlagStatus().

#define IS_TIM1_GET_IT_OK ( IT )
Value:
(((IT) == TIM1_IT_UPDATE) || \
                               ((IT) == TIM1_IT_CC1) || \
                               ((IT) == TIM1_IT_CC2) || \
                               ((IT) == TIM1_IT_CC3) || \
                               ((IT) == TIM1_IT_CC4) || \
                               ((IT) == TIM1_IT_COM) || \
                               ((IT) == TIM1_IT_TRIGGER) || \
                               ((IT) == TIM1_IT_BREAK))

Definition at line 291 of file stm8s_tim1.h.

Referenced by TIM1_GetITStatus().

#define IS_TIM1_IC_FILTER_OK ( ICFILTER ) ((ICFILTER) <= 0x0F)

TIM1 Input Capture Filer Value.

Definition at line 271 of file stm8s_tim1.h.

Referenced by TIM1_ICInit(), and TIM1_TIxExternalClockConfig().

#define IS_TIM1_IC_POLARITY_OK ( POLARITY )
Value:
(((POLARITY) == TIM1_ICPOLARITY_RISING) || \
    ((POLARITY) == TIM1_ICPOLARITY_FALLING))

Definition at line 240 of file stm8s_tim1.h.

Referenced by TIM1_EncoderInterfaceConfig(), TIM1_ICInit(), TIM1_PWMIConfig(), and TIM1_TIxExternalClockConfig().

#define IS_TIM1_IC_PRESCALER_OK ( PRESCALER )
Value:
(((PRESCALER) == TIM1_ICPSC_DIV1) || \
    ((PRESCALER) == TIM1_ICPSC_DIV2) || \
    ((PRESCALER) == TIM1_ICPSC_DIV4) || \
    ((PRESCALER) == TIM1_ICPSC_DIV8))

Definition at line 264 of file stm8s_tim1.h.

Referenced by TIM1_ICInit(), TIM1_PWMIConfig(), TIM1_SetIC1Prescaler(), TIM1_SetIC2Prescaler(), TIM1_SetIC3Prescaler(), and TIM1_SetIC4Prescaler().

#define IS_TIM1_IC_SELECTION_OK ( SELECTION )
Value:
(((SELECTION) == TIM1_ICSELECTION_DIRECTTI) || \
    ((SELECTION) == TIM1_ICSELECTION_INDIRECTTI) || \
    ((SELECTION) == TIM1_ICSELECTION_TRGI))

Definition at line 251 of file stm8s_tim1.h.

Referenced by TIM1_ICInit(), and TIM1_PWMIConfig().

#define IS_TIM1_IT_OK ( IT ) ((IT) != 0x00)

Definition at line 289 of file stm8s_tim1.h.

Referenced by TIM1_ClearITPendingBit(), and TIM1_ITConfig().

#define IS_TIM1_LOCK_LEVEL_OK ( LEVEL )
Value:
(((LEVEL) == TIM1_LOCKLEVEL_OFF) || \
                                      ((LEVEL) == TIM1_LOCKLEVEL_1) || \
                                      ((LEVEL) == TIM1_LOCKLEVEL_2) || \
                                      ((LEVEL) == TIM1_LOCKLEVEL_3))

Definition at line 198 of file stm8s_tim1.h.

Referenced by TIM1_BDTRConfig().

#define IS_TIM1_OC_MODE_OK ( MODE )
Value:
(((MODE) ==  TIM1_OCMODE_TIMING) || \
                                  ((MODE) == TIM1_OCMODE_ACTIVE) || \
                                  ((MODE) == TIM1_OCMODE_INACTIVE) || \
                                  ((MODE) == TIM1_OCMODE_TOGGLE)|| \
                                  ((MODE) == TIM1_OCMODE_PWM1) || \
                                  ((MODE) == TIM1_OCMODE_PWM2))

Definition at line 55 of file stm8s_tim1.h.

Referenced by TIM1_OC1Init(), TIM1_OC2Init(), TIM1_OC3Init(), and TIM1_OC4Init().

#define IS_TIM1_OC_POLARITY_OK ( POLARITY )
Value:
(((POLARITY) == TIM1_OCPOLARITY_HIGH) || \
    ((POLARITY) == TIM1_OCPOLARITY_LOW))

Definition at line 128 of file stm8s_tim1.h.

Referenced by TIM1_OC1Init(), TIM1_OC1PolarityConfig(), TIM1_OC2Init(), TIM1_OC2PolarityConfig(), TIM1_OC3Init(), TIM1_OC3PolarityConfig(), TIM1_OC4Init(), and TIM1_OC4PolarityConfig().

#define IS_TIM1_OCIDLE_STATE_OK ( STATE )
Value:
(((STATE) == TIM1_OCIDLESTATE_SET) || \
                                        ((STATE) == TIM1_OCIDLESTATE_RESET))

Definition at line 220 of file stm8s_tim1.h.

Referenced by TIM1_OC1Init(), TIM1_OC2Init(), TIM1_OC3Init(), and TIM1_OC4Init().

#define IS_TIM1_OCM_OK ( MODE )
Value:
(((MODE) ==  TIM1_OCMODE_TIMING) || \
                             ((MODE) == TIM1_OCMODE_ACTIVE) || \
                             ((MODE) == TIM1_OCMODE_INACTIVE) || \
                             ((MODE) == TIM1_OCMODE_TOGGLE)|| \
                             ((MODE) == TIM1_OCMODE_PWM1) || \
                             ((MODE) == TIM1_OCMODE_PWM2) || \
                             ((MODE) == (uint8_t)TIM1_FORCEDACTION_ACTIVE) || \
                             ((MODE) == (uint8_t)TIM1_FORCEDACTION_INACTIVE))

Definition at line 62 of file stm8s_tim1.h.

Referenced by TIM1_SelectOCxM().

#define IS_TIM1_OCN_POLARITY_OK ( POLARITY )
Value:
(((POLARITY) == TIM1_OCNPOLARITY_HIGH) || \
    ((POLARITY) == TIM1_OCNPOLARITY_LOW))

Definition at line 138 of file stm8s_tim1.h.

Referenced by TIM1_OC1Init(), TIM1_OC1NPolarityConfig(), TIM1_OC2Init(), TIM1_OC2NPolarityConfig(), TIM1_OC3Init(), and TIM1_OC3NPolarityConfig().

#define IS_TIM1_OCNIDLE_STATE_OK ( STATE )
Value:
(((STATE) == TIM1_OCNIDLESTATE_SET) || \
    ((STATE) == TIM1_OCNIDLESTATE_RESET))

Definition at line 230 of file stm8s_tim1.h.

Referenced by TIM1_OC1Init(), TIM1_OC2Init(), and TIM1_OC3Init().

#define IS_TIM1_OPM_MODE_OK ( MODE )
Value:
(((MODE) == TIM1_OPMODE_SINGLE) || \
                                   ((MODE) == TIM1_OPMODE_REPETITIVE))

Definition at line 78 of file stm8s_tim1.h.

Referenced by TIM1_SelectOnePulseMode().

#define IS_TIM1_OSSI_STATE_OK ( STATE )
Value:
(((STATE) == TIM1_OSSISTATE_ENABLE) || \
                                      ((STATE) == TIM1_OSSISTATE_DISABLE))

Definition at line 210 of file stm8s_tim1.h.

Referenced by TIM1_BDTRConfig().

#define IS_TIM1_OUTPUT_STATE_OK ( STATE )
Value:
(((STATE) == TIM1_OUTPUTSTATE_DISABLE) || \
                                        ((STATE) == TIM1_OUTPUTSTATE_ENABLE))

Definition at line 148 of file stm8s_tim1.h.

Referenced by TIM1_OC1Init(), TIM1_OC2Init(), TIM1_OC3Init(), and TIM1_OC4Init().

#define IS_TIM1_OUTPUTN_STATE_OK ( STATE )
Value:
(((STATE) == TIM1_OUTPUTNSTATE_DISABLE) ||\
    ((STATE) == TIM1_OUTPUTNSTATE_ENABLE))

Definition at line 158 of file stm8s_tim1.h.

Referenced by TIM1_OC1Init(), TIM1_OC2Init(), and TIM1_OC3Init().

#define IS_TIM1_PRESCALER_RELOAD_OK ( RELOAD )
Value:
(((RELOAD) == TIM1_PSCRELOADMODE_UPDATE) || \
    ((RELOAD) == TIM1_PSCRELOADMODE_IMMEDIATE))

Definition at line 367 of file stm8s_tim1.h.

Referenced by TIM1_PrescalerConfig().

#define IS_TIM1_PWMI_CHANNEL_OK ( CHANNEL )
Value:
(((CHANNEL) == TIM1_CHANNEL_1) || \
    ((CHANNEL) == TIM1_CHANNEL_2))

Definition at line 97 of file stm8s_tim1.h.

Referenced by TIM1_PWMIConfig().

#define IS_TIM1_SLAVE_MODE_OK ( MODE )
Value:
(((MODE) == TIM1_SLAVEMODE_RESET) || \
                                     ((MODE) == TIM1_SLAVEMODE_GATED) || \
                                     ((MODE) == TIM1_SLAVEMODE_TRIGGER) || \
                                     ((MODE) == TIM1_SLAVEMODE_EXTERNAL1))

Definition at line 436 of file stm8s_tim1.h.

Referenced by TIM1_SelectSlaveMode().

#define IS_TIM1_TIX_TRIGGER_SELECTION_OK ( SELECTION )
Value:
(((SELECTION) == TIM1_TS_TI1F_ED) || \
    ((SELECTION) == TIM1_TS_TI1FP1) || \
    ((SELECTION) == TIM1_TS_TI2FP2))

Definition at line 334 of file stm8s_tim1.h.

#define IS_TIM1_TIXCLK_SOURCE_OK ( SOURCE )
Value:
(((SOURCE) == TIM1_TIXEXTERNALCLK1SOURCE_TI1ED) || \
    ((SOURCE) == TIM1_TIXEXTERNALCLK1SOURCE_TI2) || \
    ((SOURCE) == TIM1_TIXEXTERNALCLK1SOURCE_TI1))

Definition at line 346 of file stm8s_tim1.h.

Referenced by TIM1_TIxExternalClockConfig().

#define IS_TIM1_TRGO_SOURCE_OK ( SOURCE )
Value:
(((SOURCE) == TIM1_TRGOSOURCE_RESET) || \
                                        ((SOURCE) == TIM1_TRGOSOURCE_ENABLE) || \
                                        ((SOURCE) == TIM1_TRGOSOURCE_UPDATE) || \
                                        ((SOURCE) == TIM1_TRGOSource_OC1)  || \
                                        ((SOURCE) == TIM1_TRGOSOURCE_OC1REF) || \
                                        ((SOURCE) == TIM1_TRGOSOURCE_OC2REF) || \
                                        ((SOURCE) == TIM1_TRGOSOURCE_OC3REF))

Definition at line 419 of file stm8s_tim1.h.

Referenced by TIM1_SelectOutputTrigger().

#define IS_TIM1_TRIGGER_SELECTION_OK ( SELECTION )
Value:
(((SELECTION) == TIM1_TS_TI1F_ED) || \
    ((SELECTION) == TIM1_TS_TI1FP1) || \
    ((SELECTION) == TIM1_TS_TI2FP2) || \
    ((SELECTION) == TIM1_TS_ETRF) || \
    ((SELECTION) == TIM1_TS_TIM5) || \
    ((SELECTION) == TIM1_TS_TIM6))

Definition at line 326 of file stm8s_tim1.h.

Referenced by TIM1_SelectInputTrigger().

#define IS_TIM1_UPDATE_SOURCE_OK ( SOURCE )
Value:
(((SOURCE) == TIM1_UPDATESOURCE_GLOBAL) || \
    ((SOURCE) == TIM1_UPDATESOURCE_REGULAR))

Definition at line 404 of file stm8s_tim1.h.

Referenced by TIM1_UpdateRequestConfig().

Enumeration Type Documentation

enum TIM1_AutomaticOutput_TypeDef

TIM1 AOE Bit Set/Reset.

Enumerator:
TIM1_AUTOMATICOUTPUT_ENABLE
TIM1_AUTOMATICOUTPUT_DISABLE

Definition at line 180 of file stm8s_tim1.h.

enum TIM1_BreakPolarity_TypeDef

TIM1 Break Polarity.

Enumerator:
TIM1_BREAKPOLARITY_LOW
TIM1_BREAKPOLARITY_HIGH

Definition at line 171 of file stm8s_tim1.h.

enum TIM1_BreakState_TypeDef

TIM1 Break Input enable/disable.

Enumerator:
TIM1_BREAK_ENABLE
TIM1_BREAK_DISABLE

Definition at line 162 of file stm8s_tim1.h.

enum TIM1_Channel_TypeDef

TIM1 Channel.

Enumerator:
TIM1_CHANNEL_1
TIM1_CHANNEL_2
TIM1_CHANNEL_3
TIM1_CHANNEL_4

Definition at line 83 of file stm8s_tim1.h.

enum TIM1_CounterMode_TypeDef

TIM1 Counter Mode.

Enumerator:
TIM1_COUNTERMODE_UP
TIM1_COUNTERMODE_DOWN
TIM1_COUNTERMODE_CENTERALIGNED1
TIM1_COUNTERMODE_CENTERALIGNED2
TIM1_COUNTERMODE_CENTERALIGNED3

Definition at line 106 of file stm8s_tim1.h.

enum TIM1_EncoderMode_TypeDef

TIM1 Encoder Mode.

Enumerator:
TIM1_ENCODERMODE_TI1
TIM1_ENCODERMODE_TI2
TIM1_ENCODERMODE_TI12

Definition at line 371 of file stm8s_tim1.h.

enum TIM1_EventSource_TypeDef

TIM1 Event Source.

Enumerator:
TIM1_EVENTSOURCE_UPDATE
TIM1_EVENTSOURCE_CC1
TIM1_EVENTSOURCE_CC2
TIM1_EVENTSOURCE_CC3
TIM1_EVENTSOURCE_CC4
TIM1_EVENTSOURCE_COM
TIM1_EVENTSOURCE_TRIGGER
TIM1_EVENTSOURCE_BREAK

Definition at line 383 of file stm8s_tim1.h.

enum TIM1_ExtTRGPolarity_TypeDef

TIM1 External Trigger Polarity.

Enumerator:
TIM1_EXTTRGPOLARITY_INVERTED
TIM1_EXTTRGPOLARITY_NONINVERTED

Definition at line 351 of file stm8s_tim1.h.

enum TIM1_ExtTRGPSC_TypeDef

TIM1 External Trigger Prescaler.

Enumerator:
TIM1_EXTTRGPSC_OFF
TIM1_EXTTRGPSC_DIV2
TIM1_EXTTRGPSC_DIV4
TIM1_EXTTRGPSC_DIV8

Definition at line 302 of file stm8s_tim1.h.

enum TIM1_FLAG_TypeDef

TIM1 Flags.

Enumerator:
TIM1_FLAG_UPDATE
TIM1_FLAG_CC1
TIM1_FLAG_CC2
TIM1_FLAG_CC3
TIM1_FLAG_CC4
TIM1_FLAG_COM
TIM1_FLAG_TRIGGER
TIM1_FLAG_BREAK
TIM1_FLAG_CC1OF
TIM1_FLAG_CC2OF
TIM1_FLAG_CC3OF
TIM1_FLAG_CC4OF

Definition at line 442 of file stm8s_tim1.h.

enum TIM1_ForcedAction_TypeDef

TIM1 Forced Action.

Enumerator:
TIM1_FORCEDACTION_ACTIVE
TIM1_FORCEDACTION_INACTIVE

Definition at line 474 of file stm8s_tim1.h.

enum TIM1_ICPolarity_TypeDef

TIM1 Input Capture Polarity.

Enumerator:
TIM1_ICPOLARITY_RISING
TIM1_ICPOLARITY_FALLING

Definition at line 234 of file stm8s_tim1.h.

enum TIM1_ICPSC_TypeDef

TIM1 Input Capture Prescaler.

Enumerator:
TIM1_ICPSC_DIV1
TIM1_ICPSC_DIV2
TIM1_ICPSC_DIV4
TIM1_ICPSC_DIV8

Definition at line 256 of file stm8s_tim1.h.

enum TIM1_ICSelection_TypeDef

TIM1 Input Capture Selection.

Enumerator:
TIM1_ICSELECTION_DIRECTTI
TIM1_ICSELECTION_INDIRECTTI
TIM1_ICSELECTION_TRGI

Definition at line 244 of file stm8s_tim1.h.

enum TIM1_IT_TypeDef

TIM1 interrupt sources.

Enumerator:
TIM1_IT_UPDATE
TIM1_IT_CC1
TIM1_IT_CC2
TIM1_IT_CC3
TIM1_IT_CC4
TIM1_IT_COM
TIM1_IT_TRIGGER
TIM1_IT_BREAK

Definition at line 277 of file stm8s_tim1.h.

enum TIM1_LockLevel_TypeDef

TIM1 Lock levels.

Enumerator:
TIM1_LOCKLEVEL_OFF
TIM1_LOCKLEVEL_1
TIM1_LOCKLEVEL_2
TIM1_LOCKLEVEL_3

Definition at line 190 of file stm8s_tim1.h.

enum TIM1_OCIdleState_TypeDef

TIM1 Output Compare Idle State.

Enumerator:
TIM1_OCIDLESTATE_SET
TIM1_OCIDLESTATE_RESET

Definition at line 214 of file stm8s_tim1.h.

enum TIM1_OCMode_TypeDef

TIM1 Output Compare and PWM modes.

Enumerator:
TIM1_OCMODE_TIMING
TIM1_OCMODE_ACTIVE
TIM1_OCMODE_INACTIVE
TIM1_OCMODE_TOGGLE
TIM1_OCMODE_PWM1
TIM1_OCMODE_PWM2

Definition at line 45 of file stm8s_tim1.h.

enum TIM1_OCNIdleState_TypeDef

TIM1 Output Compare N Idle State.

Enumerator:
TIM1_OCNIDLESTATE_SET
TIM1_OCNIDLESTATE_RESET

Definition at line 224 of file stm8s_tim1.h.

enum TIM1_OCNPolarity_TypeDef

TIM1 Output Compare N Polarity.

Enumerator:
TIM1_OCNPOLARITY_HIGH
TIM1_OCNPOLARITY_LOW

Definition at line 132 of file stm8s_tim1.h.

enum TIM1_OCPolarity_TypeDef

TIM1 Output Compare Polarity.

Enumerator:
TIM1_OCPOLARITY_HIGH
TIM1_OCPOLARITY_LOW

Definition at line 122 of file stm8s_tim1.h.

enum TIM1_OPMode_TypeDef

TIM1 One Pulse Mode.

Enumerator:
TIM1_OPMODE_SINGLE
TIM1_OPMODE_REPETITIVE

Definition at line 72 of file stm8s_tim1.h.

enum TIM1_OSSIState_TypeDef

TIM1 OSSI: Off-State Selection for Idle mode states.

Enumerator:
TIM1_OSSISTATE_ENABLE
TIM1_OSSISTATE_DISABLE

Definition at line 204 of file stm8s_tim1.h.

enum TIM1_OutputNState_TypeDef

TIM1 Output Compare N States.

Enumerator:
TIM1_OUTPUTNSTATE_DISABLE
TIM1_OUTPUTNSTATE_ENABLE

Definition at line 152 of file stm8s_tim1.h.

enum TIM1_OutputState_TypeDef

TIM1 Output Compare states.

Enumerator:
TIM1_OUTPUTSTATE_DISABLE
TIM1_OUTPUTSTATE_ENABLE

Definition at line 142 of file stm8s_tim1.h.

enum TIM1_PSCReloadMode_TypeDef

TIM1 Prescaler Reload Mode.

Enumerator:
TIM1_PSCRELOADMODE_UPDATE
TIM1_PSCRELOADMODE_IMMEDIATE

Definition at line 361 of file stm8s_tim1.h.

enum TIM1_SlaveMode_TypeDef

TIM1 Slave Mode.

Enumerator:
TIM1_SLAVEMODE_RESET
TIM1_SLAVEMODE_GATED
TIM1_SLAVEMODE_TRIGGER
TIM1_SLAVEMODE_EXTERNAL1

Definition at line 428 of file stm8s_tim1.h.

enum TIM1_TIxExternalCLK1Source_TypeDef

TIM1 TIx External Clock Source.

Enumerator:
TIM1_TIXEXTERNALCLK1SOURCE_TI1ED
TIM1_TIXEXTERNALCLK1SOURCE_TI1
TIM1_TIXEXTERNALCLK1SOURCE_TI2

Definition at line 339 of file stm8s_tim1.h.

enum TIM1_TRGOSource_TypeDef

TIM1 Trigger Output Source.

Enumerator:
TIM1_TRGOSOURCE_RESET
TIM1_TRGOSOURCE_ENABLE
TIM1_TRGOSOURCE_UPDATE
TIM1_TRGOSource_OC1
TIM1_TRGOSOURCE_OC1REF
TIM1_TRGOSOURCE_OC2REF
TIM1_TRGOSOURCE_OC3REF

Definition at line 408 of file stm8s_tim1.h.

enum TIM1_TS_TypeDef

TIM1 Internal Trigger Selection.

Enumerator:
TIM1_TS_TIM6

TRIG Input source = TIM6 TRIG Output

TIM1_TS_TIM5

TRIG Input source = TIM5 TRIG Output

TIM1_TS_TI1F_ED
TIM1_TS_TI1FP1
TIM1_TS_TI2FP2
TIM1_TS_ETRF

Definition at line 316 of file stm8s_tim1.h.

enum TIM1_UpdateSource_TypeDef

TIM1 Update Source.

Enumerator:
TIM1_UPDATESOURCE_GLOBAL
TIM1_UPDATESOURCE_REGULAR

Definition at line 398 of file stm8s_tim1.h.


STM8S/A Standard Peripherals Drivers: TIM1_Exported_Functions

Functions
TIM1_Exported_Functions
STM8S_StdPeriph_Driver

Functions

void | TIM1_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM1 peripheral Preload register on ARR.
void | TIM1_BDTRConfig (TIM1_OSSIState_TypeDef TIM1_OSSIState, TIM1_LockLevel_TypeDef TIM1_LockLevel, uint8_t TIM1_DeadTime, TIM1_BreakState_TypeDef TIM1_Break, TIM1_BreakPolarity_TypeDef TIM1_BreakPolarity, TIM1_AutomaticOutput_TypeDef TIM1_AutomaticOutput)
Configures the Break feature, dead time, Lock level, the OSSI, and the AOE(automatic output enable).
void | TIM1_CCPreloadControl (FunctionalState NewState)
Sets or Resets the TIM1 peripheral Capture Compare Preload Control bit.
void | TIM1_CCxCmd (TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState)
Enables or disables the TIM1 Capture Compare Channel x (x=1,..,4).
void | TIM1_CCxNCmd (TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState)
Enables or disables the TIM1 Capture Compare Channel xN (xN=1,..,3).
void | TIM1_ClearFlag (TIM1_FLAG_TypeDef TIM1_FLAG)
Clears the TIM1’s pending flags.
void | TIM1_ClearITPendingBit (TIM1_IT_TypeDef TIM1_IT)
Clears the TIM1's interrupt pending bits.
void | TIM1_Cmd (FunctionalState NewState)
Enables or disables the TIM1 peripheral.
void | TIM1_CounterModeConfig (TIM1_CounterMode_TypeDef TIM1_CounterMode)
Specifies the TIM1 Counter Mode to be used.
void | TIM1_CtrlPWMOutputs (FunctionalState NewState)
Enables or disables the TIM1 peripheral Main Outputs.
void | TIM1_DeInit (void)
Deinitializes the TIM1 peripheral registers to their default reset values.
void | TIM1_EncoderInterfaceConfig (TIM1_EncoderMode_TypeDef TIM1_EncoderMode, TIM1_ICPolarity_TypeDef TIM1_IC1Polarity, TIM1_ICPolarity_TypeDef TIM1_IC2Polarity)
Configures the TIM1 Encoder Interface.
void | TIM1_ETRClockMode1Config (TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, uint8_t ExtTRGFilter)
Configures the TIM1 External clock Mode1.
void | TIM1_ETRClockMode2Config (TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, uint8_t ExtTRGFilter)
Configures the TIM1 External clock Mode2.
void | TIM1_ETRConfig (TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, uint8_t ExtTRGFilter)
Configures the TIM1 External Trigger.
void | TIM1_ForcedOC1Config (TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
Forces the TIM1 Channel1 output waveform to active or inactive level.
void | TIM1_ForcedOC2Config (TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
Forces the TIM1 Channel2 output waveform to active or inactive level.
void | TIM1_ForcedOC3Config (TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
Forces the TIM1 Channel3 output waveform to active or inactive level.
void | TIM1_ForcedOC4Config (TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
Forces the TIM1 Channel4 output waveform to active or inactive level.
void | TIM1_GenerateEvent (TIM1_EventSource_TypeDef TIM1_EventSource)
Configures the TIM1 event to be generated by software.
uint16_t | TIM1_GetCapture1 (void)
Gets the TIM1 Input Capture 1 value.
uint16_t | TIM1_GetCapture2 (void)
Gets the TIM1 Input Capture 2 value.
uint16_t | TIM1_GetCapture3 (void)
Gets the TIM1 Input Capture 3 value.
uint16_t | TIM1_GetCapture4 (void)
Gets the TIM1 Input Capture 4 value.
uint16_t | TIM1_GetCounter (void)
Gets the TIM1 Counter value.
FlagStatus | TIM1_GetFlagStatus (TIM1_FLAG_TypeDef TIM1_FLAG)
Checks whether the specified TIM1 flag is set or not.
ITStatus | TIM1_GetITStatus (TIM1_IT_TypeDef TIM1_IT)
Checks whether the TIM1 interrupt has occurred or not.
uint16_t | TIM1_GetPrescaler (void)
Gets the TIM1 Prescaler value.
void | TIM1_ICInit (TIM1_Channel_TypeDef TIM1_Channel, TIM1_ICPolarity_TypeDef TIM1_ICPolarity, TIM1_ICSelection_TypeDef TIM1_ICSelection, TIM1_ICPSC_TypeDef TIM1_ICPrescaler, uint8_t TIM1_ICFilter)
Initializes the TIM1 peripheral according to the specified parameters.
void | TIM1_InternalClockConfig (void)
Configures the TIM1 internal Clock.
void | TIM1_ITConfig (TIM1_IT_TypeDef TIM1_IT, FunctionalState NewState)
Enables or disables the specified TIM1 interrupts.
void | TIM1_OC1FastConfig (FunctionalState NewState)
Configures the TIM1 Capture Compare 1 Fast feature.
void | TIM1_OC1Init (TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, TIM1_OutputNState_TypeDef TIM1_OutputNState, uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState, TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
Initializes the TIM1 Channel1 according to the specified parameters.
void | TIM1_OC1NPolarityConfig (TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
Configures the TIM1 Channel 1N polarity.
void | TIM1_OC1PolarityConfig (TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
Configures the TIM1 Channel 1 polarity.
void | TIM1_OC1PreloadConfig (FunctionalState NewState)
Enables or disables the TIM1 peripheral Preload Register on CCR1.
void | TIM1_OC2FastConfig (FunctionalState NewState)
Configures the TIM1 Capture Compare 2 Fast feature.
void | TIM1_OC2Init (TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, TIM1_OutputNState_TypeDef TIM1_OutputNState, uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState, TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
Initializes the TIM1 Channel2 according to the specified parameters.
void | TIM1_OC2NPolarityConfig (TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
Configures the TIM1 Channel 2N polarity.
void | TIM1_OC2PolarityConfig (TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
Configures the TIM1 Channel 2 polarity.
void | TIM1_OC2PreloadConfig (FunctionalState NewState)
Enables or disables the TIM1 peripheral Preload Register on CCR2.
void | TIM1_OC3FastConfig (FunctionalState NewState)
Configures the TIM1 Capture Compare 3 Fast feature.
void | TIM1_OC3Init (TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, TIM1_OutputNState_TypeDef TIM1_OutputNState, uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState, TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
Initializes the TIM1 Channel3 according to the specified parameters.
void | TIM1_OC3NPolarityConfig (TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
Configures the TIM1 Channel 3N polarity.
void | TIM1_OC3PolarityConfig (TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
Configures the TIM1 Channel 3 polarity.
void | TIM1_OC3PreloadConfig (FunctionalState NewState)
Enables or disables the TIM1 peripheral Preload Register on CCR3.
void | TIM1_OC4FastConfig (FunctionalState NewState)
Configures the TIM1 Capture Compare 4 Fast feature.
void | TIM1_OC4Init (TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState)
Initializes the TIM1 Channel4 according to the specified parameters.
void | TIM1_OC4PolarityConfig (TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
Configures the TIM1 Channel 4 polarity.
void | TIM1_OC4PreloadConfig (FunctionalState NewState)
Enables or disables the TIM1 peripheral Preload Register on CCR4.
void | TIM1_PrescalerConfig (uint16_t Prescaler, TIM1_PSCReloadMode_TypeDef TIM1_PSCReloadMode)
Configures the TIM1 Prescaler.
void | TIM1_PWMIConfig (TIM1_Channel_TypeDef TIM1_Channel, TIM1_ICPolarity_TypeDef TIM1_ICPolarity, TIM1_ICSelection_TypeDef TIM1_ICSelection, TIM1_ICPSC_TypeDef TIM1_ICPrescaler, uint8_t TIM1_ICFilter)
Configures the TIM1 peripheral in PWM Input Mode according to the specified parameters.
void | TIM1_SelectCOM (FunctionalState NewState)
Selects the TIM1 peripheral Commutation event.
void | TIM1_SelectHallSensor (FunctionalState NewState)
Enables or Disables the TIM1’s Hall sensor interface.
void | TIM1_SelectInputTrigger (TIM1_TS_TypeDef TIM1_InputTriggerSource)
Selects the TIM1 Input Trigger source.
void | TIM1_SelectMasterSlaveMode (FunctionalState NewState)
Sets or Resets the TIM1 Master/Slave Mode.
void | TIM1_SelectOCxM (TIM1_Channel_TypeDef TIM1_Channel, TIM1_OCMode_TypeDef TIM1_OCMode)
Selects the TIM1 Output Compare Mode.
void | TIM1_SelectOnePulseMode (TIM1_OPMode_TypeDef TIM1_OPMode)
Selects the TIM1’s One Pulse Mode.
void | TIM1_SelectOutputTrigger (TIM1_TRGOSource_TypeDef TIM1_TRGOSource)
Selects the TIM1 Trigger Output Mode.
void | TIM1_SelectSlaveMode (TIM1_SlaveMode_TypeDef TIM1_SlaveMode)
Selects the TIM1 Slave Mode.
void | TIM1_SetAutoreload (uint16_t Autoreload)
Sets the TIM1 Autoreload Register value.
void | TIM1_SetCompare1 (uint16_t Compare1)
Sets the TIM1 Capture Compare1 Register value.
void | TIM1_SetCompare2 (uint16_t Compare2)
Sets the TIM1 Capture Compare2 Register value.
void | TIM1_SetCompare3 (uint16_t Compare3)
Sets the TIM1 Capture Compare3 Register value.
void | TIM1_SetCompare4 (uint16_t Compare4)
Sets the TIM1 Capture Compare4 Register value.
void | TIM1_SetCounter (uint16_t Counter)
Sets the TIM1 Counter Register value.
void | TIM1_SetIC1Prescaler (TIM1_ICPSC_TypeDef TIM1_IC1Prescaler)
Sets the TIM1 Input Capture 1 prescaler.
void | TIM1_SetIC2Prescaler (TIM1_ICPSC_TypeDef TIM1_IC2Prescaler)
Sets the TIM1 Input Capture 2 prescaler.
void | TIM1_SetIC3Prescaler (TIM1_ICPSC_TypeDef TIM1_IC3Prescaler)
Sets the TIM1 Input Capture 3 prescaler.
void | TIM1_SetIC4Prescaler (TIM1_ICPSC_TypeDef TIM1_IC4Prescaler)
Sets the TIM1 Input Capture 4 prescaler.
void | TIM1_TimeBaseInit (uint16_t TIM1_Prescaler, TIM1_CounterMode_TypeDef TIM1_CounterMode, uint16_t TIM1_Period, uint8_t TIM1_RepetitionCounter)
Initializes the TIM1 Time Base Unit according to the specified parameters.
void | TIM1_TIxExternalClockConfig (TIM1_TIxExternalCLK1Source_TypeDef TIM1_TIxExternalCLKSource, TIM1_ICPolarity_TypeDef TIM1_ICPolarity, uint8_t ICFilter)
Configures the TIM1 Trigger as External Clock.
void | TIM1_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM1 Update event.
void | TIM1_UpdateRequestConfig (TIM1_UpdateSource_TypeDef TIM1_UpdateSource)
Selects the TIM1 Update Request Interrupt source.

Function Documentation

void TIM1_ARRPreloadConfig ( FunctionalState NewState )

Enables or disables TIM1 peripheral Preload register on ARR.

Parameters:
NewState new state of the TIM1 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1139 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CR1_ARPE.

void TIM1_BDTRConfig | ( | TIM1_OSSIState_TypeDef | TIM1_OSSIState,
 |  | TIM1_LockLevel_TypeDef | TIM1_LockLevel,
 |  | uint8_t | TIM1_DeadTime,
 |  | TIM1_BreakState_TypeDef | TIM1_Break,
 |  | TIM1_BreakPolarity_TypeDef | TIM1_BreakPolarity,
 |  | TIM1_AutomaticOutput_TypeDef | TIM1_AutomaticOutput
 | ) |  |

Configures the Break feature, dead time, Lock level, the OSSI, and the AOE(automatic output enable).

Parameters:
TIM1_OSSIState | specifies the OSSIS State from TIM1_OSSIState_TypeDef.
TIM1_LockLevel | specifies the lock level from TIM1_LockLevel_TypeDef.
TIM1_DeadTime | specifies the dead time value.
TIM1_Break | specifies the Break state TIM1_BreakState_TypeDef.
TIM1_BreakPolarity | specifies the Break polarity from TIM1_BreakPolarity_TypeDef.
TIM1_AutomaticOutput | specifies the Automatic Output configuration from TIM1_AutomaticOutput_TypeDef.
Return values:
None

Definition at line 388 of file stm8s_tim1.c.

References IS_TIM1_AUTOMATIC_OUTPUT_STATE_OK, IS_TIM1_BREAK_POLARITY_OK, IS_TIM1_BREAK_STATE_OK, IS_TIM1_LOCK_LEVEL_OK, IS_TIM1_OSSI_STATE_OK, and TIM1.

void TIM1_CCPreloadControl ( FunctionalState NewState )

Sets or Resets the TIM1 peripheral Capture Compare Preload Control bit.

Parameters:
NewState new state of the Capture Compare Preload Control bit. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1183 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CR2_CCPC.

void TIM1_CCxCmd | ( | TIM1_Channel_TypeDef | TIM1_Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the TIM1 Capture Compare Channel x (x=1,..,4).

Parameters:
TIM1_Channel specifies the TIM1 Channel. This parameter can be one of the following values:
  • TIM1_CHANNEL_1: TIM1 Channel1
  • TIM1_CHANNEL_2: TIM1 Channel2
  • TIM1_CHANNEL_3: TIM1 Channel3
  • TIM1_CHANNEL_4: TIM1 Channel4
NewState specifies the TIM1 Channel CCxE bit new state. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1579 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, IS_TIM1_CHANNEL_OK, TIM1, TIM1_CCER1_CC1E, TIM1_CCER1_CC2E, TIM1_CCER2_CC3E, TIM1_CCER2_CC4E, TIM1_CHANNEL_1, TIM1_CHANNEL_2, and TIM1_CHANNEL_3.

void TIM1_CCxNCmd | ( | TIM1_Channel_TypeDef | TIM1_Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the TIM1 Capture Compare Channel xN (xN=1,..,3).

Parameters:
TIM1_Channel specifies the TIM1 Channel. This parameter can be one of the following values:
  • TIM1_CHANNEL_1: TIM1 Channel1
  • TIM1_CHANNEL_2: TIM1 Channel2
  • TIM1_CHANNEL_3: TIM1 Channel3
NewState specifies the TIM1 Channel CCxNE bit new state. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1647 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, IS_TIM1_COMPLEMENTARY_CHANNEL_OK, TIM1, TIM1_CCER1_CC1NE, TIM1_CCER1_CC2NE, TIM1_CCER2_CC3NE, TIM1_CHANNEL_1, and TIM1_CHANNEL_2.

void TIM1_ClearFlag ( TIM1_FLAG_TypeDef TIM1_FLAG )

Clears the TIM1’s pending flags.

Parameters:
TIM1_FLAG specifies the flag to clear. This parameter can be one of the following values:
  • TIM1_FLAG_UPDATE: TIM1 update Flag
  • TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag
  • TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag
  • TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag
  • TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag
  • TIM1_FLAG_COM: TIM1 Commutation Flag
  • TIM1_FLAG_TRIGGER: TIM1 Trigger Flag
  • TIM1_FLAG_BREAK: TIM1 Break Flag
  • TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag
  • TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag
  • TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag
  • TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag
Return values:
None.

Definition at line 2087 of file stm8s_tim1.c.

References IS_TIM1_CLEAR_FLAG_OK, and TIM1.

void TIM1_ClearITPendingBit ( TIM1_IT_TypeDef TIM1_IT )

Clears the TIM1's interrupt pending bits.

Parameters:
TIM1_IT specifies the pending bit to clear. This parameter can be one of the following values:
  • TIM1_IT_UPDATE: TIM1 update Interrupt source
  • TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source
  • TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source
  • TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source
  • TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source
  • TIM1_IT_COM: TIM1 Commutation Interrupt source
  • TIM1_IT_TRIGGER: TIM1 Trigger Interrupt source
  • TIM1_IT_BREAK: TIM1 Break Interrupt source
Return values:
None.

Definition at line 2149 of file stm8s_tim1.c.

References IS_TIM1_IT_OK, and TIM1.

void TIM1_Cmd ( FunctionalState NewState )

Enables or disables the TIM1 peripheral.

Parameters:
NewState new state of the TIM1 peripheral. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 561 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CR1_CEN.

void TIM1_CounterModeConfig ( TIM1_CounterMode_TypeDef TIM1_CounterMode )

Specifies the TIM1 Counter Mode to be used.

Parameters:
TIM1_CounterMode specifies the Counter Mode to be used This parameter can be one of the following values:
  • TIM1_COUNTERMODE_UP: TIM1 Up Counting Mode
  • TIM1_COUNTERMODE_DOWN: TIM1 Down Counting Mode
  • TIM1_COUNTERMODE_CENTERALIGNED1: TIM1 Center Aligned Mode1
  • TIM1_CounterMode_CenterAligned2: TIM1 Center Aligned Mode2
  • TIM1_COUNTERMODE_CENTERALIGNED3: TIM1 Center Aligned Mode3
Return values:
None

Definition at line 1048 of file stm8s_tim1.c.

References IS_TIM1_COUNTER_MODE_OK, TIM1, TIM1_CR1_CMS, and TIM1_CR1_DIR.

void TIM1_CtrlPWMOutputs ( FunctionalState NewState )

Enables or disables the TIM1 peripheral Main Outputs.

Parameters:
NewState new state of the TIM1 peripheral. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 583 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_BKR_MOE.

void TIM1_DeInit ( void )

Deinitializes the TIM1 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 58 of file stm8s_tim1.c.

References TIM1, TIM1_ARRH_RESET_VALUE, TIM1_ARRL_RESET_VALUE, TIM1_BKR_RESET_VALUE, TIM1_CCER1_RESET_VALUE, TIM1_CCER2_RESET_VALUE, TIM1_CCMR1_RESET_VALUE, TIM1_CCMR2_RESET_VALUE, TIM1_CCMR3_RESET_VALUE, TIM1_CCMR4_RESET_VALUE, TIM1_CCR1H_RESET_VALUE, TIM1_CCR1L_RESET_VALUE, TIM1_CCR2H_RESET_VALUE, TIM1_CCR2L_RESET_VALUE, TIM1_CCR3H_RESET_VALUE, TIM1_CCR3L_RESET_VALUE, TIM1_CCR4H_RESET_VALUE, TIM1_CCR4L_RESET_VALUE, TIM1_CNTRH_RESET_VALUE, TIM1_CNTRL_RESET_VALUE, TIM1_CR1_RESET_VALUE, TIM1_CR2_RESET_VALUE, TIM1_DTR_RESET_VALUE, TIM1_ETR_RESET_VALUE, TIM1_IER_RESET_VALUE, TIM1_OISR_RESET_VALUE, TIM1_PSCRH_RESET_VALUE, TIM1_PSCRL_RESET_VALUE, TIM1_RCR_RESET_VALUE, TIM1_SMCR_RESET_VALUE, TIM1_SR1_RESET_VALUE, and TIM1_SR2_RESET_VALUE.

void TIM1_EncoderInterfaceConfig | ( | TIM1_EncoderMode_TypeDef | TIM1_EncoderMode,
 |  | TIM1_ICPolarity_TypeDef | TIM1_IC1Polarity,
 |  | TIM1_ICPolarity_TypeDef | TIM1_IC2Polarity
 | ) |  |

Configures the TIM1 Encoder Interface.

Parameters:
TIM1_EncoderMode specifies the TIM1 Encoder Mode. This parameter can be one of the following values
  • TIM1_ENCODERMODE_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
  • TIM1_ENCODERMODE_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
  • TIM1_ENCODERMODE_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
TIM1_IC1Polarity specifies the IC1 Polarity. This parameter can be one of the following values
  • TIM1_ICPOLARITY_FALLING
  • TIM1_ICPOLARITY_RISING
TIM1_IC2Polarity specifies the IC2 Polarity. This parameter can be one of the following values
  • TIM1_ICPOLARITY_FALLING
  • TIM1_ICPOLARITY_RISING
Return values:
None

Definition at line 975 of file stm8s_tim1.c.

References CCMR_TIxDirect_Set, IS_TIM1_ENCODER_MODE_OK, IS_TIM1_IC_POLARITY_OK, TIM1, TIM1_CCER1_CC1P, TIM1_CCER1_CC2P, TIM1_CCMR_CCxS, TIM1_ICPOLARITY_RISING, TIM1_SMCR_MSM, and TIM1_SMCR_TS.

void TIM1_ETRClockMode1Config | ( | TIM1_ExtTRGPSC_TypeDef | TIM1_ExtTRGPrescaler,
 |  | TIM1_ExtTRGPolarity_TypeDef | TIM1_ExtTRGPolarity,
 |  | uint8_t | ExtTRGFilter
 | ) |  |

Configures the TIM1 External clock Mode1.

Parameters:
TIM1_ExtTRGPrescaler specifies the external Trigger Prescaler. This parameter can be one of the following values:
  • TIM1_EXTTRGPSC_OFF
  • TIM1_EXTTRGPSC_DIV2
  • TIM1_EXTTRGPSC_DIV4
  • TIM1_EXTTRGPSC_DIV8.
TIM1_ExtTRGPolarity specifies the external Trigger Polarity. This parameter can be one of the following values:
  • TIM1_EXTTRGPOLARITY_INVERTED
  • TIM1_EXTTRGPOLARITY_NONINVERTED
ExtTRGFilter specifies the External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 662 of file stm8s_tim1.c.

References IS_TIM1_EXT_POLARITY_OK, IS_TIM1_EXT_PRESCALER_OK, TIM1, TIM1_ETRConfig(), TIM1_SLAVEMODE_EXTERNAL1, TIM1_SMCR_SMS, TIM1_SMCR_TS, and TIM1_TS_ETRF.

void TIM1_ETRClockMode2Config | ( | TIM1_ExtTRGPSC_TypeDef | TIM1_ExtTRGPrescaler,
 |  | TIM1_ExtTRGPolarity_TypeDef | TIM1_ExtTRGPolarity,
 |  | uint8_t | ExtTRGFilter
 | ) |  |

Configures the TIM1 External clock Mode2.

Parameters:
TIM1_ExtTRGPrescaler specifies the external Trigger Prescaler. This parameter can be one of the following values:
  • TIM1_EXTTRGPSC_OFF
  • TIM1_EXTTRGPSC_DIV2
  • TIM1_EXTTRGPSC_DIV4
  • TIM1_EXTTRGPSC_DIV8.
TIM1_ExtTRGPolarity specifies the external Trigger Polarity. This parameter can be one of the following values:
  • TIM1_EXTTRGPOLARITY_INVERTED
  • TIM1_EXTTRGPOLARITY_NONINVERTED
ExtTRGFilter specifies the External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 694 of file stm8s_tim1.c.

References IS_TIM1_EXT_POLARITY_OK, IS_TIM1_EXT_PRESCALER_OK, TIM1, TIM1_ETR_ECE, and TIM1_ETRConfig().

void TIM1_ETRConfig | ( | TIM1_ExtTRGPSC_TypeDef | TIM1_ExtTRGPrescaler,
 |  | TIM1_ExtTRGPolarity_TypeDef | TIM1_ExtTRGPolarity,
 |  | uint8_t | ExtTRGFilter
 | ) |  |

Configures the TIM1 External Trigger.

Parameters:
TIM1_ExtTRGPrescaler specifies the external Trigger Prescaler. This parameter can be one of the following values:
  • TIM1_EXTTRGPSC_OFF
  • TIM1_EXTTRGPSC_DIV2
  • TIM1_EXTTRGPSC_DIV4
  • TIM1_EXTTRGPSC_DIV8.
TIM1_ExtTRGPolarity specifies the external Trigger Polarity. This parameter can be one of the following values:
  • TIM1_EXTTRGPOLARITY_INVERTED
  • TIM1_EXTTRGPOLARITY_NONINVERTED
ExtTRGFilter specifies the External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 725 of file stm8s_tim1.c.

References IS_TIM1_EXT_TRG_FILTER_OK, and TIM1.

Referenced by TIM1_ETRClockMode1Config(), and TIM1_ETRClockMode2Config().

void TIM1_ForcedOC1Config ( TIM1_ForcedAction_TypeDef TIM1_ForcedAction )

Forces the TIM1 Channel1 output waveform to active or inactive level.

Parameters:
TIM1_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:
  • TIM1_FORCEDACTION_ACTIVE: Force active level on OC1REF
  • TIM1_FORCEDACTION_INACTIVE: Force inactive level on OC1REF.
Return values:
None

Definition at line 1067 of file stm8s_tim1.c.

References IS_TIM1_FORCED_ACTION_OK, TIM1, and TIM1_CCMR_OCM.

void TIM1_ForcedOC2Config ( TIM1_ForcedAction_TypeDef TIM1_ForcedAction )

Forces the TIM1 Channel2 output waveform to active or inactive level.

Parameters:
TIM1_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:
  • TIM1_FORCEDACTION_ACTIVE: Force active level on OC2REF
  • TIM1_FORCEDACTION_INACTIVE: Force inactive level on OC2REF.
Return values:
None

Definition at line 1085 of file stm8s_tim1.c.

References IS_TIM1_FORCED_ACTION_OK, TIM1, and TIM1_CCMR_OCM.

void TIM1_ForcedOC3Config ( TIM1_ForcedAction_TypeDef TIM1_ForcedAction )

Forces the TIM1 Channel3 output waveform to active or inactive level.

Parameters:
TIM1_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:
  • TIM1_FORCEDACTION_ACTIVE: Force active level on OC3REF
  • TIM1_FORCEDACTION_INACTIVE: Force inactive level on OC3REF.
Return values:
None

Definition at line 1104 of file stm8s_tim1.c.

References IS_TIM1_FORCED_ACTION_OK, TIM1, and TIM1_CCMR_OCM.

void TIM1_ForcedOC4Config ( TIM1_ForcedAction_TypeDef TIM1_ForcedAction )

Forces the TIM1 Channel4 output waveform to active or inactive level.

Parameters:
TIM1_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:
  • TIM1_FORCEDACTION_ACTIVE: Force active level on OC4REF
  • TIM1_FORCEDACTION_INACTIVE: Force inactive level on OC4REF.
Return values:
None

Definition at line 1123 of file stm8s_tim1.c.

References IS_TIM1_FORCED_ACTION_OK, TIM1, and TIM1_CCMR_OCM.

void TIM1_GenerateEvent ( TIM1_EventSource_TypeDef TIM1_EventSource )

Configures the TIM1 event to be generated by software.

Parameters:
TIM1_EventSource specifies the event source. This parameter can be one of the following values:
  • TIM1_EVENTSOURCE_UPDATE: TIM1 update Event source
  • TIM1_EVENTSOURCE_CC1: TIM1 Capture Compare 1 Event source
  • TIM1_EVENTSOURCE_CC2: TIM1 Capture Compare 2 Event source
  • TIM1_EVENTSOURCE_CC3: TIM1 Capture Compare 3 Event source
  • TIM1_EVENTSOURCE_CC4: TIM1 Capture Compare 4 Event source
  • TIM1_EVENTSOURCE_COM: TIM1 COM Event source
  • TIM1_EVENTSOURCE_TRIGGER: TIM1 Trigger Event source
  • TIM1_EventSourceBreak: TIM1 Break Event source
Return values:
None

Definition at line 1389 of file stm8s_tim1.c.

References IS_TIM1_EVENT_SOURCE_OK, and TIM1.

uint16_t TIM1_GetCapture1 ( void )

Gets the TIM1 Input Capture 1 value.

Parameters:
None
Return values:
Capture Compare 1 Register value.

Definition at line 1922 of file stm8s_tim1.c.

References TIM1.

uint16_t TIM1_GetCapture2 ( void )

Gets the TIM1 Input Capture 2 value.

Parameters:
None
Return values:
Capture Compare 2 Register value.

Definition at line 1943 of file stm8s_tim1.c.

References TIM1.

uint16_t TIM1_GetCapture3 ( void )

Gets the TIM1 Input Capture 3 value.

Parameters:
None
Return values:
Capture Compare 3 Register value.

Definition at line 1964 of file stm8s_tim1.c.

References TIM1.

uint16_t TIM1_GetCapture4 ( void )

Gets the TIM1 Input Capture 4 value.

Parameters:
None
Return values:
Capture Compare 4 Register value.

Definition at line 1984 of file stm8s_tim1.c.

References TIM1.

uint16_t TIM1_GetCounter ( void )

Gets the TIM1 Counter value.

Parameters:
None
Return values:
Counter Register value.

Definition at line 2004 of file stm8s_tim1.c.

References TIM1.

FlagStatus TIM1_GetFlagStatus ( TIM1_FLAG_TypeDef TIM1_FLAG )

Checks whether the specified TIM1 flag is set or not.

Parameters:
TIM1_FLAG specifies the flag to check. This parameter can be one of the following values:
  • TIM1_FLAG_UPDATE: TIM1 update Flag
  • TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag
  • TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag
  • TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag
  • TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag
  • TIM1_FLAG_COM: TIM1 Commutation Flag
  • TIM1_FLAG_TRIGGER: TIM1 Trigger Flag
  • TIM1_FLAG_BREAK: TIM1 Break Flag
  • TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag
  • TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag
  • TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag
  • TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag
Return values:
FlagStatus The new state of TIM1_FLAG (SET or RESET).

Definition at line 2047 of file stm8s_tim1.c.

References IS_TIM1_GET_FLAG_OK, RESET, SET, and TIM1.

ITStatus TIM1_GetITStatus ( TIM1_IT_TypeDef TIM1_IT )

Checks whether the TIM1 interrupt has occurred or not.

Parameters:
TIM1_IT specifies the TIM1 interrupt source to check. This parameter can be one of the following values:
  • TIM1_IT_UPDATE: TIM1 update Interrupt source
  • TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source
  • TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source
  • TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source
  • TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source
  • TIM1_IT_COM: TIM1 Commutation Interrupt source
  • TIM1_IT_TRIGGER: TIM1 Trigger Interrupt source
  • TIM1_IT_BREAK: TIM1 Break Interrupt source
Return values:
ITStatus The new state of the TIM1_IT(SET or RESET).

Definition at line 2112 of file stm8s_tim1.c.

References IS_TIM1_GET_IT_OK, RESET, SET, and TIM1.

uint16_t TIM1_GetPrescaler ( void )

Gets the TIM1 Prescaler value.

Parameters:
None
Return values:
Prescaler Register value.

Definition at line 2019 of file stm8s_tim1.c.

References TIM1.

void TIM1_ICInit | ( | TIM1_Channel_TypeDef | TIM1_Channel,
 |  | TIM1_ICPolarity_TypeDef | TIM1_ICPolarity,
 |  | TIM1_ICSelection_TypeDef | TIM1_ICSelection,
 |  | TIM1_ICPSC_TypeDef | TIM1_ICPrescaler,
 |  | uint8_t | TIM1_ICFilter
 | ) |  |

Initializes the TIM1 peripheral according to the specified parameters.

Parameters:
TIM1_Channel | specifies the input capture channel from TIM1_Channel_TypeDef.
TIM1_ICPolarity | specifies the Input capture polarity from TIM1_ICPolarity_TypeDef .
TIM1_ICSelection | specifies the Input capture source selection from TIM1_ICSelection_TypeDef.
TIM1_ICPrescaler | specifies the Input capture Prescaler from TIM1_ICPSC_TypeDef.
TIM1_ICFilter | specifies the Input capture filter value.
Return values:
None

Definition at line 423 of file stm8s_tim1.c.

References IS_TIM1_CHANNEL_OK, IS_TIM1_IC_FILTER_OK, IS_TIM1_IC_POLARITY_OK, IS_TIM1_IC_PRESCALER_OK, IS_TIM1_IC_SELECTION_OK, TI1_Config(), TI2_Config(), TI3_Config(), TI4_Config(), TIM1_CHANNEL_1, TIM1_CHANNEL_2, TIM1_CHANNEL_3, TIM1_SetIC1Prescaler(), TIM1_SetIC2Prescaler(), TIM1_SetIC3Prescaler(), and TIM1_SetIC4Prescaler().

void TIM1_InternalClockConfig ( void )

Configures the TIM1 internal Clock.

Parameters:
None
Return values:
None

Definition at line 640 of file stm8s_tim1.c.

References TIM1, and TIM1_SMCR_SMS.

void TIM1_ITConfig | ( | TIM1_IT_TypeDef | TIM1_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified TIM1 interrupts.

Parameters:
NewState | new state of the TIM1 peripheral. This parameter can be: ENABLE or DISABLE.
TIM1_IT specifies the TIM1 interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:
  • TIM1_IT_UPDATE: TIM1 update Interrupt source
  • TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source
  • TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source
  • TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source
  • TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source
  • TIM1_IT_CCUpdate: TIM1 Capture Compare Update Interrupt source
  • TIM1_IT_TRIGGER: TIM1 Trigger Interrupt source
  • TIM1_IT_BREAK: TIM1 Break Interrupt source
NewState | new state of the TIM1 peripheral.
Return values:
None

Definition at line 617 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, IS_TIM1_IT_OK, and TIM1.

void TIM1_OC1FastConfig ( FunctionalState NewState )

Configures the TIM1 Capture Compare 1 Fast feature.

Parameters:
NewState new state of the Output Compare Fast Enable bit. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1293 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CCMR_OCxFE.

void TIM1_OC1Init | ( | TIM1_OCMode_TypeDef | TIM1_OCMode,
 |  | TIM1_OutputState_TypeDef | TIM1_OutputState,
 |  | TIM1_OutputNState_TypeDef | TIM1_OutputNState,
 |  | uint16_t | TIM1_Pulse,
 |  | TIM1_OCPolarity_TypeDef | TIM1_OCPolarity,
 |  | TIM1_OCNPolarity_TypeDef | TIM1_OCNPolarity,
 |  | TIM1_OCIdleState_TypeDef | TIM1_OCIdleState,
 |  | TIM1_OCNIdleState_TypeDef | TIM1_OCNIdleState
 | ) |  |

Initializes the TIM1 Channel1 according to the specified parameters.

Parameters:
TIM1_OCMode | specifies the Output Compare mode from TIM1_OCMode_TypeDef.
TIM1_OutputState | specifies the Output State from TIM1_OutputState_TypeDef.
TIM1_OutputNState | specifies the Complementary Output State from TIM1_OutputNState_TypeDef.
TIM1_Pulse | specifies the Pulse width value.
TIM1_OCPolarity | specifies the Output Compare Polarity from TIM1_OCPolarity_TypeDef.
TIM1_OCNPolarity | specifies the Complementary Output Compare Polarity from TIM1_OCNPolarity_TypeDef.
TIM1_OCIdleState | specifies the Output Compare Idle State from TIM1_OCIdleState_TypeDef.
TIM1_OCNIdleState | specifies the Complementary Output Compare Idle State from TIM1_OCIdleState_TypeDef.
Return values:
None

Definition at line 154 of file stm8s_tim1.c.

References IS_TIM1_OC_MODE_OK, IS_TIM1_OC_POLARITY_OK, IS_TIM1_OCIDLE_STATE_OK, IS_TIM1_OCN_POLARITY_OK, IS_TIM1_OCNIDLE_STATE_OK, IS_TIM1_OUTPUT_STATE_OK, IS_TIM1_OUTPUTN_STATE_OK, TIM1, TIM1_CCER1_CC1E, TIM1_CCER1_CC1NE, TIM1_CCER1_CC1NP, TIM1_CCER1_CC1P, TIM1_CCMR_OCM, TIM1_OISR_OIS1, and TIM1_OISR_OIS1N.

void TIM1_OC1NPolarityConfig ( TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity )

Configures the TIM1 Channel 1N polarity.

Parameters:
TIM1_OCNPolarity specifies the OC1N Polarity. This parameter can be one of the following values:
  • TIM1_OCNPOLARITY_LOW: Output Compare active low
  • TIM1_OCNPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 1430 of file stm8s_tim1.c.

References IS_TIM1_OCN_POLARITY_OK, TIM1, TIM1_CCER1_CC1NP, and TIM1_OCNPOLARITY_HIGH.

void TIM1_OC1PolarityConfig ( TIM1_OCPolarity_TypeDef TIM1_OCPolarity )

Configures the TIM1 Channel 1 polarity.

Parameters:
TIM1_OCPolarity specifies the OC1 Polarity. This parameter can be one of the following values:
  • TIM1_OCPOLARITY_LOW: Output Compare active low
  • TIM1_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 1406 of file stm8s_tim1.c.

References IS_TIM1_OC_POLARITY_OK, TIM1, TIM1_CCER1_CC1P, and TIM1_OCPOLARITY_HIGH.

void TIM1_OC1PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM1 peripheral Preload Register on CCR1.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1205 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CCMR_OCxPE.

void TIM1_OC2FastConfig ( FunctionalState NewState )

Configures the TIM1 Capture Compare 2 Fast feature.

Parameters:
NewState new state of the Output Compare Fast Enable bit. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1315 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CCMR_OCxFE.

void TIM1_OC2Init | ( | TIM1_OCMode_TypeDef | TIM1_OCMode,
 |  | TIM1_OutputState_TypeDef | TIM1_OutputState,
 |  | TIM1_OutputNState_TypeDef | TIM1_OutputNState,
 |  | uint16_t | TIM1_Pulse,
 |  | TIM1_OCPolarity_TypeDef | TIM1_OCPolarity,
 |  | TIM1_OCNPolarity_TypeDef | TIM1_OCNPolarity,
 |  | TIM1_OCIdleState_TypeDef | TIM1_OCIdleState,
 |  | TIM1_OCNIdleState_TypeDef | TIM1_OCNIdleState
 | ) |  |

Initializes the TIM1 Channel2 according to the specified parameters.

Parameters:
TIM1_OCMode | specifies the Output Compare mode from TIM1_OCMode_TypeDef.
TIM1_OutputState | specifies the Output State from TIM1_OutputState_TypeDef.
TIM1_OutputNState | specifies the Complementary Output State from TIM1_OutputNState_TypeDef.
TIM1_Pulse | specifies the Pulse width value.
TIM1_OCPolarity | specifies the Output Compare Polarity from TIM1_OCPolarity_TypeDef.
TIM1_OCNPolarity | specifies the Complementary Output Compare Polarity from TIM1_OCNPolarity_TypeDef.
TIM1_OCIdleState | specifies the Output Compare Idle State from TIM1_OCIdleState_TypeDef.
TIM1_OCNIdleState | specifies the Complementary Output Compare Idle State from TIM1_OCIdleState_TypeDef.
Return values:
None

Definition at line 217 of file stm8s_tim1.c.

References IS_TIM1_OC_MODE_OK, IS_TIM1_OC_POLARITY_OK, IS_TIM1_OCIDLE_STATE_OK, IS_TIM1_OCN_POLARITY_OK, IS_TIM1_OCNIDLE_STATE_OK, IS_TIM1_OUTPUT_STATE_OK, IS_TIM1_OUTPUTN_STATE_OK, TIM1, TIM1_CCER1_CC2E, TIM1_CCER1_CC2NE, TIM1_CCER1_CC2NP, TIM1_CCER1_CC2P, TIM1_CCMR_OCM, TIM1_OISR_OIS2, and TIM1_OISR_OIS2N.

void TIM1_OC2NPolarityConfig ( TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity )

Configures the TIM1 Channel 2N polarity.

Parameters:
TIM1_OCNPolarity specifies the OC2N Polarity. This parameter can be one of the following values:
  • TIM1_OCNPOLARITY_LOW: Output Compare active low
  • TIM1_OCNPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 1478 of file stm8s_tim1.c.

References IS_TIM1_OCN_POLARITY_OK, TIM1, TIM1_CCER1_CC2NP, and TIM1_OCNPOLARITY_HIGH.

void TIM1_OC2PolarityConfig ( TIM1_OCPolarity_TypeDef TIM1_OCPolarity )

Configures the TIM1 Channel 2 polarity.

Parameters:
TIM1_OCPolarity specifies the OC2 Polarity. This parameter can be one of the following values:
  • TIM1_OCPOLARITY_LOW: Output Compare active low
  • TIM1_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 1454 of file stm8s_tim1.c.

References IS_TIM1_OC_POLARITY_OK, TIM1, TIM1_CCER1_CC2P, and TIM1_OCPOLARITY_HIGH.

void TIM1_OC2PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM1 peripheral Preload Register on CCR2.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1227 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CCMR_OCxPE.

void TIM1_OC3FastConfig ( FunctionalState NewState )

Configures the TIM1 Capture Compare 3 Fast feature.

Parameters:
NewState new state of the Output Compare Fast Enable bit. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1337 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CCMR_OCxFE.

void TIM1_OC3Init | ( | TIM1_OCMode_TypeDef | TIM1_OCMode,
 |  | TIM1_OutputState_TypeDef | TIM1_OutputState,
 |  | TIM1_OutputNState_TypeDef | TIM1_OutputNState,
 |  | uint16_t | TIM1_Pulse,
 |  | TIM1_OCPolarity_TypeDef | TIM1_OCPolarity,
 |  | TIM1_OCNPolarity_TypeDef | TIM1_OCNPolarity,
 |  | TIM1_OCIdleState_TypeDef | TIM1_OCIdleState,
 |  | TIM1_OCNIdleState_TypeDef | TIM1_OCNIdleState
 | ) |  |

Initializes the TIM1 Channel3 according to the specified parameters.

Parameters:
TIM1_OCMode | specifies the Output Compare mode from TIM1_OCMode_TypeDef.
TIM1_OutputState | specifies the Output State from TIM1_OutputState_TypeDef.
TIM1_OutputNState | specifies the Complementary Output State from TIM1_OutputNState_TypeDef.
TIM1_Pulse | specifies the Pulse width value.
TIM1_OCPolarity | specifies the Output Compare Polarity from TIM1_OCPolarity_TypeDef.
TIM1_OCNPolarity | specifies the Complementary Output Compare Polarity from TIM1_OCNPolarity_TypeDef.
TIM1_OCIdleState | specifies the Output Compare Idle State from TIM1_OCIdleState_TypeDef.
TIM1_OCNIdleState | specifies the Complementary Output Compare Idle State from TIM1_OCIdleState_TypeDef.
Return values:
None

Definition at line 281 of file stm8s_tim1.c.

References IS_TIM1_OC_MODE_OK, IS_TIM1_OC_POLARITY_OK, IS_TIM1_OCIDLE_STATE_OK, IS_TIM1_OCN_POLARITY_OK, IS_TIM1_OCNIDLE_STATE_OK, IS_TIM1_OUTPUT_STATE_OK, IS_TIM1_OUTPUTN_STATE_OK, TIM1, TIM1_CCER2_CC3E, TIM1_CCER2_CC3NE, TIM1_CCER2_CC3NP, TIM1_CCER2_CC3P, TIM1_CCMR_OCM, TIM1_OISR_OIS3, and TIM1_OISR_OIS3N.

void TIM1_OC3NPolarityConfig ( TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity )

Configures the TIM1 Channel 3N polarity.

Parameters:
TIM1_OCNPolarity specifies the OC3N Polarity. This parameter can be one of the following values:
  • TIM1_OCNPOLARITY_LOW: Output Compare active low
  • TIM1_OCNPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 1527 of file stm8s_tim1.c.

References IS_TIM1_OCN_POLARITY_OK, TIM1, TIM1_CCER2_CC3NP, and TIM1_OCNPOLARITY_HIGH.

void TIM1_OC3PolarityConfig ( TIM1_OCPolarity_TypeDef TIM1_OCPolarity )

Configures the TIM1 Channel 3 polarity.

Parameters:
TIM1_OCPolarity specifies the OC3 Polarity. This parameter can be one of the following values:
  • TIM1_OCPOLARITY_LOW: Output Compare active low
  • TIM1_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 1502 of file stm8s_tim1.c.

References IS_TIM1_OC_POLARITY_OK, TIM1, TIM1_CCER2_CC3P, and TIM1_OCPOLARITY_HIGH.

void TIM1_OC3PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM1 peripheral Preload Register on CCR3.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1249 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CCMR_OCxPE.

void TIM1_OC4FastConfig ( FunctionalState NewState )

Configures the TIM1 Capture Compare 4 Fast feature.

Parameters:
NewState new state of the Output Compare Fast Enable bit. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1359 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CCMR_OCxFE.

void TIM1_OC4Init | ( | TIM1_OCMode_TypeDef | TIM1_OCMode,
 |  | TIM1_OutputState_TypeDef | TIM1_OutputState,
 |  | uint16_t | TIM1_Pulse,
 |  | TIM1_OCPolarity_TypeDef | TIM1_OCPolarity,
 |  | TIM1_OCIdleState_TypeDef | TIM1_OCIdleState
 | ) |  |

Initializes the TIM1 Channel4 according to the specified parameters.

Parameters:
TIM1_OCMode | specifies the Output Compare mode from TIM1_OCMode_TypeDef.
TIM1_OutputState | specifies the Output State from TIM1_OutputState_TypeDef.
TIM1_Pulse | specifies the Pulse width value.
TIM1_OCPolarity | specifies the Output Compare Polarity from TIM1_OCPolarity_TypeDef.
TIM1_OCIdleState | specifies the Output Compare Idle State from TIM1_OCIdleState_TypeDef.
Return values:
None

Definition at line 338 of file stm8s_tim1.c.

References IS_TIM1_OC_MODE_OK, IS_TIM1_OC_POLARITY_OK, IS_TIM1_OCIDLE_STATE_OK, IS_TIM1_OUTPUT_STATE_OK, TIM1, TIM1_CCER2_CC4E, TIM1_CCER2_CC4P, TIM1_CCMR_OCM, TIM1_OCIDLESTATE_RESET, and TIM1_OISR_OIS4.

void TIM1_OC4PolarityConfig ( TIM1_OCPolarity_TypeDef TIM1_OCPolarity )

Configures the TIM1 Channel 4 polarity.

Parameters:
TIM1_OCPolarity specifies the OC4 Polarity. This parameter can be one of the following values:
  • TIM1_OCPOLARITY_LOW: Output Compare active low
  • TIM1_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 1551 of file stm8s_tim1.c.

References IS_TIM1_OC_POLARITY_OK, TIM1, TIM1_CCER2_CC4P, and TIM1_OCPOLARITY_HIGH.

void TIM1_OC4PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM1 peripheral Preload Register on CCR4.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1271 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CCMR_OCxPE.

void TIM1_PrescalerConfig | ( | uint16_t | Prescaler,
 |  | TIM1_PSCReloadMode_TypeDef | TIM1_PSCReloadMode
 | ) |  |

Configures the TIM1 Prescaler.

Parameters:
Prescaler specifies the Prescaler Register value This parameter must be a value between 0x0000 and 0xFFFF
TIM1_PSCReloadMode specifies the TIM1 Prescaler Reload mode. This parameter can be one of the following values
  • TIM1_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded immediately.
  • TIM1_PSCRELOADMODE_UPDATE: The Prescaler is loaded at the update event.
Return values:
None

Definition at line 1023 of file stm8s_tim1.c.

References IS_TIM1_PRESCALER_RELOAD_OK, and TIM1.

void TIM1_PWMIConfig | ( | TIM1_Channel_TypeDef | TIM1_Channel,
 |  | TIM1_ICPolarity_TypeDef | TIM1_ICPolarity,
 |  | TIM1_ICSelection_TypeDef | TIM1_ICSelection,
 |  | TIM1_ICPSC_TypeDef | TIM1_ICPrescaler,
 |  | uint8_t | TIM1_ICFilter
 | ) |  |

Configures the TIM1 peripheral in PWM Input Mode according to the specified parameters.

Parameters:
TIM1_Channel | specifies the input capture channel from TIM1_Channel_TypeDef.
TIM1_ICPolarity | specifies the Input capture polarity from TIM1_ICPolarity_TypeDef .
TIM1_ICSelection | specifies the Input capture source selection from TIM1_ICSelection_TypeDef.
TIM1_ICPrescaler | specifies the Input capture Prescaler from TIM1_ICPSC_TypeDef.
TIM1_ICFilter | specifies the Input capture filter value.
Return values:
None

Definition at line 488 of file stm8s_tim1.c.

References IS_TIM1_IC_POLARITY_OK, IS_TIM1_IC_PRESCALER_OK, IS_TIM1_IC_SELECTION_OK, IS_TIM1_PWMI_CHANNEL_OK, TI1_Config(), TI2_Config(), TIM1_CHANNEL_1, TIM1_ICPOLARITY_FALLING, TIM1_ICPOLARITY_RISING, TIM1_ICSELECTION_DIRECTTI, TIM1_ICSELECTION_INDIRECTTI, TIM1_SetIC1Prescaler(), and TIM1_SetIC2Prescaler().

void TIM1_SelectCOM ( FunctionalState NewState )

Selects the TIM1 peripheral Commutation event.

Parameters:
NewState new state of the Commutation event. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1161 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CR2_COMS.

void TIM1_SelectHallSensor ( FunctionalState NewState )

Enables or Disables the TIM1’s Hall sensor interface.

Parameters:
NewState new state of the TIM1 Hall sensor interface.This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 849 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CR2_TI1S.

void TIM1_SelectInputTrigger ( TIM1_TS_TypeDef TIM1_InputTriggerSource )

Selects the TIM1 Input Trigger source.

Parameters:
TIM1_InputTriggerSource specifies Input Trigger source. This parameter can be one of the following values:
  • TIM1_TS_TI1F_ED: TI1 Edge Detector
  • TIM1_TS_TI1FP1: Filtered Timer Input 1
  • TIM1_TS_TI2FP2: Filtered Timer Input 2
  • TIM1_TS_ETRF: External Trigger input
Return values:
None

Definition at line 787 of file stm8s_tim1.c.

References IS_TIM1_TRIGGER_SELECTION_OK, TIM1, and TIM1_SMCR_TS.

Referenced by TIM1_TIxExternalClockConfig().

void TIM1_SelectMasterSlaveMode ( FunctionalState NewState )

Sets or Resets the TIM1 Master/Slave Mode.

Parameters:
NewState new state of the synchronization between TIM1 and its slaves (through TRGO). This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 939 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_SMCR_MSM.

void TIM1_SelectOCxM | ( | TIM1_Channel_TypeDef | TIM1_Channel,
 |  | TIM1_OCMode_TypeDef | TIM1_OCMode
 | ) |  |

Selects the TIM1 Output Compare Mode.

This function disables the selected channel before changing the Output Compare Mode. User has to enable this channel using TIM1_CCxCmd and TIM1_CCxNCmd functions.

Parameters:
TIM1_Channel specifies the TIM1 Channel. This parameter can be one of the following values:
  • TIM1_CHANNEL_1: TIM1 Channel1
  • TIM1_CHANNEL_2: TIM1 Channel2
  • TIM1_CHANNEL_3: TIM1 Channel3
  • TIM1_CHANNEL_4: TIM1 Channel4
TIM1_OCMode specifies the TIM1 Output Compare Mode. This parameter can be one of the following values:
  • TIM1_OCMODE_TIMING
  • TIM1_OCMODE_ACTIVE
  • TIM1_OCMODE_TOGGLE
  • TIM1_OCMODE_PWM1
  • TIM1_OCMODE_PWM2
  • TIM1_FORCEDACTION_ACTIVE
  • TIM1_FORCEDACTION_INACTIVE
Return values:
None

Definition at line 1712 of file stm8s_tim1.c.

References IS_TIM1_CHANNEL_OK, IS_TIM1_OCM_OK, TIM1, TIM1_CCER1_CC1E, TIM1_CCER1_CC2E, TIM1_CCER2_CC3E, TIM1_CCER2_CC4E, TIM1_CCMR_OCM, TIM1_CHANNEL_1, TIM1_CHANNEL_2, and TIM1_CHANNEL_3.

void TIM1_SelectOnePulseMode ( TIM1_OPMode_TypeDef TIM1_OPMode )

Selects the TIM1’s One Pulse Mode.

Parameters:
TIM1_OPMode specifies the OPM Mode to be used. This parameter can be one of the following values
  • TIM1_OPMODE_SINGLE
  • TIM1_OPMODE_REPETITIVE
Return values:
None

Definition at line 873 of file stm8s_tim1.c.

References IS_TIM1_OPM_MODE_OK, TIM1, TIM1_CR1_OPM, and TIM1_OPMODE_REPETITIVE.

void TIM1_SelectOutputTrigger ( TIM1_TRGOSource_TypeDef TIM1_TRGOSource )

Selects the TIM1 Trigger Output Mode.

Parameters:
TIM1_TRGOSource specifies the Trigger Output source. This parameter can be one of the following values
  • TIM1_TRGOSOURCE_RESET
  • TIM1_TRGOSOURCE_ENABLE
  • TIM1_TRGOSOURCE_UPDATE
  • TIM1_TRGOSource_OC1
  • TIM1_TRGOSOURCE_OC1REF
  • TIM1_TRGOSOURCE_OC2REF
  • TIM1_TRGOSOURCE_OC3REF
Return values:
None

Definition at line 903 of file stm8s_tim1.c.

References IS_TIM1_TRGO_SOURCE_OK, TIM1, and TIM1_CR2_MMS.

void TIM1_SelectSlaveMode ( TIM1_SlaveMode_TypeDef TIM1_SlaveMode )

Selects the TIM1 Slave Mode.

Parameters:
TIM1_SlaveMode specifies the TIM1 Slave Mode. This parameter can be one of the following values
  • TIM1_SLAVEMODE_RESET
  • TIM1_SLAVEMODE_GATED
  • TIM1_SLAVEMODE_TRIGGER
  • TIM1_SLAVEMODE_EXTERNAL1
Return values:
None

Definition at line 923 of file stm8s_tim1.c.

References IS_TIM1_SLAVE_MODE_OK, TIM1, and TIM1_SMCR_SMS.

void TIM1_SetAutoreload ( uint16_t Autoreload )

Sets the TIM1 Autoreload Register value.

Parameters:
Autoreload specifies the Autoreload register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 1775 of file stm8s_tim1.c.

References TIM1.

void TIM1_SetCompare1 ( uint16_t Compare1 )

Sets the TIM1 Capture Compare1 Register value.

Parameters:
Compare1 specifies the Capture Compare1 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 1788 of file stm8s_tim1.c.

References TIM1.

void TIM1_SetCompare2 ( uint16_t Compare2 )

Sets the TIM1 Capture Compare2 Register value.

Parameters:
Compare2 specifies the Capture Compare2 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 1801 of file stm8s_tim1.c.

References TIM1.

void TIM1_SetCompare3 ( uint16_t Compare3 )

Sets the TIM1 Capture Compare3 Register value.

Parameters:
Compare3 specifies the Capture Compare3 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 1814 of file stm8s_tim1.c.

References TIM1.

void TIM1_SetCompare4 ( uint16_t Compare4 )

Sets the TIM1 Capture Compare4 Register value.

Parameters:
Compare4 specifies the Capture Compare4 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 1827 of file stm8s_tim1.c.

References TIM1.

void TIM1_SetCounter ( uint16_t Counter )

Sets the TIM1 Counter Register value.

Parameters:
Counter specifies the Counter register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 1762 of file stm8s_tim1.c.

References TIM1.

void TIM1_SetIC1Prescaler ( TIM1_ICPSC_TypeDef TIM1_IC1Prescaler )

Sets the TIM1 Input Capture 1 prescaler.

Parameters:
TIM1_IC1Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:
  • TIM1_ICPSC_DIV1: no prescaler
  • TIM1_ICPSC_DIV2: capture is done once every 2 events
  • TIM1_ICPSC_DIV4: capture is done once every 4 events
  • TIM1_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 1844 of file stm8s_tim1.c.

References IS_TIM1_IC_PRESCALER_OK, TIM1, and TIM1_CCMR_ICxPSC.

Referenced by TIM1_ICInit(), and TIM1_PWMIConfig().

void TIM1_SetIC2Prescaler ( TIM1_ICPSC_TypeDef TIM1_IC2Prescaler )

Sets the TIM1 Input Capture 2 prescaler.

Parameters:
TIM1_IC2Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:
  • TIM1_ICPSC_DIV1: no prescaler
  • TIM1_ICPSC_DIV2: capture is done once every 2 events
  • TIM1_ICPSC_DIV4: capture is done once every 4 events
  • TIM1_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 1864 of file stm8s_tim1.c.

References IS_TIM1_IC_PRESCALER_OK, TIM1, and TIM1_CCMR_ICxPSC.

Referenced by TIM1_ICInit(), and TIM1_PWMIConfig().

void TIM1_SetIC3Prescaler ( TIM1_ICPSC_TypeDef TIM1_IC3Prescaler )

Sets the TIM1 Input Capture 3 prescaler.

Parameters:
TIM1_IC3Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:
  • TIM1_ICPSC_DIV1: no prescaler
  • TIM1_ICPSC_DIV2: capture is done once every 2 events
  • TIM1_ICPSC_DIV4: capture is done once every 4 events
  • TIM1_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 1885 of file stm8s_tim1.c.

References IS_TIM1_IC_PRESCALER_OK, TIM1, and TIM1_CCMR_ICxPSC.

Referenced by TIM1_ICInit().

void TIM1_SetIC4Prescaler ( TIM1_ICPSC_TypeDef TIM1_IC4Prescaler )

Sets the TIM1 Input Capture 4 prescaler.

Parameters:
TIM1_IC4Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:
  • TIM1_ICPSC_DIV1: no prescaler
  • TIM1_ICPSC_DIV2: capture is done once every 2 events
  • TIM1_ICPSC_DIV4: capture is done once every 4 events
  • TIM1_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 1906 of file stm8s_tim1.c.

References IS_TIM1_IC_PRESCALER_OK, TIM1, and TIM1_CCMR_ICxPSC.

Referenced by TIM1_ICInit().

void TIM1_TimeBaseInit | ( | uint16_t | TIM1_Prescaler,
 |  | TIM1_CounterMode_TypeDef | TIM1_CounterMode,
 |  | uint16_t | TIM1_Period,
 |  | uint8_t | TIM1_RepetitionCounter
 | ) |  |

Initializes the TIM1 Time Base Unit according to the specified parameters.

Parameters:
TIM1_Prescaler | specifies the Prescaler value.
TIM1_CounterMode | specifies the counter mode from TIM1_CounterMode_TypeDef .
TIM1_Period | specifies the Period value.
TIM1_RepetitionCounter | specifies the Repetition counter value
Return values:
None

Definition at line 111 of file stm8s_tim1.c.

References IS_TIM1_COUNTER_MODE_OK, TIM1, TIM1_CR1_CMS, and TIM1_CR1_DIR.

void TIM1_TIxExternalClockConfig | ( | TIM1_TIxExternalCLK1Source_TypeDef | TIM1_TIxExternalCLKSource,
 |  | TIM1_ICPolarity_TypeDef | TIM1_ICPolarity,
 |  | uint8_t | ICFilter
 | ) |  |

Configures the TIM1 Trigger as External Clock.

Parameters:
TIM1_TIxExternalCLKSource specifies Trigger source. This parameter can be one of the following values:
  • TIM1_TIXEXTERNALCLK1SOURCE_TI1: TI1 Edge Detector
  • TIM1_TIXEXTERNALCLK1SOURCE_TI2: Filtered TIM1 Input 1
  • TIM1_TIXEXTERNALCLK1SOURCE_TI1ED: Filtered TIM1 Input 2
TIM1_ICPolarity specifies the TIx Polarity. This parameter can be:
  • TIM1_ICPOLARITY_RISING
  • TIM1_ICPOLARITY_FALLING
ICFilter specifies the filter value. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 751 of file stm8s_tim1.c.

References IS_TIM1_IC_FILTER_OK, IS_TIM1_IC_POLARITY_OK, IS_TIM1_TIXCLK_SOURCE_OK, TI1_Config(), TI2_Config(), TIM1, TIM1_ICSELECTION_DIRECTTI, TIM1_SelectInputTrigger(), TIM1_SLAVEMODE_EXTERNAL1, and TIM1_TIXEXTERNALCLK1SOURCE_TI2.

void TIM1_UpdateDisableConfig ( FunctionalState NewState )

Enables or Disables the TIM1 Update event.

Parameters:
NewState new state of the TIM1 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 803 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CR1_UDIS.

void TIM1_UpdateRequestConfig ( TIM1_UpdateSource_TypeDef TIM1_UpdateSource )

Selects the TIM1 Update Request Interrupt source.

Parameters:
TIM1_UpdateSource specifies the Update source. This parameter can be one of the following values
  • TIM1_UPDATESOURCE_REGULAR
  • TIM1_UPDATESOURCE_GLOBAL
Return values:
None

Definition at line 827 of file stm8s_tim1.c.

References IS_TIM1_UPDATE_SOURCE_OK, TIM1, TIM1_CR1_URS, and TIM1_UPDATESOURCE_GLOBAL.


STM8S/A Standard Peripherals Drivers: TIM3_Exported_Types

Defines | Enumerations
TIM3_Exported_Types
STM8S_StdPeriph_Driver

Defines

#define | IS_TIM3_CHANNEL_OK(CHANNEL)
#define | IS_TIM3_CLEAR_FLAG_OK(FLAG) ((((uint16_t)(FLAG) & 0xF9F8) == 0x0000) && ((uint16_t)(FLAG)!= 0x0000))
#define | IS_TIM3_EVENT_SOURCE_OK(SOURCE) (((SOURCE) != 0x00))
#define | IS_TIM3_FORCED_ACTION_OK(ACTION)
#define | IS_TIM3_GET_FLAG_OK(FLAG)
#define | IS_TIM3_GET_IT_OK(IT)
#define | IS_TIM3_IC_FILTER_OK(ICFILTER) ((ICFILTER) <= 0x0F)
TIM3 Input Capture Filer Value.
#define | IS_TIM3_IC_POLARITY_OK(POLARITY)
#define | IS_TIM3_IC_PRESCALER_OK(PRESCALER)
#define | IS_TIM3_IC_SELECTION_OK(SELECTION)
#define | IS_TIM3_IT_OK(IT) (((IT) != 0x00) && ((IT) <= 0x07))
#define | IS_TIM3_OC_MODE_OK(MODE)
#define | IS_TIM3_OC_POLARITY_OK(POLARITY)
#define | IS_TIM3_OCM_OK(MODE)
#define | IS_TIM3_OPM_MODE_OK(MODE)
#define | IS_TIM3_OUTPUT_STATE_OK(STATE)
#define | IS_TIM3_PRESCALER_OK(PRESCALER)
#define | IS_TIM3_PRESCALER_RELOAD_OK(RELOAD)
#define | IS_TIM3_PWMI_CHANNEL_OK(CHANNEL)
#define | IS_TIM3_UPDATE_SOURCE_OK(SOURCE)

Enumerations

enum | TIM3_Channel_TypeDef { TIM3_CHANNEL_1 = ((uint8_t)0x00), TIM3_CHANNEL_2 = ((uint8_t)0x01) }
TIM3 Channel. More...
enum | TIM3_EventSource_TypeDef { TIM3_EVENTSOURCE_UPDATE = ((uint8_t)0x01), TIM3_EVENTSOURCE_CC1 = ((uint8_t)0x02), TIM3_EVENTSOURCE_CC2 = ((uint8_t)0x04) }
TIM3 Event Source. More...
enum TIM3_FLAG_TypeDef {
TIM3_FLAG_UPDATE = ((uint16_t)0x0001), TIM3_FLAG_CC1 = ((uint16_t)0x0002), TIM3_FLAG_CC2 = ((uint16_t)0x0004), TIM3_FLAG_CC1OF = ((uint16_t)0x0200),
TIM3_FLAG_CC2OF = ((uint16_t)0x0400)
}
TIM3 Flags. More...
enum | TIM3_ForcedAction_TypeDef { TIM3_FORCEDACTION_ACTIVE = ((uint8_t)0x50), TIM3_FORCEDACTION_INACTIVE = ((uint8_t)0x40) }
TIM3 Forced Action. More...
enum | TIM3_ICPolarity_TypeDef { TIM3_ICPOLARITY_RISING = ((uint8_t)0x00), TIM3_ICPOLARITY_FALLING = ((uint8_t)0x44) }
TIM3 Input Capture Polarity. More...
enum | TIM3_ICPSC_TypeDef { TIM3_ICPSC_DIV1 = ((uint8_t)0x00), TIM3_ICPSC_DIV2 = ((uint8_t)0x04), TIM3_ICPSC_DIV4 = ((uint8_t)0x08), TIM3_ICPSC_DIV8 = ((uint8_t)0x0C) }
TIM3 Input Capture Prescaler. More...
enum | TIM3_ICSelection_TypeDef { TIM3_ICSELECTION_DIRECTTI = ((uint8_t)0x01), TIM3_ICSELECTION_INDIRECTTI = ((uint8_t)0x02), TIM3_ICSELECTION_TRGI = ((uint8_t)0x03) }
TIM3 Input Capture Selection. More...
enum | TIM3_IT_TypeDef { TIM3_IT_UPDATE = ((uint8_t)0x01), TIM3_IT_CC1 = ((uint8_t)0x02), TIM3_IT_CC2 = ((uint8_t)0x04) }
TIM3 interrupt sources. More...
enum TIM3_OCMode_TypeDef {
TIM3_OCMODE_TIMING = ((uint8_t)0x00), TIM3_OCMODE_ACTIVE = ((uint8_t)0x10), TIM3_OCMODE_INACTIVE = ((uint8_t)0x20), TIM3_OCMODE_TOGGLE = ((uint8_t)0x30),
TIM3_OCMODE_PWM1 = ((uint8_t)0x60), TIM3_OCMODE_PWM2 = ((uint8_t)0x70)
}
TIM3 Output Compare and PWM modes. More...
enum | TIM3_OCPolarity_TypeDef { TIM3_OCPOLARITY_HIGH = ((uint8_t)0x00), TIM3_OCPOLARITY_LOW = ((uint8_t)0x22) }
TIM3 Output Compare Polarity. More...
enum | TIM3_OPMode_TypeDef { TIM3_OPMODE_SINGLE = ((uint8_t)0x01), TIM3_OPMODE_REPETITIVE = ((uint8_t)0x00) }
TIM3 One Pulse Mode. More...
enum | TIM3_OutputState_TypeDef { TIM3_OUTPUTSTATE_DISABLE = ((uint8_t)0x00), TIM3_OUTPUTSTATE_ENABLE = ((uint8_t)0x11) }
TIM3 Output Compare states. More...
enum TIM3_Prescaler_TypeDef {
TIM3_PRESCALER_1 = ((uint8_t)0x00), TIM3_PRESCALER_2 = ((uint8_t)0x01), TIM3_PRESCALER_4 = ((uint8_t)0x02), TIM3_PRESCALER_8 = ((uint8_t)0x03),
TIM3_PRESCALER_16 = ((uint8_t)0x04), TIM3_PRESCALER_32 = ((uint8_t)0x05), TIM3_PRESCALER_64 = ((uint8_t)0x06), TIM3_PRESCALER_128 = ((uint8_t)0x07),
TIM3_PRESCALER_256 = ((uint8_t)0x08), TIM3_PRESCALER_512 = ((uint8_t)0x09), TIM3_PRESCALER_1024 = ((uint8_t)0x0A), TIM3_PRESCALER_2048 = ((uint8_t)0x0B),
TIM3_PRESCALER_4096 = ((uint8_t)0x0C), TIM3_PRESCALER_8192 = ((uint8_t)0x0D), TIM3_PRESCALER_16384 = ((uint8_t)0x0E), TIM3_PRESCALER_32768 = ((uint8_t)0x0F)
}
TIM3 Prescaler. More...
enum | TIM3_PSCReloadMode_TypeDef { TIM3_PSCRELOADMODE_UPDATE = ((uint8_t)0x00), TIM3_PSCRELOADMODE_IMMEDIATE = ((uint8_t)0x01) }
TIM3 Prescaler Reload Mode. More...
enum | TIM3_UpdateSource_TypeDef { TIM3_UPDATESOURCE_GLOBAL = ((uint8_t)0x00), TIM3_UPDATESOURCE_REGULAR = ((uint8_t)0x01) }
TIM3 Update Source. More...

Define Documentation

#define IS_TIM3_CHANNEL_OK ( CHANNEL )
Value:
(((CHANNEL) == TIM3_CHANNEL_1) || \
                                     ((CHANNEL) == TIM3_CHANNEL_2))

Definition at line 138 of file stm8s_tim3.h.

Referenced by TIM3_CCxCmd(), TIM3_ICInit(), and TIM3_SelectOCxM().

#define IS_TIM3_CLEAR_FLAG_OK ( FLAG ) ((((uint16_t)(FLAG) & 0xF9F8) == 0x0000) && ((uint16_t)(FLAG)!= 0x0000))

Definition at line 263 of file stm8s_tim3.h.

Referenced by TIM3_ClearFlag().

#define IS_TIM3_EVENT_SOURCE_OK ( SOURCE ) (((SOURCE) != 0x00))

Definition at line 235 of file stm8s_tim3.h.

Referenced by TIM3_GenerateEvent().

#define IS_TIM3_FORCED_ACTION_OK ( ACTION )
Value:
(((ACTION) == TIM3_FORCEDACTION_ACTIVE) || \
    ((ACTION) == TIM3_FORCEDACTION_INACTIVE))

Definition at line 52 of file stm8s_tim3.h.

Referenced by TIM3_ForcedOC1Config(), and TIM3_ForcedOC2Config().

#define IS_TIM3_GET_FLAG_OK ( FLAG )
Value:
(((FLAG) == TIM3_FLAG_UPDATE) || \
                                   ((FLAG) == TIM3_FLAG_CC1) || \
                                   ((FLAG) == TIM3_FLAG_CC2) || \
                                   ((FLAG) == TIM3_FLAG_CC1OF) || \
                                   ((FLAG) == TIM3_FLAG_CC2OF) )

Definition at line 257 of file stm8s_tim3.h.

Referenced by TIM3_GetFlagStatus().

#define IS_TIM3_GET_IT_OK ( IT )
Value:
(((IT) == TIM3_IT_UPDATE) || \
                               ((IT) == TIM3_IT_CC1) || \
                               ((IT) == TIM3_IT_CC2))

Definition at line 213 of file stm8s_tim3.h.

Referenced by TIM3_GetITStatus().

#define IS_TIM3_IC_FILTER_OK ( ICFILTER ) ((ICFILTER) <= 0x0F)

TIM3 Input Capture Filer Value.

Definition at line 201 of file stm8s_tim3.h.

Referenced by TIM3_ICInit().

#define IS_TIM3_IC_POLARITY_OK ( POLARITY )
Value:
(((POLARITY) == TIM3_ICPOLARITY_RISING) || \
    ((POLARITY) == TIM3_ICPOLARITY_FALLING))

Definition at line 171 of file stm8s_tim3.h.

Referenced by TIM3_ICInit(), and TIM3_PWMIConfig().

#define IS_TIM3_IC_PRESCALER_OK ( PRESCALER )
Value:
(((PRESCALER) == TIM3_ICPSC_DIV1) || \
    ((PRESCALER) == TIM3_ICPSC_DIV2) || \
    ((PRESCALER) == TIM3_ICPSC_DIV4) || \
    ((PRESCALER) == TIM3_ICPSC_DIV8))

Definition at line 195 of file stm8s_tim3.h.

Referenced by TIM3_ICInit(), TIM3_PWMIConfig(), TIM3_SetIC1Prescaler(), and TIM3_SetIC2Prescaler().

#define IS_TIM3_IC_SELECTION_OK ( SELECTION )
Value:
(((SELECTION) == TIM3_ICSELECTION_DIRECTTI) || \
    ((SELECTION) == TIM3_ICSELECTION_INDIRECTTI) || \
    ((SELECTION) == TIM3_ICSELECTION_TRGI))

Definition at line 182 of file stm8s_tim3.h.

Referenced by TIM3_ICInit(), and TIM3_PWMIConfig().

#define IS_TIM3_IT_OK ( IT ) (((IT) != 0x00) && ((IT) <= 0x07))

Definition at line 211 of file stm8s_tim3.h.

Referenced by TIM3_ClearITPendingBit(), and TIM3_ITConfig().

#define IS_TIM3_OC_MODE_OK ( MODE )
Value:
(((MODE) ==  TIM3_OCMODE_TIMING) || \
                                  ((MODE) == TIM3_OCMODE_ACTIVE) || \
                                  ((MODE) == TIM3_OCMODE_INACTIVE) || \
                                  ((MODE) == TIM3_OCMODE_TOGGLE)|| \
                                  ((MODE) == TIM3_OCMODE_PWM1) || \
                                  ((MODE) == TIM3_OCMODE_PWM2))

Definition at line 104 of file stm8s_tim3.h.

Referenced by TIM3_OC1Init(), and TIM3_OC2Init().

#define IS_TIM3_OC_POLARITY_OK ( POLARITY )
Value:
(((POLARITY) == TIM3_OCPOLARITY_HIGH) || \
    ((POLARITY) == TIM3_OCPOLARITY_LOW))

Definition at line 151 of file stm8s_tim3.h.

Referenced by TIM3_OC1Init(), TIM3_OC1PolarityConfig(), TIM3_OC2Init(), and TIM3_OC2PolarityConfig().

#define IS_TIM3_OCM_OK ( MODE )
Value:
(((MODE) ==  TIM3_OCMODE_TIMING) || \
                             ((MODE) == TIM3_OCMODE_ACTIVE) || \
                             ((MODE) == TIM3_OCMODE_INACTIVE) || \
                             ((MODE) == TIM3_OCMODE_TOGGLE)|| \
                             ((MODE) == TIM3_OCMODE_PWM1) || \
                             ((MODE) == TIM3_OCMODE_PWM2) || \
                             ((MODE) == (uint8_t)TIM3_FORCEDACTION_ACTIVE) || \
                             ((MODE) == (uint8_t)TIM3_FORCEDACTION_INACTIVE))

Definition at line 111 of file stm8s_tim3.h.

Referenced by TIM3_SelectOCxM().

#define IS_TIM3_OPM_MODE_OK ( MODE )
Value:
(((MODE) == TIM3_OPMODE_SINGLE) || \
                                   ((MODE) == TIM3_OPMODE_REPETITIVE))

Definition at line 127 of file stm8s_tim3.h.

Referenced by TIM3_SelectOnePulseMode().

#define IS_TIM3_OUTPUT_STATE_OK ( STATE )
Value:
(((STATE) == TIM3_OUTPUTSTATE_DISABLE) || \
                                        ((STATE) == TIM3_OUTPUTSTATE_ENABLE))

Definition at line 161 of file stm8s_tim3.h.

Referenced by TIM3_OC1Init(), and TIM3_OC2Init().

#define IS_TIM3_PRESCALER_OK ( PRESCALER )
Value:
(((PRESCALER) == TIM3_PRESCALER_1  ) || \
    ((PRESCALER) == TIM3_PRESCALER_2    ) || \
    ((PRESCALER) == TIM3_PRESCALER_4    ) || \
    ((PRESCALER) == TIM3_PRESCALER_8  ) || \
    ((PRESCALER) == TIM3_PRESCALER_16   ) || \
    ((PRESCALER) == TIM3_PRESCALER_32     ) || \
    ((PRESCALER) == TIM3_PRESCALER_64    ) || \
    ((PRESCALER) == TIM3_PRESCALER_128   ) || \
    ((PRESCALER) == TIM3_PRESCALER_256   ) || \
    ((PRESCALER) == TIM3_PRESCALER_512   ) || \
    ((PRESCALER) == TIM3_PRESCALER_1024  ) || \
    ((PRESCALER) == TIM3_PRESCALER_2048 ) || \
    ((PRESCALER) == TIM3_PRESCALER_4096 ) || \
    ((PRESCALER) == TIM3_PRESCALER_8192 ) || \
    ((PRESCALER) == TIM3_PRESCALER_16384 ) || \
    ((PRESCALER) == TIM3_PRESCALER_32768 ))

Definition at line 76 of file stm8s_tim3.h.

Referenced by TIM3_PrescalerConfig().

#define IS_TIM3_PRESCALER_RELOAD_OK ( RELOAD )
Value:
(((RELOAD) == TIM3_PSCRELOADMODE_UPDATE) || \
    ((RELOAD) == TIM3_PSCRELOADMODE_IMMEDIATE))

Definition at line 224 of file stm8s_tim3.h.

Referenced by TIM3_PrescalerConfig().

#define IS_TIM3_PWMI_CHANNEL_OK ( CHANNEL )
Value:
(((CHANNEL) == TIM3_CHANNEL_1) || \
    ((CHANNEL) == TIM3_CHANNEL_2))

Definition at line 141 of file stm8s_tim3.h.

Referenced by TIM3_PWMIConfig().

#define IS_TIM3_UPDATE_SOURCE_OK ( SOURCE )
Value:
(((SOURCE) == TIM3_UPDATESOURCE_GLOBAL) || \
    ((SOURCE) == TIM3_UPDATESOURCE_REGULAR))

Definition at line 244 of file stm8s_tim3.h.

Referenced by TIM3_UpdateRequestConfig().

Enumeration Type Documentation

enum TIM3_Channel_TypeDef

TIM3 Channel.

Enumerator:
TIM3_CHANNEL_1
TIM3_CHANNEL_2

Definition at line 132 of file stm8s_tim3.h.

enum TIM3_EventSource_TypeDef

TIM3 Event Source.

Enumerator:
TIM3_EVENTSOURCE_UPDATE
TIM3_EVENTSOURCE_CC1
TIM3_EVENTSOURCE_CC2

Definition at line 228 of file stm8s_tim3.h.

enum TIM3_FLAG_TypeDef

TIM3 Flags.

Enumerator:
TIM3_FLAG_UPDATE
TIM3_FLAG_CC1
TIM3_FLAG_CC2
TIM3_FLAG_CC1OF
TIM3_FLAG_CC2OF

Definition at line 248 of file stm8s_tim3.h.

enum TIM3_ForcedAction_TypeDef

TIM3 Forced Action.

Enumerator:
TIM3_FORCEDACTION_ACTIVE
TIM3_FORCEDACTION_INACTIVE

Definition at line 46 of file stm8s_tim3.h.

enum TIM3_ICPolarity_TypeDef

TIM3 Input Capture Polarity.

Enumerator:
TIM3_ICPOLARITY_RISING
TIM3_ICPOLARITY_FALLING

Definition at line 165 of file stm8s_tim3.h.

enum TIM3_ICPSC_TypeDef

TIM3 Input Capture Prescaler.

Enumerator:
TIM3_ICPSC_DIV1
TIM3_ICPSC_DIV2
TIM3_ICPSC_DIV4
TIM3_ICPSC_DIV8

Definition at line 187 of file stm8s_tim3.h.

enum TIM3_ICSelection_TypeDef

TIM3 Input Capture Selection.

Enumerator:
TIM3_ICSELECTION_DIRECTTI
TIM3_ICSELECTION_INDIRECTTI
TIM3_ICSELECTION_TRGI

Definition at line 175 of file stm8s_tim3.h.

enum TIM3_IT_TypeDef

TIM3 interrupt sources.

Enumerator:
TIM3_IT_UPDATE
TIM3_IT_CC1
TIM3_IT_CC2

Definition at line 204 of file stm8s_tim3.h.

enum TIM3_OCMode_TypeDef

TIM3 Output Compare and PWM modes.

Enumerator:
TIM3_OCMODE_TIMING
TIM3_OCMODE_ACTIVE
TIM3_OCMODE_INACTIVE
TIM3_OCMODE_TOGGLE
TIM3_OCMODE_PWM1
TIM3_OCMODE_PWM2

Definition at line 94 of file stm8s_tim3.h.

enum TIM3_OCPolarity_TypeDef

TIM3 Output Compare Polarity.

Enumerator:
TIM3_OCPOLARITY_HIGH
TIM3_OCPOLARITY_LOW

Definition at line 145 of file stm8s_tim3.h.

enum TIM3_OPMode_TypeDef

TIM3 One Pulse Mode.

Enumerator:
TIM3_OPMODE_SINGLE
TIM3_OPMODE_REPETITIVE

Definition at line 121 of file stm8s_tim3.h.

enum TIM3_OutputState_TypeDef

TIM3 Output Compare states.

Enumerator:
TIM3_OUTPUTSTATE_DISABLE
TIM3_OUTPUTSTATE_ENABLE

Definition at line 155 of file stm8s_tim3.h.

enum TIM3_Prescaler_TypeDef

TIM3 Prescaler.

Enumerator:
TIM3_PRESCALER_1
TIM3_PRESCALER_2
TIM3_PRESCALER_4
TIM3_PRESCALER_8
TIM3_PRESCALER_16
TIM3_PRESCALER_32
TIM3_PRESCALER_64
TIM3_PRESCALER_128
TIM3_PRESCALER_256
TIM3_PRESCALER_512
TIM3_PRESCALER_1024
TIM3_PRESCALER_2048
TIM3_PRESCALER_4096
TIM3_PRESCALER_8192
TIM3_PRESCALER_16384
TIM3_PRESCALER_32768

Definition at line 56 of file stm8s_tim3.h.

enum TIM3_PSCReloadMode_TypeDef

TIM3 Prescaler Reload Mode.

Enumerator:
TIM3_PSCRELOADMODE_UPDATE
TIM3_PSCRELOADMODE_IMMEDIATE

Definition at line 218 of file stm8s_tim3.h.

enum TIM3_UpdateSource_TypeDef

TIM3 Update Source.

Enumerator:
TIM3_UPDATESOURCE_GLOBAL
TIM3_UPDATESOURCE_REGULAR

Definition at line 238 of file stm8s_tim3.h.


STM8S/A Standard Peripherals Drivers: TIM3_Exported_Functions

Functions
TIM3_Exported_Functions
STM8S_StdPeriph_Driver

Functions

void | TIM3_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM3 peripheral Preload register on ARR.
void | TIM3_CCPreloadControl (FunctionalState NewState)
void | TIM3_CCxCmd (TIM3_Channel_TypeDef TIM3_Channel, FunctionalState NewState)
Enables or disables the TIM3 Capture Compare Channel x.
void | TIM3_ClearFlag (TIM3_FLAG_TypeDef TIM3_FLAG)
Clears the TIM3’s pending flags.
void | TIM3_ClearITPendingBit (TIM3_IT_TypeDef TIM3_IT)
Clears the TIM3's interrupt pending bits.
void | TIM3_Cmd (FunctionalState NewState)
Enables or disables the TIM3 peripheral.
void | TIM3_DeInit (void)
Deinitializes the TIM3 peripheral registers to their default reset values.
void | TIM3_ForcedOC1Config (TIM3_ForcedAction_TypeDef TIM3_ForcedAction)
Forces the TIM3 Channel1 output waveform to active or inactive level.
void | TIM3_ForcedOC2Config (TIM3_ForcedAction_TypeDef TIM3_ForcedAction)
Forces the TIM3 Channel2 output waveform to active or inactive level.
void | TIM3_GenerateEvent (TIM3_EventSource_TypeDef TIM3_EventSource)
Configures the TIM3 event to be generated by software.
uint16_t | TIM3_GetCapture1 (void)
Gets the TIM3 Input Capture 1 value.
uint16_t | TIM3_GetCapture2 (void)
Gets the TIM3 Input Capture 2 value.
uint16_t | TIM3_GetCounter (void)
Gets the TIM3 Counter value.
FlagStatus | TIM3_GetFlagStatus (TIM3_FLAG_TypeDef TIM3_FLAG)
Checks whether the specified TIM3 flag is set or not.
ITStatus | TIM3_GetITStatus (TIM3_IT_TypeDef TIM3_IT)
Checks whether the TIM3 interrupt has occurred or not.
TIM3_Prescaler_TypeDef | TIM3_GetPrescaler (void)
Gets the TIM3 Prescaler value.
void | TIM3_ICInit (TIM3_Channel_TypeDef TIM3_Channel, TIM3_ICPolarity_TypeDef TIM3_ICPolarity, TIM3_ICSelection_TypeDef TIM3_ICSelection, TIM3_ICPSC_TypeDef TIM3_ICPrescaler, uint8_t TIM3_ICFilter)
Initializes the TIM3 peripheral according to the specified parameters.
void | TIM3_InternalClockConfig (void)
void | TIM3_ITConfig (TIM3_IT_TypeDef TIM3_IT, FunctionalState NewState)
Enables or disables the specified TIM3 interrupts.
void | TIM3_OC1Init (TIM3_OCMode_TypeDef TIM3_OCMode, TIM3_OutputState_TypeDef TIM3_OutputState, uint16_t TIM3_Pulse, TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
Initializes the TIM3 Channel1 according to the specified parameters.
void | TIM3_OC1PolarityConfig (TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
Configures the TIM3 Channel 1 polarity.
void | TIM3_OC1PreloadConfig (FunctionalState NewState)
Enables or disables the TIM3 peripheral Preload Register on CCR1.
void | TIM3_OC2Init (TIM3_OCMode_TypeDef TIM3_OCMode, TIM3_OutputState_TypeDef TIM3_OutputState, uint16_t TIM3_Pulse, TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
Initializes the TIM3 Channel2 according to the specified parameters.
void | TIM3_OC2PolarityConfig (TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
Configures the TIM3 Channel 2 polarity.
void | TIM3_OC2PreloadConfig (FunctionalState NewState)
Enables or disables the TIM3 peripheral Preload Register on CCR2.
void | TIM3_PrescalerConfig (TIM3_Prescaler_TypeDef Prescaler, TIM3_PSCReloadMode_TypeDef TIM3_PSCReloadMode)
Configures the TIM3 Prescaler.
void | TIM3_PWMIConfig (TIM3_Channel_TypeDef TIM3_Channel, TIM3_ICPolarity_TypeDef TIM3_ICPolarity, TIM3_ICSelection_TypeDef TIM3_ICSelection, TIM3_ICPSC_TypeDef TIM3_ICPrescaler, uint8_t TIM3_ICFilter)
Configures the TIM3 peripheral in PWM Input Mode according to the specified parameters.
void | TIM3_SelectOCxM (TIM3_Channel_TypeDef TIM3_Channel, TIM3_OCMode_TypeDef TIM3_OCMode)
Selects the TIM3 Output Compare Mode.
void | TIM3_SelectOnePulseMode (TIM3_OPMode_TypeDef TIM3_OPMode)
Selects the TIM3’s One Pulse Mode.
void | TIM3_SetAutoreload (uint16_t Autoreload)
Sets the TIM3 Autoreload Register value.
void | TIM3_SetCompare1 (uint16_t Compare1)
Sets the TIM3 Capture Compare1 Register value.
void | TIM3_SetCompare2 (uint16_t Compare2)
Sets the TIM3 Capture Compare2 Register value.
void | TIM3_SetCounter (uint16_t Counter)
Sets the TIM3 Counter Register value.
void | TIM3_SetIC1Prescaler (TIM3_ICPSC_TypeDef TIM3_IC1Prescaler)
Sets the TIM3 Input Capture 1 prescaler.
void | TIM3_SetIC2Prescaler (TIM3_ICPSC_TypeDef TIM3_IC2Prescaler)
Sets the TIM3 Input Capture 2 prescaler.
void | TIM3_TimeBaseInit (TIM3_Prescaler_TypeDef TIM3_Prescaler, uint16_t TIM3_Period)
Initializes the TIM3 Time Base Unit according to the specified parameters.
void | TIM3_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM3 Update event.
void | TIM3_UpdateRequestConfig (TIM3_UpdateSource_TypeDef TIM3_UpdateSource)
Selects the TIM3 Update Request Interrupt source.

Function Documentation

void TIM3_ARRPreloadConfig ( FunctionalState NewState )

Enables or disables TIM3 peripheral Preload register on ARR.

Parameters:
NewState new state of the TIM3 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 483 of file stm8s_tim3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM3_CR1_ARPE.

void TIM3_CCPreloadControl ( FunctionalState NewState )
void TIM3_CCxCmd | ( | TIM3_Channel_TypeDef | TIM3_Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the TIM3 Capture Compare Channel x.

Parameters:
TIM3_Channel specifies the TIM3 Channel. This parameter can be one of the following values:
  • TIM3_CHANNEL_1: TIM3 Channel1
  • TIM3_CHANNEL_2: TIM3 Channel2
NewState specifies the TIM3 Channel CCxE bit new state. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 619 of file stm8s_tim3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, IS_TIM3_CHANNEL_OK, TIM3_CCER1_CC1E, TIM3_CCER1_CC2E, and TIM3_CHANNEL_1.

void TIM3_ClearFlag ( TIM3_FLAG_TypeDef TIM3_FLAG )

Clears the TIM3’s pending flags.

Parameters:
TIM3_FLAG specifies the flag to clear. This parameter can be one of the following values:
  • TIM3_FLAG_UPDATE: TIM3 update Flag
  • TIM3_FLAG_CC1: TIM3 Capture Compare 1 Flag
  • TIM3_FLAG_CC2: TIM3 Capture Compare 2 Flag
  • TIM3_FLAG_CC1OF: TIM3 Capture Compare 1 over capture Flag
  • TIM3_FLAG_CC2OF: TIM3 Capture Compare 2 over capture Flag
Return values:
None.

Definition at line 894 of file stm8s_tim3.c.

References IS_TIM3_CLEAR_FLAG_OK.

void TIM3_ClearITPendingBit ( TIM3_IT_TypeDef TIM3_IT )

Clears the TIM3's interrupt pending bits.

Parameters:
TIM3_IT specifies the pending bit to clear. This parameter can be one of the following values:
  • TIM3_IT_UPDATE: TIM3 update Interrupt source
  • TIM3_IT_CC1: TIM3 Capture Compare 1 Interrupt source
  • TIM3_IT_CC2: TIM3 Capture Compare 2 Interrupt source
Return values:
None.

Definition at line 945 of file stm8s_tim3.c.

References IS_TIM3_IT_OK.

void TIM3_Cmd ( FunctionalState NewState )

Enables or disables the TIM3 peripheral.

Parameters:
NewState new state of the TIM3 peripheral. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 283 of file stm8s_tim3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM3_CR1_CEN.

void TIM3_DeInit ( void )

Deinitializes the TIM3 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 51 of file stm8s_tim3.c.

References TIM3_ARRH_RESET_VALUE, TIM3_ARRL_RESET_VALUE, TIM3_CCER1_RESET_VALUE, TIM3_CCMR1_RESET_VALUE, TIM3_CCMR2_RESET_VALUE, TIM3_CCR1H_RESET_VALUE, TIM3_CCR1L_RESET_VALUE, TIM3_CCR2H_RESET_VALUE, TIM3_CCR2L_RESET_VALUE, TIM3_CNTRH_RESET_VALUE, TIM3_CNTRL_RESET_VALUE, TIM3_CR1_RESET_VALUE, TIM3_IER_RESET_VALUE, TIM3_PSCR_RESET_VALUE, TIM3_SR1_RESET_VALUE, and TIM3_SR2_RESET_VALUE.

void TIM3_ForcedOC1Config ( TIM3_ForcedAction_TypeDef TIM3_ForcedAction )

Forces the TIM3 Channel1 output waveform to active or inactive level.

Parameters:
TIM3_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:
  • TIM3_FORCEDACTION_ACTIVE: Force active level on OC1REF
  • TIM3_FORCEDACTION_INACTIVE: Force inactive level on OC1REF.
Return values:
None

Definition at line 450 of file stm8s_tim3.c.

References IS_TIM3_FORCED_ACTION_OK, and TIM3_CCMR_OCM.

void TIM3_ForcedOC2Config ( TIM3_ForcedAction_TypeDef TIM3_ForcedAction )

Forces the TIM3 Channel2 output waveform to active or inactive level.

Parameters:
TIM3_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:
  • TIM3_FORCEDACTION_ACTIVE: Force active level on OC2REF
  • TIM3_FORCEDACTION_INACTIVE: Force inactive level on OC2REF.
Return values:
None

Definition at line 468 of file stm8s_tim3.c.

References IS_TIM3_FORCED_ACTION_OK, and TIM3_CCMR_OCM.

void TIM3_GenerateEvent ( TIM3_EventSource_TypeDef TIM3_EventSource )

Configures the TIM3 event to be generated by software.

Parameters:
TIM3_EventSource specifies the event source. This parameter can be one of the following values:
  • TIM3_EVENTSOURCE_UPDATE: TIM3 update Event source
  • TIM3_EVENTSOURCE_CC1: TIM3 Capture Compare 1 Event source
  • TIM3_EVENTSOURCE_CC2: TIM3 Capture Compare 2 Event source
Return values:
None

Definition at line 552 of file stm8s_tim3.c.

References IS_TIM3_EVENT_SOURCE_OK.

uint16_t TIM3_GetCapture1 ( void )

Gets the TIM3 Input Capture 1 value.

Parameters:
None
Return values:
Capture Compare 1 Register value.

Definition at line 790 of file stm8s_tim3.c.

uint16_t TIM3_GetCapture2 ( void )

Gets the TIM3 Input Capture 2 value.

Parameters:
None
Return values:
Capture Compare 2 Register value.

Definition at line 810 of file stm8s_tim3.c.

uint16_t TIM3_GetCounter ( void )

Gets the TIM3 Counter value.

Parameters:
None
Return values:
Counter Register value.

Definition at line 830 of file stm8s_tim3.c.

FlagStatus TIM3_GetFlagStatus ( TIM3_FLAG_TypeDef TIM3_FLAG )

Checks whether the specified TIM3 flag is set or not.

Parameters:
TIM3_FLAG specifies the flag to check. This parameter can be one of the following values:
  • TIM3_FLAG_UPDATE: TIM3 update Flag
  • TIM3_FLAG_CC1: TIM3 Capture Compare 1 Flag
  • TIM3_FLAG_CC2: TIM3 Capture Compare 2 Flag
  • TIM3_FLAG_CC1OF: TIM3 Capture Compare 1 over capture Flag
  • TIM3_FLAG_CC2OF: TIM3 Capture Compare 2 over capture Flag
Return values:
FlagStatus The new state of TIM3_FLAG (SET or RESET).

Definition at line 861 of file stm8s_tim3.c.

References IS_TIM3_GET_FLAG_OK, RESET, and SET.

ITStatus TIM3_GetITStatus ( TIM3_IT_TypeDef TIM3_IT )

Checks whether the TIM3 interrupt has occurred or not.

Parameters:
TIM3_IT specifies the TIM3 interrupt source to check. This parameter can be one of the following values:
  • TIM3_IT_UPDATE: TIM3 update Interrupt source
  • TIM3_IT_CC1: TIM3 Capture Compare 1 Interrupt source
  • TIM3_IT_CC2: TIM3 Capture Compare 2 Interrupt source
Return values:
ITStatus The new state of the TIM3_IT(SET or RESET).

Definition at line 913 of file stm8s_tim3.c.

References IS_TIM3_GET_IT_OK, RESET, and SET.

TIM3_Prescaler_TypeDef TIM3_GetPrescaler ( void )

Gets the TIM3 Prescaler value.

Parameters:
None
Return values:
Prescaler Register configuration value TIM3_Prescaler_TypeDef.

Definition at line 844 of file stm8s_tim3.c.

void TIM3_ICInit | ( | TIM3_Channel_TypeDef | TIM3_Channel,
 |  | TIM3_ICPolarity_TypeDef | TIM3_ICPolarity,
 |  | TIM3_ICSelection_TypeDef | TIM3_ICSelection,
 |  | TIM3_ICPSC_TypeDef | TIM3_ICPrescaler,
 |  | uint8_t | TIM3_ICFilter
 | ) |  |

Initializes the TIM3 peripheral according to the specified parameters.

Parameters:
TIM3_Channel | specifies the Input Capture Channel from TIM3_Channel_TypeDef.
TIM3_ICPolarity | specifies the Input Capture Polarity from TIM3_ICPolarity_TypeDef.
TIM3_ICSelection | specifies the Input Capture Selection from TIM3_ICSelection_TypeDef.
TIM3_ICPrescaler | specifies the Input Capture Prescaler from TIM3_ICPSC_TypeDef.
TIM3_ICFilter | specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
Return values:
None

Definition at line 166 of file stm8s_tim3.c.

References IS_TIM3_CHANNEL_OK, IS_TIM3_IC_FILTER_OK, IS_TIM3_IC_POLARITY_OK, IS_TIM3_IC_PRESCALER_OK, IS_TIM3_IC_SELECTION_OK, TI1_Config(), TI2_Config(), TIM3_CHANNEL_2, TIM3_SetIC1Prescaler(), and TIM3_SetIC2Prescaler().

void TIM3_InternalClockConfig ( void )
void TIM3_ITConfig | ( | TIM3_IT_TypeDef | TIM3_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified TIM3 interrupts.

Parameters:
NewState | new state of the TIM3 peripheral. This parameter can be: ENABLE or DISABLE.
TIM3_IT specifies the TIM3 interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:
  • TIM3_IT_UPDATE: TIM3 update Interrupt source
  • TIM3_IT_CC1: TIM3 Capture Compare 1 Interrupt source
  • TIM3_IT_CC2: TIM3 Capture Compare 2 Interrupt source
  • TIM3_IT_CC3: TIM3 Capture Compare 3 Interrupt source
NewState | new state of the TIM3 peripheral. *
Return values:
None

Definition at line 311 of file stm8s_tim3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and IS_TIM3_IT_OK.

void TIM3_OC1Init | ( | TIM3_OCMode_TypeDef | TIM3_OCMode,
 |  | TIM3_OutputState_TypeDef | TIM3_OutputState,
 |  | uint16_t | TIM3_Pulse,
 |  | TIM3_OCPolarity_TypeDef | TIM3_OCPolarity
 | ) |  |

Initializes the TIM3 Channel1 according to the specified parameters.

Parameters:
TIM3_OCMode | specifies the Output Compare mode from TIM3_OCMode_TypeDef.
TIM3_OutputState | specifies the Output State from TIM3_OutputState_TypeDef.
TIM3_Pulse | specifies the Pulse width value.
TIM3_OCPolarity | specifies the Output Compare Polarity from TIM3_OCPolarity_TypeDef.
Return values:
None

Definition at line 100 of file stm8s_tim3.c.

References IS_TIM3_OC_MODE_OK, IS_TIM3_OC_POLARITY_OK, IS_TIM3_OUTPUT_STATE_OK, TIM3_CCER1_CC1E, TIM3_CCER1_CC1P, and TIM3_CCMR_OCM.

void TIM3_OC1PolarityConfig ( TIM3_OCPolarity_TypeDef TIM3_OCPolarity )

Configures the TIM3 Channel 1 polarity.

Parameters:
TIM3_OCPolarity specifies the OC1 Polarity. This parameter can be one of the following values:
  • TIM3_OCPOLARITY_LOW: Output Compare active low
  • TIM3_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 569 of file stm8s_tim3.c.

References IS_TIM3_OC_POLARITY_OK, TIM3_CCER1_CC1P, and TIM3_OCPOLARITY_HIGH.

void TIM3_OC1PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM3 peripheral Preload Register on CCR1.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 505 of file stm8s_tim3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM3_CCMR_OCxPE.

void TIM3_OC2Init | ( | TIM3_OCMode_TypeDef | TIM3_OCMode,
 |  | TIM3_OutputState_TypeDef | TIM3_OutputState,
 |  | uint16_t | TIM3_Pulse,
 |  | TIM3_OCPolarity_TypeDef | TIM3_OCPolarity
 | ) |  |

Initializes the TIM3 Channel2 according to the specified parameters.

Parameters:
TIM3_OCMode | specifies the Output Compare mode from TIM3_OCMode_TypeDef.
TIM3_OutputState | specifies the Output State from TIM3_OutputState_TypeDef.
TIM3_Pulse | specifies the Pulse width value.
TIM3_OCPolarity | specifies the Output Compare Polarity from TIM3_OCPolarity_TypeDef.
Return values:
None

Definition at line 131 of file stm8s_tim3.c.

References IS_TIM3_OC_MODE_OK, IS_TIM3_OC_POLARITY_OK, IS_TIM3_OUTPUT_STATE_OK, TIM3_CCER1_CC2E, TIM3_CCER1_CC2P, and TIM3_CCMR_OCM.

void TIM3_OC2PolarityConfig ( TIM3_OCPolarity_TypeDef TIM3_OCPolarity )

Configures the TIM3 Channel 2 polarity.

Parameters:
TIM3_OCPolarity specifies the OC2 Polarity. This parameter can be one of the following values:
  • TIM3_OCPOLARITY_LOW: Output Compare active low
  • TIM3_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 593 of file stm8s_tim3.c.

References IS_TIM3_OC_POLARITY_OK, TIM3_CCER1_CC2P, and TIM3_OCPOLARITY_HIGH.

void TIM3_OC2PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM3 peripheral Preload Register on CCR2.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 527 of file stm8s_tim3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM3_CCMR_OCxPE.

void TIM3_PrescalerConfig | ( | TIM3_Prescaler_TypeDef | Prescaler,
 |  | TIM3_PSCReloadMode_TypeDef | TIM3_PSCReloadMode
 | ) |  |

Configures the TIM3 Prescaler.

Parameters:
Prescaler specifies the Prescaler Register value This parameter can be one of the following values
  • TIM3_PRESCALER_1
  • TIM3_PRESCALER_2
  • TIM3_PRESCALER_4
  • TIM3_PRESCALER_8
  • TIM3_PRESCALER_16
  • TIM3_PRESCALER_32
  • TIM3_PRESCALER_64
  • TIM3_PRESCALER_128
  • TIM3_PRESCALER_256
  • TIM3_PRESCALER_512
  • TIM3_PRESCALER_1024
  • TIM3_PRESCALER_2048
  • TIM3_PRESCALER_4096
  • TIM3_PRESCALER_8192
  • TIM3_PRESCALER_16384
  • TIM3_PRESCALER_32768
TIM3_PSCReloadMode specifies the TIM3 Prescaler Reload mode. This parameter can be one of the following values
  • TIM3_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded immediately.
  • TIM3_PSCRELOADMODE_UPDATE: The Prescaler is loaded at the update event.
Return values:
None

Definition at line 427 of file stm8s_tim3.c.

References IS_TIM3_PRESCALER_OK, and IS_TIM3_PRESCALER_RELOAD_OK.

void TIM3_PWMIConfig | ( | TIM3_Channel_TypeDef | TIM3_Channel,
 |  | TIM3_ICPolarity_TypeDef | TIM3_ICPolarity,
 |  | TIM3_ICSelection_TypeDef | TIM3_ICSelection,
 |  | TIM3_ICPSC_TypeDef | TIM3_ICPrescaler,
 |  | uint8_t | TIM3_ICFilter
 | ) |  |

Configures the TIM3 peripheral in PWM Input Mode according to the specified parameters.

Parameters:
TIM3_Channel | specifies the Input Capture Channel from TIM3_Channel_TypeDef.
TIM3_ICPolarity | specifies the Input Capture Polarity from TIM3_ICPolarity_TypeDef.
TIM3_ICSelection | specifies the Input Capture Selection from TIM3_ICSelection_TypeDef.
TIM3_ICPrescaler | specifies the Input Capture Prescaler from TIM3_ICPSC_TypeDef.
TIM3_ICFilter | specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
Return values:
None

Definition at line 210 of file stm8s_tim3.c.

References IS_TIM3_IC_POLARITY_OK, IS_TIM3_IC_PRESCALER_OK, IS_TIM3_IC_SELECTION_OK, IS_TIM3_PWMI_CHANNEL_OK, TI1_Config(), TI2_Config(), TIM3_CHANNEL_2, TIM3_ICPOLARITY_FALLING, TIM3_ICPOLARITY_RISING, TIM3_ICSELECTION_DIRECTTI, TIM3_ICSELECTION_INDIRECTTI, TIM3_SetIC1Prescaler(), and TIM3_SetIC2Prescaler().

void TIM3_SelectOCxM | ( | TIM3_Channel_TypeDef | TIM3_Channel,
 |  | TIM3_OCMode_TypeDef | TIM3_OCMode
 | ) |  |

Selects the TIM3 Output Compare Mode.

This function disables the selected channel before changing the Output Compare Mode. User has to enable this channel using TIM3_CCxCmd and TIM3_CCxNCmd functions.

Parameters:
TIM3_Channel specifies the TIM3 Channel. This parameter can be one of the following values:
  • TIM3_CHANNEL_1: TIM3 Channel1
  • TIM3_CHANNEL_2: TIM3 Channel2
TIM3_OCMode specifies the TIM3 Output Compare Mode. This parameter can be one of the following values:
  • TIM3_OCMODE_TIMING
  • TIM3_OCMODE_ACTIVE
  • TIM3_OCMODE_TOGGLE
  • TIM3_OCMODE_PWM1
  • TIM3_OCMODE_PWM2
  • TIM3_FORCEDACTION_ACTIVE
  • TIM3_FORCEDACTION_INACTIVE
Return values:
None

Definition at line 671 of file stm8s_tim3.c.

References IS_TIM3_CHANNEL_OK, IS_TIM3_OCM_OK, TIM3_CCER1_CC1E, TIM3_CCER1_CC2E, TIM3_CCMR_OCM, and TIM3_CHANNEL_1.

void TIM3_SelectOnePulseMode ( TIM3_OPMode_TypeDef TIM3_OPMode )

Selects the TIM3’s One Pulse Mode.

Parameters:
TIM3_OPMode specifies the OPM Mode to be used. This parameter can be one of the following values
  • TIM3_OPMODE_SINGLE
  • TIM3_OPMODE_REPETITIVE
Return values:
None

Definition at line 383 of file stm8s_tim3.c.

References IS_TIM3_OPM_MODE_OK, TIM3_CR1_OPM, and TIM3_OPMODE_REPETITIVE.

void TIM3_SetAutoreload ( uint16_t Autoreload )

Sets the TIM3 Autoreload Register value.

Parameters:
Autoreload specifies the Autoreload register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 714 of file stm8s_tim3.c.

void TIM3_SetCompare1 ( uint16_t Compare1 )

Sets the TIM3 Capture Compare1 Register value.

Parameters:
Compare1 specifies the Capture Compare1 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 727 of file stm8s_tim3.c.

void TIM3_SetCompare2 ( uint16_t Compare2 )

Sets the TIM3 Capture Compare2 Register value.

Parameters:
Compare2 specifies the Capture Compare2 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 740 of file stm8s_tim3.c.

void TIM3_SetCounter ( uint16_t Counter )

Sets the TIM3 Counter Register value.

Parameters:
Counter specifies the Counter register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 701 of file stm8s_tim3.c.

void TIM3_SetIC1Prescaler ( TIM3_ICPSC_TypeDef TIM3_IC1Prescaler )

Sets the TIM3 Input Capture 1 prescaler.

Parameters:
TIM3_IC1Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:
  • TIM3_ICPSC_DIV1: no prescaler
  • TIM3_ICPSC_DIV2: capture is done once every 2 events
  • TIM3_ICPSC_DIV4: capture is done once every 4 events
  • TIM3_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 757 of file stm8s_tim3.c.

References IS_TIM3_IC_PRESCALER_OK, and TIM3_CCMR_ICxPSC.

Referenced by TIM3_ICInit(), and TIM3_PWMIConfig().

void TIM3_SetIC2Prescaler ( TIM3_ICPSC_TypeDef TIM3_IC2Prescaler )

Sets the TIM3 Input Capture 2 prescaler.

Parameters:
TIM3_IC2Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:
  • TIM3_ICPSC_DIV1: no prescaler
  • TIM3_ICPSC_DIV2: capture is done once every 2 events
  • TIM3_ICPSC_DIV4: capture is done once every 4 events
  • TIM3_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 776 of file stm8s_tim3.c.

References IS_TIM3_IC_PRESCALER_OK, and TIM3_CCMR_ICxPSC.

Referenced by TIM3_ICInit(), and TIM3_PWMIConfig().

void TIM3_TimeBaseInit | ( | TIM3_Prescaler_TypeDef | TIM3_Prescaler,
 |  | uint16_t | TIM3_Period
 | ) |  |

Initializes the TIM3 Time Base Unit according to the specified parameters.

Parameters:
TIM3_Prescaler | specifies the Prescaler from TIM3_Prescaler_TypeDef.
TIM3_Period | specifies the Period value.
Return values:
None

Definition at line 82 of file stm8s_tim3.c.

void TIM3_UpdateDisableConfig ( FunctionalState NewState )

Enables or Disables the TIM3 Update event.

Parameters:
NewState new state of the TIM3 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 335 of file stm8s_tim3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM3_CR1_UDIS.

void TIM3_UpdateRequestConfig ( TIM3_UpdateSource_TypeDef TIM3_UpdateSource )

Selects the TIM3 Update Request Interrupt source.

Parameters:
TIM3_UpdateSource specifies the Update source. This parameter can be one of the following values
  • TIM3_UPDATESOURCE_REGULAR
  • TIM3_UPDATESOURCE_GLOBAL
Return values:
None

Definition at line 359 of file stm8s_tim3.c.

References IS_TIM3_UPDATE_SOURCE_OK, TIM3_CR1_URS, and TIM3_UPDATESOURCE_GLOBAL.


STM8S/A Standard Peripherals Drivers: TIM4_Exported_Types

Defines | Enumerations
TIM4_Exported_Types
STM8S_StdPeriph_Driver

Defines

#define | IS_TIM4_EVENT_SOURCE_OK(SOURCE) (((SOURCE) == 0x01))
#define | IS_TIM4_GET_FLAG_OK(FLAG) ((FLAG) == TIM4_FLAG_UPDATE)
#define | IS_TIM4_IT_OK(IT) ((IT) == TIM4_IT_UPDATE)
#define | IS_TIM4_OPM_MODE_OK(MODE)
#define | IS_TIM4_PRESCALER_OK(PRESCALER)
#define | IS_TIM4_PRESCALER_RELOAD_OK(RELOAD)
#define | IS_TIM4_UPDATE_SOURCE_OK(SOURCE)

Enumerations

enum | TIM4_EventSource_TypeDef { TIM4_EVENTSOURCE_UPDATE = ((uint8_t)0x01) }
TIM4 Event Source. More...
enum | TIM4_FLAG_TypeDef { TIM4_FLAG_UPDATE = ((uint8_t)0x01) }
TIM4 Flags. More...
enum | TIM4_IT_TypeDef { TIM4_IT_UPDATE = ((uint8_t)0x01) }
TIM4 interrupt sources. More...
enum | TIM4_OPMode_TypeDef { TIM4_OPMODE_SINGLE = ((uint8_t)0x01), TIM4_OPMODE_REPETITIVE = ((uint8_t)0x00) }
TIM4 One Pulse Mode. More...
enum TIM4_Prescaler_TypeDef {
TIM4_PRESCALER_1 = ((uint8_t)0x00), TIM4_PRESCALER_2 = ((uint8_t)0x01), TIM4_PRESCALER_4 = ((uint8_t)0x02), TIM4_PRESCALER_8 = ((uint8_t)0x03),
TIM4_PRESCALER_16 = ((uint8_t)0x04), TIM4_PRESCALER_32 = ((uint8_t)0x05), TIM4_PRESCALER_64 = ((uint8_t)0x06), TIM4_PRESCALER_128 = ((uint8_t)0x07)
}
TIM4 Prescaler. More...
enum | TIM4_PSCReloadMode_TypeDef { TIM4_PSCRELOADMODE_UPDATE = ((uint8_t)0x00), TIM4_PSCRELOADMODE_IMMEDIATE = ((uint8_t)0x01) }
TIM4 Prescaler Reload Mode. More...
enum | TIM4_UpdateSource_TypeDef { TIM4_UPDATESOURCE_GLOBAL = ((uint8_t)0x00), TIM4_UPDATESOURCE_REGULAR = ((uint8_t)0x01) }
TIM4 Update Source. More...

Define Documentation

#define IS_TIM4_EVENT_SOURCE_OK ( SOURCE ) (((SOURCE) == 0x01))

Definition at line 105 of file stm8s_tim4.h.

Referenced by TIM4_GenerateEvent().

#define IS_TIM4_GET_FLAG_OK ( FLAG ) ((FLAG) == TIM4_FLAG_UPDATE)

Definition at line 113 of file stm8s_tim4.h.

Referenced by TIM4_ClearFlag(), and TIM4_GetFlagStatus().

#define IS_TIM4_IT_OK ( IT ) ((IT) == TIM4_IT_UPDATE)

Definition at line 123 of file stm8s_tim4.h.

Referenced by TIM4_ClearITPendingBit(), TIM4_GetITStatus(), and TIM4_ITConfig().

#define IS_TIM4_OPM_MODE_OK ( MODE )
Value:
(((MODE) == TIM4_OPMODE_SINGLE) || \
                                   ((MODE) == TIM4_OPMODE_REPETITIVE))

Definition at line 76 of file stm8s_tim4.h.

Referenced by TIM4_SelectOnePulseMode().

#define IS_TIM4_PRESCALER_OK ( PRESCALER )
Value:
(((PRESCALER) == TIM4_PRESCALER_1  ) || \
    ((PRESCALER) == TIM4_PRESCALER_2    ) || \
    ((PRESCALER) == TIM4_PRESCALER_4    ) || \
    ((PRESCALER) == TIM4_PRESCALER_8  ) || \
    ((PRESCALER) == TIM4_PRESCALER_16   ) || \
    ((PRESCALER) == TIM4_PRESCALER_32     ) || \
    ((PRESCALER) == TIM4_PRESCALER_64    ) || \
    ((PRESCALER) == TIM4_PRESCALER_128   ) )

Definition at line 60 of file stm8s_tim4.h.

Referenced by TIM4_PrescalerConfig(), and TIM4_TimeBaseInit().

#define IS_TIM4_PRESCALER_RELOAD_OK ( RELOAD )
Value:
(((RELOAD) == TIM4_PSCRELOADMODE_UPDATE) || \
    ((RELOAD) == TIM4_PSCRELOADMODE_IMMEDIATE))

Definition at line 86 of file stm8s_tim4.h.

Referenced by TIM4_PrescalerConfig().

#define IS_TIM4_UPDATE_SOURCE_OK ( SOURCE )
Value:
(((SOURCE) == TIM4_UPDATESOURCE_GLOBAL) || \
    ((SOURCE) == TIM4_UPDATESOURCE_REGULAR))

Definition at line 96 of file stm8s_tim4.h.

Referenced by TIM4_UpdateRequestConfig().

Enumeration Type Documentation

enum TIM4_EventSource_TypeDef

TIM4 Event Source.

Enumerator:
TIM4_EVENTSOURCE_UPDATE

Definition at line 100 of file stm8s_tim4.h.

enum TIM4_FLAG_TypeDef

TIM4 Flags.

Enumerator:
TIM4_FLAG_UPDATE

Definition at line 108 of file stm8s_tim4.h.

enum TIM4_IT_TypeDef

TIM4 interrupt sources.

Enumerator:
TIM4_IT_UPDATE

Definition at line 118 of file stm8s_tim4.h.

enum TIM4_OPMode_TypeDef

TIM4 One Pulse Mode.

Enumerator:
TIM4_OPMODE_SINGLE
TIM4_OPMODE_REPETITIVE

Definition at line 70 of file stm8s_tim4.h.

enum TIM4_Prescaler_TypeDef

TIM4 Prescaler.

Enumerator:
TIM4_PRESCALER_1
TIM4_PRESCALER_2
TIM4_PRESCALER_4
TIM4_PRESCALER_8
TIM4_PRESCALER_16
TIM4_PRESCALER_32
TIM4_PRESCALER_64
TIM4_PRESCALER_128

Definition at line 48 of file stm8s_tim4.h.

enum TIM4_PSCReloadMode_TypeDef

TIM4 Prescaler Reload Mode.

Enumerator:
TIM4_PSCRELOADMODE_UPDATE
TIM4_PSCRELOADMODE_IMMEDIATE

Definition at line 80 of file stm8s_tim4.h.

enum TIM4_UpdateSource_TypeDef

TIM4 Update Source.

Enumerator:
TIM4_UPDATESOURCE_GLOBAL
TIM4_UPDATESOURCE_REGULAR

Definition at line 90 of file stm8s_tim4.h.


STM8S/A Standard Peripherals Drivers: TIM4_Exported_Functions

Functions
TIM4_Exported_Functions
STM8S_StdPeriph_Driver

Functions

void | TIM4_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM4 peripheral Preload register on ARR.
void | TIM4_ClearFlag (TIM4_FLAG_TypeDef TIM4_FLAG)
Clears the TIM4’s pending flags.
void | TIM4_ClearITPendingBit (TIM4_IT_TypeDef TIM4_IT)
Clears the TIM4's interrupt pending bits.
void | TIM4_Cmd (FunctionalState NewState)
Enables or disables the TIM4 peripheral.
void | TIM4_DeInit (void)
Deinitializes the TIM4 peripheral registers to their default reset values.
void | TIM4_GenerateEvent (TIM4_EventSource_TypeDef TIM4_EventSource)
Configures the TIM4 event to be generated by software.
uint8_t | TIM4_GetCounter (void)
Gets the TIM4 Counter value.
FlagStatus | TIM4_GetFlagStatus (TIM4_FLAG_TypeDef TIM4_FLAG)
Checks whether the specified TIM4 flag is set or not.
ITStatus | TIM4_GetITStatus (TIM4_IT_TypeDef TIM4_IT)
Checks whether the TIM4 interrupt has occurred or not.
TIM4_Prescaler_TypeDef | TIM4_GetPrescaler (void)
Gets the TIM4 Prescaler value.
void | TIM4_ITConfig (TIM4_IT_TypeDef TIM4_IT, FunctionalState NewState)
Enables or disables the specified TIM4 interrupts.
void | TIM4_PrescalerConfig (TIM4_Prescaler_TypeDef Prescaler, TIM4_PSCReloadMode_TypeDef TIM4_PSCReloadMode)
Configures the TIM4 Prescaler.
void | TIM4_SelectOnePulseMode (TIM4_OPMode_TypeDef TIM4_OPMode)
Selects the TIM4’s One Pulse Mode.
void | TIM4_SetAutoreload (uint8_t Autoreload)
Sets the TIM4 Autoreload Register value.
void | TIM4_SetCounter (uint8_t Counter)
Sets the TIM4 Counter Register value.
void | TIM4_TimeBaseInit (TIM4_Prescaler_TypeDef TIM4_Prescaler, uint8_t TIM4_Period)
Initializes the TIM4 Time Base Unit according to the specified parameters.
void | TIM4_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM4 Update event.
void | TIM4_UpdateRequestConfig (TIM4_UpdateSource_TypeDef TIM4_UpdateSource)
Selects the TIM4 Update Request Interrupt source.

Function Documentation

void TIM4_ARRPreloadConfig ( FunctionalState NewState )

Enables or disables TIM4 peripheral Preload register on ARR.

Parameters:
NewState new state of the TIM4 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 234 of file stm8s_tim4.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM4_CR1_ARPE.

void TIM4_ClearFlag ( TIM4_FLAG_TypeDef TIM4_FLAG )

Clears the TIM4’s pending flags.

Parameters:
TIM4_FLAG specifies the flag to clear. This parameter can be one of the following values:
  • TIM4_FLAG_UPDATE: TIM4 update Flag
Return values:
None.

Definition at line 344 of file stm8s_tim4.c.

References IS_TIM4_GET_FLAG_OK.

void TIM4_ClearITPendingBit ( TIM4_IT_TypeDef TIM4_IT )

Clears the TIM4's interrupt pending bits.

Parameters:
TIM4_IT specifies the pending bit to clear. This parameter can be one of the following values:
  • TIM4_IT_UPDATE: TIM4 update Interrupt source
Return values:
None.

Definition at line 391 of file stm8s_tim4.c.

References IS_TIM4_IT_OK.

void TIM4_Cmd ( FunctionalState NewState )

Enables or disables the TIM4 peripheral.

Parameters:
NewState new state of the TIM4 peripheral. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 81 of file stm8s_tim4.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM4_CR1_CEN.

void TIM4_DeInit ( void )

Deinitializes the TIM4 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 49 of file stm8s_tim4.c.

References TIM4_ARR_RESET_VALUE, TIM4_CNTR_RESET_VALUE, TIM4_CR1_RESET_VALUE, TIM4_IER_RESET_VALUE, TIM4_PSCR_RESET_VALUE, and TIM4_SR1_RESET_VALUE.

void TIM4_GenerateEvent ( TIM4_EventSource_TypeDef TIM4_EventSource )

Configures the TIM4 event to be generated by software.

Parameters:
TIM4_EventSource specifies the event source. This parameter can be one of the following values:
  • TIM4_EVENTSOURCE_UPDATE: TIM4 update Event source
Return values:
None

Definition at line 257 of file stm8s_tim4.c.

References IS_TIM4_EVENT_SOURCE_OK.

uint8_t TIM4_GetCounter ( void )

Gets the TIM4 Counter value.

Parameters:
None
Return values:
Counter Register value.

Definition at line 295 of file stm8s_tim4.c.

FlagStatus TIM4_GetFlagStatus ( TIM4_FLAG_TypeDef TIM4_FLAG )

Checks whether the specified TIM4 flag is set or not.

Parameters:
TIM4_FLAG specifies the flag to check. This parameter can be one of the following values:
  • TIM4_FLAG_UPDATE: TIM4 update Flag
Return values:
FlagStatus The new state of TIM4_FLAG (SET or RESET).

Definition at line 319 of file stm8s_tim4.c.

References IS_TIM4_GET_FLAG_OK, RESET, and SET.

ITStatus TIM4_GetITStatus ( TIM4_IT_TypeDef TIM4_IT )

Checks whether the TIM4 interrupt has occurred or not.

Parameters:
TIM4_IT specifies the TIM4 interrupt source to check. This parameter can be one of the following values:
  • TIM4_IT_UPDATE: TIM4 update Interrupt source
Return values:
ITStatus The new state of the TIM4_IT (SET or RESET).

Definition at line 360 of file stm8s_tim4.c.

References IS_TIM4_IT_OK, RESET, and SET.

TIM4_Prescaler_TypeDef TIM4_GetPrescaler ( void )

Gets the TIM4 Prescaler value.

Parameters:
None
Return values:
Prescaler Register configuration value.

Definition at line 306 of file stm8s_tim4.c.

void TIM4_ITConfig | ( | TIM4_IT_TypeDef | TIM4_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified TIM4 interrupts.

Parameters:
NewState | new state of the TIM4 peripheral. This parameter can be: ENABLE or DISABLE.
TIM4_IT specifies the TIM4 interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:
  • TIM4_IT_UPDATE: TIM4 update Interrupt source
NewState | new state of the TIM4 peripheral.
Return values:
None

Definition at line 107 of file stm8s_tim4.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and IS_TIM4_IT_OK.

void TIM4_PrescalerConfig | ( | TIM4_Prescaler_TypeDef | Prescaler,
 |  | TIM4_PSCReloadMode_TypeDef | TIM4_PSCReloadMode
 | ) |  |

Configures the TIM4 Prescaler.

Parameters:
Prescaler specifies the Prescaler Register value This parameter can be one of the following values
  • TIM4_PRESCALER_1
  • TIM4_PRESCALER_2
  • TIM4_PRESCALER_4
  • TIM4_PRESCALER_8
  • TIM4_PRESCALER_16
  • TIM4_PRESCALER_32
  • TIM4_PRESCALER_64
  • TIM4_PRESCALER_128
TIM4_PSCReloadMode specifies the TIM4 Prescaler Reload mode. This parameter can be one of the following values
  • TIM4_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded immediately.
  • TIM4_PSCRELOADMODE_UPDATE: The Prescaler is loaded at the update event.
Return values:
None

Definition at line 215 of file stm8s_tim4.c.

References IS_TIM4_PRESCALER_OK, and IS_TIM4_PRESCALER_RELOAD_OK.

void TIM4_SelectOnePulseMode ( TIM4_OPMode_TypeDef TIM4_OPMode )

Selects the TIM4’s One Pulse Mode.

Parameters:
TIM4_OPMode specifies the OPM Mode to be used. This parameter can be one of the following values
  • TIM4_OPMODE_SINGLE
  • TIM4_OPMODE_REPETITIVE
Return values:
None

Definition at line 179 of file stm8s_tim4.c.

References IS_TIM4_OPM_MODE_OK, TIM4_CR1_OPM, and TIM4_OPMODE_REPETITIVE.

void TIM4_SetAutoreload ( uint8_t Autoreload )

Sets the TIM4 Autoreload Register value.

Parameters:
Autoreload specifies the Autoreload register new value. This parameter is between 0x00 and 0xFF.
Return values:
None

Definition at line 284 of file stm8s_tim4.c.

void TIM4_SetCounter ( uint8_t Counter )

Sets the TIM4 Counter Register value.

Parameters:
Counter specifies the Counter register new value. This parameter is between 0x00 and 0xFF.
Return values:
None

Definition at line 272 of file stm8s_tim4.c.

void TIM4_TimeBaseInit | ( | TIM4_Prescaler_TypeDef | TIM4_Prescaler,
 |  | uint8_t | TIM4_Period
 | ) |  |

Initializes the TIM4 Time Base Unit according to the specified parameters.

Parameters:
TIM4_Prescaler | specifies the Prescaler from TIM4_Prescaler_TypeDef.
TIM4_Period | specifies the Period value.
Return values:
None

Definition at line 65 of file stm8s_tim4.c.

References IS_TIM4_PRESCALER_OK.

void TIM4_UpdateDisableConfig ( FunctionalState NewState )

Enables or Disables the TIM4 Update event.

Parameters:
NewState new state of the TIM4 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 131 of file stm8s_tim4.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM4_CR1_UDIS.

void TIM4_UpdateRequestConfig ( TIM4_UpdateSource_TypeDef TIM4_UpdateSource )

Selects the TIM4 Update Request Interrupt source.

Parameters:
TIM4_UpdateSource specifies the Update source. This parameter can be one of the following values
  • TIM4_UPDATESOURCE_REGULAR
  • TIM4_UPDATESOURCE_GLOBAL
Return values:
None

Definition at line 155 of file stm8s_tim4.c.

References IS_TIM4_UPDATE_SOURCE_OK, TIM4_CR1_URS, and TIM4_UPDATESOURCE_GLOBAL.


STM8S/A Standard Peripherals Drivers: TIM6_Exported_Types

Enumerations
TIM6_Exported_Types
STM8S_StdPeriph_Driver

Enumerations

enum | TIM6_EventSource_TypeDef { TIM6_EVENTSOURCE_UPDATE = ((uint8_t)0x01), TIM6_EVENTSOURCE_TRIGGER = ((uint8_t)0x40) }
TIM6 Event Source. More...
enum | TIM6_FLAG_TypeDef { TIM6_FLAG_UPDATE = ((uint8_t)0x01), TIM6_FLAG_TRIGGER = ((uint8_t)0x40) }
TIM6 Flags. More...
enum | TIM6_IT_TypeDef { TIM6_IT_UPDATE = ((uint8_t)0x01), TIM6_IT_TRIGGER = ((uint8_t)0x40) }
TIM6 interrupt sources. More...
enum | TIM6_OPMode_TypeDef { TIM6_OPMODE_SINGLE = ((uint8_t)0x01), TIM6_OPMODE_REPETITIVE = ((uint8_t)0x00) }
TIM6 One Pulse Mode. More...
enum TIM6_Prescaler_TypeDef {
TIM6_PRESCALER_1 = ((uint8_t)0x00), TIM6_PRESCALER_2 = ((uint8_t)0x01), TIM6_PRESCALER_4 = ((uint8_t)0x02), TIM6_PRESCALER_8 = ((uint8_t)0x03),
TIM6_PRESCALER_16 = ((uint8_t)0x04), TIM6_PRESCALER_32 = ((uint8_t)0x05), TIM6_PRESCALER_64 = ((uint8_t)0x06), TIM6_PRESCALER_128 = ((uint8_t)0x07)
}
TIM6 Prescaler. More...
enum | TIM6_PSCReloadMode_TypeDef { TIM6_PSCRELOADMODE_UPDATE = ((uint8_t)0x00), TIM6_PSCRELOADMODE_IMMEDIATE = ((uint8_t)0x01) }
TIM6 Prescaler Reload Mode. More...
enum TIM6_SlaveMode_TypeDef {
TIM6_SLAVEMODE_DISABLE = ((uint8_t)0x00), TIM6_SLAVEMODE_RESET = ((uint8_t)0x04), TIM6_SLAVEMODE_GATED = ((uint8_t)0x05), TIM6_SLAVEMODE_TRIGGER = ((uint8_t)0x06),
TIM6_SLAVEMODE_EXTERNAL1 = ((uint8_t)0x07)
}
TIM6 Slave Mode. More...
enum | TIM6_TRGOSource_TypeDef { TIM6_TRGOSOURCE_RESET = ((uint8_t)0x00), TIM6_TRGOSOURCE_ENABLE = ((uint8_t)0x10), TIM6_TRGOSOURCE_UPDATE = ((uint8_t)0x20) }
TIM6 Trigger Output Source. More...
enum | TIM6_TS_TypeDef { TIM6_TS_TIM1 = ((uint8_t)0x20), TIM6_TS_TIM5 = ((uint8_t)0x30) }
TIM6 Internal Trigger Selection. More...
enum | TIM6_UpdateSource_TypeDef { TIM6_UPDATESOURCE_GLOBAL = ((uint8_t)0x00), TIM6_UPDATESOURCE_REGULAR = ((uint8_t)0x01) }
TIM6 Update Source. More...

Enumeration Type Documentation

enum TIM6_EventSource_TypeDef

TIM6 Event Source.

Enumerator:
TIM6_EVENTSOURCE_UPDATE

Update Event

TIM6_EVENTSOURCE_TRIGGER

Trigger Event

Definition at line 92 of file stm8s_tim6.h.

enum TIM6_FLAG_TypeDef

TIM6 Flags.

Enumerator:
TIM6_FLAG_UPDATE

Update Flag

TIM6_FLAG_TRIGGER

Trigger Flag

Definition at line 123 of file stm8s_tim6.h.

enum TIM6_IT_TypeDef

TIM6 interrupt sources.

Enumerator:
TIM6_IT_UPDATE

Update Interrupt

TIM6_IT_TRIGGER

Trigger Interrupt

Definition at line 132 of file stm8s_tim6.h.

enum TIM6_OPMode_TypeDef

TIM6 One Pulse Mode.

Enumerator:
TIM6_OPMODE_SINGLE

Single one Pulse mode (OPM Active)

TIM6_OPMODE_REPETITIVE

Repetitive Pulse mode (OPM inactive)

Definition at line 65 of file stm8s_tim6.h.

enum TIM6_Prescaler_TypeDef

TIM6 Prescaler.

Enumerator:
TIM6_PRESCALER_1

Time base Prescaler = 1 (No effect)

TIM6_PRESCALER_2

Time base Prescaler = 2

TIM6_PRESCALER_4

Time base Prescaler = 4

TIM6_PRESCALER_8

Time base Prescaler = 8

TIM6_PRESCALER_16

Time base Prescaler = 16

TIM6_PRESCALER_32

Time base Prescaler = 32

TIM6_PRESCALER_64

Time base Prescaler = 64

TIM6_PRESCALER_128

Time base Prescaler = 128

Definition at line 50 of file stm8s_tim6.h.

enum TIM6_PSCReloadMode_TypeDef

TIM6 Prescaler Reload Mode.

Enumerator:
TIM6_PSCRELOADMODE_UPDATE

Prescaler value is reloaded at every update

TIM6_PSCRELOADMODE_IMMEDIATE

Prescaler value is reloaded immediately

Definition at line 74 of file stm8s_tim6.h.

enum TIM6_SlaveMode_TypeDef

TIM6 Slave Mode.

Enumerator:
TIM6_SLAVEMODE_DISABLE

Disable slave mode to clock the prescaler directly with the internal clock

TIM6_SLAVEMODE_RESET

Slave Mode Selection = Reset

TIM6_SLAVEMODE_GATED

Slave Mode Selection = Gated

TIM6_SLAVEMODE_TRIGGER

Slave Mode Selection = Trigger

TIM6_SLAVEMODE_EXTERNAL1

Slave Mode Selection = External 1

Definition at line 111 of file stm8s_tim6.h.

enum TIM6_TRGOSource_TypeDef

TIM6 Trigger Output Source.

Enumerator:
TIM6_TRGOSOURCE_RESET

Trigger Output source = Reset

TIM6_TRGOSOURCE_ENABLE

Trigger Output source = TIM5 is enabled

TIM6_TRGOSOURCE_UPDATE

Trigger Output source = Update event

Definition at line 101 of file stm8s_tim6.h.

enum TIM6_TS_TypeDef

TIM6 Internal Trigger Selection.

Enumerator:
TIM6_TS_TIM1

TRIG Input source = TIM1 TRIG Output

TIM6_TS_TIM5

TRIG Input source = TIM5 TRIG Output

Definition at line 141 of file stm8s_tim6.h.

enum TIM6_UpdateSource_TypeDef

TIM6 Update Source.

Enumerator:
TIM6_UPDATESOURCE_GLOBAL

Global Update request source

TIM6_UPDATESOURCE_REGULAR

Regular Update request source

Definition at line 83 of file stm8s_tim6.h.


STM8S/A Standard Peripherals Drivers: TIM6_Private_Macros

Defines
TIM6_Private_Macros
STM8S_StdPeriph_Driver

Defines

#define | IS_TIM6_CLEAR_FLAG_OK(FLAG) ((((FLAG) & (uint8_t)0xBE) == 0x00) && ((FLAG) != 0x00))
#define | IS_TIM6_EVENT_SOURCE_OK(SOURCE)
Macro TIM6 Event source.
#define | IS_TIM6_GET_FLAG_OK(FLAG)
Macro TIM6 Flags.
#define | IS_TIM6_GET_IT_OK(IT)
#define | IS_TIM6_IT_OK(IT)
Macro TIM6 interrupts.
#define | IS_TIM6_OPM_MODE_OK(MODE)
Macro TIM6 One Pulse Mode.
#define | IS_TIM6_PRESCALER_OK(PRESCALER)
Macro used by the assert function to check the different functions parameters.
#define | IS_TIM6_PRESCALER_RELOAD_OK(RELOAD)
Macro TIM6 Prescaler reload.
#define | IS_TIM6_SLAVE_MODE_OK(MODE)
Macro TIM6 Slave mode.
#define | IS_TIM6_TRGO_SOURCE_OK(SOURCE)
Macro TIM6 TRGO source.
#define | IS_TIM6_TRIGGER_SELECTION_OK(SELECTION)
Macro TIM6 Trigger selection.
#define | IS_TIM6_UPDATE_SOURCE_OK(SOURCE)
Macro TIM6 Update source.

Define Documentation

#define IS_TIM6_CLEAR_FLAG_OK ( FLAG ) ((((FLAG) & (uint8_t)0xBE) == 0x00) && ((FLAG) != 0x00))

Definition at line 224 of file stm8s_tim6.h.

Referenced by TIM6_ClearFlag().

#define IS_TIM6_EVENT_SOURCE_OK ( SOURCE )
Value:
((((SOURCE) & (uint8_t)0xBE) == 0x00) && \
    ((SOURCE) != 0x00))

Macro TIM6 Event source.

Definition at line 197 of file stm8s_tim6.h.

Referenced by TIM6_GenerateEvent().

#define IS_TIM6_GET_FLAG_OK ( FLAG )
Value:
(((FLAG) == TIM6_FLAG_UPDATE) || \
    ((FLAG) == TIM6_FLAG_TRIGGER))

Macro TIM6 Flags.

Definition at line 220 of file stm8s_tim6.h.

Referenced by TIM6_GetFlagStatus().

#define IS_TIM6_GET_IT_OK ( IT )
Value:
(((IT) == TIM6_IT_UPDATE) || \
    ((IT) == TIM6_IT_TRIGGER))

Definition at line 233 of file stm8s_tim6.h.

Referenced by TIM6_GetITStatus().

#define IS_TIM6_IT_OK ( IT )
Value:
(((IT) != 0x00) && \
    (((IT) & (uint8_t)(~(uint8_t)(0x41)))== 0x00))

Macro TIM6 interrupts.

Definition at line 229 of file stm8s_tim6.h.

Referenced by TIM6_ClearITPendingBit(), and TIM6_ITConfig().

#define IS_TIM6_OPM_MODE_OK ( MODE )
Value:
(((MODE) == TIM6_OPMODE_SINGLE) || \
    ((MODE) == TIM6_OPMODE_REPETITIVE))

Macro TIM6 One Pulse Mode.

Definition at line 178 of file stm8s_tim6.h.

Referenced by TIM6_SelectOnePulseMode().

#define IS_TIM6_PRESCALER_OK ( PRESCALER )
Value:
(((PRESCALER) == TIM6_PRESCALER_1)    || \
    ((PRESCALER) == TIM6_PRESCALER_2)    || \
    ((PRESCALER) == TIM6_PRESCALER_4)    || \
    ((PRESCALER) == TIM6_PRESCALER_8)    || \
    ((PRESCALER) == TIM6_PRESCALER_16)   || \
    ((PRESCALER) == TIM6_PRESCALER_32)   || \
    ((PRESCALER) == TIM6_PRESCALER_64)   || \
    ((PRESCALER) == TIM6_PRESCALER_128))

Macro used by the assert function to check the different functions parameters.

Macro TIM6 Prescaler

Definition at line 166 of file stm8s_tim6.h.

Referenced by TIM6_PrescalerConfig(), and TIM6_TimeBaseInit().

#define IS_TIM6_PRESCALER_RELOAD_OK ( RELOAD )
Value:
(((RELOAD) == TIM6_PSCRELOADMODE_UPDATE) || \
    ((RELOAD) == TIM6_PSCRELOADMODE_IMMEDIATE))

Macro TIM6 Prescaler reload.

Definition at line 185 of file stm8s_tim6.h.

Referenced by TIM6_PrescalerConfig().

#define IS_TIM6_SLAVE_MODE_OK ( MODE )
Value:
(((MODE) == TIM6_SLAVEMODE_DISABLE) || \
    ((MODE) == TIM6_SLAVEMODE_RESET)   || \
    ((MODE) == TIM6_SLAVEMODE_GATED)   || \
    ((MODE) == TIM6_SLAVEMODE_TRIGGER) || \
    ((MODE) == TIM6_SLAVEMODE_EXTERNAL1))

Macro TIM6 Slave mode.

Definition at line 211 of file stm8s_tim6.h.

Referenced by TIM6_SelectSlaveMode().

#define IS_TIM6_TRGO_SOURCE_OK ( SOURCE )
Value:
(((SOURCE) == TIM6_TRGOSOURCE_RESET) || \
    ((SOURCE) == TIM6_TRGOSOURCE_ENABLE)|| \
    ((SOURCE) == TIM6_TRGOSOURCE_UPDATE))

Macro TIM6 TRGO source.

Definition at line 204 of file stm8s_tim6.h.

Referenced by TIM6_SelectOutputTrigger().

#define IS_TIM6_TRIGGER_SELECTION_OK ( SELECTION )
Value:
(((SELECTION) == TIM6_TS_TIM5) || \
    ((SELECTION) == TIM6_TS_TIM1))

Macro TIM6 Trigger selection.

Definition at line 239 of file stm8s_tim6.h.

Referenced by TIM6_SelectInputTrigger().

#define IS_TIM6_UPDATE_SOURCE_OK ( SOURCE )
Value:
(((SOURCE) == TIM6_UPDATESOURCE_GLOBAL) || \
    ((SOURCE) == TIM6_UPDATESOURCE_REGULAR))

Macro TIM6 Update source.

Definition at line 191 of file stm8s_tim6.h.

Referenced by TIM6_UpdateRequestConfig().


STM8S/A Standard Peripherals Drivers: TIM6_Exported_Functions

Functions
TIM6_Exported_Functions
STM8S_StdPeriph_Driver

Functions

void | TIM6_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM6 peripheral Preload register on ARR.
void | TIM6_ClearFlag (TIM6_FLAG_TypeDef TIM6_FLAG)
Clears the TIM’s pending flags.
void | TIM6_ClearITPendingBit (TIM6_IT_TypeDef TIM6_IT)
Clears the TIM6's interrupt pending bits.
void | TIM6_Cmd (FunctionalState NewState)
Enables or disables the TIM6 peripheral.
void | TIM6_DeInit (void)
Deinitializes the TIM6 peripheral registers to their default reset values.
void | TIM6_GenerateEvent (TIM6_EventSource_TypeDef TIM6_EventSource)
Configures the TIM6 event to be generated by software.
uint8_t | TIM6_GetCounter (void)
Gets the TIM6 Counter value.
FlagStatus | TIM6_GetFlagStatus (TIM6_FLAG_TypeDef TIM6_FLAG)
Checks whether the specified TIM6 flag is set or not.
ITStatus | TIM6_GetITStatus (TIM6_IT_TypeDef TIM6_IT)
Checks whether the TIM6 interrupt has occurred or not.
TIM6_Prescaler_TypeDef | TIM6_GetPrescaler (void)
Gets the TIM6 Prescaler value.
void | TIM6_InternalClockConfig (void)
Enables the TIM6 internal Clock.
void | TIM6_ITConfig (TIM6_IT_TypeDef TIM6_IT, FunctionalState NewState)
Enables or disables the specified TIM6 interrupts.
void | TIM6_PrescalerConfig (TIM6_Prescaler_TypeDef Prescaler, TIM6_PSCReloadMode_TypeDef TIM6_PSCReloadMode)
Configures the TIM6 Prescaler.
void | TIM6_SelectInputTrigger (TIM6_TS_TypeDef TIM6_InputTriggerSource)
Selects the TIM6 Input Trigger source.
void | TIM6_SelectMasterSlaveMode (FunctionalState NewState)
Sets or Resets the TIM6 Master/Slave Mode.
void | TIM6_SelectOnePulseMode (TIM6_OPMode_TypeDef TIM6_OPMode)
Selects the TIM6’s One Pulse Mode.
void | TIM6_SelectOutputTrigger (TIM6_TRGOSource_TypeDef TIM6_TRGOSource)
Selects the TIM6 Trigger Output Mode.
void | TIM6_SelectSlaveMode (TIM6_SlaveMode_TypeDef TIM6_SlaveMode)
Selects the TIM6 Slave Mode.
void | TIM6_SetAutoreload (uint8_t Autoreload)
Sets the TIM6 Autoreload Register value.
void | TIM6_SetCounter (uint8_t Counter)
Sets the TIM6 Counter Register value.
void | TIM6_TimeBaseInit (TIM6_Prescaler_TypeDef TIM6_Prescaler, uint8_t TIM6_Period)
Initializes the TIM6 Time Base Unit according to the specified parameters.
void | TIM6_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM6 Update event.
void | TIM6_UpdateRequestConfig (TIM6_UpdateSource_TypeDef TIM6_UpdateSource)
Selects the TIM6 Update Request Interrupt source.

Function Documentation

void TIM6_ARRPreloadConfig ( FunctionalState NewState )

Enables or disables TIM6 peripheral Preload register on ARR.

Parameters:
NewState : The new state of the TIM6 peripheral Preload register. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 205 of file stm8s_tim6.c.

References ENABLE, IS_FUNCTIONALSTATE_OK, and TIM6_CR1_ARPE.

void TIM6_ClearFlag ( TIM6_FLAG_TypeDef TIM6_FLAG )

Clears the TIM’s pending flags.

Parameters:
TIM6_FLAG : Specifies the flag to clear. This parameter can be one of the TIM6_FLAG_TypeDef enumeration.
Return values:
None

Definition at line 304 of file stm8s_tim6.c.

References IS_TIM6_CLEAR_FLAG_OK.

void TIM6_ClearITPendingBit ( TIM6_IT_TypeDef TIM6_IT )

Clears the TIM6's interrupt pending bits.

Parameters:
TIM6_IT : Specifies the pending bit to clear. This parameter can be one of the TIM6_IT_TypeDef enumeration.
Return values:
None

Definition at line 388 of file stm8s_tim6.c.

References IS_TIM6_IT_OK.

void TIM6_Cmd ( FunctionalState NewState )

Enables or disables the TIM6 peripheral.

Parameters:
NewState : The new state of the TIM6 peripheral. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 88 of file stm8s_tim6.c.

References ENABLE, IS_FUNCTIONALSTATE_OK, and TIM6_CR1_CEN.

void TIM6_DeInit ( void )

Deinitializes the TIM6 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 52 of file stm8s_tim6.c.

References TIM6_ARR_RESET_VALUE, TIM6_CNTR_RESET_VALUE, TIM6_CR1_RESET_VALUE, TIM6_CR2_RESET_VALUE, TIM6_IER_RESET_VALUE, TIM6_PSCR_RESET_VALUE, TIM6_SMCR_RESET_VALUE, and TIM6_SR1_RESET_VALUE.

void TIM6_GenerateEvent ( TIM6_EventSource_TypeDef TIM6_EventSource )

Configures the TIM6 event to be generated by software.

Parameters:
TIM6_EventSource : Specifies the event source. This parameter can be one of the TIM6_EventSource_TypeDef enumeration.
Return values:
None

Definition at line 348 of file stm8s_tim6.c.

References IS_TIM6_EVENT_SOURCE_OK.

uint8_t TIM6_GetCounter ( void )

Gets the TIM6 Counter value.

Parameters:
None
Return values:
uint8_t,: Counter Register value.

Definition at line 250 of file stm8s_tim6.c.

FlagStatus TIM6_GetFlagStatus ( TIM6_FLAG_TypeDef TIM6_FLAG )

Checks whether the specified TIM6 flag is set or not.

Parameters:
TIM6_FLAG : Specifies the flag to check. This parameter can be one of the TIM6_FLAG_TypeDef enumeration.
Return values:
FlagStatus : The new state of TIM6_FLAG. This parameter can be any of the FlagStatus enumeration.

Definition at line 364 of file stm8s_tim6.c.

References IS_TIM6_GET_FLAG_OK, RESET, and SET.

ITStatus TIM6_GetITStatus ( TIM6_IT_TypeDef TIM6_IT )

Checks whether the TIM6 interrupt has occurred or not.

Parameters:
TIM6_IT : Specifies the TIM6 interrupt source to check. This parameter can be one of the TIM6_IT_TypeDef enumeration.
Return values:
ITStatus : The new state of the TIM6_IT. This parameter can be any of the ITStatus enumeration.

Definition at line 319 of file stm8s_tim6.c.

References IS_TIM6_GET_IT_OK, RESET, and SET.

TIM6_Prescaler_TypeDef TIM6_GetPrescaler ( void )

Gets the TIM6 Prescaler value.

Parameters:
None
Return values:
TIM6_Prescaler_TypeDef : Prescaler Register configuration value.

Definition at line 263 of file stm8s_tim6.c.

void TIM6_InternalClockConfig ( void )

Enables the TIM6 internal Clock.

Parameters:
None
Return values:
None

Definition at line 471 of file stm8s_tim6.c.

References TIM6_SMCR_SMS.

void TIM6_ITConfig | ( | TIM6_IT_TypeDef | TIM6_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified TIM6 interrupts.

Parameters:
TIM6_IT | : Specifies the TIM6 interrupts sources to be enabled or disabled. This parameter can be any combination of the TIM6_IT_TypeDef enumeration.
NewState | : The new state of the TIM6 peripheral. This parameter can be any of the FunctionalState enumeration.
Return values:
None
Required preconditions:
If QST option bit is enabled, the TIM6 Interrupt vector will be mapped on IRQ number 2 (irq0). Otherwise, it will be mapped on IRQ number 27 (irq25).

Definition at line 280 of file stm8s_tim6.c.

References ENABLE, IS_FUNCTIONALSTATE_OK, and IS_TIM6_IT_OK.

void TIM6_PrescalerConfig | ( | TIM6_Prescaler_TypeDef | Prescaler,
 |  | TIM6_PSCReloadMode_TypeDef | TIM6_PSCReloadMode
 | ) |  |

Configures the TIM6 Prescaler.

Parameters:
Prescaler | : Specifies the Prescaler Register value This parameter can be one of the TIM6_Prescaler_TypeDef enumeration.
TIM6_PSCReloadMode | : Specifies the TIM6 Prescaler Reload mode. This parameter can be one of the TIM6_PSCReloadMode_TypeDef enumeration.
Return values:
None

Definition at line 178 of file stm8s_tim6.c.

References IS_TIM6_PRESCALER_OK, IS_TIM6_PRESCALER_RELOAD_OK, TIM6_EGR_UG, and TIM6_PSCRELOADMODE_IMMEDIATE.

void TIM6_SelectInputTrigger ( TIM6_TS_TypeDef TIM6_InputTriggerSource )

Selects the TIM6 Input Trigger source.

Parameters:
TIM6_InputTriggerSource : Specifies Input Trigger source. This parameter can be one of the TIM6_TS_TypeDef enumeration.
Return values:
None

Definition at line 450 of file stm8s_tim6.c.

References IS_TIM6_TRIGGER_SELECTION_OK, and TIM6_SMCR_TS.

void TIM6_SelectMasterSlaveMode ( FunctionalState NewState )

Sets or Resets the TIM6 Master/Slave Mode.

Parameters:
NewState : The new state of the synchronization between TIM6 and its slaves (through TRGO). This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 428 of file stm8s_tim6.c.

References ENABLE, IS_FUNCTIONALSTATE_OK, and TIM6_SMCR_MSM.

void TIM6_SelectOnePulseMode ( TIM6_OPMode_TypeDef TIM6_OPMode )

Selects the TIM6’s One Pulse Mode.

Parameters:
TIM6_OPMode : Specifies the OPM Mode to be used. This parameter can be one of the TIM6_OPMode_TypeDef enumeration.
Return values:
None

Definition at line 154 of file stm8s_tim6.c.

References IS_TIM6_OPM_MODE_OK, TIM6_CR1_OPM, and TIM6_OPMODE_SINGLE.

void TIM6_SelectOutputTrigger ( TIM6_TRGOSource_TypeDef TIM6_TRGOSource )

Selects the TIM6 Trigger Output Mode.

Parameters:
TIM6_TRGOSource : Specifies the Trigger Output source. This parameter can be one of the TIM6_TRGOSource_TypeDef enumeration.
Return values:
None

Definition at line 403 of file stm8s_tim6.c.

References IS_TIM6_TRGO_SOURCE_OK, and TIM6_CR2_MMS.

void TIM6_SelectSlaveMode ( TIM6_SlaveMode_TypeDef TIM6_SlaveMode )

Selects the TIM6 Slave Mode.

Parameters:
TIM6_SlaveMode : Specifies the TIM6 Slave Mode. This parameter can be one of the TIM6_SlaveMode_TypeDef enumeration.
Return values:
None

Definition at line 483 of file stm8s_tim6.c.

References IS_TIM6_SLAVE_MODE_OK, and TIM6_SMCR_SMS.

void TIM6_SetAutoreload ( uint8_t Autoreload )

Sets the TIM6 Autoreload Register value.

Parameters:
Autoreload : Specifies the Autoreload register new value. This parameter is between 0x00 and 0xFF.
Return values:
None

Definition at line 239 of file stm8s_tim6.c.

void TIM6_SetCounter ( uint8_t Counter )

Sets the TIM6 Counter Register value.

Parameters:
Counter : Specifies the Counter register new value. This parameter is between 0x00 and 0xFF.
Return values:
None

Definition at line 227 of file stm8s_tim6.c.

void TIM6_TimeBaseInit | ( | TIM6_Prescaler_TypeDef | TIM6_Prescaler,
 |  | uint8_t | TIM6_Period
 | ) |  |

Initializes the TIM6 Time Base Unit according to the specified parameters.

Parameters:
TIM6_Prescaler | : This parameter can be any of the TIM6_Prescaler_TypeDef enumeration.
TIM6_Period | : This parameter must be a value between 0x00 and 0xFF.
Return values:
None

Definition at line 71 of file stm8s_tim6.c.

References IS_TIM6_PRESCALER_OK.

void TIM6_UpdateDisableConfig ( FunctionalState NewState )

Enables or Disables the TIM6 Update event.

Parameters:
NewState : The new state of the TIM6 peripheral Preload register. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 110 of file stm8s_tim6.c.

References ENABLE, IS_FUNCTIONALSTATE_OK, and TIM6_CR1_UDIS.

void TIM6_UpdateRequestConfig ( TIM6_UpdateSource_TypeDef TIM6_UpdateSource )

Selects the TIM6 Update Request Interrupt source.

Parameters:
TIM6_UpdateSource : Specifies the Update source. This parameter can be one of the TIM6_UpdateSource_TypeDef enumeration.
Return values:
None

Definition at line 132 of file stm8s_tim6.c.

References IS_TIM6_UPDATE_SOURCE_OK, TIM6_CR1_URS, and TIM6_UPDATESOURCE_REGULAR.


STM8S/A Standard Peripherals Drivers: UART1_Exported_Types

Enumerations
UART1_Exported_Types
STM8S_StdPeriph_Driver

Enumerations

enum UART1_Flag_TypeDef {
UART1_FLAG_TXE = (uint16_t)0x0080, UART1_FLAG_TC = (uint16_t)0x0040, UART1_FLAG_RXNE = (uint16_t)0x0020, UART1_FLAG_IDLE = (uint16_t)0x0010,
UART1_FLAG_OR = (uint16_t)0x0008, UART1_FLAG_NF = (uint16_t)0x0004, UART1_FLAG_FE = (uint16_t)0x0002, UART1_FLAG_PE = (uint16_t)0x0001,
UART1_FLAG_LBDF = (uint16_t)0x0210, UART1_FLAG_SBK = (uint16_t)0x0101
}
UART1 Flag possible values. More...
enum | UART1_IrDAMode_TypeDef { UART1_IRDAMODE_NORMAL = (uint8_t)0x00, UART1_IRDAMODE_LOWPOWER = (uint8_t)0x01 }
UART1 Irda Modes. More...
enum UART1_IT_TypeDef {
UART1_IT_TXE = (uint16_t)0x0277, UART1_IT_TC = (uint16_t)0x0266, UART1_IT_RXNE = (uint16_t)0x0255, UART1_IT_IDLE = (uint16_t)0x0244,
UART1_IT_OR = (uint16_t)0x0235, UART1_IT_PE = (uint16_t)0x0100, UART1_IT_LBDF = (uint16_t)0x0346, UART1_IT_RXNE_OR = (uint16_t)0x0205
}
UART1 Interrupt definition UART1_IT possible values Elements values convention: 0xZYX X: Position of the corresponding Interrupt. More...
enum | UART1_LINBreakDetectionLength_TypeDef { UART1_LINBREAKDETECTIONLENGTH_10BITS = (uint8_t)0x00, UART1_LINBREAKDETECTIONLENGTH_11BITS = (uint8_t)0x01 }
UART1 LIN Break detection length possible values. More...
enum UART1_Mode_TypeDef {
UART1_MODE_RX_ENABLE = (uint8_t)0x08, UART1_MODE_TX_ENABLE = (uint8_t)0x04, UART1_MODE_TX_DISABLE = (uint8_t)0x80, UART1_MODE_RX_DISABLE = (uint8_t)0x40,
UART1_MODE_TXRX_ENABLE = (uint8_t)0x0C
}
UART1 Mode possible values. More...
enum | UART1_Parity_TypeDef { UART1_PARITY_NO = (uint8_t)0x00, UART1_PARITY_EVEN = (uint8_t)0x04, UART1_PARITY_ODD = (uint8_t)0x06 }
UART1 parity possible values. More...
enum | UART1_StopBits_TypeDef { UART1_STOPBITS_1 = (uint8_t)0x00, UART1_STOPBITS_0_5 = (uint8_t)0x10, UART1_STOPBITS_2 = (uint8_t)0x20, UART1_STOPBITS_1_5 = (uint8_t)0x30 }
UART1 stop bits possible values. More...
enum UART1_SyncMode_TypeDef {
UART1_SYNCMODE_CLOCK_DISABLE = (uint8_t)0x80, UART1_SYNCMODE_CLOCK_ENABLE = (uint8_t)0x08, UART1_SYNCMODE_CPOL_LOW = (uint8_t)0x40, UART1_SYNCMODE_CPOL_HIGH = (uint8_t)0x04,
UART1_SYNCMODE_CPHA_MIDDLE = (uint8_t)0x20, UART1_SYNCMODE_CPHA_BEGINING = (uint8_t)0x02, UART1_SYNCMODE_LASTBIT_DISABLE = (uint8_t)0x10, UART1_SYNCMODE_LASTBIT_ENABLE = (uint8_t)0x01
}
UART1 Synchrone modes. More...
enum | UART1_WakeUp_TypeDef { UART1_WAKEUP_IDLELINE = (uint8_t)0x00, UART1_WAKEUP_ADDRESSMARK = (uint8_t)0x08 }
UART1 WakeUP Modes. More...
enum | UART1_WordLength_TypeDef { UART1_WORDLENGTH_8D = (uint8_t)0x00, UART1_WORDLENGTH_9D = (uint8_t)0x10 }
UART1 Word length possible values. More...

Enumeration Type Documentation

enum UART1_Flag_TypeDef

UART1 Flag possible values.

Enumerator:
UART1_FLAG_TXE

Transmit Data Register Empty flag

UART1_FLAG_TC

Transmission Complete flag

UART1_FLAG_RXNE

Read Data Register Not Empty flag

UART1_FLAG_IDLE

Idle line detected flag

UART1_FLAG_OR

OverRun error flag

UART1_FLAG_NF

Noise error flag

UART1_FLAG_FE

Framing Error flag

UART1_FLAG_PE

Parity Error flag

UART1_FLAG_LBDF

Line Break Detection Flag

UART1_FLAG_SBK

Send Break characters Flag

Definition at line 119 of file stm8s_uart1.h.

enum UART1_IrDAMode_TypeDef

UART1 Irda Modes.

Enumerator:
UART1_IRDAMODE_NORMAL

0x00 Irda Normal Mode

UART1_IRDAMODE_LOWPOWER

0x01 Irda Low Power Mode

Definition at line 50 of file stm8s_uart1.h.

enum UART1_IT_TypeDef

UART1 Interrupt definition UART1_IT possible values Elements values convention: 0xZYX X: Position of the corresponding Interrupt.

  • For the following values, X means the interrupt position in the CR2 register. UART1_IT_TXE UART1_IT_TC UART1_IT_RXNE UART1_IT_IDLE UART1_IT_OR
  • For the UART1_IT_PE value, X means the flag position in the CR1 register.
  • For the UART1_IT_LBDF value, X means the flag position in the CR4 register. Y: Flag position

For the following values, Y means the flag (pending bit) position in the SR register. UART1_IT_TXE UART1_IT_TC UART1_IT_RXNE UART1_IT_IDLE UART1_IT_OR UART1_IT_PE

  • For the UART1_IT_LBDF value, Y means the flag position in the CR4 register. Z: Register index: indicate in which register the dedicated interrupt source is:
  • 1==> CR1 register
  • 2==> CR2 register
  • 3==> CR4 register
Enumerator:
UART1_IT_TXE

Transmit interrupt

UART1_IT_TC

Transmission Complete interrupt

UART1_IT_RXNE

Receive interrupt

UART1_IT_IDLE

IDLE line interrupt

UART1_IT_OR

Overrun Error interrupt

UART1_IT_PE

Parity Error interrupt

UART1_IT_LBDF

LIN break detection interrupt.

UART1_IT_RXNE_OR

Receive/Overrun interrupt

Definition at line 158 of file stm8s_uart1.h.

enum UART1_LINBreakDetectionLength_TypeDef

UART1 LIN Break detection length possible values.

Enumerator:
UART1_LINBREAKDETECTIONLENGTH_10BITS

0x01 10 bits Lin Break detection

UART1_LINBREAKDETECTIONLENGTH_11BITS

0x02 11 bits Lin Break detection

Definition at line 64 of file stm8s_uart1.h.

enum UART1_Mode_TypeDef

UART1 Mode possible values.

Enumerator:
UART1_MODE_RX_ENABLE

0x08 Receive Enable

UART1_MODE_TX_ENABLE

0x04 Transmit Enable

UART1_MODE_TX_DISABLE

0x80 Transmit Disable

UART1_MODE_RX_DISABLE

0x40 Single-wire Half-duplex mode

UART1_MODE_TXRX_ENABLE

0x0C Transmit Enable and Receive Enable

Definition at line 109 of file stm8s_uart1.h.

enum UART1_Parity_TypeDef

UART1 parity possible values.

Enumerator:
UART1_PARITY_NO

No Parity.

UART1_PARITY_EVEN

Even Parity.

UART1_PARITY_ODD

Odd Parity.

Definition at line 81 of file stm8s_uart1.h.

enum UART1_StopBits_TypeDef

UART1 stop bits possible values.

Enumerator:
UART1_STOPBITS_1

One stop bit is transmitted at the end of frame.

UART1_STOPBITS_0_5

Half stop bits is transmitted at the end of frame.

UART1_STOPBITS_2

Two stop bits are transmitted at the end of frame.

UART1_STOPBITS_1_5

One and half stop bits.

Definition at line 72 of file stm8s_uart1.h.

enum UART1_SyncMode_TypeDef

UART1 Synchrone modes.

Enumerator:
UART1_SYNCMODE_CLOCK_DISABLE

0x80 Sync mode Disable, SLK pin Disable

UART1_SYNCMODE_CLOCK_ENABLE

0x08 Sync mode Enable, SLK pin Enable

UART1_SYNCMODE_CPOL_LOW

0x40 Steady low value on SCLK pin outside transmission window

UART1_SYNCMODE_CPOL_HIGH

0x04 Steady high value on SCLK pin outside transmission window

UART1_SYNCMODE_CPHA_MIDDLE

0x20 SCLK clock line activated in middle of data bit

UART1_SYNCMODE_CPHA_BEGINING

0x02 SCLK clock line activated at beginning of data bit

UART1_SYNCMODE_LASTBIT_DISABLE

0x10 The clock pulse of the last data bit is not output to the SCLK pin

UART1_SYNCMODE_LASTBIT_ENABLE

0x01 The clock pulse of the last data bit is output to the SCLK pin

Definition at line 89 of file stm8s_uart1.h.

enum UART1_WakeUp_TypeDef

UART1 WakeUP Modes.

Enumerator:
UART1_WAKEUP_IDLELINE

0x01 Idle Line wake up

UART1_WAKEUP_ADDRESSMARK

0x02 Address Mark wake up

Definition at line 57 of file stm8s_uart1.h.

enum UART1_WordLength_TypeDef

UART1 Word length possible values.

Enumerator:
UART1_WORDLENGTH_8D

0x00 8 bits Data

UART1_WORDLENGTH_9D

0x10 9 bits Data

Definition at line 102 of file stm8s_uart1.h.


STM8S/A Standard Peripherals Drivers: UART1_Private_Macros

Defines
UART1_Private_Macros
STM8S_StdPeriph_Driver

Defines

#define | IS_UART1_ADDRESS_OK(node) ((node) < UART1_ADDRESS_MAX )
#define | IS_UART1_BAUDRATE_OK(NUM) ((NUM) <= (uint32_t)625000)
Macro used by the assert_param function in order to check the maximum baudrate value.
#define | IS_UART1_CLEAR_FLAG_OK(Flag)
Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs that can be cleared by writing 0.
#define | IS_UART1_CLEAR_IT_OK(ITPendingBit)
Macro used by the assert function in order to check the different sensitivity values for the pending bit that can be cleared by writing 0.
#define | IS_UART1_CONFIG_IT_OK(Interrupt)
Macro used by the assert_param function in order to check the different sensitivity values for the Interrupts.
#define | IS_UART1_FLAG_OK(Flag)
Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs.
#define | IS_UART1_GET_IT_OK(ITPendingBit)
Macro used by the assert function in order to check the different sensitivity values for the pending bit.
#define | IS_UART1_IRDAMODE_OK(IrDAMode)
Macro used by the assert_param function in order to check the different sensitivity values for the IrDAModes.
#define | IS_UART1_LINBREAKDETECTIONLENGTH_OK(LINBreakDetectionLength)
Macro used by the assert_param function in order to check the different sensitivity values for the LINBreakDetectionLengths.
#define | IS_UART1_MODE_OK(Mode)
Macro used by the assert function to check the different functions parameters.
#define | IS_UART1_PARITY_OK(Parity)
Macro used by the assert_param function in order to check the different sensitivity values for the Parity.
#define | IS_UART1_STOPBITS_OK(StopBit)
Macro used by the assert_param function in order to check the different sensitivity values for the UART1_StopBits.
#define | IS_UART1_SYNCMODE_OK(SyncMode)
Macro used by the assert_param function in order to check the different sensitivity values for the SyncModes; it should exclude values such as UART1_CLOCK_ENABLE|UART1_CLOCK_DISABLE.
#define | IS_UART1_WAKEUP_OK(WakeUp)
Macro used by the assert_param function in order to check the different sensitivity values for the WakeUps.
#define | IS_UART1_WORDLENGTH_OK(WordLength)
Macro used by the assert_param function in order to check the different sensitivity values for the WordLengths.
#define | UART1_ADDRESS_MAX ((uint8_t)16)
Macro used by the assert_param function in order to check the address of the UART1 or UART node.

Define Documentation

#define IS_UART1_ADDRESS_OK ( node ) ((node) < UART1_ADDRESS_MAX )

Definition at line 333 of file stm8s_uart1.h.

Referenced by UART1_SetAddress().

#define IS_UART1_BAUDRATE_OK ( NUM ) ((NUM) <= (uint32_t)625000)

Macro used by the assert_param function in order to check the maximum baudrate value.

Definition at line 325 of file stm8s_uart1.h.

Referenced by UART1_Init().

#define IS_UART1_CLEAR_FLAG_OK ( Flag )
Value:
(((Flag) == UART1_FLAG_RXNE) || \
   ((Flag) == UART1_FLAG_LBDF))

Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs that can be cleared by writing 0.

Definition at line 239 of file stm8s_uart1.h.

Referenced by UART1_ClearFlag().

#define IS_UART1_CLEAR_IT_OK ( ITPendingBit )
Value:
(((ITPendingBit) == UART1_IT_RXNE) || \
   ((ITPendingBit) == UART1_IT_LBDF))

Macro used by the assert function in order to check the different sensitivity values for the pending bit that can be cleared by writing 0.

Definition at line 275 of file stm8s_uart1.h.

Referenced by UART1_ClearITPendingBit().

#define IS_UART1_CONFIG_IT_OK ( Interrupt )
Value:
(((Interrupt) == UART1_IT_PE) || \
   ((Interrupt) == UART1_IT_TXE) || \
   ((Interrupt) == UART1_IT_TC) || \
   ((Interrupt) == UART1_IT_RXNE_OR ) || \
   ((Interrupt) == UART1_IT_IDLE) || \
   ((Interrupt) == UART1_IT_LBDF))

Macro used by the assert_param function in order to check the different sensitivity values for the Interrupts.

Definition at line 250 of file stm8s_uart1.h.

Referenced by UART1_ITConfig().

#define IS_UART1_FLAG_OK ( Flag )
Value:
(((Flag) == UART1_FLAG_TXE) || \
   ((Flag) == UART1_FLAG_TC)  || \
   ((Flag) == UART1_FLAG_RXNE) || \
   ((Flag) == UART1_FLAG_IDLE) || \
   ((Flag) == UART1_FLAG_OR) || \
   ((Flag) == UART1_FLAG_NF) || \
   ((Flag) == UART1_FLAG_FE) || \
   ((Flag) == UART1_FLAG_PE) || \
   ((Flag) == UART1_FLAG_SBK) || \
   ((Flag) == UART1_FLAG_LBDF))

Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs.

Definition at line 224 of file stm8s_uart1.h.

Referenced by UART1_GetFlagStatus().

#define IS_UART1_GET_IT_OK ( ITPendingBit )
Value:
(((ITPendingBit) == UART1_IT_TXE)  || \
   ((ITPendingBit) == UART1_IT_TC)   || \
   ((ITPendingBit) == UART1_IT_RXNE) || \
   ((ITPendingBit) == UART1_IT_IDLE) || \
   ((ITPendingBit) == UART1_IT_OR)  || \
   ((ITPendingBit) == UART1_IT_LBDF)  || \
   ((ITPendingBit) == UART1_IT_PE))

Macro used by the assert function in order to check the different sensitivity values for the pending bit.

Definition at line 262 of file stm8s_uart1.h.

Referenced by UART1_GetITStatus().

#define IS_UART1_IRDAMODE_OK ( IrDAMode )
Value:
(((IrDAMode) == UART1_IRDAMODE_LOWPOWER) || \
   ((IrDAMode) == UART1_IRDAMODE_NORMAL))

Macro used by the assert_param function in order to check the different sensitivity values for the IrDAModes.

Definition at line 284 of file stm8s_uart1.h.

Referenced by UART1_IrDAConfig().

#define IS_UART1_LINBREAKDETECTIONLENGTH_OK ( LINBreakDetectionLength )
Value:
(((LINBreakDetectionLength) == UART1_LINBREAKDETECTIONLENGTH_10BITS) || \
   ((LINBreakDetectionLength) == UART1_LINBREAKDETECTIONLENGTH_11BITS))

Macro used by the assert_param function in order to check the different sensitivity values for the LINBreakDetectionLengths.

Definition at line 300 of file stm8s_uart1.h.

Referenced by UART1_LINBreakDetectionConfig().

#define IS_UART1_MODE_OK ( Mode )
Value:
(((Mode) == (uint8_t)UART1_MODE_RX_ENABLE) || \
   ((Mode) == (uint8_t)UART1_MODE_RX_DISABLE) || \
   ((Mode) == (uint8_t)UART1_MODE_TX_ENABLE) || \
   ((Mode) == (uint8_t)UART1_MODE_TX_DISABLE) || \
   ((Mode) == (uint8_t)UART1_MODE_TXRX_ENABLE) || \
   ((Mode) == (uint8_t)((uint8_t)UART1_MODE_TX_ENABLE|(uint8_t)UART1_MODE_RX_ENABLE)) || \
   ((Mode) == (uint8_t)((uint8_t)UART1_MODE_TX_ENABLE|(uint8_t)UART1_MODE_RX_DISABLE)) || \
   ((Mode) == (uint8_t)((uint8_t)UART1_MODE_TX_DISABLE|(uint8_t)UART1_MODE_RX_DISABLE)) || \
   ((Mode) == (uint8_t)((uint8_t)UART1_MODE_TX_DISABLE|(uint8_t)UART1_MODE_RX_ENABLE)))

Macro used by the assert function to check the different functions parameters.

Macro used by the assert_param function in order to check the different sensitivity values for the MODEs possible combination should be one of the following

Definition at line 190 of file stm8s_uart1.h.

Referenced by UART1_Init().

#define IS_UART1_PARITY_OK ( Parity )
Value:
(((Parity) == UART1_PARITY_NO) || \
                                    ((Parity) == UART1_PARITY_EVEN) || \
                                    ((Parity) == UART1_PARITY_ODD ))

Macro used by the assert_param function in order to check the different sensitivity values for the Parity.

Definition at line 317 of file stm8s_uart1.h.

Referenced by UART1_Init().

#define IS_UART1_STOPBITS_OK ( StopBit )
Value:
(((StopBit) == UART1_STOPBITS_1) || \
                                       ((StopBit) == UART1_STOPBITS_0_5) || \
                                       ((StopBit) == UART1_STOPBITS_2) || \
                                       ((StopBit) == UART1_STOPBITS_1_5 ))

Macro used by the assert_param function in order to check the different sensitivity values for the UART1_StopBits.

Definition at line 308 of file stm8s_uart1.h.

Referenced by UART1_Init().

#define IS_UART1_SYNCMODE_OK ( SyncMode )
Value:
(!((((SyncMode)&(((uint8_t)UART1_SYNCMODE_CLOCK_ENABLE)|((uint8_t)UART1_SYNCMODE_CLOCK_DISABLE))) == (((uint8_t)UART1_SYNCMODE_CLOCK_ENABLE)|((uint8_t)UART1_SYNCMODE_CLOCK_DISABLE))) \
    || (((SyncMode)&(((uint8_t)UART1_SYNCMODE_CPOL_LOW )|((uint8_t)UART1_SYNCMODE_CPOL_HIGH))) == (((uint8_t)UART1_SYNCMODE_CPOL_LOW )|((uint8_t)UART1_SYNCMODE_CPOL_HIGH))) \
    ||(((SyncMode)&(((uint8_t)UART1_SYNCMODE_CPHA_MIDDLE)|((uint8_t)UART1_SYNCMODE_CPHA_BEGINING))) ==  (((uint8_t)UART1_SYNCMODE_CPHA_MIDDLE)|((uint8_t)UART1_SYNCMODE_CPHA_BEGINING))) \
    || (((SyncMode)&(((uint8_t)UART1_SYNCMODE_LASTBIT_DISABLE)|((uint8_t)UART1_SYNCMODE_LASTBIT_ENABLE))) == (((uint8_t)UART1_SYNCMODE_LASTBIT_DISABLE)|((uint8_t)UART1_SYNCMODE_LASTBIT_ENABLE)))))

Macro used by the assert_param function in order to check the different sensitivity values for the SyncModes; it should exclude values such as UART1_CLOCK_ENABLE|UART1_CLOCK_DISABLE.

Definition at line 214 of file stm8s_uart1.h.

Referenced by UART1_Init().

#define IS_UART1_WAKEUP_OK ( WakeUp )
Value:
(((WakeUp) == UART1_WAKEUP_IDLELINE) || \
   ((WakeUp) == UART1_WAKEUP_ADDRESSMARK))

Macro used by the assert_param function in order to check the different sensitivity values for the WakeUps.

Definition at line 292 of file stm8s_uart1.h.

Referenced by UART1_WakeUpConfig().

#define IS_UART1_WORDLENGTH_OK ( WordLength )
Value:
(((WordLength) == UART1_WORDLENGTH_8D) || \
   ((WordLength) == UART1_WORDLENGTH_9D))

Macro used by the assert_param function in order to check the different sensitivity values for the WordLengths.

Definition at line 205 of file stm8s_uart1.h.

Referenced by UART1_Init().

#define UART1_ADDRESS_MAX ((uint8_t)16)

Macro used by the assert_param function in order to check the address of the UART1 or UART node.

Definition at line 332 of file stm8s_uart1.h.


STM8S/A Standard Peripherals Drivers: UART1_Exported_Functions

Functions
UART1_Exported_Functions
STM8S_StdPeriph_Driver

Functions

void | UART1_ClearFlag (UART1_Flag_TypeDef UART1_FLAG)
Clears the UART1 flags.
void | UART1_ClearITPendingBit (UART1_IT_TypeDef UART1_IT)
Clears the UART1 pending flags.
void | UART1_Cmd (FunctionalState NewState)
Enable the UART1 peripheral.
void | UART1_DeInit (void)
Deinitializes the UART peripheral.
FlagStatus | UART1_GetFlagStatus (UART1_Flag_TypeDef UART1_FLAG)
Checks whether the specified UART1 flag is set or not.
ITStatus | UART1_GetITStatus (UART1_IT_TypeDef UART1_IT)
Checks whether the specified UART1 interrupt has occurred or not.
void | UART1_HalfDuplexCmd (FunctionalState NewState)
Enables or disables the UART’s Half Duplex communication.
void | UART1_Init (uint32_t BaudRate, UART1_WordLength_TypeDef WordLength, UART1_StopBits_TypeDef StopBits, UART1_Parity_TypeDef Parity, UART1_SyncMode_TypeDef SyncMode, UART1_Mode_TypeDef Mode)
Initializes the UART1 according to the specified parameters.
void | UART1_IrDACmd (FunctionalState NewState)
Enables or disables the UART’s IrDA interface.
void | UART1_IrDAConfig (UART1_IrDAMode_TypeDef UART1_IrDAMode)
Configures the UART’s IrDA interface.
void | UART1_ITConfig (UART1_IT_TypeDef UART1_IT, FunctionalState NewState)
Enables or disables the specified USART interrupts.
void | UART1_LINBreakDetectionConfig (UART1_LINBreakDetectionLength_TypeDef UART1_LINBreakDetectionLength)
Sets the UART1 LIN Break detection length.
void | UART1_LINCmd (FunctionalState NewState)
Enables or disables the UART1’s LIN mode.
uint8_t | UART1_ReceiveData8 (void)
Returns the most recent received data by the UART1 peripheral.
uint16_t | UART1_ReceiveData9 (void)
Returns the most recent received data by the UART1 peripheral.
void | UART1_ReceiverWakeUpCmd (FunctionalState NewState)
Determines if the UART1 is in mute mode or not.
void | UART1_SendBreak (void)
Transmits break characters.
void | UART1_SendData8 (uint8_t Data)
Transmits 8 bit data through the UART1 peripheral.
void | UART1_SendData9 (uint16_t Data)
Transmits 9 bit data through the UART peripheral.
void | UART1_SetAddress (uint8_t UART1_Address)
Sets the address of the UART1 node.
void | UART1_SetGuardTime (uint8_t UART1_GuardTime)
Sets the specified UART guard time.
void | UART1_SetPrescaler (uint8_t UART1_Prescaler)
Sets the system clock prescaler.
void | UART1_SmartCardCmd (FunctionalState NewState)
Enables or disables the UART1 Smart Card mode.
void | UART1_SmartCardNACKCmd (FunctionalState NewState)
Enables or disables NACK transmission.
void | UART1_WakeUpConfig (UART1_WakeUp_TypeDef UART1_WakeUp)
Selects the UART1 WakeUp method.

Function Documentation

void UART1_ClearFlag ( UART1_Flag_TypeDef UART1_FLAG )

Clears the UART1 flags.

Parameters:
UART1_FLAG specifies the flag to clear This parameter can be any combination of the following values:
  • UART1_FLAG_LBDF: LIN Break detection flag.
  • UART1_FLAG_RXNE: Receive data register not empty flag.
Note:
  • PE (Parity error), FE (Framing error), NE (Noise error), OR (OverRun error) and IDLE (Idle line detected) flags are cleared by software sequence: a read operation to UART1_SR register (UART1_GetFlagStatus())followed by a read operation to UART1_DR register(UART1_ReceiveData8() or UART1_ReceiveData9()).
  • RXNE flag can be also cleared by a read to the UART1_DR register (UART1_ReceiveData8()or UART1_ReceiveData9()).
  • TC flag can be also cleared by software sequence: a read operation to UART1_SR register (UART1_GetFlagStatus()) followed by a write operation to UART1_DR register (UART1_SendData8() or UART1_SendData9()).
  • TXE flag is cleared only by a write to the UART1_DR register (UART1_SendData8() or UART1_SendData9()).
  • SBK flag is cleared during the stop bit of break.
    Return values:
    None

Definition at line 646 of file stm8s_uart1.c.

References IS_UART1_CLEAR_FLAG_OK, UART1_CR4_LBDF, UART1_FLAG_RXNE, and UART1_SR_RXNE.

void UART1_ClearITPendingBit ( UART1_IT_TypeDef UART1_IT )

Clears the UART1 pending flags.

Parameters:
UART1_IT specifies the pending bit to clear This parameter can be one of the following values:
  • UART1_IT_LBDF: LIN Break detection interrupt
  • UART1_IT_RXNE: Receive Data register not empty interrupt.
Note:
  • PE (Parity error), FE (Framing error), NE (Noise error), OR (OverRun error) and IDLE (Idle line detected) pending bits are cleared by software sequence: a read operation to UART1_SR register (UART1_GetITStatus()) followed by a read operation to UART1_DR register (UART1_ReceiveData8() or UART1_ReceiveData9()).
  • RXNE pending bit can be also cleared by a read to the UART1_DR register (UART1_ReceiveData8() or UART1_ReceiveData9()).
  • TC (Transmit complete) pending bit can be cleared by software sequence: a read operation to UART1_SR register (UART1_GetITStatus()) followed by a write operation to UART1_DR register (UART1_SendData8() or UART1_SendData9()).
  • TXE pending bit is cleared only by a write to the UART1_DR register (UART1_SendData8() or UART1_SendData9()).
    Return values:
    None

Definition at line 775 of file stm8s_uart1.c.

References IS_UART1_CLEAR_IT_OK, UART1_CR4_LBDF, UART1_IT_RXNE, and UART1_SR_RXNE.

void UART1_Cmd ( FunctionalState NewState )

Enable the UART1 peripheral.

Parameters:
NewState : The new state of the UART Communication. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 184 of file stm8s_uart1.c.

References DISABLE, and UART1_CR1_UARTD.

void UART1_DeInit ( void )

Deinitializes the UART peripheral.

Parameters:
None
Return values:
None

Definition at line 53 of file stm8s_uart1.c.

References UART1_BRR1_RESET_VALUE, UART1_BRR2_RESET_VALUE, UART1_CR1_RESET_VALUE, UART1_CR2_RESET_VALUE, UART1_CR3_RESET_VALUE, UART1_CR4_RESET_VALUE, UART1_CR5_RESET_VALUE, UART1_GTR_RESET_VALUE, and UART1_PSCR_RESET_VALUE.

FlagStatus UART1_GetFlagStatus ( UART1_Flag_TypeDef UART1_FLAG )

Checks whether the specified UART1 flag is set or not.

Parameters:
UART1_FLAG specifies the flag to check. This parameter can be any of the UART1_Flag_TypeDef enumeration.
Return values:
FlagStatus (SET or RESET)

Definition at line 568 of file stm8s_uart1.c.

References IS_UART1_FLAG_OK, RESET, SET, UART1_FLAG_LBDF, and UART1_FLAG_SBK.

ITStatus UART1_GetITStatus ( UART1_IT_TypeDef UART1_IT )

Checks whether the specified UART1 interrupt has occurred or not.

Parameters:
UART1_IT,: Specifies the UART1 interrupt pending bit to check. This parameter can be one of the following values:
  • UART1_IT_LBDF: LIN Break detection interrupt
  • UART1_IT_TXE: Transmit Data Register empty interrupt
  • UART1_IT_TC: Transmission complete interrupt
  • UART1_IT_RXNE: Receive Data register not empty interrupt
  • UART1_IT_IDLE: Idle line detection interrupt
  • UART1_IT_OR: OverRun Error interrupt
  • UART1_IT_PE: Parity Error interrupt
Return values:
The new state of UART1_IT (SET or RESET).

Definition at line 675 of file stm8s_uart1.c.

References IS_UART1_GET_IT_OK, RESET, SET, UART1_IT_LBDF, and UART1_IT_PE.

void UART1_HalfDuplexCmd ( FunctionalState NewState )

Enables or disables the UART’s Half Duplex communication.

Parameters:
NewState new state of the UART Communication. This parameter can be: ENABLE or DISABLE.
Return values:
None

< UART1 Half Duplex Enable

< UART1 Half Duplex Disable

Definition at line 265 of file stm8s_uart1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART1_CR5_HDSEL.

void UART1_Init | ( | uint32_t | BaudRate,
 |  | UART1_WordLength_TypeDef | WordLength,
 |  | UART1_StopBits_TypeDef | StopBits,
 |  | UART1_Parity_TypeDef | Parity,
 |  | UART1_SyncMode_TypeDef | SyncMode,
 |  | UART1_Mode_TypeDef | Mode
 | ) |  |

Initializes the UART1 according to the specified parameters.

Note:
Configure in Push Pull or Open Drain mode the Tx pin by setting the correct I/O Port register according the product package and line configuration
Parameters:
BaudRate,: The baudrate.
WordLength : This parameter can be any of the UART1_WordLength_TypeDef enumeration.
StopBits,: This parameter can be any of the UART1_StopBits_TypeDef enumeration.
Parity,: This parameter can be any of the UART1_Parity_TypeDef enumeration.
SyncMode,: This parameter can be any of the UART1_SyncMode_TypeDef values.
Mode,: This parameter can be any of the UART1_Mode_TypeDef values
Return values:
None

Definition at line 90 of file stm8s_uart1.c.

References CLK_GetClockFreq(), IS_UART1_BAUDRATE_OK, IS_UART1_MODE_OK, IS_UART1_PARITY_OK, IS_UART1_STOPBITS_OK, IS_UART1_SYNCMODE_OK, IS_UART1_WORDLENGTH_OK, UART1_BRR1_DIVM, UART1_BRR2_DIVF, UART1_BRR2_DIVM, UART1_CR1_M, UART1_CR1_PCEN, UART1_CR1_PS, UART1_CR2_REN, UART1_CR2_TEN, UART1_CR3_CKEN, UART1_CR3_CPHA, UART1_CR3_CPOL, UART1_CR3_LBCL, UART1_CR3_STOP, UART1_MODE_RX_ENABLE, UART1_MODE_TX_ENABLE, and UART1_SYNCMODE_CLOCK_DISABLE.

void UART1_IrDACmd ( FunctionalState NewState )

Enables or disables the UART’s IrDA interface.

Parameters:
NewState new state of the IrDA mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 305 of file stm8s_uart1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART1_CR5_IREN.

void UART1_IrDAConfig ( UART1_IrDAMode_TypeDef UART1_IrDAMode )

Configures the UART’s IrDA interface.

Parameters:
UART1_IrDAMode specifies the IrDA mode. This parameter can be any of the UART1_IrDAMode_TypeDef values.
Return values:
None

Definition at line 285 of file stm8s_uart1.c.

References IS_UART1_IRDAMODE_OK, UART1_CR5_IRLP, and UART1_IRDAMODE_NORMAL.

void UART1_ITConfig | ( | UART1_IT_TypeDef | UART1_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified USART interrupts.

Parameters:
UART1_IT specifies the USART interrupt sources to be enabled or disabled. This parameter can be one of the following values:
  • UART1_IT_TXE: Transmit Data Register empty interrupt
  • UART1_IT_TC: Transmission complete interrupt
  • UART1_IT_RXNE_OR: Receive Data register not empty and Overrun interrupt
  • UART1_IT_IDLE: Idle line detection interrupt
  • USRT1_IT_ERR: Error interrupt
NewState new state of the specified USART interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

< Enable the Interrupt bits according to UART1_IT mask

< Disable the interrupt bits according to UART1_IT mask

Definition at line 211 of file stm8s_uart1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and IS_UART1_CONFIG_IT_OK.

void UART1_LINBreakDetectionConfig ( UART1_LINBreakDetectionLength_TypeDef UART1_LINBreakDetectionLength )

Sets the UART1 LIN Break detection length.

Parameters:
UART1_LINBreakDetectionLength specifies the LIN break detection length. This parameter can be any of the UART1_LINBreakDetectionLength_TypeDef values.
Return values:
None

Definition at line 329 of file stm8s_uart1.c.

References IS_UART1_LINBREAKDETECTIONLENGTH_OK, UART1_CR4_LBDL, and UART1_LINBREAKDETECTIONLENGTH_10BITS.

void UART1_LINCmd ( FunctionalState NewState )

Enables or disables the UART1’s LIN mode.

Parameters:
NewState is new state of the UART1 LIN mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 349 of file stm8s_uart1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART1_CR3_LINEN.

uint8_t UART1_ReceiveData8 ( void )

Returns the most recent received data by the UART1 peripheral.

Parameters:
None
Return values:
The received data.

Definition at line 451 of file stm8s_uart1.c.

uint16_t UART1_ReceiveData9 ( void )

Returns the most recent received data by the UART1 peripheral.

Parameters:
None
Return values:
The received data.

Definition at line 461 of file stm8s_uart1.c.

References UART1_CR1_R8.

void UART1_ReceiverWakeUpCmd ( FunctionalState NewState )

Determines if the UART1 is in mute mode or not.

Parameters:
NewState,: new state of the UART1 mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 430 of file stm8s_uart1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART1_CR2_RWU.

void UART1_SendBreak ( void )

Transmits break characters.

Parameters:
None
Return values:
None

Definition at line 501 of file stm8s_uart1.c.

References UART1_CR2_SBK.

void UART1_SendData8 ( uint8_t Data )

Transmits 8 bit data through the UART1 peripheral.

Parameters:
Data,: The data to transmit.
Return values:
None

Definition at line 474 of file stm8s_uart1.c.

void UART1_SendData9 ( uint16_t Data )

Transmits 9 bit data through the UART peripheral.

Parameters:
Data : The data to transmit. This parameter should be lower than 0x1FF.
Return values:
None

< Clear the transmit data bit 8 [8]

< Write the transmit data bit [8]

< Write the transmit data bit [0:7]

Definition at line 486 of file stm8s_uart1.c.

References UART1_CR1_T8.

void UART1_SetAddress ( uint8_t UART1_Address )

Sets the address of the UART1 node.

Parameters:
UART1_Address,: Indicates the address of the UART1 node.
Return values:
None

Definition at line 511 of file stm8s_uart1.c.

References IS_UART1_ADDRESS_OK, and UART1_CR4_ADD.

void UART1_SetGuardTime ( uint8_t UART1_GuardTime )

Sets the specified UART guard time.

Note:
SmartCard Mode should be Enabled
Parameters:
UART1_GuardTime,: specifies the guard time.
Return values:
None

Definition at line 528 of file stm8s_uart1.c.

void UART1_SetPrescaler ( uint8_t UART1_Prescaler )

Sets the system clock prescaler.

Note:
IrDA Low Power mode or smartcard mode should be enabled
This function is related to SmartCard and IrDa mode.
Parameters:
UART1_Prescaler,: specifies the prescaler clock. This parameter can be one of the following values:
IrDA Low Power Mode
The clock source is divided by the value given in the register (8 bits)
  • 0000 0000 Reserved
  • 0000 0001 divides the clock source by 1
  • 0000 0010 divides the clock source by 2
  • ...
Smart Card Mode
The clock source is divided by the value given in the register (5 significant bits) multiplied by 2
  • 0 0000 Reserved
  • 0 0001 divides the clock source by 2
  • 0 0010 divides the clock source by 4
  • 0 0011 divides the clock source by 6
  • ...
Return values:
None

Definition at line 556 of file stm8s_uart1.c.

void UART1_SmartCardCmd ( FunctionalState NewState )

Enables or disables the UART1 Smart Card mode.

Parameters:
NewState,: new state of the Smart Card mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 371 of file stm8s_uart1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART1_CR5_SCEN.

void UART1_SmartCardNACKCmd ( FunctionalState NewState )

Enables or disables NACK transmission.

Note:
This function is valid only for UART1 because is related to SmartCard mode.
Parameters:
NewState,: new state of the Smart Card mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 394 of file stm8s_uart1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART1_CR5_NACK.

void UART1_WakeUpConfig ( UART1_WakeUp_TypeDef UART1_WakeUp )

Selects the UART1 WakeUp method.

Parameters:
UART1_WakeUp,: specifies the UART1 wakeup method. This parameter can be any of the UART1_WakeUp_TypeDef values.
Return values:
None

Definition at line 416 of file stm8s_uart1.c.

References IS_UART1_WAKEUP_OK, and UART1_CR1_WAKE.


STM8S/A Standard Peripherals Drivers: UART2_Exported_Types

Enumerations
UART2_Exported_Types
STM8S_StdPeriph_Driver

Enumerations

enum UART2_Flag_TypeDef {
UART2_FLAG_TXE = (uint16_t)0x0080, UART2_FLAG_TC = (uint16_t)0x0040, UART2_FLAG_RXNE = (uint16_t)0x0020, UART2_FLAG_IDLE = (uint16_t)0x0010,
UART2_FLAG_OR_LHE = (uint16_t)0x0008, UART2_FLAG_NF = (uint16_t)0x0004, UART2_FLAG_FE = (uint16_t)0x0002, UART2_FLAG_PE = (uint16_t)0x0001,
UART2_FLAG_SBK = (uint16_t)0x0101, UART2_FLAG_LBDF = (uint16_t)0x0210, UART2_FLAG_LHDF = (uint16_t)0x0302, UART2_FLAG_LSF = (uint16_t)0x0301
}
UART2 Flag possible values. More...
enum | UART2_IrDAMode_TypeDef { UART2_IRDAMODE_NORMAL = (uint8_t)0x00, UART2_IRDAMODE_LOWPOWER = (uint8_t)0x01 }
UART2 Irda Modes. More...
enum UART2_IT_TypeDef {
UART2_IT_TXE = (uint16_t)0x0277, UART2_IT_TC = (uint16_t)0x0266, UART2_IT_RXNE = (uint16_t)0x0255, UART2_IT_IDLE = (uint16_t)0x0244,
UART2_IT_OR = (uint16_t)0x0235, UART2_IT_PE = (uint16_t)0x0100, UART2_IT_LBDF = (uint16_t)0x0346, UART2_IT_LHDF = (uint16_t)0x0412,
UART2_IT_RXNE_OR = (uint16_t)0x0205
}
UART2 Interrupt definition UART2_IT possible values Elements values convention: 0xZYX X: Position of the corresponding Interrupt. More...
enum | UART2_LinAutosync_TypeDef { UART2_LIN_AUTOSYNC_DISABLE = (uint8_t)0x00, UART2_LIN_AUTOSYNC_ENABLE = (uint8_t)0x01 }
UART2 automatic resynchronisation possible values. More...
enum | UART2_LINBreakDetectionLength_TypeDef { UART2_LINBREAKDETECTIONLENGTH_10BITS = (uint8_t)0x00, UART2_LINBREAKDETECTIONLENGTH_11BITS = (uint8_t)0x01 }
UART2 LIN Break detection length possible values. More...
enum | UART2_LinDivUp_TypeDef { UART2_LIN_DIVUP_LBRR1 = (uint8_t)0x00, UART2_LIN_DIVUP_NEXTRXNE = (uint8_t)0x01 }
UART2 Divider Update Method possible values. More...
enum | UART2_LinMode_TypeDef { UART2_LIN_MODE_MASTER = (uint8_t)0x00, UART2_LIN_MODE_SLAVE = (uint8_t)0x01 }
UART2 Mode possible values. More...
enum UART2_Mode_TypeDef {
UART2_MODE_RX_ENABLE = (uint8_t)0x08, UART2_MODE_TX_ENABLE = (uint8_t)0x04, UART2_MODE_TX_DISABLE = (uint8_t)0x80, UART2_MODE_RX_DISABLE = (uint8_t)0x40,
UART2_MODE_TXRX_ENABLE = (uint8_t)0x0C
}
UART2 Mode possible values. More...
enum | UART2_Parity_TypeDef { UART2_PARITY_NO = (uint8_t)0x00, UART2_PARITY_EVEN = (uint8_t)0x04, UART2_PARITY_ODD = (uint8_t)0x06 }
UART2 parity possible values. More...
enum | UART2_StopBits_TypeDef { UART2_STOPBITS_1 = (uint8_t)0x00, UART2_STOPBITS_0_5 = (uint8_t)0x10, UART2_STOPBITS_2 = (uint8_t)0x20, UART2_STOPBITS_1_5 = (uint8_t)0x30 }
UART2 stop bits possible values. More...
enum UART2_SyncMode_TypeDef {
UART2_SYNCMODE_CLOCK_DISABLE = (uint8_t)0x80, UART2_SYNCMODE_CLOCK_ENABLE = (uint8_t)0x08, UART2_SYNCMODE_CPOL_LOW = (uint8_t)0x40, UART2_SYNCMODE_CPOL_HIGH = (uint8_t)0x04,
UART2_SYNCMODE_CPHA_MIDDLE = (uint8_t)0x20, UART2_SYNCMODE_CPHA_BEGINING = (uint8_t)0x02, UART2_SYNCMODE_LASTBIT_DISABLE = (uint8_t)0x10, UART2_SYNCMODE_LASTBIT_ENABLE = (uint8_t)0x01
}
UART2 Synchrone modes. More...
enum | UART2_WakeUp_TypeDef { UART2_WAKEUP_IDLELINE = (uint8_t)0x00, UART2_WAKEUP_ADDRESSMARK = (uint8_t)0x08 }
UART2 WakeUP Modes. More...
enum | UART2_WordLength_TypeDef { UART2_WORDLENGTH_8D = (uint8_t)0x00, UART2_WORDLENGTH_9D = (uint8_t)0x10 }
UART2 Word length possible values. More...

Enumeration Type Documentation

enum UART2_Flag_TypeDef

UART2 Flag possible values.

Enumerator:
UART2_FLAG_TXE

Transmit Data Register Empty flag

UART2_FLAG_TC

Transmission Complete flag

UART2_FLAG_RXNE

Read Data Register Not Empty flag

UART2_FLAG_IDLE

Idle line detected flag

UART2_FLAG_OR_LHE

OverRun error flag

UART2_FLAG_NF

Noise error flag

UART2_FLAG_FE

Framing Error flag

UART2_FLAG_PE

Parity Error flag

UART2_FLAG_SBK

Send Break Complete interrupt flag.

UART2_FLAG_LBDF

LIN Break Detection Flag.

UART2_FLAG_LHDF

LIN Header Detection Flag.

UART2_FLAG_LSF

LIN Sync Field Flag.

Definition at line 139 of file stm8s_uart2.h.

enum UART2_IrDAMode_TypeDef

UART2 Irda Modes.

Enumerator:
UART2_IRDAMODE_NORMAL

0x00 Irda Normal Mode

UART2_IRDAMODE_LOWPOWER

0x01 Irda Low Power Mode

Definition at line 49 of file stm8s_uart2.h.

enum UART2_IT_TypeDef

UART2 Interrupt definition UART2_IT possible values Elements values convention: 0xZYX X: Position of the corresponding Interrupt.

  • For the following values, X means the interrupt position in the CR2 register. UART2_IT_TXE UART2_IT_TC UART2_IT_RXNE UART2_IT_IDLE UART2_IT_OR
  • For the UART2_IT_PE value, X means the flag position in the CR1 register.
  • For the UART2_IT_LBDF value, X means the flag position in the CR4 register.
  • For the UART2_IT_LHDF value, X means the flag position in the CR6 register. Y: Flag position

For the following values, Y means the flag (pending bit) position in the SR register. UART2_IT_TXE UART2_IT_TC UART2_IT_RXNE UART2_IT_IDLE UART2_IT_OR UART2_IT_PE

  • For the UART2_IT_LBDF value, Y means the flag position in the CR4 register.
  • For the UART2_IT_LHDF value, Y means the flag position in the CR6 register. Z: Register index: indicate in which register the dedicated interrupt source is:
  • 1==> CR1 register
  • 2==> CR2 register
  • 3==> CR4 register
  • 4==> CR6 register
Enumerator:
UART2_IT_TXE

Transmit interrupt.

UART2_IT_TC

Transmission Complete interrupt.

UART2_IT_RXNE

Data Register Not Empty interrupt.

UART2_IT_IDLE

Idle line detected interrupt.

UART2_IT_OR

OverRun error interrupt.

UART2_IT_PE

Parity Error interrupt.

UART2_IT_LBDF

LIN Break Detection interrupt.

UART2_IT_LHDF

LIN Header Detection interrupt.

UART2_IT_RXNE_OR

Receive/Overrun interrupt

Definition at line 185 of file stm8s_uart2.h.

enum UART2_LinAutosync_TypeDef

UART2 automatic resynchronisation possible values.

Enumerator:
UART2_LIN_AUTOSYNC_DISABLE

LIN Autosynchronization Disable.

UART2_LIN_AUTOSYNC_ENABLE

LIN Autosynchronization Enable.

Definition at line 97 of file stm8s_uart2.h.

enum UART2_LINBreakDetectionLength_TypeDef

UART2 LIN Break detection length possible values.

Enumerator:
UART2_LINBREAKDETECTIONLENGTH_10BITS

0x01 10 bits Lin Break detection

UART2_LINBREAKDETECTIONLENGTH_11BITS

0x02 11 bits Lin Break detection

Definition at line 66 of file stm8s_uart2.h.

enum UART2_LinDivUp_TypeDef

UART2 Divider Update Method possible values.

Enumerator:
UART2_LIN_DIVUP_LBRR1

LIN LDIV is updated as soon as LBRR1 is written.

UART2_LIN_DIVUP_NEXTRXNE

LIN LDIV is updated at the next received character.

Definition at line 103 of file stm8s_uart2.h.

enum UART2_LinMode_TypeDef

UART2 Mode possible values.

Enumerator:
UART2_LIN_MODE_MASTER

LIN Master Mode.

UART2_LIN_MODE_SLAVE

LIN Slave Mode.

Definition at line 91 of file stm8s_uart2.h.

enum UART2_Mode_TypeDef

UART2 Mode possible values.

Enumerator:
UART2_MODE_RX_ENABLE

0x08 Receive Enable

UART2_MODE_TX_ENABLE

0x04 Transmit Enable

UART2_MODE_TX_DISABLE

0x80 Transmit Disable

UART2_MODE_RX_DISABLE

0x40 Single-wire Half-duplex mode

UART2_MODE_TXRX_ENABLE

0x0C Transmit Enable and Receive Enable

Definition at line 130 of file stm8s_uart2.h.

enum UART2_Parity_TypeDef

UART2 parity possible values.

Enumerator:
UART2_PARITY_NO

No Parity.

UART2_PARITY_EVEN

Even Parity.

UART2_PARITY_ODD

Odd Parity.

Definition at line 84 of file stm8s_uart2.h.

enum UART2_StopBits_TypeDef

UART2 stop bits possible values.

Enumerator:
UART2_STOPBITS_1

One stop bit is transmitted at the end of frame.

UART2_STOPBITS_0_5

Half stop bits is transmitted at the end of frame.

UART2_STOPBITS_2

Two stop bits are transmitted at the end of frame.

UART2_STOPBITS_1_5

One and half stop bits.

Definition at line 74 of file stm8s_uart2.h.

enum UART2_SyncMode_TypeDef

UART2 Synchrone modes.

Enumerator:
UART2_SYNCMODE_CLOCK_DISABLE

0x80 Sync mode Disable, SLK pin Disable

UART2_SYNCMODE_CLOCK_ENABLE

0x08 Sync mode Enable, SLK pin Enable

UART2_SYNCMODE_CPOL_LOW

0x40 Steady low value on SCLK pin outside transmission window

UART2_SYNCMODE_CPOL_HIGH

0x04 Steady high value on SCLK pin outside transmission window

UART2_SYNCMODE_CPHA_MIDDLE

0x20 SCLK clock line activated in middle of data bit

UART2_SYNCMODE_CPHA_BEGINING

0x02 SCLK clock line activated at beginning of data bit

UART2_SYNCMODE_LASTBIT_DISABLE

0x10 The clock pulse of the last data bit is not output to the SCLK pin

UART2_SYNCMODE_LASTBIT_ENABLE

0x01 The clock pulse of the last data bit is output to the SCLK pin

Definition at line 110 of file stm8s_uart2.h.

enum UART2_WakeUp_TypeDef

UART2 WakeUP Modes.

Enumerator:
UART2_WAKEUP_IDLELINE

0x01 Idle Line wake up

UART2_WAKEUP_ADDRESSMARK

0x02 Address Mark wake up

Definition at line 58 of file stm8s_uart2.h.

enum UART2_WordLength_TypeDef

UART2 Word length possible values.

Enumerator:
UART2_WORDLENGTH_8D

0x00 8 bits Data

UART2_WORDLENGTH_9D

0x10 9 bits Data

Definition at line 123 of file stm8s_uart2.h.


STM8S/A Standard Peripherals Drivers: UART2_Private_Macros

Defines
UART2_Private_Macros
STM8S_StdPeriph_Driver

Defines

#define | IS_UART2_ADDRESS_OK(node) ((node) < UART2_ADDRESS_MAX )
#define | IS_UART2_AUTOSYNC_OK(AutosyncMode)
Macro used by the assert_param function in order to check the LIN automatic resynchronization mode.
#define | IS_UART2_BAUDRATE_OK(NUM) ((NUM) <= (uint32_t)625000)
Macro used by the assert_param function in order to check the maximum baudrate value.
#define | IS_UART2_CLEAR_FLAG_OK(Flag)
Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs that can be cleared by writing 0.
#define | IS_UART2_CLEAR_IT_OK(ITPendingBit)
Macro used by the assert function in order to check the different sensitivity values for the pending bit that can be cleared by writing 0.
#define | IS_UART2_CONFIG_IT_OK(Interrupt)
Macro used by the assert_param function in order to check the different sensitivity values for the Interrupts.
#define | IS_UART2_DIVUP_OK(DivupMethod)
Macro used by the assert_param function in order to check the LIN divider update method.
#define | IS_UART2_FLAG_OK(Flag)
Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs.
#define | IS_UART2_GET_IT_OK(ITPendingBit)
Macro used by the assert function in order to check the different sensitivity values for the pending bit.
#define | IS_UART2_IRDAMODE_OK(IrDAMode)
Macro used by the assert_param function in order to check the different sensitivity values for the IrDAModes.
#define | IS_UART2_LINBREAKDETECTIONLENGTH_OK(LINBreakDetectionLength)
Macro used by the assert_param function in order to check the different sensitivity values for the LINBreakDetectionLengths.
#define | IS_UART2_MODE_OK(Mode)
Macro used by the assert function to check the different functions parameters.
#define | IS_UART2_PARITY_OK(Parity)
Macro used by the assert_param function in order to check the different sensitivity values for the Paritys.
#define | IS_UART2_SLAVE_OK(Mode)
Macro used by the assert_param function in order to check the LIN mode.
#define | IS_UART2_STOPBITS_OK(StopBit)
Macro used by the assert_param function in order to check the different sensitivity values for the UART2_StopBits.
#define | IS_UART2_SYNCMODE_OK(SyncMode)
Macro used by the assert_param function in order to check the different sensitivity values for the SyncModes; it should exclude values such as UART2_CLOCK_ENABLE|UART2_CLOCK_DISABLE.
#define | IS_UART2_WAKEUP_OK(WakeUp)
Macro used by the assert_param function in order to check the different sensitivity values for the WakeUps.
#define | IS_UART2_WORDLENGTH_OK(WordLength)
Macro used by the assert_param function in order to check the different sensitivity values for the WordLengths.
#define | UART2_ADDRESS_MAX ((uint8_t)16)
Macro used by the assert_param function in order to check the address of the UART2 or UART node.

Define Documentation

#define IS_UART2_ADDRESS_OK ( node ) ((node) < UART2_ADDRESS_MAX )

Definition at line 369 of file stm8s_uart2.h.

Referenced by UART2_SetAddress().

#define IS_UART2_AUTOSYNC_OK ( AutosyncMode )
Value:
(((AutosyncMode) ==  UART2_LIN_AUTOSYNC_ENABLE) || \
   ((AutosyncMode) == UART2_LIN_AUTOSYNC_DISABLE))

Macro used by the assert_param function in order to check the LIN automatic resynchronization mode.

Definition at line 382 of file stm8s_uart2.h.

Referenced by UART2_LINConfig().

#define IS_UART2_BAUDRATE_OK ( NUM ) ((NUM) <= (uint32_t)625000)

Macro used by the assert_param function in order to check the maximum baudrate value.

Definition at line 361 of file stm8s_uart2.h.

Referenced by UART2_Init().

#define IS_UART2_CLEAR_FLAG_OK ( Flag )
Value:
(((Flag) == UART2_FLAG_RXNE) || \
   ((Flag) == UART2_FLAG_LHDF) || \
   ((Flag) == UART2_FLAG_LSF) || \
   ((Flag) == UART2_FLAG_LBDF))

Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs that can be cleared by writing 0.

Definition at line 272 of file stm8s_uart2.h.

Referenced by UART2_ClearFlag().

#define IS_UART2_CLEAR_IT_OK ( ITPendingBit )
Value:
(((ITPendingBit) == UART2_IT_RXNE) || \
   ((ITPendingBit) == UART2_IT_LHDF) || \
   ((ITPendingBit) == UART2_IT_LBDF))

Macro used by the assert function in order to check the different sensitivity values for the pending bit that can be cleared by writing 0.

Definition at line 310 of file stm8s_uart2.h.

Referenced by UART2_ClearITPendingBit().

#define IS_UART2_CONFIG_IT_OK ( Interrupt )
Value:
(((Interrupt) == UART2_IT_PE) || \
   ((Interrupt) == UART2_IT_TXE) || \
   ((Interrupt) == UART2_IT_TC) || \
   ((Interrupt) == UART2_IT_RXNE_OR ) || \
   ((Interrupt) == UART2_IT_IDLE) || \
   ((Interrupt) == UART2_IT_LHDF) || \
   ((Interrupt) == UART2_IT_LBDF))

Macro used by the assert_param function in order to check the different sensitivity values for the Interrupts.

Definition at line 283 of file stm8s_uart2.h.

Referenced by UART2_ITConfig().

#define IS_UART2_DIVUP_OK ( DivupMethod )
Value:
(((DivupMethod) == UART2_LIN_DIVUP_LBRR1) || \
   ((DivupMethod) == UART2_LIN_DIVUP_NEXTRXNE))

Macro used by the assert_param function in order to check the LIN divider update method.

Definition at line 389 of file stm8s_uart2.h.

Referenced by UART2_LINConfig().

#define IS_UART2_FLAG_OK ( Flag )
Value:
(((Flag) == UART2_FLAG_TXE) || \
   ((Flag) == UART2_FLAG_TC)  || \
   ((Flag) == UART2_FLAG_RXNE) || \
   ((Flag) == UART2_FLAG_IDLE) || \
   ((Flag) == UART2_FLAG_OR_LHE) || \
   ((Flag) == UART2_FLAG_NF) || \
   ((Flag) == UART2_FLAG_FE) || \
   ((Flag) == UART2_FLAG_PE) || \
   ((Flag) == UART2_FLAG_SBK) || \
   ((Flag) == UART2_FLAG_LSF) || \
   ((Flag) == UART2_FLAG_LHDF) || \
   ((Flag) == UART2_FLAG_LBDF))

Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs.

Definition at line 253 of file stm8s_uart2.h.

Referenced by UART2_GetFlagStatus().

#define IS_UART2_GET_IT_OK ( ITPendingBit )
Value:
(((ITPendingBit) == UART2_IT_TXE)  || \
   ((ITPendingBit) == UART2_IT_TC)   || \
   ((ITPendingBit) == UART2_IT_RXNE) || \
   ((ITPendingBit) == UART2_IT_IDLE) || \
   ((ITPendingBit) == UART2_IT_OR)  || \
   ((ITPendingBit) == UART2_IT_LBDF)  || \
   ((ITPendingBit) == UART2_IT_LHDF)  || \
   ((ITPendingBit) == UART2_IT_PE))

Macro used by the assert function in order to check the different sensitivity values for the pending bit.

Definition at line 296 of file stm8s_uart2.h.

Referenced by UART2_GetITStatus().

#define IS_UART2_IRDAMODE_OK ( IrDAMode )
Value:
(((IrDAMode) == UART2_IRDAMODE_LOWPOWER) || \
   ((IrDAMode) == UART2_IRDAMODE_NORMAL))

Macro used by the assert_param function in order to check the different sensitivity values for the IrDAModes.

Definition at line 320 of file stm8s_uart2.h.

Referenced by UART2_IrDAConfig().

#define IS_UART2_LINBREAKDETECTIONLENGTH_OK ( LINBreakDetectionLength )
Value:
(((LINBreakDetectionLength) == UART2_LINBREAKDETECTIONLENGTH_10BITS) || \
   ((LINBreakDetectionLength) == UART2_LINBREAKDETECTIONLENGTH_11BITS))

Macro used by the assert_param function in order to check the different sensitivity values for the LINBreakDetectionLengths.

Definition at line 336 of file stm8s_uart2.h.

Referenced by UART2_LINBreakDetectionConfig().

#define IS_UART2_MODE_OK ( Mode )
Value:
(((Mode) == (uint8_t)UART2_MODE_RX_ENABLE) || \
   ((Mode) == (uint8_t)UART2_MODE_RX_DISABLE) || \
   ((Mode) == (uint8_t)UART2_MODE_TX_ENABLE) || \
   ((Mode) == (uint8_t)UART2_MODE_TX_DISABLE) || \
   ((Mode) == (uint8_t)UART2_MODE_TXRX_ENABLE) || \
   ((Mode) == (uint8_t)((uint8_t)UART2_MODE_TX_ENABLE|(uint8_t)UART2_MODE_RX_ENABLE)) || \
   ((Mode) == (uint8_t)((uint8_t)UART2_MODE_TX_ENABLE|(uint8_t)UART2_MODE_RX_DISABLE)) || \
   ((Mode) == (uint8_t)((uint8_t)UART2_MODE_TX_DISABLE|(uint8_t)UART2_MODE_RX_DISABLE)) || \
   ((Mode) == (uint8_t)((uint8_t)UART2_MODE_TX_DISABLE|(uint8_t)UART2_MODE_RX_ENABLE)))

Macro used by the assert function to check the different functions parameters.

Macro used by the assert_param function in order to check the different sensitivity values for the MODEs possible combination should be one of the following.

Definition at line 219 of file stm8s_uart2.h.

Referenced by UART2_Init().

#define IS_UART2_PARITY_OK ( Parity )
Value:
(((Parity) == UART2_PARITY_NO) || \
                                    ((Parity) == UART2_PARITY_EVEN) || \
                                    ((Parity) == UART2_PARITY_ODD ))

Macro used by the assert_param function in order to check the different sensitivity values for the Paritys.

Definition at line 353 of file stm8s_uart2.h.

Referenced by UART2_Init().

#define IS_UART2_SLAVE_OK ( Mode )
Value:
(((Mode) == UART2_LIN_MODE_MASTER) || \
   ((Mode) == UART2_LIN_MODE_SLAVE))

Macro used by the assert_param function in order to check the LIN mode.

Definition at line 374 of file stm8s_uart2.h.

Referenced by UART2_LINConfig().

#define IS_UART2_STOPBITS_OK ( StopBit )
Value:
(((StopBit) == UART2_STOPBITS_1) || \
                                       ((StopBit) == UART2_STOPBITS_0_5) || \
                                       ((StopBit) == UART2_STOPBITS_2) || \
                                       ((StopBit) == UART2_STOPBITS_1_5 ))

Macro used by the assert_param function in order to check the different sensitivity values for the UART2_StopBits.

Definition at line 344 of file stm8s_uart2.h.

Referenced by UART2_Init().

#define IS_UART2_SYNCMODE_OK ( SyncMode )
Value:
(!((((SyncMode)&(((uint8_t)UART2_SYNCMODE_CLOCK_ENABLE)|((uint8_t)UART2_SYNCMODE_CLOCK_DISABLE))) == (((uint8_t)UART2_SYNCMODE_CLOCK_ENABLE)|((uint8_t)UART2_SYNCMODE_CLOCK_DISABLE))) || \
     (((SyncMode)&(((uint8_t)UART2_SYNCMODE_CPOL_LOW )|((uint8_t)UART2_SYNCMODE_CPOL_HIGH))) == (((uint8_t)UART2_SYNCMODE_CPOL_LOW )|((uint8_t)UART2_SYNCMODE_CPOL_HIGH))) || \
     (((SyncMode)&(((uint8_t)UART2_SYNCMODE_CPHA_MIDDLE)|((uint8_t)UART2_SYNCMODE_CPHA_BEGINING))) == (((uint8_t)UART2_SYNCMODE_CPHA_MIDDLE)|((uint8_t)UART2_SYNCMODE_CPHA_BEGINING))) || \
     (((SyncMode)&(((uint8_t)UART2_SYNCMODE_LASTBIT_DISABLE)|((uint8_t)UART2_SYNCMODE_LASTBIT_ENABLE))) == (((uint8_t)UART2_SYNCMODE_LASTBIT_DISABLE)|((uint8_t)UART2_SYNCMODE_LASTBIT_ENABLE)))))

Macro used by the assert_param function in order to check the different sensitivity values for the SyncModes; it should exclude values such as UART2_CLOCK_ENABLE|UART2_CLOCK_DISABLE.

Definition at line 243 of file stm8s_uart2.h.

Referenced by UART2_Init().

#define IS_UART2_WAKEUP_OK ( WakeUp )
Value:
(((WakeUp) == UART2_WAKEUP_IDLELINE) || \
   ((WakeUp) == UART2_WAKEUP_ADDRESSMARK))

Macro used by the assert_param function in order to check the different sensitivity values for the WakeUps.

Definition at line 328 of file stm8s_uart2.h.

Referenced by UART2_WakeUpConfig().

#define IS_UART2_WORDLENGTH_OK ( WordLength )
Value:
(((WordLength) == UART2_WORDLENGTH_8D) || \
   ((WordLength) == UART2_WORDLENGTH_9D))

Macro used by the assert_param function in order to check the different sensitivity values for the WordLengths.

Definition at line 234 of file stm8s_uart2.h.

Referenced by UART2_Init().

#define UART2_ADDRESS_MAX ((uint8_t)16)

Macro used by the assert_param function in order to check the address of the UART2 or UART node.

Definition at line 368 of file stm8s_uart2.h.


STM8S/A Standard Peripherals Drivers: UART2_Exported_Functions

Functions
UART2_Exported_Functions
STM8S_StdPeriph_Driver

Functions

void | UART2_ClearFlag (UART2_Flag_TypeDef UART2_FLAG)
Clears the UART2 flags.
void | UART2_ClearITPendingBit (UART2_IT_TypeDef UART2_IT)
Clears the UART2 pending flags.
void | UART2_Cmd (FunctionalState NewState)
Enable the UART2 peripheral.
void | UART2_DeInit (void)
Deinitializes the UART peripheral.
FlagStatus | UART2_GetFlagStatus (UART2_Flag_TypeDef UART2_FLAG)
Checks whether the specified UART2 flag is set or not.
ITStatus | UART2_GetITStatus (UART2_IT_TypeDef UART2_IT)
Checks whether the specified UART2 interrupt has occurred or not.
void | UART2_HalfDuplexCmd (FunctionalState NewState)
void | UART2_Init (uint32_t BaudRate, UART2_WordLength_TypeDef WordLength, UART2_StopBits_TypeDef StopBits, UART2_Parity_TypeDef Parity, UART2_SyncMode_TypeDef SyncMode, UART2_Mode_TypeDef Mode)
Initializes the UART2 according to the specified parameters.
void | UART2_IrDACmd (FunctionalState NewState)
Enables or disables the UART2’s IrDA interface.
void | UART2_IrDAConfig (UART2_IrDAMode_TypeDef UART2_IrDAMode)
Configures the UART2’s IrDA interface.
void | UART2_ITConfig (UART2_IT_TypeDef UART2_IT, FunctionalState NewState)
Enables or disables the specified UART2 interrupts.
void | UART2_LINBreakDetectionConfig (UART2_LINBreakDetectionLength_TypeDef UART2_LINBreakDetectionLength)
Sets the UART2 LIN Break detection length.
void | UART2_LINCmd (FunctionalState NewState)
Enables or disables the UART2 LIN mode.
void | UART2_LINConfig (UART2_LinMode_TypeDef UART2_Mode, UART2_LinAutosync_TypeDef UART2_Autosync, UART2_LinDivUp_TypeDef UART2_DivUp)
Configure the UART2 peripheral.
uint8_t | UART2_ReceiveData8 (void)
Returns the most recent received data by the UART2 peripheral.
uint16_t | UART2_ReceiveData9 (void)
Returns the most recent received data by the UART2 peripheral.
void | UART2_ReceiverWakeUpCmd (FunctionalState NewState)
Determines if the UART2 is in mute mode or not.
void | UART2_SendBreak (void)
Transmits break characters.
void | UART2_SendData8 (uint8_t Data)
Transmits 8 bit data through the UART2 peripheral.
void | UART2_SendData9 (uint16_t Data)
Transmits 9 bit data through the UART2 peripheral.
void | UART2_SetAddress (uint8_t UART2_Address)
Sets the address of the UART2 node.
void | UART2_SetGuardTime (uint8_t UART2_GuardTime)
Sets the specified UART2 guard time.
void | UART2_SetPrescaler (uint8_t UART2_Prescaler)
Sets the system clock prescaler.
void | UART2_SmartCardCmd (FunctionalState NewState)
Enables or disables the UART2 Smart Card mode.
void | UART2_SmartCardNACKCmd (FunctionalState NewState)
Enables or disables NACK transmission.
void | UART2_WakeUpConfig (UART2_WakeUp_TypeDef UART2_WakeUp)
Selects the UART2 WakeUp method.

Function Documentation

void UART2_ClearFlag ( UART2_Flag_TypeDef UART2_FLAG )

Clears the UART2 flags.

Parameters:
UART2_FLAG specifies the flag to clear This parameter can be any combination of the following values:
  • UART2_FLAG_LBDF: LIN Break detection flag.
  • UART2_FLAG_LHDF: LIN Header detection flag.
  • UART2_FLAG_LSF: LIN synchrone field flag.
  • UART2_FLAG_RXNE: Receive data register not empty flag.
Note:
:
  • PE (Parity error), FE (Framing error), NE (Noise error), OR (OverRun error) and IDLE (Idle line detected) flags are cleared by software sequence: a read operation to UART2_SR register (UART2_GetFlagStatus())followed by a read operation to UART2_DR register(UART2_ReceiveData8() or UART2_ReceiveData9()).
  • RXNE flag can be also cleared by a read to the UART2_DR register (UART2_ReceiveData8()or UART2_ReceiveData9()).
  • TC flag can be also cleared by software sequence: a read operation to UART2_SR register (UART2_GetFlagStatus()) followed by a write operation to UART2_DR register (UART2_SendData8() or UART2_SendData9()).
  • TXE flag is cleared only by a write to the UART2_DR register (UART2_SendData8() or UART2_SendData9()).
  • SBK flag is cleared during the stop bit of break.
    Return values:
    None

Definition at line 699 of file stm8s_uart2.c.

References IS_UART2_CLEAR_FLAG_OK, UART2_CR4_LBDF, UART2_CR6_LHDF, UART2_CR6_LSF, UART2_FLAG_LBDF, UART2_FLAG_LHDF, UART2_FLAG_RXNE, and UART2_SR_RXNE.

void UART2_ClearITPendingBit ( UART2_IT_TypeDef UART2_IT )

Clears the UART2 pending flags.

Parameters:
UART2_IT specifies the pending bit to clear This parameter can be one of the following values:
  • UART2_IT_LBDF: LIN Break detection interrupt
  • UART2_IT_LHDF: LIN Header detection interrupt
  • UART2_IT_RXNE: Receive Data register not empty interrupt.
Note:
  • PE (Parity error), FE (Framing error), NE (Noise error), OR (OverRun error) and IDLE (Idle line detected) pending bits are cleared by software sequence: a read operation to UART2_SR register (UART2_GetITStatus()) followed by a read operation to UART2_DR register (UART2_ReceiveData8() or UART2_ReceiveData9()).
  • RXNE pending bit can be also cleared by a read to the UART2_DR register (UART2_ReceiveData8() or UART2_ReceiveData9()).
  • TC (Transmit complete) pending bit can be cleared by software sequence: a read operation to UART2_SR register (UART2_GetITStatus()) followed by a write operation to UART2_DR register (UART2_SendData8()or UART2_SendData9()).
  • TXE pending bit is cleared only by a write to the UART2_DR register (UART2_SendData8() or UART2_SendData9()).
    Return values:
    None

Definition at line 852 of file stm8s_uart2.c.

References IS_UART2_CLEAR_IT_OK, UART2_CR4_LBDF, UART2_CR6_LHDF, UART2_IT_LBDF, UART2_IT_RXNE, and UART2_SR_RXNE.

void UART2_Cmd ( FunctionalState NewState )

Enable the UART2 peripheral.

Parameters:
NewState : The new state of the UART Communication. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 181 of file stm8s_uart2.c.

References DISABLE, and UART2_CR1_UARTD.

void UART2_DeInit ( void )

Deinitializes the UART peripheral.

Parameters:
None
Return values:
None

Definition at line 53 of file stm8s_uart2.c.

References UART2_BRR1_RESET_VALUE, UART2_BRR2_RESET_VALUE, UART2_CR1_RESET_VALUE, UART2_CR2_RESET_VALUE, UART2_CR3_RESET_VALUE, UART2_CR4_RESET_VALUE, UART2_CR5_RESET_VALUE, and UART2_CR6_RESET_VALUE.

FlagStatus UART2_GetFlagStatus ( UART2_Flag_TypeDef UART2_FLAG )

Checks whether the specified UART2 flag is set or not.

Parameters:
UART2_FLAG specifies the flag to check. This parameter can be any of the UART2_Flag_TypeDef enumeration.
Return values:
FlagStatus (SET or RESET)

Definition at line 606 of file stm8s_uart2.c.

References IS_UART2_FLAG_OK, RESET, SET, UART2_FLAG_LBDF, UART2_FLAG_LHDF, UART2_FLAG_LSF, and UART2_FLAG_SBK.

ITStatus UART2_GetITStatus ( UART2_IT_TypeDef UART2_IT )

Checks whether the specified UART2 interrupt has occurred or not.

Parameters:
UART2_IT,: Specifies the UART2 interrupt pending bit to check. This parameter can be one of the following values:
  • UART2_IT_LBDF: LIN Break detection interrupt
  • UART2_IT_TXE: Transmit Data Register empty interrupt
  • UART2_IT_TC: Transmission complete interrupt
  • UART2_IT_RXNE: Receive Data register not empty interrupt
  • UART2_IT_IDLE: Idle line detection interrupt
  • UART2_IT_OR: OverRun Error interrupt
  • UART2_IT_PE: Parity Error interrupt
Return values:
The state of UART2_IT (SET or RESET).

Definition at line 738 of file stm8s_uart2.c.

References IS_UART2_GET_IT_OK, RESET, SET, UART2_IT_LBDF, UART2_IT_LHDF, and UART2_IT_PE.

void UART2_HalfDuplexCmd ( FunctionalState NewState )
void UART2_Init | ( | uint32_t | BaudRate,
 |  | UART2_WordLength_TypeDef | WordLength,
 |  | UART2_StopBits_TypeDef | StopBits,
 |  | UART2_Parity_TypeDef | Parity,
 |  | UART2_SyncMode_TypeDef | SyncMode,
 |  | UART2_Mode_TypeDef | Mode
 | ) |  |

Initializes the UART2 according to the specified parameters.

Parameters:
BaudRate,: The baudrate.
WordLength : This parameter can be any of the UART2_WordLength_TypeDef enumeration.
StopBits,: This parameter can be any of the UART2_StopBits_TypeDef enumeration.
Parity,: This parameter can be any of the UART2_Parity_TypeDef enumeration.
SyncMode,: This parameter can be any of the UART2_SyncMode_TypeDef values.
Mode,: This parameter can be any of the UART2_Mode_TypeDef values
Return values:
None

Definition at line 85 of file stm8s_uart2.c.

References CLK_GetClockFreq(), IS_UART2_BAUDRATE_OK, IS_UART2_MODE_OK, IS_UART2_PARITY_OK, IS_UART2_STOPBITS_OK, IS_UART2_SYNCMODE_OK, IS_UART2_WORDLENGTH_OK, UART2_BRR1_DIVM, UART2_BRR2_DIVF, UART2_BRR2_DIVM, UART2_CR1_M, UART2_CR1_PCEN, UART2_CR1_PS, UART2_CR2_REN, UART2_CR2_TEN, UART2_CR3_CKEN, UART2_CR3_CPHA, UART2_CR3_CPOL, UART2_CR3_LBCL, UART2_CR3_STOP, UART2_MODE_RX_ENABLE, UART2_MODE_TX_ENABLE, and UART2_SYNCMODE_CLOCK_DISABLE.

void UART2_IrDACmd ( FunctionalState NewState )

Enables or disables the UART2’s IrDA interface.

Parameters:
NewState new state of the IrDA mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 292 of file stm8s_uart2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART2_CR5_IREN.

void UART2_IrDAConfig ( UART2_IrDAMode_TypeDef UART2_IrDAMode )

Configures the UART2’s IrDA interface.

Parameters:
UART2_IrDAMode specifies the IrDA mode. This parameter can be any of the UART2_IrDAMode_TypeDef values.
Return values:
None

Definition at line 272 of file stm8s_uart2.c.

References IS_UART2_IRDAMODE_OK, UART2_CR5_IRLP, and UART2_IRDAMODE_NORMAL.

void UART2_ITConfig | ( | UART2_IT_TypeDef | UART2_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified UART2 interrupts.

Parameters:
UART2_IT specifies the UART2 interrupt sources to be enabled or disabled. This parameter can be one of the following values:
  • UART2_IT_LBDF: LIN Break detection interrupt
  • UART2_IT_LHDF: LIN Break detection interrupt
  • UART2_IT_TXE: Transmit Data Register empty interrupt
  • UART2_IT_TC: Transmission complete interrupt
  • UART2_IT_RXNE_OR: Receive Data register not empty/Over run error interrupt
  • UART2_IT_IDLE: Idle line detection interrupt
  • UART2_IT_PE: Parity Error interrupt
NewState new state of the specified UART2 interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 210 of file stm8s_uart2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and IS_UART2_CONFIG_IT_OK.

void UART2_LINBreakDetectionConfig ( UART2_LINBreakDetectionLength_TypeDef UART2_LINBreakDetectionLength )

Sets the UART2 LIN Break detection length.

Parameters:
UART2_LINBreakDetectionLength specifies the LIN break detection length. This parameter can be any of the UART2_LINBreakDetectionLength_TypeDef values.
Return values:
None

Definition at line 316 of file stm8s_uart2.c.

References IS_UART2_LINBREAKDETECTIONLENGTH_OK, UART2_CR4_LBDL, and UART2_LINBREAKDETECTIONLENGTH_10BITS.

void UART2_LINCmd ( FunctionalState NewState )

Enables or disables the UART2 LIN mode.

Parameters:
NewState is new state of the UART2 LIN mode. This parameter can be ENABLE or DISABLE
Return values:
None

Definition at line 384 of file stm8s_uart2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART2_CR3_LINEN.

void UART2_LINConfig | ( | UART2_LinMode_TypeDef | UART2_Mode,
 |  | UART2_LinAutosync_TypeDef | UART2_Autosync,
 |  | UART2_LinDivUp_TypeDef | UART2_DivUp
 | ) |  |

Configure the UART2 peripheral.

Parameters:
UART2_Mode | specifies the LIN mode. This parameter can be any of the UART2_LinMode_TypeDef values.
UART2_Autosync | specifies the LIN automatic resynchronization mode. This parameter can be any of the UART2_LinAutosync_TypeDef values.
UART2_DivUp | specifies the LIN divider update method. This parameter can be any of the UART2_LinDivUp_TypeDef values.
Return values:
None

Definition at line 341 of file stm8s_uart2.c.

References IS_UART2_AUTOSYNC_OK, IS_UART2_DIVUP_OK, IS_UART2_SLAVE_OK, UART2_CR6_LASE, UART2_CR6_LDUM, UART2_CR6_LSLV, UART2_LIN_AUTOSYNC_DISABLE, UART2_LIN_DIVUP_LBRR1, and UART2_LIN_MODE_MASTER.

uint8_t UART2_ReceiveData8 ( void )

Returns the most recent received data by the UART2 peripheral.

Parameters:
None
Return values:
Received Data

Definition at line 487 of file stm8s_uart2.c.

uint16_t UART2_ReceiveData9 ( void )

Returns the most recent received data by the UART2 peripheral.

Parameters:
None
Return values:
Received Data

Definition at line 497 of file stm8s_uart2.c.

References UART2_CR1_R8.

void UART2_ReceiverWakeUpCmd ( FunctionalState NewState )

Determines if the UART2 is in mute mode or not.

Parameters:
NewState,: new state of the UART2 mode. This parameter can be ENABLE or DISABLE
Return values:
None

Definition at line 466 of file stm8s_uart2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART2_CR2_RWU.

void UART2_SendBreak ( void )

Transmits break characters.

Parameters:
None
Return values:
None

Definition at line 539 of file stm8s_uart2.c.

References UART2_CR2_SBK.

void UART2_SendData8 ( uint8_t Data )

Transmits 8 bit data through the UART2 peripheral.

Parameters:
Data,: the data to transmit.
Return values:
None

Definition at line 511 of file stm8s_uart2.c.

void UART2_SendData9 ( uint16_t Data )

Transmits 9 bit data through the UART2 peripheral.

Parameters:
Data,: the data to transmit.
Return values:
None

Definition at line 522 of file stm8s_uart2.c.

References UART2_CR1_T8.

void UART2_SetAddress ( uint8_t UART2_Address )

Sets the address of the UART2 node.

Parameters:
UART2_Address,: Indicates the address of the UART2 node.
Return values:
None

Definition at line 549 of file stm8s_uart2.c.

References IS_UART2_ADDRESS_OK, and UART2_CR4_ADD.

void UART2_SetGuardTime ( uint8_t UART2_GuardTime )

Sets the specified UART2 guard time.

Note:
SmartCard Mode should be Enabled
Parameters:
UART2_GuardTime,: specifies the guard time.
Return values:
None

Definition at line 566 of file stm8s_uart2.c.

void UART2_SetPrescaler ( uint8_t UART2_Prescaler )

Sets the system clock prescaler.

Note:
IrDA Low Power mode or smartcard mode should be enabled
This function is related to SmartCard and IrDa mode.
Parameters:
UART2_Prescaler,: specifies the prescaler clock. This parameter can be one of the following values:
IrDA Low Power Mode
The clock source is divided by the value given in the register (8 bits)
  • 0000 0000 Reserved
  • 0000 0001 divides the clock source by 1
  • 0000 0010 divides the clock source by 2
  • ...
Smart Card Mode
The clock source is divided by the value given in the register (5 significant bits) multiped by 2
  • 0 0000 Reserved
  • 0 0001 divides the clock source by 2
  • 0 0010 divides the clock source by 4
  • 0 0011 divides the clock source by 6
  • ...
Return values:
None

Definition at line 594 of file stm8s_uart2.c.

void UART2_SmartCardCmd ( FunctionalState NewState )

Enables or disables the UART2 Smart Card mode.

Parameters:
NewState,: new state of the Smart Card mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 406 of file stm8s_uart2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART2_CR5_SCEN.

void UART2_SmartCardNACKCmd ( FunctionalState NewState )

Enables or disables NACK transmission.

Parameters:
NewState,: new state of the Smart Card mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 429 of file stm8s_uart2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART2_CR5_NACK.

void UART2_WakeUpConfig ( UART2_WakeUp_TypeDef UART2_WakeUp )

Selects the UART2 WakeUp method.

Parameters:
UART2_WakeUp,: specifies the UART2 wakeup method. This parameter can be any of the UART2_WakeUp_TypeDef values.
Return values:
None

Definition at line 452 of file stm8s_uart2.c.

References IS_UART2_WAKEUP_OK, and UART2_CR1_WAKE.


STM8S/A Standard Peripherals Drivers: UART3_Exported_Types

Enumerations
UART3_Exported_Types
STM8S_StdPeriph_Driver

Enumerations

enum UART3_Flag_TypeDef {
UART3_FLAG_TXE = (uint16_t)0x0080, UART3_FLAG_TC = (uint16_t)0x0040, UART3_FLAG_RXNE = (uint16_t)0x0020, UART3_FLAG_IDLE = (uint16_t)0x0010,
UART3_FLAG_OR_LHE = (uint16_t)0x0008, UART3_FLAG_NF = (uint16_t)0x0004, UART3_FLAG_FE = (uint16_t)0x0002, UART3_FLAG_PE = (uint16_t)0x0001,
UART3_FLAG_SBK = (uint16_t)0x0101, UART3_FLAG_LBDF = (uint16_t)0x0210, UART3_FLAG_LHDF = (uint16_t)0x0302, UART3_FLAG_LSF = (uint16_t)0x0301
}
UART3 Flag possible values. More...
enum UART3_IT_TypeDef {
UART3_IT_TXE = (uint16_t)0x0277, UART3_IT_TC = (uint16_t)0x0266, UART3_IT_RXNE = (uint16_t)0x0255, UART3_IT_IDLE = (uint16_t)0x0244,
UART3_IT_OR = (uint16_t)0x0235, UART3_IT_PE = (uint16_t)0x0100, UART3_IT_LBDF = (uint16_t)0x0346, UART3_IT_LHDF = (uint16_t)0x0412,
UART3_IT_RXNE_OR = (uint16_t)0x0205
}
UART3 Interrupt definition UART3_IT possible values Elements values convention: 0xZYX X: Position of the corresponding Interrupt. More...
enum | UART3_LinAutosync_TypeDef { UART3_LIN_AUTOSYNC_DISABLE = (uint8_t)0x00, UART3_LIN_AUTOSYNC_ENABLE = (uint8_t)0x01 }
UART3 automatic resynchronisation possible values. More...
enum | UART3_LINBreakDetectionLength_TypeDef { UART3_LINBREAKDETECTIONLENGTH_10BITS = (uint8_t)0x00, UART3_LINBREAKDETECTIONLENGTH_11BITS = (uint8_t)0x01 }
UART3 LIN Break detection length possible values. More...
enum | UART3_LinDivUp_TypeDef { UART3_LIN_DIVUP_LBRR1 = (uint8_t)0x00, UART3_LIN_DIVUP_NEXTRXNE = (uint8_t)0x01 }
UART3 Divider Update Method possible values. More...
enum | UART3_LinMode_TypeDef { UART3_LIN_MODE_MASTER = (uint8_t)0x00, UART3_LIN_MODE_SLAVE = (uint8_t)0x01 }
UART3 Mode possible values. More...
enum UART3_Mode_TypeDef {
UART3_MODE_RX_ENABLE = (uint8_t)0x08, UART3_MODE_TX_ENABLE = (uint8_t)0x04, UART3_MODE_TX_DISABLE = (uint8_t)0x80, UART3_MODE_RX_DISABLE = (uint8_t)0x40,
UART3_MODE_TXRX_ENABLE = (uint8_t)0x0C
}
UART3 Mode Transmit/Receive possible values. More...
enum | UART3_Parity_TypeDef { UART3_PARITY_NO = (uint8_t)0x00, UART3_PARITY_EVEN = (uint8_t)0x04, UART3_PARITY_ODD = (uint8_t)0x06 }
UART3 parity possible values. More...
enum | UART3_StopBits_TypeDef { UART3_STOPBITS_1 = (uint8_t)0x00, UART3_STOPBITS_2 = (uint8_t)0x20 }
UART3 stop bits possible values. More...
enum | UART3_WakeUp_TypeDef { UART3_WAKEUP_IDLELINE = (uint8_t)0x00, UART3_WAKEUP_ADDRESSMARK = (uint8_t)0x08 }
UART3 WakeUP Modes. More...
enum | UART3_WordLength_TypeDef { UART3_WORDLENGTH_8D = (uint8_t)0x00, UART3_WORDLENGTH_9D = (uint8_t)0x10 }
UART3 Word length possible values. More...

Enumeration Type Documentation

enum UART3_Flag_TypeDef

UART3 Flag possible values.

Enumerator:
UART3_FLAG_TXE

Transmit Data Register Empty flag

UART3_FLAG_TC

Transmission Complete flag

UART3_FLAG_RXNE

Read Data Register Not Empty flag

UART3_FLAG_IDLE

Idle line detected flag

UART3_FLAG_OR_LHE

OverRun error flag

UART3_FLAG_NF

Noise error flag

UART3_FLAG_FE

Framing Error flag

UART3_FLAG_PE

Parity Error flag

UART3_FLAG_SBK

Send Break Complete interrupt flag.

UART3_FLAG_LBDF

LIN Break Detection Flag.

UART3_FLAG_LHDF

LIN Header Detection Flag.

UART3_FLAG_LSF

LIN Sync Field Flag.

Definition at line 115 of file stm8s_uart3.h.

enum UART3_IT_TypeDef

UART3 Interrupt definition UART3_IT possible values Elements values convention: 0xZYX X: Position of the corresponding Interrupt.

  • For the following values, X means the interrupt position in the CR2 register. UART3_IT_TXE UART3_IT_TC UART3_IT_RXNE UART3_IT_IDLE UART3_IT_OR
  • For the UART3_IT_PE value, X means the flag position in the CR1 register.
  • For the UART3_IT_LBDF value, X means the flag position in the CR4 register.
  • For the UART3_IT_LHDF value, X means the flag position in the CR6 register. Y: Flag position

For the following values, Y means the flag (pending bit) position in the SR register. UART3_IT_TXE UART3_IT_TC UART3_IT_RXNE UART3_IT_IDLE UART3_IT_OR UART3_IT_PE

  • For the UART3_IT_LBDF value, Y means the flag position in the CR4 register.
  • For the UART3_IT_LHDF value, Y means the flag position in the CR6 register. Z: Register index: indicate in which register the dedicated interrupt source is:
  • 1==> CR1 register
  • 2==> CR2 register
  • 3==> CR4 register
  • 4==> CR6 register
Enumerator:
UART3_IT_TXE

Transmit interrupt.

UART3_IT_TC

Transmission Complete interrupt.

UART3_IT_RXNE

Data Register Not Empty interrupt.

UART3_IT_IDLE

Idle line detected interrupt.

UART3_IT_OR

OverRun error interrupt.

UART3_IT_PE

Parity Error interrupt.

UART3_IT_LBDF

LIN Break Detection interrupt.

UART3_IT_LHDF

LIN Header Detection interrupt.

UART3_IT_RXNE_OR

Receive/Overrun interrupt

Definition at line 161 of file stm8s_uart3.h.

enum UART3_LinAutosync_TypeDef

UART3 automatic resynchronisation possible values.

Enumerator:
UART3_LIN_AUTOSYNC_DISABLE

LIN Autosynchronization Disable.

UART3_LIN_AUTOSYNC_ENABLE

LIN Autosynchronization Enable.

Definition at line 101 of file stm8s_uart3.h.

enum UART3_LINBreakDetectionLength_TypeDef

UART3 LIN Break detection length possible values.

Enumerator:
UART3_LINBREAKDETECTIONLENGTH_10BITS

10 bits Lin Break detection

UART3_LINBREAKDETECTIONLENGTH_11BITS

11 bits Lin Break detection

Definition at line 55 of file stm8s_uart3.h.

enum UART3_LinDivUp_TypeDef

UART3 Divider Update Method possible values.

Enumerator:
UART3_LIN_DIVUP_LBRR1

LIN LDIV is updated as soon as LBRR1 is written.

UART3_LIN_DIVUP_NEXTRXNE

LIN LDIV is updated at the next received character.

Definition at line 107 of file stm8s_uart3.h.

enum UART3_LinMode_TypeDef

UART3 Mode possible values.

Enumerator:
UART3_LIN_MODE_MASTER

LIN Master Mode.

UART3_LIN_MODE_SLAVE

LIN Slave Mode.

Definition at line 95 of file stm8s_uart3.h.

enum UART3_Mode_TypeDef

UART3 Mode Transmit/Receive possible values.

Enumerator:
UART3_MODE_RX_ENABLE

0x08 Receive Enable

UART3_MODE_TX_ENABLE

0x04 Transmit Enable

UART3_MODE_TX_DISABLE

0x80 Receive Enable

UART3_MODE_RX_DISABLE

0x40 Single-wire Half-duplex mode

UART3_MODE_TXRX_ENABLE

0x0C Receive Enable and Transmit enable

Definition at line 85 of file stm8s_uart3.h.

enum UART3_Parity_TypeDef

UART3 parity possible values.

Enumerator:
UART3_PARITY_NO

No Parity.

UART3_PARITY_EVEN

Even Parity.

UART3_PARITY_ODD

Odd Parity.

Definition at line 70 of file stm8s_uart3.h.

enum UART3_StopBits_TypeDef

UART3 stop bits possible values.

Enumerator:
UART3_STOPBITS_1

One stop bit is transmitted at the end of frame.

UART3_STOPBITS_2

Two stop bits are transmitted at the end of frame.

Definition at line 63 of file stm8s_uart3.h.

enum UART3_WakeUp_TypeDef

UART3 WakeUP Modes.

Enumerator:
UART3_WAKEUP_IDLELINE

0x01 Idle Line wake up

UART3_WAKEUP_ADDRESSMARK

0x02 Address Mark wake up

Definition at line 48 of file stm8s_uart3.h.

enum UART3_WordLength_TypeDef

UART3 Word length possible values.

Enumerator:
UART3_WORDLENGTH_8D

0x00 8 bits Data

UART3_WORDLENGTH_9D

0x10 9 bits Data

Definition at line 78 of file stm8s_uart3.h.


STM8S/A Standard Peripherals Drivers: UART3_Private_Macros

Defines
UART3_Private_Macros
STM8S_StdPeriph_Driver

Defines

#define | IS_UART3_ADDRESS_OK(Node) ((Node) < UART3_ADDRESS_MAX)
#define | IS_UART3_AUTOSYNC_OK(AutosyncMode)
Macro used by the assert_param function in order to check the LIN automatic resynchronization mode.
#define | IS_UART3_BAUDRATE_OK(NUM) ((NUM) <= (uint32_t)625000)
Macro used by the assert_param function in order to check the maximum baudrate value.
#define | IS_UART3_CLEAR_FLAG_OK(Flag)
Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs that can be cleared by writing 0.
#define | IS_UART3_CLEAR_IT_OK(ITPendingBit)
Macro used by the assert function in order to check the different sensitivity values for the pending bit that can be cleared by writing 0.
#define | IS_UART3_CONFIG_IT_OK(Interrupt)
Macro used by the assert_param function in order to check the different sensitivity values for the Interrupts.
#define | IS_UART3_DIVUP_OK(DivupMethod)
Macro used by the assert_param function in order to check the LIN divider update method.
#define | IS_UART3_FLAG_OK(Flag)
Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs.
#define | IS_UART3_GET_IT_OK(ITPendingBit)
Macro used by the assert function in order to check the different sensitivity values for the pending bit.
#define | IS_UART3_LINBREAKDETECTIONLENGTH_OK(LINBreakDetectionLengths)
Macro used by the assert_param function in order to check the different sensitivity values for the LINBreakDetectionLengths.
#define | IS_UART3_MODE_OK(Mode)
Macro used by the assert_param function in order to check the different sensitivity values for the MODEs.
#define | IS_UART3_PARITY_OK(Parity)
Macro used by the assert_param function in order to check the different sensitivity values for the Parity.
#define | IS_UART3_SLAVE_OK(Mode)
Macro used by the assert_param function in order to check the LIN mode.
#define | IS_UART3_STOPBITS_OK(StopBit)
Macro used by the assert_param function in order to check the different sensitivity values for the UART3_StopBits.
#define | IS_UART3_WAKEUP_OK(WakeUpMode)
Macro used by the assert_param function in order to check the different sensitivity values for the WakeUps.
#define | IS_UART3_WORDLENGTH_OK(WordLength)
Macro used by the assert_param function in order to check the different sensitivity values for the WordLengths.
#define | UART3_ADDRESS_MAX ((uint8_t)16)
Macro used by the assert_param function in order to check the address of the UART3 or UART node.

Define Documentation

#define IS_UART3_ADDRESS_OK ( Node ) ((Node) < UART3_ADDRESS_MAX)

Definition at line 320 of file stm8s_uart3.h.

Referenced by UART3_SetAddress().

#define IS_UART3_AUTOSYNC_OK ( AutosyncMode )
Value:
(((AutosyncMode) ==  UART3_LIN_AUTOSYNC_ENABLE) || \
   ((AutosyncMode) == UART3_LIN_AUTOSYNC_DISABLE))

Macro used by the assert_param function in order to check the LIN automatic resynchronization mode.

Definition at line 333 of file stm8s_uart3.h.

Referenced by UART3_LINConfig().

#define IS_UART3_BAUDRATE_OK ( NUM ) ((NUM) <= (uint32_t)625000)

Macro used by the assert_param function in order to check the maximum baudrate value.

Definition at line 313 of file stm8s_uart3.h.

Referenced by UART3_Init().

#define IS_UART3_CLEAR_FLAG_OK ( Flag )
Value:
(((Flag) == UART3_FLAG_RXNE) || \
   ((Flag) == UART3_FLAG_LHDF) || \
   ((Flag) == UART3_FLAG_LSF) || \
   ((Flag) == UART3_FLAG_LBDF))

Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs that can be cleared by writing 0.

Definition at line 209 of file stm8s_uart3.h.

Referenced by UART3_ClearFlag().

#define IS_UART3_CLEAR_IT_OK ( ITPendingBit )
Value:
(((ITPendingBit) == UART3_IT_RXNE) || \
   ((ITPendingBit) == UART3_IT_LHDF) || \
   ((ITPendingBit) == UART3_IT_LBDF))

Macro used by the assert function in order to check the different sensitivity values for the pending bit that can be cleared by writing 0.

Definition at line 247 of file stm8s_uart3.h.

Referenced by UART3_ClearITPendingBit().

#define IS_UART3_CONFIG_IT_OK ( Interrupt )
Value:
(((Interrupt) == UART3_IT_PE) || \
   ((Interrupt) == UART3_IT_TXE) || \
   ((Interrupt) == UART3_IT_TC) || \
   ((Interrupt) == UART3_IT_RXNE_OR ) || \
   ((Interrupt) == UART3_IT_IDLE) || \
   ((Interrupt) == UART3_IT_LHDF) || \
   ((Interrupt) == UART3_IT_LBDF))

Macro used by the assert_param function in order to check the different sensitivity values for the Interrupts.

Definition at line 220 of file stm8s_uart3.h.

Referenced by UART3_ITConfig().

#define IS_UART3_DIVUP_OK ( DivupMethod )
Value:
(((DivupMethod) == UART3_LIN_DIVUP_LBRR1) || \
   ((DivupMethod) == UART3_LIN_DIVUP_NEXTRXNE))

Macro used by the assert_param function in order to check the LIN divider update method.

Definition at line 341 of file stm8s_uart3.h.

Referenced by UART3_LINConfig().

#define IS_UART3_FLAG_OK ( Flag )
Value:
(((Flag) == UART3_FLAG_TXE) || \
   ((Flag) == UART3_FLAG_TC)  || \
   ((Flag) == UART3_FLAG_RXNE) || \
   ((Flag) == UART3_FLAG_IDLE) || \
   ((Flag) == UART3_FLAG_OR_LHE) || \
   ((Flag) == UART3_FLAG_NF) || \
   ((Flag) == UART3_FLAG_FE) || \
   ((Flag) == UART3_FLAG_PE) || \
   ((Flag) == UART3_FLAG_SBK) || \
   ((Flag) == UART3_FLAG_LSF) || \
   ((Flag) == UART3_FLAG_LHDF) || \
   ((Flag) == UART3_FLAG_LBDF))

Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs.

Definition at line 190 of file stm8s_uart3.h.

Referenced by UART3_GetFlagStatus().

#define IS_UART3_GET_IT_OK ( ITPendingBit )
Value:
(((ITPendingBit) == UART3_IT_TXE)  || \
   ((ITPendingBit) == UART3_IT_TC)   || \
   ((ITPendingBit) == UART3_IT_RXNE) || \
   ((ITPendingBit) == UART3_IT_IDLE) || \
   ((ITPendingBit) == UART3_IT_OR)  || \
   ((ITPendingBit) == UART3_IT_LBDF)  || \
   ((ITPendingBit) == UART3_IT_LHDF)  || \
   ((ITPendingBit) == UART3_IT_PE))

Macro used by the assert function in order to check the different sensitivity values for the pending bit.

Definition at line 233 of file stm8s_uart3.h.

Referenced by UART3_GetITStatus().

#define IS_UART3_LINBREAKDETECTIONLENGTH_OK ( LINBreakDetectionLengths )
Value:
(((LINBreakDetectionLengths) == UART3_LINBREAKDETECTIONLENGTH_10BITS) || \
   ((LINBreakDetectionLengths) == UART3_LINBREAKDETECTIONLENGTH_11BITS))

Macro used by the assert_param function in order to check the different sensitivity values for the LINBreakDetectionLengths.

Definition at line 288 of file stm8s_uart3.h.

Referenced by UART3_LINBreakDetectionConfig().

#define IS_UART3_MODE_OK ( Mode )
Value:
(((Mode) == (uint8_t)UART3_MODE_RX_ENABLE) || \
   ((Mode) == (uint8_t)UART3_MODE_RX_DISABLE) || \
   ((Mode) == (uint8_t)UART3_MODE_TX_ENABLE) || \
   ((Mode) == (uint8_t)UART3_MODE_TX_DISABLE) || \
   ((Mode) == (uint8_t)UART3_MODE_TXRX_ENABLE) || \
   ((Mode) == (uint8_t)((uint8_t)UART3_MODE_TX_ENABLE|(uint8_t)UART3_MODE_RX_ENABLE)) || \
   ((Mode) == (uint8_t)((uint8_t)UART3_MODE_TX_ENABLE|(uint8_t)UART3_MODE_RX_DISABLE)) || \
   ((Mode) == (uint8_t)((uint8_t)UART3_MODE_TX_DISABLE|(uint8_t)UART3_MODE_RX_DISABLE)) || \
   ((Mode) == (uint8_t)((uint8_t)UART3_MODE_TX_DISABLE|(uint8_t)UART3_MODE_RX_ENABLE)))

Macro used by the assert_param function in order to check the different sensitivity values for the MODEs.

Definition at line 256 of file stm8s_uart3.h.

Referenced by UART3_Init().

#define IS_UART3_PARITY_OK ( Parity )
Value:
(((Parity) == UART3_PARITY_NO) || \
   ((Parity) == UART3_PARITY_EVEN) || \
   ((Parity) == UART3_PARITY_ODD ))

Macro used by the assert_param function in order to check the different sensitivity values for the Parity.

Definition at line 304 of file stm8s_uart3.h.

Referenced by UART3_Init().

#define IS_UART3_SLAVE_OK ( Mode )
Value:
(((Mode) == UART3_LIN_MODE_MASTER) || \
   ((Mode) == UART3_LIN_MODE_SLAVE))

Macro used by the assert_param function in order to check the LIN mode.

Definition at line 325 of file stm8s_uart3.h.

Referenced by UART3_LINConfig().

#define IS_UART3_STOPBITS_OK ( StopBit )
Value:
(((StopBit) == UART3_STOPBITS_1) || \
   ((StopBit) == UART3_STOPBITS_2))

Macro used by the assert_param function in order to check the different sensitivity values for the UART3_StopBits.

Definition at line 296 of file stm8s_uart3.h.

Referenced by UART3_Init().

#define IS_UART3_WAKEUP_OK ( WakeUpMode )
Value:
(((WakeUpMode) == UART3_WAKEUP_IDLELINE) || \
   ((WakeUpMode) == UART3_WAKEUP_ADDRESSMARK))

Macro used by the assert_param function in order to check the different sensitivity values for the WakeUps.

Definition at line 280 of file stm8s_uart3.h.

Referenced by UART3_WakeUpConfig().

#define IS_UART3_WORDLENGTH_OK ( WordLength )
Value:
(((WordLength) == UART3_WORDLENGTH_8D) || \
   ((WordLength) == UART3_WORDLENGTH_9D))

Macro used by the assert_param function in order to check the different sensitivity values for the WordLengths.

Definition at line 271 of file stm8s_uart3.h.

Referenced by UART3_Init().

#define UART3_ADDRESS_MAX ((uint8_t)16)

Macro used by the assert_param function in order to check the address of the UART3 or UART node.

Definition at line 319 of file stm8s_uart3.h.


STM8S/A Standard Peripherals Drivers: UART3_Exported_Functions

Functions
UART3_Exported_Functions
STM8S_StdPeriph_Driver

Functions

void | UART3_ClearFlag (UART3_Flag_TypeDef UART3_FLAG)
Clears the UART3 flags.
void | UART3_ClearITPendingBit (UART3_IT_TypeDef UART3_IT)
Clears the UART3 pending flags.
void | UART3_Cmd (FunctionalState NewState)
Enable the UART1 peripheral.
void | UART3_DeInit (void)
Deinitializes the UART peripheral.
FlagStatus | UART3_GetFlagStatus (UART3_Flag_TypeDef UART3_FLAG)
Checks whether the specified UART3 flag is set or not.
ITStatus | UART3_GetITStatus (UART3_IT_TypeDef UART3_IT)
Checks whether the specified UART3 interrupt has occurred or not.
void | UART3_Init (uint32_t BaudRate, UART3_WordLength_TypeDef WordLength, UART3_StopBits_TypeDef StopBits, UART3_Parity_TypeDef Parity, UART3_Mode_TypeDef Mode)
Initializes the UART3 according to the specified parameters.
void | UART3_ITConfig (UART3_IT_TypeDef UART3_IT, FunctionalState NewState)
Enables or disables the specified UART3 interrupts.
void | UART3_LINBreakDetectionConfig (UART3_LINBreakDetectionLength_TypeDef UART3_LINBreakDetectionLength)
Sets the UART3 LIN Break detection length.
void | UART3_LINCmd (FunctionalState NewState)
Enables or disables the UART3 LIN mode.
void | UART3_LINConfig (UART3_LinMode_TypeDef UART3_Mode, UART3_LinAutosync_TypeDef UART3_Autosync, UART3_LinDivUp_TypeDef UART3_DivUp)
Configure the UART3 peripheral.
uint8_t | UART3_ReceiveData8 (void)
Returns the most recent received data by the UART3 peripheral.
uint16_t | UART3_ReceiveData9 (void)
Returns the most recent received data by the UART3 peripheral.
void | UART3_ReceiverWakeUpCmd (FunctionalState NewState)
Determines if the UART3 is in mute mode or not.
void | UART3_SendBreak (void)
Transmits break characters.
void | UART3_SendData8 (uint8_t Data)
Transmits 8 bit data through the UART3 peripheral.
void | UART3_SendData9 (uint16_t Data)
Transmits 9 bit data through the UART3 peripheral.
void | UART3_SetAddress (uint8_t UART3_Address)
Sets the address of the UART3 node.
void | UART3_WakeUpConfig (UART3_WakeUp_TypeDef UART3_WakeUp)
Selects the UART3 WakeUp method.

Function Documentation

void UART3_ClearFlag ( UART3_Flag_TypeDef UART3_FLAG )

Clears the UART3 flags.

Parameters:
UART3_FLAG specifies the flag to clear This parameter can be any combination of the following values:
  • UART3_FLAG_LBDF: LIN Break detection flag.
  • UART3_FLAG_LHDF: LIN Header detection flag.
  • UART3_FLAG_LSF: LIN synchrone field flag.
  • UART3_FLAG_RXNE: Receive data register not empty flag.
Note:
  • PE (Parity error), FE (Framing error), NF (Noise error), OR (OverRun error) and IDLE (Idle line detected) flags are cleared by software sequence: a read operation to UART3_SR register (UART3_GetFlagStatus())followed by a read operation to UART3_DR register(UART3_ReceiveData8() or UART3_ReceiveData9()).
  • RXNE flag can be also cleared by a read to the UART3_DR register (UART3_ReceiveData8()or UART3_ReceiveData9()).
  • TC flag can be also cleared by software sequence: a read operation to UART3_SR register (UART3_GetFlagStatus()) followed by a write operation to UART3_DR register (UART3_SendData8() or UART3_SendData9()).
  • TXE flag is cleared only by a write to the UART3_DR register (UART3_SendData8() or UART3_SendData9()).
  • SBK flag is cleared during the stop bit of break.
    Return values:
    None

Definition at line 551 of file stm8s_uart3.c.

References IS_UART3_CLEAR_FLAG_OK, UART3_CR4_LBDF, UART3_CR6_LHDF, UART3_CR6_LSF, UART3_FLAG_LBDF, UART3_FLAG_LHDF, UART3_FLAG_RXNE, and UART3_SR_RXNE.

void UART3_ClearITPendingBit ( UART3_IT_TypeDef UART3_IT )

Clears the UART3 pending flags.

Parameters:
UART3_IT specifies the pending bit to clear This parameter can be one of the following values:
  • UART3_IT_LBDF: LIN Break detection interrupt
  • UART3_IT_LHDF: LIN Header detection interrupt
  • UART3_IT_RXNE: Receive Data register not empty interrupt.
Note:
  • PE (Parity error), FE (Framing error), NF (Noise error), OR (OverRun error) and IDLE (Idle line detected) pending bits are cleared by software sequence: a read operation to UART3_SR register (UART3_GetITStatus()) followed by a read operation to UART3_DR register (UART3_ReceiveData8() or UART3_ReceiveData9()).
  • RXNE pending bit can be also cleared by a read to the UART3_DR register (UART3_ReceiveData8() or UART3_ReceiveData9() ).
  • TC (Transmit complete) pending bit can be cleared by software sequence: a read operation to UART3_SR register (UART3_GetITStatus()) followed by a write operation to UART3_DR register (UART3_SendData8()or UART3_SendData9()).
  • TXE pending bit is cleared only by a write to the UART3_DR register (UART3_SendData8() or UART3_SendData9()).
    Return values:
    None

Definition at line 706 of file stm8s_uart3.c.

References IS_UART3_CLEAR_IT_OK, UART3_CR4_LBDF, UART3_CR6_LHDF, UART3_IT_LBDF, UART3_IT_RXNE, and UART3_SR_RXNE.

void UART3_Cmd ( FunctionalState NewState )

Enable the UART1 peripheral.

Parameters:
NewState : The new state of the UART Communication. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 160 of file stm8s_uart3.c.

References DISABLE, and UART3_CR1_UARTD.

void UART3_DeInit ( void )

Deinitializes the UART peripheral.

Parameters:
None
Return values:
None

Definition at line 54 of file stm8s_uart3.c.

References UART3_BRR1_RESET_VALUE, UART3_BRR2_RESET_VALUE, UART3_CR1_RESET_VALUE, UART3_CR2_RESET_VALUE, UART3_CR3_RESET_VALUE, UART3_CR4_RESET_VALUE, and UART3_CR6_RESET_VALUE.

FlagStatus UART3_GetFlagStatus ( UART3_Flag_TypeDef UART3_FLAG )

Checks whether the specified UART3 flag is set or not.

Parameters:
UART3_FLAG specifies the flag to check. This parameter can be any of the UART3_Flag_TypeDef enumeration.
Return values:
FlagStatus (SET or RESET)

Definition at line 458 of file stm8s_uart3.c.

References IS_UART3_FLAG_OK, RESET, SET, UART3_FLAG_LBDF, UART3_FLAG_LHDF, UART3_FLAG_LSF, and UART3_FLAG_SBK.

ITStatus UART3_GetITStatus ( UART3_IT_TypeDef UART3_IT )

Checks whether the specified UART3 interrupt has occurred or not.

Parameters:
UART3_IT,: Specifies the UART3 interrupt pending bit to check. This parameter can be one of the following values:
  • UART3_IT_LBDF: LIN Break detection interrupt
  • UART3_IT_TXE: Transmit Data Register empty interrupt
  • UART3_IT_TC: Transmission complete interrupt
  • UART3_IT_RXNE: Receive Data register not empty interrupt
  • UART3_IT_IDLE: Idle line detection interrupt
  • UART3_IT_OR: OverRun Error interrupt
  • UART3_IT_PE: Parity Error interrupt
Return values:
The state of UART3_IT (SET or RESET).

Definition at line 591 of file stm8s_uart3.c.

References IS_UART3_GET_IT_OK, RESET, SET, UART3_IT_LBDF, UART3_IT_LHDF, and UART3_IT_PE.

void UART3_Init | ( | uint32_t | BaudRate,
 |  | UART3_WordLength_TypeDef | WordLength,
 |  | UART3_StopBits_TypeDef | StopBits,
 |  | UART3_Parity_TypeDef | Parity,
 |  | UART3_Mode_TypeDef | Mode
 | ) |  |

Initializes the UART3 according to the specified parameters.

Parameters:
BaudRate,: The baudrate.
WordLength : This parameter can be any of the UART3_WordLength_TypeDef enumeration.
StopBits,: This parameter can be any of the UART3_StopBits_TypeDef enumeration.
Parity,: This parameter can be any of the UART3_Parity_TypeDef enumeration.
Mode,: This parameter can be any of the UART3_Mode_TypeDef values
Return values:
None

Definition at line 83 of file stm8s_uart3.c.

References CLK_GetClockFreq(), IS_UART3_BAUDRATE_OK, IS_UART3_MODE_OK, IS_UART3_PARITY_OK, IS_UART3_STOPBITS_OK, IS_UART3_WORDLENGTH_OK, UART3_BRR1_DIVM, UART3_BRR2_DIVF, UART3_BRR2_DIVM, UART3_CR1_M, UART3_CR1_PCEN, UART3_CR1_PS, UART3_CR2_REN, UART3_CR2_TEN, UART3_CR3_STOP, UART3_MODE_RX_ENABLE, and UART3_MODE_TX_ENABLE.

void UART3_ITConfig | ( | UART3_IT_TypeDef | UART3_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified UART3 interrupts.

Parameters:
UART3_IT specifies the UART3 interrupt sources to be enabled or disabled. This parameter can be one of the following values:
  • UART3_IT_LBDF: LIN Break detection interrupt
  • UART3_IT_LHDF: LIN Break detection interrupt
  • UART3_IT_TXE: Transmit Data Register empty interrupt
  • UART3_IT_TC: Transmission complete interrupt
  • UART3_IT_RXNE_OR: Receive Data register not empty/Over run error interrupt
  • UART3_IT_IDLE: Idle line detection interrupt
  • UART3_IT_PE: Parity Error interrupt
NewState new state of the specified UART3 interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 189 of file stm8s_uart3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and IS_UART3_CONFIG_IT_OK.

void UART3_LINBreakDetectionConfig ( UART3_LINBreakDetectionLength_TypeDef UART3_LINBreakDetectionLength )

Sets the UART3 LIN Break detection length.

Parameters:
UART3_LINBreakDetectionLength specifies the LIN break detection length. This parameter can be any of the UART3_LINBreakDetectionLength_TypeDef values.
Return values:
None

Definition at line 252 of file stm8s_uart3.c.

References IS_UART3_LINBREAKDETECTIONLENGTH_OK, UART3_CR4_LBDL, and UART3_LINBREAKDETECTIONLENGTH_10BITS.

void UART3_LINCmd ( FunctionalState NewState )

Enables or disables the UART3 LIN mode.

Parameters:
NewState is new state of the UART3 LIN mode. This parameter can be ENABLE or DISABLE
Return values:
None

Definition at line 320 of file stm8s_uart3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART3_CR3_LINEN.

void UART3_LINConfig | ( | UART3_LinMode_TypeDef | UART3_Mode,
 |  | UART3_LinAutosync_TypeDef | UART3_Autosync,
 |  | UART3_LinDivUp_TypeDef | UART3_DivUp
 | ) |  |

Configure the UART3 peripheral.

Parameters:
UART3_Mode | specifies the LIN mode. This parameter can be any of the UART3_LinMode_TypeDef values.
UART3_Autosync | specifies the LIN automatic resynchronization mode. This parameter can be any of the UART3_LinAutosync_TypeDef values.
UART3_DivUp | specifies the LIN divider update method. This parameter can be any of the UART3_LinDivUp_TypeDef values.
Return values:
None

Definition at line 277 of file stm8s_uart3.c.

References IS_UART3_AUTOSYNC_OK, IS_UART3_DIVUP_OK, IS_UART3_SLAVE_OK, UART3_CR6_LASE, UART3_CR6_LDUM, UART3_CR6_LSLV, UART3_LIN_AUTOSYNC_DISABLE, UART3_LIN_DIVUP_LBRR1, and UART3_LIN_MODE_MASTER.

uint8_t UART3_ReceiveData8 ( void )

Returns the most recent received data by the UART3 peripheral.

Parameters:
None
Return values:
Received Data

Definition at line 380 of file stm8s_uart3.c.

uint16_t UART3_ReceiveData9 ( void )

Returns the most recent received data by the UART3 peripheral.

Parameters:
None
Return values:
Received Data

Definition at line 390 of file stm8s_uart3.c.

References UART3_CR1_R8.

void UART3_ReceiverWakeUpCmd ( FunctionalState NewState )

Determines if the UART3 is in mute mode or not.

Parameters:
NewState,: new state of the UART3 mode. This parameter can be ENABLE or DISABLE
Return values:
None

Definition at line 358 of file stm8s_uart3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART3_CR2_RWU.

void UART3_SendBreak ( void )

Transmits break characters.

Parameters:
None
Return values:
None

Definition at line 431 of file stm8s_uart3.c.

References UART3_CR2_SBK.

void UART3_SendData8 ( uint8_t Data )

Transmits 8 bit data through the UART3 peripheral.

Parameters:
Data the data to transmit.
Return values:
None

Definition at line 403 of file stm8s_uart3.c.

void UART3_SendData9 ( uint16_t Data )

Transmits 9 bit data through the UART3 peripheral.

Parameters:
Data,: the data to transmit.
Return values:
None

Definition at line 414 of file stm8s_uart3.c.

References UART3_CR1_T8.

void UART3_SetAddress ( uint8_t UART3_Address )

Sets the address of the UART3 node.

Parameters:
UART3_Address,: Indicates the address of the UART3 node.
Return values:
None

Definition at line 441 of file stm8s_uart3.c.

References IS_UART3_ADDRESS_OK, and UART3_CR4_ADD.

void UART3_WakeUpConfig ( UART3_WakeUp_TypeDef UART3_WakeUp )

Selects the UART3 WakeUp method.

Parameters:
UART3_WakeUp,: specifies the UART3 wakeup method. This parameter can be any of the UART3_WakeUp_TypeDef values.
Return values:
None

Definition at line 343 of file stm8s_uart3.c.

References IS_UART3_WAKEUP_OK, and UART3_CR1_WAKE.


STM8S/A Standard Peripherals Drivers: UART4_Exported_Types

Enumerations
UART4_Exported_Types
STM8S_StdPeriph_Driver

Enumerations

enum UART4_Flag_TypeDef {
UART4_FLAG_TXE = (uint16_t)0x0080, UART4_FLAG_TC = (uint16_t)0x0040, UART4_FLAG_RXNE = (uint16_t)0x0020, UART4_FLAG_IDLE = (uint16_t)0x0010,
UART4_FLAG_OR_LHE = (uint16_t)0x0008, UART4_FLAG_NF = (uint16_t)0x0004, UART4_FLAG_FE = (uint16_t)0x0002, UART4_FLAG_PE = (uint16_t)0x0001,
UART4_FLAG_SBK = (uint16_t)0x0101, UART4_FLAG_LBDF = (uint16_t)0x0210, UART4_FLAG_LHDF = (uint16_t)0x0302, UART4_FLAG_LSF = (uint16_t)0x0301
}
UART4 Flag possible values. More...
enum | UART4_IrDAMode_TypeDef { UART4_IRDAMODE_NORMAL = (uint8_t)0x00, UART4_IRDAMODE_LOWPOWER = (uint8_t)0x01 }
UART4 Irda Modes. More...
enum UART4_IT_TypeDef {
UART4_IT_TXE = (uint16_t)0x0277, UART4_IT_TC = (uint16_t)0x0266, UART4_IT_RXNE = (uint16_t)0x0255, UART4_IT_IDLE = (uint16_t)0x0244,
UART4_IT_OR = (uint16_t)0x0235, UART4_IT_PE = (uint16_t)0x0100, UART4_IT_LBDF = (uint16_t)0x0346, UART4_IT_LHDF = (uint16_t)0x0412,
UART4_IT_RXNE_OR = (uint16_t)0x0205
}
UART4 Interrupt definition UART4_IT possible values Elements values convention: 0xZYX X: Position of the corresponding Interrupt. More...
enum | UART4_LinAutosync_TypeDef { UART4_LIN_AUTOSYNC_DISABLE = (uint8_t)0x00, UART4_LIN_AUTOSYNC_ENABLE = (uint8_t)0x01 }
UART4 automatic resynchronisation possible values. More...
enum | UART4_LINBreakDetectionLength_TypeDef { UART4_LINBREAKDETECTIONLENGTH_10BITS = (uint8_t)0x00, UART4_LINBREAKDETECTIONLENGTH_11BITS = (uint8_t)0x01 }
UART4 LIN Break detection length possible values. More...
enum | UART4_LinDivUp_TypeDef { UART4_LIN_DIVUP_LBRR1 = (uint8_t)0x00, UART4_LIN_DIVUP_NEXTRXNE = (uint8_t)0x01 }
UART4 Divider Update Method possible values. More...
enum | UART4_LinMode_TypeDef { UART4_LIN_MODE_MASTER = (uint8_t)0x00, UART4_LIN_MODE_SLAVE = (uint8_t)0x01 }
UART4 Mode possible values. More...
enum UART4_Mode_TypeDef {
UART4_MODE_RX_ENABLE = (uint8_t)0x08, UART4_MODE_TX_ENABLE = (uint8_t)0x04, UART4_MODE_TX_DISABLE = (uint8_t)0x80, UART4_MODE_RX_DISABLE = (uint8_t)0x40,
UART4_MODE_TXRX_ENABLE = (uint8_t)0x0C
}
UART4 Mode possible values. More...
enum | UART4_Parity_TypeDef { UART4_PARITY_NO = (uint8_t)0x00, UART4_PARITY_EVEN = (uint8_t)0x04, UART4_PARITY_ODD = (uint8_t)0x06 }
UART4 parity possible values. More...
enum | UART4_StopBits_TypeDef { UART4_STOPBITS_1 = (uint8_t)0x00, UART4_STOPBITS_0_5 = (uint8_t)0x10, UART4_STOPBITS_2 = (uint8_t)0x20, UART4_STOPBITS_1_5 = (uint8_t)0x30 }
UART4 stop bits possible values. More...
enum UART4_SyncMode_TypeDef {
UART4_SYNCMODE_CLOCK_DISABLE = (uint8_t)0x80, UART4_SYNCMODE_CLOCK_ENABLE = (uint8_t)0x08, UART4_SYNCMODE_CPOL_LOW = (uint8_t)0x40, UART4_SYNCMODE_CPOL_HIGH = (uint8_t)0x04,
UART4_SYNCMODE_CPHA_MIDDLE = (uint8_t)0x20, UART4_SYNCMODE_CPHA_BEGINING = (uint8_t)0x02, UART4_SYNCMODE_LASTBIT_DISABLE = (uint8_t)0x10, UART4_SYNCMODE_LASTBIT_ENABLE = (uint8_t)0x01
}
UART4 Synchrone modes. More...
enum | UART4_WakeUp_TypeDef { UART4_WAKEUP_IDLELINE = (uint8_t)0x00, UART4_WAKEUP_ADDRESSMARK = (uint8_t)0x08 }
UART4 WakeUP Modes. More...
enum | UART4_WordLength_TypeDef { UART4_WORDLENGTH_8D = (uint8_t)0x00, UART4_WORDLENGTH_9D = (uint8_t)0x10 }
UART4 Word length possible values. More...

Enumeration Type Documentation

enum UART4_Flag_TypeDef

UART4 Flag possible values.

Enumerator:
UART4_FLAG_TXE

Transmit Data Register Empty flag

UART4_FLAG_TC

Transmission Complete flag

UART4_FLAG_RXNE

Read Data Register Not Empty flag

UART4_FLAG_IDLE

Idle line detected flag

UART4_FLAG_OR_LHE

OverRun error flag

UART4_FLAG_NF

Noise error flag

UART4_FLAG_FE

Framing Error flag

UART4_FLAG_PE

Parity Error flag

UART4_FLAG_SBK

Send Break Complete interrupt flag.

UART4_FLAG_LBDF

LIN Break Detection Flag.

UART4_FLAG_LHDF

LIN Header Detection Flag.

UART4_FLAG_LSF

LIN Sync Field Flag.

Definition at line 139 of file stm8s_uart4.h.

enum UART4_IrDAMode_TypeDef

UART4 Irda Modes.

Enumerator:
UART4_IRDAMODE_NORMAL

0x00 Irda Normal Mode

UART4_IRDAMODE_LOWPOWER

0x01 Irda Low Power Mode

Definition at line 49 of file stm8s_uart4.h.

enum UART4_IT_TypeDef

UART4 Interrupt definition UART4_IT possible values Elements values convention: 0xZYX X: Position of the corresponding Interrupt.

  • For the following values, X means the interrupt position in the CR2 register. UART4_IT_TXE UART4_IT_TC UART4_IT_RXNE UART4_IT_IDLE UART4_IT_OR
  • For the UART4_IT_PE value, X means the flag position in the CR1 register.
  • For the UART4_IT_LBDF value, X means the flag position in the CR4 register.
  • For the UART4_IT_LHDF value, X means the flag position in the CR6 register. Y: Flag position

For the following values, Y means the flag (pending bit) position in the SR register. UART4_IT_TXE UART4_IT_TC UART4_IT_RXNE UART4_IT_IDLE UART4_IT_OR UART4_IT_PE

  • For the UART4_IT_LBDF value, Y means the flag position in the CR4 register.
  • For the UART4_IT_LHDF value, Y means the flag position in the CR6 register. Z: Register index: indicate in which register the dedicated interrupt source is:
  • 1==> CR1 register
  • 2==> CR2 register
  • 3==> CR4 register
  • 4==> CR6 register
Enumerator:
UART4_IT_TXE

Transmit interrupt.

UART4_IT_TC

Transmission Complete interrupt.

UART4_IT_RXNE

Data Register Not Empty interrupt.

UART4_IT_IDLE

Idle line detected interrupt.

UART4_IT_OR

OverRun error interrupt.

UART4_IT_PE

Parity Error interrupt.

UART4_IT_LBDF

LIN Break Detection interrupt.

UART4_IT_LHDF

LIN Header Detection interrupt.

UART4_IT_RXNE_OR

Receive/Overrun interrupt

Definition at line 185 of file stm8s_uart4.h.

enum UART4_LinAutosync_TypeDef

UART4 automatic resynchronisation possible values.

Enumerator:
UART4_LIN_AUTOSYNC_DISABLE

LIN Autosynchronization Disable.

UART4_LIN_AUTOSYNC_ENABLE

LIN Autosynchronization Enable.

Definition at line 97 of file stm8s_uart4.h.

enum UART4_LINBreakDetectionLength_TypeDef

UART4 LIN Break detection length possible values.

Enumerator:
UART4_LINBREAKDETECTIONLENGTH_10BITS

0x01 10 bits Lin Break detection

UART4_LINBREAKDETECTIONLENGTH_11BITS

0x02 11 bits Lin Break detection

Definition at line 66 of file stm8s_uart4.h.

enum UART4_LinDivUp_TypeDef

UART4 Divider Update Method possible values.

Enumerator:
UART4_LIN_DIVUP_LBRR1

LIN LDIV is updated as soon as LBRR1 is written.

UART4_LIN_DIVUP_NEXTRXNE

LIN LDIV is updated at the next received character.

Definition at line 103 of file stm8s_uart4.h.

enum UART4_LinMode_TypeDef

UART4 Mode possible values.

Enumerator:
UART4_LIN_MODE_MASTER

LIN Master Mode.

UART4_LIN_MODE_SLAVE

LIN Slave Mode.

Definition at line 91 of file stm8s_uart4.h.

enum UART4_Mode_TypeDef

UART4 Mode possible values.

Enumerator:
UART4_MODE_RX_ENABLE

0x08 Receive Enable

UART4_MODE_TX_ENABLE

0x04 Transmit Enable

UART4_MODE_TX_DISABLE

0x80 Transmit Disable

UART4_MODE_RX_DISABLE

0x40 Single-wire Half-duplex mode

UART4_MODE_TXRX_ENABLE

0x0C Transmit Enable and Receive Enable

Definition at line 130 of file stm8s_uart4.h.

enum UART4_Parity_TypeDef

UART4 parity possible values.

Enumerator:
UART4_PARITY_NO

No Parity.

UART4_PARITY_EVEN

Even Parity.

UART4_PARITY_ODD

Odd Parity.

Definition at line 84 of file stm8s_uart4.h.

enum UART4_StopBits_TypeDef

UART4 stop bits possible values.

Enumerator:
UART4_STOPBITS_1

One stop bit is transmitted at the end of frame.

UART4_STOPBITS_0_5

Half stop bits is transmitted at the end of frame.

UART4_STOPBITS_2

Two stop bits are transmitted at the end of frame.

UART4_STOPBITS_1_5

One and half stop bits.

Definition at line 74 of file stm8s_uart4.h.

enum UART4_SyncMode_TypeDef

UART4 Synchrone modes.

Enumerator:
UART4_SYNCMODE_CLOCK_DISABLE

0x80 Sync mode Disable, SLK pin Disable

UART4_SYNCMODE_CLOCK_ENABLE

0x08 Sync mode Enable, SLK pin Enable

UART4_SYNCMODE_CPOL_LOW

0x40 Steady low value on SCLK pin outside transmission window

UART4_SYNCMODE_CPOL_HIGH

0x04 Steady high value on SCLK pin outside transmission window

UART4_SYNCMODE_CPHA_MIDDLE

0x20 SCLK clock line activated in middle of data bit

UART4_SYNCMODE_CPHA_BEGINING

0x02 SCLK clock line activated at beginning of data bit

UART4_SYNCMODE_LASTBIT_DISABLE

0x10 The clock pulse of the last data bit is not output to the SCLK pin

UART4_SYNCMODE_LASTBIT_ENABLE

0x01 The clock pulse of the last data bit is output to the SCLK pin

Definition at line 110 of file stm8s_uart4.h.

enum UART4_WakeUp_TypeDef

UART4 WakeUP Modes.

Enumerator:
UART4_WAKEUP_IDLELINE

0x01 Idle Line wake up

UART4_WAKEUP_ADDRESSMARK

0x02 Address Mark wake up

Definition at line 58 of file stm8s_uart4.h.

enum UART4_WordLength_TypeDef

UART4 Word length possible values.

Enumerator:
UART4_WORDLENGTH_8D

0x00 8 bits Data

UART4_WORDLENGTH_9D

0x10 9 bits Data

Definition at line 123 of file stm8s_uart4.h.


STM8S/A Standard Peripherals Drivers: UART4_Private_Macros

Defines
UART4_Private_Macros
STM8S_StdPeriph_Driver

Defines

#define | IS_UART4_ADDRESS_OK(node) ((node) < UART4_ADDRESS_MAX )
#define | IS_UART4_AUTOSYNC_OK(AutosyncMode)
Macro used by the assert_param function in order to check the LIN automatic resynchronization mode.
#define | IS_UART4_BAUDRATE_OK(NUM) ((NUM) <= (uint32_t)625000)
Macro used by the assert_param function in order to check the maximum baudrate value.
#define | IS_UART4_CLEAR_FLAG_OK(Flag)
Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs that can be cleared by writing 0.
#define | IS_UART4_CLEAR_IT_OK(ITPendingBit)
Macro used by the assert function in order to check the different sensitivity values for the pending bit that can be cleared by writing 0.
#define | IS_UART4_CONFIG_IT_OK(Interrupt)
Macro used by the assert_param function in order to check the different sensitivity values for the Interrupts.
#define | IS_UART4_DIVUP_OK(DivupMethod)
Macro used by the assert_param function in order to check the LIN divider update method.
#define | IS_UART4_FLAG_OK(Flag)
Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs.
#define | IS_UART4_GET_IT_OK(ITPendingBit)
Macro used by the assert function in order to check the different sensitivity values for the pending bit.
#define | IS_UART4_IRDAMODE_OK(IrDAMode)
Macro used by the assert_param function in order to check the different sensitivity values for the IrDAModes.
#define | IS_UART4_LINBREAKDETECTIONLENGTH_OK(LINBreakDetectionLength)
Macro used by the assert_param function in order to check the different sensitivity values for the LINBreakDetectionLengths.
#define | IS_UART4_MODE_OK(Mode)
Macro used by the assert function to check the different functions parameters.
#define | IS_UART4_PARITY_OK(Parity)
Macro used by the assert_param function in order to check the different sensitivity values for the Paritys.
#define | IS_UART4_SLAVE_OK(Mode)
Macro used by the assert_param function in order to check the LIN mode.
#define | IS_UART4_STOPBITS_OK(StopBit)
Macro used by the assert_param function in order to check the different sensitivity values for the UART4_StopBits.
#define | IS_UART4_SYNCMODE_OK(SyncMode)
Macro used by the assert_param function in order to check the different sensitivity values for the SyncModes; it should exclude values such as UART4_CLOCK_ENABLE|UART4_CLOCK_DISABLE.
#define | IS_UART4_WAKEUP_OK(WakeUp)
Macro used by the assert_param function in order to check the different sensitivity values for the WakeUps.
#define | IS_UART4_WORDLENGTH_OK(WordLength)
Macro used by the assert_param function in order to check the different sensitivity values for the WordLengths.
#define | UART4_ADDRESS_MAX ((uint8_t)16)
Macro used by the assert_param function in order to check the address of the UART4 or UART node.

Define Documentation

#define IS_UART4_ADDRESS_OK ( node ) ((node) < UART4_ADDRESS_MAX )

Definition at line 367 of file stm8s_uart4.h.

Referenced by UART4_SetAddress().

#define IS_UART4_AUTOSYNC_OK ( AutosyncMode )
Value:
(((AutosyncMode) ==  UART4_LIN_AUTOSYNC_ENABLE) || \
   ((AutosyncMode) == UART4_LIN_AUTOSYNC_DISABLE))

Macro used by the assert_param function in order to check the LIN automatic resynchronization mode.

Definition at line 380 of file stm8s_uart4.h.

Referenced by UART4_LINConfig().

#define IS_UART4_BAUDRATE_OK ( NUM ) ((NUM) <= (uint32_t)625000)

Macro used by the assert_param function in order to check the maximum baudrate value.

Definition at line 360 of file stm8s_uart4.h.

Referenced by UART4_Init().

#define IS_UART4_CLEAR_FLAG_OK ( Flag )
Value:
(((Flag) == UART4_FLAG_RXNE) || \
   ((Flag) == UART4_FLAG_LHDF) || \
   ((Flag) == UART4_FLAG_LSF) || \
   ((Flag) == UART4_FLAG_LBDF))

Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs that can be cleared by writing 0.

Definition at line 271 of file stm8s_uart4.h.

Referenced by UART4_ClearFlag().

#define IS_UART4_CLEAR_IT_OK ( ITPendingBit )
Value:
(((ITPendingBit) == UART4_IT_RXNE) || \
   ((ITPendingBit) == UART4_IT_LHDF) || \
   ((ITPendingBit) == UART4_IT_LBDF))

Macro used by the assert function in order to check the different sensitivity values for the pending bit that can be cleared by writing 0.

Definition at line 309 of file stm8s_uart4.h.

Referenced by UART4_ClearITPendingBit().

#define IS_UART4_CONFIG_IT_OK ( Interrupt )
Value:
(((Interrupt) == UART4_IT_PE) || \
   ((Interrupt) == UART4_IT_TXE) || \
   ((Interrupt) == UART4_IT_TC) || \
   ((Interrupt) == UART4_IT_RXNE_OR ) || \
   ((Interrupt) == UART4_IT_IDLE) || \
   ((Interrupt) == UART4_IT_LHDF) || \
   ((Interrupt) == UART4_IT_LBDF))

Macro used by the assert_param function in order to check the different sensitivity values for the Interrupts.

Definition at line 282 of file stm8s_uart4.h.

Referenced by UART4_ITConfig().

#define IS_UART4_DIVUP_OK ( DivupMethod )
Value:
(((DivupMethod) == UART4_LIN_DIVUP_LBRR1) || \
   ((DivupMethod) == UART4_LIN_DIVUP_NEXTRXNE))

Macro used by the assert_param function in order to check the LIN divider update method.

Definition at line 387 of file stm8s_uart4.h.

Referenced by UART4_LINConfig().

#define IS_UART4_FLAG_OK ( Flag )
Value:
(((Flag) == UART4_FLAG_TXE) || \
   ((Flag) == UART4_FLAG_TC)  || \
   ((Flag) == UART4_FLAG_RXNE) || \
   ((Flag) == UART4_FLAG_IDLE) || \
   ((Flag) == UART4_FLAG_OR_LHE) || \
   ((Flag) == UART4_FLAG_NF) || \
   ((Flag) == UART4_FLAG_FE) || \
   ((Flag) == UART4_FLAG_PE) || \
   ((Flag) == UART4_FLAG_SBK) || \
   ((Flag) == UART4_FLAG_LSF) || \
   ((Flag) == UART4_FLAG_LHDF) || \
   ((Flag) == UART4_FLAG_LBDF))

Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs.

Definition at line 252 of file stm8s_uart4.h.

Referenced by UART4_GetFlagStatus().

#define IS_UART4_GET_IT_OK ( ITPendingBit )
Value:
(((ITPendingBit) == UART4_IT_TXE)  || \
   ((ITPendingBit) == UART4_IT_TC)   || \
   ((ITPendingBit) == UART4_IT_RXNE) || \
   ((ITPendingBit) == UART4_IT_IDLE) || \
   ((ITPendingBit) == UART4_IT_OR)  || \
   ((ITPendingBit) == UART4_IT_LBDF)  || \
   ((ITPendingBit) == UART4_IT_LHDF)  || \
   ((ITPendingBit) == UART4_IT_PE))

Macro used by the assert function in order to check the different sensitivity values for the pending bit.

Definition at line 295 of file stm8s_uart4.h.

Referenced by UART4_GetITStatus().

#define IS_UART4_IRDAMODE_OK ( IrDAMode )
Value:
(((IrDAMode) == UART4_IRDAMODE_LOWPOWER) || \
   ((IrDAMode) == UART4_IRDAMODE_NORMAL))

Macro used by the assert_param function in order to check the different sensitivity values for the IrDAModes.

Definition at line 319 of file stm8s_uart4.h.

Referenced by UART4_IrDAConfig().

#define IS_UART4_LINBREAKDETECTIONLENGTH_OK ( LINBreakDetectionLength )
Value:
(((LINBreakDetectionLength) == UART4_LINBREAKDETECTIONLENGTH_10BITS) || \
   ((LINBreakDetectionLength) == UART4_LINBREAKDETECTIONLENGTH_11BITS))

Macro used by the assert_param function in order to check the different sensitivity values for the LINBreakDetectionLengths.

Definition at line 335 of file stm8s_uart4.h.

Referenced by UART4_LINBreakDetectionConfig().

#define IS_UART4_MODE_OK ( Mode )
Value:
(((Mode) == (uint8_t)UART4_MODE_RX_ENABLE) || \
   ((Mode) == (uint8_t)UART4_MODE_RX_DISABLE) || \
   ((Mode) == (uint8_t)UART4_MODE_TX_ENABLE) || \
   ((Mode) == (uint8_t)UART4_MODE_TX_DISABLE) || \
   ((Mode) == (uint8_t)UART4_MODE_TXRX_ENABLE) || \
   ((Mode) == (uint8_t)((uint8_t)UART4_MODE_TX_ENABLE|(uint8_t)UART4_MODE_RX_ENABLE)) || \
   ((Mode) == (uint8_t)((uint8_t)UART4_MODE_TX_ENABLE|(uint8_t)UART4_MODE_RX_DISABLE)) || \
   ((Mode) == (uint8_t)((uint8_t)UART4_MODE_TX_DISABLE|(uint8_t)UART4_MODE_RX_DISABLE)) || \
   ((Mode) == (uint8_t)((uint8_t)UART4_MODE_TX_DISABLE|(uint8_t)UART4_MODE_RX_ENABLE)))

Macro used by the assert function to check the different functions parameters.

Macro used by the assert_param function in order to check the different sensitivity values for the MODEs possible combination should be one of the following.

Definition at line 218 of file stm8s_uart4.h.

Referenced by UART4_Init().

#define IS_UART4_PARITY_OK ( Parity )
Value:
(((Parity) == UART4_PARITY_NO) || \
                                    ((Parity) == UART4_PARITY_EVEN) || \
                                    ((Parity) == UART4_PARITY_ODD ))

Macro used by the assert_param function in order to check the different sensitivity values for the Paritys.

Definition at line 352 of file stm8s_uart4.h.

Referenced by UART4_Init().

#define IS_UART4_SLAVE_OK ( Mode )
Value:
(((Mode) == UART4_LIN_MODE_MASTER) || \
   ((Mode) == UART4_LIN_MODE_SLAVE))

Macro used by the assert_param function in order to check the LIN mode.

Definition at line 372 of file stm8s_uart4.h.

Referenced by UART4_LINConfig().

#define IS_UART4_STOPBITS_OK ( StopBit )
Value:
(((StopBit) == UART4_STOPBITS_1) || \
                                       ((StopBit) == UART4_STOPBITS_0_5) || \
                                       ((StopBit) == UART4_STOPBITS_2) || \
                                       ((StopBit) == UART4_STOPBITS_1_5 ))

Macro used by the assert_param function in order to check the different sensitivity values for the UART4_StopBits.

Definition at line 343 of file stm8s_uart4.h.

Referenced by UART4_Init().

#define IS_UART4_SYNCMODE_OK ( SyncMode )
Value:
(!((((SyncMode)&(((uint8_t)UART4_SYNCMODE_CLOCK_ENABLE)|((uint8_t)UART4_SYNCMODE_CLOCK_DISABLE))) == (((uint8_t)UART4_SYNCMODE_CLOCK_ENABLE)|((uint8_t)UART4_SYNCMODE_CLOCK_DISABLE))) || \
     (((SyncMode)&(((uint8_t)UART4_SYNCMODE_CPOL_LOW )|((uint8_t)UART4_SYNCMODE_CPOL_HIGH))) == (((uint8_t)UART4_SYNCMODE_CPOL_LOW )|((uint8_t)UART4_SYNCMODE_CPOL_HIGH))) || \
     (((SyncMode)&(((uint8_t)UART4_SYNCMODE_CPHA_MIDDLE)|((uint8_t)UART4_SYNCMODE_CPHA_BEGINING))) == (((uint8_t)UART4_SYNCMODE_CPHA_MIDDLE)|((uint8_t)UART4_SYNCMODE_CPHA_BEGINING))) || \
     (((SyncMode)&(((uint8_t)UART4_SYNCMODE_LASTBIT_DISABLE)|((uint8_t)UART4_SYNCMODE_LASTBIT_ENABLE))) == (((uint8_t)UART4_SYNCMODE_LASTBIT_DISABLE)|((uint8_t)UART4_SYNCMODE_LASTBIT_ENABLE)))))

Macro used by the assert_param function in order to check the different sensitivity values for the SyncModes; it should exclude values such as UART4_CLOCK_ENABLE|UART4_CLOCK_DISABLE.

Definition at line 242 of file stm8s_uart4.h.

Referenced by UART4_Init().

#define IS_UART4_WAKEUP_OK ( WakeUp )
Value:
(((WakeUp) == UART4_WAKEUP_IDLELINE) || \
   ((WakeUp) == UART4_WAKEUP_ADDRESSMARK))

Macro used by the assert_param function in order to check the different sensitivity values for the WakeUps.

Definition at line 327 of file stm8s_uart4.h.

Referenced by UART4_WakeUpConfig().

#define IS_UART4_WORDLENGTH_OK ( WordLength )
Value:
(((WordLength) == UART4_WORDLENGTH_8D) || \
   ((WordLength) == UART4_WORDLENGTH_9D))

Macro used by the assert_param function in order to check the different sensitivity values for the WordLengths.

Definition at line 233 of file stm8s_uart4.h.

Referenced by UART4_Init().

#define UART4_ADDRESS_MAX ((uint8_t)16)

Macro used by the assert_param function in order to check the address of the UART4 or UART node.

Definition at line 366 of file stm8s_uart4.h.


STM8S/A Standard Peripherals Drivers: UART4_Exported_Functions

Functions
UART4_Exported_Functions
STM8S_StdPeriph_Driver

Functions

void | UART4_ClearFlag (UART4_Flag_TypeDef UART4_FLAG)
Clears the UART4 flags.
void | UART4_ClearITPendingBit (UART4_IT_TypeDef UART4_IT)
Clears the UART4 pending flags.
void | UART4_Cmd (FunctionalState NewState)
Enable the UART4 peripheral.
void | UART4_DeInit (void)
Deinitializes the UART peripheral.
FlagStatus | UART4_GetFlagStatus (UART4_Flag_TypeDef UART4_FLAG)
Checks whether the specified UART4 flag is set or not.
ITStatus | UART4_GetITStatus (UART4_IT_TypeDef UART4_IT)
Checks whether the specified UART4 interrupt has occurred or not.
void | UART4_HalfDuplexCmd (FunctionalState NewState)
Enables or disables the UART’s Half Duplex communication.
void | UART4_Init (uint32_t BaudRate, UART4_WordLength_TypeDef WordLength, UART4_StopBits_TypeDef StopBits, UART4_Parity_TypeDef Parity, UART4_SyncMode_TypeDef SyncMode, UART4_Mode_TypeDef Mode)
Initializes the UART4 according to the specified parameters.
void | UART4_IrDACmd (FunctionalState NewState)
Enables or disables the UART4’s IrDA interface.
void | UART4_IrDAConfig (UART4_IrDAMode_TypeDef UART4_IrDAMode)
Configures the UART4’s IrDA interface.
void | UART4_ITConfig (UART4_IT_TypeDef UART4_IT, FunctionalState NewState)
Enables or disables the specified UART4 interrupts.
void | UART4_LINBreakDetectionConfig (UART4_LINBreakDetectionLength_TypeDef UART4_LINBreakDetectionLength)
Sets the UART4 LIN Break detection length.
void | UART4_LINCmd (FunctionalState NewState)
Enables or disables the UART4 LIN mode.
void | UART4_LINConfig (UART4_LinMode_TypeDef UART4_Mode, UART4_LinAutosync_TypeDef UART4_Autosync, UART4_LinDivUp_TypeDef UART4_DivUp)
Configure the UART4 peripheral.
uint8_t | UART4_ReceiveData8 (void)
Returns the most recent received data by the UART4 peripheral.
uint16_t | UART4_ReceiveData9 (void)
Returns the most recent received data by the UART4 peripheral.
void | UART4_ReceiverWakeUpCmd (FunctionalState NewState)
Determines if the UART4 is in mute mode or not.
void | UART4_SendBreak (void)
Transmits break characters.
void | UART4_SendData8 (uint8_t Data)
Transmits 8 bit data through the UART4 peripheral.
void | UART4_SendData9 (uint16_t Data)
Transmits 9 bit data through the UART4 peripheral.
void | UART4_SetAddress (uint8_t UART4_Address)
Sets the address of the UART4 node.
void | UART4_SetGuardTime (uint8_t UART4_GuardTime)
Sets the specified UART4 guard time.
void | UART4_SetPrescaler (uint8_t UART4_Prescaler)
Sets the system clock prescaler.
void | UART4_SmartCardCmd (FunctionalState NewState)
Enables or disables the UART4 Smart Card mode.
void | UART4_SmartCardNACKCmd (FunctionalState NewState)
Enables or disables NACK transmission.
void | UART4_WakeUpConfig (UART4_WakeUp_TypeDef UART4_WakeUp)
Selects the UART4 WakeUp method.

Function Documentation

void UART4_ClearFlag ( UART4_Flag_TypeDef UART4_FLAG )

Clears the UART4 flags.

Parameters:
UART4_FLAG specifies the flag to clear This parameter can be any combination of the following values:
  • UART4_FLAG_LBDF: LIN Break detection flag.
  • UART4_FLAG_LHDF: LIN Header detection flag.
  • UART4_FLAG_LSF: LIN synchrone field flag.
  • UART4_FLAG_RXNE: Receive data register not empty flag.
Note:
:
  • PE (Parity error), FE (Framing error), NE (Noise error), OR (OverRun error) and IDLE (Idle line detected) flags are cleared by software sequence: a read operation to UART4_SR register (UART4_GetFlagStatus())followed by a read operation to UART4_DR register(UART4_ReceiveData8() or UART4_ReceiveData9()).
  • RXNE flag can be also cleared by a read to the UART4_DR register (UART4_ReceiveData8()or UART4_ReceiveData9()).
  • TC flag can be also cleared by software sequence: a read operation to UART4_SR register (UART4_GetFlagStatus()) followed by a write operation to UART4_DR register (UART4_SendData8() or UART4_SendData9()).
  • TXE flag is cleared only by a write to the UART4_DR register (UART4_SendData8() or UART4_SendData9()).
  • SBK flag is cleared during the stop bit of break.
    Return values:
    None

Definition at line 719 of file stm8s_uart4.c.

References IS_UART4_CLEAR_FLAG_OK, UART4_FLAG_LBDF, UART4_FLAG_LHDF, and UART4_FLAG_RXNE.

void UART4_ClearITPendingBit ( UART4_IT_TypeDef UART4_IT )

Clears the UART4 pending flags.

Parameters:
UART4_IT specifies the pending bit to clear This parameter can be one of the following values:
  • UART4_IT_LBDF: LIN Break detection interrupt
  • UART4_IT_LHDF: LIN Header detection interrupt
  • UART4_IT_RXNE: Receive Data register not empty interrupt.
Note:
  • PE (Parity error), FE (Framing error), NE (Noise error), OR (OverRun error) and IDLE (Idle line detected) pending bits are cleared by software sequence: a read operation to UART4_SR register (UART4_GetITStatus()) followed by a read operation to UART4_DR register (UART4_ReceiveData8() or UART4_ReceiveData9()).
  • RXNE pending bit can be also cleared by a read to the UART4_DR register (UART4_ReceiveData8() or UART4_ReceiveData9()).
  • TC (Transmit complete) pending bit can be cleared by software sequence: a read operation to UART4_SR register (UART4_GetITStatus()) followed by a write operation to UART4_DR register (UART4_SendData8()or UART4_SendData9()).
  • TXE pending bit is cleared only by a write to the UART4_DR register (UART4_SendData8() or UART4_SendData9()).
    Return values:
    None

Definition at line 872 of file stm8s_uart4.c.

References IS_UART4_CLEAR_IT_OK, UART4_IT_LBDF, and UART4_IT_RXNE.

void UART4_Cmd ( FunctionalState NewState )

Enable the UART4 peripheral.

Parameters:
NewState : The new state of the UART Communication. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 181 of file stm8s_uart4.c.

References DISABLE.

void UART4_DeInit ( void )

Deinitializes the UART peripheral.

Parameters:
None
Return values:
None

Definition at line 53 of file stm8s_uart4.c.

FlagStatus UART4_GetFlagStatus ( UART4_Flag_TypeDef UART4_FLAG )

Checks whether the specified UART4 flag is set or not.

Parameters:
UART4_FLAG specifies the flag to check. This parameter can be any of the UART4_Flag_TypeDef enumeration.
Return values:
FlagStatus (SET or RESET)

Definition at line 626 of file stm8s_uart4.c.

References IS_UART4_FLAG_OK, RESET, SET, UART4_FLAG_LBDF, UART4_FLAG_LHDF, UART4_FLAG_LSF, and UART4_FLAG_SBK.

ITStatus UART4_GetITStatus ( UART4_IT_TypeDef UART4_IT )

Checks whether the specified UART4 interrupt has occurred or not.

Parameters:
UART4_IT,: Specifies the UART4 interrupt pending bit to check. This parameter can be one of the following values:
  • UART4_IT_LBDF: LIN Break detection interrupt
  • UART4_IT_TXE: Transmit Data Register empty interrupt
  • UART4_IT_TC: Transmission complete interrupt
  • UART4_IT_RXNE: Receive Data register not empty interrupt
  • UART4_IT_IDLE: Idle line detection interrupt
  • UART4_IT_OR: OverRun Error interrupt
  • UART4_IT_PE: Parity Error interrupt
Return values:
The state of UART4_IT (SET or RESET).

Definition at line 758 of file stm8s_uart4.c.

References IS_UART4_GET_IT_OK, RESET, SET, UART4_IT_LBDF, UART4_IT_LHDF, and UART4_IT_PE.

void UART4_HalfDuplexCmd ( FunctionalState NewState )

Enables or disables the UART’s Half Duplex communication.

Parameters:
NewState new state of the UART Communication. This parameter can be: ENABLE or DISABLE.
Return values:
None

< UART4 Half Duplex Enable

< UART4 Half Duplex Disable

Definition at line 272 of file stm8s_uart4.c.

References DISABLE, and IS_FUNCTIONALSTATE_OK.

void UART4_Init | ( | uint32_t | BaudRate,
 |  | UART4_WordLength_TypeDef | WordLength,
 |  | UART4_StopBits_TypeDef | StopBits,
 |  | UART4_Parity_TypeDef | Parity,
 |  | UART4_SyncMode_TypeDef | SyncMode,
 |  | UART4_Mode_TypeDef | Mode
 | ) |  |

Initializes the UART4 according to the specified parameters.

Parameters:
BaudRate,: The baudrate.
WordLength : This parameter can be any of the UART4_WordLength_TypeDef enumeration.
StopBits,: This parameter can be any of the UART4_StopBits_TypeDef enumeration.
Parity,: This parameter can be any of the UART4_Parity_TypeDef enumeration.
SyncMode,: This parameter can be any of the UART4_SyncMode_TypeDef values.
Mode,: This parameter can be any of the UART4_Mode_TypeDef values
Return values:
None

Definition at line 85 of file stm8s_uart4.c.

References CLK_GetClockFreq(), IS_UART4_BAUDRATE_OK, IS_UART4_MODE_OK, IS_UART4_PARITY_OK, IS_UART4_STOPBITS_OK, IS_UART4_SYNCMODE_OK, IS_UART4_WORDLENGTH_OK, UART4_MODE_RX_ENABLE, UART4_MODE_TX_ENABLE, and UART4_SYNCMODE_CLOCK_DISABLE.

void UART4_IrDACmd ( FunctionalState NewState )

Enables or disables the UART4’s IrDA interface.

Parameters:
NewState new state of the IrDA mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 312 of file stm8s_uart4.c.

References DISABLE, and IS_FUNCTIONALSTATE_OK.

void UART4_IrDAConfig ( UART4_IrDAMode_TypeDef UART4_IrDAMode )

Configures the UART4’s IrDA interface.

Parameters:
UART4_IrDAMode specifies the IrDA mode. This parameter can be any of the UART4_IrDAMode_TypeDef values.
Return values:
None

Definition at line 292 of file stm8s_uart4.c.

References IS_UART4_IRDAMODE_OK, and UART4_IRDAMODE_NORMAL.

void UART4_ITConfig | ( | UART4_IT_TypeDef | UART4_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified UART4 interrupts.

Parameters:
UART4_IT specifies the UART4 interrupt sources to be enabled or disabled. This parameter can be one of the following values:
  • UART4_IT_LBDF: LIN Break detection interrupt
  • UART4_IT_LHDF: LIN Break detection interrupt
  • UART4_IT_TXE: Transmit Data Register empty interrupt
  • UART4_IT_TC: Transmission complete interrupt
  • UART4_IT_RXNE_OR: Receive Data register not empty/Over run error interrupt
  • UART4_IT_IDLE: Idle line detection interrupt
  • UART4_IT_PE: Parity Error interrupt
NewState new state of the specified UART4 interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 210 of file stm8s_uart4.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and IS_UART4_CONFIG_IT_OK.

void UART4_LINBreakDetectionConfig ( UART4_LINBreakDetectionLength_TypeDef UART4_LINBreakDetectionLength )

Sets the UART4 LIN Break detection length.

Parameters:
UART4_LINBreakDetectionLength specifies the LIN break detection length. This parameter can be any of the UART4_LINBreakDetectionLength_TypeDef values.
Return values:
None

Definition at line 336 of file stm8s_uart4.c.

References IS_UART4_LINBREAKDETECTIONLENGTH_OK, and UART4_LINBREAKDETECTIONLENGTH_10BITS.

void UART4_LINCmd ( FunctionalState NewState )

Enables or disables the UART4 LIN mode.

Parameters:
NewState is new state of the UART4 LIN mode. This parameter can be ENABLE or DISABLE
Return values:
None

Definition at line 404 of file stm8s_uart4.c.

References DISABLE, and IS_FUNCTIONALSTATE_OK.

void UART4_LINConfig | ( | UART4_LinMode_TypeDef | UART4_Mode,
 |  | UART4_LinAutosync_TypeDef | UART4_Autosync,
 |  | UART4_LinDivUp_TypeDef | UART4_DivUp
 | ) |  |

Configure the UART4 peripheral.

Parameters:
UART4_Mode | specifies the LIN mode. This parameter can be any of the UART4_LinMode_TypeDef values.
UART4_Autosync | specifies the LIN automatic resynchronization mode. This parameter can be any of the UART4_LinAutosync_TypeDef values.
UART4_DivUp | specifies the LIN divider update method. This parameter can be any of the UART4_LinDivUp_TypeDef values.
Return values:
None

Definition at line 361 of file stm8s_uart4.c.

References IS_UART4_AUTOSYNC_OK, IS_UART4_DIVUP_OK, IS_UART4_SLAVE_OK, UART4_LIN_AUTOSYNC_DISABLE, UART4_LIN_DIVUP_LBRR1, and UART4_LIN_MODE_MASTER.

uint8_t UART4_ReceiveData8 ( void )

Returns the most recent received data by the UART4 peripheral.

Parameters:
None
Return values:
Received Data

Definition at line 507 of file stm8s_uart4.c.

uint16_t UART4_ReceiveData9 ( void )

Returns the most recent received data by the UART4 peripheral.

Parameters:
None
Return values:
Received Data

Definition at line 517 of file stm8s_uart4.c.

void UART4_ReceiverWakeUpCmd ( FunctionalState NewState )

Determines if the UART4 is in mute mode or not.

Parameters:
NewState,: new state of the UART4 mode. This parameter can be ENABLE or DISABLE
Return values:
None

Definition at line 486 of file stm8s_uart4.c.

References DISABLE, and IS_FUNCTIONALSTATE_OK.

void UART4_SendBreak ( void )

Transmits break characters.

Parameters:
None
Return values:
None

Definition at line 559 of file stm8s_uart4.c.

void UART4_SendData8 ( uint8_t Data )

Transmits 8 bit data through the UART4 peripheral.

Parameters:
Data,: the data to transmit.
Return values:
None

Definition at line 531 of file stm8s_uart4.c.

void UART4_SendData9 ( uint16_t Data )

Transmits 9 bit data through the UART4 peripheral.

Parameters:
Data,: the data to transmit.
Return values:
None

Definition at line 542 of file stm8s_uart4.c.

void UART4_SetAddress ( uint8_t UART4_Address )

Sets the address of the UART4 node.

Parameters:
UART4_Address,: Indicates the address of the UART4 node.
Return values:
None

Definition at line 569 of file stm8s_uart4.c.

References IS_UART4_ADDRESS_OK.

void UART4_SetGuardTime ( uint8_t UART4_GuardTime )

Sets the specified UART4 guard time.

Note:
SmartCard Mode should be Enabled
Parameters:
UART4_GuardTime,: specifies the guard time.
Return values:
None

Definition at line 586 of file stm8s_uart4.c.

void UART4_SetPrescaler ( uint8_t UART4_Prescaler )

Sets the system clock prescaler.

Note:
IrDA Low Power mode or smartcard mode should be enabled
This function is related to SmartCard and IrDa mode.
Parameters:
UART4_Prescaler,: specifies the prescaler clock. This parameter can be one of the following values:
IrDA Low Power Mode
The clock source is divided by the value given in the register (8 bits)
  • 0000 0000 Reserved
  • 0000 0001 divides the clock source by 1
  • 0000 0010 divides the clock source by 2
  • ...
Smart Card Mode
The clock source is divided by the value given in the register (5 significant bits) multiplied by 2
  • 0 0000 Reserved
  • 0 0001 divides the clock source by 2
  • 0 0010 divides the clock source by 4
  • 0 0011 divides the clock source by 6
  • ...
Return values:
None

Definition at line 614 of file stm8s_uart4.c.

void UART4_SmartCardCmd ( FunctionalState NewState )

Enables or disables the UART4 Smart Card mode.

Parameters:
NewState,: new state of the Smart Card mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 426 of file stm8s_uart4.c.

References DISABLE, and IS_FUNCTIONALSTATE_OK.

void UART4_SmartCardNACKCmd ( FunctionalState NewState )

Enables or disables NACK transmission.

Parameters:
NewState,: new state of the Smart Card mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 449 of file stm8s_uart4.c.

References DISABLE, and IS_FUNCTIONALSTATE_OK.

void UART4_WakeUpConfig ( UART4_WakeUp_TypeDef UART4_WakeUp )

Selects the UART4 WakeUp method.

Parameters:
UART4_WakeUp,: specifies the UART4 wakeup method. This parameter can be any of the UART4_WakeUp_TypeDef values.
Return values:
None

Definition at line 472 of file stm8s_uart4.c.

References IS_UART4_WAKEUP_OK.


STM8S/A Standard Peripherals Drivers: WWDG_Private_Macros

Defines
WWDG_Private_Macros
STM8S_StdPeriph_Driver

Defines

#define | IS_WWDG_COUNTERVALUE_OK(CounterValue) ((CounterValue) <= 0x7F)
Macro used by the assert function in order to check the different values of the counter register.
#define | IS_WWDG_WINDOWLIMITVALUE_OK(WindowLimitValue) ((WindowLimitValue) <= 0x7F)
Macro used by the assert function in order to check the values of the window register.

Define Documentation

#define IS_WWDG_COUNTERVALUE_OK ( CounterValue ) ((CounterValue) <= 0x7F)

Macro used by the assert function in order to check the different values of the counter register.

Definition at line 55 of file stm8s_wwdg.h.

Referenced by WWDG_SetCounter().

#define IS_WWDG_WINDOWLIMITVALUE_OK ( WindowLimitValue ) ((WindowLimitValue) <= 0x7F)

Macro used by the assert function in order to check the values of the window register.

Definition at line 49 of file stm8s_wwdg.h.

Referenced by WWDG_Init(), and WWDG_SetWindowValue().


STM8S/A Standard Peripherals Drivers: WWDG_Exported_Functions

Functions
WWDG_Exported_Functions
STM8S_StdPeriph_Driver

Functions

uint8_t | WWDG_GetCounter (void)
Gets the WWDG Counter Value.
void | WWDG_Init (uint8_t Counter, uint8_t WindowValue)
Initializes the WWDG peripheral.
void | WWDG_SetCounter (uint8_t Counter)
Refreshes the WWDG peripheral.
void | WWDG_SetWindowValue (uint8_t WindowValue)
Sets the WWDG window value.
void | WWDG_SWReset (void)
Generates immediate WWDG RESET.

Function Documentation

uint8_t WWDG_GetCounter ( void )

Gets the WWDG Counter Value.

This value could be used to check if WWDG is in the window, where refresh is allowed.

Parameters:
None
Return values:
WWDG Counter Value

Definition at line 86 of file stm8s_wwdg.c.

References WWDG.

void WWDG_Init | ( | uint8_t | Counter,
 |  | uint8_t | WindowValue
 | ) |  |

Initializes the WWDG peripheral.

This function set Window Register = WindowValue, Counter Register according to Counter and ENABLE WWDG

Parameters:
Counter | : WWDG counter value
WindowValue | : specifies the WWDG Window Register, range is 0x00 to 0x7F.
Return values:
None

Definition at line 53 of file stm8s_wwdg.c.

References IS_WWDG_WINDOWLIMITVALUE_OK, WWDG, WWDG_CR_T6, WWDG_CR_WDGA, and WWDG_WR_RESET_VALUE.

void WWDG_SetCounter ( uint8_t Counter )

Refreshes the WWDG peripheral.

Parameters:
Counter : WWDG Counter Value This parameter must be a number between 0x40 and 0x7F.
Return values:
None

Definition at line 69 of file stm8s_wwdg.c.

References BIT_MASK, IS_WWDG_COUNTERVALUE_OK, and WWDG.

void WWDG_SetWindowValue ( uint8_t WindowValue )

Sets the WWDG window value.

Parameters:
WindowValue,: specifies the window value to be compared to the downcounter. This parameter value must be lower than 0x80.
Return values:
None

Definition at line 108 of file stm8s_wwdg.c.

References IS_WWDG_WINDOWLIMITVALUE_OK, WWDG, WWDG_CR_T6, and WWDG_CR_WDGA.

void WWDG_SWReset ( void )

Generates immediate WWDG RESET.

Parameters:
None
Return values:
None

Definition at line 96 of file stm8s_wwdg.c.

References WWDG, and WWDG_CR_WDGA.


STM8S/A Standard Peripherals Drivers: ADC1_Public_Functions

Functions
ADC1_Public_Functions
STM8S_StdPeriph_Driver

Functions

void | ADC1_AWDChannelConfig (ADC1_Channel_TypeDef Channel, FunctionalState NewState)
Enables or disables the analog watchdog for the given channel.
void | ADC1_ClearFlag (ADC1_Flag_TypeDef Flag)
Clear the specified ADC1 Flag.
void | ADC1_ClearITPendingBit (ADC1_IT_TypeDef ITPendingBit)
Clear the ADC1 End of Conversion pending bit.
void | ADC1_Cmd (FunctionalState NewState)
Enables or Disables the ADC1 peripheral.
void | ADC1_ConversionConfig (ADC1_ConvMode_TypeDef ADC1_ConversionMode, ADC1_Channel_TypeDef ADC1_Channel, ADC1_Align_TypeDef ADC1_Align)
Configure the ADC1 conversion on selected channel.
void | ADC1_DataBufferCmd (FunctionalState NewState)
Enables or Disables the ADC1 data store into the Data Buffer registers rather than in the Data Register.
void | ADC1_DeInit (void)
Deinitializes the ADC1 peripheral registers to their default reset values.
void | ADC1_ExternalTriggerConfig (ADC1_ExtTrig_TypeDef ADC1_ExtTrigger, FunctionalState NewState)
Configure the ADC1 conversion on external trigger event.
FlagStatus | ADC1_GetAWDChannelStatus (ADC1_Channel_TypeDef Channel)
Checks the specified analog watchdog channel status.
uint16_t | ADC1_GetBufferValue (uint8_t Buffer)
Get one sample of measured signal.
uint16_t | ADC1_GetConversionValue (void)
Get one sample of measured signal.
FlagStatus | ADC1_GetFlagStatus (ADC1_Flag_TypeDef Flag)
Checks the specified ADC1 flag status.
ITStatus | ADC1_GetITStatus (ADC1_IT_TypeDef ITPendingBit)
Returns the specified pending bit status.
void | ADC1_Init (ADC1_ConvMode_TypeDef ADC1_ConversionMode, ADC1_Channel_TypeDef ADC1_Channel, ADC1_PresSel_TypeDef ADC1_PrescalerSelection, ADC1_ExtTrig_TypeDef ADC1_ExtTrigger, FunctionalState ADC1_ExtTriggerState, ADC1_Align_TypeDef ADC1_Align, ADC1_SchmittTrigg_TypeDef ADC1_SchmittTriggerChannel, FunctionalState ADC1_SchmittTriggerState)
Initializes the ADC1 peripheral according to the specified parameters.
void | ADC1_ITConfig (ADC1_IT_TypeDef ADC1_IT, FunctionalState NewState)
Enables or disables the ADC1 interrupt.
void | ADC1_PrescalerConfig (ADC1_PresSel_TypeDef ADC1_Prescaler)
Configure the ADC1 prescaler division factor.
void | ADC1_ScanModeCmd (FunctionalState NewState)
Enables or Disables the ADC1 scan mode.
void | ADC1_SchmittTriggerConfig (ADC1_SchmittTrigg_TypeDef ADC1_SchmittTriggerChannel, FunctionalState NewState)
Enables or disables the ADC1 Schmitt Trigger on a selected channel.
void | ADC1_SetHighThreshold (uint16_t Threshold)
Sets the high threshold of the analog watchdog.
void | ADC1_SetLowThreshold (uint16_t Threshold)
Sets the low threshold of the analog watchdog.
void | ADC1_StartConversion (void)
Start ADC1 conversion.

Function Documentation

void ADC1_AWDChannelConfig | ( | ADC1_Channel_TypeDef | Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the analog watchdog for the given channel.

Parameters:
Channel | specifies the desired Channel. It can be set of the values of ADC1_Channel_TypeDef.
NewState | specifies the analog watchdog new state. can have one of the values of FunctionalState.
Return values:
None

Definition at line 405 of file stm8s_adc1.c.

References DISABLE, IS_ADC1_CHANNEL_OK, and IS_FUNCTIONALSTATE_OK.

void ADC1_ClearFlag ( ADC1_Flag_TypeDef Flag )

Clear the specified ADC1 Flag.

Parameters:
Flag,: ADC1 flag. can be one of the values of ADC1_Flag_TypeDef.
Return values:
None

Definition at line 567 of file stm8s_adc1.c.

References IS_ADC1_FLAG_OK.

void ADC1_ClearITPendingBit ( ADC1_IT_TypeDef ITPendingBit )

Clear the ADC1 End of Conversion pending bit.

Parameters:
ITPendingBit : the IT pending bit to clear. This parameter can be one of the following values:
  • ADC1_IT_AWD : Analog WDG IT status
  • ADC1_IT_AWS0 : Analog channel 0 IT status
  • ADC1_IT_AWS1 : Analog channel 1 IT status
  • ADC1_IT_AWS2 : Analog channel 2 IT status
  • ADC1_IT_AWS3 : Analog channel 3 IT status
  • ADC1_IT_AWS4 : Analog channel 4 IT status
  • ADC1_IT_AWS5 : Analog channel 5 IT status
  • ADC1_IT_AWS6 : Analog channel 6 IT status
  • ADC1_IT_AWS7 : Analog channel 7 IT status
  • ADC1_IT_AWS8 : Analog channel 8 IT status
  • ADC1_IT_AWS9 : Analog channel 9 IT status
  • ADC1_IT_EOC : EOC pending bit
Return values:
None

Definition at line 662 of file stm8s_adc1.c.

References IS_ADC1_ITPENDINGBIT_OK.

void ADC1_Cmd ( FunctionalState NewState )

Enables or Disables the ADC1 peripheral.

Parameters:
NewState,: specifies the peripheral enabled or disabled state.
Return values:
None

Definition at line 126 of file stm8s_adc1.c.

References DISABLE, and IS_FUNCTIONALSTATE_OK.

void ADC1_ConversionConfig | ( | ADC1_ConvMode_TypeDef | ADC1_ConversionMode,
 |  | ADC1_Channel_TypeDef | ADC1_Channel,
 |  | ADC1_Align_TypeDef | ADC1_Align
 | ) |  |

Configure the ADC1 conversion on selected channel.

Parameters:
ADC1_ConversionMode | Specifies the conversion type. It can be set of the values of ADC1_ConvMode_TypeDef
ADC1_Channel | specifies the ADC1 Channel. It can be set of the values of ADC1_Channel_TypeDef
ADC1_Align | specifies the converted data alignment. It can be set of the values of ADC1_Align_TypeDef
Return values:
None

Definition at line 286 of file stm8s_adc1.c.

References ADC1_CONVERSIONMODE_CONTINUOUS, IS_ADC1_ALIGN_OK, IS_ADC1_CHANNEL_OK, and IS_ADC1_CONVERSIONMODE_OK.

Referenced by ADC1_Init().

void ADC1_DataBufferCmd ( FunctionalState NewState )

Enables or Disables the ADC1 data store into the Data Buffer registers rather than in the Data Register.

Parameters:
NewState,: specifies the selected mode enabled or disabled state.
Return values:
None

Definition at line 166 of file stm8s_adc1.c.

References DISABLE, and IS_FUNCTIONALSTATE_OK.

void ADC1_DeInit ( void )

Deinitializes the ADC1 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 52 of file stm8s_adc1.c.

void ADC1_ExternalTriggerConfig | ( | ADC1_ExtTrig_TypeDef | ADC1_ExtTrigger,
 |  | FunctionalState | NewState
 | ) |  |

Configure the ADC1 conversion on external trigger event.

Full description:
The selected external trigger event can be enabled or disabled.
Parameters:
ADC1_ExtTrigger | to select the External trigger event. can have one of the values of ADC1_ExtTrig_TypeDef.
NewState | to enable/disable the selected external trigger can have one of the values of FunctionalState.
Return values:
None

Definition at line 325 of file stm8s_adc1.c.

References DISABLE, IS_ADC1_EXTTRIG_OK, and IS_FUNCTIONALSTATE_OK.

Referenced by ADC1_Init().

FlagStatus ADC1_GetAWDChannelStatus ( ADC1_Channel_TypeDef Channel )

Checks the specified analog watchdog channel status.

Parameters:
Channel,: specify the channel of which to check the analog watchdog can be one of the values of ADC1_Channel_TypeDef.
Return values:
FlagStatus Status of the analog watchdog.

Definition at line 502 of file stm8s_adc1.c.

References IS_ADC1_CHANNEL_OK.

uint16_t ADC1_GetBufferValue ( uint8_t Buffer )

Get one sample of measured signal.

Parameters:
Buffer specifies the buffer to read.
Return values:
BufferValue,: value read from the given buffer.
Required preconditions:
ADC1 conversion finished.

Definition at line 466 of file stm8s_adc1.c.

References ADC1_BaseAddress, and IS_ADC1_BUFFER_OK.

uint16_t ADC1_GetConversionValue ( void )

Get one sample of measured signal.

Parameters:
None
Return values:
ConversionValue,: value of the measured signal.
Required preconditions:
ADC1 conversion finished.

Definition at line 370 of file stm8s_adc1.c.

FlagStatus ADC1_GetFlagStatus ( ADC1_Flag_TypeDef Flag )

Checks the specified ADC1 flag status.

Parameters:
Flag,: ADC1 flag. can be one of the values of ADC1_Flag_TypeDef.
Return values:
FlagStatus Status of the ADC1 flag.

Definition at line 527 of file stm8s_adc1.c.

References IS_ADC1_FLAG_OK.

ITStatus ADC1_GetITStatus ( ADC1_IT_TypeDef ITPendingBit )

Returns the specified pending bit status.

Parameters:
ITPendingBit : the IT pending bit to check. This parameter can be one of the following values:
  • ADC1_IT_AWD : Analog WDG IT status
  • ADC1_IT_AWS0 : Analog channel 0 IT status
  • ADC1_IT_AWS1 : Analog channel 1 IT status
  • ADC1_IT_AWS2 : Analog channel 2 IT status
  • ADC1_IT_AWS3 : Analog channel 3 IT status
  • ADC1_IT_AWS4 : Analog channel 4 IT status
  • ADC1_IT_AWS5 : Analog channel 5 IT status
  • ADC1_IT_AWS6 : Analog channel 6 IT status
  • ADC1_IT_AWS7 : Analog channel 7 IT status
  • ADC1_IT_AWS8 : Analog channel 8 IT status
  • ADC1_IT_AWS9 : Analog channel 9 IT status
  • ADC1_IT_EOC : EOC pending bit
Return values:
ITStatus,: status of the specified pending bit.

Definition at line 616 of file stm8s_adc1.c.

References IS_ADC1_ITPENDINGBIT_OK, and RESET.

void ADC1_Init | ( | ADC1_ConvMode_TypeDef | ADC1_ConversionMode,
 |  | ADC1_Channel_TypeDef | ADC1_Channel,
 |  | ADC1_PresSel_TypeDef | ADC1_PrescalerSelection,
 |  | ADC1_ExtTrig_TypeDef | ADC1_ExtTrigger,
 |  | FunctionalState | ADC1_ExtTriggerState,
 |  | ADC1_Align_TypeDef | ADC1_Align,
 |  | ADC1_SchmittTrigg_TypeDef | ADC1_SchmittTriggerChannel,
 |  | FunctionalState | ADC1_SchmittTriggerState
 | ) |  |

Initializes the ADC1 peripheral according to the specified parameters.

Parameters:
ADC1_ConversionMode,: specifies the conversion mode can be one of the values of ADC1_ConvMode_TypeDef.
ADC1_Channel,: specifies the channel to convert can be one of the values of ADC1_Channel_TypeDef.
ADC1_PrescalerSelection,: specifies the ADC1 prescaler can be one of the values of ADC1_PresSel_TypeDef.
ADC1_ExtTrigger,: specifies the external trigger can be one of the values of ADC1_ExtTrig_TypeDef.
ADC1_ExtTriggerState,: specifies the external trigger new state can be one of the values of FunctionalState.
ADC1_Align,: specifies the converted data alignment can be one of the values of ADC1_Align_TypeDef.
ADC1_SchmittTriggerChannel,: specifies the schmitt trigger channel can be one of the values of ADC1_SchmittTrigg_TypeDef.
ADC1_SchmittTriggerState,: specifies the schmitt trigger state can be one of the values of FunctionalState.
Return values:
None

Definition at line 88 of file stm8s_adc1.c.

References ADC1_ConversionConfig(), ADC1_ExternalTriggerConfig(), ADC1_PrescalerConfig(), ADC1_SchmittTriggerConfig(), IS_ADC1_ALIGN_OK, IS_ADC1_CHANNEL_OK, IS_ADC1_CONVERSIONMODE_OK, IS_ADC1_EXTTRIG_OK, IS_ADC1_PRESSEL_OK, IS_ADC1_SCHMITTTRIG_OK, and IS_FUNCTIONALSTATE_OK.

void ADC1_ITConfig | ( | ADC1_IT_TypeDef | ADC1_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the ADC1 interrupt.

Parameters:
ADC1_IT specifies the name of the interrupt to enable or disable. This parameter can be one of the following values:
  • ADC1_IT_AWDITEN : Analog WDG interrupt enable
  • ADC1_IT_EOCITEN : EOC iterrupt enable
NewState specifies the state of the interrupt to apply.
Return values:
None

Definition at line 190 of file stm8s_adc1.c.

References DISABLE, IS_ADC1_IT_OK, and IS_FUNCTIONALSTATE_OK.

void ADC1_PrescalerConfig ( ADC1_PresSel_TypeDef ADC1_Prescaler )

Configure the ADC1 prescaler division factor.

Parameters:
ADC1_Prescaler,: the selected precaler. It can be one of the values of ADC1_PresSel_TypeDef.
Return values:
None

Definition at line 214 of file stm8s_adc1.c.

References IS_ADC1_PRESSEL_OK.

Referenced by ADC1_Init().

void ADC1_ScanModeCmd ( FunctionalState NewState )

Enables or Disables the ADC1 scan mode.

Parameters:
NewState,: specifies the selected mode enabled or disabled state.
Return values:
None

Definition at line 146 of file stm8s_adc1.c.

References DISABLE, and IS_FUNCTIONALSTATE_OK.

void ADC1_SchmittTriggerConfig | ( | ADC1_SchmittTrigg_TypeDef | ADC1_SchmittTriggerChannel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the ADC1 Schmitt Trigger on a selected channel.

Parameters:
ADC1_SchmittTriggerChannel | specifies the desired Channel. It can be set of the values of ADC1_SchmittTrigg_TypeDef.
NewState | specifies Channel new status. can have one of the values of FunctionalState.
Return values:
None

Definition at line 233 of file stm8s_adc1.c.

References ADC1_SCHMITTTRIG_ALL, ADC1_SCHMITTTRIG_CHANNEL8, DISABLE, IS_ADC1_SCHMITTTRIG_OK, and IS_FUNCTIONALSTATE_OK.

Referenced by ADC1_Init().

void ADC1_SetHighThreshold ( uint16_t Threshold )

Sets the high threshold of the analog watchdog.

Parameters:
Threshold specifies the high threshold value. this value depends on the reference voltage range.
Return values:
None

Definition at line 441 of file stm8s_adc1.c.

void ADC1_SetLowThreshold ( uint16_t Threshold )

Sets the low threshold of the analog watchdog.

Parameters:
Threshold specifies the low threshold value. this value depends on the reference voltage range.
Return values:
None

Definition at line 453 of file stm8s_adc1.c.

void ADC1_StartConversion ( void )

Start ADC1 conversion.

Full description:
This function triggers the start of conversion, after ADC1 configuration.
Parameters:
None
Return values:
None
Required preconditions:
Enable the ADC1 peripheral before calling this function

Definition at line 358 of file stm8s_adc1.c.


STM8S/A Standard Peripherals Drivers: ADC2_Public_Functions

Functions
ADC2_Public_Functions
STM8S_StdPeriph_Driver

Functions

void | ADC2_ClearFlag (void)
Clear the ADC2 EOC Flag.
void | ADC2_ClearITPendingBit (void)
Clear the ADC2 End of Conversion pending bit.
void | ADC2_Cmd (FunctionalState NewState)
Enables or Disables the ADC2 peripheral.
void | ADC2_ConversionConfig (ADC2_ConvMode_TypeDef ADC2_ConversionMode, ADC2_Channel_TypeDef ADC2_Channel, ADC2_Align_TypeDef ADC2_Align)
Configure the ADC2 conversion on selected channel.
void | ADC2_DeInit (void)
Deinitializes the ADC2 peripheral registers to their default reset values.
void | ADC2_ExternalTriggerConfig (ADC2_ExtTrig_TypeDef ADC2_ExtTrigger, FunctionalState NewState)
Configure the ADC2 conversion on external trigger event.
uint16_t | ADC2_GetConversionValue (void)
Get one sample of measured signal.
FlagStatus | ADC2_GetFlagStatus (void)
Checks the ADC2 EOC flag status.
ITStatus | ADC2_GetITStatus (void)
Returns the EOC pending bit status.
void | ADC2_Init (ADC2_ConvMode_TypeDef ADC2_ConversionMode, ADC2_Channel_TypeDef ADC2_Channel, ADC2_PresSel_TypeDef ADC2_PrescalerSelection, ADC2_ExtTrig_TypeDef ADC2_ExtTrigger, FunctionalState ADC2_ExtTriggerState, ADC2_Align_TypeDef ADC2_Align, ADC2_SchmittTrigg_TypeDef ADC2_SchmittTriggerChannel, FunctionalState ADC2_SchmittTriggerState)
Initializes the ADC2 peripheral according to the specified parameters.
void | ADC2_ITConfig (FunctionalState NewState)
Enables or disables the ADC2 interrupt.
void | ADC2_PrescalerConfig (ADC2_PresSel_TypeDef ADC2_Prescaler)
Configure the ADC2 prescaler division factor.
void | ADC2_SchmittTriggerConfig (ADC2_SchmittTrigg_TypeDef ADC2_SchmittTriggerChannel, FunctionalState NewState)
Enables or disables the ADC2 Schmitt Trigger on a selected channel.
void | ADC2_StartConversion (void)
Start ADC2 conversion.

Function Documentation

void ADC2_ClearFlag ( void )

Clear the ADC2 EOC Flag.

Parameters:
None
Return values:
None

Definition at line 363 of file stm8s_adc2.c.

void ADC2_ClearITPendingBit ( void )

Clear the ADC2 End of Conversion pending bit.

Parameters:
None
Return values:
None

Definition at line 384 of file stm8s_adc2.c.

void ADC2_Cmd ( FunctionalState NewState )

Enables or Disables the ADC2 peripheral.

Parameters:
NewState,: specifies the peripheral enabled or disabled state.
Return values:
None

Definition at line 121 of file stm8s_adc2.c.

References DISABLE, and IS_FUNCTIONALSTATE_OK.

void ADC2_ConversionConfig | ( | ADC2_ConvMode_TypeDef | ADC2_ConversionMode,
 |  | ADC2_Channel_TypeDef | ADC2_Channel,
 |  | ADC2_Align_TypeDef | ADC2_Align
 | ) |  |

Configure the ADC2 conversion on selected channel.

Parameters:
ADC2_ConversionMode | Specifies the conversion type. It can be set of the values of ADC2_ConvMode_TypeDef
ADC2_Channel | specifies the ADC2 Channel. It can be set of the values of ADC2_Channel_TypeDef
ADC2_Align | specifies the converted data alignment. It can be set of the values of ADC2_Align_TypeDef
Return values:
None

Definition at line 236 of file stm8s_adc2.c.

References ADC2_CONVERSIONMODE_CONTINUOUS, IS_ADC2_ALIGN_OK, IS_ADC2_CHANNEL_OK, and IS_ADC2_CONVERSIONMODE_OK.

Referenced by ADC2_Init().

void ADC2_DeInit ( void )

Deinitializes the ADC2 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 54 of file stm8s_adc2.c.

void ADC2_ExternalTriggerConfig | ( | ADC2_ExtTrig_TypeDef | ADC2_ExtTrigger,
 |  | FunctionalState | NewState
 | ) |  |

Configure the ADC2 conversion on external trigger event.

Full description:
The selected external trigger event can be enabled or disabled.
Parameters:
ADC2_ExtTrigger | to select the External trigger event. can have one of the values of ADC2_ExtTrig_TypeDef.
NewState | to enable/disable the selected external trigger can have one of the values of FunctionalState.
Return values:
None

Definition at line 275 of file stm8s_adc2.c.

References DISABLE, IS_ADC2_EXTTRIG_OK, and IS_FUNCTIONALSTATE_OK.

Referenced by ADC2_Init().

uint16_t ADC2_GetConversionValue ( void )

Get one sample of measured signal.

Parameters:
None
Return values:
ConversionValue,: value of the measured signal.
Required preconditions:
ADC2 conversion finished.

Definition at line 320 of file stm8s_adc2.c.

FlagStatus ADC2_GetFlagStatus ( void )

Checks the ADC2 EOC flag status.

Parameters:
None
Return values:
FlagStatus Status of the ADC2 EOC flag.

Definition at line 352 of file stm8s_adc2.c.

ITStatus ADC2_GetITStatus ( void )

Returns the EOC pending bit status.

Parameters:
None
Return values:
FlagStatus,: status of the EOC pending bit.

Definition at line 374 of file stm8s_adc2.c.

void ADC2_Init | ( | ADC2_ConvMode_TypeDef | ADC2_ConversionMode,
 |  | ADC2_Channel_TypeDef | ADC2_Channel,
 |  | ADC2_PresSel_TypeDef | ADC2_PrescalerSelection,
 |  | ADC2_ExtTrig_TypeDef | ADC2_ExtTrigger,
 |  | FunctionalState | ADC2_ExtTriggerState,
 |  | ADC2_Align_TypeDef | ADC2_Align,
 |  | ADC2_SchmittTrigg_TypeDef | ADC2_SchmittTriggerChannel,
 |  | FunctionalState | ADC2_SchmittTriggerState
 | ) |  |

Initializes the ADC2 peripheral according to the specified parameters.

Parameters:
ADC2_ConversionMode,: specifies the conversion mode can be one of the values of ADC2_ConvMode_TypeDef.
ADC2_Channel,: specifies the channel to convert can be one of the values of ADC2_Channel_TypeDef.
ADC2_PrescalerSelection,: specifies the ADC2 prescaler can be one of the values of ADC2_PresSel_TypeDef.
ADC2_ExtTrigger,: specifies the external trigger can be one of the values of ADC2_ExtTrig_TypeDef.
ADC2_ExtTriggerState,: specifies the external trigger new state can be one of the values of FunctionalState.
ADC2_Align,: specifies the converted data alignment can be one of the values of ADC2_Align_TypeDef.
ADC2_SchmittTriggerChannel,: specifies the schmitt trigger channel can be one of the values of ADC2_SchmittTrigg_TypeDef.
ADC2_SchmittTriggerState,: specifies the schmitt trigger state can be one of the values of FunctionalState.
Return values:
None

Definition at line 83 of file stm8s_adc2.c.

References ADC2_ConversionConfig(), ADC2_ExternalTriggerConfig(), ADC2_PrescalerConfig(), ADC2_SchmittTriggerConfig(), IS_ADC2_ALIGN_OK, IS_ADC2_CHANNEL_OK, IS_ADC2_CONVERSIONMODE_OK, IS_ADC2_EXTTRIG_OK, IS_ADC2_PRESSEL_OK, IS_ADC2_SCHMITTTRIG_OK, and IS_FUNCTIONALSTATE_OK.

void ADC2_ITConfig ( FunctionalState NewState )

Enables or disables the ADC2 interrupt.

Parameters:
NewState specifies the state of ADC2 interrupt.
Return values:
None

Definition at line 141 of file stm8s_adc2.c.

References DISABLE, and IS_FUNCTIONALSTATE_OK.

void ADC2_PrescalerConfig ( ADC2_PresSel_TypeDef ADC2_Prescaler )

Configure the ADC2 prescaler division factor.

Parameters:
ADC2_Prescaler,: the selected prescaler. It can be one of the values of ADC2_PresSel_TypeDef.
Return values:
None

Definition at line 164 of file stm8s_adc2.c.

References IS_ADC2_PRESSEL_OK.

Referenced by ADC2_Init().

void ADC2_SchmittTriggerConfig | ( | ADC2_SchmittTrigg_TypeDef | ADC2_SchmittTriggerChannel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the ADC2 Schmitt Trigger on a selected channel.

Parameters:
ADC2_SchmittTriggerChannel | specifies the desired Channel. It can be set of the values of ADC2_SchmittTrigg_TypeDef.
NewState | specifies the Channel ADC2 Schmitt Trigger new status. can have one of the values of FunctionalState.
Return values:
None

Definition at line 183 of file stm8s_adc2.c.

References ADC2_SCHMITTTRIG_ALL, ADC2_SCHMITTTRIG_CHANNEL8, DISABLE, IS_ADC2_SCHMITTTRIG_OK, and IS_FUNCTIONALSTATE_OK.

Referenced by ADC2_Init().

void ADC2_StartConversion ( void )

Start ADC2 conversion.

Full description:
This function triggers the start of conversion, after ADC2 configuration.
Parameters:
None
Return values:
None
Required preconditions:
Enable the ADC2 peripheral before calling this function

Definition at line 308 of file stm8s_adc2.c.


STM8S/A Standard Peripherals Drivers: AWU_Public_Functions

Functions
AWU_Public_Functions
STM8S_StdPeriph_Driver

Functions

void | AWU_Cmd (FunctionalState NewState)
Enable or disable the AWU peripheral.
void | AWU_DeInit (void)
Deinitializes the AWU peripheral registers to their default reset values.
FlagStatus | AWU_GetFlagStatus (void)
Returns status of the AWU peripheral flag.
void | AWU_IdleModeEnable (void)
Configures AWU in Idle mode to reduce power consumption.
void | AWU_Init (AWU_Timebase_TypeDef AWU_TimeBase)
Initializes the AWU peripheral according to the specified parameters.
void | AWU_LSICalibrationConfig (uint32_t LSIFreqHz)
Update APR register with the measured LSI frequency.

Function Documentation

void AWU_Cmd ( FunctionalState NewState )

Enable or disable the AWU peripheral.

Parameters:
NewState Indicates the new state of the AWU peripheral.
Return values:
None
Required preconditions:
Initialisation of AWU and LS RC calibration must be done before.

Definition at line 112 of file stm8s_awu.c.

References AWU, AWU_CSR_AWUEN, and DISABLE.

void AWU_DeInit ( void )

Deinitializes the AWU peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 73 of file stm8s_awu.c.

References AWU, AWU_APR_RESET_VALUE, AWU_CSR_RESET_VALUE, and AWU_TBR_RESET_VALUE.

FlagStatus AWU_GetFlagStatus ( void )

Returns status of the AWU peripheral flag.

Parameters:
None
Return values:
FlagStatus : Status of the AWU flag. This parameter can be any of the FlagStatus enumeration.

Definition at line 183 of file stm8s_awu.c.

References AWU, AWU_CSR_AWUF, RESET, and SET.

void AWU_IdleModeEnable ( void )

Configures AWU in Idle mode to reduce power consumption.

Parameters:
None
Return values:
None

Definition at line 168 of file stm8s_awu.c.

References AWU, AWU_CSR_AWUEN, and AWU_TBR_AWUTB.

void AWU_Init ( AWU_Timebase_TypeDef AWU_TimeBase )

Initializes the AWU peripheral according to the specified parameters.

Parameters:
AWU_TimeBase : Time base selection (interval between AWU interrupts). can be one of the values of AWU_Timebase_TypeDef.
Return values:
None
Required preconditions:
The LS RC calibration must be performed before calling this function.

Definition at line 88 of file stm8s_awu.c.

References APR_Array, AWU, AWU_APR_APR, AWU_CSR_AWUEN, AWU_TBR_AWUTB, IS_AWU_TIMEBASE_OK, and TBR_Array.

void AWU_LSICalibrationConfig ( uint32_t LSIFreqHz )

Update APR register with the measured LSI frequency.

Note on the APR calculation:
A is the integer part of lsifreqkhz/4 and x the decimal part. x <= A/(1+2A) is equivalent to A >= x(1+2A) and also to 4A >= 4x(1+2A) [F1] but we know that A + x = lsifreqkhz/4 ==> 4x = lsifreqkhz-4A so [F1] can be written : 4A >= (lsifreqkhz-4A)(1+2A)
Parameters:
LSIFreqHz Low Speed RC frequency measured by timer (in Hz).
Return values:
None
Required preconditions:
  • AWU must be disabled to avoid unwanted interrupts.

Definition at line 139 of file stm8s_awu.c.

References AWU, and IS_LSI_FREQUENCY_OK.


STM8S/A Standard Peripherals Drivers: BEEP_Public_Functions

Functions
BEEP_Public_Functions
STM8S_StdPeriph_Driver

Functions

void | BEEP_Cmd (FunctionalState NewState)
Enable or disable the BEEP function.
void | BEEP_DeInit (void)
Deinitializes the BEEP peripheral registers to their default reset values.
void | BEEP_Init (BEEP_Frequency_TypeDef BEEP_Frequency)
Initializes the BEEP function according to the specified parameters.
void | BEEP_LSICalibrationConfig (uint32_t LSIFreqHz)
Update CSR register with the measured LSI frequency.

Function Documentation

void BEEP_Cmd ( FunctionalState NewState )

Enable or disable the BEEP function.

Parameters:
NewState Indicates the new state of the BEEP function.
Return values:
None
Required preconditions:
Initialisation of BEEP and LS RC calibration must be done before.

Definition at line 91 of file stm8s_beep.c.

References BEEP, BEEP_CSR_BEEPEN, and DISABLE.

void BEEP_DeInit ( void )

Deinitializes the BEEP peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 54 of file stm8s_beep.c.

References BEEP, and BEEP_CSR_RESET_VALUE.

void BEEP_Init ( BEEP_Frequency_TypeDef BEEP_Frequency )

Initializes the BEEP function according to the specified parameters.

Parameters:
BEEP_Frequency Frequency selection. can be one of the values of BEEP_Frequency_TypeDef.
Return values:
None
Required preconditions:
The LS RC calibration must be performed before calling this function.

Definition at line 67 of file stm8s_beep.c.

References BEEP, BEEP_CALIBRATION_DEFAULT, BEEP_CSR_BEEPDIV, BEEP_CSR_BEEPSEL, and IS_BEEP_FREQUENCY_OK.

void BEEP_LSICalibrationConfig ( uint32_t LSIFreqHz )

Update CSR register with the measured LSI frequency.

Note on the APR calculation:
A is the integer part of LSIFreqkHz/4 and x the decimal part. x <= A/(1+2A) is equivalent to A >= x(1+2A) and also to 4A >= 4x(1+2A) [F1] but we know that A + x = LSIFreqkHz/4 ==> 4x = LSIFreqkHz-4A so [F1] can be written : 4A >= (LSIFreqkHz-4A)(1+2A)
Parameters:
LSIFreqHz Low Speed RC frequency measured by timer (in Hz).
Return values:
None
Required preconditions:
  • BEEP must be disabled to avoid unwanted interrupts.

Definition at line 118 of file stm8s_beep.c.

References BEEP, BEEP_CSR_BEEPDIV, and IS_LSI_FREQUENCY_OK.


STM8S/A Standard Peripherals Drivers: CAN_Public_Functions

Functions
CAN_Public_Functions
STM8S_StdPeriph_Driver

Functions

void | CAN_CancelTransmit (CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox)
Cancels a transmit request.
void | CAN_ClearFlag (CAN_FLAG_TypeDef CAN_Flag)
Clears the CAN's pending flags.
void | CAN_ClearITPendingBit (CAN_IT_TypeDef CAN_IT)
Clears the CAN’s interrupt pending bits.
void | CAN_DeInit (void)
Deinitializes the CAN peripheral registers to their default reset values.
void | CAN_FIFORelease (void)
Releases the CAN FIFO.
void | CAN_FilterInit (CAN_FilterNumber_TypeDef CAN_FilterNumber, FunctionalState CAN_FilterActivation, CAN_FilterMode_TypeDef CAN_FilterMode, CAN_FilterScale_TypeDef CAN_FilterScale, uint8_t CAN_FilterID1, uint8_t CAN_FilterID2, uint8_t CAN_FilterID3, uint8_t CAN_FilterID4, uint8_t CAN_FilterIDMask1, uint8_t CAN_FilterIDMask2, uint8_t CAN_FilterIDMask3, uint8_t CAN_FilterIDMask4)
Initializes the CAN peripheral Filter according to the specified parameters.
FlagStatus | CAN_GetFlagStatus (CAN_FLAG_TypeDef CAN_Flag)
Checks whether the specified CAN flag is set or not.
ITStatus | CAN_GetITStatus (CAN_IT_TypeDef CAN_IT)
Checks whether the specified CAN interrupt has occurred or not.
CAN_ErrorCode_TypeDef | CAN_GetLastErrorCode (void)
Gets the Last Error Code.
uint16_t | CAN_GetMessageTimeStamp (void)
Returns the Received time stamp.
uint8_t | CAN_GetReceivedData (uint8_t CAN_DataIndex)
Gets the CAN Data of the received message.
uint8_t | CAN_GetReceivedDLC (void)
Gets the CAN DLC of the received message.
uint8_t | CAN_GetReceivedFMI (void)
Gets the CAN FMI of the received message.
uint32_t | CAN_GetReceivedId (void)
Gets the CAN Id of the received message.
CAN_Id_TypeDef | CAN_GetReceivedIDE (void)
Gets the CAN IDE of the received message.
CAN_RTR_TypeDef | CAN_GetReceivedRTR (void)
Gets the CAN RTR of the received message.
CAN_Page_TypeDef | CAN_GetSelectedPage (void)
Gets the selected registers page.
CAN_InitStatus_TypeDef | CAN_Init (CAN_MasterCtrl_TypeDef CAN_MasterCtrl, CAN_Mode_TypeDef CAN_Mode, CAN_SynJumpWidth_TypeDef CAN_SynJumpWidth, CAN_BitSeg1_TypeDef CAN_BitSeg1, CAN_BitSeg2_TypeDef CAN_BitSeg2, uint8_t CAN_Prescaler)
Initializes the CAN peripheral according to the specified parameters.
void | CAN_ITConfig (CAN_IT_TypeDef CAN_IT, FunctionalState NewState)
Enables or disables the specified CAN interrupts.
CAN_NbrPendingMessage_TypeDef | CAN_MessagePending (void)
Returns the number of pending messages.
CAN_ModeStatus_TypeDef | CAN_OperatingModeRequest (CAN_OperatingMode_TypeDef CAN_OperatingMode)
Select the CAN Operation mode.
void | CAN_Receive (void)
Receives a message which contains CAN Id, IDE, RTR DLC, data and FMI number.
void | CAN_SelectPage (CAN_Page_TypeDef CAN_Page)
Sets the registers page to be selected.
CAN_Sleep_TypeDef | CAN_Sleep (void)
Enters the Sleep low power mode.
void | CAN_ST7CompatibilityCmd (CAN_ST7Compatibility_TypeDef CAN_ST7Compatibility)
Enables or Disables the ST7 CAN Compatibility.
CAN_TxStatus_TypeDef | CAN_Transmit (uint32_t CAN_Id, CAN_Id_TypeDef CAN_IDE, CAN_RTR_TypeDef CAN_RTR, uint8_t CAN_DLC, uint8_t *CAN_Data)
Initiates the transmission of a message.
CAN_TxStatus_TypeDef | CAN_TransmitStatus (CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox)
Checks the transmission of a message.
void | CAN_TTComModeCmd (FunctionalState NewState)
Enables or disables the CAN Time TriggerOperation communication mode.
CAN_WakeUp_TypeDef | CAN_WakeUp (void)
Wakes the CAN up.
static ITStatus | CheckITStatus (uint8_t CAN_Reg, uint8_t It_Bit)
Checks whether the CAN interrupt has occurred or not.

Function Documentation

void CAN_CancelTransmit ( CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox )

Cancels a transmit request.

Parameters:
CAN_TransmitMailbox : the Transmission mailbox, can be one of CAN_TransmitMailBox_TypeDef
Return values:
None

Definition at line 724 of file stm8s_can.c.

References CAN_GetSelectedPage(), CAN_MCSR_ABRQ, CAN_SelectPage(), and IS_CAN_TRANSMITMAILBOX_OK.

void CAN_ClearFlag ( CAN_FLAG_TypeDef CAN_Flag )

Clears the CAN's pending flags.

Parameters:
CAN_Flag : Flag to be cleared, can be one of the following parameters: CAN_FLAG_RQCP0 Request MailBox0 Flag CAN_FLAG_RQCP1 Request MailBox1 Flag CAN_FLAG_RQCP2 Request MailBox2 Flag CAN_FLAG_FF FIFO Full Flag CAN_FLAG_FOV FIFO Overrun Flag CAN_FLAG_WKU wake up Flag CAN_FLAG_LEC Last error code Flag
Return values:
None

Definition at line 1077 of file stm8s_can.c.

References CAN_GetSelectedPage(), CAN_Page_Config, CAN_SelectPage(), IS_CAN_FLAG_CLEAR_OK, and RESET.

void CAN_ClearITPendingBit ( CAN_IT_TypeDef CAN_IT )

Clears the CAN’s interrupt pending bits.

Parameters:
CAN_IT,: specifies the interrupt pending bit to clear, can be one of the following parameters: CAN_IT_TME = Transmit mailbox empty interrupt CAN_IT_FF =FIFO full interrupt CAN_IT_FOV =FIFO overrun interrupt CAN_IT_WKU =Wake-up interrupt CAN_IT_ERR =General Error interrupt CAN_IT_EWG =Error warning interrupt CAN_IT_EPV =Error passive interrupt CAN_IT_BOF = Bus-off interrupt CAN_IT_LEC =Last error code interrupt
Return values:
None

Definition at line 1348 of file stm8s_can.c.

References CAN_ESR_RESET_VALUE, CAN_GetSelectedPage(), CAN_IT_BOF, CAN_IT_EPV, CAN_IT_ERR, CAN_IT_EWG, CAN_IT_FF, CAN_IT_FOV, CAN_IT_LEC, CAN_IT_TME, CAN_IT_WKU, CAN_MSR_ERRI, CAN_MSR_WKUI, CAN_Page_Config, CAN_RFR_FOVR, CAN_RFR_FULL, CAN_SelectPage(), CAN_TSR_RQCP012, and IS_CAN_IT_PENDING_BIT_OK.

void CAN_DeInit ( void )

Deinitializes the CAN peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 62 of file stm8s_can.c.

References CAN_BTR1_RESET_VALUE, CAN_BTR2_RESET_VALUE, CAN_DGR_RESET_VALUE, CAN_EIER_RESET_VALUE, CAN_ESR_RESET_VALUE, CAN_FCR_RESET_VALUE, CAN_FMR1_RESET_VALUE, CAN_FMR2_RESET_VALUE, CAN_IER_RESET_VALUE, CAN_MCR_INRQ, CAN_MCR_RESET_VALUE, CAN_MDLC_RESET_VALUE, CAN_MSR_RESET_VALUE, CAN_OperatingMode_Initialization, CAN_OperatingMode_Normal, CAN_OperatingModeRequest(), CAN_Page_Config, CAN_Page_RxFifo, CAN_Page_TxMailBox0, CAN_Page_TxMailBox1, CAN_Page_TxMailBox2, CAN_PSR_RESET_VALUE, CAN_RFR_RESET_VALUE, and CAN_TSR_RESET_VALUE.

void CAN_FIFORelease ( void )

Releases the CAN FIFO.

Parameters:
None
Return values:
None

Definition at line 742 of file stm8s_can.c.

References CAN_RFR_RFOM.

Referenced by CAN_Receive().

void CAN_FilterInit | ( | CAN_FilterNumber_TypeDef | CAN_FilterNumber,
 |  | FunctionalState | CAN_FilterActivation,
 |  | CAN_FilterMode_TypeDef | CAN_FilterMode,
 |  | CAN_FilterScale_TypeDef | CAN_FilterScale,
 |  | uint8_t | CAN_FilterID1,
 |  | uint8_t | CAN_FilterID2,
 |  | uint8_t | CAN_FilterID3,
 |  | uint8_t | CAN_FilterID4,
 |  | uint8_t | CAN_FilterIDMask1,
 |  | uint8_t | CAN_FilterIDMask2,
 |  | uint8_t | CAN_FilterIDMask3,
 |  | uint8_t | CAN_FilterIDMask4
 | ) |  |

Initializes the CAN peripheral Filter according to the specified parameters.

Parameters:
CAN_FilterNumber | : CAN Filter number , can be one of CAN_FilterNumber_TypeDef
CAN_FilterActivation | : CAN Filter Activation state , can be one of FunctionalState
CAN_FilterMode | : CAN Filter Mode , can be one of CAN_FilterMode_TypeDef
CAN_FilterScale | : CAN Filter Scale , can be one of CAN_FilterScale_TypeDef
CAN_FilterID1 | : CAN Filter ID 1 , can be a value from 0x00 to 0xFF
CAN_FilterID2 | : CAN Filter ID 2 , can be a value from 0x00 to 0xFF
CAN_FilterID3 | : CAN Filter ID 3 , can be a value from 0x00 to 0xFF
CAN_FilterID4 | : CAN Filter ID 4 , can be a value from 0x00 to 0xFF
CAN_FilterIDMask1 | : CAN Filter ID 1/ Mask 1 , can be a value from 0x00 to 0xFF depending of CAN_FilterMode parameter
CAN_FilterIDMask2 | : CAN Filter ID 2/ Mask 2 , can be a value from 0x00 to 0xFF depending of CAN_FilterMode parameter
CAN_FilterIDMask3 | : CAN Filter ID 3/ Mask 3 , can be a value from 0x00 to 0xFF depending of CAN_FilterMode parameter
CAN_FilterIDMask4 | : CAN Filter ID 4/ Mask 4 , can be a value from 0x00 to 0xFF depending of CAN_FilterMode parameter
Return values:
None

Definition at line 194 of file stm8s_can.c.

References CAN_FCR1_FSC00, CAN_FCR1_FSC01, CAN_FilterMode_IdList, CAN_FilterMode_IdList_IdMask, CAN_FilterMode_IdMask, CAN_FilterNumber_0, CAN_FilterNumber_1, CAN_FilterNumber_2, CAN_FilterNumber_3, CAN_FilterNumber_4, CAN_FilterScale_16_8Bit, CAN_FilterScale_16Bit, CAN_FilterScale_32Bit, CAN_FilterScale_8Bit, CAN_GetSelectedPage(), CAN_IDLIST_IDMASK_MASK, CAN_IDMASK_IDLIST_MASK, CAN_OperatingMode_Initialization, CAN_OperatingMode_Normal, CAN_OperatingModeRequest(), CAN_Page_Config, CAN_Page_Filter01, CAN_Page_Filter23, CAN_Page_Filter45, CAN_SelectPage(), DISABLE, IS_CAN_FILTER_MODE_OK, IS_CAN_FILTER_NUMBER_OK, IS_CAN_FILTER_SCALE_OK, and IS_FUNCTIONALSTATE_OK.

FlagStatus CAN_GetFlagStatus ( CAN_FLAG_TypeDef CAN_Flag )

Checks whether the specified CAN flag is set or not.

Parameters:
CAN_Flag : specifies the flag to check, can be one of CAN_FLAG_TypeDef enumeration.
Return values:
The new state of CAN_FLAG which can be one of FlagStatus.

Definition at line 1119 of file stm8s_can.c.

References CAN_GetSelectedPage(), CAN_Page_Config, CAN_SelectPage(), IS_CAN_FLAG_STATUS_OK, RESET, and SET.

ITStatus CAN_GetITStatus ( CAN_IT_TypeDef CAN_IT )

Checks whether the specified CAN interrupt has occurred or not.

Parameters:
CAN_IT,: specifies the CAN interrupt source to check, can be one of CAN_IT_TypeDef.
Return values:
The new state of CAN_IT, which can be one of ITStatus.

Definition at line 1203 of file stm8s_can.c.

References CAN_EIER_BOFIE, CAN_EIER_EPVIE, CAN_EIER_ERRIE, CAN_EIER_EWGIE, CAN_EIER_LECIE, CAN_ESR_BOFF, CAN_ESR_EPVF, CAN_ESR_EWGF, CAN_ESR_LEC, CAN_GetSelectedPage(), CAN_IER_FFIE, CAN_IER_FMPIE, CAN_IER_FOVIE, CAN_IER_TMEIE, CAN_IER_WKUIE, CAN_IT_BOF, CAN_IT_EPV, CAN_IT_ERR, CAN_IT_EWG, CAN_IT_FF, CAN_IT_FMP, CAN_IT_FOV, CAN_IT_LEC, CAN_IT_TME, CAN_IT_WKU, CAN_MSR_WKUI, CAN_Page_Config, CAN_RFR_FMP01, CAN_RFR_FOVR, CAN_RFR_FULL, CAN_SelectPage(), CAN_TSR_RQCP012, CheckITStatus(), IS_CAN_IT_STATUS_OK, and RESET.

CAN_ErrorCode_TypeDef CAN_GetLastErrorCode ( void )

Gets the Last Error Code.

Parameters:
None
Return values:
Error Code.

Definition at line 1051 of file stm8s_can.c.

References CAN_ErrorCode_NoErr, CAN_ESR_LEC, CAN_GetSelectedPage(), CAN_Page_Config, and CAN_SelectPage().

uint16_t CAN_GetMessageTimeStamp ( void )

Returns the Received time stamp.

Parameters:
None
Return values:
uint16_t the received time stamp.

Definition at line 902 of file stm8s_can.c.

References CAN_GetSelectedPage(), CAN_Page_RxFifo, and CAN_SelectPage().

uint8_t CAN_GetReceivedData ( uint8_t CAN_DataIndex )

Gets the CAN Data of the received message.

Parameters:
CAN_DataIndex : number of the received Data, it can be an integer between 0 to 7.
Return values:
the received CAN message ith Data.
Required preconditions:
This function is used to get data loaded by CAN_Receive function. Before using this function, CAN_Receive function must be called.

Definition at line 878 of file stm8s_can.c.

References _Data, and IS_CAN_DLC_OK.

uint8_t CAN_GetReceivedDLC ( void )

Gets the CAN DLC of the received message.

Parameters:
None
Return values:
the received CAN message DLC.
Required preconditions:
This function is used to get data loaded by CAN_Receive function. Before using this function, CAN_Receive function must be called.

Definition at line 864 of file stm8s_can.c.

References _DLC.

uint8_t CAN_GetReceivedFMI ( void )

Gets the CAN FMI of the received message.

Parameters:
None
Return values:
the received CAN message FMI.
Required preconditions:
This function is used to get data loaded by CAN_Receive function. Before using this function, CAN_Receive function must be called.

Definition at line 892 of file stm8s_can.c.

References _FMI.

uint32_t CAN_GetReceivedId ( void )

Gets the CAN Id of the received message.

Parameters:
None
Return values:
the received CAN message Id.
Required preconditions:
This function is used to get data loaded by CAN_Receive function. Before using this function, CAN_Receive function must be called.

Definition at line 825 of file stm8s_can.c.

References _Id.

CAN_Id_TypeDef CAN_GetReceivedIDE ( void )

Gets the CAN IDE of the received message.

Parameters:
None
Return values:
the received CAN message IDE.
Required preconditions:
This function is used to get data loaded by CAN_Receive function. Before using this function, CAN_Receive function must be called.

Definition at line 838 of file stm8s_can.c.

References _IDE.

CAN_RTR_TypeDef CAN_GetReceivedRTR ( void )

Gets the CAN RTR of the received message.

Parameters:
None
Return values:
the received CAN message RTR.
Required preconditions:
This function is used to get data loaded by CAN_Receive function. Before using this function, CAN_Receive function must be called.

Definition at line 851 of file stm8s_can.c.

References _RTR.

CAN_Page_TypeDef CAN_GetSelectedPage ( void )

Gets the selected registers page.

Parameters:
None
Return values:
the selected page which can be one of the CAN_Page_TypeDef.

Definition at line 1407 of file stm8s_can.c.

Referenced by CAN_CancelTransmit(), CAN_ClearFlag(), CAN_ClearITPendingBit(), CAN_FilterInit(), CAN_GetFlagStatus(), CAN_GetITStatus(), CAN_GetLastErrorCode(), CAN_GetMessageTimeStamp(), CAN_Init(), CAN_ITConfig(), CAN_Receive(), CAN_Transmit(), and CAN_TTComModeCmd().

CAN_InitStatus_TypeDef CAN_Init | ( | CAN_MasterCtrl_TypeDef | CAN_MasterCtrl,
 |  | CAN_Mode_TypeDef | CAN_Mode,
 |  | CAN_SynJumpWidth_TypeDef | CAN_SynJumpWidth,
 |  | CAN_BitSeg1_TypeDef | CAN_BitSeg1,
 |  | CAN_BitSeg2_TypeDef | CAN_BitSeg2,
 |  | uint8_t | CAN_Prescaler
 | ) |  |

Initializes the CAN peripheral according to the specified parameters.

Parameters:
CAN_MasterCtrl | : Master control option, can be one or a combination of CAN_MasterCtrl_TypeDef.
CAN_Mode | : CAN mode , can be one of CAN_Mode_TypeDef.
CAN_SynJumpWidth | : CAN Synchronisation Jump Width , can be one of CAN_SynJumpWidth_TypeDef.
CAN_BitSeg1 | : CAN bit segment 1 , can be one of CAN_BitSeg1_TypeDef.
CAN_BitSeg2 | : CAN bit segment 2 , can be one of CAN_BitSeg2_TypeDef.
CAN_Prescaler | : CAN Baud Rate Prescaler , can be a value from 0x01 to 0xFF.
Return values:
Indicates if initialization is succeed. it can be one of CAN_InitStatus_TypeDef enumeration.

Definition at line 106 of file stm8s_can.c.

References CAN_ACKNOWLEDGE_TIMEOUT, CAN_GetSelectedPage(), CAN_InitStatus_Failed, CAN_InitStatus_Success, CAN_MCR_INRQ, CAN_MSR_INAK, CAN_Page_Config, CAN_SelectPage(), IS_CAN_BITSEG1_OK, IS_CAN_BITSEG2_OK, IS_CAN_MASTERCTRL_OK, IS_CAN_MODE_OK, IS_CAN_PRESCALER_OK, and IS_CAN_SYNJUMPWIDTH_OK.

void CAN_ITConfig | ( | CAN_IT_TypeDef | CAN_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified CAN interrupts.

Parameters:
CAN_IT,: specifies the CAN interrupt sources to be enabled or disabled.
NewState : CAN_IT new state , can be one of FunctionalState
Return values:
None

Definition at line 487 of file stm8s_can.c.

References CAN_GetSelectedPage(), CAN_Page_Config, CAN_SelectPage(), DISABLE, IS_CAN_IT_CONFIG_OK, and IS_FUNCTIONALSTATE_OK.

CAN_NbrPendingMessage_TypeDef CAN_MessagePending ( void )

Returns the number of pending messages.

Return values:
Number of pending messages.

Definition at line 752 of file stm8s_can.c.

References CAN_NbrPendingMessage_0, and CAN_RFR_FMP01.

CAN_ModeStatus_TypeDef CAN_OperatingModeRequest ( CAN_OperatingMode_TypeDef CAN_OperatingMode )

Select the CAN Operation mode.

Parameters:
CAN_OperatingMode CAN Operating Mode , this parameter can be one of CAN_OperatingMode_TypeDef enumeration.
Return values:
the status of the requested mode which can be
  • CAN_ModeStatus_Failed CAN failed entering the specific mode
  • CAN_ModeStatus_Success CAN Succeed entering the specific mode

Definition at line 974 of file stm8s_can.c.

References CAN_ACKNOWLEDGE_TIMEOUT, CAN_MCR_INRQ, CAN_MCR_SLEEP, CAN_MODE_MASK, CAN_ModeStatus_Failed, CAN_ModeStatus_Success, CAN_MSR_INAK, CAN_MSR_SLAK, CAN_OperatingMode_Initialization, CAN_OperatingMode_Normal, CAN_OperatingMode_Sleep, and IS_CAN_OPERATINGMODE_OK.

Referenced by CAN_DeInit(), and CAN_FilterInit().

void CAN_Receive ( void )

Receives a message which contains CAN Id, IDE, RTR DLC, data and FMI number.

In order to get these data, use CAN_GetReceivedId(), CAN_GetReceivedIDE(), CAN_GetReceivedRTR(), CAN_GetReceivedDLC(), CAN_GetReceivedFMI() and CAN_GetReceivedData() functions.

Parameters:
None
Return values:
None

Definition at line 767 of file stm8s_can.c.

References _Data, _DLC, _FMI, _Id, _IDE, _RTR, CAN_EXTID_SIZE, CAN_FIFORelease(), CAN_GetSelectedPage(), CAN_Id_Extended, CAN_Id_Standard, CAN_Page_RxFifo, CAN_SelectPage(), and CAN_STDID_SIZE.

void CAN_SelectPage ( CAN_Page_TypeDef CAN_Page )

Sets the registers page to be selected.

Parameters:
CAN_Page,: the selected page which can be one of the CAN_Page_TypeDef.
Return values:
None

Definition at line 1417 of file stm8s_can.c.

Referenced by CAN_CancelTransmit(), CAN_ClearFlag(), CAN_ClearITPendingBit(), CAN_FilterInit(), CAN_GetFlagStatus(), CAN_GetITStatus(), CAN_GetLastErrorCode(), CAN_GetMessageTimeStamp(), CAN_Init(), CAN_ITConfig(), CAN_Receive(), CAN_Transmit(), and CAN_TTComModeCmd().

CAN_Sleep_TypeDef CAN_Sleep ( void )

Enters the Sleep low power mode.

Parameters:
None
Return values:
CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed in an other case.

Definition at line 924 of file stm8s_can.c.

References CAN_MCR_INRQ, CAN_MCR_SLEEP, CAN_MSR_INAK, CAN_MSR_SLAK, CAN_Sleep_Failed, and CAN_Sleep_Ok.

void CAN_ST7CompatibilityCmd ( CAN_ST7Compatibility_TypeDef CAN_ST7Compatibility )

Enables or Disables the ST7 CAN Compatibility.

if the ST7 compatibility is Enabled, CAN provides only 2 mailboxes. if the ST7 compatibility is Disabled, CAN provides 3 mailboxes.

Parameters:
CAN_ST7Compatibility : CAN ST7 Compatibility , this parameter can be one of CAN_ST7Compatibility_TypeDef enumeration.
Return values:
None

Definition at line 525 of file stm8s_can.c.

References CAN_DGR_TXM2E, and IS_CAN_ST7_COMPATIBILITY_OK.

CAN_TxStatus_TypeDef CAN_Transmit | ( | uint32_t | CAN_Id,
 |  | CAN_Id_TypeDef | CAN_IDE,
 |  | CAN_RTR_TypeDef | CAN_RTR,
 |  | uint8_t | CAN_DLC,
 |  | uint8_t * | CAN_Data
 | ) |  |

Initiates the transmission of a message.

Parameters:
CAN_Id | the ID number of the message, its size depends on CAN_IDE value.
[in] | CAN_IDE | the ID type of the message, this parameter can be one of the CAN_Id_TypeDef enumeration.
[in] | CAN_RTR | the message type, this parameter can be one of the CAN_RTR_TypeDef enumeration.
[in] | CAN_DLC | the number of data in the message type, this parameter can be a value between 0 to 7.
[in] | CAN_Data | pointer to a the uint8_t table which contains data to sent.
Return values:
Transmit Status, this returned value can be one of the CAN_TxStatus_TypeDef enumeration.

Definition at line 587 of file stm8s_can.c.

References CAN_EXTID_SIZE, CAN_GetSelectedPage(), CAN_Id_Standard, CAN_MCSR_TXRQ, CAN_SelectPage(), CAN_STDID_SIZE, CAN_TPR_TME0, CAN_TPR_TME1, CAN_TPR_TME2, CAN_TxStatus_MailBox0Ok, CAN_TxStatus_MailBox1Ok, CAN_TxStatus_MailBox2Ok, CAN_TxStatus_NoMailBox, IS_CAN_DLC_OK, IS_CAN_EXTID_OK, IS_CAN_IDTYPE_OK, IS_CAN_RTR_OK, and IS_CAN_STDID_OK.

CAN_TxStatus_TypeDef CAN_TransmitStatus ( CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox )

Checks the transmission of a message.

Parameters:
CAN_TransmitMailbox : the number of the mailbox that is used for transmission, can be on of CAN_TransmitMailBox_TypeDef.
Return values:
CAN_TxStatus_Ok if the CAN driver transmits the message, CAN_TxStatus_Failed in an other case.

Definition at line 672 of file stm8s_can.c.

References CAN_TPR_TME0, CAN_TPR_TME1, CAN_TPR_TME2, CAN_TransmitMailBox_0, CAN_TransmitMailBox_1, CAN_TransmitMailBox_2, CAN_TSR_RQCP0, CAN_TSR_RQCP1, CAN_TSR_RQCP2, CAN_TSR_TXOK0, CAN_TSR_TXOK1, CAN_TSR_TXOK2, CAN_TxStatus_Failed, CAN_TxStatus_MailBoxEmpty, CAN_TxStatus_Ok, CAN_TxStatus_Pending, and IS_CAN_TRANSMITMAILBOX_OK.

void CAN_TTComModeCmd ( FunctionalState NewState )

Enables or disables the CAN Time TriggerOperation communication mode.

Parameters:
NewState : Mode new state , can be one of FunctionalState
Return values:
None

Definition at line 541 of file stm8s_can.c.

References CAN_GetSelectedPage(), CAN_MCR_TTCM, CAN_MDLCR_TGT, CAN_Page_RxFifo, CAN_Page_TxMailBox0, CAN_Page_TxMailBox1, CAN_Page_TxMailBox2, CAN_SelectPage(), DISABLE, and IS_FUNCTIONALSTATE_OK.

CAN_WakeUp_TypeDef CAN_WakeUp ( void )

Wakes the CAN up.

Parameters:
None
Return values:
CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed in an other case.

Definition at line 947 of file stm8s_can.c.

References CAN_MCR_SLEEP, CAN_MSR_SLAK, CAN_WakeUp_Failed, and CAN_WakeUp_Ok.

static ITStatus CheckITStatus | ( | uint8_t | CAN_Reg,
 |  | uint8_t | It_Bit
 | ) |  | [static]

Checks whether the CAN interrupt has occurred or not.

Parameters:
CAN_Reg,: specifies the CAN interrupt register to check.
It_Bit,: specifies the interrupt source bit to check.
Return values:
The new state of the CAN Interrupt, which can be one of ITStatus.

Definition at line 1428 of file stm8s_can.c.

References RESET, and SET.

Referenced by CAN_GetITStatus().


STM8S/A Standard Peripherals Drivers: CLK_Private_Constants

Variables
CLK_Private_Constants
STM8S_StdPeriph_Driver

Variables

CONST uint8_t | CLKPrescTable [8] = {1, 2, 4, 8, 10, 16, 20, 40}
CONST uint8_t | HSIDivFactor [4] = {1, 2, 4, 8}

Variable Documentation

CONST uint8_t CLKPrescTable[8] = {1, 2, 4, 8, 10, 16, 20, 40}

Holds the different CLK prescaler values

Definition at line 49 of file stm8s_clk.c.

CONST uint8_t HSIDivFactor[4] = {1, 2, 4, 8}

Holds the different HSI Divider factors

Definition at line 48 of file stm8s_clk.c.

Referenced by CLK_GetClockFreq().


STM8S/A Standard Peripherals Drivers: CLK_Public_Functions

Functions
CLK_Public_Functions
STM8S_StdPeriph_Driver

Functions

void | CLK_AdjustHSICalibrationValue (CLK_HSITrimValue_TypeDef CLK_HSICalibrationValue)
Adjusts the Internal High Speed oscillator (HSI) calibration value.
void | CLK_CCOCmd (FunctionalState NewState)
Enables or disablle the Configurable Clock Output (CCO).
void | CLK_CCOConfig (CLK_Output_TypeDef CLK_CCO)
Output the selected clock on a dedicated I/O pin.
void | CLK_ClearITPendingBit (CLK_IT_TypeDef CLK_IT)
Clears the CLK’s interrupt pending bits.
void | CLK_ClockSecuritySystemEnable (void)
Enables the Clock Security System.
void | CLK_ClockSwitchCmd (FunctionalState NewState)
Starts or Stops manually the clock switch execution.
ErrorStatus | CLK_ClockSwitchConfig (CLK_SwitchMode_TypeDef CLK_SwitchMode, CLK_Source_TypeDef CLK_NewClock, FunctionalState ITState, CLK_CurrentClockState_TypeDef CLK_CurrentClockState)
configures the Switch from one clock to another
void | CLK_DeInit (void)
Deinitializes the CLK peripheral registers to their default reset values.
void | CLK_FastHaltWakeUpCmd (FunctionalState NewState)
Configures the High Speed Internal oscillator (HSI).
uint32_t | CLK_GetClockFreq (void)
This function returns the frequencies of different on chip clocks.
FlagStatus | CLK_GetFlagStatus (CLK_Flag_TypeDef CLK_FLAG)
Checks whether the specified CLK flag is set or not.
ITStatus | CLK_GetITStatus (CLK_IT_TypeDef CLK_IT)
Checks whether the specified CLK interrupt has is enabled or not.
CLK_Source_TypeDef | CLK_GetSYSCLKSource (void)
Returns the clock source used as system clock.
void | CLK_HSECmd (FunctionalState NewState)
Enable or Disable the External High Speed oscillator (HSE).
void | CLK_HSICmd (FunctionalState NewState)
Enables or disables the Internal High Speed oscillator (HSI).
void | CLK_HSIPrescalerConfig (CLK_Prescaler_TypeDef HSIPrescaler)
Configures the HSI clock dividers.
void | CLK_ITConfig (CLK_IT_TypeDef CLK_IT, FunctionalState NewState)
Enables or disables the specified CLK interrupts.
void | CLK_LSICmd (FunctionalState NewState)
Enables or disables the Internal Low Speed oscillator (LSI).
void | CLK_PeripheralClockConfig (CLK_Peripheral_TypeDef CLK_Peripheral, FunctionalState NewState)
Enables or disables the specified peripheral CLK.
void | CLK_SlowActiveHaltWakeUpCmd (FunctionalState NewState)
Configures the slow active halt wake up.
void | CLK_SWIMConfig (CLK_SWIMDivider_TypeDef CLK_SWIMDivider)
Configures the SWIM clock frequency on the fly.
void | CLK_SYSCLKConfig (CLK_Prescaler_TypeDef CLK_Prescaler)
Configures the HSI and CPU clock dividers.
void | CLK_SYSCLKEmergencyClear (void)
Reset the SWBSY flag (SWICR Register)

Function Documentation

void CLK_AdjustHSICalibrationValue ( CLK_HSITrimValue_TypeDef CLK_HSICalibrationValue )

Adjusts the Internal High Speed oscillator (HSI) calibration value.

Full description:
Parameters:
CLK_HSICalibrationValue calibration trimming value. can be one of the values of CLK_HSITrimValue_TypeDef
Return values:
None

Definition at line 604 of file stm8s_clk.c.

References CLK, CLK_HSITRIMR_HSITRIM, and IS_CLK_HSITRIMVALUE_OK.

void CLK_CCOCmd ( FunctionalState NewState )

Enables or disablle the Configurable Clock Output (CCO).

Parameters:
NewState : New state of CCEN bit (CCO register). This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 189 of file stm8s_clk.c.

References CLK, CLK_CCOR_CCOEN, DISABLE, and IS_FUNCTIONALSTATE_OK.

void CLK_CCOConfig ( CLK_Output_TypeDef CLK_CCO )

Output the selected clock on a dedicated I/O pin.

Parameters:
CLK_CCO : Specifies the clock source. This parameter can be any of the CLK_Output_TypeDef enumeration.
Return values:
None
Required preconditions:
The dedicated I/O pin must be set at 1 in the corresponding Px_CR1 register
to be set as input with pull-up or push-pull output.

Definition at line 436 of file stm8s_clk.c.

References CLK, CLK_CCOR_CCOEN, CLK_CCOR_CCOSEL, and IS_CLK_OUTPUT_OK.

void CLK_ClearITPendingBit ( CLK_IT_TypeDef CLK_IT )

Clears the CLK’s interrupt pending bits.

Parameters:
CLK_IT specifies the interrupt pending bits. can be one of the values of CLK_IT_TypeDef
Return values:
None

Definition at line 729 of file stm8s_clk.c.

References CLK, CLK_CSSR_CSSD, CLK_IT_CSSD, CLK_SWCR_SWIF, and IS_CLK_IT_OK.

void CLK_ClockSecuritySystemEnable ( void )

Enables the Clock Security System.

Full description:
once CSS is enabled it cannot be disabled until the next reset.
Parameters:
None
Return values:
None

Definition at line 547 of file stm8s_clk.c.

References CLK, and CLK_CSSR_CSSEN.

void CLK_ClockSwitchCmd ( FunctionalState NewState )

Starts or Stops manually the clock switch execution.

Full description:
NewState parameter set the SWEN.
Parameters:
NewState new state of SWEN, value accepted ENABLE, DISABLE.
Return values:
None

Definition at line 213 of file stm8s_clk.c.

References CLK, CLK_SWCR_SWEN, DISABLE, and IS_FUNCTIONALSTATE_OK.

ErrorStatus CLK_ClockSwitchConfig | ( | CLK_SwitchMode_TypeDef | CLK_SwitchMode,
 |  | CLK_Source_TypeDef | CLK_NewClock,
 |  | FunctionalState | ITState,
 |  | CLK_CurrentClockState_TypeDef | CLK_CurrentClockState
 | ) |  |

configures the Switch from one clock to another

Parameters:
CLK_SwitchMode | select the clock switch mode. It can be set of the values of CLK_SwitchMode_TypeDef
CLK_NewClock | choice of the future clock. It can be set of the values of CLK_Source_TypeDef
ITState | Enable or Disable the Clock Switch interrupt.
CLK_CurrentClockState | current clock to switch OFF or to keep ON. It can be set of the values of CLK_CurrentClockState_TypeDef
Note:
LSI selected as master clock source only if LSI_EN option bit is set.
Return values:
ErrorStatus this shows the clock switch status (ERROR/SUCCESS).

Definition at line 309 of file stm8s_clk.c.

References CLK, CLK_CURRENTCLOCKSTATE_DISABLE, CLK_ECKR_HSEEN, CLK_ICKR_HSIEN, CLK_ICKR_LSIEN, CLK_SOURCE_HSE, CLK_SOURCE_HSI, CLK_SOURCE_LSI, CLK_SWCR_SWBSY, CLK_SWCR_SWEN, CLK_SWCR_SWIEN, CLK_SWCR_SWIF, CLK_SWITCHMODE_AUTO, CLK_TIMEOUT, DISABLE, ERROR, IS_CLK_CURRENTCLOCKSTATE_OK, IS_CLK_SOURCE_OK, IS_CLK_SWITCHMODE_OK, IS_FUNCTIONALSTATE_OK, and SUCCESS.

void CLK_DeInit ( void )

Deinitializes the CLK peripheral registers to their default reset values.

Parameters:
None
Return values:
None
Warning:
Resetting the CCOR register:
When the CCOEN bit is set, the reset of the CCOR register require two consecutive write instructions in order to reset first the CCOEN bit and the second one is to reset the CCOSEL bits.

Definition at line 72 of file stm8s_clk.c.

References CLK, CLK_CCOR_CCOEN, CLK_CCOR_RESET_VALUE, CLK_CKDIVR_RESET_VALUE, CLK_CSSR_RESET_VALUE, CLK_ECKR_RESET_VALUE, CLK_HSITRIMR_RESET_VALUE, CLK_ICKR_RESET_VALUE, CLK_PCKENR1_RESET_VALUE, CLK_PCKENR2_RESET_VALUE, CLK_SWCR_RESET_VALUE, CLK_SWIMCCR_RESET_VALUE, and CLK_SWR_RESET_VALUE.

void CLK_FastHaltWakeUpCmd ( FunctionalState NewState )

Configures the High Speed Internal oscillator (HSI).

Full description:
If CLK_FastHaltWakeup is enabled, HSI oscillator is automatically switched-on (HSIEN=1) and selected as next clock master (CKM=SWI=HSI) when resuming from HALT/ActiveHalt modes.
Parameters:
NewState this parameter is the Wake-up Mode state.
Return values:
None

Definition at line 99 of file stm8s_clk.c.

References CLK, CLK_ICKR_FHWU, DISABLE, and IS_FUNCTIONALSTATE_OK.

uint32_t CLK_GetClockFreq ( void )

This function returns the frequencies of different on chip clocks.

Parameters:
None
Return values:
the master clock frequency

Definition at line 569 of file stm8s_clk.c.

References CLK, CLK_CKDIVR_HSIDIV, CLK_SOURCE_HSI, CLK_SOURCE_LSI, HSE_VALUE, HSI_VALUE, HSIDivFactor, and LSI_VALUE.

Referenced by UART1_Init(), UART2_Init(), UART3_Init(), and UART4_Init().

FlagStatus CLK_GetFlagStatus ( CLK_Flag_TypeDef CLK_FLAG )

Checks whether the specified CLK flag is set or not.

Full description:
Parameters:
CLK_FLAG Flag to check. can be one of the values of CLK_Flag_TypeDef
Return values:
FlagStatus,status of the checked flag

Definition at line 634 of file stm8s_clk.c.

References CLK, IS_CLK_FLAG_OK, RESET, and SET.

ITStatus CLK_GetITStatus ( CLK_IT_TypeDef CLK_IT )

Checks whether the specified CLK interrupt has is enabled or not.

Parameters:
CLK_IT specifies the CLK interrupt. can be one of the values of CLK_IT_TypeDef
Return values:
ITStatus,new state of CLK_IT (SET or RESET).

Definition at line 687 of file stm8s_clk.c.

References CLK, CLK_IT_SWIF, IS_CLK_IT_OK, RESET, and SET.

CLK_Source_TypeDef CLK_GetSYSCLKSource ( void )

Returns the clock source used as system clock.

Parameters:
None
Return values:
Clock source used. can be one of the values of CLK_Source_TypeDef

Definition at line 559 of file stm8s_clk.c.

References CLK.

void CLK_HSECmd ( FunctionalState NewState )

Enable or Disable the External High Speed oscillator (HSE).

Parameters:
NewState new state of HSEEN, value accepted ENABLE, DISABLE.
Return values:
None

Definition at line 121 of file stm8s_clk.c.

References CLK, CLK_ECKR_HSEEN, DISABLE, and IS_FUNCTIONALSTATE_OK.

void CLK_HSICmd ( FunctionalState NewState )

Enables or disables the Internal High Speed oscillator (HSI).

Parameters:
NewState new state of HSIEN, value accepted ENABLE, DISABLE.
Return values:
None

Definition at line 143 of file stm8s_clk.c.

References CLK, CLK_ICKR_HSIEN, DISABLE, and IS_FUNCTIONALSTATE_OK.

void CLK_HSIPrescalerConfig ( CLK_Prescaler_TypeDef HSIPrescaler )

Configures the HSI clock dividers.

Parameters:
HSIPrescaler : Specifies the HSI clock divider to apply. This parameter can be any of the CLK_Prescaler_TypeDef enumeration.
Return values:
None

Definition at line 415 of file stm8s_clk.c.

References CLK, CLK_CKDIVR_HSIDIV, and IS_CLK_HSIPRESCALER_OK.

void CLK_ITConfig | ( | CLK_IT_TypeDef | CLK_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified CLK interrupts.

Parameters:
CLK_IT | This parameter specifies the interrupt sources. It can be one of the values of CLK_IT_TypeDef.
NewState | New state of the Interrupt. Value accepted ENABLE, DISABLE.
Return values:
None

Definition at line 459 of file stm8s_clk.c.

References CLK, CLK_CSSR_CSSDIE, CLK_IT_CSSD, CLK_IT_SWIF, CLK_SWCR_SWIEN, DISABLE, IS_CLK_IT_OK, and IS_FUNCTIONALSTATE_OK.

void CLK_LSICmd ( FunctionalState NewState )

Enables or disables the Internal Low Speed oscillator (LSI).

Parameters:
NewState new state of LSIEN, value accepted ENABLE, DISABLE.
Note:
Before using the LSI clock you have to enable the option bytes (LSI_EN option bit is set).
Return values:
None

Definition at line 166 of file stm8s_clk.c.

References CLK, CLK_ICKR_LSIEN, DISABLE, and IS_FUNCTIONALSTATE_OK.

void CLK_PeripheralClockConfig | ( | CLK_Peripheral_TypeDef | CLK_Peripheral,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified peripheral CLK.

Parameters:
CLK_Peripheral | : This parameter specifies the peripheral clock to gate. This parameter can be any of the CLK_Peripheral_TypeDef enumeration.
NewState | : New state of specified peripheral clock. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 263 of file stm8s_clk.c.

References CLK, DISABLE, IS_CLK_PERIPHERAL_OK, and IS_FUNCTIONALSTATE_OK.

void CLK_SlowActiveHaltWakeUpCmd ( FunctionalState NewState )

Configures the slow active halt wake up.

Parameters:
NewState,: specifies the Slow Active Halt wake up state. can be set of the following values:
  • DISABLE: Slow Active Halt mode disabled;
  • ENABLE: Slow Active Halt mode enabled.
Return values:
None

Definition at line 238 of file stm8s_clk.c.

References CLK, CLK_ICKR_SWUAH, DISABLE, and IS_FUNCTIONALSTATE_OK.

void CLK_SWIMConfig ( CLK_SWIMDivider_TypeDef CLK_SWIMDivider )

Configures the SWIM clock frequency on the fly.

Parameters:
CLK_SWIMDivider Specifies the SWIM clock divider to apply. can be one of the value of CLK_SWIMDivider_TypeDef
Return values:
None

Definition at line 523 of file stm8s_clk.c.

References CLK, CLK_SWIMCCR_SWIMDIV, CLK_SWIMDIVIDER_2, and IS_CLK_SWIMDIVIDER_OK.

void CLK_SYSCLKConfig ( CLK_Prescaler_TypeDef CLK_Prescaler )

Configures the HSI and CPU clock dividers.

Parameters:
CLK_Prescaler Specifies the HSI or CPU clock divider to apply.
Return values:
None

Definition at line 500 of file stm8s_clk.c.

References CLK, CLK_CKDIVR_CPUDIV, CLK_CKDIVR_HSIDIV, and IS_CLK_PRESCALER_OK.

void CLK_SYSCLKEmergencyClear ( void )

Reset the SWBSY flag (SWICR Register)

Full description:
This function reset SWBSY flag in order to reset clock switch operations (target oscillator is broken, stabilization is longing too much, etc.). If at the same time
software attempts to set SWEN and clear SWBSY, SWBSY action takes precedence.
Parameters:
None
Return values:
None

Definition at line 622 of file stm8s_clk.c.

References CLK, and CLK_SWCR_SWBSY.


STM8S/A Standard Peripherals Drivers: EXTI_Public_Functions

Functions
EXTI_Public_Functions
STM8S_StdPeriph_Driver

Functions

void | EXTI_DeInit (void)
Deinitializes the external interrupt control registers to their default reset value.
EXTI_Sensitivity_TypeDef | EXTI_GetExtIntSensitivity (EXTI_Port_TypeDef Port)
Get the external interrupt sensitivity of the selected port.
EXTI_TLISensitivity_TypeDef | EXTI_GetTLISensitivity (void)
Get the TLI interrupt sensitivity.
void | EXTI_SetExtIntSensitivity (EXTI_Port_TypeDef Port, EXTI_Sensitivity_TypeDef SensitivityValue)
Set the external interrupt sensitivity of the selected port.
void | EXTI_SetTLISensitivity (EXTI_TLISensitivity_TypeDef SensitivityValue)
Set the TLI interrupt sensitivity.

Function Documentation

void EXTI_DeInit ( void )

Deinitializes the external interrupt control registers to their default reset value.

Parameters:
None
Return values:
None

Definition at line 53 of file stm8s_exti.c.

References EXTI, EXTI_CR1_RESET_VALUE, and EXTI_CR2_RESET_VALUE.

EXTI_Sensitivity_TypeDef EXTI_GetExtIntSensitivity ( EXTI_Port_TypeDef Port )

Get the external interrupt sensitivity of the selected port.

Parameters:
Port The port number to access.
Return values:
EXTI_Sensitivity_TypeDef The external interrupt sensitivity of the selected port.

Definition at line 126 of file stm8s_exti.c.

References EXTI, EXTI_CR1_PAIS, EXTI_CR1_PBIS, EXTI_CR1_PCIS, EXTI_CR1_PDIS, EXTI_CR2_PEIS, EXTI_PORT_GPIOA, EXTI_PORT_GPIOB, EXTI_PORT_GPIOC, EXTI_PORT_GPIOD, EXTI_PORT_GPIOE, and IS_EXTI_PORT_OK.

EXTI_TLISensitivity_TypeDef EXTI_GetTLISensitivity ( void )

Get the TLI interrupt sensitivity.

Parameters:
None
Return values:
EXTI_TLISensitivity_TypeDef The TLI interrupt sensitivity read.

Definition at line 162 of file stm8s_exti.c.

References EXTI, and EXTI_CR2_TLIS.

void EXTI_SetExtIntSensitivity | ( | EXTI_Port_TypeDef | Port,
 |  | EXTI_Sensitivity_TypeDef | SensitivityValue
 | ) |  |

Set the external interrupt sensitivity of the selected port.

Warning:
  • The modification of external interrupt sensitivity is only possible when the interrupts are disabled.
  • The normal behavior is to disable the interrupts before calling this function, and re-enable them after.
Parameters:
Port | The port number to access.
SensitivityValue | The external interrupt sensitivity value to set.
Return values:
None
Required preconditions:
Global interrupts must be disabled before calling this function.

Definition at line 70 of file stm8s_exti.c.

References EXTI, EXTI_CR1_PAIS, EXTI_CR1_PBIS, EXTI_CR1_PCIS, EXTI_CR1_PDIS, EXTI_CR2_PEIS, EXTI_PORT_GPIOA, EXTI_PORT_GPIOB, EXTI_PORT_GPIOC, EXTI_PORT_GPIOD, EXTI_PORT_GPIOE, IS_EXTI_PORT_OK, and IS_EXTI_SENSITIVITY_OK.

void EXTI_SetTLISensitivity ( EXTI_TLISensitivity_TypeDef SensitivityValue )

Set the TLI interrupt sensitivity.

Parameters:
SensitivityValue The TLI interrupt sensitivity value.
Return values:
None
Required preconditions:
Global interrupts must be disabled before calling this function.

Definition at line 111 of file stm8s_exti.c.

References EXTI, EXTI_CR2_TLIS, and IS_EXTI_TLISENSITIVITY_OK.


STM8S/A Standard Peripherals Drivers: FLASH_Public_functions

Functions
FLASH_Public_functions
STM8S_StdPeriph_Driver

Functions

void | FLASH_DeInit (void)
DeInitializes the FLASH registers to their default reset values.
void | FLASH_EraseByte (uint32_t Address)
Erases one byte in the program or data EEPROM memory.
void | FLASH_EraseOptionByte (uint16_t Address)
Erases option byte.
uint32_t | FLASH_GetBootSize (void)
Returns the Boot memory size in bytes.
FlagStatus | FLASH_GetFlagStatus (FLASH_Flag_TypeDef FLASH_FLAG)
Checks whether the specified SPI flag is set or not.
FLASH_LPMode_TypeDef | FLASH_GetLowPowerMode (void)
Returns the Flash behaviour type in low power mode.
FLASH_ProgramTime_TypeDef | FLASH_GetProgrammingTime (void)
Returns the fixed programming time.
void | FLASH_ITConfig (FunctionalState NewState)
Enables or Disables the Flash interrupt mode.
void | FLASH_Lock (FLASH_MemType_TypeDef FLASH_MemType)
Locks the program or data EEPROM memory.
void | FLASH_ProgramByte (uint32_t Address, uint8_t Data)
Programs one byte in program or data EEPROM memory.
void | FLASH_ProgramOptionByte (uint16_t Address, uint8_t Data)
Programs option byte.
void | FLASH_ProgramWord (uint32_t Address, uint32_t Data)
Programs one word (4 bytes) in program or data EEPROM memory.
uint8_t | FLASH_ReadByte (uint32_t Address)
Reads any byte from flash memory.
uint16_t | FLASH_ReadOptionByte (uint16_t Address)
Reads one option byte.
void | FLASH_SetLowPowerMode (FLASH_LPMode_TypeDef FLASH_LPMode)
Select the Flash behaviour in low power mode.
void | FLASH_SetProgrammingTime (FLASH_ProgramTime_TypeDef FLASH_ProgTime)
Sets the fixed programming time.
void | FLASH_Unlock (FLASH_MemType_TypeDef FLASH_MemType)
Unlocks the program or data EEPROM memory.

Function Documentation

void FLASH_DeInit ( void )

DeInitializes the FLASH registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 126 of file stm8s_flash.c.

References FLASH, FLASH_CR1_RESET_VALUE, FLASH_CR2_RESET_VALUE, FLASH_IAPSR_DUL, FLASH_IAPSR_PUL, and FLASH_NCR2_RESET_VALUE.

void FLASH_EraseByte ( uint32_t Address )

Erases one byte in the program or data EEPROM memory.

Note:
PointerAttr define is declared in the stm8s.h file to select if the pointer will be declared as near (2 bytes) or far (3 bytes).
Parameters:
Address : Address of the byte to erase
Return values:
None

Definition at line 164 of file stm8s_flash.c.

References FLASH_CLEAR_BYTE, IS_FLASH_ADDRESS_OK, MemoryAddressCast, and PointerAttr.

void FLASH_EraseOptionByte ( uint16_t Address )

Erases option byte.

Parameters:
Address : Option byte address to erase
Return values:
None

Definition at line 270 of file stm8s_flash.c.

References FLASH, FLASH_CLEAR_BYTE, FLASH_CR2_OPT, FLASH_MEMTYPE_PROG, FLASH_NCR2_NOPT, FLASH_SET_BYTE, IS_OPTION_BYTE_ADDRESS_OK, and NEAR.

uint32_t FLASH_GetBootSize ( void )

Returns the Boot memory size in bytes.

Parameters:
None
Return values:
Boot memory size in bytes

Definition at line 392 of file stm8s_flash.c.

References FLASH.

FlagStatus FLASH_GetFlagStatus ( FLASH_Flag_TypeDef FLASH_FLAG )

Checks whether the specified SPI flag is set or not.

Parameters:
FLASH_FLAG : Specifies the flag to check. This parameter can be any of the FLASH_Flag_TypeDef enumeration.
Return values:
FlagStatus : Indicates the state of FLASH_FLAG. This parameter can be any of the FlagStatus enumeration.
Note:
This function can clear the EOP, WR_PG_DIS flags in the IAPSR register.

Definition at line 417 of file stm8s_flash.c.

References FLASH, IS_FLASH_FLAGS_OK, RESET, and SET.

FLASH_LPMode_TypeDef FLASH_GetLowPowerMode ( void )

Returns the Flash behaviour type in low power mode.

Parameters:
None
Return values:
FLASH_LPMode_TypeDef Flash behaviour type in low power mode

Definition at line 372 of file stm8s_flash.c.

References FLASH, FLASH_CR1_AHALT, and FLASH_CR1_HALT.

FLASH_ProgramTime_TypeDef FLASH_GetProgrammingTime ( void )

Returns the fixed programming time.

Parameters:
None
Return values:
FLASH_ProgramTime_TypeDef Fixed programming time value

Definition at line 382 of file stm8s_flash.c.

References FLASH, and FLASH_CR1_FIX.

void FLASH_ITConfig ( FunctionalState NewState )

Enables or Disables the Flash interrupt mode.

Parameters:
NewState : The new state of the flash interrupt mode This parameter can be a value of FunctionalState enumeration.
Return values:
None

Definition at line 142 of file stm8s_flash.c.

References DISABLE, FLASH, FLASH_CR1_IE, and IS_FUNCTIONALSTATE_OK.

void FLASH_Lock ( FLASH_MemType_TypeDef FLASH_MemType )

Locks the program or data EEPROM memory.

Parameters:
FLASH_MemType : Memory type This parameter can be a value of FLASH_MemType_TypeDef
Return values:
None

Definition at line 112 of file stm8s_flash.c.

References FLASH, and IS_MEMORY_TYPE_OK.

void FLASH_ProgramByte | ( | uint32_t | Address,
 |  | uint8_t | Data
 | ) |  |

Programs one byte in program or data EEPROM memory.

Note:
PointerAttr define is declared in the stm8s.h file to select if the pointer will be declared as near (2 bytes) or far (3 bytes).
Parameters:
Address | : Address where the byte will be programmed
Data | : Value to be programmed
Return values:
None

Definition at line 181 of file stm8s_flash.c.

References IS_FLASH_ADDRESS_OK, MemoryAddressCast, and PointerAttr.

void FLASH_ProgramOptionByte | ( | uint16_t | Address,
 |  | uint8_t | Data
 | ) |  |

Programs option byte.

Parameters:
Address | : option byte address to program
Data | : Value to write
Return values:
None

Definition at line 237 of file stm8s_flash.c.

References FLASH, FLASH_CR2_OPT, FLASH_MEMTYPE_PROG, FLASH_NCR2_NOPT, IS_OPTION_BYTE_ADDRESS_OK, and NEAR.

void FLASH_ProgramWord | ( | uint32_t | Address,
 |  | uint32_t | Data
 | ) |  |

Programs one word (4 bytes) in program or data EEPROM memory.

Note:
PointerAttr define is declared in the stm8s.h file to select if the pointer will be declared as near (2 bytes) or far (3 bytes).
Parameters:
Address | : The address where the data will be programmed
Data | : Value to be programmed
Return values:
None

Definition at line 212 of file stm8s_flash.c.

References FLASH, FLASH_CR2_WPRG, FLASH_NCR2_NWPRG, IS_FLASH_ADDRESS_OK, MemoryAddressCast, and PointerAttr.

uint8_t FLASH_ReadByte ( uint32_t Address )

Reads any byte from flash memory.

Note:
PointerAttr define is declared in the stm8s.h file to select if the pointer will be declared as near (2 bytes) or far (3 bytes).
Parameters:
Address : Address to read
Return values:
Value of the byte

Definition at line 195 of file stm8s_flash.c.

References IS_FLASH_ADDRESS_OK, MemoryAddressCast, and PointerAttr.

uint16_t FLASH_ReadOptionByte ( uint16_t Address )

Reads one option byte.

Parameters:
Address option byte address to read.
Return values:
Option byte read value + its complement

Definition at line 303 of file stm8s_flash.c.

References FLASH_OPTIONBYTE_ERROR, IS_OPTION_BYTE_ADDRESS_OK, and NEAR.

void FLASH_SetLowPowerMode ( FLASH_LPMode_TypeDef FLASH_LPMode )

Select the Flash behaviour in low power mode.

Parameters:
FLASH_LPMode Low power mode selection This parameter can be any of the FLASH_LPMode_TypeDef values.
Return values:
None

Definition at line 340 of file stm8s_flash.c.

References FLASH, FLASH_CR1_AHALT, FLASH_CR1_HALT, and IS_FLASH_LOW_POWER_MODE_OK.

void FLASH_SetProgrammingTime ( FLASH_ProgramTime_TypeDef FLASH_ProgTime )

Sets the fixed programming time.

Parameters:
FLASH_ProgTime Indicates the programming time to be fixed This parameter can be any of the FLASH_ProgramTime_TypeDef values.
Return values:
None

Definition at line 358 of file stm8s_flash.c.

References FLASH, FLASH_CR1_FIX, and IS_FLASH_PROGRAM_TIME_OK.

void FLASH_Unlock ( FLASH_MemType_TypeDef FLASH_MemType )

Unlocks the program or data EEPROM memory.

Parameters:
FLASH_MemType : Memory type to unlock This parameter can be a value of FLASH_MemType_TypeDef
Return values:
None

Definition at line 87 of file stm8s_flash.c.

References FLASH, FLASH_MEMTYPE_PROG, FLASH_RASS_KEY1, FLASH_RASS_KEY2, and IS_MEMORY_TYPE_OK.


STM8S/A Standard Peripherals Drivers: GPIO_Public_Functions

Functions
GPIO_Public_Functions
STM8S_StdPeriph_Driver

Functions

void | GPIO_DeInit (GPIO_TypeDef *GPIOx)
Deinitializes the GPIOx peripheral registers to their default reset values.
void | GPIO_ExternalPullUpConfig (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef GPIO_Pin, FunctionalState NewState)
Configures the external pull-up on GPIOx pins.
void | GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef GPIO_Pin, GPIO_Mode_TypeDef GPIO_Mode)
Initializes the GPIOx according to the specified parameters.
uint8_t | GPIO_ReadInputData (GPIO_TypeDef *GPIOx)
Reads the specified GPIO input data port.
BitStatus | GPIO_ReadInputPin (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
Reads the specified GPIO input data pin.
uint8_t | GPIO_ReadOutputData (GPIO_TypeDef *GPIOx)
Reads the specified GPIO output data port.
void | GPIO_Write (GPIO_TypeDef *GPIOx, uint8_t PortVal)
Writes data to the specified GPIO data port.
void | GPIO_WriteHigh (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef PortPins)
Writes high level to the specified GPIO pins.
void | GPIO_WriteLow (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef PortPins)
Writes low level to the specified GPIO pins.
void | GPIO_WriteReverse (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef PortPins)
Writes reverse level to the specified GPIO pins.

Function Documentation

void GPIO_DeInit ( GPIO_TypeDef * GPIOx )

Deinitializes the GPIOx peripheral registers to their default reset values.

Parameters:
GPIOx,: Select the GPIO peripheral number (x = A to I).
Return values:
None

Definition at line 53 of file stm8s_gpio.c.

References GPIO_struct::CR1, GPIO_struct::CR2, GPIO_struct::DDR, GPIO_CR1_RESET_VALUE, GPIO_CR2_RESET_VALUE, GPIO_DDR_RESET_VALUE, GPIO_ODR_RESET_VALUE, and GPIO_struct::ODR.

void GPIO_ExternalPullUpConfig | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_Pin_TypeDef | GPIO_Pin,
 |  | FunctionalState | NewState
 | ) |  |

Configures the external pull-up on GPIOx pins.

Parameters:
GPIOx | : Select the GPIO peripheral number (x = A to I).
GPIO_Pin | : Specifies the pin number
NewState | : The new state of the pull up pin.
Return values:
None

Definition at line 225 of file stm8s_gpio.c.

References GPIO_struct::CR1, DISABLE, IS_FUNCTIONALSTATE_OK, and IS_GPIO_PIN_OK.

void GPIO_Init | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_Pin_TypeDef | GPIO_Pin,
 |  | GPIO_Mode_TypeDef | GPIO_Mode
 | ) |  |

Initializes the GPIOx according to the specified parameters.

Parameters:
GPIOx | : Select the GPIO peripheral number (x = A to I).
GPIO_Pin | : This parameter contains the pin number, it can be any value of the GPIO_Pin_TypeDef enumeration.
GPIO_Mode | : This parameter can be a value of the GPIO_Mode_TypeDef enumeration.
Return values:
None

Definition at line 71 of file stm8s_gpio.c.

References GPIO_struct::CR1, GPIO_struct::CR2, GPIO_struct::DDR, IS_GPIO_MODE_OK, IS_GPIO_PIN_OK, and GPIO_struct::ODR.

uint8_t GPIO_ReadInputData ( GPIO_TypeDef * GPIOx )

Reads the specified GPIO input data port.

Note:
The port must be configured in input mode.
Parameters:
GPIOx : Select the GPIO peripheral number (x = A to I).
Return values:
GPIO input data port value.

Definition at line 202 of file stm8s_gpio.c.

References GPIO_struct::IDR.

BitStatus GPIO_ReadInputPin | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_Pin_TypeDef | GPIO_Pin
 | ) |  |

Reads the specified GPIO input data pin.

Parameters:
GPIOx | : Select the GPIO peripheral number (x = A to I).
GPIO_Pin | : Specifies the pin number.
Return values:
BitStatus : GPIO input pin status.

Definition at line 213 of file stm8s_gpio.c.

References GPIO_struct::IDR.

uint8_t GPIO_ReadOutputData ( GPIO_TypeDef * GPIOx )

Reads the specified GPIO output data port.

Note:
The port must be configured in input mode.
Parameters:
GPIOx : Select the GPIO peripheral number (x = A to I).
Return values:
GPIO output data port value.

Definition at line 191 of file stm8s_gpio.c.

References GPIO_struct::ODR.

void GPIO_Write | ( | GPIO_TypeDef * | GPIOx,
 |  | uint8_t | PortVal
 | ) |  |

Writes data to the specified GPIO data port.

Note:
The port must be configured in output mode.
Parameters:
GPIOx | : Select the GPIO peripheral number (x = A to I).
PortVal | : Specifies the value to be written to the port output data register.
Return values:
None

Definition at line 141 of file stm8s_gpio.c.

References GPIO_struct::ODR.

void GPIO_WriteHigh | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_Pin_TypeDef | PortPins
 | ) |  |

Writes high level to the specified GPIO pins.

Note:
The port must be configured in output mode.
Parameters:
GPIOx | : Select the GPIO peripheral number (x = A to I).
PortPins | : Specifies the pins to be turned high to the port output. data register.
Return values:
None

Definition at line 154 of file stm8s_gpio.c.

References GPIO_struct::ODR.

void GPIO_WriteLow | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_Pin_TypeDef | PortPins
 | ) |  |

Writes low level to the specified GPIO pins.

Note:
The port must be configured in output mode.
Parameters:
GPIOx | : Select the GPIO peripheral number (x = A to I).
PortPins | : Specifies the pins to be turned low to the port output. data register.
Return values:
None

Definition at line 167 of file stm8s_gpio.c.

References GPIO_struct::ODR.

void GPIO_WriteReverse | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_Pin_TypeDef | PortPins
 | ) |  |

Writes reverse level to the specified GPIO pins.

Note:
The port must be configured in output mode.
Parameters:
GPIOx | : Select the GPIO peripheral number (x = A to I).
PortPins | : Specifies the pins to be reversed to the port output. data register.
Return values:
None

Definition at line 180 of file stm8s_gpio.c.

References GPIO_struct::ODR.


STM8S/A Standard Peripherals Drivers: I2C_Private_Defines

Defines
I2C_Private_Defines
STM8S_StdPeriph_Driver

Defines

#define | FLAG_Mask ((uint16_t)0x00FF)
#define | ITEN_Mask ((uint16_t)0x0700)
#define | REGISTER_Mask ((uint16_t)0x3000)
#define | REGISTER_SR1_Index ((uint16_t)0x0100)
#define | REGISTER_SR2_Index ((uint16_t)0x0200)

Define Documentation

#define FLAG_Mask ((uint16_t)0x00FF)

Definition at line 46 of file stm8s_i2c.c.

Referenced by I2C_ClearFlag(), and I2C_ClearITPendingBit().

#define ITEN_Mask ((uint16_t)0x0700)

Definition at line 44 of file stm8s_i2c.c.

Referenced by I2C_GetITStatus().

#define REGISTER_Mask ((uint16_t)0x3000)

Definition at line 40 of file stm8s_i2c.c.

Referenced by I2C_GetITStatus().

#define REGISTER_SR1_Index ((uint16_t)0x0100)

Definition at line 41 of file stm8s_i2c.c.

Referenced by I2C_GetITStatus().

#define REGISTER_SR2_Index ((uint16_t)0x0200)

Definition at line 42 of file stm8s_i2c.c.


STM8S/A Standard Peripherals Drivers: I2C_Public_Functions

Functions
I2C_Public_Functions
STM8S_StdPeriph_Driver

Functions

void | I2C_AcknowledgeConfig (I2C_Ack_TypeDef Ack)
Enable or Disable the I2C acknowledge and position acknowledge feature.
ErrorStatus | I2C_CheckEvent (I2C_Event_TypeDef I2C_Event)
I2C State Monitoring Functions.
void | I2C_ClearFlag (I2C_Flag_TypeDef I2C_FLAG)
Clear flags.
void | I2C_ClearITPendingBit (I2C_ITPendingBit_TypeDef I2C_ITPendingBit)
Clear IT pending bit.
void | I2C_Cmd (FunctionalState NewState)
Enables or disables the I2C peripheral.
void | I2C_DeInit (void)
Deinitializes the I2C peripheral registers to their default reset values.
void | I2C_FastModeDutyCycleConfig (I2C_DutyCycle_TypeDef I2C_DutyCycle)
Selects the specified I2C fast mode duty cycle.
void | I2C_GeneralCallCmd (FunctionalState NewState)
Enables or disables the I2C General Call feature.
void | I2C_GenerateSTART (FunctionalState NewState)
Generates I2C communication START condition.
void | I2C_GenerateSTOP (FunctionalState NewState)
Generates I2C communication STOP condition.
FlagStatus | I2C_GetFlagStatus (I2C_Flag_TypeDef I2C_Flag)
3) Flag-based state monitoring
ITStatus | I2C_GetITStatus (I2C_ITPendingBit_TypeDef I2C_ITPendingBit)
Checks whether the specified I2C interrupt has occurred or not.
I2C_Event_TypeDef | I2C_GetLastEvent (void)
2) Advanced state monitoring
void | I2C_Init (uint32_t OutputClockFrequencyHz, uint16_t OwnAddress, I2C_DutyCycle_TypeDef I2C_DutyCycle, I2C_Ack_TypeDef Ack, I2C_AddMode_TypeDef AddMode, uint8_t InputClockFrequencyMHz)
Initializes the I2C according to the specified parameters in standard or fast mode.
void | I2C_ITConfig (I2C_IT_TypeDef I2C_IT, FunctionalState NewState)
Enables or disables the specified I2C interrupt.
uint8_t | I2C_ReceiveData (void)
Returns the most recent received data.
void | I2C_Send7bitAddress (uint8_t Address, I2C_Direction_TypeDef Direction)
Transmits the 7-bit address (to select the) slave device.
void | I2C_SendData (uint8_t Data)
Send a byte by writing in the DR register.
void | I2C_SoftwareResetCmd (FunctionalState NewState)
Enables or disables I2C software reset.
void | I2C_StretchClockCmd (FunctionalState NewState)
Enables or disables the I2C clock stretching.

Function Documentation

void I2C_AcknowledgeConfig ( I2C_Ack_TypeDef Ack )

Enable or Disable the I2C acknowledge and position acknowledge feature.

Note:
This function must be called before data reception start
Parameters:
Ack : Specifies the acknowledge mode to apply. This parameter can be any of the I2C_Ack_TypeDef enumeration.
Return values:
None

Definition at line 345 of file stm8s_i2c.c.

References I2C, I2C_ACK_CURR, I2C_ACK_NONE, I2C_CR2_ACK, I2C_CR2_POS, and IS_I2C_ACK_OK.

Referenced by I2C_Init().

ErrorStatus I2C_CheckEvent ( I2C_Event_TypeDef I2C_Event )

I2C State Monitoring Functions.

This I2C driver provides three different ways for I2C state monitoring depending on the application requirements and constraints:

1) Basic state monitoring: Using I2C_CheckEvent() function: It compares the status registers (SR1, SR2 and SR3) content to a given event (can be the combination of one or more flags). It returns SUCCESS if the current status includes the given flags and returns ERROR if one or more flags are missing in the current status.

  • When to use:
    • This function is suitable for most applications as well as for startup activity since the events are fully described in the product reference manual (RM0016).
    • It is also suitable for users who need to define their own events.
  • Limitations:
    • If an error occurs (ie. error flags are set besides to the monitored flags), the I2C_CheckEvent() function may return SUCCESS despite the communication hold or corrupted real state. In this case, it is advised to use error interrupts to monitor the error events and handle them in the interrupt IRQ handler.
Note:
For error management, it is advised to use the following functions:
  • I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
  • I2C_IRQHandler() which is called when the I2C interrupts occur.
  • I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the I2C_IRQHandler() function in order to determine which error occurred.
  • I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() and/or I2C_GenerateStop() in order to clear the error flag and source and return to correct communication status.

2) Advanced state monitoring: Using the function I2C_GetLastEvent() which returns the image of both SR1 & SR3 status registers in a single word (uint16_t) (Status Register 3 value is shifted left by 8 bits and concatenated to Status Register 1).

  • When to use:
    • This function is suitable for the same applications above but it allows to overcome the limitations of I2C_GetFlagStatus() function (see below). The returned value could be compared to events already defined in the library (stm8s_i2c.h) or to custom values defined by user.
    • This function is suitable when multiple flags are monitored at the same time.
    • At the opposite of I2C_CheckEvent() function, this function allows user to choose when an event is accepted (when all events flags are set and no other flags are set or just when the needed flags are set like I2C_CheckEvent() function).
  • Limitations:
    • User may need to define his own events.
    • Same remark concerning the error management is applicable for this function if user decides to check only regular communication flags (and ignores error flags).

3) Flag-based state monitoring: Using the function I2C_GetFlagStatus() which simply returns the status of one single flag (ie. I2C_FLAG_RXNE ...).

  • When to use:
    • This function could be used for specific applications or in debug phase.
    • It is suitable when only one flag checking is needed (most I2C events are monitored through multiple flags).
  • Limitations:
    • When calling this function, the Status register is accessed. Some flags are cleared when the status register is accessed. So checking the status of one Flag, may clear other ones.
    • Function may need to be called twice or more in order to monitor one single event.

For detailed description of Events, please refer to section I2C_Events in stm8s_i2c.h file.

1) Basic state monitoring Checks whether the last I2C Event is equal to the one passed as parameter.

Parameters:
I2C_Event,: specifies the event to be checked. This parameter can be one of the following values:
  • I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1
  • I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1
  • I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1
  • I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2
  • (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2
  • I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3
  • (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3
  • I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2
  • I2C_EVENT_SLAVE_STOP_DETECTED : EV4
  • I2C_EVENT_MASTER_MODE_SELECT : EV5
  • I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6
  • I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6
  • I2C_EVENT_MASTER_BYTE_RECEIVED : EV7
  • I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8
  • I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2
  • I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9
Note:
: For detailed description of Events, please refer to section I2C_Events in stm8s_i2c.h file.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: Last event is equal to the I2C_EVENT
  • ERROR: Last event is different from the I2C_EVENT

Definition at line 578 of file stm8s_i2c.c.

References __IO, ERROR, I2C, I2C_EVENT_SLAVE_ACK_FAILURE, I2C_SR2_AF, IS_I2C_EVENT_OK, and SUCCESS.

void I2C_ClearFlag ( I2C_Flag_TypeDef I2C_FLAG )

Clear flags.

Parameters:
I2C_FLAG : Specifies the flag to clear This parameter can be any combination of the following values:
  • I2C_FLAG_WAKEUPFROMHALT: Wakeup from Halt
  • I2C_FLAG_OVERRUNUNDERRUN: Overrun/Underrun flag (Slave mode)
  • I2C_FLAG_ACKNOWLEDGEFAILURE: Acknowledge failure flag
  • I2C_FLAG_ARBITRATIONLOSS: Arbitration lost flag (Master mode)
  • I2C_FLAG_BUSERROR: Bus error flag.
Note:
Notes:
  • STOPF (STOP detection) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation to I2C_CR2 register.
  • ADD10 (10-bit header sent) is cleared by software sequence: a read operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the second byte of the address in DR register.
  • BTF (Byte Transfer Finished) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a read/write to I2C_DR register (I2C_SendData()).
  • ADDR (Address sent) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to I2C_SR3 register ((void)(I2C->SR3)).
  • SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR register (I2C_SendData()).
Return values:
None

Definition at line 759 of file stm8s_i2c.c.

References FLAG_Mask, I2C, and IS_I2C_CLEAR_FLAG_OK.

void I2C_ClearITPendingBit ( I2C_ITPendingBit_TypeDef I2C_ITPendingBit )

Clear IT pending bit.

Parameters:
I2C_ITPendingBit : specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:
  • I2C_ITPENDINGBIT_WAKEUPFROMHALT: Wakeup from Halt
  • I2C_ITPENDINGBIT_OVERRUNUNDERRUN: Overrun/Underrun interrupt (Slave mode)
  • I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE: Acknowledge failure interrupt
  • I2C_ITPENDINGBIT_ARBITRATIONLOSS: Arbitration lost interrupt (Master mode)
  • I2C_ITPENDINGBIT_BUSERROR: Bus error interrupt

Notes:

  • STOPF (STOP detection) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to I2C_CR2 register (I2C_AcknowledgeConfig() to configure the I2C peripheral Acknowledge).
  • ADD10 (10-bit header sent) is cleared by software sequence: a read operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second byte of the address in I2C_DR register.
  • BTF (Byte Transfer Finished) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a read/write to I2C_DR register (I2C_SendData()).
  • ADDR (Address sent) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to I2C_SR3 register ((void)(I2C->SR3)).
  • SB (Start Bit) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to I2C_DR register (I2C_SendData()).
    Return values:
    None

Definition at line 871 of file stm8s_i2c.c.

References FLAG_Mask, I2C, and IS_I2C_CLEAR_ITPENDINGBIT_OK.

void I2C_Cmd ( FunctionalState NewState )

Enables or disables the I2C peripheral.

Parameters:
NewState : Indicate the new I2C peripheral state. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 202 of file stm8s_i2c.c.

References DISABLE, I2C, I2C_CR1_PE, and IS_FUNCTIONALSTATE_OK.

void I2C_DeInit ( void )

Deinitializes the I2C peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 67 of file stm8s_i2c.c.

References I2C, I2C_CCRH_RESET_VALUE, I2C_CCRL_RESET_VALUE, I2C_CR1_RESET_VALUE, I2C_CR2_RESET_VALUE, I2C_FREQR_RESET_VALUE, I2C_ITR_RESET_VALUE, I2C_OARH_RESET_VALUE, I2C_OARL_RESET_VALUE, and I2C_TRISER_RESET_VALUE.

void I2C_FastModeDutyCycleConfig ( I2C_DutyCycle_TypeDef I2C_DutyCycle )

Selects the specified I2C fast mode duty cycle.

Parameters:
I2C_DutyCycle : Specifies the duty cycle to apply. This parameter can be any of the I2C_DutyCycle_TypeDef enumeration.
Return values:
None

Definition at line 405 of file stm8s_i2c.c.

References I2C, I2C_CCRH_DUTY, I2C_DUTYCYCLE_16_9, and IS_I2C_DUTYCYCLE_OK.

void I2C_GeneralCallCmd ( FunctionalState NewState )

Enables or disables the I2C General Call feature.

Parameters:
NewState : State of the General Call feature. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 225 of file stm8s_i2c.c.

References DISABLE, I2C, I2C_CR1_ENGC, and IS_FUNCTIONALSTATE_OK.

void I2C_GenerateSTART ( FunctionalState NewState )

Generates I2C communication START condition.

Note:
CCR must be programmed, i.e. I2C_Init function must have been called with a valid I2C_ClockSpeed
Parameters:
NewState : Enable or disable the start condition. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 250 of file stm8s_i2c.c.

References DISABLE, I2C, I2C_CR2_START, and IS_FUNCTIONALSTATE_OK.

void I2C_GenerateSTOP ( FunctionalState NewState )

Generates I2C communication STOP condition.

Parameters:
NewState : Enable or disable the stop condition. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 273 of file stm8s_i2c.c.

References DISABLE, I2C, I2C_CR2_STOP, and IS_FUNCTIONALSTATE_OK.

FlagStatus I2C_GetFlagStatus ( I2C_Flag_TypeDef I2C_Flag )

3) Flag-based state monitoring

Checks whether the specified I2C flag is set or not.

Parameters:
I2C_Flag,: specifies the flag to check. This parameter can be one of the following values:
  • I2C_FLAG_GENERALCALL: General call header flag (Slave mode)
  • I2C_FLAG_TRANSMITTERRECEIVER: Transmitter/Receiver flag
  • I2C_FLAG_BUSBUSY: Bus busy flag
  • I2C_FLAG_MASTERSLAVE: Master/Slave flag
  • I2C_FLAG_WAKEUPFROMHALT: Wake up from HALT flag
  • I2C_FLAG_OVERRUNUNDERRUN: Overrun/Underrun flag (Slave mode)
  • I2C_FLAG_ACKNOWLEDGEFAILURE: Acknowledge failure flag
  • I2C_FLAG_ARBITRATIONLOSS: Arbitration lost flag (Master mode)
  • I2C_FLAG_BUSERROR: Bus error flag
  • I2C_FLAG_TXEMPTY: Data register empty flag (Transmitter)
  • I2C_FLAG_RXNOTEMPTY: Data register not empty (Receiver) flag
  • I2C_FLAG_STOPDETECTION: Stop detection flag (Slave mode)
  • I2C_FLAG_HEADERSENT: 10-bit header sent flag (Master mode)
  • I2C_FLAG_TRANSFERFINISHED: Byte transfer finished flag
  • I2C_FLAG_ADDRESSSENTMATCHED: Address sent flag (Master mode) “ADSL” Address matched flag (Slave mode)”ENDAD”
  • I2C_FLAG_STARTDETECTION: Start bit flag (Master mode)
Return values:
The new state of I2C_FLAG (SET or RESET).

Definition at line 679 of file stm8s_i2c.c.

References I2C, IS_I2C_FLAG_OK, RESET, and SET.

ITStatus I2C_GetITStatus ( I2C_ITPendingBit_TypeDef I2C_ITPendingBit )

Checks whether the specified I2C interrupt has occurred or not.

Parameters:
I2C_ITPendingBit,: specifies the interrupt source to check. This parameter can be one of the following values:
  • I2C_ITPENDINGBIT_WAKEUPFROMHALT: Wakeup from Halt
  • I2C_ITPENDINGBIT_OVERRUNUNDERRUN: Overrun/Underrun flag (Slave mode)
  • I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE: Acknowledge failure flag
  • I2C_ITPENDINGBIT_ARBITRATIONLOSS: Arbitration lost flag (Master mode)
  • I2C_ITPENDINGBIT_BUSERROR: Bus error flag
  • I2C_ITPENDINGBIT_TXEMPTY: Data register empty flag (Transmitter)
  • I2C_ITPENDINGBIT_RXNOTEMPTY: Data register not empty (Receiver) flag
  • I2C_ITPENDINGBIT_STOPDETECTION: Stop detection flag (Slave mode)
  • I2C_ITPENDINGBIT_HEADERSENT: 10-bit header sent flag (Master mode)
  • I2C_ITPENDINGBIT_TRANSFERFINISHED: Byte transfer finished flag
  • I2C_ITPENDINGBIT_ADDRESSSENTMATCHED: Address sent flag (Master mode) “ADSL” Address matched flag (Slave mode)“ENDAD”
  • I2C_ITPENDINGBIT_STARTDETECTION: Start bit flag (Master mode)
Return values:
The new state of I2C_ITPendingBit This parameter can be any of the ITStatus enumeration.

Definition at line 791 of file stm8s_i2c.c.

References __IO, I2C, IS_I2C_ITPENDINGBIT_OK, ITEN_Mask, REGISTER_Mask, REGISTER_SR1_Index, RESET, and SET.

I2C_Event_TypeDef I2C_GetLastEvent ( void )

2) Advanced state monitoring

Returns the last I2C Event.

Note:
: For detailed description of Events, please refer to section I2C_Events in stm8s_i2c.h file.
Return values:
The last event This parameter can be any of the I2C_Event_TypeDef enumeration.

Definition at line 628 of file stm8s_i2c.c.

References __IO, I2C, I2C_EVENT_SLAVE_ACK_FAILURE, and I2C_SR2_AF.

void I2C_Init | ( | uint32_t | OutputClockFrequencyHz,
 |  | uint16_t | OwnAddress,
 |  | I2C_DutyCycle_TypeDef | I2C_DutyCycle,
 |  | I2C_Ack_TypeDef | Ack,
 |  | I2C_AddMode_TypeDef | AddMode,
 |  | uint8_t | InputClockFrequencyMHz
 | ) |  |

Initializes the I2C according to the specified parameters in standard or fast mode.

Parameters:
OutputClockFrequencyHz | : Specifies the output clock frequency in Hz.
OwnAddress | : Specifies the own address.
I2C_DutyCycle | : Specifies the duty cycle to apply in fast mode. This parameter can be any of the I2C_DutyCycle_TypeDef enumeration.
Note:
This parameter don't have impact when the OutputClockFrequency lower than 100KHz.
Parameters:
Ack | : Specifies the acknowledge mode to apply. This parameter can be any of the I2C_Ack_TypeDef enumeration.
AddMode | : Specifies the acknowledge address to apply. This parameter can be any of the I2C_AddMode_TypeDef enumeration.
InputClockFrequencyMHz | : Specifies the input clock frequency in MHz.
Return values:
None

Definition at line 96 of file stm8s_i2c.c.

References I2C, I2C_AcknowledgeConfig(), I2C_CCRH_CCR, I2C_CCRH_DUTY, I2C_CCRH_FS, I2C_CCRL_CCR, I2C_CR1_PE, I2C_DUTYCYCLE_2, I2C_FREQR_FREQ, I2C_MAX_STANDARD_FREQ, I2C_OARH_ADDCONF, IS_I2C_ACK_OK, IS_I2C_ADDMODE_OK, IS_I2C_DUTYCYCLE_OK, IS_I2C_INPUT_CLOCK_FREQ_OK, IS_I2C_OUTPUT_CLOCK_FREQ_OK, and IS_I2C_OWN_ADDRESS_OK.

void I2C_ITConfig | ( | I2C_IT_TypeDef | I2C_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C interrupt.

Parameters:
I2C_IT | : Name of the interrupt to enable or disable. This parameter can be any of the I2C_IT_TypeDef enumeration.
NewState | : State of the interrupt to apply. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 381 of file stm8s_i2c.c.

References DISABLE, I2C, IS_FUNCTIONALSTATE_OK, and IS_I2C_INTERRUPT_OK.

uint8_t I2C_ReceiveData ( void )

Returns the most recent received data.

Parameters:
None
Return values:
uint8_t : The value of the received byte data.

Definition at line 427 of file stm8s_i2c.c.

References I2C.

void I2C_Send7bitAddress | ( | uint8_t | Address,
 |  | I2C_Direction_TypeDef | Direction
 | ) |  |

Transmits the 7-bit address (to select the) slave device.

Parameters:
Address | : Specifies the slave address which will be transmitted.
Direction | : Specifies whether the I2C device will be a Transmitter or a Receiver. This parameter can be any of the I2C_Direction_TypeDef enumeration.
Return values:
None

Definition at line 440 of file stm8s_i2c.c.

References I2C, IS_I2C_ADDRESS_OK, and IS_I2C_DIRECTION_OK.

void I2C_SendData ( uint8_t Data )

Send a byte by writing in the DR register.

Parameters:
Data : Byte to be sent.
Return values:
None

Definition at line 458 of file stm8s_i2c.c.

References I2C.

void I2C_SoftwareResetCmd ( FunctionalState NewState )

Enables or disables I2C software reset.

Parameters:
NewState : Specifies the new state of the I2C software reset. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 296 of file stm8s_i2c.c.

References DISABLE, I2C, I2C_CR2_SWRST, and IS_FUNCTIONALSTATE_OK.

void I2C_StretchClockCmd ( FunctionalState NewState )

Enables or disables the I2C clock stretching.

Parameters:
NewState : Specifies the new state of the I2C Clock stretching. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 320 of file stm8s_i2c.c.

References DISABLE, I2C, I2C_CR1_NOSTRETCH, and IS_FUNCTIONALSTATE_OK.


STM8S/A Standard Peripherals Drivers: ITC_Private_Functions

Functions
ITC_Private_Functions
STM8S_StdPeriph_Driver

Functions

uint8_t ITC_GetCPUCC (void)
Utility function used to read CC register.

Function Documentation

uint8_t ITC_GetCPUCC ( void )

Utility function used to read CC register.

Parameters:
None
Return values:
CPU CC register value

Definition at line 50 of file stm8s_itc.c.

Referenced by ITC_GetSoftIntStatus().


STM8S/A Standard Peripherals Drivers: ITC_Public_Functions

Functions
ITC_Public_Functions
STM8S_StdPeriph_Driver

Functions

void | ITC_DeInit (void)
Deinitializes the ITC registers to their default reset value.
uint8_t | ITC_GetSoftIntStatus (void)
Gets the interrupt software priority bits (I1, I0) value from CPU CC register.
ITC_PriorityLevel_TypeDef | ITC_GetSoftwarePriority (ITC_Irq_TypeDef IrqNum)
Gets the software priority of the specified interrupt source.
void | ITC_SetSoftwarePriority (ITC_Irq_TypeDef IrqNum, ITC_PriorityLevel_TypeDef PriorityValue)
Sets the software priority of the specified interrupt source.

Function Documentation

void ITC_DeInit ( void )

Deinitializes the ITC registers to their default reset value.

Parameters:
None
Return values:
None

Definition at line 80 of file stm8s_itc.c.

References ITC, and ITC_SPRX_RESET_VALUE.

uint8_t ITC_GetSoftIntStatus ( void )

Gets the interrupt software priority bits (I1, I0) value from CPU CC register.

Parameters:
None
Return values:
The interrupt software priority bits value.

Definition at line 97 of file stm8s_itc.c.

References CPU_CC_I1I0, and ITC_GetCPUCC().

ITC_PriorityLevel_TypeDef ITC_GetSoftwarePriority ( ITC_Irq_TypeDef IrqNum )

Gets the software priority of the specified interrupt source.

Parameters:
IrqNum : Specifies the peripheral interrupt source.
Return values:
ITC_PriorityLevel_TypeDef : Specifies the software priority of the interrupt source.

Definition at line 107 of file stm8s_itc.c.

References IS_ITC_IRQ_OK, ITC, ITC_IRQ_AWU, ITC_IRQ_CLK, ITC_IRQ_EEPROM_EEC, ITC_IRQ_I2C, ITC_IRQ_PORTA, ITC_IRQ_PORTB, ITC_IRQ_PORTC, ITC_IRQ_PORTD, ITC_IRQ_PORTE, ITC_IRQ_SPI, ITC_IRQ_TIM1_CAPCOM, ITC_IRQ_TIM1_OVF, ITC_IRQ_TIM2_CAPCOM, ITC_IRQ_TIM2_OVF, ITC_IRQ_TIM3_CAPCOM, ITC_IRQ_TIM3_OVF, ITC_IRQ_TIM4_OVF, and ITC_IRQ_TLI.

void ITC_SetSoftwarePriority | ( | ITC_Irq_TypeDef | IrqNum,
 |  | ITC_PriorityLevel_TypeDef | PriorityValue
 | ) |  |

Sets the software priority of the specified interrupt source.

Note:
- The modification of the software priority is only possible when the interrupts are disabled.
  • The normal behavior is to disable the interrupt before calling this function, and re-enable it after.
  • The priority level 0 cannot be set (see product specification for more details).
Parameters:
IrqNum | : Specifies the peripheral interrupt source.
PriorityValue | : Specifies the software priority value to set, can be a value of ITC_PriorityLevel_TypeDef .
Return values:
None

Definition at line 220 of file stm8s_itc.c.

References IS_ITC_INTERRUPTS_DISABLED, IS_ITC_IRQ_OK, IS_ITC_PRIORITY_OK, ITC, ITC_IRQ_AWU, ITC_IRQ_CLK, ITC_IRQ_EEPROM_EEC, ITC_IRQ_I2C, ITC_IRQ_PORTA, ITC_IRQ_PORTB, ITC_IRQ_PORTC, ITC_IRQ_PORTD, ITC_IRQ_PORTE, ITC_IRQ_SPI, ITC_IRQ_TIM1_CAPCOM, ITC_IRQ_TIM1_OVF, ITC_IRQ_TIM2_CAPCOM, ITC_IRQ_TIM2_OVF, ITC_IRQ_TIM3_CAPCOM, ITC_IRQ_TIM3_OVF, ITC_IRQ_TIM4_OVF, and ITC_IRQ_TLI.


STM8S/A Standard Peripherals Drivers: RST_Public_Functions

Functions
RST_Public_Functions
STM8S_StdPeriph_Driver

Functions

void | RST_ClearFlag (RST_Flag_TypeDef RST_Flag)
Clears the specified RST flag.
FlagStatus | RST_GetFlagStatus (RST_Flag_TypeDef RST_Flag)
Checks whether the specified RST flag is set or not.

Function Documentation

void RST_ClearFlag ( RST_Flag_TypeDef RST_Flag )

Clears the specified RST flag.

Parameters:
RST_Flag : specify the reset flag to clear. This parameter can be a value of RST_Flag_TypeDef.
Return values:
None

Definition at line 69 of file stm8s_rst.c.

References IS_RST_FLAG_OK, and RST.

FlagStatus RST_GetFlagStatus ( RST_Flag_TypeDef RST_Flag )

Checks whether the specified RST flag is set or not.

Parameters:
RST_Flag : specify the reset flag to check. This parameter can be a value of RST_Flag_TypeDef.
Return values:
FlagStatus,: status of the given RST flag.

Definition at line 54 of file stm8s_rst.c.

References IS_RST_FLAG_OK, RESET, RST, and SET.


STM8S/A Standard Peripherals Drivers: SPI_Public_Functions

Functions
SPI_Public_Functions
STM8S_StdPeriph_Driver

Functions

void | SPI_BiDirectionalLineConfig (SPI_Direction_TypeDef SPI_Direction)
Selects the data transfer direction in bi-directional mode.
void | SPI_CalculateCRCCmd (FunctionalState NewState)
Enables or disables the CRC value calculation of the transferred bytes.
void | SPI_ClearFlag (SPI_Flag_TypeDef SPI_FLAG)
Clears the SPI flags.
void | SPI_ClearITPendingBit (SPI_IT_TypeDef SPI_IT)
Clears the interrupt pending bits.
void | SPI_Cmd (FunctionalState NewState)
Enables or disables the SPI peripheral.
void | SPI_DeInit (void)
Deinitializes the SPI peripheral registers to their default reset values.
uint8_t | SPI_GetCRC (SPI_CRC_TypeDef SPI_CRC)
Returns the transmit or the receive CRC register value.
uint8_t | SPI_GetCRCPolynomial (void)
Returns the CRC Polynomial register value.
FlagStatus | SPI_GetFlagStatus (SPI_Flag_TypeDef SPI_FLAG)
Checks whether the specified SPI flag is set or not.
ITStatus | SPI_GetITStatus (SPI_IT_TypeDef SPI_IT)
Checks whether the specified interrupt has occurred or not.
void | SPI_Init (SPI_FirstBit_TypeDef FirstBit, SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, SPI_Mode_TypeDef Mode, SPI_ClockPolarity_TypeDef ClockPolarity, SPI_ClockPhase_TypeDef ClockPhase, SPI_DataDirection_TypeDef Data_Direction, SPI_NSS_TypeDef Slave_Management, uint8_t CRCPolynomial)
Initializes the SPI according to the specified parameters.
void | SPI_ITConfig (SPI_IT_TypeDef SPI_IT, FunctionalState NewState)
Enables or disables the specified interrupts.
void | SPI_NSSInternalSoftwareCmd (FunctionalState NewState)
Configures internally by software the NSS pin.
uint8_t | SPI_ReceiveData (void)
Returns the most recent received data by the SPI peripheral.
void | SPI_ResetCRC (void)
Reset the Rx CRCR and Tx CRCR registers.
void | SPI_SendData (uint8_t Data)
Transmits a Data through the SPI peripheral.
void | SPI_TransmitCRC (void)
Enables the transmit of the CRC value.

Function Documentation

void SPI_BiDirectionalLineConfig ( SPI_Direction_TypeDef SPI_Direction )

Selects the data transfer direction in bi-directional mode.

Parameters:
SPI_Direction Specifies the data transfer direction in bi-directional mode.
Return values:
None

Definition at line 288 of file stm8s_spi.c.

References IS_SPI_DIRECTION_OK, SPI, SPI_CR2_BDOE, and SPI_DIRECTION_RX.

void SPI_CalculateCRCCmd ( FunctionalState NewState )

Enables or disables the CRC value calculation of the transferred bytes.

Parameters:
NewState Indicates the new state of the SPI CRC value calculation. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 218 of file stm8s_spi.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, SPI, and SPI_CR2_CRCEN.

Referenced by SPI_ResetCRC().

void SPI_ClearFlag ( SPI_Flag_TypeDef SPI_FLAG )

Clears the SPI flags.

Parameters:
SPI_FLAG : Specifies the flag to clear. This parameter can be one of the following values:
  • SPI_FLAG_CRCERR
  • SPI_FLAG_WKUP
Note:
- OVR (OverRun Error) interrupt pending bit is cleared by software sequence: a read operation to SPI_DR register (SPI_ReceiveData()) followed by a read operation to SPI_SR register (SPI_GetFlagStatus()).
  • MODF (Mode Fault) interrupt pending bit is cleared by software sequence: a read/write operation to SPI_SR register (SPI_GetFlagStatus()) followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
Return values:
None

Definition at line 346 of file stm8s_spi.c.

References IS_SPI_CLEAR_FLAGS_OK, and SPI.

void SPI_ClearITPendingBit ( SPI_IT_TypeDef SPI_IT )

Clears the interrupt pending bits.

Parameters:
SPI_IT,: Specifies the interrupt pending bit to clear. This parameter can be one of the following values:
  • SPI_IT_CRCERR
  • SPI_IT_WKUP
Note:
- OVR (OverRun Error) interrupt pending bit is cleared by software sequence: a read operation to SPI_DR register (SPI_ReceiveData()) followed by a read operation to SPI_SR register (SPI_GetITStatus()).
  • MODF (Mode Fault) interrupt pending bit is cleared by software sequence: a read/write operation to SPI_SR register (SPI_GetITStatus()) followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
Return values:
None

Definition at line 412 of file stm8s_spi.c.

References IS_SPI_CLEAR_IT_OK, and SPI.

void SPI_Cmd ( FunctionalState NewState )

Enables or disables the SPI peripheral.

Parameters:
NewState New state of the SPI peripheral. This parameter can be: ENABLE or DISABLE
Return values:
None

Definition at line 119 of file stm8s_spi.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, SPI, and SPI_CR1_SPE.

Referenced by SPI_ResetCRC().

void SPI_DeInit ( void )

Deinitializes the SPI peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 50 of file stm8s_spi.c.

References SPI, SPI_CR1_RESET_VALUE, SPI_CR2_RESET_VALUE, SPI_CRCPR_RESET_VALUE, SPI_ICR_RESET_VALUE, and SPI_SR_RESET_VALUE.

uint8_t SPI_GetCRC ( SPI_CRC_TypeDef SPI_CRC )

Returns the transmit or the receive CRC register value.

Parameters:
SPI_CRC Specifies the CRC register to be read.
Return values:
The selected CRC register value.

Definition at line 238 of file stm8s_spi.c.

References IS_SPI_CRC_OK, SPI, and SPI_CRC_RX.

uint8_t SPI_GetCRCPolynomial ( void )

Returns the CRC Polynomial register value.

Parameters:
None
Return values:
The CRC Polynomial register value.

Definition at line 278 of file stm8s_spi.c.

References SPI.

FlagStatus SPI_GetFlagStatus ( SPI_Flag_TypeDef SPI_FLAG )

Checks whether the specified SPI flag is set or not.

Parameters:
SPI_FLAG : Specifies the flag to check. This parameter can be any of the SPI_Flag_TypeDef enumeration.
Return values:
FlagStatus : Indicates the state of SPI_FLAG. This parameter can be any of the FlagStatus enumeration.

Definition at line 311 of file stm8s_spi.c.

References IS_SPI_FLAGS_OK, RESET, SET, and SPI.

ITStatus SPI_GetITStatus ( SPI_IT_TypeDef SPI_IT )

Checks whether the specified interrupt has occurred or not.

Parameters:
SPI_IT,: Specifies the SPI interrupt pending bit to check. This parameter can be one of the following values:
  • SPI_IT_CRCERR
  • SPI_IT_WKUP
  • SPI_IT_OVR
  • SPI_IT_MODF
  • SPI_IT_RXNE
  • SPI_IT_TXE
Return values:
ITStatus : Indicates the state of the SPI_IT. This parameter can be any of the ITStatus enumeration.

Definition at line 366 of file stm8s_spi.c.

References IS_SPI_GET_IT_OK, RESET, SET, and SPI.

void SPI_Init | ( | SPI_FirstBit_TypeDef | FirstBit,
 |  | SPI_BaudRatePrescaler_TypeDef | BaudRatePrescaler,
 |  | SPI_Mode_TypeDef | Mode,
 |  | SPI_ClockPolarity_TypeDef | ClockPolarity,
 |  | SPI_ClockPhase_TypeDef | ClockPhase,
 |  | SPI_DataDirection_TypeDef | Data_Direction,
 |  | SPI_NSS_TypeDef | Slave_Management,
 |  | uint8_t | CRCPolynomial
 | ) |  |

Initializes the SPI according to the specified parameters.

Parameters:
FirstBit | : This parameter can be any of the SPI_FirstBit_TypeDef enumeration.
BaudRatePrescaler | : This parameter can be any of the SPI_BaudRatePrescaler_TypeDef enumeration.
Mode | : This parameter can be any of the SPI_Mode_TypeDef enumeration.
ClockPolarity | : This parameter can be any of the SPI_ClockPolarity_TypeDef enumeration.
ClockPhase | : This parameter can be any of the SPI_ClockPhase_TypeDef enumeration.
Data_Direction | : This parameter can be any of the SPI_DataDirection_TypeDef enumeration.
Slave_Management | : This parameter can be any of the SPI_NSS_TypeDef enumeration.
CRCPolynomial | : Configures the CRC polynomial.
Return values:
None

Definition at line 78 of file stm8s_spi.c.

References IS_SPI_BAUDRATE_PRESCALER_OK, IS_SPI_CRC_POLYNOMIAL_OK, IS_SPI_DATA_DIRECTION_OK, IS_SPI_FIRSTBIT_OK, IS_SPI_MODE_OK, IS_SPI_PHASE_OK, IS_SPI_POLARITY_OK, IS_SPI_SLAVEMANAGEMENT_OK, SPI, SPI_CR2_SSI, and SPI_MODE_MASTER.

void SPI_ITConfig | ( | SPI_IT_TypeDef | SPI_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified interrupts.

Parameters:
SPI_IT Specifies the SPI interrupts sources to be enabled or disabled.
NewState,: The new state of the specified SPI interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 141 of file stm8s_spi.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, IS_SPI_CONFIG_IT_OK, and SPI.

void SPI_NSSInternalSoftwareCmd ( FunctionalState NewState )

Configures internally by software the NSS pin.

Parameters:
NewState Indicates the new state of the SPI Software slave management. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 187 of file stm8s_spi.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, SPI, and SPI_CR2_SSI.

uint8_t SPI_ReceiveData ( void )

Returns the most recent received data by the SPI peripheral.

Parameters:
None
Return values:
The value of the received data.

Definition at line 176 of file stm8s_spi.c.

References SPI.

void SPI_ResetCRC ( void )

Reset the Rx CRCR and Tx CRCR registers.

Parameters:
None
Return values:
None

Definition at line 263 of file stm8s_spi.c.

References ENABLE, SPI_CalculateCRCCmd(), and SPI_Cmd().

void SPI_SendData ( uint8_t Data )

Transmits a Data through the SPI peripheral.

Parameters:
Data : Byte to be transmitted.
Return values:
None

Definition at line 166 of file stm8s_spi.c.

References SPI.

void SPI_TransmitCRC ( void )

Enables the transmit of the CRC value.

Parameters:
None
Return values:
None

Definition at line 207 of file stm8s_spi.c.

References SPI, and SPI_CR2_CRCNEXT.


STM8S/A Standard Peripherals Drivers: TIM1_Public_Functions

Functions
TIM1_Public_Functions
STM8S_StdPeriph_Driver

Functions

static void | TI1_Config (uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
Configure the TI1 as Input.
static void | TI2_Config (uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
Configure the TI2 as Input.
static void | TI3_Config (uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
Configure the TI3 as Input.
static void | TI4_Config (uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
Configure the TI4 as Input.
void | TIM1_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM1 peripheral Preload register on ARR.
void | TIM1_BDTRConfig (TIM1_OSSIState_TypeDef TIM1_OSSIState, TIM1_LockLevel_TypeDef TIM1_LockLevel, uint8_t TIM1_DeadTime, TIM1_BreakState_TypeDef TIM1_Break, TIM1_BreakPolarity_TypeDef TIM1_BreakPolarity, TIM1_AutomaticOutput_TypeDef TIM1_AutomaticOutput)
Configures the Break feature, dead time, Lock level, the OSSI, and the AOE(automatic output enable).
void | TIM1_CCPreloadControl (FunctionalState NewState)
Sets or Resets the TIM1 peripheral Capture Compare Preload Control bit.
void | TIM1_CCxCmd (TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState)
Enables or disables the TIM1 Capture Compare Channel x (x=1,..,4).
void | TIM1_CCxNCmd (TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState)
Enables or disables the TIM1 Capture Compare Channel xN (xN=1,..,3).
void | TIM1_ClearFlag (TIM1_FLAG_TypeDef TIM1_FLAG)
Clears the TIM1’s pending flags.
void | TIM1_ClearITPendingBit (TIM1_IT_TypeDef TIM1_IT)
Clears the TIM1's interrupt pending bits.
void | TIM1_Cmd (FunctionalState NewState)
Enables or disables the TIM1 peripheral.
void | TIM1_CounterModeConfig (TIM1_CounterMode_TypeDef TIM1_CounterMode)
Specifies the TIM1 Counter Mode to be used.
void | TIM1_CtrlPWMOutputs (FunctionalState NewState)
Enables or disables the TIM1 peripheral Main Outputs.
void | TIM1_DeInit (void)
Deinitializes the TIM1 peripheral registers to their default reset values.
void | TIM1_EncoderInterfaceConfig (TIM1_EncoderMode_TypeDef TIM1_EncoderMode, TIM1_ICPolarity_TypeDef TIM1_IC1Polarity, TIM1_ICPolarity_TypeDef TIM1_IC2Polarity)
Configures the TIM1 Encoder Interface.
void | TIM1_ETRClockMode1Config (TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, uint8_t ExtTRGFilter)
Configures the TIM1 External clock Mode1.
void | TIM1_ETRClockMode2Config (TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, uint8_t ExtTRGFilter)
Configures the TIM1 External clock Mode2.
void | TIM1_ETRConfig (TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, uint8_t ExtTRGFilter)
Configures the TIM1 External Trigger.
void | TIM1_ForcedOC1Config (TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
Forces the TIM1 Channel1 output waveform to active or inactive level.
void | TIM1_ForcedOC2Config (TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
Forces the TIM1 Channel2 output waveform to active or inactive level.
void | TIM1_ForcedOC3Config (TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
Forces the TIM1 Channel3 output waveform to active or inactive level.
void | TIM1_ForcedOC4Config (TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
Forces the TIM1 Channel4 output waveform to active or inactive level.
void | TIM1_GenerateEvent (TIM1_EventSource_TypeDef TIM1_EventSource)
Configures the TIM1 event to be generated by software.
uint16_t | TIM1_GetCapture1 (void)
Gets the TIM1 Input Capture 1 value.
uint16_t | TIM1_GetCapture2 (void)
Gets the TIM1 Input Capture 2 value.
uint16_t | TIM1_GetCapture3 (void)
Gets the TIM1 Input Capture 3 value.
uint16_t | TIM1_GetCapture4 (void)
Gets the TIM1 Input Capture 4 value.
uint16_t | TIM1_GetCounter (void)
Gets the TIM1 Counter value.
FlagStatus | TIM1_GetFlagStatus (TIM1_FLAG_TypeDef TIM1_FLAG)
Checks whether the specified TIM1 flag is set or not.
ITStatus | TIM1_GetITStatus (TIM1_IT_TypeDef TIM1_IT)
Checks whether the TIM1 interrupt has occurred or not.
uint16_t | TIM1_GetPrescaler (void)
Gets the TIM1 Prescaler value.
void | TIM1_ICInit (TIM1_Channel_TypeDef TIM1_Channel, TIM1_ICPolarity_TypeDef TIM1_ICPolarity, TIM1_ICSelection_TypeDef TIM1_ICSelection, TIM1_ICPSC_TypeDef TIM1_ICPrescaler, uint8_t TIM1_ICFilter)
Initializes the TIM1 peripheral according to the specified parameters.
void | TIM1_InternalClockConfig (void)
Configures the TIM1 internal Clock.
void | TIM1_ITConfig (TIM1_IT_TypeDef TIM1_IT, FunctionalState NewState)
Enables or disables the specified TIM1 interrupts.
void | TIM1_OC1FastConfig (FunctionalState NewState)
Configures the TIM1 Capture Compare 1 Fast feature.
void | TIM1_OC1Init (TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, TIM1_OutputNState_TypeDef TIM1_OutputNState, uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState, TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
Initializes the TIM1 Channel1 according to the specified parameters.
void | TIM1_OC1NPolarityConfig (TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
Configures the TIM1 Channel 1N polarity.
void | TIM1_OC1PolarityConfig (TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
Configures the TIM1 Channel 1 polarity.
void | TIM1_OC1PreloadConfig (FunctionalState NewState)
Enables or disables the TIM1 peripheral Preload Register on CCR1.
void | TIM1_OC2FastConfig (FunctionalState NewState)
Configures the TIM1 Capture Compare 2 Fast feature.
void | TIM1_OC2Init (TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, TIM1_OutputNState_TypeDef TIM1_OutputNState, uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState, TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
Initializes the TIM1 Channel2 according to the specified parameters.
void | TIM1_OC2NPolarityConfig (TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
Configures the TIM1 Channel 2N polarity.
void | TIM1_OC2PolarityConfig (TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
Configures the TIM1 Channel 2 polarity.
void | TIM1_OC2PreloadConfig (FunctionalState NewState)
Enables or disables the TIM1 peripheral Preload Register on CCR2.
void | TIM1_OC3FastConfig (FunctionalState NewState)
Configures the TIM1 Capture Compare 3 Fast feature.
void | TIM1_OC3Init (TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, TIM1_OutputNState_TypeDef TIM1_OutputNState, uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState, TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
Initializes the TIM1 Channel3 according to the specified parameters.
void | TIM1_OC3NPolarityConfig (TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
Configures the TIM1 Channel 3N polarity.
void | TIM1_OC3PolarityConfig (TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
Configures the TIM1 Channel 3 polarity.
void | TIM1_OC3PreloadConfig (FunctionalState NewState)
Enables or disables the TIM1 peripheral Preload Register on CCR3.
void | TIM1_OC4FastConfig (FunctionalState NewState)
Configures the TIM1 Capture Compare 4 Fast feature.
void | TIM1_OC4Init (TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState)
Initializes the TIM1 Channel4 according to the specified parameters.
void | TIM1_OC4PolarityConfig (TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
Configures the TIM1 Channel 4 polarity.
void | TIM1_OC4PreloadConfig (FunctionalState NewState)
Enables or disables the TIM1 peripheral Preload Register on CCR4.
void | TIM1_PrescalerConfig (uint16_t Prescaler, TIM1_PSCReloadMode_TypeDef TIM1_PSCReloadMode)
Configures the TIM1 Prescaler.
void | TIM1_PWMIConfig (TIM1_Channel_TypeDef TIM1_Channel, TIM1_ICPolarity_TypeDef TIM1_ICPolarity, TIM1_ICSelection_TypeDef TIM1_ICSelection, TIM1_ICPSC_TypeDef TIM1_ICPrescaler, uint8_t TIM1_ICFilter)
Configures the TIM1 peripheral in PWM Input Mode according to the specified parameters.
void | TIM1_SelectCOM (FunctionalState NewState)
Selects the TIM1 peripheral Commutation event.
void | TIM1_SelectHallSensor (FunctionalState NewState)
Enables or Disables the TIM1’s Hall sensor interface.
void | TIM1_SelectInputTrigger (TIM1_TS_TypeDef TIM1_InputTriggerSource)
Selects the TIM1 Input Trigger source.
void | TIM1_SelectMasterSlaveMode (FunctionalState NewState)
Sets or Resets the TIM1 Master/Slave Mode.
void | TIM1_SelectOCxM (TIM1_Channel_TypeDef TIM1_Channel, TIM1_OCMode_TypeDef TIM1_OCMode)
Selects the TIM1 Output Compare Mode.
void | TIM1_SelectOnePulseMode (TIM1_OPMode_TypeDef TIM1_OPMode)
Selects the TIM1’s One Pulse Mode.
void | TIM1_SelectOutputTrigger (TIM1_TRGOSource_TypeDef TIM1_TRGOSource)
Selects the TIM1 Trigger Output Mode.
void | TIM1_SelectSlaveMode (TIM1_SlaveMode_TypeDef TIM1_SlaveMode)
Selects the TIM1 Slave Mode.
void | TIM1_SetAutoreload (uint16_t Autoreload)
Sets the TIM1 Autoreload Register value.
void | TIM1_SetCompare1 (uint16_t Compare1)
Sets the TIM1 Capture Compare1 Register value.
void | TIM1_SetCompare2 (uint16_t Compare2)
Sets the TIM1 Capture Compare2 Register value.
void | TIM1_SetCompare3 (uint16_t Compare3)
Sets the TIM1 Capture Compare3 Register value.
void | TIM1_SetCompare4 (uint16_t Compare4)
Sets the TIM1 Capture Compare4 Register value.
void | TIM1_SetCounter (uint16_t Counter)
Sets the TIM1 Counter Register value.
void | TIM1_SetIC1Prescaler (TIM1_ICPSC_TypeDef TIM1_IC1Prescaler)
Sets the TIM1 Input Capture 1 prescaler.
void | TIM1_SetIC2Prescaler (TIM1_ICPSC_TypeDef TIM1_IC2Prescaler)
Sets the TIM1 Input Capture 2 prescaler.
void | TIM1_SetIC3Prescaler (TIM1_ICPSC_TypeDef TIM1_IC3Prescaler)
Sets the TIM1 Input Capture 3 prescaler.
void | TIM1_SetIC4Prescaler (TIM1_ICPSC_TypeDef TIM1_IC4Prescaler)
Sets the TIM1 Input Capture 4 prescaler.
void | TIM1_TimeBaseInit (uint16_t TIM1_Prescaler, TIM1_CounterMode_TypeDef TIM1_CounterMode, uint16_t TIM1_Period, uint8_t TIM1_RepetitionCounter)
Initializes the TIM1 Time Base Unit according to the specified parameters.
void | TIM1_TIxExternalClockConfig (TIM1_TIxExternalCLK1Source_TypeDef TIM1_TIxExternalCLKSource, TIM1_ICPolarity_TypeDef TIM1_ICPolarity, uint8_t ICFilter)
Configures the TIM1 Trigger as External Clock.
void | TIM1_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM1 Update event.
void | TIM1_UpdateRequestConfig (TIM1_UpdateSource_TypeDef TIM1_UpdateSource)
Selects the TIM1 Update Request Interrupt source.

Function Documentation

static void TI1_Config | ( | uint8_t | TIM1_ICPolarity,
 |  | uint8_t | TIM1_ICSelection,
 |  | uint8_t | TIM1_ICFilter
 | ) |  | [static]

Configure the TI1 as Input.

Parameters:
TIM1_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM1_ICPOLARITY_FALLING
  • TIM1_ICPOLARITY_RISING
TIM1_ICSelection specifies the input to be used. This parameter can be one of the following values:
  • TIM1_ICSELECTION_DIRECTTI: TIM1 Input 1 is selected to be connected to IC1.
  • TIM1_ICSELECTION_INDIRECTTI: TIM1 Input 1 is selected to be connected to IC2.
TIM1_ICFilter Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 2174 of file stm8s_tim1.c.

References TIM1, TIM1_CCER1_CC1E, TIM1_CCER1_CC1P, TIM1_CCMR_CCxS, TIM1_CCMR_ICxF, and TIM1_ICPOLARITY_RISING.

Referenced by TIM1_ICInit(), TIM1_PWMIConfig(), and TIM1_TIxExternalClockConfig().

static void TI2_Config | ( | uint8_t | TIM1_ICPolarity,
 |  | uint8_t | TIM1_ICSelection,
 |  | uint8_t | TIM1_ICFilter
 | ) |  | [static]

Configure the TI2 as Input.

Parameters:
TIM1_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM1_ICPOLARITY_FALLING
  • TIM1_ICPOLARITY_RISING
TIM1_ICSelection specifies the input to be used. This parameter can be one of the following values:
  • TIM1_ICSELECTION_DIRECTTI: TIM1 Input 2 is selected to be connected to IC2.
  • TIM1_ICSELECTION_INDIRECTTI: TIM1 Input 2 is selected to be connected to IC1.
TIM1_ICFilter Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 2215 of file stm8s_tim1.c.

References TIM1, TIM1_CCER1_CC2E, TIM1_CCER1_CC2P, TIM1_CCMR_CCxS, TIM1_CCMR_ICxF, and TIM1_ICPOLARITY_RISING.

Referenced by TIM1_ICInit(), TIM1_PWMIConfig(), and TIM1_TIxExternalClockConfig().

static void TI3_Config | ( | uint8_t | TIM1_ICPolarity,
 |  | uint8_t | TIM1_ICSelection,
 |  | uint8_t | TIM1_ICFilter
 | ) |  | [static]

Configure the TI3 as Input.

Parameters:
TIM1_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM1_ICPOLARITY_FALLING
  • TIM1_ICPOLARITY_RISING
TIM1_ICSelection specifies the input to be used. This parameter can be one of the following values:
  • TIM1_ICSELECTION_DIRECTTI: TIM1 Input 3 is selected to be connected to IC3.
  • TIM1_ICSELECTION_INDIRECTTI: TIM1 Input 3 is selected to be connected to IC4.
TIM1_ICFilter Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 2254 of file stm8s_tim1.c.

References TIM1, TIM1_CCER2_CC3E, TIM1_CCER2_CC3P, TIM1_CCMR_CCxS, TIM1_CCMR_ICxF, and TIM1_ICPOLARITY_RISING.

Referenced by TIM1_ICInit().

static void TI4_Config | ( | uint8_t | TIM1_ICPolarity,
 |  | uint8_t | TIM1_ICSelection,
 |  | uint8_t | TIM1_ICFilter
 | ) |  | [static]

Configure the TI4 as Input.

Parameters:
TIM1_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM1_ICPOLARITY_FALLING
  • TIM1_ICPOLARITY_RISING
TIM1_ICSelection specifies the input to be used. This parameter can be one of the following values:
  • TIM1_ICSELECTION_DIRECTTI: TIM1 Input 4 is selected to be connected to IC4.
  • TIM1_ICSELECTION_INDIRECTTI: TIM1 Input 4 is selected to be connected to IC3.
TIM1_ICFilter Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 2294 of file stm8s_tim1.c.

References TIM1, TIM1_CCER2_CC4E, TIM1_CCER2_CC4P, TIM1_CCMR_CCxS, TIM1_CCMR_ICxF, and TIM1_ICPOLARITY_RISING.

Referenced by TIM1_ICInit().

void TIM1_ARRPreloadConfig ( FunctionalState NewState )

Enables or disables TIM1 peripheral Preload register on ARR.

Parameters:
NewState new state of the TIM1 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1139 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CR1_ARPE.

void TIM1_BDTRConfig | ( | TIM1_OSSIState_TypeDef | TIM1_OSSIState,
 |  | TIM1_LockLevel_TypeDef | TIM1_LockLevel,
 |  | uint8_t | TIM1_DeadTime,
 |  | TIM1_BreakState_TypeDef | TIM1_Break,
 |  | TIM1_BreakPolarity_TypeDef | TIM1_BreakPolarity,
 |  | TIM1_AutomaticOutput_TypeDef | TIM1_AutomaticOutput
 | ) |  |

Configures the Break feature, dead time, Lock level, the OSSI, and the AOE(automatic output enable).

Parameters:
TIM1_OSSIState | specifies the OSSIS State from TIM1_OSSIState_TypeDef.
TIM1_LockLevel | specifies the lock level from TIM1_LockLevel_TypeDef.
TIM1_DeadTime | specifies the dead time value.
TIM1_Break | specifies the Break state TIM1_BreakState_TypeDef.
TIM1_BreakPolarity | specifies the Break polarity from TIM1_BreakPolarity_TypeDef.
TIM1_AutomaticOutput | specifies the Automatic Output configuration from TIM1_AutomaticOutput_TypeDef.
Return values:
None

Definition at line 388 of file stm8s_tim1.c.

References IS_TIM1_AUTOMATIC_OUTPUT_STATE_OK, IS_TIM1_BREAK_POLARITY_OK, IS_TIM1_BREAK_STATE_OK, IS_TIM1_LOCK_LEVEL_OK, IS_TIM1_OSSI_STATE_OK, and TIM1.

void TIM1_CCPreloadControl ( FunctionalState NewState )

Sets or Resets the TIM1 peripheral Capture Compare Preload Control bit.

Parameters:
NewState new state of the Capture Compare Preload Control bit. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1183 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CR2_CCPC.

void TIM1_CCxCmd | ( | TIM1_Channel_TypeDef | TIM1_Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the TIM1 Capture Compare Channel x (x=1,..,4).

Parameters:
TIM1_Channel specifies the TIM1 Channel. This parameter can be one of the following values:
  • TIM1_CHANNEL_1: TIM1 Channel1
  • TIM1_CHANNEL_2: TIM1 Channel2
  • TIM1_CHANNEL_3: TIM1 Channel3
  • TIM1_CHANNEL_4: TIM1 Channel4
NewState specifies the TIM1 Channel CCxE bit new state. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1579 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, IS_TIM1_CHANNEL_OK, TIM1, TIM1_CCER1_CC1E, TIM1_CCER1_CC2E, TIM1_CCER2_CC3E, TIM1_CCER2_CC4E, TIM1_CHANNEL_1, TIM1_CHANNEL_2, and TIM1_CHANNEL_3.

void TIM1_CCxNCmd | ( | TIM1_Channel_TypeDef | TIM1_Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the TIM1 Capture Compare Channel xN (xN=1,..,3).

Parameters:
TIM1_Channel specifies the TIM1 Channel. This parameter can be one of the following values:
  • TIM1_CHANNEL_1: TIM1 Channel1
  • TIM1_CHANNEL_2: TIM1 Channel2
  • TIM1_CHANNEL_3: TIM1 Channel3
NewState specifies the TIM1 Channel CCxNE bit new state. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1647 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, IS_TIM1_COMPLEMENTARY_CHANNEL_OK, TIM1, TIM1_CCER1_CC1NE, TIM1_CCER1_CC2NE, TIM1_CCER2_CC3NE, TIM1_CHANNEL_1, and TIM1_CHANNEL_2.

void TIM1_ClearFlag ( TIM1_FLAG_TypeDef TIM1_FLAG )

Clears the TIM1’s pending flags.

Parameters:
TIM1_FLAG specifies the flag to clear. This parameter can be one of the following values:
  • TIM1_FLAG_UPDATE: TIM1 update Flag
  • TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag
  • TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag
  • TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag
  • TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag
  • TIM1_FLAG_COM: TIM1 Commutation Flag
  • TIM1_FLAG_TRIGGER: TIM1 Trigger Flag
  • TIM1_FLAG_BREAK: TIM1 Break Flag
  • TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag
  • TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag
  • TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag
  • TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag
Return values:
None.

Definition at line 2087 of file stm8s_tim1.c.

References IS_TIM1_CLEAR_FLAG_OK, and TIM1.

void TIM1_ClearITPendingBit ( TIM1_IT_TypeDef TIM1_IT )

Clears the TIM1's interrupt pending bits.

Parameters:
TIM1_IT specifies the pending bit to clear. This parameter can be one of the following values:
  • TIM1_IT_UPDATE: TIM1 update Interrupt source
  • TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source
  • TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source
  • TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source
  • TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source
  • TIM1_IT_COM: TIM1 Commutation Interrupt source
  • TIM1_IT_TRIGGER: TIM1 Trigger Interrupt source
  • TIM1_IT_BREAK: TIM1 Break Interrupt source
Return values:
None.

Definition at line 2149 of file stm8s_tim1.c.

References IS_TIM1_IT_OK, and TIM1.

void TIM1_Cmd ( FunctionalState NewState )

Enables or disables the TIM1 peripheral.

Parameters:
NewState new state of the TIM1 peripheral. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 561 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CR1_CEN.

void TIM1_CounterModeConfig ( TIM1_CounterMode_TypeDef TIM1_CounterMode )

Specifies the TIM1 Counter Mode to be used.

Parameters:
TIM1_CounterMode specifies the Counter Mode to be used This parameter can be one of the following values:
  • TIM1_COUNTERMODE_UP: TIM1 Up Counting Mode
  • TIM1_COUNTERMODE_DOWN: TIM1 Down Counting Mode
  • TIM1_COUNTERMODE_CENTERALIGNED1: TIM1 Center Aligned Mode1
  • TIM1_CounterMode_CenterAligned2: TIM1 Center Aligned Mode2
  • TIM1_COUNTERMODE_CENTERALIGNED3: TIM1 Center Aligned Mode3
Return values:
None

Definition at line 1048 of file stm8s_tim1.c.

References IS_TIM1_COUNTER_MODE_OK, TIM1, TIM1_CR1_CMS, and TIM1_CR1_DIR.

void TIM1_CtrlPWMOutputs ( FunctionalState NewState )

Enables or disables the TIM1 peripheral Main Outputs.

Parameters:
NewState new state of the TIM1 peripheral. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 583 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_BKR_MOE.

void TIM1_DeInit ( void )

Deinitializes the TIM1 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 58 of file stm8s_tim1.c.

References TIM1, TIM1_ARRH_RESET_VALUE, TIM1_ARRL_RESET_VALUE, TIM1_BKR_RESET_VALUE, TIM1_CCER1_RESET_VALUE, TIM1_CCER2_RESET_VALUE, TIM1_CCMR1_RESET_VALUE, TIM1_CCMR2_RESET_VALUE, TIM1_CCMR3_RESET_VALUE, TIM1_CCMR4_RESET_VALUE, TIM1_CCR1H_RESET_VALUE, TIM1_CCR1L_RESET_VALUE, TIM1_CCR2H_RESET_VALUE, TIM1_CCR2L_RESET_VALUE, TIM1_CCR3H_RESET_VALUE, TIM1_CCR3L_RESET_VALUE, TIM1_CCR4H_RESET_VALUE, TIM1_CCR4L_RESET_VALUE, TIM1_CNTRH_RESET_VALUE, TIM1_CNTRL_RESET_VALUE, TIM1_CR1_RESET_VALUE, TIM1_CR2_RESET_VALUE, TIM1_DTR_RESET_VALUE, TIM1_ETR_RESET_VALUE, TIM1_IER_RESET_VALUE, TIM1_OISR_RESET_VALUE, TIM1_PSCRH_RESET_VALUE, TIM1_PSCRL_RESET_VALUE, TIM1_RCR_RESET_VALUE, TIM1_SMCR_RESET_VALUE, TIM1_SR1_RESET_VALUE, and TIM1_SR2_RESET_VALUE.

void TIM1_EncoderInterfaceConfig | ( | TIM1_EncoderMode_TypeDef | TIM1_EncoderMode,
 |  | TIM1_ICPolarity_TypeDef | TIM1_IC1Polarity,
 |  | TIM1_ICPolarity_TypeDef | TIM1_IC2Polarity
 | ) |  |

Configures the TIM1 Encoder Interface.

Parameters:
TIM1_EncoderMode specifies the TIM1 Encoder Mode. This parameter can be one of the following values
  • TIM1_ENCODERMODE_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
  • TIM1_ENCODERMODE_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
  • TIM1_ENCODERMODE_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
TIM1_IC1Polarity specifies the IC1 Polarity. This parameter can be one of the following values
  • TIM1_ICPOLARITY_FALLING
  • TIM1_ICPOLARITY_RISING
TIM1_IC2Polarity specifies the IC2 Polarity. This parameter can be one of the following values
  • TIM1_ICPOLARITY_FALLING
  • TIM1_ICPOLARITY_RISING
Return values:
None

Definition at line 975 of file stm8s_tim1.c.

References CCMR_TIxDirect_Set, IS_TIM1_ENCODER_MODE_OK, IS_TIM1_IC_POLARITY_OK, TIM1, TIM1_CCER1_CC1P, TIM1_CCER1_CC2P, TIM1_CCMR_CCxS, TIM1_ICPOLARITY_RISING, TIM1_SMCR_MSM, and TIM1_SMCR_TS.

void TIM1_ETRClockMode1Config | ( | TIM1_ExtTRGPSC_TypeDef | TIM1_ExtTRGPrescaler,
 |  | TIM1_ExtTRGPolarity_TypeDef | TIM1_ExtTRGPolarity,
 |  | uint8_t | ExtTRGFilter
 | ) |  |

Configures the TIM1 External clock Mode1.

Parameters:
TIM1_ExtTRGPrescaler specifies the external Trigger Prescaler. This parameter can be one of the following values:
  • TIM1_EXTTRGPSC_OFF
  • TIM1_EXTTRGPSC_DIV2
  • TIM1_EXTTRGPSC_DIV4
  • TIM1_EXTTRGPSC_DIV8.
TIM1_ExtTRGPolarity specifies the external Trigger Polarity. This parameter can be one of the following values:
  • TIM1_EXTTRGPOLARITY_INVERTED
  • TIM1_EXTTRGPOLARITY_NONINVERTED
ExtTRGFilter specifies the External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 662 of file stm8s_tim1.c.

References IS_TIM1_EXT_POLARITY_OK, IS_TIM1_EXT_PRESCALER_OK, TIM1, TIM1_ETRConfig(), TIM1_SLAVEMODE_EXTERNAL1, TIM1_SMCR_SMS, TIM1_SMCR_TS, and TIM1_TS_ETRF.

void TIM1_ETRClockMode2Config | ( | TIM1_ExtTRGPSC_TypeDef | TIM1_ExtTRGPrescaler,
 |  | TIM1_ExtTRGPolarity_TypeDef | TIM1_ExtTRGPolarity,
 |  | uint8_t | ExtTRGFilter
 | ) |  |

Configures the TIM1 External clock Mode2.

Parameters:
TIM1_ExtTRGPrescaler specifies the external Trigger Prescaler. This parameter can be one of the following values:
  • TIM1_EXTTRGPSC_OFF
  • TIM1_EXTTRGPSC_DIV2
  • TIM1_EXTTRGPSC_DIV4
  • TIM1_EXTTRGPSC_DIV8.
TIM1_ExtTRGPolarity specifies the external Trigger Polarity. This parameter can be one of the following values:
  • TIM1_EXTTRGPOLARITY_INVERTED
  • TIM1_EXTTRGPOLARITY_NONINVERTED
ExtTRGFilter specifies the External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 694 of file stm8s_tim1.c.

References IS_TIM1_EXT_POLARITY_OK, IS_TIM1_EXT_PRESCALER_OK, TIM1, TIM1_ETR_ECE, and TIM1_ETRConfig().

void TIM1_ETRConfig | ( | TIM1_ExtTRGPSC_TypeDef | TIM1_ExtTRGPrescaler,
 |  | TIM1_ExtTRGPolarity_TypeDef | TIM1_ExtTRGPolarity,
 |  | uint8_t | ExtTRGFilter
 | ) |  |

Configures the TIM1 External Trigger.

Parameters:
TIM1_ExtTRGPrescaler specifies the external Trigger Prescaler. This parameter can be one of the following values:
  • TIM1_EXTTRGPSC_OFF
  • TIM1_EXTTRGPSC_DIV2
  • TIM1_EXTTRGPSC_DIV4
  • TIM1_EXTTRGPSC_DIV8.
TIM1_ExtTRGPolarity specifies the external Trigger Polarity. This parameter can be one of the following values:
  • TIM1_EXTTRGPOLARITY_INVERTED
  • TIM1_EXTTRGPOLARITY_NONINVERTED
ExtTRGFilter specifies the External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 725 of file stm8s_tim1.c.

References IS_TIM1_EXT_TRG_FILTER_OK, and TIM1.

Referenced by TIM1_ETRClockMode1Config(), and TIM1_ETRClockMode2Config().

void TIM1_ForcedOC1Config ( TIM1_ForcedAction_TypeDef TIM1_ForcedAction )

Forces the TIM1 Channel1 output waveform to active or inactive level.

Parameters:
TIM1_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:
  • TIM1_FORCEDACTION_ACTIVE: Force active level on OC1REF
  • TIM1_FORCEDACTION_INACTIVE: Force inactive level on OC1REF.
Return values:
None

Definition at line 1067 of file stm8s_tim1.c.

References IS_TIM1_FORCED_ACTION_OK, TIM1, and TIM1_CCMR_OCM.

void TIM1_ForcedOC2Config ( TIM1_ForcedAction_TypeDef TIM1_ForcedAction )

Forces the TIM1 Channel2 output waveform to active or inactive level.

Parameters:
TIM1_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:
  • TIM1_FORCEDACTION_ACTIVE: Force active level on OC2REF
  • TIM1_FORCEDACTION_INACTIVE: Force inactive level on OC2REF.
Return values:
None

Definition at line 1085 of file stm8s_tim1.c.

References IS_TIM1_FORCED_ACTION_OK, TIM1, and TIM1_CCMR_OCM.

void TIM1_ForcedOC3Config ( TIM1_ForcedAction_TypeDef TIM1_ForcedAction )

Forces the TIM1 Channel3 output waveform to active or inactive level.

Parameters:
TIM1_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:
  • TIM1_FORCEDACTION_ACTIVE: Force active level on OC3REF
  • TIM1_FORCEDACTION_INACTIVE: Force inactive level on OC3REF.
Return values:
None

Definition at line 1104 of file stm8s_tim1.c.

References IS_TIM1_FORCED_ACTION_OK, TIM1, and TIM1_CCMR_OCM.

void TIM1_ForcedOC4Config ( TIM1_ForcedAction_TypeDef TIM1_ForcedAction )

Forces the TIM1 Channel4 output waveform to active or inactive level.

Parameters:
TIM1_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:
  • TIM1_FORCEDACTION_ACTIVE: Force active level on OC4REF
  • TIM1_FORCEDACTION_INACTIVE: Force inactive level on OC4REF.
Return values:
None

Definition at line 1123 of file stm8s_tim1.c.

References IS_TIM1_FORCED_ACTION_OK, TIM1, and TIM1_CCMR_OCM.

void TIM1_GenerateEvent ( TIM1_EventSource_TypeDef TIM1_EventSource )

Configures the TIM1 event to be generated by software.

Parameters:
TIM1_EventSource specifies the event source. This parameter can be one of the following values:
  • TIM1_EVENTSOURCE_UPDATE: TIM1 update Event source
  • TIM1_EVENTSOURCE_CC1: TIM1 Capture Compare 1 Event source
  • TIM1_EVENTSOURCE_CC2: TIM1 Capture Compare 2 Event source
  • TIM1_EVENTSOURCE_CC3: TIM1 Capture Compare 3 Event source
  • TIM1_EVENTSOURCE_CC4: TIM1 Capture Compare 4 Event source
  • TIM1_EVENTSOURCE_COM: TIM1 COM Event source
  • TIM1_EVENTSOURCE_TRIGGER: TIM1 Trigger Event source
  • TIM1_EventSourceBreak: TIM1 Break Event source
Return values:
None

Definition at line 1389 of file stm8s_tim1.c.

References IS_TIM1_EVENT_SOURCE_OK, and TIM1.

uint16_t TIM1_GetCapture1 ( void )

Gets the TIM1 Input Capture 1 value.

Parameters:
None
Return values:
Capture Compare 1 Register value.

Definition at line 1922 of file stm8s_tim1.c.

References TIM1.

uint16_t TIM1_GetCapture2 ( void )

Gets the TIM1 Input Capture 2 value.

Parameters:
None
Return values:
Capture Compare 2 Register value.

Definition at line 1943 of file stm8s_tim1.c.

References TIM1.

uint16_t TIM1_GetCapture3 ( void )

Gets the TIM1 Input Capture 3 value.

Parameters:
None
Return values:
Capture Compare 3 Register value.

Definition at line 1964 of file stm8s_tim1.c.

References TIM1.

uint16_t TIM1_GetCapture4 ( void )

Gets the TIM1 Input Capture 4 value.

Parameters:
None
Return values:
Capture Compare 4 Register value.

Definition at line 1984 of file stm8s_tim1.c.

References TIM1.

uint16_t TIM1_GetCounter ( void )

Gets the TIM1 Counter value.

Parameters:
None
Return values:
Counter Register value.

Definition at line 2004 of file stm8s_tim1.c.

References TIM1.

FlagStatus TIM1_GetFlagStatus ( TIM1_FLAG_TypeDef TIM1_FLAG )

Checks whether the specified TIM1 flag is set or not.

Parameters:
TIM1_FLAG specifies the flag to check. This parameter can be one of the following values:
  • TIM1_FLAG_UPDATE: TIM1 update Flag
  • TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag
  • TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag
  • TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag
  • TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag
  • TIM1_FLAG_COM: TIM1 Commutation Flag
  • TIM1_FLAG_TRIGGER: TIM1 Trigger Flag
  • TIM1_FLAG_BREAK: TIM1 Break Flag
  • TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag
  • TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag
  • TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag
  • TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag
Return values:
FlagStatus The new state of TIM1_FLAG (SET or RESET).

Definition at line 2047 of file stm8s_tim1.c.

References IS_TIM1_GET_FLAG_OK, RESET, SET, and TIM1.

ITStatus TIM1_GetITStatus ( TIM1_IT_TypeDef TIM1_IT )

Checks whether the TIM1 interrupt has occurred or not.

Parameters:
TIM1_IT specifies the TIM1 interrupt source to check. This parameter can be one of the following values:
  • TIM1_IT_UPDATE: TIM1 update Interrupt source
  • TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source
  • TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source
  • TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source
  • TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source
  • TIM1_IT_COM: TIM1 Commutation Interrupt source
  • TIM1_IT_TRIGGER: TIM1 Trigger Interrupt source
  • TIM1_IT_BREAK: TIM1 Break Interrupt source
Return values:
ITStatus The new state of the TIM1_IT(SET or RESET).

Definition at line 2112 of file stm8s_tim1.c.

References IS_TIM1_GET_IT_OK, RESET, SET, and TIM1.

uint16_t TIM1_GetPrescaler ( void )

Gets the TIM1 Prescaler value.

Parameters:
None
Return values:
Prescaler Register value.

Definition at line 2019 of file stm8s_tim1.c.

References TIM1.

void TIM1_ICInit | ( | TIM1_Channel_TypeDef | TIM1_Channel,
 |  | TIM1_ICPolarity_TypeDef | TIM1_ICPolarity,
 |  | TIM1_ICSelection_TypeDef | TIM1_ICSelection,
 |  | TIM1_ICPSC_TypeDef | TIM1_ICPrescaler,
 |  | uint8_t | TIM1_ICFilter
 | ) |  |

Initializes the TIM1 peripheral according to the specified parameters.

Parameters:
TIM1_Channel | specifies the input capture channel from TIM1_Channel_TypeDef.
TIM1_ICPolarity | specifies the Input capture polarity from TIM1_ICPolarity_TypeDef .
TIM1_ICSelection | specifies the Input capture source selection from TIM1_ICSelection_TypeDef.
TIM1_ICPrescaler | specifies the Input capture Prescaler from TIM1_ICPSC_TypeDef.
TIM1_ICFilter | specifies the Input capture filter value.
Return values:
None

Definition at line 423 of file stm8s_tim1.c.

References IS_TIM1_CHANNEL_OK, IS_TIM1_IC_FILTER_OK, IS_TIM1_IC_POLARITY_OK, IS_TIM1_IC_PRESCALER_OK, IS_TIM1_IC_SELECTION_OK, TI1_Config(), TI2_Config(), TI3_Config(), TI4_Config(), TIM1_CHANNEL_1, TIM1_CHANNEL_2, TIM1_CHANNEL_3, TIM1_SetIC1Prescaler(), TIM1_SetIC2Prescaler(), TIM1_SetIC3Prescaler(), and TIM1_SetIC4Prescaler().

void TIM1_InternalClockConfig ( void )

Configures the TIM1 internal Clock.

Parameters:
None
Return values:
None

Definition at line 640 of file stm8s_tim1.c.

References TIM1, and TIM1_SMCR_SMS.

void TIM1_ITConfig | ( | TIM1_IT_TypeDef | TIM1_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified TIM1 interrupts.

Parameters:
NewState | new state of the TIM1 peripheral. This parameter can be: ENABLE or DISABLE.
TIM1_IT specifies the TIM1 interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:
  • TIM1_IT_UPDATE: TIM1 update Interrupt source
  • TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source
  • TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source
  • TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source
  • TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source
  • TIM1_IT_CCUpdate: TIM1 Capture Compare Update Interrupt source
  • TIM1_IT_TRIGGER: TIM1 Trigger Interrupt source
  • TIM1_IT_BREAK: TIM1 Break Interrupt source
NewState | new state of the TIM1 peripheral.
Return values:
None

Definition at line 617 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, IS_TIM1_IT_OK, and TIM1.

void TIM1_OC1FastConfig ( FunctionalState NewState )

Configures the TIM1 Capture Compare 1 Fast feature.

Parameters:
NewState new state of the Output Compare Fast Enable bit. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1293 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CCMR_OCxFE.

void TIM1_OC1Init | ( | TIM1_OCMode_TypeDef | TIM1_OCMode,
 |  | TIM1_OutputState_TypeDef | TIM1_OutputState,
 |  | TIM1_OutputNState_TypeDef | TIM1_OutputNState,
 |  | uint16_t | TIM1_Pulse,
 |  | TIM1_OCPolarity_TypeDef | TIM1_OCPolarity,
 |  | TIM1_OCNPolarity_TypeDef | TIM1_OCNPolarity,
 |  | TIM1_OCIdleState_TypeDef | TIM1_OCIdleState,
 |  | TIM1_OCNIdleState_TypeDef | TIM1_OCNIdleState
 | ) |  |

Initializes the TIM1 Channel1 according to the specified parameters.

Parameters:
TIM1_OCMode | specifies the Output Compare mode from TIM1_OCMode_TypeDef.
TIM1_OutputState | specifies the Output State from TIM1_OutputState_TypeDef.
TIM1_OutputNState | specifies the Complementary Output State from TIM1_OutputNState_TypeDef.
TIM1_Pulse | specifies the Pulse width value.
TIM1_OCPolarity | specifies the Output Compare Polarity from TIM1_OCPolarity_TypeDef.
TIM1_OCNPolarity | specifies the Complementary Output Compare Polarity from TIM1_OCNPolarity_TypeDef.
TIM1_OCIdleState | specifies the Output Compare Idle State from TIM1_OCIdleState_TypeDef.
TIM1_OCNIdleState | specifies the Complementary Output Compare Idle State from TIM1_OCIdleState_TypeDef.
Return values:
None

Definition at line 154 of file stm8s_tim1.c.

References IS_TIM1_OC_MODE_OK, IS_TIM1_OC_POLARITY_OK, IS_TIM1_OCIDLE_STATE_OK, IS_TIM1_OCN_POLARITY_OK, IS_TIM1_OCNIDLE_STATE_OK, IS_TIM1_OUTPUT_STATE_OK, IS_TIM1_OUTPUTN_STATE_OK, TIM1, TIM1_CCER1_CC1E, TIM1_CCER1_CC1NE, TIM1_CCER1_CC1NP, TIM1_CCER1_CC1P, TIM1_CCMR_OCM, TIM1_OISR_OIS1, and TIM1_OISR_OIS1N.

void TIM1_OC1NPolarityConfig ( TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity )

Configures the TIM1 Channel 1N polarity.

Parameters:
TIM1_OCNPolarity specifies the OC1N Polarity. This parameter can be one of the following values:
  • TIM1_OCNPOLARITY_LOW: Output Compare active low
  • TIM1_OCNPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 1430 of file stm8s_tim1.c.

References IS_TIM1_OCN_POLARITY_OK, TIM1, TIM1_CCER1_CC1NP, and TIM1_OCNPOLARITY_HIGH.

void TIM1_OC1PolarityConfig ( TIM1_OCPolarity_TypeDef TIM1_OCPolarity )

Configures the TIM1 Channel 1 polarity.

Parameters:
TIM1_OCPolarity specifies the OC1 Polarity. This parameter can be one of the following values:
  • TIM1_OCPOLARITY_LOW: Output Compare active low
  • TIM1_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 1406 of file stm8s_tim1.c.

References IS_TIM1_OC_POLARITY_OK, TIM1, TIM1_CCER1_CC1P, and TIM1_OCPOLARITY_HIGH.

void TIM1_OC1PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM1 peripheral Preload Register on CCR1.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1205 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CCMR_OCxPE.

void TIM1_OC2FastConfig ( FunctionalState NewState )

Configures the TIM1 Capture Compare 2 Fast feature.

Parameters:
NewState new state of the Output Compare Fast Enable bit. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1315 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CCMR_OCxFE.

void TIM1_OC2Init | ( | TIM1_OCMode_TypeDef | TIM1_OCMode,
 |  | TIM1_OutputState_TypeDef | TIM1_OutputState,
 |  | TIM1_OutputNState_TypeDef | TIM1_OutputNState,
 |  | uint16_t | TIM1_Pulse,
 |  | TIM1_OCPolarity_TypeDef | TIM1_OCPolarity,
 |  | TIM1_OCNPolarity_TypeDef | TIM1_OCNPolarity,
 |  | TIM1_OCIdleState_TypeDef | TIM1_OCIdleState,
 |  | TIM1_OCNIdleState_TypeDef | TIM1_OCNIdleState
 | ) |  |

Initializes the TIM1 Channel2 according to the specified parameters.

Parameters:
TIM1_OCMode | specifies the Output Compare mode from TIM1_OCMode_TypeDef.
TIM1_OutputState | specifies the Output State from TIM1_OutputState_TypeDef.
TIM1_OutputNState | specifies the Complementary Output State from TIM1_OutputNState_TypeDef.
TIM1_Pulse | specifies the Pulse width value.
TIM1_OCPolarity | specifies the Output Compare Polarity from TIM1_OCPolarity_TypeDef.
TIM1_OCNPolarity | specifies the Complementary Output Compare Polarity from TIM1_OCNPolarity_TypeDef.
TIM1_OCIdleState | specifies the Output Compare Idle State from TIM1_OCIdleState_TypeDef.
TIM1_OCNIdleState | specifies the Complementary Output Compare Idle State from TIM1_OCIdleState_TypeDef.
Return values:
None

Definition at line 217 of file stm8s_tim1.c.

References IS_TIM1_OC_MODE_OK, IS_TIM1_OC_POLARITY_OK, IS_TIM1_OCIDLE_STATE_OK, IS_TIM1_OCN_POLARITY_OK, IS_TIM1_OCNIDLE_STATE_OK, IS_TIM1_OUTPUT_STATE_OK, IS_TIM1_OUTPUTN_STATE_OK, TIM1, TIM1_CCER1_CC2E, TIM1_CCER1_CC2NE, TIM1_CCER1_CC2NP, TIM1_CCER1_CC2P, TIM1_CCMR_OCM, TIM1_OISR_OIS2, and TIM1_OISR_OIS2N.

void TIM1_OC2NPolarityConfig ( TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity )

Configures the TIM1 Channel 2N polarity.

Parameters:
TIM1_OCNPolarity specifies the OC2N Polarity. This parameter can be one of the following values:
  • TIM1_OCNPOLARITY_LOW: Output Compare active low
  • TIM1_OCNPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 1478 of file stm8s_tim1.c.

References IS_TIM1_OCN_POLARITY_OK, TIM1, TIM1_CCER1_CC2NP, and TIM1_OCNPOLARITY_HIGH.

void TIM1_OC2PolarityConfig ( TIM1_OCPolarity_TypeDef TIM1_OCPolarity )

Configures the TIM1 Channel 2 polarity.

Parameters:
TIM1_OCPolarity specifies the OC2 Polarity. This parameter can be one of the following values:
  • TIM1_OCPOLARITY_LOW: Output Compare active low
  • TIM1_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 1454 of file stm8s_tim1.c.

References IS_TIM1_OC_POLARITY_OK, TIM1, TIM1_CCER1_CC2P, and TIM1_OCPOLARITY_HIGH.

void TIM1_OC2PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM1 peripheral Preload Register on CCR2.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1227 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CCMR_OCxPE.

void TIM1_OC3FastConfig ( FunctionalState NewState )

Configures the TIM1 Capture Compare 3 Fast feature.

Parameters:
NewState new state of the Output Compare Fast Enable bit. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1337 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CCMR_OCxFE.

void TIM1_OC3Init | ( | TIM1_OCMode_TypeDef | TIM1_OCMode,
 |  | TIM1_OutputState_TypeDef | TIM1_OutputState,
 |  | TIM1_OutputNState_TypeDef | TIM1_OutputNState,
 |  | uint16_t | TIM1_Pulse,
 |  | TIM1_OCPolarity_TypeDef | TIM1_OCPolarity,
 |  | TIM1_OCNPolarity_TypeDef | TIM1_OCNPolarity,
 |  | TIM1_OCIdleState_TypeDef | TIM1_OCIdleState,
 |  | TIM1_OCNIdleState_TypeDef | TIM1_OCNIdleState
 | ) |  |

Initializes the TIM1 Channel3 according to the specified parameters.

Parameters:
TIM1_OCMode | specifies the Output Compare mode from TIM1_OCMode_TypeDef.
TIM1_OutputState | specifies the Output State from TIM1_OutputState_TypeDef.
TIM1_OutputNState | specifies the Complementary Output State from TIM1_OutputNState_TypeDef.
TIM1_Pulse | specifies the Pulse width value.
TIM1_OCPolarity | specifies the Output Compare Polarity from TIM1_OCPolarity_TypeDef.
TIM1_OCNPolarity | specifies the Complementary Output Compare Polarity from TIM1_OCNPolarity_TypeDef.
TIM1_OCIdleState | specifies the Output Compare Idle State from TIM1_OCIdleState_TypeDef.
TIM1_OCNIdleState | specifies the Complementary Output Compare Idle State from TIM1_OCIdleState_TypeDef.
Return values:
None

Definition at line 281 of file stm8s_tim1.c.

References IS_TIM1_OC_MODE_OK, IS_TIM1_OC_POLARITY_OK, IS_TIM1_OCIDLE_STATE_OK, IS_TIM1_OCN_POLARITY_OK, IS_TIM1_OCNIDLE_STATE_OK, IS_TIM1_OUTPUT_STATE_OK, IS_TIM1_OUTPUTN_STATE_OK, TIM1, TIM1_CCER2_CC3E, TIM1_CCER2_CC3NE, TIM1_CCER2_CC3NP, TIM1_CCER2_CC3P, TIM1_CCMR_OCM, TIM1_OISR_OIS3, and TIM1_OISR_OIS3N.

void TIM1_OC3NPolarityConfig ( TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity )

Configures the TIM1 Channel 3N polarity.

Parameters:
TIM1_OCNPolarity specifies the OC3N Polarity. This parameter can be one of the following values:
  • TIM1_OCNPOLARITY_LOW: Output Compare active low
  • TIM1_OCNPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 1527 of file stm8s_tim1.c.

References IS_TIM1_OCN_POLARITY_OK, TIM1, TIM1_CCER2_CC3NP, and TIM1_OCNPOLARITY_HIGH.

void TIM1_OC3PolarityConfig ( TIM1_OCPolarity_TypeDef TIM1_OCPolarity )

Configures the TIM1 Channel 3 polarity.

Parameters:
TIM1_OCPolarity specifies the OC3 Polarity. This parameter can be one of the following values:
  • TIM1_OCPOLARITY_LOW: Output Compare active low
  • TIM1_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 1502 of file stm8s_tim1.c.

References IS_TIM1_OC_POLARITY_OK, TIM1, TIM1_CCER2_CC3P, and TIM1_OCPOLARITY_HIGH.

void TIM1_OC3PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM1 peripheral Preload Register on CCR3.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1249 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CCMR_OCxPE.

void TIM1_OC4FastConfig ( FunctionalState NewState )

Configures the TIM1 Capture Compare 4 Fast feature.

Parameters:
NewState new state of the Output Compare Fast Enable bit. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1359 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CCMR_OCxFE.

void TIM1_OC4Init | ( | TIM1_OCMode_TypeDef | TIM1_OCMode,
 |  | TIM1_OutputState_TypeDef | TIM1_OutputState,
 |  | uint16_t | TIM1_Pulse,
 |  | TIM1_OCPolarity_TypeDef | TIM1_OCPolarity,
 |  | TIM1_OCIdleState_TypeDef | TIM1_OCIdleState
 | ) |  |

Initializes the TIM1 Channel4 according to the specified parameters.

Parameters:
TIM1_OCMode | specifies the Output Compare mode from TIM1_OCMode_TypeDef.
TIM1_OutputState | specifies the Output State from TIM1_OutputState_TypeDef.
TIM1_Pulse | specifies the Pulse width value.
TIM1_OCPolarity | specifies the Output Compare Polarity from TIM1_OCPolarity_TypeDef.
TIM1_OCIdleState | specifies the Output Compare Idle State from TIM1_OCIdleState_TypeDef.
Return values:
None

Definition at line 338 of file stm8s_tim1.c.

References IS_TIM1_OC_MODE_OK, IS_TIM1_OC_POLARITY_OK, IS_TIM1_OCIDLE_STATE_OK, IS_TIM1_OUTPUT_STATE_OK, TIM1, TIM1_CCER2_CC4E, TIM1_CCER2_CC4P, TIM1_CCMR_OCM, TIM1_OCIDLESTATE_RESET, and TIM1_OISR_OIS4.

void TIM1_OC4PolarityConfig ( TIM1_OCPolarity_TypeDef TIM1_OCPolarity )

Configures the TIM1 Channel 4 polarity.

Parameters:
TIM1_OCPolarity specifies the OC4 Polarity. This parameter can be one of the following values:
  • TIM1_OCPOLARITY_LOW: Output Compare active low
  • TIM1_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 1551 of file stm8s_tim1.c.

References IS_TIM1_OC_POLARITY_OK, TIM1, TIM1_CCER2_CC4P, and TIM1_OCPOLARITY_HIGH.

void TIM1_OC4PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM1 peripheral Preload Register on CCR4.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1271 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CCMR_OCxPE.

void TIM1_PrescalerConfig | ( | uint16_t | Prescaler,
 |  | TIM1_PSCReloadMode_TypeDef | TIM1_PSCReloadMode
 | ) |  |

Configures the TIM1 Prescaler.

Parameters:
Prescaler specifies the Prescaler Register value This parameter must be a value between 0x0000 and 0xFFFF
TIM1_PSCReloadMode specifies the TIM1 Prescaler Reload mode. This parameter can be one of the following values
  • TIM1_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded immediately.
  • TIM1_PSCRELOADMODE_UPDATE: The Prescaler is loaded at the update event.
Return values:
None

Definition at line 1023 of file stm8s_tim1.c.

References IS_TIM1_PRESCALER_RELOAD_OK, and TIM1.

void TIM1_PWMIConfig | ( | TIM1_Channel_TypeDef | TIM1_Channel,
 |  | TIM1_ICPolarity_TypeDef | TIM1_ICPolarity,
 |  | TIM1_ICSelection_TypeDef | TIM1_ICSelection,
 |  | TIM1_ICPSC_TypeDef | TIM1_ICPrescaler,
 |  | uint8_t | TIM1_ICFilter
 | ) |  |

Configures the TIM1 peripheral in PWM Input Mode according to the specified parameters.

Parameters:
TIM1_Channel | specifies the input capture channel from TIM1_Channel_TypeDef.
TIM1_ICPolarity | specifies the Input capture polarity from TIM1_ICPolarity_TypeDef .
TIM1_ICSelection | specifies the Input capture source selection from TIM1_ICSelection_TypeDef.
TIM1_ICPrescaler | specifies the Input capture Prescaler from TIM1_ICPSC_TypeDef.
TIM1_ICFilter | specifies the Input capture filter value.
Return values:
None

Definition at line 488 of file stm8s_tim1.c.

References IS_TIM1_IC_POLARITY_OK, IS_TIM1_IC_PRESCALER_OK, IS_TIM1_IC_SELECTION_OK, IS_TIM1_PWMI_CHANNEL_OK, TI1_Config(), TI2_Config(), TIM1_CHANNEL_1, TIM1_ICPOLARITY_FALLING, TIM1_ICPOLARITY_RISING, TIM1_ICSELECTION_DIRECTTI, TIM1_ICSELECTION_INDIRECTTI, TIM1_SetIC1Prescaler(), and TIM1_SetIC2Prescaler().

void TIM1_SelectCOM ( FunctionalState NewState )

Selects the TIM1 peripheral Commutation event.

Parameters:
NewState new state of the Commutation event. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1161 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CR2_COMS.

void TIM1_SelectHallSensor ( FunctionalState NewState )

Enables or Disables the TIM1’s Hall sensor interface.

Parameters:
NewState new state of the TIM1 Hall sensor interface.This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 849 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CR2_TI1S.

void TIM1_SelectInputTrigger ( TIM1_TS_TypeDef TIM1_InputTriggerSource )

Selects the TIM1 Input Trigger source.

Parameters:
TIM1_InputTriggerSource specifies Input Trigger source. This parameter can be one of the following values:
  • TIM1_TS_TI1F_ED: TI1 Edge Detector
  • TIM1_TS_TI1FP1: Filtered Timer Input 1
  • TIM1_TS_TI2FP2: Filtered Timer Input 2
  • TIM1_TS_ETRF: External Trigger input
Return values:
None

Definition at line 787 of file stm8s_tim1.c.

References IS_TIM1_TRIGGER_SELECTION_OK, TIM1, and TIM1_SMCR_TS.

Referenced by TIM1_TIxExternalClockConfig().

void TIM1_SelectMasterSlaveMode ( FunctionalState NewState )

Sets or Resets the TIM1 Master/Slave Mode.

Parameters:
NewState new state of the synchronization between TIM1 and its slaves (through TRGO). This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 939 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_SMCR_MSM.

void TIM1_SelectOCxM | ( | TIM1_Channel_TypeDef | TIM1_Channel,
 |  | TIM1_OCMode_TypeDef | TIM1_OCMode
 | ) |  |

Selects the TIM1 Output Compare Mode.

This function disables the selected channel before changing the Output Compare Mode. User has to enable this channel using TIM1_CCxCmd and TIM1_CCxNCmd functions.

Parameters:
TIM1_Channel specifies the TIM1 Channel. This parameter can be one of the following values:
  • TIM1_CHANNEL_1: TIM1 Channel1
  • TIM1_CHANNEL_2: TIM1 Channel2
  • TIM1_CHANNEL_3: TIM1 Channel3
  • TIM1_CHANNEL_4: TIM1 Channel4
TIM1_OCMode specifies the TIM1 Output Compare Mode. This parameter can be one of the following values:
  • TIM1_OCMODE_TIMING
  • TIM1_OCMODE_ACTIVE
  • TIM1_OCMODE_TOGGLE
  • TIM1_OCMODE_PWM1
  • TIM1_OCMODE_PWM2
  • TIM1_FORCEDACTION_ACTIVE
  • TIM1_FORCEDACTION_INACTIVE
Return values:
None

Definition at line 1712 of file stm8s_tim1.c.

References IS_TIM1_CHANNEL_OK, IS_TIM1_OCM_OK, TIM1, TIM1_CCER1_CC1E, TIM1_CCER1_CC2E, TIM1_CCER2_CC3E, TIM1_CCER2_CC4E, TIM1_CCMR_OCM, TIM1_CHANNEL_1, TIM1_CHANNEL_2, and TIM1_CHANNEL_3.

void TIM1_SelectOnePulseMode ( TIM1_OPMode_TypeDef TIM1_OPMode )

Selects the TIM1’s One Pulse Mode.

Parameters:
TIM1_OPMode specifies the OPM Mode to be used. This parameter can be one of the following values
  • TIM1_OPMODE_SINGLE
  • TIM1_OPMODE_REPETITIVE
Return values:
None

Definition at line 873 of file stm8s_tim1.c.

References IS_TIM1_OPM_MODE_OK, TIM1, TIM1_CR1_OPM, and TIM1_OPMODE_REPETITIVE.

void TIM1_SelectOutputTrigger ( TIM1_TRGOSource_TypeDef TIM1_TRGOSource )

Selects the TIM1 Trigger Output Mode.

Parameters:
TIM1_TRGOSource specifies the Trigger Output source. This parameter can be one of the following values
  • TIM1_TRGOSOURCE_RESET
  • TIM1_TRGOSOURCE_ENABLE
  • TIM1_TRGOSOURCE_UPDATE
  • TIM1_TRGOSource_OC1
  • TIM1_TRGOSOURCE_OC1REF
  • TIM1_TRGOSOURCE_OC2REF
  • TIM1_TRGOSOURCE_OC3REF
Return values:
None

Definition at line 903 of file stm8s_tim1.c.

References IS_TIM1_TRGO_SOURCE_OK, TIM1, and TIM1_CR2_MMS.

void TIM1_SelectSlaveMode ( TIM1_SlaveMode_TypeDef TIM1_SlaveMode )

Selects the TIM1 Slave Mode.

Parameters:
TIM1_SlaveMode specifies the TIM1 Slave Mode. This parameter can be one of the following values
  • TIM1_SLAVEMODE_RESET
  • TIM1_SLAVEMODE_GATED
  • TIM1_SLAVEMODE_TRIGGER
  • TIM1_SLAVEMODE_EXTERNAL1
Return values:
None

Definition at line 923 of file stm8s_tim1.c.

References IS_TIM1_SLAVE_MODE_OK, TIM1, and TIM1_SMCR_SMS.

void TIM1_SetAutoreload ( uint16_t Autoreload )

Sets the TIM1 Autoreload Register value.

Parameters:
Autoreload specifies the Autoreload register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 1775 of file stm8s_tim1.c.

References TIM1.

void TIM1_SetCompare1 ( uint16_t Compare1 )

Sets the TIM1 Capture Compare1 Register value.

Parameters:
Compare1 specifies the Capture Compare1 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 1788 of file stm8s_tim1.c.

References TIM1.

void TIM1_SetCompare2 ( uint16_t Compare2 )

Sets the TIM1 Capture Compare2 Register value.

Parameters:
Compare2 specifies the Capture Compare2 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 1801 of file stm8s_tim1.c.

References TIM1.

void TIM1_SetCompare3 ( uint16_t Compare3 )

Sets the TIM1 Capture Compare3 Register value.

Parameters:
Compare3 specifies the Capture Compare3 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 1814 of file stm8s_tim1.c.

References TIM1.

void TIM1_SetCompare4 ( uint16_t Compare4 )

Sets the TIM1 Capture Compare4 Register value.

Parameters:
Compare4 specifies the Capture Compare4 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 1827 of file stm8s_tim1.c.

References TIM1.

void TIM1_SetCounter ( uint16_t Counter )

Sets the TIM1 Counter Register value.

Parameters:
Counter specifies the Counter register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 1762 of file stm8s_tim1.c.

References TIM1.

void TIM1_SetIC1Prescaler ( TIM1_ICPSC_TypeDef TIM1_IC1Prescaler )

Sets the TIM1 Input Capture 1 prescaler.

Parameters:
TIM1_IC1Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:
  • TIM1_ICPSC_DIV1: no prescaler
  • TIM1_ICPSC_DIV2: capture is done once every 2 events
  • TIM1_ICPSC_DIV4: capture is done once every 4 events
  • TIM1_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 1844 of file stm8s_tim1.c.

References IS_TIM1_IC_PRESCALER_OK, TIM1, and TIM1_CCMR_ICxPSC.

Referenced by TIM1_ICInit(), and TIM1_PWMIConfig().

void TIM1_SetIC2Prescaler ( TIM1_ICPSC_TypeDef TIM1_IC2Prescaler )

Sets the TIM1 Input Capture 2 prescaler.

Parameters:
TIM1_IC2Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:
  • TIM1_ICPSC_DIV1: no prescaler
  • TIM1_ICPSC_DIV2: capture is done once every 2 events
  • TIM1_ICPSC_DIV4: capture is done once every 4 events
  • TIM1_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 1864 of file stm8s_tim1.c.

References IS_TIM1_IC_PRESCALER_OK, TIM1, and TIM1_CCMR_ICxPSC.

Referenced by TIM1_ICInit(), and TIM1_PWMIConfig().

void TIM1_SetIC3Prescaler ( TIM1_ICPSC_TypeDef TIM1_IC3Prescaler )

Sets the TIM1 Input Capture 3 prescaler.

Parameters:
TIM1_IC3Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:
  • TIM1_ICPSC_DIV1: no prescaler
  • TIM1_ICPSC_DIV2: capture is done once every 2 events
  • TIM1_ICPSC_DIV4: capture is done once every 4 events
  • TIM1_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 1885 of file stm8s_tim1.c.

References IS_TIM1_IC_PRESCALER_OK, TIM1, and TIM1_CCMR_ICxPSC.

Referenced by TIM1_ICInit().

void TIM1_SetIC4Prescaler ( TIM1_ICPSC_TypeDef TIM1_IC4Prescaler )

Sets the TIM1 Input Capture 4 prescaler.

Parameters:
TIM1_IC4Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:
  • TIM1_ICPSC_DIV1: no prescaler
  • TIM1_ICPSC_DIV2: capture is done once every 2 events
  • TIM1_ICPSC_DIV4: capture is done once every 4 events
  • TIM1_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 1906 of file stm8s_tim1.c.

References IS_TIM1_IC_PRESCALER_OK, TIM1, and TIM1_CCMR_ICxPSC.

Referenced by TIM1_ICInit().

void TIM1_TimeBaseInit | ( | uint16_t | TIM1_Prescaler,
 |  | TIM1_CounterMode_TypeDef | TIM1_CounterMode,
 |  | uint16_t | TIM1_Period,
 |  | uint8_t | TIM1_RepetitionCounter
 | ) |  |

Initializes the TIM1 Time Base Unit according to the specified parameters.

Parameters:
TIM1_Prescaler | specifies the Prescaler value.
TIM1_CounterMode | specifies the counter mode from TIM1_CounterMode_TypeDef .
TIM1_Period | specifies the Period value.
TIM1_RepetitionCounter | specifies the Repetition counter value
Return values:
None

Definition at line 111 of file stm8s_tim1.c.

References IS_TIM1_COUNTER_MODE_OK, TIM1, TIM1_CR1_CMS, and TIM1_CR1_DIR.

void TIM1_TIxExternalClockConfig | ( | TIM1_TIxExternalCLK1Source_TypeDef | TIM1_TIxExternalCLKSource,
 |  | TIM1_ICPolarity_TypeDef | TIM1_ICPolarity,
 |  | uint8_t | ICFilter
 | ) |  |

Configures the TIM1 Trigger as External Clock.

Parameters:
TIM1_TIxExternalCLKSource specifies Trigger source. This parameter can be one of the following values:
  • TIM1_TIXEXTERNALCLK1SOURCE_TI1: TI1 Edge Detector
  • TIM1_TIXEXTERNALCLK1SOURCE_TI2: Filtered TIM1 Input 1
  • TIM1_TIXEXTERNALCLK1SOURCE_TI1ED: Filtered TIM1 Input 2
TIM1_ICPolarity specifies the TIx Polarity. This parameter can be:
  • TIM1_ICPOLARITY_RISING
  • TIM1_ICPOLARITY_FALLING
ICFilter specifies the filter value. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 751 of file stm8s_tim1.c.

References IS_TIM1_IC_FILTER_OK, IS_TIM1_IC_POLARITY_OK, IS_TIM1_TIXCLK_SOURCE_OK, TI1_Config(), TI2_Config(), TIM1, TIM1_ICSELECTION_DIRECTTI, TIM1_SelectInputTrigger(), TIM1_SLAVEMODE_EXTERNAL1, and TIM1_TIXEXTERNALCLK1SOURCE_TI2.

void TIM1_UpdateDisableConfig ( FunctionalState NewState )

Enables or Disables the TIM1 Update event.

Parameters:
NewState new state of the TIM1 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 803 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CR1_UDIS.

void TIM1_UpdateRequestConfig ( TIM1_UpdateSource_TypeDef TIM1_UpdateSource )

Selects the TIM1 Update Request Interrupt source.

Parameters:
TIM1_UpdateSource specifies the Update source. This parameter can be one of the following values
  • TIM1_UPDATESOURCE_REGULAR
  • TIM1_UPDATESOURCE_GLOBAL
Return values:
None

Definition at line 827 of file stm8s_tim1.c.

References IS_TIM1_UPDATE_SOURCE_OK, TIM1, TIM1_CR1_URS, and TIM1_UPDATESOURCE_GLOBAL.


STM8S/A Standard Peripherals Drivers: TIM2_Public_Functions

Functions
TIM2_Public_Functions
STM8S_StdPeriph_Driver

Functions

static void | TI1_Config (uint8_t TIM2_ICPolarity, uint8_t TIM2_ICSelection, uint8_t TIM2_ICFilter)
Configure the TI1 as Input.
static void | TI2_Config (uint8_t TIM2_ICPolarity, uint8_t TIM2_ICSelection, uint8_t TIM2_ICFilter)
Configure the TI2 as Input.
static void | TI3_Config (uint8_t TIM2_ICPolarity, uint8_t TIM2_ICSelection, uint8_t TIM2_ICFilter)
Configure the TI3 as Input.
void | TIM2_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM2 peripheral Preload register on ARR.
void | TIM2_CCxCmd (TIM2_Channel_TypeDef TIM2_Channel, FunctionalState NewState)
Enables or disables the TIM2 Capture Compare Channel x.
void | TIM2_ClearFlag (TIM2_FLAG_TypeDef TIM2_FLAG)
Clears the TIM2’s pending flags.
void | TIM2_ClearITPendingBit (TIM2_IT_TypeDef TIM2_IT)
Clears the TIM2's interrupt pending bits.
void | TIM2_Cmd (FunctionalState NewState)
Enables or disables the TIM2 peripheral.
void | TIM2_DeInit (void)
Deinitializes the TIM2 peripheral registers to their default reset values.
void | TIM2_ForcedOC1Config (TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
Forces the TIM2 Channel1 output waveform to active or inactive level.
void | TIM2_ForcedOC2Config (TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
Forces the TIM2 Channel2 output waveform to active or inactive level.
void | TIM2_ForcedOC3Config (TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
Forces the TIM2 Channel3 output waveform to active or inactive level.
void | TIM2_GenerateEvent (TIM2_EventSource_TypeDef TIM2_EventSource)
Configures the TIM2 event to be generated by software.
uint16_t | TIM2_GetCapture1 (void)
Gets the TIM2 Input Capture 1 value.
uint16_t | TIM2_GetCapture2 (void)
Gets the TIM2 Input Capture 2 value.
uint16_t | TIM2_GetCapture3 (void)
Gets the TIM2 Input Capture 3 value.
uint16_t | TIM2_GetCounter (void)
Gets the TIM2 Counter value.
FlagStatus | TIM2_GetFlagStatus (TIM2_FLAG_TypeDef TIM2_FLAG)
Checks whether the specified TIM2 flag is set or not.
ITStatus | TIM2_GetITStatus (TIM2_IT_TypeDef TIM2_IT)
Checks whether the TIM2 interrupt has occurred or not.
TIM2_Prescaler_TypeDef | TIM2_GetPrescaler (void)
Gets the TIM2 Prescaler value.
void | TIM2_ICInit (TIM2_Channel_TypeDef TIM2_Channel, TIM2_ICPolarity_TypeDef TIM2_ICPolarity, TIM2_ICSelection_TypeDef TIM2_ICSelection, TIM2_ICPSC_TypeDef TIM2_ICPrescaler, uint8_t TIM2_ICFilter)
Initializes the TIM2 peripheral according to the specified parameters.
void | TIM2_ITConfig (TIM2_IT_TypeDef TIM2_IT, FunctionalState NewState)
Enables or disables the specified TIM2 interrupts.
void | TIM2_OC1Init (TIM2_OCMode_TypeDef TIM2_OCMode, TIM2_OutputState_TypeDef TIM2_OutputState, uint16_t TIM2_Pulse, TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Initializes the TIM2 Channel1 according to the specified parameters.
void | TIM2_OC1PolarityConfig (TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Configures the TIM2 Channel 1 polarity.
void | TIM2_OC1PreloadConfig (FunctionalState NewState)
Enables or disables the TIM2 peripheral Preload Register on CCR1.
void | TIM2_OC2Init (TIM2_OCMode_TypeDef TIM2_OCMode, TIM2_OutputState_TypeDef TIM2_OutputState, uint16_t TIM2_Pulse, TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Initializes the TIM2 Channel2 according to the specified parameters.
void | TIM2_OC2PolarityConfig (TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Configures the TIM2 Channel 2 polarity.
void | TIM2_OC2PreloadConfig (FunctionalState NewState)
Enables or disables the TIM2 peripheral Preload Register on CCR2.
void | TIM2_OC3Init (TIM2_OCMode_TypeDef TIM2_OCMode, TIM2_OutputState_TypeDef TIM2_OutputState, uint16_t TIM2_Pulse, TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Initializes the TIM2 Channel3 according to the specified parameters.
void | TIM2_OC3PolarityConfig (TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Configures the TIM2 Channel 3 polarity.
void | TIM2_OC3PreloadConfig (FunctionalState NewState)
Enables or disables the TIM2 peripheral Preload Register on CCR3.
void | TIM2_PrescalerConfig (TIM2_Prescaler_TypeDef Prescaler, TIM2_PSCReloadMode_TypeDef TIM2_PSCReloadMode)
Configures the TIM2 Prescaler.
void | TIM2_PWMIConfig (TIM2_Channel_TypeDef TIM2_Channel, TIM2_ICPolarity_TypeDef TIM2_ICPolarity, TIM2_ICSelection_TypeDef TIM2_ICSelection, TIM2_ICPSC_TypeDef TIM2_ICPrescaler, uint8_t TIM2_ICFilter)
Configures the TIM2 peripheral in PWM Input Mode according to the specified parameters.
void | TIM2_SelectOCxM (TIM2_Channel_TypeDef TIM2_Channel, TIM2_OCMode_TypeDef TIM2_OCMode)
Selects the TIM2 Output Compare Mode.
void | TIM2_SelectOnePulseMode (TIM2_OPMode_TypeDef TIM2_OPMode)
Selects the TIM2’s One Pulse Mode.
void | TIM2_SetAutoreload (uint16_t Autoreload)
Sets the TIM2 Autoreload Register value.
void | TIM2_SetCompare1 (uint16_t Compare1)
Sets the TIM2 Capture Compare1 Register value.
void | TIM2_SetCompare2 (uint16_t Compare2)
Sets the TIM2 Capture Compare2 Register value.
void | TIM2_SetCompare3 (uint16_t Compare3)
Sets the TIM2 Capture Compare3 Register value.
void | TIM2_SetCounter (uint16_t Counter)
Sets the TIM2 Counter Register value.
void | TIM2_SetIC1Prescaler (TIM2_ICPSC_TypeDef TIM2_IC1Prescaler)
Sets the TIM2 Input Capture 1 Prescaler.
void | TIM2_SetIC2Prescaler (TIM2_ICPSC_TypeDef TIM2_IC2Prescaler)
Sets the TIM2 Input Capture 2 prescaler.
void | TIM2_SetIC3Prescaler (TIM2_ICPSC_TypeDef TIM2_IC3Prescaler)
Sets the TIM2 Input Capture 3 prescaler.
void | TIM2_TimeBaseInit (TIM2_Prescaler_TypeDef TIM2_Prescaler, uint16_t TIM2_Period)
Initializes the TIM2 Time Base Unit according to the specified parameters.
void | TIM2_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM2 Update event.
void | TIM2_UpdateRequestConfig (TIM2_UpdateSource_TypeDef TIM2_UpdateSource)
Selects the TIM2 Update Request Interrupt source.

Function Documentation

static void TI1_Config | ( | uint8_t | TIM2_ICPolarity,
 |  | uint8_t | TIM2_ICSelection,
 |  | uint8_t | TIM2_ICFilter
 | ) |  | [static]

Configure the TI1 as Input.

Parameters:
TIM2_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM2_ICPOLARITY_FALLING
  • TIM2_ICPOLARITY_RISING
TIM2_ICSelection specifies the input to be used. This parameter can be one of the following values:
  • TIM2_ICSELECTION_DIRECTTI: TIM2 Input 1 is selected to be connected to IC1.
  • TIM2_ICSELECTION_INDIRECTTI: TIM2 Input 1 is selected to be connected to IC2.
TIM2_ICFilter Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 1181 of file stm8s_tim2.c.

References TIM2_CCER1_CC1E, TIM2_CCER1_CC1P, TIM2_CCMR_CCxS, TIM2_CCMR_ICxF, and TIM2_ICPOLARITY_RISING.

Referenced by TIM2_ICInit(), and TIM2_PWMIConfig().

static void TI2_Config | ( | uint8_t | TIM2_ICPolarity,
 |  | uint8_t | TIM2_ICSelection,
 |  | uint8_t | TIM2_ICFilter
 | ) |  | [static]

Configure the TI2 as Input.

Parameters:
TIM2_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM2_ICPOLARITY_FALLING
  • TIM2_ICPOLARITY_RISING
TIM2_ICSelection specifies the input to be used. This parameter can be one of the following values:
  • TIM2_ICSELECTION_DIRECTTI: TIM2 Input 2 is selected to be connected to IC2.
  • TIM2_ICSELECTION_INDIRECTTI: TIM2 Input 2 is selected to be connected to IC1.
TIM2_ICFilter Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 1221 of file stm8s_tim2.c.

References TIM2_CCER1_CC2E, TIM2_CCER1_CC2P, TIM2_CCMR_CCxS, TIM2_CCMR_ICxF, and TIM2_ICPOLARITY_RISING.

Referenced by TIM2_ICInit(), and TIM2_PWMIConfig().

static void TI3_Config | ( | uint8_t | TIM2_ICPolarity,
 |  | uint8_t | TIM2_ICSelection,
 |  | uint8_t | TIM2_ICFilter
 | ) |  | [static]

Configure the TI3 as Input.

Parameters:
TIM2_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM2_ICPOLARITY_FALLING
  • TIM2_ICPOLARITY_RISING
TIM2_ICSelection specifies the input to be used. This parameter can be one of the following values:
  • TIM2_ICSELECTION_DIRECTTI: TIM2 Input 3 is selected to be connected to IC3.
TIM2_ICFilter Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 1261 of file stm8s_tim2.c.

References TIM2_CCER2_CC3E, TIM2_CCER2_CC3P, TIM2_CCMR_CCxS, TIM2_CCMR_ICxF, and TIM2_ICPOLARITY_RISING.

Referenced by TIM2_ICInit().

void TIM2_ARRPreloadConfig ( FunctionalState NewState )

Enables or disables TIM2 peripheral Preload register on ARR.

Parameters:
NewState new state of the TIM2 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 561 of file stm8s_tim2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM2_CR1_ARPE.

void TIM2_CCxCmd | ( | TIM2_Channel_TypeDef | TIM2_Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the TIM2 Capture Compare Channel x.

Parameters:
TIM2_Channel specifies the TIM2 Channel. This parameter can be one of the following values:
  • TIM2_CHANNEL_1: TIM2 Channel1
  • TIM2_CHANNEL_2: TIM2 Channel2
  • TIM2_CHANNEL_3: TIM2 Channel3
NewState specifies the TIM2 Channel CCxE bit new state. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 745 of file stm8s_tim2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, IS_TIM2_CHANNEL_OK, TIM2_CCER1_CC1E, TIM2_CCER1_CC2E, TIM2_CCER2_CC3E, TIM2_CHANNEL_1, and TIM2_CHANNEL_2.

void TIM2_ClearFlag ( TIM2_FLAG_TypeDef TIM2_FLAG )

Clears the TIM2’s pending flags.

Parameters:
TIM2_FLAG specifies the flag to clear. This parameter can be one of the following values:
  • TIM2_FLAG_UPDATE: TIM2 update Flag
  • TIM2_FLAG_CC1: TIM2 Capture Compare 1 Flag
  • TIM2_FLAG_CC2: TIM2 Capture Compare 2 Flag
  • TIM2_FLAG_CC3: TIM2 Capture Compare 3 Flag
  • TIM2_FLAG_CC1OF: TIM2 Capture Compare 1 over capture Flag
  • TIM2_FLAG_CC2OF: TIM2 Capture Compare 2 over capture Flag
  • TIM2_FLAG_CC3OF: TIM2 Capture Compare 3 over capture Flag
Return values:
None.

Definition at line 1103 of file stm8s_tim2.c.

References IS_TIM2_CLEAR_FLAG_OK.

void TIM2_ClearITPendingBit ( TIM2_IT_TypeDef TIM2_IT )

Clears the TIM2's interrupt pending bits.

Parameters:
TIM2_IT specifies the pending bit to clear. This parameter can be one of the following values:
  • TIM2_IT_UPDATE: TIM2 update Interrupt source
  • TIM2_IT_CC1: TIM2 Capture Compare 1 Interrupt source
  • TIM2_IT_CC2: TIM2 Capture Compare 2 Interrupt source
  • TIM2_IT_CC3: TIM2 Capture Compare 3 Interrupt source
Return values:
None.

Definition at line 1156 of file stm8s_tim2.c.

References IS_TIM2_IT_OK.

void TIM2_Cmd ( FunctionalState NewState )

Enables or disables the TIM2 peripheral.

Parameters:
NewState new state of the TIM2 peripheral. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 339 of file stm8s_tim2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM2_CR1_CEN.

void TIM2_DeInit ( void )

Deinitializes the TIM2 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 52 of file stm8s_tim2.c.

References TIM2_ARRH_RESET_VALUE, TIM2_ARRL_RESET_VALUE, TIM2_CCER1_RESET_VALUE, TIM2_CCER2_RESET_VALUE, TIM2_CCMR1_RESET_VALUE, TIM2_CCMR2_RESET_VALUE, TIM2_CCMR3_RESET_VALUE, TIM2_CCR1H_RESET_VALUE, TIM2_CCR1L_RESET_VALUE, TIM2_CCR2H_RESET_VALUE, TIM2_CCR2L_RESET_VALUE, TIM2_CCR3H_RESET_VALUE, TIM2_CCR3L_RESET_VALUE, TIM2_CNTRH_RESET_VALUE, TIM2_CNTRL_RESET_VALUE, TIM2_CR1_RESET_VALUE, TIM2_IER_RESET_VALUE, TIM2_PSCR_RESET_VALUE, TIM2_SR1_RESET_VALUE, and TIM2_SR2_RESET_VALUE.

void TIM2_ForcedOC1Config ( TIM2_ForcedAction_TypeDef TIM2_ForcedAction )

Forces the TIM2 Channel1 output waveform to active or inactive level.

Parameters:
TIM2_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:
  • TIM2_FORCEDACTION_ACTIVE: Force active level on OC1REF
  • TIM2_FORCEDACTION_INACTIVE: Force inactive level on OC1REF.
Return values:
None

Definition at line 507 of file stm8s_tim2.c.

References IS_TIM2_FORCED_ACTION_OK, and TIM2_CCMR_OCM.

void TIM2_ForcedOC2Config ( TIM2_ForcedAction_TypeDef TIM2_ForcedAction )

Forces the TIM2 Channel2 output waveform to active or inactive level.

Parameters:
TIM2_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:
  • TIM2_FORCEDACTION_ACTIVE: Force active level on OC2REF
  • TIM2_FORCEDACTION_INACTIVE: Force inactive level on OC2REF.
Return values:
None

Definition at line 526 of file stm8s_tim2.c.

References IS_TIM2_FORCED_ACTION_OK, and TIM2_CCMR_OCM.

void TIM2_ForcedOC3Config ( TIM2_ForcedAction_TypeDef TIM2_ForcedAction )

Forces the TIM2 Channel3 output waveform to active or inactive level.

Parameters:
TIM2_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:
  • TIM2_FORCEDACTION_ACTIVE: Force active level on OC3REF
  • TIM2_FORCEDACTION_INACTIVE: Force inactive level on OC3REF.
Return values:
None

Definition at line 545 of file stm8s_tim2.c.

References IS_TIM2_FORCED_ACTION_OK, and TIM2_CCMR_OCM.

void TIM2_GenerateEvent ( TIM2_EventSource_TypeDef TIM2_EventSource )

Configures the TIM2 event to be generated by software.

Parameters:
TIM2_EventSource specifies the event source. This parameter can be one of the following values:
  • TIM2_EVENTSOURCE_UPDATE: TIM2 update Event source
  • TIM2_EVENTSOURCE_CC1: TIM2 Capture Compare 1 Event source
  • TIM2_EVENTSOURCE_CC2: TIM2 Capture Compare 2 Event source
  • TIM2_EVENTSOURCE_CC3: TIM2 Capture Compare 3 Event source
Return values:
None

Definition at line 653 of file stm8s_tim2.c.

References IS_TIM2_EVENT_SOURCE_OK.

uint16_t TIM2_GetCapture1 ( void )

Gets the TIM2 Input Capture 1 value.

Parameters:
None
Return values:
Capture Compare 1 Register value.

Definition at line 975 of file stm8s_tim2.c.

uint16_t TIM2_GetCapture2 ( void )

Gets the TIM2 Input Capture 2 value.

Parameters:
None
Return values:
Capture Compare 2 Register value.

Definition at line 995 of file stm8s_tim2.c.

uint16_t TIM2_GetCapture3 ( void )

Gets the TIM2 Input Capture 3 value.

Parameters:
None
Return values:
Capture Compare 3 Register value.

Definition at line 1015 of file stm8s_tim2.c.

uint16_t TIM2_GetCounter ( void )

Gets the TIM2 Counter value.

Parameters:
None
Return values:
Counter Register value.

Definition at line 1035 of file stm8s_tim2.c.

FlagStatus TIM2_GetFlagStatus ( TIM2_FLAG_TypeDef TIM2_FLAG )

Checks whether the specified TIM2 flag is set or not.

Parameters:
TIM2_FLAG specifies the flag to check. This parameter can be one of the following values:
  • TIM2_FLAG_UPDATE: TIM2 update Flag
  • TIM2_FLAG_CC1: TIM2 Capture Compare 1 Flag
  • TIM2_FLAG_CC2: TIM2 Capture Compare 2 Flag
  • TIM2_FLAG_CC3: TIM2 Capture Compare 3 Flag
  • TIM2_FLAG_CC1OF: TIM2 Capture Compare 1 over capture Flag
  • TIM2_FLAG_CC2OF: TIM2 Capture Compare 2 over capture Flag
  • TIM2_FLAG_CC3OF: TIM2 Capture Compare 3 over capture Flag
Return values:
FlagStatus The new state of TIM2_FLAG (SET or RESET).

Definition at line 1068 of file stm8s_tim2.c.

References IS_TIM2_GET_FLAG_OK, RESET, and SET.

ITStatus TIM2_GetITStatus ( TIM2_IT_TypeDef TIM2_IT )

Checks whether the TIM2 interrupt has occurred or not.

Parameters:
TIM2_IT specifies the TIM2 interrupt source to check. This parameter can be one of the following values:
  • TIM2_IT_UPDATE: TIM2 update Interrupt source
  • TIM2_IT_CC1: TIM2 Capture Compare 1 Interrupt source
  • TIM2_IT_CC2: TIM2 Capture Compare 2 Interrupt source
  • TIM2_IT_CC3: TIM2 Capture Compare 3 Interrupt source
Return values:
ITStatus The new state of the TIM2_IT(SET or RESET).

Definition at line 1123 of file stm8s_tim2.c.

References IS_TIM2_GET_IT_OK, RESET, and SET.

TIM2_Prescaler_TypeDef TIM2_GetPrescaler ( void )

Gets the TIM2 Prescaler value.

Parameters:
None
Return values:
Prescaler Register configuration value TIM2_Prescaler_TypeDef.

Definition at line 1049 of file stm8s_tim2.c.

void TIM2_ICInit | ( | TIM2_Channel_TypeDef | TIM2_Channel,
 |  | TIM2_ICPolarity_TypeDef | TIM2_ICPolarity,
 |  | TIM2_ICSelection_TypeDef | TIM2_ICSelection,
 |  | TIM2_ICPSC_TypeDef | TIM2_ICPrescaler,
 |  | uint8_t | TIM2_ICFilter
 | ) |  |

Initializes the TIM2 peripheral according to the specified parameters.

Parameters:
TIM2_Channel | specifies the Input Capture Channel from TIM2_Channel_TypeDef.
TIM2_ICPolarity | specifies the Input Capture Polarity from TIM2_ICPolarity_TypeDef.
TIM2_ICSelection | specifies the Input Capture Selection from TIM2_ICSelection_TypeDef.
TIM2_ICPrescaler | specifies the Input Capture Prescaler from TIM2_ICPSC_TypeDef.
TIM2_ICFilter | specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
Return values:
None

Definition at line 212 of file stm8s_tim2.c.

References IS_TIM2_CHANNEL_OK, IS_TIM2_IC_FILTER_OK, IS_TIM2_IC_POLARITY_OK, IS_TIM2_IC_PRESCALER_OK, IS_TIM2_IC_SELECTION_OK, TI1_Config(), TI2_Config(), TI3_Config(), TIM2_CHANNEL_1, TIM2_CHANNEL_2, TIM2_SetIC1Prescaler(), TIM2_SetIC2Prescaler(), and TIM2_SetIC3Prescaler().

void TIM2_ITConfig | ( | TIM2_IT_TypeDef | TIM2_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified TIM2 interrupts.

Parameters:
NewState | new state of the TIM2 peripheral. This parameter can be: ENABLE or DISABLE.
TIM2_IT specifies the TIM2 interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:
  • TIM2_IT_UPDATE: TIM2 update Interrupt source
  • TIM2_IT_CC1: TIM2 Capture Compare 1 Interrupt source
  • TIM2_IT_CC2: TIM2 Capture Compare 2 Interrupt source
  • TIM2_IT_CC3: TIM2 Capture Compare 3 Interrupt source
NewState | new state of the TIM2 peripheral.
Return values:
None

Definition at line 368 of file stm8s_tim2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and IS_TIM2_IT_OK.

void TIM2_OC1Init | ( | TIM2_OCMode_TypeDef | TIM2_OCMode,
 |  | TIM2_OutputState_TypeDef | TIM2_OutputState,
 |  | uint16_t | TIM2_Pulse,
 |  | TIM2_OCPolarity_TypeDef | TIM2_OCPolarity
 | ) |  |

Initializes the TIM2 Channel1 according to the specified parameters.

Parameters:
TIM2_OCMode | specifies the Output Compare mode from TIM2_OCMode_TypeDef.
TIM2_OutputState | specifies the Output State from TIM2_OutputState_TypeDef.
TIM2_Pulse | specifies the Pulse width value.
TIM2_OCPolarity | specifies the Output Compare Polarity from TIM2_OCPolarity_TypeDef.
Return values:
None

Definition at line 108 of file stm8s_tim2.c.

References IS_TIM2_OC_MODE_OK, IS_TIM2_OC_POLARITY_OK, IS_TIM2_OUTPUT_STATE_OK, TIM2_CCER1_CC1E, TIM2_CCER1_CC1P, and TIM2_CCMR_OCM.

void TIM2_OC1PolarityConfig ( TIM2_OCPolarity_TypeDef TIM2_OCPolarity )

Configures the TIM2 Channel 1 polarity.

Parameters:
TIM2_OCPolarity specifies the OC1 Polarity. This parameter can be one of the following values:
  • TIM2_OCPOLARITY_LOW: Output Compare active low
  • TIM2_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 670 of file stm8s_tim2.c.

References IS_TIM2_OC_POLARITY_OK, TIM2_CCER1_CC1P, and TIM2_OCPOLARITY_HIGH.

void TIM2_OC1PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM2 peripheral Preload Register on CCR1.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 583 of file stm8s_tim2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM2_CCMR_OCxPE.

void TIM2_OC2Init | ( | TIM2_OCMode_TypeDef | TIM2_OCMode,
 |  | TIM2_OutputState_TypeDef | TIM2_OutputState,
 |  | uint16_t | TIM2_Pulse,
 |  | TIM2_OCPolarity_TypeDef | TIM2_OCPolarity
 | ) |  |

Initializes the TIM2 Channel2 according to the specified parameters.

Parameters:
TIM2_OCMode | specifies the Output Compare mode from TIM2_OCMode_TypeDef.
TIM2_OutputState | specifies the Output State from TIM2_OutputState_TypeDef.
TIM2_Pulse | specifies the Pulse width value.
TIM2_OCPolarity | specifies the Output Compare Polarity from TIM2_OCPolarity_TypeDef.
Return values:
None

Definition at line 142 of file stm8s_tim2.c.

References IS_TIM2_OC_MODE_OK, IS_TIM2_OC_POLARITY_OK, IS_TIM2_OUTPUT_STATE_OK, TIM2_CCER1_CC2E, TIM2_CCER1_CC2P, and TIM2_CCMR_OCM.

void TIM2_OC2PolarityConfig ( TIM2_OCPolarity_TypeDef TIM2_OCPolarity )

Configures the TIM2 Channel 2 polarity.

Parameters:
TIM2_OCPolarity specifies the OC2 Polarity. This parameter can be one of the following values:
  • TIM2_OCPOLARITY_LOW: Output Compare active low
  • TIM2_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 694 of file stm8s_tim2.c.

References IS_TIM2_OC_POLARITY_OK, TIM2_CCER1_CC2P, and TIM2_OCPOLARITY_HIGH.

void TIM2_OC2PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM2 peripheral Preload Register on CCR2.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 605 of file stm8s_tim2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM2_CCMR_OCxPE.

void TIM2_OC3Init | ( | TIM2_OCMode_TypeDef | TIM2_OCMode,
 |  | TIM2_OutputState_TypeDef | TIM2_OutputState,
 |  | uint16_t | TIM2_Pulse,
 |  | TIM2_OCPolarity_TypeDef | TIM2_OCPolarity
 | ) |  |

Initializes the TIM2 Channel3 according to the specified parameters.

Parameters:
TIM2_OCMode | specifies the Output Compare mode from TIM2_OCMode_TypeDef.
TIM2_OutputState | specifies the Output State from TIM2_OutputState_TypeDef.
TIM2_Pulse | specifies the Pulse width value.
TIM2_OCPolarity | specifies the Output Compare Polarity from TIM2_OCPolarity_TypeDef.
Return values:
None

Definition at line 179 of file stm8s_tim2.c.

References IS_TIM2_OC_MODE_OK, IS_TIM2_OC_POLARITY_OK, IS_TIM2_OUTPUT_STATE_OK, TIM2_CCER2_CC3E, TIM2_CCER2_CC3P, and TIM2_CCMR_OCM.

void TIM2_OC3PolarityConfig ( TIM2_OCPolarity_TypeDef TIM2_OCPolarity )

Configures the TIM2 Channel 3 polarity.

Parameters:
TIM2_OCPolarity specifies the OC3 Polarity. This parameter can be one of the following values:
  • TIM2_OCPOLARITY_LOW: Output Compare active low
  • TIM2_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 718 of file stm8s_tim2.c.

References IS_TIM2_OC_POLARITY_OK, TIM2_CCER2_CC3P, and TIM2_OCPOLARITY_HIGH.

void TIM2_OC3PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM2 peripheral Preload Register on CCR3.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 627 of file stm8s_tim2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM2_CCMR_OCxPE.

void TIM2_PrescalerConfig | ( | TIM2_Prescaler_TypeDef | Prescaler,
 |  | TIM2_PSCReloadMode_TypeDef | TIM2_PSCReloadMode
 | ) |  |

Configures the TIM2 Prescaler.

Parameters:
Prescaler specifies the Prescaler Register value This parameter can be one of the following values
  • TIM2_PRESCALER_1
  • TIM2_PRESCALER_2
  • TIM2_PRESCALER_4
  • TIM2_PRESCALER_8
  • TIM2_PRESCALER_16
  • TIM2_PRESCALER_32
  • TIM2_PRESCALER_64
  • TIM2_PRESCALER_128
  • TIM2_PRESCALER_256
  • TIM2_PRESCALER_512
  • TIM2_PRESCALER_1024
  • TIM2_PRESCALER_2048
  • TIM2_PRESCALER_4096
  • TIM2_PRESCALER_8192
  • TIM2_PRESCALER_16384
  • TIM2_PRESCALER_32768
TIM2_PSCReloadMode specifies the TIM2 Prescaler Reload mode. This parameter can be one of the following values
  • TIM2_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded immediately.
  • TIM2_PSCRELOADMODE_UPDATE: The Prescaler is loaded at the update event.
Return values:
None

Definition at line 484 of file stm8s_tim2.c.

References IS_TIM2_PRESCALER_OK, and IS_TIM2_PRESCALER_RELOAD_OK.

void TIM2_PWMIConfig | ( | TIM2_Channel_TypeDef | TIM2_Channel,
 |  | TIM2_ICPolarity_TypeDef | TIM2_ICPolarity,
 |  | TIM2_ICSelection_TypeDef | TIM2_ICSelection,
 |  | TIM2_ICPSC_TypeDef | TIM2_ICPrescaler,
 |  | uint8_t | TIM2_ICFilter
 | ) |  |

Configures the TIM2 peripheral in PWM Input Mode according to the specified parameters.

Parameters:
TIM2_Channel | specifies the Input Capture Channel from TIM2_Channel_TypeDef.
TIM2_ICPolarity | specifies the Input Capture Polarity from TIM2_ICPolarity_TypeDef.
TIM2_ICSelection | specifies the Input Capture Selection from TIM2_ICSelection_TypeDef.
TIM2_ICPrescaler | specifies the Input Capture Prescaler from TIM2_ICPSC_TypeDef.
TIM2_ICFilter | specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
Return values:
None

Definition at line 266 of file stm8s_tim2.c.

References IS_TIM2_IC_POLARITY_OK, IS_TIM2_IC_PRESCALER_OK, IS_TIM2_IC_SELECTION_OK, IS_TIM2_PWMI_CHANNEL_OK, TI1_Config(), TI2_Config(), TIM2_CHANNEL_1, TIM2_ICPOLARITY_FALLING, TIM2_ICPOLARITY_RISING, TIM2_ICSELECTION_DIRECTTI, TIM2_ICSELECTION_INDIRECTTI, TIM2_SetIC1Prescaler(), and TIM2_SetIC2Prescaler().

void TIM2_SelectOCxM | ( | TIM2_Channel_TypeDef | TIM2_Channel,
 |  | TIM2_OCMode_TypeDef | TIM2_OCMode
 | ) |  |

Selects the TIM2 Output Compare Mode.

This function disables the selected channel before changing the Output Compare Mode. User has to enable this channel using TIM2_CCxCmd and TIM2_CCxNCmd functions.

Parameters:
TIM2_Channel specifies the TIM2 Channel. This parameter can be one of the following values:
  • TIM2_CHANNEL_1: TIM2 Channel1
  • TIM2_CHANNEL_2: TIM2 Channel2
  • TIM2_CHANNEL_3: TIM2 Channel3
TIM2_OCMode specifies the TIM2 Output Compare Mode. This parameter can be one of the following values:
  • TIM2_OCMODE_TIMING
  • TIM2_OCMODE_ACTIVE
  • TIM2_OCMODE_TOGGLE
  • TIM2_OCMODE_PWM1
  • TIM2_OCMODE_PWM2
  • TIM2_FORCEDACTION_ACTIVE
  • TIM2_FORCEDACTION_INACTIVE
Return values:
None

Definition at line 810 of file stm8s_tim2.c.

References IS_TIM2_CHANNEL_OK, IS_TIM2_OCM_OK, TIM2_CCER1_CC1E, TIM2_CCER1_CC2E, TIM2_CCER2_CC3E, TIM2_CCMR_OCM, TIM2_CHANNEL_1, and TIM2_CHANNEL_2.

void TIM2_SelectOnePulseMode ( TIM2_OPMode_TypeDef TIM2_OPMode )

Selects the TIM2’s One Pulse Mode.

Parameters:
TIM2_OPMode specifies the OPM Mode to be used. This parameter can be one of the following values
  • TIM2_OPMODE_SINGLE
  • TIM2_OPMODE_REPETITIVE
Return values:
None

Definition at line 440 of file stm8s_tim2.c.

References IS_TIM2_OPM_MODE_OK, TIM2_CR1_OPM, and TIM2_OPMODE_REPETITIVE.

void TIM2_SetAutoreload ( uint16_t Autoreload )

Sets the TIM2 Autoreload Register value.

Parameters:
Autoreload specifies the Autoreload register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 864 of file stm8s_tim2.c.

void TIM2_SetCompare1 ( uint16_t Compare1 )

Sets the TIM2 Capture Compare1 Register value.

Parameters:
Compare1 specifies the Capture Compare1 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 877 of file stm8s_tim2.c.

void TIM2_SetCompare2 ( uint16_t Compare2 )

Sets the TIM2 Capture Compare2 Register value.

Parameters:
Compare2 specifies the Capture Compare2 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 890 of file stm8s_tim2.c.

void TIM2_SetCompare3 ( uint16_t Compare3 )

Sets the TIM2 Capture Compare3 Register value.

Parameters:
Compare3 specifies the Capture Compare3 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 903 of file stm8s_tim2.c.

void TIM2_SetCounter ( uint16_t Counter )

Sets the TIM2 Counter Register value.

Parameters:
Counter specifies the Counter register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 851 of file stm8s_tim2.c.

void TIM2_SetIC1Prescaler ( TIM2_ICPSC_TypeDef TIM2_IC1Prescaler )

Sets the TIM2 Input Capture 1 Prescaler.

Parameters:
TIM2_IC1Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:
  • TIM2_ICPSC_DIV1: no prescaler
  • TIM2_ICPSC_DIV2: capture is done once every 2 events
  • TIM2_ICPSC_DIV4: capture is done once every 4 events
  • TIM2_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 920 of file stm8s_tim2.c.

References IS_TIM2_IC_PRESCALER_OK, and TIM2_CCMR_ICxPSC.

Referenced by TIM2_ICInit(), and TIM2_PWMIConfig().

void TIM2_SetIC2Prescaler ( TIM2_ICPSC_TypeDef TIM2_IC2Prescaler )

Sets the TIM2 Input Capture 2 prescaler.

Parameters:
TIM2_IC2Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:
  • TIM2_ICPSC_DIV1: no prescaler
  • TIM2_ICPSC_DIV2: capture is done once every 2 events
  • TIM2_ICPSC_DIV4: capture is done once every 4 events
  • TIM2_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 940 of file stm8s_tim2.c.

References IS_TIM2_IC_PRESCALER_OK, and TIM2_CCMR_ICxPSC.

Referenced by TIM2_ICInit(), and TIM2_PWMIConfig().

void TIM2_SetIC3Prescaler ( TIM2_ICPSC_TypeDef TIM2_IC3Prescaler )

Sets the TIM2 Input Capture 3 prescaler.

Parameters:
TIM2_IC3Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:
  • TIM2_ICPSC_DIV1: no prescaler
  • TIM2_ICPSC_DIV2: capture is done once every 2 events
  • TIM2_ICPSC_DIV4: capture is done once every 4 events
  • TIM2_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 960 of file stm8s_tim2.c.

References IS_TIM2_IC_PRESCALER_OK, and TIM2_CCMR_ICxPSC.

Referenced by TIM2_ICInit().

void TIM2_TimeBaseInit | ( | TIM2_Prescaler_TypeDef | TIM2_Prescaler,
 |  | uint16_t | TIM2_Period
 | ) |  |

Initializes the TIM2 Time Base Unit according to the specified parameters.

Parameters:
TIM2_Prescaler | specifies the Prescaler from TIM2_Prescaler_TypeDef.
TIM2_Period | specifies the Period value.
Return values:
None

Definition at line 89 of file stm8s_tim2.c.

void TIM2_UpdateDisableConfig ( FunctionalState NewState )

Enables or Disables the TIM2 Update event.

Parameters:
NewState new state of the TIM2 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 392 of file stm8s_tim2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM2_CR1_UDIS.

void TIM2_UpdateRequestConfig ( TIM2_UpdateSource_TypeDef TIM2_UpdateSource )

Selects the TIM2 Update Request Interrupt source.

Parameters:
TIM2_UpdateSource specifies the Update source. This parameter can be one of the following values
  • TIM2_UPDATESOURCE_REGULAR
  • TIM2_UPDATESOURCE_GLOBAL
Return values:
None

Definition at line 416 of file stm8s_tim2.c.

References IS_TIM2_UPDATE_SOURCE_OK, TIM2_CR1_URS, and TIM2_UPDATESOURCE_GLOBAL.


STM8S/A Standard Peripherals Drivers: TIM3_Public_Functions

Functions
TIM3_Public_Functions
STM8S_StdPeriph_Driver

Functions

static void | TI1_Config (uint8_t TIM3_ICPolarity, uint8_t TIM3_ICSelection, uint8_t TIM3_ICFilter)
Configure the TI1 as Input.
static void | TI2_Config (uint8_t TIM3_ICPolarity, uint8_t TIM3_ICSelection, uint8_t TIM3_ICFilter)
Configure the TI2 as Input.
void | TIM3_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM3 peripheral Preload register on ARR.
void | TIM3_CCxCmd (TIM3_Channel_TypeDef TIM3_Channel, FunctionalState NewState)
Enables or disables the TIM3 Capture Compare Channel x.
void | TIM3_ClearFlag (TIM3_FLAG_TypeDef TIM3_FLAG)
Clears the TIM3’s pending flags.
void | TIM3_ClearITPendingBit (TIM3_IT_TypeDef TIM3_IT)
Clears the TIM3's interrupt pending bits.
void | TIM3_Cmd (FunctionalState NewState)
Enables or disables the TIM3 peripheral.
void | TIM3_DeInit (void)
Deinitializes the TIM3 peripheral registers to their default reset values.
void | TIM3_ForcedOC1Config (TIM3_ForcedAction_TypeDef TIM3_ForcedAction)
Forces the TIM3 Channel1 output waveform to active or inactive level.
void | TIM3_ForcedOC2Config (TIM3_ForcedAction_TypeDef TIM3_ForcedAction)
Forces the TIM3 Channel2 output waveform to active or inactive level.
void | TIM3_GenerateEvent (TIM3_EventSource_TypeDef TIM3_EventSource)
Configures the TIM3 event to be generated by software.
uint16_t | TIM3_GetCapture1 (void)
Gets the TIM3 Input Capture 1 value.
uint16_t | TIM3_GetCapture2 (void)
Gets the TIM3 Input Capture 2 value.
uint16_t | TIM3_GetCounter (void)
Gets the TIM3 Counter value.
FlagStatus | TIM3_GetFlagStatus (TIM3_FLAG_TypeDef TIM3_FLAG)
Checks whether the specified TIM3 flag is set or not.
ITStatus | TIM3_GetITStatus (TIM3_IT_TypeDef TIM3_IT)
Checks whether the TIM3 interrupt has occurred or not.
TIM3_Prescaler_TypeDef | TIM3_GetPrescaler (void)
Gets the TIM3 Prescaler value.
void | TIM3_ICInit (TIM3_Channel_TypeDef TIM3_Channel, TIM3_ICPolarity_TypeDef TIM3_ICPolarity, TIM3_ICSelection_TypeDef TIM3_ICSelection, TIM3_ICPSC_TypeDef TIM3_ICPrescaler, uint8_t TIM3_ICFilter)
Initializes the TIM3 peripheral according to the specified parameters.
void | TIM3_ITConfig (TIM3_IT_TypeDef TIM3_IT, FunctionalState NewState)
Enables or disables the specified TIM3 interrupts.
void | TIM3_OC1Init (TIM3_OCMode_TypeDef TIM3_OCMode, TIM3_OutputState_TypeDef TIM3_OutputState, uint16_t TIM3_Pulse, TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
Initializes the TIM3 Channel1 according to the specified parameters.
void | TIM3_OC1PolarityConfig (TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
Configures the TIM3 Channel 1 polarity.
void | TIM3_OC1PreloadConfig (FunctionalState NewState)
Enables or disables the TIM3 peripheral Preload Register on CCR1.
void | TIM3_OC2Init (TIM3_OCMode_TypeDef TIM3_OCMode, TIM3_OutputState_TypeDef TIM3_OutputState, uint16_t TIM3_Pulse, TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
Initializes the TIM3 Channel2 according to the specified parameters.
void | TIM3_OC2PolarityConfig (TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
Configures the TIM3 Channel 2 polarity.
void | TIM3_OC2PreloadConfig (FunctionalState NewState)
Enables or disables the TIM3 peripheral Preload Register on CCR2.
void | TIM3_PrescalerConfig (TIM3_Prescaler_TypeDef Prescaler, TIM3_PSCReloadMode_TypeDef TIM3_PSCReloadMode)
Configures the TIM3 Prescaler.
void | TIM3_PWMIConfig (TIM3_Channel_TypeDef TIM3_Channel, TIM3_ICPolarity_TypeDef TIM3_ICPolarity, TIM3_ICSelection_TypeDef TIM3_ICSelection, TIM3_ICPSC_TypeDef TIM3_ICPrescaler, uint8_t TIM3_ICFilter)
Configures the TIM3 peripheral in PWM Input Mode according to the specified parameters.
void | TIM3_SelectOCxM (TIM3_Channel_TypeDef TIM3_Channel, TIM3_OCMode_TypeDef TIM3_OCMode)
Selects the TIM3 Output Compare Mode.
void | TIM3_SelectOnePulseMode (TIM3_OPMode_TypeDef TIM3_OPMode)
Selects the TIM3’s One Pulse Mode.
void | TIM3_SetAutoreload (uint16_t Autoreload)
Sets the TIM3 Autoreload Register value.
void | TIM3_SetCompare1 (uint16_t Compare1)
Sets the TIM3 Capture Compare1 Register value.
void | TIM3_SetCompare2 (uint16_t Compare2)
Sets the TIM3 Capture Compare2 Register value.
void | TIM3_SetCounter (uint16_t Counter)
Sets the TIM3 Counter Register value.
void | TIM3_SetIC1Prescaler (TIM3_ICPSC_TypeDef TIM3_IC1Prescaler)
Sets the TIM3 Input Capture 1 prescaler.
void | TIM3_SetIC2Prescaler (TIM3_ICPSC_TypeDef TIM3_IC2Prescaler)
Sets the TIM3 Input Capture 2 prescaler.
void | TIM3_TimeBaseInit (TIM3_Prescaler_TypeDef TIM3_Prescaler, uint16_t TIM3_Period)
Initializes the TIM3 Time Base Unit according to the specified parameters.
void | TIM3_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM3 Update event.
void | TIM3_UpdateRequestConfig (TIM3_UpdateSource_TypeDef TIM3_UpdateSource)
Selects the TIM3 Update Request Interrupt source.

Function Documentation

static void TI1_Config | ( | uint8_t | TIM3_ICPolarity,
 |  | uint8_t | TIM3_ICSelection,
 |  | uint8_t | TIM3_ICFilter
 | ) |  | [static]

Configure the TI1 as Input.

Parameters:
TIM3_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM3_ICPOLARITY_FALLING
  • TIM3_ICPOLARITY_RISING
TIM3_ICSelection specifies the input to be used. This parameter can be one of the following values:
  • TIM3_ICSELECTION_DIRECTTI: TIM3 Input 1 is selected to be connected to IC1.
  • TIM3_ICSELECTION_INDIRECTTI: TIM3 Input 1 is selected to be connected to IC2.
TIM3_ICFilter Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 970 of file stm8s_tim3.c.

References TIM3_CCER1_CC1E, TIM3_CCER1_CC1P, TIM3_CCMR_CCxS, TIM3_CCMR_ICxF, and TIM3_ICPOLARITY_RISING.

Referenced by TIM3_ICInit(), and TIM3_PWMIConfig().

static void TI2_Config | ( | uint8_t | TIM3_ICPolarity,
 |  | uint8_t | TIM3_ICSelection,
 |  | uint8_t | TIM3_ICFilter
 | ) |  | [static]

Configure the TI2 as Input.

Parameters:
TIM3_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM3_ICPOLARITY_FALLING
  • TIM3_ICPOLARITY_RISING
TIM3_ICSelection specifies the input to be used. This parameter can be one of the following values:
  • TIM3_ICSELECTION_DIRECTTI: TIM3 Input 2 is selected to be connected to IC2.
  • TIM3_ICSELECTION_INDIRECTTI: TIM3 Input 2 is selected to be connected to IC1.
TIM3_ICFilter Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 1009 of file stm8s_tim3.c.

References TIM3_CCER1_CC2E, TIM3_CCER1_CC2P, TIM3_CCMR_CCxS, TIM3_CCMR_ICxF, and TIM3_ICPOLARITY_RISING.

Referenced by TIM3_ICInit(), and TIM3_PWMIConfig().

void TIM3_ARRPreloadConfig ( FunctionalState NewState )

Enables or disables TIM3 peripheral Preload register on ARR.

Parameters:
NewState new state of the TIM3 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 483 of file stm8s_tim3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM3_CR1_ARPE.

void TIM3_CCxCmd | ( | TIM3_Channel_TypeDef | TIM3_Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the TIM3 Capture Compare Channel x.

Parameters:
TIM3_Channel specifies the TIM3 Channel. This parameter can be one of the following values:
  • TIM3_CHANNEL_1: TIM3 Channel1
  • TIM3_CHANNEL_2: TIM3 Channel2
NewState specifies the TIM3 Channel CCxE bit new state. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 619 of file stm8s_tim3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, IS_TIM3_CHANNEL_OK, TIM3_CCER1_CC1E, TIM3_CCER1_CC2E, and TIM3_CHANNEL_1.

void TIM3_ClearFlag ( TIM3_FLAG_TypeDef TIM3_FLAG )

Clears the TIM3’s pending flags.

Parameters:
TIM3_FLAG specifies the flag to clear. This parameter can be one of the following values:
  • TIM3_FLAG_UPDATE: TIM3 update Flag
  • TIM3_FLAG_CC1: TIM3 Capture Compare 1 Flag
  • TIM3_FLAG_CC2: TIM3 Capture Compare 2 Flag
  • TIM3_FLAG_CC1OF: TIM3 Capture Compare 1 over capture Flag
  • TIM3_FLAG_CC2OF: TIM3 Capture Compare 2 over capture Flag
Return values:
None.

Definition at line 894 of file stm8s_tim3.c.

References IS_TIM3_CLEAR_FLAG_OK.

void TIM3_ClearITPendingBit ( TIM3_IT_TypeDef TIM3_IT )

Clears the TIM3's interrupt pending bits.

Parameters:
TIM3_IT specifies the pending bit to clear. This parameter can be one of the following values:
  • TIM3_IT_UPDATE: TIM3 update Interrupt source
  • TIM3_IT_CC1: TIM3 Capture Compare 1 Interrupt source
  • TIM3_IT_CC2: TIM3 Capture Compare 2 Interrupt source
Return values:
None.

Definition at line 945 of file stm8s_tim3.c.

References IS_TIM3_IT_OK.

void TIM3_Cmd ( FunctionalState NewState )

Enables or disables the TIM3 peripheral.

Parameters:
NewState new state of the TIM3 peripheral. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 283 of file stm8s_tim3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM3_CR1_CEN.

void TIM3_DeInit ( void )

Deinitializes the TIM3 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 51 of file stm8s_tim3.c.

References TIM3_ARRH_RESET_VALUE, TIM3_ARRL_RESET_VALUE, TIM3_CCER1_RESET_VALUE, TIM3_CCMR1_RESET_VALUE, TIM3_CCMR2_RESET_VALUE, TIM3_CCR1H_RESET_VALUE, TIM3_CCR1L_RESET_VALUE, TIM3_CCR2H_RESET_VALUE, TIM3_CCR2L_RESET_VALUE, TIM3_CNTRH_RESET_VALUE, TIM3_CNTRL_RESET_VALUE, TIM3_CR1_RESET_VALUE, TIM3_IER_RESET_VALUE, TIM3_PSCR_RESET_VALUE, TIM3_SR1_RESET_VALUE, and TIM3_SR2_RESET_VALUE.

void TIM3_ForcedOC1Config ( TIM3_ForcedAction_TypeDef TIM3_ForcedAction )

Forces the TIM3 Channel1 output waveform to active or inactive level.

Parameters:
TIM3_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:
  • TIM3_FORCEDACTION_ACTIVE: Force active level on OC1REF
  • TIM3_FORCEDACTION_INACTIVE: Force inactive level on OC1REF.
Return values:
None

Definition at line 450 of file stm8s_tim3.c.

References IS_TIM3_FORCED_ACTION_OK, and TIM3_CCMR_OCM.

void TIM3_ForcedOC2Config ( TIM3_ForcedAction_TypeDef TIM3_ForcedAction )

Forces the TIM3 Channel2 output waveform to active or inactive level.

Parameters:
TIM3_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:
  • TIM3_FORCEDACTION_ACTIVE: Force active level on OC2REF
  • TIM3_FORCEDACTION_INACTIVE: Force inactive level on OC2REF.
Return values:
None

Definition at line 468 of file stm8s_tim3.c.

References IS_TIM3_FORCED_ACTION_OK, and TIM3_CCMR_OCM.

void TIM3_GenerateEvent ( TIM3_EventSource_TypeDef TIM3_EventSource )

Configures the TIM3 event to be generated by software.

Parameters:
TIM3_EventSource specifies the event source. This parameter can be one of the following values:
  • TIM3_EVENTSOURCE_UPDATE: TIM3 update Event source
  • TIM3_EVENTSOURCE_CC1: TIM3 Capture Compare 1 Event source
  • TIM3_EVENTSOURCE_CC2: TIM3 Capture Compare 2 Event source
Return values:
None

Definition at line 552 of file stm8s_tim3.c.

References IS_TIM3_EVENT_SOURCE_OK.

uint16_t TIM3_GetCapture1 ( void )

Gets the TIM3 Input Capture 1 value.

Parameters:
None
Return values:
Capture Compare 1 Register value.

Definition at line 790 of file stm8s_tim3.c.

uint16_t TIM3_GetCapture2 ( void )

Gets the TIM3 Input Capture 2 value.

Parameters:
None
Return values:
Capture Compare 2 Register value.

Definition at line 810 of file stm8s_tim3.c.

uint16_t TIM3_GetCounter ( void )

Gets the TIM3 Counter value.

Parameters:
None
Return values:
Counter Register value.

Definition at line 830 of file stm8s_tim3.c.

FlagStatus TIM3_GetFlagStatus ( TIM3_FLAG_TypeDef TIM3_FLAG )

Checks whether the specified TIM3 flag is set or not.

Parameters:
TIM3_FLAG specifies the flag to check. This parameter can be one of the following values:
  • TIM3_FLAG_UPDATE: TIM3 update Flag
  • TIM3_FLAG_CC1: TIM3 Capture Compare 1 Flag
  • TIM3_FLAG_CC2: TIM3 Capture Compare 2 Flag
  • TIM3_FLAG_CC1OF: TIM3 Capture Compare 1 over capture Flag
  • TIM3_FLAG_CC2OF: TIM3 Capture Compare 2 over capture Flag
Return values:
FlagStatus The new state of TIM3_FLAG (SET or RESET).

Definition at line 861 of file stm8s_tim3.c.

References IS_TIM3_GET_FLAG_OK, RESET, and SET.

ITStatus TIM3_GetITStatus ( TIM3_IT_TypeDef TIM3_IT )

Checks whether the TIM3 interrupt has occurred or not.

Parameters:
TIM3_IT specifies the TIM3 interrupt source to check. This parameter can be one of the following values:
  • TIM3_IT_UPDATE: TIM3 update Interrupt source
  • TIM3_IT_CC1: TIM3 Capture Compare 1 Interrupt source
  • TIM3_IT_CC2: TIM3 Capture Compare 2 Interrupt source
Return values:
ITStatus The new state of the TIM3_IT(SET or RESET).

Definition at line 913 of file stm8s_tim3.c.

References IS_TIM3_GET_IT_OK, RESET, and SET.

TIM3_Prescaler_TypeDef TIM3_GetPrescaler ( void )

Gets the TIM3 Prescaler value.

Parameters:
None
Return values:
Prescaler Register configuration value TIM3_Prescaler_TypeDef.

Definition at line 844 of file stm8s_tim3.c.

void TIM3_ICInit | ( | TIM3_Channel_TypeDef | TIM3_Channel,
 |  | TIM3_ICPolarity_TypeDef | TIM3_ICPolarity,
 |  | TIM3_ICSelection_TypeDef | TIM3_ICSelection,
 |  | TIM3_ICPSC_TypeDef | TIM3_ICPrescaler,
 |  | uint8_t | TIM3_ICFilter
 | ) |  |

Initializes the TIM3 peripheral according to the specified parameters.

Parameters:
TIM3_Channel | specifies the Input Capture Channel from TIM3_Channel_TypeDef.
TIM3_ICPolarity | specifies the Input Capture Polarity from TIM3_ICPolarity_TypeDef.
TIM3_ICSelection | specifies the Input Capture Selection from TIM3_ICSelection_TypeDef.
TIM3_ICPrescaler | specifies the Input Capture Prescaler from TIM3_ICPSC_TypeDef.
TIM3_ICFilter | specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
Return values:
None

Definition at line 166 of file stm8s_tim3.c.

References IS_TIM3_CHANNEL_OK, IS_TIM3_IC_FILTER_OK, IS_TIM3_IC_POLARITY_OK, IS_TIM3_IC_PRESCALER_OK, IS_TIM3_IC_SELECTION_OK, TI1_Config(), TI2_Config(), TIM3_CHANNEL_2, TIM3_SetIC1Prescaler(), and TIM3_SetIC2Prescaler().

void TIM3_ITConfig | ( | TIM3_IT_TypeDef | TIM3_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified TIM3 interrupts.

Parameters:
NewState | new state of the TIM3 peripheral. This parameter can be: ENABLE or DISABLE.
TIM3_IT specifies the TIM3 interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:
  • TIM3_IT_UPDATE: TIM3 update Interrupt source
  • TIM3_IT_CC1: TIM3 Capture Compare 1 Interrupt source
  • TIM3_IT_CC2: TIM3 Capture Compare 2 Interrupt source
  • TIM3_IT_CC3: TIM3 Capture Compare 3 Interrupt source
NewState | new state of the TIM3 peripheral. *
Return values:
None

Definition at line 311 of file stm8s_tim3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and IS_TIM3_IT_OK.

void TIM3_OC1Init | ( | TIM3_OCMode_TypeDef | TIM3_OCMode,
 |  | TIM3_OutputState_TypeDef | TIM3_OutputState,
 |  | uint16_t | TIM3_Pulse,
 |  | TIM3_OCPolarity_TypeDef | TIM3_OCPolarity
 | ) |  |

Initializes the TIM3 Channel1 according to the specified parameters.

Parameters:
TIM3_OCMode | specifies the Output Compare mode from TIM3_OCMode_TypeDef.
TIM3_OutputState | specifies the Output State from TIM3_OutputState_TypeDef.
TIM3_Pulse | specifies the Pulse width value.
TIM3_OCPolarity | specifies the Output Compare Polarity from TIM3_OCPolarity_TypeDef.
Return values:
None

Definition at line 100 of file stm8s_tim3.c.

References IS_TIM3_OC_MODE_OK, IS_TIM3_OC_POLARITY_OK, IS_TIM3_OUTPUT_STATE_OK, TIM3_CCER1_CC1E, TIM3_CCER1_CC1P, and TIM3_CCMR_OCM.

void TIM3_OC1PolarityConfig ( TIM3_OCPolarity_TypeDef TIM3_OCPolarity )

Configures the TIM3 Channel 1 polarity.

Parameters:
TIM3_OCPolarity specifies the OC1 Polarity. This parameter can be one of the following values:
  • TIM3_OCPOLARITY_LOW: Output Compare active low
  • TIM3_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 569 of file stm8s_tim3.c.

References IS_TIM3_OC_POLARITY_OK, TIM3_CCER1_CC1P, and TIM3_OCPOLARITY_HIGH.

void TIM3_OC1PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM3 peripheral Preload Register on CCR1.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 505 of file stm8s_tim3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM3_CCMR_OCxPE.

void TIM3_OC2Init | ( | TIM3_OCMode_TypeDef | TIM3_OCMode,
 |  | TIM3_OutputState_TypeDef | TIM3_OutputState,
 |  | uint16_t | TIM3_Pulse,
 |  | TIM3_OCPolarity_TypeDef | TIM3_OCPolarity
 | ) |  |

Initializes the TIM3 Channel2 according to the specified parameters.

Parameters:
TIM3_OCMode | specifies the Output Compare mode from TIM3_OCMode_TypeDef.
TIM3_OutputState | specifies the Output State from TIM3_OutputState_TypeDef.
TIM3_Pulse | specifies the Pulse width value.
TIM3_OCPolarity | specifies the Output Compare Polarity from TIM3_OCPolarity_TypeDef.
Return values:
None

Definition at line 131 of file stm8s_tim3.c.

References IS_TIM3_OC_MODE_OK, IS_TIM3_OC_POLARITY_OK, IS_TIM3_OUTPUT_STATE_OK, TIM3_CCER1_CC2E, TIM3_CCER1_CC2P, and TIM3_CCMR_OCM.

void TIM3_OC2PolarityConfig ( TIM3_OCPolarity_TypeDef TIM3_OCPolarity )

Configures the TIM3 Channel 2 polarity.

Parameters:
TIM3_OCPolarity specifies the OC2 Polarity. This parameter can be one of the following values:
  • TIM3_OCPOLARITY_LOW: Output Compare active low
  • TIM3_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 593 of file stm8s_tim3.c.

References IS_TIM3_OC_POLARITY_OK, TIM3_CCER1_CC2P, and TIM3_OCPOLARITY_HIGH.

void TIM3_OC2PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM3 peripheral Preload Register on CCR2.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 527 of file stm8s_tim3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM3_CCMR_OCxPE.

void TIM3_PrescalerConfig | ( | TIM3_Prescaler_TypeDef | Prescaler,
 |  | TIM3_PSCReloadMode_TypeDef | TIM3_PSCReloadMode
 | ) |  |

Configures the TIM3 Prescaler.

Parameters:
Prescaler specifies the Prescaler Register value This parameter can be one of the following values
  • TIM3_PRESCALER_1
  • TIM3_PRESCALER_2
  • TIM3_PRESCALER_4
  • TIM3_PRESCALER_8
  • TIM3_PRESCALER_16
  • TIM3_PRESCALER_32
  • TIM3_PRESCALER_64
  • TIM3_PRESCALER_128
  • TIM3_PRESCALER_256
  • TIM3_PRESCALER_512
  • TIM3_PRESCALER_1024
  • TIM3_PRESCALER_2048
  • TIM3_PRESCALER_4096
  • TIM3_PRESCALER_8192
  • TIM3_PRESCALER_16384
  • TIM3_PRESCALER_32768
TIM3_PSCReloadMode specifies the TIM3 Prescaler Reload mode. This parameter can be one of the following values
  • TIM3_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded immediately.
  • TIM3_PSCRELOADMODE_UPDATE: The Prescaler is loaded at the update event.
Return values:
None

Definition at line 427 of file stm8s_tim3.c.

References IS_TIM3_PRESCALER_OK, and IS_TIM3_PRESCALER_RELOAD_OK.

void TIM3_PWMIConfig | ( | TIM3_Channel_TypeDef | TIM3_Channel,
 |  | TIM3_ICPolarity_TypeDef | TIM3_ICPolarity,
 |  | TIM3_ICSelection_TypeDef | TIM3_ICSelection,
 |  | TIM3_ICPSC_TypeDef | TIM3_ICPrescaler,
 |  | uint8_t | TIM3_ICFilter
 | ) |  |

Configures the TIM3 peripheral in PWM Input Mode according to the specified parameters.

Parameters:
TIM3_Channel | specifies the Input Capture Channel from TIM3_Channel_TypeDef.
TIM3_ICPolarity | specifies the Input Capture Polarity from TIM3_ICPolarity_TypeDef.
TIM3_ICSelection | specifies the Input Capture Selection from TIM3_ICSelection_TypeDef.
TIM3_ICPrescaler | specifies the Input Capture Prescaler from TIM3_ICPSC_TypeDef.
TIM3_ICFilter | specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
Return values:
None

Definition at line 210 of file stm8s_tim3.c.

References IS_TIM3_IC_POLARITY_OK, IS_TIM3_IC_PRESCALER_OK, IS_TIM3_IC_SELECTION_OK, IS_TIM3_PWMI_CHANNEL_OK, TI1_Config(), TI2_Config(), TIM3_CHANNEL_2, TIM3_ICPOLARITY_FALLING, TIM3_ICPOLARITY_RISING, TIM3_ICSELECTION_DIRECTTI, TIM3_ICSELECTION_INDIRECTTI, TIM3_SetIC1Prescaler(), and TIM3_SetIC2Prescaler().

void TIM3_SelectOCxM | ( | TIM3_Channel_TypeDef | TIM3_Channel,
 |  | TIM3_OCMode_TypeDef | TIM3_OCMode
 | ) |  |

Selects the TIM3 Output Compare Mode.

This function disables the selected channel before changing the Output Compare Mode. User has to enable this channel using TIM3_CCxCmd and TIM3_CCxNCmd functions.

Parameters:
TIM3_Channel specifies the TIM3 Channel. This parameter can be one of the following values:
  • TIM3_CHANNEL_1: TIM3 Channel1
  • TIM3_CHANNEL_2: TIM3 Channel2
TIM3_OCMode specifies the TIM3 Output Compare Mode. This parameter can be one of the following values:
  • TIM3_OCMODE_TIMING
  • TIM3_OCMODE_ACTIVE
  • TIM3_OCMODE_TOGGLE
  • TIM3_OCMODE_PWM1
  • TIM3_OCMODE_PWM2
  • TIM3_FORCEDACTION_ACTIVE
  • TIM3_FORCEDACTION_INACTIVE
Return values:
None

Definition at line 671 of file stm8s_tim3.c.

References IS_TIM3_CHANNEL_OK, IS_TIM3_OCM_OK, TIM3_CCER1_CC1E, TIM3_CCER1_CC2E, TIM3_CCMR_OCM, and TIM3_CHANNEL_1.

void TIM3_SelectOnePulseMode ( TIM3_OPMode_TypeDef TIM3_OPMode )

Selects the TIM3’s One Pulse Mode.

Parameters:
TIM3_OPMode specifies the OPM Mode to be used. This parameter can be one of the following values
  • TIM3_OPMODE_SINGLE
  • TIM3_OPMODE_REPETITIVE
Return values:
None

Definition at line 383 of file stm8s_tim3.c.

References IS_TIM3_OPM_MODE_OK, TIM3_CR1_OPM, and TIM3_OPMODE_REPETITIVE.

void TIM3_SetAutoreload ( uint16_t Autoreload )

Sets the TIM3 Autoreload Register value.

Parameters:
Autoreload specifies the Autoreload register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 714 of file stm8s_tim3.c.

void TIM3_SetCompare1 ( uint16_t Compare1 )

Sets the TIM3 Capture Compare1 Register value.

Parameters:
Compare1 specifies the Capture Compare1 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 727 of file stm8s_tim3.c.

void TIM3_SetCompare2 ( uint16_t Compare2 )

Sets the TIM3 Capture Compare2 Register value.

Parameters:
Compare2 specifies the Capture Compare2 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 740 of file stm8s_tim3.c.

void TIM3_SetCounter ( uint16_t Counter )

Sets the TIM3 Counter Register value.

Parameters:
Counter specifies the Counter register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 701 of file stm8s_tim3.c.

void TIM3_SetIC1Prescaler ( TIM3_ICPSC_TypeDef TIM3_IC1Prescaler )

Sets the TIM3 Input Capture 1 prescaler.

Parameters:
TIM3_IC1Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:
  • TIM3_ICPSC_DIV1: no prescaler
  • TIM3_ICPSC_DIV2: capture is done once every 2 events
  • TIM3_ICPSC_DIV4: capture is done once every 4 events
  • TIM3_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 757 of file stm8s_tim3.c.

References IS_TIM3_IC_PRESCALER_OK, and TIM3_CCMR_ICxPSC.

Referenced by TIM3_ICInit(), and TIM3_PWMIConfig().

void TIM3_SetIC2Prescaler ( TIM3_ICPSC_TypeDef TIM3_IC2Prescaler )

Sets the TIM3 Input Capture 2 prescaler.

Parameters:
TIM3_IC2Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:
  • TIM3_ICPSC_DIV1: no prescaler
  • TIM3_ICPSC_DIV2: capture is done once every 2 events
  • TIM3_ICPSC_DIV4: capture is done once every 4 events
  • TIM3_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 776 of file stm8s_tim3.c.

References IS_TIM3_IC_PRESCALER_OK, and TIM3_CCMR_ICxPSC.

Referenced by TIM3_ICInit(), and TIM3_PWMIConfig().

void TIM3_TimeBaseInit | ( | TIM3_Prescaler_TypeDef | TIM3_Prescaler,
 |  | uint16_t | TIM3_Period
 | ) |  |

Initializes the TIM3 Time Base Unit according to the specified parameters.

Parameters:
TIM3_Prescaler | specifies the Prescaler from TIM3_Prescaler_TypeDef.
TIM3_Period | specifies the Period value.
Return values:
None

Definition at line 82 of file stm8s_tim3.c.

void TIM3_UpdateDisableConfig ( FunctionalState NewState )

Enables or Disables the TIM3 Update event.

Parameters:
NewState new state of the TIM3 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 335 of file stm8s_tim3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM3_CR1_UDIS.

void TIM3_UpdateRequestConfig ( TIM3_UpdateSource_TypeDef TIM3_UpdateSource )

Selects the TIM3 Update Request Interrupt source.

Parameters:
TIM3_UpdateSource specifies the Update source. This parameter can be one of the following values
  • TIM3_UPDATESOURCE_REGULAR
  • TIM3_UPDATESOURCE_GLOBAL
Return values:
None

Definition at line 359 of file stm8s_tim3.c.

References IS_TIM3_UPDATE_SOURCE_OK, TIM3_CR1_URS, and TIM3_UPDATESOURCE_GLOBAL.


STM8S/A Standard Peripherals Drivers: TIM4_Public_Functions

Functions
TIM4_Public_Functions
STM8S_StdPeriph_Driver

Functions

void | TIM4_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM4 peripheral Preload register on ARR.
void | TIM4_ClearFlag (TIM4_FLAG_TypeDef TIM4_FLAG)
Clears the TIM4’s pending flags.
void | TIM4_ClearITPendingBit (TIM4_IT_TypeDef TIM4_IT)
Clears the TIM4's interrupt pending bits.
void | TIM4_Cmd (FunctionalState NewState)
Enables or disables the TIM4 peripheral.
void | TIM4_DeInit (void)
Deinitializes the TIM4 peripheral registers to their default reset values.
void | TIM4_GenerateEvent (TIM4_EventSource_TypeDef TIM4_EventSource)
Configures the TIM4 event to be generated by software.
uint8_t | TIM4_GetCounter (void)
Gets the TIM4 Counter value.
FlagStatus | TIM4_GetFlagStatus (TIM4_FLAG_TypeDef TIM4_FLAG)
Checks whether the specified TIM4 flag is set or not.
ITStatus | TIM4_GetITStatus (TIM4_IT_TypeDef TIM4_IT)
Checks whether the TIM4 interrupt has occurred or not.
TIM4_Prescaler_TypeDef | TIM4_GetPrescaler (void)
Gets the TIM4 Prescaler value.
void | TIM4_ITConfig (TIM4_IT_TypeDef TIM4_IT, FunctionalState NewState)
Enables or disables the specified TIM4 interrupts.
void | TIM4_PrescalerConfig (TIM4_Prescaler_TypeDef Prescaler, TIM4_PSCReloadMode_TypeDef TIM4_PSCReloadMode)
Configures the TIM4 Prescaler.
void | TIM4_SelectOnePulseMode (TIM4_OPMode_TypeDef TIM4_OPMode)
Selects the TIM4’s One Pulse Mode.
void | TIM4_SetAutoreload (uint8_t Autoreload)
Sets the TIM4 Autoreload Register value.
void | TIM4_SetCounter (uint8_t Counter)
Sets the TIM4 Counter Register value.
void | TIM4_TimeBaseInit (TIM4_Prescaler_TypeDef TIM4_Prescaler, uint8_t TIM4_Period)
Initializes the TIM4 Time Base Unit according to the specified parameters.
void | TIM4_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM4 Update event.
void | TIM4_UpdateRequestConfig (TIM4_UpdateSource_TypeDef TIM4_UpdateSource)
Selects the TIM4 Update Request Interrupt source.

Function Documentation

void TIM4_ARRPreloadConfig ( FunctionalState NewState )

Enables or disables TIM4 peripheral Preload register on ARR.

Parameters:
NewState new state of the TIM4 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 234 of file stm8s_tim4.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM4_CR1_ARPE.

void TIM4_ClearFlag ( TIM4_FLAG_TypeDef TIM4_FLAG )

Clears the TIM4’s pending flags.

Parameters:
TIM4_FLAG specifies the flag to clear. This parameter can be one of the following values:
  • TIM4_FLAG_UPDATE: TIM4 update Flag
Return values:
None.

Definition at line 344 of file stm8s_tim4.c.

References IS_TIM4_GET_FLAG_OK.

void TIM4_ClearITPendingBit ( TIM4_IT_TypeDef TIM4_IT )

Clears the TIM4's interrupt pending bits.

Parameters:
TIM4_IT specifies the pending bit to clear. This parameter can be one of the following values:
  • TIM4_IT_UPDATE: TIM4 update Interrupt source
Return values:
None.

Definition at line 391 of file stm8s_tim4.c.

References IS_TIM4_IT_OK.

void TIM4_Cmd ( FunctionalState NewState )

Enables or disables the TIM4 peripheral.

Parameters:
NewState new state of the TIM4 peripheral. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 81 of file stm8s_tim4.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM4_CR1_CEN.

void TIM4_DeInit ( void )

Deinitializes the TIM4 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 49 of file stm8s_tim4.c.

References TIM4_ARR_RESET_VALUE, TIM4_CNTR_RESET_VALUE, TIM4_CR1_RESET_VALUE, TIM4_IER_RESET_VALUE, TIM4_PSCR_RESET_VALUE, and TIM4_SR1_RESET_VALUE.

void TIM4_GenerateEvent ( TIM4_EventSource_TypeDef TIM4_EventSource )

Configures the TIM4 event to be generated by software.

Parameters:
TIM4_EventSource specifies the event source. This parameter can be one of the following values:
  • TIM4_EVENTSOURCE_UPDATE: TIM4 update Event source
Return values:
None

Definition at line 257 of file stm8s_tim4.c.

References IS_TIM4_EVENT_SOURCE_OK.

uint8_t TIM4_GetCounter ( void )

Gets the TIM4 Counter value.

Parameters:
None
Return values:
Counter Register value.

Definition at line 295 of file stm8s_tim4.c.

FlagStatus TIM4_GetFlagStatus ( TIM4_FLAG_TypeDef TIM4_FLAG )

Checks whether the specified TIM4 flag is set or not.

Parameters:
TIM4_FLAG specifies the flag to check. This parameter can be one of the following values:
  • TIM4_FLAG_UPDATE: TIM4 update Flag
Return values:
FlagStatus The new state of TIM4_FLAG (SET or RESET).

Definition at line 319 of file stm8s_tim4.c.

References IS_TIM4_GET_FLAG_OK, RESET, and SET.

ITStatus TIM4_GetITStatus ( TIM4_IT_TypeDef TIM4_IT )

Checks whether the TIM4 interrupt has occurred or not.

Parameters:
TIM4_IT specifies the TIM4 interrupt source to check. This parameter can be one of the following values:
  • TIM4_IT_UPDATE: TIM4 update Interrupt source
Return values:
ITStatus The new state of the TIM4_IT (SET or RESET).

Definition at line 360 of file stm8s_tim4.c.

References IS_TIM4_IT_OK, RESET, and SET.

TIM4_Prescaler_TypeDef TIM4_GetPrescaler ( void )

Gets the TIM4 Prescaler value.

Parameters:
None
Return values:
Prescaler Register configuration value.

Definition at line 306 of file stm8s_tim4.c.

void TIM4_ITConfig | ( | TIM4_IT_TypeDef | TIM4_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified TIM4 interrupts.

Parameters:
NewState | new state of the TIM4 peripheral. This parameter can be: ENABLE or DISABLE.
TIM4_IT specifies the TIM4 interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:
  • TIM4_IT_UPDATE: TIM4 update Interrupt source
NewState | new state of the TIM4 peripheral.
Return values:
None

Definition at line 107 of file stm8s_tim4.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and IS_TIM4_IT_OK.

void TIM4_PrescalerConfig | ( | TIM4_Prescaler_TypeDef | Prescaler,
 |  | TIM4_PSCReloadMode_TypeDef | TIM4_PSCReloadMode
 | ) |  |

Configures the TIM4 Prescaler.

Parameters:
Prescaler specifies the Prescaler Register value This parameter can be one of the following values
  • TIM4_PRESCALER_1
  • TIM4_PRESCALER_2
  • TIM4_PRESCALER_4
  • TIM4_PRESCALER_8
  • TIM4_PRESCALER_16
  • TIM4_PRESCALER_32
  • TIM4_PRESCALER_64
  • TIM4_PRESCALER_128
TIM4_PSCReloadMode specifies the TIM4 Prescaler Reload mode. This parameter can be one of the following values
  • TIM4_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded immediately.
  • TIM4_PSCRELOADMODE_UPDATE: The Prescaler is loaded at the update event.
Return values:
None

Definition at line 215 of file stm8s_tim4.c.

References IS_TIM4_PRESCALER_OK, and IS_TIM4_PRESCALER_RELOAD_OK.

void TIM4_SelectOnePulseMode ( TIM4_OPMode_TypeDef TIM4_OPMode )

Selects the TIM4’s One Pulse Mode.

Parameters:
TIM4_OPMode specifies the OPM Mode to be used. This parameter can be one of the following values
  • TIM4_OPMODE_SINGLE
  • TIM4_OPMODE_REPETITIVE
Return values:
None

Definition at line 179 of file stm8s_tim4.c.

References IS_TIM4_OPM_MODE_OK, TIM4_CR1_OPM, and TIM4_OPMODE_REPETITIVE.

void TIM4_SetAutoreload ( uint8_t Autoreload )

Sets the TIM4 Autoreload Register value.

Parameters:
Autoreload specifies the Autoreload register new value. This parameter is between 0x00 and 0xFF.
Return values:
None

Definition at line 284 of file stm8s_tim4.c.

void TIM4_SetCounter ( uint8_t Counter )

Sets the TIM4 Counter Register value.

Parameters:
Counter specifies the Counter register new value. This parameter is between 0x00 and 0xFF.
Return values:
None

Definition at line 272 of file stm8s_tim4.c.

void TIM4_TimeBaseInit | ( | TIM4_Prescaler_TypeDef | TIM4_Prescaler,
 |  | uint8_t | TIM4_Period
 | ) |  |

Initializes the TIM4 Time Base Unit according to the specified parameters.

Parameters:
TIM4_Prescaler | specifies the Prescaler from TIM4_Prescaler_TypeDef.
TIM4_Period | specifies the Period value.
Return values:
None

Definition at line 65 of file stm8s_tim4.c.

References IS_TIM4_PRESCALER_OK.

void TIM4_UpdateDisableConfig ( FunctionalState NewState )

Enables or Disables the TIM4 Update event.

Parameters:
NewState new state of the TIM4 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 131 of file stm8s_tim4.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM4_CR1_UDIS.

void TIM4_UpdateRequestConfig ( TIM4_UpdateSource_TypeDef TIM4_UpdateSource )

Selects the TIM4 Update Request Interrupt source.

Parameters:
TIM4_UpdateSource specifies the Update source. This parameter can be one of the following values
  • TIM4_UPDATESOURCE_REGULAR
  • TIM4_UPDATESOURCE_GLOBAL
Return values:
None

Definition at line 155 of file stm8s_tim4.c.

References IS_TIM4_UPDATE_SOURCE_OK, TIM4_CR1_URS, and TIM4_UPDATESOURCE_GLOBAL.


STM8S/A Standard Peripherals Drivers: TIM5_Public_Functions

Functions
TIM5_Public_Functions
STM8S_StdPeriph_Driver

Functions

static void | TI1_Config (uint8_t TIM5_ICPolarity, uint8_t TIM5_ICSelection, uint8_t TIM5_ICFilter)
Configure the TI1 as Input.
static void | TI2_Config (uint8_t TIM5_ICPolarity, uint8_t TIM5_ICSelection, uint8_t TIM5_ICFilter)
Configure the TI2 as Input.
static void | TI3_Config (uint8_t TIM5_ICPolarity, uint8_t TIM5_ICSelection, uint8_t TIM5_ICFilter)
Configure the TI3 as Input.
void | TIM5_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM5 peripheral Preload register on ARR.
void | TIM5_CCxCmd (TIM5_Channel_TypeDef TIM5_Channel, FunctionalState NewState)
Enables or disables the TIM5 Capture Compare Channel x.
void | TIM5_ClearFlag (TIM5_FLAG_TypeDef TIM5_FLAG)
Clears the TIM5’s pending flags.
void | TIM5_ClearITPendingBit (TIM5_IT_TypeDef TIM5_IT)
Clears the TIM5's interrupt pending bits.
void | TIM5_Cmd (FunctionalState NewState)
Enables or disables the TIM5 peripheral.
void | TIM5_DeInit (void)
Deinitializes the TIM5 peripheral registers to their default reset values.
void | TIM5_EncoderInterfaceConfig (TIM5_EncoderMode_TypeDef TIM5_EncoderMode, TIM5_ICPolarity_TypeDef TIM5_IC1Polarity, TIM5_ICPolarity_TypeDef TIM5_IC2Polarity)
Configures the TIM5 Encoder Interface.
void | TIM5_ForcedOC1Config (TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
Forces the TIM5 Channel1 output waveform to active or inactive level.
void | TIM5_ForcedOC2Config (TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
Forces the TIM5 Channel2 output waveform to active or inactive level.
void | TIM5_ForcedOC3Config (TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
Forces the TIM5 Channel3 output waveform to active or inactive level.
void | TIM5_GenerateEvent (TIM5_EventSource_TypeDef TIM5_EventSource)
Configures the TIM5 event to be generated by software.
uint16_t | TIM5_GetCapture1 (void)
Gets the TIM5 Input Capture 1 value.
uint16_t | TIM5_GetCapture2 (void)
Gets the TIM5 Input Capture 2 value.
uint16_t | TIM5_GetCapture3 (void)
Gets the TIM5 Input Capture 3 value.
uint16_t | TIM5_GetCounter (void)
Gets the TIM5 Counter value.
FlagStatus | TIM5_GetFlagStatus (TIM5_FLAG_TypeDef TIM5_FLAG)
Checks whether the specified TIM5 flag is set or not.
ITStatus | TIM5_GetITStatus (TIM5_IT_TypeDef TIM5_IT)
Checks whether the TIM5 interrupt has occurred or not.
TIM5_Prescaler_TypeDef | TIM5_GetPrescaler (void)
Gets the TIM5 Prescaler value.
void | TIM5_ICInit (TIM5_Channel_TypeDef TIM5_Channel, TIM5_ICPolarity_TypeDef TIM5_ICPolarity, TIM5_ICSelection_TypeDef TIM5_ICSelection, TIM5_ICPSC_TypeDef TIM5_ICPrescaler, uint8_t TIM5_ICFilter)
Initializes the TIM5 peripheral according to the specified parameters.
void | TIM5_InternalClockConfig (void)
Enables the TIM5 internal Clock.
void | TIM5_ITConfig (TIM5_IT_TypeDef TIM5_IT, FunctionalState NewState)
Enables or disables the specified TIM5 interrupts.
void | TIM5_OC1Init (TIM5_OCMode_TypeDef TIM5_OCMode, TIM5_OutputState_TypeDef TIM5_OutputState, uint16_t TIM5_Pulse, TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Initializes the TIM5 Channel1 according to the specified parameters.
void | TIM5_OC1PolarityConfig (TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Configures the TIM5 Channel 1 polarity.
void | TIM5_OC1PreloadConfig (FunctionalState NewState)
Enables or disables the TIM5 peripheral Preload Register on CCR1.
void | TIM5_OC2Init (TIM5_OCMode_TypeDef TIM5_OCMode, TIM5_OutputState_TypeDef TIM5_OutputState, uint16_t TIM5_Pulse, TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Initializes the TIM5 Channel2 according to the specified parameters.
void | TIM5_OC2PolarityConfig (TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Configures the TIM5 Channel 2 polarity.
void | TIM5_OC2PreloadConfig (FunctionalState NewState)
Enables or disables the TIM5 peripheral Preload Register on CCR2.
void | TIM5_OC3Init (TIM5_OCMode_TypeDef TIM5_OCMode, TIM5_OutputState_TypeDef TIM5_OutputState, uint16_t TIM5_Pulse, TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Initializes the TIM5 Channel3 according to the specified parameters.
void | TIM5_OC3PolarityConfig (TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Configures the TIM5 Channel 3 polarity.
void | TIM5_OC3PreloadConfig (FunctionalState NewState)
Enables or disables the TIM5 peripheral Preload Register on CCR3.
void | TIM5_PrescalerConfig (TIM5_Prescaler_TypeDef Prescaler, TIM5_PSCReloadMode_TypeDef TIM5_PSCReloadMode)
Configures the TIM5 Prescaler.
void | TIM5_PWMIConfig (TIM5_Channel_TypeDef TIM5_Channel, TIM5_ICPolarity_TypeDef TIM5_ICPolarity, TIM5_ICSelection_TypeDef TIM5_ICSelection, TIM5_ICPSC_TypeDef TIM5_ICPrescaler, uint8_t TIM5_ICFilter)
Configures the TIM5 peripheral in PWM Input Mode according to the specified parameters.
void | TIM5_SelectInputTrigger (TIM5_TS_TypeDef TIM5_InputTriggerSource)
Selects the TIM5 Input Trigger source.
void | TIM5_SelectOCxM (TIM5_Channel_TypeDef TIM5_Channel, TIM5_OCMode_TypeDef TIM5_OCMode)
Selects the TIM5 Output Compare Mode.
void | TIM5_SelectOnePulseMode (TIM5_OPMode_TypeDef TIM5_OPMode)
Selects the TIM5’s One Pulse Mode.
void | TIM5_SelectOutputTrigger (TIM5_TRGOSource_TypeDef TIM5_TRGOSource)
Selects the TIM5 Trigger Output Mode.
void | TIM5_SelectSlaveMode (TIM5_SlaveMode_TypeDef TIM5_SlaveMode)
Selects the TIM5 Slave Mode.
void | TIM5_SetAutoreload (uint16_t Autoreload)
Sets the TIM5 Autoreload Register value.
void | TIM5_SetCompare1 (uint16_t Compare1)
Sets the TIM5 Capture Compare1 Register value.
void | TIM5_SetCompare2 (uint16_t Compare2)
Sets the TIM5 Capture Compare2 Register value.
void | TIM5_SetCompare3 (uint16_t Compare3)
Sets the TIM5 Capture Compare3 Register value.
void | TIM5_SetCounter (uint16_t Counter)
Sets the TIM5 Counter Register value.
void | TIM5_SetIC1Prescaler (TIM5_ICPSC_TypeDef TIM5_IC1Prescaler)
Sets the TIM5 Input Capture 1 prescaler.
void | TIM5_SetIC2Prescaler (TIM5_ICPSC_TypeDef TIM5_IC2Prescaler)
Sets the TIM5 Input Capture 2 prescaler.
void | TIM5_SetIC3Prescaler (TIM5_ICPSC_TypeDef TIM5_IC3Prescaler)
Sets the TIM5 Input Capture 3 prescaler.
void | TIM5_TimeBaseInit (TIM5_Prescaler_TypeDef TIM5_Prescaler, uint16_t TIM5_Period)
Initializes the TIM5 Time Base Unit according to the specified parameters.
void | TIM5_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM5 Update event.
void | TIM5_UpdateRequestConfig (TIM5_UpdateSource_TypeDef TIM5_UpdateSource)
Selects the TIM5 Update Request Interrupt source.

Function Documentation

static void TI1_Config | ( | uint8_t | TIM5_ICPolarity,
 |  | uint8_t | TIM5_ICSelection,
 |  | uint8_t | TIM5_ICFilter
 | ) |  | [static]

Configure the TI1 as Input.

Parameters:
TIM5_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM5_ICPOLARITY_FALLING
  • TIM5_ICPOLARITY_RISING
TIM5_ICSelection specifies the input to be used. This parameter can be one of the following values:
  • TIM5_ICSELECTION_DIRECTTI: TIM5 Input 1 is selected to be connected to IC1.
  • TIM5_ICSELECTION_INDIRECTTI: TIM5 Input 1 is selected to be connected to IC2.
TIM5_ICFilter Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 1161 of file stm8s_tim5.c.

References TIM5_CCER1_CC1E, TIM5_CCER1_CC1P, TIM5_CCMR_CCxS, TIM5_CCMR_ICxF, and TIM5_ICPOLARITY_RISING.

Referenced by TIM5_ICInit(), and TIM5_PWMIConfig().

static void TI2_Config | ( | uint8_t | TIM5_ICPolarity,
 |  | uint8_t | TIM5_ICSelection,
 |  | uint8_t | TIM5_ICFilter
 | ) |  | [static]

Configure the TI2 as Input.

Parameters:
TIM5_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM5_ICPOLARITY_FALLING
  • TIM5_ICPOLARITY_RISING
TIM5_ICSelection specifies the input to be used. This parameter can be one of the following values:
  • TIM5_ICSELECTION_DIRECTTI: TIM5 Input 2 is selected to be connected to IC2.
  • TIM5_ICSELECTION_INDIRECTTI: TIM5 Input 2 is selected to be connected to IC1.
TIM5_ICFilter Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 1201 of file stm8s_tim5.c.

References TIM5_CCER1_CC2E, TIM5_CCER1_CC2P, TIM5_CCMR_CCxS, TIM5_CCMR_ICxF, and TIM5_ICPOLARITY_RISING.

Referenced by TIM5_ICInit(), and TIM5_PWMIConfig().

static void TI3_Config | ( | uint8_t | TIM5_ICPolarity,
 |  | uint8_t | TIM5_ICSelection,
 |  | uint8_t | TIM5_ICFilter
 | ) |  | [static]

Configure the TI3 as Input.

Parameters:
TIM5_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM5_ICPOLARITY_FALLING
  • TIM5_ICPOLARITY_RISING
TIM5_ICSelection specifies the input to be used. This parameter can be one of the following values:
  • TIM5_ICSELECTION_DIRECTTI: TIM5 Input 3 is selected to be connected to IC3.
TIM5_ICFilter Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 1241 of file stm8s_tim5.c.

References TIM5_CCER2_CC3E, TIM5_CCER2_CC3P, TIM5_CCMR_CCxS, TIM5_CCMR_ICxF, and TIM5_ICPOLARITY_RISING.

Referenced by TIM5_ICInit().

void TIM5_ARRPreloadConfig ( FunctionalState NewState )

Enables or disables TIM5 peripheral Preload register on ARR.

Parameters:
NewState new state of the TIM5 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 556 of file stm8s_tim5.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM5_CR1_ARPE.

void TIM5_CCxCmd | ( | TIM5_Channel_TypeDef | TIM5_Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the TIM5 Capture Compare Channel x.

Parameters:
TIM5_Channel specifies the TIM5 Channel. This parameter can be one of the following values:
  • TIM5_Channel1: TIM5 Channel1
  • TIM5_Channel2: TIM5 Channel2
  • TIM5_Channel3: TIM5 Channel3
NewState specifies the TIM5 Channel CCxE bit new state. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 741 of file stm8s_tim5.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, IS_TIM5_CHANNEL_OK, TIM5_CCER1_CC1E, TIM5_CCER1_CC2E, TIM5_CCER2_CC3E, TIM5_CHANNEL_1, and TIM5_CHANNEL_2.

void TIM5_ClearFlag ( TIM5_FLAG_TypeDef TIM5_FLAG )

Clears the TIM5’s pending flags.

Parameters:
TIM5_FLAG specifies the flag to clear. This parameter can be one of the following values:
  • TIM5_FLAG_UPDATE: TIM5 update Flag
  • TIM5_FLAG_CC1: TIM5 Capture Compare 1 Flag
  • TIM5_FLAG_CC2: TIM5 Capture Compare 2 Flag
  • TIM5_FLAG_CC3: TIM5 Capture Compare 3 Flag
  • TIM5_FLAG_CC1OF: TIM5 Capture Compare 1 overcapture Flag
  • TIM5_FLAG_CC2OF: TIM5 Capture Compare 2 overcapture Flag
  • TIM5_FLAG_CC3OF: TIM5 Capture Compare 3 overcapture Flag
Return values:
None.

Definition at line 1082 of file stm8s_tim5.c.

References IS_TIM5_CLEAR_FLAG_OK.

void TIM5_ClearITPendingBit ( TIM5_IT_TypeDef TIM5_IT )

Clears the TIM5's interrupt pending bits.

Parameters:
TIM5_IT specifies the pending bit to clear. This parameter can be one of the following values:
  • TIM5_IT_UPDATE: TIM5 update Interrupt source
  • TIM5_IT_CC1: TIM5 Capture Compare 1 Interrupt source
  • TIM5_IT_CC2: TIM5 Capture Compare 2 Interrupt source
  • TIM5_IT_CC3: TIM5 Capture Compare 3 Interrupt source
Return values:
None.

Definition at line 1136 of file stm8s_tim5.c.

References IS_TIM5_IT_OK.

void TIM5_Cmd ( FunctionalState NewState )

Enables or disables the TIM5 peripheral.

Parameters:
NewState new state of the TIM5 peripheral.This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 334 of file stm8s_tim5.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM5_CR1_CEN.

void TIM5_DeInit ( void )

Deinitializes the TIM5 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 52 of file stm8s_tim5.c.

References TIM5_ARRH_RESET_VALUE, TIM5_ARRL_RESET_VALUE, TIM5_CCER1_RESET_VALUE, TIM5_CCER2_RESET_VALUE, TIM5_CCMR1_RESET_VALUE, TIM5_CCMR2_RESET_VALUE, TIM5_CCMR3_RESET_VALUE, TIM5_CCR1H_RESET_VALUE, TIM5_CCR1L_RESET_VALUE, TIM5_CCR2H_RESET_VALUE, TIM5_CCR2L_RESET_VALUE, TIM5_CCR3H_RESET_VALUE, TIM5_CCR3L_RESET_VALUE, TIM5_CNTRH_RESET_VALUE, TIM5_CNTRL_RESET_VALUE, TIM5_CR1_RESET_VALUE, TIM5_CR2_RESET_VALUE, TIM5_IER_RESET_VALUE, TIM5_PSCR_RESET_VALUE, TIM5_SMCR_RESET_VALUE, TIM5_SR1_RESET_VALUE, and TIM5_SR2_RESET_VALUE.

void TIM5_EncoderInterfaceConfig | ( | TIM5_EncoderMode_TypeDef | TIM5_EncoderMode,
 |  | TIM5_ICPolarity_TypeDef | TIM5_IC1Polarity,
 |  | TIM5_ICPolarity_TypeDef | TIM5_IC2Polarity
 | ) |  |

Configures the TIM5 Encoder Interface.

Parameters:
TIM5_EncoderMode | : Specifies the TIM5 Encoder Mode. This parameter can be one of the TIM5_EncoderMode_TypeDef enumeration.
TIM5_IC1Polarity | : Specifies the IC1 Polarity. This parameter can be one of the TIM5_ICPolarity_TypeDef enumeration.
TIM5_IC2Polarity | : Specifies the IC2 Polarity. This parameter can be one of the TIM5_ICPolarity_TypeDef enumeration.
Return values:
None

Definition at line 1357 of file stm8s_tim5.c.

References IS_TIM5_ENCODER_MODE_OK, IS_TIM5_IC_POLARITY_OK, TIM5_CCER1_CC1P, TIM5_CCER1_CC2P, TIM5_CCMR_CCxS, TIM5_CCMR_TIxDirect_Set, TIM5_ICPOLARITY_FALLING, TIM5_SMCR_MSM, and TIM5_SMCR_TS.

void TIM5_ForcedOC1Config ( TIM5_ForcedAction_TypeDef TIM5_ForcedAction )

Forces the TIM5 Channel1 output waveform to active or inactive level.

Parameters:
TIM5_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:
  • TIM5_FORCEDACTION_ACTIVE: Force active level on OC1REF
  • TIM5_FORCEDACTION_INACTIVE: Force inactive level on OC1REF.
Return values:
None

Definition at line 502 of file stm8s_tim5.c.

References IS_TIM5_FORCED_ACTION_OK, and TIM5_CCMR_OCM.

void TIM5_ForcedOC2Config ( TIM5_ForcedAction_TypeDef TIM5_ForcedAction )

Forces the TIM5 Channel2 output waveform to active or inactive level.

Parameters:
TIM5_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:
  • TIM5_FORCEDACTION_ACTIVE: Force active level on OC2REF
  • TIM5_FORCEDACTION_INACTIVE: Force inactive level on OC2REF.
Return values:
None

Definition at line 521 of file stm8s_tim5.c.

References IS_TIM5_FORCED_ACTION_OK, and TIM5_CCMR_OCM.

void TIM5_ForcedOC3Config ( TIM5_ForcedAction_TypeDef TIM5_ForcedAction )

Forces the TIM5 Channel3 output waveform to active or inactive level.

Parameters:
TIM5_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:
  • TIM5_FORCEDACTION_ACTIVE: Force active level on OC3REF
  • TIM5_FORCEDACTION_INACTIVE: Force inactive level on OC3REF.
Return values:
None

Definition at line 540 of file stm8s_tim5.c.

References IS_TIM5_FORCED_ACTION_OK, and TIM5_CCMR_OCM.

void TIM5_GenerateEvent ( TIM5_EventSource_TypeDef TIM5_EventSource )

Configures the TIM5 event to be generated by software.

Parameters:
TIM5_EventSource specifies the event source. This parameter can be one of the following values:
  • TIM5_EVENTSOURCE_UPDATE: TIM5 update Event source
  • TIM5_EVENTSOURCE_CC1: TIM5 Capture Compare 1 Event source
  • TIM5_EVENTSOURCE_CC2: TIM5 Capture Compare 2 Event source
  • TIM5_EVENTSOURCE_CC3: TIM5 Capture Compare 3 Event source
Return values:
None

Definition at line 648 of file stm8s_tim5.c.

References IS_TIM5_EVENT_SOURCE_OK.

uint16_t TIM5_GetCapture1 ( void )

Gets the TIM5 Input Capture 1 value.

Parameters:
None
Return values:
Capture Compare 1 Register value.

Definition at line 970 of file stm8s_tim5.c.

uint16_t TIM5_GetCapture2 ( void )

Gets the TIM5 Input Capture 2 value.

Parameters:
None
Return values:
Capture Compare 2 Register value.

Definition at line 985 of file stm8s_tim5.c.

uint16_t TIM5_GetCapture3 ( void )

Gets the TIM5 Input Capture 3 value.

Parameters:
None
Return values:
Capture Compare 3 Register value.

Definition at line 1000 of file stm8s_tim5.c.

uint16_t TIM5_GetCounter ( void )

Gets the TIM5 Counter value.

Parameters:
None
Return values:
Counter Register value.

Definition at line 1014 of file stm8s_tim5.c.

FlagStatus TIM5_GetFlagStatus ( TIM5_FLAG_TypeDef TIM5_FLAG )

Checks whether the specified TIM5 flag is set or not.

Parameters:
TIM5_FLAG specifies the flag to check. This parameter can be one of the following values:
  • TIM5_FLAG_UPDATE: TIM5 update Flag
  • TIM5_FLAG_CC1: TIM5 Capture Compare 1 Flag
  • TIM5_FLAG_CC2: TIM5 Capture Compare 2 Flag
  • TIM5_FLAG_CC3: TIM5 Capture Compare 3 Flag
  • TIM5_FLAG_CC1OF: TIM5 Capture Compare 1 overcapture Flag
  • TIM5_FLAG_CC2OF: TIM5 Capture Compare 2 overcapture Flag
  • TIM5_FLAG_CC3OF: TIM5 Capture Compare 3 overcapture Flag
Return values:
FlagStatus The new state of TIM5_FLAG (SET or RESET).

Definition at line 1047 of file stm8s_tim5.c.

References IS_TIM5_GET_FLAG_OK, RESET, and SET.

ITStatus TIM5_GetITStatus ( TIM5_IT_TypeDef TIM5_IT )

Checks whether the TIM5 interrupt has occurred or not.

Parameters:
TIM5_IT specifies the TIM5 interrupt source to check. This parameter can be one of the following values:
  • TIM5_IT_UPDATE: TIM5 update Interrupt source
  • TIM5_IT_CC1: TIM5 Capture Compare 1 Interrupt source
  • TIM5_IT_CC2: TIM5 Capture Compare 2 Interrupt source
  • TIM5_IT_CC3: TIM5 Capture Compare 3 Interrupt source
Return values:
ITStatus The new state of the TIM5_IT(SET or RESET).

Definition at line 1103 of file stm8s_tim5.c.

References IS_TIM5_GET_IT_OK, RESET, and SET.

TIM5_Prescaler_TypeDef TIM5_GetPrescaler ( void )

Gets the TIM5 Prescaler value.

Parameters:
None
Return values:
Prescaler Register configuration value TIM5_Prescaler_TypeDef .

Definition at line 1028 of file stm8s_tim5.c.

void TIM5_ICInit | ( | TIM5_Channel_TypeDef | TIM5_Channel,
 |  | TIM5_ICPolarity_TypeDef | TIM5_ICPolarity,
 |  | TIM5_ICSelection_TypeDef | TIM5_ICSelection,
 |  | TIM5_ICPSC_TypeDef | TIM5_ICPrescaler,
 |  | uint8_t | TIM5_ICFilter
 | ) |  |

Initializes the TIM5 peripheral according to the specified parameters.

Parameters:
TIM5_Channel | specifies the Input Capture Channel from TIM5_Channel_TypeDef.
TIM5_ICPolarity | specifies the Input Capture Polarity from TIM5_ICPolarity_TypeDef.
TIM5_ICSelection | specifies theInput Capture Selection from TIM5_ICSelection_TypeDef.
TIM5_ICPrescaler | specifies the Input Capture Prescaler from TIM5_ICPSC_TypeDef.
TIM5_ICFilter | specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
Return values:
None

Definition at line 207 of file stm8s_tim5.c.

References IS_TIM5_CHANNEL_OK, IS_TIM5_IC_FILTER_OK, IS_TIM5_IC_POLARITY_OK, IS_TIM5_IC_PRESCALER_OK, IS_TIM5_IC_SELECTION_OK, TI1_Config(), TI2_Config(), TI3_Config(), TIM5_CHANNEL_1, TIM5_CHANNEL_2, TIM5_SetIC1Prescaler(), TIM5_SetIC2Prescaler(), and TIM5_SetIC3Prescaler().

void TIM5_InternalClockConfig ( void )

Enables the TIM5 internal Clock.

Parameters:
None
Return values:
None

Definition at line 1271 of file stm8s_tim5.c.

References TIM5_SMCR_SMS.

void TIM5_ITConfig | ( | TIM5_IT_TypeDef | TIM5_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified TIM5 interrupts.

Parameters:
NewState | new state of the TIM5 peripheral. This parameter can be: ENABLE or DISABLE.
TIM5_IT specifies the TIM5 interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:
  • TIM5_IT_UPDATE: TIM5 update Interrupt source
  • TIM5_IT_CC1: TIM5 Capture Compare 1 Interrupt source
  • TIM5_IT_CC2: TIM5 Capture Compare 2 Interrupt source
  • TIM5_IT_CC3: TIM5 Capture Compare 3 Interrupt source
NewState | new state of the TIM5 peripheral.
Return values:
None

Definition at line 363 of file stm8s_tim5.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and IS_TIM5_IT_OK.

void TIM5_OC1Init | ( | TIM5_OCMode_TypeDef | TIM5_OCMode,
 |  | TIM5_OutputState_TypeDef | TIM5_OutputState,
 |  | uint16_t | TIM5_Pulse,
 |  | TIM5_OCPolarity_TypeDef | TIM5_OCPolarity
 | ) |  |

Initializes the TIM5 Channel1 according to the specified parameters.

Parameters:
TIM5_OCMode | specifies the Output Compare mode from TIM5_OCMode_TypeDef.
TIM5_OutputState | specifies the Output State from TIM5_OutputState_TypeDef.
TIM5_Pulse | specifies the Pulse width value.
TIM5_OCPolarity | specifies the Output Compare Polarity from TIM5_OCPolarity_TypeDef.
Return values:
None

Definition at line 108 of file stm8s_tim5.c.

References IS_TIM5_OC_MODE_OK, IS_TIM5_OC_POLARITY_OK, IS_TIM5_OUTPUT_STATE_OK, TIM5_CCER1_CC1E, TIM5_CCER1_CC1P, and TIM5_CCMR_OCM.

void TIM5_OC1PolarityConfig ( TIM5_OCPolarity_TypeDef TIM5_OCPolarity )

Configures the TIM5 Channel 1 polarity.

Parameters:
TIM5_OCPolarity specifies the OC1 Polarity. This parameter can be one of the following values:
  • TIM5_OCPOLARITY_LOW: Output Compare active low
  • TIM5_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 665 of file stm8s_tim5.c.

References IS_TIM5_OC_POLARITY_OK, TIM5_CCER1_CC1P, and TIM5_OCPOLARITY_HIGH.

void TIM5_OC1PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM5 peripheral Preload Register on CCR1.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 578 of file stm8s_tim5.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM5_CCMR_OCxPE.

void TIM5_OC2Init | ( | TIM5_OCMode_TypeDef | TIM5_OCMode,
 |  | TIM5_OutputState_TypeDef | TIM5_OutputState,
 |  | uint16_t | TIM5_Pulse,
 |  | TIM5_OCPolarity_TypeDef | TIM5_OCPolarity
 | ) |  |

Initializes the TIM5 Channel2 according to the specified parameters.

Parameters:
TIM5_OCMode | specifies the Output Compare mode from TIM5_OCMode_TypeDef.
TIM5_OutputState | specifies the Output State from TIM5_OutputState_TypeDef.
TIM5_Pulse | specifies the Pulse width value.
TIM5_OCPolarity | specifies the Output Compare Polarity from TIM5_OCPolarity_TypeDef.
Return values:
None

Definition at line 141 of file stm8s_tim5.c.

References IS_TIM5_OC_MODE_OK, IS_TIM5_OC_POLARITY_OK, IS_TIM5_OUTPUT_STATE_OK, TIM5_CCER1_CC2E, TIM5_CCER1_CC2P, and TIM5_CCMR_OCM.

void TIM5_OC2PolarityConfig ( TIM5_OCPolarity_TypeDef TIM5_OCPolarity )

Configures the TIM5 Channel 2 polarity.

Parameters:
TIM5_OCPolarity specifies the OC2 Polarity. This parameter can be one of the following values:
  • TIM5_OCPOLARITY_LOW: Output Compare active low
  • TIM5_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 690 of file stm8s_tim5.c.

References IS_TIM5_OC_POLARITY_OK, TIM5_CCER1_CC2P, and TIM5_OCPOLARITY_HIGH.

void TIM5_OC2PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM5 peripheral Preload Register on CCR2.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 600 of file stm8s_tim5.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM5_CCMR_OCxPE.

void TIM5_OC3Init | ( | TIM5_OCMode_TypeDef | TIM5_OCMode,
 |  | TIM5_OutputState_TypeDef | TIM5_OutputState,
 |  | uint16_t | TIM5_Pulse,
 |  | TIM5_OCPolarity_TypeDef | TIM5_OCPolarity
 | ) |  |

Initializes the TIM5 Channel3 according to the specified parameters.

Parameters:
TIM5_OCMode | specifies the Output Compare mode from TIM5_OCMode_TypeDef.
TIM5_OutputState | specifies the Output State from TIM5_OutputState_TypeDef.
TIM5_Pulse | specifies the Pulse width value.
TIM5_OCPolarity | specifies the Output Compare Polarity from TIM5_OCPolarity_TypeDef.
Return values:
None

Definition at line 175 of file stm8s_tim5.c.

References IS_TIM5_OC_MODE_OK, IS_TIM5_OC_POLARITY_OK, IS_TIM5_OUTPUT_STATE_OK, TIM5_CCER2_CC3E, TIM5_CCER2_CC3P, and TIM5_CCMR_OCM.

void TIM5_OC3PolarityConfig ( TIM5_OCPolarity_TypeDef TIM5_OCPolarity )

Configures the TIM5 Channel 3 polarity.

Parameters:
TIM5_OCPolarity specifies the OC3 Polarity. This parameter can be one of the following values:
  • TIM5_OCPOLARITY_LOW: Output Compare active low
  • TIM5_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 714 of file stm8s_tim5.c.

References IS_TIM5_OC_POLARITY_OK, TIM5_CCER2_CC3P, and TIM5_OCPOLARITY_HIGH.

void TIM5_OC3PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM5 peripheral Preload Register on CCR3.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 622 of file stm8s_tim5.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM5_CCMR_OCxPE.

void TIM5_PrescalerConfig | ( | TIM5_Prescaler_TypeDef | Prescaler,
 |  | TIM5_PSCReloadMode_TypeDef | TIM5_PSCReloadMode
 | ) |  |

Configures the TIM5 Prescaler.

Parameters:
Prescaler specifies the Prescaler Register value This parameter can be one of the following values
  • TIM5_PRESCALER_1
  • TIM5_PRESCALER_2
  • TIM5_PRESCALER_4
  • TIM5_PRESCALER_8
  • TIM5_PRESCALER_16
  • TIM5_PRESCALER_32
  • TIM5_PRESCALER_64
  • TIM5_PRESCALER_128
  • TIM5_PRESCALER_256
  • TIM5_PRESCALER_512
  • TIM5_PRESCALER_1024
  • TIM5_PRESCALER_2048
  • TIM5_PRESCALER_4096
  • TIM5_PRESCALER_8192
  • TIM5_PRESCALER_16384
  • TIM5_PRESCALER_32768
TIM5_PSCReloadMode specifies the TIM5 Prescaler Reload mode. This parameter can be one of the following values
  • TIM5_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded immediately.
  • TIM5_PSCRELOADMODE_UPDATE: The Prescaler is loaded at the update event.
Return values:
None

Definition at line 479 of file stm8s_tim5.c.

References IS_TIM5_PRESCALER_OK, and IS_TIM5_PRESCALER_RELOAD_OK.

void TIM5_PWMIConfig | ( | TIM5_Channel_TypeDef | TIM5_Channel,
 |  | TIM5_ICPolarity_TypeDef | TIM5_ICPolarity,
 |  | TIM5_ICSelection_TypeDef | TIM5_ICSelection,
 |  | TIM5_ICPSC_TypeDef | TIM5_ICPrescaler,
 |  | uint8_t | TIM5_ICFilter
 | ) |  |

Configures the TIM5 peripheral in PWM Input Mode according to the specified parameters.

Parameters:
TIM5_Channel | specifies the Input Capture Channel from TIM5_Channel_TypeDef.
TIM5_ICPolarity | specifies the Input Capture Polarity from TIM5_ICPolarity_TypeDef.
TIM5_ICSelection | specifies theInput Capture Selection from TIM5_ICSelection_TypeDef.
TIM5_ICPrescaler | specifies the Input Capture Prescaler from TIM5_ICPSC_TypeDef.
TIM5_ICFilter | specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
Return values:
None

Definition at line 261 of file stm8s_tim5.c.

References IS_TIM5_IC_POLARITY_OK, IS_TIM5_IC_PRESCALER_OK, IS_TIM5_IC_SELECTION_OK, IS_TIM5_PWMI_CHANNEL_OK, TI1_Config(), TI2_Config(), TIM5_CHANNEL_1, TIM5_ICPOLARITY_FALLING, TIM5_ICPOLARITY_RISING, TIM5_ICSELECTION_DIRECTTI, TIM5_ICSELECTION_INDIRECTTI, TIM5_SetIC1Prescaler(), and TIM5_SetIC2Prescaler().

void TIM5_SelectInputTrigger ( TIM5_TS_TypeDef TIM5_InputTriggerSource )

Selects the TIM5 Input Trigger source.

Parameters:
TIM5_InputTriggerSource : Specifies Input Trigger source. This parameter can be one of the TIM5_TS_TypeDef enumeration.
Return values:
None

Definition at line 1331 of file stm8s_tim5.c.

References IS_TIM5_TRIGGER_SELECTION_OK, and TIM5_SMCR_TS.

void TIM5_SelectOCxM | ( | TIM5_Channel_TypeDef | TIM5_Channel,
 |  | TIM5_OCMode_TypeDef | TIM5_OCMode
 | ) |  |

Selects the TIM5 Output Compare Mode.

This function disables the selected channel before changing the Output Compare Mode. User has to enable this channel using TIM5_CCxCmd and TIM5_CCxNCmd functions.

Parameters:
TIM5_Channel specifies the TIM5 Channel. This parameter can be one of the following values:
  • TIM5_Channel1: TIM5 Channel1
  • TIM5_Channel2: TIM5 Channel2
  • TIM5_Channel3: TIM5 Channel3
TIM5_OCMode specifies the TIM5 Output Compare Mode. This parameter can be one of the following values:
  • TIM5_OCMODE_TIMING
  • TIM5_OCMODE_ACTIVE
  • TIM5_OCMODE_TOGGLE
  • TIM5_OCMODE_PWM1
  • TIM5_OCMODE_PWM2
  • TIM5_FORCEDACTION_ACTIVE
  • TIM5_FORCEDACTION_INACTIVE
Return values:
None

Definition at line 806 of file stm8s_tim5.c.

References IS_TIM5_CHANNEL_OK, IS_TIM5_OCM_OK, TIM5_CCER1_CC1E, TIM5_CCER1_CC2E, TIM5_CCER2_CC3E, TIM5_CCMR_OCM, TIM5_CHANNEL_1, and TIM5_CHANNEL_2.

void TIM5_SelectOnePulseMode ( TIM5_OPMode_TypeDef TIM5_OPMode )

Selects the TIM5’s One Pulse Mode.

Parameters:
TIM5_OPMode specifies the OPM Mode to be used. This parameter can be one of the following values
  • TIM5_OPMODE_SINGLE
  • TIM5_OPMODE_REPETITIVE
Return values:
None

Definition at line 435 of file stm8s_tim5.c.

References IS_TIM5_OPM_MODE_OK, TIM5_CR1_OPM, and TIM5_OPMODE_REPETITIVE.

void TIM5_SelectOutputTrigger ( TIM5_TRGOSource_TypeDef TIM5_TRGOSource )

Selects the TIM5 Trigger Output Mode.

Parameters:
TIM5_TRGOSource : Specifies the Trigger Output source. This parameter can be one of the TIM5_TRGOSource_TypeDef enumeration.
Return values:
None

Definition at line 1283 of file stm8s_tim5.c.

References IS_TIM5_TRGO_SOURCE_OK, and TIM5_CR2_MMS.

void TIM5_SelectSlaveMode ( TIM5_SlaveMode_TypeDef TIM5_SlaveMode )

Selects the TIM5 Slave Mode.

Parameters:
TIM5_SlaveMode : Specifies the TIM5 Slave Mode. This parameter can be one of the TIM5_SlaveMode_TypeDef enumeration.
Return values:
None

Definition at line 1307 of file stm8s_tim5.c.

References IS_TIM5_SLAVE_MODE_OK, and TIM5_SMCR_SMS.

void TIM5_SetAutoreload ( uint16_t Autoreload )

Sets the TIM5 Autoreload Register value.

Parameters:
Autoreload specifies the Autoreload register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 860 of file stm8s_tim5.c.

void TIM5_SetCompare1 ( uint16_t Compare1 )

Sets the TIM5 Capture Compare1 Register value.

Parameters:
Compare1 specifies the Capture Compare1 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 873 of file stm8s_tim5.c.

void TIM5_SetCompare2 ( uint16_t Compare2 )

Sets the TIM5 Capture Compare2 Register value.

Parameters:
Compare2 specifies the Capture Compare2 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 886 of file stm8s_tim5.c.

void TIM5_SetCompare3 ( uint16_t Compare3 )

Sets the TIM5 Capture Compare3 Register value.

Parameters:
Compare3 specifies the Capture Compare3 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 899 of file stm8s_tim5.c.

void TIM5_SetCounter ( uint16_t Counter )

Sets the TIM5 Counter Register value.

Parameters:
Counter specifies the Counter register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 847 of file stm8s_tim5.c.

void TIM5_SetIC1Prescaler ( TIM5_ICPSC_TypeDef TIM5_IC1Prescaler )

Sets the TIM5 Input Capture 1 prescaler.

Parameters:
TIM5_IC1Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:
  • TIM5_ICPSC_DIV1: no prescaler
  • TIM5_ICPSC_DIV2: capture is done once every 2 events
  • TIM5_ICPSC_DIV4: capture is done once every 4 events
  • TIM5_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 916 of file stm8s_tim5.c.

References IS_TIM5_IC_PRESCALER_OK, and TIM5_CCMR_ICxPSC.

Referenced by TIM5_ICInit(), and TIM5_PWMIConfig().

void TIM5_SetIC2Prescaler ( TIM5_ICPSC_TypeDef TIM5_IC2Prescaler )

Sets the TIM5 Input Capture 2 prescaler.

Parameters:
TIM5_IC2Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:
  • TIM5_ICPSC_DIV1: no prescaler
  • TIM5_ICPSC_DIV2: capture is done once every 2 events
  • TIM5_ICPSC_DIV4: capture is done once every 4 events
  • TIM5_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 936 of file stm8s_tim5.c.

References IS_TIM5_IC_PRESCALER_OK, and TIM5_CCMR_ICxPSC.

Referenced by TIM5_ICInit(), and TIM5_PWMIConfig().

void TIM5_SetIC3Prescaler ( TIM5_ICPSC_TypeDef TIM5_IC3Prescaler )

Sets the TIM5 Input Capture 3 prescaler.

Parameters:
TIM5_IC3Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:
  • TIM5_ICPSC_DIV1: no prescaler
  • TIM5_ICPSC_DIV2: capture is done once every 2 events
  • TIM5_ICPSC_DIV4: capture is done once every 4 events
  • TIM5_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 956 of file stm8s_tim5.c.

References IS_TIM5_IC_PRESCALER_OK, and TIM5_CCMR_ICxPSC.

Referenced by TIM5_ICInit().

void TIM5_TimeBaseInit | ( | TIM5_Prescaler_TypeDef | TIM5_Prescaler,
 |  | uint16_t | TIM5_Period
 | ) |  |

Initializes the TIM5 Time Base Unit according to the specified parameters.

Parameters:
TIM5_Prescaler | specifies the Prescaler from TIM5_Prescaler_TypeDef.
TIM5_Period | specifies the Period value.
Return values:
None

Definition at line 90 of file stm8s_tim5.c.

void TIM5_UpdateDisableConfig ( FunctionalState NewState )

Enables or Disables the TIM5 Update event.

Parameters:
NewState new state of the TIM5 peripheral Preload register.This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 387 of file stm8s_tim5.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM5_CR1_UDIS.

void TIM5_UpdateRequestConfig ( TIM5_UpdateSource_TypeDef TIM5_UpdateSource )

Selects the TIM5 Update Request Interrupt source.

Parameters:
TIM5_UpdateSource specifies the Update source. This parameter can be one of the following values
  • TIM5_UPDATESOURCE_REGULAR
  • TIM5_UPDATESOURCE_GLOBAL
Return values:
None

Definition at line 411 of file stm8s_tim5.c.

References IS_TIM5_UPDATE_SOURCE_OK, TIM5_CR1_URS, and TIM5_UPDATESOURCE_GLOBAL.


STM8S/A Standard Peripherals Drivers: TIM6_Public_Functions

Functions
TIM6_Public_Functions
STM8S_StdPeriph_Driver

Functions

void | TIM6_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM6 peripheral Preload register on ARR.
void | TIM6_ClearFlag (TIM6_FLAG_TypeDef TIM6_FLAG)
Clears the TIM’s pending flags.
void | TIM6_ClearITPendingBit (TIM6_IT_TypeDef TIM6_IT)
Clears the TIM6's interrupt pending bits.
void | TIM6_Cmd (FunctionalState NewState)
Enables or disables the TIM6 peripheral.
void | TIM6_DeInit (void)
Deinitializes the TIM6 peripheral registers to their default reset values.
void | TIM6_GenerateEvent (TIM6_EventSource_TypeDef TIM6_EventSource)
Configures the TIM6 event to be generated by software.
uint8_t | TIM6_GetCounter (void)
Gets the TIM6 Counter value.
FlagStatus | TIM6_GetFlagStatus (TIM6_FLAG_TypeDef TIM6_FLAG)
Checks whether the specified TIM6 flag is set or not.
ITStatus | TIM6_GetITStatus (TIM6_IT_TypeDef TIM6_IT)
Checks whether the TIM6 interrupt has occurred or not.
TIM6_Prescaler_TypeDef | TIM6_GetPrescaler (void)
Gets the TIM6 Prescaler value.
void | TIM6_InternalClockConfig (void)
Enables the TIM6 internal Clock.
void | TIM6_ITConfig (TIM6_IT_TypeDef TIM6_IT, FunctionalState NewState)
Enables or disables the specified TIM6 interrupts.
void | TIM6_PrescalerConfig (TIM6_Prescaler_TypeDef Prescaler, TIM6_PSCReloadMode_TypeDef TIM6_PSCReloadMode)
Configures the TIM6 Prescaler.
void | TIM6_SelectInputTrigger (TIM6_TS_TypeDef TIM6_InputTriggerSource)
Selects the TIM6 Input Trigger source.
void | TIM6_SelectMasterSlaveMode (FunctionalState NewState)
Sets or Resets the TIM6 Master/Slave Mode.
void | TIM6_SelectOnePulseMode (TIM6_OPMode_TypeDef TIM6_OPMode)
Selects the TIM6’s One Pulse Mode.
void | TIM6_SelectOutputTrigger (TIM6_TRGOSource_TypeDef TIM6_TRGOSource)
Selects the TIM6 Trigger Output Mode.
void | TIM6_SelectSlaveMode (TIM6_SlaveMode_TypeDef TIM6_SlaveMode)
Selects the TIM6 Slave Mode.
void | TIM6_SetAutoreload (uint8_t Autoreload)
Sets the TIM6 Autoreload Register value.
void | TIM6_SetCounter (uint8_t Counter)
Sets the TIM6 Counter Register value.
void | TIM6_TimeBaseInit (TIM6_Prescaler_TypeDef TIM6_Prescaler, uint8_t TIM6_Period)
Initializes the TIM6 Time Base Unit according to the specified parameters.
void | TIM6_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM6 Update event.
void | TIM6_UpdateRequestConfig (TIM6_UpdateSource_TypeDef TIM6_UpdateSource)
Selects the TIM6 Update Request Interrupt source.

Function Documentation

void TIM6_ARRPreloadConfig ( FunctionalState NewState )

Enables or disables TIM6 peripheral Preload register on ARR.

Parameters:
NewState : The new state of the TIM6 peripheral Preload register. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 205 of file stm8s_tim6.c.

References ENABLE, IS_FUNCTIONALSTATE_OK, and TIM6_CR1_ARPE.

void TIM6_ClearFlag ( TIM6_FLAG_TypeDef TIM6_FLAG )

Clears the TIM’s pending flags.

Parameters:
TIM6_FLAG : Specifies the flag to clear. This parameter can be one of the TIM6_FLAG_TypeDef enumeration.
Return values:
None

Definition at line 304 of file stm8s_tim6.c.

References IS_TIM6_CLEAR_FLAG_OK.

void TIM6_ClearITPendingBit ( TIM6_IT_TypeDef TIM6_IT )

Clears the TIM6's interrupt pending bits.

Parameters:
TIM6_IT : Specifies the pending bit to clear. This parameter can be one of the TIM6_IT_TypeDef enumeration.
Return values:
None

Definition at line 388 of file stm8s_tim6.c.

References IS_TIM6_IT_OK.

void TIM6_Cmd ( FunctionalState NewState )

Enables or disables the TIM6 peripheral.

Parameters:
NewState : The new state of the TIM6 peripheral. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 88 of file stm8s_tim6.c.

References ENABLE, IS_FUNCTIONALSTATE_OK, and TIM6_CR1_CEN.

void TIM6_DeInit ( void )

Deinitializes the TIM6 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 52 of file stm8s_tim6.c.

References TIM6_ARR_RESET_VALUE, TIM6_CNTR_RESET_VALUE, TIM6_CR1_RESET_VALUE, TIM6_CR2_RESET_VALUE, TIM6_IER_RESET_VALUE, TIM6_PSCR_RESET_VALUE, TIM6_SMCR_RESET_VALUE, and TIM6_SR1_RESET_VALUE.

void TIM6_GenerateEvent ( TIM6_EventSource_TypeDef TIM6_EventSource )

Configures the TIM6 event to be generated by software.

Parameters:
TIM6_EventSource : Specifies the event source. This parameter can be one of the TIM6_EventSource_TypeDef enumeration.
Return values:
None

Definition at line 348 of file stm8s_tim6.c.

References IS_TIM6_EVENT_SOURCE_OK.

uint8_t TIM6_GetCounter ( void )

Gets the TIM6 Counter value.

Parameters:
None
Return values:
uint8_t,: Counter Register value.

Definition at line 250 of file stm8s_tim6.c.

FlagStatus TIM6_GetFlagStatus ( TIM6_FLAG_TypeDef TIM6_FLAG )

Checks whether the specified TIM6 flag is set or not.

Parameters:
TIM6_FLAG : Specifies the flag to check. This parameter can be one of the TIM6_FLAG_TypeDef enumeration.
Return values:
FlagStatus : The new state of TIM6_FLAG. This parameter can be any of the FlagStatus enumeration.

Definition at line 364 of file stm8s_tim6.c.

References IS_TIM6_GET_FLAG_OK, RESET, and SET.

ITStatus TIM6_GetITStatus ( TIM6_IT_TypeDef TIM6_IT )

Checks whether the TIM6 interrupt has occurred or not.

Parameters:
TIM6_IT : Specifies the TIM6 interrupt source to check. This parameter can be one of the TIM6_IT_TypeDef enumeration.
Return values:
ITStatus : The new state of the TIM6_IT. This parameter can be any of the ITStatus enumeration.

Definition at line 319 of file stm8s_tim6.c.

References IS_TIM6_GET_IT_OK, RESET, and SET.

TIM6_Prescaler_TypeDef TIM6_GetPrescaler ( void )

Gets the TIM6 Prescaler value.

Parameters:
None
Return values:
TIM6_Prescaler_TypeDef : Prescaler Register configuration value.

Definition at line 263 of file stm8s_tim6.c.

void TIM6_InternalClockConfig ( void )

Enables the TIM6 internal Clock.

Parameters:
None
Return values:
None

Definition at line 471 of file stm8s_tim6.c.

References TIM6_SMCR_SMS.

void TIM6_ITConfig | ( | TIM6_IT_TypeDef | TIM6_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified TIM6 interrupts.

Parameters:
TIM6_IT | : Specifies the TIM6 interrupts sources to be enabled or disabled. This parameter can be any combination of the TIM6_IT_TypeDef enumeration.
NewState | : The new state of the TIM6 peripheral. This parameter can be any of the FunctionalState enumeration.
Return values:
None
Required preconditions:
If QST option bit is enabled, the TIM6 Interrupt vector will be mapped on IRQ number 2 (irq0). Otherwise, it will be mapped on IRQ number 27 (irq25).

Definition at line 280 of file stm8s_tim6.c.

References ENABLE, IS_FUNCTIONALSTATE_OK, and IS_TIM6_IT_OK.

void TIM6_PrescalerConfig | ( | TIM6_Prescaler_TypeDef | Prescaler,
 |  | TIM6_PSCReloadMode_TypeDef | TIM6_PSCReloadMode
 | ) |  |

Configures the TIM6 Prescaler.

Parameters:
Prescaler | : Specifies the Prescaler Register value This parameter can be one of the TIM6_Prescaler_TypeDef enumeration.
TIM6_PSCReloadMode | : Specifies the TIM6 Prescaler Reload mode. This parameter can be one of the TIM6_PSCReloadMode_TypeDef enumeration.
Return values:
None

Definition at line 178 of file stm8s_tim6.c.

References IS_TIM6_PRESCALER_OK, IS_TIM6_PRESCALER_RELOAD_OK, TIM6_EGR_UG, and TIM6_PSCRELOADMODE_IMMEDIATE.

void TIM6_SelectInputTrigger ( TIM6_TS_TypeDef TIM6_InputTriggerSource )

Selects the TIM6 Input Trigger source.

Parameters:
TIM6_InputTriggerSource : Specifies Input Trigger source. This parameter can be one of the TIM6_TS_TypeDef enumeration.
Return values:
None

Definition at line 450 of file stm8s_tim6.c.

References IS_TIM6_TRIGGER_SELECTION_OK, and TIM6_SMCR_TS.

void TIM6_SelectMasterSlaveMode ( FunctionalState NewState )

Sets or Resets the TIM6 Master/Slave Mode.

Parameters:
NewState : The new state of the synchronization between TIM6 and its slaves (through TRGO). This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 428 of file stm8s_tim6.c.

References ENABLE, IS_FUNCTIONALSTATE_OK, and TIM6_SMCR_MSM.

void TIM6_SelectOnePulseMode ( TIM6_OPMode_TypeDef TIM6_OPMode )

Selects the TIM6’s One Pulse Mode.

Parameters:
TIM6_OPMode : Specifies the OPM Mode to be used. This parameter can be one of the TIM6_OPMode_TypeDef enumeration.
Return values:
None

Definition at line 154 of file stm8s_tim6.c.

References IS_TIM6_OPM_MODE_OK, TIM6_CR1_OPM, and TIM6_OPMODE_SINGLE.

void TIM6_SelectOutputTrigger ( TIM6_TRGOSource_TypeDef TIM6_TRGOSource )

Selects the TIM6 Trigger Output Mode.

Parameters:
TIM6_TRGOSource : Specifies the Trigger Output source. This parameter can be one of the TIM6_TRGOSource_TypeDef enumeration.
Return values:
None

Definition at line 403 of file stm8s_tim6.c.

References IS_TIM6_TRGO_SOURCE_OK, and TIM6_CR2_MMS.

void TIM6_SelectSlaveMode ( TIM6_SlaveMode_TypeDef TIM6_SlaveMode )

Selects the TIM6 Slave Mode.

Parameters:
TIM6_SlaveMode : Specifies the TIM6 Slave Mode. This parameter can be one of the TIM6_SlaveMode_TypeDef enumeration.
Return values:
None

Definition at line 483 of file stm8s_tim6.c.

References IS_TIM6_SLAVE_MODE_OK, and TIM6_SMCR_SMS.

void TIM6_SetAutoreload ( uint8_t Autoreload )

Sets the TIM6 Autoreload Register value.

Parameters:
Autoreload : Specifies the Autoreload register new value. This parameter is between 0x00 and 0xFF.
Return values:
None

Definition at line 239 of file stm8s_tim6.c.

void TIM6_SetCounter ( uint8_t Counter )

Sets the TIM6 Counter Register value.

Parameters:
Counter : Specifies the Counter register new value. This parameter is between 0x00 and 0xFF.
Return values:
None

Definition at line 227 of file stm8s_tim6.c.

void TIM6_TimeBaseInit | ( | TIM6_Prescaler_TypeDef | TIM6_Prescaler,
 |  | uint8_t | TIM6_Period
 | ) |  |

Initializes the TIM6 Time Base Unit according to the specified parameters.

Parameters:
TIM6_Prescaler | : This parameter can be any of the TIM6_Prescaler_TypeDef enumeration.
TIM6_Period | : This parameter must be a value between 0x00 and 0xFF.
Return values:
None

Definition at line 71 of file stm8s_tim6.c.

References IS_TIM6_PRESCALER_OK.

void TIM6_UpdateDisableConfig ( FunctionalState NewState )

Enables or Disables the TIM6 Update event.

Parameters:
NewState : The new state of the TIM6 peripheral Preload register. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 110 of file stm8s_tim6.c.

References ENABLE, IS_FUNCTIONALSTATE_OK, and TIM6_CR1_UDIS.

void TIM6_UpdateRequestConfig ( TIM6_UpdateSource_TypeDef TIM6_UpdateSource )

Selects the TIM6 Update Request Interrupt source.

Parameters:
TIM6_UpdateSource : Specifies the Update source. This parameter can be one of the TIM6_UpdateSource_TypeDef enumeration.
Return values:
None

Definition at line 132 of file stm8s_tim6.c.

References IS_TIM6_UPDATE_SOURCE_OK, TIM6_CR1_URS, and TIM6_UPDATESOURCE_REGULAR.


STM8S/A Standard Peripherals Drivers: UART1_Public_Functions

Functions
UART1_Public_Functions
STM8S_StdPeriph_Driver

Functions

void | UART1_ClearFlag (UART1_Flag_TypeDef UART1_FLAG)
Clears the UART1 flags.
void | UART1_ClearITPendingBit (UART1_IT_TypeDef UART1_IT)
Clears the UART1 pending flags.
void | UART1_Cmd (FunctionalState NewState)
Enable the UART1 peripheral.
void | UART1_DeInit (void)
Deinitializes the UART peripheral.
FlagStatus | UART1_GetFlagStatus (UART1_Flag_TypeDef UART1_FLAG)
Checks whether the specified UART1 flag is set or not.
ITStatus | UART1_GetITStatus (UART1_IT_TypeDef UART1_IT)
Checks whether the specified UART1 interrupt has occurred or not.
void | UART1_HalfDuplexCmd (FunctionalState NewState)
Enables or disables the UART’s Half Duplex communication.
void | UART1_Init (uint32_t BaudRate, UART1_WordLength_TypeDef WordLength, UART1_StopBits_TypeDef StopBits, UART1_Parity_TypeDef Parity, UART1_SyncMode_TypeDef SyncMode, UART1_Mode_TypeDef Mode)
Initializes the UART1 according to the specified parameters.
void | UART1_IrDACmd (FunctionalState NewState)
Enables or disables the UART’s IrDA interface.
void | UART1_IrDAConfig (UART1_IrDAMode_TypeDef UART1_IrDAMode)
Configures the UART’s IrDA interface.
void | UART1_ITConfig (UART1_IT_TypeDef UART1_IT, FunctionalState NewState)
Enables or disables the specified USART interrupts.
void | UART1_LINBreakDetectionConfig (UART1_LINBreakDetectionLength_TypeDef UART1_LINBreakDetectionLength)
Sets the UART1 LIN Break detection length.
void | UART1_LINCmd (FunctionalState NewState)
Enables or disables the UART1’s LIN mode.
uint8_t | UART1_ReceiveData8 (void)
Returns the most recent received data by the UART1 peripheral.
uint16_t | UART1_ReceiveData9 (void)
Returns the most recent received data by the UART1 peripheral.
void | UART1_ReceiverWakeUpCmd (FunctionalState NewState)
Determines if the UART1 is in mute mode or not.
void | UART1_SendBreak (void)
Transmits break characters.
void | UART1_SendData8 (uint8_t Data)
Transmits 8 bit data through the UART1 peripheral.
void | UART1_SendData9 (uint16_t Data)
Transmits 9 bit data through the UART peripheral.
void | UART1_SetAddress (uint8_t UART1_Address)
Sets the address of the UART1 node.
void | UART1_SetGuardTime (uint8_t UART1_GuardTime)
Sets the specified UART guard time.
void | UART1_SetPrescaler (uint8_t UART1_Prescaler)
Sets the system clock prescaler.
void | UART1_SmartCardCmd (FunctionalState NewState)
Enables or disables the UART1 Smart Card mode.
void | UART1_SmartCardNACKCmd (FunctionalState NewState)
Enables or disables NACK transmission.
void | UART1_WakeUpConfig (UART1_WakeUp_TypeDef UART1_WakeUp)
Selects the UART1 WakeUp method.

Function Documentation

void UART1_ClearFlag ( UART1_Flag_TypeDef UART1_FLAG )

Clears the UART1 flags.

Parameters:
UART1_FLAG specifies the flag to clear This parameter can be any combination of the following values:
  • UART1_FLAG_LBDF: LIN Break detection flag.
  • UART1_FLAG_RXNE: Receive data register not empty flag.
Note:
  • PE (Parity error), FE (Framing error), NE (Noise error), OR (OverRun error) and IDLE (Idle line detected) flags are cleared by software sequence: a read operation to UART1_SR register (UART1_GetFlagStatus())followed by a read operation to UART1_DR register(UART1_ReceiveData8() or UART1_ReceiveData9()).
  • RXNE flag can be also cleared by a read to the UART1_DR register (UART1_ReceiveData8()or UART1_ReceiveData9()).
  • TC flag can be also cleared by software sequence: a read operation to UART1_SR register (UART1_GetFlagStatus()) followed by a write operation to UART1_DR register (UART1_SendData8() or UART1_SendData9()).
  • TXE flag is cleared only by a write to the UART1_DR register (UART1_SendData8() or UART1_SendData9()).
  • SBK flag is cleared during the stop bit of break.
    Return values:
    None

Definition at line 646 of file stm8s_uart1.c.

References IS_UART1_CLEAR_FLAG_OK, UART1_CR4_LBDF, UART1_FLAG_RXNE, and UART1_SR_RXNE.

void UART1_ClearITPendingBit ( UART1_IT_TypeDef UART1_IT )

Clears the UART1 pending flags.

Parameters:
UART1_IT specifies the pending bit to clear This parameter can be one of the following values:
  • UART1_IT_LBDF: LIN Break detection interrupt
  • UART1_IT_RXNE: Receive Data register not empty interrupt.
Note:
  • PE (Parity error), FE (Framing error), NE (Noise error), OR (OverRun error) and IDLE (Idle line detected) pending bits are cleared by software sequence: a read operation to UART1_SR register (UART1_GetITStatus()) followed by a read operation to UART1_DR register (UART1_ReceiveData8() or UART1_ReceiveData9()).
  • RXNE pending bit can be also cleared by a read to the UART1_DR register (UART1_ReceiveData8() or UART1_ReceiveData9()).
  • TC (Transmit complete) pending bit can be cleared by software sequence: a read operation to UART1_SR register (UART1_GetITStatus()) followed by a write operation to UART1_DR register (UART1_SendData8() or UART1_SendData9()).
  • TXE pending bit is cleared only by a write to the UART1_DR register (UART1_SendData8() or UART1_SendData9()).
    Return values:
    None

Definition at line 775 of file stm8s_uart1.c.

References IS_UART1_CLEAR_IT_OK, UART1_CR4_LBDF, UART1_IT_RXNE, and UART1_SR_RXNE.

void UART1_Cmd ( FunctionalState NewState )

Enable the UART1 peripheral.

Parameters:
NewState : The new state of the UART Communication. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 184 of file stm8s_uart1.c.

References DISABLE, and UART1_CR1_UARTD.

void UART1_DeInit ( void )

Deinitializes the UART peripheral.

Parameters:
None
Return values:
None

Definition at line 53 of file stm8s_uart1.c.

References UART1_BRR1_RESET_VALUE, UART1_BRR2_RESET_VALUE, UART1_CR1_RESET_VALUE, UART1_CR2_RESET_VALUE, UART1_CR3_RESET_VALUE, UART1_CR4_RESET_VALUE, UART1_CR5_RESET_VALUE, UART1_GTR_RESET_VALUE, and UART1_PSCR_RESET_VALUE.

FlagStatus UART1_GetFlagStatus ( UART1_Flag_TypeDef UART1_FLAG )

Checks whether the specified UART1 flag is set or not.

Parameters:
UART1_FLAG specifies the flag to check. This parameter can be any of the UART1_Flag_TypeDef enumeration.
Return values:
FlagStatus (SET or RESET)

Definition at line 568 of file stm8s_uart1.c.

References IS_UART1_FLAG_OK, RESET, SET, UART1_FLAG_LBDF, and UART1_FLAG_SBK.

ITStatus UART1_GetITStatus ( UART1_IT_TypeDef UART1_IT )

Checks whether the specified UART1 interrupt has occurred or not.

Parameters:
UART1_IT,: Specifies the UART1 interrupt pending bit to check. This parameter can be one of the following values:
  • UART1_IT_LBDF: LIN Break detection interrupt
  • UART1_IT_TXE: Transmit Data Register empty interrupt
  • UART1_IT_TC: Transmission complete interrupt
  • UART1_IT_RXNE: Receive Data register not empty interrupt
  • UART1_IT_IDLE: Idle line detection interrupt
  • UART1_IT_OR: OverRun Error interrupt
  • UART1_IT_PE: Parity Error interrupt
Return values:
The new state of UART1_IT (SET or RESET).

Definition at line 675 of file stm8s_uart1.c.

References IS_UART1_GET_IT_OK, RESET, SET, UART1_IT_LBDF, and UART1_IT_PE.

void UART1_HalfDuplexCmd ( FunctionalState NewState )

Enables or disables the UART’s Half Duplex communication.

Parameters:
NewState new state of the UART Communication. This parameter can be: ENABLE or DISABLE.
Return values:
None

< UART1 Half Duplex Enable

< UART1 Half Duplex Disable

Definition at line 265 of file stm8s_uart1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART1_CR5_HDSEL.

void UART1_Init | ( | uint32_t | BaudRate,
 |  | UART1_WordLength_TypeDef | WordLength,
 |  | UART1_StopBits_TypeDef | StopBits,
 |  | UART1_Parity_TypeDef | Parity,
 |  | UART1_SyncMode_TypeDef | SyncMode,
 |  | UART1_Mode_TypeDef | Mode
 | ) |  |

Initializes the UART1 according to the specified parameters.

Note:
Configure in Push Pull or Open Drain mode the Tx pin by setting the correct I/O Port register according the product package and line configuration
Parameters:
BaudRate,: The baudrate.
WordLength : This parameter can be any of the UART1_WordLength_TypeDef enumeration.
StopBits,: This parameter can be any of the UART1_StopBits_TypeDef enumeration.
Parity,: This parameter can be any of the UART1_Parity_TypeDef enumeration.
SyncMode,: This parameter can be any of the UART1_SyncMode_TypeDef values.
Mode,: This parameter can be any of the UART1_Mode_TypeDef values
Return values:
None

Definition at line 90 of file stm8s_uart1.c.

References CLK_GetClockFreq(), IS_UART1_BAUDRATE_OK, IS_UART1_MODE_OK, IS_UART1_PARITY_OK, IS_UART1_STOPBITS_OK, IS_UART1_SYNCMODE_OK, IS_UART1_WORDLENGTH_OK, UART1_BRR1_DIVM, UART1_BRR2_DIVF, UART1_BRR2_DIVM, UART1_CR1_M, UART1_CR1_PCEN, UART1_CR1_PS, UART1_CR2_REN, UART1_CR2_TEN, UART1_CR3_CKEN, UART1_CR3_CPHA, UART1_CR3_CPOL, UART1_CR3_LBCL, UART1_CR3_STOP, UART1_MODE_RX_ENABLE, UART1_MODE_TX_ENABLE, and UART1_SYNCMODE_CLOCK_DISABLE.

void UART1_IrDACmd ( FunctionalState NewState )

Enables or disables the UART’s IrDA interface.

Parameters:
NewState new state of the IrDA mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 305 of file stm8s_uart1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART1_CR5_IREN.

void UART1_IrDAConfig ( UART1_IrDAMode_TypeDef UART1_IrDAMode )

Configures the UART’s IrDA interface.

Parameters:
UART1_IrDAMode specifies the IrDA mode. This parameter can be any of the UART1_IrDAMode_TypeDef values.
Return values:
None

Definition at line 285 of file stm8s_uart1.c.

References IS_UART1_IRDAMODE_OK, UART1_CR5_IRLP, and UART1_IRDAMODE_NORMAL.

void UART1_ITConfig | ( | UART1_IT_TypeDef | UART1_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified USART interrupts.

Parameters:
UART1_IT specifies the USART interrupt sources to be enabled or disabled. This parameter can be one of the following values:
  • UART1_IT_TXE: Transmit Data Register empty interrupt
  • UART1_IT_TC: Transmission complete interrupt
  • UART1_IT_RXNE_OR: Receive Data register not empty and Overrun interrupt
  • UART1_IT_IDLE: Idle line detection interrupt
  • USRT1_IT_ERR: Error interrupt
NewState new state of the specified USART interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

< Enable the Interrupt bits according to UART1_IT mask

< Disable the interrupt bits according to UART1_IT mask

Definition at line 211 of file stm8s_uart1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and IS_UART1_CONFIG_IT_OK.

void UART1_LINBreakDetectionConfig ( UART1_LINBreakDetectionLength_TypeDef UART1_LINBreakDetectionLength )

Sets the UART1 LIN Break detection length.

Parameters:
UART1_LINBreakDetectionLength specifies the LIN break detection length. This parameter can be any of the UART1_LINBreakDetectionLength_TypeDef values.
Return values:
None

Definition at line 329 of file stm8s_uart1.c.

References IS_UART1_LINBREAKDETECTIONLENGTH_OK, UART1_CR4_LBDL, and UART1_LINBREAKDETECTIONLENGTH_10BITS.

void UART1_LINCmd ( FunctionalState NewState )

Enables or disables the UART1’s LIN mode.

Parameters:
NewState is new state of the UART1 LIN mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 349 of file stm8s_uart1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART1_CR3_LINEN.

uint8_t UART1_ReceiveData8 ( void )

Returns the most recent received data by the UART1 peripheral.

Parameters:
None
Return values:
The received data.

Definition at line 451 of file stm8s_uart1.c.

uint16_t UART1_ReceiveData9 ( void )

Returns the most recent received data by the UART1 peripheral.

Parameters:
None
Return values:
The received data.

Definition at line 461 of file stm8s_uart1.c.

References UART1_CR1_R8.

void UART1_ReceiverWakeUpCmd ( FunctionalState NewState )

Determines if the UART1 is in mute mode or not.

Parameters:
NewState,: new state of the UART1 mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 430 of file stm8s_uart1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART1_CR2_RWU.

void UART1_SendBreak ( void )

Transmits break characters.

Parameters:
None
Return values:
None

Definition at line 501 of file stm8s_uart1.c.

References UART1_CR2_SBK.

void UART1_SendData8 ( uint8_t Data )

Transmits 8 bit data through the UART1 peripheral.

Parameters:
Data,: The data to transmit.
Return values:
None

Definition at line 474 of file stm8s_uart1.c.

void UART1_SendData9 ( uint16_t Data )

Transmits 9 bit data through the UART peripheral.

Parameters:
Data : The data to transmit. This parameter should be lower than 0x1FF.
Return values:
None

< Clear the transmit data bit 8 [8]

< Write the transmit data bit [8]

< Write the transmit data bit [0:7]

Definition at line 486 of file stm8s_uart1.c.

References UART1_CR1_T8.

void UART1_SetAddress ( uint8_t UART1_Address )

Sets the address of the UART1 node.

Parameters:
UART1_Address,: Indicates the address of the UART1 node.
Return values:
None

Definition at line 511 of file stm8s_uart1.c.

References IS_UART1_ADDRESS_OK, and UART1_CR4_ADD.

void UART1_SetGuardTime ( uint8_t UART1_GuardTime )

Sets the specified UART guard time.

Note:
SmartCard Mode should be Enabled
Parameters:
UART1_GuardTime,: specifies the guard time.
Return values:
None

Definition at line 528 of file stm8s_uart1.c.

void UART1_SetPrescaler ( uint8_t UART1_Prescaler )

Sets the system clock prescaler.

Note:
IrDA Low Power mode or smartcard mode should be enabled
This function is related to SmartCard and IrDa mode.
Parameters:
UART1_Prescaler,: specifies the prescaler clock. This parameter can be one of the following values:
IrDA Low Power Mode
The clock source is divided by the value given in the register (8 bits)
  • 0000 0000 Reserved
  • 0000 0001 divides the clock source by 1
  • 0000 0010 divides the clock source by 2
  • ...
Smart Card Mode
The clock source is divided by the value given in the register (5 significant bits) multiplied by 2
  • 0 0000 Reserved
  • 0 0001 divides the clock source by 2
  • 0 0010 divides the clock source by 4
  • 0 0011 divides the clock source by 6
  • ...
Return values:
None

Definition at line 556 of file stm8s_uart1.c.

void UART1_SmartCardCmd ( FunctionalState NewState )

Enables or disables the UART1 Smart Card mode.

Parameters:
NewState,: new state of the Smart Card mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 371 of file stm8s_uart1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART1_CR5_SCEN.

void UART1_SmartCardNACKCmd ( FunctionalState NewState )

Enables or disables NACK transmission.

Note:
This function is valid only for UART1 because is related to SmartCard mode.
Parameters:
NewState,: new state of the Smart Card mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 394 of file stm8s_uart1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART1_CR5_NACK.

void UART1_WakeUpConfig ( UART1_WakeUp_TypeDef UART1_WakeUp )

Selects the UART1 WakeUp method.

Parameters:
UART1_WakeUp,: specifies the UART1 wakeup method. This parameter can be any of the UART1_WakeUp_TypeDef values.
Return values:
None

Definition at line 416 of file stm8s_uart1.c.

References IS_UART1_WAKEUP_OK, and UART1_CR1_WAKE.


STM8S/A Standard Peripherals Drivers: UART2_Public_Functions

Functions
UART2_Public_Functions
STM8S_StdPeriph_Driver

Functions

void | UART2_ClearFlag (UART2_Flag_TypeDef UART2_FLAG)
Clears the UART2 flags.
void | UART2_ClearITPendingBit (UART2_IT_TypeDef UART2_IT)
Clears the UART2 pending flags.
void | UART2_Cmd (FunctionalState NewState)
Enable the UART2 peripheral.
void | UART2_DeInit (void)
Deinitializes the UART peripheral.
FlagStatus | UART2_GetFlagStatus (UART2_Flag_TypeDef UART2_FLAG)
Checks whether the specified UART2 flag is set or not.
ITStatus | UART2_GetITStatus (UART2_IT_TypeDef UART2_IT)
Checks whether the specified UART2 interrupt has occurred or not.
void | UART2_Init (uint32_t BaudRate, UART2_WordLength_TypeDef WordLength, UART2_StopBits_TypeDef StopBits, UART2_Parity_TypeDef Parity, UART2_SyncMode_TypeDef SyncMode, UART2_Mode_TypeDef Mode)
Initializes the UART2 according to the specified parameters.
void | UART2_IrDACmd (FunctionalState NewState)
Enables or disables the UART2’s IrDA interface.
void | UART2_IrDAConfig (UART2_IrDAMode_TypeDef UART2_IrDAMode)
Configures the UART2’s IrDA interface.
void | UART2_ITConfig (UART2_IT_TypeDef UART2_IT, FunctionalState NewState)
Enables or disables the specified UART2 interrupts.
void | UART2_LINBreakDetectionConfig (UART2_LINBreakDetectionLength_TypeDef UART2_LINBreakDetectionLength)
Sets the UART2 LIN Break detection length.
void | UART2_LINCmd (FunctionalState NewState)
Enables or disables the UART2 LIN mode.
void | UART2_LINConfig (UART2_LinMode_TypeDef UART2_Mode, UART2_LinAutosync_TypeDef UART2_Autosync, UART2_LinDivUp_TypeDef UART2_DivUp)
Configure the UART2 peripheral.
uint8_t | UART2_ReceiveData8 (void)
Returns the most recent received data by the UART2 peripheral.
uint16_t | UART2_ReceiveData9 (void)
Returns the most recent received data by the UART2 peripheral.
void | UART2_ReceiverWakeUpCmd (FunctionalState NewState)
Determines if the UART2 is in mute mode or not.
void | UART2_SendBreak (void)
Transmits break characters.
void | UART2_SendData8 (uint8_t Data)
Transmits 8 bit data through the UART2 peripheral.
void | UART2_SendData9 (uint16_t Data)
Transmits 9 bit data through the UART2 peripheral.
void | UART2_SetAddress (uint8_t UART2_Address)
Sets the address of the UART2 node.
void | UART2_SetGuardTime (uint8_t UART2_GuardTime)
Sets the specified UART2 guard time.
void | UART2_SetPrescaler (uint8_t UART2_Prescaler)
Sets the system clock prescaler.
void | UART2_SmartCardCmd (FunctionalState NewState)
Enables or disables the UART2 Smart Card mode.
void | UART2_SmartCardNACKCmd (FunctionalState NewState)
Enables or disables NACK transmission.
void | UART2_WakeUpConfig (UART2_WakeUp_TypeDef UART2_WakeUp)
Selects the UART2 WakeUp method.

Function Documentation

void UART2_ClearFlag ( UART2_Flag_TypeDef UART2_FLAG )

Clears the UART2 flags.

Parameters:
UART2_FLAG specifies the flag to clear This parameter can be any combination of the following values:
  • UART2_FLAG_LBDF: LIN Break detection flag.
  • UART2_FLAG_LHDF: LIN Header detection flag.
  • UART2_FLAG_LSF: LIN synchrone field flag.
  • UART2_FLAG_RXNE: Receive data register not empty flag.
Note:
:
  • PE (Parity error), FE (Framing error), NE (Noise error), OR (OverRun error) and IDLE (Idle line detected) flags are cleared by software sequence: a read operation to UART2_SR register (UART2_GetFlagStatus())followed by a read operation to UART2_DR register(UART2_ReceiveData8() or UART2_ReceiveData9()).
  • RXNE flag can be also cleared by a read to the UART2_DR register (UART2_ReceiveData8()or UART2_ReceiveData9()).
  • TC flag can be also cleared by software sequence: a read operation to UART2_SR register (UART2_GetFlagStatus()) followed by a write operation to UART2_DR register (UART2_SendData8() or UART2_SendData9()).
  • TXE flag is cleared only by a write to the UART2_DR register (UART2_SendData8() or UART2_SendData9()).
  • SBK flag is cleared during the stop bit of break.
    Return values:
    None

Definition at line 699 of file stm8s_uart2.c.

References IS_UART2_CLEAR_FLAG_OK, UART2_CR4_LBDF, UART2_CR6_LHDF, UART2_CR6_LSF, UART2_FLAG_LBDF, UART2_FLAG_LHDF, UART2_FLAG_RXNE, and UART2_SR_RXNE.

void UART2_ClearITPendingBit ( UART2_IT_TypeDef UART2_IT )

Clears the UART2 pending flags.

Parameters:
UART2_IT specifies the pending bit to clear This parameter can be one of the following values:
  • UART2_IT_LBDF: LIN Break detection interrupt
  • UART2_IT_LHDF: LIN Header detection interrupt
  • UART2_IT_RXNE: Receive Data register not empty interrupt.
Note:
  • PE (Parity error), FE (Framing error), NE (Noise error), OR (OverRun error) and IDLE (Idle line detected) pending bits are cleared by software sequence: a read operation to UART2_SR register (UART2_GetITStatus()) followed by a read operation to UART2_DR register (UART2_ReceiveData8() or UART2_ReceiveData9()).
  • RXNE pending bit can be also cleared by a read to the UART2_DR register (UART2_ReceiveData8() or UART2_ReceiveData9()).
  • TC (Transmit complete) pending bit can be cleared by software sequence: a read operation to UART2_SR register (UART2_GetITStatus()) followed by a write operation to UART2_DR register (UART2_SendData8()or UART2_SendData9()).
  • TXE pending bit is cleared only by a write to the UART2_DR register (UART2_SendData8() or UART2_SendData9()).
    Return values:
    None

Definition at line 852 of file stm8s_uart2.c.

References IS_UART2_CLEAR_IT_OK, UART2_CR4_LBDF, UART2_CR6_LHDF, UART2_IT_LBDF, UART2_IT_RXNE, and UART2_SR_RXNE.

void UART2_Cmd ( FunctionalState NewState )

Enable the UART2 peripheral.

Parameters:
NewState : The new state of the UART Communication. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 181 of file stm8s_uart2.c.

References DISABLE, and UART2_CR1_UARTD.

void UART2_DeInit ( void )

Deinitializes the UART peripheral.

Parameters:
None
Return values:
None

Definition at line 53 of file stm8s_uart2.c.

References UART2_BRR1_RESET_VALUE, UART2_BRR2_RESET_VALUE, UART2_CR1_RESET_VALUE, UART2_CR2_RESET_VALUE, UART2_CR3_RESET_VALUE, UART2_CR4_RESET_VALUE, UART2_CR5_RESET_VALUE, and UART2_CR6_RESET_VALUE.

FlagStatus UART2_GetFlagStatus ( UART2_Flag_TypeDef UART2_FLAG )

Checks whether the specified UART2 flag is set or not.

Parameters:
UART2_FLAG specifies the flag to check. This parameter can be any of the UART2_Flag_TypeDef enumeration.
Return values:
FlagStatus (SET or RESET)

Definition at line 606 of file stm8s_uart2.c.

References IS_UART2_FLAG_OK, RESET, SET, UART2_FLAG_LBDF, UART2_FLAG_LHDF, UART2_FLAG_LSF, and UART2_FLAG_SBK.

ITStatus UART2_GetITStatus ( UART2_IT_TypeDef UART2_IT )

Checks whether the specified UART2 interrupt has occurred or not.

Parameters:
UART2_IT,: Specifies the UART2 interrupt pending bit to check. This parameter can be one of the following values:
  • UART2_IT_LBDF: LIN Break detection interrupt
  • UART2_IT_TXE: Transmit Data Register empty interrupt
  • UART2_IT_TC: Transmission complete interrupt
  • UART2_IT_RXNE: Receive Data register not empty interrupt
  • UART2_IT_IDLE: Idle line detection interrupt
  • UART2_IT_OR: OverRun Error interrupt
  • UART2_IT_PE: Parity Error interrupt
Return values:
The state of UART2_IT (SET or RESET).

Definition at line 738 of file stm8s_uart2.c.

References IS_UART2_GET_IT_OK, RESET, SET, UART2_IT_LBDF, UART2_IT_LHDF, and UART2_IT_PE.

void UART2_Init | ( | uint32_t | BaudRate,
 |  | UART2_WordLength_TypeDef | WordLength,
 |  | UART2_StopBits_TypeDef | StopBits,
 |  | UART2_Parity_TypeDef | Parity,
 |  | UART2_SyncMode_TypeDef | SyncMode,
 |  | UART2_Mode_TypeDef | Mode
 | ) |  |

Initializes the UART2 according to the specified parameters.

Parameters:
BaudRate,: The baudrate.
WordLength : This parameter can be any of the UART2_WordLength_TypeDef enumeration.
StopBits,: This parameter can be any of the UART2_StopBits_TypeDef enumeration.
Parity,: This parameter can be any of the UART2_Parity_TypeDef enumeration.
SyncMode,: This parameter can be any of the UART2_SyncMode_TypeDef values.
Mode,: This parameter can be any of the UART2_Mode_TypeDef values
Return values:
None

Definition at line 85 of file stm8s_uart2.c.

References CLK_GetClockFreq(), IS_UART2_BAUDRATE_OK, IS_UART2_MODE_OK, IS_UART2_PARITY_OK, IS_UART2_STOPBITS_OK, IS_UART2_SYNCMODE_OK, IS_UART2_WORDLENGTH_OK, UART2_BRR1_DIVM, UART2_BRR2_DIVF, UART2_BRR2_DIVM, UART2_CR1_M, UART2_CR1_PCEN, UART2_CR1_PS, UART2_CR2_REN, UART2_CR2_TEN, UART2_CR3_CKEN, UART2_CR3_CPHA, UART2_CR3_CPOL, UART2_CR3_LBCL, UART2_CR3_STOP, UART2_MODE_RX_ENABLE, UART2_MODE_TX_ENABLE, and UART2_SYNCMODE_CLOCK_DISABLE.

void UART2_IrDACmd ( FunctionalState NewState )

Enables or disables the UART2’s IrDA interface.

Parameters:
NewState new state of the IrDA mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 292 of file stm8s_uart2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART2_CR5_IREN.

void UART2_IrDAConfig ( UART2_IrDAMode_TypeDef UART2_IrDAMode )

Configures the UART2’s IrDA interface.

Parameters:
UART2_IrDAMode specifies the IrDA mode. This parameter can be any of the UART2_IrDAMode_TypeDef values.
Return values:
None

Definition at line 272 of file stm8s_uart2.c.

References IS_UART2_IRDAMODE_OK, UART2_CR5_IRLP, and UART2_IRDAMODE_NORMAL.

void UART2_ITConfig | ( | UART2_IT_TypeDef | UART2_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified UART2 interrupts.

Parameters:
UART2_IT specifies the UART2 interrupt sources to be enabled or disabled. This parameter can be one of the following values:
  • UART2_IT_LBDF: LIN Break detection interrupt
  • UART2_IT_LHDF: LIN Break detection interrupt
  • UART2_IT_TXE: Transmit Data Register empty interrupt
  • UART2_IT_TC: Transmission complete interrupt
  • UART2_IT_RXNE_OR: Receive Data register not empty/Over run error interrupt
  • UART2_IT_IDLE: Idle line detection interrupt
  • UART2_IT_PE: Parity Error interrupt
NewState new state of the specified UART2 interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 210 of file stm8s_uart2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and IS_UART2_CONFIG_IT_OK.

void UART2_LINBreakDetectionConfig ( UART2_LINBreakDetectionLength_TypeDef UART2_LINBreakDetectionLength )

Sets the UART2 LIN Break detection length.

Parameters:
UART2_LINBreakDetectionLength specifies the LIN break detection length. This parameter can be any of the UART2_LINBreakDetectionLength_TypeDef values.
Return values:
None

Definition at line 316 of file stm8s_uart2.c.

References IS_UART2_LINBREAKDETECTIONLENGTH_OK, UART2_CR4_LBDL, and UART2_LINBREAKDETECTIONLENGTH_10BITS.

void UART2_LINCmd ( FunctionalState NewState )

Enables or disables the UART2 LIN mode.

Parameters:
NewState is new state of the UART2 LIN mode. This parameter can be ENABLE or DISABLE
Return values:
None

Definition at line 384 of file stm8s_uart2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART2_CR3_LINEN.

void UART2_LINConfig | ( | UART2_LinMode_TypeDef | UART2_Mode,
 |  | UART2_LinAutosync_TypeDef | UART2_Autosync,
 |  | UART2_LinDivUp_TypeDef | UART2_DivUp
 | ) |  |

Configure the UART2 peripheral.

Parameters:
UART2_Mode | specifies the LIN mode. This parameter can be any of the UART2_LinMode_TypeDef values.
UART2_Autosync | specifies the LIN automatic resynchronization mode. This parameter can be any of the UART2_LinAutosync_TypeDef values.
UART2_DivUp | specifies the LIN divider update method. This parameter can be any of the UART2_LinDivUp_TypeDef values.
Return values:
None

Definition at line 341 of file stm8s_uart2.c.

References IS_UART2_AUTOSYNC_OK, IS_UART2_DIVUP_OK, IS_UART2_SLAVE_OK, UART2_CR6_LASE, UART2_CR6_LDUM, UART2_CR6_LSLV, UART2_LIN_AUTOSYNC_DISABLE, UART2_LIN_DIVUP_LBRR1, and UART2_LIN_MODE_MASTER.

uint8_t UART2_ReceiveData8 ( void )

Returns the most recent received data by the UART2 peripheral.

Parameters:
None
Return values:
Received Data

Definition at line 487 of file stm8s_uart2.c.

uint16_t UART2_ReceiveData9 ( void )

Returns the most recent received data by the UART2 peripheral.

Parameters:
None
Return values:
Received Data

Definition at line 497 of file stm8s_uart2.c.

References UART2_CR1_R8.

void UART2_ReceiverWakeUpCmd ( FunctionalState NewState )

Determines if the UART2 is in mute mode or not.

Parameters:
NewState,: new state of the UART2 mode. This parameter can be ENABLE or DISABLE
Return values:
None

Definition at line 466 of file stm8s_uart2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART2_CR2_RWU.

void UART2_SendBreak ( void )

Transmits break characters.

Parameters:
None
Return values:
None

Definition at line 539 of file stm8s_uart2.c.

References UART2_CR2_SBK.

void UART2_SendData8 ( uint8_t Data )

Transmits 8 bit data through the UART2 peripheral.

Parameters:
Data,: the data to transmit.
Return values:
None

Definition at line 511 of file stm8s_uart2.c.

void UART2_SendData9 ( uint16_t Data )

Transmits 9 bit data through the UART2 peripheral.

Parameters:
Data,: the data to transmit.
Return values:
None

Definition at line 522 of file stm8s_uart2.c.

References UART2_CR1_T8.

void UART2_SetAddress ( uint8_t UART2_Address )

Sets the address of the UART2 node.

Parameters:
UART2_Address,: Indicates the address of the UART2 node.
Return values:
None

Definition at line 549 of file stm8s_uart2.c.

References IS_UART2_ADDRESS_OK, and UART2_CR4_ADD.

void UART2_SetGuardTime ( uint8_t UART2_GuardTime )

Sets the specified UART2 guard time.

Note:
SmartCard Mode should be Enabled
Parameters:
UART2_GuardTime,: specifies the guard time.
Return values:
None

Definition at line 566 of file stm8s_uart2.c.

void UART2_SetPrescaler ( uint8_t UART2_Prescaler )

Sets the system clock prescaler.

Note:
IrDA Low Power mode or smartcard mode should be enabled
This function is related to SmartCard and IrDa mode.
Parameters:
UART2_Prescaler,: specifies the prescaler clock. This parameter can be one of the following values:
IrDA Low Power Mode
The clock source is divided by the value given in the register (8 bits)
  • 0000 0000 Reserved
  • 0000 0001 divides the clock source by 1
  • 0000 0010 divides the clock source by 2
  • ...
Smart Card Mode
The clock source is divided by the value given in the register (5 significant bits) multiped by 2
  • 0 0000 Reserved
  • 0 0001 divides the clock source by 2
  • 0 0010 divides the clock source by 4
  • 0 0011 divides the clock source by 6
  • ...
Return values:
None

Definition at line 594 of file stm8s_uart2.c.

void UART2_SmartCardCmd ( FunctionalState NewState )

Enables or disables the UART2 Smart Card mode.

Parameters:
NewState,: new state of the Smart Card mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 406 of file stm8s_uart2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART2_CR5_SCEN.

void UART2_SmartCardNACKCmd ( FunctionalState NewState )

Enables or disables NACK transmission.

Parameters:
NewState,: new state of the Smart Card mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 429 of file stm8s_uart2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART2_CR5_NACK.

void UART2_WakeUpConfig ( UART2_WakeUp_TypeDef UART2_WakeUp )

Selects the UART2 WakeUp method.

Parameters:
UART2_WakeUp,: specifies the UART2 wakeup method. This parameter can be any of the UART2_WakeUp_TypeDef values.
Return values:
None

Definition at line 452 of file stm8s_uart2.c.

References IS_UART2_WAKEUP_OK, and UART2_CR1_WAKE.


STM8S/A Standard Peripherals Drivers: UART3_Public_Functions

Functions
UART3_Public_Functions
STM8S_StdPeriph_Driver

Functions

void | UART3_ClearFlag (UART3_Flag_TypeDef UART3_FLAG)
Clears the UART3 flags.
void | UART3_ClearITPendingBit (UART3_IT_TypeDef UART3_IT)
Clears the UART3 pending flags.
void | UART3_Cmd (FunctionalState NewState)
Enable the UART1 peripheral.
void | UART3_DeInit (void)
Deinitializes the UART peripheral.
FlagStatus | UART3_GetFlagStatus (UART3_Flag_TypeDef UART3_FLAG)
Checks whether the specified UART3 flag is set or not.
ITStatus | UART3_GetITStatus (UART3_IT_TypeDef UART3_IT)
Checks whether the specified UART3 interrupt has occurred or not.
void | UART3_Init (uint32_t BaudRate, UART3_WordLength_TypeDef WordLength, UART3_StopBits_TypeDef StopBits, UART3_Parity_TypeDef Parity, UART3_Mode_TypeDef Mode)
Initializes the UART3 according to the specified parameters.
void | UART3_ITConfig (UART3_IT_TypeDef UART3_IT, FunctionalState NewState)
Enables or disables the specified UART3 interrupts.
void | UART3_LINBreakDetectionConfig (UART3_LINBreakDetectionLength_TypeDef UART3_LINBreakDetectionLength)
Sets the UART3 LIN Break detection length.
void | UART3_LINCmd (FunctionalState NewState)
Enables or disables the UART3 LIN mode.
void | UART3_LINConfig (UART3_LinMode_TypeDef UART3_Mode, UART3_LinAutosync_TypeDef UART3_Autosync, UART3_LinDivUp_TypeDef UART3_DivUp)
Configure the UART3 peripheral.
uint8_t | UART3_ReceiveData8 (void)
Returns the most recent received data by the UART3 peripheral.
uint16_t | UART3_ReceiveData9 (void)
Returns the most recent received data by the UART3 peripheral.
void | UART3_ReceiverWakeUpCmd (FunctionalState NewState)
Determines if the UART3 is in mute mode or not.
void | UART3_SendBreak (void)
Transmits break characters.
void | UART3_SendData8 (uint8_t Data)
Transmits 8 bit data through the UART3 peripheral.
void | UART3_SendData9 (uint16_t Data)
Transmits 9 bit data through the UART3 peripheral.
void | UART3_SetAddress (uint8_t UART3_Address)
Sets the address of the UART3 node.
void | UART3_WakeUpConfig (UART3_WakeUp_TypeDef UART3_WakeUp)
Selects the UART3 WakeUp method.

Function Documentation

void UART3_ClearFlag ( UART3_Flag_TypeDef UART3_FLAG )

Clears the UART3 flags.

Parameters:
UART3_FLAG specifies the flag to clear This parameter can be any combination of the following values:
  • UART3_FLAG_LBDF: LIN Break detection flag.
  • UART3_FLAG_LHDF: LIN Header detection flag.
  • UART3_FLAG_LSF: LIN synchrone field flag.
  • UART3_FLAG_RXNE: Receive data register not empty flag.
Note:
  • PE (Parity error), FE (Framing error), NF (Noise error), OR (OverRun error) and IDLE (Idle line detected) flags are cleared by software sequence: a read operation to UART3_SR register (UART3_GetFlagStatus())followed by a read operation to UART3_DR register(UART3_ReceiveData8() or UART3_ReceiveData9()).
  • RXNE flag can be also cleared by a read to the UART3_DR register (UART3_ReceiveData8()or UART3_ReceiveData9()).
  • TC flag can be also cleared by software sequence: a read operation to UART3_SR register (UART3_GetFlagStatus()) followed by a write operation to UART3_DR register (UART3_SendData8() or UART3_SendData9()).
  • TXE flag is cleared only by a write to the UART3_DR register (UART3_SendData8() or UART3_SendData9()).
  • SBK flag is cleared during the stop bit of break.
    Return values:
    None

Definition at line 551 of file stm8s_uart3.c.

References IS_UART3_CLEAR_FLAG_OK, UART3_CR4_LBDF, UART3_CR6_LHDF, UART3_CR6_LSF, UART3_FLAG_LBDF, UART3_FLAG_LHDF, UART3_FLAG_RXNE, and UART3_SR_RXNE.

void UART3_ClearITPendingBit ( UART3_IT_TypeDef UART3_IT )

Clears the UART3 pending flags.

Parameters:
UART3_IT specifies the pending bit to clear This parameter can be one of the following values:
  • UART3_IT_LBDF: LIN Break detection interrupt
  • UART3_IT_LHDF: LIN Header detection interrupt
  • UART3_IT_RXNE: Receive Data register not empty interrupt.
Note:
  • PE (Parity error), FE (Framing error), NF (Noise error), OR (OverRun error) and IDLE (Idle line detected) pending bits are cleared by software sequence: a read operation to UART3_SR register (UART3_GetITStatus()) followed by a read operation to UART3_DR register (UART3_ReceiveData8() or UART3_ReceiveData9()).
  • RXNE pending bit can be also cleared by a read to the UART3_DR register (UART3_ReceiveData8() or UART3_ReceiveData9() ).
  • TC (Transmit complete) pending bit can be cleared by software sequence: a read operation to UART3_SR register (UART3_GetITStatus()) followed by a write operation to UART3_DR register (UART3_SendData8()or UART3_SendData9()).
  • TXE pending bit is cleared only by a write to the UART3_DR register (UART3_SendData8() or UART3_SendData9()).
    Return values:
    None

Definition at line 706 of file stm8s_uart3.c.

References IS_UART3_CLEAR_IT_OK, UART3_CR4_LBDF, UART3_CR6_LHDF, UART3_IT_LBDF, UART3_IT_RXNE, and UART3_SR_RXNE.

void UART3_Cmd ( FunctionalState NewState )

Enable the UART1 peripheral.

Parameters:
NewState : The new state of the UART Communication. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 160 of file stm8s_uart3.c.

References DISABLE, and UART3_CR1_UARTD.

void UART3_DeInit ( void )

Deinitializes the UART peripheral.

Parameters:
None
Return values:
None

Definition at line 54 of file stm8s_uart3.c.

References UART3_BRR1_RESET_VALUE, UART3_BRR2_RESET_VALUE, UART3_CR1_RESET_VALUE, UART3_CR2_RESET_VALUE, UART3_CR3_RESET_VALUE, UART3_CR4_RESET_VALUE, and UART3_CR6_RESET_VALUE.

FlagStatus UART3_GetFlagStatus ( UART3_Flag_TypeDef UART3_FLAG )

Checks whether the specified UART3 flag is set or not.

Parameters:
UART3_FLAG specifies the flag to check. This parameter can be any of the UART3_Flag_TypeDef enumeration.
Return values:
FlagStatus (SET or RESET)

Definition at line 458 of file stm8s_uart3.c.

References IS_UART3_FLAG_OK, RESET, SET, UART3_FLAG_LBDF, UART3_FLAG_LHDF, UART3_FLAG_LSF, and UART3_FLAG_SBK.

ITStatus UART3_GetITStatus ( UART3_IT_TypeDef UART3_IT )

Checks whether the specified UART3 interrupt has occurred or not.

Parameters:
UART3_IT,: Specifies the UART3 interrupt pending bit to check. This parameter can be one of the following values:
  • UART3_IT_LBDF: LIN Break detection interrupt
  • UART3_IT_TXE: Transmit Data Register empty interrupt
  • UART3_IT_TC: Transmission complete interrupt
  • UART3_IT_RXNE: Receive Data register not empty interrupt
  • UART3_IT_IDLE: Idle line detection interrupt
  • UART3_IT_OR: OverRun Error interrupt
  • UART3_IT_PE: Parity Error interrupt
Return values:
The state of UART3_IT (SET or RESET).

Definition at line 591 of file stm8s_uart3.c.

References IS_UART3_GET_IT_OK, RESET, SET, UART3_IT_LBDF, UART3_IT_LHDF, and UART3_IT_PE.

void UART3_Init | ( | uint32_t | BaudRate,
 |  | UART3_WordLength_TypeDef | WordLength,
 |  | UART3_StopBits_TypeDef | StopBits,
 |  | UART3_Parity_TypeDef | Parity,
 |  | UART3_Mode_TypeDef | Mode
 | ) |  |

Initializes the UART3 according to the specified parameters.

Parameters:
BaudRate,: The baudrate.
WordLength : This parameter can be any of the UART3_WordLength_TypeDef enumeration.
StopBits,: This parameter can be any of the UART3_StopBits_TypeDef enumeration.
Parity,: This parameter can be any of the UART3_Parity_TypeDef enumeration.
Mode,: This parameter can be any of the UART3_Mode_TypeDef values
Return values:
None

Definition at line 83 of file stm8s_uart3.c.

References CLK_GetClockFreq(), IS_UART3_BAUDRATE_OK, IS_UART3_MODE_OK, IS_UART3_PARITY_OK, IS_UART3_STOPBITS_OK, IS_UART3_WORDLENGTH_OK, UART3_BRR1_DIVM, UART3_BRR2_DIVF, UART3_BRR2_DIVM, UART3_CR1_M, UART3_CR1_PCEN, UART3_CR1_PS, UART3_CR2_REN, UART3_CR2_TEN, UART3_CR3_STOP, UART3_MODE_RX_ENABLE, and UART3_MODE_TX_ENABLE.

void UART3_ITConfig | ( | UART3_IT_TypeDef | UART3_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified UART3 interrupts.

Parameters:
UART3_IT specifies the UART3 interrupt sources to be enabled or disabled. This parameter can be one of the following values:
  • UART3_IT_LBDF: LIN Break detection interrupt
  • UART3_IT_LHDF: LIN Break detection interrupt
  • UART3_IT_TXE: Transmit Data Register empty interrupt
  • UART3_IT_TC: Transmission complete interrupt
  • UART3_IT_RXNE_OR: Receive Data register not empty/Over run error interrupt
  • UART3_IT_IDLE: Idle line detection interrupt
  • UART3_IT_PE: Parity Error interrupt
NewState new state of the specified UART3 interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 189 of file stm8s_uart3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and IS_UART3_CONFIG_IT_OK.

void UART3_LINBreakDetectionConfig ( UART3_LINBreakDetectionLength_TypeDef UART3_LINBreakDetectionLength )

Sets the UART3 LIN Break detection length.

Parameters:
UART3_LINBreakDetectionLength specifies the LIN break detection length. This parameter can be any of the UART3_LINBreakDetectionLength_TypeDef values.
Return values:
None

Definition at line 252 of file stm8s_uart3.c.

References IS_UART3_LINBREAKDETECTIONLENGTH_OK, UART3_CR4_LBDL, and UART3_LINBREAKDETECTIONLENGTH_10BITS.

void UART3_LINCmd ( FunctionalState NewState )

Enables or disables the UART3 LIN mode.

Parameters:
NewState is new state of the UART3 LIN mode. This parameter can be ENABLE or DISABLE
Return values:
None

Definition at line 320 of file stm8s_uart3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART3_CR3_LINEN.

void UART3_LINConfig | ( | UART3_LinMode_TypeDef | UART3_Mode,
 |  | UART3_LinAutosync_TypeDef | UART3_Autosync,
 |  | UART3_LinDivUp_TypeDef | UART3_DivUp
 | ) |  |

Configure the UART3 peripheral.

Parameters:
UART3_Mode | specifies the LIN mode. This parameter can be any of the UART3_LinMode_TypeDef values.
UART3_Autosync | specifies the LIN automatic resynchronization mode. This parameter can be any of the UART3_LinAutosync_TypeDef values.
UART3_DivUp | specifies the LIN divider update method. This parameter can be any of the UART3_LinDivUp_TypeDef values.
Return values:
None

Definition at line 277 of file stm8s_uart3.c.

References IS_UART3_AUTOSYNC_OK, IS_UART3_DIVUP_OK, IS_UART3_SLAVE_OK, UART3_CR6_LASE, UART3_CR6_LDUM, UART3_CR6_LSLV, UART3_LIN_AUTOSYNC_DISABLE, UART3_LIN_DIVUP_LBRR1, and UART3_LIN_MODE_MASTER.

uint8_t UART3_ReceiveData8 ( void )

Returns the most recent received data by the UART3 peripheral.

Parameters:
None
Return values:
Received Data

Definition at line 380 of file stm8s_uart3.c.

uint16_t UART3_ReceiveData9 ( void )

Returns the most recent received data by the UART3 peripheral.

Parameters:
None
Return values:
Received Data

Definition at line 390 of file stm8s_uart3.c.

References UART3_CR1_R8.

void UART3_ReceiverWakeUpCmd ( FunctionalState NewState )

Determines if the UART3 is in mute mode or not.

Parameters:
NewState,: new state of the UART3 mode. This parameter can be ENABLE or DISABLE
Return values:
None

Definition at line 358 of file stm8s_uart3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART3_CR2_RWU.

void UART3_SendBreak ( void )

Transmits break characters.

Parameters:
None
Return values:
None

Definition at line 431 of file stm8s_uart3.c.

References UART3_CR2_SBK.

void UART3_SendData8 ( uint8_t Data )

Transmits 8 bit data through the UART3 peripheral.

Parameters:
Data the data to transmit.
Return values:
None

Definition at line 403 of file stm8s_uart3.c.

void UART3_SendData9 ( uint16_t Data )

Transmits 9 bit data through the UART3 peripheral.

Parameters:
Data,: the data to transmit.
Return values:
None

Definition at line 414 of file stm8s_uart3.c.

References UART3_CR1_T8.

void UART3_SetAddress ( uint8_t UART3_Address )

Sets the address of the UART3 node.

Parameters:
UART3_Address,: Indicates the address of the UART3 node.
Return values:
None

Definition at line 441 of file stm8s_uart3.c.

References IS_UART3_ADDRESS_OK, and UART3_CR4_ADD.

void UART3_WakeUpConfig ( UART3_WakeUp_TypeDef UART3_WakeUp )

Selects the UART3 WakeUp method.

Parameters:
UART3_WakeUp,: specifies the UART3 wakeup method. This parameter can be any of the UART3_WakeUp_TypeDef values.
Return values:
None

Definition at line 343 of file stm8s_uart3.c.

References IS_UART3_WAKEUP_OK, and UART3_CR1_WAKE.


STM8S/A Standard Peripherals Drivers: UART4_Public_Functions

Functions
UART4_Public_Functions
STM8S_StdPeriph_Driver

Functions

void | UART4_ClearFlag (UART4_Flag_TypeDef UART4_FLAG)
Clears the UART4 flags.
void | UART4_ClearITPendingBit (UART4_IT_TypeDef UART4_IT)
Clears the UART4 pending flags.
void | UART4_Cmd (FunctionalState NewState)
Enable the UART4 peripheral.
void | UART4_DeInit (void)
Deinitializes the UART peripheral.
FlagStatus | UART4_GetFlagStatus (UART4_Flag_TypeDef UART4_FLAG)
Checks whether the specified UART4 flag is set or not.
ITStatus | UART4_GetITStatus (UART4_IT_TypeDef UART4_IT)
Checks whether the specified UART4 interrupt has occurred or not.
void | UART4_HalfDuplexCmd (FunctionalState NewState)
Enables or disables the UART’s Half Duplex communication.
void | UART4_Init (uint32_t BaudRate, UART4_WordLength_TypeDef WordLength, UART4_StopBits_TypeDef StopBits, UART4_Parity_TypeDef Parity, UART4_SyncMode_TypeDef SyncMode, UART4_Mode_TypeDef Mode)
Initializes the UART4 according to the specified parameters.
void | UART4_IrDACmd (FunctionalState NewState)
Enables or disables the UART4’s IrDA interface.
void | UART4_IrDAConfig (UART4_IrDAMode_TypeDef UART4_IrDAMode)
Configures the UART4’s IrDA interface.
void | UART4_ITConfig (UART4_IT_TypeDef UART4_IT, FunctionalState NewState)
Enables or disables the specified UART4 interrupts.
void | UART4_LINBreakDetectionConfig (UART4_LINBreakDetectionLength_TypeDef UART4_LINBreakDetectionLength)
Sets the UART4 LIN Break detection length.
void | UART4_LINCmd (FunctionalState NewState)
Enables or disables the UART4 LIN mode.
void | UART4_LINConfig (UART4_LinMode_TypeDef UART4_Mode, UART4_LinAutosync_TypeDef UART4_Autosync, UART4_LinDivUp_TypeDef UART4_DivUp)
Configure the UART4 peripheral.
uint8_t | UART4_ReceiveData8 (void)
Returns the most recent received data by the UART4 peripheral.
uint16_t | UART4_ReceiveData9 (void)
Returns the most recent received data by the UART4 peripheral.
void | UART4_ReceiverWakeUpCmd (FunctionalState NewState)
Determines if the UART4 is in mute mode or not.
void | UART4_SendBreak (void)
Transmits break characters.
void | UART4_SendData8 (uint8_t Data)
Transmits 8 bit data through the UART4 peripheral.
void | UART4_SendData9 (uint16_t Data)
Transmits 9 bit data through the UART4 peripheral.
void | UART4_SetAddress (uint8_t UART4_Address)
Sets the address of the UART4 node.
void | UART4_SetGuardTime (uint8_t UART4_GuardTime)
Sets the specified UART4 guard time.
void | UART4_SetPrescaler (uint8_t UART4_Prescaler)
Sets the system clock prescaler.
void | UART4_SmartCardCmd (FunctionalState NewState)
Enables or disables the UART4 Smart Card mode.
void | UART4_SmartCardNACKCmd (FunctionalState NewState)
Enables or disables NACK transmission.
void | UART4_WakeUpConfig (UART4_WakeUp_TypeDef UART4_WakeUp)
Selects the UART4 WakeUp method.

Function Documentation

void UART4_ClearFlag ( UART4_Flag_TypeDef UART4_FLAG )

Clears the UART4 flags.

Parameters:
UART4_FLAG specifies the flag to clear This parameter can be any combination of the following values:
  • UART4_FLAG_LBDF: LIN Break detection flag.
  • UART4_FLAG_LHDF: LIN Header detection flag.
  • UART4_FLAG_LSF: LIN synchrone field flag.
  • UART4_FLAG_RXNE: Receive data register not empty flag.
Note:
:
  • PE (Parity error), FE (Framing error), NE (Noise error), OR (OverRun error) and IDLE (Idle line detected) flags are cleared by software sequence: a read operation to UART4_SR register (UART4_GetFlagStatus())followed by a read operation to UART4_DR register(UART4_ReceiveData8() or UART4_ReceiveData9()).
  • RXNE flag can be also cleared by a read to the UART4_DR register (UART4_ReceiveData8()or UART4_ReceiveData9()).
  • TC flag can be also cleared by software sequence: a read operation to UART4_SR register (UART4_GetFlagStatus()) followed by a write operation to UART4_DR register (UART4_SendData8() or UART4_SendData9()).
  • TXE flag is cleared only by a write to the UART4_DR register (UART4_SendData8() or UART4_SendData9()).
  • SBK flag is cleared during the stop bit of break.
    Return values:
    None

Definition at line 719 of file stm8s_uart4.c.

References IS_UART4_CLEAR_FLAG_OK, UART4_FLAG_LBDF, UART4_FLAG_LHDF, and UART4_FLAG_RXNE.

void UART4_ClearITPendingBit ( UART4_IT_TypeDef UART4_IT )

Clears the UART4 pending flags.

Parameters:
UART4_IT specifies the pending bit to clear This parameter can be one of the following values:
  • UART4_IT_LBDF: LIN Break detection interrupt
  • UART4_IT_LHDF: LIN Header detection interrupt
  • UART4_IT_RXNE: Receive Data register not empty interrupt.
Note:
  • PE (Parity error), FE (Framing error), NE (Noise error), OR (OverRun error) and IDLE (Idle line detected) pending bits are cleared by software sequence: a read operation to UART4_SR register (UART4_GetITStatus()) followed by a read operation to UART4_DR register (UART4_ReceiveData8() or UART4_ReceiveData9()).
  • RXNE pending bit can be also cleared by a read to the UART4_DR register (UART4_ReceiveData8() or UART4_ReceiveData9()).
  • TC (Transmit complete) pending bit can be cleared by software sequence: a read operation to UART4_SR register (UART4_GetITStatus()) followed by a write operation to UART4_DR register (UART4_SendData8()or UART4_SendData9()).
  • TXE pending bit is cleared only by a write to the UART4_DR register (UART4_SendData8() or UART4_SendData9()).
    Return values:
    None

Definition at line 872 of file stm8s_uart4.c.

References IS_UART4_CLEAR_IT_OK, UART4_IT_LBDF, and UART4_IT_RXNE.

void UART4_Cmd ( FunctionalState NewState )

Enable the UART4 peripheral.

Parameters:
NewState : The new state of the UART Communication. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 181 of file stm8s_uart4.c.

References DISABLE.

void UART4_DeInit ( void )

Deinitializes the UART peripheral.

Parameters:
None
Return values:
None

Definition at line 53 of file stm8s_uart4.c.

FlagStatus UART4_GetFlagStatus ( UART4_Flag_TypeDef UART4_FLAG )

Checks whether the specified UART4 flag is set or not.

Parameters:
UART4_FLAG specifies the flag to check. This parameter can be any of the UART4_Flag_TypeDef enumeration.
Return values:
FlagStatus (SET or RESET)

Definition at line 626 of file stm8s_uart4.c.

References IS_UART4_FLAG_OK, RESET, SET, UART4_FLAG_LBDF, UART4_FLAG_LHDF, UART4_FLAG_LSF, and UART4_FLAG_SBK.

ITStatus UART4_GetITStatus ( UART4_IT_TypeDef UART4_IT )

Checks whether the specified UART4 interrupt has occurred or not.

Parameters:
UART4_IT,: Specifies the UART4 interrupt pending bit to check. This parameter can be one of the following values:
  • UART4_IT_LBDF: LIN Break detection interrupt
  • UART4_IT_TXE: Transmit Data Register empty interrupt
  • UART4_IT_TC: Transmission complete interrupt
  • UART4_IT_RXNE: Receive Data register not empty interrupt
  • UART4_IT_IDLE: Idle line detection interrupt
  • UART4_IT_OR: OverRun Error interrupt
  • UART4_IT_PE: Parity Error interrupt
Return values:
The state of UART4_IT (SET or RESET).

Definition at line 758 of file stm8s_uart4.c.

References IS_UART4_GET_IT_OK, RESET, SET, UART4_IT_LBDF, UART4_IT_LHDF, and UART4_IT_PE.

void UART4_HalfDuplexCmd ( FunctionalState NewState )

Enables or disables the UART’s Half Duplex communication.

Parameters:
NewState new state of the UART Communication. This parameter can be: ENABLE or DISABLE.
Return values:
None

< UART4 Half Duplex Enable

< UART4 Half Duplex Disable

Definition at line 272 of file stm8s_uart4.c.

References DISABLE, and IS_FUNCTIONALSTATE_OK.

void UART4_Init | ( | uint32_t | BaudRate,
 |  | UART4_WordLength_TypeDef | WordLength,
 |  | UART4_StopBits_TypeDef | StopBits,
 |  | UART4_Parity_TypeDef | Parity,
 |  | UART4_SyncMode_TypeDef | SyncMode,
 |  | UART4_Mode_TypeDef | Mode
 | ) |  |

Initializes the UART4 according to the specified parameters.

Parameters:
BaudRate,: The baudrate.
WordLength : This parameter can be any of the UART4_WordLength_TypeDef enumeration.
StopBits,: This parameter can be any of the UART4_StopBits_TypeDef enumeration.
Parity,: This parameter can be any of the UART4_Parity_TypeDef enumeration.
SyncMode,: This parameter can be any of the UART4_SyncMode_TypeDef values.
Mode,: This parameter can be any of the UART4_Mode_TypeDef values
Return values:
None

Definition at line 85 of file stm8s_uart4.c.

References CLK_GetClockFreq(), IS_UART4_BAUDRATE_OK, IS_UART4_MODE_OK, IS_UART4_PARITY_OK, IS_UART4_STOPBITS_OK, IS_UART4_SYNCMODE_OK, IS_UART4_WORDLENGTH_OK, UART4_MODE_RX_ENABLE, UART4_MODE_TX_ENABLE, and UART4_SYNCMODE_CLOCK_DISABLE.

void UART4_IrDACmd ( FunctionalState NewState )

Enables or disables the UART4’s IrDA interface.

Parameters:
NewState new state of the IrDA mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 312 of file stm8s_uart4.c.

References DISABLE, and IS_FUNCTIONALSTATE_OK.

void UART4_IrDAConfig ( UART4_IrDAMode_TypeDef UART4_IrDAMode )

Configures the UART4’s IrDA interface.

Parameters:
UART4_IrDAMode specifies the IrDA mode. This parameter can be any of the UART4_IrDAMode_TypeDef values.
Return values:
None

Definition at line 292 of file stm8s_uart4.c.

References IS_UART4_IRDAMODE_OK, and UART4_IRDAMODE_NORMAL.

void UART4_ITConfig | ( | UART4_IT_TypeDef | UART4_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified UART4 interrupts.

Parameters:
UART4_IT specifies the UART4 interrupt sources to be enabled or disabled. This parameter can be one of the following values:
  • UART4_IT_LBDF: LIN Break detection interrupt
  • UART4_IT_LHDF: LIN Break detection interrupt
  • UART4_IT_TXE: Transmit Data Register empty interrupt
  • UART4_IT_TC: Transmission complete interrupt
  • UART4_IT_RXNE_OR: Receive Data register not empty/Over run error interrupt
  • UART4_IT_IDLE: Idle line detection interrupt
  • UART4_IT_PE: Parity Error interrupt
NewState new state of the specified UART4 interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 210 of file stm8s_uart4.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and IS_UART4_CONFIG_IT_OK.

void UART4_LINBreakDetectionConfig ( UART4_LINBreakDetectionLength_TypeDef UART4_LINBreakDetectionLength )

Sets the UART4 LIN Break detection length.

Parameters:
UART4_LINBreakDetectionLength specifies the LIN break detection length. This parameter can be any of the UART4_LINBreakDetectionLength_TypeDef values.
Return values:
None

Definition at line 336 of file stm8s_uart4.c.

References IS_UART4_LINBREAKDETECTIONLENGTH_OK, and UART4_LINBREAKDETECTIONLENGTH_10BITS.

void UART4_LINCmd ( FunctionalState NewState )

Enables or disables the UART4 LIN mode.

Parameters:
NewState is new state of the UART4 LIN mode. This parameter can be ENABLE or DISABLE
Return values:
None

Definition at line 404 of file stm8s_uart4.c.

References DISABLE, and IS_FUNCTIONALSTATE_OK.

void UART4_LINConfig | ( | UART4_LinMode_TypeDef | UART4_Mode,
 |  | UART4_LinAutosync_TypeDef | UART4_Autosync,
 |  | UART4_LinDivUp_TypeDef | UART4_DivUp
 | ) |  |

Configure the UART4 peripheral.

Parameters:
UART4_Mode | specifies the LIN mode. This parameter can be any of the UART4_LinMode_TypeDef values.
UART4_Autosync | specifies the LIN automatic resynchronization mode. This parameter can be any of the UART4_LinAutosync_TypeDef values.
UART4_DivUp | specifies the LIN divider update method. This parameter can be any of the UART4_LinDivUp_TypeDef values.
Return values:
None

Definition at line 361 of file stm8s_uart4.c.

References IS_UART4_AUTOSYNC_OK, IS_UART4_DIVUP_OK, IS_UART4_SLAVE_OK, UART4_LIN_AUTOSYNC_DISABLE, UART4_LIN_DIVUP_LBRR1, and UART4_LIN_MODE_MASTER.

uint8_t UART4_ReceiveData8 ( void )

Returns the most recent received data by the UART4 peripheral.

Parameters:
None
Return values:
Received Data

Definition at line 507 of file stm8s_uart4.c.

uint16_t UART4_ReceiveData9 ( void )

Returns the most recent received data by the UART4 peripheral.

Parameters:
None
Return values:
Received Data

Definition at line 517 of file stm8s_uart4.c.

void UART4_ReceiverWakeUpCmd ( FunctionalState NewState )

Determines if the UART4 is in mute mode or not.

Parameters:
NewState,: new state of the UART4 mode. This parameter can be ENABLE or DISABLE
Return values:
None

Definition at line 486 of file stm8s_uart4.c.

References DISABLE, and IS_FUNCTIONALSTATE_OK.

void UART4_SendBreak ( void )

Transmits break characters.

Parameters:
None
Return values:
None

Definition at line 559 of file stm8s_uart4.c.

void UART4_SendData8 ( uint8_t Data )

Transmits 8 bit data through the UART4 peripheral.

Parameters:
Data,: the data to transmit.
Return values:
None

Definition at line 531 of file stm8s_uart4.c.

void UART4_SendData9 ( uint16_t Data )

Transmits 9 bit data through the UART4 peripheral.

Parameters:
Data,: the data to transmit.
Return values:
None

Definition at line 542 of file stm8s_uart4.c.

void UART4_SetAddress ( uint8_t UART4_Address )

Sets the address of the UART4 node.

Parameters:
UART4_Address,: Indicates the address of the UART4 node.
Return values:
None

Definition at line 569 of file stm8s_uart4.c.

References IS_UART4_ADDRESS_OK.

void UART4_SetGuardTime ( uint8_t UART4_GuardTime )

Sets the specified UART4 guard time.

Note:
SmartCard Mode should be Enabled
Parameters:
UART4_GuardTime,: specifies the guard time.
Return values:
None

Definition at line 586 of file stm8s_uart4.c.

void UART4_SetPrescaler ( uint8_t UART4_Prescaler )

Sets the system clock prescaler.

Note:
IrDA Low Power mode or smartcard mode should be enabled
This function is related to SmartCard and IrDa mode.
Parameters:
UART4_Prescaler,: specifies the prescaler clock. This parameter can be one of the following values:
IrDA Low Power Mode
The clock source is divided by the value given in the register (8 bits)
  • 0000 0000 Reserved
  • 0000 0001 divides the clock source by 1
  • 0000 0010 divides the clock source by 2
  • ...
Smart Card Mode
The clock source is divided by the value given in the register (5 significant bits) multiplied by 2
  • 0 0000 Reserved
  • 0 0001 divides the clock source by 2
  • 0 0010 divides the clock source by 4
  • 0 0011 divides the clock source by 6
  • ...
Return values:
None

Definition at line 614 of file stm8s_uart4.c.

void UART4_SmartCardCmd ( FunctionalState NewState )

Enables or disables the UART4 Smart Card mode.

Parameters:
NewState,: new state of the Smart Card mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 426 of file stm8s_uart4.c.

References DISABLE, and IS_FUNCTIONALSTATE_OK.

void UART4_SmartCardNACKCmd ( FunctionalState NewState )

Enables or disables NACK transmission.

Parameters:
NewState,: new state of the Smart Card mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 449 of file stm8s_uart4.c.

References DISABLE, and IS_FUNCTIONALSTATE_OK.

void UART4_WakeUpConfig ( UART4_WakeUp_TypeDef UART4_WakeUp )

Selects the UART4 WakeUp method.

Parameters:
UART4_WakeUp,: specifies the UART4 wakeup method. This parameter can be any of the UART4_WakeUp_TypeDef values.
Return values:
None

Definition at line 472 of file stm8s_uart4.c.

References IS_UART4_WAKEUP_OK.


STM8S/A Standard Peripherals Drivers: WWDG_Public_Functions

Functions
WWDG_Public_Functions
STM8S_StdPeriph_Driver

Functions

uint8_t | WWDG_GetCounter (void)
Gets the WWDG Counter Value.
void | WWDG_Init (uint8_t Counter, uint8_t WindowValue)
Initializes the WWDG peripheral.
void | WWDG_SetCounter (uint8_t Counter)
Refreshes the WWDG peripheral.
void | WWDG_SetWindowValue (uint8_t WindowValue)
Sets the WWDG window value.
void | WWDG_SWReset (void)
Generates immediate WWDG RESET.

Function Documentation

uint8_t WWDG_GetCounter ( void )

Gets the WWDG Counter Value.

This value could be used to check if WWDG is in the window, where refresh is allowed.

Parameters:
None
Return values:
WWDG Counter Value

Definition at line 86 of file stm8s_wwdg.c.

References WWDG.

void WWDG_Init | ( | uint8_t | Counter,
 |  | uint8_t | WindowValue
 | ) |  |

Initializes the WWDG peripheral.

This function set Window Register = WindowValue, Counter Register according to Counter and ENABLE WWDG

Parameters:
Counter | : WWDG counter value
WindowValue | : specifies the WWDG Window Register, range is 0x00 to 0x7F.
Return values:
None

Definition at line 53 of file stm8s_wwdg.c.

References IS_WWDG_WINDOWLIMITVALUE_OK, WWDG, WWDG_CR_T6, WWDG_CR_WDGA, and WWDG_WR_RESET_VALUE.

void WWDG_SetCounter ( uint8_t Counter )

Refreshes the WWDG peripheral.

Parameters:
Counter : WWDG Counter Value This parameter must be a number between 0x40 and 0x7F.
Return values:
None

Definition at line 69 of file stm8s_wwdg.c.

References BIT_MASK, IS_WWDG_COUNTERVALUE_OK, and WWDG.

void WWDG_SetWindowValue ( uint8_t WindowValue )

Sets the WWDG window value.

Parameters:
WindowValue,: specifies the window value to be compared to the downcounter. This parameter value must be lower than 0x80.
Return values:
None

Definition at line 108 of file stm8s_wwdg.c.

References IS_WWDG_WINDOWLIMITVALUE_OK, WWDG, WWDG_CR_T6, and WWDG_CR_WDGA.

void WWDG_SWReset ( void )

Generates immediate WWDG RESET.

Parameters:
None
Return values:
None

Definition at line 96 of file stm8s_wwdg.c.

References WWDG, and WWDG_CR_WDGA.


STM8S/A Standard Peripherals Drivers: STM8S_StdPeriph_Driver

Modules | Defines | Enumerations | Variables
STM8S_StdPeriph_Driver

Modules

Exported_types
MAP_FILE_Exported_Types_and_Constants
GPIO_Registers_Reset_Value
IWDG_Private_Define
IWDG_Private_Macros
IWDG_Exported_Types
IWDG_Exported_Functions
RST_Exported_Types
RST_Private_Macros
RST_Exported_functions
SPI_Exported_Types
SPI_Private_Macros

Macros used by the assert_param function to check the different functions parameters.

SPI_Exported_Functions
TIM1_Exported_Types
TIM1_Exported_Functions
TIM3_Exported_Types
TIM3_Exported_Functions
TIM4_Exported_Types
TIM4_Exported_Functions
TIM6_Exported_Types
TIM6_Private_Macros
TIM6_Exported_Functions
UART1_Exported_Types
UART1_Private_Macros
UART1_Exported_Functions
UART2_Exported_Types
UART2_Private_Macros
UART2_Exported_Functions
UART3_Exported_Types
UART3_Private_Macros
UART3_Exported_Functions
UART4_Exported_Types
UART4_Private_Macros
UART4_Exported_Functions
WWDG_Private_Macros
WWDG_Exported_Functions
ADC1_Public_Functions
ADC2_Public_Functions
AWU_Public_Functions
BEEP_Public_Functions
CAN_Public_Functions
CLK_Private_Constants
CLK_Public_Functions
EXTI_Public_Functions
FLASH_Public_functions
GPIO_Public_Functions
I2C_Private_Defines
I2C_Public_Functions
ITC_Private_Functions
ITC_Public_Functions
RST_Public_Functions
SPI_Public_Functions
TIM1_Public_Functions
TIM2_Public_Functions
TIM3_Public_Functions
TIM4_Public_Functions
TIM5_Public_Functions
TIM6_Public_Functions
UART1_Public_Functions
UART2_Public_Functions
UART3_Public_Functions
UART4_Public_Functions
WWDG_Public_Functions

Defines

#define | __STM8S_STDPERIPH_VERSION
#define | __STM8S_STDPERIPH_VERSION_MAIN ((uint8_t)0x02)
#define | __STM8S_STDPERIPH_VERSION_RC ((uint8_t)0x00)
#define | __STM8S_STDPERIPH_VERSION_SUB1 ((uint8_t)0x03)
#define | __STM8S_STDPERIPH_VERSION_SUB2 ((uint8_t)0x00)
#define | BIT_MASK ((uint8_t)0x7F)
#define | CAN_ACKNOWLEDGE_TIMEOUT ((uint16_t)0xFFFF)
#define | CAN_IDLIST_IDMASK_MASK ((uint8_t) 0x55)
#define | CAN_IDMASK_IDLIST_MASK ((uint8_t) 0xAA)
#define | CAN_MODE_MASK ((uint8_t) 0x03)
#define | CONST const
#define | EEPROM __eeprom
#define | FAR __far
#define | FLASH_CLEAR_BYTE ((uint8_t)0x00)
#define | FLASH_SET_BYTE ((uint8_t)0xFF)
#define | HSE_VALUE ((uint32_t)16000000)
In the following line adjust the value of External High Speed oscillator (HSE) used in your application.
#define | HSI_VALUE ((uint32_t)16000000)
Definition of Device on-chip RC oscillator frequencies.
#define | IN_RAM(a) a
#define | IS_TIM2_CHANNEL_OK(CHANNEL)
#define | IS_TIM2_CLEAR_FLAG_OK(FLAG) ((((uint16_t)(FLAG) & 0xF1F0) == 0x0000) && ((uint16_t)(FLAG) != 0x0000))
#define | IS_TIM2_EVENT_SOURCE_OK(SOURCE) (((SOURCE) != 0x00))
#define | IS_TIM2_FORCED_ACTION_OK(ACTION)
#define | IS_TIM2_GET_FLAG_OK(FLAG)
#define | IS_TIM2_GET_IT_OK(IT)
#define | IS_TIM2_IC_FILTER_OK(ICFILTER) ((ICFILTER) <= 0x0F)
TIM2 Input Capture Filer Value.
#define | IS_TIM2_IC_POLARITY_OK(POLARITY)
#define | IS_TIM2_IC_PRESCALER_OK(PRESCALER)
#define | IS_TIM2_IC_SELECTION1_OK(SELECTION)
#define | IS_TIM2_IC_SELECTION_OK(SELECTION)
#define | IS_TIM2_IT_OK(IT) (((IT) != 0x00) && ((IT) <= 0x0F))
#define | IS_TIM2_OC_MODE_OK(MODE)
#define | IS_TIM2_OC_POLARITY_OK(POLARITY)
#define | IS_TIM2_OCM_OK(MODE)
#define | IS_TIM2_OPM_MODE_OK(MODE)
#define | IS_TIM2_OUTPUT_STATE_OK(STATE)
#define | IS_TIM2_PRESCALER_OK(PRESCALER)
#define | IS_TIM2_PRESCALER_RELOAD_OK(RELOAD)
#define | IS_TIM2_PWMI_CHANNEL_OK(CHANNEL)
#define | IS_TIM2_UPDATE_SOURCE_OK(SOURCE)
#define | IS_TIM5_CHANNEL_OK(CHANNEL)
#define | IS_TIM5_CLEAR_FLAG_OK(FLAG) ((((uint16_t)(FLAG) & 0xF1F0) == 0x0000) && ((uint16_t)(FLAG) != 0x0000))
#define | IS_TIM5_ENCODER_MODE_OK(MODE)
Macro TIM5 encoder mode.
#define | IS_TIM5_EVENT_SOURCE_OK(SOURCE) (((SOURCE) != 0x00))
#define | IS_TIM5_EXT_FILTER_OK(EXTFILTER) ((EXTFILTER) <= 0x0F)
Macro TIM5 External Trigger Filter.
#define | IS_TIM5_EXT_POLARITY_OK(POLARITY)
Macro TIM5 Trigger Polarity.
#define | IS_TIM5_EXT_PRESCALER_OK(PRESCALER)
Macro TIM5 external trigger prescaler.
#define | IS_TIM5_FORCED_ACTION_OK(ACTION)
#define | IS_TIM5_GET_FLAG_OK(FLAG)
#define | IS_TIM5_GET_IT_OK(IT)
#define | IS_TIM5_IC_FILTER_OK(ICFILTER) ((ICFILTER) <= 0x0F)
TIM5 Input Capture Filer Value.
#define | IS_TIM5_IC_POLARITY_OK(POLARITY)
#define | IS_TIM5_IC_PRESCALER_OK(PRESCALER)
#define | IS_TIM5_IC_SELECTION1_OK(SELECTION)
#define | IS_TIM5_IC_SELECTION_OK(SELECTION)
#define | IS_TIM5_IT_OK(IT) (((IT) != 0x00) && ((IT) <= 0x4F))
#define | IS_TIM5_OC_MODE_OK(MODE)
#define | IS_TIM5_OC_POLARITY_OK(POLARITY)
#define | IS_TIM5_OCM_OK(MODE)
#define | IS_TIM5_OPM_MODE_OK(MODE)
#define | IS_TIM5_OUTPUT_STATE_OK(STATE)
#define | IS_TIM5_PRESCALER_OK(PRESCALER)
#define | IS_TIM5_PRESCALER_RELOAD_OK(RELOAD)
#define | IS_TIM5_PWMI_CHANNEL_OK(CHANNEL)
#define | IS_TIM5_SLAVE_MODE_OK(MODE)
Macro TIM5 Slave mode.
#define | IS_TIM5_TIX_TRIGGER_SELECTION_OK(SELECTION)
#define | IS_TIM5_TRGO_SOURCE_OK(SOURCE)
Macro TIM5 TRGO source.
#define | IS_TIM5_TRIGGER_SELECTION_OK(SELECTION)
Macro TIM5 Trigger Selection.
#define | IS_TIM5_UPDATE_SOURCE_OK(SOURCE)
#define | LSI_VALUE ((uint32_t)128000)
#define | MemoryAddressCast uint32_t
#define | NEAR __near
#define | OPERATION_TIMEOUT ((uint16_t)0xFFFF)
#define | PointerAttr FAR
#define | TINY __tiny
#define | USE_STDPERIPH_DRIVER

Enumerations

enum | TIM2_Channel_TypeDef { TIM2_CHANNEL_1 = ((uint8_t)0x00), TIM2_CHANNEL_2 = ((uint8_t)0x01), TIM2_CHANNEL_3 = ((uint8_t)0x02) }
TIM2 Channel. More...
enum | TIM2_EventSource_TypeDef { TIM2_EVENTSOURCE_UPDATE = ((uint8_t)0x01), TIM2_EVENTSOURCE_CC1 = ((uint8_t)0x02), TIM2_EVENTSOURCE_CC2 = ((uint8_t)0x04), TIM2_EVENTSOURCE_CC3 = ((uint8_t)0x08) }
TIM2 Event Source. More...
enum TIM2_FLAG_TypeDef {
TIM2_FLAG_UPDATE = ((uint16_t)0x0001), TIM2_FLAG_CC1 = ((uint16_t)0x0002), TIM2_FLAG_CC2 = ((uint16_t)0x0004), TIM2_FLAG_CC3 = ((uint16_t)0x0008),
TIM2_FLAG_CC1OF = ((uint16_t)0x0200), TIM2_FLAG_CC2OF = ((uint16_t)0x0400), TIM2_FLAG_CC3OF = ((uint16_t)0x0800)
}
TIM2 Flags. More...
enum | TIM2_ForcedAction_TypeDef { TIM2_FORCEDACTION_ACTIVE = ((uint8_t)0x50), TIM2_FORCEDACTION_INACTIVE = ((uint8_t)0x40) }
TIM2 Forced Action. More...
enum | TIM2_ICPolarity_TypeDef { TIM2_ICPOLARITY_RISING = ((uint8_t)0x00), TIM2_ICPOLARITY_FALLING = ((uint8_t)0x44) }
TIM2 Input Capture Polarity. More...
enum | TIM2_ICPSC_TypeDef { TIM2_ICPSC_DIV1 = ((uint8_t)0x00), TIM2_ICPSC_DIV2 = ((uint8_t)0x04), TIM2_ICPSC_DIV4 = ((uint8_t)0x08), TIM2_ICPSC_DIV8 = ((uint8_t)0x0C) }
TIM2 Input Capture Prescaler. More...
enum | TIM2_ICSelection_TypeDef { TIM2_ICSELECTION_DIRECTTI = ((uint8_t)0x01), TIM2_ICSELECTION_INDIRECTTI = ((uint8_t)0x02), TIM2_ICSELECTION_TRGI = ((uint8_t)0x03) }
TIM2 Input Capture Selection. More...
enum | TIM2_IT_TypeDef { TIM2_IT_UPDATE = ((uint8_t)0x01), TIM2_IT_CC1 = ((uint8_t)0x02), TIM2_IT_CC2 = ((uint8_t)0x04), TIM2_IT_CC3 = ((uint8_t)0x08) }
TIM2 interrupt sources. More...
enum TIM2_OCMode_TypeDef {
TIM2_OCMODE_TIMING = ((uint8_t)0x00), TIM2_OCMODE_ACTIVE = ((uint8_t)0x10), TIM2_OCMODE_INACTIVE = ((uint8_t)0x20), TIM2_OCMODE_TOGGLE = ((uint8_t)0x30),
TIM2_OCMODE_PWM1 = ((uint8_t)0x60), TIM2_OCMODE_PWM2 = ((uint8_t)0x70)
}
TIM2 Output Compare and PWM modes. More...
enum | TIM2_OCPolarity_TypeDef { TIM2_OCPOLARITY_HIGH = ((uint8_t)0x00), TIM2_OCPOLARITY_LOW = ((uint8_t)0x22) }
TIM2 Output Compare Polarity. More...
enum | TIM2_OPMode_TypeDef { TIM2_OPMODE_SINGLE = ((uint8_t)0x01), TIM2_OPMODE_REPETITIVE = ((uint8_t)0x00) }
TIM2 One Pulse Mode. More...
enum | TIM2_OutputState_TypeDef { TIM2_OUTPUTSTATE_DISABLE = ((uint8_t)0x00), TIM2_OUTPUTSTATE_ENABLE = ((uint8_t)0x11) }
TIM2 Output Compare states. More...
enum TIM2_Prescaler_TypeDef {
TIM2_PRESCALER_1 = ((uint8_t)0x00), TIM2_PRESCALER_2 = ((uint8_t)0x01), TIM2_PRESCALER_4 = ((uint8_t)0x02), TIM2_PRESCALER_8 = ((uint8_t)0x03),
TIM2_PRESCALER_16 = ((uint8_t)0x04), TIM2_PRESCALER_32 = ((uint8_t)0x05), TIM2_PRESCALER_64 = ((uint8_t)0x06), TIM2_PRESCALER_128 = ((uint8_t)0x07),
TIM2_PRESCALER_256 = ((uint8_t)0x08), TIM2_PRESCALER_512 = ((uint8_t)0x09), TIM2_PRESCALER_1024 = ((uint8_t)0x0A), TIM2_PRESCALER_2048 = ((uint8_t)0x0B),
TIM2_PRESCALER_4096 = ((uint8_t)0x0C), TIM2_PRESCALER_8192 = ((uint8_t)0x0D), TIM2_PRESCALER_16384 = ((uint8_t)0x0E), TIM2_PRESCALER_32768 = ((uint8_t)0x0F)
}
TIM2 Prescaler. More...
enum | TIM2_PSCReloadMode_TypeDef { TIM2_PSCRELOADMODE_UPDATE = ((uint8_t)0x00), TIM2_PSCRELOADMODE_IMMEDIATE = ((uint8_t)0x01) }
TIM2 Prescaler Reload Mode. More...
enum | TIM2_UpdateSource_TypeDef { TIM2_UPDATESOURCE_GLOBAL = ((uint8_t)0x00), TIM2_UPDATESOURCE_REGULAR = ((uint8_t)0x01) }
TIM2 Update Source. More...
enum | TIM5_Channel_TypeDef { TIM5_CHANNEL_1 = ((uint8_t)0x00), TIM5_CHANNEL_2 = ((uint8_t)0x01), TIM5_CHANNEL_3 = ((uint8_t)0x02) }
TIM5 Channel. More...
enum | TIM5_EncoderMode_TypeDef { TIM5_ENCODERMODE_TI1 = ((uint8_t)0x01), TIM5_ENCODERMODE_TI2 = ((uint8_t)0x02), TIM5_ENCODERMODE_TI12 = ((uint8_t)0x03) }
TIM5 Encoder Mode. More...
enum TIM5_EventSource_TypeDef {
TIM5_EVENTSOURCE_UPDATE = ((uint8_t)0x01), TIM5_EVENTSOURCE_CC1 = ((uint8_t)0x02), TIM5_EVENTSOURCE_CC2 = ((uint8_t)0x04), TIM5_EVENTSOURCE_CC3 = ((uint8_t)0x08),
TIM5_EVENTSOURCE_TRIGGER = ((uint8_t)0x40)
}
TIM5 Event Source. More...
enum | TIM5_ExtTRGPolarity_TypeDef { TIM5_EXTTRGPOLARITY_INVERTED = ((uint8_t)0x80), TIM5_EXTTRGPOLARITY_NONINVERTED = ((uint8_t)0x00) }
TIM5 External Trigger Polarity. More...
enum | TIM5_ExtTRGPSC_TypeDef { TIM5_EXTTRGPSC_OFF = ((uint8_t)0x00), TIM5_EXTTRGPSC_DIV2 = ((uint8_t)0x10), TIM5_EXTTRGPSC_DIV4 = ((uint8_t)0x20), TIM5_EXTTRGPSC_DIV8 = ((uint8_t)0x30) }
TIM5 External Trigger Prescaler. More...
enum TIM5_FLAG_TypeDef {
TIM5_FLAG_UPDATE = ((uint16_t)0x0001), TIM5_FLAG_CC1 = ((uint16_t)0x0002), TIM5_FLAG_CC2 = ((uint16_t)0x0004), TIM5_FLAG_CC3 = ((uint16_t)0x0008),
TIM5_FLAG_TRIGGER = ((uint16_t)0x0040), TIM5_FLAG_CC1OF = ((uint16_t)0x0200), TIM5_FLAG_CC2OF = ((uint16_t)0x0400), TIM5_FLAG_CC3OF = ((uint16_t)0x0800)
}
TIM5 Flags. More...
enum | TIM5_ForcedAction_TypeDef { TIM5_FORCEDACTION_ACTIVE = ((uint8_t)0x50), TIM5_FORCEDACTION_INACTIVE = ((uint8_t)0x40) }
TIM5 Forced Action. More...
enum | TIM5_ICPolarity_TypeDef { TIM5_ICPOLARITY_RISING = ((uint8_t)0x00), TIM5_ICPOLARITY_FALLING = ((uint8_t)0x44) }
TIM5 Input Capture Polarity. More...
enum | TIM5_ICPSC_TypeDef { TIM5_ICPSC_DIV1 = ((uint8_t)0x00), TIM5_ICPSC_DIV2 = ((uint8_t)0x04), TIM5_ICPSC_DIV4 = ((uint8_t)0x08), TIM5_ICPSC_DIV8 = ((uint8_t)0x0C) }
TIM5 Input Capture Prescaler. More...
enum | TIM5_ICSelection_TypeDef { TIM5_ICSELECTION_DIRECTTI = ((uint8_t)0x01), TIM5_ICSELECTION_INDIRECTTI = ((uint8_t)0x02), TIM5_ICSELECTION_TRGI = ((uint8_t)0x03) }
TIM5 Input Capture Selection. More...
enum TIM5_IT_TypeDef {
TIM5_IT_UPDATE = ((uint8_t)0x01), TIM5_IT_CC1 = ((uint8_t)0x02), TIM5_IT_CC2 = ((uint8_t)0x04), TIM5_IT_CC3 = ((uint8_t)0x08),
TIM5_IT_TRIGGER = ((uint8_t)0x40)
}
TIM5 interrupt sources. More...
enum TIM5_OCMode_TypeDef {
TIM5_OCMODE_TIMING = ((uint8_t)0x00), TIM5_OCMODE_ACTIVE = ((uint8_t)0x10), TIM5_OCMODE_INACTIVE = ((uint8_t)0x20), TIM5_OCMODE_TOGGLE = ((uint8_t)0x30),
TIM5_OCMODE_PWM1 = ((uint8_t)0x60), TIM5_OCMODE_PWM2 = ((uint8_t)0x70)
}
TIM5 Output Compare and PWM modes. More...
enum | TIM5_OCPolarity_TypeDef { TIM5_OCPOLARITY_HIGH = ((uint8_t)0x00), TIM5_OCPOLARITY_LOW = ((uint8_t)0x22) }
TIM5 Output Compare Polarity. More...
enum | TIM5_OPMode_TypeDef { TIM5_OPMODE_SINGLE = ((uint8_t)0x01), TIM5_OPMODE_REPETITIVE = ((uint8_t)0x00) }
TIM5 One Pulse Mode. More...
enum | TIM5_OutputState_TypeDef { TIM5_OUTPUTSTATE_DISABLE = ((uint8_t)0x00), TIM5_OUTPUTSTATE_ENABLE = ((uint8_t)0x11) }
TIM5 Output Compare states. More...
enum TIM5_Prescaler_TypeDef {
TIM5_PRESCALER_1 = ((uint8_t)0x00), TIM5_PRESCALER_2 = ((uint8_t)0x01), TIM5_PRESCALER_4 = ((uint8_t)0x02), TIM5_PRESCALER_8 = ((uint8_t)0x03),
TIM5_PRESCALER_16 = ((uint8_t)0x04), TIM5_PRESCALER_32 = ((uint8_t)0x05), TIM5_PRESCALER_64 = ((uint8_t)0x06), TIM5_PRESCALER_128 = ((uint8_t)0x07),
TIM5_PRESCALER_256 = ((uint8_t)0x08), TIM5_PRESCALER_512 = ((uint8_t)0x09), TIM5_PRESCALER_1024 = ((uint8_t)0x0A), TIM5_PRESCALER_2048 = ((uint8_t)0x0B),
TIM5_PRESCALER_4096 = ((uint8_t)0x0C), TIM5_PRESCALER_8192 = ((uint8_t)0x0D), TIM5_PRESCALER_16384 = ((uint8_t)0x0E), TIM5_PRESCALER_32768 = ((uint8_t)0x0F)
}
TIM5 Prescaler. More...
enum | TIM5_PSCReloadMode_TypeDef { TIM5_PSCRELOADMODE_UPDATE = ((uint8_t)0x00), TIM5_PSCRELOADMODE_IMMEDIATE = ((uint8_t)0x01) }
TIM5 Prescaler Reload Mode. More...
enum | TIM5_SlaveMode_TypeDef { TIM5_SLAVEMODE_RESET = ((uint8_t)0x04), TIM5_SLAVEMODE_GATED = ((uint8_t)0x05), TIM5_SLAVEMODE_TRIGGER = ((uint8_t)0x06), TIM5_SLAVEMODE_EXTERNAL1 = ((uint8_t)0x07) }
TIM5 Slave Mode. More...
enum TIM5_TRGOSource_TypeDef {
TIM5_TRGOSOURCE_RESET = ((uint8_t)0x00), TIM5_TRGOSOURCE_ENABLE = ((uint8_t)0x10), TIM5_TRGOSOURCE_UPDATE = ((uint8_t)0x20), TIM5_TRGOSOURCE_OC1 = ((uint8_t)0x30),
TIM5_TRGOSOURCE_OC1REF = ((uint8_t)0x40), TIM5_TRGOSOURCE_OC2REF = ((uint8_t)0x50)
}
TIM5 Trigger Output Source. More...
enum | TIM5_TS_TypeDef { TIM5_TS_TIM6 = ((uint8_t)0x00), TIM5_TS_TIM1 = ((uint8_t)0x03) }
TIM5 Internal Trigger Selection. More...
enum | TIM5_UpdateSource_TypeDef { TIM5_UPDATESOURCE_GLOBAL = ((uint8_t)0x00), TIM5_UPDATESOURCE_REGULAR = ((uint8_t)0x01) }
TIM5 Update Source. More...

Variables

__IO uint8_t | _Data [8] = {0}
__IO uint8_t | _DLC = 0
__IO uint8_t | _FMI = 0
__IO uint32_t | _Id = 0
__IO uint8_t | _IDE = 0
__IO uint8_t | _RTR = 0
CONST uint8_t | APR_Array [17]
Contains the different values to write in the APR register (used by AWU_Init function)
CONST uint8_t | TBR_Array [17]
Contains the different values to write in the TBR register (used by AWU_Init function)

Define Documentation

#define __STM8S_STDPERIPH_VERSION
Value:
( (__STM8S_STDPERIPH_VERSION_MAIN << 24)\
                                          |(__STM8S_STDPERIPH_VERSION_SUB1 << 16)\
                                          |(__STM8S_STDPERIPH_VERSION_SUB2 << 8)\
                                          |(__STM8S_STDPERIPH_VERSION_RC))

Definition at line 186 of file stm8s.h.

#define __STM8S_STDPERIPH_VERSION_MAIN ((uint8_t)0x02)

< [31:16] STM8S Standard Peripheral Library main version V2.3.0 [31:24] main version

Definition at line 182 of file stm8s.h.

#define __STM8S_STDPERIPH_VERSION_RC ((uint8_t)0x00)

[7:0] release candidate

Definition at line 185 of file stm8s.h.

#define __STM8S_STDPERIPH_VERSION_SUB1 ((uint8_t)0x03)

[23:16] sub1 version

Definition at line 183 of file stm8s.h.

#define __STM8S_STDPERIPH_VERSION_SUB2 ((uint8_t)0x00)

[15:8] sub2 version

Definition at line 184 of file stm8s.h.

#define BIT_MASK ((uint8_t)0x7F)

Definition at line 35 of file stm8s_wwdg.c.

Referenced by WWDG_SetCounter().

#define CAN_ACKNOWLEDGE_TIMEOUT ((uint16_t)0xFFFF)

Definition at line 39 of file stm8s_can.c.

Referenced by CAN_Init(), and CAN_OperatingModeRequest().

#define CAN_IDLIST_IDMASK_MASK ((uint8_t) 0x55)

Definition at line 36 of file stm8s_can.c.

Referenced by CAN_FilterInit().

#define CAN_IDMASK_IDLIST_MASK ((uint8_t) 0xAA)

Definition at line 37 of file stm8s_can.c.

Referenced by CAN_FilterInit().

#define CAN_MODE_MASK ((uint8_t) 0x03)

Definition at line 38 of file stm8s_can.c.

Referenced by CAN_OperatingModeRequest().

#define CONST const

Definition at line 146 of file stm8s.h.

#define EEPROM __eeprom

Definition at line 145 of file stm8s.h.

#define FAR __far

Definition at line 142 of file stm8s.h.

#define FLASH_CLEAR_BYTE ((uint8_t)0x00)
 This driver provides functions to configure and program the Flash memory of all
 STM8S devices.

 It includes as well functions that can be either executed from RAM or not, and
 other functions that must be executed from RAM otherwise useless.

 The table below lists the functions that can be executed from RAM.

 +--------------------------------------------------------------------------------|
 |   Functions prototypes      |    RAM execution            |     Comments       |
 ---------------------------------------------------------------------------------|
 |                             | Mandatory in case of block  | Can be executed    |
 | FLASH_WaitForLastOperation  | Operation:                  | from Flash in case |
 |                             | - Block programming         | of byte and word   |
 |                             | - Block erase               | Operations         |
 |--------------------------------------------------------------------------------|
 | FLASH_ProgramBlock          |       Exclusively           | useless from Flash |
 |--------------------------------------------------------------------------------|
 | FLASH_EraseBlock            |       Exclusively           | useless from Flash |
 |--------------------------------------------------------------------------------|

 To be able to execute functions from RAM several steps have to be followed.
 These steps may differ from one toolchain to another.
 A detailed description is available below within this driver.
 You can also refer to the FLASH examples provided within the
 STM8S_StdPeriph_Lib package.

Definition at line 69 of file stm8s_flash.c.

Referenced by FLASH_EraseByte(), and FLASH_EraseOptionByte().

#define FLASH_SET_BYTE ((uint8_t)0xFF)

Definition at line 70 of file stm8s_flash.c.

Referenced by FLASH_EraseOptionByte().

#define HSE_VALUE ((uint32_t)16000000)

In the following line adjust the value of External High Speed oscillator (HSE) used in your application.

Tip: To avoid modifying this file each time you need to use different HSE, you can define the HSE value in your toolchain compiler preprocessor.

Definition at line 111 of file stm8s.h.

Referenced by CLK_GetClockFreq().

#define HSI_VALUE ((uint32_t)16000000)

Definition of Device on-chip RC oscillator frequencies.

Typical Value of the HSI in Hz

Definition at line 118 of file stm8s.h.

Referenced by CLK_GetClockFreq().

#define IN_RAM ( a ) a

Definition at line 178 of file stm8s.h.

#define IS_TIM2_CHANNEL_OK ( CHANNEL )
Value:
(((CHANNEL) == TIM2_CHANNEL_1) || \
                                     ((CHANNEL) == TIM2_CHANNEL_2) || \
                                     ((CHANNEL) == TIM2_CHANNEL_3))

Definition at line 135 of file stm8s_tim2.h.

Referenced by TIM2_CCxCmd(), TIM2_ICInit(), and TIM2_SelectOCxM().

#define IS_TIM2_CLEAR_FLAG_OK ( FLAG ) ((((uint16_t)(FLAG) & 0xF1F0) == 0x0000) && ((uint16_t)(FLAG) != 0x0000))

Definition at line 271 of file stm8s_tim2.h.

Referenced by TIM2_ClearFlag().

#define IS_TIM2_EVENT_SOURCE_OK ( SOURCE ) (((SOURCE) != 0x00))

Definition at line 239 of file stm8s_tim2.h.

Referenced by TIM2_GenerateEvent().

#define IS_TIM2_FORCED_ACTION_OK ( ACTION )
Value:
(((ACTION) == TIM2_FORCEDACTION_ACTIVE) || \
    ((ACTION) == TIM2_FORCEDACTION_INACTIVE))

Definition at line 49 of file stm8s_tim2.h.

Referenced by TIM2_ForcedOC1Config(), TIM2_ForcedOC2Config(), and TIM2_ForcedOC3Config().

#define IS_TIM2_GET_FLAG_OK ( FLAG )
Value:
(((FLAG) == TIM2_FLAG_UPDATE) || \
                                   ((FLAG) == TIM2_FLAG_CC1) || \
                                   ((FLAG) == TIM2_FLAG_CC2) || \
                                   ((FLAG) == TIM2_FLAG_CC3) || \
                                   ((FLAG) == TIM2_FLAG_CC1OF) || \
                                   ((FLAG) == TIM2_FLAG_CC2OF) || \
                                   ((FLAG) == TIM2_FLAG_CC3OF))

Definition at line 263 of file stm8s_tim2.h.

Referenced by TIM2_GetFlagStatus().

#define IS_TIM2_GET_IT_OK ( IT )
Value:
(((IT) == TIM2_IT_UPDATE) || \
                               ((IT) == TIM2_IT_CC1) || \
                               ((IT) == TIM2_IT_CC2) || \
                               ((IT) == TIM2_IT_CC3))

Definition at line 215 of file stm8s_tim2.h.

Referenced by TIM2_GetITStatus().

#define IS_TIM2_IC_FILTER_OK ( ICFILTER ) ((ICFILTER) <= 0x0F)

TIM2 Input Capture Filer Value.

Definition at line 202 of file stm8s_tim2.h.

Referenced by TIM2_ICInit().

#define IS_TIM2_IC_POLARITY_OK ( POLARITY )
Value:
(((POLARITY) == TIM2_ICPOLARITY_RISING) || \
    ((POLARITY) == TIM2_ICPOLARITY_FALLING))

Definition at line 169 of file stm8s_tim2.h.

Referenced by TIM2_ICInit(), and TIM2_PWMIConfig().

#define IS_TIM2_IC_PRESCALER_OK ( PRESCALER )
Value:
(((PRESCALER) == TIM2_ICPSC_DIV1) || \
    ((PRESCALER) == TIM2_ICPSC_DIV2) || \
    ((PRESCALER) == TIM2_ICPSC_DIV4) || \
    ((PRESCALER) == TIM2_ICPSC_DIV8))

Definition at line 196 of file stm8s_tim2.h.

Referenced by TIM2_ICInit(), TIM2_PWMIConfig(), TIM2_SetIC1Prescaler(), TIM2_SetIC2Prescaler(), and TIM2_SetIC3Prescaler().

#define IS_TIM2_IC_SELECTION1_OK ( SELECTION )
Value:
(((SELECTION) == TIM2_ICSELECTION_DIRECTTI) || \
    ((SELECTION) == TIM2_ICSELECTION_TRGI))

Definition at line 184 of file stm8s_tim2.h.

#define IS_TIM2_IC_SELECTION_OK ( SELECTION )
Value:
(((SELECTION) == TIM2_ICSELECTION_DIRECTTI) || \
    ((SELECTION) == TIM2_ICSELECTION_INDIRECTTI) || \
    ((SELECTION) == TIM2_ICSELECTION_TRGI))

Definition at line 180 of file stm8s_tim2.h.

Referenced by TIM2_ICInit(), and TIM2_PWMIConfig().

#define IS_TIM2_IT_OK ( IT ) (((IT) != 0x00) && ((IT) <= 0x0F))

Definition at line 213 of file stm8s_tim2.h.

Referenced by TIM2_ClearITPendingBit(), and TIM2_ITConfig().

#define IS_TIM2_OC_MODE_OK ( MODE )
Value:
(((MODE) ==  TIM2_OCMODE_TIMING) || \
                                  ((MODE) == TIM2_OCMODE_ACTIVE) || \
                                  ((MODE) == TIM2_OCMODE_INACTIVE) || \
                                  ((MODE) == TIM2_OCMODE_TOGGLE)|| \
                                  ((MODE) == TIM2_OCMODE_PWM1) || \
                                  ((MODE) == TIM2_OCMODE_PWM2))

Definition at line 101 of file stm8s_tim2.h.

Referenced by TIM2_OC1Init(), TIM2_OC2Init(), and TIM2_OC3Init().

#define IS_TIM2_OC_POLARITY_OK ( POLARITY )
Value:
(((POLARITY) == TIM2_OCPOLARITY_HIGH) || \
    ((POLARITY) == TIM2_OCPOLARITY_LOW))

Definition at line 149 of file stm8s_tim2.h.

Referenced by TIM2_OC1Init(), TIM2_OC1PolarityConfig(), TIM2_OC2Init(), TIM2_OC2PolarityConfig(), TIM2_OC3Init(), and TIM2_OC3PolarityConfig().

#define IS_TIM2_OCM_OK ( MODE )
Value:
(((MODE) ==  TIM2_OCMODE_TIMING) || \
                             ((MODE) == TIM2_OCMODE_ACTIVE) || \
                             ((MODE) == TIM2_OCMODE_INACTIVE) || \
                             ((MODE) == TIM2_OCMODE_TOGGLE)|| \
                             ((MODE) == TIM2_OCMODE_PWM1) || \
                             ((MODE) == TIM2_OCMODE_PWM2) || \
                             ((MODE) == (uint8_t)TIM2_FORCEDACTION_ACTIVE) || \
                             ((MODE) == (uint8_t)TIM2_FORCEDACTION_INACTIVE))

Definition at line 108 of file stm8s_tim2.h.

Referenced by TIM2_SelectOCxM().

#define IS_TIM2_OPM_MODE_OK ( MODE )
Value:
(((MODE) == TIM2_OPMODE_SINGLE) || \
                                   ((MODE) == TIM2_OPMODE_REPETITIVE))

Definition at line 124 of file stm8s_tim2.h.

Referenced by TIM2_SelectOnePulseMode().

#define IS_TIM2_OUTPUT_STATE_OK ( STATE )
Value:
(((STATE) == TIM2_OUTPUTSTATE_DISABLE) || \
                                        ((STATE) == TIM2_OUTPUTSTATE_ENABLE))

Definition at line 159 of file stm8s_tim2.h.

Referenced by TIM2_OC1Init(), TIM2_OC2Init(), and TIM2_OC3Init().

#define IS_TIM2_PRESCALER_OK ( PRESCALER )
Value:
(((PRESCALER) == TIM2_PRESCALER_1  ) || \
    ((PRESCALER) == TIM2_PRESCALER_2    ) || \
    ((PRESCALER) == TIM2_PRESCALER_4    ) || \
    ((PRESCALER) == TIM2_PRESCALER_8  ) || \
    ((PRESCALER) == TIM2_PRESCALER_16   ) || \
    ((PRESCALER) == TIM2_PRESCALER_32     ) || \
    ((PRESCALER) == TIM2_PRESCALER_64    ) || \
    ((PRESCALER) == TIM2_PRESCALER_128   ) || \
    ((PRESCALER) == TIM2_PRESCALER_256   ) || \
    ((PRESCALER) == TIM2_PRESCALER_512   ) || \
    ((PRESCALER) == TIM2_PRESCALER_1024  ) || \
    ((PRESCALER) == TIM2_PRESCALER_2048 ) || \
    ((PRESCALER) == TIM2_PRESCALER_4096 ) || \
    ((PRESCALER) == TIM2_PRESCALER_8192 ) || \
    ((PRESCALER) == TIM2_PRESCALER_16384 ) || \
    ((PRESCALER) == TIM2_PRESCALER_32768 ))

Definition at line 73 of file stm8s_tim2.h.

Referenced by TIM2_PrescalerConfig().

#define IS_TIM2_PRESCALER_RELOAD_OK ( RELOAD )
Value:
(((RELOAD) == TIM2_PSCRELOADMODE_UPDATE) || \
    ((RELOAD) == TIM2_PSCRELOADMODE_IMMEDIATE))

Definition at line 227 of file stm8s_tim2.h.

Referenced by TIM2_PrescalerConfig().

#define IS_TIM2_PWMI_CHANNEL_OK ( CHANNEL )
Value:
(((CHANNEL) == TIM2_CHANNEL_1) || \
    ((CHANNEL) == TIM2_CHANNEL_2))

Definition at line 139 of file stm8s_tim2.h.

Referenced by TIM2_PWMIConfig().

#define IS_TIM2_UPDATE_SOURCE_OK ( SOURCE )
Value:
(((SOURCE) == TIM2_UPDATESOURCE_GLOBAL) || \
    ((SOURCE) == TIM2_UPDATESOURCE_REGULAR))

Definition at line 248 of file stm8s_tim2.h.

Referenced by TIM2_UpdateRequestConfig().

#define IS_TIM5_CHANNEL_OK ( CHANNEL )
Value:
(((CHANNEL) == TIM5_CHANNEL_1) || \
                                     ((CHANNEL) == TIM5_CHANNEL_2) || \
                                     ((CHANNEL) == TIM5_CHANNEL_3))

Definition at line 135 of file stm8s_tim5.h.

Referenced by TIM5_CCxCmd(), TIM5_ICInit(), and TIM5_SelectOCxM().

#define IS_TIM5_CLEAR_FLAG_OK ( FLAG ) ((((uint16_t)(FLAG) & 0xF1F0) == 0x0000) && ((uint16_t)(FLAG) != 0x0000))

Definition at line 301 of file stm8s_tim5.h.

Referenced by TIM5_ClearFlag().

#define IS_TIM5_ENCODER_MODE_OK ( MODE )
Value:
(((MODE) == TIM5_ENCODERMODE_TI1) || \
    ((MODE) == TIM5_ENCODERMODE_TI2) || \
    ((MODE) == TIM5_ENCODERMODE_TI12))

Macro TIM5 encoder mode.

Definition at line 359 of file stm8s_tim5.h.

Referenced by TIM5_EncoderInterfaceConfig().

#define IS_TIM5_EVENT_SOURCE_OK ( SOURCE ) (((SOURCE) != 0x00))

Definition at line 242 of file stm8s_tim5.h.

Referenced by TIM5_GenerateEvent().

#define IS_TIM5_EXT_FILTER_OK ( EXTFILTER ) ((EXTFILTER) <= 0x0F)

Macro TIM5 External Trigger Filter.

Definition at line 403 of file stm8s_tim5.h.

#define IS_TIM5_EXT_POLARITY_OK ( POLARITY )
Value:
(((POLARITY) == TIM5_EXTTRGPOLARITY_INVERTED) || \
    ((POLARITY) == TIM5_EXTTRGPOLARITY_NONINVERTED))

Macro TIM5 Trigger Polarity.

Definition at line 396 of file stm8s_tim5.h.

#define IS_TIM5_EXT_PRESCALER_OK ( PRESCALER )
Value:
(((PRESCALER) == TIM5_EXTTRGPSC_OFF)  || \
    ((PRESCALER) == TIM5_EXTTRGPSC_DIV2) || \
    ((PRESCALER) == TIM5_EXTTRGPSC_DIV4) || \
    ((PRESCALER) == TIM5_EXTTRGPSC_DIV8))

Macro TIM5 external trigger prescaler.

Definition at line 378 of file stm8s_tim5.h.

#define IS_TIM5_FORCED_ACTION_OK ( ACTION )
Value:
(((ACTION) == TIM5_FORCEDACTION_ACTIVE) || \
                                       ((ACTION) == TIM5_FORCEDACTION_INACTIVE))

Definition at line 49 of file stm8s_tim5.h.

Referenced by TIM5_ForcedOC1Config(), TIM5_ForcedOC2Config(), and TIM5_ForcedOC3Config().

#define IS_TIM5_GET_FLAG_OK ( FLAG )
Value:
(((FLAG) == TIM5_FLAG_UPDATE) || \
                                ((FLAG) == TIM5_FLAG_CC1) || \
                                ((FLAG) == TIM5_FLAG_CC2) || \
                                ((FLAG) == TIM5_FLAG_CC3) || \
                                ((FLAG) == TIM5_FLAG_TRIGGER) || \
                                ((FLAG) == TIM5_FLAG_CC1OF) || \
                                ((FLAG) == TIM5_FLAG_CC2OF) || \
                                ((FLAG) == TIM5_FLAG_CC3OF))

Definition at line 292 of file stm8s_tim5.h.

Referenced by TIM5_GetFlagStatus().

#define IS_TIM5_GET_IT_OK ( IT )
Value:
(((IT) == TIM5_IT_UPDATE) || \
                            ((IT) == TIM5_IT_CC1) || \
                            ((IT) == TIM5_IT_CC2) || \
                            ((IT) == TIM5_IT_CC3) || \
                            ((IT) == TIM5_IT_TRIGGER))

Definition at line 216 of file stm8s_tim5.h.

Referenced by TIM5_GetITStatus().

#define IS_TIM5_IC_FILTER_OK ( ICFILTER ) ((ICFILTER) <= 0x0F)

TIM5 Input Capture Filer Value.

Definition at line 202 of file stm8s_tim5.h.

Referenced by TIM5_ICInit().

#define IS_TIM5_IC_POLARITY_OK ( POLARITY )
Value:
(((POLARITY) == TIM5_ICPOLARITY_RISING) || \
                                       ((POLARITY) == TIM5_ICPOLARITY_FALLING))

Definition at line 169 of file stm8s_tim5.h.

Referenced by TIM5_EncoderInterfaceConfig(), TIM5_ICInit(), and TIM5_PWMIConfig().

#define IS_TIM5_IC_PRESCALER_OK ( PRESCALER )
Value:
(((PRESCALER) == TIM5_ICPSC_DIV1) || \
                                         ((PRESCALER) == TIM5_ICPSC_DIV2) || \
                                         ((PRESCALER) == TIM5_ICPSC_DIV4) || \
                                         ((PRESCALER) == TIM5_ICPSC_DIV8))

Definition at line 196 of file stm8s_tim5.h.

Referenced by TIM5_ICInit(), TIM5_PWMIConfig(), TIM5_SetIC1Prescaler(), TIM5_SetIC2Prescaler(), and TIM5_SetIC3Prescaler().

#define IS_TIM5_IC_SELECTION1_OK ( SELECTION )
Value:
(((SELECTION) == TIM5_ICSELECTION_DIRECTTI) || \
                                             ((SELECTION) == TIM5_ICSELECTION_TRGI))

Definition at line 184 of file stm8s_tim5.h.

#define IS_TIM5_IC_SELECTION_OK ( SELECTION )
Value:
(((SELECTION) == TIM5_ICSELECTION_DIRECTTI) || \
                                           ((SELECTION) == TIM5_ICSELECTION_INDIRECTTI) || \
                                           ((SELECTION) == TIM5_ICSELECTION_TRGI))

Definition at line 180 of file stm8s_tim5.h.

Referenced by TIM5_ICInit(), and TIM5_PWMIConfig().

#define IS_TIM5_IT_OK ( IT ) (((IT) != 0x00) && ((IT) <= 0x4F))

Definition at line 214 of file stm8s_tim5.h.

Referenced by TIM5_ClearITPendingBit(), and TIM5_ITConfig().

#define IS_TIM5_OC_MODE_OK ( MODE )
Value:
(((MODE) ==  TIM5_OCMODE_TIMING) || \
                                  ((MODE) == TIM5_OCMODE_ACTIVE) || \
                                  ((MODE) == TIM5_OCMODE_INACTIVE) || \
                                  ((MODE) == TIM5_OCMODE_TOGGLE)|| \
                                  ((MODE) == TIM5_OCMODE_PWM1) || \
                                  ((MODE) == TIM5_OCMODE_PWM2))

Definition at line 101 of file stm8s_tim5.h.

Referenced by TIM5_OC1Init(), TIM5_OC2Init(), and TIM5_OC3Init().

#define IS_TIM5_OC_POLARITY_OK ( POLARITY )
Value:
(((POLARITY) == TIM5_OCPOLARITY_HIGH) || \
                                       ((POLARITY) == TIM5_OCPOLARITY_LOW))

Definition at line 149 of file stm8s_tim5.h.

Referenced by TIM5_OC1Init(), TIM5_OC1PolarityConfig(), TIM5_OC2Init(), TIM5_OC2PolarityConfig(), TIM5_OC3Init(), and TIM5_OC3PolarityConfig().

#define IS_TIM5_OCM_OK ( MODE )
Value:
(((MODE) ==  TIM5_OCMODE_TIMING) || \
                             ((MODE) == TIM5_OCMODE_ACTIVE) || \
                             ((MODE) == TIM5_OCMODE_INACTIVE) || \
                             ((MODE) == TIM5_OCMODE_TOGGLE)|| \
                             ((MODE) == TIM5_OCMODE_PWM1) || \
                             ((MODE) == TIM5_OCMODE_PWM2) ||  \
                             ((MODE) == (uint8_t)TIM5_FORCEDACTION_ACTIVE) || \
                             ((MODE) == (uint8_t)TIM5_FORCEDACTION_INACTIVE))

Definition at line 108 of file stm8s_tim5.h.

Referenced by TIM5_SelectOCxM().

#define IS_TIM5_OPM_MODE_OK ( MODE )
Value:
(((MODE) == TIM5_OPMODE_SINGLE) || \
                                   ((MODE) == TIM5_OPMODE_REPETITIVE))

Definition at line 124 of file stm8s_tim5.h.

Referenced by TIM5_SelectOnePulseMode().

#define IS_TIM5_OUTPUT_STATE_OK ( STATE )
Value:
(((STATE) == TIM5_OUTPUTSTATE_DISABLE) || \
                                     ((STATE) == TIM5_OUTPUTSTATE_ENABLE))

Definition at line 159 of file stm8s_tim5.h.

Referenced by TIM5_OC1Init(), TIM5_OC2Init(), and TIM5_OC3Init().

#define IS_TIM5_PRESCALER_OK ( PRESCALER )
Value:
(((PRESCALER) == TIM5_PRESCALER_1) || \
                 ((PRESCALER) == TIM5_PRESCALER_2     ) || \
                 ((PRESCALER) == TIM5_PRESCALER_4     ) || \
                 ((PRESCALER) == TIM5_PRESCALER_8    ) || \
                 ((PRESCALER) == TIM5_PRESCALER_16    ) || \
                 ((PRESCALER) == TIM5_PRESCALER_32      ) || \
                 ((PRESCALER) == TIM5_PRESCALER_64     ) || \
                 ((PRESCALER) == TIM5_PRESCALER_128    ) || \
                 ((PRESCALER) == TIM5_PRESCALER_256    ) || \
                 ((PRESCALER) == TIM5_PRESCALER_512    ) || \
                 ((PRESCALER) == TIM5_PRESCALER_1024   ) || \
                 ((PRESCALER) == TIM5_PRESCALER_2048  ) || \
                 ((PRESCALER) == TIM5_PRESCALER_4096  ) || \
                 ((PRESCALER) == TIM5_PRESCALER_8192  ) || \
                 ((PRESCALER) == TIM5_PRESCALER_16384  ) || \
                 ((PRESCALER) == TIM5_PRESCALER_32768  ))

Definition at line 73 of file stm8s_tim5.h.

Referenced by TIM5_PrescalerConfig().

#define IS_TIM5_PRESCALER_RELOAD_OK ( RELOAD )
Value:
(((RELOAD) == TIM5_PSCRELOADMODE_UPDATE) || \
                                          ((RELOAD) == TIM5_PSCRELOADMODE_IMMEDIATE))

Definition at line 229 of file stm8s_tim5.h.

Referenced by TIM5_PrescalerConfig().

#define IS_TIM5_PWMI_CHANNEL_OK ( CHANNEL )
Value:
(((CHANNEL) == TIM5_CHANNEL_1) || \
                                          ((CHANNEL) == TIM5_CHANNEL_2))

Definition at line 139 of file stm8s_tim5.h.

Referenced by TIM5_PWMIConfig().

#define IS_TIM5_SLAVE_MODE_OK ( MODE )
Value:
(((MODE) == TIM5_SLAVEMODE_RESET)   || \
    ((MODE) == TIM5_SLAVEMODE_GATED)   || \
    ((MODE) == TIM5_SLAVEMODE_TRIGGER) || \
    ((MODE) == TIM5_SLAVEMODE_EXTERNAL1))

Macro TIM5 Slave mode.

Definition at line 318 of file stm8s_tim5.h.

Referenced by TIM5_SelectSlaveMode().

#define IS_TIM5_TIX_TRIGGER_SELECTION_OK ( SELECTION )
Value:
(((SELECTION) == TIM5_TS_TI1F_ED) || \
    ((SELECTION) == TIM5_TS_TI1FP1)  || \
    ((SELECTION) == TIM5_TS_TI2FP2))

Definition at line 341 of file stm8s_tim5.h.

#define IS_TIM5_TRGO_SOURCE_OK ( SOURCE )
Value:
(((SOURCE) == TIM5_TRGOSOURCE_RESET)  || \
    ((SOURCE) == TIM5_TRGOSOURCE_ENABLE) || \
    ((SOURCE) == TIM5_TRGOSOURCE_UPDATE) || \
    ((SOURCE) == TIM5_TRGOSOURCE_OC1)    || \
    ((SOURCE) == TIM5_TRGOSOURCE_OC1REF) || \
    ((SOURCE) == TIM5_TRGOSOURCE_OC2REF))

Macro TIM5 TRGO source.

Definition at line 271 of file stm8s_tim5.h.

Referenced by TIM5_SelectOutputTrigger().

#define IS_TIM5_TRIGGER_SELECTION_OK ( SELECTION )
Value:
(((SELECTION) == TIM5_TS_TIM6)  || \
    ((SELECTION) == TIM5_TS_TIM1)  )

Macro TIM5 Trigger Selection.

Definition at line 336 of file stm8s_tim5.h.

Referenced by TIM5_SelectInputTrigger().

#define IS_TIM5_UPDATE_SOURCE_OK ( SOURCE )
Value:
(((SOURCE) == TIM5_UPDATESOURCE_GLOBAL) || \
                                       ((SOURCE) == TIM5_UPDATESOURCE_REGULAR))

Definition at line 252 of file stm8s_tim5.h.

Referenced by TIM5_UpdateRequestConfig().

#define LSI_VALUE ((uint32_t)128000)

Typical Value of the LSI in Hz

Definition at line 119 of file stm8s.h.

Referenced by CLK_GetClockFreq().

#define MemoryAddressCast uint32_t

Definition at line 161 of file stm8s.h.

Referenced by FLASH_EraseByte(), FLASH_ProgramByte(), FLASH_ProgramWord(), and FLASH_ReadByte().

#define NEAR __near

Definition at line 143 of file stm8s.h.

Referenced by FLASH_EraseOptionByte(), FLASH_ProgramOptionByte(), and FLASH_ReadOptionByte().

#define OPERATION_TIMEOUT ((uint16_t)0xFFFF)

Definition at line 71 of file stm8s_flash.c.

#define PointerAttr FAR

< Used with memory Models for code higher than 64K

Definition at line 160 of file stm8s.h.

Referenced by FLASH_EraseByte(), FLASH_ProgramByte(), FLASH_ProgramWord(), and FLASH_ReadByte().

#define TINY __tiny

Definition at line 144 of file stm8s.h.

#define USE_STDPERIPH_DRIVER

< STM8S High density devices with CAN

< STM8S High density devices without CAN

< STM8S Value Line High density devices

< STM8A High density devices with CAN

< STM8A High density devices without CAN

< STM8S Medium density devices

< STM8S Value Line Medium density devices

< STM8A Medium density devices

< STM8A Low density devices

< STM8S Low density devices

< STM8S Value Line Low density devices

< STM8S Low density devices

< STM8S Value Line Low denisty devices

Definition at line 96 of file stm8s.h.

Enumeration Type Documentation

enum TIM2_Channel_TypeDef

TIM2 Channel.

Enumerator:
TIM2_CHANNEL_1
TIM2_CHANNEL_2
TIM2_CHANNEL_3

Definition at line 128 of file stm8s_tim2.h.

enum TIM2_EventSource_TypeDef

TIM2 Event Source.

Enumerator:
TIM2_EVENTSOURCE_UPDATE
TIM2_EVENTSOURCE_CC1
TIM2_EVENTSOURCE_CC2
TIM2_EVENTSOURCE_CC3

Definition at line 231 of file stm8s_tim2.h.

enum TIM2_FLAG_TypeDef

TIM2 Flags.

Enumerator:
TIM2_FLAG_UPDATE
TIM2_FLAG_CC1
TIM2_FLAG_CC2
TIM2_FLAG_CC3
TIM2_FLAG_CC1OF
TIM2_FLAG_CC2OF
TIM2_FLAG_CC3OF

Definition at line 252 of file stm8s_tim2.h.

enum TIM2_ForcedAction_TypeDef

TIM2 Forced Action.

Enumerator:
TIM2_FORCEDACTION_ACTIVE
TIM2_FORCEDACTION_INACTIVE

Definition at line 43 of file stm8s_tim2.h.

enum TIM2_ICPolarity_TypeDef

TIM2 Input Capture Polarity.

Enumerator:
TIM2_ICPOLARITY_RISING
TIM2_ICPOLARITY_FALLING

Definition at line 163 of file stm8s_tim2.h.

enum TIM2_ICPSC_TypeDef

TIM2 Input Capture Prescaler.

Enumerator:
TIM2_ICPSC_DIV1
TIM2_ICPSC_DIV2
TIM2_ICPSC_DIV4
TIM2_ICPSC_DIV8

Definition at line 188 of file stm8s_tim2.h.

enum TIM2_ICSelection_TypeDef

TIM2 Input Capture Selection.

Enumerator:
TIM2_ICSELECTION_DIRECTTI
TIM2_ICSELECTION_INDIRECTTI
TIM2_ICSELECTION_TRGI

Definition at line 173 of file stm8s_tim2.h.

enum TIM2_IT_TypeDef

TIM2 interrupt sources.

Enumerator:
TIM2_IT_UPDATE
TIM2_IT_CC1
TIM2_IT_CC2
TIM2_IT_CC3

Definition at line 205 of file stm8s_tim2.h.

enum TIM2_OCMode_TypeDef

TIM2 Output Compare and PWM modes.

Enumerator:
TIM2_OCMODE_TIMING
TIM2_OCMODE_ACTIVE
TIM2_OCMODE_INACTIVE
TIM2_OCMODE_TOGGLE
TIM2_OCMODE_PWM1
TIM2_OCMODE_PWM2

Definition at line 91 of file stm8s_tim2.h.

enum TIM2_OCPolarity_TypeDef

TIM2 Output Compare Polarity.

Enumerator:
TIM2_OCPOLARITY_HIGH
TIM2_OCPOLARITY_LOW

Definition at line 143 of file stm8s_tim2.h.

enum TIM2_OPMode_TypeDef

TIM2 One Pulse Mode.

Enumerator:
TIM2_OPMODE_SINGLE
TIM2_OPMODE_REPETITIVE

Definition at line 118 of file stm8s_tim2.h.

enum TIM2_OutputState_TypeDef

TIM2 Output Compare states.

Enumerator:
TIM2_OUTPUTSTATE_DISABLE
TIM2_OUTPUTSTATE_ENABLE

Definition at line 153 of file stm8s_tim2.h.

enum TIM2_Prescaler_TypeDef

TIM2 Prescaler.

Enumerator:
TIM2_PRESCALER_1
TIM2_PRESCALER_2
TIM2_PRESCALER_4
TIM2_PRESCALER_8
TIM2_PRESCALER_16
TIM2_PRESCALER_32
TIM2_PRESCALER_64
TIM2_PRESCALER_128
TIM2_PRESCALER_256
TIM2_PRESCALER_512
TIM2_PRESCALER_1024
TIM2_PRESCALER_2048
TIM2_PRESCALER_4096
TIM2_PRESCALER_8192
TIM2_PRESCALER_16384
TIM2_PRESCALER_32768

Definition at line 53 of file stm8s_tim2.h.

enum TIM2_PSCReloadMode_TypeDef

TIM2 Prescaler Reload Mode.

Enumerator:
TIM2_PSCRELOADMODE_UPDATE
TIM2_PSCRELOADMODE_IMMEDIATE

Definition at line 221 of file stm8s_tim2.h.

enum TIM2_UpdateSource_TypeDef

TIM2 Update Source.

Enumerator:
TIM2_UPDATESOURCE_GLOBAL
TIM2_UPDATESOURCE_REGULAR

Definition at line 242 of file stm8s_tim2.h.

enum TIM5_Channel_TypeDef

TIM5 Channel.

Enumerator:
TIM5_CHANNEL_1
TIM5_CHANNEL_2
TIM5_CHANNEL_3

Definition at line 128 of file stm8s_tim5.h.

enum TIM5_EncoderMode_TypeDef

TIM5 Encoder Mode.

Enumerator:
TIM5_ENCODERMODE_TI1

Encoder mode 1

TIM5_ENCODERMODE_TI2

Encoder mode 2

TIM5_ENCODERMODE_TI12

Encoder mode 3

Definition at line 350 of file stm8s_tim5.h.

enum TIM5_EventSource_TypeDef

TIM5 Event Source.

Enumerator:
TIM5_EVENTSOURCE_UPDATE
TIM5_EVENTSOURCE_CC1
TIM5_EVENTSOURCE_CC2
TIM5_EVENTSOURCE_CC3
TIM5_EVENTSOURCE_TRIGGER

Definition at line 233 of file stm8s_tim5.h.

enum TIM5_ExtTRGPolarity_TypeDef

TIM5 External Trigger Polarity.

Enumerator:
TIM5_EXTTRGPOLARITY_INVERTED

External Trigger Polarity = inverted

TIM5_EXTTRGPOLARITY_NONINVERTED

External Trigger Polarity = non inverted

Definition at line 387 of file stm8s_tim5.h.

enum TIM5_ExtTRGPSC_TypeDef

TIM5 External Trigger Prescaler.

Enumerator:
TIM5_EXTTRGPSC_OFF

No External Trigger prescaler

TIM5_EXTTRGPSC_DIV2

External Trigger prescaler = 2 (ETRP frequency divided by 2)

TIM5_EXTTRGPSC_DIV4

External Trigger prescaler = 4 (ETRP frequency divided by 4)

TIM5_EXTTRGPSC_DIV8

External Trigger prescaler = 8 (ETRP frequency divided by 8)

Definition at line 367 of file stm8s_tim5.h.

enum TIM5_FLAG_TypeDef

TIM5 Flags.

Enumerator:
TIM5_FLAG_UPDATE
TIM5_FLAG_CC1
TIM5_FLAG_CC2
TIM5_FLAG_CC3
TIM5_FLAG_TRIGGER
TIM5_FLAG_CC1OF
TIM5_FLAG_CC2OF
TIM5_FLAG_CC3OF

Definition at line 280 of file stm8s_tim5.h.

enum TIM5_ForcedAction_TypeDef

TIM5 Forced Action.

Enumerator:
TIM5_FORCEDACTION_ACTIVE
TIM5_FORCEDACTION_INACTIVE

Definition at line 43 of file stm8s_tim5.h.

enum TIM5_ICPolarity_TypeDef

TIM5 Input Capture Polarity.

Enumerator:
TIM5_ICPOLARITY_RISING
TIM5_ICPOLARITY_FALLING

Definition at line 163 of file stm8s_tim5.h.

enum TIM5_ICPSC_TypeDef

TIM5 Input Capture Prescaler.

Enumerator:
TIM5_ICPSC_DIV1
TIM5_ICPSC_DIV2
TIM5_ICPSC_DIV4
TIM5_ICPSC_DIV8

Definition at line 188 of file stm8s_tim5.h.

enum TIM5_ICSelection_TypeDef

TIM5 Input Capture Selection.

Enumerator:
TIM5_ICSELECTION_DIRECTTI
TIM5_ICSELECTION_INDIRECTTI
TIM5_ICSELECTION_TRGI

Definition at line 173 of file stm8s_tim5.h.

enum TIM5_IT_TypeDef

TIM5 interrupt sources.

Enumerator:
TIM5_IT_UPDATE
TIM5_IT_CC1
TIM5_IT_CC2
TIM5_IT_CC3
TIM5_IT_TRIGGER

Definition at line 205 of file stm8s_tim5.h.

enum TIM5_OCMode_TypeDef

TIM5 Output Compare and PWM modes.

Enumerator:
TIM5_OCMODE_TIMING
TIM5_OCMODE_ACTIVE
TIM5_OCMODE_INACTIVE
TIM5_OCMODE_TOGGLE
TIM5_OCMODE_PWM1
TIM5_OCMODE_PWM2

Definition at line 91 of file stm8s_tim5.h.

enum TIM5_OCPolarity_TypeDef

TIM5 Output Compare Polarity.

Enumerator:
TIM5_OCPOLARITY_HIGH
TIM5_OCPOLARITY_LOW

Definition at line 143 of file stm8s_tim5.h.

enum TIM5_OPMode_TypeDef

TIM5 One Pulse Mode.

Enumerator:
TIM5_OPMODE_SINGLE
TIM5_OPMODE_REPETITIVE

Definition at line 118 of file stm8s_tim5.h.

enum TIM5_OutputState_TypeDef

TIM5 Output Compare states.

Enumerator:
TIM5_OUTPUTSTATE_DISABLE
TIM5_OUTPUTSTATE_ENABLE

Definition at line 153 of file stm8s_tim5.h.

enum TIM5_Prescaler_TypeDef

TIM5 Prescaler.

Enumerator:
TIM5_PRESCALER_1
TIM5_PRESCALER_2
TIM5_PRESCALER_4
TIM5_PRESCALER_8
TIM5_PRESCALER_16
TIM5_PRESCALER_32
TIM5_PRESCALER_64
TIM5_PRESCALER_128
TIM5_PRESCALER_256
TIM5_PRESCALER_512
TIM5_PRESCALER_1024
TIM5_PRESCALER_2048
TIM5_PRESCALER_4096
TIM5_PRESCALER_8192
TIM5_PRESCALER_16384
TIM5_PRESCALER_32768

Definition at line 53 of file stm8s_tim5.h.

enum TIM5_PSCReloadMode_TypeDef

TIM5 Prescaler Reload Mode.

Enumerator:
TIM5_PSCRELOADMODE_UPDATE
TIM5_PSCRELOADMODE_IMMEDIATE

Definition at line 223 of file stm8s_tim5.h.

enum TIM5_SlaveMode_TypeDef

TIM5 Slave Mode.

Enumerator:
TIM5_SLAVEMODE_RESET

Slave Mode Selection = Reset

TIM5_SLAVEMODE_GATED

Slave Mode Selection = Gated

TIM5_SLAVEMODE_TRIGGER

Slave Mode Selection = Trigger

TIM5_SLAVEMODE_EXTERNAL1

Slave Mode Selection = External 1

Definition at line 307 of file stm8s_tim5.h.

enum TIM5_TRGOSource_TypeDef

TIM5 Trigger Output Source.

Enumerator:
TIM5_TRGOSOURCE_RESET

Trigger Output source = Reset

TIM5_TRGOSOURCE_ENABLE

Trigger Output source = TIM5 is enabled

TIM5_TRGOSOURCE_UPDATE

Trigger Output source = Update event

TIM5_TRGOSOURCE_OC1

Trigger Output source = output compare channel1

TIM5_TRGOSOURCE_OC1REF

Trigger Output source = output compare channel 1 reference

TIM5_TRGOSOURCE_OC2REF

Trigger Output source = output compare channel 2 reference

Definition at line 258 of file stm8s_tim5.h.

enum TIM5_TS_TypeDef

TIM5 Internal Trigger Selection.

Enumerator:
TIM5_TS_TIM6

TRIG Input source = TIM6 TRIG Output

TIM5_TS_TIM1

TRIG Input source = TIM1 TRIG Output

Definition at line 327 of file stm8s_tim5.h.

enum TIM5_UpdateSource_TypeDef

TIM5 Update Source.

Enumerator:
TIM5_UPDATESOURCE_GLOBAL
TIM5_UPDATESOURCE_REGULAR

Definition at line 245 of file stm8s_tim5.h.

Variable Documentation

__IO uint8_t _Data[8] = {0}

Definition at line 46 of file stm8s_can.c.

Referenced by CAN_GetReceivedData(), and CAN_Receive().

__IO uint8_t _DLC = 0

Definition at line 45 of file stm8s_can.c.

Referenced by CAN_GetReceivedDLC(), and CAN_Receive().

__IO uint8_t _FMI = 0

Definition at line 47 of file stm8s_can.c.

Referenced by CAN_GetReceivedFMI(), and CAN_Receive().

__IO uint32_t _Id = 0

Definition at line 42 of file stm8s_can.c.

Referenced by CAN_GetReceivedId(), and CAN_Receive().

__IO uint8_t _IDE = 0

Definition at line 43 of file stm8s_can.c.

Referenced by CAN_GetReceivedIDE(), and CAN_Receive().

__IO uint8_t _RTR = 0

Definition at line 44 of file stm8s_can.c.

Referenced by CAN_GetReceivedRTR(), and CAN_Receive().

CONST uint8_t APR_Array[17]
Initial value:
    {
        0, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 61, 23, 23, 62
    }

Contains the different values to write in the APR register (used by AWU_Init function)

Definition at line 49 of file stm8s_awu.c.

Referenced by AWU_Init().

CONST uint8_t TBR_Array[17]
Initial value:
    {
        0,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 12, 14, 15, 15
    }

Contains the different values to write in the TBR register (used by AWU_Init function)

Definition at line 55 of file stm8s_awu.c.

Referenced by AWU_Init().


STM8S/A Standard Peripherals Drivers: AWU_Registers_Reset_Value

Defines
AWU_Registers_Reset_Value

Defines

#define | AWU_APR_RESET_VALUE ((uint8_t)0x3F)
#define | AWU_CSR_RESET_VALUE ((uint8_t)0x00)
#define | AWU_TBR_RESET_VALUE ((uint8_t)0x00)

Define Documentation

#define AWU_APR_RESET_VALUE ((uint8_t)0x3F)

Definition at line 452 of file stm8s.h.

Referenced by AWU_DeInit().

#define AWU_CSR_RESET_VALUE ((uint8_t)0x00)

Definition at line 451 of file stm8s.h.

Referenced by AWU_DeInit().

#define AWU_TBR_RESET_VALUE ((uint8_t)0x00)

Definition at line 453 of file stm8s.h.

Referenced by AWU_DeInit().


STM8S/A Standard Peripherals Drivers: AWU_Registers_Bits_Definition

Defines
AWU_Registers_Bits_Definition

Defines

#define | AWU_APR_APR ((uint8_t)0x3F)
#define | AWU_CSR_AWUEN ((uint8_t)0x10)
#define | AWU_CSR_AWUF ((uint8_t)0x20)
#define | AWU_CSR_MSR ((uint8_t)0x01)
#define | AWU_TBR_AWUTB ((uint8_t)0x0F)

Define Documentation

#define AWU_APR_APR ((uint8_t)0x3F)

Asynchronous Prescaler divider mask

Definition at line 467 of file stm8s.h.

Referenced by AWU_Init().

#define AWU_CSR_AWUEN ((uint8_t)0x10)

Auto Wake-up enable mask

Definition at line 464 of file stm8s.h.

Referenced by AWU_Cmd(), AWU_IdleModeEnable(), and AWU_Init().

#define AWU_CSR_AWUF ((uint8_t)0x20)

Interrupt flag mask

Definition at line 463 of file stm8s.h.

Referenced by AWU_GetFlagStatus().

#define AWU_CSR_MSR ((uint8_t)0x01)

LSI Measurement enable mask

Definition at line 465 of file stm8s.h.

#define AWU_TBR_AWUTB ((uint8_t)0x0F)

Timebase selection mask

Definition at line 469 of file stm8s.h.

Referenced by AWU_IdleModeEnable(), and AWU_Init().


STM8S/A Standard Peripherals Drivers: BEEP_Registers_Reset_Value

Defines
BEEP_Registers_Reset_Value

Defines

#define BEEP_CSR_RESET_VALUE ((uint8_t)0x1F)

Define Documentation

#define BEEP_CSR_RESET_VALUE ((uint8_t)0x1F)

Definition at line 489 of file stm8s.h.

Referenced by BEEP_DeInit().


STM8S/A Standard Peripherals Drivers: BEEP_Registers_Bits_Definition

Defines
BEEP_Registers_Bits_Definition

Defines

#define | BEEP_CSR_BEEPDIV ((uint8_t)0x1F)
#define | BEEP_CSR_BEEPEN ((uint8_t)0x20)
#define | BEEP_CSR_BEEPSEL ((uint8_t)0xC0)

Define Documentation

#define BEEP_CSR_BEEPDIV ((uint8_t)0x1F)

Beeper Divider prescalar mask

Definition at line 499 of file stm8s.h.

Referenced by BEEP_Init(), and BEEP_LSICalibrationConfig().

#define BEEP_CSR_BEEPEN ((uint8_t)0x20)

Beeper enable mask

Definition at line 498 of file stm8s.h.

Referenced by BEEP_Cmd().

#define BEEP_CSR_BEEPSEL ((uint8_t)0xC0)

Beeper frequency selection mask

Definition at line 497 of file stm8s.h.

Referenced by BEEP_Init().


STM8S/A Standard Peripherals Drivers: CLK_Registers_Reset_Value

Defines
CLK_Registers_Reset_Value

Defines

#define | CLK_CCOR_RESET_VALUE ((uint8_t)0x00)
#define | CLK_CKDIVR_RESET_VALUE ((uint8_t)0x18)
#define | CLK_CMSR_RESET_VALUE ((uint8_t)0xE1)
#define | CLK_CSSR_RESET_VALUE ((uint8_t)0x00)
#define | CLK_ECKR_RESET_VALUE ((uint8_t)0x00)
#define | CLK_HSITRIMR_RESET_VALUE ((uint8_t)0x00)
#define | CLK_ICKR_RESET_VALUE ((uint8_t)0x01)
#define | CLK_PCKENR1_RESET_VALUE ((uint8_t)0xFF)
#define | CLK_PCKENR2_RESET_VALUE ((uint8_t)0xFF)
#define | CLK_SWCR_RESET_VALUE ((uint8_t)0x00)
#define | CLK_SWIMCCR_RESET_VALUE ((uint8_t)0x00)
#define | CLK_SWR_RESET_VALUE ((uint8_t)0xE1)

Define Documentation

#define CLK_CCOR_RESET_VALUE ((uint8_t)0x00)

Definition at line 540 of file stm8s.h.

Referenced by CLK_DeInit().

#define CLK_CKDIVR_RESET_VALUE ((uint8_t)0x18)

Definition at line 536 of file stm8s.h.

Referenced by CLK_DeInit().

#define CLK_CMSR_RESET_VALUE ((uint8_t)0xE1)

Definition at line 533 of file stm8s.h.

#define CLK_CSSR_RESET_VALUE ((uint8_t)0x00)

Definition at line 539 of file stm8s.h.

Referenced by CLK_DeInit().

#define CLK_ECKR_RESET_VALUE ((uint8_t)0x00)

Definition at line 532 of file stm8s.h.

Referenced by CLK_DeInit().

#define CLK_HSITRIMR_RESET_VALUE ((uint8_t)0x00)

Definition at line 541 of file stm8s.h.

Referenced by CLK_DeInit().

#define CLK_ICKR_RESET_VALUE ((uint8_t)0x01)

Definition at line 531 of file stm8s.h.

Referenced by CLK_DeInit().

#define CLK_PCKENR1_RESET_VALUE ((uint8_t)0xFF)

Definition at line 537 of file stm8s.h.

Referenced by CLK_DeInit().

#define CLK_PCKENR2_RESET_VALUE ((uint8_t)0xFF)

Definition at line 538 of file stm8s.h.

Referenced by CLK_DeInit().

#define CLK_SWCR_RESET_VALUE ((uint8_t)0x00)

Definition at line 535 of file stm8s.h.

Referenced by CLK_DeInit().

#define CLK_SWIMCCR_RESET_VALUE ((uint8_t)0x00)

Definition at line 542 of file stm8s.h.

Referenced by CLK_DeInit().

#define CLK_SWR_RESET_VALUE ((uint8_t)0xE1)

Definition at line 534 of file stm8s.h.

Referenced by CLK_DeInit().


STM8S/A Standard Peripherals Drivers: CLK_Registers_Bits_Definition

Defines
CLK_Registers_Bits_Definition

Defines

#define | CLK_CCOR_CCOBSY ((uint8_t)0x40)
#define | CLK_CCOR_CCOEN ((uint8_t)0x01)
#define | CLK_CCOR_CCORDY ((uint8_t)0x20)
#define | CLK_CCOR_CCOSEL ((uint8_t)0x1E)
#define | CLK_CKDIVR_CPUDIV ((uint8_t)0x07)
#define | CLK_CKDIVR_HSIDIV ((uint8_t)0x18)
#define | CLK_CMSR_CKM ((uint8_t)0xFF)
#define | CLK_CSSR_AUX ((uint8_t)0x02)
#define | CLK_CSSR_CSSD ((uint8_t)0x08)
#define | CLK_CSSR_CSSDIE ((uint8_t)0x04)
#define | CLK_CSSR_CSSEN ((uint8_t)0x01)
#define | CLK_ECKR_HSEEN ((uint8_t)0x01)
#define | CLK_ECKR_HSERDY ((uint8_t)0x02)
#define | CLK_HSITRIMR_HSITRIM ((uint8_t)0x07)
#define | CLK_ICKR_FHWU ((uint8_t)0x04)
#define | CLK_ICKR_HSIEN ((uint8_t)0x01)
#define | CLK_ICKR_HSIRDY ((uint8_t)0x02)
#define | CLK_ICKR_LSIEN ((uint8_t)0x08)
#define | CLK_ICKR_LSIRDY ((uint8_t)0x10)
#define | CLK_ICKR_SWUAH ((uint8_t)0x20)
#define | CLK_PCKENR1_I2C ((uint8_t)0x01)
#define | CLK_PCKENR1_SPI ((uint8_t)0x02)
#define | CLK_PCKENR1_TIM1 ((uint8_t)0x80)
#define | CLK_PCKENR1_TIM2 ((uint8_t)0x20)
#define | CLK_PCKENR1_TIM3 ((uint8_t)0x40)
#define | CLK_PCKENR1_TIM4 ((uint8_t)0x10)
#define | CLK_PCKENR1_TIM5 ((uint8_t)0x20)
#define | CLK_PCKENR1_TIM6 ((uint8_t)0x10)
#define | CLK_PCKENR1_UART1 ((uint8_t)0x04)
#define | CLK_PCKENR1_UART2 ((uint8_t)0x08)
#define | CLK_PCKENR1_UART3 ((uint8_t)0x08)
#define | CLK_PCKENR2_ADC ((uint8_t)0x08)
#define | CLK_PCKENR2_AWU ((uint8_t)0x04)
#define | CLK_PCKENR2_CAN ((uint8_t)0x80)
#define | CLK_SWCR_SWBSY ((uint8_t)0x01)
#define | CLK_SWCR_SWEN ((uint8_t)0x02)
#define | CLK_SWCR_SWIEN ((uint8_t)0x04)
#define | CLK_SWCR_SWIF ((uint8_t)0x08)
#define | CLK_SWIMCCR_SWIMDIV ((uint8_t)0x01)
#define | CLK_SWR_SWI ((uint8_t)0xFF)

Define Documentation

#define CLK_CCOR_CCOBSY ((uint8_t)0x40)

Configurable clock output busy

Definition at line 594 of file stm8s.h.

#define CLK_CCOR_CCOEN ((uint8_t)0x01)

Configurable clock output enable

Definition at line 597 of file stm8s.h.

Referenced by CLK_CCOCmd(), CLK_CCOConfig(), and CLK_DeInit().

#define CLK_CCOR_CCORDY ((uint8_t)0x20)

Configurable clock output ready

Definition at line 595 of file stm8s.h.

#define CLK_CCOR_CCOSEL ((uint8_t)0x1E)

Configurable clock output selection

Definition at line 596 of file stm8s.h.

Referenced by CLK_CCOConfig().

#define CLK_CKDIVR_CPUDIV ((uint8_t)0x07)

CPU clock prescaler

Definition at line 571 of file stm8s.h.

Referenced by CLK_SYSCLKConfig().

#define CLK_CKDIVR_HSIDIV ((uint8_t)0x18)

High speed internal clock prescaler

Definition at line 570 of file stm8s.h.

Referenced by CLK_GetClockFreq(), CLK_HSIPrescalerConfig(), and CLK_SYSCLKConfig().

#define CLK_CMSR_CKM ((uint8_t)0xFF)

Clock master status bits

Definition at line 561 of file stm8s.h.

#define CLK_CSSR_AUX ((uint8_t)0x02)

Auxiliary oscillator connected to master clock

Definition at line 591 of file stm8s.h.

#define CLK_CSSR_CSSD ((uint8_t)0x08)

Clock security system detection

Definition at line 589 of file stm8s.h.

Referenced by CLK_ClearITPendingBit().

#define CLK_CSSR_CSSDIE ((uint8_t)0x04)

Clock security system detection interrupt enable

Definition at line 590 of file stm8s.h.

Referenced by CLK_ITConfig().

#define CLK_CSSR_CSSEN ((uint8_t)0x01)

Clock security system enable

Definition at line 592 of file stm8s.h.

Referenced by CLK_ClockSecuritySystemEnable().

#define CLK_ECKR_HSEEN ((uint8_t)0x01)

High speed external crystal oscillator enable

Definition at line 559 of file stm8s.h.

Referenced by CLK_ClockSwitchConfig(), and CLK_HSECmd().

#define CLK_ECKR_HSERDY ((uint8_t)0x02)

High speed external crystal oscillator ready

Definition at line 558 of file stm8s.h.

#define CLK_HSITRIMR_HSITRIM ((uint8_t)0x07)

High speed internal oscillator trimmer

Definition at line 599 of file stm8s.h.

Referenced by CLK_AdjustHSICalibrationValue().

#define CLK_ICKR_FHWU ((uint8_t)0x04)

Fast Wake-up from Active Halt/Halt mode

Definition at line 554 of file stm8s.h.

Referenced by CLK_FastHaltWakeUpCmd().

#define CLK_ICKR_HSIEN ((uint8_t)0x01)

High speed internal RC oscillator enable

Definition at line 556 of file stm8s.h.

Referenced by CLK_ClockSwitchConfig(), and CLK_HSICmd().

#define CLK_ICKR_HSIRDY ((uint8_t)0x02)

High speed internal RC oscillator ready

Definition at line 555 of file stm8s.h.

#define CLK_ICKR_LSIEN ((uint8_t)0x08)

Low speed internal RC oscillator enable

Definition at line 553 of file stm8s.h.

Referenced by CLK_ClockSwitchConfig(), and CLK_LSICmd().

#define CLK_ICKR_LSIRDY ((uint8_t)0x10)

Low speed internal oscillator ready

Definition at line 552 of file stm8s.h.

#define CLK_ICKR_SWUAH ((uint8_t)0x20)

Slow Wake-up from Active Halt/Halt modes

Definition at line 551 of file stm8s.h.

Referenced by CLK_SlowActiveHaltWakeUpCmd().

#define CLK_PCKENR1_I2C ((uint8_t)0x01)

I2C clock enable

Definition at line 583 of file stm8s.h.

#define CLK_PCKENR1_SPI ((uint8_t)0x02)

SPI clock enable

Definition at line 582 of file stm8s.h.

#define CLK_PCKENR1_TIM1 ((uint8_t)0x80)

Timer 1 clock enable

Definition at line 573 of file stm8s.h.

#define CLK_PCKENR1_TIM2 ((uint8_t)0x20)

Timer 2 clock enable

Definition at line 575 of file stm8s.h.

#define CLK_PCKENR1_TIM3 ((uint8_t)0x40)

Timer 3 clock enable

Definition at line 574 of file stm8s.h.

#define CLK_PCKENR1_TIM4 ((uint8_t)0x10)

Timer 4 clock enable

Definition at line 577 of file stm8s.h.

#define CLK_PCKENR1_TIM5 ((uint8_t)0x20)

Timer 5 clock enable

Definition at line 576 of file stm8s.h.

#define CLK_PCKENR1_TIM6 ((uint8_t)0x10)

Timer 6 clock enable

Definition at line 578 of file stm8s.h.

#define CLK_PCKENR1_UART1 ((uint8_t)0x04)

UART1 clock enable

Definition at line 581 of file stm8s.h.

#define CLK_PCKENR1_UART2 ((uint8_t)0x08)

UART2 clock enable

Definition at line 580 of file stm8s.h.

#define CLK_PCKENR1_UART3 ((uint8_t)0x08)

UART3 clock enable

Definition at line 579 of file stm8s.h.

#define CLK_PCKENR2_ADC ((uint8_t)0x08)

ADC clock enable

Definition at line 586 of file stm8s.h.

#define CLK_PCKENR2_AWU ((uint8_t)0x04)

AWU clock enable

Definition at line 587 of file stm8s.h.

#define CLK_PCKENR2_CAN ((uint8_t)0x80)

CAN clock enable

Definition at line 585 of file stm8s.h.

#define CLK_SWCR_SWBSY ((uint8_t)0x01)

Switch busy flag

Definition at line 568 of file stm8s.h.

Referenced by CLK_ClockSwitchConfig(), and CLK_SYSCLKEmergencyClear().

#define CLK_SWCR_SWEN ((uint8_t)0x02)

Switch start/stop

Definition at line 567 of file stm8s.h.

Referenced by CLK_ClockSwitchCmd(), and CLK_ClockSwitchConfig().

#define CLK_SWCR_SWIEN ((uint8_t)0x04)

Clock switch interrupt enable

Definition at line 566 of file stm8s.h.

Referenced by CLK_ClockSwitchConfig(), and CLK_ITConfig().

#define CLK_SWCR_SWIF ((uint8_t)0x08)

Clock switch interrupt flag

Definition at line 565 of file stm8s.h.

Referenced by CLK_ClearITPendingBit(), and CLK_ClockSwitchConfig().

#define CLK_SWIMCCR_SWIMDIV ((uint8_t)0x01)

SWIM Clock Dividing Factor

Definition at line 601 of file stm8s.h.

Referenced by CLK_SWIMConfig().

#define CLK_SWR_SWI ((uint8_t)0xFF)

Clock master selection bits

Definition at line 563 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: TIM1_Registers_Reset_Value

Defines
TIM1_Registers_Reset_Value

Defines

#define | TIM1_ARRH_RESET_VALUE ((uint8_t)0xFF)
#define | TIM1_ARRL_RESET_VALUE ((uint8_t)0xFF)
#define | TIM1_BKR_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCER1_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCER2_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCMR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCMR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCMR3_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCMR4_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCR1H_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCR1L_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCR2H_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCR2L_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCR3H_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCR3L_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCR4H_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCR4L_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CNTRH_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CNTRL_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_DTR_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_EGR_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_ETR_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_IER_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_OISR_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_PSCRH_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_PSCRL_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_RCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_SMCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_SR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_SR2_RESET_VALUE ((uint8_t)0x00)

Define Documentation

#define TIM1_ARRH_RESET_VALUE ((uint8_t)0xFF)

Definition at line 671 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_ARRL_RESET_VALUE ((uint8_t)0xFF)

Definition at line 672 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_BKR_RESET_VALUE ((uint8_t)0x00)

Definition at line 682 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CCER1_RESET_VALUE ((uint8_t)0x00)

Definition at line 665 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CCER2_RESET_VALUE ((uint8_t)0x00)

Definition at line 666 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CCMR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 661 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CCMR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 662 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CCMR3_RESET_VALUE ((uint8_t)0x00)

Definition at line 663 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CCMR4_RESET_VALUE ((uint8_t)0x00)

Definition at line 664 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CCR1H_RESET_VALUE ((uint8_t)0x00)

Definition at line 674 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CCR1L_RESET_VALUE ((uint8_t)0x00)

Definition at line 675 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CCR2H_RESET_VALUE ((uint8_t)0x00)

Definition at line 676 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CCR2L_RESET_VALUE ((uint8_t)0x00)

Definition at line 677 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CCR3H_RESET_VALUE ((uint8_t)0x00)

Definition at line 678 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CCR3L_RESET_VALUE ((uint8_t)0x00)

Definition at line 679 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CCR4H_RESET_VALUE ((uint8_t)0x00)

Definition at line 680 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CCR4L_RESET_VALUE ((uint8_t)0x00)

Definition at line 681 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CNTRH_RESET_VALUE ((uint8_t)0x00)

Definition at line 667 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CNTRL_RESET_VALUE ((uint8_t)0x00)

Definition at line 668 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 653 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 654 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_DTR_RESET_VALUE ((uint8_t)0x00)

Definition at line 683 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_EGR_RESET_VALUE ((uint8_t)0x00)

Definition at line 660 of file stm8s.h.

#define TIM1_ETR_RESET_VALUE ((uint8_t)0x00)

Definition at line 656 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_IER_RESET_VALUE ((uint8_t)0x00)

Definition at line 657 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_OISR_RESET_VALUE ((uint8_t)0x00)

Definition at line 684 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_PSCRH_RESET_VALUE ((uint8_t)0x00)

Definition at line 669 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_PSCRL_RESET_VALUE ((uint8_t)0x00)

Definition at line 670 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_RCR_RESET_VALUE ((uint8_t)0x00)

Definition at line 673 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_SMCR_RESET_VALUE ((uint8_t)0x00)

Definition at line 655 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_SR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 658 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_SR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 659 of file stm8s.h.

Referenced by TIM1_DeInit().


STM8S/A Standard Peripherals Drivers: TIM1_Registers_Bits_Definition

Defines
TIM1_Registers_Bits_Definition

Defines

#define | CCMR_TIxDirect_Set ((uint8_t)0x01)
#define | TIM1_ARRH_ARR ((uint8_t)0xFF)
#define | TIM1_ARRL_ARR ((uint8_t)0xFF)
#define | TIM1_BKR_AOE ((uint8_t)0x40)
#define | TIM1_BKR_BKE ((uint8_t)0x10)
#define | TIM1_BKR_BKP ((uint8_t)0x20)
#define | TIM1_BKR_LOCK ((uint8_t)0x03)
#define | TIM1_BKR_MOE ((uint8_t)0x80)
#define | TIM1_BKR_OSSI ((uint8_t)0x04)
#define | TIM1_BKR_OSSR ((uint8_t)0x08)
#define | TIM1_CCER1_CC1E ((uint8_t)0x01)
#define | TIM1_CCER1_CC1NE ((uint8_t)0x04)
#define | TIM1_CCER1_CC1NP ((uint8_t)0x08)
#define | TIM1_CCER1_CC1P ((uint8_t)0x02)
#define | TIM1_CCER1_CC2E ((uint8_t)0x10)
#define | TIM1_CCER1_CC2NE ((uint8_t)0x40)
#define | TIM1_CCER1_CC2NP ((uint8_t)0x80)
#define | TIM1_CCER1_CC2P ((uint8_t)0x20)
#define | TIM1_CCER2_CC3E ((uint8_t)0x01)
#define | TIM1_CCER2_CC3NE ((uint8_t)0x04)
#define | TIM1_CCER2_CC3NP ((uint8_t)0x08)
#define | TIM1_CCER2_CC3P ((uint8_t)0x02)
#define | TIM1_CCER2_CC4E ((uint8_t)0x10)
#define | TIM1_CCER2_CC4P ((uint8_t)0x20)
#define | TIM1_CCMR_CCxS ((uint8_t)0x03)
#define | TIM1_CCMR_ICxF ((uint8_t)0xF0)
#define | TIM1_CCMR_ICxPSC ((uint8_t)0x0C)
#define | TIM1_CCMR_OCM ((uint8_t)0x70)
#define | TIM1_CCMR_OCxFE ((uint8_t)0x04)
#define | TIM1_CCMR_OCxPE ((uint8_t)0x08)
#define | TIM1_CCR1H_CCR1 ((uint8_t)0xFF)
#define | TIM1_CCR1L_CCR1 ((uint8_t)0xFF)
#define | TIM1_CCR2H_CCR2 ((uint8_t)0xFF)
#define | TIM1_CCR2L_CCR2 ((uint8_t)0xFF)
#define | TIM1_CCR3H_CCR3 ((uint8_t)0xFF)
#define | TIM1_CCR3L_CCR3 ((uint8_t)0xFF)
#define | TIM1_CCR4H_CCR4 ((uint8_t)0xFF)
#define | TIM1_CCR4L_CCR4 ((uint8_t)0xFF)
#define | TIM1_CNTRH_CNT ((uint8_t)0xFF)
#define | TIM1_CNTRL_CNT ((uint8_t)0xFF)
#define | TIM1_CR1_ARPE ((uint8_t)0x80)
#define | TIM1_CR1_CEN ((uint8_t)0x01)
#define | TIM1_CR1_CMS ((uint8_t)0x60)
#define | TIM1_CR1_DIR ((uint8_t)0x10)
#define | TIM1_CR1_OPM ((uint8_t)0x08)
#define | TIM1_CR1_UDIS ((uint8_t)0x02)
#define | TIM1_CR1_URS ((uint8_t)0x04)
#define | TIM1_CR2_CCPC ((uint8_t)0x01)
#define | TIM1_CR2_COMS ((uint8_t)0x04)
#define | TIM1_CR2_MMS ((uint8_t)0x70)
#define | TIM1_CR2_TI1S ((uint8_t)0x80)
#define | TIM1_DTR_DTG ((uint8_t)0xFF)
#define | TIM1_EGR_BG ((uint8_t)0x80)
#define | TIM1_EGR_CC1G ((uint8_t)0x02)
#define | TIM1_EGR_CC2G ((uint8_t)0x04)
#define | TIM1_EGR_CC3G ((uint8_t)0x08)
#define | TIM1_EGR_CC4G ((uint8_t)0x10)
#define | TIM1_EGR_COMG ((uint8_t)0x20)
#define | TIM1_EGR_TG ((uint8_t)0x40)
#define | TIM1_EGR_UG ((uint8_t)0x01)
#define | TIM1_ETR_ECE ((uint8_t)0x40)
#define | TIM1_ETR_ETF ((uint8_t)0x0F)
#define | TIM1_ETR_ETP ((uint8_t)0x80)
#define | TIM1_ETR_ETPS ((uint8_t)0x30)
#define | TIM1_IER_BIE ((uint8_t)0x80)
#define | TIM1_IER_CC1IE ((uint8_t)0x02)
#define | TIM1_IER_CC2IE ((uint8_t)0x04)
#define | TIM1_IER_CC3IE ((uint8_t)0x08)
#define | TIM1_IER_CC4IE ((uint8_t)0x10)
#define | TIM1_IER_COMIE ((uint8_t)0x20)
#define | TIM1_IER_TIE ((uint8_t)0x40)
#define | TIM1_IER_UIE ((uint8_t)0x01)
#define | TIM1_OISR_OIS1 ((uint8_t)0x01)
#define | TIM1_OISR_OIS1N ((uint8_t)0x02)
#define | TIM1_OISR_OIS2 ((uint8_t)0x04)
#define | TIM1_OISR_OIS2N ((uint8_t)0x08)
#define | TIM1_OISR_OIS3 ((uint8_t)0x10)
#define | TIM1_OISR_OIS3N ((uint8_t)0x20)
#define | TIM1_OISR_OIS4 ((uint8_t)0x40)
#define | TIM1_PSCH_PSC ((uint8_t)0xFF)
#define | TIM1_PSCL_PSC ((uint8_t)0xFF)
#define | TIM1_RCR_REP ((uint8_t)0xFF)
#define | TIM1_SMCR_MSM ((uint8_t)0x80)
#define | TIM1_SMCR_SMS ((uint8_t)0x07)
#define | TIM1_SMCR_TS ((uint8_t)0x70)
#define | TIM1_SR1_BIF ((uint8_t)0x80)
#define | TIM1_SR1_CC1IF ((uint8_t)0x02)
#define | TIM1_SR1_CC2IF ((uint8_t)0x04)
#define | TIM1_SR1_CC3IF ((uint8_t)0x08)
#define | TIM1_SR1_CC4IF ((uint8_t)0x10)
#define | TIM1_SR1_COMIF ((uint8_t)0x20)
#define | TIM1_SR1_TIF ((uint8_t)0x40)
#define | TIM1_SR1_UIF ((uint8_t)0x01)
#define | TIM1_SR2_CC1OF ((uint8_t)0x02)
#define | TIM1_SR2_CC2OF ((uint8_t)0x04)
#define | TIM1_SR2_CC3OF ((uint8_t)0x08)
#define | TIM1_SR2_CC4OF ((uint8_t)0x10)

Define Documentation

#define CCMR_TIxDirect_Set ((uint8_t)0x01)

Definition at line 755 of file stm8s.h.

Referenced by TIM1_EncoderInterfaceConfig().

#define TIM1_ARRH_ARR ((uint8_t)0xFF)

Autoreload Value (MSB) mask.

Definition at line 781 of file stm8s.h.

#define TIM1_ARRL_ARR ((uint8_t)0xFF)

Autoreload Value (LSB) mask.

Definition at line 782 of file stm8s.h.

#define TIM1_BKR_AOE ((uint8_t)0x40)

Automatic Output Enable mask.

Definition at line 799 of file stm8s.h.

#define TIM1_BKR_BKE ((uint8_t)0x10)

Break Enable mask.

Definition at line 801 of file stm8s.h.

#define TIM1_BKR_BKP ((uint8_t)0x20)

Break Polarity mask.

Definition at line 800 of file stm8s.h.

#define TIM1_BKR_LOCK ((uint8_t)0x03)

Lock Configuration mask.

Definition at line 804 of file stm8s.h.

#define TIM1_BKR_MOE ((uint8_t)0x80)

Main Output Enable mask.

Definition at line 798 of file stm8s.h.

Referenced by TIM1_CtrlPWMOutputs().

#define TIM1_BKR_OSSI ((uint8_t)0x04)

Off-State Selection for Idle mode mask.

Definition at line 803 of file stm8s.h.

#define TIM1_BKR_OSSR ((uint8_t)0x08)

Off-State Selection for Run mode mask.

Definition at line 802 of file stm8s.h.

#define TIM1_CCER1_CC1E ((uint8_t)0x01)

Capture/Compare 1 output enable mask.

Definition at line 764 of file stm8s.h.

Referenced by TI1_Config(), TIM1_CCxCmd(), TIM1_OC1Init(), and TIM1_SelectOCxM().

#define TIM1_CCER1_CC1NE ((uint8_t)0x04)

Capture/Compare 1 Complementary output enable mask.

Definition at line 762 of file stm8s.h.

Referenced by TIM1_CCxNCmd(), and TIM1_OC1Init().

#define TIM1_CCER1_CC1NP ((uint8_t)0x08)

Capture/Compare 1 Complementary output Polarity mask.

Definition at line 761 of file stm8s.h.

Referenced by TIM1_OC1Init(), and TIM1_OC1NPolarityConfig().

#define TIM1_CCER1_CC1P ((uint8_t)0x02)

Capture/Compare 1 output Polarity mask.

Definition at line 763 of file stm8s.h.

Referenced by TI1_Config(), TIM1_EncoderInterfaceConfig(), TIM1_OC1Init(), and TIM1_OC1PolarityConfig().

#define TIM1_CCER1_CC2E ((uint8_t)0x10)

Capture/Compare 2 output enable mask.

Definition at line 760 of file stm8s.h.

Referenced by TI2_Config(), TIM1_CCxCmd(), TIM1_OC2Init(), and TIM1_SelectOCxM().

#define TIM1_CCER1_CC2NE ((uint8_t)0x40)

Capture/Compare 2 Complementary output enable mask.

Definition at line 758 of file stm8s.h.

Referenced by TIM1_CCxNCmd(), and TIM1_OC2Init().

#define TIM1_CCER1_CC2NP ((uint8_t)0x80)

Capture/Compare 2 Complementary output Polarity mask.

Definition at line 757 of file stm8s.h.

Referenced by TIM1_OC2Init(), and TIM1_OC2NPolarityConfig().

#define TIM1_CCER1_CC2P ((uint8_t)0x20)

Capture/Compare 2 output Polarity mask.

Definition at line 759 of file stm8s.h.

Referenced by TI2_Config(), TIM1_EncoderInterfaceConfig(), TIM1_OC2Init(), and TIM1_OC2PolarityConfig().

#define TIM1_CCER2_CC3E ((uint8_t)0x01)

Capture/Compare 3 output enable mask.

Definition at line 771 of file stm8s.h.

Referenced by TI3_Config(), TIM1_CCxCmd(), TIM1_OC3Init(), and TIM1_SelectOCxM().

#define TIM1_CCER2_CC3NE ((uint8_t)0x04)

Capture/Compare 3 Complementary output enable mask.

Definition at line 769 of file stm8s.h.

Referenced by TIM1_CCxNCmd(), and TIM1_OC3Init().

#define TIM1_CCER2_CC3NP ((uint8_t)0x08)

Capture/Compare 3 Complementary output Polarity mask.

Definition at line 768 of file stm8s.h.

Referenced by TIM1_OC3Init(), and TIM1_OC3NPolarityConfig().

#define TIM1_CCER2_CC3P ((uint8_t)0x02)

Capture/Compare 3 output Polarity mask.

Definition at line 770 of file stm8s.h.

Referenced by TI3_Config(), TIM1_OC3Init(), and TIM1_OC3PolarityConfig().

#define TIM1_CCER2_CC4E ((uint8_t)0x10)

Capture/Compare 4 output enable mask.

Definition at line 767 of file stm8s.h.

Referenced by TI4_Config(), TIM1_CCxCmd(), TIM1_OC4Init(), and TIM1_SelectOCxM().

#define TIM1_CCER2_CC4P ((uint8_t)0x20)

Capture/Compare 4 output Polarity mask.

Definition at line 766 of file stm8s.h.

Referenced by TI4_Config(), TIM1_OC4Init(), and TIM1_OC4PolarityConfig().

#define TIM1_CCMR_CCxS ((uint8_t)0x03)

Capture/Compare x Selection mask.

Definition at line 753 of file stm8s.h.

Referenced by TI1_Config(), TI2_Config(), TI3_Config(), TI4_Config(), and TIM1_EncoderInterfaceConfig().

#define TIM1_CCMR_ICxF ((uint8_t)0xF0)

Input Capture x Filter mask.

Definition at line 749 of file stm8s.h.

Referenced by TI1_Config(), TI2_Config(), TI3_Config(), and TI4_Config().

#define TIM1_CCMR_ICxPSC ((uint8_t)0x0C)

Input Capture x Prescaler mask.

Definition at line 748 of file stm8s.h.

Referenced by TIM1_SetIC1Prescaler(), TIM1_SetIC2Prescaler(), TIM1_SetIC3Prescaler(), and TIM1_SetIC4Prescaler().

#define TIM1_CCMR_OCM ((uint8_t)0x70)

Output Compare x Mode mask.

Definition at line 750 of file stm8s.h.

Referenced by TIM1_ForcedOC1Config(), TIM1_ForcedOC2Config(), TIM1_ForcedOC3Config(), TIM1_ForcedOC4Config(), TIM1_OC1Init(), TIM1_OC2Init(), TIM1_OC3Init(), TIM1_OC4Init(), and TIM1_SelectOCxM().

#define TIM1_CCMR_OCxFE ((uint8_t)0x04)

Output Compare x Fast Enable mask.

Definition at line 752 of file stm8s.h.

Referenced by TIM1_OC1FastConfig(), TIM1_OC2FastConfig(), TIM1_OC3FastConfig(), and TIM1_OC4FastConfig().

#define TIM1_CCMR_OCxPE ((uint8_t)0x08)

Output Compare x Preload Enable mask.

Definition at line 751 of file stm8s.h.

Referenced by TIM1_OC1PreloadConfig(), TIM1_OC2PreloadConfig(), TIM1_OC3PreloadConfig(), and TIM1_OC4PreloadConfig().

#define TIM1_CCR1H_CCR1 ((uint8_t)0xFF)

Capture/Compare 1 Value (MSB) mask.

Definition at line 786 of file stm8s.h.

#define TIM1_CCR1L_CCR1 ((uint8_t)0xFF)

Capture/Compare 1 Value (LSB) mask.

Definition at line 787 of file stm8s.h.

#define TIM1_CCR2H_CCR2 ((uint8_t)0xFF)

Capture/Compare 2 Value (MSB) mask.

Definition at line 789 of file stm8s.h.

#define TIM1_CCR2L_CCR2 ((uint8_t)0xFF)

Capture/Compare 2 Value (LSB) mask.

Definition at line 790 of file stm8s.h.

#define TIM1_CCR3H_CCR3 ((uint8_t)0xFF)

Capture/Compare 3 Value (MSB) mask.

Definition at line 792 of file stm8s.h.

#define TIM1_CCR3L_CCR3 ((uint8_t)0xFF)

Capture/Compare 3 Value (LSB) mask.

Definition at line 793 of file stm8s.h.

#define TIM1_CCR4H_CCR4 ((uint8_t)0xFF)

Capture/Compare 4 Value (MSB) mask.

Definition at line 795 of file stm8s.h.

#define TIM1_CCR4L_CCR4 ((uint8_t)0xFF)

Capture/Compare 4 Value (LSB) mask.

Definition at line 796 of file stm8s.h.

#define TIM1_CNTRH_CNT ((uint8_t)0xFF)

Counter Value (MSB) mask.

Definition at line 773 of file stm8s.h.

#define TIM1_CNTRL_CNT ((uint8_t)0xFF)

Counter Value (LSB) mask.

Definition at line 775 of file stm8s.h.

#define TIM1_CR1_ARPE ((uint8_t)0x80)

Auto-Reload Preload Enable mask.

Definition at line 694 of file stm8s.h.

Referenced by TIM1_ARRPreloadConfig().

#define TIM1_CR1_CEN ((uint8_t)0x01)

Counter Enable mask.

Definition at line 700 of file stm8s.h.

Referenced by TIM1_Cmd().

#define TIM1_CR1_CMS ((uint8_t)0x60)

Center-aligned Mode Selection mask.

Definition at line 695 of file stm8s.h.

Referenced by TIM1_CounterModeConfig(), and TIM1_TimeBaseInit().

#define TIM1_CR1_DIR ((uint8_t)0x10)

Direction mask.

Definition at line 696 of file stm8s.h.

Referenced by TIM1_CounterModeConfig(), and TIM1_TimeBaseInit().

#define TIM1_CR1_OPM ((uint8_t)0x08)

One Pulse Mode mask.

Definition at line 697 of file stm8s.h.

Referenced by TIM1_SelectOnePulseMode().

#define TIM1_CR1_UDIS ((uint8_t)0x02)

Update DIsable mask.

Definition at line 699 of file stm8s.h.

Referenced by TIM1_UpdateDisableConfig().

#define TIM1_CR1_URS ((uint8_t)0x04)

Update Request Source mask.

Definition at line 698 of file stm8s.h.

Referenced by TIM1_UpdateRequestConfig().

#define TIM1_CR2_CCPC ((uint8_t)0x01)

Capture/Compare Preloaded Control mask.

Definition at line 705 of file stm8s.h.

Referenced by TIM1_CCPreloadControl().

#define TIM1_CR2_COMS ((uint8_t)0x04)

Capture/Compare Control Update Selection mask.

Definition at line 704 of file stm8s.h.

Referenced by TIM1_SelectCOM().

#define TIM1_CR2_MMS ((uint8_t)0x70)

MMS Selection mask.

Definition at line 703 of file stm8s.h.

Referenced by TIM1_SelectOutputTrigger().

#define TIM1_CR2_TI1S ((uint8_t)0x80)

TI1S Selection mask.

Definition at line 702 of file stm8s.h.

Referenced by TIM1_SelectHallSensor().

#define TIM1_DTR_DTG ((uint8_t)0xFF)

Dead-Time Generator set-up mask.

Definition at line 806 of file stm8s.h.

#define TIM1_EGR_BG ((uint8_t)0x80)

Break Generation mask.

Definition at line 739 of file stm8s.h.

#define TIM1_EGR_CC1G ((uint8_t)0x02)

Capture/Compare 1 Generation mask.

Definition at line 745 of file stm8s.h.

#define TIM1_EGR_CC2G ((uint8_t)0x04)

Capture/Compare 2 Generation mask.

Definition at line 744 of file stm8s.h.

#define TIM1_EGR_CC3G ((uint8_t)0x08)

Capture/Compare 3 Generation mask.

Definition at line 743 of file stm8s.h.

#define TIM1_EGR_CC4G ((uint8_t)0x10)

Capture/Compare 4 Generation mask.

Definition at line 742 of file stm8s.h.

#define TIM1_EGR_COMG ((uint8_t)0x20)

Capture/Compare Control Update Generation mask.

Definition at line 741 of file stm8s.h.

#define TIM1_EGR_TG ((uint8_t)0x40)

Trigger Generation mask.

Definition at line 740 of file stm8s.h.

#define TIM1_EGR_UG ((uint8_t)0x01)

Update Generation mask.

Definition at line 746 of file stm8s.h.

#define TIM1_ETR_ECE ((uint8_t)0x40)

External Clock mask.

Definition at line 712 of file stm8s.h.

Referenced by TIM1_ETRClockMode2Config().

#define TIM1_ETR_ETF ((uint8_t)0x0F)

External Trigger Filter mask.

Definition at line 714 of file stm8s.h.

#define TIM1_ETR_ETP ((uint8_t)0x80)

External Trigger Polarity mask.

Definition at line 711 of file stm8s.h.

#define TIM1_ETR_ETPS ((uint8_t)0x30)

External Trigger Prescaler mask.

Definition at line 713 of file stm8s.h.

#define TIM1_IER_BIE ((uint8_t)0x80)

Break Interrupt Enable mask.

Definition at line 716 of file stm8s.h.

#define TIM1_IER_CC1IE ((uint8_t)0x02)

Capture/Compare 1 Interrupt Enable mask.

Definition at line 722 of file stm8s.h.

#define TIM1_IER_CC2IE ((uint8_t)0x04)

Capture/Compare 2 Interrupt Enable mask.

Definition at line 721 of file stm8s.h.

#define TIM1_IER_CC3IE ((uint8_t)0x08)

Capture/Compare 3 Interrupt Enable mask.

Definition at line 720 of file stm8s.h.

#define TIM1_IER_CC4IE ((uint8_t)0x10)

Capture/Compare 4 Interrupt Enable mask.

Definition at line 719 of file stm8s.h.

#define TIM1_IER_COMIE ((uint8_t)0x20)

Commutation Interrupt Enable mask.

Definition at line 718 of file stm8s.h.

#define TIM1_IER_TIE ((uint8_t)0x40)

Trigger Interrupt Enable mask.

Definition at line 717 of file stm8s.h.

#define TIM1_IER_UIE ((uint8_t)0x01)

Update Interrupt Enable mask.

Definition at line 723 of file stm8s.h.

#define TIM1_OISR_OIS1 ((uint8_t)0x01)

Output Idle state 1 (OC1 output) mask.

Definition at line 814 of file stm8s.h.

Referenced by TIM1_OC1Init().

#define TIM1_OISR_OIS1N ((uint8_t)0x02)

Output Idle state 1 (OC1N output) mask.

Definition at line 813 of file stm8s.h.

Referenced by TIM1_OC1Init().

#define TIM1_OISR_OIS2 ((uint8_t)0x04)

Output Idle state 2 (OC2 output) mask.

Definition at line 812 of file stm8s.h.

Referenced by TIM1_OC2Init().

#define TIM1_OISR_OIS2N ((uint8_t)0x08)

Output Idle state 2 (OC2N output) mask.

Definition at line 811 of file stm8s.h.

Referenced by TIM1_OC2Init().

#define TIM1_OISR_OIS3 ((uint8_t)0x10)

Output Idle state 3 (OC3 output) mask.

Definition at line 810 of file stm8s.h.

Referenced by TIM1_OC3Init().

#define TIM1_OISR_OIS3N ((uint8_t)0x20)

Output Idle state 3 (OC3N output) mask.

Definition at line 809 of file stm8s.h.

Referenced by TIM1_OC3Init().

#define TIM1_OISR_OIS4 ((uint8_t)0x40)

Output Idle state 4 (OC4 output) mask.

Definition at line 808 of file stm8s.h.

Referenced by TIM1_OC4Init().

#define TIM1_PSCH_PSC ((uint8_t)0xFF)

Prescaler Value (MSB) mask.

Definition at line 777 of file stm8s.h.

#define TIM1_PSCL_PSC ((uint8_t)0xFF)

Prescaler Value (LSB) mask.

Definition at line 779 of file stm8s.h.

#define TIM1_RCR_REP ((uint8_t)0xFF)

Repetition Counter Value mask.

Definition at line 784 of file stm8s.h.

#define TIM1_SMCR_MSM ((uint8_t)0x80)

Master/Slave Mode mask.

Definition at line 707 of file stm8s.h.

Referenced by TIM1_EncoderInterfaceConfig(), and TIM1_SelectMasterSlaveMode().

#define TIM1_SMCR_SMS ((uint8_t)0x07)

Slave Mode Selection mask.

Definition at line 709 of file stm8s.h.

Referenced by TIM1_ETRClockMode1Config(), TIM1_InternalClockConfig(), and TIM1_SelectSlaveMode().

#define TIM1_SMCR_TS ((uint8_t)0x70)

Trigger Selection mask.

Definition at line 708 of file stm8s.h.

Referenced by TIM1_EncoderInterfaceConfig(), TIM1_ETRClockMode1Config(), and TIM1_SelectInputTrigger().

#define TIM1_SR1_BIF ((uint8_t)0x80)

Break Interrupt Flag mask.

Definition at line 725 of file stm8s.h.

#define TIM1_SR1_CC1IF ((uint8_t)0x02)

Capture/Compare 1 Interrupt Flag mask.

Definition at line 731 of file stm8s.h.

#define TIM1_SR1_CC2IF ((uint8_t)0x04)

Capture/Compare 2 Interrupt Flag mask.

Definition at line 730 of file stm8s.h.

#define TIM1_SR1_CC3IF ((uint8_t)0x08)

Capture/Compare 3 Interrupt Flag mask.

Definition at line 729 of file stm8s.h.

#define TIM1_SR1_CC4IF ((uint8_t)0x10)

Capture/Compare 4 Interrupt Flag mask.

Definition at line 728 of file stm8s.h.

#define TIM1_SR1_COMIF ((uint8_t)0x20)

Commutation Interrupt Flag mask.

Definition at line 727 of file stm8s.h.

#define TIM1_SR1_TIF ((uint8_t)0x40)

Trigger Interrupt Flag mask.

Definition at line 726 of file stm8s.h.

#define TIM1_SR1_UIF ((uint8_t)0x01)

Update Interrupt Flag mask.

Definition at line 732 of file stm8s.h.

#define TIM1_SR2_CC1OF ((uint8_t)0x02)

Capture/Compare 1 Overcapture Flag mask.

Definition at line 737 of file stm8s.h.

#define TIM1_SR2_CC2OF ((uint8_t)0x04)

Capture/Compare 2 Overcapture Flag mask.

Definition at line 736 of file stm8s.h.

#define TIM1_SR2_CC3OF ((uint8_t)0x08)

Capture/Compare 3 Overcapture Flag mask.

Definition at line 735 of file stm8s.h.

#define TIM1_SR2_CC4OF ((uint8_t)0x10)

Capture/Compare 4 Overcapture Flag mask.

Definition at line 734 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: TIM2_Registers_Reset_Value

Defines
TIM2_Registers_Reset_Value

Defines

#define | TIM2_ARRH_RESET_VALUE ((uint8_t)0xFF)
#define | TIM2_ARRL_RESET_VALUE ((uint8_t)0xFF)
#define | TIM2_CCER1_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCER2_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCMR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCMR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCMR3_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCR1H_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCR1L_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCR2H_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCR2L_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCR3H_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCR3L_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CNTRH_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CNTRL_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_EGR_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_IER_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_PSCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_SR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_SR2_RESET_VALUE ((uint8_t)0x00)

Define Documentation

#define TIM2_ARRH_RESET_VALUE ((uint8_t)0xFF)

Definition at line 871 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_ARRL_RESET_VALUE ((uint8_t)0xFF)

Definition at line 872 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_CCER1_RESET_VALUE ((uint8_t)0x00)

Definition at line 866 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_CCER2_RESET_VALUE ((uint8_t)0x00)

Definition at line 867 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_CCMR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 863 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_CCMR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 864 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_CCMR3_RESET_VALUE ((uint8_t)0x00)

Definition at line 865 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_CCR1H_RESET_VALUE ((uint8_t)0x00)

Definition at line 873 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_CCR1L_RESET_VALUE ((uint8_t)0x00)

Definition at line 874 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_CCR2H_RESET_VALUE ((uint8_t)0x00)

Definition at line 875 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_CCR2L_RESET_VALUE ((uint8_t)0x00)

Definition at line 876 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_CCR3H_RESET_VALUE ((uint8_t)0x00)

Definition at line 877 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_CCR3L_RESET_VALUE ((uint8_t)0x00)

Definition at line 878 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_CNTRH_RESET_VALUE ((uint8_t)0x00)

Definition at line 868 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_CNTRL_RESET_VALUE ((uint8_t)0x00)

Definition at line 869 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_CR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 858 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_EGR_RESET_VALUE ((uint8_t)0x00)

Definition at line 862 of file stm8s.h.

#define TIM2_IER_RESET_VALUE ((uint8_t)0x00)

Definition at line 859 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_PSCR_RESET_VALUE ((uint8_t)0x00)

Definition at line 870 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_SR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 860 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_SR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 861 of file stm8s.h.

Referenced by TIM2_DeInit().


STM8S/A Standard Peripherals Drivers: TIM2_Registers_Bits_Definition

Defines
TIM2_Registers_Bits_Definition

Defines

#define | TIM2_ARRH_ARR ((uint8_t)0xFF)
#define | TIM2_ARRL_ARR ((uint8_t)0xFF)
#define | TIM2_CCER1_CC1E ((uint8_t)0x01)
#define | TIM2_CCER1_CC1P ((uint8_t)0x02)
#define | TIM2_CCER1_CC2E ((uint8_t)0x10)
#define | TIM2_CCER1_CC2P ((uint8_t)0x20)
#define | TIM2_CCER2_CC3E ((uint8_t)0x01)
#define | TIM2_CCER2_CC3P ((uint8_t)0x02)
#define | TIM2_CCMR_CCxS ((uint8_t)0x03)
#define | TIM2_CCMR_ICxF ((uint8_t)0xF0)
#define | TIM2_CCMR_ICxPSC ((uint8_t)0x0C)
#define | TIM2_CCMR_OCM ((uint8_t)0x70)
#define | TIM2_CCMR_OCxPE ((uint8_t)0x08)
#define | TIM2_CCR1H_CCR1 ((uint8_t)0xFF)
#define | TIM2_CCR1L_CCR1 ((uint8_t)0xFF)
#define | TIM2_CCR2H_CCR2 ((uint8_t)0xFF)
#define | TIM2_CCR2L_CCR2 ((uint8_t)0xFF)
#define | TIM2_CCR3H_CCR3 ((uint8_t)0xFF)
#define | TIM2_CCR3L_CCR3 ((uint8_t)0xFF)
#define | TIM2_CNTRH_CNT ((uint8_t)0xFF)
#define | TIM2_CNTRL_CNT ((uint8_t)0xFF)
#define | TIM2_CR1_ARPE ((uint8_t)0x80)
#define | TIM2_CR1_CEN ((uint8_t)0x01)
#define | TIM2_CR1_OPM ((uint8_t)0x08)
#define | TIM2_CR1_UDIS ((uint8_t)0x02)
#define | TIM2_CR1_URS ((uint8_t)0x04)
#define | TIM2_EGR_CC1G ((uint8_t)0x02)
#define | TIM2_EGR_CC2G ((uint8_t)0x04)
#define | TIM2_EGR_CC3G ((uint8_t)0x08)
#define | TIM2_EGR_UG ((uint8_t)0x01)
#define | TIM2_IER_CC1IE ((uint8_t)0x02)
#define | TIM2_IER_CC2IE ((uint8_t)0x04)
#define | TIM2_IER_CC3IE ((uint8_t)0x08)
#define | TIM2_IER_UIE ((uint8_t)0x01)
#define | TIM2_PSCR_PSC ((uint8_t)0xFF)
#define | TIM2_SR1_CC1IF ((uint8_t)0x02)
#define | TIM2_SR1_CC2IF ((uint8_t)0x04)
#define | TIM2_SR1_CC3IF ((uint8_t)0x08)
#define | TIM2_SR1_UIF ((uint8_t)0x01)
#define | TIM2_SR2_CC1OF ((uint8_t)0x02)
#define | TIM2_SR2_CC2OF ((uint8_t)0x04)
#define | TIM2_SR2_CC3OF ((uint8_t)0x08)

Define Documentation

#define TIM2_ARRH_ARR ((uint8_t)0xFF)

Autoreload Value (MSB) mask.

Definition at line 932 of file stm8s.h.

#define TIM2_ARRL_ARR ((uint8_t)0xFF)

Autoreload Value (LSB) mask.

Definition at line 933 of file stm8s.h.

#define TIM2_CCER1_CC1E ((uint8_t)0x01)

Capture/Compare 1 output enable mask.

Definition at line 922 of file stm8s.h.

Referenced by TI1_Config(), TIM2_CCxCmd(), TIM2_OC1Init(), and TIM2_SelectOCxM().

#define TIM2_CCER1_CC1P ((uint8_t)0x02)

Capture/Compare 1 output Polarity mask.

Definition at line 921 of file stm8s.h.

Referenced by TI1_Config(), TIM2_OC1Init(), and TIM2_OC1PolarityConfig().

#define TIM2_CCER1_CC2E ((uint8_t)0x10)

Capture/Compare 2 output enable mask.

Definition at line 920 of file stm8s.h.

Referenced by TI2_Config(), TIM2_CCxCmd(), TIM2_OC2Init(), and TIM2_SelectOCxM().

#define TIM2_CCER1_CC2P ((uint8_t)0x20)

Capture/Compare 2 output Polarity mask.

Definition at line 919 of file stm8s.h.

Referenced by TI2_Config(), TIM2_OC2Init(), and TIM2_OC2PolarityConfig().

#define TIM2_CCER2_CC3E ((uint8_t)0x01)

Capture/Compare 3 output enable mask.

Definition at line 925 of file stm8s.h.

Referenced by TI3_Config(), TIM2_CCxCmd(), TIM2_OC3Init(), and TIM2_SelectOCxM().

#define TIM2_CCER2_CC3P ((uint8_t)0x02)

Capture/Compare 3 output Polarity mask.

Definition at line 924 of file stm8s.h.

Referenced by TI3_Config(), TIM2_OC3Init(), and TIM2_OC3PolarityConfig().

#define TIM2_CCMR_CCxS ((uint8_t)0x03)

Capture/Compare x Selection mask.

Definition at line 917 of file stm8s.h.

Referenced by TI1_Config(), TI2_Config(), and TI3_Config().

#define TIM2_CCMR_ICxF ((uint8_t)0xF0)

Input Capture x Filter mask.

Definition at line 914 of file stm8s.h.

Referenced by TI1_Config(), TI2_Config(), and TI3_Config().

#define TIM2_CCMR_ICxPSC ((uint8_t)0x0C)

Input Capture x Prescaler mask.

Definition at line 913 of file stm8s.h.

Referenced by TIM2_SetIC1Prescaler(), TIM2_SetIC2Prescaler(), and TIM2_SetIC3Prescaler().

#define TIM2_CCMR_OCM ((uint8_t)0x70)

Output Compare x Mode mask.

Definition at line 915 of file stm8s.h.

Referenced by TIM2_ForcedOC1Config(), TIM2_ForcedOC2Config(), TIM2_ForcedOC3Config(), TIM2_OC1Init(), TIM2_OC2Init(), TIM2_OC3Init(), and TIM2_SelectOCxM().

#define TIM2_CCMR_OCxPE ((uint8_t)0x08)

Output Compare x Preload Enable mask.

Definition at line 916 of file stm8s.h.

Referenced by TIM2_OC1PreloadConfig(), TIM2_OC2PreloadConfig(), and TIM2_OC3PreloadConfig().

#define TIM2_CCR1H_CCR1 ((uint8_t)0xFF)

Capture/Compare 1 Value (MSB) mask.

Definition at line 935 of file stm8s.h.

#define TIM2_CCR1L_CCR1 ((uint8_t)0xFF)

Capture/Compare 1 Value (LSB) mask.

Definition at line 936 of file stm8s.h.

#define TIM2_CCR2H_CCR2 ((uint8_t)0xFF)

Capture/Compare 2 Value (MSB) mask.

Definition at line 938 of file stm8s.h.

#define TIM2_CCR2L_CCR2 ((uint8_t)0xFF)

Capture/Compare 2 Value (LSB) mask.

Definition at line 939 of file stm8s.h.

#define TIM2_CCR3H_CCR3 ((uint8_t)0xFF)

Capture/Compare 3 Value (MSB) mask.

Definition at line 941 of file stm8s.h.

#define TIM2_CCR3L_CCR3 ((uint8_t)0xFF)

Capture/Compare 3 Value (LSB) mask.

Definition at line 942 of file stm8s.h.

#define TIM2_CNTRH_CNT ((uint8_t)0xFF)

Counter Value (MSB) mask.

Definition at line 927 of file stm8s.h.

#define TIM2_CNTRL_CNT ((uint8_t)0xFF)

Counter Value (LSB) mask.

Definition at line 928 of file stm8s.h.

#define TIM2_CR1_ARPE ((uint8_t)0x80)

Auto-Reload Preload Enable mask.

Definition at line 888 of file stm8s.h.

Referenced by TIM2_ARRPreloadConfig().

#define TIM2_CR1_CEN ((uint8_t)0x01)

Counter Enable mask.

Definition at line 892 of file stm8s.h.

Referenced by TIM2_Cmd().

#define TIM2_CR1_OPM ((uint8_t)0x08)

One Pulse Mode mask.

Definition at line 889 of file stm8s.h.

Referenced by TIM2_SelectOnePulseMode().

#define TIM2_CR1_UDIS ((uint8_t)0x02)

Update DIsable mask.

Definition at line 891 of file stm8s.h.

Referenced by TIM2_UpdateDisableConfig().

#define TIM2_CR1_URS ((uint8_t)0x04)

Update Request Source mask.

Definition at line 890 of file stm8s.h.

Referenced by TIM2_UpdateRequestConfig().

#define TIM2_EGR_CC1G ((uint8_t)0x02)

Capture/Compare 1 Generation mask.

Definition at line 910 of file stm8s.h.

#define TIM2_EGR_CC2G ((uint8_t)0x04)

Capture/Compare 2 Generation mask.

Definition at line 909 of file stm8s.h.

#define TIM2_EGR_CC3G ((uint8_t)0x08)

Capture/Compare 3 Generation mask.

Definition at line 908 of file stm8s.h.

#define TIM2_EGR_UG ((uint8_t)0x01)

Update Generation mask.

Definition at line 911 of file stm8s.h.

#define TIM2_IER_CC1IE ((uint8_t)0x02)

Capture/Compare 1 Interrupt Enable mask.

Definition at line 896 of file stm8s.h.

#define TIM2_IER_CC2IE ((uint8_t)0x04)

Capture/Compare 2 Interrupt Enable mask.

Definition at line 895 of file stm8s.h.

#define TIM2_IER_CC3IE ((uint8_t)0x08)

Capture/Compare 3 Interrupt Enable mask.

Definition at line 894 of file stm8s.h.

#define TIM2_IER_UIE ((uint8_t)0x01)

Update Interrupt Enable mask.

Definition at line 897 of file stm8s.h.

#define TIM2_PSCR_PSC ((uint8_t)0xFF)

Prescaler Value (MSB) mask.

Definition at line 930 of file stm8s.h.

#define TIM2_SR1_CC1IF ((uint8_t)0x02)

Capture/Compare 1 Interrupt Flag mask.

Definition at line 901 of file stm8s.h.

#define TIM2_SR1_CC2IF ((uint8_t)0x04)

Capture/Compare 2 Interrupt Flag mask.

Definition at line 900 of file stm8s.h.

#define TIM2_SR1_CC3IF ((uint8_t)0x08)

Capture/Compare 3 Interrupt Flag mask.

Definition at line 899 of file stm8s.h.

#define TIM2_SR1_UIF ((uint8_t)0x01)

Update Interrupt Flag mask.

Definition at line 902 of file stm8s.h.

#define TIM2_SR2_CC1OF ((uint8_t)0x02)

Capture/Compare 1 Overcapture Flag mask.

Definition at line 906 of file stm8s.h.

#define TIM2_SR2_CC2OF ((uint8_t)0x04)

Capture/Compare 2 Overcapture Flag mask.

Definition at line 905 of file stm8s.h.

#define TIM2_SR2_CC3OF ((uint8_t)0x08)

Capture/Compare 3 Overcapture Flag mask.

Definition at line 904 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: TIM3_Registers_Reset_Value

Defines
TIM3_Registers_Reset_Value

Defines

#define | TIM3_ARRH_RESET_VALUE ((uint8_t)0xFF)
#define | TIM3_ARRL_RESET_VALUE ((uint8_t)0xFF)
#define | TIM3_CCER1_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CCMR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CCMR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CCR1H_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CCR1L_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CCR2H_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CCR2L_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CNTRH_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CNTRL_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_EGR_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_IER_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_PSCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_SR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_SR2_RESET_VALUE ((uint8_t)0x00)

Define Documentation

#define TIM3_ARRH_RESET_VALUE ((uint8_t)0xFF)

Definition at line 989 of file stm8s.h.

Referenced by TIM3_DeInit().

#define TIM3_ARRL_RESET_VALUE ((uint8_t)0xFF)

Definition at line 990 of file stm8s.h.

Referenced by TIM3_DeInit().

#define TIM3_CCER1_RESET_VALUE ((uint8_t)0x00)

Definition at line 985 of file stm8s.h.

Referenced by TIM3_DeInit().

#define TIM3_CCMR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 983 of file stm8s.h.

Referenced by TIM3_DeInit().

#define TIM3_CCMR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 984 of file stm8s.h.

Referenced by TIM3_DeInit().

#define TIM3_CCR1H_RESET_VALUE ((uint8_t)0x00)

Definition at line 991 of file stm8s.h.

Referenced by TIM3_DeInit().

#define TIM3_CCR1L_RESET_VALUE ((uint8_t)0x00)

Definition at line 992 of file stm8s.h.

Referenced by TIM3_DeInit().

#define TIM3_CCR2H_RESET_VALUE ((uint8_t)0x00)

Definition at line 993 of file stm8s.h.

Referenced by TIM3_DeInit().

#define TIM3_CCR2L_RESET_VALUE ((uint8_t)0x00)

Definition at line 994 of file stm8s.h.

Referenced by TIM3_DeInit().

#define TIM3_CNTRH_RESET_VALUE ((uint8_t)0x00)

Definition at line 986 of file stm8s.h.

Referenced by TIM3_DeInit().

#define TIM3_CNTRL_RESET_VALUE ((uint8_t)0x00)

Definition at line 987 of file stm8s.h.

Referenced by TIM3_DeInit().

#define TIM3_CR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 978 of file stm8s.h.

Referenced by TIM3_DeInit().

#define TIM3_EGR_RESET_VALUE ((uint8_t)0x00)

Definition at line 982 of file stm8s.h.

#define TIM3_IER_RESET_VALUE ((uint8_t)0x00)

Definition at line 979 of file stm8s.h.

Referenced by TIM3_DeInit().

#define TIM3_PSCR_RESET_VALUE ((uint8_t)0x00)

Definition at line 988 of file stm8s.h.

Referenced by TIM3_DeInit().

#define TIM3_SR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 980 of file stm8s.h.

Referenced by TIM3_DeInit().

#define TIM3_SR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 981 of file stm8s.h.

Referenced by TIM3_DeInit().


STM8S/A Standard Peripherals Drivers: TIM3_Registers_Bits_Definition

Defines
TIM3_Registers_Bits_Definition

Defines

#define | TIM3_ARRH_ARR ((uint8_t)0xFF)
#define | TIM3_ARRL_ARR ((uint8_t)0xFF)
#define | TIM3_CCER1_CC1E ((uint8_t)0x01)
#define | TIM3_CCER1_CC1P ((uint8_t)0x02)
#define | TIM3_CCER1_CC2E ((uint8_t)0x10)
#define | TIM3_CCER1_CC2P ((uint8_t)0x20)
#define | TIM3_CCMR_CCxS ((uint8_t)0x03)
#define | TIM3_CCMR_ICxF ((uint8_t)0xF0)
#define | TIM3_CCMR_ICxPSC ((uint8_t)0x0C)
#define | TIM3_CCMR_OCM ((uint8_t)0x70)
#define | TIM3_CCMR_OCxPE ((uint8_t)0x08)
#define | TIM3_CCR1H_CCR1 ((uint8_t)0xFF)
#define | TIM3_CCR1L_CCR1 ((uint8_t)0xFF)
#define | TIM3_CCR2H_CCR2 ((uint8_t)0xFF)
#define | TIM3_CCR2L_CCR2 ((uint8_t)0xFF)
#define | TIM3_CNTRH_CNT ((uint8_t)0xFF)
#define | TIM3_CNTRL_CNT ((uint8_t)0xFF)
#define | TIM3_CR1_ARPE ((uint8_t)0x80)
#define | TIM3_CR1_CEN ((uint8_t)0x01)
#define | TIM3_CR1_OPM ((uint8_t)0x08)
#define | TIM3_CR1_UDIS ((uint8_t)0x02)
#define | TIM3_CR1_URS ((uint8_t)0x04)
#define | TIM3_EGR_CC1G ((uint8_t)0x02)
#define | TIM3_EGR_CC2G ((uint8_t)0x04)
#define | TIM3_EGR_UG ((uint8_t)0x01)
#define | TIM3_IER_CC1IE ((uint8_t)0x02)
#define | TIM3_IER_CC2IE ((uint8_t)0x04)
#define | TIM3_IER_UIE ((uint8_t)0x01)
#define | TIM3_PSCR_PSC ((uint8_t)0xFF)
#define | TIM3_SR1_CC1IF ((uint8_t)0x02)
#define | TIM3_SR1_CC2IF ((uint8_t)0x04)
#define | TIM3_SR1_UIF ((uint8_t)0x01)
#define | TIM3_SR2_CC1OF ((uint8_t)0x02)
#define | TIM3_SR2_CC2OF ((uint8_t)0x04)

Define Documentation

#define TIM3_ARRH_ARR ((uint8_t)0xFF)

Autoreload Value (MSB) mask.

Definition at line 1041 of file stm8s.h.

#define TIM3_ARRL_ARR ((uint8_t)0xFF)

Autoreload Value (LSB) mask.

Definition at line 1042 of file stm8s.h.

#define TIM3_CCER1_CC1E ((uint8_t)0x01)

Capture/Compare 1 output enable mask.

Definition at line 1034 of file stm8s.h.

Referenced by TI1_Config(), TIM3_CCxCmd(), TIM3_OC1Init(), and TIM3_SelectOCxM().

#define TIM3_CCER1_CC1P ((uint8_t)0x02)

Capture/Compare 1 output Polarity mask.

Definition at line 1033 of file stm8s.h.

Referenced by TI1_Config(), TIM3_OC1Init(), and TIM3_OC1PolarityConfig().

#define TIM3_CCER1_CC2E ((uint8_t)0x10)

Capture/Compare 2 output enable mask.

Definition at line 1032 of file stm8s.h.

Referenced by TI2_Config(), TIM3_CCxCmd(), TIM3_OC2Init(), and TIM3_SelectOCxM().

#define TIM3_CCER1_CC2P ((uint8_t)0x20)

Capture/Compare 2 output Polarity mask.

Definition at line 1031 of file stm8s.h.

Referenced by TI2_Config(), TIM3_OC2Init(), and TIM3_OC2PolarityConfig().

#define TIM3_CCMR_CCxS ((uint8_t)0x03)

Capture/Compare x Selection mask.

Definition at line 1029 of file stm8s.h.

Referenced by TI1_Config(), and TI2_Config().

#define TIM3_CCMR_ICxF ((uint8_t)0xF0)

Input Capture x Filter mask.

Definition at line 1026 of file stm8s.h.

Referenced by TI1_Config(), and TI2_Config().

#define TIM3_CCMR_ICxPSC ((uint8_t)0x0C)

Input Capture x Prescaler mask.

Definition at line 1025 of file stm8s.h.

Referenced by TIM3_SetIC1Prescaler(), and TIM3_SetIC2Prescaler().

#define TIM3_CCMR_OCM ((uint8_t)0x70)

Output Compare x Mode mask.

Definition at line 1027 of file stm8s.h.

Referenced by TIM3_ForcedOC1Config(), TIM3_ForcedOC2Config(), TIM3_OC1Init(), TIM3_OC2Init(), and TIM3_SelectOCxM().

#define TIM3_CCMR_OCxPE ((uint8_t)0x08)

Output Compare x Preload Enable mask.

Definition at line 1028 of file stm8s.h.

Referenced by TIM3_OC1PreloadConfig(), and TIM3_OC2PreloadConfig().

#define TIM3_CCR1H_CCR1 ((uint8_t)0xFF)

Capture/Compare 1 Value (MSB) mask.

Definition at line 1044 of file stm8s.h.

#define TIM3_CCR1L_CCR1 ((uint8_t)0xFF)

Capture/Compare 1 Value (LSB) mask.

Definition at line 1045 of file stm8s.h.

#define TIM3_CCR2H_CCR2 ((uint8_t)0xFF)

Capture/Compare 2 Value (MSB) mask.

Definition at line 1047 of file stm8s.h.

#define TIM3_CCR2L_CCR2 ((uint8_t)0xFF)

Capture/Compare 2 Value (LSB) mask.

Definition at line 1048 of file stm8s.h.

#define TIM3_CNTRH_CNT ((uint8_t)0xFF)

Counter Value (MSB) mask.

Definition at line 1036 of file stm8s.h.

#define TIM3_CNTRL_CNT ((uint8_t)0xFF)

Counter Value (LSB) mask.

Definition at line 1037 of file stm8s.h.

#define TIM3_CR1_ARPE ((uint8_t)0x80)

Auto-Reload Preload Enable mask.

Definition at line 1004 of file stm8s.h.

Referenced by TIM3_ARRPreloadConfig().

#define TIM3_CR1_CEN ((uint8_t)0x01)

Counter Enable mask.

Definition at line 1008 of file stm8s.h.

Referenced by TIM3_Cmd().

#define TIM3_CR1_OPM ((uint8_t)0x08)

One Pulse Mode mask.

Definition at line 1005 of file stm8s.h.

Referenced by TIM3_SelectOnePulseMode().

#define TIM3_CR1_UDIS ((uint8_t)0x02)

Update DIsable mask.

Definition at line 1007 of file stm8s.h.

Referenced by TIM3_UpdateDisableConfig().

#define TIM3_CR1_URS ((uint8_t)0x04)

Update Request Source mask.

Definition at line 1006 of file stm8s.h.

Referenced by TIM3_UpdateRequestConfig().

#define TIM3_EGR_CC1G ((uint8_t)0x02)

Capture/Compare 1 Generation mask.

Definition at line 1022 of file stm8s.h.

#define TIM3_EGR_CC2G ((uint8_t)0x04)

Capture/Compare 2 Generation mask.

Definition at line 1021 of file stm8s.h.

#define TIM3_EGR_UG ((uint8_t)0x01)

Update Generation mask.

Definition at line 1023 of file stm8s.h.

#define TIM3_IER_CC1IE ((uint8_t)0x02)

Capture/Compare 1 Interrupt Enable mask.

Definition at line 1011 of file stm8s.h.

#define TIM3_IER_CC2IE ((uint8_t)0x04)

Capture/Compare 2 Interrupt Enable mask.

Definition at line 1010 of file stm8s.h.

#define TIM3_IER_UIE ((uint8_t)0x01)

Update Interrupt Enable mask.

Definition at line 1012 of file stm8s.h.

#define TIM3_PSCR_PSC ((uint8_t)0xFF)

Prescaler Value (MSB) mask.

Definition at line 1039 of file stm8s.h.

#define TIM3_SR1_CC1IF ((uint8_t)0x02)

Capture/Compare 1 Interrupt Flag mask.

Definition at line 1015 of file stm8s.h.

#define TIM3_SR1_CC2IF ((uint8_t)0x04)

Capture/Compare 2 Interrupt Flag mask.

Definition at line 1014 of file stm8s.h.

#define TIM3_SR1_UIF ((uint8_t)0x01)

Update Interrupt Flag mask.

Definition at line 1016 of file stm8s.h.

#define TIM3_SR2_CC1OF ((uint8_t)0x02)

Capture/Compare 1 Overcapture Flag mask.

Definition at line 1019 of file stm8s.h.

#define TIM3_SR2_CC2OF ((uint8_t)0x04)

Capture/Compare 2 Overcapture Flag mask.

Definition at line 1018 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: TIM4_Registers_Reset_Value

Defines
TIM4_Registers_Reset_Value

Defines

#define | TIM4_ARR_RESET_VALUE ((uint8_t)0xFF)
#define | TIM4_CNTR_RESET_VALUE ((uint8_t)0x00)
#define | TIM4_CR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM4_EGR_RESET_VALUE ((uint8_t)0x00)
#define | TIM4_IER_RESET_VALUE ((uint8_t)0x00)
#define | TIM4_PSCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM4_SR1_RESET_VALUE ((uint8_t)0x00)

Define Documentation

#define TIM4_ARR_RESET_VALUE ((uint8_t)0xFF)

Definition at line 1084 of file stm8s.h.

Referenced by TIM4_DeInit().

#define TIM4_CNTR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1082 of file stm8s.h.

Referenced by TIM4_DeInit().

#define TIM4_CR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1078 of file stm8s.h.

Referenced by TIM4_DeInit().

#define TIM4_EGR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1081 of file stm8s.h.

#define TIM4_IER_RESET_VALUE ((uint8_t)0x00)

Definition at line 1079 of file stm8s.h.

Referenced by TIM4_DeInit().

#define TIM4_PSCR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1083 of file stm8s.h.

Referenced by TIM4_DeInit().

#define TIM4_SR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1080 of file stm8s.h.

Referenced by TIM4_DeInit().


STM8S/A Standard Peripherals Drivers: TIM4_Registers_Bits_Definition

Defines
TIM4_Registers_Bits_Definition

Defines

#define | TIM4_ARR_ARR ((uint8_t)0xFF)
#define | TIM4_CNTR_CNT ((uint8_t)0xFF)
#define | TIM4_CR1_ARPE ((uint8_t)0x80)
#define | TIM4_CR1_CEN ((uint8_t)0x01)
#define | TIM4_CR1_OPM ((uint8_t)0x08)
#define | TIM4_CR1_UDIS ((uint8_t)0x02)
#define | TIM4_CR1_URS ((uint8_t)0x04)
#define | TIM4_EGR_UG ((uint8_t)0x01)
#define | TIM4_IER_UIE ((uint8_t)0x01)
#define | TIM4_PSCR_PSC ((uint8_t)0x07)
#define | TIM4_SR1_UIF ((uint8_t)0x01)

Define Documentation

#define TIM4_ARR_ARR ((uint8_t)0xFF)

Autoreload Value mask.

Definition at line 1110 of file stm8s.h.

#define TIM4_CNTR_CNT ((uint8_t)0xFF)

Counter Value (LSB) mask.

Definition at line 1106 of file stm8s.h.

#define TIM4_CR1_ARPE ((uint8_t)0x80)

Auto-Reload Preload Enable mask.

Definition at line 1094 of file stm8s.h.

Referenced by TIM4_ARRPreloadConfig().

#define TIM4_CR1_CEN ((uint8_t)0x01)

Counter Enable mask.

Definition at line 1098 of file stm8s.h.

Referenced by TIM4_Cmd().

#define TIM4_CR1_OPM ((uint8_t)0x08)

One Pulse Mode mask.

Definition at line 1095 of file stm8s.h.

Referenced by TIM4_SelectOnePulseMode().

#define TIM4_CR1_UDIS ((uint8_t)0x02)

Update DIsable mask.

Definition at line 1097 of file stm8s.h.

Referenced by TIM4_UpdateDisableConfig().

#define TIM4_CR1_URS ((uint8_t)0x04)

Update Request Source mask.

Definition at line 1096 of file stm8s.h.

Referenced by TIM4_UpdateRequestConfig().

#define TIM4_EGR_UG ((uint8_t)0x01)

Update Generation mask.

Definition at line 1104 of file stm8s.h.

#define TIM4_IER_UIE ((uint8_t)0x01)

Update Interrupt Enable mask.

Definition at line 1100 of file stm8s.h.

#define TIM4_PSCR_PSC ((uint8_t)0x07)

Prescaler Value mask.

Definition at line 1108 of file stm8s.h.

#define TIM4_SR1_UIF ((uint8_t)0x01)

Update Interrupt Flag mask.

Definition at line 1102 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: TIM5_Registers_Reset_Value

Defines
TIM5_Registers_Reset_Value

Defines

#define | TIM5_ARRH_RESET_VALUE ((uint8_t)0xFF)
#define | TIM5_ARRL_RESET_VALUE ((uint8_t)0xFF)
#define | TIM5_CCER1_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCER2_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCMR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCMR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCMR3_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCR1H_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCR1L_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCR2H_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCR2L_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCR3H_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCR3L_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CNTRH_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CNTRL_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_EGR_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_IER_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_PSCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_SMCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_SR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_SR2_RESET_VALUE ((uint8_t)0x00)

Define Documentation

#define TIM5_ARRH_RESET_VALUE ((uint8_t)0xFF)

Definition at line 1167 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_ARRL_RESET_VALUE ((uint8_t)0xFF)

Definition at line 1168 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_CCER1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1162 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_CCER2_RESET_VALUE ((uint8_t)0x00)

Definition at line 1163 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_CCMR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1159 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_CCMR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 1160 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_CCMR3_RESET_VALUE ((uint8_t)0x00)

Definition at line 1161 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_CCR1H_RESET_VALUE ((uint8_t)0x00)

Definition at line 1169 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_CCR1L_RESET_VALUE ((uint8_t)0x00)

Definition at line 1170 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_CCR2H_RESET_VALUE ((uint8_t)0x00)

Definition at line 1171 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_CCR2L_RESET_VALUE ((uint8_t)0x00)

Definition at line 1172 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_CCR3H_RESET_VALUE ((uint8_t)0x00)

Definition at line 1173 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_CCR3L_RESET_VALUE ((uint8_t)0x00)

Definition at line 1174 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_CNTRH_RESET_VALUE ((uint8_t)0x00)

Definition at line 1164 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_CNTRL_RESET_VALUE ((uint8_t)0x00)

Definition at line 1165 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_CR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1152 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_CR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 1153 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_EGR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1158 of file stm8s.h.

#define TIM5_IER_RESET_VALUE ((uint8_t)0x00)

Definition at line 1155 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_PSCR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1166 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_SMCR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1154 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_SR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1156 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_SR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 1157 of file stm8s.h.

Referenced by TIM5_DeInit().


STM8S/A Standard Peripherals Drivers: TIM5_Registers_Bits_Definition

Defines
TIM5_Registers_Bits_Definition

Defines

#define | TIM5_ARRH_ARR ((uint8_t)0xFF)
#define | TIM5_ARRL_ARR ((uint8_t)0xFF)
#define | TIM5_CCER1_CC1E ((uint8_t)0x01)
#define | TIM5_CCER1_CC1P ((uint8_t)0x02)
#define | TIM5_CCER1_CC2E ((uint8_t)0x10)
#define | TIM5_CCER1_CC2P ((uint8_t)0x20)
#define | TIM5_CCER2_CC3E ((uint8_t)0x01)
#define | TIM5_CCER2_CC3P ((uint8_t)0x02)
#define | TIM5_CCMR_CCxS ((uint8_t)0x03)
#define | TIM5_CCMR_ICxF ((uint8_t)0xF0)
#define | TIM5_CCMR_ICxPSC ((uint8_t)0x0C)
#define | TIM5_CCMR_OCM ((uint8_t)0x70)
#define | TIM5_CCMR_OCxPE ((uint8_t)0x08)
#define | TIM5_CCMR_TIxDirect_Set ((uint8_t)0x01)
#define | TIM5_CCR1H_CCR1 ((uint8_t)0xFF)
#define | TIM5_CCR1L_CCR1 ((uint8_t)0xFF)
#define | TIM5_CCR2H_CCR2 ((uint8_t)0xFF)
#define | TIM5_CCR2L_CCR2 ((uint8_t)0xFF)
#define | TIM5_CCR3H_CCR3 ((uint8_t)0xFF)
#define | TIM5_CCR3L_CCR3 ((uint8_t)0xFF)
#define | TIM5_CNTRH_CNT ((uint8_t)0xFF)
#define | TIM5_CNTRL_CNT ((uint8_t)0xFF)
#define | TIM5_CR1_ARPE ((uint8_t)0x80)
#define | TIM5_CR1_CEN ((uint8_t)0x01)
#define | TIM5_CR1_OPM ((uint8_t)0x08)
#define | TIM5_CR1_UDIS ((uint8_t)0x02)
#define | TIM5_CR1_URS ((uint8_t)0x04)
#define | TIM5_CR2_MMS ((uint8_t)0x70)
#define | TIM5_CR2_TI1S ((uint8_t)0x80)
#define | TIM5_EGR_CC1G ((uint8_t)0x02)
#define | TIM5_EGR_CC2G ((uint8_t)0x04)
#define | TIM5_EGR_CC3G ((uint8_t)0x08)
#define | TIM5_EGR_TG ((uint8_t)0x40)
#define | TIM5_EGR_UG ((uint8_t)0x01)
#define | TIM5_IER_CC1IE ((uint8_t)0x02)
#define | TIM5_IER_CC2IE ((uint8_t)0x04)
#define | TIM5_IER_CC3IE ((uint8_t)0x08)
#define | TIM5_IER_TIE ((uint8_t)0x40)
#define | TIM5_IER_UIE ((uint8_t)0x01)
#define | TIM5_PSCR_PSC ((uint8_t)0xFF)
#define | TIM5_SMCR_MSM ((uint8_t)0x80)
#define | TIM5_SMCR_SMS ((uint8_t)0x07)
#define | TIM5_SMCR_TS ((uint8_t)0x70)
#define | TIM5_SR1_CC1IF ((uint8_t)0x02)
#define | TIM5_SR1_CC2IF ((uint8_t)0x04)
#define | TIM5_SR1_CC3IF ((uint8_t)0x08)
#define | TIM5_SR1_TIF ((uint8_t)0x40)
#define | TIM5_SR1_UIF ((uint8_t)0x01)
#define | TIM5_SR2_CC1OF ((uint8_t)0x02)
#define | TIM5_SR2_CC2OF ((uint8_t)0x04)
#define | TIM5_SR2_CC3OF ((uint8_t)0x08)

Define Documentation

#define TIM5_ARRH_ARR ((uint8_t)0xFF)

Autoreload Value (MSB) mask.

Definition at line 1238 of file stm8s.h.

#define TIM5_ARRL_ARR ((uint8_t)0xFF)

Autoreload Value (LSB) mask.

Definition at line 1239 of file stm8s.h.

#define TIM5_CCER1_CC1E ((uint8_t)0x01)

Capture/Compare 1 output enable mask.

Definition at line 1228 of file stm8s.h.

Referenced by TI1_Config(), TIM5_CCxCmd(), TIM5_OC1Init(), and TIM5_SelectOCxM().

#define TIM5_CCER1_CC1P ((uint8_t)0x02)

Capture/Compare 1 output Polarity mask.

Definition at line 1227 of file stm8s.h.

Referenced by TI1_Config(), TIM5_EncoderInterfaceConfig(), TIM5_OC1Init(), and TIM5_OC1PolarityConfig().

#define TIM5_CCER1_CC2E ((uint8_t)0x10)

Capture/Compare 2 output enable mask.

Definition at line 1226 of file stm8s.h.

Referenced by TI2_Config(), TIM5_CCxCmd(), TIM5_OC2Init(), and TIM5_SelectOCxM().

#define TIM5_CCER1_CC2P ((uint8_t)0x20)

Capture/Compare 2 output Polarity mask.

Definition at line 1225 of file stm8s.h.

Referenced by TI2_Config(), TIM5_EncoderInterfaceConfig(), TIM5_OC2Init(), and TIM5_OC2PolarityConfig().

#define TIM5_CCER2_CC3E ((uint8_t)0x01)

Capture/Compare 3 output enable mask.

Definition at line 1231 of file stm8s.h.

Referenced by TI3_Config(), TIM5_CCxCmd(), TIM5_OC3Init(), and TIM5_SelectOCxM().

#define TIM5_CCER2_CC3P ((uint8_t)0x02)

Capture/Compare 3 output Polarity mask.

Definition at line 1230 of file stm8s.h.

Referenced by TI3_Config(), TIM5_OC3Init(), and TIM5_OC3PolarityConfig().

#define TIM5_CCMR_CCxS ((uint8_t)0x03)

Capture/Compare x Selection mask.

Definition at line 1223 of file stm8s.h.

Referenced by TI1_Config(), TI2_Config(), TI3_Config(), and TIM5_EncoderInterfaceConfig().

#define TIM5_CCMR_ICxF ((uint8_t)0xF0)

Input Capture x Filter mask.

Definition at line 1220 of file stm8s.h.

Referenced by TI1_Config(), TI2_Config(), and TI3_Config().

#define TIM5_CCMR_ICxPSC ((uint8_t)0x0C)

Input Capture x Prescaler mask.

Definition at line 1219 of file stm8s.h.

Referenced by TIM5_SetIC1Prescaler(), TIM5_SetIC2Prescaler(), and TIM5_SetIC3Prescaler().

#define TIM5_CCMR_OCM ((uint8_t)0x70)

Output Compare x Mode mask.

Definition at line 1221 of file stm8s.h.

Referenced by TIM5_ForcedOC1Config(), TIM5_ForcedOC2Config(), TIM5_ForcedOC3Config(), TIM5_OC1Init(), TIM5_OC2Init(), TIM5_OC3Init(), and TIM5_SelectOCxM().

#define TIM5_CCMR_OCxPE ((uint8_t)0x08)

Output Compare x Preload Enable mask.

Definition at line 1222 of file stm8s.h.

Referenced by TIM5_OC1PreloadConfig(), TIM5_OC2PreloadConfig(), and TIM5_OC3PreloadConfig().

#define TIM5_CCMR_TIxDirect_Set ((uint8_t)0x01)

Definition at line 1250 of file stm8s.h.

Referenced by TIM5_EncoderInterfaceConfig().

#define TIM5_CCR1H_CCR1 ((uint8_t)0xFF)

Capture/Compare 1 Value (MSB) mask.

Definition at line 1241 of file stm8s.h.

#define TIM5_CCR1L_CCR1 ((uint8_t)0xFF)

Capture/Compare 1 Value (LSB) mask.

Definition at line 1242 of file stm8s.h.

#define TIM5_CCR2H_CCR2 ((uint8_t)0xFF)

Capture/Compare 2 Value (MSB) mask.

Definition at line 1244 of file stm8s.h.

#define TIM5_CCR2L_CCR2 ((uint8_t)0xFF)

Capture/Compare 2 Value (LSB) mask.

Definition at line 1245 of file stm8s.h.

#define TIM5_CCR3H_CCR3 ((uint8_t)0xFF)

Capture/Compare 3 Value (MSB) mask.

Definition at line 1247 of file stm8s.h.

#define TIM5_CCR3L_CCR3 ((uint8_t)0xFF)

Capture/Compare 3 Value (LSB) mask.

Definition at line 1248 of file stm8s.h.

#define TIM5_CNTRH_CNT ((uint8_t)0xFF)

Counter Value (MSB) mask.

Definition at line 1233 of file stm8s.h.

#define TIM5_CNTRL_CNT ((uint8_t)0xFF)

Counter Value (LSB) mask.

Definition at line 1234 of file stm8s.h.

#define TIM5_CR1_ARPE ((uint8_t)0x80)

Auto-Reload Preload Enable mask.

Definition at line 1184 of file stm8s.h.

Referenced by TIM5_ARRPreloadConfig().

#define TIM5_CR1_CEN ((uint8_t)0x01)

Counter Enable mask.

Definition at line 1188 of file stm8s.h.

Referenced by TIM5_Cmd().

#define TIM5_CR1_OPM ((uint8_t)0x08)

One Pulse Mode mask.

Definition at line 1185 of file stm8s.h.

Referenced by TIM5_SelectOnePulseMode().

#define TIM5_CR1_UDIS ((uint8_t)0x02)

Update DIsable mask.

Definition at line 1187 of file stm8s.h.

Referenced by TIM5_UpdateDisableConfig().

#define TIM5_CR1_URS ((uint8_t)0x04)

Update Request Source mask.

Definition at line 1186 of file stm8s.h.

Referenced by TIM5_UpdateRequestConfig().

#define TIM5_CR2_MMS ((uint8_t)0x70)

MMS Selection Mask.

Definition at line 1191 of file stm8s.h.

Referenced by TIM5_SelectOutputTrigger().

#define TIM5_CR2_TI1S ((uint8_t)0x80)

TI1S Selection Mask.

Definition at line 1190 of file stm8s.h.

#define TIM5_EGR_CC1G ((uint8_t)0x02)

Capture/Compare 1 Generation mask.

Definition at line 1216 of file stm8s.h.

#define TIM5_EGR_CC2G ((uint8_t)0x04)

Capture/Compare 2 Generation mask.

Definition at line 1215 of file stm8s.h.

#define TIM5_EGR_CC3G ((uint8_t)0x08)

Capture/Compare 3 Generation mask.

Definition at line 1214 of file stm8s.h.

#define TIM5_EGR_TG ((uint8_t)0x40)

Trigger Generation mask.

Definition at line 1213 of file stm8s.h.

#define TIM5_EGR_UG ((uint8_t)0x01)

Update Generation mask.

Definition at line 1217 of file stm8s.h.

#define TIM5_IER_CC1IE ((uint8_t)0x02)

Capture/Compare 1 Interrupt Enable mask.

Definition at line 1200 of file stm8s.h.

#define TIM5_IER_CC2IE ((uint8_t)0x04)

Capture/Compare 2 Interrupt Enable mask.

Definition at line 1199 of file stm8s.h.

#define TIM5_IER_CC3IE ((uint8_t)0x08)

Capture/Compare 3 Interrupt Enable mask.

Definition at line 1198 of file stm8s.h.

#define TIM5_IER_TIE ((uint8_t)0x40)

Trigger Interrupt Enable mask.

Definition at line 1197 of file stm8s.h.

#define TIM5_IER_UIE ((uint8_t)0x01)

Update Interrupt Enable mask.

Definition at line 1201 of file stm8s.h.

#define TIM5_PSCR_PSC ((uint8_t)0xFF)

Prescaler Value (MSB) mask.

Definition at line 1236 of file stm8s.h.

#define TIM5_SMCR_MSM ((uint8_t)0x80)

Master/Slave Mode Mask.

Definition at line 1193 of file stm8s.h.

Referenced by TIM5_EncoderInterfaceConfig().

#define TIM5_SMCR_SMS ((uint8_t)0x07)

Slave Mode Selection Mask.

Definition at line 1195 of file stm8s.h.

Referenced by TIM5_InternalClockConfig(), and TIM5_SelectSlaveMode().

#define TIM5_SMCR_TS ((uint8_t)0x70)

Trigger Selection Mask.

Definition at line 1194 of file stm8s.h.

Referenced by TIM5_EncoderInterfaceConfig(), and TIM5_SelectInputTrigger().

#define TIM5_SR1_CC1IF ((uint8_t)0x02)

Capture/Compare 1 Interrupt Flag mask.

Definition at line 1206 of file stm8s.h.

#define TIM5_SR1_CC2IF ((uint8_t)0x04)

Capture/Compare 2 Interrupt Flag mask.

Definition at line 1205 of file stm8s.h.

#define TIM5_SR1_CC3IF ((uint8_t)0x08)

Capture/Compare 3 Interrupt Flag mask.

Definition at line 1204 of file stm8s.h.

#define TIM5_SR1_TIF ((uint8_t)0x40)

Trigger Interrupt Flag mask.

Definition at line 1203 of file stm8s.h.

#define TIM5_SR1_UIF ((uint8_t)0x01)

Update Interrupt Flag mask.

Definition at line 1207 of file stm8s.h.

#define TIM5_SR2_CC1OF ((uint8_t)0x02)

Capture/Compare 1 Overcapture Flag mask.

Definition at line 1211 of file stm8s.h.

#define TIM5_SR2_CC2OF ((uint8_t)0x04)

Capture/Compare 2 Overcapture Flag mask.

Definition at line 1210 of file stm8s.h.

#define TIM5_SR2_CC3OF ((uint8_t)0x08)

Capture/Compare 3 Overcapture Flag mask.

Definition at line 1209 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: TIM6_Registers_Reset_Value

Defines
TIM6_Registers_Reset_Value

Defines

#define | TIM6_ARR_RESET_VALUE ((uint8_t)0xFF)
#define | TIM6_CNTR_RESET_VALUE ((uint8_t)0x00)
#define | TIM6_CR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM6_CR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM6_EGR_RESET_VALUE ((uint8_t)0x00)
#define | TIM6_IER_RESET_VALUE ((uint8_t)0x00)
#define | TIM6_PSCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM6_SMCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM6_SR1_RESET_VALUE ((uint8_t)0x00)

Define Documentation

#define TIM6_ARR_RESET_VALUE ((uint8_t)0xFF)

Definition at line 1284 of file stm8s.h.

Referenced by TIM6_DeInit().

#define TIM6_CNTR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1282 of file stm8s.h.

Referenced by TIM6_DeInit().

#define TIM6_CR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1276 of file stm8s.h.

Referenced by TIM6_DeInit().

#define TIM6_CR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 1277 of file stm8s.h.

Referenced by TIM6_DeInit().

#define TIM6_EGR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1281 of file stm8s.h.

#define TIM6_IER_RESET_VALUE ((uint8_t)0x00)

Definition at line 1279 of file stm8s.h.

Referenced by TIM6_DeInit().

#define TIM6_PSCR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1283 of file stm8s.h.

Referenced by TIM6_DeInit().

#define TIM6_SMCR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1278 of file stm8s.h.

Referenced by TIM6_DeInit().

#define TIM6_SR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1280 of file stm8s.h.

Referenced by TIM6_DeInit().


STM8S/A Standard Peripherals Drivers: TIM6_Registers_Bits_Definition

Defines
TIM6_Registers_Bits_Definition

Defines

#define | TIM6_ARR_ARR ((uint8_t)0xFF)
#define | TIM6_CNTR_CNT ((uint8_t)0xFF)
#define | TIM6_CR1_ARPE ((uint8_t)0x80)
#define | TIM6_CR1_CEN ((uint8_t)0x01)
#define | TIM6_CR1_OPM ((uint8_t)0x08)
#define | TIM6_CR1_UDIS ((uint8_t)0x02)
#define | TIM6_CR1_URS ((uint8_t)0x04)
#define | TIM6_CR2_MMS ((uint8_t)0x70)
#define | TIM6_EGR_TG ((uint8_t)0x40)
#define | TIM6_EGR_UG ((uint8_t)0x01)
#define | TIM6_IER_TIE ((uint8_t)0x40)
#define | TIM6_IER_UIE ((uint8_t)0x01)
#define | TIM6_PSCR_PSC ((uint8_t)0x07)
#define | TIM6_SMCR_MSM ((uint8_t)0x80)
#define | TIM6_SMCR_SMS ((uint8_t)0x07)
#define | TIM6_SMCR_TS ((uint8_t)0x70)
#define | TIM6_SR1_TIF ((uint8_t)0x40)
#define | TIM6_SR1_UIF ((uint8_t)0x01)

Define Documentation

#define TIM6_ARR_ARR ((uint8_t)0xFF)

Autoreload Value Mask.

Definition at line 1319 of file stm8s.h.

#define TIM6_CNTR_CNT ((uint8_t)0xFF)

Counter Value (LSB) Mask.

Definition at line 1315 of file stm8s.h.

#define TIM6_CR1_ARPE ((uint8_t)0x80)

Auto-Reload Preload Enable Mask.

Definition at line 1294 of file stm8s.h.

Referenced by TIM6_ARRPreloadConfig().

#define TIM6_CR1_CEN ((uint8_t)0x01)

Counter Enable Mask.

Definition at line 1298 of file stm8s.h.

Referenced by TIM6_Cmd().

#define TIM6_CR1_OPM ((uint8_t)0x08)

One Pulse Mode Mask.

Definition at line 1295 of file stm8s.h.

Referenced by TIM6_SelectOnePulseMode().

#define TIM6_CR1_UDIS ((uint8_t)0x02)

Update DIsable Mask.

Definition at line 1297 of file stm8s.h.

Referenced by TIM6_UpdateDisableConfig().

#define TIM6_CR1_URS ((uint8_t)0x04)

Update Request Source Mask.

Definition at line 1296 of file stm8s.h.

Referenced by TIM6_UpdateRequestConfig().

#define TIM6_CR2_MMS ((uint8_t)0x70)

MMS Selection Mask.

Definition at line 1300 of file stm8s.h.

Referenced by TIM6_SelectOutputTrigger().

#define TIM6_EGR_TG ((uint8_t)0x40)

Trigger Generation mask.

Definition at line 1312 of file stm8s.h.

#define TIM6_EGR_UG ((uint8_t)0x01)

Update Generation Mask.

Definition at line 1313 of file stm8s.h.

Referenced by TIM6_PrescalerConfig().

#define TIM6_IER_TIE ((uint8_t)0x40)

Trigger Interrupt Enable Mask.

Definition at line 1306 of file stm8s.h.

#define TIM6_IER_UIE ((uint8_t)0x01)

Update Interrupt Enable Mask.

Definition at line 1307 of file stm8s.h.

#define TIM6_PSCR_PSC ((uint8_t)0x07)

Prescaler Value Mask.

Definition at line 1317 of file stm8s.h.

#define TIM6_SMCR_MSM ((uint8_t)0x80)

Master/Slave Mode Mask.

Definition at line 1302 of file stm8s.h.

Referenced by TIM6_SelectMasterSlaveMode().

#define TIM6_SMCR_SMS ((uint8_t)0x07)

Slave Mode Selection Mask.

Definition at line 1304 of file stm8s.h.

Referenced by TIM6_InternalClockConfig(), and TIM6_SelectSlaveMode().

#define TIM6_SMCR_TS ((uint8_t)0x70)

Trigger Selection Mask.

Definition at line 1303 of file stm8s.h.

Referenced by TIM6_SelectInputTrigger().

#define TIM6_SR1_TIF ((uint8_t)0x40)

Trigger Interrupt Flag mask.

Definition at line 1309 of file stm8s.h.

#define TIM6_SR1_UIF ((uint8_t)0x01)

Update Interrupt Flag Mask.

Definition at line 1310 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: I2C_Registers_Reset_Value

Defines
I2C_Registers_Reset_Value

Defines

#define | I2C_CCRH_RESET_VALUE ((uint8_t)0x00)
#define | I2C_CCRL_RESET_VALUE ((uint8_t)0x00)
#define | I2C_CR1_RESET_VALUE ((uint8_t)0x00)
#define | I2C_CR2_RESET_VALUE ((uint8_t)0x00)
#define | I2C_DR_RESET_VALUE ((uint8_t)0x00)
#define | I2C_FREQR_RESET_VALUE ((uint8_t)0x00)
#define | I2C_ITR_RESET_VALUE ((uint8_t)0x00)
#define | I2C_OARH_RESET_VALUE ((uint8_t)0x00)
#define | I2C_OARL_RESET_VALUE ((uint8_t)0x00)
#define | I2C_SR1_RESET_VALUE ((uint8_t)0x00)
#define | I2C_SR2_RESET_VALUE ((uint8_t)0x00)
#define | I2C_SR3_RESET_VALUE ((uint8_t)0x00)
#define | I2C_TRISER_RESET_VALUE ((uint8_t)0x02)

Define Documentation

#define I2C_CCRH_RESET_VALUE ((uint8_t)0x00)

Definition at line 1363 of file stm8s.h.

Referenced by I2C_DeInit().

#define I2C_CCRL_RESET_VALUE ((uint8_t)0x00)

Definition at line 1362 of file stm8s.h.

Referenced by I2C_DeInit().

#define I2C_CR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1352 of file stm8s.h.

Referenced by I2C_DeInit().

#define I2C_CR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 1353 of file stm8s.h.

Referenced by I2C_DeInit().

#define I2C_DR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1357 of file stm8s.h.

#define I2C_FREQR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1354 of file stm8s.h.

Referenced by I2C_DeInit().

#define I2C_ITR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1361 of file stm8s.h.

Referenced by I2C_DeInit().

#define I2C_OARH_RESET_VALUE ((uint8_t)0x00)

Definition at line 1356 of file stm8s.h.

Referenced by I2C_DeInit().

#define I2C_OARL_RESET_VALUE ((uint8_t)0x00)

Definition at line 1355 of file stm8s.h.

Referenced by I2C_DeInit().

#define I2C_SR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1358 of file stm8s.h.

#define I2C_SR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 1359 of file stm8s.h.

#define I2C_SR3_RESET_VALUE ((uint8_t)0x00)

Definition at line 1360 of file stm8s.h.

#define I2C_TRISER_RESET_VALUE ((uint8_t)0x02)

Definition at line 1364 of file stm8s.h.

Referenced by I2C_DeInit().


STM8S/A Standard Peripherals Drivers: I2C_Registers_Bits_Definition

Defines
I2C_Registers_Bits_Definition

Defines

#define | I2C_CCRH_CCR ((uint8_t)0x0F)
#define | I2C_CCRH_DUTY ((uint8_t)0x40)
#define | I2C_CCRH_FS ((uint8_t)0x80)
#define | I2C_CCRL_CCR ((uint8_t)0xFF)
#define | I2C_CR1_ENGC ((uint8_t)0x40)
#define | I2C_CR1_NOSTRETCH ((uint8_t)0x80)
#define | I2C_CR1_PE ((uint8_t)0x01)
#define | I2C_CR2_ACK ((uint8_t)0x04)
#define | I2C_CR2_POS ((uint8_t)0x08)
#define | I2C_CR2_START ((uint8_t)0x01)
#define | I2C_CR2_STOP ((uint8_t)0x02)
#define | I2C_CR2_SWRST ((uint8_t)0x80)
#define | I2C_DR_DR ((uint8_t)0xFF)
#define | I2C_FREQR_FREQ ((uint8_t)0x3F)
#define | I2C_ITR_ITBUFEN ((uint8_t)0x04)
#define | I2C_ITR_ITERREN ((uint8_t)0x01)
#define | I2C_ITR_ITEVTEN ((uint8_t)0x02)
#define | I2C_OARH_ADD ((uint8_t)0x06)
#define | I2C_OARH_ADDCONF ((uint8_t)0x40)
#define | I2C_OARH_ADDMODE ((uint8_t)0x80)
#define | I2C_OARL_ADD ((uint8_t)0xFE)
#define | I2C_OARL_ADD0 ((uint8_t)0x01)
#define | I2C_SR1_ADD10 ((uint8_t)0x08)
#define | I2C_SR1_ADDR ((uint8_t)0x02)
#define | I2C_SR1_BTF ((uint8_t)0x04)
#define | I2C_SR1_RXNE ((uint8_t)0x40)
#define | I2C_SR1_SB ((uint8_t)0x01)
#define | I2C_SR1_STOPF ((uint8_t)0x10)
#define | I2C_SR1_TXE ((uint8_t)0x80)
#define | I2C_SR2_AF ((uint8_t)0x04)
#define | I2C_SR2_ARLO ((uint8_t)0x02)
#define | I2C_SR2_BERR ((uint8_t)0x01)
#define | I2C_SR2_OVR ((uint8_t)0x08)
#define | I2C_SR2_WUFH ((uint8_t)0x20)
#define | I2C_SR3_BUSY ((uint8_t)0x02)
#define | I2C_SR3_GENCALL ((uint8_t)0x10)
#define | I2C_SR3_MSL ((uint8_t)0x01)
#define | I2C_SR3_TRA ((uint8_t)0x04)
#define | I2C_TRISER_TRISE ((uint8_t)0x3F)

Define Documentation

#define I2C_CCRH_CCR ((uint8_t)0x0F)

Clock Control Register in Fast/Standard mode (Master mode) bits [11..8]

Definition at line 1422 of file stm8s.h.

Referenced by I2C_Init().

#define I2C_CCRH_DUTY ((uint8_t)0x40)

Fast Mode Duty Cycle

Definition at line 1421 of file stm8s.h.

Referenced by I2C_FastModeDutyCycleConfig(), and I2C_Init().

#define I2C_CCRH_FS ((uint8_t)0x80)

Master Mode Selection

Definition at line 1420 of file stm8s.h.

Referenced by I2C_Init().

#define I2C_CCRL_CCR ((uint8_t)0xFF)

Clock Control Register (Master mode)

Definition at line 1418 of file stm8s.h.

Referenced by I2C_Init().

#define I2C_CR1_ENGC ((uint8_t)0x40)

General Call Enable

Definition at line 1375 of file stm8s.h.

Referenced by I2C_GeneralCallCmd().

#define I2C_CR1_NOSTRETCH ((uint8_t)0x80)

Clock Stretching Disable (Slave mode)

Definition at line 1374 of file stm8s.h.

Referenced by I2C_StretchClockCmd().

#define I2C_CR1_PE ((uint8_t)0x01)

Peripheral Enable

Definition at line 1376 of file stm8s.h.

Referenced by I2C_Cmd(), and I2C_Init().

#define I2C_CR2_ACK ((uint8_t)0x04)

Acknowledge Enable

Definition at line 1380 of file stm8s.h.

Referenced by I2C_AcknowledgeConfig().

#define I2C_CR2_POS ((uint8_t)0x08)

Acknowledge

Definition at line 1379 of file stm8s.h.

Referenced by I2C_AcknowledgeConfig().

#define I2C_CR2_START ((uint8_t)0x01)

Start Generation

Definition at line 1382 of file stm8s.h.

Referenced by I2C_GenerateSTART().

#define I2C_CR2_STOP ((uint8_t)0x02)

Stop Generation

Definition at line 1381 of file stm8s.h.

Referenced by I2C_GenerateSTOP().

#define I2C_CR2_SWRST ((uint8_t)0x80)

Software Reset

Definition at line 1378 of file stm8s.h.

Referenced by I2C_SoftwareResetCmd().

#define I2C_DR_DR ((uint8_t)0xFF)

Data Register

Definition at line 1393 of file stm8s.h.

#define I2C_FREQR_FREQ ((uint8_t)0x3F)

Peripheral Clock Frequency

Definition at line 1384 of file stm8s.h.

Referenced by I2C_Init().

#define I2C_ITR_ITBUFEN ((uint8_t)0x04)

Buffer Interrupt Enable

Definition at line 1414 of file stm8s.h.

#define I2C_ITR_ITERREN ((uint8_t)0x01)

Error Interrupt Enable

Definition at line 1416 of file stm8s.h.

#define I2C_ITR_ITEVTEN ((uint8_t)0x02)

Event Interrupt Enable

Definition at line 1415 of file stm8s.h.

#define I2C_OARH_ADD ((uint8_t)0x06)

Interface Address bits [9..8]

Definition at line 1391 of file stm8s.h.

#define I2C_OARH_ADDCONF ((uint8_t)0x40)

Address Mode Configuration

Definition at line 1390 of file stm8s.h.

Referenced by I2C_Init().

#define I2C_OARH_ADDMODE ((uint8_t)0x80)

Addressing Mode (Slave mode)

Definition at line 1389 of file stm8s.h.

#define I2C_OARL_ADD ((uint8_t)0xFE)

Interface Address bits [7..1]

Definition at line 1386 of file stm8s.h.

#define I2C_OARL_ADD0 ((uint8_t)0x01)

Interface Address bit0

Definition at line 1387 of file stm8s.h.

#define I2C_SR1_ADD10 ((uint8_t)0x08)

10-bit header sent (Master mode)

Definition at line 1398 of file stm8s.h.

#define I2C_SR1_ADDR ((uint8_t)0x02)

Address sent (master mode)/matched (slave mode)

Definition at line 1400 of file stm8s.h.

#define I2C_SR1_BTF ((uint8_t)0x04)

Byte Transfer Finished

Definition at line 1399 of file stm8s.h.

#define I2C_SR1_RXNE ((uint8_t)0x40)

Data Register not Empty (receivers)

Definition at line 1396 of file stm8s.h.

#define I2C_SR1_SB ((uint8_t)0x01)

Start Bit (Master mode)

Definition at line 1401 of file stm8s.h.

#define I2C_SR1_STOPF ((uint8_t)0x10)

Stop detection (Slave mode)

Definition at line 1397 of file stm8s.h.

#define I2C_SR1_TXE ((uint8_t)0x80)

Data Register Empty (transmitters)

Definition at line 1395 of file stm8s.h.

#define I2C_SR2_AF ((uint8_t)0x04)

Acknowledge Failure

Definition at line 1405 of file stm8s.h.

Referenced by I2C_CheckEvent(), and I2C_GetLastEvent().

#define I2C_SR2_ARLO ((uint8_t)0x02)

Arbitration Lost (master mode)

Definition at line 1406 of file stm8s.h.

#define I2C_SR2_BERR ((uint8_t)0x01)

Bus Error

Definition at line 1407 of file stm8s.h.

#define I2C_SR2_OVR ((uint8_t)0x08)

Overrun/Underrun

Definition at line 1404 of file stm8s.h.

#define I2C_SR2_WUFH ((uint8_t)0x20)

Wake-up from Halt

Definition at line 1403 of file stm8s.h.

#define I2C_SR3_BUSY ((uint8_t)0x02)

Bus Busy

Definition at line 1411 of file stm8s.h.

#define I2C_SR3_GENCALL ((uint8_t)0x10)

General Call Header (Slave mode)

Definition at line 1409 of file stm8s.h.

#define I2C_SR3_MSL ((uint8_t)0x01)

Master/Slave

Definition at line 1412 of file stm8s.h.

#define I2C_SR3_TRA ((uint8_t)0x04)

Transmitter/Receiver

Definition at line 1410 of file stm8s.h.

#define I2C_TRISER_TRISE ((uint8_t)0x3F)

Maximum Rise Time in Fast/Standard mode (Master mode)

Definition at line 1424 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: ITC_Registers_Reset_Value

Defines
ITC_Registers_Reset_Value

Defines

#define ITC_SPRX_RESET_VALUE ((uint8_t)0xFF)

Define Documentation

#define ITC_SPRX_RESET_VALUE ((uint8_t)0xFF)

Reset value of Software Priority registers

Definition at line 1452 of file stm8s.h.

Referenced by ITC_DeInit().


STM8S/A Standard Peripherals Drivers: CPU_Registers_Bits_Definition

Defines
CPU_Registers_Bits_Definition

Defines

#define CPU_CC_I1I0 ((uint8_t)0x28)

Define Documentation

#define CPU_CC_I1I0 ((uint8_t)0x28)

Condition Code register, I1 and I0 bits mask

Definition at line 1462 of file stm8s.h.

Referenced by ITC_GetSoftIntStatus().


STM8S/A Standard Peripherals Drivers: EXTI_Registers_Reset_Value

Defines
EXTI_Registers_Reset_Value

Defines

#define | EXTI_CR1_RESET_VALUE ((uint8_t)0x00)
#define | EXTI_CR2_RESET_VALUE ((uint8_t)0x00)

Define Documentation

#define EXTI_CR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1484 of file stm8s.h.

Referenced by EXTI_DeInit().

#define EXTI_CR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 1485 of file stm8s.h.

Referenced by EXTI_DeInit().


STM8S/A Standard Peripherals Drivers: EXTI_Registers_Bits_Definition

Defines
EXTI_Registers_Bits_Definition

Defines

#define | EXTI_CR1_PAIS ((uint8_t)0x03)
#define | EXTI_CR1_PBIS ((uint8_t)0x0C)
#define | EXTI_CR1_PCIS ((uint8_t)0x30)
#define | EXTI_CR1_PDIS ((uint8_t)0xC0)
#define | EXTI_CR2_PEIS ((uint8_t)0x03)
#define | EXTI_CR2_TLIS ((uint8_t)0x04)

Define Documentation

#define EXTI_CR1_PAIS ((uint8_t)0x03)

PORTA external interrupt sensitivity bits mask

Definition at line 1498 of file stm8s.h.

Referenced by EXTI_GetExtIntSensitivity(), and EXTI_SetExtIntSensitivity().

#define EXTI_CR1_PBIS ((uint8_t)0x0C)

PORTB external interrupt sensitivity bits mask

Definition at line 1497 of file stm8s.h.

Referenced by EXTI_GetExtIntSensitivity(), and EXTI_SetExtIntSensitivity().

#define EXTI_CR1_PCIS ((uint8_t)0x30)

PORTC external interrupt sensitivity bits mask

Definition at line 1496 of file stm8s.h.

Referenced by EXTI_GetExtIntSensitivity(), and EXTI_SetExtIntSensitivity().

#define EXTI_CR1_PDIS ((uint8_t)0xC0)

PORTD external interrupt sensitivity bits mask

Definition at line 1495 of file stm8s.h.

Referenced by EXTI_GetExtIntSensitivity(), and EXTI_SetExtIntSensitivity().

#define EXTI_CR2_PEIS ((uint8_t)0x03)

PORTE external interrupt sensitivity bits mask

Definition at line 1501 of file stm8s.h.

Referenced by EXTI_GetExtIntSensitivity(), and EXTI_SetExtIntSensitivity().

#define EXTI_CR2_TLIS ((uint8_t)0x04)

Top level interrupt sensitivity bit mask

Definition at line 1500 of file stm8s.h.

Referenced by EXTI_GetTLISensitivity(), and EXTI_SetTLISensitivity().


STM8S/A Standard Peripherals Drivers: FLASH_Registers_Reset_Value

Defines
FLASH_Registers_Reset_Value

Defines

#define | FLASH_CR1_RESET_VALUE ((uint8_t)0x00)
#define | FLASH_CR2_RESET_VALUE ((uint8_t)0x00)
#define | FLASH_DUKR_RESET_VALUE ((uint8_t)0x00)
#define | FLASH_IAPSR_RESET_VALUE ((uint8_t)0x40)
#define | FLASH_NCR2_RESET_VALUE ((uint8_t)0xFF)
#define | FLASH_PUKR_RESET_VALUE ((uint8_t)0x00)

Define Documentation

#define FLASH_CR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1534 of file stm8s.h.

Referenced by FLASH_DeInit().

#define FLASH_CR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 1535 of file stm8s.h.

Referenced by FLASH_DeInit().

#define FLASH_DUKR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1539 of file stm8s.h.

#define FLASH_IAPSR_RESET_VALUE ((uint8_t)0x40)

Definition at line 1537 of file stm8s.h.

#define FLASH_NCR2_RESET_VALUE ((uint8_t)0xFF)

Definition at line 1536 of file stm8s.h.

Referenced by FLASH_DeInit().

#define FLASH_PUKR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1538 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: FLASH_Registers_Bits_Definition

Defines
FLASH_Registers_Bits_Definition

Defines

#define | FLASH_CR1_AHALT ((uint8_t)0x04)
#define | FLASH_CR1_FIX ((uint8_t)0x01)
#define | FLASH_CR1_HALT ((uint8_t)0x08)
#define | FLASH_CR1_IE ((uint8_t)0x02)
#define | FLASH_CR2_ERASE ((uint8_t)0x20)
#define | FLASH_CR2_FPRG ((uint8_t)0x10)
#define | FLASH_CR2_OPT ((uint8_t)0x80)
#define | FLASH_CR2_PRG ((uint8_t)0x01)
#define | FLASH_CR2_WPRG ((uint8_t)0x40)
#define | FLASH_DUKR_DUK ((uint8_t)0xFF)
#define | FLASH_IAPSR_DUL ((uint8_t)0x08)
#define | FLASH_IAPSR_EOP ((uint8_t)0x04)
#define | FLASH_IAPSR_HVOFF ((uint8_t)0x40)
#define | FLASH_IAPSR_PUL ((uint8_t)0x02)
#define | FLASH_IAPSR_WR_PG_DIS ((uint8_t)0x01)
#define | FLASH_NCR2_NERASE ((uint8_t)0x20)
#define | FLASH_NCR2_NFPRG ((uint8_t)0x10)
#define | FLASH_NCR2_NOPT ((uint8_t)0x80)
#define | FLASH_NCR2_NPRG ((uint8_t)0x01)
#define | FLASH_NCR2_NWPRG ((uint8_t)0x40)
#define | FLASH_PUKR_PUK ((uint8_t)0xFF)

Define Documentation

#define FLASH_CR1_AHALT ((uint8_t)0x04)

Standby in Active Halt mode mask

Definition at line 1550 of file stm8s.h.

Referenced by FLASH_GetLowPowerMode(), and FLASH_SetLowPowerMode().

#define FLASH_CR1_FIX ((uint8_t)0x01)

Fix programming time mask

Definition at line 1552 of file stm8s.h.

Referenced by FLASH_GetProgrammingTime(), and FLASH_SetProgrammingTime().

#define FLASH_CR1_HALT ((uint8_t)0x08)

Standby in Halt mode mask

Definition at line 1549 of file stm8s.h.

Referenced by FLASH_GetLowPowerMode(), and FLASH_SetLowPowerMode().

#define FLASH_CR1_IE ((uint8_t)0x02)

Flash Interrupt enable mask

Definition at line 1551 of file stm8s.h.

Referenced by FLASH_ITConfig().

#define FLASH_CR2_ERASE ((uint8_t)0x20)

Erase block mask

Definition at line 1556 of file stm8s.h.

#define FLASH_CR2_FPRG ((uint8_t)0x10)

Fast programming mode mask

Definition at line 1557 of file stm8s.h.

#define FLASH_CR2_OPT ((uint8_t)0x80)

Select option byte mask

Definition at line 1554 of file stm8s.h.

Referenced by FLASH_EraseOptionByte(), and FLASH_ProgramOptionByte().

#define FLASH_CR2_PRG ((uint8_t)0x01)

Program block mask

Definition at line 1558 of file stm8s.h.

#define FLASH_CR2_WPRG ((uint8_t)0x40)

Word Programming mask

Definition at line 1555 of file stm8s.h.

Referenced by FLASH_ProgramWord().

#define FLASH_DUKR_DUK ((uint8_t)0xFF)

Data EEPROM unprotection mask

Definition at line 1574 of file stm8s.h.

#define FLASH_IAPSR_DUL ((uint8_t)0x08)

Data EEPROM unlocked flag mask

Definition at line 1567 of file stm8s.h.

Referenced by FLASH_DeInit().

#define FLASH_IAPSR_EOP ((uint8_t)0x04)

End of operation flag mask

Definition at line 1568 of file stm8s.h.

#define FLASH_IAPSR_HVOFF ((uint8_t)0x40)

End of high voltage flag mask

Definition at line 1566 of file stm8s.h.

#define FLASH_IAPSR_PUL ((uint8_t)0x02)

Flash Program memory unlocked flag mask

Definition at line 1569 of file stm8s.h.

Referenced by FLASH_DeInit().

#define FLASH_IAPSR_WR_PG_DIS ((uint8_t)0x01)

Write attempted to protected page mask

Definition at line 1570 of file stm8s.h.

#define FLASH_NCR2_NERASE ((uint8_t)0x20)

Erase block mask

Definition at line 1562 of file stm8s.h.

#define FLASH_NCR2_NFPRG ((uint8_t)0x10)

Fast programming mode mask

Definition at line 1563 of file stm8s.h.

#define FLASH_NCR2_NOPT ((uint8_t)0x80)

Select option byte mask

Definition at line 1560 of file stm8s.h.

Referenced by FLASH_EraseOptionByte(), and FLASH_ProgramOptionByte().

#define FLASH_NCR2_NPRG ((uint8_t)0x01)

Program block mask

Definition at line 1564 of file stm8s.h.

#define FLASH_NCR2_NWPRG ((uint8_t)0x40)

Word Programming mask

Definition at line 1561 of file stm8s.h.

Referenced by FLASH_ProgramWord().

#define FLASH_PUKR_PUK ((uint8_t)0xFF)

Flash Program memory unprotection mask

Definition at line 1572 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: IWDG_Registers_Reset_Value

Defines
IWDG_Registers_Reset_Value

Defines

#define | IWDG_PR_RESET_VALUE ((uint8_t)0x00)
#define | IWDG_RLR_RESET_VALUE ((uint8_t)0xFF)

Define Documentation

#define IWDG_PR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1621 of file stm8s.h.

#define IWDG_RLR_RESET_VALUE ((uint8_t)0xFF)

Definition at line 1622 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: WWDG_Registers_Reset_Value

Defines
WWDG_Registers_Reset_Value

Defines

#define | WWDG_CR_RESET_VALUE ((uint8_t)0x7F)
#define | WWDG_WR_RESET_VALUE ((uint8_t)0x7F)

Define Documentation

#define WWDG_CR_RESET_VALUE ((uint8_t)0x7F)

Definition at line 1644 of file stm8s.h.

#define WWDG_WR_RESET_VALUE ((uint8_t)0x7F)

Definition at line 1645 of file stm8s.h.

Referenced by WWDG_Init().


STM8S/A Standard Peripherals Drivers: WWDG_Registers_Bits_Definition

Defines
WWDG_Registers_Bits_Definition

Defines

#define | WWDG_CR_T ((uint8_t)0x7F)
#define | WWDG_CR_T6 ((uint8_t)0x40)
#define | WWDG_CR_WDGA ((uint8_t)0x80)
#define | WWDG_WR_MSB ((uint8_t)0x80)
#define | WWDG_WR_W ((uint8_t)0x7F)

Define Documentation

#define WWDG_CR_T ((uint8_t)0x7F)

T bits mask

Definition at line 1657 of file stm8s.h.

#define WWDG_CR_T6 ((uint8_t)0x40)

T6 bit mask

Definition at line 1656 of file stm8s.h.

Referenced by WWDG_Init(), and WWDG_SetWindowValue().

#define WWDG_CR_WDGA ((uint8_t)0x80)

WDGA bit mask

Definition at line 1655 of file stm8s.h.

Referenced by WWDG_Init(), WWDG_SetWindowValue(), and WWDG_SWReset().

#define WWDG_WR_MSB ((uint8_t)0x80)

MSB bit mask

Definition at line 1659 of file stm8s.h.

#define WWDG_WR_W ((uint8_t)0x7F)

W bits mask

Definition at line 1660 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: RST_Registers_Bits_Definition

Defines
RST_Registers_Bits_Definition

Defines

#define | RST_SR_EMCF ((uint8_t)0x10)
#define | RST_SR_ILLOPF ((uint8_t)0x04)
#define | RST_SR_IWDGF ((uint8_t)0x02)
#define | RST_SR_SWIMF ((uint8_t)0x08)
#define | RST_SR_WWDGF ((uint8_t)0x01)

Define Documentation

#define RST_SR_EMCF ((uint8_t)0x10)

EMC reset flag bit mask

Definition at line 1681 of file stm8s.h.

#define RST_SR_ILLOPF ((uint8_t)0x04)

Illegal opcode reset flag bit mask

Definition at line 1683 of file stm8s.h.

#define RST_SR_IWDGF ((uint8_t)0x02)

IWDG reset flag bit mask

Definition at line 1684 of file stm8s.h.

#define RST_SR_SWIMF ((uint8_t)0x08)

SWIM reset flag bit mask

Definition at line 1682 of file stm8s.h.

#define RST_SR_WWDGF ((uint8_t)0x01)

WWDG reset flag bit mask

Definition at line 1685 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: SPI_Registers_Reset_Value

Defines
SPI_Registers_Reset_Value

Defines

#define | SPI_CR1_RESET_VALUE ((uint8_t)0x00)
#define | SPI_CR2_RESET_VALUE ((uint8_t)0x00)
#define | SPI_CRCPR_RESET_VALUE ((uint8_t)0x07)
#define | SPI_DR_RESET_VALUE ((uint8_t)0x00)
#define | SPI_ICR_RESET_VALUE ((uint8_t)0x00)
#define | SPI_RXCRCR_RESET_VALUE ((uint8_t)0x00)
#define | SPI_SR_RESET_VALUE ((uint8_t)0x02)
#define | SPI_TXCRCR_RESET_VALUE ((uint8_t)0x00)

Define Documentation

#define SPI_CR1_RESET_VALUE ((uint8_t)0x00)

Control Register 1 reset value

Definition at line 1713 of file stm8s.h.

Referenced by SPI_DeInit().

#define SPI_CR2_RESET_VALUE ((uint8_t)0x00)

Control Register 2 reset value

Definition at line 1714 of file stm8s.h.

Referenced by SPI_DeInit().

#define SPI_CRCPR_RESET_VALUE ((uint8_t)0x07)

Polynomial Register reset value

Definition at line 1718 of file stm8s.h.

Referenced by SPI_DeInit().

#define SPI_DR_RESET_VALUE ((uint8_t)0x00)

Data Register reset value

Definition at line 1717 of file stm8s.h.

#define SPI_ICR_RESET_VALUE ((uint8_t)0x00)

Interrupt Control Register reset value

Definition at line 1715 of file stm8s.h.

Referenced by SPI_DeInit().

#define SPI_RXCRCR_RESET_VALUE ((uint8_t)0x00)

RX CRC Register reset value

Definition at line 1719 of file stm8s.h.

#define SPI_SR_RESET_VALUE ((uint8_t)0x02)

Status Register reset value

Definition at line 1716 of file stm8s.h.

Referenced by SPI_DeInit().

#define SPI_TXCRCR_RESET_VALUE ((uint8_t)0x00)

TX CRC Register reset value

Definition at line 1720 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: SPI_Registers_Bits_Definition

Defines
SPI_Registers_Bits_Definition

Defines

#define | SPI_CR1_BR ((uint8_t)0x38)
#define | SPI_CR1_CPHA ((uint8_t)0x01)
#define | SPI_CR1_CPOL ((uint8_t)0x02)
#define | SPI_CR1_LSBFIRST ((uint8_t)0x80)
#define | SPI_CR1_MSTR ((uint8_t)0x04)
#define | SPI_CR1_SPE ((uint8_t)0x40)
#define | SPI_CR2_BDM ((uint8_t)0x80)
#define | SPI_CR2_BDOE ((uint8_t)0x40)
#define | SPI_CR2_CRCEN ((uint8_t)0x20)
#define | SPI_CR2_CRCNEXT ((uint8_t)0x10)
#define | SPI_CR2_RXONLY ((uint8_t)0x04)
#define | SPI_CR2_SSI ((uint8_t)0x01)
#define | SPI_CR2_SSM ((uint8_t)0x02)
#define | SPI_ICR_ERRIE ((uint8_t)0x20)
#define | SPI_ICR_RXEI ((uint8_t)0x40)
#define | SPI_ICR_TXEI ((uint8_t)0x80)
#define | SPI_ICR_WKIE ((uint8_t)0x10)
#define | SPI_SR_BSY ((uint8_t)0x80)
#define | SPI_SR_CRCERR ((uint8_t)0x10)
#define | SPI_SR_MODF ((uint8_t)0x20)
#define | SPI_SR_OVR ((uint8_t)0x40)
#define | SPI_SR_RXNE ((uint8_t)0x01)
#define | SPI_SR_TXE ((uint8_t)0x02)
#define | SPI_SR_WKUP ((uint8_t)0x08)

Define Documentation

#define SPI_CR1_BR ((uint8_t)0x38)

Baud rate control mask

Definition at line 1732 of file stm8s.h.

#define SPI_CR1_CPHA ((uint8_t)0x01)

Clock Phase mask

Definition at line 1735 of file stm8s.h.

#define SPI_CR1_CPOL ((uint8_t)0x02)

Clock Polarity mask

Definition at line 1734 of file stm8s.h.

#define SPI_CR1_LSBFIRST ((uint8_t)0x80)

Frame format mask

Definition at line 1730 of file stm8s.h.

#define SPI_CR1_MSTR ((uint8_t)0x04)

Master Selection mask

Definition at line 1733 of file stm8s.h.

#define SPI_CR1_SPE ((uint8_t)0x40)

Enable bits mask

Definition at line 1731 of file stm8s.h.

Referenced by SPI_Cmd().

#define SPI_CR2_BDM ((uint8_t)0x80)

Bi-directional data mode enable mask

Definition at line 1737 of file stm8s.h.

#define SPI_CR2_BDOE ((uint8_t)0x40)

Output enable in bi-directional mode mask

Definition at line 1738 of file stm8s.h.

Referenced by SPI_BiDirectionalLineConfig().

#define SPI_CR2_CRCEN ((uint8_t)0x20)

Hardware CRC calculation enable mask

Definition at line 1739 of file stm8s.h.

Referenced by SPI_CalculateCRCCmd().

#define SPI_CR2_CRCNEXT ((uint8_t)0x10)

Transmit CRC next mask

Definition at line 1740 of file stm8s.h.

Referenced by SPI_TransmitCRC().

#define SPI_CR2_RXONLY ((uint8_t)0x04)

Receive only mask

Definition at line 1741 of file stm8s.h.

#define SPI_CR2_SSI ((uint8_t)0x01)

Internal slave select mask

Definition at line 1743 of file stm8s.h.

Referenced by SPI_Init(), and SPI_NSSInternalSoftwareCmd().

#define SPI_CR2_SSM ((uint8_t)0x02)

Software slave management mask

Definition at line 1742 of file stm8s.h.

#define SPI_ICR_ERRIE ((uint8_t)0x20)

Error interrupt enable mask

Definition at line 1747 of file stm8s.h.

#define SPI_ICR_RXEI ((uint8_t)0x40)

Rx buffer empty interrupt enable mask

Definition at line 1746 of file stm8s.h.

#define SPI_ICR_TXEI ((uint8_t)0x80)

Tx buffer empty interrupt enable mask

Definition at line 1745 of file stm8s.h.

#define SPI_ICR_WKIE ((uint8_t)0x10)

Wake-up interrupt enable mask

Definition at line 1748 of file stm8s.h.

#define SPI_SR_BSY ((uint8_t)0x80)

Busy flag

Definition at line 1750 of file stm8s.h.

#define SPI_SR_CRCERR ((uint8_t)0x10)

CRC error flag

Definition at line 1753 of file stm8s.h.

#define SPI_SR_MODF ((uint8_t)0x20)

Mode fault

Definition at line 1752 of file stm8s.h.

#define SPI_SR_OVR ((uint8_t)0x40)

Overrun flag

Definition at line 1751 of file stm8s.h.

#define SPI_SR_RXNE ((uint8_t)0x01)

Receive buffer not empty

Definition at line 1756 of file stm8s.h.

#define SPI_SR_TXE ((uint8_t)0x02)

Transmit buffer empty

Definition at line 1755 of file stm8s.h.

#define SPI_SR_WKUP ((uint8_t)0x08)

Wake-Up flag

Definition at line 1754 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: UART1_Registers_Reset_Value

Defines
UART1_Registers_Reset_Value

Defines

#define | UART1_BRR1_RESET_VALUE ((uint8_t)0x00)
#define | UART1_BRR2_RESET_VALUE ((uint8_t)0x00)
#define | UART1_CR1_RESET_VALUE ((uint8_t)0x00)
#define | UART1_CR2_RESET_VALUE ((uint8_t)0x00)
#define | UART1_CR3_RESET_VALUE ((uint8_t)0x00)
#define | UART1_CR4_RESET_VALUE ((uint8_t)0x00)
#define | UART1_CR5_RESET_VALUE ((uint8_t)0x00)
#define | UART1_GTR_RESET_VALUE ((uint8_t)0x00)
#define | UART1_PSCR_RESET_VALUE ((uint8_t)0x00)
#define | UART1_SR_RESET_VALUE ((uint8_t)0xC0)

Define Documentation

#define UART1_BRR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1788 of file stm8s.h.

Referenced by UART1_DeInit().

#define UART1_BRR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 1789 of file stm8s.h.

Referenced by UART1_DeInit().

#define UART1_CR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1790 of file stm8s.h.

Referenced by UART1_DeInit().

#define UART1_CR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 1791 of file stm8s.h.

Referenced by UART1_DeInit().

#define UART1_CR3_RESET_VALUE ((uint8_t)0x00)

Definition at line 1792 of file stm8s.h.

Referenced by UART1_DeInit().

#define UART1_CR4_RESET_VALUE ((uint8_t)0x00)

Definition at line 1793 of file stm8s.h.

Referenced by UART1_DeInit().

#define UART1_CR5_RESET_VALUE ((uint8_t)0x00)

Definition at line 1794 of file stm8s.h.

Referenced by UART1_DeInit().

#define UART1_GTR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1795 of file stm8s.h.

Referenced by UART1_DeInit().

#define UART1_PSCR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1796 of file stm8s.h.

Referenced by UART1_DeInit().

#define UART1_SR_RESET_VALUE ((uint8_t)0xC0)

Definition at line 1787 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: UART1_Registers_Bits_Definition

Defines
UART1_Registers_Bits_Definition

Defines

#define | UART1_BRR1_DIVM ((uint8_t)0xFF)
#define | UART1_BRR2_DIVF ((uint8_t)0x0F)
#define | UART1_BRR2_DIVM ((uint8_t)0xF0)
#define | UART1_CR1_M ((uint8_t)0x10)
#define | UART1_CR1_PCEN ((uint8_t)0x04)
#define | UART1_CR1_PIEN ((uint8_t)0x01)
#define | UART1_CR1_PS ((uint8_t)0x02)
#define | UART1_CR1_R8 ((uint8_t)0x80)
#define | UART1_CR1_T8 ((uint8_t)0x40)
#define | UART1_CR1_UARTD ((uint8_t)0x20)
#define | UART1_CR1_WAKE ((uint8_t)0x08)
#define | UART1_CR2_ILIEN ((uint8_t)0x10)
#define | UART1_CR2_REN ((uint8_t)0x04)
#define | UART1_CR2_RIEN ((uint8_t)0x20)
#define | UART1_CR2_RWU ((uint8_t)0x02)
#define | UART1_CR2_SBK ((uint8_t)0x01)
#define | UART1_CR2_TCIEN ((uint8_t)0x40)
#define | UART1_CR2_TEN ((uint8_t)0x08)
#define | UART1_CR2_TIEN ((uint8_t)0x80)
#define | UART1_CR3_CKEN ((uint8_t)0x08)
#define | UART1_CR3_CPHA ((uint8_t)0x02)
#define | UART1_CR3_CPOL ((uint8_t)0x04)
#define | UART1_CR3_LBCL ((uint8_t)0x01)
#define | UART1_CR3_LINEN ((uint8_t)0x40)
#define | UART1_CR3_STOP ((uint8_t)0x30)
#define | UART1_CR4_ADD ((uint8_t)0x0F)
#define | UART1_CR4_LBDF ((uint8_t)0x10)
#define | UART1_CR4_LBDIEN ((uint8_t)0x40)
#define | UART1_CR4_LBDL ((uint8_t)0x20)
#define | UART1_CR5_HDSEL ((uint8_t)0x08)
#define | UART1_CR5_IREN ((uint8_t)0x02)
#define | UART1_CR5_IRLP ((uint8_t)0x04)
#define | UART1_CR5_NACK ((uint8_t)0x10)
#define | UART1_CR5_SCEN ((uint8_t)0x20)
#define | UART1_SR_FE ((uint8_t)0x02)
#define | UART1_SR_IDLE ((uint8_t)0x10)
#define | UART1_SR_NF ((uint8_t)0x04)
#define | UART1_SR_OR ((uint8_t)0x08)
#define | UART1_SR_PE ((uint8_t)0x01)
#define | UART1_SR_RXNE ((uint8_t)0x20)
#define | UART1_SR_TC ((uint8_t)0x40)
#define | UART1_SR_TXE ((uint8_t)0x80)

Define Documentation

#define UART1_BRR1_DIVM ((uint8_t)0xFF)

LSB mantissa of UART1DIV [7:0] mask

Definition at line 1815 of file stm8s.h.

Referenced by UART1_Init().

#define UART1_BRR2_DIVF ((uint8_t)0x0F)

Fraction bits of UART1DIV [3:0] mask

Definition at line 1818 of file stm8s.h.

Referenced by UART1_Init().

#define UART1_BRR2_DIVM ((uint8_t)0xF0)

MSB mantissa of UART1DIV [11:8] mask

Definition at line 1817 of file stm8s.h.

Referenced by UART1_Init().

#define UART1_CR1_M ((uint8_t)0x10)

Word length mask

Definition at line 1823 of file stm8s.h.

Referenced by UART1_Init().

#define UART1_CR1_PCEN ((uint8_t)0x04)

Parity Control Enable mask

Definition at line 1825 of file stm8s.h.

Referenced by UART1_Init().

#define UART1_CR1_PIEN ((uint8_t)0x01)

UART1 Parity Interrupt Enable mask

Definition at line 1827 of file stm8s.h.

#define UART1_CR1_PS ((uint8_t)0x02)

UART1 Parity Selection

Definition at line 1826 of file stm8s.h.

Referenced by UART1_Init().

#define UART1_CR1_R8 ((uint8_t)0x80)

Receive Data bit 8

Definition at line 1820 of file stm8s.h.

Referenced by UART1_ReceiveData9().

#define UART1_CR1_T8 ((uint8_t)0x40)

Transmit data bit 8

Definition at line 1821 of file stm8s.h.

Referenced by UART1_SendData9().

#define UART1_CR1_UARTD ((uint8_t)0x20)

UART1 Disable (for low power consumption)

Definition at line 1822 of file stm8s.h.

Referenced by UART1_Cmd().

#define UART1_CR1_WAKE ((uint8_t)0x08)

Wake-up method mask

Definition at line 1824 of file stm8s.h.

Referenced by UART1_WakeUpConfig().

#define UART1_CR2_ILIEN ((uint8_t)0x10)

IDLE Line Interrupt Enable mask

Definition at line 1832 of file stm8s.h.

#define UART1_CR2_REN ((uint8_t)0x04)

Receiver Enable mask

Definition at line 1834 of file stm8s.h.

Referenced by UART1_Init().

#define UART1_CR2_RIEN ((uint8_t)0x20)

Receiver Interrupt Enable mask

Definition at line 1831 of file stm8s.h.

#define UART1_CR2_RWU ((uint8_t)0x02)

Receiver Wake-Up mask

Definition at line 1835 of file stm8s.h.

Referenced by UART1_ReceiverWakeUpCmd().

#define UART1_CR2_SBK ((uint8_t)0x01)

Send Break mask

Definition at line 1836 of file stm8s.h.

Referenced by UART1_SendBreak().

#define UART1_CR2_TCIEN ((uint8_t)0x40)

Transmission Complete Interrupt Enable mask

Definition at line 1830 of file stm8s.h.

#define UART1_CR2_TEN ((uint8_t)0x08)

Transmitter Enable mask

Definition at line 1833 of file stm8s.h.

Referenced by UART1_Init().

#define UART1_CR2_TIEN ((uint8_t)0x80)

Transmitter Interrupt Enable mask

Definition at line 1829 of file stm8s.h.

#define UART1_CR3_CKEN ((uint8_t)0x08)

Clock Enable mask

Definition at line 1840 of file stm8s.h.

Referenced by UART1_Init().

#define UART1_CR3_CPHA ((uint8_t)0x02)

Clock Phase mask

Definition at line 1842 of file stm8s.h.

Referenced by UART1_Init().

#define UART1_CR3_CPOL ((uint8_t)0x04)

Clock Polarity mask

Definition at line 1841 of file stm8s.h.

Referenced by UART1_Init().

#define UART1_CR3_LBCL ((uint8_t)0x01)

Last Bit Clock pulse mask

Definition at line 1843 of file stm8s.h.

Referenced by UART1_Init().

#define UART1_CR3_LINEN ((uint8_t)0x40)

Alternate Function output mask

Definition at line 1838 of file stm8s.h.

Referenced by UART1_LINCmd().

#define UART1_CR3_STOP ((uint8_t)0x30)

STOP bits [1:0] mask

Definition at line 1839 of file stm8s.h.

Referenced by UART1_Init().

#define UART1_CR4_ADD ((uint8_t)0x0F)

Address of the UART1 node mask

Definition at line 1848 of file stm8s.h.

Referenced by UART1_SetAddress().

#define UART1_CR4_LBDF ((uint8_t)0x10)

LIN Break Detection Flag mask

Definition at line 1847 of file stm8s.h.

Referenced by UART1_ClearFlag(), and UART1_ClearITPendingBit().

#define UART1_CR4_LBDIEN ((uint8_t)0x40)

LIN Break Detection Interrupt Enable mask

Definition at line 1845 of file stm8s.h.

#define UART1_CR4_LBDL ((uint8_t)0x20)

LIN Break Detection Length mask

Definition at line 1846 of file stm8s.h.

Referenced by UART1_LINBreakDetectionConfig().

#define UART1_CR5_HDSEL ((uint8_t)0x08)

Half-Duplex Selection mask

Definition at line 1852 of file stm8s.h.

Referenced by UART1_HalfDuplexCmd().

#define UART1_CR5_IREN ((uint8_t)0x02)

Irda Enable mask

Definition at line 1854 of file stm8s.h.

Referenced by UART1_IrDACmd().

#define UART1_CR5_IRLP ((uint8_t)0x04)

Irda Low Power Selection mask

Definition at line 1853 of file stm8s.h.

Referenced by UART1_IrDAConfig().

#define UART1_CR5_NACK ((uint8_t)0x10)

Smart Card Nack Enable mask

Definition at line 1851 of file stm8s.h.

Referenced by UART1_SmartCardNACKCmd().

#define UART1_CR5_SCEN ((uint8_t)0x20)

Smart Card Enable mask

Definition at line 1850 of file stm8s.h.

Referenced by UART1_SmartCardCmd().

#define UART1_SR_FE ((uint8_t)0x02)

Framing Error mask

Definition at line 1812 of file stm8s.h.

#define UART1_SR_IDLE ((uint8_t)0x10)

IDLE line detected mask

Definition at line 1809 of file stm8s.h.

#define UART1_SR_NF ((uint8_t)0x04)

Noise Flag mask

Definition at line 1811 of file stm8s.h.

#define UART1_SR_OR ((uint8_t)0x08)

OverRun error mask

Definition at line 1810 of file stm8s.h.

#define UART1_SR_PE ((uint8_t)0x01)

Parity Error mask

Definition at line 1813 of file stm8s.h.

#define UART1_SR_RXNE ((uint8_t)0x20)

Read Data Register Not Empty mask

Definition at line 1808 of file stm8s.h.

Referenced by UART1_ClearFlag(), and UART1_ClearITPendingBit().

#define UART1_SR_TC ((uint8_t)0x40)

Transmission Complete mask

Definition at line 1807 of file stm8s.h.

#define UART1_SR_TXE ((uint8_t)0x80)

Transmit Data Register Empty mask

Definition at line 1806 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: UART2_Registers_Reset_Value

Defines
UART2_Registers_Reset_Value

Defines

#define | UART2_BRR1_RESET_VALUE ((uint8_t)0x00)
#define | UART2_BRR2_RESET_VALUE ((uint8_t)0x00)
#define | UART2_CR1_RESET_VALUE ((uint8_t)0x00)
#define | UART2_CR2_RESET_VALUE ((uint8_t)0x00)
#define | UART2_CR3_RESET_VALUE ((uint8_t)0x00)
#define | UART2_CR4_RESET_VALUE ((uint8_t)0x00)
#define | UART2_CR5_RESET_VALUE ((uint8_t)0x00)
#define | UART2_CR6_RESET_VALUE ((uint8_t)0x00)
#define | UART2_GTR_RESET_VALUE ((uint8_t)0x00)
#define | UART2_PSCR_RESET_VALUE ((uint8_t)0x00)
#define | UART2_SR_RESET_VALUE ((uint8_t)0xC0)

Define Documentation

#define UART2_BRR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1887 of file stm8s.h.

Referenced by UART2_DeInit().

#define UART2_BRR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 1888 of file stm8s.h.

Referenced by UART2_DeInit().

#define UART2_CR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1889 of file stm8s.h.

Referenced by UART2_DeInit().

#define UART2_CR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 1890 of file stm8s.h.

Referenced by UART2_DeInit().

#define UART2_CR3_RESET_VALUE ((uint8_t)0x00)

Definition at line 1891 of file stm8s.h.

Referenced by UART2_DeInit().

#define UART2_CR4_RESET_VALUE ((uint8_t)0x00)

Definition at line 1892 of file stm8s.h.

Referenced by UART2_DeInit().

#define UART2_CR5_RESET_VALUE ((uint8_t)0x00)

Definition at line 1893 of file stm8s.h.

Referenced by UART2_DeInit().

#define UART2_CR6_RESET_VALUE ((uint8_t)0x00)

Definition at line 1894 of file stm8s.h.

Referenced by UART2_DeInit().

#define UART2_GTR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1895 of file stm8s.h.

#define UART2_PSCR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1896 of file stm8s.h.

#define UART2_SR_RESET_VALUE ((uint8_t)0xC0)

Definition at line 1886 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: UART2_Registers_Bits_Definition

Defines
UART2_Registers_Bits_Definition

Defines

#define | UART2_BRR1_DIVM ((uint8_t)0xFF)
#define | UART2_BRR2_DIVF ((uint8_t)0x0F)
#define | UART2_BRR2_DIVM ((uint8_t)0xF0)
#define | UART2_CR1_M ((uint8_t)0x10)
#define | UART2_CR1_PCEN ((uint8_t)0x04)
#define | UART2_CR1_PIEN ((uint8_t)0x01)
#define | UART2_CR1_PS ((uint8_t)0x02)
#define | UART2_CR1_R8 ((uint8_t)0x80)
#define | UART2_CR1_T8 ((uint8_t)0x40)
#define | UART2_CR1_UARTD ((uint8_t)0x20)
#define | UART2_CR1_WAKE ((uint8_t)0x08)
#define | UART2_CR2_ILIEN ((uint8_t)0x10)
#define | UART2_CR2_REN ((uint8_t)0x04)
#define | UART2_CR2_RIEN ((uint8_t)0x20)
#define | UART2_CR2_RWU ((uint8_t)0x02)
#define | UART2_CR2_SBK ((uint8_t)0x01)
#define | UART2_CR2_TCIEN ((uint8_t)0x40)
#define | UART2_CR2_TEN ((uint8_t)0x08)
#define | UART2_CR2_TIEN ((uint8_t)0x80)
#define | UART2_CR3_CKEN ((uint8_t)0x08)
#define | UART2_CR3_CPHA ((uint8_t)0x02)
#define | UART2_CR3_CPOL ((uint8_t)0x04)
#define | UART2_CR3_LBCL ((uint8_t)0x01)
#define | UART2_CR3_LINEN ((uint8_t)0x40)
#define | UART2_CR3_STOP ((uint8_t)0x30)
#define | UART2_CR4_ADD ((uint8_t)0x0F)
#define | UART2_CR4_LBDF ((uint8_t)0x10)
#define | UART2_CR4_LBDIEN ((uint8_t)0x40)
#define | UART2_CR4_LBDL ((uint8_t)0x20)
#define | UART2_CR5_IREN ((uint8_t)0x02)
#define | UART2_CR5_IRLP ((uint8_t)0x04)
#define | UART2_CR5_NACK ((uint8_t)0x10)
#define | UART2_CR5_SCEN ((uint8_t)0x20)
#define | UART2_CR6_LASE ((uint8_t)0x10)
#define | UART2_CR6_LDUM ((uint8_t)0x80)
#define | UART2_CR6_LHDF ((uint8_t)0x02)
#define | UART2_CR6_LHDIEN ((uint8_t)0x04)
#define | UART2_CR6_LSF ((uint8_t)0x01)
#define | UART2_CR6_LSLV ((uint8_t)0x20)
#define | UART2_SR_FE ((uint8_t)0x02)
#define | UART2_SR_IDLE ((uint8_t)0x10)
#define | UART2_SR_NF ((uint8_t)0x04)
#define | UART2_SR_OR ((uint8_t)0x08)
#define | UART2_SR_PE ((uint8_t)0x01)
#define | UART2_SR_RXNE ((uint8_t)0x20)
#define | UART2_SR_TC ((uint8_t)0x40)
#define | UART2_SR_TXE ((uint8_t)0x80)

Define Documentation

#define UART2_BRR1_DIVM ((uint8_t)0xFF)

LSB mantissa of UART2DIV [7:0] mask

Definition at line 1915 of file stm8s.h.

Referenced by UART2_Init().

#define UART2_BRR2_DIVF ((uint8_t)0x0F)

Fraction bits of UART2DIV [3:0] mask

Definition at line 1918 of file stm8s.h.

Referenced by UART2_Init().

#define UART2_BRR2_DIVM ((uint8_t)0xF0)

MSB mantissa of UART2DIV [11:8] mask

Definition at line 1917 of file stm8s.h.

Referenced by UART2_Init().

#define UART2_CR1_M ((uint8_t)0x10)

Word length mask

Definition at line 1923 of file stm8s.h.

Referenced by UART2_Init().

#define UART2_CR1_PCEN ((uint8_t)0x04)

Parity Control Enable mask

Definition at line 1925 of file stm8s.h.

Referenced by UART2_Init().

#define UART2_CR1_PIEN ((uint8_t)0x01)

UART2 Parity Interrupt Enable mask

Definition at line 1927 of file stm8s.h.

#define UART2_CR1_PS ((uint8_t)0x02)

UART2 Parity Selection

Definition at line 1926 of file stm8s.h.

Referenced by UART2_Init().

#define UART2_CR1_R8 ((uint8_t)0x80)

Receive Data bit 8

Definition at line 1920 of file stm8s.h.

Referenced by UART2_ReceiveData9().

#define UART2_CR1_T8 ((uint8_t)0x40)

Transmit data bit 8

Definition at line 1921 of file stm8s.h.

Referenced by UART2_SendData9().

#define UART2_CR1_UARTD ((uint8_t)0x20)

UART2 Disable (for low power consumption)

Definition at line 1922 of file stm8s.h.

Referenced by UART2_Cmd().

#define UART2_CR1_WAKE ((uint8_t)0x08)

Wake-up method mask

Definition at line 1924 of file stm8s.h.

Referenced by UART2_WakeUpConfig().

#define UART2_CR2_ILIEN ((uint8_t)0x10)

IDLE Line Interrupt Enable mask

Definition at line 1932 of file stm8s.h.

#define UART2_CR2_REN ((uint8_t)0x04)

Receiver Enable mask

Definition at line 1934 of file stm8s.h.

Referenced by UART2_Init().

#define UART2_CR2_RIEN ((uint8_t)0x20)

Receiver Interrupt Enable mask

Definition at line 1931 of file stm8s.h.

#define UART2_CR2_RWU ((uint8_t)0x02)

Receiver Wake-Up mask

Definition at line 1935 of file stm8s.h.

Referenced by UART2_ReceiverWakeUpCmd().

#define UART2_CR2_SBK ((uint8_t)0x01)

Send Break mask

Definition at line 1936 of file stm8s.h.

Referenced by UART2_SendBreak().

#define UART2_CR2_TCIEN ((uint8_t)0x40)

Transmission Complete Interrupt Enable mask

Definition at line 1930 of file stm8s.h.

#define UART2_CR2_TEN ((uint8_t)0x08)

Transmitter Enable mask

Definition at line 1933 of file stm8s.h.

Referenced by UART2_Init().

#define UART2_CR2_TIEN ((uint8_t)0x80)

Transmitter Interrupt Enable mask

Definition at line 1929 of file stm8s.h.

#define UART2_CR3_CKEN ((uint8_t)0x08)

Clock Enable mask

Definition at line 1940 of file stm8s.h.

Referenced by UART2_Init().

#define UART2_CR3_CPHA ((uint8_t)0x02)

Clock Phase mask

Definition at line 1942 of file stm8s.h.

Referenced by UART2_Init().

#define UART2_CR3_CPOL ((uint8_t)0x04)

Clock Polarity mask

Definition at line 1941 of file stm8s.h.

Referenced by UART2_Init().

#define UART2_CR3_LBCL ((uint8_t)0x01)

Last Bit Clock pulse mask

Definition at line 1943 of file stm8s.h.

Referenced by UART2_Init().

#define UART2_CR3_LINEN ((uint8_t)0x40)

Alternate Function output mask

Definition at line 1938 of file stm8s.h.

Referenced by UART2_LINCmd().

#define UART2_CR3_STOP ((uint8_t)0x30)

STOP bits [1:0] mask

Definition at line 1939 of file stm8s.h.

Referenced by UART2_Init().

#define UART2_CR4_ADD ((uint8_t)0x0F)

Address of the UART2 node mask

Definition at line 1948 of file stm8s.h.

Referenced by UART2_SetAddress().

#define UART2_CR4_LBDF ((uint8_t)0x10)

LIN Break Detection Flag mask

Definition at line 1947 of file stm8s.h.

Referenced by UART2_ClearFlag(), and UART2_ClearITPendingBit().

#define UART2_CR4_LBDIEN ((uint8_t)0x40)

LIN Break Detection Interrupt Enable mask

Definition at line 1945 of file stm8s.h.

#define UART2_CR4_LBDL ((uint8_t)0x20)

LIN Break Detection Length mask

Definition at line 1946 of file stm8s.h.

Referenced by UART2_LINBreakDetectionConfig().

#define UART2_CR5_IREN ((uint8_t)0x02)

Irda Enable mask

Definition at line 1953 of file stm8s.h.

Referenced by UART2_IrDACmd().

#define UART2_CR5_IRLP ((uint8_t)0x04)

Irda Low Power Selection mask

Definition at line 1952 of file stm8s.h.

Referenced by UART2_IrDAConfig().

#define UART2_CR5_NACK ((uint8_t)0x10)

Smart Card Nack Enable mask

Definition at line 1951 of file stm8s.h.

Referenced by UART2_SmartCardNACKCmd().

#define UART2_CR5_SCEN ((uint8_t)0x20)

Smart Card Enable mask

Definition at line 1950 of file stm8s.h.

Referenced by UART2_SmartCardCmd().

#define UART2_CR6_LASE ((uint8_t)0x10)

LIN Auto synchronization Enable

Definition at line 1957 of file stm8s.h.

Referenced by UART2_LINConfig().

#define UART2_CR6_LDUM ((uint8_t)0x80)

LIN Divider Update Method

Definition at line 1955 of file stm8s.h.

Referenced by UART2_LINConfig().

#define UART2_CR6_LHDF ((uint8_t)0x02)

LIN Header Detection Flag

Definition at line 1959 of file stm8s.h.

Referenced by UART2_ClearFlag(), and UART2_ClearITPendingBit().

#define UART2_CR6_LHDIEN ((uint8_t)0x04)

LIN Header Detection Interrupt Enable

Definition at line 1958 of file stm8s.h.

#define UART2_CR6_LSF ((uint8_t)0x01)

LIN Synch Field

Definition at line 1960 of file stm8s.h.

Referenced by UART2_ClearFlag().

#define UART2_CR6_LSLV ((uint8_t)0x20)

LIN Slave Enable

Definition at line 1956 of file stm8s.h.

Referenced by UART2_LINConfig().

#define UART2_SR_FE ((uint8_t)0x02)

Framing Error mask

Definition at line 1912 of file stm8s.h.

#define UART2_SR_IDLE ((uint8_t)0x10)

IDLE line detected mask

Definition at line 1909 of file stm8s.h.

#define UART2_SR_NF ((uint8_t)0x04)

Noise Flag mask

Definition at line 1911 of file stm8s.h.

#define UART2_SR_OR ((uint8_t)0x08)

OverRun error mask

Definition at line 1910 of file stm8s.h.

#define UART2_SR_PE ((uint8_t)0x01)

Parity Error mask

Definition at line 1913 of file stm8s.h.

#define UART2_SR_RXNE ((uint8_t)0x20)

Read Data Register Not Empty mask

Definition at line 1908 of file stm8s.h.

Referenced by UART2_ClearFlag(), and UART2_ClearITPendingBit().

#define UART2_SR_TC ((uint8_t)0x40)

Transmission Complete mask

Definition at line 1907 of file stm8s.h.

#define UART2_SR_TXE ((uint8_t)0x80)

Transmit Data Register Empty mask

Definition at line 1906 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: UART3_Registers_Reset_Value

Defines
UART3_Registers_Reset_Value

Defines

#define | UART3_BRR1_RESET_VALUE ((uint8_t)0x00)
#define | UART3_BRR2_RESET_VALUE ((uint8_t)0x00)
#define | UART3_CR1_RESET_VALUE ((uint8_t)0x00)
#define | UART3_CR2_RESET_VALUE ((uint8_t)0x00)
#define | UART3_CR3_RESET_VALUE ((uint8_t)0x00)
#define | UART3_CR4_RESET_VALUE ((uint8_t)0x00)
#define | UART3_CR6_RESET_VALUE ((uint8_t)0x00)
#define | UART3_SR_RESET_VALUE ((uint8_t)0xC0)

Define Documentation

#define UART3_BRR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1992 of file stm8s.h.

Referenced by UART3_DeInit().

#define UART3_BRR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 1993 of file stm8s.h.

Referenced by UART3_DeInit().

#define UART3_CR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1994 of file stm8s.h.

Referenced by UART3_DeInit().

#define UART3_CR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 1995 of file stm8s.h.

Referenced by UART3_DeInit().

#define UART3_CR3_RESET_VALUE ((uint8_t)0x00)

Definition at line 1996 of file stm8s.h.

Referenced by UART3_DeInit().

#define UART3_CR4_RESET_VALUE ((uint8_t)0x00)

Definition at line 1997 of file stm8s.h.

Referenced by UART3_DeInit().

#define UART3_CR6_RESET_VALUE ((uint8_t)0x00)

Definition at line 1998 of file stm8s.h.

Referenced by UART3_DeInit().

#define UART3_SR_RESET_VALUE ((uint8_t)0xC0)

Definition at line 1991 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: UART3_Registers_Bits_Definition

Defines
UART3_Registers_Bits_Definition

Defines

#define | UART3_BRR1_DIVM ((uint8_t)0xFF)
#define | UART3_BRR2_DIVF ((uint8_t)0x0F)
#define | UART3_BRR2_DIVM ((uint8_t)0xF0)
#define | UART3_CR1_M ((uint8_t)0x10)
#define | UART3_CR1_PCEN ((uint8_t)0x04)
#define | UART3_CR1_PIEN ((uint8_t)0x01)
#define | UART3_CR1_PS ((uint8_t)0x02)
#define | UART3_CR1_R8 ((uint8_t)0x80)
#define | UART3_CR1_T8 ((uint8_t)0x40)
#define | UART3_CR1_UARTD ((uint8_t)0x20)
#define | UART3_CR1_WAKE ((uint8_t)0x08)
#define | UART3_CR2_ILIEN ((uint8_t)0x10)
#define | UART3_CR2_REN ((uint8_t)0x04)
#define | UART3_CR2_RIEN ((uint8_t)0x20)
#define | UART3_CR2_RWU ((uint8_t)0x02)
#define | UART3_CR2_SBK ((uint8_t)0x01)
#define | UART3_CR2_TCIEN ((uint8_t)0x40)
#define | UART3_CR2_TEN ((uint8_t)0x08)
#define | UART3_CR2_TIEN ((uint8_t)0x80)
#define | UART3_CR3_LINEN ((uint8_t)0x40)
#define | UART3_CR3_STOP ((uint8_t)0x30)
#define | UART3_CR4_ADD ((uint8_t)0x0F)
#define | UART3_CR4_LBDF ((uint8_t)0x10)
#define | UART3_CR4_LBDIEN ((uint8_t)0x40)
#define | UART3_CR4_LBDL ((uint8_t)0x20)
#define | UART3_CR6_LASE ((uint8_t)0x10)
#define | UART3_CR6_LDUM ((uint8_t)0x80)
#define | UART3_CR6_LHDF ((uint8_t)0x02)
#define | UART3_CR6_LHDIEN ((uint8_t)0x04)
#define | UART3_CR6_LSF ((uint8_t)0x01)
#define | UART3_CR6_LSLV ((uint8_t)0x20)
#define | UART3_SR_FE ((uint8_t)0x02)
#define | UART3_SR_IDLE ((uint8_t)0x10)
#define | UART3_SR_NF ((uint8_t)0x04)
#define | UART3_SR_OR ((uint8_t)0x08)
#define | UART3_SR_PE ((uint8_t)0x01)
#define | UART3_SR_RXNE ((uint8_t)0x20)
#define | UART3_SR_TC ((uint8_t)0x40)
#define | UART3_SR_TXE ((uint8_t)0x80)

Define Documentation

#define UART3_BRR1_DIVM ((uint8_t)0xFF)

LSB mantissa of UARTDIV [7:0] mask

Definition at line 2017 of file stm8s.h.

Referenced by UART3_Init().

#define UART3_BRR2_DIVF ((uint8_t)0x0F)

Fraction bits of UARTDIV [3:0] mask

Definition at line 2020 of file stm8s.h.

Referenced by UART3_Init().

#define UART3_BRR2_DIVM ((uint8_t)0xF0)

MSB mantissa of UARTDIV [11:8] mask

Definition at line 2019 of file stm8s.h.

Referenced by UART3_Init().

#define UART3_CR1_M ((uint8_t)0x10)

Word length mask

Definition at line 2025 of file stm8s.h.

Referenced by UART3_Init().

#define UART3_CR1_PCEN ((uint8_t)0x04)

Parity control enable mask

Definition at line 2027 of file stm8s.h.

Referenced by UART3_Init().

#define UART3_CR1_PIEN ((uint8_t)0x01)

Parity interrupt enable bit mask

Definition at line 2029 of file stm8s.h.

#define UART3_CR1_PS ((uint8_t)0x02)

Parity selection bit mask

Definition at line 2028 of file stm8s.h.

Referenced by UART3_Init().

#define UART3_CR1_R8 ((uint8_t)0x80)

Receive Data bit 8

Definition at line 2022 of file stm8s.h.

Referenced by UART3_ReceiveData9().

#define UART3_CR1_T8 ((uint8_t)0x40)

Transmit data bit 8

Definition at line 2023 of file stm8s.h.

Referenced by UART3_SendData9().

#define UART3_CR1_UARTD ((uint8_t)0x20)

UART Disable (for low power consumption)

Definition at line 2024 of file stm8s.h.

Referenced by UART3_Cmd().

#define UART3_CR1_WAKE ((uint8_t)0x08)

Wake-up method mask

Definition at line 2026 of file stm8s.h.

Referenced by UART3_WakeUpConfig().

#define UART3_CR2_ILIEN ((uint8_t)0x10)

IDLE Line Interrupt Enable mask

Definition at line 2034 of file stm8s.h.

#define UART3_CR2_REN ((uint8_t)0x04)

Receiver Enable mask

Definition at line 2036 of file stm8s.h.

Referenced by UART3_Init().

#define UART3_CR2_RIEN ((uint8_t)0x20)

Receiver Interrupt Enable mask

Definition at line 2033 of file stm8s.h.

#define UART3_CR2_RWU ((uint8_t)0x02)

Receiver Wake-Up mask

Definition at line 2037 of file stm8s.h.

Referenced by UART3_ReceiverWakeUpCmd().

#define UART3_CR2_SBK ((uint8_t)0x01)

Send Break mask

Definition at line 2038 of file stm8s.h.

Referenced by UART3_SendBreak().

#define UART3_CR2_TCIEN ((uint8_t)0x40)

Transmission Complete Interrupt Enable mask

Definition at line 2032 of file stm8s.h.

#define UART3_CR2_TEN ((uint8_t)0x08)

Transmitter Enable mask

Definition at line 2035 of file stm8s.h.

Referenced by UART3_Init().

#define UART3_CR2_TIEN ((uint8_t)0x80)

Transmitter Interrupt Enable mask

Definition at line 2031 of file stm8s.h.

#define UART3_CR3_LINEN ((uint8_t)0x40)

Alternate Function output mask

Definition at line 2040 of file stm8s.h.

Referenced by UART3_LINCmd().

#define UART3_CR3_STOP ((uint8_t)0x30)

STOP bits [1:0] mask

Definition at line 2041 of file stm8s.h.

Referenced by UART3_Init().

#define UART3_CR4_ADD ((uint8_t)0x0F)

Address of the UART3 node mask

Definition at line 2046 of file stm8s.h.

Referenced by UART3_SetAddress().

#define UART3_CR4_LBDF ((uint8_t)0x10)

LIN Break Detection Flag mask

Definition at line 2045 of file stm8s.h.

Referenced by UART3_ClearFlag(), and UART3_ClearITPendingBit().

#define UART3_CR4_LBDIEN ((uint8_t)0x40)

LIN Break Detection Interrupt Enable mask

Definition at line 2043 of file stm8s.h.

#define UART3_CR4_LBDL ((uint8_t)0x20)

LIN Break Detection Length mask

Definition at line 2044 of file stm8s.h.

Referenced by UART3_LINBreakDetectionConfig().

#define UART3_CR6_LASE ((uint8_t)0x10)

LIN Auto synchronization Enable

Definition at line 2050 of file stm8s.h.

Referenced by UART3_LINConfig().

#define UART3_CR6_LDUM ((uint8_t)0x80)

LIN Divider Update Method

Definition at line 2048 of file stm8s.h.

Referenced by UART3_LINConfig().

#define UART3_CR6_LHDF ((uint8_t)0x02)

LIN Header Detection Flag

Definition at line 2052 of file stm8s.h.

Referenced by UART3_ClearFlag(), and UART3_ClearITPendingBit().

#define UART3_CR6_LHDIEN ((uint8_t)0x04)

LIN Header Detection Interrupt Enable

Definition at line 2051 of file stm8s.h.

#define UART3_CR6_LSF ((uint8_t)0x01)

LIN Synch Field

Definition at line 2053 of file stm8s.h.

Referenced by UART3_ClearFlag().

#define UART3_CR6_LSLV ((uint8_t)0x20)

LIN Slave Enable

Definition at line 2049 of file stm8s.h.

Referenced by UART3_LINConfig().

#define UART3_SR_FE ((uint8_t)0x02)

Framing Error mask

Definition at line 2014 of file stm8s.h.

#define UART3_SR_IDLE ((uint8_t)0x10)

IDLE line detected mask

Definition at line 2011 of file stm8s.h.

#define UART3_SR_NF ((uint8_t)0x04)

Noise Flag mask

Definition at line 2013 of file stm8s.h.

#define UART3_SR_OR ((uint8_t)0x08)

OverRun error mask

Definition at line 2012 of file stm8s.h.

#define UART3_SR_PE ((uint8_t)0x01)

Parity Error mask

Definition at line 2015 of file stm8s.h.

#define UART3_SR_RXNE ((uint8_t)0x20)

Read Data Register Not Empty mask

Definition at line 2010 of file stm8s.h.

Referenced by UART3_ClearFlag(), and UART3_ClearITPendingBit().

#define UART3_SR_TC ((uint8_t)0x40)

Transmission Complete mask

Definition at line 2009 of file stm8s.h.

#define UART3_SR_TXE ((uint8_t)0x80)

Transmit Data Register Empty mask

Definition at line 2008 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: CAN_Registers_Bits_Definition

Defines
CAN_Registers_Bits_Definition

Defines

#define | CAN_DGR_LBKM ((uint8_t)0x01)
#define | CAN_DGR_RX ((uint8_t)0x08)
#define | CAN_DGR_SAMP ((uint8_t)0x04)
#define | CAN_DGR_SLIM ((uint8_t)0x02)
#define | CAN_DGR_TXM2E ((uint8_t)0x10)
#define | CAN_EIER_BOFIE ((uint8_t)0x04)
#define | CAN_EIER_EPVIE ((uint8_t)0x02)
#define | CAN_EIER_ERRIE ((uint8_t)0x80)
#define | CAN_EIER_EWGIE ((uint8_t)0x01)
#define | CAN_EIER_LECIE ((uint8_t)0x10)
#define | CAN_ESR_BOFF ((uint8_t)0x04)
#define | CAN_ESR_EPVF ((uint8_t)0x02)
#define | CAN_ESR_EWGF ((uint8_t)0x01)
#define | CAN_ESR_LEC ((uint8_t)0x70)
#define | CAN_ESR_LEC0 ((uint8_t)0x10)
#define | CAN_ESR_LEC1 ((uint8_t)0x20)
#define | CAN_ESR_LEC2 ((uint8_t)0x40)
#define | CAN_FCR1_FACT0 ((uint8_t)0x01)
#define | CAN_FCR1_FACT1 ((uint8_t)0x10)
#define | CAN_FCR1_FSC00 ((uint8_t)0x02)
#define | CAN_FCR1_FSC01 ((uint8_t)0x04)
#define | CAN_FCR1_FSC10 ((uint8_t)0x20)
#define | CAN_FCR1_FSC11 ((uint8_t)0x40)
#define | CAN_FCR2_FACT2 ((uint8_t)0x01)
#define | CAN_FCR2_FACT3 ((uint8_t)0x10)
#define | CAN_FCR2_FSC20 ((uint8_t)0x02)
#define | CAN_FCR2_FSC21 ((uint8_t)0x04)
#define | CAN_FCR2_FSC30 ((uint8_t)0x20)
#define | CAN_FCR2_FSC31 ((uint8_t)0x40)
#define | CAN_FCR3_FACT4 ((uint8_t)0x01)
#define | CAN_FCR3_FACT5 ((uint8_t)0x10)
#define | CAN_FCR3_FSC40 ((uint8_t)0x02)
#define | CAN_FCR3_FSC41 ((uint8_t)0x04)
#define | CAN_FCR3_FSC50 ((uint8_t)0x20)
#define | CAN_FCR3_FSC51 ((uint8_t)0x40)
#define | CAN_FMR1_FMH0 ((uint8_t)0x02)
#define | CAN_FMR1_FMH1 ((uint8_t)0x08)
#define | CAN_FMR1_FMH2 ((uint8_t)0x20)
#define | CAN_FMR1_FMH3 ((uint8_t)0x80)
#define | CAN_FMR1_FML0 ((uint8_t)0x01)
#define | CAN_FMR1_FML1 ((uint8_t)0x04)
#define | CAN_FMR1_FML2 ((uint8_t)0x10)
#define | CAN_FMR1_FML3 ((uint8_t)0x40)
#define | CAN_FMR2_FMH4 ((uint8_t)0x02)
#define | CAN_FMR2_FMH5 ((uint8_t)0x08)
#define | CAN_FMR2_FML4 ((uint8_t)0x01)
#define | CAN_FMR2_FML5 ((uint8_t)0x04)
#define | CAN_IER_FFIE ((uint8_t)0x04)
#define | CAN_IER_FMPIE ((uint8_t)0x02)
#define | CAN_IER_FOVIE ((uint8_t)0x08)
#define | CAN_IER_TMEIE ((uint8_t)0x01)
#define | CAN_IER_WKUIE ((uint8_t)0x80)
#define | CAN_MCR_ABOM ((uint8_t)0x40)
#define | CAN_MCR_AWUM ((uint8_t)0x20)
#define | CAN_MCR_INRQ ((uint8_t)0x01)
#define | CAN_MCR_NART ((uint8_t)0x10)
#define | CAN_MCR_RFLM ((uint8_t)0x08)
#define | CAN_MCR_SLEEP ((uint8_t)0x02)
#define | CAN_MCR_TTCM ((uint8_t)0x80)
#define | CAN_MCR_TXFP ((uint8_t)0x04)
#define | CAN_MCSR_ABRQ ((uint8_t)0x02)
#define | CAN_MCSR_ALST ((uint8_t)0x10)
#define | CAN_MCSR_RQCP ((uint8_t)0x04)
#define | CAN_MCSR_TERR ((uint8_t)0x20)
#define | CAN_MCSR_TXOK ((uint8_t)0x08)
#define | CAN_MCSR_TXRQ ((uint8_t)0x01)
#define | CAN_MDLCR_DLC ((uint8_t)0x0F)
#define | CAN_MDLCR_TGT ((uint8_t)0x80)
#define | CAN_MIDR1_IDE ((uint8_t)0x40)
#define | CAN_MIDR1_RTR ((uint8_t)0x20)
#define | CAN_MSR_ERRI ((uint8_t)0x04)
#define | CAN_MSR_INAK ((uint8_t)0x01)
#define | CAN_MSR_RX ((uint8_t)0x20)
#define | CAN_MSR_SLAK ((uint8_t)0x02)
#define | CAN_MSR_TX ((uint8_t)0x10)
#define | CAN_MSR_WKUI ((uint8_t)0x08)
#define | CAN_PSR_PS0 ((uint8_t)0x01)
#define | CAN_PSR_PS1 ((uint8_t)0x02)
#define | CAN_PSR_PS2 ((uint8_t)0x04)
#define | CAN_RECR_REC0 ((uint8_t)0x01)
#define | CAN_RECR_REC1 ((uint8_t)0x02)
#define | CAN_RECR_REC2 ((uint8_t)0x04)
#define | CAN_RECR_REC3 ((uint8_t)0x08)
#define | CAN_RECR_REC4 ((uint8_t)0x10)
#define | CAN_RECR_REC5 ((uint8_t)0x20)
#define | CAN_RECR_REC6 ((uint8_t)0x40)
#define | CAN_RECR_REC7 ((uint8_t)0x80)
#define | CAN_RFR_FMP01 ((uint8_t)0x03)
#define | CAN_RFR_FOVR ((uint8_t)0x10)
#define | CAN_RFR_FULL ((uint8_t)0x08)
#define | CAN_RFR_RFOM ((uint8_t)0x20)
#define | CAN_TECR_TEC0 ((uint8_t)0x01)
#define | CAN_TECR_TEC1 ((uint8_t)0x02)
#define | CAN_TECR_TEC2 ((uint8_t)0x04)
#define | CAN_TECR_TEC3 ((uint8_t)0x08)
#define | CAN_TECR_TEC4 ((uint8_t)0x10)
#define | CAN_TECR_TEC5 ((uint8_t)0x20)
#define | CAN_TECR_TEC6 ((uint8_t)0x40)
#define | CAN_TECR_TEC7 ((uint8_t)0x80)
#define | CAN_TPR_CODE0 ((uint8_t)0x01)
#define | CAN_TPR_LOW0 ((uint8_t)0x20)
#define | CAN_TPR_LOW1 ((uint8_t)0x40)
#define | CAN_TPR_LOW2 ((uint8_t)0x80)
#define | CAN_TPR_TME0 ((uint8_t)0x04)
#define | CAN_TPR_TME1 ((uint8_t)0x08)
#define | CAN_TPR_TME2 ((uint8_t)0x10)
#define | CAN_TSR_RQCP0 ((uint8_t)0x01)
#define | CAN_TSR_RQCP012 ((uint8_t)0x07)
#define | CAN_TSR_RQCP1 ((uint8_t)0x02)
#define | CAN_TSR_RQCP2 ((uint8_t)0x04)
#define | CAN_TSR_TXOK0 ((uint8_t)0x10)
#define | CAN_TSR_TXOK1 ((uint8_t)0x20)
#define | CAN_TSR_TXOK2 ((uint8_t)0x40)

Define Documentation

#define CAN_DGR_LBKM ((uint8_t)0x01)

Definition at line 2383 of file stm8s.h.

#define CAN_DGR_RX ((uint8_t)0x08)

Definition at line 2386 of file stm8s.h.

#define CAN_DGR_SAMP ((uint8_t)0x04)

Definition at line 2385 of file stm8s.h.

#define CAN_DGR_SLIM ((uint8_t)0x02)

Definition at line 2384 of file stm8s.h.

#define CAN_DGR_TXM2E ((uint8_t)0x10)

Definition at line 2387 of file stm8s.h.

Referenced by CAN_ST7CompatibilityCmd().

#define CAN_EIER_BOFIE ((uint8_t)0x04)

Definition at line 2424 of file stm8s.h.

Referenced by CAN_GetITStatus().

#define CAN_EIER_EPVIE ((uint8_t)0x02)

Definition at line 2423 of file stm8s.h.

Referenced by CAN_GetITStatus().

#define CAN_EIER_ERRIE ((uint8_t)0x80)

Definition at line 2426 of file stm8s.h.

Referenced by CAN_GetITStatus().

#define CAN_EIER_EWGIE ((uint8_t)0x01)

Definition at line 2422 of file stm8s.h.

Referenced by CAN_GetITStatus().

#define CAN_EIER_LECIE ((uint8_t)0x10)

Definition at line 2425 of file stm8s.h.

Referenced by CAN_GetITStatus().

#define CAN_ESR_BOFF ((uint8_t)0x04)

Definition at line 2415 of file stm8s.h.

Referenced by CAN_GetITStatus().

#define CAN_ESR_EPVF ((uint8_t)0x02)

Definition at line 2414 of file stm8s.h.

Referenced by CAN_GetITStatus().

#define CAN_ESR_EWGF ((uint8_t)0x01)

Definition at line 2413 of file stm8s.h.

Referenced by CAN_GetITStatus().

#define CAN_ESR_LEC ((uint8_t)0x70)

Definition at line 2419 of file stm8s.h.

Referenced by CAN_GetITStatus(), and CAN_GetLastErrorCode().

#define CAN_ESR_LEC0 ((uint8_t)0x10)

Definition at line 2416 of file stm8s.h.

#define CAN_ESR_LEC1 ((uint8_t)0x20)

Definition at line 2417 of file stm8s.h.

#define CAN_ESR_LEC2 ((uint8_t)0x40)

Definition at line 2418 of file stm8s.h.

#define CAN_FCR1_FACT0 ((uint8_t)0x01)

Definition at line 2464 of file stm8s.h.

#define CAN_FCR1_FACT1 ((uint8_t)0x10)

Definition at line 2465 of file stm8s.h.

#define CAN_FCR1_FSC00 ((uint8_t)0x02)

Definition at line 2471 of file stm8s.h.

Referenced by CAN_FilterInit().

#define CAN_FCR1_FSC01 ((uint8_t)0x04)

Definition at line 2472 of file stm8s.h.

Referenced by CAN_FilterInit().

#define CAN_FCR1_FSC10 ((uint8_t)0x20)

Definition at line 2473 of file stm8s.h.

#define CAN_FCR1_FSC11 ((uint8_t)0x40)

Definition at line 2474 of file stm8s.h.

#define CAN_FCR2_FACT2 ((uint8_t)0x01)

Definition at line 2466 of file stm8s.h.

#define CAN_FCR2_FACT3 ((uint8_t)0x10)

Definition at line 2467 of file stm8s.h.

#define CAN_FCR2_FSC20 ((uint8_t)0x02)

Definition at line 2475 of file stm8s.h.

#define CAN_FCR2_FSC21 ((uint8_t)0x04)

Definition at line 2476 of file stm8s.h.

#define CAN_FCR2_FSC30 ((uint8_t)0x20)

Definition at line 2477 of file stm8s.h.

#define CAN_FCR2_FSC31 ((uint8_t)0x40)

Definition at line 2478 of file stm8s.h.

#define CAN_FCR3_FACT4 ((uint8_t)0x01)

Definition at line 2468 of file stm8s.h.

#define CAN_FCR3_FACT5 ((uint8_t)0x10)

Definition at line 2469 of file stm8s.h.

#define CAN_FCR3_FSC40 ((uint8_t)0x02)

Definition at line 2479 of file stm8s.h.

#define CAN_FCR3_FSC41 ((uint8_t)0x04)

Definition at line 2480 of file stm8s.h.

#define CAN_FCR3_FSC50 ((uint8_t)0x20)

Definition at line 2481 of file stm8s.h.

#define CAN_FCR3_FSC51 ((uint8_t)0x40)

Definition at line 2482 of file stm8s.h.

#define CAN_FMR1_FMH0 ((uint8_t)0x02)

Definition at line 2450 of file stm8s.h.

#define CAN_FMR1_FMH1 ((uint8_t)0x08)

Definition at line 2452 of file stm8s.h.

#define CAN_FMR1_FMH2 ((uint8_t)0x20)

Definition at line 2454 of file stm8s.h.

#define CAN_FMR1_FMH3 ((uint8_t)0x80)

Definition at line 2456 of file stm8s.h.

#define CAN_FMR1_FML0 ((uint8_t)0x01)

Definition at line 2449 of file stm8s.h.

#define CAN_FMR1_FML1 ((uint8_t)0x04)

Definition at line 2451 of file stm8s.h.

#define CAN_FMR1_FML2 ((uint8_t)0x10)

Definition at line 2453 of file stm8s.h.

#define CAN_FMR1_FML3 ((uint8_t)0x40)

Definition at line 2455 of file stm8s.h.

#define CAN_FMR2_FMH4 ((uint8_t)0x02)

Definition at line 2459 of file stm8s.h.

#define CAN_FMR2_FMH5 ((uint8_t)0x08)

Definition at line 2461 of file stm8s.h.

#define CAN_FMR2_FML4 ((uint8_t)0x01)

Definition at line 2458 of file stm8s.h.

#define CAN_FMR2_FML5 ((uint8_t)0x04)

Definition at line 2460 of file stm8s.h.

#define CAN_IER_FFIE ((uint8_t)0x04)

Definition at line 2377 of file stm8s.h.

Referenced by CAN_GetITStatus().

#define CAN_IER_FMPIE ((uint8_t)0x02)

Definition at line 2376 of file stm8s.h.

Referenced by CAN_GetITStatus().

#define CAN_IER_FOVIE ((uint8_t)0x08)

Definition at line 2378 of file stm8s.h.

Referenced by CAN_GetITStatus().

#define CAN_IER_TMEIE ((uint8_t)0x01)

Definition at line 2375 of file stm8s.h.

Referenced by CAN_GetITStatus().

#define CAN_IER_WKUIE ((uint8_t)0x80)

Definition at line 2379 of file stm8s.h.

Referenced by CAN_GetITStatus().

#define CAN_MCR_ABOM ((uint8_t)0x40)

Definition at line 2341 of file stm8s.h.

#define CAN_MCR_AWUM ((uint8_t)0x20)

Definition at line 2340 of file stm8s.h.

#define CAN_MCR_INRQ ((uint8_t)0x01)

Definition at line 2335 of file stm8s.h.

Referenced by CAN_DeInit(), CAN_Init(), CAN_OperatingModeRequest(), and CAN_Sleep().

#define CAN_MCR_NART ((uint8_t)0x10)

Definition at line 2339 of file stm8s.h.

#define CAN_MCR_RFLM ((uint8_t)0x08)

Definition at line 2338 of file stm8s.h.

#define CAN_MCR_SLEEP ((uint8_t)0x02)

Definition at line 2336 of file stm8s.h.

Referenced by CAN_OperatingModeRequest(), CAN_Sleep(), and CAN_WakeUp().

#define CAN_MCR_TTCM ((uint8_t)0x80)

Definition at line 2342 of file stm8s.h.

Referenced by CAN_TTComModeCmd().

#define CAN_MCR_TXFP ((uint8_t)0x04)

Definition at line 2337 of file stm8s.h.

#define CAN_MCSR_ABRQ ((uint8_t)0x02)

Definition at line 2397 of file stm8s.h.

Referenced by CAN_CancelTransmit().

#define CAN_MCSR_ALST ((uint8_t)0x10)

Definition at line 2400 of file stm8s.h.

#define CAN_MCSR_RQCP ((uint8_t)0x04)

Definition at line 2398 of file stm8s.h.

#define CAN_MCSR_TERR ((uint8_t)0x20)

Definition at line 2401 of file stm8s.h.

#define CAN_MCSR_TXOK ((uint8_t)0x08)

Definition at line 2399 of file stm8s.h.

#define CAN_MCSR_TXRQ ((uint8_t)0x01)

Definition at line 2396 of file stm8s.h.

Referenced by CAN_Transmit().

#define CAN_MDLCR_DLC ((uint8_t)0x0F)

Definition at line 2403 of file stm8s.h.

#define CAN_MDLCR_TGT ((uint8_t)0x80)

Definition at line 2404 of file stm8s.h.

Referenced by CAN_TTComModeCmd().

#define CAN_MIDR1_IDE ((uint8_t)0x40)

Definition at line 2407 of file stm8s.h.

#define CAN_MIDR1_RTR ((uint8_t)0x20)

Definition at line 2406 of file stm8s.h.

#define CAN_MSR_ERRI ((uint8_t)0x04)

Definition at line 2347 of file stm8s.h.

Referenced by CAN_ClearITPendingBit().

#define CAN_MSR_INAK ((uint8_t)0x01)

Definition at line 2345 of file stm8s.h.

Referenced by CAN_Init(), CAN_OperatingModeRequest(), and CAN_Sleep().

#define CAN_MSR_RX ((uint8_t)0x20)

Definition at line 2350 of file stm8s.h.

#define CAN_MSR_SLAK ((uint8_t)0x02)

Definition at line 2346 of file stm8s.h.

Referenced by CAN_OperatingModeRequest(), CAN_Sleep(), and CAN_WakeUp().

#define CAN_MSR_TX ((uint8_t)0x10)

Definition at line 2349 of file stm8s.h.

#define CAN_MSR_WKUI ((uint8_t)0x08)

Definition at line 2348 of file stm8s.h.

Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().

#define CAN_PSR_PS0 ((uint8_t)0x01)

Definition at line 2391 of file stm8s.h.

#define CAN_PSR_PS1 ((uint8_t)0x02)

Definition at line 2392 of file stm8s.h.

#define CAN_PSR_PS2 ((uint8_t)0x04)

Definition at line 2393 of file stm8s.h.

#define CAN_RECR_REC0 ((uint8_t)0x01)

Definition at line 2439 of file stm8s.h.

#define CAN_RECR_REC1 ((uint8_t)0x02)

Definition at line 2440 of file stm8s.h.

#define CAN_RECR_REC2 ((uint8_t)0x04)

Definition at line 2441 of file stm8s.h.

#define CAN_RECR_REC3 ((uint8_t)0x08)

Definition at line 2442 of file stm8s.h.

#define CAN_RECR_REC4 ((uint8_t)0x10)

Definition at line 2443 of file stm8s.h.

#define CAN_RECR_REC5 ((uint8_t)0x20)

Definition at line 2444 of file stm8s.h.

#define CAN_RECR_REC6 ((uint8_t)0x40)

Definition at line 2445 of file stm8s.h.

#define CAN_RECR_REC7 ((uint8_t)0x80)

Definition at line 2446 of file stm8s.h.

#define CAN_RFR_FMP01 ((uint8_t)0x03)

Definition at line 2369 of file stm8s.h.

Referenced by CAN_GetITStatus(), and CAN_MessagePending().

#define CAN_RFR_FOVR ((uint8_t)0x10)

Definition at line 2371 of file stm8s.h.

Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().

#define CAN_RFR_FULL ((uint8_t)0x08)

Definition at line 2370 of file stm8s.h.

Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().

#define CAN_RFR_RFOM ((uint8_t)0x20)

Definition at line 2372 of file stm8s.h.

Referenced by CAN_FIFORelease().

#define CAN_TECR_TEC0 ((uint8_t)0x01)

Definition at line 2429 of file stm8s.h.

#define CAN_TECR_TEC1 ((uint8_t)0x02)

Definition at line 2430 of file stm8s.h.

#define CAN_TECR_TEC2 ((uint8_t)0x04)

Definition at line 2431 of file stm8s.h.

#define CAN_TECR_TEC3 ((uint8_t)0x08)

Definition at line 2432 of file stm8s.h.

#define CAN_TECR_TEC4 ((uint8_t)0x10)

Definition at line 2433 of file stm8s.h.

#define CAN_TECR_TEC5 ((uint8_t)0x20)

Definition at line 2434 of file stm8s.h.

#define CAN_TECR_TEC6 ((uint8_t)0x40)

Definition at line 2435 of file stm8s.h.

#define CAN_TECR_TEC7 ((uint8_t)0x80)

Definition at line 2436 of file stm8s.h.

#define CAN_TPR_CODE0 ((uint8_t)0x01)

Definition at line 2361 of file stm8s.h.

#define CAN_TPR_LOW0 ((uint8_t)0x20)

Definition at line 2365 of file stm8s.h.

#define CAN_TPR_LOW1 ((uint8_t)0x40)

Definition at line 2366 of file stm8s.h.

#define CAN_TPR_LOW2 ((uint8_t)0x80)

Definition at line 2367 of file stm8s.h.

#define CAN_TPR_TME0 ((uint8_t)0x04)

Definition at line 2362 of file stm8s.h.

Referenced by CAN_Transmit(), and CAN_TransmitStatus().

#define CAN_TPR_TME1 ((uint8_t)0x08)

Definition at line 2363 of file stm8s.h.

Referenced by CAN_Transmit(), and CAN_TransmitStatus().

#define CAN_TPR_TME2 ((uint8_t)0x10)

Definition at line 2364 of file stm8s.h.

Referenced by CAN_Transmit(), and CAN_TransmitStatus().

#define CAN_TSR_RQCP0 ((uint8_t)0x01)

Definition at line 2353 of file stm8s.h.

Referenced by CAN_TransmitStatus().

#define CAN_TSR_RQCP012 ((uint8_t)0x07)

Definition at line 2356 of file stm8s.h.

Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().

#define CAN_TSR_RQCP1 ((uint8_t)0x02)

Definition at line 2354 of file stm8s.h.

Referenced by CAN_TransmitStatus().

#define CAN_TSR_RQCP2 ((uint8_t)0x04)

Definition at line 2355 of file stm8s.h.

Referenced by CAN_TransmitStatus().

#define CAN_TSR_TXOK0 ((uint8_t)0x10)

Definition at line 2357 of file stm8s.h.

Referenced by CAN_TransmitStatus().

#define CAN_TSR_TXOK1 ((uint8_t)0x20)

Definition at line 2358 of file stm8s.h.

Referenced by CAN_TransmitStatus().

#define CAN_TSR_TXOK2 ((uint8_t)0x40)

Definition at line 2359 of file stm8s.h.

Referenced by CAN_TransmitStatus().


STM8S/A Standard Peripherals Drivers: CAN_Registers_Reset_Value

Defines
CAN_Registers_Reset_Value

Defines

#define | CAN_BTR1_RESET_VALUE ((uint8_t)0x40)
#define | CAN_BTR2_RESET_VALUE ((uint8_t)0x23)
#define | CAN_DGR_RESET_VALUE ((uint8_t)0x0C)
#define | CAN_EIER_RESET_VALUE ((uint8_t)0x00)
#define | CAN_ESR_RESET_VALUE ((uint8_t)0x00)
#define | CAN_FCR_RESET_VALUE ((uint8_t)0x00)
#define | CAN_FMR1_RESET_VALUE ((uint8_t)0x00)
#define | CAN_FMR2_RESET_VALUE ((uint8_t)0x00)
#define | CAN_IER_RESET_VALUE ((uint8_t)0x00)
#define | CAN_MCR_RESET_VALUE ((uint8_t)0x02)
#define | CAN_MCSR_RESET_VALUE ((uint8_t)0x00)
#define | CAN_MDLC_RESET_VALUE ((uint8_t)0x00)
#define | CAN_MFMI_RESET_VALUE ((uint8_t)0x00)
#define | CAN_MSR_RESET_VALUE ((uint8_t)0x02)
#define | CAN_PSR_RESET_VALUE ((uint8_t)0x00)
#define | CAN_RECR_RESET_VALUE ((uint8_t)0x00)
#define | CAN_RFR_RESET_VALUE ((uint8_t)0x00)
#define | CAN_TECR_RESET_VALUE ((uint8_t)0x00)
#define | CAN_TPR_RESET_VALUE ((uint8_t)0x0C)
#define | CAN_TSR_RESET_VALUE ((uint8_t)0x00)

Define Documentation

#define CAN_BTR1_RESET_VALUE ((uint8_t)0x40)

Definition at line 2504 of file stm8s.h.

Referenced by CAN_DeInit().

#define CAN_BTR2_RESET_VALUE ((uint8_t)0x23)

Definition at line 2505 of file stm8s.h.

Referenced by CAN_DeInit().

#define CAN_DGR_RESET_VALUE ((uint8_t)0x0C)

Definition at line 2497 of file stm8s.h.

Referenced by CAN_DeInit().

#define CAN_EIER_RESET_VALUE ((uint8_t)0x00)

Definition at line 2501 of file stm8s.h.

Referenced by CAN_DeInit().

#define CAN_ESR_RESET_VALUE ((uint8_t)0x00)

Definition at line 2500 of file stm8s.h.

Referenced by CAN_ClearITPendingBit(), and CAN_DeInit().

#define CAN_FCR_RESET_VALUE ((uint8_t)0x00)

Definition at line 2508 of file stm8s.h.

Referenced by CAN_DeInit().

#define CAN_FMR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 2506 of file stm8s.h.

Referenced by CAN_DeInit().

#define CAN_FMR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 2507 of file stm8s.h.

Referenced by CAN_DeInit().

#define CAN_IER_RESET_VALUE ((uint8_t)0x00)

Definition at line 2496 of file stm8s.h.

Referenced by CAN_DeInit().

#define CAN_MCR_RESET_VALUE ((uint8_t)0x02)

Definition at line 2491 of file stm8s.h.

Referenced by CAN_DeInit().

#define CAN_MCSR_RESET_VALUE ((uint8_t)0x00)

Definition at line 2512 of file stm8s.h.

#define CAN_MDLC_RESET_VALUE ((uint8_t)0x00)

Definition at line 2511 of file stm8s.h.

Referenced by CAN_DeInit().

#define CAN_MFMI_RESET_VALUE ((uint8_t)0x00)

Definition at line 2510 of file stm8s.h.

#define CAN_MSR_RESET_VALUE ((uint8_t)0x02)

Definition at line 2492 of file stm8s.h.

Referenced by CAN_DeInit().

#define CAN_PSR_RESET_VALUE ((uint8_t)0x00)

Definition at line 2498 of file stm8s.h.

Referenced by CAN_DeInit().

#define CAN_RECR_RESET_VALUE ((uint8_t)0x00)

Definition at line 2503 of file stm8s.h.

#define CAN_RFR_RESET_VALUE ((uint8_t)0x00)

Definition at line 2495 of file stm8s.h.

Referenced by CAN_DeInit().

#define CAN_TECR_RESET_VALUE ((uint8_t)0x00)

Definition at line 2502 of file stm8s.h.

#define CAN_TPR_RESET_VALUE ((uint8_t)0x0C)

Definition at line 2494 of file stm8s.h.

#define CAN_TSR_RESET_VALUE ((uint8_t)0x00)

Definition at line 2493 of file stm8s.h.

Referenced by CAN_DeInit().


STM8S/A Standard Peripherals Drivers: CFG_Registers_Reset_Value

Defines
CFG_Registers_Reset_Value

Defines

#define CFG_GCR_RESET_VALUE ((uint8_t)0x00)

Define Documentation

#define CFG_GCR_RESET_VALUE ((uint8_t)0x00)

Definition at line 2532 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: CFG_Registers_Bits_Definition

Defines
CFG_Registers_Bits_Definition

Defines

#define | CFG_GCR_AL ((uint8_t)0x02)
#define | CFG_GCR_SWD ((uint8_t)0x01)

Define Documentation

#define CFG_GCR_AL ((uint8_t)0x02)

Activation Level bit mask

Definition at line 2543 of file stm8s.h.

#define CFG_GCR_SWD ((uint8_t)0x01)

Swim disable bit mask

Definition at line 2542 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: MAP_FILE_Base_Addresses

Defines
MAP_FILE_Base_Addresses

Defines

#define | ADC1_BaseAddress 0x53E0
#define | ADC2_BaseAddress 0x5400
#define | AWU_BaseAddress 0x50F0
#define | BEEP_BaseAddress 0x50F3
#define | CAN_BaseAddress 0x5420
#define | CFG_BaseAddress 0x7F60
#define | CLK_BaseAddress 0x50C0
#define | DM_BaseAddress 0x7F90
#define | EXTI_BaseAddress 0x50A0
#define | FLASH_BaseAddress 0x505A
#define | GPIOA_BaseAddress 0x5000
#define | GPIOB_BaseAddress 0x5005
#define | GPIOC_BaseAddress 0x500A
#define | GPIOD_BaseAddress 0x500F
#define | GPIOE_BaseAddress 0x5014
#define | GPIOF_BaseAddress 0x5019
#define | GPIOG_BaseAddress 0x501E
#define | GPIOH_BaseAddress 0x5023
#define | GPIOI_BaseAddress 0x5028
#define | I2C_BaseAddress 0x5210
#define | ITC_BaseAddress 0x7F70
#define | IWDG_BaseAddress 0x50E0
#define | OPT_BaseAddress 0x4800
#define | RST_BaseAddress 0x50B3
#define | SPI_BaseAddress 0x5200
#define | TIM1_BaseAddress 0x5250
#define | TIM2_BaseAddress 0x5300
#define | TIM3_BaseAddress 0x5320
#define | TIM4_BaseAddress 0x5340
#define | TIM5_BaseAddress 0x5300
#define | TIM6_BaseAddress 0x5340
#define | UART1_BaseAddress 0x5230
#define | UART2_BaseAddress 0x5240
#define | UART3_BaseAddress 0x5240
#define | UART4_BaseAddress 0x5230
#define | WWDG_BaseAddress 0x50D1

Define Documentation

#define ADC1_BaseAddress 0x53E0

Definition at line 2586 of file stm8s.h.

Referenced by ADC1_GetBufferValue().

#define ADC2_BaseAddress 0x5400

Definition at line 2587 of file stm8s.h.

#define AWU_BaseAddress 0x50F0

Definition at line 2572 of file stm8s.h.

#define BEEP_BaseAddress 0x50F3

Definition at line 2573 of file stm8s.h.

#define CAN_BaseAddress 0x5420

Definition at line 2588 of file stm8s.h.

#define CFG_BaseAddress 0x7F60

Definition at line 2589 of file stm8s.h.

#define CLK_BaseAddress 0x50C0

Definition at line 2569 of file stm8s.h.

#define DM_BaseAddress 0x7F90

Definition at line 2591 of file stm8s.h.

#define EXTI_BaseAddress 0x50A0

Definition at line 2567 of file stm8s.h.

#define FLASH_BaseAddress 0x505A

Definition at line 2566 of file stm8s.h.

#define GPIOA_BaseAddress 0x5000

Definition at line 2557 of file stm8s.h.

#define GPIOB_BaseAddress 0x5005

Definition at line 2558 of file stm8s.h.

#define GPIOC_BaseAddress 0x500A

Definition at line 2559 of file stm8s.h.

#define GPIOD_BaseAddress 0x500F

Definition at line 2560 of file stm8s.h.

#define GPIOE_BaseAddress 0x5014

Definition at line 2561 of file stm8s.h.

#define GPIOF_BaseAddress 0x5019

Definition at line 2562 of file stm8s.h.

#define GPIOG_BaseAddress 0x501E

Definition at line 2563 of file stm8s.h.

#define GPIOH_BaseAddress 0x5023

Definition at line 2564 of file stm8s.h.

#define GPIOI_BaseAddress 0x5028

Definition at line 2565 of file stm8s.h.

#define I2C_BaseAddress 0x5210

Definition at line 2575 of file stm8s.h.

#define ITC_BaseAddress 0x7F70

Definition at line 2590 of file stm8s.h.

#define IWDG_BaseAddress 0x50E0

Definition at line 2571 of file stm8s.h.

#define OPT_BaseAddress 0x4800

Definition at line 2556 of file stm8s.h.

#define RST_BaseAddress 0x50B3

Definition at line 2568 of file stm8s.h.

#define SPI_BaseAddress 0x5200

Definition at line 2574 of file stm8s.h.

#define TIM1_BaseAddress 0x5250

Definition at line 2580 of file stm8s.h.

#define TIM2_BaseAddress 0x5300

Definition at line 2581 of file stm8s.h.

#define TIM3_BaseAddress 0x5320

Definition at line 2582 of file stm8s.h.

#define TIM4_BaseAddress 0x5340

Definition at line 2583 of file stm8s.h.

#define TIM5_BaseAddress 0x5300

Definition at line 2584 of file stm8s.h.

#define TIM6_BaseAddress 0x5340

Definition at line 2585 of file stm8s.h.

#define UART1_BaseAddress 0x5230

Definition at line 2576 of file stm8s.h.

#define UART2_BaseAddress 0x5240

Definition at line 2577 of file stm8s.h.

#define UART3_BaseAddress 0x5240

Definition at line 2578 of file stm8s.h.

#define UART4_BaseAddress 0x5230

Definition at line 2579 of file stm8s.h.

#define WWDG_BaseAddress 0x50D1

Definition at line 2570 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: ADC1_Exported_Types

Enumerations
ADC1_Exported_Types

Enumerations

enum | ADC1_Align_TypeDef { ADC1_ALIGN_LEFT = (uint8_t)0x00, ADC1_ALIGN_RIGHT = (uint8_t)0x08 }
ADC1 data alignment. More...
enum ADC1_Channel_TypeDef {
ADC1_CHANNEL_0 = (uint8_t)0x00, ADC1_CHANNEL_1 = (uint8_t)0x01, ADC1_CHANNEL_2 = (uint8_t)0x02, ADC1_CHANNEL_3 = (uint8_t)0x03,
ADC1_CHANNEL_4 = (uint8_t)0x04, ADC1_CHANNEL_5 = (uint8_t)0x05, ADC1_CHANNEL_6 = (uint8_t)0x06, ADC1_CHANNEL_7 = (uint8_t)0x07,
ADC1_CHANNEL_8 = (uint8_t)0x08, ADC1_CHANNEL_9 = (uint8_t)0x09, ADC1_CHANNEL_12 = (uint8_t)0x0C
}
ADC1 analog channel selection. More...
enum | ADC1_ConvMode_TypeDef { ADC1_CONVERSIONMODE_SINGLE = (uint8_t)0x00, ADC1_CONVERSIONMODE_CONTINUOUS = (uint8_t)0x01 }
ADC1 conversion mode selection. More...
enum | ADC1_ExtTrig_TypeDef { ADC1_EXTTRIG_TIM = (uint8_t)0x00, ADC1_EXTTRIG_GPIO = (uint8_t)0x10 }
ADC1 External conversion trigger event selection. More...
enum ADC1_Flag_TypeDef {
ADC1_FLAG_OVR = (uint8_t)0x41, ADC1_FLAG_AWD = (uint8_t)0x40, ADC1_FLAG_AWS0 = (uint8_t)0x10, ADC1_FLAG_AWS1 = (uint8_t)0x11,
ADC1_FLAG_AWS2 = (uint8_t)0x12, ADC1_FLAG_AWS3 = (uint8_t)0x13, ADC1_FLAG_AWS4 = (uint8_t)0x14, ADC1_FLAG_AWS5 = (uint8_t)0x15,
ADC1_FLAG_AWS6 = (uint8_t)0x16, ADC1_FLAG_AWS7 = (uint8_t)0x17, ADC1_FLAG_AWS8 = (uint8_t)0x18, ADC1_FLAG_AWS9 = (uint8_t)0x19,
ADC1_FLAG_AWS12 = (uint8_t)0x1C, ADC1_FLAG_EOC = (uint8_t)0x80
}
ADC1 Flags. More...
enum ADC1_IT_TypeDef {
ADC1_IT_AWDIE = (uint16_t)0x010, ADC1_IT_EOCIE = (uint16_t)0x020, ADC1_IT_AWD = (uint16_t)0x140, ADC1_IT_AWS0 = (uint16_t)0x110,
ADC1_IT_AWS1 = (uint16_t)0x111, ADC1_IT_AWS2 = (uint16_t)0x112, ADC1_IT_AWS3 = (uint16_t)0x113, ADC1_IT_AWS4 = (uint16_t)0x114,
ADC1_IT_AWS5 = (uint16_t)0x115, ADC1_IT_AWS6 = (uint16_t)0x116, ADC1_IT_AWS7 = (uint16_t)0x117, ADC1_IT_AWS8 = (uint16_t)0x118,
ADC1_IT_AWS9 = (uint16_t)0x119, ADC1_IT_AWS12 = (uint16_t)0x11C, ADC1_IT_EOC = (uint16_t)0x080
}
ADC1 Interrupt source. More...
enum ADC1_PresSel_TypeDef {
ADC1_PRESSEL_FCPU_D2 = (uint8_t)0x00, ADC1_PRESSEL_FCPU_D3 = (uint8_t)0x10, ADC1_PRESSEL_FCPU_D4 = (uint8_t)0x20, ADC1_PRESSEL_FCPU_D6 = (uint8_t)0x30,
ADC1_PRESSEL_FCPU_D8 = (uint8_t)0x40, ADC1_PRESSEL_FCPU_D10 = (uint8_t)0x50, ADC1_PRESSEL_FCPU_D12 = (uint8_t)0x60, ADC1_PRESSEL_FCPU_D18 = (uint8_t)0x70
}
ADC1 clock prescaler selection. More...
enum ADC1_SchmittTrigg_TypeDef {
ADC1_SCHMITTTRIG_CHANNEL0 = (uint8_t)0x00, ADC1_SCHMITTTRIG_CHANNEL1 = (uint8_t)0x01, ADC1_SCHMITTTRIG_CHANNEL2 = (uint8_t)0x02, ADC1_SCHMITTTRIG_CHANNEL3 = (uint8_t)0x03,
ADC1_SCHMITTTRIG_CHANNEL4 = (uint8_t)0x04, ADC1_SCHMITTTRIG_CHANNEL5 = (uint8_t)0x05, ADC1_SCHMITTTRIG_CHANNEL6 = (uint8_t)0x06, ADC1_SCHMITTTRIG_CHANNEL7 = (uint8_t)0x07,
ADC1_SCHMITTTRIG_CHANNEL8 = (uint8_t)0x08, ADC1_SCHMITTTRIG_CHANNEL9 = (uint8_t)0x09, ADC1_SCHMITTTRIG_CHANNEL12 = (uint8_t)0x0C, ADC1_SCHMITTTRIG_ALL = (uint8_t)0xFF
}
ADC1 schmitt Trigger. More...

Enumeration Type Documentation

enum ADC1_Align_TypeDef

ADC1 data alignment.

Enumerator:
ADC1_ALIGN_LEFT

Data alignment left.

ADC1_ALIGN_RIGHT

Data alignment right.

Definition at line 68 of file stm8s_adc1.h.

enum ADC1_Channel_TypeDef

ADC1 analog channel selection.

Enumerator:
ADC1_CHANNEL_0

Analog channel 0.

ADC1_CHANNEL_1

Analog channel 1.

ADC1_CHANNEL_2

Analog channel 2.

ADC1_CHANNEL_3

Analog channel 3.

ADC1_CHANNEL_4

Analog channel 4.

ADC1_CHANNEL_5

Analog channel 5.

ADC1_CHANNEL_6

Analog channel 6.

ADC1_CHANNEL_7

Analog channel 7.

ADC1_CHANNEL_8

Analog channel 8.

ADC1_CHANNEL_9

Analog channel 9.

ADC1_CHANNEL_12

Analog channel 12.

Definition at line 155 of file stm8s_adc1.h.

enum ADC1_ConvMode_TypeDef

ADC1 conversion mode selection.

Enumerator:
ADC1_CONVERSIONMODE_SINGLE

Single conversion mode.

ADC1_CONVERSIONMODE_CONTINUOUS

Continuous conversion mode.

Definition at line 145 of file stm8s_adc1.h.

enum ADC1_ExtTrig_TypeDef

ADC1 External conversion trigger event selection.

Enumerator:
ADC1_EXTTRIG_TIM

Conversion from Internal TIM1 TRGO event.

ADC1_EXTTRIG_GPIO

Conversion from External interrupt on ADC_ETR pin.

Definition at line 59 of file stm8s_adc1.h.

enum ADC1_Flag_TypeDef

ADC1 Flags.

Enumerator:
ADC1_FLAG_OVR

Overrun status flag.

ADC1_FLAG_AWD

Analog WDG status.

ADC1_FLAG_AWS0

Analog channel 0 status.

ADC1_FLAG_AWS1

Analog channel 1 status.

ADC1_FLAG_AWS2

Analog channel 2 status.

ADC1_FLAG_AWS3

Analog channel 3 status.

ADC1_FLAG_AWS4

Analog channel 4 status.

ADC1_FLAG_AWS5

Analog channel 5 status.

ADC1_FLAG_AWS6

Analog channel 6 status.

ADC1_FLAG_AWS7

Analog channel 7 status.

ADC1_FLAG_AWS8

Analog channel 8 status.

ADC1_FLAG_AWS9

Analog channel 9 status.

ADC1_FLAG_AWS12

Analog channel 12 status.

ADC1_FLAG_EOC

EOC falg.

Definition at line 101 of file stm8s_adc1.h.

enum ADC1_IT_TypeDef

ADC1 Interrupt source.

Enumerator:
ADC1_IT_AWDIE

Analog WDG interrupt enable.

ADC1_IT_EOCIE

EOC interrupt enable.

ADC1_IT_AWD

Analog WDG status.

ADC1_IT_AWS0

Analog channel 0 status.

ADC1_IT_AWS1

Analog channel 1 status.

ADC1_IT_AWS2

Analog channel 2 status.

ADC1_IT_AWS3

Analog channel 3 status.

ADC1_IT_AWS4

Analog channel 4 status.

ADC1_IT_AWS5

Analog channel 5 status.

ADC1_IT_AWS6

Analog channel 6 status.

ADC1_IT_AWS7

Analog channel 7 status.

ADC1_IT_AWS8

Analog channel 8 status.

ADC1_IT_AWS9

Analog channel 9 status.

ADC1_IT_AWS12

Analog channel 12 status.

ADC1_IT_EOC

EOC pending bit.

Definition at line 77 of file stm8s_adc1.h.

enum ADC1_PresSel_TypeDef

ADC1 clock prescaler selection.

Enumerator:
ADC1_PRESSEL_FCPU_D2

Prescaler selection fADC1 = fcpu/2.

ADC1_PRESSEL_FCPU_D3

Prescaler selection fADC1 = fcpu/3.

ADC1_PRESSEL_FCPU_D4

Prescaler selection fADC1 = fcpu/4.

ADC1_PRESSEL_FCPU_D6

Prescaler selection fADC1 = fcpu/6.

ADC1_PRESSEL_FCPU_D8

Prescaler selection fADC1 = fcpu/8.

ADC1_PRESSEL_FCPU_D10

Prescaler selection fADC1 = fcpu/10.

ADC1_PRESSEL_FCPU_D12

Prescaler selection fADC1 = fcpu/12.

ADC1_PRESSEL_FCPU_D18

Prescaler selection fADC1 = fcpu/18.

Definition at line 44 of file stm8s_adc1.h.

enum ADC1_SchmittTrigg_TypeDef

ADC1 schmitt Trigger.

Enumerator:
ADC1_SCHMITTTRIG_CHANNEL0

Schmitt trigger disable on AIN0.

ADC1_SCHMITTTRIG_CHANNEL1

Schmitt trigger disable on AIN1.

ADC1_SCHMITTTRIG_CHANNEL2

Schmitt trigger disable on AIN2.

ADC1_SCHMITTTRIG_CHANNEL3

Schmitt trigger disable on AIN3.

ADC1_SCHMITTTRIG_CHANNEL4

Schmitt trigger disable on AIN4.

ADC1_SCHMITTTRIG_CHANNEL5

Schmitt trigger disable on AIN5.

ADC1_SCHMITTTRIG_CHANNEL6

Schmitt trigger disable on AIN6.

ADC1_SCHMITTTRIG_CHANNEL7

Schmitt trigger disable on AIN7.

ADC1_SCHMITTTRIG_CHANNEL8

Schmitt trigger disable on AIN8.

ADC1_SCHMITTTRIG_CHANNEL9

Schmitt trigger disable on AIN9.

ADC1_SCHMITTTRIG_CHANNEL12

Schmitt trigger disable on AIN12.

ADC1_SCHMITTTRIG_ALL

Schmitt trigger disable on All channels.

Definition at line 124 of file stm8s_adc1.h.


STM8S/A Standard Peripherals Drivers: ADC1_Private_Macros

Defines
ADC1_Private_Macros

Macros used by the assert function to check the different functions parameters. More...

Defines

#define | IS_ADC1_ALIGN_OK(ALIGN)
Macro used by the assert function to check the different alignment modes.
#define | IS_ADC1_BUFFER_OK(BUFFER) ((BUFFER) <= (uint8_t)0x09)
Macro used by the assert function to check the possible buffer values.
#define | IS_ADC1_CHANNEL_OK(CHANNEL)
Macro used by the assert function to check the different channels values.
#define | IS_ADC1_CONVERSIONMODE_OK(MODE)
Macro used by the assert function to check the different conversion modes.
#define | IS_ADC1_EXTTRIG_OK(EXTRIG)
Macro used by the assert function to check the different external trigger values.
#define | IS_ADC1_FLAG_OK(FLAG)
Macro used by the assert function to check the ADC1 Flag.
#define | IS_ADC1_IT_OK(IT)
Macro used by the assert function to check the Interrupt source.
#define | IS_ADC1_ITPENDINGBIT_OK(ITPENDINGBIT)
Macro used by the assert function to check the ADC1 pending bits.
#define | IS_ADC1_PRESSEL_OK(PRESCALER)
Macro used by the assert function to check the different prescaler's values.
#define | IS_ADC1_SCHMITTTRIG_OK(SCHMITTTRIG)
Macro used by the assert function to check the different schmitt trigger values.

Detailed Description

Macros used by the assert function to check the different functions parameters.

Define Documentation

#define IS_ADC1_ALIGN_OK ( ALIGN )
Value:
(((ALIGN) == ADC1_ALIGN_LEFT) || \
                                ((ALIGN) == ADC1_ALIGN_RIGHT))

Macro used by the assert function to check the different alignment modes.

Definition at line 207 of file stm8s_adc1.h.

Referenced by ADC1_ConversionConfig(), and ADC1_Init().

#define IS_ADC1_BUFFER_OK ( BUFFER ) ((BUFFER) <= (uint8_t)0x09)

Macro used by the assert function to check the possible buffer values.

Definition at line 290 of file stm8s_adc1.h.

Referenced by ADC1_GetBufferValue().

#define IS_ADC1_CHANNEL_OK ( CHANNEL )
Value:
(((CHANNEL) == ADC1_CHANNEL_0) || \
                                    ((CHANNEL) == ADC1_CHANNEL_1) || \
                                    ((CHANNEL) == ADC1_CHANNEL_2) || \
                                    ((CHANNEL) == ADC1_CHANNEL_3) || \
                                    ((CHANNEL) == ADC1_CHANNEL_4) || \
                                    ((CHANNEL) == ADC1_CHANNEL_5) || \
                                    ((CHANNEL) == ADC1_CHANNEL_6) || \
                                    ((CHANNEL) == ADC1_CHANNEL_7) || \
                                    ((CHANNEL) == ADC1_CHANNEL_8) || \
                                    ((CHANNEL) == ADC1_CHANNEL_12) || \
                                    ((CHANNEL) == ADC1_CHANNEL_9))

Macro used by the assert function to check the different channels values.

Definition at line 275 of file stm8s_adc1.h.

Referenced by ADC1_AWDChannelConfig(), ADC1_ConversionConfig(), ADC1_GetAWDChannelStatus(), and ADC1_Init().

#define IS_ADC1_CONVERSIONMODE_OK ( MODE )
Value:
(((MODE) == ADC1_CONVERSIONMODE_SINGLE) || \
                                        ((MODE) == ADC1_CONVERSIONMODE_CONTINUOUS))

Macro used by the assert function to check the different conversion modes.

Definition at line 269 of file stm8s_adc1.h.

Referenced by ADC1_ConversionConfig(), and ADC1_Init().

#define IS_ADC1_EXTTRIG_OK ( EXTRIG )
Value:
(((EXTRIG) == ADC1_EXTTRIG_TIM) || \
                                   ((EXTRIG) == ADC1_EXTTRIG_GPIO))

Macro used by the assert function to check the different external trigger values.

Definition at line 201 of file stm8s_adc1.h.

Referenced by ADC1_ExternalTriggerConfig(), and ADC1_Init().

#define IS_ADC1_FLAG_OK ( FLAG )
Value:
(((FLAG) == ADC1_FLAG_EOC)|| \
                              ((FLAG) == ADC1_FLAG_OVR) || \
                              ((FLAG) == ADC1_FLAG_AWD) || \
                              ((FLAG) == ADC1_FLAG_AWS0) || \
                              ((FLAG) == ADC1_FLAG_AWS1) || \
                              ((FLAG) == ADC1_FLAG_AWS2) || \
                              ((FLAG) == ADC1_FLAG_AWS3) || \
                              ((FLAG) == ADC1_FLAG_AWS4) || \
                              ((FLAG) == ADC1_FLAG_AWS5) || \
                              ((FLAG) == ADC1_FLAG_AWS6) || \
                              ((FLAG) == ADC1_FLAG_AWS7) || \
                              ((FLAG) == ADC1_FLAG_AWS8) || \
                              ((FLAG) == ADC1_FLAG_AWS9))

Macro used by the assert function to check the ADC1 Flag.

Definition at line 219 of file stm8s_adc1.h.

Referenced by ADC1_ClearFlag(), and ADC1_GetFlagStatus().

#define IS_ADC1_IT_OK ( IT )
Value:
(((IT) == ADC1_IT_EOCIE) || \
                          ((IT) == ADC1_IT_AWDIE))

Macro used by the assert function to check the Interrupt source.

Definition at line 213 of file stm8s_adc1.h.

Referenced by ADC1_ITConfig().

#define IS_ADC1_ITPENDINGBIT_OK ( ITPENDINGBIT )
Value:
(((ITPENDINGBIT) == ADC1_IT_EOC) || \
    ((ITPENDINGBIT) == ADC1_IT_AWD) || \
    ((ITPENDINGBIT) == ADC1_IT_AWS0) || \
    ((ITPENDINGBIT) == ADC1_IT_AWS1) || \
    ((ITPENDINGBIT) == ADC1_IT_AWS2) || \
    ((ITPENDINGBIT) == ADC1_IT_AWS3) || \
    ((ITPENDINGBIT) == ADC1_IT_AWS4) || \
    ((ITPENDINGBIT) == ADC1_IT_AWS5) || \
    ((ITPENDINGBIT) == ADC1_IT_AWS6) || \
    ((ITPENDINGBIT) == ADC1_IT_AWS7) || \
    ((ITPENDINGBIT) == ADC1_IT_AWS8) || \
    ((ITPENDINGBIT) == ADC1_IT_AWS12) || \
    ((ITPENDINGBIT) == ADC1_IT_AWS9))

Macro used by the assert function to check the ADC1 pending bits.

Definition at line 236 of file stm8s_adc1.h.

Referenced by ADC1_ClearITPendingBit(), and ADC1_GetITStatus().

#define IS_ADC1_PRESSEL_OK ( PRESCALER )
Value:
(((PRESCALER) == ADC1_PRESSEL_FCPU_D2) || \
                                      ((PRESCALER) == ADC1_PRESSEL_FCPU_D3) || \
                                      ((PRESCALER) == ADC1_PRESSEL_FCPU_D4) || \
                                      ((PRESCALER) == ADC1_PRESSEL_FCPU_D6) || \
                                      ((PRESCALER) == ADC1_PRESSEL_FCPU_D8) || \
                                      ((PRESCALER) == ADC1_PRESSEL_FCPU_D10) || \
                                      ((PRESCALER) == ADC1_PRESSEL_FCPU_D12) || \
                                      ((PRESCALER) == ADC1_PRESSEL_FCPU_D18))

Macro used by the assert function to check the different prescaler's values.

Definition at line 189 of file stm8s_adc1.h.

Referenced by ADC1_Init(), and ADC1_PrescalerConfig().

#define IS_ADC1_SCHMITTTRIG_OK ( SCHMITTTRIG )
Value:
(((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL0) || \
    ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL1) || \
    ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL2) || \
    ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL3) || \
    ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL4) || \
    ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL5) || \
    ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL6) || \
    ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL7) || \
    ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL8) || \
    ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL12) || \
    ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_ALL) || \
    ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL9))

Macro used by the assert function to check the different schmitt trigger values.

Definition at line 253 of file stm8s_adc1.h.

Referenced by ADC1_Init(), and ADC1_SchmittTriggerConfig().


STM8S/A Standard Peripherals Drivers: ADC1_Exported_Functions

Functions
ADC1_Exported_Functions

Functions

void | ADC1_AWDChannelConfig (ADC1_Channel_TypeDef Channel, FunctionalState NewState)
Enables or disables the analog watchdog for the given channel.
void | ADC1_ClearFlag (ADC1_Flag_TypeDef Flag)
Clear the specified ADC1 Flag.
void | ADC1_ClearITPendingBit (ADC1_IT_TypeDef ITPendingBit)
Clear the ADC1 End of Conversion pending bit.
void | ADC1_Cmd (FunctionalState NewState)
Enables or Disables the ADC1 peripheral.
void | ADC1_ConversionConfig (ADC1_ConvMode_TypeDef ADC1_ConversionMode, ADC1_Channel_TypeDef ADC1_Channel, ADC1_Align_TypeDef ADC1_Align)
Configure the ADC1 conversion on selected channel.
void | ADC1_DataBufferCmd (FunctionalState NewState)
Enables or Disables the ADC1 data store into the Data Buffer registers rather than in the Data Register.
void | ADC1_DeInit (void)
Deinitializes the ADC1 peripheral registers to their default reset values.
void | ADC1_ExternalTriggerConfig (ADC1_ExtTrig_TypeDef ADC1_ExtTrigger, FunctionalState NewState)
Configure the ADC1 conversion on external trigger event.
FlagStatus | ADC1_GetAWDChannelStatus (ADC1_Channel_TypeDef Channel)
Checks the specified analog watchdog channel status.
uint16_t | ADC1_GetBufferValue (uint8_t Buffer)
Get one sample of measured signal.
uint16_t | ADC1_GetConversionValue (void)
Get one sample of measured signal.
FlagStatus | ADC1_GetFlagStatus (ADC1_Flag_TypeDef Flag)
Checks the specified ADC1 flag status.
ITStatus | ADC1_GetITStatus (ADC1_IT_TypeDef ITPendingBit)
Returns the specified pending bit status.
void | ADC1_Init (ADC1_ConvMode_TypeDef ADC1_ConversionMode, ADC1_Channel_TypeDef ADC1_Channel, ADC1_PresSel_TypeDef ADC1_PrescalerSelection, ADC1_ExtTrig_TypeDef ADC1_ExtTrigger, FunctionalState ADC1_ExtTriggerState, ADC1_Align_TypeDef ADC1_Align, ADC1_SchmittTrigg_TypeDef ADC1_SchmittTriggerChannel, FunctionalState ADC1_SchmittTriggerState)
Initializes the ADC1 peripheral according to the specified parameters.
void | ADC1_ITConfig (ADC1_IT_TypeDef ADC1_IT, FunctionalState NewState)
Enables or disables the ADC1 interrupt.
void | ADC1_PrescalerConfig (ADC1_PresSel_TypeDef ADC1_Prescaler)
Configure the ADC1 prescaler division factor.
void | ADC1_ScanModeCmd (FunctionalState NewState)
Enables or Disables the ADC1 scan mode.
void | ADC1_SchmittTriggerConfig (ADC1_SchmittTrigg_TypeDef ADC1_SchmittTriggerChannel, FunctionalState NewState)
Enables or disables the ADC1 Schmitt Trigger on a selected channel.
void | ADC1_SetHighThreshold (uint16_t Threshold)
Sets the high threshold of the analog watchdog.
void | ADC1_SetLowThreshold (uint16_t Threshold)
Sets the low threshold of the analog watchdog.
void | ADC1_StartConversion (void)
Start ADC1 conversion.

Function Documentation

void ADC1_AWDChannelConfig | ( | ADC1_Channel_TypeDef | Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the analog watchdog for the given channel.

Parameters:
Channel | specifies the desired Channel. It can be set of the values of ADC1_Channel_TypeDef.
NewState | specifies the analog watchdog new state. can have one of the values of FunctionalState.
Return values:
None

Definition at line 405 of file stm8s_adc1.c.

References DISABLE, IS_ADC1_CHANNEL_OK, and IS_FUNCTIONALSTATE_OK.

void ADC1_ClearFlag ( ADC1_Flag_TypeDef Flag )

Clear the specified ADC1 Flag.

Parameters:
Flag,: ADC1 flag. can be one of the values of ADC1_Flag_TypeDef.
Return values:
None

Definition at line 567 of file stm8s_adc1.c.

References IS_ADC1_FLAG_OK.

void ADC1_ClearITPendingBit ( ADC1_IT_TypeDef ITPendingBit )

Clear the ADC1 End of Conversion pending bit.

Parameters:
ITPendingBit : the IT pending bit to clear. This parameter can be one of the following values:
  • ADC1_IT_AWD : Analog WDG IT status
  • ADC1_IT_AWS0 : Analog channel 0 IT status
  • ADC1_IT_AWS1 : Analog channel 1 IT status
  • ADC1_IT_AWS2 : Analog channel 2 IT status
  • ADC1_IT_AWS3 : Analog channel 3 IT status
  • ADC1_IT_AWS4 : Analog channel 4 IT status
  • ADC1_IT_AWS5 : Analog channel 5 IT status
  • ADC1_IT_AWS6 : Analog channel 6 IT status
  • ADC1_IT_AWS7 : Analog channel 7 IT status
  • ADC1_IT_AWS8 : Analog channel 8 IT status
  • ADC1_IT_AWS9 : Analog channel 9 IT status
  • ADC1_IT_EOC : EOC pending bit
Return values:
None

Definition at line 662 of file stm8s_adc1.c.

References IS_ADC1_ITPENDINGBIT_OK.

void ADC1_Cmd ( FunctionalState NewState )

Enables or Disables the ADC1 peripheral.

Parameters:
NewState,: specifies the peripheral enabled or disabled state.
Return values:
None

Definition at line 126 of file stm8s_adc1.c.

References DISABLE, and IS_FUNCTIONALSTATE_OK.

void ADC1_ConversionConfig | ( | ADC1_ConvMode_TypeDef | ADC1_ConversionMode,
 |  | ADC1_Channel_TypeDef | ADC1_Channel,
 |  | ADC1_Align_TypeDef | ADC1_Align
 | ) |  |

Configure the ADC1 conversion on selected channel.

Parameters:
ADC1_ConversionMode | Specifies the conversion type. It can be set of the values of ADC1_ConvMode_TypeDef
ADC1_Channel | specifies the ADC1 Channel. It can be set of the values of ADC1_Channel_TypeDef
ADC1_Align | specifies the converted data alignment. It can be set of the values of ADC1_Align_TypeDef
Return values:
None

Definition at line 286 of file stm8s_adc1.c.

References ADC1_CONVERSIONMODE_CONTINUOUS, IS_ADC1_ALIGN_OK, IS_ADC1_CHANNEL_OK, and IS_ADC1_CONVERSIONMODE_OK.

Referenced by ADC1_Init().

void ADC1_DataBufferCmd ( FunctionalState NewState )

Enables or Disables the ADC1 data store into the Data Buffer registers rather than in the Data Register.

Parameters:
NewState,: specifies the selected mode enabled or disabled state.
Return values:
None

Definition at line 166 of file stm8s_adc1.c.

References DISABLE, and IS_FUNCTIONALSTATE_OK.

void ADC1_DeInit ( void )

Deinitializes the ADC1 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 52 of file stm8s_adc1.c.

void ADC1_ExternalTriggerConfig | ( | ADC1_ExtTrig_TypeDef | ADC1_ExtTrigger,
 |  | FunctionalState | NewState
 | ) |  |

Configure the ADC1 conversion on external trigger event.

Full description:
The selected external trigger event can be enabled or disabled.
Parameters:
ADC1_ExtTrigger | to select the External trigger event. can have one of the values of ADC1_ExtTrig_TypeDef.
NewState | to enable/disable the selected external trigger can have one of the values of FunctionalState.
Return values:
None

Definition at line 325 of file stm8s_adc1.c.

References DISABLE, IS_ADC1_EXTTRIG_OK, and IS_FUNCTIONALSTATE_OK.

Referenced by ADC1_Init().

FlagStatus ADC1_GetAWDChannelStatus ( ADC1_Channel_TypeDef Channel )

Checks the specified analog watchdog channel status.

Parameters:
Channel,: specify the channel of which to check the analog watchdog can be one of the values of ADC1_Channel_TypeDef.
Return values:
FlagStatus Status of the analog watchdog.

Definition at line 502 of file stm8s_adc1.c.

References IS_ADC1_CHANNEL_OK.

uint16_t ADC1_GetBufferValue ( uint8_t Buffer )

Get one sample of measured signal.

Parameters:
Buffer specifies the buffer to read.
Return values:
BufferValue,: value read from the given buffer.
Required preconditions:
ADC1 conversion finished.

Definition at line 466 of file stm8s_adc1.c.

References ADC1_BaseAddress, and IS_ADC1_BUFFER_OK.

uint16_t ADC1_GetConversionValue ( void )

Get one sample of measured signal.

Parameters:
None
Return values:
ConversionValue,: value of the measured signal.
Required preconditions:
ADC1 conversion finished.

Definition at line 370 of file stm8s_adc1.c.

FlagStatus ADC1_GetFlagStatus ( ADC1_Flag_TypeDef Flag )

Checks the specified ADC1 flag status.

Parameters:
Flag,: ADC1 flag. can be one of the values of ADC1_Flag_TypeDef.
Return values:
FlagStatus Status of the ADC1 flag.

Definition at line 527 of file stm8s_adc1.c.

References IS_ADC1_FLAG_OK.

ITStatus ADC1_GetITStatus ( ADC1_IT_TypeDef ITPendingBit )

Returns the specified pending bit status.

Parameters:
ITPendingBit : the IT pending bit to check. This parameter can be one of the following values:
  • ADC1_IT_AWD : Analog WDG IT status
  • ADC1_IT_AWS0 : Analog channel 0 IT status
  • ADC1_IT_AWS1 : Analog channel 1 IT status
  • ADC1_IT_AWS2 : Analog channel 2 IT status
  • ADC1_IT_AWS3 : Analog channel 3 IT status
  • ADC1_IT_AWS4 : Analog channel 4 IT status
  • ADC1_IT_AWS5 : Analog channel 5 IT status
  • ADC1_IT_AWS6 : Analog channel 6 IT status
  • ADC1_IT_AWS7 : Analog channel 7 IT status
  • ADC1_IT_AWS8 : Analog channel 8 IT status
  • ADC1_IT_AWS9 : Analog channel 9 IT status
  • ADC1_IT_EOC : EOC pending bit
Return values:
ITStatus,: status of the specified pending bit.

Definition at line 616 of file stm8s_adc1.c.

References IS_ADC1_ITPENDINGBIT_OK, and RESET.

void ADC1_Init | ( | ADC1_ConvMode_TypeDef | ADC1_ConversionMode,
 |  | ADC1_Channel_TypeDef | ADC1_Channel,
 |  | ADC1_PresSel_TypeDef | ADC1_PrescalerSelection,
 |  | ADC1_ExtTrig_TypeDef | ADC1_ExtTrigger,
 |  | FunctionalState | ADC1_ExtTriggerState,
 |  | ADC1_Align_TypeDef | ADC1_Align,
 |  | ADC1_SchmittTrigg_TypeDef | ADC1_SchmittTriggerChannel,
 |  | FunctionalState | ADC1_SchmittTriggerState
 | ) |  |

Initializes the ADC1 peripheral according to the specified parameters.

Parameters:
ADC1_ConversionMode,: specifies the conversion mode can be one of the values of ADC1_ConvMode_TypeDef.
ADC1_Channel,: specifies the channel to convert can be one of the values of ADC1_Channel_TypeDef.
ADC1_PrescalerSelection,: specifies the ADC1 prescaler can be one of the values of ADC1_PresSel_TypeDef.
ADC1_ExtTrigger,: specifies the external trigger can be one of the values of ADC1_ExtTrig_TypeDef.
ADC1_ExtTriggerState,: specifies the external trigger new state can be one of the values of FunctionalState.
ADC1_Align,: specifies the converted data alignment can be one of the values of ADC1_Align_TypeDef.
ADC1_SchmittTriggerChannel,: specifies the schmitt trigger channel can be one of the values of ADC1_SchmittTrigg_TypeDef.
ADC1_SchmittTriggerState,: specifies the schmitt trigger state can be one of the values of FunctionalState.
Return values:
None

Definition at line 88 of file stm8s_adc1.c.

References ADC1_ConversionConfig(), ADC1_ExternalTriggerConfig(), ADC1_PrescalerConfig(), ADC1_SchmittTriggerConfig(), IS_ADC1_ALIGN_OK, IS_ADC1_CHANNEL_OK, IS_ADC1_CONVERSIONMODE_OK, IS_ADC1_EXTTRIG_OK, IS_ADC1_PRESSEL_OK, IS_ADC1_SCHMITTTRIG_OK, and IS_FUNCTIONALSTATE_OK.

void ADC1_ITConfig | ( | ADC1_IT_TypeDef | ADC1_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the ADC1 interrupt.

Parameters:
ADC1_IT specifies the name of the interrupt to enable or disable. This parameter can be one of the following values:
  • ADC1_IT_AWDITEN : Analog WDG interrupt enable
  • ADC1_IT_EOCITEN : EOC iterrupt enable
NewState specifies the state of the interrupt to apply.
Return values:
None

Definition at line 190 of file stm8s_adc1.c.

References DISABLE, IS_ADC1_IT_OK, and IS_FUNCTIONALSTATE_OK.

void ADC1_PrescalerConfig ( ADC1_PresSel_TypeDef ADC1_Prescaler )

Configure the ADC1 prescaler division factor.

Parameters:
ADC1_Prescaler,: the selected precaler. It can be one of the values of ADC1_PresSel_TypeDef.
Return values:
None

Definition at line 214 of file stm8s_adc1.c.

References IS_ADC1_PRESSEL_OK.

Referenced by ADC1_Init().

void ADC1_ScanModeCmd ( FunctionalState NewState )

Enables or Disables the ADC1 scan mode.

Parameters:
NewState,: specifies the selected mode enabled or disabled state.
Return values:
None

Definition at line 146 of file stm8s_adc1.c.

References DISABLE, and IS_FUNCTIONALSTATE_OK.

void ADC1_SchmittTriggerConfig | ( | ADC1_SchmittTrigg_TypeDef | ADC1_SchmittTriggerChannel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the ADC1 Schmitt Trigger on a selected channel.

Parameters:
ADC1_SchmittTriggerChannel | specifies the desired Channel. It can be set of the values of ADC1_SchmittTrigg_TypeDef.
NewState | specifies Channel new status. can have one of the values of FunctionalState.
Return values:
None

Definition at line 233 of file stm8s_adc1.c.

References ADC1_SCHMITTTRIG_ALL, ADC1_SCHMITTTRIG_CHANNEL8, DISABLE, IS_ADC1_SCHMITTTRIG_OK, and IS_FUNCTIONALSTATE_OK.

Referenced by ADC1_Init().

void ADC1_SetHighThreshold ( uint16_t Threshold )

Sets the high threshold of the analog watchdog.

Parameters:
Threshold specifies the high threshold value. this value depends on the reference voltage range.
Return values:
None

Definition at line 441 of file stm8s_adc1.c.

void ADC1_SetLowThreshold ( uint16_t Threshold )

Sets the low threshold of the analog watchdog.

Parameters:
Threshold specifies the low threshold value. this value depends on the reference voltage range.
Return values:
None

Definition at line 453 of file stm8s_adc1.c.

void ADC1_StartConversion ( void )

Start ADC1 conversion.

Full description:
This function triggers the start of conversion, after ADC1 configuration.
Parameters:
None
Return values:
None
Required preconditions:
Enable the ADC1 peripheral before calling this function

Definition at line 358 of file stm8s_adc1.c.


STM8S/A Standard Peripherals Drivers: ADC2_Exported_Types

Enumerations
ADC2_Exported_Types

Enumerations

enum | ADC2_Align_TypeDef { ADC2_ALIGN_LEFT = (uint8_t)0x00, ADC2_ALIGN_RIGHT = (uint8_t)0x08 }
ADC2 data alignment. More...
enum ADC2_Channel_TypeDef {
ADC2_CHANNEL_0 = (uint8_t)0x00, ADC2_CHANNEL_1 = (uint8_t)0x01, ADC2_CHANNEL_2 = (uint8_t)0x02, ADC2_CHANNEL_3 = (uint8_t)0x03,
ADC2_CHANNEL_4 = (uint8_t)0x04, ADC2_CHANNEL_5 = (uint8_t)0x05, ADC2_CHANNEL_6 = (uint8_t)0x06, ADC2_CHANNEL_7 = (uint8_t)0x07,
ADC2_CHANNEL_8 = (uint8_t)0x08, ADC2_CHANNEL_9 = (uint8_t)0x09, ADC2_CHANNEL_10 = (uint8_t)0x0A, ADC2_CHANNEL_11 = (uint8_t)0x0B,
ADC2_CHANNEL_12 = (uint8_t)0x0C, ADC2_CHANNEL_13 = (uint8_t)0x0D, ADC2_CHANNEL_14 = (uint8_t)0x0E, ADC2_CHANNEL_15 = (uint8_t)0x0F
}
ADC2 analog channel selection. More...
enum | ADC2_ConvMode_TypeDef { ADC2_CONVERSIONMODE_SINGLE = (uint8_t)0x00, ADC2_CONVERSIONMODE_CONTINUOUS = (uint8_t)0x01 }
ADC2 conversion mode selection. More...
enum | ADC2_ExtTrig_TypeDef { ADC2_EXTTRIG_TIM = (uint8_t)0x00, ADC2_EXTTRIG_GPIO = (uint8_t)0x01 }
ADC2 External conversion trigger event selection. More...
enum ADC2_PresSel_TypeDef {
ADC2_PRESSEL_FCPU_D2 = (uint8_t)0x00, ADC2_PRESSEL_FCPU_D3 = (uint8_t)0x10, ADC2_PRESSEL_FCPU_D4 = (uint8_t)0x20, ADC2_PRESSEL_FCPU_D6 = (uint8_t)0x30,
ADC2_PRESSEL_FCPU_D8 = (uint8_t)0x40, ADC2_PRESSEL_FCPU_D10 = (uint8_t)0x50, ADC2_PRESSEL_FCPU_D12 = (uint8_t)0x60, ADC2_PRESSEL_FCPU_D18 = (uint8_t)0x70
}
ADC2 clock prescaler selection. More...
enum ADC2_SchmittTrigg_TypeDef {
ADC2_SCHMITTTRIG_CHANNEL0 = (uint8_t)0x00, ADC2_SCHMITTTRIG_CHANNEL1 = (uint8_t)0x01, ADC2_SCHMITTTRIG_CHANNEL2 = (uint8_t)0x02, ADC2_SCHMITTTRIG_CHANNEL3 = (uint8_t)0x03,
ADC2_SCHMITTTRIG_CHANNEL4 = (uint8_t)0x04, ADC2_SCHMITTTRIG_CHANNEL5 = (uint8_t)0x05, ADC2_SCHMITTTRIG_CHANNEL6 = (uint8_t)0x06, ADC2_SCHMITTTRIG_CHANNEL7 = (uint8_t)0x07,
ADC2_SCHMITTTRIG_CHANNEL8 = (uint8_t)0x08, ADC2_SCHMITTTRIG_CHANNEL9 = (uint8_t)0x09, ADC2_SCHMITTTRIG_CHANNEL10 = (uint8_t)0x0A, ADC2_SCHMITTTRIG_CHANNEL11 = (uint8_t)0x0B,
ADC2_SCHMITTTRIG_CHANNEL12 = (uint8_t)0x0C, ADC2_SCHMITTTRIG_CHANNEL13 = (uint8_t)0x0D, ADC2_SCHMITTTRIG_CHANNEL14 = (uint8_t)0x0E, ADC2_SCHMITTTRIG_CHANNEL15 = (uint8_t)0x0F,
ADC2_SCHMITTTRIG_ALL = (uint8_t)0x1F
}
ADC2 schmitt Trigger. More...

Enumeration Type Documentation

enum ADC2_Align_TypeDef

ADC2 data alignment.

Enumerator:
ADC2_ALIGN_LEFT

Data alignment left.

ADC2_ALIGN_RIGHT

Data alignment right.

Definition at line 68 of file stm8s_adc2.h.

enum ADC2_Channel_TypeDef

ADC2 analog channel selection.

Enumerator:
ADC2_CHANNEL_0

Analog channel 0.

ADC2_CHANNEL_1

Analog channel 1.

ADC2_CHANNEL_2

Analog channel 2.

ADC2_CHANNEL_3

Analog channel 3.

ADC2_CHANNEL_4

Analog channel 4.

ADC2_CHANNEL_5

Analog channel 5.

ADC2_CHANNEL_6

Analog channel 6.

ADC2_CHANNEL_7

Analog channel 7.

ADC2_CHANNEL_8

Analog channel 8.

ADC2_CHANNEL_9

Analog channel 9.

ADC2_CHANNEL_10

Analog channel 10.

ADC2_CHANNEL_11

Analog channel 11.

ADC2_CHANNEL_12

Analog channel 12.

ADC2_CHANNEL_13

Analog channel 13.

ADC2_CHANNEL_14

Analog channel 14.

ADC2_CHANNEL_15

Analog channel 15.

Definition at line 110 of file stm8s_adc2.h.

enum ADC2_ConvMode_TypeDef

ADC2 conversion mode selection.

Enumerator:
ADC2_CONVERSIONMODE_SINGLE

Single conversion mode.

ADC2_CONVERSIONMODE_CONTINUOUS

Continuous conversion mode.

Definition at line 101 of file stm8s_adc2.h.

enum ADC2_ExtTrig_TypeDef

ADC2 External conversion trigger event selection.

Enumerator:
ADC2_EXTTRIG_TIM

Conversion from Internal TIM TRGO event.

ADC2_EXTTRIG_GPIO

Conversion from External interrupt on ADC_ETR pin.

Definition at line 60 of file stm8s_adc2.h.

enum ADC2_PresSel_TypeDef

ADC2 clock prescaler selection.

Enumerator:
ADC2_PRESSEL_FCPU_D2

Prescaler selection fADC2 = fcpu/2.

ADC2_PRESSEL_FCPU_D3

Prescaler selection fADC2 = fcpu/3.

ADC2_PRESSEL_FCPU_D4

Prescaler selection fADC2 = fcpu/4.

ADC2_PRESSEL_FCPU_D6

Prescaler selection fADC2 = fcpu/6.

ADC2_PRESSEL_FCPU_D8

Prescaler selection fADC2 = fcpu/8.

ADC2_PRESSEL_FCPU_D10

Prescaler selection fADC2 = fcpu/10.

ADC2_PRESSEL_FCPU_D12

Prescaler selection fADC2 = fcpu/12.

ADC2_PRESSEL_FCPU_D18

Prescaler selection fADC2 = fcpu/18.

Definition at line 46 of file stm8s_adc2.h.

enum ADC2_SchmittTrigg_TypeDef

ADC2 schmitt Trigger.

Enumerator:
ADC2_SCHMITTTRIG_CHANNEL0

Schmitt trigger disable on AIN0.

ADC2_SCHMITTTRIG_CHANNEL1

Schmitt trigger disable on AIN1.

ADC2_SCHMITTTRIG_CHANNEL2

Schmitt trigger disable on AIN2.

ADC2_SCHMITTTRIG_CHANNEL3

Schmitt trigger disable on AIN3.

ADC2_SCHMITTTRIG_CHANNEL4

Schmitt trigger disable on AIN4.

ADC2_SCHMITTTRIG_CHANNEL5

Schmitt trigger disable on AIN5.

ADC2_SCHMITTTRIG_CHANNEL6

Schmitt trigger disable on AIN6.

ADC2_SCHMITTTRIG_CHANNEL7

Schmitt trigger disable on AIN7.

ADC2_SCHMITTTRIG_CHANNEL8

Schmitt trigger disable on AIN8.

ADC2_SCHMITTTRIG_CHANNEL9

Schmitt trigger disable on AIN9.

ADC2_SCHMITTTRIG_CHANNEL10

Schmitt trigger disable on AIN10.

ADC2_SCHMITTTRIG_CHANNEL11

Schmitt trigger disable on AIN11.

ADC2_SCHMITTTRIG_CHANNEL12

Schmitt trigger disable on AIN12.

ADC2_SCHMITTTRIG_CHANNEL13

Schmitt trigger disable on AIN13.

ADC2_SCHMITTTRIG_CHANNEL14

Schmitt trigger disable on AIN14.

ADC2_SCHMITTTRIG_CHANNEL15

Schmitt trigger disable on AIN15.

ADC2_SCHMITTTRIG_ALL

Schmitt trigger disable on all channels.

Definition at line 76 of file stm8s_adc2.h.


STM8S/A Standard Peripherals Drivers: ADC2_Private_Macros

Defines
ADC2_Private_Macros

Macros used by the assert function to check the different functions parameters. More...

Defines

#define | IS_ADC2_ALIGN_OK(ALIGN)
Macro used by the assert function to check the different alignment modes.
#define | IS_ADC2_CHANNEL_OK(CHANNEL)
Macro used by the assert function to check the different channels values.
#define | IS_ADC2_CONVERSIONMODE_OK(MODE)
Macro used by the assert function to check the different conversion modes.
#define | IS_ADC2_EXTTRIG_OK(EXTRIG)
Macro used by the assert function to check the different external trigger values.
#define | IS_ADC2_PRESSEL_OK(PRESCALER)
Macro used by the assert function to check the different prescaler's values.
#define | IS_ADC2_SCHMITTTRIG_OK(SCHMITTTRIG)
Macro used by the assert function to check the different schmitt trigger values.

Detailed Description

Macros used by the assert function to check the different functions parameters.

Define Documentation

#define IS_ADC2_ALIGN_OK ( ALIGN )
Value:
(((ALIGN) == ADC2_ALIGN_LEFT) || \
                                ((ALIGN) == ADC2_ALIGN_RIGHT))

Macro used by the assert function to check the different alignment modes.

Definition at line 165 of file stm8s_adc2.h.

Referenced by ADC2_ConversionConfig(), and ADC2_Init().

#define IS_ADC2_CHANNEL_OK ( CHANNEL )
Value:
(((CHANNEL) == ADC2_CHANNEL_0) || \
                                    ((CHANNEL) == ADC2_CHANNEL_1) || \
                                    ((CHANNEL) == ADC2_CHANNEL_2) || \
                                    ((CHANNEL) == ADC2_CHANNEL_3) || \
                                    ((CHANNEL) == ADC2_CHANNEL_4) || \
                                    ((CHANNEL) == ADC2_CHANNEL_5) || \
                                    ((CHANNEL) == ADC2_CHANNEL_6) || \
                                    ((CHANNEL) == ADC2_CHANNEL_7) || \
                                    ((CHANNEL) == ADC2_CHANNEL_8) || \
                                    ((CHANNEL) == ADC2_CHANNEL_9) || \
                                    ((CHANNEL) == ADC2_CHANNEL_10) || \
                                    ((CHANNEL) == ADC2_CHANNEL_11) || \
                                    ((CHANNEL) == ADC2_CHANNEL_12) || \
                                    ((CHANNEL) == ADC2_CHANNEL_13) || \
                                    ((CHANNEL) == ADC2_CHANNEL_14) || \
                                    ((CHANNEL) == ADC2_CHANNEL_15))

Macro used by the assert function to check the different channels values.

Definition at line 199 of file stm8s_adc2.h.

Referenced by ADC2_ConversionConfig(), and ADC2_Init().

#define IS_ADC2_CONVERSIONMODE_OK ( MODE )
Value:
(((MODE) == ADC2_CONVERSIONMODE_SINGLE) || \
                                        ((MODE) == ADC2_CONVERSIONMODE_CONTINUOUS))

Macro used by the assert function to check the different conversion modes.

Definition at line 193 of file stm8s_adc2.h.

Referenced by ADC2_ConversionConfig(), and ADC2_Init().

#define IS_ADC2_EXTTRIG_OK ( EXTRIG )
Value:
(((EXTRIG) == ADC2_EXTTRIG_TIM) || \
                                                                   ((EXTRIG) == ADC2_EXTTRIG_GPIO))

Macro used by the assert function to check the different external trigger values.

Definition at line 159 of file stm8s_adc2.h.

Referenced by ADC2_ExternalTriggerConfig(), and ADC2_Init().

#define IS_ADC2_PRESSEL_OK ( PRESCALER )
Value:
(((PRESCALER) == ADC2_PRESSEL_FCPU_D2) || \
                                      ((PRESCALER) == ADC2_PRESSEL_FCPU_D3) || \
                                      ((PRESCALER) == ADC2_PRESSEL_FCPU_D4) || \
                                      ((PRESCALER) == ADC2_PRESSEL_FCPU_D6) || \
                                      ((PRESCALER) == ADC2_PRESSEL_FCPU_D8) || \
                                      ((PRESCALER) == ADC2_PRESSEL_FCPU_D10) || \
                                      ((PRESCALER) == ADC2_PRESSEL_FCPU_D12) || \
                                      ((PRESCALER) == ADC2_PRESSEL_FCPU_D18))

Macro used by the assert function to check the different prescaler's values.

Definition at line 147 of file stm8s_adc2.h.

Referenced by ADC2_Init(), and ADC2_PrescalerConfig().

#define IS_ADC2_SCHMITTTRIG_OK ( SCHMITTTRIG )
Value:
(((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL0) || \
    ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL1) || \
    ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL2) || \
    ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL3) || \
    ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL4) || \
    ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL5) || \
    ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL6) || \
    ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL7) || \
    ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL8) || \
    ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL9) || \
    ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL10) || \
    ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL11) || \
    ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL12) || \
    ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL13) || \
    ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL14) || \
    ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL15) || \
    ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_ALL))

Macro used by the assert function to check the different schmitt trigger values.

Definition at line 172 of file stm8s_adc2.h.

Referenced by ADC2_Init(), and ADC2_SchmittTriggerConfig().


STM8S/A Standard Peripherals Drivers: ADC2_Exported_Functions

Functions
ADC2_Exported_Functions

Functions

void | ADC2_ClearFlag (void)
Clear the ADC2 EOC Flag.
void | ADC2_ClearITPendingBit (void)
Clear the ADC2 End of Conversion pending bit.
void | ADC2_Cmd (FunctionalState NewState)
Enables or Disables the ADC2 peripheral.
void | ADC2_ConversionConfig (ADC2_ConvMode_TypeDef ADC2_ConversionMode, ADC2_Channel_TypeDef ADC2_Channel, ADC2_Align_TypeDef ADC2_Align)
Configure the ADC2 conversion on selected channel.
void | ADC2_DeInit (void)
Deinitializes the ADC2 peripheral registers to their default reset values.
void | ADC2_ExternalTriggerConfig (ADC2_ExtTrig_TypeDef ADC2_ExtTrigger, FunctionalState NewState)
Configure the ADC2 conversion on external trigger event.
uint16_t | ADC2_GetConversionValue (void)
Get one sample of measured signal.
FlagStatus | ADC2_GetFlagStatus (void)
Checks the ADC2 EOC flag status.
ITStatus | ADC2_GetITStatus (void)
Returns the EOC pending bit status.
void | ADC2_Init (ADC2_ConvMode_TypeDef ADC2_ConversionMode, ADC2_Channel_TypeDef ADC2_Channel, ADC2_PresSel_TypeDef ADC2_PrescalerSelection, ADC2_ExtTrig_TypeDef ADC2_ExtTrigger, FunctionalState ADC2_ExtTriggerState, ADC2_Align_TypeDef ADC2_Align, ADC2_SchmittTrigg_TypeDef ADC2_SchmittTriggerChannel, FunctionalState ADC2_SchmittTriggerState)
Initializes the ADC2 peripheral according to the specified parameters.
void | ADC2_ITConfig (FunctionalState NewState)
Enables or disables the ADC2 interrupt.
void | ADC2_PrescalerConfig (ADC2_PresSel_TypeDef ADC2_Prescaler)
Configure the ADC2 prescaler division factor.
void | ADC2_SchmittTriggerConfig (ADC2_SchmittTrigg_TypeDef ADC2_SchmittTriggerChannel, FunctionalState NewState)
Enables or disables the ADC2 Schmitt Trigger on a selected channel.
void | ADC2_StartConversion (void)
Start ADC2 conversion.

Function Documentation

void ADC2_ClearFlag ( void )

Clear the ADC2 EOC Flag.

Parameters:
None
Return values:
None

Definition at line 363 of file stm8s_adc2.c.

void ADC2_ClearITPendingBit ( void )

Clear the ADC2 End of Conversion pending bit.

Parameters:
None
Return values:
None

Definition at line 384 of file stm8s_adc2.c.

void ADC2_Cmd ( FunctionalState NewState )

Enables or Disables the ADC2 peripheral.

Parameters:
NewState,: specifies the peripheral enabled or disabled state.
Return values:
None

Definition at line 121 of file stm8s_adc2.c.

References DISABLE, and IS_FUNCTIONALSTATE_OK.

void ADC2_ConversionConfig | ( | ADC2_ConvMode_TypeDef | ADC2_ConversionMode,
 |  | ADC2_Channel_TypeDef | ADC2_Channel,
 |  | ADC2_Align_TypeDef | ADC2_Align
 | ) |  |

Configure the ADC2 conversion on selected channel.

Parameters:
ADC2_ConversionMode | Specifies the conversion type. It can be set of the values of ADC2_ConvMode_TypeDef
ADC2_Channel | specifies the ADC2 Channel. It can be set of the values of ADC2_Channel_TypeDef
ADC2_Align | specifies the converted data alignment. It can be set of the values of ADC2_Align_TypeDef
Return values:
None

Definition at line 236 of file stm8s_adc2.c.

References ADC2_CONVERSIONMODE_CONTINUOUS, IS_ADC2_ALIGN_OK, IS_ADC2_CHANNEL_OK, and IS_ADC2_CONVERSIONMODE_OK.

Referenced by ADC2_Init().

void ADC2_DeInit ( void )

Deinitializes the ADC2 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 54 of file stm8s_adc2.c.

void ADC2_ExternalTriggerConfig | ( | ADC2_ExtTrig_TypeDef | ADC2_ExtTrigger,
 |  | FunctionalState | NewState
 | ) |  |

Configure the ADC2 conversion on external trigger event.

Full description:
The selected external trigger event can be enabled or disabled.
Parameters:
ADC2_ExtTrigger | to select the External trigger event. can have one of the values of ADC2_ExtTrig_TypeDef.
NewState | to enable/disable the selected external trigger can have one of the values of FunctionalState.
Return values:
None

Definition at line 275 of file stm8s_adc2.c.

References DISABLE, IS_ADC2_EXTTRIG_OK, and IS_FUNCTIONALSTATE_OK.

Referenced by ADC2_Init().

uint16_t ADC2_GetConversionValue ( void )

Get one sample of measured signal.

Parameters:
None
Return values:
ConversionValue,: value of the measured signal.
Required preconditions:
ADC2 conversion finished.

Definition at line 320 of file stm8s_adc2.c.

FlagStatus ADC2_GetFlagStatus ( void )

Checks the ADC2 EOC flag status.

Parameters:
None
Return values:
FlagStatus Status of the ADC2 EOC flag.

Definition at line 352 of file stm8s_adc2.c.

ITStatus ADC2_GetITStatus ( void )

Returns the EOC pending bit status.

Parameters:
None
Return values:
FlagStatus,: status of the EOC pending bit.

Definition at line 374 of file stm8s_adc2.c.

void ADC2_Init | ( | ADC2_ConvMode_TypeDef | ADC2_ConversionMode,
 |  | ADC2_Channel_TypeDef | ADC2_Channel,
 |  | ADC2_PresSel_TypeDef | ADC2_PrescalerSelection,
 |  | ADC2_ExtTrig_TypeDef | ADC2_ExtTrigger,
 |  | FunctionalState | ADC2_ExtTriggerState,
 |  | ADC2_Align_TypeDef | ADC2_Align,
 |  | ADC2_SchmittTrigg_TypeDef | ADC2_SchmittTriggerChannel,
 |  | FunctionalState | ADC2_SchmittTriggerState
 | ) |  |

Initializes the ADC2 peripheral according to the specified parameters.

Parameters:
ADC2_ConversionMode,: specifies the conversion mode can be one of the values of ADC2_ConvMode_TypeDef.
ADC2_Channel,: specifies the channel to convert can be one of the values of ADC2_Channel_TypeDef.
ADC2_PrescalerSelection,: specifies the ADC2 prescaler can be one of the values of ADC2_PresSel_TypeDef.
ADC2_ExtTrigger,: specifies the external trigger can be one of the values of ADC2_ExtTrig_TypeDef.
ADC2_ExtTriggerState,: specifies the external trigger new state can be one of the values of FunctionalState.
ADC2_Align,: specifies the converted data alignment can be one of the values of ADC2_Align_TypeDef.
ADC2_SchmittTriggerChannel,: specifies the schmitt trigger channel can be one of the values of ADC2_SchmittTrigg_TypeDef.
ADC2_SchmittTriggerState,: specifies the schmitt trigger state can be one of the values of FunctionalState.
Return values:
None

Definition at line 83 of file stm8s_adc2.c.

References ADC2_ConversionConfig(), ADC2_ExternalTriggerConfig(), ADC2_PrescalerConfig(), ADC2_SchmittTriggerConfig(), IS_ADC2_ALIGN_OK, IS_ADC2_CHANNEL_OK, IS_ADC2_CONVERSIONMODE_OK, IS_ADC2_EXTTRIG_OK, IS_ADC2_PRESSEL_OK, IS_ADC2_SCHMITTTRIG_OK, and IS_FUNCTIONALSTATE_OK.

void ADC2_ITConfig ( FunctionalState NewState )

Enables or disables the ADC2 interrupt.

Parameters:
NewState specifies the state of ADC2 interrupt.
Return values:
None

Definition at line 141 of file stm8s_adc2.c.

References DISABLE, and IS_FUNCTIONALSTATE_OK.

void ADC2_PrescalerConfig ( ADC2_PresSel_TypeDef ADC2_Prescaler )

Configure the ADC2 prescaler division factor.

Parameters:
ADC2_Prescaler,: the selected prescaler. It can be one of the values of ADC2_PresSel_TypeDef.
Return values:
None

Definition at line 164 of file stm8s_adc2.c.

References IS_ADC2_PRESSEL_OK.

Referenced by ADC2_Init().

void ADC2_SchmittTriggerConfig | ( | ADC2_SchmittTrigg_TypeDef | ADC2_SchmittTriggerChannel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the ADC2 Schmitt Trigger on a selected channel.

Parameters:
ADC2_SchmittTriggerChannel | specifies the desired Channel. It can be set of the values of ADC2_SchmittTrigg_TypeDef.
NewState | specifies the Channel ADC2 Schmitt Trigger new status. can have one of the values of FunctionalState.
Return values:
None

Definition at line 183 of file stm8s_adc2.c.

References ADC2_SCHMITTTRIG_ALL, ADC2_SCHMITTTRIG_CHANNEL8, DISABLE, IS_ADC2_SCHMITTTRIG_OK, and IS_FUNCTIONALSTATE_OK.

Referenced by ADC2_Init().

void ADC2_StartConversion ( void )

Start ADC2 conversion.

Full description:
This function triggers the start of conversion, after ADC2 configuration.
Parameters:
None
Return values:
None
Required preconditions:
Enable the ADC2 peripheral before calling this function

Definition at line 308 of file stm8s_adc2.c.


STM8S/A Standard Peripherals Drivers: AWU_Exported_Types

Enumerations
AWU_Exported_Types

Enumerations

enum AWU_Timebase_TypeDef {
AWU_TIMEBASE_NO_IT = (uint8_t)0, AWU_TIMEBASE_250US = (uint8_t)1, AWU_TIMEBASE_500US = (uint8_t)2, AWU_TIMEBASE_1MS = (uint8_t)3,
AWU_TIMEBASE_2MS = (uint8_t)4, AWU_TIMEBASE_4MS = (uint8_t)5, AWU_TIMEBASE_8MS = (uint8_t)6, AWU_TIMEBASE_16MS = (uint8_t)7,
AWU_TIMEBASE_32MS = (uint8_t)8, AWU_TIMEBASE_64MS = (uint8_t)9, AWU_TIMEBASE_128MS = (uint8_t)10, AWU_TIMEBASE_256MS = (uint8_t)11,
AWU_TIMEBASE_512MS = (uint8_t)12, AWU_TIMEBASE_1S = (uint8_t)13, AWU_TIMEBASE_2S = (uint8_t)14, AWU_TIMEBASE_12S = (uint8_t)15,
AWU_TIMEBASE_30S = (uint8_t)16
}
AWU TimeBase selection. More...

Enumeration Type Documentation

enum AWU_Timebase_TypeDef

AWU TimeBase selection.

Enumerator:
AWU_TIMEBASE_NO_IT

No AWU interrupt selected

AWU_TIMEBASE_250US

AWU Timebase equals 0.25 ms

AWU_TIMEBASE_500US

AWU Timebase equals 0.5 ms

AWU_TIMEBASE_1MS

AWU Timebase equals 1 ms

AWU_TIMEBASE_2MS

AWU Timebase equals 2 ms

AWU_TIMEBASE_4MS

AWU Timebase equals 4 ms

AWU_TIMEBASE_8MS

AWU Timebase equals 8 ms

AWU_TIMEBASE_16MS

AWU Timebase equals 16 ms

AWU_TIMEBASE_32MS

AWU Timebase equals 32 ms

AWU_TIMEBASE_64MS

AWU Timebase equals 64 ms

AWU_TIMEBASE_128MS

AWU Timebase equals 128 ms

AWU_TIMEBASE_256MS

AWU Timebase equals 256 ms

AWU_TIMEBASE_512MS

AWU Timebase equals 512 ms

AWU_TIMEBASE_1S

AWU Timebase equals 1 s

AWU_TIMEBASE_2S

AWU Timebase equals 2 s

AWU_TIMEBASE_12S

AWU Timebase equals 12 s

AWU_TIMEBASE_30S

AWU Timebase equals 30 s

Definition at line 45 of file stm8s_awu.h.


STM8S/A Standard Peripherals Drivers: AWU_Exported_Constants

Defines
AWU_Exported_Constants

Defines

#define | LSI_FREQUENCY_MAX ((uint32_t)150000)
#define | LSI_FREQUENCY_MIN ((uint32_t)110000)

Define Documentation

#define LSI_FREQUENCY_MAX ((uint32_t)150000)

LSI maximum value in Hertz

Definition at line 77 of file stm8s_awu.h.

#define LSI_FREQUENCY_MIN ((uint32_t)110000)

LSI minimum value in Hertz

Definition at line 76 of file stm8s_awu.h.


STM8S/A Standard Peripherals Drivers: AWU_Private_Macros

Defines
AWU_Private_Macros

Defines

#define | IS_AWU_TIMEBASE_OK(TB)
Macro used by the assert function to check the different functions parameters.
#define | IS_LSI_FREQUENCY_OK(FREQ)
Macro used by the assert function to check the LSI frequency (in Hz)

Define Documentation

#define IS_AWU_TIMEBASE_OK ( TB )
Value:
(((TB) == AWU_TIMEBASE_NO_IT) || \
   ((TB) == AWU_TIMEBASE_250US) || \
   ((TB) == AWU_TIMEBASE_500US) || \
   ((TB) == AWU_TIMEBASE_1MS)   || \
   ((TB) == AWU_TIMEBASE_2MS)   || \
   ((TB) == AWU_TIMEBASE_4MS)   || \
   ((TB) == AWU_TIMEBASE_8MS)   || \
   ((TB) == AWU_TIMEBASE_16MS)  || \
   ((TB) == AWU_TIMEBASE_32MS)  || \
   ((TB) == AWU_TIMEBASE_64MS)  || \
   ((TB) == AWU_TIMEBASE_128MS) || \
   ((TB) == AWU_TIMEBASE_256MS) || \
   ((TB) == AWU_TIMEBASE_512MS) || \
   ((TB) == AWU_TIMEBASE_1S)    || \
   ((TB) == AWU_TIMEBASE_2S)    || \
   ((TB) == AWU_TIMEBASE_12S)   || \
   ((TB) == AWU_TIMEBASE_30S))

Macro used by the assert function to check the different functions parameters.

Macro used by the assert function to check the AWU timebases

Definition at line 98 of file stm8s_awu.h.

Referenced by AWU_Init().

#define IS_LSI_FREQUENCY_OK ( FREQ )
Value:
(((FREQ) >= LSI_FREQUENCY_MIN) && \
   ((FREQ) <= LSI_FREQUENCY_MAX))

Macro used by the assert function to check the LSI frequency (in Hz)

Definition at line 120 of file stm8s_awu.h.

Referenced by AWU_LSICalibrationConfig(), and BEEP_LSICalibrationConfig().


STM8S/A Standard Peripherals Drivers: AWU_Exported_Functions

Functions
AWU_Exported_Functions

Functions

void | AWU_Cmd (FunctionalState NewState)
Enable or disable the AWU peripheral.
void | AWU_DeInit (void)
Deinitializes the AWU peripheral registers to their default reset values.
FlagStatus | AWU_GetFlagStatus (void)
Returns status of the AWU peripheral flag.
void | AWU_IdleModeEnable (void)
Configures AWU in Idle mode to reduce power consumption.
void | AWU_Init (AWU_Timebase_TypeDef AWU_TimeBase)
Initializes the AWU peripheral according to the specified parameters.
void | AWU_LSICalibrationConfig (uint32_t LSIFreqHz)
Update APR register with the measured LSI frequency.

Function Documentation

void AWU_Cmd ( FunctionalState NewState )

Enable or disable the AWU peripheral.

Parameters:
NewState Indicates the new state of the AWU peripheral.
Return values:
None
Required preconditions:
Initialisation of AWU and LS RC calibration must be done before.

Definition at line 112 of file stm8s_awu.c.

References AWU, AWU_CSR_AWUEN, and DISABLE.

void AWU_DeInit ( void )

Deinitializes the AWU peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 73 of file stm8s_awu.c.

References AWU, AWU_APR_RESET_VALUE, AWU_CSR_RESET_VALUE, and AWU_TBR_RESET_VALUE.

FlagStatus AWU_GetFlagStatus ( void )

Returns status of the AWU peripheral flag.

Parameters:
None
Return values:
FlagStatus : Status of the AWU flag. This parameter can be any of the FlagStatus enumeration.

Definition at line 183 of file stm8s_awu.c.

References AWU, AWU_CSR_AWUF, RESET, and SET.

void AWU_IdleModeEnable ( void )

Configures AWU in Idle mode to reduce power consumption.

Parameters:
None
Return values:
None

Definition at line 168 of file stm8s_awu.c.

References AWU, AWU_CSR_AWUEN, and AWU_TBR_AWUTB.

void AWU_Init ( AWU_Timebase_TypeDef AWU_TimeBase )

Initializes the AWU peripheral according to the specified parameters.

Parameters:
AWU_TimeBase : Time base selection (interval between AWU interrupts). can be one of the values of AWU_Timebase_TypeDef.
Return values:
None
Required preconditions:
The LS RC calibration must be performed before calling this function.

Definition at line 88 of file stm8s_awu.c.

References APR_Array, AWU, AWU_APR_APR, AWU_CSR_AWUEN, AWU_TBR_AWUTB, IS_AWU_TIMEBASE_OK, and TBR_Array.

void AWU_LSICalibrationConfig ( uint32_t LSIFreqHz )

Update APR register with the measured LSI frequency.

Note on the APR calculation:
A is the integer part of lsifreqkhz/4 and x the decimal part. x <= A/(1+2A) is equivalent to A >= x(1+2A) and also to 4A >= 4x(1+2A) [F1] but we know that A + x = lsifreqkhz/4 ==> 4x = lsifreqkhz-4A so [F1] can be written : 4A >= (lsifreqkhz-4A)(1+2A)
Parameters:
LSIFreqHz Low Speed RC frequency measured by timer (in Hz).
Return values:
None
Required preconditions:
  • AWU must be disabled to avoid unwanted interrupts.

Definition at line 139 of file stm8s_awu.c.

References AWU, and IS_LSI_FREQUENCY_OK.


STM8S/A Standard Peripherals Drivers: BEEP_Exported_Types

Enumerations
BEEP_Exported_Types

Enumerations

enum BEEP_Frequency_TypeDef { BEEP_FREQUENCY_1KHZ = (uint8_t)0x00, BEEP_FREQUENCY_2KHZ = (uint8_t)0x40, BEEP_FREQUENCY_4KHZ = (uint8_t)0x80 }
BEEP Frequency selection. More...

Enumeration Type Documentation

enum BEEP_Frequency_TypeDef

BEEP Frequency selection.

Enumerator:
BEEP_FREQUENCY_1KHZ

Beep signal output frequency equals to 1 KHz

BEEP_FREQUENCY_2KHZ

Beep signal output frequency equals to 2 KHz

BEEP_FREQUENCY_4KHZ

Beep signal output frequency equals to 4 KHz

Definition at line 45 of file stm8s_beep.h.


STM8S/A Standard Peripherals Drivers: BEEP_Exported_Constants

Defines
BEEP_Exported_Constants

Defines

#define | BEEP_CALIBRATION_DEFAULT ((uint8_t)0x0B)
#define | LSI_FREQUENCY_MAX ((uint32_t)150000)
#define | LSI_FREQUENCY_MIN ((uint32_t)110000)

Define Documentation

#define BEEP_CALIBRATION_DEFAULT ((uint8_t)0x0B)

Default value when calibration is not done

Definition at line 61 of file stm8s_beep.h.

Referenced by BEEP_Init().

#define LSI_FREQUENCY_MAX ((uint32_t)150000)

LSI maximum value in Hertz

Definition at line 64 of file stm8s_beep.h.

#define LSI_FREQUENCY_MIN ((uint32_t)110000)

LSI minimum value in Hertz

Definition at line 63 of file stm8s_beep.h.


STM8S/A Standard Peripherals Drivers: BEEP_Private_Macros

Defines
BEEP_Private_Macros

Defines

#define | IS_BEEP_FREQUENCY_OK(FREQ)
Macro used by the assert function to check the different functions parameters.
#define | IS_LSI_FREQUENCY_OK(FREQ)
Macro used by the assert function to check the LSI frequency (in Hz).

Define Documentation

#define IS_BEEP_FREQUENCY_OK ( FREQ )
Value:
(((FREQ) == BEEP_FREQUENCY_1KHZ) || \
   ((FREQ) == BEEP_FREQUENCY_2KHZ) || \
   ((FREQ) == BEEP_FREQUENCY_4KHZ))

Macro used by the assert function to check the different functions parameters.

Macro used by the assert function to check the BEEP frequencies.

Definition at line 84 of file stm8s_beep.h.

Referenced by BEEP_Init().

#define IS_LSI_FREQUENCY_OK ( FREQ )
Value:
(((FREQ) >= LSI_FREQUENCY_MIN) && \
   ((FREQ) <= LSI_FREQUENCY_MAX))

Macro used by the assert function to check the LSI frequency (in Hz).

Definition at line 92 of file stm8s_beep.h.


STM8S/A Standard Peripherals Drivers: BEEP_Exported_Functions

Functions
BEEP_Exported_Functions

Functions

void | BEEP_Cmd (FunctionalState NewState)
Enable or disable the BEEP function.
void | BEEP_DeInit (void)
Deinitializes the BEEP peripheral registers to their default reset values.
void | BEEP_Init (BEEP_Frequency_TypeDef BEEP_Frequency)
Initializes the BEEP function according to the specified parameters.
void | BEEP_LSICalibrationConfig (uint32_t LSIFreqHz)
Update CSR register with the measured LSI frequency.

Function Documentation

void BEEP_Cmd ( FunctionalState NewState )

Enable or disable the BEEP function.

Parameters:
NewState Indicates the new state of the BEEP function.
Return values:
None
Required preconditions:
Initialisation of BEEP and LS RC calibration must be done before.

Definition at line 91 of file stm8s_beep.c.

References BEEP, BEEP_CSR_BEEPEN, and DISABLE.

void BEEP_DeInit ( void )

Deinitializes the BEEP peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 54 of file stm8s_beep.c.

References BEEP, and BEEP_CSR_RESET_VALUE.

void BEEP_Init ( BEEP_Frequency_TypeDef BEEP_Frequency )

Initializes the BEEP function according to the specified parameters.

Parameters:
BEEP_Frequency Frequency selection. can be one of the values of BEEP_Frequency_TypeDef.
Return values:
None
Required preconditions:
The LS RC calibration must be performed before calling this function.

Definition at line 67 of file stm8s_beep.c.

References BEEP, BEEP_CALIBRATION_DEFAULT, BEEP_CSR_BEEPDIV, BEEP_CSR_BEEPSEL, and IS_BEEP_FREQUENCY_OK.

void BEEP_LSICalibrationConfig ( uint32_t LSIFreqHz )

Update CSR register with the measured LSI frequency.

Note on the APR calculation:
A is the integer part of LSIFreqkHz/4 and x the decimal part. x <= A/(1+2A) is equivalent to A >= x(1+2A) and also to 4A >= 4x(1+2A) [F1] but we know that A + x = LSIFreqkHz/4 ==> 4x = LSIFreqkHz-4A so [F1] can be written : 4A >= (LSIFreqkHz-4A)(1+2A)
Parameters:
LSIFreqHz Low Speed RC frequency measured by timer (in Hz).
Return values:
None
Required preconditions:
  • BEEP must be disabled to avoid unwanted interrupts.

Definition at line 118 of file stm8s_beep.c.

References BEEP, BEEP_CSR_BEEPDIV, and IS_LSI_FREQUENCY_OK.


STM8S/A Standard Peripherals Drivers: CAN_Exported_Types

Enumerations
CAN_Exported_Types

Enumerations

enum CAN_BitSeg1_TypeDef {
CAN_BitSeg1_1TimeQuantum = ((uint8_t)0x00), CAN_BitSeg1_2TimeQuantum = ((uint8_t)0x01), CAN_BitSeg1_3TimeQuantum = ((uint8_t)0x02), CAN_BitSeg1_4TimeQuantum = ((uint8_t)0x03),
CAN_BitSeg1_5TimeQuantum = ((uint8_t)0x04), CAN_BitSeg1_6TimeQuantum = ((uint8_t)0x05), CAN_BitSeg1_7TimeQuantum = ((uint8_t)0x06), CAN_BitSeg1_8TimeQuantum = ((uint8_t)0x07),
CAN_BitSeg1_9TimeQuantum = ((uint8_t)0x08), CAN_BitSeg1_10TimeQuantum = ((uint8_t)0x09), CAN_BitSeg1_11TimeQuantum = ((uint8_t)0x0A), CAN_BitSeg1_12TimeQuantum = ((uint8_t)0x0B),
CAN_BitSeg1_13TimeQuantum = ((uint8_t)0x0C), CAN_BitSeg1_14TimeQuantum = ((uint8_t)0x0D), CAN_BitSeg1_15TimeQuantum = ((uint8_t)0x0E), CAN_BitSeg1_16TimeQuantum = ((uint8_t)0x0F)
}
time quantum in bit segment 1 More...
enum CAN_BitSeg2_TypeDef {
CAN_BitSeg2_1TimeQuantum = ((uint8_t)0x00), CAN_BitSeg2_2TimeQuantum = ((uint8_t)0x10), CAN_BitSeg2_3TimeQuantum = ((uint8_t)0x20), CAN_BitSeg2_4TimeQuantum = ((uint8_t)0x30),
CAN_BitSeg2_5TimeQuantum = ((uint8_t)0x40), CAN_BitSeg2_6TimeQuantum = ((uint8_t)0x50), CAN_BitSeg2_7TimeQuantum = ((uint8_t)0x60), CAN_BitSeg2_8TimeQuantum = ((uint8_t)0x70)
}
time quantum in bit segment 2 More...
enum CAN_ErrorCode_TypeDef {
CAN_ErrorCode_NoErr = ((uint8_t)0x00), CAN_ErrorCode_StuffErr = ((uint8_t)0x10), CAN_ErrorCode_FormErr = ((uint8_t)0x20), CAN_ErrorCode_ACKErr = ((uint8_t)0x30),
CAN_ErrorCode_BitRecessiveErr = ((uint8_t)0x40), CAN_ErrorCode_BitDominantErr = ((uint8_t)0x50), CAN_ErrorCode_CRCErr = ((uint8_t)0x60), CAN_ErrorCode_SoftwareSetErr = ((uint8_t)0x70)
}
CAN Error Code description. More...
enum | CAN_FilterMode_TypeDef { CAN_FilterMode_IdMask = ((uint8_t)0x00), CAN_FilterMode_IdMask_IdList = ((uint8_t)0x10), CAN_FilterMode_IdList_IdMask = ((uint8_t)0x11), CAN_FilterMode_IdList = ((uint8_t)0x01) }
CAN filter mode. More...
enum CAN_FilterNumber_TypeDef {
CAN_FilterNumber_0 = ((uint8_t)0x00), CAN_FilterNumber_1 = ((uint8_t)0x01), CAN_FilterNumber_2 = ((uint8_t)0x02), CAN_FilterNumber_3 = ((uint8_t)0x03),
CAN_FilterNumber_4 = ((uint8_t)0x04), CAN_FilterNumber_5 = ((uint8_t)0x05)
}
CAN filter number. More...
enum | CAN_FilterScale_TypeDef { CAN_FilterScale_8Bit = ((uint8_t)0x00), CAN_FilterScale_16_8Bit = ((uint8_t)0x02), CAN_FilterScale_16Bit = ((uint8_t)0x04), CAN_FilterScale_32Bit = ((uint8_t)0x06) }
CAN filter scale. More...
enum CAN_FLAG_TypeDef {
CAN_FLAG_RQCP0 = ((uint16_t)0x3401), CAN_FLAG_RQCP1 = ((uint16_t)0x3402), CAN_FLAG_RQCP2 = ((uint16_t)0x3404), CAN_FLAG_FMP = ((uint16_t)0x1203),
CAN_FLAG_FF = ((uint16_t)0x3208), CAN_FLAG_FOV = ((uint16_t)0x3210), CAN_FLAG_WKU = ((uint16_t)0x3108), CAN_FLAG_EWG = ((uint16_t)0x1001),
CAN_FLAG_EPV = ((uint16_t)0x1002), CAN_FLAG_BOF = ((uint16_t)0x1004), CAN_FLAG_LEC = ((uint16_t)0x3070)
}
CAN flags. More...
enum | CAN_Id_TypeDef { CAN_Id_Standard = ((uint8_t)0x00), CAN_Id_Extended = ((uint8_t)0x40) }
CAN identifier type. More...
enum | CAN_InitStatus_TypeDef { CAN_InitStatus_Failed = 0, CAN_InitStatus_Success = ! CAN_InitStatus_Failed }
CAN sleep constants. More...
enum CAN_IT_TypeDef {
CAN_IT_TME = ((uint16_t)0x0001), CAN_IT_FMP = ((uint16_t)0x0002), CAN_IT_FF = ((uint16_t)0x0004), CAN_IT_FOV = ((uint16_t)0x0008),
CAN_IT_WKU = ((uint16_t)0x0080), CAN_IT_ERR = ((uint16_t)0x4000), CAN_IT_EWG = ((uint16_t)0x0100), CAN_IT_EPV = ((uint16_t)0x0200),
CAN_IT_BOF = ((uint16_t)0x0400), CAN_IT_LEC = ((uint16_t)0x0800)
}
CAN interrupts. More...
enum CAN_MasterCtrl_TypeDef {
CAN_MasterCtrl_AllDisabled = ((uint8_t)0x00), CAN_MasterCtrl_AllEnabled = ((uint8_t)0xFC), CAN_MasterCtrl_TimeTriggerCOMMode = ((uint8_t)0x80), CAN_MasterCtrl_AutoBusOffManagement = ((uint8_t)0x40),
CAN_MasterCtrl_AutoWakeUpMode = ((uint8_t)0x20), CAN_MasterCtrl_NoAutoReTx = ((uint8_t)0x10), CAN_MasterCtrl_RxFifoLockedMode = ((uint8_t)0x08), CAN_MasterCtrl_TxFifoPriority = ((uint8_t)0x04)
}
CAN Time Triggered Communication mode. More...
enum | CAN_Mode_TypeDef { CAN_Mode_Normal = ((uint8_t)0x00), CAN_Mode_LoopBack = ((uint8_t)0x01), CAN_Mode_Silent = ((uint8_t)0x02), CAN_Mode_Silent_LoopBack = ((uint8_t)0x03) }
CAN mode options. More...
enum | CAN_ModeStatus_TypeDef { CAN_ModeStatus_Failed = ((uint8_t)0x00), CAN_ModeStatus_Success = ! CAN_ModeStatus_Failed }
CAN operating mode status. More...
enum | CAN_NbrPendingMessage_TypeDef { CAN_NbrPendingMessage_0 = ((uint8_t)0x00), CAN_NbrPendingMessage_1 = ((uint8_t)0x01), CAN_NbrPendingMessage_2 = ((uint8_t)0x02), CAN_NbrPendingMessage_3 = ((uint8_t)0x03) }
CAN Pending Messages number. More...
enum | CAN_OperatingMode_TypeDef { CAN_OperatingMode_Initialization = ((uint8_t)0x00), CAN_OperatingMode_Normal = ((uint8_t)0x01), CAN_OperatingMode_Sleep = ((uint8_t)0x02) }
CAN operating mode. More...
enum CAN_Page_TypeDef {
CAN_Page_TxMailBox0 = ((uint8_t) 0), CAN_Page_TxMailBox1 = ((uint8_t) 1), CAN_Page_TxMailBox2 = ((uint8_t) 5), CAN_Page_Filter01 = ((uint8_t) 2),
CAN_Page_Filter23 = ((uint8_t) 3), CAN_Page_Filter45 = ((uint8_t) 4), CAN_Page_Config = ((uint8_t) 6), CAN_Page_RxFifo = ((uint8_t) 7)
}
CAN Page Mapping. More...
enum | CAN_RTR_TypeDef { CAN_RTR_Data = ((uint8_t)0x00), CAN_RTR_Remote = ((uint8_t)0x20) }
CAN remote transmission request. More...
enum | CAN_Sleep_TypeDef { CAN_Sleep_Failed = ((uint8_t)0x00), CAN_Sleep_Ok = ((uint8_t)0x01) }
CAN sleep Status. More...
enum | CAN_ST7Compatibility_TypeDef { CAN_ST7Compatibility_Enable = ((uint8_t)0x00), CAN_ST7Compatibility_Disable = ((uint8_t)0x10) }
CAN ST7 Compatibility. More...
enum | CAN_SynJumpWidth_TypeDef { CAN_SynJumpWidth_1TimeQuantum = ((uint8_t)0x00), CAN_SynJumpWidth_2TimeQuantum = ((uint8_t)0x40), CAN_SynJumpWidth_3TimeQuantum = ((uint8_t)0x80), CAN_SynJumpWidth_4TimeQuantum = ((uint8_t)0xC0) }
CAN synchronisation jump width (SJW) More...
enum | CAN_TransmitMailBox_TypeDef { CAN_TransmitMailBox_0 = ((uint8_t) 0x00), CAN_TransmitMailBox_1 = ((uint8_t) 0x01), CAN_TransmitMailBox_2 = ((uint8_t) 0x05) }
CAN Tx mailboxes. More...
enum CAN_TxStatus_TypeDef {
CAN_TxStatus_Failed = ((uint8_t)0xF0), CAN_TxStatus_Ok = ((uint8_t)0xF1), CAN_TxStatus_Pending = ((uint8_t)0xF2), CAN_TxStatus_NoMailBox = ((uint8_t)0xF4),
CAN_TxStatus_MailBoxEmpty = ((uint8_t)0xF5), CAN_TxStatus_MailBox0Ok = ((uint8_t)0x00), CAN_TxStatus_MailBox1Ok = ((uint8_t)0x01), CAN_TxStatus_MailBox2Ok = ((uint8_t)0x05)
}
CAN transmit Status. More...
enum | CAN_WakeUp_TypeDef { CAN_WakeUp_Failed = ((uint8_t)0x00), CAN_WakeUp_Ok = ((uint8_t)0x01) }
CAN wake up status. More...

Enumeration Type Documentation

enum CAN_BitSeg1_TypeDef

time quantum in bit segment 1

Enumerator:
CAN_BitSeg1_1TimeQuantum

1 time quantum

CAN_BitSeg1_2TimeQuantum

2 time quantum

CAN_BitSeg1_3TimeQuantum

3 time quantum

CAN_BitSeg1_4TimeQuantum

4 time quantum

CAN_BitSeg1_5TimeQuantum

5 time quantum

CAN_BitSeg1_6TimeQuantum

6 time quantum

CAN_BitSeg1_7TimeQuantum

7 time quantum

CAN_BitSeg1_8TimeQuantum

8 time quantum

CAN_BitSeg1_9TimeQuantum

9 time quantum

CAN_BitSeg1_10TimeQuantum

10 time quantum

CAN_BitSeg1_11TimeQuantum

11 time quantum

CAN_BitSeg1_12TimeQuantum

12 time quantum

CAN_BitSeg1_13TimeQuantum

13 time quantum

CAN_BitSeg1_14TimeQuantum

14 time quantum

CAN_BitSeg1_15TimeQuantum

15 time quantum

CAN_BitSeg1_16TimeQuantum

16 time quantum

Definition at line 126 of file stm8s_can.h.

enum CAN_BitSeg2_TypeDef

time quantum in bit segment 2

Enumerator:
CAN_BitSeg2_1TimeQuantum

1 time quantum

CAN_BitSeg2_2TimeQuantum

2 time quantum

CAN_BitSeg2_3TimeQuantum

3 time quantum

CAN_BitSeg2_4TimeQuantum

4 time quantum

CAN_BitSeg2_5TimeQuantum

5 time quantum

CAN_BitSeg2_6TimeQuantum

6 time quantum

CAN_BitSeg2_7TimeQuantum

7 time quantum

CAN_BitSeg2_8TimeQuantum

8 time quantum

Definition at line 148 of file stm8s_can.h.

enum CAN_ErrorCode_TypeDef

CAN Error Code description.

Enumerator:
CAN_ErrorCode_NoErr

No Error

CAN_ErrorCode_StuffErr

Stuff Error

CAN_ErrorCode_FormErr

Form Error

CAN_ErrorCode_ACKErr

Acknowledgment Error

CAN_ErrorCode_BitRecessiveErr

Bit Recessive Error

CAN_ErrorCode_BitDominantErr

Bit Dominant Error

CAN_ErrorCode_CRCErr

CRC Error

CAN_ErrorCode_SoftwareSetErr

Software Set Error

Definition at line 311 of file stm8s_can.h.

enum CAN_FilterMode_TypeDef

CAN filter mode.

Enumerator:
CAN_FilterMode_IdMask

id/mask mode

CAN_FilterMode_IdMask_IdList

Id/Mask mode First and IdList mode second

CAN_FilterMode_IdList_IdMask

IdList mode First and IdMask mode second

CAN_FilterMode_IdList

identifier list mode

Definition at line 175 of file stm8s_can.h.

enum CAN_FilterNumber_TypeDef

CAN filter number.

Enumerator:
CAN_FilterNumber_0

Filter number 0

CAN_FilterNumber_1

Filter number 1

CAN_FilterNumber_2

Filter number 2

CAN_FilterNumber_3

Filter number 3

CAN_FilterNumber_4

Filter number 4

CAN_FilterNumber_5

Filter number 5

Definition at line 163 of file stm8s_can.h.

enum CAN_FilterScale_TypeDef

CAN filter scale.

Enumerator:
CAN_FilterScale_8Bit

8-bit filter scale

CAN_FilterScale_16_8Bit

16/8-bit filter scale

CAN_FilterScale_16Bit

16-bit filter scale

CAN_FilterScale_32Bit

32-bit filter scale

Definition at line 185 of file stm8s_can.h.

enum CAN_FLAG_TypeDef

CAN flags.

Enumerator:
CAN_FLAG_RQCP0

Request MailBox0 Flag

CAN_FLAG_RQCP1

Request MailBox1 Flag

CAN_FLAG_RQCP2

Request MailBox2 Flag

CAN_FLAG_FMP

FIFO Message Pending Flag

CAN_FLAG_FF

FIFO Full Flag

CAN_FLAG_FOV

FIFO Overrun Flag

CAN_FLAG_WKU

wake up Flag

CAN_FLAG_EWG

Error Warning Flag

CAN_FLAG_EPV

Error Passive Flag

CAN_FLAG_BOF

Bus-Off Flag

CAN_FLAG_LEC

Last error code Flag

Definition at line 260 of file stm8s_can.h.

enum CAN_Id_TypeDef

CAN identifier type.

Enumerator:
CAN_Id_Standard

Standard Id

CAN_Id_Extended

Extended Id

Definition at line 215 of file stm8s_can.h.

enum CAN_InitStatus_TypeDef

CAN sleep constants.

Enumerator:
CAN_InitStatus_Failed

CAN initialization failed

CAN_InitStatus_Success

CAN initialization OK

Definition at line 66 of file stm8s_can.h.

enum CAN_IT_TypeDef

CAN interrupts.

Enumerator:
CAN_IT_TME

Transmit mailbox empty interrupt

CAN_IT_FMP

FIFO message pending interrupt

CAN_IT_FF

FIFO full interrupt

CAN_IT_FOV

FIFO overrun interrupt

CAN_IT_WKU

Wake-up interrupt

CAN_IT_ERR

Genaral Error interrupt

CAN_IT_EWG

Error warning interrupt

CAN_IT_EPV

Error passive interrupt

CAN_IT_BOF

Bus-off interrupt

CAN_IT_LEC

Last error code interrupt

Definition at line 283 of file stm8s_can.h.

enum CAN_MasterCtrl_TypeDef

CAN Time Triggered Communication mode.

Enumerator:
CAN_MasterCtrl_AllDisabled

CAN ALL Master Control Option are DISABLED

CAN_MasterCtrl_AllEnabled

CAN ALL Master Control Option are DISABLED

CAN_MasterCtrl_TimeTriggerCOMMode

CAN Time Triggered Communication mode ENABLED

CAN_MasterCtrl_AutoBusOffManagement

CAN Auto Bus Off Management ENABLED

CAN_MasterCtrl_AutoWakeUpMode

CAN Automatic WakeUp Mode ENABLED , sleep mode is left automatically by hardware

CAN_MasterCtrl_NoAutoReTx

CAN Non Automatic Retransmission ENABLED, MSG will be transmitted only once

CAN_MasterCtrl_RxFifoLockedMode

CAN Receive FIFO Locked against overrun ENABLED

CAN_MasterCtrl_TxFifoPriority

CAN Transmit FIFO Priority driven by the request order (not by the identifier of the MSG)

Definition at line 92 of file stm8s_can.h.

enum CAN_Mode_TypeDef

CAN mode options.

Enumerator:
CAN_Mode_Normal

normal mode

CAN_Mode_LoopBack

loopback mode

CAN_Mode_Silent

silent mode

CAN_Mode_Silent_LoopBack

loopback combined with silent mode

Definition at line 106 of file stm8s_can.h.

enum CAN_ModeStatus_TypeDef

CAN operating mode status.

Enumerator:
CAN_ModeStatus_Failed

CAN entering the specific mode failed

CAN_ModeStatus_Success

CAN entering the specific mode Succeed

Definition at line 83 of file stm8s_can.h.

enum CAN_NbrPendingMessage_TypeDef

CAN Pending Messages number.

Enumerator:
CAN_NbrPendingMessage_0

No Msg Pending

CAN_NbrPendingMessage_1

1 Msg Pending

CAN_NbrPendingMessage_2

2 Msg Pending

CAN_NbrPendingMessage_3

3 Msg Pending

Definition at line 205 of file stm8s_can.h.

enum CAN_OperatingMode_TypeDef

CAN operating mode.

Enumerator:
CAN_OperatingMode_Initialization

Initialization mode

CAN_OperatingMode_Normal

Normal mode

CAN_OperatingMode_Sleep

sleep mode

Definition at line 74 of file stm8s_can.h.

enum CAN_Page_TypeDef

CAN Page Mapping.

Enumerator:
CAN_Page_TxMailBox0

CAN TX mailbox 0 reg page

CAN_Page_TxMailBox1

CAN TX mailbox 1 reg page

CAN_Page_TxMailBox2

CAN TX mailbox 2 reg page

CAN_Page_Filter01

CAN Filters 0 & 1 reg page

CAN_Page_Filter23

CAN Filters 2 & 3 reg page

CAN_Page_Filter45

CAN Filters 4 & 5 reg page

CAN_Page_Config

CAN Configuration control/status reg page

CAN_Page_RxFifo

CAN RX FIFO registers page

Definition at line 49 of file stm8s_can.h.

enum CAN_RTR_TypeDef

CAN remote transmission request.

Enumerator:
CAN_RTR_Data

Data frame

CAN_RTR_Remote

Remote frame

Definition at line 223 of file stm8s_can.h.

enum CAN_Sleep_TypeDef

CAN sleep Status.

Enumerator:
CAN_Sleep_Failed

CAN did not enter the sleep mode

CAN_Sleep_Ok

CAN entered the sleep mode

Definition at line 245 of file stm8s_can.h.

enum CAN_ST7Compatibility_TypeDef

CAN ST7 Compatibility.

Enumerator:
CAN_ST7Compatibility_Enable

CAN is compatible with ST7 beCAN (only 2 mailboxes are available)

CAN_ST7Compatibility_Disable

CAN is not compatible with ST7 beCAN ( 3 mailboxes are available)

Definition at line 303 of file stm8s_can.h.

enum CAN_SynJumpWidth_TypeDef

CAN synchronisation jump width (SJW)

Enumerator:
CAN_SynJumpWidth_1TimeQuantum

1 time quantum

CAN_SynJumpWidth_2TimeQuantum

2 time quantum

CAN_SynJumpWidth_3TimeQuantum

3 time quantum

CAN_SynJumpWidth_4TimeQuantum

4 time quantum

Definition at line 116 of file stm8s_can.h.

enum CAN_TransmitMailBox_TypeDef

CAN Tx mailboxes.

Enumerator:
CAN_TransmitMailBox_0

CAN TX mailbox 0 reg page

CAN_TransmitMailBox_1

CAN TX mailbox 1 reg page

CAN_TransmitMailBox_2

CAN TX mailbox 2 reg page

Definition at line 196 of file stm8s_can.h.

enum CAN_TxStatus_TypeDef

CAN transmit Status.

Enumerator:
CAN_TxStatus_Failed

CAN transmission failed

CAN_TxStatus_Ok

CAN transmission succeeded

CAN_TxStatus_Pending

CAN transmission pending

CAN_TxStatus_NoMailBox

CAN cell did not provide an empty mailbox

CAN_TxStatus_MailBoxEmpty

CAN Tx mailbox is Empty

CAN_TxStatus_MailBox0Ok

CAN transmission succeeded by mail box 1

CAN_TxStatus_MailBox1Ok

CAN transmission succeeded by mail box 2

CAN_TxStatus_MailBox2Ok

CAN transmission succeeded by mail box 3

Definition at line 231 of file stm8s_can.h.

enum CAN_WakeUp_TypeDef

CAN wake up status.

Enumerator:
CAN_WakeUp_Failed

CAN did not leave the sleep mode

CAN_WakeUp_Ok

CAN leaved the sleep mode

Definition at line 252 of file stm8s_can.h.


STM8S/A Standard Peripherals Drivers: CAN_Private_Macros

Defines
CAN_Private_Macros

Defines

#define | CAN_IT_CONFIG_MASK ~(uint16_t)(CAN_IT_TME|CAN_IT_FMP|CAN_IT_FF|CAN_IT_FOV|CAN_IT_WKU|CAN_IT_EWG|CAN_IT_EPV|CAN_IT_BOF|CAN_IT_LEC|CAN_IT_ERR)
Macro used by the assert function in order to check the CAN Configuration interrupts.
#define | IS_CAN_BITSEG1_OK(BS1) ((BS1) <= CAN_BitSeg1_16TimeQuantum)
Macro used by the assert function in order to check time quantum in bit segment 1 .
#define | IS_CAN_BITSEG2_OK(BS2) ((((BS2) >= CAN_BitSeg2_2TimeQuantum) && ((BS2) <= CAN_BitSeg2_8TimeQuantum))|| ((BS2) == CAN_BitSeg2_1TimeQuantum))
Macro used by the assert function in order to check time quantum in bit segment 2.
#define | IS_CAN_DLC_OK(DLC) ((DLC) <= CAN_DLC_MAX)
Macro used by the assert function in order to check the DLC to be sent.
#define | IS_CAN_EXTID_OK(EXTID) ((EXTID) <= ((uint32_t)CAN_EXTID_SIZE))
Macro used by the assert function in order to check the Extended ID to be sent.
#define | IS_CAN_FILTER_MODE_OK(MODE)
Macro used by the assert function in order to check CAN filter mode.
#define | IS_CAN_FILTER_NUMBER_OK(NUMBER)
Macro used by the assert function in order to check CAN filter number.
#define | IS_CAN_FILTER_SCALE_OK(SCALE)
Macro used by the assert function in order to check CAN filter scale.
#define | IS_CAN_FLAG_CLEAR_OK(FLAG)
Macro used by the assert function in order to check CAN flags which can be cleared by CAN_ClearFlag.
#define | IS_CAN_FLAG_STATUS_OK(FLAG)
Macro used by the assert function in order to check CAN flags which can be got by CAN_GetFlagStatus.
#define | IS_CAN_IDTYPE_OK(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || ((IDTYPE) == CAN_Id_Extended))
Macro used by the assert function in order to check the type of the ID to be sent.
#define | IS_CAN_IT_CONFIG_OK(IT) (((IT) != 0x0000) && ((uint16_t)((uint16_t)(IT) & (uint16_t)CAN_IT_CONFIG_MASK) == 0x0000))
#define | IS_CAN_IT_PENDING_BIT_OK(IT)
Macro used by the assert function in order to check the CAN Pending bit interrupts.
#define | IS_CAN_IT_STATUS_OK(IT)
Macro used by the assert function in order to check the CAN status interrupts.
#define | IS_CAN_LAST_ERROR_CODE_OK(CODE) (((CODE) & 0x8F) == 0x00)
Macro used by the assert function in order to check the Last Error Code.
#define | IS_CAN_MASTERCTRL_OK(MODE)
Macro used by the assert function in order to check CAN Time Triggered Communication mode.
#define | IS_CAN_MODE_OK(MODE)
Macro used by the assert function in order to check CAN mode options .
#define | IS_CAN_OPERATINGMODE_OK(MODE)
Macro used by the assert function in order to check CAN operating mode.
#define | IS_CAN_PRESCALER_OK(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 64))
Macro used by the assert function in order to check CAN clock prescaler.
#define | IS_CAN_RTR_OK(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
Macro used by the assert function in order to check CAN transmission Frame Type.
#define | IS_CAN_ST7_COMPATIBILITY_OK(STATE) (((STATE) == CAN_ST7Compatibility_Enable) || ((STATE) == CAN_ST7Compatibility_Disable))
Macro used by the assert function in order to check the CAN ST7 Compatibility parameters.
#define | IS_CAN_STDID_OK(STDID) ((STDID) <= ((uint16_t)CAN_STDID_SIZE))
Macro used by the assert function in order to check the Standard ID to be sent.
#define | IS_CAN_SYNJUMPWIDTH_OK(SJW)
Macro used by the assert function in order to check the CAN synchronisation jump width (SJW).
#define | IS_CAN_TRANSMITMAILBOX_OK(TRANSMITMAILBOX)
Macro used by the assert function in order to check CAN Tx mailboxes.

Define Documentation

#define CAN_IT_CONFIG_MASK ~(uint16_t)(CAN_IT_TME|CAN_IT_FMP|CAN_IT_FF|CAN_IT_FOV|CAN_IT_WKU|CAN_IT_EWG|CAN_IT_EPV|CAN_IT_BOF|CAN_IT_LEC|CAN_IT_ERR)

Macro used by the assert function in order to check the CAN Configuration interrupts.

Definition at line 435 of file stm8s_can.h.

#define IS_CAN_BITSEG1_OK ( BS1 ) ((BS1) <= CAN_BitSeg1_16TimeQuantum)

Macro used by the assert function in order to check time quantum in bit segment 1 .

Definition at line 357 of file stm8s_can.h.

Referenced by CAN_Init().

#define IS_CAN_BITSEG2_OK ( BS2 ) ((((BS2) >= CAN_BitSeg2_2TimeQuantum) && ((BS2) <= CAN_BitSeg2_8TimeQuantum))|| ((BS2) == CAN_BitSeg2_1TimeQuantum))

Macro used by the assert function in order to check time quantum in bit segment 2.

Definition at line 361 of file stm8s_can.h.

Referenced by CAN_Init().

#define IS_CAN_DLC_OK ( DLC ) ((DLC) <= CAN_DLC_MAX)

Macro used by the assert function in order to check the DLC to be sent.

Definition at line 406 of file stm8s_can.h.

Referenced by CAN_GetReceivedData(), and CAN_Transmit().

#define IS_CAN_EXTID_OK ( EXTID ) ((EXTID) <= ((uint32_t)CAN_EXTID_SIZE))

Macro used by the assert function in order to check the Extended ID to be sent.

Definition at line 402 of file stm8s_can.h.

Referenced by CAN_Transmit().

#define IS_CAN_FILTER_MODE_OK ( MODE )
Value:
(((MODE) == CAN_FilterMode_IdMask) || \
                                     ((MODE) == CAN_FilterMode_IdMask_IdList) || \
                                     ((MODE) == CAN_FilterMode_IdList_IdMask) || \
                                  ((MODE) == CAN_FilterMode_IdList))

Macro used by the assert function in order to check CAN filter mode.

Definition at line 378 of file stm8s_can.h.

Referenced by CAN_FilterInit().

#define IS_CAN_FILTER_NUMBER_OK ( NUMBER )
Value:
(((NUMBER) == CAN_FilterNumber_0) || \
                                       ((NUMBER) == CAN_FilterNumber_1) || \
                                       ((NUMBER) == CAN_FilterNumber_2) || \
                                       ((NUMBER) == CAN_FilterNumber_3) || \
                                       ((NUMBER) == CAN_FilterNumber_4) || \
                                       ((NUMBER) == CAN_FilterNumber_5))

Macro used by the assert function in order to check CAN filter number.

Definition at line 369 of file stm8s_can.h.

Referenced by CAN_FilterInit().

#define IS_CAN_FILTER_SCALE_OK ( SCALE )
Value:
(((SCALE) == CAN_FilterScale_8Bit)|| \
                                    ((SCALE) == CAN_FilterScale_16_8Bit) ||\
                                    ((SCALE) == CAN_FilterScale_16Bit  )||\
                                    ((SCALE) == CAN_FilterScale_32Bit))

Macro used by the assert function in order to check CAN filter scale.

Definition at line 385 of file stm8s_can.h.

Referenced by CAN_FilterInit().

#define IS_CAN_FLAG_CLEAR_OK ( FLAG )
Value:
(((FLAG) == CAN_FLAG_RQCP0) || ((FLAG) == CAN_FLAG_RQCP1) ||\
                                    ((FLAG) == CAN_FLAG_RQCP2) ||  ((FLAG) == CAN_FLAG_FF)   ||\
                                    ((FLAG) == CAN_FLAG_FOV)  ||  ((FLAG) == CAN_FLAG_WKU) ||\
                                    ((FLAG) == CAN_FLAG_LEC))

Macro used by the assert function in order to check CAN flags which can be cleared by CAN_ClearFlag.

Definition at line 428 of file stm8s_can.h.

Referenced by CAN_ClearFlag().

#define IS_CAN_FLAG_STATUS_OK ( FLAG )
Value:
(((FLAG) == CAN_FLAG_RQCP0) || ((FLAG) == CAN_FLAG_RQCP1) ||\
                                  ((FLAG) == CAN_FLAG_RQCP2) || ((FLAG) == CAN_FLAG_FMP) ||\
                                  ((FLAG) == CAN_FLAG_FF) || ((FLAG) == CAN_FLAG_FOV) ||\
                                  ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_EWG) ||\
                                  ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_BOF) ||\
                                  ((FLAG) == CAN_FLAG_LEC))

Macro used by the assert function in order to check CAN flags which can be got by CAN_GetFlagStatus.

Definition at line 419 of file stm8s_can.h.

Referenced by CAN_GetFlagStatus().

#define IS_CAN_IDTYPE_OK ( IDTYPE ) (((IDTYPE) == CAN_Id_Standard) || ((IDTYPE) == CAN_Id_Extended))

Macro used by the assert function in order to check the type of the ID to be sent.

Definition at line 410 of file stm8s_can.h.

Referenced by CAN_Transmit().

#define IS_CAN_IT_CONFIG_OK ( IT ) (((IT) != 0x0000) && ((uint16_t)((uint16_t)(IT) & (uint16_t)CAN_IT_CONFIG_MASK) == 0x0000))

Definition at line 436 of file stm8s_can.h.

Referenced by CAN_ITConfig().

#define IS_CAN_IT_PENDING_BIT_OK ( IT )
Value:
(((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF)  ||\
                                      ((IT) == CAN_IT_FOV)  || ((IT) == CAN_IT_WKU) ||\
                                      ((IT) == CAN_IT_ERR)  || ((IT) == CAN_IT_EWG) ||\
                                      ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF)||\
                                      ((IT) == CAN_IT_LEC))

Macro used by the assert function in order to check the CAN Pending bit interrupts.

Definition at line 448 of file stm8s_can.h.

Referenced by CAN_ClearITPendingBit().

#define IS_CAN_IT_STATUS_OK ( IT )
Value:
(((IT) == CAN_IT_TME)   || ((IT) == CAN_IT_FMP) ||\
                             ((IT) == CAN_IT_FF)    || ((IT) == CAN_IT_FOV) || \
                             ((IT) == CAN_IT_WKU)   || ((IT) == CAN_IT_ERR)  || \
                             ((IT) == CAN_IT_EWG)   || ((IT) == CAN_IT_EPV)  || \
                             ((IT) == CAN_IT_BOF)   || ((IT) == CAN_IT_LEC)  )

Macro used by the assert function in order to check the CAN status interrupts.

Definition at line 440 of file stm8s_can.h.

Referenced by CAN_GetITStatus().

#define IS_CAN_LAST_ERROR_CODE_OK ( CODE ) (((CODE) & 0x8F) == 0x00)

Macro used by the assert function in order to check the Last Error Code.

Definition at line 456 of file stm8s_can.h.

#define IS_CAN_MASTERCTRL_OK ( MODE )
Value:
(((MODE) == CAN_MasterCtrl_AllDisabled) || \
                                    (((MODE) <= CAN_MasterCtrl_AllEnabled) && ((MODE) >= CAN_MasterCtrl_TxFifoPriority)))

Macro used by the assert function in order to check CAN Time Triggered Communication mode.

Definition at line 342 of file stm8s_can.h.

Referenced by CAN_Init().

#define IS_CAN_MODE_OK ( MODE )
Value:
(((MODE) == CAN_Mode_Normal) || ((MODE) == CAN_Mode_LoopBack)|| \
                           ((MODE) == CAN_Mode_Silent) || ((MODE) == CAN_Mode_Silent_LoopBack))

Macro used by the assert function in order to check CAN mode options .

Definition at line 347 of file stm8s_can.h.

Referenced by CAN_Init().

#define IS_CAN_OPERATINGMODE_OK ( MODE )
Value:
(((MODE) == CAN_OperatingMode_Initialization) ||\
                                    ((MODE) == CAN_OperatingMode_Normal)|| \
                        ((MODE) == CAN_OperatingMode_Sleep))

Macro used by the assert function in order to check CAN operating mode.

Definition at line 336 of file stm8s_can.h.

Referenced by CAN_OperatingModeRequest().

#define IS_CAN_PRESCALER_OK ( PRESCALER ) (((PRESCALER) >= 1) && ((PRESCALER) <= 64))

Macro used by the assert function in order to check CAN clock prescaler.

Definition at line 365 of file stm8s_can.h.

Referenced by CAN_Init().

#define IS_CAN_RTR_OK ( RTR ) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))

Macro used by the assert function in order to check CAN transmission Frame Type.

Definition at line 414 of file stm8s_can.h.

Referenced by CAN_Transmit().

#define IS_CAN_ST7_COMPATIBILITY_OK ( STATE ) (((STATE) == CAN_ST7Compatibility_Enable) || ((STATE) == CAN_ST7Compatibility_Disable))

Macro used by the assert function in order to check the CAN ST7 Compatibility parameters.

Definition at line 332 of file stm8s_can.h.

Referenced by CAN_ST7CompatibilityCmd().

#define IS_CAN_STDID_OK ( STDID ) ((STDID) <= ((uint16_t)CAN_STDID_SIZE))

Macro used by the assert function in order to check the Standard ID to be sent.

Definition at line 398 of file stm8s_can.h.

Referenced by CAN_Transmit().

#define IS_CAN_SYNJUMPWIDTH_OK ( SJW )
Value:
(((SJW) == CAN_SynJumpWidth_1TimeQuantum) || ((SJW) == CAN_SynJumpWidth_2TimeQuantum)|| \
                         ((SJW) == CAN_SynJumpWidth_3TimeQuantum) || ((SJW) == CAN_SynJumpWidth_4TimeQuantum))

Macro used by the assert function in order to check the CAN synchronisation jump width (SJW).

Definition at line 352 of file stm8s_can.h.

Referenced by CAN_Init().

#define IS_CAN_TRANSMITMAILBOX_OK ( TRANSMITMAILBOX )
Value:
(((TRANSMITMAILBOX) == CAN_TransmitMailBox_0) || \
                                                 ((TRANSMITMAILBOX) == CAN_TransmitMailBox_1) || \
                                                 ((TRANSMITMAILBOX) == CAN_TransmitMailBox_2))

Macro used by the assert function in order to check CAN Tx mailboxes.

Definition at line 392 of file stm8s_can.h.

Referenced by CAN_CancelTransmit(), and CAN_TransmitStatus().


STM8S/A Standard Peripherals Drivers: CAN_Exported_Functions

Functions
CAN_Exported_Functions

Functions

void | CAN_CancelTransmit (CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox)
Cancels a transmit request.
void | CAN_ClearFlag (CAN_FLAG_TypeDef CAN_Flag)
Clears the CAN's pending flags.
void | CAN_ClearITPendingBit (CAN_IT_TypeDef CAN_IT)
Clears the CAN’s interrupt pending bits.
void | CAN_DeInit (void)
Deinitializes the CAN peripheral registers to their default reset values.
void | CAN_FIFORelease (void)
Releases the CAN FIFO.
void | CAN_FilterInit (CAN_FilterNumber_TypeDef CAN_FilterNumber, FunctionalState CAN_FilterActivation, CAN_FilterMode_TypeDef CAN_FilterMode, CAN_FilterScale_TypeDef CAN_FilterScale, uint8_t CAN_FilterID1, uint8_t CAN_FilterID2, uint8_t CAN_FilterID3, uint8_t CAN_FilterID4, uint8_t CAN_FilterIDMask1, uint8_t CAN_FilterIDMask2, uint8_t CAN_FilterIDMask3, uint8_t CAN_FilterIDMask4)
Initializes the CAN peripheral Filter according to the specified parameters.
FlagStatus | CAN_GetFlagStatus (CAN_FLAG_TypeDef CAN_Flag)
Checks whether the specified CAN flag is set or not.
ITStatus | CAN_GetITStatus (CAN_IT_TypeDef CAN_IT)
Checks whether the specified CAN interrupt has occurred or not.
CAN_ErrorCode_TypeDef | CAN_GetLastErrorCode (void)
Gets the Last Error Code.
uint16_t | CAN_GetMessageTimeStamp (void)
Returns the Received time stamp.
uint8_t | CAN_GetReceivedData (uint8_t CAN_DataIndex)
Gets the CAN Data of the received message.
uint8_t | CAN_GetReceivedDLC (void)
Gets the CAN DLC of the received message.
uint8_t | CAN_GetReceivedFMI (void)
Gets the CAN FMI of the received message.
uint32_t | CAN_GetReceivedId (void)
Gets the CAN Id of the received message.
CAN_Id_TypeDef | CAN_GetReceivedIDE (void)
Gets the CAN IDE of the received message.
CAN_RTR_TypeDef | CAN_GetReceivedRTR (void)
Gets the CAN RTR of the received message.
CAN_Page_TypeDef | CAN_GetSelectedPage (void)
Gets the selected registers page.
CAN_InitStatus_TypeDef | CAN_Init (CAN_MasterCtrl_TypeDef CAN_MasterCtrl, CAN_Mode_TypeDef CAN_Mode, CAN_SynJumpWidth_TypeDef CAN_SynJumpWidth, CAN_BitSeg1_TypeDef CAN_BitSeg1, CAN_BitSeg2_TypeDef CAN_BitSeg2, uint8_t CAN_Prescaler)
Initializes the CAN peripheral according to the specified parameters.
void | CAN_ITConfig (CAN_IT_TypeDef CAN_IT, FunctionalState NewState)
Enables or disables the specified CAN interrupts.
CAN_NbrPendingMessage_TypeDef | CAN_MessagePending (void)
Returns the number of pending messages.
CAN_ModeStatus_TypeDef | CAN_OperatingModeRequest (CAN_OperatingMode_TypeDef CAN_OperatingMode)
Select the CAN Operation mode.
void | CAN_Receive (void)
Receives a message which contains CAN Id, IDE, RTR DLC, data and FMI number.
void | CAN_SelectPage (CAN_Page_TypeDef CAN_Page)
Sets the registers page to be selected.
CAN_Sleep_TypeDef | CAN_Sleep (void)
Enters the Sleep low power mode.
void | CAN_ST7CompatibilityCmd (CAN_ST7Compatibility_TypeDef CAN_ST7Compatibility)
Enables or Disables the ST7 CAN Compatibility.
CAN_TxStatus_TypeDef | CAN_Transmit (uint32_t CAN_Id, CAN_Id_TypeDef CAN_IDE, CAN_RTR_TypeDef CAN_RTR, uint8_t CAN_DLC, uint8_t *CAN_Data)
Initiates the transmission of a message.
CAN_TxStatus_TypeDef | CAN_TransmitStatus (CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox)
Checks the transmission of a message.
void | CAN_TTComModeCmd (FunctionalState NewState)
Enables or disables the CAN Time TriggerOperation communication mode.
CAN_WakeUp_TypeDef | CAN_WakeUp (void)
Wakes the CAN up.

Function Documentation

void CAN_CancelTransmit ( CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox )

Cancels a transmit request.

Parameters:
CAN_TransmitMailbox : the Transmission mailbox, can be one of CAN_TransmitMailBox_TypeDef
Return values:
None

Definition at line 724 of file stm8s_can.c.

References CAN_GetSelectedPage(), CAN_MCSR_ABRQ, CAN_SelectPage(), and IS_CAN_TRANSMITMAILBOX_OK.

void CAN_ClearFlag ( CAN_FLAG_TypeDef CAN_Flag )

Clears the CAN's pending flags.

Parameters:
CAN_Flag : Flag to be cleared, can be one of the following parameters: CAN_FLAG_RQCP0 Request MailBox0 Flag CAN_FLAG_RQCP1 Request MailBox1 Flag CAN_FLAG_RQCP2 Request MailBox2 Flag CAN_FLAG_FF FIFO Full Flag CAN_FLAG_FOV FIFO Overrun Flag CAN_FLAG_WKU wake up Flag CAN_FLAG_LEC Last error code Flag
Return values:
None

Definition at line 1077 of file stm8s_can.c.

References CAN_GetSelectedPage(), CAN_Page_Config, CAN_SelectPage(), IS_CAN_FLAG_CLEAR_OK, and RESET.

void CAN_ClearITPendingBit ( CAN_IT_TypeDef CAN_IT )

Clears the CAN’s interrupt pending bits.

Parameters:
CAN_IT,: specifies the interrupt pending bit to clear, can be one of the following parameters: CAN_IT_TME = Transmit mailbox empty interrupt CAN_IT_FF =FIFO full interrupt CAN_IT_FOV =FIFO overrun interrupt CAN_IT_WKU =Wake-up interrupt CAN_IT_ERR =General Error interrupt CAN_IT_EWG =Error warning interrupt CAN_IT_EPV =Error passive interrupt CAN_IT_BOF = Bus-off interrupt CAN_IT_LEC =Last error code interrupt
Return values:
None

Definition at line 1348 of file stm8s_can.c.

References CAN_ESR_RESET_VALUE, CAN_GetSelectedPage(), CAN_IT_BOF, CAN_IT_EPV, CAN_IT_ERR, CAN_IT_EWG, CAN_IT_FF, CAN_IT_FOV, CAN_IT_LEC, CAN_IT_TME, CAN_IT_WKU, CAN_MSR_ERRI, CAN_MSR_WKUI, CAN_Page_Config, CAN_RFR_FOVR, CAN_RFR_FULL, CAN_SelectPage(), CAN_TSR_RQCP012, and IS_CAN_IT_PENDING_BIT_OK.

void CAN_DeInit ( void )

Deinitializes the CAN peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 62 of file stm8s_can.c.

References CAN_BTR1_RESET_VALUE, CAN_BTR2_RESET_VALUE, CAN_DGR_RESET_VALUE, CAN_EIER_RESET_VALUE, CAN_ESR_RESET_VALUE, CAN_FCR_RESET_VALUE, CAN_FMR1_RESET_VALUE, CAN_FMR2_RESET_VALUE, CAN_IER_RESET_VALUE, CAN_MCR_INRQ, CAN_MCR_RESET_VALUE, CAN_MDLC_RESET_VALUE, CAN_MSR_RESET_VALUE, CAN_OperatingMode_Initialization, CAN_OperatingMode_Normal, CAN_OperatingModeRequest(), CAN_Page_Config, CAN_Page_RxFifo, CAN_Page_TxMailBox0, CAN_Page_TxMailBox1, CAN_Page_TxMailBox2, CAN_PSR_RESET_VALUE, CAN_RFR_RESET_VALUE, and CAN_TSR_RESET_VALUE.

void CAN_FIFORelease ( void )

Releases the CAN FIFO.

Parameters:
None
Return values:
None

Definition at line 742 of file stm8s_can.c.

References CAN_RFR_RFOM.

Referenced by CAN_Receive().

void CAN_FilterInit | ( | CAN_FilterNumber_TypeDef | CAN_FilterNumber,
 |  | FunctionalState | CAN_FilterActivation,
 |  | CAN_FilterMode_TypeDef | CAN_FilterMode,
 |  | CAN_FilterScale_TypeDef | CAN_FilterScale,
 |  | uint8_t | CAN_FilterID1,
 |  | uint8_t | CAN_FilterID2,
 |  | uint8_t | CAN_FilterID3,
 |  | uint8_t | CAN_FilterID4,
 |  | uint8_t | CAN_FilterIDMask1,
 |  | uint8_t | CAN_FilterIDMask2,
 |  | uint8_t | CAN_FilterIDMask3,
 |  | uint8_t | CAN_FilterIDMask4
 | ) |  |

Initializes the CAN peripheral Filter according to the specified parameters.

Parameters:
CAN_FilterNumber | : CAN Filter number , can be one of CAN_FilterNumber_TypeDef
CAN_FilterActivation | : CAN Filter Activation state , can be one of FunctionalState
CAN_FilterMode | : CAN Filter Mode , can be one of CAN_FilterMode_TypeDef
CAN_FilterScale | : CAN Filter Scale , can be one of CAN_FilterScale_TypeDef
CAN_FilterID1 | : CAN Filter ID 1 , can be a value from 0x00 to 0xFF
CAN_FilterID2 | : CAN Filter ID 2 , can be a value from 0x00 to 0xFF
CAN_FilterID3 | : CAN Filter ID 3 , can be a value from 0x00 to 0xFF
CAN_FilterID4 | : CAN Filter ID 4 , can be a value from 0x00 to 0xFF
CAN_FilterIDMask1 | : CAN Filter ID 1/ Mask 1 , can be a value from 0x00 to 0xFF depending of CAN_FilterMode parameter
CAN_FilterIDMask2 | : CAN Filter ID 2/ Mask 2 , can be a value from 0x00 to 0xFF depending of CAN_FilterMode parameter
CAN_FilterIDMask3 | : CAN Filter ID 3/ Mask 3 , can be a value from 0x00 to 0xFF depending of CAN_FilterMode parameter
CAN_FilterIDMask4 | : CAN Filter ID 4/ Mask 4 , can be a value from 0x00 to 0xFF depending of CAN_FilterMode parameter
Return values:
None

Definition at line 194 of file stm8s_can.c.

References CAN_FCR1_FSC00, CAN_FCR1_FSC01, CAN_FilterMode_IdList, CAN_FilterMode_IdList_IdMask, CAN_FilterMode_IdMask, CAN_FilterNumber_0, CAN_FilterNumber_1, CAN_FilterNumber_2, CAN_FilterNumber_3, CAN_FilterNumber_4, CAN_FilterScale_16_8Bit, CAN_FilterScale_16Bit, CAN_FilterScale_32Bit, CAN_FilterScale_8Bit, CAN_GetSelectedPage(), CAN_IDLIST_IDMASK_MASK, CAN_IDMASK_IDLIST_MASK, CAN_OperatingMode_Initialization, CAN_OperatingMode_Normal, CAN_OperatingModeRequest(), CAN_Page_Config, CAN_Page_Filter01, CAN_Page_Filter23, CAN_Page_Filter45, CAN_SelectPage(), DISABLE, IS_CAN_FILTER_MODE_OK, IS_CAN_FILTER_NUMBER_OK, IS_CAN_FILTER_SCALE_OK, and IS_FUNCTIONALSTATE_OK.

FlagStatus CAN_GetFlagStatus ( CAN_FLAG_TypeDef CAN_Flag )

Checks whether the specified CAN flag is set or not.

Parameters:
CAN_Flag : specifies the flag to check, can be one of CAN_FLAG_TypeDef enumeration.
Return values:
The new state of CAN_FLAG which can be one of FlagStatus.

Definition at line 1119 of file stm8s_can.c.

References CAN_GetSelectedPage(), CAN_Page_Config, CAN_SelectPage(), IS_CAN_FLAG_STATUS_OK, RESET, and SET.

ITStatus CAN_GetITStatus ( CAN_IT_TypeDef CAN_IT )

Checks whether the specified CAN interrupt has occurred or not.

Parameters:
CAN_IT,: specifies the CAN interrupt source to check, can be one of CAN_IT_TypeDef.
Return values:
The new state of CAN_IT, which can be one of ITStatus.

Definition at line 1203 of file stm8s_can.c.

References CAN_EIER_BOFIE, CAN_EIER_EPVIE, CAN_EIER_ERRIE, CAN_EIER_EWGIE, CAN_EIER_LECIE, CAN_ESR_BOFF, CAN_ESR_EPVF, CAN_ESR_EWGF, CAN_ESR_LEC, CAN_GetSelectedPage(), CAN_IER_FFIE, CAN_IER_FMPIE, CAN_IER_FOVIE, CAN_IER_TMEIE, CAN_IER_WKUIE, CAN_IT_BOF, CAN_IT_EPV, CAN_IT_ERR, CAN_IT_EWG, CAN_IT_FF, CAN_IT_FMP, CAN_IT_FOV, CAN_IT_LEC, CAN_IT_TME, CAN_IT_WKU, CAN_MSR_WKUI, CAN_Page_Config, CAN_RFR_FMP01, CAN_RFR_FOVR, CAN_RFR_FULL, CAN_SelectPage(), CAN_TSR_RQCP012, CheckITStatus(), IS_CAN_IT_STATUS_OK, and RESET.

CAN_ErrorCode_TypeDef CAN_GetLastErrorCode ( void )

Gets the Last Error Code.

Parameters:
None
Return values:
Error Code.

Definition at line 1051 of file stm8s_can.c.

References CAN_ErrorCode_NoErr, CAN_ESR_LEC, CAN_GetSelectedPage(), CAN_Page_Config, and CAN_SelectPage().

uint16_t CAN_GetMessageTimeStamp ( void )

Returns the Received time stamp.

Parameters:
None
Return values:
uint16_t the received time stamp.

Definition at line 902 of file stm8s_can.c.

References CAN_GetSelectedPage(), CAN_Page_RxFifo, and CAN_SelectPage().

uint8_t CAN_GetReceivedData ( uint8_t CAN_DataIndex )

Gets the CAN Data of the received message.

Parameters:
CAN_DataIndex : number of the received Data, it can be an integer between 0 to 7.
Return values:
the received CAN message ith Data.
Required preconditions:
This function is used to get data loaded by CAN_Receive function. Before using this function, CAN_Receive function must be called.

Definition at line 878 of file stm8s_can.c.

References _Data, and IS_CAN_DLC_OK.

uint8_t CAN_GetReceivedDLC ( void )

Gets the CAN DLC of the received message.

Parameters:
None
Return values:
the received CAN message DLC.
Required preconditions:
This function is used to get data loaded by CAN_Receive function. Before using this function, CAN_Receive function must be called.

Definition at line 864 of file stm8s_can.c.

References _DLC.

uint8_t CAN_GetReceivedFMI ( void )

Gets the CAN FMI of the received message.

Parameters:
None
Return values:
the received CAN message FMI.
Required preconditions:
This function is used to get data loaded by CAN_Receive function. Before using this function, CAN_Receive function must be called.

Definition at line 892 of file stm8s_can.c.

References _FMI.

uint32_t CAN_GetReceivedId ( void )

Gets the CAN Id of the received message.

Parameters:
None
Return values:
the received CAN message Id.
Required preconditions:
This function is used to get data loaded by CAN_Receive function. Before using this function, CAN_Receive function must be called.

Definition at line 825 of file stm8s_can.c.

References _Id.

CAN_Id_TypeDef CAN_GetReceivedIDE ( void )

Gets the CAN IDE of the received message.

Parameters:
None
Return values:
the received CAN message IDE.
Required preconditions:
This function is used to get data loaded by CAN_Receive function. Before using this function, CAN_Receive function must be called.

Definition at line 838 of file stm8s_can.c.

References _IDE.

CAN_RTR_TypeDef CAN_GetReceivedRTR ( void )

Gets the CAN RTR of the received message.

Parameters:
None
Return values:
the received CAN message RTR.
Required preconditions:
This function is used to get data loaded by CAN_Receive function. Before using this function, CAN_Receive function must be called.

Definition at line 851 of file stm8s_can.c.

References _RTR.

CAN_Page_TypeDef CAN_GetSelectedPage ( void )

Gets the selected registers page.

Parameters:
None
Return values:
the selected page which can be one of the CAN_Page_TypeDef.

Definition at line 1407 of file stm8s_can.c.

Referenced by CAN_CancelTransmit(), CAN_ClearFlag(), CAN_ClearITPendingBit(), CAN_FilterInit(), CAN_GetFlagStatus(), CAN_GetITStatus(), CAN_GetLastErrorCode(), CAN_GetMessageTimeStamp(), CAN_Init(), CAN_ITConfig(), CAN_Receive(), CAN_Transmit(), and CAN_TTComModeCmd().

CAN_InitStatus_TypeDef CAN_Init | ( | CAN_MasterCtrl_TypeDef | CAN_MasterCtrl,
 |  | CAN_Mode_TypeDef | CAN_Mode,
 |  | CAN_SynJumpWidth_TypeDef | CAN_SynJumpWidth,
 |  | CAN_BitSeg1_TypeDef | CAN_BitSeg1,
 |  | CAN_BitSeg2_TypeDef | CAN_BitSeg2,
 |  | uint8_t | CAN_Prescaler
 | ) |  |

Initializes the CAN peripheral according to the specified parameters.

Parameters:
CAN_MasterCtrl | : Master control option, can be one or a combination of CAN_MasterCtrl_TypeDef.
CAN_Mode | : CAN mode , can be one of CAN_Mode_TypeDef.
CAN_SynJumpWidth | : CAN Synchronisation Jump Width , can be one of CAN_SynJumpWidth_TypeDef.
CAN_BitSeg1 | : CAN bit segment 1 , can be one of CAN_BitSeg1_TypeDef.
CAN_BitSeg2 | : CAN bit segment 2 , can be one of CAN_BitSeg2_TypeDef.
CAN_Prescaler | : CAN Baud Rate Prescaler , can be a value from 0x01 to 0xFF.
Return values:
Indicates if initialization is succeed. it can be one of CAN_InitStatus_TypeDef enumeration.

Definition at line 106 of file stm8s_can.c.

References CAN_ACKNOWLEDGE_TIMEOUT, CAN_GetSelectedPage(), CAN_InitStatus_Failed, CAN_InitStatus_Success, CAN_MCR_INRQ, CAN_MSR_INAK, CAN_Page_Config, CAN_SelectPage(), IS_CAN_BITSEG1_OK, IS_CAN_BITSEG2_OK, IS_CAN_MASTERCTRL_OK, IS_CAN_MODE_OK, IS_CAN_PRESCALER_OK, and IS_CAN_SYNJUMPWIDTH_OK.

void CAN_ITConfig | ( | CAN_IT_TypeDef | CAN_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified CAN interrupts.

Parameters:
CAN_IT,: specifies the CAN interrupt sources to be enabled or disabled.
NewState : CAN_IT new state , can be one of FunctionalState
Return values:
None

Definition at line 487 of file stm8s_can.c.

References CAN_GetSelectedPage(), CAN_Page_Config, CAN_SelectPage(), DISABLE, IS_CAN_IT_CONFIG_OK, and IS_FUNCTIONALSTATE_OK.

CAN_NbrPendingMessage_TypeDef CAN_MessagePending ( void )

Returns the number of pending messages.

Return values:
Number of pending messages.

Definition at line 752 of file stm8s_can.c.

References CAN_NbrPendingMessage_0, and CAN_RFR_FMP01.

CAN_ModeStatus_TypeDef CAN_OperatingModeRequest ( CAN_OperatingMode_TypeDef CAN_OperatingMode )

Select the CAN Operation mode.

Parameters:
CAN_OperatingMode CAN Operating Mode , this parameter can be one of CAN_OperatingMode_TypeDef enumeration.
Return values:
the status of the requested mode which can be
  • CAN_ModeStatus_Failed CAN failed entering the specific mode
  • CAN_ModeStatus_Success CAN Succeed entering the specific mode

Definition at line 974 of file stm8s_can.c.

References CAN_ACKNOWLEDGE_TIMEOUT, CAN_MCR_INRQ, CAN_MCR_SLEEP, CAN_MODE_MASK, CAN_ModeStatus_Failed, CAN_ModeStatus_Success, CAN_MSR_INAK, CAN_MSR_SLAK, CAN_OperatingMode_Initialization, CAN_OperatingMode_Normal, CAN_OperatingMode_Sleep, and IS_CAN_OPERATINGMODE_OK.

Referenced by CAN_DeInit(), and CAN_FilterInit().

void CAN_Receive ( void )

Receives a message which contains CAN Id, IDE, RTR DLC, data and FMI number.

In order to get these data, use CAN_GetReceivedId(), CAN_GetReceivedIDE(), CAN_GetReceivedRTR(), CAN_GetReceivedDLC(), CAN_GetReceivedFMI() and CAN_GetReceivedData() functions.

Parameters:
None
Return values:
None

Definition at line 767 of file stm8s_can.c.

References _Data, _DLC, _FMI, _Id, _IDE, _RTR, CAN_EXTID_SIZE, CAN_FIFORelease(), CAN_GetSelectedPage(), CAN_Id_Extended, CAN_Id_Standard, CAN_Page_RxFifo, CAN_SelectPage(), and CAN_STDID_SIZE.

void CAN_SelectPage ( CAN_Page_TypeDef CAN_Page )

Sets the registers page to be selected.

Parameters:
CAN_Page,: the selected page which can be one of the CAN_Page_TypeDef.
Return values:
None

Definition at line 1417 of file stm8s_can.c.

Referenced by CAN_CancelTransmit(), CAN_ClearFlag(), CAN_ClearITPendingBit(), CAN_FilterInit(), CAN_GetFlagStatus(), CAN_GetITStatus(), CAN_GetLastErrorCode(), CAN_GetMessageTimeStamp(), CAN_Init(), CAN_ITConfig(), CAN_Receive(), CAN_Transmit(), and CAN_TTComModeCmd().

CAN_Sleep_TypeDef CAN_Sleep ( void )

Enters the Sleep low power mode.

Parameters:
None
Return values:
CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed in an other case.

Definition at line 924 of file stm8s_can.c.

References CAN_MCR_INRQ, CAN_MCR_SLEEP, CAN_MSR_INAK, CAN_MSR_SLAK, CAN_Sleep_Failed, and CAN_Sleep_Ok.

void CAN_ST7CompatibilityCmd ( CAN_ST7Compatibility_TypeDef CAN_ST7Compatibility )

Enables or Disables the ST7 CAN Compatibility.

if the ST7 compatibility is Enabled, CAN provides only 2 mailboxes. if the ST7 compatibility is Disabled, CAN provides 3 mailboxes.

Parameters:
CAN_ST7Compatibility : CAN ST7 Compatibility , this parameter can be one of CAN_ST7Compatibility_TypeDef enumeration.
Return values:
None

Definition at line 525 of file stm8s_can.c.

References CAN_DGR_TXM2E, and IS_CAN_ST7_COMPATIBILITY_OK.

CAN_TxStatus_TypeDef CAN_Transmit | ( | uint32_t | CAN_Id,
 |  | CAN_Id_TypeDef | CAN_IDE,
 |  | CAN_RTR_TypeDef | CAN_RTR,
 |  | uint8_t | CAN_DLC,
 |  | uint8_t * | CAN_Data
 | ) |  |

Initiates the transmission of a message.

Parameters:
CAN_Id | the ID number of the message, its size depends on CAN_IDE value.
[in] | CAN_IDE | the ID type of the message, this parameter can be one of the CAN_Id_TypeDef enumeration.
[in] | CAN_RTR | the message type, this parameter can be one of the CAN_RTR_TypeDef enumeration.
[in] | CAN_DLC | the number of data in the message type, this parameter can be a value between 0 to 7.
[in] | CAN_Data | pointer to a the uint8_t table which contains data to sent.
Return values:
Transmit Status, this returned value can be one of the CAN_TxStatus_TypeDef enumeration.

Definition at line 587 of file stm8s_can.c.

References CAN_EXTID_SIZE, CAN_GetSelectedPage(), CAN_Id_Standard, CAN_MCSR_TXRQ, CAN_SelectPage(), CAN_STDID_SIZE, CAN_TPR_TME0, CAN_TPR_TME1, CAN_TPR_TME2, CAN_TxStatus_MailBox0Ok, CAN_TxStatus_MailBox1Ok, CAN_TxStatus_MailBox2Ok, CAN_TxStatus_NoMailBox, IS_CAN_DLC_OK, IS_CAN_EXTID_OK, IS_CAN_IDTYPE_OK, IS_CAN_RTR_OK, and IS_CAN_STDID_OK.

CAN_TxStatus_TypeDef CAN_TransmitStatus ( CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox )

Checks the transmission of a message.

Parameters:
CAN_TransmitMailbox : the number of the mailbox that is used for transmission, can be on of CAN_TransmitMailBox_TypeDef.
Return values:
CAN_TxStatus_Ok if the CAN driver transmits the message, CAN_TxStatus_Failed in an other case.

Definition at line 672 of file stm8s_can.c.

References CAN_TPR_TME0, CAN_TPR_TME1, CAN_TPR_TME2, CAN_TransmitMailBox_0, CAN_TransmitMailBox_1, CAN_TransmitMailBox_2, CAN_TSR_RQCP0, CAN_TSR_RQCP1, CAN_TSR_RQCP2, CAN_TSR_TXOK0, CAN_TSR_TXOK1, CAN_TSR_TXOK2, CAN_TxStatus_Failed, CAN_TxStatus_MailBoxEmpty, CAN_TxStatus_Ok, CAN_TxStatus_Pending, and IS_CAN_TRANSMITMAILBOX_OK.

void CAN_TTComModeCmd ( FunctionalState NewState )

Enables or disables the CAN Time TriggerOperation communication mode.

Parameters:
NewState : Mode new state , can be one of FunctionalState
Return values:
None

Definition at line 541 of file stm8s_can.c.

References CAN_GetSelectedPage(), CAN_MCR_TTCM, CAN_MDLCR_TGT, CAN_Page_RxFifo, CAN_Page_TxMailBox0, CAN_Page_TxMailBox1, CAN_Page_TxMailBox2, CAN_SelectPage(), DISABLE, and IS_FUNCTIONALSTATE_OK.

CAN_WakeUp_TypeDef CAN_WakeUp ( void )

Wakes the CAN up.

Parameters:
None
Return values:
CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed in an other case.

Definition at line 947 of file stm8s_can.c.

References CAN_MCR_SLEEP, CAN_MSR_SLAK, CAN_WakeUp_Failed, and CAN_WakeUp_Ok.


STM8S/A Standard Peripherals Drivers: CLK_Exported_Types

Enumerations
CLK_Exported_Types

Enumerations

enum | CLK_CSSConfig_TypeDef { CLK_CSSCONFIG_ENABLEWITHIT = (uint8_t)0x05, CLK_CSSCONFIG_ENABLE = (uint8_t)0x01, CLK_CSSCONFIG_DISABLE = (uint8_t)0x00 }
Clock security system configuration. More...
enum | CLK_CurrentClockState_TypeDef { CLK_CURRENTCLOCKSTATE_DISABLE = (uint8_t)0x00, CLK_CURRENTCLOCKSTATE_ENABLE = (uint8_t)0x01 }
Current Clock State. More...
enum CLK_Flag_TypeDef {
CLK_FLAG_LSIRDY = (uint16_t)0x0110, CLK_FLAG_HSIRDY = (uint16_t)0x0102, CLK_FLAG_HSERDY = (uint16_t)0x0202, CLK_FLAG_SWIF = (uint16_t)0x0308,
CLK_FLAG_SWBSY = (uint16_t)0x0301, CLK_FLAG_CSSD = (uint16_t)0x0408, CLK_FLAG_AUX = (uint16_t)0x0402, CLK_FLAG_CCOBSY = (uint16_t)0x0504,
CLK_FLAG_CCORDY = (uint16_t)0x0502
}
CLK Flags. More...
enum CLK_HSITrimValue_TypeDef {
CLK_HSITRIMVALUE_0 = (uint8_t)0x00, CLK_HSITRIMVALUE_1 = (uint8_t)0x01, CLK_HSITRIMVALUE_2 = (uint8_t)0x02, CLK_HSITRIMVALUE_3 = (uint8_t)0x03,
CLK_HSITRIMVALUE_4 = (uint8_t)0x04, CLK_HSITRIMVALUE_5 = (uint8_t)0x05, CLK_HSITRIMVALUE_6 = (uint8_t)0x06, CLK_HSITRIMVALUE_7 = (uint8_t)0x07
}
CLK HSI Calibration Value. More...
enum | CLK_IT_TypeDef { CLK_IT_CSSD = (uint8_t)0x0C, CLK_IT_SWIF = (uint8_t)0x1C }
CLK interrupt configuration and Flags cleared by software. More...
enum CLK_Output_TypeDef {
CLK_OUTPUT_HSI = (uint8_t)0x00, CLK_OUTPUT_LSI = (uint8_t)0x02, CLK_OUTPUT_HSE = (uint8_t)0x04, CLK_OUTPUT_CPU = (uint8_t)0x08,
CLK_OUTPUT_CPUDIV2 = (uint8_t)0x0A, CLK_OUTPUT_CPUDIV4 = (uint8_t)0x0C, CLK_OUTPUT_CPUDIV8 = (uint8_t)0x0E, CLK_OUTPUT_CPUDIV16 = (uint8_t)0x10,
CLK_OUTPUT_CPUDIV32 = (uint8_t)0x12, CLK_OUTPUT_CPUDIV64 = (uint8_t)0x14, CLK_OUTPUT_HSIRC = (uint8_t)0x16, CLK_OUTPUT_MASTER = (uint8_t)0x18,
CLK_OUTPUT_OTHERS = (uint8_t)0x1A
}
CLK Clock Output. More...
enum CLK_Peripheral_TypeDef {
CLK_PERIPHERAL_I2C = (uint8_t)0x00, CLK_PERIPHERAL_SPI = (uint8_t)0x01, CLK_PERIPHERAL_UART1 = (uint8_t)0x03, CLK_PERIPHERAL_UART2 = (uint8_t)0x03,
CLK_PERIPHERAL_UART3 = (uint8_t)0x03, CLK_PERIPHERAL_TIMER6 = (uint8_t)0x04, CLK_PERIPHERAL_TIMER4 = (uint8_t)0x04, CLK_PERIPHERAL_TIMER5 = (uint8_t)0x05,
CLK_PERIPHERAL_TIMER2 = (uint8_t)0x05, CLK_PERIPHERAL_TIMER3 = (uint8_t)0x06, CLK_PERIPHERAL_TIMER1 = (uint8_t)0x07, CLK_PERIPHERAL_AWU = (uint8_t)0x12,
CLK_PERIPHERAL_ADC = (uint8_t)0x13, CLK_PERIPHERAL_CAN = (uint8_t)0x17
}
CLK Enable peripheral. More...
enum CLK_Prescaler_TypeDef {
CLK_PRESCALER_HSIDIV1 = (uint8_t)0x00, CLK_PRESCALER_HSIDIV2 = (uint8_t)0x08, CLK_PRESCALER_HSIDIV4 = (uint8_t)0x10, CLK_PRESCALER_HSIDIV8 = (uint8_t)0x18,
CLK_PRESCALER_CPUDIV1 = (uint8_t)0x80, CLK_PRESCALER_CPUDIV2 = (uint8_t)0x81, CLK_PRESCALER_CPUDIV4 = (uint8_t)0x82, CLK_PRESCALER_CPUDIV8 = (uint8_t)0x83,
CLK_PRESCALER_CPUDIV16 = (uint8_t)0x84, CLK_PRESCALER_CPUDIV32 = (uint8_t)0x85, CLK_PRESCALER_CPUDIV64 = (uint8_t)0x86, CLK_PRESCALER_CPUDIV128 = (uint8_t)0x87
}
CLK Clock Divisor. More...
enum | CLK_Source_TypeDef { CLK_SOURCE_HSI = (uint8_t)0xE1, CLK_SOURCE_LSI = (uint8_t)0xD2, CLK_SOURCE_HSE = (uint8_t)0xB4 }
CLK Clock Source. More...
enum | CLK_SWIMDivider_TypeDef { CLK_SWIMDIVIDER_2 = (uint8_t)0x00, CLK_SWIMDIVIDER_OTHER = (uint8_t)0x01 }
SWIM Clock divider. More...
enum | CLK_SwitchMode_TypeDef { CLK_SWITCHMODE_MANUAL = (uint8_t)0x00, CLK_SWITCHMODE_AUTO = (uint8_t)0x01 }
Switch Mode Auto, Manual. More...

Enumeration Type Documentation

enum CLK_CSSConfig_TypeDef

Clock security system configuration.

Enumerator:
CLK_CSSCONFIG_ENABLEWITHIT

Enable CSS with detection interrupt

CLK_CSSCONFIG_ENABLE

Enable CSS without detection interrupt

CLK_CSSCONFIG_DISABLE

Leave CSS desactivated (to be used in CLK_Init() function)

Definition at line 61 of file stm8s_clk.h.

enum CLK_CurrentClockState_TypeDef

Current Clock State.

Enumerator:
CLK_CURRENTCLOCKSTATE_DISABLE

Current clock disable

CLK_CURRENTCLOCKSTATE_ENABLE

Current clock enable

Definition at line 53 of file stm8s_clk.h.

enum CLK_Flag_TypeDef

CLK Flags.

Enumerator:
CLK_FLAG_LSIRDY

Low speed internal oscillator ready Flag

CLK_FLAG_HSIRDY

High speed internal oscillator ready Flag

CLK_FLAG_HSERDY

High speed external oscillator ready Flag

CLK_FLAG_SWIF

Clock switch interrupt Flag

CLK_FLAG_SWBSY

Switch busy Flag

CLK_FLAG_CSSD

Clock security system detection Flag

CLK_FLAG_AUX

Auxiliary oscillator connected to master clock

CLK_FLAG_CCOBSY

Configurable clock output busy

CLK_FLAG_CCORDY

Configurable clock output ready

Definition at line 151 of file stm8s_clk.h.

enum CLK_HSITrimValue_TypeDef

CLK HSI Calibration Value.

Enumerator:
CLK_HSITRIMVALUE_0

HSI Calibration Value 0

CLK_HSITRIMVALUE_1

HSI Calibration Value 1

CLK_HSITRIMVALUE_2

HSI Calibration Value 2

CLK_HSITRIMVALUE_3

HSI Calibration Value 3

CLK_HSITRIMVALUE_4

HSI Calibration Value 4

CLK_HSITRIMVALUE_5

HSI Calibration Value 5

CLK_HSITRIMVALUE_6

HSI Calibration Value 6

CLK_HSITRIMVALUE_7

HSI Calibration Value 7

Definition at line 79 of file stm8s_clk.h.

enum CLK_IT_TypeDef

CLK interrupt configuration and Flags cleared by software.

Enumerator:
CLK_IT_CSSD

Clock security system detection Flag

CLK_IT_SWIF

Clock switch interrupt Flag

Definition at line 166 of file stm8s_clk.h.

enum CLK_Output_TypeDef

CLK Clock Output.

Enumerator:
CLK_OUTPUT_HSI

Clock Output HSI

CLK_OUTPUT_LSI

Clock Output LSI

CLK_OUTPUT_HSE

Clock Output HSE

CLK_OUTPUT_CPU

Clock Output CPU

CLK_OUTPUT_CPUDIV2

Clock Output CPU/2

CLK_OUTPUT_CPUDIV4

Clock Output CPU/4

CLK_OUTPUT_CPUDIV8

Clock Output CPU/8

CLK_OUTPUT_CPUDIV16

Clock Output CPU/16

CLK_OUTPUT_CPUDIV32

Clock Output CPU/32

CLK_OUTPUT_CPUDIV64

Clock Output CPU/64

CLK_OUTPUT_HSIRC

Clock Output HSI RC

CLK_OUTPUT_MASTER

Clock Output Master

CLK_OUTPUT_OTHERS

Clock Output OTHER

Definition at line 93 of file stm8s_clk.h.

enum CLK_Peripheral_TypeDef

CLK Enable peripheral.

Enumerator:
CLK_PERIPHERAL_I2C

Peripheral Clock Enable 1, I2C

CLK_PERIPHERAL_SPI

Peripheral Clock Enable 1, SPI

CLK_PERIPHERAL_UART1

Peripheral Clock Enable 1, UART1

CLK_PERIPHERAL_UART2

Peripheral Clock Enable 1, UART2

CLK_PERIPHERAL_UART3

Peripheral Clock Enable 1, UART3

CLK_PERIPHERAL_TIMER6

Peripheral Clock Enable 1, Timer6

CLK_PERIPHERAL_TIMER4

Peripheral Clock Enable 1, Timer4

CLK_PERIPHERAL_TIMER5

Peripheral Clock Enable 1, Timer5

CLK_PERIPHERAL_TIMER2

Peripheral Clock Enable 1, Timer2

CLK_PERIPHERAL_TIMER3

Peripheral Clock Enable 1, Timer3

CLK_PERIPHERAL_TIMER1

Peripheral Clock Enable 1, Timer1

CLK_PERIPHERAL_AWU

Peripheral Clock Enable 2, AWU

CLK_PERIPHERAL_ADC

Peripheral Clock Enable 2, ADC

CLK_PERIPHERAL_CAN

Peripheral Clock Enable 2, CAN

Definition at line 118 of file stm8s_clk.h.

enum CLK_Prescaler_TypeDef

CLK Clock Divisor.

Enumerator:
CLK_PRESCALER_HSIDIV1

High speed internal clock prescaler: 1

CLK_PRESCALER_HSIDIV2

High speed internal clock prescaler: 2

CLK_PRESCALER_HSIDIV4

High speed internal clock prescaler: 4

CLK_PRESCALER_HSIDIV8

High speed internal clock prescaler: 8

CLK_PRESCALER_CPUDIV1

CPU clock division factors 1

CLK_PRESCALER_CPUDIV2

CPU clock division factors 2

CLK_PRESCALER_CPUDIV4

CPU clock division factors 4

CLK_PRESCALER_CPUDIV8

CPU clock division factors 8

CLK_PRESCALER_CPUDIV16

CPU clock division factors 16

CLK_PRESCALER_CPUDIV32

CPU clock division factors 32

CLK_PRESCALER_CPUDIV64

CPU clock division factors 64

CLK_PRESCALER_CPUDIV128

CPU clock division factors 128

Definition at line 180 of file stm8s_clk.h.

enum CLK_Source_TypeDef

CLK Clock Source.

Enumerator:
CLK_SOURCE_HSI

Clock Source HSI.

CLK_SOURCE_LSI

Clock Source LSI.

CLK_SOURCE_HSE

Clock Source HSE.

Definition at line 70 of file stm8s_clk.h.

enum CLK_SWIMDivider_TypeDef

SWIM Clock divider.

Enumerator:
CLK_SWIMDIVIDER_2

SWIM clock is divided by 2

CLK_SWIMDIVIDER_OTHER

SWIM clock is not divided by 2

Definition at line 198 of file stm8s_clk.h.

enum CLK_SwitchMode_TypeDef

Switch Mode Auto, Manual.

Enumerator:
CLK_SWITCHMODE_MANUAL

Enable the manual clock switching mode

CLK_SWITCHMODE_AUTO

Enable the automatic clock switching mode

Definition at line 45 of file stm8s_clk.h.


STM8S/A Standard Peripherals Drivers: CLK_Exported_Constants

Defines
CLK_Exported_Constants

Defines

#define CLK_TIMEOUT ((uint16_t)0xFFFF)

Define Documentation

#define CLK_TIMEOUT ((uint16_t)0xFFFF)

Max Timeout for the clock switch operation.

Definition at line 212 of file stm8s_clk.h.

Referenced by CLK_ClockSwitchConfig().


STM8S/A Standard Peripherals Drivers: CLK_Private_Macros

Defines
CLK_Private_Macros

Defines

#define | IS_CLK_CSSCONFIG_OK(CSSVALUE)
Macros used by the assert function in order to check the CSS configuration.
#define | IS_CLK_CURRENTCLOCKSTATE_OK(STATE)
Macros used by the assert function in order to check the current clock state.
#define | IS_CLK_FLAG_OK(FLAG)
Macros used by the assert function in order to check the different clock flags.
#define | IS_CLK_HSIPRESCALER_OK(PRESCALER)
Macros used by the assert function in order to check the different HSI prescaler values.
#define | IS_CLK_HSITRIMVALUE_OK(TRIMVALUE)
Macros used by the assert function in order to check the different HSI trimming values.
#define | IS_CLK_IT_OK(IT) (((IT) == CLK_IT_CSSD) || ((IT) == CLK_IT_SWIF))
Macros used by the assert function in order to check the different clock IT pending bits.
#define | IS_CLK_OUTPUT_OK(OUTPUT)
Macros used by the assert function in order to check the different clocks to output.
#define | IS_CLK_PERIPHERAL_OK(PERIPHERAL)
Macros used by the assert function in order to check the different peripheral's clock.
#define | IS_CLK_PRESCALER_OK(PRESCALER)
Macros used by the assert function in order to check the different clock prescaler values.
#define | IS_CLK_SOURCE_OK(SOURCE)
Macros used by the assert function in order to check the different clock sources.
#define | IS_CLK_SWIMDIVIDER_OK(SWIMDIVIDER) (((SWIMDIVIDER) == CLK_SWIMDIVIDER_2) || ((SWIMDIVIDER) == CLK_SWIMDIVIDER_OTHER))
Macros used by the assert function in order to check the different SWIM dividers values.
#define | IS_CLK_SWITCHMODE_OK(MODE) (((MODE) == CLK_SWITCHMODE_MANUAL) || ((MODE) == CLK_SWITCHMODE_AUTO))
Macros used by the assert function in order to check the different functions parameters.

Define Documentation

#define IS_CLK_CSSCONFIG_OK ( CSSVALUE )
Value:
(((CSSVALUE) == CLK_CSSCONFIG_ENABLEWITHIT) ||\
                                       ((CSSVALUE) == CLK_CSSCONFIG_ENABLE) ||\
                                       ((CSSVALUE) == CLK_CSSCONFIG_DISABLE))

Macros used by the assert function in order to check the CSS configuration.

Definition at line 240 of file stm8s_clk.h.

#define IS_CLK_CURRENTCLOCKSTATE_OK ( STATE )
Value:
(((STATE) == CLK_CURRENTCLOCKSTATE_DISABLE) ||\
                                            ((STATE) == CLK_CURRENTCLOCKSTATE_ENABLE))

Macros used by the assert function in order to check the current clock state.

Definition at line 234 of file stm8s_clk.h.

Referenced by CLK_ClockSwitchConfig().

#define IS_CLK_FLAG_OK ( FLAG )
Value:
(((FLAG) == CLK_FLAG_LSIRDY) ||\
                              ((FLAG) == CLK_FLAG_HSIRDY) ||\
                              ((FLAG) == CLK_FLAG_HSERDY) ||\
                              ((FLAG) == CLK_FLAG_SWIF) ||\
                              ((FLAG) == CLK_FLAG_SWBSY) ||\
                              ((FLAG) == CLK_FLAG_CSSD) ||\
                              ((FLAG) == CLK_FLAG_AUX) ||\
                              ((FLAG) == CLK_FLAG_CCOBSY) ||\
                              ((FLAG) == CLK_FLAG_CCORDY))

Macros used by the assert function in order to check the different clock flags.

Definition at line 301 of file stm8s_clk.h.

Referenced by CLK_GetFlagStatus().

#define IS_CLK_HSIPRESCALER_OK ( PRESCALER )
Value:
(((PRESCALER) == CLK_PRESCALER_HSIDIV1) ||\
    ((PRESCALER) == CLK_PRESCALER_HSIDIV2) ||\
    ((PRESCALER) == CLK_PRESCALER_HSIDIV4) ||\
    ((PRESCALER) == CLK_PRESCALER_HSIDIV8))

Macros used by the assert function in order to check the different HSI prescaler values.

Definition at line 319 of file stm8s_clk.h.

Referenced by CLK_HSIPrescalerConfig().

#define IS_CLK_HSITRIMVALUE_OK ( TRIMVALUE )
Value:
(((TRIMVALUE) == CLK_HSITRIMVALUE_0) ||\
    ((TRIMVALUE) == CLK_HSITRIMVALUE_1) ||\
    ((TRIMVALUE) == CLK_HSITRIMVALUE_2) ||\
    ((TRIMVALUE) == CLK_HSITRIMVALUE_3) ||\
    ((TRIMVALUE) == CLK_HSITRIMVALUE_4) ||\
    ((TRIMVALUE) == CLK_HSITRIMVALUE_5) ||\
    ((TRIMVALUE) == CLK_HSITRIMVALUE_6) ||\
    ((TRIMVALUE) == CLK_HSITRIMVALUE_7))

Macros used by the assert function in order to check the different HSI trimming values.

Definition at line 254 of file stm8s_clk.h.

Referenced by CLK_AdjustHSICalibrationValue().

#define IS_CLK_IT_OK ( IT ) (((IT) == CLK_IT_CSSD) || ((IT) == CLK_IT_SWIF))

Macros used by the assert function in order to check the different clock IT pending bits.

Definition at line 314 of file stm8s_clk.h.

Referenced by CLK_ClearITPendingBit(), CLK_GetITStatus(), and CLK_ITConfig().

#define IS_CLK_OUTPUT_OK ( OUTPUT )
Value:
(((OUTPUT) == CLK_OUTPUT_HSI) ||\
                                  ((OUTPUT) == CLK_OUTPUT_HSE) ||\
                                  ((OUTPUT) == CLK_OUTPUT_LSI) ||\
                                  ((OUTPUT) == CLK_OUTPUT_CPU) ||\
                                  ((OUTPUT) == CLK_OUTPUT_CPUDIV2) ||\
                                  ((OUTPUT) == CLK_OUTPUT_CPUDIV4) ||\
                                  ((OUTPUT) == CLK_OUTPUT_CPUDIV8) ||\
                                  ((OUTPUT) == CLK_OUTPUT_CPUDIV16) ||\
                                  ((OUTPUT) == CLK_OUTPUT_CPUDIV32) ||\
                                  ((OUTPUT) == CLK_OUTPUT_CPUDIV64) ||\
                                  ((OUTPUT) == CLK_OUTPUT_HSIRC) ||\
                                  ((OUTPUT) == CLK_OUTPUT_MASTER) ||\
                                  ((OUTPUT) == CLK_OUTPUT_OTHERS))

Macros used by the assert function in order to check the different clocks to output.

Definition at line 266 of file stm8s_clk.h.

Referenced by CLK_CCOConfig().

#define IS_CLK_PERIPHERAL_OK ( PERIPHERAL )
Value:
(((PERIPHERAL) == CLK_PERIPHERAL_I2C) ||\
    ((PERIPHERAL) == CLK_PERIPHERAL_SPI) ||\
    ((PERIPHERAL) == CLK_PERIPHERAL_UART3) ||\
    ((PERIPHERAL) == CLK_PERIPHERAL_UART2) ||\
    ((PERIPHERAL) == CLK_PERIPHERAL_UART1) ||\
    ((PERIPHERAL) == CLK_PERIPHERAL_TIMER4) ||\
    ((PERIPHERAL) == CLK_PERIPHERAL_TIMER2) ||\
    ((PERIPHERAL) == CLK_PERIPHERAL_TIMER5) ||\
    ((PERIPHERAL) == CLK_PERIPHERAL_TIMER6) ||\
    ((PERIPHERAL) == CLK_PERIPHERAL_TIMER3) ||\
    ((PERIPHERAL) == CLK_PERIPHERAL_TIMER1) ||\
    ((PERIPHERAL) == CLK_PERIPHERAL_CAN) ||\
    ((PERIPHERAL) == CLK_PERIPHERAL_ADC) ||\
    ((PERIPHERAL) == CLK_PERIPHERAL_AWU))

Macros used by the assert function in order to check the different peripheral's clock.

Definition at line 283 of file stm8s_clk.h.

Referenced by CLK_PeripheralClockConfig().

#define IS_CLK_PRESCALER_OK ( PRESCALER )
Value:
(((PRESCALER) == CLK_PRESCALER_HSIDIV1) ||\
                                        ((PRESCALER) == CLK_PRESCALER_HSIDIV2) ||\
                                        ((PRESCALER) == CLK_PRESCALER_HSIDIV4) ||\
                                        ((PRESCALER) == CLK_PRESCALER_HSIDIV8) ||\
                                        ((PRESCALER) == CLK_PRESCALER_CPUDIV1) ||\
                                        ((PRESCALER) == CLK_PRESCALER_CPUDIV2) ||\
                                        ((PRESCALER) == CLK_PRESCALER_CPUDIV4) ||\
                                        ((PRESCALER) == CLK_PRESCALER_CPUDIV8) ||\
                                        ((PRESCALER) == CLK_PRESCALER_CPUDIV16) ||\
                                        ((PRESCALER) == CLK_PRESCALER_CPUDIV32) ||\
                                        ((PRESCALER) == CLK_PRESCALER_CPUDIV64) ||\
                                        ((PRESCALER) == CLK_PRESCALER_CPUDIV128))

Macros used by the assert function in order to check the different clock prescaler values.

Definition at line 327 of file stm8s_clk.h.

Referenced by CLK_SYSCLKConfig().

#define IS_CLK_SOURCE_OK ( SOURCE )
Value:
(((SOURCE) == CLK_SOURCE_HSI) ||\
                                  ((SOURCE) == CLK_SOURCE_LSI) ||\
                                  ((SOURCE) == CLK_SOURCE_HSE))

Macros used by the assert function in order to check the different clock sources.

Definition at line 247 of file stm8s_clk.h.

Referenced by CLK_ClockSwitchConfig().

#define IS_CLK_SWIMDIVIDER_OK ( SWIMDIVIDER ) (((SWIMDIVIDER) == CLK_SWIMDIVIDER_2) || ((SWIMDIVIDER) == CLK_SWIMDIVIDER_OTHER))

Macros used by the assert function in order to check the different SWIM dividers values.

Definition at line 343 of file stm8s_clk.h.

Referenced by CLK_SWIMConfig().

#define IS_CLK_SWITCHMODE_OK ( MODE ) (((MODE) == CLK_SWITCHMODE_MANUAL) || ((MODE) == CLK_SWITCHMODE_AUTO))

Macros used by the assert function in order to check the different functions parameters.

Macros used by the assert function in order to check the clock switching modes.

Definition at line 229 of file stm8s_clk.h.

Referenced by CLK_ClockSwitchConfig().


STM8S/A Standard Peripherals Drivers: CLK_Exported_functions

Functions
CLK_Exported_functions

Functions

void | CLK_AdjustHSICalibrationValue (CLK_HSITrimValue_TypeDef CLK_HSICalibrationValue)
Adjusts the Internal High Speed oscillator (HSI) calibration value.
void | CLK_CCOCmd (FunctionalState NewState)
Enables or disablle the Configurable Clock Output (CCO).
void | CLK_CCOConfig (CLK_Output_TypeDef CLK_CCO)
Output the selected clock on a dedicated I/O pin.
void | CLK_ClearITPendingBit (CLK_IT_TypeDef CLK_IT)
Clears the CLK’s interrupt pending bits.
void | CLK_ClockSecuritySystemEnable (void)
Enables the Clock Security System.
void | CLK_ClockSwitchCmd (FunctionalState NewState)
Starts or Stops manually the clock switch execution.
ErrorStatus | CLK_ClockSwitchConfig (CLK_SwitchMode_TypeDef CLK_SwitchMode, CLK_Source_TypeDef CLK_NewClock, FunctionalState ITState, CLK_CurrentClockState_TypeDef CLK_CurrentClockState)
configures the Switch from one clock to another
void | CLK_DeInit (void)
Deinitializes the CLK peripheral registers to their default reset values.
void | CLK_FastHaltWakeUpCmd (FunctionalState NewState)
Configures the High Speed Internal oscillator (HSI).
uint32_t | CLK_GetClockFreq (void)
This function returns the frequencies of different on chip clocks.
FlagStatus | CLK_GetFlagStatus (CLK_Flag_TypeDef CLK_FLAG)
Checks whether the specified CLK flag is set or not.
ITStatus | CLK_GetITStatus (CLK_IT_TypeDef CLK_IT)
Checks whether the specified CLK interrupt has is enabled or not.
CLK_Source_TypeDef | CLK_GetSYSCLKSource (void)
Returns the clock source used as system clock.
void | CLK_HSECmd (FunctionalState NewState)
Enable or Disable the External High Speed oscillator (HSE).
void | CLK_HSICmd (FunctionalState NewState)
Enables or disables the Internal High Speed oscillator (HSI).
void | CLK_HSIPrescalerConfig (CLK_Prescaler_TypeDef HSIPrescaler)
Configures the HSI clock dividers.
void | CLK_ITConfig (CLK_IT_TypeDef CLK_IT, FunctionalState NewState)
Enables or disables the specified CLK interrupts.
void | CLK_LSICmd (FunctionalState NewState)
Enables or disables the Internal Low Speed oscillator (LSI).
void | CLK_PeripheralClockConfig (CLK_Peripheral_TypeDef CLK_Peripheral, FunctionalState NewState)
Enables or disables the specified peripheral CLK.
void | CLK_SlowActiveHaltWakeUpCmd (FunctionalState NewState)
Configures the slow active halt wake up.
void | CLK_SWIMConfig (CLK_SWIMDivider_TypeDef CLK_SWIMDivider)
Configures the SWIM clock frequency on the fly.
void | CLK_SYSCLKConfig (CLK_Prescaler_TypeDef CLK_Prescaler)
Configures the HSI and CPU clock dividers.
void | CLK_SYSCLKEmergencyClear (void)
Reset the SWBSY flag (SWICR Register)

Function Documentation

void CLK_AdjustHSICalibrationValue ( CLK_HSITrimValue_TypeDef CLK_HSICalibrationValue )

Adjusts the Internal High Speed oscillator (HSI) calibration value.

Full description:
Parameters:
CLK_HSICalibrationValue calibration trimming value. can be one of the values of CLK_HSITrimValue_TypeDef
Return values:
None

Definition at line 604 of file stm8s_clk.c.

References CLK, CLK_HSITRIMR_HSITRIM, and IS_CLK_HSITRIMVALUE_OK.

void CLK_CCOCmd ( FunctionalState NewState )

Enables or disablle the Configurable Clock Output (CCO).

Parameters:
NewState : New state of CCEN bit (CCO register). This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 189 of file stm8s_clk.c.

References CLK, CLK_CCOR_CCOEN, DISABLE, and IS_FUNCTIONALSTATE_OK.

void CLK_CCOConfig ( CLK_Output_TypeDef CLK_CCO )

Output the selected clock on a dedicated I/O pin.

Parameters:
CLK_CCO : Specifies the clock source. This parameter can be any of the CLK_Output_TypeDef enumeration.
Return values:
None
Required preconditions:
The dedicated I/O pin must be set at 1 in the corresponding Px_CR1 register
to be set as input with pull-up or push-pull output.

Definition at line 436 of file stm8s_clk.c.

References CLK, CLK_CCOR_CCOEN, CLK_CCOR_CCOSEL, and IS_CLK_OUTPUT_OK.

void CLK_ClearITPendingBit ( CLK_IT_TypeDef CLK_IT )

Clears the CLK’s interrupt pending bits.

Parameters:
CLK_IT specifies the interrupt pending bits. can be one of the values of CLK_IT_TypeDef
Return values:
None

Definition at line 729 of file stm8s_clk.c.

References CLK, CLK_CSSR_CSSD, CLK_IT_CSSD, CLK_SWCR_SWIF, and IS_CLK_IT_OK.

void CLK_ClockSecuritySystemEnable ( void )

Enables the Clock Security System.

Full description:
once CSS is enabled it cannot be disabled until the next reset.
Parameters:
None
Return values:
None

Definition at line 547 of file stm8s_clk.c.

References CLK, and CLK_CSSR_CSSEN.

void CLK_ClockSwitchCmd ( FunctionalState NewState )

Starts or Stops manually the clock switch execution.

Full description:
NewState parameter set the SWEN.
Parameters:
NewState new state of SWEN, value accepted ENABLE, DISABLE.
Return values:
None

Definition at line 213 of file stm8s_clk.c.

References CLK, CLK_SWCR_SWEN, DISABLE, and IS_FUNCTIONALSTATE_OK.

ErrorStatus CLK_ClockSwitchConfig | ( | CLK_SwitchMode_TypeDef | CLK_SwitchMode,
 |  | CLK_Source_TypeDef | CLK_NewClock,
 |  | FunctionalState | ITState,
 |  | CLK_CurrentClockState_TypeDef | CLK_CurrentClockState
 | ) |  |

configures the Switch from one clock to another

Parameters:
CLK_SwitchMode | select the clock switch mode. It can be set of the values of CLK_SwitchMode_TypeDef
CLK_NewClock | choice of the future clock. It can be set of the values of CLK_Source_TypeDef
ITState | Enable or Disable the Clock Switch interrupt.
CLK_CurrentClockState | current clock to switch OFF or to keep ON. It can be set of the values of CLK_CurrentClockState_TypeDef
Note:
LSI selected as master clock source only if LSI_EN option bit is set.
Return values:
ErrorStatus this shows the clock switch status (ERROR/SUCCESS).

Definition at line 309 of file stm8s_clk.c.

References CLK, CLK_CURRENTCLOCKSTATE_DISABLE, CLK_ECKR_HSEEN, CLK_ICKR_HSIEN, CLK_ICKR_LSIEN, CLK_SOURCE_HSE, CLK_SOURCE_HSI, CLK_SOURCE_LSI, CLK_SWCR_SWBSY, CLK_SWCR_SWEN, CLK_SWCR_SWIEN, CLK_SWCR_SWIF, CLK_SWITCHMODE_AUTO, CLK_TIMEOUT, DISABLE, ERROR, IS_CLK_CURRENTCLOCKSTATE_OK, IS_CLK_SOURCE_OK, IS_CLK_SWITCHMODE_OK, IS_FUNCTIONALSTATE_OK, and SUCCESS.

void CLK_DeInit ( void )

Deinitializes the CLK peripheral registers to their default reset values.

Parameters:
None
Return values:
None
Warning:
Resetting the CCOR register:
When the CCOEN bit is set, the reset of the CCOR register require two consecutive write instructions in order to reset first the CCOEN bit and the second one is to reset the CCOSEL bits.

Definition at line 72 of file stm8s_clk.c.

References CLK, CLK_CCOR_CCOEN, CLK_CCOR_RESET_VALUE, CLK_CKDIVR_RESET_VALUE, CLK_CSSR_RESET_VALUE, CLK_ECKR_RESET_VALUE, CLK_HSITRIMR_RESET_VALUE, CLK_ICKR_RESET_VALUE, CLK_PCKENR1_RESET_VALUE, CLK_PCKENR2_RESET_VALUE, CLK_SWCR_RESET_VALUE, CLK_SWIMCCR_RESET_VALUE, and CLK_SWR_RESET_VALUE.

void CLK_FastHaltWakeUpCmd ( FunctionalState NewState )

Configures the High Speed Internal oscillator (HSI).

Full description:
If CLK_FastHaltWakeup is enabled, HSI oscillator is automatically switched-on (HSIEN=1) and selected as next clock master (CKM=SWI=HSI) when resuming from HALT/ActiveHalt modes.
Parameters:
NewState this parameter is the Wake-up Mode state.
Return values:
None

Definition at line 99 of file stm8s_clk.c.

References CLK, CLK_ICKR_FHWU, DISABLE, and IS_FUNCTIONALSTATE_OK.

uint32_t CLK_GetClockFreq ( void )

This function returns the frequencies of different on chip clocks.

Parameters:
None
Return values:
the master clock frequency

Definition at line 569 of file stm8s_clk.c.

References CLK, CLK_CKDIVR_HSIDIV, CLK_SOURCE_HSI, CLK_SOURCE_LSI, HSE_VALUE, HSI_VALUE, HSIDivFactor, and LSI_VALUE.

Referenced by UART1_Init(), UART2_Init(), UART3_Init(), and UART4_Init().

FlagStatus CLK_GetFlagStatus ( CLK_Flag_TypeDef CLK_FLAG )

Checks whether the specified CLK flag is set or not.

Full description:
Parameters:
CLK_FLAG Flag to check. can be one of the values of CLK_Flag_TypeDef
Return values:
FlagStatus,status of the checked flag

Definition at line 634 of file stm8s_clk.c.

References CLK, IS_CLK_FLAG_OK, RESET, and SET.

ITStatus CLK_GetITStatus ( CLK_IT_TypeDef CLK_IT )

Checks whether the specified CLK interrupt has is enabled or not.

Parameters:
CLK_IT specifies the CLK interrupt. can be one of the values of CLK_IT_TypeDef
Return values:
ITStatus,new state of CLK_IT (SET or RESET).

Definition at line 687 of file stm8s_clk.c.

References CLK, CLK_IT_SWIF, IS_CLK_IT_OK, RESET, and SET.

CLK_Source_TypeDef CLK_GetSYSCLKSource ( void )

Returns the clock source used as system clock.

Parameters:
None
Return values:
Clock source used. can be one of the values of CLK_Source_TypeDef

Definition at line 559 of file stm8s_clk.c.

References CLK.

void CLK_HSECmd ( FunctionalState NewState )

Enable or Disable the External High Speed oscillator (HSE).

Parameters:
NewState new state of HSEEN, value accepted ENABLE, DISABLE.
Return values:
None

Definition at line 121 of file stm8s_clk.c.

References CLK, CLK_ECKR_HSEEN, DISABLE, and IS_FUNCTIONALSTATE_OK.

void CLK_HSICmd ( FunctionalState NewState )

Enables or disables the Internal High Speed oscillator (HSI).

Parameters:
NewState new state of HSIEN, value accepted ENABLE, DISABLE.
Return values:
None

Definition at line 143 of file stm8s_clk.c.

References CLK, CLK_ICKR_HSIEN, DISABLE, and IS_FUNCTIONALSTATE_OK.

void CLK_HSIPrescalerConfig ( CLK_Prescaler_TypeDef HSIPrescaler )

Configures the HSI clock dividers.

Parameters:
HSIPrescaler : Specifies the HSI clock divider to apply. This parameter can be any of the CLK_Prescaler_TypeDef enumeration.
Return values:
None

Definition at line 415 of file stm8s_clk.c.

References CLK, CLK_CKDIVR_HSIDIV, and IS_CLK_HSIPRESCALER_OK.

void CLK_ITConfig | ( | CLK_IT_TypeDef | CLK_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified CLK interrupts.

Parameters:
CLK_IT | This parameter specifies the interrupt sources. It can be one of the values of CLK_IT_TypeDef.
NewState | New state of the Interrupt. Value accepted ENABLE, DISABLE.
Return values:
None

Definition at line 459 of file stm8s_clk.c.

References CLK, CLK_CSSR_CSSDIE, CLK_IT_CSSD, CLK_IT_SWIF, CLK_SWCR_SWIEN, DISABLE, IS_CLK_IT_OK, and IS_FUNCTIONALSTATE_OK.

void CLK_LSICmd ( FunctionalState NewState )

Enables or disables the Internal Low Speed oscillator (LSI).

Parameters:
NewState new state of LSIEN, value accepted ENABLE, DISABLE.
Note:
Before using the LSI clock you have to enable the option bytes (LSI_EN option bit is set).
Return values:
None

Definition at line 166 of file stm8s_clk.c.

References CLK, CLK_ICKR_LSIEN, DISABLE, and IS_FUNCTIONALSTATE_OK.

void CLK_PeripheralClockConfig | ( | CLK_Peripheral_TypeDef | CLK_Peripheral,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified peripheral CLK.

Parameters:
CLK_Peripheral | : This parameter specifies the peripheral clock to gate. This parameter can be any of the CLK_Peripheral_TypeDef enumeration.
NewState | : New state of specified peripheral clock. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 263 of file stm8s_clk.c.

References CLK, DISABLE, IS_CLK_PERIPHERAL_OK, and IS_FUNCTIONALSTATE_OK.

void CLK_SlowActiveHaltWakeUpCmd ( FunctionalState NewState )

Configures the slow active halt wake up.

Parameters:
NewState,: specifies the Slow Active Halt wake up state. can be set of the following values:
  • DISABLE: Slow Active Halt mode disabled;
  • ENABLE: Slow Active Halt mode enabled.
Return values:
None

Definition at line 238 of file stm8s_clk.c.

References CLK, CLK_ICKR_SWUAH, DISABLE, and IS_FUNCTIONALSTATE_OK.

void CLK_SWIMConfig ( CLK_SWIMDivider_TypeDef CLK_SWIMDivider )

Configures the SWIM clock frequency on the fly.

Parameters:
CLK_SWIMDivider Specifies the SWIM clock divider to apply. can be one of the value of CLK_SWIMDivider_TypeDef
Return values:
None

Definition at line 523 of file stm8s_clk.c.

References CLK, CLK_SWIMCCR_SWIMDIV, CLK_SWIMDIVIDER_2, and IS_CLK_SWIMDIVIDER_OK.

void CLK_SYSCLKConfig ( CLK_Prescaler_TypeDef CLK_Prescaler )

Configures the HSI and CPU clock dividers.

Parameters:
CLK_Prescaler Specifies the HSI or CPU clock divider to apply.
Return values:
None

Definition at line 500 of file stm8s_clk.c.

References CLK, CLK_CKDIVR_CPUDIV, CLK_CKDIVR_HSIDIV, and IS_CLK_PRESCALER_OK.

void CLK_SYSCLKEmergencyClear ( void )

Reset the SWBSY flag (SWICR Register)

Full description:
This function reset SWBSY flag in order to reset clock switch operations (target oscillator is broken, stabilization is longing too much, etc.). If at the same time
software attempts to set SWEN and clear SWBSY, SWBSY action takes precedence.
Parameters:
None
Return values:
None

Definition at line 622 of file stm8s_clk.c.

References CLK, and CLK_SWCR_SWBSY.


STM8S/A Standard Peripherals Drivers: EXTI_Exported_Types

Enumerations
EXTI_Exported_Types

Enumerations

enum EXTI_Port_TypeDef {
EXTI_PORT_GPIOA = (uint8_t)0x00, EXTI_PORT_GPIOB = (uint8_t)0x01, EXTI_PORT_GPIOC = (uint8_t)0x02, EXTI_PORT_GPIOD = (uint8_t)0x03,
EXTI_PORT_GPIOE = (uint8_t)0x04
}
EXTI PortNum possible values. More...
enum | EXTI_Sensitivity_TypeDef { EXTI_SENSITIVITY_FALL_LOW = (uint8_t)0x00, EXTI_SENSITIVITY_RISE_ONLY = (uint8_t)0x01, EXTI_SENSITIVITY_FALL_ONLY = (uint8_t)0x02, EXTI_SENSITIVITY_RISE_FALL = (uint8_t)0x03 }
EXTI Sensitivity values for PORTA to PORTE. More...
enum | EXTI_TLISensitivity_TypeDef { EXTI_TLISENSITIVITY_FALL_ONLY = (uint8_t)0x00, EXTI_TLISENSITIVITY_RISE_ONLY = (uint8_t)0x04 }
EXTI Sensitivity values for TLI. More...

Enumeration Type Documentation

enum EXTI_Port_TypeDef

EXTI PortNum possible values.

Enumerator:
EXTI_PORT_GPIOA

GPIO Port A

EXTI_PORT_GPIOB

GPIO Port B

EXTI_PORT_GPIOC

GPIO Port C

EXTI_PORT_GPIOD

GPIO Port D

EXTI_PORT_GPIOE

GPIO Port E

Definition at line 62 of file stm8s_exti.h.

enum EXTI_Sensitivity_TypeDef

EXTI Sensitivity values for PORTA to PORTE.

Enumerator:
EXTI_SENSITIVITY_FALL_LOW

Interrupt on Falling edge and Low level

EXTI_SENSITIVITY_RISE_ONLY

Interrupt on Rising edge only

EXTI_SENSITIVITY_FALL_ONLY

Interrupt on Falling edge only

EXTI_SENSITIVITY_RISE_FALL

Interrupt on Rising and Falling edges

Definition at line 44 of file stm8s_exti.h.

enum EXTI_TLISensitivity_TypeDef

EXTI Sensitivity values for TLI.

Enumerator:
EXTI_TLISENSITIVITY_FALL_ONLY

Top Level Interrupt on Falling edge only

EXTI_TLISENSITIVITY_RISE_ONLY

Top Level Interrupt on Rising edge only

Definition at line 54 of file stm8s_exti.h.


STM8S/A Standard Peripherals Drivers: EXTI_Private_Macros

Defines
EXTI_Private_Macros

Defines

#define | IS_EXTI_PINMASK_OK(PinMask) ((((PinMask) & (uint8_t)0x00) == (uint8_t)0x00) && ((PinMask) != (uint8_t)0x00))
Macro used by the assert function in order to check the different values of the EXTI PinMask.
#define | IS_EXTI_PORT_OK(PORT)
Macro used by the assert function in order to check the different Port values.
#define | IS_EXTI_SENSITIVITY_OK(SensitivityValue)
Macro used by the assert function in order to check the different sensitivity values for PORTA to PORTE.
#define | IS_EXTI_TLISENSITIVITY_OK(SensitivityValue)
Macro used by the assert function in order to check the different sensitivity values for TLI.

Define Documentation

#define IS_EXTI_PINMASK_OK ( PinMask ) ((((PinMask) & (uint8_t)0x00) == (uint8_t)0x00) && ((PinMask) != (uint8_t)0x00))

Macro used by the assert function in order to check the different values of the EXTI PinMask.

Definition at line 109 of file stm8s_exti.h.

#define IS_EXTI_PORT_OK ( PORT )
Value:
(((PORT) == EXTI_PORT_GPIOA) ||\
   ((PORT) == EXTI_PORT_GPIOB) ||\
   ((PORT) == EXTI_PORT_GPIOC) ||\
   ((PORT) == EXTI_PORT_GPIOD) ||\
   ((PORT) == EXTI_PORT_GPIOE))

Macro used by the assert function in order to check the different Port values.

Definition at line 99 of file stm8s_exti.h.

Referenced by EXTI_GetExtIntSensitivity(), and EXTI_SetExtIntSensitivity().

#define IS_EXTI_SENSITIVITY_OK ( SensitivityValue )
Value:
(((SensitivityValue) == EXTI_SENSITIVITY_FALL_LOW) || \
   ((SensitivityValue) == EXTI_SENSITIVITY_RISE_ONLY) || \
   ((SensitivityValue) == EXTI_SENSITIVITY_FALL_ONLY) || \
   ((SensitivityValue) == EXTI_SENSITIVITY_RISE_FALL))

Macro used by the assert function in order to check the different sensitivity values for PORTA to PORTE.

Definition at line 83 of file stm8s_exti.h.

Referenced by EXTI_SetExtIntSensitivity().

#define IS_EXTI_TLISENSITIVITY_OK ( SensitivityValue )
Value:
(((SensitivityValue) == EXTI_TLISENSITIVITY_FALL_ONLY) || \
   ((SensitivityValue) == EXTI_TLISENSITIVITY_RISE_ONLY))

Macro used by the assert function in order to check the different sensitivity values for TLI.

Definition at line 92 of file stm8s_exti.h.

Referenced by EXTI_SetTLISensitivity().


STM8S/A Standard Peripherals Drivers: EXTI_Exported_Functions

Functions
EXTI_Exported_Functions

Functions

void | EXTI_DeInit (void)
Deinitializes the external interrupt control registers to their default reset value.
EXTI_Sensitivity_TypeDef | EXTI_GetExtIntSensitivity (EXTI_Port_TypeDef Port)
Get the external interrupt sensitivity of the selected port.
EXTI_TLISensitivity_TypeDef | EXTI_GetTLISensitivity (void)
Get the TLI interrupt sensitivity.
void | EXTI_SetExtIntSensitivity (EXTI_Port_TypeDef Port, EXTI_Sensitivity_TypeDef SensitivityValue)
Set the external interrupt sensitivity of the selected port.
void | EXTI_SetTLISensitivity (EXTI_TLISensitivity_TypeDef SensitivityValue)
Set the TLI interrupt sensitivity.

Function Documentation

void EXTI_DeInit ( void )

Deinitializes the external interrupt control registers to their default reset value.

Parameters:
None
Return values:
None

Definition at line 53 of file stm8s_exti.c.

References EXTI, EXTI_CR1_RESET_VALUE, and EXTI_CR2_RESET_VALUE.

EXTI_Sensitivity_TypeDef EXTI_GetExtIntSensitivity ( EXTI_Port_TypeDef Port )

Get the external interrupt sensitivity of the selected port.

Parameters:
Port The port number to access.
Return values:
EXTI_Sensitivity_TypeDef The external interrupt sensitivity of the selected port.

Definition at line 126 of file stm8s_exti.c.

References EXTI, EXTI_CR1_PAIS, EXTI_CR1_PBIS, EXTI_CR1_PCIS, EXTI_CR1_PDIS, EXTI_CR2_PEIS, EXTI_PORT_GPIOA, EXTI_PORT_GPIOB, EXTI_PORT_GPIOC, EXTI_PORT_GPIOD, EXTI_PORT_GPIOE, and IS_EXTI_PORT_OK.

EXTI_TLISensitivity_TypeDef EXTI_GetTLISensitivity ( void )

Get the TLI interrupt sensitivity.

Parameters:
None
Return values:
EXTI_TLISensitivity_TypeDef The TLI interrupt sensitivity read.

Definition at line 162 of file stm8s_exti.c.

References EXTI, and EXTI_CR2_TLIS.

void EXTI_SetExtIntSensitivity | ( | EXTI_Port_TypeDef | Port,
 |  | EXTI_Sensitivity_TypeDef | SensitivityValue
 | ) |  |

Set the external interrupt sensitivity of the selected port.

Warning:
  • The modification of external interrupt sensitivity is only possible when the interrupts are disabled.
  • The normal behavior is to disable the interrupts before calling this function, and re-enable them after.
Parameters:
Port | The port number to access.
SensitivityValue | The external interrupt sensitivity value to set.
Return values:
None
Required preconditions:
Global interrupts must be disabled before calling this function.

Definition at line 70 of file stm8s_exti.c.

References EXTI, EXTI_CR1_PAIS, EXTI_CR1_PBIS, EXTI_CR1_PCIS, EXTI_CR1_PDIS, EXTI_CR2_PEIS, EXTI_PORT_GPIOA, EXTI_PORT_GPIOB, EXTI_PORT_GPIOC, EXTI_PORT_GPIOD, EXTI_PORT_GPIOE, IS_EXTI_PORT_OK, and IS_EXTI_SENSITIVITY_OK.

void EXTI_SetTLISensitivity ( EXTI_TLISensitivity_TypeDef SensitivityValue )

Set the TLI interrupt sensitivity.

Parameters:
SensitivityValue The TLI interrupt sensitivity value.
Return values:
None
Required preconditions:
Global interrupts must be disabled before calling this function.

Definition at line 111 of file stm8s_exti.c.

References EXTI, EXTI_CR2_TLIS, and IS_EXTI_TLISENSITIVITY_OK.


STM8S/A Standard Peripherals Drivers: FLASH_Exported_Constants

Defines
FLASH_Exported_Constants

Defines

#define | FLASH_OPTIONBYTE_ERROR ((uint16_t)0x5555)
#define | FLASH_PROG_START_PHYSICAL_ADDRESS ((uint32_t)0x008000)
#define | FLASH_RASS_KEY1 ((uint8_t)0x56)
#define | FLASH_RASS_KEY2 ((uint8_t)0xAE)
#define | OPTION_BYTE_END_PHYSICAL_ADDRESS ((uint16_t)0x487F)
#define | OPTION_BYTE_START_PHYSICAL_ADDRESS ((uint16_t)0x4800)

Define Documentation

#define FLASH_OPTIONBYTE_ERROR ((uint16_t)0x5555)

Error code option byte (if value read is not equal to complement value read)

Definition at line 75 of file stm8s_flash.h.

Referenced by FLASH_ReadOptionByte().

#define FLASH_PROG_START_PHYSICAL_ADDRESS ((uint32_t)0x008000)

Program memory: start address

Definition at line 41 of file stm8s_flash.h.

#define FLASH_RASS_KEY1 ((uint8_t)0x56)

First RASS key

Definition at line 70 of file stm8s_flash.h.

Referenced by FLASH_Unlock().

#define FLASH_RASS_KEY2 ((uint8_t)0xAE)

Second RASS key

Definition at line 71 of file stm8s_flash.h.

Referenced by FLASH_Unlock().

#define OPTION_BYTE_END_PHYSICAL_ADDRESS ((uint16_t)0x487F)

Definition at line 74 of file stm8s_flash.h.

#define OPTION_BYTE_START_PHYSICAL_ADDRESS ((uint16_t)0x4800)

Definition at line 73 of file stm8s_flash.h.


STM8S/A Standard Peripherals Drivers: FLASH_Exported_Types

Enumerations
FLASH_Exported_Types

Enumerations

enum | FLASH_Flag_TypeDef { FLASH_FLAG_DUL = (uint8_t)0x08, FLASH_FLAG_EOP = (uint8_t)0x04, FLASH_FLAG_PUL = (uint8_t)0x02, FLASH_FLAG_WR_PG_DIS = (uint8_t)0x01 }
FLASH flags definition. More...
enum | FLASH_LPMode_TypeDef { FLASH_LPMODE_POWERDOWN = (uint8_t)0x04, FLASH_LPMODE_STANDBY = (uint8_t)0x08, FLASH_LPMODE_POWERDOWN_STANDBY = (uint8_t)0x00, FLASH_LPMODE_STANDBY_POWERDOWN = (uint8_t)0x0C }
FLASH Low Power mode select. More...
enum | FLASH_MemType_TypeDef { FLASH_MEMTYPE_PROG = (uint8_t)0xFD, FLASH_MEMTYPE_DATA = (uint8_t)0xF7 }
FLASH Memory types. More...
enum | FLASH_ProgramMode_TypeDef { FLASH_PROGRAMMODE_STANDARD = (uint8_t)0x00, FLASH_PROGRAMMODE_FAST = (uint8_t)0x10 }
FLASH programming modes. More...
enum | FLASH_ProgramTime_TypeDef { FLASH_PROGRAMTIME_STANDARD = (uint8_t)0x00, FLASH_PROGRAMTIME_TPROG = (uint8_t)0x01 }
FLASH fixed programming time. More...
enum | FLASH_Status_TypeDef { FLASH_STATUS_SUCCESSFUL_OPERATION = (uint8_t)0x04, FLASH_STATUS_TIMEOUT = (uint8_t)0x02, FLASH_STATUS_WRITE_PROTECTION_ERROR = (uint8_t)0x01 }
FLASH status of the last operation. More...

Enumeration Type Documentation

enum FLASH_Flag_TypeDef

FLASH flags definition.

  • Warning : FLAG value = mapping position register
Enumerator:
FLASH_FLAG_DUL

Data EEPROM unlocked flag

FLASH_FLAG_EOP

End of programming (write or erase operation) flag

FLASH_FLAG_PUL

Flash Program memory unlocked flag

FLASH_FLAG_WR_PG_DIS

Write attempted to protected page flag

Definition at line 139 of file stm8s_flash.h.

enum FLASH_LPMode_TypeDef

FLASH Low Power mode select.

Enumerator:
FLASH_LPMODE_POWERDOWN

HALT: Power-Down / ACTIVE-HALT: Power-Down

FLASH_LPMODE_STANDBY

HALT: Standby / ACTIVE-HALT: Standby

FLASH_LPMODE_POWERDOWN_STANDBY

HALT: Power-Down / ACTIVE-HALT: Standby

FLASH_LPMODE_STANDBY_POWERDOWN

HALT: Standby / ACTIVE-HALT: Power-Down

Definition at line 114 of file stm8s_flash.h.

enum FLASH_MemType_TypeDef

FLASH Memory types.

Enumerator:
FLASH_MEMTYPE_PROG

Program memory

FLASH_MEMTYPE_DATA

Data EEPROM memory

Definition at line 90 of file stm8s_flash.h.

enum FLASH_ProgramMode_TypeDef

FLASH programming modes.

Enumerator:
FLASH_PROGRAMMODE_STANDARD

Standard programming mode

FLASH_PROGRAMMODE_FAST

Fast programming mode

Definition at line 98 of file stm8s_flash.h.

enum FLASH_ProgramTime_TypeDef

FLASH fixed programming time.

Enumerator:
FLASH_PROGRAMTIME_STANDARD

Standard programming time fixed at 1/2 tprog

FLASH_PROGRAMTIME_TPROG

Programming time fixed at tprog

Definition at line 106 of file stm8s_flash.h.

enum FLASH_Status_TypeDef

FLASH status of the last operation.

Enumerator:
FLASH_STATUS_SUCCESSFUL_OPERATION

End of operation flag

FLASH_STATUS_TIMEOUT

Time out error

FLASH_STATUS_WRITE_PROTECTION_ERROR

Write attempted to protected page

Definition at line 125 of file stm8s_flash.h.


STM8S/A Standard Peripherals Drivers: FLASH_Private_Macros

Defines
FLASH_Private_Macros

Macros used by the assert function in order to check the different functions parameters. More...

Defines

#define | IS_FLASH_ADDRESS_OK(ADDRESS)
Macro used by the assert function in order to check the different sensitivity values for the data eeprom and flash program Address.
#define | IS_FLASH_DATA_ADDRESS_OK(ADDRESS)
Macro used by the assert function in order to check the different sensitivity values for the data eeprom Address.
#define | IS_FLASH_DATA_BLOCK_NUMBER_OK(BLOCKNUM) ((BLOCKNUM) < FLASH_DATA_BLOCKS_NUMBER)
Macro used by the assert function in order to check the different sensitivity values for the data eeprom Block number.
#define | IS_FLASH_FLAGS_OK(FLAG)
Macro used by the assert function in order to check the different flags values.
#define | IS_FLASH_LOW_POWER_MODE_OK(LPMODE)
Macro used by the assert function in order to check the different sensitivity values for the low power mode.
#define | IS_FLASH_PROG_ADDRESS_OK(ADDRESS)
Macro used by the assert function in order to check the different sensitivity values for the flash program Address.
#define | IS_FLASH_PROG_BLOCK_NUMBER_OK(BLOCKNUM) ((BLOCKNUM) < FLASH_PROG_BLOCKS_NUMBER)
Macro used by the assert function in order to check the different sensitivity values for the flash program Block number.
#define | IS_FLASH_PROGRAM_MODE_OK(MODE)
Macro used by the assert function in order to check the different sensitivity values for the flash program mode.
#define | IS_FLASH_PROGRAM_TIME_OK(TIME)
Macro used by the assert function in order to check the program time mode.
#define | IS_MEMORY_TYPE_OK(MEMTYPE)
Macro used by the assert function in order to check the different sensitivity values for the flash memory type.
#define | IS_OPTION_BYTE_ADDRESS_OK(ADDRESS)
Macro used by the assert function in order to check the different sensitivity values for the option bytes Address.

Detailed Description

Macros used by the assert function in order to check the different functions parameters.

Define Documentation

#define IS_FLASH_ADDRESS_OK ( ADDRESS )
Value:
((((ADDRESS) >= FLASH_PROG_START_PHYSICAL_ADDRESS) && ((ADDRESS) <= FLASH_PROG_END_PHYSICAL_ADDRESS)) || \
                                     (((ADDRESS) >= FLASH_DATA_START_PHYSICAL_ADDRESS) && ((ADDRESS) <= FLASH_DATA_END_PHYSICAL_ADDRESS)))

Macro used by the assert function in order to check the different sensitivity values for the data eeprom and flash program Address.

Definition at line 179 of file stm8s_flash.h.

Referenced by FLASH_EraseByte(), FLASH_ProgramByte(), FLASH_ProgramWord(), and FLASH_ReadByte().

#define IS_FLASH_DATA_ADDRESS_OK ( ADDRESS )
Value:
(((ADDRESS) >= FLASH_DATA_START_PHYSICAL_ADDRESS) && \
    ((ADDRESS) <= FLASH_DATA_END_PHYSICAL_ADDRESS))

Macro used by the assert function in order to check the different sensitivity values for the data eeprom Address.

Definition at line 173 of file stm8s_flash.h.

#define IS_FLASH_DATA_BLOCK_NUMBER_OK ( BLOCKNUM ) ((BLOCKNUM) < FLASH_DATA_BLOCKS_NUMBER)

Macro used by the assert function in order to check the different sensitivity values for the data eeprom Block number.

Definition at line 190 of file stm8s_flash.h.

#define IS_FLASH_FLAGS_OK ( FLAG )
Value:
(((FLAG) == FLASH_FLAG_DUL) || \
                                 ((FLAG) == FLASH_FLAG_EOP) || \
                                 ((FLAG) == FLASH_FLAG_PUL) || \
                                 ((FLAG) == FLASH_FLAG_WR_PG_DIS))

Macro used by the assert function in order to check the different flags values.

Definition at line 242 of file stm8s_flash.h.

Referenced by FLASH_GetFlagStatus().

#define IS_FLASH_LOW_POWER_MODE_OK ( LPMODE )
Value:
(((LPMODE) == FLASH_LPMODE_POWERDOWN) || \
    ((LPMODE) == FLASH_LPMODE_STANDBY) || \
    ((LPMODE) == FLASH_LPMODE_POWERDOWN_STANDBY) || \
    ((LPMODE) == FLASH_LPMODE_STANDBY_POWERDOWN))

Macro used by the assert function in order to check the different sensitivity values for the low power mode.

Definition at line 218 of file stm8s_flash.h.

Referenced by FLASH_SetLowPowerMode().

#define IS_FLASH_PROG_ADDRESS_OK ( ADDRESS )
Value:
(((ADDRESS) >= FLASH_PROG_START_PHYSICAL_ADDRESS) && \
    ((ADDRESS) <= FLASH_PROG_END_PHYSICAL_ADDRESS))

Macro used by the assert function in order to check the different sensitivity values for the flash program Address.

Definition at line 166 of file stm8s_flash.h.

#define IS_FLASH_PROG_BLOCK_NUMBER_OK ( BLOCKNUM ) ((BLOCKNUM) < FLASH_PROG_BLOCKS_NUMBER)

Macro used by the assert function in order to check the different sensitivity values for the flash program Block number.

Definition at line 185 of file stm8s_flash.h.

#define IS_FLASH_PROGRAM_MODE_OK ( MODE )
Value:
(((MODE) == FLASH_PROGRAMMODE_STANDARD) || \
                                        ((MODE) == FLASH_PROGRAMMODE_FAST))

Macro used by the assert function in order to check the different sensitivity values for the flash program mode.

Definition at line 203 of file stm8s_flash.h.

#define IS_FLASH_PROGRAM_TIME_OK ( TIME )
Value:
(((TIME) == FLASH_PROGRAMTIME_STANDARD) || \
                                        ((TIME) == FLASH_PROGRAMTIME_TPROG))

Macro used by the assert function in order to check the program time mode.

Definition at line 210 of file stm8s_flash.h.

Referenced by FLASH_SetProgrammingTime().

#define IS_MEMORY_TYPE_OK ( MEMTYPE )
Value:
(((MEMTYPE) == FLASH_MEMTYPE_PROG) || \
                                    ((MEMTYPE) == FLASH_MEMTYPE_DATA))

Macro used by the assert function in order to check the different sensitivity values for the flash memory type.

Definition at line 196 of file stm8s_flash.h.

Referenced by FLASH_Lock(), and FLASH_Unlock().

#define IS_OPTION_BYTE_ADDRESS_OK ( ADDRESS )
Value:
(((ADDRESS) >= OPTION_BYTE_START_PHYSICAL_ADDRESS) && \
    ((ADDRESS) <= OPTION_BYTE_END_PHYSICAL_ADDRESS))

Macro used by the assert function in order to check the different sensitivity values for the option bytes Address.

Definition at line 227 of file stm8s_flash.h.

Referenced by FLASH_EraseOptionByte(), FLASH_ProgramOptionByte(), and FLASH_ReadOptionByte().


STM8S/A Standard Peripherals Drivers: FLASH_Exported_Functions

Functions
FLASH_Exported_Functions

Functions

void | FLASH_DeInit (void)
DeInitializes the FLASH registers to their default reset values.
void | FLASH_EraseByte (uint32_t Address)
Erases one byte in the program or data EEPROM memory.
void | FLASH_EraseOptionByte (uint16_t Address)
Erases option byte.
uint32_t | FLASH_GetBootSize (void)
Returns the Boot memory size in bytes.
FlagStatus | FLASH_GetFlagStatus (FLASH_Flag_TypeDef FLASH_FLAG)
Checks whether the specified SPI flag is set or not.
FLASH_LPMode_TypeDef | FLASH_GetLowPowerMode (void)
Returns the Flash behaviour type in low power mode.
FLASH_ProgramTime_TypeDef | FLASH_GetProgrammingTime (void)
Returns the fixed programming time.
void | FLASH_ITConfig (FunctionalState NewState)
Enables or Disables the Flash interrupt mode.
void | FLASH_Lock (FLASH_MemType_TypeDef FLASH_MemType)
Locks the program or data EEPROM memory.
void | FLASH_ProgramByte (uint32_t Address, uint8_t Data)
Programs one byte in program or data EEPROM memory.
void | FLASH_ProgramOptionByte (uint16_t Address, uint8_t Data)
Programs option byte.
void | FLASH_ProgramWord (uint32_t Address, uint32_t Data)
Programs one word (4 bytes) in program or data EEPROM memory.
uint8_t | FLASH_ReadByte (uint32_t Address)
Reads any byte from flash memory.
uint16_t | FLASH_ReadOptionByte (uint16_t Address)
Reads one option byte.
void | FLASH_SetLowPowerMode (FLASH_LPMode_TypeDef FLASH_LPMode)
Select the Flash behaviour in low power mode.
void | FLASH_SetProgrammingTime (FLASH_ProgramTime_TypeDef FLASH_ProgTime)
Sets the fixed programming time.
void | FLASH_Unlock (FLASH_MemType_TypeDef FLASH_MemType)
Unlocks the program or data EEPROM memory.
IN_RAM (void FLASH_EraseBlock(uint16_t BlockNum, FLASH_MemType_TypeDef FLASH_MemType))
IN_RAM (void FLASH_ProgramBlock(uint16_t BlockNum, FLASH_MemType_TypeDef FLASH_MemType, FLASH_ProgramMode_TypeDef FLASH_ProgMode, uint8_t *Buffer))
IN_RAM (FLASH_Status_TypeDef FLASH_WaitForLastOperation(FLASH_MemType_TypeDef FLASH_MemType))

Function Documentation

void FLASH_DeInit ( void )

DeInitializes the FLASH registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 126 of file stm8s_flash.c.

References FLASH, FLASH_CR1_RESET_VALUE, FLASH_CR2_RESET_VALUE, FLASH_IAPSR_DUL, FLASH_IAPSR_PUL, and FLASH_NCR2_RESET_VALUE.

void FLASH_EraseByte ( uint32_t Address )

Erases one byte in the program or data EEPROM memory.

Note:
PointerAttr define is declared in the stm8s.h file to select if the pointer will be declared as near (2 bytes) or far (3 bytes).
Parameters:
Address : Address of the byte to erase
Return values:
None

Definition at line 164 of file stm8s_flash.c.

References FLASH_CLEAR_BYTE, IS_FLASH_ADDRESS_OK, MemoryAddressCast, and PointerAttr.

void FLASH_EraseOptionByte ( uint16_t Address )

Erases option byte.

Parameters:
Address : Option byte address to erase
Return values:
None

Definition at line 270 of file stm8s_flash.c.

References FLASH, FLASH_CLEAR_BYTE, FLASH_CR2_OPT, FLASH_MEMTYPE_PROG, FLASH_NCR2_NOPT, FLASH_SET_BYTE, IS_OPTION_BYTE_ADDRESS_OK, and NEAR.

uint32_t FLASH_GetBootSize ( void )

Returns the Boot memory size in bytes.

Parameters:
None
Return values:
Boot memory size in bytes

Definition at line 392 of file stm8s_flash.c.

References FLASH.

FlagStatus FLASH_GetFlagStatus ( FLASH_Flag_TypeDef FLASH_FLAG )

Checks whether the specified SPI flag is set or not.

Parameters:
FLASH_FLAG : Specifies the flag to check. This parameter can be any of the FLASH_Flag_TypeDef enumeration.
Return values:
FlagStatus : Indicates the state of FLASH_FLAG. This parameter can be any of the FlagStatus enumeration.
Note:
This function can clear the EOP, WR_PG_DIS flags in the IAPSR register.

Definition at line 417 of file stm8s_flash.c.

References FLASH, IS_FLASH_FLAGS_OK, RESET, and SET.

FLASH_LPMode_TypeDef FLASH_GetLowPowerMode ( void )

Returns the Flash behaviour type in low power mode.

Parameters:
None
Return values:
FLASH_LPMode_TypeDef Flash behaviour type in low power mode

Definition at line 372 of file stm8s_flash.c.

References FLASH, FLASH_CR1_AHALT, and FLASH_CR1_HALT.

FLASH_ProgramTime_TypeDef FLASH_GetProgrammingTime ( void )

Returns the fixed programming time.

Parameters:
None
Return values:
FLASH_ProgramTime_TypeDef Fixed programming time value

Definition at line 382 of file stm8s_flash.c.

References FLASH, and FLASH_CR1_FIX.

void FLASH_ITConfig ( FunctionalState NewState )

Enables or Disables the Flash interrupt mode.

Parameters:
NewState : The new state of the flash interrupt mode This parameter can be a value of FunctionalState enumeration.
Return values:
None

Definition at line 142 of file stm8s_flash.c.

References DISABLE, FLASH, FLASH_CR1_IE, and IS_FUNCTIONALSTATE_OK.

void FLASH_Lock ( FLASH_MemType_TypeDef FLASH_MemType )

Locks the program or data EEPROM memory.

Parameters:
FLASH_MemType : Memory type This parameter can be a value of FLASH_MemType_TypeDef
Return values:
None

Definition at line 112 of file stm8s_flash.c.

References FLASH, and IS_MEMORY_TYPE_OK.

void FLASH_ProgramByte | ( | uint32_t | Address,
 |  | uint8_t | Data
 | ) |  |

Programs one byte in program or data EEPROM memory.

Note:
PointerAttr define is declared in the stm8s.h file to select if the pointer will be declared as near (2 bytes) or far (3 bytes).
Parameters:
Address | : Address where the byte will be programmed
Data | : Value to be programmed
Return values:
None

Definition at line 181 of file stm8s_flash.c.

References IS_FLASH_ADDRESS_OK, MemoryAddressCast, and PointerAttr.

void FLASH_ProgramOptionByte | ( | uint16_t | Address,
 |  | uint8_t | Data
 | ) |  |

Programs option byte.

Parameters:
Address | : option byte address to program
Data | : Value to write
Return values:
None

Definition at line 237 of file stm8s_flash.c.

References FLASH, FLASH_CR2_OPT, FLASH_MEMTYPE_PROG, FLASH_NCR2_NOPT, IS_OPTION_BYTE_ADDRESS_OK, and NEAR.

void FLASH_ProgramWord | ( | uint32_t | Address,
 |  | uint32_t | Data
 | ) |  |

Programs one word (4 bytes) in program or data EEPROM memory.

Note:
PointerAttr define is declared in the stm8s.h file to select if the pointer will be declared as near (2 bytes) or far (3 bytes).
Parameters:
Address | : The address where the data will be programmed
Data | : Value to be programmed
Return values:
None

Definition at line 212 of file stm8s_flash.c.

References FLASH, FLASH_CR2_WPRG, FLASH_NCR2_NWPRG, IS_FLASH_ADDRESS_OK, MemoryAddressCast, and PointerAttr.

uint8_t FLASH_ReadByte ( uint32_t Address )

Reads any byte from flash memory.

Note:
PointerAttr define is declared in the stm8s.h file to select if the pointer will be declared as near (2 bytes) or far (3 bytes).
Parameters:
Address : Address to read
Return values:
Value of the byte

Definition at line 195 of file stm8s_flash.c.

References IS_FLASH_ADDRESS_OK, MemoryAddressCast, and PointerAttr.

uint16_t FLASH_ReadOptionByte ( uint16_t Address )

Reads one option byte.

Parameters:
Address option byte address to read.
Return values:
Option byte read value + its complement

Definition at line 303 of file stm8s_flash.c.

References FLASH_OPTIONBYTE_ERROR, IS_OPTION_BYTE_ADDRESS_OK, and NEAR.

void FLASH_SetLowPowerMode ( FLASH_LPMode_TypeDef FLASH_LPMode )

Select the Flash behaviour in low power mode.

Parameters:
FLASH_LPMode Low power mode selection This parameter can be any of the FLASH_LPMode_TypeDef values.
Return values:
None

Definition at line 340 of file stm8s_flash.c.

References FLASH, FLASH_CR1_AHALT, FLASH_CR1_HALT, and IS_FLASH_LOW_POWER_MODE_OK.

void FLASH_SetProgrammingTime ( FLASH_ProgramTime_TypeDef FLASH_ProgTime )

Sets the fixed programming time.

Parameters:
FLASH_ProgTime Indicates the programming time to be fixed This parameter can be any of the FLASH_ProgramTime_TypeDef values.
Return values:
None

Definition at line 358 of file stm8s_flash.c.

References FLASH, FLASH_CR1_FIX, and IS_FLASH_PROGRAM_TIME_OK.

void FLASH_Unlock ( FLASH_MemType_TypeDef FLASH_MemType )

Unlocks the program or data EEPROM memory.

Parameters:
FLASH_MemType : Memory type to unlock This parameter can be a value of FLASH_MemType_TypeDef
Return values:
None

Definition at line 87 of file stm8s_flash.c.

References FLASH, FLASH_MEMTYPE_PROG, FLASH_RASS_KEY1, FLASH_RASS_KEY2, and IS_MEMORY_TYPE_OK.

IN_RAM ( void FLASH_EraseBlockuint16_t BlockNum, FLASH_MemType_TypeDef FLASH_MemType )
 All the functions declared below must be executed from RAM exclusively, except
 for the FLASH_WaitForLastOperation function which can be executed from Flash.

 Steps of the execution from RAM differs from one toolchain to another.
 for more details refer to stm8s_flash.c file.

 To enable execution from RAM you can either uncomment the following define
 in the stm8s.h file or define it in your toolchain compiler preprocessor
 - #define RAM_EXECUTION  (1)
IN_RAM ( void FLASH_ProgramBlockuint16_t BlockNum, FLASH_MemType_TypeDef FLASH_MemType, FLASH_ProgramMode_TypeDef FLASH_ProgMode, uint8_t *Buffer )
IN_RAM ( FLASH_Status_TypeDef FLASH_WaitForLastOperationFLASH_MemType_TypeDef FLASH_MemType )


STM8S/A Standard Peripherals Drivers: GPIO_Exported_Types

Enumerations
GPIO_Exported_Types

Enumerations

enum GPIO_Mode_TypeDef {
GPIO_MODE_IN_FL_NO_IT = (uint8_t)0x00, GPIO_MODE_IN_PU_NO_IT = (uint8_t)0x40, GPIO_MODE_IN_FL_IT = (uint8_t)0x20, GPIO_MODE_IN_PU_IT = (uint8_t)0x60,
GPIO_MODE_OUT_OD_LOW_FAST = (uint8_t)0xA0, GPIO_MODE_OUT_PP_LOW_FAST = (uint8_t)0xE0, GPIO_MODE_OUT_OD_LOW_SLOW = (uint8_t)0x80, GPIO_MODE_OUT_PP_LOW_SLOW = (uint8_t)0xC0,
GPIO_MODE_OUT_OD_HIZ_FAST = (uint8_t)0xB0, GPIO_MODE_OUT_PP_HIGH_FAST = (uint8_t)0xF0, GPIO_MODE_OUT_OD_HIZ_SLOW = (uint8_t)0x90, GPIO_MODE_OUT_PP_HIGH_SLOW = (uint8_t)0xD0
}
GPIO modes. More...
enum GPIO_Pin_TypeDef {
GPIO_PIN_0 = ((uint8_t)0x01), GPIO_PIN_1 = ((uint8_t)0x02), GPIO_PIN_2 = ((uint8_t)0x04), GPIO_PIN_3 = ((uint8_t)0x08),
GPIO_PIN_4 = ((uint8_t)0x10), GPIO_PIN_5 = ((uint8_t)0x20), GPIO_PIN_6 = ((uint8_t)0x40), GPIO_PIN_7 = ((uint8_t)0x80),
GPIO_PIN_LNIB = ((uint8_t)0x0F), GPIO_PIN_HNIB = ((uint8_t)0xF0), GPIO_PIN_ALL = ((uint8_t)0xFF)
}
Definition of the GPIO pins. More...

Enumeration Type Documentation

enum GPIO_Mode_TypeDef

GPIO modes.

Bits definitions:

  • Bit 7: 0 = INPUT mode 1 = OUTPUT mode 1 = PULL-UP (input) or PUSH-PULL (output)
  • Bit 5: 0 = No external interrupt (input) or No slope control (output) 1 = External interrupt (input) or Slow control enabled (output)
  • Bit 4: 0 = Low level (output) 1 = High level (output push-pull) or HI-Z (output open-drain)
Enumerator:
GPIO_MODE_IN_FL_NO_IT

Input floating, no external interrupt

GPIO_MODE_IN_PU_NO_IT

Input pull-up, no external interrupt

GPIO_MODE_IN_FL_IT

Input floating, external interrupt

GPIO_MODE_IN_PU_IT

Input pull-up, external interrupt

GPIO_MODE_OUT_OD_LOW_FAST

Output open-drain, low level, 10MHz

GPIO_MODE_OUT_PP_LOW_FAST

Output push-pull, low level, 10MHz

GPIO_MODE_OUT_OD_LOW_SLOW

Output open-drain, low level, 2MHz

GPIO_MODE_OUT_PP_LOW_SLOW

Output push-pull, low level, 2MHz

GPIO_MODE_OUT_OD_HIZ_FAST

Output open-drain, high-impedance level,10MHz

GPIO_MODE_OUT_PP_HIGH_FAST

Output push-pull, high level, 10MHz

GPIO_MODE_OUT_OD_HIZ_SLOW

Output open-drain, high-impedance level, 2MHz

GPIO_MODE_OUT_PP_HIGH_SLOW

Output push-pull, high level, 2MHz

Definition at line 54 of file stm8s_gpio.h.

enum GPIO_Pin_TypeDef

Definition of the GPIO pins.

Used by the GPIO_Init function in order to select the pins to be initialized.

Enumerator:
GPIO_PIN_0

Pin 0 selected

GPIO_PIN_1

Pin 1 selected

GPIO_PIN_2

Pin 2 selected

GPIO_PIN_3

Pin 3 selected

GPIO_PIN_4

Pin 4 selected

GPIO_PIN_5

Pin 5 selected

GPIO_PIN_6

Pin 6 selected

GPIO_PIN_7

Pin 7 selected

GPIO_PIN_LNIB

Low nibble pins selected

GPIO_PIN_HNIB

High nibble pins selected

GPIO_PIN_ALL

All pins selected

Definition at line 75 of file stm8s_gpio.h.


STM8S/A Standard Peripherals Drivers: GPIO_Private_Macros

Defines
GPIO_Private_Macros

Defines

#define | IS_GPIO_MODE_OK(MODE)
Macro used by the assert function to check the different functions parameters.
#define | IS_GPIO_PIN_OK(PIN) ((PIN) != (uint8_t)0x00)
Macro used by the assert function in order to check the different values of GPIO_Pins.

Define Documentation

#define IS_GPIO_MODE_OK ( MODE )
Value:
(((MODE) == GPIO_MODE_IN_FL_NO_IT)    || \
   ((MODE) == GPIO_MODE_IN_PU_NO_IT)    || \
   ((MODE) == GPIO_MODE_IN_FL_IT)       || \
   ((MODE) == GPIO_MODE_IN_PU_IT)       || \
   ((MODE) == GPIO_MODE_OUT_OD_LOW_FAST)  || \
   ((MODE) == GPIO_MODE_OUT_PP_LOW_FAST)  || \
   ((MODE) == GPIO_MODE_OUT_OD_LOW_SLOW)  || \
   ((MODE) == GPIO_MODE_OUT_PP_LOW_SLOW)  || \
   ((MODE) == GPIO_MODE_OUT_OD_HIZ_FAST)  || \
   ((MODE) == GPIO_MODE_OUT_PP_HIGH_FAST)  || \
   ((MODE) == GPIO_MODE_OUT_OD_HIZ_SLOW)  || \
   ((MODE) == GPIO_MODE_OUT_PP_HIGH_SLOW))

Macro used by the assert function to check the different functions parameters.

Macro used by the assert function in order to check the different values of GPIOMode_TypeDef.

Definition at line 110 of file stm8s_gpio.h.

Referenced by GPIO_Init().

#define IS_GPIO_PIN_OK ( PIN ) ((PIN) != (uint8_t)0x00)

Macro used by the assert function in order to check the different values of GPIO_Pins.

Definition at line 128 of file stm8s_gpio.h.

Referenced by GPIO_ExternalPullUpConfig(), and GPIO_Init().


STM8S/A Standard Peripherals Drivers: GPIO_Exported_Functions

Functions
GPIO_Exported_Functions

Functions

void | GPIO_DeInit (GPIO_TypeDef *GPIOx)
Deinitializes the GPIOx peripheral registers to their default reset values.
void | GPIO_ExternalPullUpConfig (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef GPIO_Pin, FunctionalState NewState)
Configures the external pull-up on GPIOx pins.
void | GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef GPIO_Pin, GPIO_Mode_TypeDef GPIO_Mode)
Initializes the GPIOx according to the specified parameters.
uint8_t | GPIO_ReadInputData (GPIO_TypeDef *GPIOx)
Reads the specified GPIO input data port.
BitStatus | GPIO_ReadInputPin (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
Reads the specified GPIO input data pin.
uint8_t | GPIO_ReadOutputData (GPIO_TypeDef *GPIOx)
Reads the specified GPIO output data port.
void | GPIO_Write (GPIO_TypeDef *GPIOx, uint8_t PortVal)
Writes data to the specified GPIO data port.
void | GPIO_WriteHigh (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef PortPins)
Writes high level to the specified GPIO pins.
void | GPIO_WriteLow (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef PortPins)
Writes low level to the specified GPIO pins.
void | GPIO_WriteReverse (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef PortPins)
Writes reverse level to the specified GPIO pins.

Function Documentation

void GPIO_DeInit ( GPIO_TypeDef * GPIOx )

Deinitializes the GPIOx peripheral registers to their default reset values.

Parameters:
GPIOx,: Select the GPIO peripheral number (x = A to I).
Return values:
None

Definition at line 53 of file stm8s_gpio.c.

References GPIO_struct::CR1, GPIO_struct::CR2, GPIO_struct::DDR, GPIO_CR1_RESET_VALUE, GPIO_CR2_RESET_VALUE, GPIO_DDR_RESET_VALUE, GPIO_ODR_RESET_VALUE, and GPIO_struct::ODR.

void GPIO_ExternalPullUpConfig | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_Pin_TypeDef | GPIO_Pin,
 |  | FunctionalState | NewState
 | ) |  |

Configures the external pull-up on GPIOx pins.

Parameters:
GPIOx | : Select the GPIO peripheral number (x = A to I).
GPIO_Pin | : Specifies the pin number
NewState | : The new state of the pull up pin.
Return values:
None

Definition at line 225 of file stm8s_gpio.c.

References GPIO_struct::CR1, DISABLE, IS_FUNCTIONALSTATE_OK, and IS_GPIO_PIN_OK.

void GPIO_Init | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_Pin_TypeDef | GPIO_Pin,
 |  | GPIO_Mode_TypeDef | GPIO_Mode
 | ) |  |

Initializes the GPIOx according to the specified parameters.

Parameters:
GPIOx | : Select the GPIO peripheral number (x = A to I).
GPIO_Pin | : This parameter contains the pin number, it can be any value of the GPIO_Pin_TypeDef enumeration.
GPIO_Mode | : This parameter can be a value of the GPIO_Mode_TypeDef enumeration.
Return values:
None

Definition at line 71 of file stm8s_gpio.c.

References GPIO_struct::CR1, GPIO_struct::CR2, GPIO_struct::DDR, IS_GPIO_MODE_OK, IS_GPIO_PIN_OK, and GPIO_struct::ODR.

uint8_t GPIO_ReadInputData ( GPIO_TypeDef * GPIOx )

Reads the specified GPIO input data port.

Note:
The port must be configured in input mode.
Parameters:
GPIOx : Select the GPIO peripheral number (x = A to I).
Return values:
GPIO input data port value.

Definition at line 202 of file stm8s_gpio.c.

References GPIO_struct::IDR.

BitStatus GPIO_ReadInputPin | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_Pin_TypeDef | GPIO_Pin
 | ) |  |

Reads the specified GPIO input data pin.

Parameters:
GPIOx | : Select the GPIO peripheral number (x = A to I).
GPIO_Pin | : Specifies the pin number.
Return values:
BitStatus : GPIO input pin status.

Definition at line 213 of file stm8s_gpio.c.

References GPIO_struct::IDR.

uint8_t GPIO_ReadOutputData ( GPIO_TypeDef * GPIOx )

Reads the specified GPIO output data port.

Note:
The port must be configured in input mode.
Parameters:
GPIOx : Select the GPIO peripheral number (x = A to I).
Return values:
GPIO output data port value.

Definition at line 191 of file stm8s_gpio.c.

References GPIO_struct::ODR.

void GPIO_Write | ( | GPIO_TypeDef * | GPIOx,
 |  | uint8_t | PortVal
 | ) |  |

Writes data to the specified GPIO data port.

Note:
The port must be configured in output mode.
Parameters:
GPIOx | : Select the GPIO peripheral number (x = A to I).
PortVal | : Specifies the value to be written to the port output data register.
Return values:
None

Definition at line 141 of file stm8s_gpio.c.

References GPIO_struct::ODR.

void GPIO_WriteHigh | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_Pin_TypeDef | PortPins
 | ) |  |

Writes high level to the specified GPIO pins.

Note:
The port must be configured in output mode.
Parameters:
GPIOx | : Select the GPIO peripheral number (x = A to I).
PortPins | : Specifies the pins to be turned high to the port output. data register.
Return values:
None

Definition at line 154 of file stm8s_gpio.c.

References GPIO_struct::ODR.

void GPIO_WriteLow | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_Pin_TypeDef | PortPins
 | ) |  |

Writes low level to the specified GPIO pins.

Note:
The port must be configured in output mode.
Parameters:
GPIOx | : Select the GPIO peripheral number (x = A to I).
PortPins | : Specifies the pins to be turned low to the port output. data register.
Return values:
None

Definition at line 167 of file stm8s_gpio.c.

References GPIO_struct::ODR.

void GPIO_WriteReverse | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_Pin_TypeDef | PortPins
 | ) |  |

Writes reverse level to the specified GPIO pins.

Note:
The port must be configured in output mode.
Parameters:
GPIOx | : Select the GPIO peripheral number (x = A to I).
PortPins | : Specifies the pins to be reversed to the port output. data register.
Return values:
None

Definition at line 180 of file stm8s_gpio.c.

References GPIO_struct::ODR.


STM8S/A Standard Peripherals Drivers: I2C_Exported_Types

Enumerations
I2C_Exported_Types

Enumerations

enum | I2C_Ack_TypeDef { I2C_ACK_NONE = (uint8_t)0x00, I2C_ACK_CURR = (uint8_t)0x01, I2C_ACK_NEXT = (uint8_t)0x02 }
I2C Acknowledgement configuration. More...
enum | I2C_AddMode_TypeDef { I2C_ADDMODE_7BIT = (uint8_t)0x00, I2C_ADDMODE_10BIT = (uint8_t)0x80 }
I2C Addressing Mode (slave mode only) More...
enum | I2C_Direction_TypeDef { I2C_DIRECTION_TX = (uint8_t)0x00, I2C_DIRECTION_RX = (uint8_t)0x01 }
I2C transfer direction Warning: the values correspond to the ADD0 bit position in the OARL register. More...
enum | I2C_DutyCycle_TypeDef { I2C_DUTYCYCLE_2 = (uint8_t)0x00, I2C_DUTYCYCLE_16_9 = (uint8_t)0x40 }
I2C duty cycle (fast mode only) More...
enum I2C_Event_TypeDef {
I2C_EVENT_MASTER_MODE_SELECT = (uint16_t)0x0301, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED = (uint16_t)0x0782, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED = (uint16_t)0x0302, I2C_EVENT_MASTER_MODE_ADDRESS10 = (uint16_t)0x0308,
I2C_EVENT_MASTER_BYTE_RECEIVED = (uint16_t)0x0340, I2C_EVENT_MASTER_BYTE_TRANSMITTING = (uint16_t)0x0780, I2C_EVENT_MASTER_BYTE_TRANSMITTED = (uint16_t)0x0784, I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED = (uint16_t)0x0202,
I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED = (uint16_t)0x0682, I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED = (uint16_t)0x1200, I2C_EVENT_SLAVE_BYTE_RECEIVED = (uint16_t)0x0240, I2C_EVENT_SLAVE_STOP_DETECTED = (uint16_t)0x0010,
I2C_EVENT_SLAVE_BYTE_TRANSMITTED = (uint16_t)0x0684, I2C_EVENT_SLAVE_BYTE_TRANSMITTING = (uint16_t)0x0680, I2C_EVENT_SLAVE_ACK_FAILURE = (uint16_t)0x0004
}
I2C possible events Values convention: 0xXXYY XX = Event SR3 corresponding value YY = Event SR1 corresponding value. More...
enum I2C_Flag_TypeDef {
I2C_FLAG_TXEMPTY = (uint16_t)0x0180, I2C_FLAG_RXNOTEMPTY = (uint16_t)0x0140, I2C_FLAG_STOPDETECTION = (uint16_t)0x0110, I2C_FLAG_HEADERSENT = (uint16_t)0x0108,
I2C_FLAG_TRANSFERFINISHED = (uint16_t)0x0104, I2C_FLAG_ADDRESSSENTMATCHED = (uint16_t)0x0102, I2C_FLAG_STARTDETECTION = (uint16_t)0x0101, I2C_FLAG_WAKEUPFROMHALT = (uint16_t)0x0220,
I2C_FLAG_OVERRUNUNDERRUN = (uint16_t)0x0208, I2C_FLAG_ACKNOWLEDGEFAILURE = (uint16_t)0x0204, I2C_FLAG_ARBITRATIONLOSS = (uint16_t)0x0202, I2C_FLAG_BUSERROR = (uint16_t)0x0201,
I2C_FLAG_GENERALCALL = (uint16_t)0x0310, I2C_FLAG_TRANSMITTERRECEIVER = (uint16_t)0x0304, I2C_FLAG_BUSBUSY = (uint16_t)0x0302, I2C_FLAG_MASTERSLAVE = (uint16_t)0x0301
}
I2C Flags. More...
enum | I2C_IT_TypeDef { I2C_IT_ERR = (uint8_t)0x01, I2C_IT_EVT = (uint8_t)0x02, I2C_IT_BUF = (uint8_t)0x04 }
I2C Interrupt sources Warning: the values correspond to the bit position in the ITR register. More...
enum I2C_ITPendingBit_TypeDef {
I2C_ITPENDINGBIT_TXEMPTY = (uint16_t)0x1680, I2C_ITPENDINGBIT_RXNOTEMPTY = (uint16_t)0x1640, I2C_ITPENDINGBIT_STOPDETECTION = (uint16_t)0x1210, I2C_ITPENDINGBIT_HEADERSENT = (uint16_t)0x1208,
I2C_ITPENDINGBIT_TRANSFERFINISHED = (uint16_t)0x1204, I2C_ITPENDINGBIT_ADDRESSSENTMATCHED = (uint16_t)0x1202, I2C_ITPENDINGBIT_STARTDETECTION = (uint16_t)0x1201, I2C_ITPENDINGBIT_WAKEUPFROMHALT = (uint16_t)0x2220,
I2C_ITPENDINGBIT_OVERRUNUNDERRUN = (uint16_t)0x2108, I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE = (uint16_t)0x2104, I2C_ITPENDINGBIT_ARBITRATIONLOSS = (uint16_t)0x2102, I2C_ITPENDINGBIT_BUSERROR = (uint16_t)0x2101
}
I2C Pending bits Elements values convention: 0xXYZZ X = SRx registers index X = 1 : SR1 X = 2 : SR2 Y = Position of the corresponding Interrupt ZZ = flag mask in the dedicated register(X register) More...

Enumeration Type Documentation

enum I2C_Ack_TypeDef

I2C Acknowledgement configuration.

Enumerator:
I2C_ACK_NONE

No acknowledge

I2C_ACK_CURR

Acknowledge on the current byte

I2C_ACK_NEXT

Acknowledge on the next byte

Definition at line 53 of file stm8s_i2c.h.

enum I2C_AddMode_TypeDef

I2C Addressing Mode (slave mode only)

Enumerator:
I2C_ADDMODE_7BIT

7-bit slave address (10-bit address not acknowledged)

I2C_ADDMODE_10BIT

10-bit slave address (7-bit address not acknowledged)

Definition at line 63 of file stm8s_i2c.h.

enum I2C_Direction_TypeDef

I2C transfer direction Warning: the values correspond to the ADD0 bit position in the OARL register.

Enumerator:
I2C_DIRECTION_TX

Transmission direction

I2C_DIRECTION_RX

Reception direction

Definition at line 84 of file stm8s_i2c.h.

enum I2C_DutyCycle_TypeDef

I2C duty cycle (fast mode only)

Enumerator:
I2C_DUTYCYCLE_2

Fast mode Tlow/THigh = 2

I2C_DUTYCYCLE_16_9

Fast mode Tlow/Thigh = 16/9

Definition at line 44 of file stm8s_i2c.h.

enum I2C_Event_TypeDef

I2C possible events Values convention: 0xXXYY XX = Event SR3 corresponding value YY = Event SR1 corresponding value.

Note:
if Event = EV3_2 the rule above does not apply YY = Event SR2 corresponding value
Enumerator:
I2C_EVENT_MASTER_MODE_SELECT

Communication start.

After sending the START condition (I2C_GenerateSTART() function) the master has to wait for this event. It means that the Start condition has been correctly released on the I2C bus (the bus is free, no other devices is communicating). BUSY, MSL and SB flag

I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED

Address Acknowledge.

After checking on EV5 (start condition correctly released on the bus), the master sends the address of the slave(s) with which it will communicate (I2C_Send7bitAddress() function, it also determines the direction of the communication: Master transmitter or Receiver). Then the master has to wait that a slave acknowledges his address. If an acknowledge is sent on the bus, one of the following events will be set:

1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED event is set.

2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED is set

3) In case of 10-Bit addressing mode, the master (just after generating the START and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() function). Then master should wait on EV9. It means that the 10-bit addressing header has been correctly sent on the bus. Then master should send the second part of the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master should wait for event EV6. BUSY, MSL, ADDR, TXE and TRA flags

I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED

BUSY, MSL and ADDR flags

I2C_EVENT_MASTER_MODE_ADDRESS10

BUSY, MSL and ADD10 flags

I2C_EVENT_MASTER_BYTE_RECEIVED

Communication events.

If a communication is established (START condition generated and slave address acknowledged) then the master has to check on one of the following events for communication procedures:

1) Master Receiver mode: The master has to wait on the event EV7 then to read the data received from the slave (I2C_ReceiveData() function).

2) Master Transmitter mode: The master has to send data (I2C_SendData() function) then to wait on event EV8 or EV8_2. These two events are similar:

  • EV8 means that the data has been written in the data register and is being shifted out.
  • EV8_2 means that the data has been physically shifted out and output on the bus. In most cases, using EV8 is sufficient for the application. Using EV8_2 leads to a slower communication but ensures more reliable test. EV8_2 is also more suitable than EV8 for testing on the last data transmission (before Stop condition generation).
Note:
In case the user software does not guarantee that this event EV7 is managed before the current byte end of transfer, then user may check on EV7 and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). In this case the communication may be slower. BUSY, MSL and RXNE flags
I2C_EVENT_MASTER_BYTE_TRANSMITTING

TRA, BUSY, MSL, TXE flags

I2C_EVENT_MASTER_BYTE_TRANSMITTED

EV8_2: TRA, BUSY, MSL, TXE and BTF flags

I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED

Communication start events.

Wait on one of these events at the start of the communication. It means that the I2C peripheral detected a Start condition on the bus (generated by master device) followed by the peripheral address. The peripheral generates an ACK condition on the bus (if the acknowledge feature is enabled through function I2C_AcknowledgeConfig()) and the events listed above are set :

1) In normal case (only one address managed by the slave), when the address sent by the master matches the own address of the peripheral (configured by I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set (where XXX could be TRANSMITTER or RECEIVER).

2) In case the address sent by the master is General Call (address 0x00) and if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. BUSY and ADDR flags

I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED

TRA, BUSY, TXE and ADDR flags

I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED

EV2: GENCALL and BUSY flags

I2C_EVENT_SLAVE_BYTE_RECEIVED

Communication events.

Wait on one of these events when EV1 has already been checked :

  • Slave RECEIVER mode:
    • EV2: When the application is expecting a data byte to be received.
    • EV4: When the application is expecting the end of the communication: master sends a stop condition and data transmission is stopped.
  • Slave Transmitter mode:
    • EV3: When a byte has been transmitted by the slave and the application is expecting the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be used when the user software doesn't guarantee the EV3 is managed before the current byte end of transfer.
    • EV3_2: When the master sends a NACK in order to tell slave that data transmission shall end (before sending the STOP condition). In this case slave has to stop sending data bytes and expect a Stop condition on the bus.
Note:
In case the user software does not guarantee that the event EV2 is managed before the current byte end of transfer, then user may check on EV2 and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). In this case the communication may be slower. BUSY and RXNE flags
I2C_EVENT_SLAVE_STOP_DETECTED

STOPF flag

I2C_EVENT_SLAVE_BYTE_TRANSMITTED

TRA, BUSY, TXE and BTF flags

I2C_EVENT_SLAVE_BYTE_TRANSMITTING

TRA, BUSY and TXE flags

I2C_EVENT_SLAVE_ACK_FAILURE

AF flag

Definition at line 163 of file stm8s_i2c.h.

enum I2C_Flag_TypeDef

I2C Flags.

Elements values convention: 0xXXYY X = SRx registers index X = 1 : SR1 X = 2 : SR2 X = 3 : SR3 Y = Flag mask in the register

Enumerator:
I2C_FLAG_TXEMPTY

Transmit Data Register Empty flag

I2C_FLAG_RXNOTEMPTY

Read Data Register Not Empty flag

I2C_FLAG_STOPDETECTION

Stop detected flag

I2C_FLAG_HEADERSENT

10-bit Header sent flag

I2C_FLAG_TRANSFERFINISHED

Data Byte Transfer Finished flag

I2C_FLAG_ADDRESSSENTMATCHED

Address Sent/Matched (master/slave) flag

I2C_FLAG_STARTDETECTION

Start bit sent flag

I2C_FLAG_WAKEUPFROMHALT

Wake Up From Halt Flag

I2C_FLAG_OVERRUNUNDERRUN

Overrun/Underrun flag

I2C_FLAG_ACKNOWLEDGEFAILURE

Acknowledge Failure Flag

I2C_FLAG_ARBITRATIONLOSS

Arbitration Loss Flag

I2C_FLAG_BUSERROR

Misplaced Start or Stop condition

I2C_FLAG_GENERALCALL

General Call header received Flag

I2C_FLAG_TRANSMITTERRECEIVER

Transmitter Receiver Flag

I2C_FLAG_BUSBUSY

Bus Busy Flag

I2C_FLAG_MASTERSLAVE

Master Slave Flag

Definition at line 100 of file stm8s_i2c.h.

enum I2C_IT_TypeDef

I2C Interrupt sources Warning: the values correspond to the bit position in the ITR register.

Enumerator:
I2C_IT_ERR

Error Interruption

I2C_IT_EVT

Event Interruption

I2C_IT_BUF

Buffer Interruption

Definition at line 73 of file stm8s_i2c.h.

enum I2C_ITPendingBit_TypeDef

I2C Pending bits Elements values convention: 0xXYZZ X = SRx registers index X = 1 : SR1 X = 2 : SR2 Y = Position of the corresponding Interrupt ZZ = flag mask in the dedicated register(X register)

Enumerator:
I2C_ITPENDINGBIT_TXEMPTY

Transmit Data Register Empty

I2C_ITPENDINGBIT_RXNOTEMPTY

Read Data Register Not Empty

I2C_ITPENDINGBIT_STOPDETECTION

Stop detected

I2C_ITPENDINGBIT_HEADERSENT

10-bit Header sent

I2C_ITPENDINGBIT_TRANSFERFINISHED

Data Byte Transfer Finished

I2C_ITPENDINGBIT_ADDRESSSENTMATCHED

Address Sent/Matched (master/slave)

I2C_ITPENDINGBIT_STARTDETECTION

Start bit sent

I2C_ITPENDINGBIT_WAKEUPFROMHALT

Wake Up From Halt

I2C_ITPENDINGBIT_OVERRUNUNDERRUN

Overrun/Underrun

I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE

Acknowledge Failure

I2C_ITPENDINGBIT_ARBITRATIONLOSS

Arbitration Loss

I2C_ITPENDINGBIT_BUSERROR

Misplaced Start or Stop condition

Definition at line 135 of file stm8s_i2c.h.


STM8S/A Standard Peripherals Drivers: I2C_Exported_Constants

Defines
I2C_Exported_Constants

Defines

#define | I2C_MAX_FAST_FREQ ((uint32_t)400000)
#define | I2C_MAX_INPUT_FREQ ((uint8_t)16)
#define | I2C_MAX_STANDARD_FREQ ((uint32_t)100000)

Define Documentation

#define I2C_MAX_FAST_FREQ ((uint32_t)400000)

Definition at line 336 of file stm8s_i2c.h.

#define I2C_MAX_INPUT_FREQ ((uint8_t)16)

Definition at line 340 of file stm8s_i2c.h.

#define I2C_MAX_STANDARD_FREQ ((uint32_t)100000)

Definition at line 335 of file stm8s_i2c.h.

Referenced by I2C_Init().


STM8S/A Standard Peripherals Drivers: I2C_Private_Macros

Defines
I2C_Private_Macros

Defines

#define | IS_I2C_ACK_OK(ACK)
Macro used by the assert function to check the different acknowledgement configuration.
#define | IS_I2C_ADDMODE_OK(ADDMODE)
Macro used by the assert function to check the different I2C addressing modes.
#define | IS_I2C_ADDRESS_OK(ADD) (((ADD) & (uint8_t)0x01) == (uint8_t)0x00)
#define | IS_I2C_CLEAR_FLAG_OK(FLAG)
Macro used by the assert function to check the I2C flags to clear.
#define | IS_I2C_CLEAR_ITPENDINGBIT_OK(ITPENDINGBIT)
Macro used by the assert function to check the different I2C possible pending bits to clear by writing 0.
#define | IS_I2C_DIRECTION_OK(DIR)
Macro used by the assert function to check the different I2C communcation direction.
#define | IS_I2C_DUTYCYCLE_OK(DUTY)
Macro used by the assert function to check the different functions parameters.
#define | IS_I2C_EVENT_OK(EVENT)
Macro used by the assert function to check the different I2C possible events.
#define | IS_I2C_FLAG_OK(FLAG)
Macro used by the assert function to check the different I2C flags.
#define | IS_I2C_INPUT_CLOCK_FREQ_OK(FREQ) (((FREQ) >= (uint8_t)1) && ((FREQ) <= I2C_MAX_INPUT_FREQ))
Macro used by the assert function to check that I2C Input clock frequency must be between 1MHz and 50MHz.
#define | IS_I2C_INTERRUPT_OK(IT)
Macro used by the assert function to check the different I2C interrupt types.
#define | IS_I2C_ITPENDINGBIT_OK(ITPENDINGBIT)
Macro used by the assert function to check the different I2C possible pending bits.
#define | IS_I2C_OUTPUT_CLOCK_FREQ_OK(FREQ) (((FREQ) >= (uint8_t)1) && ((FREQ) <= I2C_MAX_FAST_FREQ))
Macro used by the assert function to check that I2C Output clock frequency must be between 1Hz and 400kHz.
#define | IS_I2C_OWN_ADDRESS_OK(ADDRESS) ((ADDRESS) <= (uint16_t)0x03FF)
Macro used by the assert function to check the different I2C possible own address.

Define Documentation

#define IS_I2C_ACK_OK ( ACK )
Value:
(((ACK) == I2C_ACK_NONE) || \
   ((ACK) == I2C_ACK_CURR) || \
   ((ACK) == I2C_ACK_NEXT))

Macro used by the assert function to check the different acknowledgement configuration.

Definition at line 368 of file stm8s_i2c.h.

Referenced by I2C_AcknowledgeConfig(), and I2C_Init().

#define IS_I2C_ADDMODE_OK ( ADDMODE )
Value:
(((ADDMODE) == I2C_ADDMODE_7BIT) || \
   ((ADDMODE) == I2C_ADDMODE_10BIT))

Macro used by the assert function to check the different I2C addressing modes.

Definition at line 376 of file stm8s_i2c.h.

Referenced by I2C_Init().

#define IS_I2C_ADDRESS_OK ( ADD ) (((ADD) & (uint8_t)0x01) == (uint8_t)0x00)

Definition at line 480 of file stm8s_i2c.h.

Referenced by I2C_Send7bitAddress().

#define IS_I2C_CLEAR_FLAG_OK ( FLAG )
Value:
((((uint16_t)(FLAG) & (uint16_t)0xFD00) == 0x00) \
                                     && ((uint16_t)(FLAG) != 0x00))

Macro used by the assert function to check the I2C flags to clear.

Definition at line 422 of file stm8s_i2c.h.

Referenced by I2C_ClearFlag().

#define IS_I2C_CLEAR_ITPENDINGBIT_OK ( ITPENDINGBIT )
Value:
(((ITPENDINGBIT) == I2C_ITPENDINGBIT_WAKEUPFROMHALT)     || \
    ((ITPENDINGBIT) == I2C_ITPENDINGBIT_OVERRUNUNDERRUN)    || \
    ((ITPENDINGBIT) == I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE) || \
    ((ITPENDINGBIT) == I2C_ITPENDINGBIT_ARBITRATIONLOSS)    || \
    ((ITPENDINGBIT) == I2C_ITPENDINGBIT_BUSERROR))

Macro used by the assert function to check the different I2C possible pending bits to clear by writing 0.

Definition at line 446 of file stm8s_i2c.h.

Referenced by I2C_ClearITPendingBit().

#define IS_I2C_DIRECTION_OK ( DIR )
Value:
(((DIR) == I2C_DIRECTION_TX) || \
   ((DIR) == I2C_DIRECTION_RX))

Macro used by the assert function to check the different I2C communcation direction.

Definition at line 394 of file stm8s_i2c.h.

Referenced by I2C_Send7bitAddress().

#define IS_I2C_DUTYCYCLE_OK ( DUTY )
Value:
(((DUTY) == I2C_DUTYCYCLE_2) || \
   ((DUTY) == I2C_DUTYCYCLE_16_9))

Macro used by the assert function to check the different functions parameters.

Macro used by the assert function to check the different I2C duty cycles.

Definition at line 361 of file stm8s_i2c.h.

Referenced by I2C_FastModeDutyCycleConfig(), and I2C_Init().

#define IS_I2C_EVENT_OK ( EVENT )
Value:
(((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
                             ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
                             ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | (uint16_t)I2C_FLAG_GENERALCALL)) || \
                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | (uint16_t)I2C_FLAG_GENERALCALL)) || \
                             ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE) || \
                             ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
                             ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
                             ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
                             ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
                             ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
                             ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10))

Macro used by the assert function to check the different I2C possible events.

Definition at line 456 of file stm8s_i2c.h.

Referenced by I2C_CheckEvent().

#define IS_I2C_FLAG_OK ( FLAG )
Value:
(((FLAG) == I2C_FLAG_TXEMPTY)         || \
   ((FLAG) == I2C_FLAG_RXNOTEMPTY)       || \
   ((FLAG) == I2C_FLAG_STOPDETECTION)      || \
   ((FLAG) == I2C_FLAG_HEADERSENT)       || \
   ((FLAG) == I2C_FLAG_TRANSFERFINISHED)   || \
   ((FLAG) == I2C_FLAG_ADDRESSSENTMATCHED)  || \
   ((FLAG) == I2C_FLAG_STARTDETECTION)    || \
   ((FLAG) == I2C_FLAG_WAKEUPFROMHALT)    || \
   ((FLAG) == I2C_FLAG_OVERRUNUNDERRUN)    || \
   ((FLAG) == I2C_FLAG_ACKNOWLEDGEFAILURE)  || \
   ((FLAG) == I2C_FLAG_ARBITRATIONLOSS)    || \
   ((FLAG) == I2C_FLAG_BUSERROR)       || \
   ((FLAG) == I2C_FLAG_GENERALCALL)      || \
   ((FLAG) == I2C_FLAG_TRANSMITTERRECEIVER) || \
   ((FLAG) == I2C_FLAG_BUSBUSY) || \
   ((FLAG) == I2C_FLAG_MASTERSLAVE))

Macro used by the assert function to check the different I2C flags.

Definition at line 401 of file stm8s_i2c.h.

Referenced by I2C_GetFlagStatus().

#define IS_I2C_INPUT_CLOCK_FREQ_OK ( FREQ ) (((FREQ) >= (uint8_t)1) && ((FREQ) <= I2C_MAX_INPUT_FREQ))

Macro used by the assert function to check that I2C Input clock frequency must be between 1MHz and 50MHz.

Definition at line 486 of file stm8s_i2c.h.

Referenced by I2C_Init().

#define IS_I2C_INTERRUPT_OK ( IT )
Value:
(((IT) == I2C_IT_ERR)     || \
   ((IT) == I2C_IT_EVT)     || \
   ((IT) == I2C_IT_BUF)     || \
   ((IT) == (I2C_IT_ERR | I2C_IT_EVT)) || \
   ((IT) == (I2C_IT_ERR | I2C_IT_BUF)) || \
   ((IT) == (I2C_IT_EVT | I2C_IT_BUF)) || \
   ((IT) == (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR)))

Macro used by the assert function to check the different I2C interrupt types.

Definition at line 383 of file stm8s_i2c.h.

Referenced by I2C_ITConfig().

#define IS_I2C_ITPENDINGBIT_OK ( ITPENDINGBIT )
Value:
(((ITPENDINGBIT) == I2C_ITPENDINGBIT_TXEMPTY)                                           || \
    ((ITPENDINGBIT) == I2C_ITPENDINGBIT_RXNOTEMPTY)                             || \
    ((ITPENDINGBIT) == I2C_ITPENDINGBIT_STOPDETECTION)                  || \
    ((ITPENDINGBIT) == I2C_ITPENDINGBIT_HEADERSENT)                             || \
    ((ITPENDINGBIT) == I2C_ITPENDINGBIT_TRANSFERFINISHED)       || \
    ((ITPENDINGBIT) == I2C_ITPENDINGBIT_ADDRESSSENTMATCHED) || \
    ((ITPENDINGBIT) == I2C_ITPENDINGBIT_STARTDETECTION)                 || \
    ((ITPENDINGBIT) == I2C_ITPENDINGBIT_WAKEUPFROMHALT)                 || \
    ((ITPENDINGBIT) == I2C_ITPENDINGBIT_OVERRUNUNDERRUN)                || \
    ((ITPENDINGBIT) == I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE) || \
    ((ITPENDINGBIT) == I2C_ITPENDINGBIT_ARBITRATIONLOSS)                || \
    ((ITPENDINGBIT) == I2C_ITPENDINGBIT_BUSERROR))

Macro used by the assert function to check the different I2C possible pending bits.

Definition at line 428 of file stm8s_i2c.h.

Referenced by I2C_GetITStatus().

#define IS_I2C_OUTPUT_CLOCK_FREQ_OK ( FREQ ) (((FREQ) >= (uint8_t)1) && ((FREQ) <= I2C_MAX_FAST_FREQ))

Macro used by the assert function to check that I2C Output clock frequency must be between 1Hz and 400kHz.

Definition at line 493 of file stm8s_i2c.h.

Referenced by I2C_Init().

#define IS_I2C_OWN_ADDRESS_OK ( ADDRESS ) ((ADDRESS) <= (uint16_t)0x03FF)

Macro used by the assert function to check the different I2C possible own address.

Definition at line 476 of file stm8s_i2c.h.

Referenced by I2C_Init().


STM8S/A Standard Peripherals Drivers: I2C_Exported_Functions

Functions
I2C_Exported_Functions

Functions

void | I2C_AcknowledgeConfig (I2C_Ack_TypeDef Ack)
Enable or Disable the I2C acknowledge and position acknowledge feature.
ErrorStatus | I2C_CheckEvent (I2C_Event_TypeDef I2C_Event)
I2C State Monitoring Functions.
void | I2C_ClearFlag (I2C_Flag_TypeDef I2C_FLAG)
Clear flags.
void | I2C_ClearITPendingBit (I2C_ITPendingBit_TypeDef I2C_ITPendingBit)
Clear IT pending bit.
void | I2C_Cmd (FunctionalState NewState)
Enables or disables the I2C peripheral.
void | I2C_DeInit (void)
Deinitializes the I2C peripheral registers to their default reset values.
void | I2C_FastModeDutyCycleConfig (I2C_DutyCycle_TypeDef I2C_DutyCycle)
Selects the specified I2C fast mode duty cycle.
void | I2C_GeneralCallCmd (FunctionalState NewState)
Enables or disables the I2C General Call feature.
void | I2C_GenerateSTART (FunctionalState NewState)
Generates I2C communication START condition.
void | I2C_GenerateSTOP (FunctionalState NewState)
Generates I2C communication STOP condition.
FlagStatus | I2C_GetFlagStatus (I2C_Flag_TypeDef I2C_Flag)
3) Flag-based state monitoring
ITStatus | I2C_GetITStatus (I2C_ITPendingBit_TypeDef I2C_ITPendingBit)
Checks whether the specified I2C interrupt has occurred or not.
I2C_Event_TypeDef | I2C_GetLastEvent (void)
2) Advanced state monitoring
void | I2C_Init (uint32_t OutputClockFrequencyHz, uint16_t OwnAddress, I2C_DutyCycle_TypeDef I2C_DutyCycle, I2C_Ack_TypeDef Ack, I2C_AddMode_TypeDef AddMode, uint8_t InputClockFrequencyMHz)
Initializes the I2C according to the specified parameters in standard or fast mode.
void | I2C_ITConfig (I2C_IT_TypeDef I2C_IT, FunctionalState NewState)
Enables or disables the specified I2C interrupt.
uint8_t | I2C_ReceiveData (void)
Returns the most recent received data.
void | I2C_Send7bitAddress (uint8_t Address, I2C_Direction_TypeDef Direction)
Transmits the 7-bit address (to select the) slave device.
void | I2C_SendData (uint8_t Data)
Send a byte by writing in the DR register.
void | I2C_SoftwareResetCmd (FunctionalState NewState)
Enables or disables I2C software reset.
void | I2C_StretchClockCmd (FunctionalState NewState)
Enables or disables the I2C clock stretching.

Function Documentation

void I2C_AcknowledgeConfig ( I2C_Ack_TypeDef Ack )

Enable or Disable the I2C acknowledge and position acknowledge feature.

Note:
This function must be called before data reception start
Parameters:
Ack : Specifies the acknowledge mode to apply. This parameter can be any of the I2C_Ack_TypeDef enumeration.
Return values:
None

Definition at line 345 of file stm8s_i2c.c.

References I2C, I2C_ACK_CURR, I2C_ACK_NONE, I2C_CR2_ACK, I2C_CR2_POS, and IS_I2C_ACK_OK.

Referenced by I2C_Init().

ErrorStatus I2C_CheckEvent ( I2C_Event_TypeDef I2C_Event )

I2C State Monitoring Functions.

This I2C driver provides three different ways for I2C state monitoring depending on the application requirements and constraints:

1) Basic state monitoring: Using I2C_CheckEvent() function: It compares the status registers (SR1, SR2 and SR3) content to a given event (can be the combination of one or more flags). It returns SUCCESS if the current status includes the given flags and returns ERROR if one or more flags are missing in the current status.

  • When to use:
    • This function is suitable for most applications as well as for startup activity since the events are fully described in the product reference manual (RM0016).
    • It is also suitable for users who need to define their own events.
  • Limitations:
    • If an error occurs (ie. error flags are set besides to the monitored flags), the I2C_CheckEvent() function may return SUCCESS despite the communication hold or corrupted real state. In this case, it is advised to use error interrupts to monitor the error events and handle them in the interrupt IRQ handler.
Note:
For error management, it is advised to use the following functions:
  • I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
  • I2C_IRQHandler() which is called when the I2C interrupts occur.
  • I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the I2Cx_IRQHandler() function in order to determine which error occurred.
  • I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() and/or I2C_GenerateStop() in order to clear the error flag and source and return to correct communication status.

2) Advanced state monitoring: Using the function I2C_GetLastEvent() which returns the image of both SR1 & SR3 status registers in a single word (uint16_t) (Status Register 3 value is shifted left by 8 bits and concatenated to Status Register 1).

  • When to use:
    • This function is suitable for the same applications above but it allows to overcome the limitations of I2C_GetFlagStatus() function (see below). The returned value could be compared to events already defined in the library (stm8s_i2c.h) or to custom values defined by user.
    • This function is suitable when multiple flags are monitored at the same time.
    • At the opposite of I2C_CheckEvent() function, this function allows user to choose when an event is accepted (when all events flags are set and no other flags are set or just when the needed flags are set like I2C_CheckEvent() function).
  • Limitations:
    • User may need to define his own events.
    • Same remark concerning the error management is applicable for this function if user decides to check only regular communication flags (and ignores error flags).

3) Flag-based state monitoring: Using the function I2C_GetFlagStatus() which simply returns the status of one single flag (ie. I2C_FLAG_RXNE ...).

  • When to use:
    • This function could be used for specific applications or in debug phase.
    • It is suitable when only one flag checking is needed (most I2C events are monitored through multiple flags).
  • Limitations:
    • When calling this function, the Status register is accessed. Some flags are cleared when the status register is accessed. So checking the status of one Flag, may clear other ones.
    • Function may need to be called twice or more in order to monitor one single event.

1) Basic state monitoring

This I2C driver provides three different ways for I2C state monitoring depending on the application requirements and constraints:

1) Basic state monitoring: Using I2C_CheckEvent() function: It compares the status registers (SR1, SR2 and SR3) content to a given event (can be the combination of one or more flags). It returns SUCCESS if the current status includes the given flags and returns ERROR if one or more flags are missing in the current status.

  • When to use:
    • This function is suitable for most applications as well as for startup activity since the events are fully described in the product reference manual (RM0016).
    • It is also suitable for users who need to define their own events.
  • Limitations:
    • If an error occurs (ie. error flags are set besides to the monitored flags), the I2C_CheckEvent() function may return SUCCESS despite the communication hold or corrupted real state. In this case, it is advised to use error interrupts to monitor the error events and handle them in the interrupt IRQ handler.
Note:
For error management, it is advised to use the following functions:
  • I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
  • I2C_IRQHandler() which is called when the I2C interrupts occur.
  • I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the I2C_IRQHandler() function in order to determine which error occurred.
  • I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() and/or I2C_GenerateStop() in order to clear the error flag and source and return to correct communication status.

2) Advanced state monitoring: Using the function I2C_GetLastEvent() which returns the image of both SR1 & SR3 status registers in a single word (uint16_t) (Status Register 3 value is shifted left by 8 bits and concatenated to Status Register 1).

  • When to use:
    • This function is suitable for the same applications above but it allows to overcome the limitations of I2C_GetFlagStatus() function (see below). The returned value could be compared to events already defined in the library (stm8s_i2c.h) or to custom values defined by user.
    • This function is suitable when multiple flags are monitored at the same time.
    • At the opposite of I2C_CheckEvent() function, this function allows user to choose when an event is accepted (when all events flags are set and no other flags are set or just when the needed flags are set like I2C_CheckEvent() function).
  • Limitations:
    • User may need to define his own events.
    • Same remark concerning the error management is applicable for this function if user decides to check only regular communication flags (and ignores error flags).

3) Flag-based state monitoring: Using the function I2C_GetFlagStatus() which simply returns the status of one single flag (ie. I2C_FLAG_RXNE ...).

  • When to use:
    • This function could be used for specific applications or in debug phase.
    • It is suitable when only one flag checking is needed (most I2C events are monitored through multiple flags).
  • Limitations:
    • When calling this function, the Status register is accessed. Some flags are cleared when the status register is accessed. So checking the status of one Flag, may clear other ones.
    • Function may need to be called twice or more in order to monitor one single event.

For detailed description of Events, please refer to section I2C_Events in stm8s_i2c.h file.

1) Basic state monitoring Checks whether the last I2C Event is equal to the one passed as parameter.

Parameters:
I2C_Event,: specifies the event to be checked. This parameter can be one of the following values:
  • I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1
  • I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1
  • I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1
  • I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2
  • (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2
  • I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3
  • (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3
  • I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2
  • I2C_EVENT_SLAVE_STOP_DETECTED : EV4
  • I2C_EVENT_MASTER_MODE_SELECT : EV5
  • I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6
  • I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6
  • I2C_EVENT_MASTER_BYTE_RECEIVED : EV7
  • I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8
  • I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2
  • I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9
Note:
: For detailed description of Events, please refer to section I2C_Events in stm8s_i2c.h file.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: Last event is equal to the I2C_EVENT
  • ERROR: Last event is different from the I2C_EVENT

Definition at line 578 of file stm8s_i2c.c.

References __IO, ERROR, I2C, I2C_EVENT_SLAVE_ACK_FAILURE, I2C_SR2_AF, IS_I2C_EVENT_OK, and SUCCESS.

void I2C_ClearFlag ( I2C_Flag_TypeDef I2C_FLAG )

Clear flags.

Parameters:
I2C_FLAG : Specifies the flag to clear This parameter can be any combination of the following values:
  • I2C_FLAG_WAKEUPFROMHALT: Wakeup from Halt
  • I2C_FLAG_OVERRUNUNDERRUN: Overrun/Underrun flag (Slave mode)
  • I2C_FLAG_ACKNOWLEDGEFAILURE: Acknowledge failure flag
  • I2C_FLAG_ARBITRATIONLOSS: Arbitration lost flag (Master mode)
  • I2C_FLAG_BUSERROR: Bus error flag.
Note:
Notes:
  • STOPF (STOP detection) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation to I2C_CR2 register.
  • ADD10 (10-bit header sent) is cleared by software sequence: a read operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the second byte of the address in DR register.
  • BTF (Byte Transfer Finished) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a read/write to I2C_DR register (I2C_SendData()).
  • ADDR (Address sent) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to I2C_SR3 register ((void)(I2C->SR3)).
  • SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR register (I2C_SendData()).
Return values:
None

Definition at line 759 of file stm8s_i2c.c.

References FLAG_Mask, I2C, and IS_I2C_CLEAR_FLAG_OK.

void I2C_ClearITPendingBit ( I2C_ITPendingBit_TypeDef I2C_ITPendingBit )

Clear IT pending bit.

Parameters:
I2C_ITPendingBit : specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:
  • I2C_ITPENDINGBIT_WAKEUPFROMHALT: Wakeup from Halt
  • I2C_ITPENDINGBIT_OVERRUNUNDERRUN: Overrun/Underrun interrupt (Slave mode)
  • I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE: Acknowledge failure interrupt
  • I2C_ITPENDINGBIT_ARBITRATIONLOSS: Arbitration lost interrupt (Master mode)
  • I2C_ITPENDINGBIT_BUSERROR: Bus error interrupt

Notes:

  • STOPF (STOP detection) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to I2C_CR2 register (I2C_AcknowledgeConfig() to configure the I2C peripheral Acknowledge).
  • ADD10 (10-bit header sent) is cleared by software sequence: a read operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second byte of the address in I2C_DR register.
  • BTF (Byte Transfer Finished) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a read/write to I2C_DR register (I2C_SendData()).
  • ADDR (Address sent) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to I2C_SR3 register ((void)(I2C->SR3)).
  • SB (Start Bit) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to I2C_DR register (I2C_SendData()).
    Return values:
    None

Definition at line 871 of file stm8s_i2c.c.

References FLAG_Mask, I2C, and IS_I2C_CLEAR_ITPENDINGBIT_OK.

void I2C_Cmd ( FunctionalState NewState )

Enables or disables the I2C peripheral.

Parameters:
NewState : Indicate the new I2C peripheral state. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 202 of file stm8s_i2c.c.

References DISABLE, I2C, I2C_CR1_PE, and IS_FUNCTIONALSTATE_OK.

void I2C_DeInit ( void )

Deinitializes the I2C peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 67 of file stm8s_i2c.c.

References I2C, I2C_CCRH_RESET_VALUE, I2C_CCRL_RESET_VALUE, I2C_CR1_RESET_VALUE, I2C_CR2_RESET_VALUE, I2C_FREQR_RESET_VALUE, I2C_ITR_RESET_VALUE, I2C_OARH_RESET_VALUE, I2C_OARL_RESET_VALUE, and I2C_TRISER_RESET_VALUE.

void I2C_FastModeDutyCycleConfig ( I2C_DutyCycle_TypeDef I2C_DutyCycle )

Selects the specified I2C fast mode duty cycle.

Parameters:
I2C_DutyCycle : Specifies the duty cycle to apply. This parameter can be any of the I2C_DutyCycle_TypeDef enumeration.
Return values:
None

Definition at line 405 of file stm8s_i2c.c.

References I2C, I2C_CCRH_DUTY, I2C_DUTYCYCLE_16_9, and IS_I2C_DUTYCYCLE_OK.

void I2C_GeneralCallCmd ( FunctionalState NewState )

Enables or disables the I2C General Call feature.

Parameters:
NewState : State of the General Call feature. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 225 of file stm8s_i2c.c.

References DISABLE, I2C, I2C_CR1_ENGC, and IS_FUNCTIONALSTATE_OK.

void I2C_GenerateSTART ( FunctionalState NewState )

Generates I2C communication START condition.

Note:
CCR must be programmed, i.e. I2C_Init function must have been called with a valid I2C_ClockSpeed
Parameters:
NewState : Enable or disable the start condition. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 250 of file stm8s_i2c.c.

References DISABLE, I2C, I2C_CR2_START, and IS_FUNCTIONALSTATE_OK.

void I2C_GenerateSTOP ( FunctionalState NewState )

Generates I2C communication STOP condition.

Parameters:
NewState : Enable or disable the stop condition. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 273 of file stm8s_i2c.c.

References DISABLE, I2C, I2C_CR2_STOP, and IS_FUNCTIONALSTATE_OK.

FlagStatus I2C_GetFlagStatus ( I2C_Flag_TypeDef I2C_Flag )

3) Flag-based state monitoring

Checks whether the specified I2C flag is set or not.

Parameters:
I2C_Flag,: specifies the flag to check. This parameter can be one of the following values:
  • I2C_FLAG_GENERALCALL: General call header flag (Slave mode)
  • I2C_FLAG_TRANSMITTERRECEIVER: Transmitter/Receiver flag
  • I2C_FLAG_BUSBUSY: Bus busy flag
  • I2C_FLAG_MASTERSLAVE: Master/Slave flag
  • I2C_FLAG_WAKEUPFROMHALT: Wake up from HALT flag
  • I2C_FLAG_OVERRUNUNDERRUN: Overrun/Underrun flag (Slave mode)
  • I2C_FLAG_ACKNOWLEDGEFAILURE: Acknowledge failure flag
  • I2C_FLAG_ARBITRATIONLOSS: Arbitration lost flag (Master mode)
  • I2C_FLAG_BUSERROR: Bus error flag
  • I2C_FLAG_TXEMPTY: Data register empty flag (Transmitter)
  • I2C_FLAG_RXNOTEMPTY: Data register not empty (Receiver) flag
  • I2C_FLAG_STOPDETECTION: Stop detection flag (Slave mode)
  • I2C_FLAG_HEADERSENT: 10-bit header sent flag (Master mode)
  • I2C_FLAG_TRANSFERFINISHED: Byte transfer finished flag
  • I2C_FLAG_ADDRESSSENTMATCHED: Address sent flag (Master mode) “ADSL” Address matched flag (Slave mode)”ENDAD”
  • I2C_FLAG_STARTDETECTION: Start bit flag (Master mode)
Return values:
The new state of I2C_FLAG (SET or RESET).

Definition at line 679 of file stm8s_i2c.c.

References I2C, IS_I2C_FLAG_OK, RESET, and SET.

ITStatus I2C_GetITStatus ( I2C_ITPendingBit_TypeDef I2C_ITPendingBit )

Checks whether the specified I2C interrupt has occurred or not.

Parameters:
I2C_ITPendingBit,: specifies the interrupt source to check. This parameter can be one of the following values:
  • I2C_ITPENDINGBIT_WAKEUPFROMHALT: Wakeup from Halt
  • I2C_ITPENDINGBIT_OVERRUNUNDERRUN: Overrun/Underrun flag (Slave mode)
  • I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE: Acknowledge failure flag
  • I2C_ITPENDINGBIT_ARBITRATIONLOSS: Arbitration lost flag (Master mode)
  • I2C_ITPENDINGBIT_BUSERROR: Bus error flag
  • I2C_ITPENDINGBIT_TXEMPTY: Data register empty flag (Transmitter)
  • I2C_ITPENDINGBIT_RXNOTEMPTY: Data register not empty (Receiver) flag
  • I2C_ITPENDINGBIT_STOPDETECTION: Stop detection flag (Slave mode)
  • I2C_ITPENDINGBIT_HEADERSENT: 10-bit header sent flag (Master mode)
  • I2C_ITPENDINGBIT_TRANSFERFINISHED: Byte transfer finished flag
  • I2C_ITPENDINGBIT_ADDRESSSENTMATCHED: Address sent flag (Master mode) “ADSL” Address matched flag (Slave mode)“ENDAD”
  • I2C_ITPENDINGBIT_STARTDETECTION: Start bit flag (Master mode)
Return values:
The new state of I2C_ITPendingBit This parameter can be any of the ITStatus enumeration.

Definition at line 791 of file stm8s_i2c.c.

References __IO, I2C, IS_I2C_ITPENDINGBIT_OK, ITEN_Mask, REGISTER_Mask, REGISTER_SR1_Index, RESET, and SET.

I2C_Event_TypeDef I2C_GetLastEvent ( void )

2) Advanced state monitoring

Returns the last I2C Event.

Note:
: For detailed description of Events, please refer to section I2C_Events in stm8s_i2c.h file.
Return values:
The last event This parameter can be any of the I2C_Event_TypeDef enumeration.

Definition at line 628 of file stm8s_i2c.c.

References __IO, I2C, I2C_EVENT_SLAVE_ACK_FAILURE, and I2C_SR2_AF.

void I2C_Init | ( | uint32_t | OutputClockFrequencyHz,
 |  | uint16_t | OwnAddress,
 |  | I2C_DutyCycle_TypeDef | I2C_DutyCycle,
 |  | I2C_Ack_TypeDef | Ack,
 |  | I2C_AddMode_TypeDef | AddMode,
 |  | uint8_t | InputClockFrequencyMHz
 | ) |  |

Initializes the I2C according to the specified parameters in standard or fast mode.

Parameters:
OutputClockFrequencyHz | : Specifies the output clock frequency in Hz.
OwnAddress | : Specifies the own address.
I2C_DutyCycle | : Specifies the duty cycle to apply in fast mode. This parameter can be any of the I2C_DutyCycle_TypeDef enumeration.
Note:
This parameter don't have impact when the OutputClockFrequency lower than 100KHz.
Parameters:
Ack | : Specifies the acknowledge mode to apply. This parameter can be any of the I2C_Ack_TypeDef enumeration.
AddMode | : Specifies the acknowledge address to apply. This parameter can be any of the I2C_AddMode_TypeDef enumeration.
InputClockFrequencyMHz | : Specifies the input clock frequency in MHz.
Return values:
None

Definition at line 96 of file stm8s_i2c.c.

References I2C, I2C_AcknowledgeConfig(), I2C_CCRH_CCR, I2C_CCRH_DUTY, I2C_CCRH_FS, I2C_CCRL_CCR, I2C_CR1_PE, I2C_DUTYCYCLE_2, I2C_FREQR_FREQ, I2C_MAX_STANDARD_FREQ, I2C_OARH_ADDCONF, IS_I2C_ACK_OK, IS_I2C_ADDMODE_OK, IS_I2C_DUTYCYCLE_OK, IS_I2C_INPUT_CLOCK_FREQ_OK, IS_I2C_OUTPUT_CLOCK_FREQ_OK, and IS_I2C_OWN_ADDRESS_OK.

void I2C_ITConfig | ( | I2C_IT_TypeDef | I2C_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C interrupt.

Parameters:
I2C_IT | : Name of the interrupt to enable or disable. This parameter can be any of the I2C_IT_TypeDef enumeration.
NewState | : State of the interrupt to apply. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 381 of file stm8s_i2c.c.

References DISABLE, I2C, IS_FUNCTIONALSTATE_OK, and IS_I2C_INTERRUPT_OK.

uint8_t I2C_ReceiveData ( void )

Returns the most recent received data.

Parameters:
None
Return values:
uint8_t : The value of the received byte data.

Definition at line 427 of file stm8s_i2c.c.

References I2C.

void I2C_Send7bitAddress | ( | uint8_t | Address,
 |  | I2C_Direction_TypeDef | Direction
 | ) |  |

Transmits the 7-bit address (to select the) slave device.

Parameters:
Address | : Specifies the slave address which will be transmitted.
Direction | : Specifies whether the I2C device will be a Transmitter or a Receiver. This parameter can be any of the I2C_Direction_TypeDef enumeration.
Return values:
None

Definition at line 440 of file stm8s_i2c.c.

References I2C, IS_I2C_ADDRESS_OK, and IS_I2C_DIRECTION_OK.

void I2C_SendData ( uint8_t Data )

Send a byte by writing in the DR register.

Parameters:
Data : Byte to be sent.
Return values:
None

Definition at line 458 of file stm8s_i2c.c.

References I2C.

void I2C_SoftwareResetCmd ( FunctionalState NewState )

Enables or disables I2C software reset.

Parameters:
NewState : Specifies the new state of the I2C software reset. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 296 of file stm8s_i2c.c.

References DISABLE, I2C, I2C_CR2_SWRST, and IS_FUNCTIONALSTATE_OK.

void I2C_StretchClockCmd ( FunctionalState NewState )

Enables or disables the I2C clock stretching.

Parameters:
NewState : Specifies the new state of the I2C Clock stretching. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 320 of file stm8s_i2c.c.

References DISABLE, I2C, I2C_CR1_NOSTRETCH, and IS_FUNCTIONALSTATE_OK.


STM8S/A Standard Peripherals Drivers: ITC_Exported_Types

Enumerations
ITC_Exported_Types

Enumerations

enum ITC_Irq_TypeDef {
ITC_IRQ_TLI = (uint8_t)0, ITC_IRQ_AWU = (uint8_t)1, ITC_IRQ_CLK = (uint8_t)2, ITC_IRQ_PORTA = (uint8_t)3,
ITC_IRQ_PORTB = (uint8_t)4, ITC_IRQ_PORTC = (uint8_t)5, ITC_IRQ_PORTD = (uint8_t)6, ITC_IRQ_PORTE = (uint8_t)7,
ITC_IRQ_SPI = (uint8_t)10, ITC_IRQ_TIM1_OVF = (uint8_t)11, ITC_IRQ_TIM1_CAPCOM = (uint8_t)12, ITC_IRQ_TIM2_OVF = (uint8_t)13,
ITC_IRQ_TIM2_CAPCOM = (uint8_t)14, ITC_IRQ_TIM3_OVF = (uint8_t)15, ITC_IRQ_TIM3_CAPCOM = (uint8_t)16, ITC_IRQ_I2C = (uint8_t)19,
ITC_IRQ_TIM4_OVF = (uint8_t)23, ITC_IRQ_EEPROM_EEC = (uint8_t)24
}
ITC Interrupt Lines selection. More...
enum ITC_PriorityLevel_TypeDef { ITC_PRIORITYLEVEL_0 = (uint8_t)0x02, ITC_PRIORITYLEVEL_1 = (uint8_t)0x01, ITC_PRIORITYLEVEL_2 = (uint8_t)0x00, ITC_PRIORITYLEVEL_3 = (uint8_t)0x03 }
ITC Priority Levels selection. More...

Enumeration Type Documentation

enum ITC_Irq_TypeDef

ITC Interrupt Lines selection.

Enumerator:
ITC_IRQ_TLI

Software interrupt

ITC_IRQ_AWU

Auto wake up from halt interrupt

ITC_IRQ_CLK

Clock controller interrupt

ITC_IRQ_PORTA

Port A external interrupts

ITC_IRQ_PORTB

Port B external interrupts

ITC_IRQ_PORTC

Port C external interrupts

ITC_IRQ_PORTD

Port D external interrupts

ITC_IRQ_PORTE

Port E external interrupts

ITC_IRQ_SPI

SPI interrupt

ITC_IRQ_TIM1_OVF

TIM1 update/overflow/underflow/trigger/ break interrupt

ITC_IRQ_TIM1_CAPCOM

TIM1 capture/compare interrupt

ITC_IRQ_TIM2_OVF

TIM2 update /overflow interrupt

ITC_IRQ_TIM2_CAPCOM

TIM2 capture/compare interrupt

ITC_IRQ_TIM3_OVF

TIM3 update /overflow interrupt

ITC_IRQ_TIM3_CAPCOM

TIM3 update /overflow interrupt

ITC_IRQ_I2C

I2C interrupt

ITC_IRQ_TIM4_OVF

TIM4 update /overflow interrupt

ITC_IRQ_EEPROM_EEC

Flash interrupt

Definition at line 44 of file stm8s_itc.h.

enum ITC_PriorityLevel_TypeDef

ITC Priority Levels selection.

Enumerator:
ITC_PRIORITYLEVEL_0

Software priority level 0 (cannot be written)

ITC_PRIORITYLEVEL_1

Software priority level 1

ITC_PRIORITYLEVEL_2

Software priority level 2

ITC_PRIORITYLEVEL_3

Software priority level 3

Definition at line 120 of file stm8s_itc.h.


STM8S/A Standard Peripherals Drivers: ITC_Exported_Constants

Defines
ITC_Exported_Constants

Defines

#define CPU_SOFT_INT_DISABLED ((uint8_t)0x28)

Define Documentation

#define CPU_SOFT_INT_DISABLED ((uint8_t)0x28)

Mask for I1 and I0 bits in CPU_CC register

Definition at line 136 of file stm8s_itc.h.


STM8S/A Standard Peripherals Drivers: ITC_Private_Macros

Defines
ITC_Private_Macros

Macros used by the assert function in order to check the different functions parameters. More...

Defines

#define | IS_ITC_INTERRUPTS_DISABLED (ITC_GetSoftIntStatus() == CPU_SOFT_INT_DISABLED)
#define | IS_ITC_IRQ_OK(IRQ) ((IRQ) <= (uint8_t)24)
#define | IS_ITC_PRIORITY_OK(PriorityValue)

Detailed Description

Macros used by the assert function in order to check the different functions parameters.

Define Documentation

#define IS_ITC_INTERRUPTS_DISABLED (ITC_GetSoftIntStatus() == CPU_SOFT_INT_DISABLED)

Definition at line 161 of file stm8s_itc.h.

Referenced by ITC_SetSoftwarePriority().

#define IS_ITC_IRQ_OK ( IRQ ) ((IRQ) <= (uint8_t)24)

Definition at line 151 of file stm8s_itc.h.

Referenced by ITC_GetSoftwarePriority(), and ITC_SetSoftwarePriority().

#define IS_ITC_PRIORITY_OK ( PriorityValue )
Value:
(((PriorityValue) == ITC_PRIORITYLEVEL_0) || \
   ((PriorityValue) == ITC_PRIORITYLEVEL_1) || \
   ((PriorityValue) == ITC_PRIORITYLEVEL_2) || \
   ((PriorityValue) == ITC_PRIORITYLEVEL_3))

Definition at line 154 of file stm8s_itc.h.

Referenced by ITC_SetSoftwarePriority().


STM8S/A Standard Peripherals Drivers: ITC_Exported_Functions

Functions
ITC_Exported_Functions

Functions

void | ITC_DeInit (void)
Deinitializes the ITC registers to their default reset value.
uint8_t | ITC_GetCPUCC (void)
Utility function used to read CC register.
uint8_t | ITC_GetSoftIntStatus (void)
Gets the interrupt software priority bits (I1, I0) value from CPU CC register.
ITC_PriorityLevel_TypeDef | ITC_GetSoftwarePriority (ITC_Irq_TypeDef IrqNum)
Gets the software priority of the specified interrupt source.
void | ITC_SetSoftwarePriority (ITC_Irq_TypeDef IrqNum, ITC_PriorityLevel_TypeDef PriorityValue)
Sets the software priority of the specified interrupt source.

Function Documentation

void ITC_DeInit ( void )

Deinitializes the ITC registers to their default reset value.

Parameters:
None
Return values:
None

Definition at line 80 of file stm8s_itc.c.

References ITC, and ITC_SPRX_RESET_VALUE.

uint8_t ITC_GetCPUCC ( void )

Utility function used to read CC register.

Parameters:
None
Return values:
CPU CC register value

Definition at line 50 of file stm8s_itc.c.

Referenced by ITC_GetSoftIntStatus().

uint8_t ITC_GetSoftIntStatus ( void )

Gets the interrupt software priority bits (I1, I0) value from CPU CC register.

Parameters:
None
Return values:
The interrupt software priority bits value.

Definition at line 97 of file stm8s_itc.c.

References CPU_CC_I1I0, and ITC_GetCPUCC().

ITC_PriorityLevel_TypeDef ITC_GetSoftwarePriority ( ITC_Irq_TypeDef IrqNum )

Gets the software priority of the specified interrupt source.

Parameters:
IrqNum : Specifies the peripheral interrupt source.
Return values:
ITC_PriorityLevel_TypeDef : Specifies the software priority of the interrupt source.

Definition at line 107 of file stm8s_itc.c.

References IS_ITC_IRQ_OK, ITC, ITC_IRQ_AWU, ITC_IRQ_CLK, ITC_IRQ_EEPROM_EEC, ITC_IRQ_I2C, ITC_IRQ_PORTA, ITC_IRQ_PORTB, ITC_IRQ_PORTC, ITC_IRQ_PORTD, ITC_IRQ_PORTE, ITC_IRQ_SPI, ITC_IRQ_TIM1_CAPCOM, ITC_IRQ_TIM1_OVF, ITC_IRQ_TIM2_CAPCOM, ITC_IRQ_TIM2_OVF, ITC_IRQ_TIM3_CAPCOM, ITC_IRQ_TIM3_OVF, ITC_IRQ_TIM4_OVF, and ITC_IRQ_TLI.

void ITC_SetSoftwarePriority | ( | ITC_Irq_TypeDef | IrqNum,
 |  | ITC_PriorityLevel_TypeDef | PriorityValue
 | ) |  |

Sets the software priority of the specified interrupt source.

Note:
- The modification of the software priority is only possible when the interrupts are disabled.
  • The normal behavior is to disable the interrupt before calling this function, and re-enable it after.
  • The priority level 0 cannot be set (see product specification for more details).
Parameters:
IrqNum | : Specifies the peripheral interrupt source.
PriorityValue | : Specifies the software priority value to set, can be a value of ITC_PriorityLevel_TypeDef .
Return values:
None

Definition at line 220 of file stm8s_itc.c.

References IS_ITC_INTERRUPTS_DISABLED, IS_ITC_IRQ_OK, IS_ITC_PRIORITY_OK, ITC, ITC_IRQ_AWU, ITC_IRQ_CLK, ITC_IRQ_EEPROM_EEC, ITC_IRQ_I2C, ITC_IRQ_PORTA, ITC_IRQ_PORTB, ITC_IRQ_PORTC, ITC_IRQ_PORTD, ITC_IRQ_PORTE, ITC_IRQ_SPI, ITC_IRQ_TIM1_CAPCOM, ITC_IRQ_TIM1_OVF, ITC_IRQ_TIM2_CAPCOM, ITC_IRQ_TIM2_OVF, ITC_IRQ_TIM3_CAPCOM, ITC_IRQ_TIM3_OVF, ITC_IRQ_TIM4_OVF, and ITC_IRQ_TLI.


STM8S/A Standard Peripherals Drivers: TIM2_Exported_Functions

Functions
TIM2_Exported_Functions

Functions

void | TIM2_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM2 peripheral Preload register on ARR.
void | TIM2_CCPreloadControl (FunctionalState NewState)
void | TIM2_CCxCmd (TIM2_Channel_TypeDef TIM2_Channel, FunctionalState NewState)
Enables or disables the TIM2 Capture Compare Channel x.
void | TIM2_ClearFlag (TIM2_FLAG_TypeDef TIM2_FLAG)
Clears the TIM2’s pending flags.
void | TIM2_ClearITPendingBit (TIM2_IT_TypeDef TIM2_IT)
Clears the TIM2's interrupt pending bits.
void | TIM2_Cmd (FunctionalState NewState)
Enables or disables the TIM2 peripheral.
void | TIM2_DeInit (void)
Deinitializes the TIM2 peripheral registers to their default reset values.
void | TIM2_ForcedOC1Config (TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
Forces the TIM2 Channel1 output waveform to active or inactive level.
void | TIM2_ForcedOC2Config (TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
Forces the TIM2 Channel2 output waveform to active or inactive level.
void | TIM2_ForcedOC3Config (TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
Forces the TIM2 Channel3 output waveform to active or inactive level.
void | TIM2_GenerateEvent (TIM2_EventSource_TypeDef TIM2_EventSource)
Configures the TIM2 event to be generated by software.
uint16_t | TIM2_GetCapture1 (void)
Gets the TIM2 Input Capture 1 value.
uint16_t | TIM2_GetCapture2 (void)
Gets the TIM2 Input Capture 2 value.
uint16_t | TIM2_GetCapture3 (void)
Gets the TIM2 Input Capture 3 value.
uint16_t | TIM2_GetCounter (void)
Gets the TIM2 Counter value.
FlagStatus | TIM2_GetFlagStatus (TIM2_FLAG_TypeDef TIM2_FLAG)
Checks whether the specified TIM2 flag is set or not.
ITStatus | TIM2_GetITStatus (TIM2_IT_TypeDef TIM2_IT)
Checks whether the TIM2 interrupt has occurred or not.
TIM2_Prescaler_TypeDef | TIM2_GetPrescaler (void)
Gets the TIM2 Prescaler value.
void | TIM2_ICInit (TIM2_Channel_TypeDef TIM2_Channel, TIM2_ICPolarity_TypeDef TIM2_ICPolarity, TIM2_ICSelection_TypeDef TIM2_ICSelection, TIM2_ICPSC_TypeDef TIM2_ICPrescaler, uint8_t TIM2_ICFilter)
Initializes the TIM2 peripheral according to the specified parameters.
void | TIM2_InternalClockConfig (void)
void | TIM2_ITConfig (TIM2_IT_TypeDef TIM2_IT, FunctionalState NewState)
Enables or disables the specified TIM2 interrupts.
void | TIM2_OC1Init (TIM2_OCMode_TypeDef TIM2_OCMode, TIM2_OutputState_TypeDef TIM2_OutputState, uint16_t TIM2_Pulse, TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Initializes the TIM2 Channel1 according to the specified parameters.
void | TIM2_OC1PolarityConfig (TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Configures the TIM2 Channel 1 polarity.
void | TIM2_OC1PreloadConfig (FunctionalState NewState)
Enables or disables the TIM2 peripheral Preload Register on CCR1.
void | TIM2_OC2Init (TIM2_OCMode_TypeDef TIM2_OCMode, TIM2_OutputState_TypeDef TIM2_OutputState, uint16_t TIM2_Pulse, TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Initializes the TIM2 Channel2 according to the specified parameters.
void | TIM2_OC2PolarityConfig (TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Configures the TIM2 Channel 2 polarity.
void | TIM2_OC2PreloadConfig (FunctionalState NewState)
Enables or disables the TIM2 peripheral Preload Register on CCR2.
void | TIM2_OC3Init (TIM2_OCMode_TypeDef TIM2_OCMode, TIM2_OutputState_TypeDef TIM2_OutputState, uint16_t TIM2_Pulse, TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Initializes the TIM2 Channel3 according to the specified parameters.
void | TIM2_OC3PolarityConfig (TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Configures the TIM2 Channel 3 polarity.
void | TIM2_OC3PreloadConfig (FunctionalState NewState)
Enables or disables the TIM2 peripheral Preload Register on CCR3.
void | TIM2_PrescalerConfig (TIM2_Prescaler_TypeDef Prescaler, TIM2_PSCReloadMode_TypeDef TIM2_PSCReloadMode)
Configures the TIM2 Prescaler.
void | TIM2_PWMIConfig (TIM2_Channel_TypeDef TIM2_Channel, TIM2_ICPolarity_TypeDef TIM2_ICPolarity, TIM2_ICSelection_TypeDef TIM2_ICSelection, TIM2_ICPSC_TypeDef TIM2_ICPrescaler, uint8_t TIM2_ICFilter)
Configures the TIM2 peripheral in PWM Input Mode according to the specified parameters.
void | TIM2_SelectOCxM (TIM2_Channel_TypeDef TIM2_Channel, TIM2_OCMode_TypeDef TIM2_OCMode)
Selects the TIM2 Output Compare Mode.
void | TIM2_SelectOnePulseMode (TIM2_OPMode_TypeDef TIM2_OPMode)
Selects the TIM2’s One Pulse Mode.
void | TIM2_SetAutoreload (uint16_t Autoreload)
Sets the TIM2 Autoreload Register value.
void | TIM2_SetCompare1 (uint16_t Compare1)
Sets the TIM2 Capture Compare1 Register value.
void | TIM2_SetCompare2 (uint16_t Compare2)
Sets the TIM2 Capture Compare2 Register value.
void | TIM2_SetCompare3 (uint16_t Compare3)
Sets the TIM2 Capture Compare3 Register value.
void | TIM2_SetCounter (uint16_t Counter)
Sets the TIM2 Counter Register value.
void | TIM2_SetIC1Prescaler (TIM2_ICPSC_TypeDef TIM2_IC1Prescaler)
Sets the TIM2 Input Capture 1 Prescaler.
void | TIM2_SetIC2Prescaler (TIM2_ICPSC_TypeDef TIM2_IC2Prescaler)
Sets the TIM2 Input Capture 2 prescaler.
void | TIM2_SetIC3Prescaler (TIM2_ICPSC_TypeDef TIM2_IC3Prescaler)
Sets the TIM2 Input Capture 3 prescaler.
void | TIM2_TimeBaseInit (TIM2_Prescaler_TypeDef TIM2_Prescaler, uint16_t TIM2_Period)
Initializes the TIM2 Time Base Unit according to the specified parameters.
void | TIM2_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM2 Update event.
void | TIM2_UpdateRequestConfig (TIM2_UpdateSource_TypeDef TIM2_UpdateSource)
Selects the TIM2 Update Request Interrupt source.

Function Documentation

void TIM2_ARRPreloadConfig ( FunctionalState NewState )

Enables or disables TIM2 peripheral Preload register on ARR.

Parameters:
NewState new state of the TIM2 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 561 of file stm8s_tim2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM2_CR1_ARPE.

void TIM2_CCPreloadControl ( FunctionalState NewState )
void TIM2_CCxCmd | ( | TIM2_Channel_TypeDef | TIM2_Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the TIM2 Capture Compare Channel x.

Parameters:
TIM2_Channel specifies the TIM2 Channel. This parameter can be one of the following values:
  • TIM2_CHANNEL_1: TIM2 Channel1
  • TIM2_CHANNEL_2: TIM2 Channel2
  • TIM2_CHANNEL_3: TIM2 Channel3
NewState specifies the TIM2 Channel CCxE bit new state. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 745 of file stm8s_tim2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, IS_TIM2_CHANNEL_OK, TIM2_CCER1_CC1E, TIM2_CCER1_CC2E, TIM2_CCER2_CC3E, TIM2_CHANNEL_1, and TIM2_CHANNEL_2.

void TIM2_ClearFlag ( TIM2_FLAG_TypeDef TIM2_FLAG )

Clears the TIM2’s pending flags.

Parameters:
TIM2_FLAG specifies the flag to clear. This parameter can be one of the following values:
  • TIM2_FLAG_UPDATE: TIM2 update Flag
  • TIM2_FLAG_CC1: TIM2 Capture Compare 1 Flag
  • TIM2_FLAG_CC2: TIM2 Capture Compare 2 Flag
  • TIM2_FLAG_CC3: TIM2 Capture Compare 3 Flag
  • TIM2_FLAG_CC1OF: TIM2 Capture Compare 1 over capture Flag
  • TIM2_FLAG_CC2OF: TIM2 Capture Compare 2 over capture Flag
  • TIM2_FLAG_CC3OF: TIM2 Capture Compare 3 over capture Flag
Return values:
None.

Definition at line 1103 of file stm8s_tim2.c.

References IS_TIM2_CLEAR_FLAG_OK.

void TIM2_ClearITPendingBit ( TIM2_IT_TypeDef TIM2_IT )

Clears the TIM2's interrupt pending bits.

Parameters:
TIM2_IT specifies the pending bit to clear. This parameter can be one of the following values:
  • TIM2_IT_UPDATE: TIM2 update Interrupt source
  • TIM2_IT_CC1: TIM2 Capture Compare 1 Interrupt source
  • TIM2_IT_CC2: TIM2 Capture Compare 2 Interrupt source
  • TIM2_IT_CC3: TIM2 Capture Compare 3 Interrupt source
Return values:
None.

Definition at line 1156 of file stm8s_tim2.c.

References IS_TIM2_IT_OK.

void TIM2_Cmd ( FunctionalState NewState )

Enables or disables the TIM2 peripheral.

Parameters:
NewState new state of the TIM2 peripheral. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 339 of file stm8s_tim2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM2_CR1_CEN.

void TIM2_DeInit ( void )

Deinitializes the TIM2 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 52 of file stm8s_tim2.c.

References TIM2_ARRH_RESET_VALUE, TIM2_ARRL_RESET_VALUE, TIM2_CCER1_RESET_VALUE, TIM2_CCER2_RESET_VALUE, TIM2_CCMR1_RESET_VALUE, TIM2_CCMR2_RESET_VALUE, TIM2_CCMR3_RESET_VALUE, TIM2_CCR1H_RESET_VALUE, TIM2_CCR1L_RESET_VALUE, TIM2_CCR2H_RESET_VALUE, TIM2_CCR2L_RESET_VALUE, TIM2_CCR3H_RESET_VALUE, TIM2_CCR3L_RESET_VALUE, TIM2_CNTRH_RESET_VALUE, TIM2_CNTRL_RESET_VALUE, TIM2_CR1_RESET_VALUE, TIM2_IER_RESET_VALUE, TIM2_PSCR_RESET_VALUE, TIM2_SR1_RESET_VALUE, and TIM2_SR2_RESET_VALUE.

void TIM2_ForcedOC1Config ( TIM2_ForcedAction_TypeDef TIM2_ForcedAction )

Forces the TIM2 Channel1 output waveform to active or inactive level.

Parameters:
TIM2_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:
  • TIM2_FORCEDACTION_ACTIVE: Force active level on OC1REF
  • TIM2_FORCEDACTION_INACTIVE: Force inactive level on OC1REF.
Return values:
None

Definition at line 507 of file stm8s_tim2.c.

References IS_TIM2_FORCED_ACTION_OK, and TIM2_CCMR_OCM.

void TIM2_ForcedOC2Config ( TIM2_ForcedAction_TypeDef TIM2_ForcedAction )

Forces the TIM2 Channel2 output waveform to active or inactive level.

Parameters:
TIM2_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:
  • TIM2_FORCEDACTION_ACTIVE: Force active level on OC2REF
  • TIM2_FORCEDACTION_INACTIVE: Force inactive level on OC2REF.
Return values:
None

Definition at line 526 of file stm8s_tim2.c.

References IS_TIM2_FORCED_ACTION_OK, and TIM2_CCMR_OCM.

void TIM2_ForcedOC3Config ( TIM2_ForcedAction_TypeDef TIM2_ForcedAction )

Forces the TIM2 Channel3 output waveform to active or inactive level.

Parameters:
TIM2_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:
  • TIM2_FORCEDACTION_ACTIVE: Force active level on OC3REF
  • TIM2_FORCEDACTION_INACTIVE: Force inactive level on OC3REF.
Return values:
None

Definition at line 545 of file stm8s_tim2.c.

References IS_TIM2_FORCED_ACTION_OK, and TIM2_CCMR_OCM.

void TIM2_GenerateEvent ( TIM2_EventSource_TypeDef TIM2_EventSource )

Configures the TIM2 event to be generated by software.

Parameters:
TIM2_EventSource specifies the event source. This parameter can be one of the following values:
  • TIM2_EVENTSOURCE_UPDATE: TIM2 update Event source
  • TIM2_EVENTSOURCE_CC1: TIM2 Capture Compare 1 Event source
  • TIM2_EVENTSOURCE_CC2: TIM2 Capture Compare 2 Event source
  • TIM2_EVENTSOURCE_CC3: TIM2 Capture Compare 3 Event source
Return values:
None

Definition at line 653 of file stm8s_tim2.c.

References IS_TIM2_EVENT_SOURCE_OK.

uint16_t TIM2_GetCapture1 ( void )

Gets the TIM2 Input Capture 1 value.

Parameters:
None
Return values:
Capture Compare 1 Register value.

Definition at line 975 of file stm8s_tim2.c.

uint16_t TIM2_GetCapture2 ( void )

Gets the TIM2 Input Capture 2 value.

Parameters:
None
Return values:
Capture Compare 2 Register value.

Definition at line 995 of file stm8s_tim2.c.

uint16_t TIM2_GetCapture3 ( void )

Gets the TIM2 Input Capture 3 value.

Parameters:
None
Return values:
Capture Compare 3 Register value.

Definition at line 1015 of file stm8s_tim2.c.

uint16_t TIM2_GetCounter ( void )

Gets the TIM2 Counter value.

Parameters:
None
Return values:
Counter Register value.

Definition at line 1035 of file stm8s_tim2.c.

FlagStatus TIM2_GetFlagStatus ( TIM2_FLAG_TypeDef TIM2_FLAG )

Checks whether the specified TIM2 flag is set or not.

Parameters:
TIM2_FLAG specifies the flag to check. This parameter can be one of the following values:
  • TIM2_FLAG_UPDATE: TIM2 update Flag
  • TIM2_FLAG_CC1: TIM2 Capture Compare 1 Flag
  • TIM2_FLAG_CC2: TIM2 Capture Compare 2 Flag
  • TIM2_FLAG_CC3: TIM2 Capture Compare 3 Flag
  • TIM2_FLAG_CC1OF: TIM2 Capture Compare 1 over capture Flag
  • TIM2_FLAG_CC2OF: TIM2 Capture Compare 2 over capture Flag
  • TIM2_FLAG_CC3OF: TIM2 Capture Compare 3 over capture Flag
Return values:
FlagStatus The new state of TIM2_FLAG (SET or RESET).

Definition at line 1068 of file stm8s_tim2.c.

References IS_TIM2_GET_FLAG_OK, RESET, and SET.

ITStatus TIM2_GetITStatus ( TIM2_IT_TypeDef TIM2_IT )

Checks whether the TIM2 interrupt has occurred or not.

Parameters:
TIM2_IT specifies the TIM2 interrupt source to check. This parameter can be one of the following values:
  • TIM2_IT_UPDATE: TIM2 update Interrupt source
  • TIM2_IT_CC1: TIM2 Capture Compare 1 Interrupt source
  • TIM2_IT_CC2: TIM2 Capture Compare 2 Interrupt source
  • TIM2_IT_CC3: TIM2 Capture Compare 3 Interrupt source
Return values:
ITStatus The new state of the TIM2_IT(SET or RESET).

Definition at line 1123 of file stm8s_tim2.c.

References IS_TIM2_GET_IT_OK, RESET, and SET.

TIM2_Prescaler_TypeDef TIM2_GetPrescaler ( void )

Gets the TIM2 Prescaler value.

Parameters:
None
Return values:
Prescaler Register configuration value TIM2_Prescaler_TypeDef.

Definition at line 1049 of file stm8s_tim2.c.

void TIM2_ICInit | ( | TIM2_Channel_TypeDef | TIM2_Channel,
 |  | TIM2_ICPolarity_TypeDef | TIM2_ICPolarity,
 |  | TIM2_ICSelection_TypeDef | TIM2_ICSelection,
 |  | TIM2_ICPSC_TypeDef | TIM2_ICPrescaler,
 |  | uint8_t | TIM2_ICFilter
 | ) |  |

Initializes the TIM2 peripheral according to the specified parameters.

Parameters:
TIM2_Channel | specifies the Input Capture Channel from TIM2_Channel_TypeDef.
TIM2_ICPolarity | specifies the Input Capture Polarity from TIM2_ICPolarity_TypeDef.
TIM2_ICSelection | specifies the Input Capture Selection from TIM2_ICSelection_TypeDef.
TIM2_ICPrescaler | specifies the Input Capture Prescaler from TIM2_ICPSC_TypeDef.
TIM2_ICFilter | specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
Return values:
None

Definition at line 212 of file stm8s_tim2.c.

References IS_TIM2_CHANNEL_OK, IS_TIM2_IC_FILTER_OK, IS_TIM2_IC_POLARITY_OK, IS_TIM2_IC_PRESCALER_OK, IS_TIM2_IC_SELECTION_OK, TI1_Config(), TI2_Config(), TI3_Config(), TIM2_CHANNEL_1, TIM2_CHANNEL_2, TIM2_SetIC1Prescaler(), TIM2_SetIC2Prescaler(), and TIM2_SetIC3Prescaler().

void TIM2_InternalClockConfig ( void )
void TIM2_ITConfig | ( | TIM2_IT_TypeDef | TIM2_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified TIM2 interrupts.

Parameters:
NewState | new state of the TIM2 peripheral. This parameter can be: ENABLE or DISABLE.
TIM2_IT specifies the TIM2 interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:
  • TIM2_IT_UPDATE: TIM2 update Interrupt source
  • TIM2_IT_CC1: TIM2 Capture Compare 1 Interrupt source
  • TIM2_IT_CC2: TIM2 Capture Compare 2 Interrupt source
  • TIM2_IT_CC3: TIM2 Capture Compare 3 Interrupt source
NewState | new state of the TIM2 peripheral.
Return values:
None

Definition at line 368 of file stm8s_tim2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and IS_TIM2_IT_OK.

void TIM2_OC1Init | ( | TIM2_OCMode_TypeDef | TIM2_OCMode,
 |  | TIM2_OutputState_TypeDef | TIM2_OutputState,
 |  | uint16_t | TIM2_Pulse,
 |  | TIM2_OCPolarity_TypeDef | TIM2_OCPolarity
 | ) |  |

Initializes the TIM2 Channel1 according to the specified parameters.

Parameters:
TIM2_OCMode | specifies the Output Compare mode from TIM2_OCMode_TypeDef.
TIM2_OutputState | specifies the Output State from TIM2_OutputState_TypeDef.
TIM2_Pulse | specifies the Pulse width value.
TIM2_OCPolarity | specifies the Output Compare Polarity from TIM2_OCPolarity_TypeDef.
Return values:
None

Definition at line 108 of file stm8s_tim2.c.

References IS_TIM2_OC_MODE_OK, IS_TIM2_OC_POLARITY_OK, IS_TIM2_OUTPUT_STATE_OK, TIM2_CCER1_CC1E, TIM2_CCER1_CC1P, and TIM2_CCMR_OCM.

void TIM2_OC1PolarityConfig ( TIM2_OCPolarity_TypeDef TIM2_OCPolarity )

Configures the TIM2 Channel 1 polarity.

Parameters:
TIM2_OCPolarity specifies the OC1 Polarity. This parameter can be one of the following values:
  • TIM2_OCPOLARITY_LOW: Output Compare active low
  • TIM2_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 670 of file stm8s_tim2.c.

References IS_TIM2_OC_POLARITY_OK, TIM2_CCER1_CC1P, and TIM2_OCPOLARITY_HIGH.

void TIM2_OC1PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM2 peripheral Preload Register on CCR1.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 583 of file stm8s_tim2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM2_CCMR_OCxPE.

void TIM2_OC2Init | ( | TIM2_OCMode_TypeDef | TIM2_OCMode,
 |  | TIM2_OutputState_TypeDef | TIM2_OutputState,
 |  | uint16_t | TIM2_Pulse,
 |  | TIM2_OCPolarity_TypeDef | TIM2_OCPolarity
 | ) |  |

Initializes the TIM2 Channel2 according to the specified parameters.

Parameters:
TIM2_OCMode | specifies the Output Compare mode from TIM2_OCMode_TypeDef.
TIM2_OutputState | specifies the Output State from TIM2_OutputState_TypeDef.
TIM2_Pulse | specifies the Pulse width value.
TIM2_OCPolarity | specifies the Output Compare Polarity from TIM2_OCPolarity_TypeDef.
Return values:
None

Definition at line 142 of file stm8s_tim2.c.

References IS_TIM2_OC_MODE_OK, IS_TIM2_OC_POLARITY_OK, IS_TIM2_OUTPUT_STATE_OK, TIM2_CCER1_CC2E, TIM2_CCER1_CC2P, and TIM2_CCMR_OCM.

void TIM2_OC2PolarityConfig ( TIM2_OCPolarity_TypeDef TIM2_OCPolarity )

Configures the TIM2 Channel 2 polarity.

Parameters:
TIM2_OCPolarity specifies the OC2 Polarity. This parameter can be one of the following values:
  • TIM2_OCPOLARITY_LOW: Output Compare active low
  • TIM2_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 694 of file stm8s_tim2.c.

References IS_TIM2_OC_POLARITY_OK, TIM2_CCER1_CC2P, and TIM2_OCPOLARITY_HIGH.

void TIM2_OC2PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM2 peripheral Preload Register on CCR2.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 605 of file stm8s_tim2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM2_CCMR_OCxPE.

void TIM2_OC3Init | ( | TIM2_OCMode_TypeDef | TIM2_OCMode,
 |  | TIM2_OutputState_TypeDef | TIM2_OutputState,
 |  | uint16_t | TIM2_Pulse,
 |  | TIM2_OCPolarity_TypeDef | TIM2_OCPolarity
 | ) |  |

Initializes the TIM2 Channel3 according to the specified parameters.

Parameters:
TIM2_OCMode | specifies the Output Compare mode from TIM2_OCMode_TypeDef.
TIM2_OutputState | specifies the Output State from TIM2_OutputState_TypeDef.
TIM2_Pulse | specifies the Pulse width value.
TIM2_OCPolarity | specifies the Output Compare Polarity from TIM2_OCPolarity_TypeDef.
Return values:
None

Definition at line 179 of file stm8s_tim2.c.

References IS_TIM2_OC_MODE_OK, IS_TIM2_OC_POLARITY_OK, IS_TIM2_OUTPUT_STATE_OK, TIM2_CCER2_CC3E, TIM2_CCER2_CC3P, and TIM2_CCMR_OCM.

void TIM2_OC3PolarityConfig ( TIM2_OCPolarity_TypeDef TIM2_OCPolarity )

Configures the TIM2 Channel 3 polarity.

Parameters:
TIM2_OCPolarity specifies the OC3 Polarity. This parameter can be one of the following values:
  • TIM2_OCPOLARITY_LOW: Output Compare active low
  • TIM2_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 718 of file stm8s_tim2.c.

References IS_TIM2_OC_POLARITY_OK, TIM2_CCER2_CC3P, and TIM2_OCPOLARITY_HIGH.

void TIM2_OC3PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM2 peripheral Preload Register on CCR3.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 627 of file stm8s_tim2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM2_CCMR_OCxPE.

void TIM2_PrescalerConfig | ( | TIM2_Prescaler_TypeDef | Prescaler,
 |  | TIM2_PSCReloadMode_TypeDef | TIM2_PSCReloadMode
 | ) |  |

Configures the TIM2 Prescaler.

Parameters:
Prescaler specifies the Prescaler Register value This parameter can be one of the following values
  • TIM2_PRESCALER_1
  • TIM2_PRESCALER_2
  • TIM2_PRESCALER_4
  • TIM2_PRESCALER_8
  • TIM2_PRESCALER_16
  • TIM2_PRESCALER_32
  • TIM2_PRESCALER_64
  • TIM2_PRESCALER_128
  • TIM2_PRESCALER_256
  • TIM2_PRESCALER_512
  • TIM2_PRESCALER_1024
  • TIM2_PRESCALER_2048
  • TIM2_PRESCALER_4096
  • TIM2_PRESCALER_8192
  • TIM2_PRESCALER_16384
  • TIM2_PRESCALER_32768
TIM2_PSCReloadMode specifies the TIM2 Prescaler Reload mode. This parameter can be one of the following values
  • TIM2_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded immediately.
  • TIM2_PSCRELOADMODE_UPDATE: The Prescaler is loaded at the update event.
Return values:
None

Definition at line 484 of file stm8s_tim2.c.

References IS_TIM2_PRESCALER_OK, and IS_TIM2_PRESCALER_RELOAD_OK.

void TIM2_PWMIConfig | ( | TIM2_Channel_TypeDef | TIM2_Channel,
 |  | TIM2_ICPolarity_TypeDef | TIM2_ICPolarity,
 |  | TIM2_ICSelection_TypeDef | TIM2_ICSelection,
 |  | TIM2_ICPSC_TypeDef | TIM2_ICPrescaler,
 |  | uint8_t | TIM2_ICFilter
 | ) |  |

Configures the TIM2 peripheral in PWM Input Mode according to the specified parameters.

Parameters:
TIM2_Channel | specifies the Input Capture Channel from TIM2_Channel_TypeDef.
TIM2_ICPolarity | specifies the Input Capture Polarity from TIM2_ICPolarity_TypeDef.
TIM2_ICSelection | specifies the Input Capture Selection from TIM2_ICSelection_TypeDef.
TIM2_ICPrescaler | specifies the Input Capture Prescaler from TIM2_ICPSC_TypeDef.
TIM2_ICFilter | specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
Return values:
None

Definition at line 266 of file stm8s_tim2.c.

References IS_TIM2_IC_POLARITY_OK, IS_TIM2_IC_PRESCALER_OK, IS_TIM2_IC_SELECTION_OK, IS_TIM2_PWMI_CHANNEL_OK, TI1_Config(), TI2_Config(), TIM2_CHANNEL_1, TIM2_ICPOLARITY_FALLING, TIM2_ICPOLARITY_RISING, TIM2_ICSELECTION_DIRECTTI, TIM2_ICSELECTION_INDIRECTTI, TIM2_SetIC1Prescaler(), and TIM2_SetIC2Prescaler().

void TIM2_SelectOCxM | ( | TIM2_Channel_TypeDef | TIM2_Channel,
 |  | TIM2_OCMode_TypeDef | TIM2_OCMode
 | ) |  |

Selects the TIM2 Output Compare Mode.

This function disables the selected channel before changing the Output Compare Mode. User has to enable this channel using TIM2_CCxCmd and TIM2_CCxNCmd functions.

Parameters:
TIM2_Channel specifies the TIM2 Channel. This parameter can be one of the following values:
  • TIM2_CHANNEL_1: TIM2 Channel1
  • TIM2_CHANNEL_2: TIM2 Channel2
  • TIM2_CHANNEL_3: TIM2 Channel3
TIM2_OCMode specifies the TIM2 Output Compare Mode. This parameter can be one of the following values:
  • TIM2_OCMODE_TIMING
  • TIM2_OCMODE_ACTIVE
  • TIM2_OCMODE_TOGGLE
  • TIM2_OCMODE_PWM1
  • TIM2_OCMODE_PWM2
  • TIM2_FORCEDACTION_ACTIVE
  • TIM2_FORCEDACTION_INACTIVE
Return values:
None

Definition at line 810 of file stm8s_tim2.c.

References IS_TIM2_CHANNEL_OK, IS_TIM2_OCM_OK, TIM2_CCER1_CC1E, TIM2_CCER1_CC2E, TIM2_CCER2_CC3E, TIM2_CCMR_OCM, TIM2_CHANNEL_1, and TIM2_CHANNEL_2.

void TIM2_SelectOnePulseMode ( TIM2_OPMode_TypeDef TIM2_OPMode )

Selects the TIM2’s One Pulse Mode.

Parameters:
TIM2_OPMode specifies the OPM Mode to be used. This parameter can be one of the following values
  • TIM2_OPMODE_SINGLE
  • TIM2_OPMODE_REPETITIVE
Return values:
None

Definition at line 440 of file stm8s_tim2.c.

References IS_TIM2_OPM_MODE_OK, TIM2_CR1_OPM, and TIM2_OPMODE_REPETITIVE.

void TIM2_SetAutoreload ( uint16_t Autoreload )

Sets the TIM2 Autoreload Register value.

Parameters:
Autoreload specifies the Autoreload register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 864 of file stm8s_tim2.c.

void TIM2_SetCompare1 ( uint16_t Compare1 )

Sets the TIM2 Capture Compare1 Register value.

Parameters:
Compare1 specifies the Capture Compare1 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 877 of file stm8s_tim2.c.

void TIM2_SetCompare2 ( uint16_t Compare2 )

Sets the TIM2 Capture Compare2 Register value.

Parameters:
Compare2 specifies the Capture Compare2 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 890 of file stm8s_tim2.c.

void TIM2_SetCompare3 ( uint16_t Compare3 )

Sets the TIM2 Capture Compare3 Register value.

Parameters:
Compare3 specifies the Capture Compare3 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 903 of file stm8s_tim2.c.

void TIM2_SetCounter ( uint16_t Counter )

Sets the TIM2 Counter Register value.

Parameters:
Counter specifies the Counter register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 851 of file stm8s_tim2.c.

void TIM2_SetIC1Prescaler ( TIM2_ICPSC_TypeDef TIM2_IC1Prescaler )

Sets the TIM2 Input Capture 1 Prescaler.

Parameters:
TIM2_IC1Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:
  • TIM2_ICPSC_DIV1: no prescaler
  • TIM2_ICPSC_DIV2: capture is done once every 2 events
  • TIM2_ICPSC_DIV4: capture is done once every 4 events
  • TIM2_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 920 of file stm8s_tim2.c.

References IS_TIM2_IC_PRESCALER_OK, and TIM2_CCMR_ICxPSC.

Referenced by TIM2_ICInit(), and TIM2_PWMIConfig().

void TIM2_SetIC2Prescaler ( TIM2_ICPSC_TypeDef TIM2_IC2Prescaler )

Sets the TIM2 Input Capture 2 prescaler.

Parameters:
TIM2_IC2Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:
  • TIM2_ICPSC_DIV1: no prescaler
  • TIM2_ICPSC_DIV2: capture is done once every 2 events
  • TIM2_ICPSC_DIV4: capture is done once every 4 events
  • TIM2_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 940 of file stm8s_tim2.c.

References IS_TIM2_IC_PRESCALER_OK, and TIM2_CCMR_ICxPSC.

Referenced by TIM2_ICInit(), and TIM2_PWMIConfig().

void TIM2_SetIC3Prescaler ( TIM2_ICPSC_TypeDef TIM2_IC3Prescaler )

Sets the TIM2 Input Capture 3 prescaler.

Parameters:
TIM2_IC3Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:
  • TIM2_ICPSC_DIV1: no prescaler
  • TIM2_ICPSC_DIV2: capture is done once every 2 events
  • TIM2_ICPSC_DIV4: capture is done once every 4 events
  • TIM2_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 960 of file stm8s_tim2.c.

References IS_TIM2_IC_PRESCALER_OK, and TIM2_CCMR_ICxPSC.

Referenced by TIM2_ICInit().

void TIM2_TimeBaseInit | ( | TIM2_Prescaler_TypeDef | TIM2_Prescaler,
 |  | uint16_t | TIM2_Period
 | ) |  |

Initializes the TIM2 Time Base Unit according to the specified parameters.

Parameters:
TIM2_Prescaler | specifies the Prescaler from TIM2_Prescaler_TypeDef.
TIM2_Period | specifies the Period value.
Return values:
None

Definition at line 89 of file stm8s_tim2.c.

void TIM2_UpdateDisableConfig ( FunctionalState NewState )

Enables or Disables the TIM2 Update event.

Parameters:
NewState new state of the TIM2 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 392 of file stm8s_tim2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM2_CR1_UDIS.

void TIM2_UpdateRequestConfig ( TIM2_UpdateSource_TypeDef TIM2_UpdateSource )

Selects the TIM2 Update Request Interrupt source.

Parameters:
TIM2_UpdateSource specifies the Update source. This parameter can be one of the following values
  • TIM2_UPDATESOURCE_REGULAR
  • TIM2_UPDATESOURCE_GLOBAL
Return values:
None

Definition at line 416 of file stm8s_tim2.c.

References IS_TIM2_UPDATE_SOURCE_OK, TIM2_CR1_URS, and TIM2_UPDATESOURCE_GLOBAL.


STM8S/A Standard Peripherals Drivers: TIM5_Exported_Functions

Functions
TIM5_Exported_Functions

Functions

void | TIM5_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM5 peripheral Preload register on ARR.
void | TIM5_CCPreloadControl (FunctionalState NewState)
void | TIM5_CCxCmd (TIM5_Channel_TypeDef TIM5_Channel, FunctionalState NewState)
Enables or disables the TIM5 Capture Compare Channel x.
void | TIM5_ClearFlag (TIM5_FLAG_TypeDef TIM5_FLAG)
Clears the TIM5’s pending flags.
void | TIM5_ClearITPendingBit (TIM5_IT_TypeDef TIM5_IT)
Clears the TIM5's interrupt pending bits.
void | TIM5_Cmd (FunctionalState NewState)
Enables or disables the TIM5 peripheral.
void | TIM5_DeInit (void)
Deinitializes the TIM5 peripheral registers to their default reset values.
void | TIM5_EncoderInterfaceConfig (TIM5_EncoderMode_TypeDef TIM5_EncoderMode, TIM5_ICPolarity_TypeDef TIM5_IC1Polarity, TIM5_ICPolarity_TypeDef TIM5_IC2Polarity)
Configures the TIM5 Encoder Interface.
void | TIM5_ForcedOC1Config (TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
Forces the TIM5 Channel1 output waveform to active or inactive level.
void | TIM5_ForcedOC2Config (TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
Forces the TIM5 Channel2 output waveform to active or inactive level.
void | TIM5_ForcedOC3Config (TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
Forces the TIM5 Channel3 output waveform to active or inactive level.
void | TIM5_GenerateEvent (TIM5_EventSource_TypeDef TIM5_EventSource)
Configures the TIM5 event to be generated by software.
uint16_t | TIM5_GetCapture1 (void)
Gets the TIM5 Input Capture 1 value.
uint16_t | TIM5_GetCapture2 (void)
Gets the TIM5 Input Capture 2 value.
uint16_t | TIM5_GetCapture3 (void)
Gets the TIM5 Input Capture 3 value.
uint16_t | TIM5_GetCounter (void)
Gets the TIM5 Counter value.
FlagStatus | TIM5_GetFlagStatus (TIM5_FLAG_TypeDef TIM5_FLAG)
Checks whether the specified TIM5 flag is set or not.
ITStatus | TIM5_GetITStatus (TIM5_IT_TypeDef TIM5_IT)
Checks whether the TIM5 interrupt has occurred or not.
TIM5_Prescaler_TypeDef | TIM5_GetPrescaler (void)
Gets the TIM5 Prescaler value.
void | TIM5_ICInit (TIM5_Channel_TypeDef TIM5_Channel, TIM5_ICPolarity_TypeDef TIM5_ICPolarity, TIM5_ICSelection_TypeDef TIM5_ICSelection, TIM5_ICPSC_TypeDef TIM5_ICPrescaler, uint8_t TIM5_ICFilter)
Initializes the TIM5 peripheral according to the specified parameters.
void | TIM5_InternalClockConfig (void)
Enables the TIM5 internal Clock.
void | TIM5_ITConfig (TIM5_IT_TypeDef TIM5_IT, FunctionalState NewState)
Enables or disables the specified TIM5 interrupts.
void | TIM5_OC1Init (TIM5_OCMode_TypeDef TIM5_OCMode, TIM5_OutputState_TypeDef TIM5_OutputState, uint16_t TIM5_Pulse, TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Initializes the TIM5 Channel1 according to the specified parameters.
void | TIM5_OC1PolarityConfig (TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Configures the TIM5 Channel 1 polarity.
void | TIM5_OC1PreloadConfig (FunctionalState NewState)
Enables or disables the TIM5 peripheral Preload Register on CCR1.
void | TIM5_OC2Init (TIM5_OCMode_TypeDef TIM5_OCMode, TIM5_OutputState_TypeDef TIM5_OutputState, uint16_t TIM5_Pulse, TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Initializes the TIM5 Channel2 according to the specified parameters.
void | TIM5_OC2PolarityConfig (TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Configures the TIM5 Channel 2 polarity.
void | TIM5_OC2PreloadConfig (FunctionalState NewState)
Enables or disables the TIM5 peripheral Preload Register on CCR2.
void | TIM5_OC3Init (TIM5_OCMode_TypeDef TIM5_OCMode, TIM5_OutputState_TypeDef TIM5_OutputState, uint16_t TIM5_Pulse, TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Initializes the TIM5 Channel3 according to the specified parameters.
void | TIM5_OC3PolarityConfig (TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Configures the TIM5 Channel 3 polarity.
void | TIM5_OC3PreloadConfig (FunctionalState NewState)
Enables or disables the TIM5 peripheral Preload Register on CCR3.
void | TIM5_PrescalerConfig (TIM5_Prescaler_TypeDef Prescaler, TIM5_PSCReloadMode_TypeDef TIM5_PSCReloadMode)
Configures the TIM5 Prescaler.
void | TIM5_PWMIConfig (TIM5_Channel_TypeDef TIM5_Channel, TIM5_ICPolarity_TypeDef TIM5_ICPolarity, TIM5_ICSelection_TypeDef TIM5_ICSelection, TIM5_ICPSC_TypeDef TIM5_ICPrescaler, uint8_t TIM5_ICFilter)
Configures the TIM5 peripheral in PWM Input Mode according to the specified parameters.
void | TIM5_SelectInputTrigger (TIM5_TS_TypeDef TIM5_InputTriggerSource)
Selects the TIM5 Input Trigger source.
void | TIM5_SelectOCxM (TIM5_Channel_TypeDef TIM5_Channel, TIM5_OCMode_TypeDef TIM5_OCMode)
Selects the TIM5 Output Compare Mode.
void | TIM5_SelectOnePulseMode (TIM5_OPMode_TypeDef TIM5_OPMode)
Selects the TIM5’s One Pulse Mode.
void | TIM5_SelectOutputTrigger (TIM5_TRGOSource_TypeDef TIM5_TRGOSource)
Selects the TIM5 Trigger Output Mode.
void | TIM5_SelectSlaveMode (TIM5_SlaveMode_TypeDef TIM5_SlaveMode)
Selects the TIM5 Slave Mode.
void | TIM5_SetAutoreload (uint16_t Autoreload)
Sets the TIM5 Autoreload Register value.
void | TIM5_SetCompare1 (uint16_t Compare1)
Sets the TIM5 Capture Compare1 Register value.
void | TIM5_SetCompare2 (uint16_t Compare2)
Sets the TIM5 Capture Compare2 Register value.
void | TIM5_SetCompare3 (uint16_t Compare3)
Sets the TIM5 Capture Compare3 Register value.
void | TIM5_SetCounter (uint16_t Counter)
Sets the TIM5 Counter Register value.
void | TIM5_SetIC1Prescaler (TIM5_ICPSC_TypeDef TIM5_IC1Prescaler)
Sets the TIM5 Input Capture 1 prescaler.
void | TIM5_SetIC2Prescaler (TIM5_ICPSC_TypeDef TIM5_IC2Prescaler)
Sets the TIM5 Input Capture 2 prescaler.
void | TIM5_SetIC3Prescaler (TIM5_ICPSC_TypeDef TIM5_IC3Prescaler)
Sets the TIM5 Input Capture 3 prescaler.
void | TIM5_TimeBaseInit (TIM5_Prescaler_TypeDef TIM5_Prescaler, uint16_t TIM5_Period)
Initializes the TIM5 Time Base Unit according to the specified parameters.
void | TIM5_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM5 Update event.
void | TIM5_UpdateRequestConfig (TIM5_UpdateSource_TypeDef TIM5_UpdateSource)
Selects the TIM5 Update Request Interrupt source.

Function Documentation

void TIM5_ARRPreloadConfig ( FunctionalState NewState )

Enables or disables TIM5 peripheral Preload register on ARR.

Parameters:
NewState new state of the TIM5 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 556 of file stm8s_tim5.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM5_CR1_ARPE.

void TIM5_CCPreloadControl ( FunctionalState NewState )
void TIM5_CCxCmd | ( | TIM5_Channel_TypeDef | TIM5_Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the TIM5 Capture Compare Channel x.

Parameters:
TIM5_Channel specifies the TIM5 Channel. This parameter can be one of the following values:
  • TIM5_Channel1: TIM5 Channel1
  • TIM5_Channel2: TIM5 Channel2
  • TIM5_Channel3: TIM5 Channel3
NewState specifies the TIM5 Channel CCxE bit new state. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 741 of file stm8s_tim5.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, IS_TIM5_CHANNEL_OK, TIM5_CCER1_CC1E, TIM5_CCER1_CC2E, TIM5_CCER2_CC3E, TIM5_CHANNEL_1, and TIM5_CHANNEL_2.

void TIM5_ClearFlag ( TIM5_FLAG_TypeDef TIM5_FLAG )

Clears the TIM5’s pending flags.

Parameters:
TIM5_FLAG specifies the flag to clear. This parameter can be one of the following values:
  • TIM5_FLAG_UPDATE: TIM5 update Flag
  • TIM5_FLAG_CC1: TIM5 Capture Compare 1 Flag
  • TIM5_FLAG_CC2: TIM5 Capture Compare 2 Flag
  • TIM5_FLAG_CC3: TIM5 Capture Compare 3 Flag
  • TIM5_FLAG_CC1OF: TIM5 Capture Compare 1 overcapture Flag
  • TIM5_FLAG_CC2OF: TIM5 Capture Compare 2 overcapture Flag
  • TIM5_FLAG_CC3OF: TIM5 Capture Compare 3 overcapture Flag
Return values:
None.

Definition at line 1082 of file stm8s_tim5.c.

References IS_TIM5_CLEAR_FLAG_OK.

void TIM5_ClearITPendingBit ( TIM5_IT_TypeDef TIM5_IT )

Clears the TIM5's interrupt pending bits.

Parameters:
TIM5_IT specifies the pending bit to clear. This parameter can be one of the following values:
  • TIM5_IT_UPDATE: TIM5 update Interrupt source
  • TIM5_IT_CC1: TIM5 Capture Compare 1 Interrupt source
  • TIM5_IT_CC2: TIM5 Capture Compare 2 Interrupt source
  • TIM5_IT_CC3: TIM5 Capture Compare 3 Interrupt source
Return values:
None.

Definition at line 1136 of file stm8s_tim5.c.

References IS_TIM5_IT_OK.

void TIM5_Cmd ( FunctionalState NewState )

Enables or disables the TIM5 peripheral.

Parameters:
NewState new state of the TIM5 peripheral.This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 334 of file stm8s_tim5.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM5_CR1_CEN.

void TIM5_DeInit ( void )

Deinitializes the TIM5 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 52 of file stm8s_tim5.c.

References TIM5_ARRH_RESET_VALUE, TIM5_ARRL_RESET_VALUE, TIM5_CCER1_RESET_VALUE, TIM5_CCER2_RESET_VALUE, TIM5_CCMR1_RESET_VALUE, TIM5_CCMR2_RESET_VALUE, TIM5_CCMR3_RESET_VALUE, TIM5_CCR1H_RESET_VALUE, TIM5_CCR1L_RESET_VALUE, TIM5_CCR2H_RESET_VALUE, TIM5_CCR2L_RESET_VALUE, TIM5_CCR3H_RESET_VALUE, TIM5_CCR3L_RESET_VALUE, TIM5_CNTRH_RESET_VALUE, TIM5_CNTRL_RESET_VALUE, TIM5_CR1_RESET_VALUE, TIM5_CR2_RESET_VALUE, TIM5_IER_RESET_VALUE, TIM5_PSCR_RESET_VALUE, TIM5_SMCR_RESET_VALUE, TIM5_SR1_RESET_VALUE, and TIM5_SR2_RESET_VALUE.

void TIM5_EncoderInterfaceConfig | ( | TIM5_EncoderMode_TypeDef | TIM5_EncoderMode,
 |  | TIM5_ICPolarity_TypeDef | TIM5_IC1Polarity,
 |  | TIM5_ICPolarity_TypeDef | TIM5_IC2Polarity
 | ) |  |

Configures the TIM5 Encoder Interface.

Parameters:
TIM5_EncoderMode | : Specifies the TIM5 Encoder Mode. This parameter can be one of the TIM5_EncoderMode_TypeDef enumeration.
TIM5_IC1Polarity | : Specifies the IC1 Polarity. This parameter can be one of the TIM5_ICPolarity_TypeDef enumeration.
TIM5_IC2Polarity | : Specifies the IC2 Polarity. This parameter can be one of the TIM5_ICPolarity_TypeDef enumeration.
Return values:
None

Definition at line 1357 of file stm8s_tim5.c.

References IS_TIM5_ENCODER_MODE_OK, IS_TIM5_IC_POLARITY_OK, TIM5_CCER1_CC1P, TIM5_CCER1_CC2P, TIM5_CCMR_CCxS, TIM5_CCMR_TIxDirect_Set, TIM5_ICPOLARITY_FALLING, TIM5_SMCR_MSM, and TIM5_SMCR_TS.

void TIM5_ForcedOC1Config ( TIM5_ForcedAction_TypeDef TIM5_ForcedAction )

Forces the TIM5 Channel1 output waveform to active or inactive level.

Parameters:
TIM5_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:
  • TIM5_FORCEDACTION_ACTIVE: Force active level on OC1REF
  • TIM5_FORCEDACTION_INACTIVE: Force inactive level on OC1REF.
Return values:
None

Definition at line 502 of file stm8s_tim5.c.

References IS_TIM5_FORCED_ACTION_OK, and TIM5_CCMR_OCM.

void TIM5_ForcedOC2Config ( TIM5_ForcedAction_TypeDef TIM5_ForcedAction )

Forces the TIM5 Channel2 output waveform to active or inactive level.

Parameters:
TIM5_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:
  • TIM5_FORCEDACTION_ACTIVE: Force active level on OC2REF
  • TIM5_FORCEDACTION_INACTIVE: Force inactive level on OC2REF.
Return values:
None

Definition at line 521 of file stm8s_tim5.c.

References IS_TIM5_FORCED_ACTION_OK, and TIM5_CCMR_OCM.

void TIM5_ForcedOC3Config ( TIM5_ForcedAction_TypeDef TIM5_ForcedAction )

Forces the TIM5 Channel3 output waveform to active or inactive level.

Parameters:
TIM5_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:
  • TIM5_FORCEDACTION_ACTIVE: Force active level on OC3REF
  • TIM5_FORCEDACTION_INACTIVE: Force inactive level on OC3REF.
Return values:
None

Definition at line 540 of file stm8s_tim5.c.

References IS_TIM5_FORCED_ACTION_OK, and TIM5_CCMR_OCM.

void TIM5_GenerateEvent ( TIM5_EventSource_TypeDef TIM5_EventSource )

Configures the TIM5 event to be generated by software.

Parameters:
TIM5_EventSource specifies the event source. This parameter can be one of the following values:
  • TIM5_EVENTSOURCE_UPDATE: TIM5 update Event source
  • TIM5_EVENTSOURCE_CC1: TIM5 Capture Compare 1 Event source
  • TIM5_EVENTSOURCE_CC2: TIM5 Capture Compare 2 Event source
  • TIM5_EVENTSOURCE_CC3: TIM5 Capture Compare 3 Event source
Return values:
None

Definition at line 648 of file stm8s_tim5.c.

References IS_TIM5_EVENT_SOURCE_OK.

uint16_t TIM5_GetCapture1 ( void )

Gets the TIM5 Input Capture 1 value.

Parameters:
None
Return values:
Capture Compare 1 Register value.

Definition at line 970 of file stm8s_tim5.c.

uint16_t TIM5_GetCapture2 ( void )

Gets the TIM5 Input Capture 2 value.

Parameters:
None
Return values:
Capture Compare 2 Register value.

Definition at line 985 of file stm8s_tim5.c.

uint16_t TIM5_GetCapture3 ( void )

Gets the TIM5 Input Capture 3 value.

Parameters:
None
Return values:
Capture Compare 3 Register value.

Definition at line 1000 of file stm8s_tim5.c.

uint16_t TIM5_GetCounter ( void )

Gets the TIM5 Counter value.

Parameters:
None
Return values:
Counter Register value.

Definition at line 1014 of file stm8s_tim5.c.

FlagStatus TIM5_GetFlagStatus ( TIM5_FLAG_TypeDef TIM5_FLAG )

Checks whether the specified TIM5 flag is set or not.

Parameters:
TIM5_FLAG specifies the flag to check. This parameter can be one of the following values:
  • TIM5_FLAG_UPDATE: TIM5 update Flag
  • TIM5_FLAG_CC1: TIM5 Capture Compare 1 Flag
  • TIM5_FLAG_CC2: TIM5 Capture Compare 2 Flag
  • TIM5_FLAG_CC3: TIM5 Capture Compare 3 Flag
  • TIM5_FLAG_CC1OF: TIM5 Capture Compare 1 overcapture Flag
  • TIM5_FLAG_CC2OF: TIM5 Capture Compare 2 overcapture Flag
  • TIM5_FLAG_CC3OF: TIM5 Capture Compare 3 overcapture Flag
Return values:
FlagStatus The new state of TIM5_FLAG (SET or RESET).

Definition at line 1047 of file stm8s_tim5.c.

References IS_TIM5_GET_FLAG_OK, RESET, and SET.

ITStatus TIM5_GetITStatus ( TIM5_IT_TypeDef TIM5_IT )

Checks whether the TIM5 interrupt has occurred or not.

Parameters:
TIM5_IT specifies the TIM5 interrupt source to check. This parameter can be one of the following values:
  • TIM5_IT_UPDATE: TIM5 update Interrupt source
  • TIM5_IT_CC1: TIM5 Capture Compare 1 Interrupt source
  • TIM5_IT_CC2: TIM5 Capture Compare 2 Interrupt source
  • TIM5_IT_CC3: TIM5 Capture Compare 3 Interrupt source
Return values:
ITStatus The new state of the TIM5_IT(SET or RESET).

Definition at line 1103 of file stm8s_tim5.c.

References IS_TIM5_GET_IT_OK, RESET, and SET.

TIM5_Prescaler_TypeDef TIM5_GetPrescaler ( void )

Gets the TIM5 Prescaler value.

Parameters:
None
Return values:
Prescaler Register configuration value TIM5_Prescaler_TypeDef .

Definition at line 1028 of file stm8s_tim5.c.

void TIM5_ICInit | ( | TIM5_Channel_TypeDef | TIM5_Channel,
 |  | TIM5_ICPolarity_TypeDef | TIM5_ICPolarity,
 |  | TIM5_ICSelection_TypeDef | TIM5_ICSelection,
 |  | TIM5_ICPSC_TypeDef | TIM5_ICPrescaler,
 |  | uint8_t | TIM5_ICFilter
 | ) |  |

Initializes the TIM5 peripheral according to the specified parameters.

Parameters:
TIM5_Channel | specifies the Input Capture Channel from TIM5_Channel_TypeDef.
TIM5_ICPolarity | specifies the Input Capture Polarity from TIM5_ICPolarity_TypeDef.
TIM5_ICSelection | specifies theInput Capture Selection from TIM5_ICSelection_TypeDef.
TIM5_ICPrescaler | specifies the Input Capture Prescaler from TIM5_ICPSC_TypeDef.
TIM5_ICFilter | specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
Return values:
None

Definition at line 207 of file stm8s_tim5.c.

References IS_TIM5_CHANNEL_OK, IS_TIM5_IC_FILTER_OK, IS_TIM5_IC_POLARITY_OK, IS_TIM5_IC_PRESCALER_OK, IS_TIM5_IC_SELECTION_OK, TI1_Config(), TI2_Config(), TI3_Config(), TIM5_CHANNEL_1, TIM5_CHANNEL_2, TIM5_SetIC1Prescaler(), TIM5_SetIC2Prescaler(), and TIM5_SetIC3Prescaler().

void TIM5_InternalClockConfig ( void )

Enables the TIM5 internal Clock.

Parameters:
None
Return values:
None

Definition at line 1271 of file stm8s_tim5.c.

References TIM5_SMCR_SMS.

void TIM5_ITConfig | ( | TIM5_IT_TypeDef | TIM5_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified TIM5 interrupts.

Parameters:
NewState | new state of the TIM5 peripheral. This parameter can be: ENABLE or DISABLE.
TIM5_IT specifies the TIM5 interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:
  • TIM5_IT_UPDATE: TIM5 update Interrupt source
  • TIM5_IT_CC1: TIM5 Capture Compare 1 Interrupt source
  • TIM5_IT_CC2: TIM5 Capture Compare 2 Interrupt source
  • TIM5_IT_CC3: TIM5 Capture Compare 3 Interrupt source
NewState | new state of the TIM5 peripheral.
Return values:
None

Definition at line 363 of file stm8s_tim5.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and IS_TIM5_IT_OK.

void TIM5_OC1Init | ( | TIM5_OCMode_TypeDef | TIM5_OCMode,
 |  | TIM5_OutputState_TypeDef | TIM5_OutputState,
 |  | uint16_t | TIM5_Pulse,
 |  | TIM5_OCPolarity_TypeDef | TIM5_OCPolarity
 | ) |  |

Initializes the TIM5 Channel1 according to the specified parameters.

Parameters:
TIM5_OCMode | specifies the Output Compare mode from TIM5_OCMode_TypeDef.
TIM5_OutputState | specifies the Output State from TIM5_OutputState_TypeDef.
TIM5_Pulse | specifies the Pulse width value.
TIM5_OCPolarity | specifies the Output Compare Polarity from TIM5_OCPolarity_TypeDef.
Return values:
None

Definition at line 108 of file stm8s_tim5.c.

References IS_TIM5_OC_MODE_OK, IS_TIM5_OC_POLARITY_OK, IS_TIM5_OUTPUT_STATE_OK, TIM5_CCER1_CC1E, TIM5_CCER1_CC1P, and TIM5_CCMR_OCM.

void TIM5_OC1PolarityConfig ( TIM5_OCPolarity_TypeDef TIM5_OCPolarity )

Configures the TIM5 Channel 1 polarity.

Parameters:
TIM5_OCPolarity specifies the OC1 Polarity. This parameter can be one of the following values:
  • TIM5_OCPOLARITY_LOW: Output Compare active low
  • TIM5_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 665 of file stm8s_tim5.c.

References IS_TIM5_OC_POLARITY_OK, TIM5_CCER1_CC1P, and TIM5_OCPOLARITY_HIGH.

void TIM5_OC1PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM5 peripheral Preload Register on CCR1.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 578 of file stm8s_tim5.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM5_CCMR_OCxPE.

void TIM5_OC2Init | ( | TIM5_OCMode_TypeDef | TIM5_OCMode,
 |  | TIM5_OutputState_TypeDef | TIM5_OutputState,
 |  | uint16_t | TIM5_Pulse,
 |  | TIM5_OCPolarity_TypeDef | TIM5_OCPolarity
 | ) |  |

Initializes the TIM5 Channel2 according to the specified parameters.

Parameters:
TIM5_OCMode | specifies the Output Compare mode from TIM5_OCMode_TypeDef.
TIM5_OutputState | specifies the Output State from TIM5_OutputState_TypeDef.
TIM5_Pulse | specifies the Pulse width value.
TIM5_OCPolarity | specifies the Output Compare Polarity from TIM5_OCPolarity_TypeDef.
Return values:
None

Definition at line 141 of file stm8s_tim5.c.

References IS_TIM5_OC_MODE_OK, IS_TIM5_OC_POLARITY_OK, IS_TIM5_OUTPUT_STATE_OK, TIM5_CCER1_CC2E, TIM5_CCER1_CC2P, and TIM5_CCMR_OCM.

void TIM5_OC2PolarityConfig ( TIM5_OCPolarity_TypeDef TIM5_OCPolarity )

Configures the TIM5 Channel 2 polarity.

Parameters:
TIM5_OCPolarity specifies the OC2 Polarity. This parameter can be one of the following values:
  • TIM5_OCPOLARITY_LOW: Output Compare active low
  • TIM5_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 690 of file stm8s_tim5.c.

References IS_TIM5_OC_POLARITY_OK, TIM5_CCER1_CC2P, and TIM5_OCPOLARITY_HIGH.

void TIM5_OC2PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM5 peripheral Preload Register on CCR2.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 600 of file stm8s_tim5.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM5_CCMR_OCxPE.

void TIM5_OC3Init | ( | TIM5_OCMode_TypeDef | TIM5_OCMode,
 |  | TIM5_OutputState_TypeDef | TIM5_OutputState,
 |  | uint16_t | TIM5_Pulse,
 |  | TIM5_OCPolarity_TypeDef | TIM5_OCPolarity
 | ) |  |

Initializes the TIM5 Channel3 according to the specified parameters.

Parameters:
TIM5_OCMode | specifies the Output Compare mode from TIM5_OCMode_TypeDef.
TIM5_OutputState | specifies the Output State from TIM5_OutputState_TypeDef.
TIM5_Pulse | specifies the Pulse width value.
TIM5_OCPolarity | specifies the Output Compare Polarity from TIM5_OCPolarity_TypeDef.
Return values:
None

Definition at line 175 of file stm8s_tim5.c.

References IS_TIM5_OC_MODE_OK, IS_TIM5_OC_POLARITY_OK, IS_TIM5_OUTPUT_STATE_OK, TIM5_CCER2_CC3E, TIM5_CCER2_CC3P, and TIM5_CCMR_OCM.

void TIM5_OC3PolarityConfig ( TIM5_OCPolarity_TypeDef TIM5_OCPolarity )

Configures the TIM5 Channel 3 polarity.

Parameters:
TIM5_OCPolarity specifies the OC3 Polarity. This parameter can be one of the following values:
  • TIM5_OCPOLARITY_LOW: Output Compare active low
  • TIM5_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 714 of file stm8s_tim5.c.

References IS_TIM5_OC_POLARITY_OK, TIM5_CCER2_CC3P, and TIM5_OCPOLARITY_HIGH.

void TIM5_OC3PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM5 peripheral Preload Register on CCR3.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 622 of file stm8s_tim5.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM5_CCMR_OCxPE.

void TIM5_PrescalerConfig | ( | TIM5_Prescaler_TypeDef | Prescaler,
 |  | TIM5_PSCReloadMode_TypeDef | TIM5_PSCReloadMode
 | ) |  |

Configures the TIM5 Prescaler.

Parameters:
Prescaler specifies the Prescaler Register value This parameter can be one of the following values
  • TIM5_PRESCALER_1
  • TIM5_PRESCALER_2
  • TIM5_PRESCALER_4
  • TIM5_PRESCALER_8
  • TIM5_PRESCALER_16
  • TIM5_PRESCALER_32
  • TIM5_PRESCALER_64
  • TIM5_PRESCALER_128
  • TIM5_PRESCALER_256
  • TIM5_PRESCALER_512
  • TIM5_PRESCALER_1024
  • TIM5_PRESCALER_2048
  • TIM5_PRESCALER_4096
  • TIM5_PRESCALER_8192
  • TIM5_PRESCALER_16384
  • TIM5_PRESCALER_32768
TIM5_PSCReloadMode specifies the TIM5 Prescaler Reload mode. This parameter can be one of the following values
  • TIM5_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded immediately.
  • TIM5_PSCRELOADMODE_UPDATE: The Prescaler is loaded at the update event.
Return values:
None

Definition at line 479 of file stm8s_tim5.c.

References IS_TIM5_PRESCALER_OK, and IS_TIM5_PRESCALER_RELOAD_OK.

void TIM5_PWMIConfig | ( | TIM5_Channel_TypeDef | TIM5_Channel,
 |  | TIM5_ICPolarity_TypeDef | TIM5_ICPolarity,
 |  | TIM5_ICSelection_TypeDef | TIM5_ICSelection,
 |  | TIM5_ICPSC_TypeDef | TIM5_ICPrescaler,
 |  | uint8_t | TIM5_ICFilter
 | ) |  |

Configures the TIM5 peripheral in PWM Input Mode according to the specified parameters.

Parameters:
TIM5_Channel | specifies the Input Capture Channel from TIM5_Channel_TypeDef.
TIM5_ICPolarity | specifies the Input Capture Polarity from TIM5_ICPolarity_TypeDef.
TIM5_ICSelection | specifies theInput Capture Selection from TIM5_ICSelection_TypeDef.
TIM5_ICPrescaler | specifies the Input Capture Prescaler from TIM5_ICPSC_TypeDef.
TIM5_ICFilter | specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
Return values:
None

Definition at line 261 of file stm8s_tim5.c.

References IS_TIM5_IC_POLARITY_OK, IS_TIM5_IC_PRESCALER_OK, IS_TIM5_IC_SELECTION_OK, IS_TIM5_PWMI_CHANNEL_OK, TI1_Config(), TI2_Config(), TIM5_CHANNEL_1, TIM5_ICPOLARITY_FALLING, TIM5_ICPOLARITY_RISING, TIM5_ICSELECTION_DIRECTTI, TIM5_ICSELECTION_INDIRECTTI, TIM5_SetIC1Prescaler(), and TIM5_SetIC2Prescaler().

void TIM5_SelectInputTrigger ( TIM5_TS_TypeDef TIM5_InputTriggerSource )

Selects the TIM5 Input Trigger source.

Parameters:
TIM5_InputTriggerSource : Specifies Input Trigger source. This parameter can be one of the TIM5_TS_TypeDef enumeration.
Return values:
None

Definition at line 1331 of file stm8s_tim5.c.

References IS_TIM5_TRIGGER_SELECTION_OK, and TIM5_SMCR_TS.

void TIM5_SelectOCxM | ( | TIM5_Channel_TypeDef | TIM5_Channel,
 |  | TIM5_OCMode_TypeDef | TIM5_OCMode
 | ) |  |

Selects the TIM5 Output Compare Mode.

This function disables the selected channel before changing the Output Compare Mode. User has to enable this channel using TIM5_CCxCmd and TIM5_CCxNCmd functions.

Parameters:
TIM5_Channel specifies the TIM5 Channel. This parameter can be one of the following values:
  • TIM5_Channel1: TIM5 Channel1
  • TIM5_Channel2: TIM5 Channel2
  • TIM5_Channel3: TIM5 Channel3
TIM5_OCMode specifies the TIM5 Output Compare Mode. This parameter can be one of the following values:
  • TIM5_OCMODE_TIMING
  • TIM5_OCMODE_ACTIVE
  • TIM5_OCMODE_TOGGLE
  • TIM5_OCMODE_PWM1
  • TIM5_OCMODE_PWM2
  • TIM5_FORCEDACTION_ACTIVE
  • TIM5_FORCEDACTION_INACTIVE
Return values:
None

Definition at line 806 of file stm8s_tim5.c.

References IS_TIM5_CHANNEL_OK, IS_TIM5_OCM_OK, TIM5_CCER1_CC1E, TIM5_CCER1_CC2E, TIM5_CCER2_CC3E, TIM5_CCMR_OCM, TIM5_CHANNEL_1, and TIM5_CHANNEL_2.

void TIM5_SelectOnePulseMode ( TIM5_OPMode_TypeDef TIM5_OPMode )

Selects the TIM5’s One Pulse Mode.

Parameters:
TIM5_OPMode specifies the OPM Mode to be used. This parameter can be one of the following values
  • TIM5_OPMODE_SINGLE
  • TIM5_OPMODE_REPETITIVE
Return values:
None

Definition at line 435 of file stm8s_tim5.c.

References IS_TIM5_OPM_MODE_OK, TIM5_CR1_OPM, and TIM5_OPMODE_REPETITIVE.

void TIM5_SelectOutputTrigger ( TIM5_TRGOSource_TypeDef TIM5_TRGOSource )

Selects the TIM5 Trigger Output Mode.

Parameters:
TIM5_TRGOSource : Specifies the Trigger Output source. This parameter can be one of the TIM5_TRGOSource_TypeDef enumeration.
Return values:
None

Definition at line 1283 of file stm8s_tim5.c.

References IS_TIM5_TRGO_SOURCE_OK, and TIM5_CR2_MMS.

void TIM5_SelectSlaveMode ( TIM5_SlaveMode_TypeDef TIM5_SlaveMode )

Selects the TIM5 Slave Mode.

Parameters:
TIM5_SlaveMode : Specifies the TIM5 Slave Mode. This parameter can be one of the TIM5_SlaveMode_TypeDef enumeration.
Return values:
None

Definition at line 1307 of file stm8s_tim5.c.

References IS_TIM5_SLAVE_MODE_OK, and TIM5_SMCR_SMS.

void TIM5_SetAutoreload ( uint16_t Autoreload )

Sets the TIM5 Autoreload Register value.

Parameters:
Autoreload specifies the Autoreload register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 860 of file stm8s_tim5.c.

void TIM5_SetCompare1 ( uint16_t Compare1 )

Sets the TIM5 Capture Compare1 Register value.

Parameters:
Compare1 specifies the Capture Compare1 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 873 of file stm8s_tim5.c.

void TIM5_SetCompare2 ( uint16_t Compare2 )

Sets the TIM5 Capture Compare2 Register value.

Parameters:
Compare2 specifies the Capture Compare2 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 886 of file stm8s_tim5.c.

void TIM5_SetCompare3 ( uint16_t Compare3 )

Sets the TIM5 Capture Compare3 Register value.

Parameters:
Compare3 specifies the Capture Compare3 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 899 of file stm8s_tim5.c.

void TIM5_SetCounter ( uint16_t Counter )

Sets the TIM5 Counter Register value.

Parameters:
Counter specifies the Counter register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 847 of file stm8s_tim5.c.

void TIM5_SetIC1Prescaler ( TIM5_ICPSC_TypeDef TIM5_IC1Prescaler )

Sets the TIM5 Input Capture 1 prescaler.

Parameters:
TIM5_IC1Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:
  • TIM5_ICPSC_DIV1: no prescaler
  • TIM5_ICPSC_DIV2: capture is done once every 2 events
  • TIM5_ICPSC_DIV4: capture is done once every 4 events
  • TIM5_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 916 of file stm8s_tim5.c.

References IS_TIM5_IC_PRESCALER_OK, and TIM5_CCMR_ICxPSC.

Referenced by TIM5_ICInit(), and TIM5_PWMIConfig().

void TIM5_SetIC2Prescaler ( TIM5_ICPSC_TypeDef TIM5_IC2Prescaler )

Sets the TIM5 Input Capture 2 prescaler.

Parameters:
TIM5_IC2Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:
  • TIM5_ICPSC_DIV1: no prescaler
  • TIM5_ICPSC_DIV2: capture is done once every 2 events
  • TIM5_ICPSC_DIV4: capture is done once every 4 events
  • TIM5_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 936 of file stm8s_tim5.c.

References IS_TIM5_IC_PRESCALER_OK, and TIM5_CCMR_ICxPSC.

Referenced by TIM5_ICInit(), and TIM5_PWMIConfig().

void TIM5_SetIC3Prescaler ( TIM5_ICPSC_TypeDef TIM5_IC3Prescaler )

Sets the TIM5 Input Capture 3 prescaler.

Parameters:
TIM5_IC3Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:
  • TIM5_ICPSC_DIV1: no prescaler
  • TIM5_ICPSC_DIV2: capture is done once every 2 events
  • TIM5_ICPSC_DIV4: capture is done once every 4 events
  • TIM5_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 956 of file stm8s_tim5.c.

References IS_TIM5_IC_PRESCALER_OK, and TIM5_CCMR_ICxPSC.

Referenced by TIM5_ICInit().

void TIM5_TimeBaseInit | ( | TIM5_Prescaler_TypeDef | TIM5_Prescaler,
 |  | uint16_t | TIM5_Period
 | ) |  |

Initializes the TIM5 Time Base Unit according to the specified parameters.

Parameters:
TIM5_Prescaler | specifies the Prescaler from TIM5_Prescaler_TypeDef.
TIM5_Period | specifies the Period value.
Return values:
None

Definition at line 90 of file stm8s_tim5.c.

void TIM5_UpdateDisableConfig ( FunctionalState NewState )

Enables or Disables the TIM5 Update event.

Parameters:
NewState new state of the TIM5 peripheral Preload register.This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 387 of file stm8s_tim5.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM5_CR1_UDIS.

void TIM5_UpdateRequestConfig ( TIM5_UpdateSource_TypeDef TIM5_UpdateSource )

Selects the TIM5 Update Request Interrupt source.

Parameters:
TIM5_UpdateSource specifies the Update source. This parameter can be one of the following values
  • TIM5_UPDATESOURCE_REGULAR
  • TIM5_UPDATESOURCE_GLOBAL
Return values:
None

Definition at line 411 of file stm8s_tim5.c.

References IS_TIM5_UPDATE_SOURCE_OK, TIM5_CR1_URS, and TIM5_UPDATESOURCE_GLOBAL.


STM8S/A Standard Peripherals Drivers: IWDG_Public_Functions

Functions
IWDG_Public_Functions

Functions

void | IWDG_Enable (void)
Enables IWDG.
void | IWDG_ReloadCounter (void)
Reloads IWDG counter.
void | IWDG_SetPrescaler (IWDG_Prescaler_TypeDef IWDG_Prescaler)
Sets IWDG Prescaler value.
void | IWDG_SetReload (uint8_t IWDG_Reload)
Sets IWDG Reload value.
void | IWDG_WriteAccessCmd (IWDG_WriteAccess_TypeDef IWDG_WriteAccess)
Enables or disables write access to Prescaler and Reload registers.

Function Documentation

void IWDG_Enable ( void )

Enables IWDG.

Parameters:
None
Return values:
None

Definition at line 99 of file stm8s_iwdg.c.

References IWDG, and IWDG_KEY_ENABLE.

void IWDG_ReloadCounter ( void )

Reloads IWDG counter.

Note:
Write access should be enabled
Parameters:
None
Return values:
None

Definition at line 89 of file stm8s_iwdg.c.

References IWDG, and IWDG_KEY_REFRESH.

void IWDG_SetPrescaler ( IWDG_Prescaler_TypeDef IWDG_Prescaler )

Sets IWDG Prescaler value.

Note:
Write access should be enabled
Parameters:
IWDG_Prescaler : Specifies the IWDG Prescaler value. This parameter can be a value of IWDG_Prescaler_TypeDef.
Return values:
None

Definition at line 63 of file stm8s_iwdg.c.

References IS_IWDG_PRESCALER_OK, and IWDG.

void IWDG_SetReload ( uint8_t IWDG_Reload )

Sets IWDG Reload value.

Note:
Write access should be enabled
Parameters:
IWDG_Reload : Reload register value. This parameter must be a number between 0 and 0xFF.
Return values:
None

Definition at line 78 of file stm8s_iwdg.c.

References IWDG.

void IWDG_WriteAccessCmd ( IWDG_WriteAccess_TypeDef IWDG_WriteAccess )

Enables or disables write access to Prescaler and Reload registers.

Parameters:
IWDG_WriteAccess : New state of write access to Prescaler and Reload registers. This parameter can be a value of IWDG_WriteAccess_TypeDef.
Return values:
None

Definition at line 48 of file stm8s_iwdg.c.

References IS_IWDG_WRITEACCESS_MODE_OK, and IWDG.


STM8S/A Standard Peripherals Drivers: AWU_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
AWU_struct Struct Reference

Auto Wake Up (AWU) peripheral registers. More...

#include <stm8s.h>

Data Fields

__IO uint8_t | APR
__IO uint8_t | CSR
__IO uint8_t | TBR

Detailed Description

Auto Wake Up (AWU) peripheral registers.

Definition at line 440 of file stm8s.h.

Field Documentation

__IO uint8_t AWU_struct::APR

AWU Asynchronous prescaler buffer

Definition at line 443 of file stm8s.h.

__IO uint8_t AWU_struct::CSR

AWU Control status register

Definition at line 442 of file stm8s.h.

__IO uint8_t AWU_struct::TBR

AWU Time base selection register

Definition at line 444 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: BEEP_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
BEEP_struct Struct Reference

Beeper (BEEP) peripheral registers. More...

#include <stm8s.h>

Data Fields

__IO uint8_t CSR

Detailed Description

Beeper (BEEP) peripheral registers.

Definition at line 480 of file stm8s.h.

Field Documentation

__IO uint8_t BEEP_struct::CSR

BEEP Control status register

Definition at line 482 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: CAN_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
CAN_TypeDef Struct Reference

Controller Area Network (CAN) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | DGR
__IO uint8_t | IER
__IO uint8_t | MCR
__IO uint8_t | MSR
union {
struct {
__IO uint8_t BTR1
__IO uint8_t BTR2
__IO uint8_t EIER
__IO uint8_t ESR
__IO uint8_t FCR1
__IO uint8_t FCR2
__IO uint8_t FCR3
__IO uint8_t FMR1
__IO uint8_t FMR2
__IO uint8_t RECR
uint8_t Reserved1 [2]
uint8_t Reserved2 [3]
__IO uint8_t TECR
} Config
struct {
__IO uint8_t FR01
__IO uint8_t FR02
__IO uint8_t FR03
__IO uint8_t FR04
__IO uint8_t FR05
__IO uint8_t FR06
__IO uint8_t FR07
__IO uint8_t FR08
__IO uint8_t FR09
__IO uint8_t FR10
__IO uint8_t FR11
__IO uint8_t FR12
__IO uint8_t FR13
__IO uint8_t FR14
__IO uint8_t FR15
__IO uint8_t FR16
} Filter
struct {
__IO uint8_t F0R1
__IO uint8_t F0R2
__IO uint8_t F0R3
__IO uint8_t F0R4
__IO uint8_t F0R5
__IO uint8_t F0R6
__IO uint8_t F0R7
__IO uint8_t F0R8
__IO uint8_t F1R1
__IO uint8_t F1R2
__IO uint8_t F1R3
__IO uint8_t F1R4
__IO uint8_t F1R5
__IO uint8_t F1R6
__IO uint8_t F1R7
__IO uint8_t F1R8
} Filter01
struct {
__IO uint8_t F2R1
__IO uint8_t F2R2
__IO uint8_t F2R3
__IO uint8_t F2R4
__IO uint8_t F2R5
__IO uint8_t F2R6
__IO uint8_t F2R7
__IO uint8_t F2R8
__IO uint8_t F3R1
__IO uint8_t F3R2
__IO uint8_t F3R3
__IO uint8_t F3R4
__IO uint8_t F3R5
__IO uint8_t F3R6
__IO uint8_t F3R7
__IO uint8_t F3R8
} Filter23
struct {
__IO uint8_t F4R1
__IO uint8_t F4R2
__IO uint8_t F4R3
__IO uint8_t F4R4
__IO uint8_t F4R5
__IO uint8_t F4R6
__IO uint8_t F4R7
__IO uint8_t F4R8
__IO uint8_t F5R1
__IO uint8_t F5R2
__IO uint8_t F5R3
__IO uint8_t F5R4
__IO uint8_t F5R5
__IO uint8_t F5R6
__IO uint8_t F5R7
__IO uint8_t F5R8
} Filter45
struct {
__IO uint8_t MDAR1
__IO uint8_t MDAR2
__IO uint8_t MDAR3
__IO uint8_t MDAR4
__IO uint8_t MDAR5
__IO uint8_t MDAR6
__IO uint8_t MDAR7
__IO uint8_t MDAR8
__IO uint8_t MDLCR
__IO uint8_t MFMI
__IO uint8_t MIDR1
__IO uint8_t MIDR2
__IO uint8_t MIDR3
__IO uint8_t MIDR4
__IO uint8_t MTSRH
__IO uint8_t MTSRL
} RxFIFO
struct {
__IO uint8_t MCSR
__IO uint8_t MDAR1
__IO uint8_t MDAR2
__IO uint8_t MDAR3
__IO uint8_t MDAR4
__IO uint8_t MDAR5
__IO uint8_t MDAR6
__IO uint8_t MDAR7
__IO uint8_t MDAR8
__IO uint8_t MDLCR
__IO uint8_t MIDR1
__IO uint8_t MIDR2
__IO uint8_t MIDR3
__IO uint8_t MIDR4
__IO uint8_t MTSRH
__IO uint8_t MTSRL
} TxMailbox
} Page
__IO uint8_t | PSR
__IO uint8_t | RFR
__IO uint8_t | TPR
__IO uint8_t | TSR

Detailed Description

Controller Area Network (CAN)

Definition at line 2174 of file stm8s.h.

Field Documentation

__IO uint8_t CAN_TypeDef::BTR1

Definition at line 2297 of file stm8s.h.

__IO uint8_t CAN_TypeDef::BTR2

Definition at line 2298 of file stm8s.h.

struct { ... } CAN_TypeDef::Config
__IO uint8_t CAN_TypeDef::DGR

CAN diagnosis register

Definition at line 2182 of file stm8s.h.

__IO uint8_t CAN_TypeDef::EIER

Definition at line 2294 of file stm8s.h.

__IO uint8_t CAN_TypeDef::ESR

Definition at line 2293 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F0R1

Definition at line 2230 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F0R2

Definition at line 2231 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F0R3

Definition at line 2232 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F0R4

Definition at line 2233 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F0R5

Definition at line 2234 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F0R6

Definition at line 2235 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F0R7

Definition at line 2236 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F0R8

Definition at line 2237 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F1R1

Definition at line 2239 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F1R2

Definition at line 2240 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F1R3

Definition at line 2241 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F1R4

Definition at line 2242 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F1R5

Definition at line 2243 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F1R6

Definition at line 2244 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F1R7

Definition at line 2245 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F1R8

Definition at line 2246 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F2R1

Definition at line 2251 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F2R2

Definition at line 2252 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F2R3

Definition at line 2253 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F2R4

Definition at line 2254 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F2R5

Definition at line 2255 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F2R6

Definition at line 2256 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F2R7

Definition at line 2257 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F2R8

Definition at line 2258 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F3R1

Definition at line 2260 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F3R2

Definition at line 2261 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F3R3

Definition at line 2262 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F3R4

Definition at line 2263 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F3R5

Definition at line 2264 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F3R6

Definition at line 2265 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F3R7

Definition at line 2266 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F3R8

Definition at line 2267 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F4R1

Definition at line 2272 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F4R2

Definition at line 2273 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F4R3

Definition at line 2274 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F4R4

Definition at line 2275 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F4R5

Definition at line 2276 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F4R6

Definition at line 2277 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F4R7

Definition at line 2278 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F4R8

Definition at line 2279 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F5R1

Definition at line 2281 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F5R2

Definition at line 2282 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F5R3

Definition at line 2283 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F5R4

Definition at line 2284 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F5R5

Definition at line 2285 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F5R6

Definition at line 2286 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F5R7

Definition at line 2287 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F5R8

Definition at line 2288 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FCR1

Definition at line 2302 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FCR2

Definition at line 2303 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FCR3

Definition at line 2304 of file stm8s.h.

struct { ... } CAN_TypeDef::Filter
struct { ... } CAN_TypeDef::Filter01
struct { ... } CAN_TypeDef::Filter23
struct { ... } CAN_TypeDef::Filter45
__IO uint8_t CAN_TypeDef::FMR1

Definition at line 2300 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FMR2

Definition at line 2301 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FR01

Definition at line 2209 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FR02

Definition at line 2210 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FR03

Definition at line 2211 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FR04

Definition at line 2212 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FR05

Definition at line 2213 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FR06

Definition at line 2214 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FR07

Definition at line 2215 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FR08

Definition at line 2216 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FR09

Definition at line 2218 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FR10

Definition at line 2219 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FR11

Definition at line 2220 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FR12

Definition at line 2221 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FR13

Definition at line 2222 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FR14

Definition at line 2223 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FR15

Definition at line 2224 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FR16

Definition at line 2225 of file stm8s.h.

__IO uint8_t CAN_TypeDef::IER

CAN interrupt enable register

Definition at line 2181 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MCR

CAN master control register

Definition at line 2176 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MCSR

Definition at line 2189 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MDAR1

Definition at line 2195 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MDAR2

Definition at line 2196 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MDAR3

Definition at line 2197 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MDAR4

Definition at line 2198 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MDAR5

Definition at line 2199 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MDAR6

Definition at line 2200 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MDAR7

Definition at line 2201 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MDAR8

Definition at line 2202 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MDLCR

Definition at line 2190 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MFMI

Definition at line 2310 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MIDR1

Definition at line 2191 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MIDR2

Definition at line 2192 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MIDR3

Definition at line 2193 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MIDR4

Definition at line 2194 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MSR

CAN master status register

Definition at line 2177 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MTSRH

Definition at line 2204 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MTSRL

Definition at line 2203 of file stm8s.h.

union { ... } CAN_TypeDef::Page
__IO uint8_t CAN_TypeDef::PSR

CAN page selection register

Definition at line 2183 of file stm8s.h.

__IO uint8_t CAN_TypeDef::RECR

Definition at line 2296 of file stm8s.h.

uint8_t CAN_TypeDef::Reserved1[2]

Definition at line 2299 of file stm8s.h.

uint8_t CAN_TypeDef::Reserved2[3]

Definition at line 2305 of file stm8s.h.

__IO uint8_t CAN_TypeDef::RFR

CAN receive FIFO register

Definition at line 2180 of file stm8s.h.

struct { ... } CAN_TypeDef::RxFIFO
__IO uint8_t CAN_TypeDef::TECR

Definition at line 2295 of file stm8s.h.

__IO uint8_t CAN_TypeDef::TPR

CAN transmit priority register

Definition at line 2179 of file stm8s.h.

__IO uint8_t CAN_TypeDef::TSR

CAN transmit status register

Definition at line 2178 of file stm8s.h.

struct { ... } CAN_TypeDef::TxMailbox
The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: CFG_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
CFG_struct Struct Reference

Configuration Registers (CFG) More...

#include <stm8s.h>

Data Fields

__IO uint8_t GCR

Detailed Description

Configuration Registers (CFG)

Definition at line 2522 of file stm8s.h.

Field Documentation

__IO uint8_t CFG_struct::GCR

Global Configuration register

Definition at line 2524 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: CLK_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
CLK_struct Struct Reference

Clock Controller (CLK) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | CCOR
__IO uint8_t | CKDIVR
__IO uint8_t | CMSR
__IO uint8_t | CSSR
__IO uint8_t | ECKR
__IO uint8_t | HSITRIMR
__IO uint8_t | ICKR
__IO uint8_t | PCKENR1
__IO uint8_t | PCKENR2
uint8_t RESERVED
uint8_t RESERVED1
__IO uint8_t | SWCR
__IO uint8_t | SWIMCCR
__IO uint8_t | SWR

Detailed Description

Clock Controller (CLK)

Definition at line 508 of file stm8s.h.

Field Documentation

__IO uint8_t CLK_struct::CCOR

Configurable Clock Output Register

Definition at line 519 of file stm8s.h.

__IO uint8_t CLK_struct::CKDIVR

Clock Divider Register

Definition at line 516 of file stm8s.h.

__IO uint8_t CLK_struct::CMSR

Clock Master Status Register

Definition at line 513 of file stm8s.h.

__IO uint8_t CLK_struct::CSSR

Clock Security System Register

Definition at line 518 of file stm8s.h.

__IO uint8_t CLK_struct::ECKR

External Clocks Control Register

Definition at line 511 of file stm8s.h.

__IO uint8_t CLK_struct::HSITRIMR

HSI Calibration Trimmer Register

Definition at line 522 of file stm8s.h.

__IO uint8_t CLK_struct::ICKR

Internal Clocks Control Register

Definition at line 510 of file stm8s.h.

__IO uint8_t CLK_struct::PCKENR1

Peripheral Clock Gating Register 1

Definition at line 517 of file stm8s.h.

__IO uint8_t CLK_struct::PCKENR2

Peripheral Clock Gating Register 2

Definition at line 520 of file stm8s.h.

uint8_t CLK_struct::RESERVED

Reserved byte

Definition at line 512 of file stm8s.h.

uint8_t CLK_struct::RESERVED1

Reserved byte

Definition at line 521 of file stm8s.h.

__IO uint8_t CLK_struct::SWCR

Switch Control Register

Definition at line 515 of file stm8s.h.

__IO uint8_t CLK_struct::SWIMCCR

SWIM clock control register

Definition at line 523 of file stm8s.h.

__IO uint8_t CLK_struct::SWR

Clock Master Switch Register

Definition at line 514 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: EXTI_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
EXTI_struct Struct Reference

External Interrupt Controller (EXTI) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | CR1
__IO uint8_t | CR2

Detailed Description

External Interrupt Controller (EXTI)

Definition at line 1473 of file stm8s.h.

Field Documentation

__IO uint8_t EXTI_struct::CR1

External Interrupt Control Register for PORTA to PORTD

Definition at line 1475 of file stm8s.h.

__IO uint8_t EXTI_struct::CR2

External Interrupt Control Register for PORTE and TLI

Definition at line 1476 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: FLASH_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
FLASH_struct Struct Reference

FLASH program and Data memory (FLASH) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | CR1
__IO uint8_t | CR2
__IO uint8_t | DUKR
__IO uint8_t | FPR
__IO uint8_t | IAPSR
__IO uint8_t | NCR2
__IO uint8_t | NFPR
__IO uint8_t | PUKR
uint8_t RESERVED1
uint8_t RESERVED2
uint8_t RESERVED3

Detailed Description

FLASH program and Data memory (FLASH)

Definition at line 1514 of file stm8s.h.

Field Documentation

__IO uint8_t FLASH_struct::CR1

Flash control register 1

Definition at line 1516 of file stm8s.h.

__IO uint8_t FLASH_struct::CR2

Flash control register 2

Definition at line 1517 of file stm8s.h.

__IO uint8_t FLASH_struct::DUKR

Data EEPROM unprotection register

Definition at line 1526 of file stm8s.h.

__IO uint8_t FLASH_struct::FPR

Flash protection register

Definition at line 1519 of file stm8s.h.

__IO uint8_t FLASH_struct::IAPSR

Flash in-application programming status register

Definition at line 1521 of file stm8s.h.

__IO uint8_t FLASH_struct::NCR2

Flash complementary control register 2

Definition at line 1518 of file stm8s.h.

__IO uint8_t FLASH_struct::NFPR

Flash complementary protection register

Definition at line 1520 of file stm8s.h.

__IO uint8_t FLASH_struct::PUKR

Flash program memory unprotection register

Definition at line 1524 of file stm8s.h.

uint8_t FLASH_struct::RESERVED1

Reserved byte

Definition at line 1522 of file stm8s.h.

uint8_t FLASH_struct::RESERVED2

Reserved byte

Definition at line 1523 of file stm8s.h.

uint8_t FLASH_struct::RESERVED3

Reserved byte

Definition at line 1525 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: I2C_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
I2C_struct Struct Reference

Inter-Integrated Circuit (I2C) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | CCRH
__IO uint8_t | CCRL
__IO uint8_t | CR1
__IO uint8_t | CR2
__IO uint8_t | DR
__IO uint8_t | FREQR
__IO uint8_t | ITR
__IO uint8_t | OARH
__IO uint8_t | OARL
uint8_t RESERVED1
uint8_t RESERVED2
__IO uint8_t | SR1
__IO uint8_t | SR2
__IO uint8_t | SR3
__IO uint8_t | TRISER

Detailed Description

Inter-Integrated Circuit (I2C)

Definition at line 1328 of file stm8s.h.

Field Documentation

__IO uint8_t I2C_struct::CCRH

I2C clock control register high

Definition at line 1342 of file stm8s.h.

__IO uint8_t I2C_struct::CCRL

I2C clock control register low

Definition at line 1341 of file stm8s.h.

__IO uint8_t I2C_struct::CR1

I2C control register 1

Definition at line 1330 of file stm8s.h.

__IO uint8_t I2C_struct::CR2

I2C control register 2

Definition at line 1331 of file stm8s.h.

__IO uint8_t I2C_struct::DR

I2C data register

Definition at line 1336 of file stm8s.h.

__IO uint8_t I2C_struct::FREQR

I2C frequency register

Definition at line 1332 of file stm8s.h.

__IO uint8_t I2C_struct::ITR

I2C interrupt register

Definition at line 1340 of file stm8s.h.

__IO uint8_t I2C_struct::OARH

I2C own address register MSB

Definition at line 1334 of file stm8s.h.

__IO uint8_t I2C_struct::OARL

I2C own address register LSB

Definition at line 1333 of file stm8s.h.

uint8_t I2C_struct::RESERVED1

Reserved byte

Definition at line 1335 of file stm8s.h.

uint8_t I2C_struct::RESERVED2

Reserved byte

Definition at line 1344 of file stm8s.h.

__IO uint8_t I2C_struct::SR1

I2C status register 1

Definition at line 1337 of file stm8s.h.

__IO uint8_t I2C_struct::SR2

I2C status register 2

Definition at line 1338 of file stm8s.h.

__IO uint8_t I2C_struct::SR3

I2C status register 3

Definition at line 1339 of file stm8s.h.

__IO uint8_t I2C_struct::TRISER

I2C maximum rise time register

Definition at line 1343 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: ITC_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
ITC_struct Struct Reference

Interrupt Controller (ITC) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | ISPR1
__IO uint8_t | ISPR2
__IO uint8_t | ISPR3
__IO uint8_t | ISPR4
__IO uint8_t | ISPR5
__IO uint8_t | ISPR6
__IO uint8_t | ISPR7
__IO uint8_t | ISPR8

Detailed Description

Interrupt Controller (ITC)

Definition at line 1435 of file stm8s.h.

Field Documentation

__IO uint8_t ITC_struct::ISPR1

Interrupt Software Priority register 1

Definition at line 1437 of file stm8s.h.

__IO uint8_t ITC_struct::ISPR2

Interrupt Software Priority register 2

Definition at line 1438 of file stm8s.h.

__IO uint8_t ITC_struct::ISPR3

Interrupt Software Priority register 3

Definition at line 1439 of file stm8s.h.

__IO uint8_t ITC_struct::ISPR4

Interrupt Software Priority register 4

Definition at line 1440 of file stm8s.h.

__IO uint8_t ITC_struct::ISPR5

Interrupt Software Priority register 5

Definition at line 1441 of file stm8s.h.

__IO uint8_t ITC_struct::ISPR6

Interrupt Software Priority register 6

Definition at line 1442 of file stm8s.h.

__IO uint8_t ITC_struct::ISPR7

Interrupt Software Priority register 7

Definition at line 1443 of file stm8s.h.

__IO uint8_t ITC_struct::ISPR8

Interrupt Software Priority register 8

Definition at line 1444 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: IWDG_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
IWDG_struct Struct Reference

Independent Watchdog (IWDG) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | KR
__IO uint8_t | PR
__IO uint8_t | RLR

Detailed Description

Independent Watchdog (IWDG)

Definition at line 1609 of file stm8s.h.

Field Documentation

__IO uint8_t IWDG_struct::KR

Key Register

Definition at line 1611 of file stm8s.h.

__IO uint8_t IWDG_struct::PR

Prescaler Register

Definition at line 1612 of file stm8s.h.

__IO uint8_t IWDG_struct::RLR

Reload Register

Definition at line 1613 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: OPT_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
OPT_struct Struct Reference

Option Bytes (OPT) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | NOPT1
__IO uint8_t | NOPT2
__IO uint8_t | NOPT3
__IO uint8_t | NOPT4
__IO uint8_t | NOPT5
__IO uint8_t | NOPT7
__IO uint8_t | OPT0
__IO uint8_t | OPT1
__IO uint8_t | OPT2
__IO uint8_t | OPT3
__IO uint8_t | OPT4
__IO uint8_t | OPT5
__IO uint8_t | OPT7
uint8_t RESERVED1
uint8_t RESERVED2

Detailed Description

Option Bytes (OPT)

Definition at line 1584 of file stm8s.h.

Field Documentation

__IO uint8_t OPT_struct::NOPT1

Complementary Option byte 1

Definition at line 1588 of file stm8s.h.

__IO uint8_t OPT_struct::NOPT2

Complementary Option byte 2

Definition at line 1590 of file stm8s.h.

__IO uint8_t OPT_struct::NOPT3

Complementary Option byte 3

Definition at line 1592 of file stm8s.h.

__IO uint8_t OPT_struct::NOPT4

Complementary Option byte 4

Definition at line 1594 of file stm8s.h.

__IO uint8_t OPT_struct::NOPT5

Complementary Option byte 5

Definition at line 1596 of file stm8s.h.

__IO uint8_t OPT_struct::NOPT7

Complementary Option byte 7

Definition at line 1600 of file stm8s.h.

__IO uint8_t OPT_struct::OPT0

Option byte 0: Read-out protection (not accessible in IAP mode)

Definition at line 1586 of file stm8s.h.

__IO uint8_t OPT_struct::OPT1

Option byte 1: User boot code

Definition at line 1587 of file stm8s.h.

__IO uint8_t OPT_struct::OPT2

Option byte 2: Alternate function remapping

Definition at line 1589 of file stm8s.h.

__IO uint8_t OPT_struct::OPT3

Option byte 3: Watchdog option

Definition at line 1591 of file stm8s.h.

__IO uint8_t OPT_struct::OPT4

Option byte 4: Clock option

Definition at line 1593 of file stm8s.h.

__IO uint8_t OPT_struct::OPT5

Option byte 5: HSE clock startup

Definition at line 1595 of file stm8s.h.

__IO uint8_t OPT_struct::OPT7

Option byte 7: flash wait states

Definition at line 1599 of file stm8s.h.

uint8_t OPT_struct::RESERVED1

Reserved Option byte

Definition at line 1597 of file stm8s.h.

uint8_t OPT_struct::RESERVED2

Reserved Option byte

Definition at line 1598 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: RST_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
RST_struct Struct Reference

Reset Controller (RST) More...

#include <stm8s.h>

Data Fields

__IO uint8_t SR

Detailed Description

Reset Controller (RST)

Definition at line 1671 of file stm8s.h.

Field Documentation

__IO uint8_t RST_struct::SR

Reset status register

Definition at line 1673 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: SPI_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
SPI_struct Struct Reference

Serial Peripheral Interface (SPI) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | CR1
__IO uint8_t | CR2
__IO uint8_t | CRCPR
__IO uint8_t | DR
__IO uint8_t | ICR
__IO uint8_t | RXCRCR
__IO uint8_t | SR
__IO uint8_t | TXCRCR

Detailed Description

Serial Peripheral Interface (SPI)

Definition at line 1696 of file stm8s.h.

Field Documentation

__IO uint8_t SPI_struct::CR1

SPI control register 1

Definition at line 1698 of file stm8s.h.

__IO uint8_t SPI_struct::CR2

SPI control register 2

Definition at line 1699 of file stm8s.h.

__IO uint8_t SPI_struct::CRCPR

SPI CRC polynomial register

Definition at line 1703 of file stm8s.h.

__IO uint8_t SPI_struct::DR

SPI data I/O register

Definition at line 1702 of file stm8s.h.

__IO uint8_t SPI_struct::ICR

SPI interrupt control register

Definition at line 1700 of file stm8s.h.

__IO uint8_t SPI_struct::RXCRCR

SPI Rx CRC register

Definition at line 1704 of file stm8s.h.

__IO uint8_t SPI_struct::SR

SPI status register

Definition at line 1701 of file stm8s.h.

__IO uint8_t SPI_struct::TXCRCR

SPI Tx CRC register

Definition at line 1705 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: TIM1_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
TIM1_struct Struct Reference

16-bit timer with complementary PWM outputs (TIM1) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | ARRH
__IO uint8_t | ARRL
__IO uint8_t | BKR
__IO uint8_t | CCER1
__IO uint8_t | CCER2
__IO uint8_t | CCMR1
__IO uint8_t | CCMR2
__IO uint8_t | CCMR3
__IO uint8_t | CCMR4
__IO uint8_t | CCR1H
__IO uint8_t | CCR1L
__IO uint8_t | CCR2H
__IO uint8_t | CCR2L
__IO uint8_t | CCR3H
__IO uint8_t | CCR3L
__IO uint8_t | CCR4H
__IO uint8_t | CCR4L
__IO uint8_t | CNTRH
__IO uint8_t | CNTRL
__IO uint8_t | CR1
__IO uint8_t | CR2
__IO uint8_t | DTR
__IO uint8_t | EGR
__IO uint8_t | ETR
__IO uint8_t | IER
__IO uint8_t | OISR
__IO uint8_t | PSCRH
__IO uint8_t | PSCRL
__IO uint8_t | RCR
__IO uint8_t | SMCR
__IO uint8_t | SR1
__IO uint8_t | SR2

Detailed Description

16-bit timer with complementary PWM outputs (TIM1)

Definition at line 612 of file stm8s.h.

Field Documentation

__IO uint8_t TIM1_struct::ARRH

auto-reload register high

Definition at line 632 of file stm8s.h.

__IO uint8_t TIM1_struct::ARRL

auto-reload register low

Definition at line 633 of file stm8s.h.

__IO uint8_t TIM1_struct::BKR

Break Register

Definition at line 643 of file stm8s.h.

__IO uint8_t TIM1_struct::CCER1

CC enable register 1

Definition at line 626 of file stm8s.h.

__IO uint8_t TIM1_struct::CCER2

CC enable register 2

Definition at line 627 of file stm8s.h.

__IO uint8_t TIM1_struct::CCMR1

CC mode register 1

Definition at line 622 of file stm8s.h.

__IO uint8_t TIM1_struct::CCMR2

CC mode register 2

Definition at line 623 of file stm8s.h.

__IO uint8_t TIM1_struct::CCMR3

CC mode register 3

Definition at line 624 of file stm8s.h.

__IO uint8_t TIM1_struct::CCMR4

CC mode register 4

Definition at line 625 of file stm8s.h.

__IO uint8_t TIM1_struct::CCR1H

capture/compare register 1 high

Definition at line 635 of file stm8s.h.

__IO uint8_t TIM1_struct::CCR1L

capture/compare register 1 low

Definition at line 636 of file stm8s.h.

__IO uint8_t TIM1_struct::CCR2H

capture/compare register 2 high

Definition at line 637 of file stm8s.h.

__IO uint8_t TIM1_struct::CCR2L

capture/compare register 2 low

Definition at line 638 of file stm8s.h.

__IO uint8_t TIM1_struct::CCR3H

capture/compare register 3 high

Definition at line 639 of file stm8s.h.

__IO uint8_t TIM1_struct::CCR3L

capture/compare register 3 low

Definition at line 640 of file stm8s.h.

__IO uint8_t TIM1_struct::CCR4H

capture/compare register 3 high

Definition at line 641 of file stm8s.h.

__IO uint8_t TIM1_struct::CCR4L

capture/compare register 3 low

Definition at line 642 of file stm8s.h.

__IO uint8_t TIM1_struct::CNTRH

counter high

Definition at line 628 of file stm8s.h.

__IO uint8_t TIM1_struct::CNTRL

counter low

Definition at line 629 of file stm8s.h.

__IO uint8_t TIM1_struct::CR1

control register 1

Definition at line 614 of file stm8s.h.

__IO uint8_t TIM1_struct::CR2

control register 2

Definition at line 615 of file stm8s.h.

__IO uint8_t TIM1_struct::DTR

dead-time register

Definition at line 644 of file stm8s.h.

__IO uint8_t TIM1_struct::EGR

event generation register

Definition at line 621 of file stm8s.h.

__IO uint8_t TIM1_struct::ETR

external trigger register

Definition at line 617 of file stm8s.h.

__IO uint8_t TIM1_struct::IER

interrupt enable register

Definition at line 618 of file stm8s.h.

__IO uint8_t TIM1_struct::OISR

Output idle register

Definition at line 645 of file stm8s.h.

__IO uint8_t TIM1_struct::PSCRH

prescaler high

Definition at line 630 of file stm8s.h.

__IO uint8_t TIM1_struct::PSCRL

prescaler low

Definition at line 631 of file stm8s.h.

__IO uint8_t TIM1_struct::RCR

Repetition Counter register

Definition at line 634 of file stm8s.h.

__IO uint8_t TIM1_struct::SMCR

Synchro mode control register

Definition at line 616 of file stm8s.h.

__IO uint8_t TIM1_struct::SR1

status register 1

Definition at line 619 of file stm8s.h.

__IO uint8_t TIM1_struct::SR2

status register 2

Definition at line 620 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: TIM2_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
TIM2_struct Struct Reference

16-bit timer (TIM2) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | ARRH
__IO uint8_t | ARRL
__IO uint8_t | CCER1
__IO uint8_t | CCER2
__IO uint8_t | CCMR1
__IO uint8_t | CCMR2
__IO uint8_t | CCMR3
__IO uint8_t | CCR1H
__IO uint8_t | CCR1L
__IO uint8_t | CCR2H
__IO uint8_t | CCR2L
__IO uint8_t | CCR3H
__IO uint8_t | CCR3L
__IO uint8_t | CNTRH
__IO uint8_t | CNTRL
__IO uint8_t | CR1
__IO uint8_t | EGR
__IO uint8_t | IER
__IO uint8_t | PSCR
__IO uint8_t | SR1
__IO uint8_t | SR2

Detailed Description

16-bit timer (TIM2)

Definition at line 824 of file stm8s.h.

Field Documentation

__IO uint8_t TIM2_struct::ARRH

auto-reload register high

Definition at line 843 of file stm8s.h.

__IO uint8_t TIM2_struct::ARRL

auto-reload register low

Definition at line 844 of file stm8s.h.

__IO uint8_t TIM2_struct::CCER1

CC enable register 1

Definition at line 838 of file stm8s.h.

__IO uint8_t TIM2_struct::CCER2

CC enable register 2

Definition at line 839 of file stm8s.h.

__IO uint8_t TIM2_struct::CCMR1

CC mode register 1

Definition at line 835 of file stm8s.h.

__IO uint8_t TIM2_struct::CCMR2

CC mode register 2

Definition at line 836 of file stm8s.h.

__IO uint8_t TIM2_struct::CCMR3

CC mode register 3

Definition at line 837 of file stm8s.h.

__IO uint8_t TIM2_struct::CCR1H

capture/compare register 1 high

Definition at line 845 of file stm8s.h.

__IO uint8_t TIM2_struct::CCR1L

capture/compare register 1 low

Definition at line 846 of file stm8s.h.

__IO uint8_t TIM2_struct::CCR2H

capture/compare register 2 high

Definition at line 847 of file stm8s.h.

__IO uint8_t TIM2_struct::CCR2L

capture/compare register 2 low

Definition at line 848 of file stm8s.h.

__IO uint8_t TIM2_struct::CCR3H

capture/compare register 3 high

Definition at line 849 of file stm8s.h.

__IO uint8_t TIM2_struct::CCR3L

capture/compare register 3 low

Definition at line 850 of file stm8s.h.

__IO uint8_t TIM2_struct::CNTRH

counter high

Definition at line 840 of file stm8s.h.

__IO uint8_t TIM2_struct::CNTRL

counter low

Definition at line 841 of file stm8s.h.

__IO uint8_t TIM2_struct::CR1

control register 1

Definition at line 826 of file stm8s.h.

__IO uint8_t TIM2_struct::EGR

event generation register

Definition at line 834 of file stm8s.h.

__IO uint8_t TIM2_struct::IER

interrupt enable register

Definition at line 831 of file stm8s.h.

__IO uint8_t TIM2_struct::PSCR

prescaler register

Definition at line 842 of file stm8s.h.

__IO uint8_t TIM2_struct::SR1

status register 1

Definition at line 832 of file stm8s.h.

__IO uint8_t TIM2_struct::SR2

status register 2

Definition at line 833 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: TIM3_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
TIM3_struct Struct Reference

16-bit timer (TIM3) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | ARRH
__IO uint8_t | ARRL
__IO uint8_t | CCER1
__IO uint8_t | CCMR1
__IO uint8_t | CCMR2
__IO uint8_t | CCR1H
__IO uint8_t | CCR1L
__IO uint8_t | CCR2H
__IO uint8_t | CCR2L
__IO uint8_t | CNTRH
__IO uint8_t | CNTRL
__IO uint8_t | CR1
__IO uint8_t | EGR
__IO uint8_t | IER
__IO uint8_t | PSCR
__IO uint8_t | SR1
__IO uint8_t | SR2

Detailed Description

16-bit timer (TIM3)

Definition at line 952 of file stm8s.h.

Field Documentation

__IO uint8_t TIM3_struct::ARRH

auto-reload register high

Definition at line 965 of file stm8s.h.

__IO uint8_t TIM3_struct::ARRL

auto-reload register low

Definition at line 966 of file stm8s.h.

__IO uint8_t TIM3_struct::CCER1

CC enable register 1

Definition at line 961 of file stm8s.h.

__IO uint8_t TIM3_struct::CCMR1

CC mode register 1

Definition at line 959 of file stm8s.h.

__IO uint8_t TIM3_struct::CCMR2

CC mode register 2

Definition at line 960 of file stm8s.h.

__IO uint8_t TIM3_struct::CCR1H

capture/compare register 1 high

Definition at line 967 of file stm8s.h.

__IO uint8_t TIM3_struct::CCR1L

capture/compare register 1 low

Definition at line 968 of file stm8s.h.

__IO uint8_t TIM3_struct::CCR2H

capture/compare register 2 high

Definition at line 969 of file stm8s.h.

__IO uint8_t TIM3_struct::CCR2L

capture/compare register 2 low

Definition at line 970 of file stm8s.h.

__IO uint8_t TIM3_struct::CNTRH

counter high

Definition at line 962 of file stm8s.h.

__IO uint8_t TIM3_struct::CNTRL

counter low

Definition at line 963 of file stm8s.h.

__IO uint8_t TIM3_struct::CR1

control register 1

Definition at line 954 of file stm8s.h.

__IO uint8_t TIM3_struct::EGR

event generation register

Definition at line 958 of file stm8s.h.

__IO uint8_t TIM3_struct::IER

interrupt enable register

Definition at line 955 of file stm8s.h.

__IO uint8_t TIM3_struct::PSCR

prescaler register

Definition at line 964 of file stm8s.h.

__IO uint8_t TIM3_struct::SR1

status register 1

Definition at line 956 of file stm8s.h.

__IO uint8_t TIM3_struct::SR2

status register 2

Definition at line 957 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: TIM4_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
TIM4_struct Struct Reference

8-bit system timer (TIM4) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | ARR
__IO uint8_t | CNTR
__IO uint8_t | CR1
__IO uint8_t | EGR
__IO uint8_t | IER
__IO uint8_t | PSCR
__IO uint8_t | SR1

Detailed Description

8-bit system timer (TIM4)

Definition at line 1058 of file stm8s.h.

Field Documentation

__IO uint8_t TIM4_struct::ARR

auto-reload register

Definition at line 1070 of file stm8s.h.

__IO uint8_t TIM4_struct::CNTR

counter register

Definition at line 1068 of file stm8s.h.

__IO uint8_t TIM4_struct::CR1

control register 1

Definition at line 1060 of file stm8s.h.

__IO uint8_t TIM4_struct::EGR

event generation register

Definition at line 1067 of file stm8s.h.

__IO uint8_t TIM4_struct::IER

interrupt enable register

Definition at line 1065 of file stm8s.h.

__IO uint8_t TIM4_struct::PSCR

prescaler register

Definition at line 1069 of file stm8s.h.

__IO uint8_t TIM4_struct::SR1

status register 1

Definition at line 1066 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: TIM5_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
TIM5_struct Struct Reference

16-bit timer with synchro module (TIM5) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | ARRH
__IO uint8_t | ARRL
__IO uint8_t | CCER1
__IO uint8_t | CCER2
__IO uint8_t | CCMR1
__IO uint8_t | CCMR2
__IO uint8_t | CCMR3
__IO uint8_t | CCR1H
__IO uint8_t | CCR1L
__IO uint8_t | CCR2H
__IO uint8_t | CCR2L
__IO uint8_t | CCR3H
__IO uint8_t | CCR3L
__IO uint8_t | CNTRH
__IO uint8_t | CNTRL
__IO uint8_t | CR1
__IO uint8_t | CR2
__IO uint8_t | EGR
__IO uint8_t | IER
__IO uint8_t | PSCR
__IO uint8_t | SMCR
__IO uint8_t | SR1
__IO uint8_t | SR2

Detailed Description

16-bit timer with synchro module (TIM5)

Definition at line 1121 of file stm8s.h.

Field Documentation

__IO uint8_t TIM5_struct::ARRH

TIM5 Auto-Reload Register High

Definition at line 1138 of file stm8s.h.

__IO uint8_t TIM5_struct::ARRL

TIM5 Auto-Reload Register Low

Definition at line 1139 of file stm8s.h.

__IO uint8_t TIM5_struct::CCER1

TIM5 Capture/Compare Enable Register 1

Definition at line 1133 of file stm8s.h.

__IO uint8_t TIM5_struct::CCER2

TIM5 Capture/Compare Enable Register 2

Definition at line 1134 of file stm8s.h.

__IO uint8_t TIM5_struct::CCMR1

TIM5 Capture/Compare Mode Register 1

Definition at line 1130 of file stm8s.h.

__IO uint8_t TIM5_struct::CCMR2

TIM5 Capture/Compare Mode Register 2

Definition at line 1131 of file stm8s.h.

__IO uint8_t TIM5_struct::CCMR3

TIM5 Capture/Compare Mode Register 3

Definition at line 1132 of file stm8s.h.

__IO uint8_t TIM5_struct::CCR1H

TIM5 Capture/Compare Register 1 High

Definition at line 1140 of file stm8s.h.

__IO uint8_t TIM5_struct::CCR1L

TIM5 Capture/Compare Register 1 Low

Definition at line 1141 of file stm8s.h.

__IO uint8_t TIM5_struct::CCR2H

TIM5 Capture/Compare Register 2 High

Definition at line 1142 of file stm8s.h.

__IO uint8_t TIM5_struct::CCR2L

TIM5 Capture/Compare Register 2 Low

Definition at line 1143 of file stm8s.h.

__IO uint8_t TIM5_struct::CCR3H

TIM5 Capture/Compare Register 3 High

Definition at line 1144 of file stm8s.h.

__IO uint8_t TIM5_struct::CCR3L

TIM5 Capture/Compare Register 3 Low

Definition at line 1145 of file stm8s.h.

__IO uint8_t TIM5_struct::CNTRH

TIM5 Counter High

Definition at line 1135 of file stm8s.h.

__IO uint8_t TIM5_struct::CNTRL

TIM5 Counter Low

Definition at line 1136 of file stm8s.h.

__IO uint8_t TIM5_struct::CR1

TIM5 Control Register 1

Definition at line 1123 of file stm8s.h.

__IO uint8_t TIM5_struct::CR2

TIM5 Control Register 2

Definition at line 1124 of file stm8s.h.

__IO uint8_t TIM5_struct::EGR

TIM5 Event Generation Register

Definition at line 1129 of file stm8s.h.

__IO uint8_t TIM5_struct::IER

TIM5 Interrupt Enable Register

Definition at line 1126 of file stm8s.h.

__IO uint8_t TIM5_struct::PSCR

TIM5 Prescaler Register

Definition at line 1137 of file stm8s.h.

__IO uint8_t TIM5_struct::SMCR

TIM5 Slave Mode Control Register

Definition at line 1125 of file stm8s.h.

__IO uint8_t TIM5_struct::SR1

TIM5 Status Register 1

Definition at line 1127 of file stm8s.h.

__IO uint8_t TIM5_struct::SR2

TIM5 Status Register 2

Definition at line 1128 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: TIM6_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
TIM6_struct Struct Reference

8-bit system timer with synchro module(TIM6) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | ARR
__IO uint8_t | CNTR
__IO uint8_t | CR1
__IO uint8_t | CR2
__IO uint8_t | EGR
__IO uint8_t | IER
__IO uint8_t | PSCR
__IO uint8_t | SMCR
__IO uint8_t | SR1

Detailed Description

8-bit system timer with synchro module(TIM6)

Definition at line 1260 of file stm8s.h.

Field Documentation

__IO uint8_t TIM6_struct::ARR

auto-reload register

Definition at line 1270 of file stm8s.h.

__IO uint8_t TIM6_struct::CNTR

counter register

Definition at line 1268 of file stm8s.h.

__IO uint8_t TIM6_struct::CR1

control register 1

Definition at line 1262 of file stm8s.h.

__IO uint8_t TIM6_struct::CR2

control register 2

Definition at line 1263 of file stm8s.h.

__IO uint8_t TIM6_struct::EGR

event generation register

Definition at line 1267 of file stm8s.h.

__IO uint8_t TIM6_struct::IER

interrupt enable register

Definition at line 1265 of file stm8s.h.

__IO uint8_t TIM6_struct::PSCR

prescaler register

Definition at line 1269 of file stm8s.h.

__IO uint8_t TIM6_struct::SMCR

Synchro mode control register

Definition at line 1264 of file stm8s.h.

__IO uint8_t TIM6_struct::SR1

status register 1

Definition at line 1266 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: UART1_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
UART1_struct Struct Reference

Universal Synchronous Asynchronous Receiver Transmitter (UART1) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | BRR1
__IO uint8_t | BRR2
__IO uint8_t | CR1
__IO uint8_t | CR2
__IO uint8_t | CR3
__IO uint8_t | CR4
__IO uint8_t | CR5
__IO uint8_t | DR
__IO uint8_t | GTR
__IO uint8_t | PSCR
__IO uint8_t | SR

Detailed Description

Universal Synchronous Asynchronous Receiver Transmitter (UART1)

Definition at line 1767 of file stm8s.h.

Field Documentation

__IO uint8_t UART1_struct::BRR1

UART1 baud rate register

Definition at line 1771 of file stm8s.h.

__IO uint8_t UART1_struct::BRR2

UART1 DIV mantissa[11:8] SCIDIV fraction

Definition at line 1772 of file stm8s.h.

__IO uint8_t UART1_struct::CR1

UART1 control register 1

Definition at line 1773 of file stm8s.h.

__IO uint8_t UART1_struct::CR2

UART1 control register 2

Definition at line 1774 of file stm8s.h.

__IO uint8_t UART1_struct::CR3

UART1 control register 3

Definition at line 1775 of file stm8s.h.

__IO uint8_t UART1_struct::CR4

UART1 control register 4

Definition at line 1776 of file stm8s.h.

__IO uint8_t UART1_struct::CR5

UART1 control register 5

Definition at line 1777 of file stm8s.h.

__IO uint8_t UART1_struct::DR

UART1 data register

Definition at line 1770 of file stm8s.h.

__IO uint8_t UART1_struct::GTR

UART1 guard time register

Definition at line 1778 of file stm8s.h.

__IO uint8_t UART1_struct::PSCR

UART1 prescaler register

Definition at line 1779 of file stm8s.h.

__IO uint8_t UART1_struct::SR

UART1 status register

Definition at line 1769 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: UART2_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
UART2_struct Struct Reference

Universal Synchronous Asynchronous Receiver Transmitter (UART2) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | BRR1
__IO uint8_t | BRR2
__IO uint8_t | CR1
__IO uint8_t | CR2
__IO uint8_t | CR3
__IO uint8_t | CR4
__IO uint8_t | CR5
__IO uint8_t | CR6
__IO uint8_t | DR
__IO uint8_t | GTR
__IO uint8_t | PSCR
__IO uint8_t | SR

Detailed Description

Universal Synchronous Asynchronous Receiver Transmitter (UART2)

Definition at line 1865 of file stm8s.h.

Field Documentation

__IO uint8_t UART2_struct::BRR1

UART1 baud rate register

Definition at line 1869 of file stm8s.h.

__IO uint8_t UART2_struct::BRR2

UART1 DIV mantissa[11:8] SCIDIV fraction

Definition at line 1870 of file stm8s.h.

__IO uint8_t UART2_struct::CR1

UART1 control register 1

Definition at line 1871 of file stm8s.h.

__IO uint8_t UART2_struct::CR2

UART1 control register 2

Definition at line 1872 of file stm8s.h.

__IO uint8_t UART2_struct::CR3

UART1 control register 3

Definition at line 1873 of file stm8s.h.

__IO uint8_t UART2_struct::CR4

UART1 control register 4

Definition at line 1874 of file stm8s.h.

__IO uint8_t UART2_struct::CR5

UART1 control register 5

Definition at line 1875 of file stm8s.h.

__IO uint8_t UART2_struct::CR6

UART1 control register 6

Definition at line 1876 of file stm8s.h.

__IO uint8_t UART2_struct::DR

UART1 data register

Definition at line 1868 of file stm8s.h.

__IO uint8_t UART2_struct::GTR

UART1 guard time register

Definition at line 1877 of file stm8s.h.

__IO uint8_t UART2_struct::PSCR

UART1 prescaler register

Definition at line 1878 of file stm8s.h.

__IO uint8_t UART2_struct::SR

UART1 status register

Definition at line 1867 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: UART3_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
UART3_struct Struct Reference

LIN Universal Asynchronous Receiver Transmitter (UART3) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | BRR1
__IO uint8_t | BRR2
__IO uint8_t | CR1
__IO uint8_t | CR2
__IO uint8_t | CR3
__IO uint8_t | CR4
__IO uint8_t | CR6
__IO uint8_t | DR
uint8_t RESERVED
__IO uint8_t | SR

Detailed Description

LIN Universal Asynchronous Receiver Transmitter (UART3)

Definition at line 1972 of file stm8s.h.

Field Documentation

__IO uint8_t UART3_struct::BRR1

baud rate register

Definition at line 1976 of file stm8s.h.

__IO uint8_t UART3_struct::BRR2

DIV mantissa[11:8] SCIDIV fraction

Definition at line 1977 of file stm8s.h.

__IO uint8_t UART3_struct::CR1

control register 1

Definition at line 1978 of file stm8s.h.

__IO uint8_t UART3_struct::CR2

control register 2

Definition at line 1979 of file stm8s.h.

__IO uint8_t UART3_struct::CR3

control register 3

Definition at line 1980 of file stm8s.h.

__IO uint8_t UART3_struct::CR4

control register 4

Definition at line 1981 of file stm8s.h.

__IO uint8_t UART3_struct::CR6

control register 5

Definition at line 1983 of file stm8s.h.

__IO uint8_t UART3_struct::DR

data register

Definition at line 1975 of file stm8s.h.

uint8_t UART3_struct::RESERVED

Reserved byte

Definition at line 1982 of file stm8s.h.

__IO uint8_t UART3_struct::SR

status register

Definition at line 1974 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: WWDG_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
WWDG_struct Struct Reference

Window Watchdog (WWDG) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | CR
__IO uint8_t | WR

Detailed Description

Window Watchdog (WWDG)

Definition at line 1633 of file stm8s.h.

Field Documentation

__IO uint8_t WWDG_struct::CR

Control Register

Definition at line 1635 of file stm8s.h.

__IO uint8_t WWDG_struct::WR

Window Register

Definition at line 1636 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
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  • o
  • p
  • r
  • s
  • t
  • w
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- a -

  • APR : AWU_struct
  • ARR : TIM4_struct , TIM6_struct
  • ARRH : TIM1_struct , TIM2_struct , TIM5_struct , TIM3_struct
  • ARRL : TIM2_struct , TIM5_struct , TIM3_struct , TIM1_struct


STM8S/A Standard Peripherals Drivers: stm8s.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Data Structures | Defines | Typedefs | Enumerations
stm8s.h File Reference

This file contains all HW registers definitions and memory mapping. More...

#include "stm8s_conf.h"
#include <intrinsics.h>

Go to the source code of this file.

Data Structures

struct | AWU_struct
Auto Wake Up (AWU) peripheral registers. More...
struct | BEEP_struct
Beeper (BEEP) peripheral registers. More...
struct | CAN_TypeDef
Controller Area Network (CAN) More...
struct | CFG_struct
Configuration Registers (CFG) More...
struct | CLK_struct
Clock Controller (CLK) More...
struct | EXTI_struct
External Interrupt Controller (EXTI) More...
struct | FLASH_struct
FLASH program and Data memory (FLASH) More...
struct | GPIO_struct
General Purpose I/Os (GPIO) More...
struct | I2C_struct
Inter-Integrated Circuit (I2C) More...
struct | ITC_struct
Interrupt Controller (ITC) More...
struct | IWDG_struct
Independent Watchdog (IWDG) More...
struct | OPT_struct
Option Bytes (OPT) More...
struct | RST_struct
Reset Controller (RST) More...
struct | SPI_struct
Serial Peripheral Interface (SPI) More...
struct | TIM1_struct
16-bit timer with complementary PWM outputs (TIM1) More...
struct | TIM2_struct
16-bit timer (TIM2) More...
struct | TIM3_struct
16-bit timer (TIM3) More...
struct | TIM4_struct
8-bit system timer (TIM4) More...
struct | TIM5_struct
16-bit timer with synchro module (TIM5) More...
struct | TIM6_struct
8-bit system timer with synchro module(TIM6) More...
struct | UART1_struct
Universal Synchronous Asynchronous Receiver Transmitter (UART1) More...
struct | UART2_struct
Universal Synchronous Asynchronous Receiver Transmitter (UART2) More...
struct | UART3_struct
LIN Universal Asynchronous Receiver Transmitter (UART3) More...
struct | WWDG_struct
Window Watchdog (WWDG) More...

Defines

#define | __I volatile const
IO definitions.
#define | __IO volatile
#define | __O volatile
#define | __STM8S_STDPERIPH_VERSION
#define | __STM8S_STDPERIPH_VERSION_MAIN ((uint8_t)0x02)
#define | __STM8S_STDPERIPH_VERSION_RC ((uint8_t)0x00)
#define | __STM8S_STDPERIPH_VERSION_SUB1 ((uint8_t)0x03)
#define | __STM8S_STDPERIPH_VERSION_SUB2 ((uint8_t)0x00)
#define | ADC1_BaseAddress 0x53E0
#define | ADC2_BaseAddress 0x5400
#define | AffBit(VAR, Place, Value)
#define | AREA 0x00
#define | AWU ((AWU_TypeDef *) AWU_BaseAddress)
#define | AWU_APR_APR ((uint8_t)0x3F)
#define | AWU_APR_RESET_VALUE ((uint8_t)0x3F)
#define | AWU_BaseAddress 0x50F0
#define | AWU_CSR_AWUEN ((uint8_t)0x10)
#define | AWU_CSR_AWUF ((uint8_t)0x20)
#define | AWU_CSR_MSR ((uint8_t)0x01)
#define | AWU_CSR_RESET_VALUE ((uint8_t)0x00)
#define | AWU_TBR_AWUTB ((uint8_t)0x0F)
#define | AWU_TBR_RESET_VALUE ((uint8_t)0x00)
#define | BEEP ((BEEP_TypeDef *) BEEP_BaseAddress)
#define | BEEP_BaseAddress 0x50F3
#define | BEEP_CSR_BEEPDIV ((uint8_t)0x1F)
#define | BEEP_CSR_BEEPEN ((uint8_t)0x20)
#define | BEEP_CSR_BEEPSEL ((uint8_t)0xC0)
#define | BEEP_CSR_RESET_VALUE ((uint8_t)0x1F)
#define | BitClr(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) &= (~(1<<(7-(BIT)%8))) )
#define | BitSet(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) |= (1<<(7-(BIT)%8)) )
#define | BitVal(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) & (1<<(7-(BIT)%8)) )
#define | BYTE_0(n) ((uint8_t)((n) & (uint8_t)0xFF))
#define | BYTE_1(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)8)))
#define | BYTE_2(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)16)))
#define | BYTE_3(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)24)))
#define | CAN_BaseAddress 0x5420
#define | CAN_BTR1_RESET_VALUE ((uint8_t)0x40)
#define | CAN_BTR2_RESET_VALUE ((uint8_t)0x23)
#define | CAN_DGR_LBKM ((uint8_t)0x01)
#define | CAN_DGR_RESET_VALUE ((uint8_t)0x0C)
#define | CAN_DGR_RX ((uint8_t)0x08)
#define | CAN_DGR_SAMP ((uint8_t)0x04)
#define | CAN_DGR_SLIM ((uint8_t)0x02)
#define | CAN_DGR_TXM2E ((uint8_t)0x10)
#define | CAN_EIER_BOFIE ((uint8_t)0x04)
#define | CAN_EIER_EPVIE ((uint8_t)0x02)
#define | CAN_EIER_ERRIE ((uint8_t)0x80)
#define | CAN_EIER_EWGIE ((uint8_t)0x01)
#define | CAN_EIER_LECIE ((uint8_t)0x10)
#define | CAN_EIER_RESET_VALUE ((uint8_t)0x00)
#define | CAN_ESR_BOFF ((uint8_t)0x04)
#define | CAN_ESR_EPVF ((uint8_t)0x02)
#define | CAN_ESR_EWGF ((uint8_t)0x01)
#define | CAN_ESR_LEC ((uint8_t)0x70)
#define | CAN_ESR_LEC0 ((uint8_t)0x10)
#define | CAN_ESR_LEC1 ((uint8_t)0x20)
#define | CAN_ESR_LEC2 ((uint8_t)0x40)
#define | CAN_ESR_RESET_VALUE ((uint8_t)0x00)
#define | CAN_FCR1_FACT0 ((uint8_t)0x01)
#define | CAN_FCR1_FACT1 ((uint8_t)0x10)
#define | CAN_FCR1_FSC00 ((uint8_t)0x02)
#define | CAN_FCR1_FSC01 ((uint8_t)0x04)
#define | CAN_FCR1_FSC10 ((uint8_t)0x20)
#define | CAN_FCR1_FSC11 ((uint8_t)0x40)
#define | CAN_FCR2_FACT2 ((uint8_t)0x01)
#define | CAN_FCR2_FACT3 ((uint8_t)0x10)
#define | CAN_FCR2_FSC20 ((uint8_t)0x02)
#define | CAN_FCR2_FSC21 ((uint8_t)0x04)
#define | CAN_FCR2_FSC30 ((uint8_t)0x20)
#define | CAN_FCR2_FSC31 ((uint8_t)0x40)
#define | CAN_FCR3_FACT4 ((uint8_t)0x01)
#define | CAN_FCR3_FACT5 ((uint8_t)0x10)
#define | CAN_FCR3_FSC40 ((uint8_t)0x02)
#define | CAN_FCR3_FSC41 ((uint8_t)0x04)
#define | CAN_FCR3_FSC50 ((uint8_t)0x20)
#define | CAN_FCR3_FSC51 ((uint8_t)0x40)
#define | CAN_FCR_RESET_VALUE ((uint8_t)0x00)
#define | CAN_FMR1_FMH0 ((uint8_t)0x02)
#define | CAN_FMR1_FMH1 ((uint8_t)0x08)
#define | CAN_FMR1_FMH2 ((uint8_t)0x20)
#define | CAN_FMR1_FMH3 ((uint8_t)0x80)
#define | CAN_FMR1_FML0 ((uint8_t)0x01)
#define | CAN_FMR1_FML1 ((uint8_t)0x04)
#define | CAN_FMR1_FML2 ((uint8_t)0x10)
#define | CAN_FMR1_FML3 ((uint8_t)0x40)
#define | CAN_FMR1_RESET_VALUE ((uint8_t)0x00)
#define | CAN_FMR2_FMH4 ((uint8_t)0x02)
#define | CAN_FMR2_FMH5 ((uint8_t)0x08)
#define | CAN_FMR2_FML4 ((uint8_t)0x01)
#define | CAN_FMR2_FML5 ((uint8_t)0x04)
#define | CAN_FMR2_RESET_VALUE ((uint8_t)0x00)
#define | CAN_IER_FFIE ((uint8_t)0x04)
#define | CAN_IER_FMPIE ((uint8_t)0x02)
#define | CAN_IER_FOVIE ((uint8_t)0x08)
#define | CAN_IER_RESET_VALUE ((uint8_t)0x00)
#define | CAN_IER_TMEIE ((uint8_t)0x01)
#define | CAN_IER_WKUIE ((uint8_t)0x80)
#define | CAN_MCR_ABOM ((uint8_t)0x40)
#define | CAN_MCR_AWUM ((uint8_t)0x20)
#define | CAN_MCR_INRQ ((uint8_t)0x01)
#define | CAN_MCR_NART ((uint8_t)0x10)
#define | CAN_MCR_RESET_VALUE ((uint8_t)0x02)
#define | CAN_MCR_RFLM ((uint8_t)0x08)
#define | CAN_MCR_SLEEP ((uint8_t)0x02)
#define | CAN_MCR_TTCM ((uint8_t)0x80)
#define | CAN_MCR_TXFP ((uint8_t)0x04)
#define | CAN_MCSR_ABRQ ((uint8_t)0x02)
#define | CAN_MCSR_ALST ((uint8_t)0x10)
#define | CAN_MCSR_RESET_VALUE ((uint8_t)0x00)
#define | CAN_MCSR_RQCP ((uint8_t)0x04)
#define | CAN_MCSR_TERR ((uint8_t)0x20)
#define | CAN_MCSR_TXOK ((uint8_t)0x08)
#define | CAN_MCSR_TXRQ ((uint8_t)0x01)
#define | CAN_MDLC_RESET_VALUE ((uint8_t)0x00)
#define | CAN_MDLCR_DLC ((uint8_t)0x0F)
#define | CAN_MDLCR_TGT ((uint8_t)0x80)
#define | CAN_MFMI_RESET_VALUE ((uint8_t)0x00)
#define | CAN_MIDR1_IDE ((uint8_t)0x40)
#define | CAN_MIDR1_RTR ((uint8_t)0x20)
#define | CAN_MSR_ERRI ((uint8_t)0x04)
#define | CAN_MSR_INAK ((uint8_t)0x01)
#define | CAN_MSR_RESET_VALUE ((uint8_t)0x02)
#define | CAN_MSR_RX ((uint8_t)0x20)
#define | CAN_MSR_SLAK ((uint8_t)0x02)
#define | CAN_MSR_TX ((uint8_t)0x10)
#define | CAN_MSR_WKUI ((uint8_t)0x08)
#define | CAN_PSR_PS0 ((uint8_t)0x01)
#define | CAN_PSR_PS1 ((uint8_t)0x02)
#define | CAN_PSR_PS2 ((uint8_t)0x04)
#define | CAN_PSR_RESET_VALUE ((uint8_t)0x00)
#define | CAN_RECR_REC0 ((uint8_t)0x01)
#define | CAN_RECR_REC1 ((uint8_t)0x02)
#define | CAN_RECR_REC2 ((uint8_t)0x04)
#define | CAN_RECR_REC3 ((uint8_t)0x08)
#define | CAN_RECR_REC4 ((uint8_t)0x10)
#define | CAN_RECR_REC5 ((uint8_t)0x20)
#define | CAN_RECR_REC6 ((uint8_t)0x40)
#define | CAN_RECR_REC7 ((uint8_t)0x80)
#define | CAN_RECR_RESET_VALUE ((uint8_t)0x00)
#define | CAN_RFR_FMP01 ((uint8_t)0x03)
#define | CAN_RFR_FOVR ((uint8_t)0x10)
#define | CAN_RFR_FULL ((uint8_t)0x08)
#define | CAN_RFR_RESET_VALUE ((uint8_t)0x00)
#define | CAN_RFR_RFOM ((uint8_t)0x20)
#define | CAN_TECR_RESET_VALUE ((uint8_t)0x00)
#define | CAN_TECR_TEC0 ((uint8_t)0x01)
#define | CAN_TECR_TEC1 ((uint8_t)0x02)
#define | CAN_TECR_TEC2 ((uint8_t)0x04)
#define | CAN_TECR_TEC3 ((uint8_t)0x08)
#define | CAN_TECR_TEC4 ((uint8_t)0x10)
#define | CAN_TECR_TEC5 ((uint8_t)0x20)
#define | CAN_TECR_TEC6 ((uint8_t)0x40)
#define | CAN_TECR_TEC7 ((uint8_t)0x80)
#define | CAN_TPR_CODE0 ((uint8_t)0x01)
#define | CAN_TPR_LOW0 ((uint8_t)0x20)
#define | CAN_TPR_LOW1 ((uint8_t)0x40)
#define | CAN_TPR_LOW2 ((uint8_t)0x80)
#define | CAN_TPR_RESET_VALUE ((uint8_t)0x0C)
#define | CAN_TPR_TME0 ((uint8_t)0x04)
#define | CAN_TPR_TME1 ((uint8_t)0x08)
#define | CAN_TPR_TME2 ((uint8_t)0x10)
#define | CAN_TSR_RESET_VALUE ((uint8_t)0x00)
#define | CAN_TSR_RQCP0 ((uint8_t)0x01)
#define | CAN_TSR_RQCP012 ((uint8_t)0x07)
#define | CAN_TSR_RQCP1 ((uint8_t)0x02)
#define | CAN_TSR_RQCP2 ((uint8_t)0x04)
#define | CAN_TSR_TXOK0 ((uint8_t)0x10)
#define | CAN_TSR_TXOK1 ((uint8_t)0x20)
#define | CAN_TSR_TXOK2 ((uint8_t)0x40)
#define | CCMR_TIxDirect_Set ((uint8_t)0x01)
#define | CFG ((CFG_TypeDef *) CFG_BaseAddress)
#define | CFG_BaseAddress 0x7F60
#define | CFG_GCR_AL ((uint8_t)0x02)
#define | CFG_GCR_RESET_VALUE ((uint8_t)0x00)
#define | CFG_GCR_SWD ((uint8_t)0x01)
#define | ChgBit(VAR, Place) ( (VAR) ^= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) )
#define | CLK ((CLK_TypeDef *) CLK_BaseAddress)
#define | CLK_BaseAddress 0x50C0
#define | CLK_CCOR_CCOBSY ((uint8_t)0x40)
#define | CLK_CCOR_CCOEN ((uint8_t)0x01)
#define | CLK_CCOR_CCORDY ((uint8_t)0x20)
#define | CLK_CCOR_CCOSEL ((uint8_t)0x1E)
#define | CLK_CCOR_RESET_VALUE ((uint8_t)0x00)
#define | CLK_CKDIVR_CPUDIV ((uint8_t)0x07)
#define | CLK_CKDIVR_HSIDIV ((uint8_t)0x18)
#define | CLK_CKDIVR_RESET_VALUE ((uint8_t)0x18)
#define | CLK_CMSR_CKM ((uint8_t)0xFF)
#define | CLK_CMSR_RESET_VALUE ((uint8_t)0xE1)
#define | CLK_CSSR_AUX ((uint8_t)0x02)
#define | CLK_CSSR_CSSD ((uint8_t)0x08)
#define | CLK_CSSR_CSSDIE ((uint8_t)0x04)
#define | CLK_CSSR_CSSEN ((uint8_t)0x01)
#define | CLK_CSSR_RESET_VALUE ((uint8_t)0x00)
#define | CLK_ECKR_HSEEN ((uint8_t)0x01)
#define | CLK_ECKR_HSERDY ((uint8_t)0x02)
#define | CLK_ECKR_RESET_VALUE ((uint8_t)0x00)
#define | CLK_HSITRIMR_HSITRIM ((uint8_t)0x07)
#define | CLK_HSITRIMR_RESET_VALUE ((uint8_t)0x00)
#define | CLK_ICKR_FHWU ((uint8_t)0x04)
#define | CLK_ICKR_HSIEN ((uint8_t)0x01)
#define | CLK_ICKR_HSIRDY ((uint8_t)0x02)
#define | CLK_ICKR_LSIEN ((uint8_t)0x08)
#define | CLK_ICKR_LSIRDY ((uint8_t)0x10)
#define | CLK_ICKR_RESET_VALUE ((uint8_t)0x01)
#define | CLK_ICKR_SWUAH ((uint8_t)0x20)
#define | CLK_PCKENR1_I2C ((uint8_t)0x01)
#define | CLK_PCKENR1_RESET_VALUE ((uint8_t)0xFF)
#define | CLK_PCKENR1_SPI ((uint8_t)0x02)
#define | CLK_PCKENR1_TIM1 ((uint8_t)0x80)
#define | CLK_PCKENR1_TIM2 ((uint8_t)0x20)
#define | CLK_PCKENR1_TIM3 ((uint8_t)0x40)
#define | CLK_PCKENR1_TIM4 ((uint8_t)0x10)
#define | CLK_PCKENR1_TIM5 ((uint8_t)0x20)
#define | CLK_PCKENR1_TIM6 ((uint8_t)0x10)
#define | CLK_PCKENR1_UART1 ((uint8_t)0x04)
#define | CLK_PCKENR1_UART2 ((uint8_t)0x08)
#define | CLK_PCKENR1_UART3 ((uint8_t)0x08)
#define | CLK_PCKENR2_ADC ((uint8_t)0x08)
#define | CLK_PCKENR2_AWU ((uint8_t)0x04)
#define | CLK_PCKENR2_CAN ((uint8_t)0x80)
#define | CLK_PCKENR2_RESET_VALUE ((uint8_t)0xFF)
#define | CLK_SWCR_RESET_VALUE ((uint8_t)0x00)
#define | CLK_SWCR_SWBSY ((uint8_t)0x01)
#define | CLK_SWCR_SWEN ((uint8_t)0x02)
#define | CLK_SWCR_SWIEN ((uint8_t)0x04)
#define | CLK_SWCR_SWIF ((uint8_t)0x08)
#define | CLK_SWIMCCR_RESET_VALUE ((uint8_t)0x00)
#define | CLK_SWIMCCR_SWIMDIV ((uint8_t)0x01)
#define | CLK_SWR_RESET_VALUE ((uint8_t)0xE1)
#define | CLK_SWR_SWI ((uint8_t)0xFF)
#define | ClrBit(VAR, Place) ( (VAR) &= (uint8_t)((uint8_t)((uint8_t)1<<(uint8_t)(Place))^(uint8_t)255) )
#define | CONST const
#define | CPU_CC_I1I0 ((uint8_t)0x28)
#define | disableInterrupts() __disable_interrupt()
#define | DM ((DM_TypeDef *) DM_BaseAddress)
#define | DM_BaseAddress 0x7F90
#define | EEPROM __eeprom
#define | enableInterrupts() __enable_interrupt()
#define | EXTI ((EXTI_TypeDef *) EXTI_BaseAddress)
#define | EXTI_BaseAddress 0x50A0
#define | EXTI_CR1_PAIS ((uint8_t)0x03)
#define | EXTI_CR1_PBIS ((uint8_t)0x0C)
#define | EXTI_CR1_PCIS ((uint8_t)0x30)
#define | EXTI_CR1_PDIS ((uint8_t)0xC0)
#define | EXTI_CR1_RESET_VALUE ((uint8_t)0x00)
#define | EXTI_CR2_PEIS ((uint8_t)0x03)
#define | EXTI_CR2_RESET_VALUE ((uint8_t)0x00)
#define | EXTI_CR2_TLIS ((uint8_t)0x04)
#define | FAR __far
#define | FLASH ((FLASH_TypeDef *) FLASH_BaseAddress)
#define | FLASH_BaseAddress 0x505A
#define | FLASH_CR1_AHALT ((uint8_t)0x04)
#define | FLASH_CR1_FIX ((uint8_t)0x01)
#define | FLASH_CR1_HALT ((uint8_t)0x08)
#define | FLASH_CR1_IE ((uint8_t)0x02)
#define | FLASH_CR1_RESET_VALUE ((uint8_t)0x00)
#define | FLASH_CR2_ERASE ((uint8_t)0x20)
#define | FLASH_CR2_FPRG ((uint8_t)0x10)
#define | FLASH_CR2_OPT ((uint8_t)0x80)
#define | FLASH_CR2_PRG ((uint8_t)0x01)
#define | FLASH_CR2_RESET_VALUE ((uint8_t)0x00)
#define | FLASH_CR2_WPRG ((uint8_t)0x40)
#define | FLASH_DUKR_DUK ((uint8_t)0xFF)
#define | FLASH_DUKR_RESET_VALUE ((uint8_t)0x00)
#define | FLASH_IAPSR_DUL ((uint8_t)0x08)
#define | FLASH_IAPSR_EOP ((uint8_t)0x04)
#define | FLASH_IAPSR_HVOFF ((uint8_t)0x40)
#define | FLASH_IAPSR_PUL ((uint8_t)0x02)
#define | FLASH_IAPSR_RESET_VALUE ((uint8_t)0x40)
#define | FLASH_IAPSR_WR_PG_DIS ((uint8_t)0x01)
#define | FLASH_NCR2_NERASE ((uint8_t)0x20)
#define | FLASH_NCR2_NFPRG ((uint8_t)0x10)
#define | FLASH_NCR2_NOPT ((uint8_t)0x80)
#define | FLASH_NCR2_NPRG ((uint8_t)0x01)
#define | FLASH_NCR2_NWPRG ((uint8_t)0x40)
#define | FLASH_NCR2_RESET_VALUE ((uint8_t)0xFF)
#define | FLASH_PUKR_PUK ((uint8_t)0xFF)
#define | FLASH_PUKR_RESET_VALUE ((uint8_t)0x00)
#define | GPIO_CR1_RESET_VALUE ((uint8_t)0x00)
#define | GPIO_CR2_RESET_VALUE ((uint8_t)0x00)
#define | GPIO_DDR_RESET_VALUE ((uint8_t)0x00)
#define | GPIO_ODR_RESET_VALUE ((uint8_t)0x00)
#define | GPIOA ((GPIO_TypeDef *) GPIOA_BaseAddress)
#define | GPIOA_BaseAddress 0x5000
#define | GPIOB ((GPIO_TypeDef *) GPIOB_BaseAddress)
#define | GPIOB_BaseAddress 0x5005
#define | GPIOC ((GPIO_TypeDef *) GPIOC_BaseAddress)
#define | GPIOC_BaseAddress 0x500A
#define | GPIOD ((GPIO_TypeDef *) GPIOD_BaseAddress)
#define | GPIOD_BaseAddress 0x500F
#define | GPIOE ((GPIO_TypeDef *) GPIOE_BaseAddress)
#define | GPIOE_BaseAddress 0x5014
#define | GPIOF ((GPIO_TypeDef *) GPIOF_BaseAddress)
#define | GPIOF_BaseAddress 0x5019
#define | GPIOG_BaseAddress 0x501E
#define | GPIOH_BaseAddress 0x5023
#define | GPIOI_BaseAddress 0x5028
#define | halt() __halt()
#define | HSE_VALUE ((uint32_t)16000000)
In the following line adjust the value of External High Speed oscillator (HSE) used in your application.
#define | HSI_VALUE ((uint32_t)16000000)
Definition of Device on-chip RC oscillator frequencies.
#define | I2C ((I2C_TypeDef *) I2C_BaseAddress)
#define | I2C_BaseAddress 0x5210
#define | I2C_CCRH_CCR ((uint8_t)0x0F)
#define | I2C_CCRH_DUTY ((uint8_t)0x40)
#define | I2C_CCRH_FS ((uint8_t)0x80)
#define | I2C_CCRH_RESET_VALUE ((uint8_t)0x00)
#define | I2C_CCRL_CCR ((uint8_t)0xFF)
#define | I2C_CCRL_RESET_VALUE ((uint8_t)0x00)
#define | I2C_CR1_ENGC ((uint8_t)0x40)
#define | I2C_CR1_NOSTRETCH ((uint8_t)0x80)
#define | I2C_CR1_PE ((uint8_t)0x01)
#define | I2C_CR1_RESET_VALUE ((uint8_t)0x00)
#define | I2C_CR2_ACK ((uint8_t)0x04)
#define | I2C_CR2_POS ((uint8_t)0x08)
#define | I2C_CR2_RESET_VALUE ((uint8_t)0x00)
#define | I2C_CR2_START ((uint8_t)0x01)
#define | I2C_CR2_STOP ((uint8_t)0x02)
#define | I2C_CR2_SWRST ((uint8_t)0x80)
#define | I2C_DR_DR ((uint8_t)0xFF)
#define | I2C_DR_RESET_VALUE ((uint8_t)0x00)
#define | I2C_FREQR_FREQ ((uint8_t)0x3F)
#define | I2C_FREQR_RESET_VALUE ((uint8_t)0x00)
#define | I2C_ITR_ITBUFEN ((uint8_t)0x04)
#define | I2C_ITR_ITERREN ((uint8_t)0x01)
#define | I2C_ITR_ITEVTEN ((uint8_t)0x02)
#define | I2C_ITR_RESET_VALUE ((uint8_t)0x00)
#define | I2C_OARH_ADD ((uint8_t)0x06)
#define | I2C_OARH_ADDCONF ((uint8_t)0x40)
#define | I2C_OARH_ADDMODE ((uint8_t)0x80)
#define | I2C_OARH_RESET_VALUE ((uint8_t)0x00)
#define | I2C_OARL_ADD ((uint8_t)0xFE)
#define | I2C_OARL_ADD0 ((uint8_t)0x01)
#define | I2C_OARL_RESET_VALUE ((uint8_t)0x00)
#define | I2C_SR1_ADD10 ((uint8_t)0x08)
#define | I2C_SR1_ADDR ((uint8_t)0x02)
#define | I2C_SR1_BTF ((uint8_t)0x04)
#define | I2C_SR1_RESET_VALUE ((uint8_t)0x00)
#define | I2C_SR1_RXNE ((uint8_t)0x40)
#define | I2C_SR1_SB ((uint8_t)0x01)
#define | I2C_SR1_STOPF ((uint8_t)0x10)
#define | I2C_SR1_TXE ((uint8_t)0x80)
#define | I2C_SR2_AF ((uint8_t)0x04)
#define | I2C_SR2_ARLO ((uint8_t)0x02)
#define | I2C_SR2_BERR ((uint8_t)0x01)
#define | I2C_SR2_OVR ((uint8_t)0x08)
#define | I2C_SR2_RESET_VALUE ((uint8_t)0x00)
#define | I2C_SR2_WUFH ((uint8_t)0x20)
#define | I2C_SR3_BUSY ((uint8_t)0x02)
#define | I2C_SR3_GENCALL ((uint8_t)0x10)
#define | I2C_SR3_MSL ((uint8_t)0x01)
#define | I2C_SR3_RESET_VALUE ((uint8_t)0x00)
#define | I2C_SR3_TRA ((uint8_t)0x04)
#define | I2C_TRISER_RESET_VALUE ((uint8_t)0x02)
#define | I2C_TRISER_TRISE ((uint8_t)0x3F)
#define | IN_RAM(a) a
#define | IS_FUNCTIONALSTATE_OK(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
#define | IS_STATE_VALUE_OK(SensitivityValue)
#define | ITC ((ITC_TypeDef *) ITC_BaseAddress)
#define | ITC_BaseAddress 0x7F70
#define | ITC_SPRX_RESET_VALUE ((uint8_t)0xFF)
#define | IWDG ((IWDG_TypeDef *) IWDG_BaseAddress)
#define | IWDG_BaseAddress 0x50E0
#define | IWDG_PR_RESET_VALUE ((uint8_t)0x00)
#define | IWDG_RLR_RESET_VALUE ((uint8_t)0xFF)
#define | LSI_VALUE ((uint32_t)128000)
#define | MemoryAddressCast uint32_t
#define | MskBit(Dest, Msk, Src) ( (Dest) = ((Msk) & (Src)) | ((~(Msk)) & (Dest)) )
#define | NEAR __near
#define | nop() __no_operation()
#define | OPT ((OPT_TypeDef *) OPT_BaseAddress)
#define | OPT_BaseAddress 0x4800
#define | PointerAttr FAR
#define | rim() __enable_interrupt()
#define | RST ((RST_TypeDef *) RST_BaseAddress)
#define | RST_BaseAddress 0x50B3
#define | RST_SR_EMCF ((uint8_t)0x10)
#define | RST_SR_ILLOPF ((uint8_t)0x04)
#define | RST_SR_IWDGF ((uint8_t)0x02)
#define | RST_SR_SWIMF ((uint8_t)0x08)
#define | RST_SR_WWDGF ((uint8_t)0x01)
#define | S16_MAX (32767)
#define | S16_MIN (-32768)
#define | S32_MAX (2147483647)
#define | S32_MIN (-2147483648uL)
#define | S8_MAX (127)
#define | S8_MIN (-128)
#define | SetBit(VAR, Place) ( (VAR) |= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) )
#define | sim() __disable_interrupt()
#define | SPI ((SPI_TypeDef *) SPI_BaseAddress)
#define | SPI_BaseAddress 0x5200
#define | SPI_CR1_BR ((uint8_t)0x38)
#define | SPI_CR1_CPHA ((uint8_t)0x01)
#define | SPI_CR1_CPOL ((uint8_t)0x02)
#define | SPI_CR1_LSBFIRST ((uint8_t)0x80)
#define | SPI_CR1_MSTR ((uint8_t)0x04)
#define | SPI_CR1_RESET_VALUE ((uint8_t)0x00)
#define | SPI_CR1_SPE ((uint8_t)0x40)
#define | SPI_CR2_BDM ((uint8_t)0x80)
#define | SPI_CR2_BDOE ((uint8_t)0x40)
#define | SPI_CR2_CRCEN ((uint8_t)0x20)
#define | SPI_CR2_CRCNEXT ((uint8_t)0x10)
#define | SPI_CR2_RESET_VALUE ((uint8_t)0x00)
#define | SPI_CR2_RXONLY ((uint8_t)0x04)
#define | SPI_CR2_SSI ((uint8_t)0x01)
#define | SPI_CR2_SSM ((uint8_t)0x02)
#define | SPI_CRCPR_RESET_VALUE ((uint8_t)0x07)
#define | SPI_DR_RESET_VALUE ((uint8_t)0x00)
#define | SPI_ICR_ERRIE ((uint8_t)0x20)
#define | SPI_ICR_RESET_VALUE ((uint8_t)0x00)
#define | SPI_ICR_RXEI ((uint8_t)0x40)
#define | SPI_ICR_TXEI ((uint8_t)0x80)
#define | SPI_ICR_WKIE ((uint8_t)0x10)
#define | SPI_RXCRCR_RESET_VALUE ((uint8_t)0x00)
#define | SPI_SR_BSY ((uint8_t)0x80)
#define | SPI_SR_CRCERR ((uint8_t)0x10)
#define | SPI_SR_MODF ((uint8_t)0x20)
#define | SPI_SR_OVR ((uint8_t)0x40)
#define | SPI_SR_RESET_VALUE ((uint8_t)0x02)
#define | SPI_SR_RXNE ((uint8_t)0x01)
#define | SPI_SR_TXE ((uint8_t)0x02)
#define | SPI_SR_WKUP ((uint8_t)0x08)
#define | SPI_TXCRCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM1 ((TIM1_TypeDef *) TIM1_BaseAddress)
#define | TIM1_ARRH_ARR ((uint8_t)0xFF)
#define | TIM1_ARRH_RESET_VALUE ((uint8_t)0xFF)
#define | TIM1_ARRL_ARR ((uint8_t)0xFF)
#define | TIM1_ARRL_RESET_VALUE ((uint8_t)0xFF)
#define | TIM1_BaseAddress 0x5250
#define | TIM1_BKR_AOE ((uint8_t)0x40)
#define | TIM1_BKR_BKE ((uint8_t)0x10)
#define | TIM1_BKR_BKP ((uint8_t)0x20)
#define | TIM1_BKR_LOCK ((uint8_t)0x03)
#define | TIM1_BKR_MOE ((uint8_t)0x80)
#define | TIM1_BKR_OSSI ((uint8_t)0x04)
#define | TIM1_BKR_OSSR ((uint8_t)0x08)
#define | TIM1_BKR_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCER1_CC1E ((uint8_t)0x01)
#define | TIM1_CCER1_CC1NE ((uint8_t)0x04)
#define | TIM1_CCER1_CC1NP ((uint8_t)0x08)
#define | TIM1_CCER1_CC1P ((uint8_t)0x02)
#define | TIM1_CCER1_CC2E ((uint8_t)0x10)
#define | TIM1_CCER1_CC2NE ((uint8_t)0x40)
#define | TIM1_CCER1_CC2NP ((uint8_t)0x80)
#define | TIM1_CCER1_CC2P ((uint8_t)0x20)
#define | TIM1_CCER1_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCER2_CC3E ((uint8_t)0x01)
#define | TIM1_CCER2_CC3NE ((uint8_t)0x04)
#define | TIM1_CCER2_CC3NP ((uint8_t)0x08)
#define | TIM1_CCER2_CC3P ((uint8_t)0x02)
#define | TIM1_CCER2_CC4E ((uint8_t)0x10)
#define | TIM1_CCER2_CC4P ((uint8_t)0x20)
#define | TIM1_CCER2_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCMR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCMR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCMR3_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCMR4_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCMR_CCxS ((uint8_t)0x03)
#define | TIM1_CCMR_ICxF ((uint8_t)0xF0)
#define | TIM1_CCMR_ICxPSC ((uint8_t)0x0C)
#define | TIM1_CCMR_OCM ((uint8_t)0x70)
#define | TIM1_CCMR_OCxFE ((uint8_t)0x04)
#define | TIM1_CCMR_OCxPE ((uint8_t)0x08)
#define | TIM1_CCR1H_CCR1 ((uint8_t)0xFF)
#define | TIM1_CCR1H_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCR1L_CCR1 ((uint8_t)0xFF)
#define | TIM1_CCR1L_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCR2H_CCR2 ((uint8_t)0xFF)
#define | TIM1_CCR2H_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCR2L_CCR2 ((uint8_t)0xFF)
#define | TIM1_CCR2L_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCR3H_CCR3 ((uint8_t)0xFF)
#define | TIM1_CCR3H_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCR3L_CCR3 ((uint8_t)0xFF)
#define | TIM1_CCR3L_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCR4H_CCR4 ((uint8_t)0xFF)
#define | TIM1_CCR4H_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCR4L_CCR4 ((uint8_t)0xFF)
#define | TIM1_CCR4L_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CNTRH_CNT ((uint8_t)0xFF)
#define | TIM1_CNTRH_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CNTRL_CNT ((uint8_t)0xFF)
#define | TIM1_CNTRL_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CR1_ARPE ((uint8_t)0x80)
#define | TIM1_CR1_CEN ((uint8_t)0x01)
#define | TIM1_CR1_CMS ((uint8_t)0x60)
#define | TIM1_CR1_DIR ((uint8_t)0x10)
#define | TIM1_CR1_OPM ((uint8_t)0x08)
#define | TIM1_CR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CR1_UDIS ((uint8_t)0x02)
#define | TIM1_CR1_URS ((uint8_t)0x04)
#define | TIM1_CR2_CCPC ((uint8_t)0x01)
#define | TIM1_CR2_COMS ((uint8_t)0x04)
#define | TIM1_CR2_MMS ((uint8_t)0x70)
#define | TIM1_CR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CR2_TI1S ((uint8_t)0x80)
#define | TIM1_DTR_DTG ((uint8_t)0xFF)
#define | TIM1_DTR_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_EGR_BG ((uint8_t)0x80)
#define | TIM1_EGR_CC1G ((uint8_t)0x02)
#define | TIM1_EGR_CC2G ((uint8_t)0x04)
#define | TIM1_EGR_CC3G ((uint8_t)0x08)
#define | TIM1_EGR_CC4G ((uint8_t)0x10)
#define | TIM1_EGR_COMG ((uint8_t)0x20)
#define | TIM1_EGR_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_EGR_TG ((uint8_t)0x40)
#define | TIM1_EGR_UG ((uint8_t)0x01)
#define | TIM1_ETR_ECE ((uint8_t)0x40)
#define | TIM1_ETR_ETF ((uint8_t)0x0F)
#define | TIM1_ETR_ETP ((uint8_t)0x80)
#define | TIM1_ETR_ETPS ((uint8_t)0x30)
#define | TIM1_ETR_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_IER_BIE ((uint8_t)0x80)
#define | TIM1_IER_CC1IE ((uint8_t)0x02)
#define | TIM1_IER_CC2IE ((uint8_t)0x04)
#define | TIM1_IER_CC3IE ((uint8_t)0x08)
#define | TIM1_IER_CC4IE ((uint8_t)0x10)
#define | TIM1_IER_COMIE ((uint8_t)0x20)
#define | TIM1_IER_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_IER_TIE ((uint8_t)0x40)
#define | TIM1_IER_UIE ((uint8_t)0x01)
#define | TIM1_OISR_OIS1 ((uint8_t)0x01)
#define | TIM1_OISR_OIS1N ((uint8_t)0x02)
#define | TIM1_OISR_OIS2 ((uint8_t)0x04)
#define | TIM1_OISR_OIS2N ((uint8_t)0x08)
#define | TIM1_OISR_OIS3 ((uint8_t)0x10)
#define | TIM1_OISR_OIS3N ((uint8_t)0x20)
#define | TIM1_OISR_OIS4 ((uint8_t)0x40)
#define | TIM1_OISR_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_PSCH_PSC ((uint8_t)0xFF)
#define | TIM1_PSCL_PSC ((uint8_t)0xFF)
#define | TIM1_PSCRH_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_PSCRL_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_RCR_REP ((uint8_t)0xFF)
#define | TIM1_RCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_SMCR_MSM ((uint8_t)0x80)
#define | TIM1_SMCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_SMCR_SMS ((uint8_t)0x07)
#define | TIM1_SMCR_TS ((uint8_t)0x70)
#define | TIM1_SR1_BIF ((uint8_t)0x80)
#define | TIM1_SR1_CC1IF ((uint8_t)0x02)
#define | TIM1_SR1_CC2IF ((uint8_t)0x04)
#define | TIM1_SR1_CC3IF ((uint8_t)0x08)
#define | TIM1_SR1_CC4IF ((uint8_t)0x10)
#define | TIM1_SR1_COMIF ((uint8_t)0x20)
#define | TIM1_SR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_SR1_TIF ((uint8_t)0x40)
#define | TIM1_SR1_UIF ((uint8_t)0x01)
#define | TIM1_SR2_CC1OF ((uint8_t)0x02)
#define | TIM1_SR2_CC2OF ((uint8_t)0x04)
#define | TIM1_SR2_CC3OF ((uint8_t)0x08)
#define | TIM1_SR2_CC4OF ((uint8_t)0x10)
#define | TIM1_SR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_ARRH_ARR ((uint8_t)0xFF)
#define | TIM2_ARRH_RESET_VALUE ((uint8_t)0xFF)
#define | TIM2_ARRL_ARR ((uint8_t)0xFF)
#define | TIM2_ARRL_RESET_VALUE ((uint8_t)0xFF)
#define | TIM2_BaseAddress 0x5300
#define | TIM2_CCER1_CC1E ((uint8_t)0x01)
#define | TIM2_CCER1_CC1P ((uint8_t)0x02)
#define | TIM2_CCER1_CC2E ((uint8_t)0x10)
#define | TIM2_CCER1_CC2P ((uint8_t)0x20)
#define | TIM2_CCER1_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCER2_CC3E ((uint8_t)0x01)
#define | TIM2_CCER2_CC3P ((uint8_t)0x02)
#define | TIM2_CCER2_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCMR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCMR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCMR3_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCMR_CCxS ((uint8_t)0x03)
#define | TIM2_CCMR_ICxF ((uint8_t)0xF0)
#define | TIM2_CCMR_ICxPSC ((uint8_t)0x0C)
#define | TIM2_CCMR_OCM ((uint8_t)0x70)
#define | TIM2_CCMR_OCxPE ((uint8_t)0x08)
#define | TIM2_CCR1H_CCR1 ((uint8_t)0xFF)
#define | TIM2_CCR1H_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCR1L_CCR1 ((uint8_t)0xFF)
#define | TIM2_CCR1L_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCR2H_CCR2 ((uint8_t)0xFF)
#define | TIM2_CCR2H_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCR2L_CCR2 ((uint8_t)0xFF)
#define | TIM2_CCR2L_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCR3H_CCR3 ((uint8_t)0xFF)
#define | TIM2_CCR3H_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCR3L_CCR3 ((uint8_t)0xFF)
#define | TIM2_CCR3L_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CNTRH_CNT ((uint8_t)0xFF)
#define | TIM2_CNTRH_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CNTRL_CNT ((uint8_t)0xFF)
#define | TIM2_CNTRL_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CR1_ARPE ((uint8_t)0x80)
#define | TIM2_CR1_CEN ((uint8_t)0x01)
#define | TIM2_CR1_OPM ((uint8_t)0x08)
#define | TIM2_CR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CR1_UDIS ((uint8_t)0x02)
#define | TIM2_CR1_URS ((uint8_t)0x04)
#define | TIM2_EGR_CC1G ((uint8_t)0x02)
#define | TIM2_EGR_CC2G ((uint8_t)0x04)
#define | TIM2_EGR_CC3G ((uint8_t)0x08)
#define | TIM2_EGR_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_EGR_UG ((uint8_t)0x01)
#define | TIM2_IER_CC1IE ((uint8_t)0x02)
#define | TIM2_IER_CC2IE ((uint8_t)0x04)
#define | TIM2_IER_CC3IE ((uint8_t)0x08)
#define | TIM2_IER_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_IER_UIE ((uint8_t)0x01)
#define | TIM2_PSCR_PSC ((uint8_t)0xFF)
#define | TIM2_PSCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_SR1_CC1IF ((uint8_t)0x02)
#define | TIM2_SR1_CC2IF ((uint8_t)0x04)
#define | TIM2_SR1_CC3IF ((uint8_t)0x08)
#define | TIM2_SR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_SR1_UIF ((uint8_t)0x01)
#define | TIM2_SR2_CC1OF ((uint8_t)0x02)
#define | TIM2_SR2_CC2OF ((uint8_t)0x04)
#define | TIM2_SR2_CC3OF ((uint8_t)0x08)
#define | TIM2_SR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_ARRH_ARR ((uint8_t)0xFF)
#define | TIM3_ARRH_RESET_VALUE ((uint8_t)0xFF)
#define | TIM3_ARRL_ARR ((uint8_t)0xFF)
#define | TIM3_ARRL_RESET_VALUE ((uint8_t)0xFF)
#define | TIM3_BaseAddress 0x5320
#define | TIM3_CCER1_CC1E ((uint8_t)0x01)
#define | TIM3_CCER1_CC1P ((uint8_t)0x02)
#define | TIM3_CCER1_CC2E ((uint8_t)0x10)
#define | TIM3_CCER1_CC2P ((uint8_t)0x20)
#define | TIM3_CCER1_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CCMR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CCMR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CCMR_CCxS ((uint8_t)0x03)
#define | TIM3_CCMR_ICxF ((uint8_t)0xF0)
#define | TIM3_CCMR_ICxPSC ((uint8_t)0x0C)
#define | TIM3_CCMR_OCM ((uint8_t)0x70)
#define | TIM3_CCMR_OCxPE ((uint8_t)0x08)
#define | TIM3_CCR1H_CCR1 ((uint8_t)0xFF)
#define | TIM3_CCR1H_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CCR1L_CCR1 ((uint8_t)0xFF)
#define | TIM3_CCR1L_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CCR2H_CCR2 ((uint8_t)0xFF)
#define | TIM3_CCR2H_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CCR2L_CCR2 ((uint8_t)0xFF)
#define | TIM3_CCR2L_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CNTRH_CNT ((uint8_t)0xFF)
#define | TIM3_CNTRH_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CNTRL_CNT ((uint8_t)0xFF)
#define | TIM3_CNTRL_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CR1_ARPE ((uint8_t)0x80)
#define | TIM3_CR1_CEN ((uint8_t)0x01)
#define | TIM3_CR1_OPM ((uint8_t)0x08)
#define | TIM3_CR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CR1_UDIS ((uint8_t)0x02)
#define | TIM3_CR1_URS ((uint8_t)0x04)
#define | TIM3_EGR_CC1G ((uint8_t)0x02)
#define | TIM3_EGR_CC2G ((uint8_t)0x04)
#define | TIM3_EGR_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_EGR_UG ((uint8_t)0x01)
#define | TIM3_IER_CC1IE ((uint8_t)0x02)
#define | TIM3_IER_CC2IE ((uint8_t)0x04)
#define | TIM3_IER_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_IER_UIE ((uint8_t)0x01)
#define | TIM3_PSCR_PSC ((uint8_t)0xFF)
#define | TIM3_PSCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_SR1_CC1IF ((uint8_t)0x02)
#define | TIM3_SR1_CC2IF ((uint8_t)0x04)
#define | TIM3_SR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_SR1_UIF ((uint8_t)0x01)
#define | TIM3_SR2_CC1OF ((uint8_t)0x02)
#define | TIM3_SR2_CC2OF ((uint8_t)0x04)
#define | TIM3_SR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM4_ARR_ARR ((uint8_t)0xFF)
#define | TIM4_ARR_RESET_VALUE ((uint8_t)0xFF)
#define | TIM4_BaseAddress 0x5340
#define | TIM4_CNTR_CNT ((uint8_t)0xFF)
#define | TIM4_CNTR_RESET_VALUE ((uint8_t)0x00)
#define | TIM4_CR1_ARPE ((uint8_t)0x80)
#define | TIM4_CR1_CEN ((uint8_t)0x01)
#define | TIM4_CR1_OPM ((uint8_t)0x08)
#define | TIM4_CR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM4_CR1_UDIS ((uint8_t)0x02)
#define | TIM4_CR1_URS ((uint8_t)0x04)
#define | TIM4_EGR_RESET_VALUE ((uint8_t)0x00)
#define | TIM4_EGR_UG ((uint8_t)0x01)
#define | TIM4_IER_RESET_VALUE ((uint8_t)0x00)
#define | TIM4_IER_UIE ((uint8_t)0x01)
#define | TIM4_PSCR_PSC ((uint8_t)0x07)
#define | TIM4_PSCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM4_SR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM4_SR1_UIF ((uint8_t)0x01)
#define | TIM5_ARRH_ARR ((uint8_t)0xFF)
#define | TIM5_ARRH_RESET_VALUE ((uint8_t)0xFF)
#define | TIM5_ARRL_ARR ((uint8_t)0xFF)
#define | TIM5_ARRL_RESET_VALUE ((uint8_t)0xFF)
#define | TIM5_BaseAddress 0x5300
#define | TIM5_CCER1_CC1E ((uint8_t)0x01)
#define | TIM5_CCER1_CC1P ((uint8_t)0x02)
#define | TIM5_CCER1_CC2E ((uint8_t)0x10)
#define | TIM5_CCER1_CC2P ((uint8_t)0x20)
#define | TIM5_CCER1_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCER2_CC3E ((uint8_t)0x01)
#define | TIM5_CCER2_CC3P ((uint8_t)0x02)
#define | TIM5_CCER2_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCMR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCMR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCMR3_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCMR_CCxS ((uint8_t)0x03)
#define | TIM5_CCMR_ICxF ((uint8_t)0xF0)
#define | TIM5_CCMR_ICxPSC ((uint8_t)0x0C)
#define | TIM5_CCMR_OCM ((uint8_t)0x70)
#define | TIM5_CCMR_OCxPE ((uint8_t)0x08)
#define | TIM5_CCMR_TIxDirect_Set ((uint8_t)0x01)
#define | TIM5_CCR1H_CCR1 ((uint8_t)0xFF)
#define | TIM5_CCR1H_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCR1L_CCR1 ((uint8_t)0xFF)
#define | TIM5_CCR1L_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCR2H_CCR2 ((uint8_t)0xFF)
#define | TIM5_CCR2H_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCR2L_CCR2 ((uint8_t)0xFF)
#define | TIM5_CCR2L_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCR3H_CCR3 ((uint8_t)0xFF)
#define | TIM5_CCR3H_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCR3L_CCR3 ((uint8_t)0xFF)
#define | TIM5_CCR3L_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CNTRH_CNT ((uint8_t)0xFF)
#define | TIM5_CNTRH_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CNTRL_CNT ((uint8_t)0xFF)
#define | TIM5_CNTRL_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CR1_ARPE ((uint8_t)0x80)
#define | TIM5_CR1_CEN ((uint8_t)0x01)
#define | TIM5_CR1_OPM ((uint8_t)0x08)
#define | TIM5_CR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CR1_UDIS ((uint8_t)0x02)
#define | TIM5_CR1_URS ((uint8_t)0x04)
#define | TIM5_CR2_MMS ((uint8_t)0x70)
#define | TIM5_CR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CR2_TI1S ((uint8_t)0x80)
#define | TIM5_EGR_CC1G ((uint8_t)0x02)
#define | TIM5_EGR_CC2G ((uint8_t)0x04)
#define | TIM5_EGR_CC3G ((uint8_t)0x08)
#define | TIM5_EGR_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_EGR_TG ((uint8_t)0x40)
#define | TIM5_EGR_UG ((uint8_t)0x01)
#define | TIM5_IER_CC1IE ((uint8_t)0x02)
#define | TIM5_IER_CC2IE ((uint8_t)0x04)
#define | TIM5_IER_CC3IE ((uint8_t)0x08)
#define | TIM5_IER_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_IER_TIE ((uint8_t)0x40)
#define | TIM5_IER_UIE ((uint8_t)0x01)
#define | TIM5_PSCR_PSC ((uint8_t)0xFF)
#define | TIM5_PSCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_SMCR_MSM ((uint8_t)0x80)
#define | TIM5_SMCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_SMCR_SMS ((uint8_t)0x07)
#define | TIM5_SMCR_TS ((uint8_t)0x70)
#define | TIM5_SR1_CC1IF ((uint8_t)0x02)
#define | TIM5_SR1_CC2IF ((uint8_t)0x04)
#define | TIM5_SR1_CC3IF ((uint8_t)0x08)
#define | TIM5_SR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_SR1_TIF ((uint8_t)0x40)
#define | TIM5_SR1_UIF ((uint8_t)0x01)
#define | TIM5_SR2_CC1OF ((uint8_t)0x02)
#define | TIM5_SR2_CC2OF ((uint8_t)0x04)
#define | TIM5_SR2_CC3OF ((uint8_t)0x08)
#define | TIM5_SR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM6_ARR_ARR ((uint8_t)0xFF)
#define | TIM6_ARR_RESET_VALUE ((uint8_t)0xFF)
#define | TIM6_BaseAddress 0x5340
#define | TIM6_CNTR_CNT ((uint8_t)0xFF)
#define | TIM6_CNTR_RESET_VALUE ((uint8_t)0x00)
#define | TIM6_CR1_ARPE ((uint8_t)0x80)
#define | TIM6_CR1_CEN ((uint8_t)0x01)
#define | TIM6_CR1_OPM ((uint8_t)0x08)
#define | TIM6_CR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM6_CR1_UDIS ((uint8_t)0x02)
#define | TIM6_CR1_URS ((uint8_t)0x04)
#define | TIM6_CR2_MMS ((uint8_t)0x70)
#define | TIM6_CR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM6_EGR_RESET_VALUE ((uint8_t)0x00)
#define | TIM6_EGR_TG ((uint8_t)0x40)
#define | TIM6_EGR_UG ((uint8_t)0x01)
#define | TIM6_IER_RESET_VALUE ((uint8_t)0x00)
#define | TIM6_IER_TIE ((uint8_t)0x40)
#define | TIM6_IER_UIE ((uint8_t)0x01)
#define | TIM6_PSCR_PSC ((uint8_t)0x07)
#define | TIM6_PSCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM6_SMCR_MSM ((uint8_t)0x80)
#define | TIM6_SMCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM6_SMCR_SMS ((uint8_t)0x07)
#define | TIM6_SMCR_TS ((uint8_t)0x70)
#define | TIM6_SR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM6_SR1_TIF ((uint8_t)0x40)
#define | TIM6_SR1_UIF ((uint8_t)0x01)
#define | TINY __tiny
#define | trap() __trap()
#define | U16_MAX (65535u)
#define | U32_MAX (4294967295uL)
#define | U8_MAX (255)
#define | UART1_BaseAddress 0x5230
#define | UART1_BRR1_DIVM ((uint8_t)0xFF)
#define | UART1_BRR1_RESET_VALUE ((uint8_t)0x00)
#define | UART1_BRR2_DIVF ((uint8_t)0x0F)
#define | UART1_BRR2_DIVM ((uint8_t)0xF0)
#define | UART1_BRR2_RESET_VALUE ((uint8_t)0x00)
#define | UART1_CR1_M ((uint8_t)0x10)
#define | UART1_CR1_PCEN ((uint8_t)0x04)
#define | UART1_CR1_PIEN ((uint8_t)0x01)
#define | UART1_CR1_PS ((uint8_t)0x02)
#define | UART1_CR1_R8 ((uint8_t)0x80)
#define | UART1_CR1_RESET_VALUE ((uint8_t)0x00)
#define | UART1_CR1_T8 ((uint8_t)0x40)
#define | UART1_CR1_UARTD ((uint8_t)0x20)
#define | UART1_CR1_WAKE ((uint8_t)0x08)
#define | UART1_CR2_ILIEN ((uint8_t)0x10)
#define | UART1_CR2_REN ((uint8_t)0x04)
#define | UART1_CR2_RESET_VALUE ((uint8_t)0x00)
#define | UART1_CR2_RIEN ((uint8_t)0x20)
#define | UART1_CR2_RWU ((uint8_t)0x02)
#define | UART1_CR2_SBK ((uint8_t)0x01)
#define | UART1_CR2_TCIEN ((uint8_t)0x40)
#define | UART1_CR2_TEN ((uint8_t)0x08)
#define | UART1_CR2_TIEN ((uint8_t)0x80)
#define | UART1_CR3_CKEN ((uint8_t)0x08)
#define | UART1_CR3_CPHA ((uint8_t)0x02)
#define | UART1_CR3_CPOL ((uint8_t)0x04)
#define | UART1_CR3_LBCL ((uint8_t)0x01)
#define | UART1_CR3_LINEN ((uint8_t)0x40)
#define | UART1_CR3_RESET_VALUE ((uint8_t)0x00)
#define | UART1_CR3_STOP ((uint8_t)0x30)
#define | UART1_CR4_ADD ((uint8_t)0x0F)
#define | UART1_CR4_LBDF ((uint8_t)0x10)
#define | UART1_CR4_LBDIEN ((uint8_t)0x40)
#define | UART1_CR4_LBDL ((uint8_t)0x20)
#define | UART1_CR4_RESET_VALUE ((uint8_t)0x00)
#define | UART1_CR5_HDSEL ((uint8_t)0x08)
#define | UART1_CR5_IREN ((uint8_t)0x02)
#define | UART1_CR5_IRLP ((uint8_t)0x04)
#define | UART1_CR5_NACK ((uint8_t)0x10)
#define | UART1_CR5_RESET_VALUE ((uint8_t)0x00)
#define | UART1_CR5_SCEN ((uint8_t)0x20)
#define | UART1_GTR_RESET_VALUE ((uint8_t)0x00)
#define | UART1_PSCR_RESET_VALUE ((uint8_t)0x00)
#define | UART1_SR_FE ((uint8_t)0x02)
#define | UART1_SR_IDLE ((uint8_t)0x10)
#define | UART1_SR_NF ((uint8_t)0x04)
#define | UART1_SR_OR ((uint8_t)0x08)
#define | UART1_SR_PE ((uint8_t)0x01)
#define | UART1_SR_RESET_VALUE ((uint8_t)0xC0)
#define | UART1_SR_RXNE ((uint8_t)0x20)
#define | UART1_SR_TC ((uint8_t)0x40)
#define | UART1_SR_TXE ((uint8_t)0x80)
#define | UART2_BaseAddress 0x5240
#define | UART2_BRR1_DIVM ((uint8_t)0xFF)
#define | UART2_BRR1_RESET_VALUE ((uint8_t)0x00)
#define | UART2_BRR2_DIVF ((uint8_t)0x0F)
#define | UART2_BRR2_DIVM ((uint8_t)0xF0)
#define | UART2_BRR2_RESET_VALUE ((uint8_t)0x00)
#define | UART2_CR1_M ((uint8_t)0x10)
#define | UART2_CR1_PCEN ((uint8_t)0x04)
#define | UART2_CR1_PIEN ((uint8_t)0x01)
#define | UART2_CR1_PS ((uint8_t)0x02)
#define | UART2_CR1_R8 ((uint8_t)0x80)
#define | UART2_CR1_RESET_VALUE ((uint8_t)0x00)
#define | UART2_CR1_T8 ((uint8_t)0x40)
#define | UART2_CR1_UARTD ((uint8_t)0x20)
#define | UART2_CR1_WAKE ((uint8_t)0x08)
#define | UART2_CR2_ILIEN ((uint8_t)0x10)
#define | UART2_CR2_REN ((uint8_t)0x04)
#define | UART2_CR2_RESET_VALUE ((uint8_t)0x00)
#define | UART2_CR2_RIEN ((uint8_t)0x20)
#define | UART2_CR2_RWU ((uint8_t)0x02)
#define | UART2_CR2_SBK ((uint8_t)0x01)
#define | UART2_CR2_TCIEN ((uint8_t)0x40)
#define | UART2_CR2_TEN ((uint8_t)0x08)
#define | UART2_CR2_TIEN ((uint8_t)0x80)
#define | UART2_CR3_CKEN ((uint8_t)0x08)
#define | UART2_CR3_CPHA ((uint8_t)0x02)
#define | UART2_CR3_CPOL ((uint8_t)0x04)
#define | UART2_CR3_LBCL ((uint8_t)0x01)
#define | UART2_CR3_LINEN ((uint8_t)0x40)
#define | UART2_CR3_RESET_VALUE ((uint8_t)0x00)
#define | UART2_CR3_STOP ((uint8_t)0x30)
#define | UART2_CR4_ADD ((uint8_t)0x0F)
#define | UART2_CR4_LBDF ((uint8_t)0x10)
#define | UART2_CR4_LBDIEN ((uint8_t)0x40)
#define | UART2_CR4_LBDL ((uint8_t)0x20)
#define | UART2_CR4_RESET_VALUE ((uint8_t)0x00)
#define | UART2_CR5_IREN ((uint8_t)0x02)
#define | UART2_CR5_IRLP ((uint8_t)0x04)
#define | UART2_CR5_NACK ((uint8_t)0x10)
#define | UART2_CR5_RESET_VALUE ((uint8_t)0x00)
#define | UART2_CR5_SCEN ((uint8_t)0x20)
#define | UART2_CR6_LASE ((uint8_t)0x10)
#define | UART2_CR6_LDUM ((uint8_t)0x80)
#define | UART2_CR6_LHDF ((uint8_t)0x02)
#define | UART2_CR6_LHDIEN ((uint8_t)0x04)
#define | UART2_CR6_LSF ((uint8_t)0x01)
#define | UART2_CR6_LSLV ((uint8_t)0x20)
#define | UART2_CR6_RESET_VALUE ((uint8_t)0x00)
#define | UART2_GTR_RESET_VALUE ((uint8_t)0x00)
#define | UART2_PSCR_RESET_VALUE ((uint8_t)0x00)
#define | UART2_SR_FE ((uint8_t)0x02)
#define | UART2_SR_IDLE ((uint8_t)0x10)
#define | UART2_SR_NF ((uint8_t)0x04)
#define | UART2_SR_OR ((uint8_t)0x08)
#define | UART2_SR_PE ((uint8_t)0x01)
#define | UART2_SR_RESET_VALUE ((uint8_t)0xC0)
#define | UART2_SR_RXNE ((uint8_t)0x20)
#define | UART2_SR_TC ((uint8_t)0x40)
#define | UART2_SR_TXE ((uint8_t)0x80)
#define | UART3_BaseAddress 0x5240
#define | UART3_BRR1_DIVM ((uint8_t)0xFF)
#define | UART3_BRR1_RESET_VALUE ((uint8_t)0x00)
#define | UART3_BRR2_DIVF ((uint8_t)0x0F)
#define | UART3_BRR2_DIVM ((uint8_t)0xF0)
#define | UART3_BRR2_RESET_VALUE ((uint8_t)0x00)
#define | UART3_CR1_M ((uint8_t)0x10)
#define | UART3_CR1_PCEN ((uint8_t)0x04)
#define | UART3_CR1_PIEN ((uint8_t)0x01)
#define | UART3_CR1_PS ((uint8_t)0x02)
#define | UART3_CR1_R8 ((uint8_t)0x80)
#define | UART3_CR1_RESET_VALUE ((uint8_t)0x00)
#define | UART3_CR1_T8 ((uint8_t)0x40)
#define | UART3_CR1_UARTD ((uint8_t)0x20)
#define | UART3_CR1_WAKE ((uint8_t)0x08)
#define | UART3_CR2_ILIEN ((uint8_t)0x10)
#define | UART3_CR2_REN ((uint8_t)0x04)
#define | UART3_CR2_RESET_VALUE ((uint8_t)0x00)
#define | UART3_CR2_RIEN ((uint8_t)0x20)
#define | UART3_CR2_RWU ((uint8_t)0x02)
#define | UART3_CR2_SBK ((uint8_t)0x01)
#define | UART3_CR2_TCIEN ((uint8_t)0x40)
#define | UART3_CR2_TEN ((uint8_t)0x08)
#define | UART3_CR2_TIEN ((uint8_t)0x80)
#define | UART3_CR3_LINEN ((uint8_t)0x40)
#define | UART3_CR3_RESET_VALUE ((uint8_t)0x00)
#define | UART3_CR3_STOP ((uint8_t)0x30)
#define | UART3_CR4_ADD ((uint8_t)0x0F)
#define | UART3_CR4_LBDF ((uint8_t)0x10)
#define | UART3_CR4_LBDIEN ((uint8_t)0x40)
#define | UART3_CR4_LBDL ((uint8_t)0x20)
#define | UART3_CR4_RESET_VALUE ((uint8_t)0x00)
#define | UART3_CR6_LASE ((uint8_t)0x10)
#define | UART3_CR6_LDUM ((uint8_t)0x80)
#define | UART3_CR6_LHDF ((uint8_t)0x02)
#define | UART3_CR6_LHDIEN ((uint8_t)0x04)
#define | UART3_CR6_LSF ((uint8_t)0x01)
#define | UART3_CR6_LSLV ((uint8_t)0x20)
#define | UART3_CR6_RESET_VALUE ((uint8_t)0x00)
#define | UART3_SR_FE ((uint8_t)0x02)
#define | UART3_SR_IDLE ((uint8_t)0x10)
#define | UART3_SR_NF ((uint8_t)0x04)
#define | UART3_SR_OR ((uint8_t)0x08)
#define | UART3_SR_PE ((uint8_t)0x01)
#define | UART3_SR_RESET_VALUE ((uint8_t)0xC0)
#define | UART3_SR_RXNE ((uint8_t)0x20)
#define | UART3_SR_TC ((uint8_t)0x40)
#define | UART3_SR_TXE ((uint8_t)0x80)
#define | UART4_BaseAddress 0x5230
#define | USE_STDPERIPH_DRIVER
#define | ValBit(VAR, Place) ((uint8_t)(VAR) & (uint8_t)((uint8_t)1<<(uint8_t)(Place)))
#define | wfi() __wait_for_interrupt()
#define | WWDG ((WWDG_TypeDef *) WWDG_BaseAddress)
#define | WWDG_BaseAddress 0x50D1
#define | WWDG_CR_RESET_VALUE ((uint8_t)0x7F)
#define | WWDG_CR_T ((uint8_t)0x7F)
#define | WWDG_CR_T6 ((uint8_t)0x40)
#define | WWDG_CR_WDGA ((uint8_t)0x80)
#define | WWDG_WR_MSB ((uint8_t)0x80)
#define | WWDG_WR_RESET_VALUE ((uint8_t)0x7F)
#define | WWDG_WR_W ((uint8_t)0x7F)

Typedefs

typedef struct AWU_struct | AWU_TypeDef
Auto Wake Up (AWU) peripheral registers.
typedef struct BEEP_struct | BEEP_TypeDef
Beeper (BEEP) peripheral registers.
typedef enum FlagStatus | BitAction
typedef enum FlagStatus | BitStatus
typedef struct CFG_struct | CFG_TypeDef
Configuration Registers (CFG)
typedef struct CLK_struct | CLK_TypeDef
Clock Controller (CLK)
typedef struct EXTI_struct | EXTI_TypeDef
External Interrupt Controller (EXTI)
typedef struct FLASH_struct | FLASH_TypeDef
FLASH program and Data memory (FLASH)
typedef struct GPIO_struct | GPIO_TypeDef
General Purpose I/Os (GPIO)
typedef struct I2C_struct | I2C_TypeDef
Inter-Integrated Circuit (I2C)
typedef signed short | int16_t
typedef signed long | int32_t
typedef signed char | int8_t
typedef struct ITC_struct | ITC_TypeDef
Interrupt Controller (ITC)
typedef enum FlagStatus | ITStatus
typedef struct IWDG_struct | IWDG_TypeDef
Independent Watchdog (IWDG)
typedef struct OPT_struct | OPT_TypeDef
Option Bytes (OPT)
typedef struct RST_struct | RST_TypeDef
Reset Controller (RST)
typedef int16_t | s16
typedef int32_t | s32
typedef int8_t | s8
typedef struct SPI_struct | SPI_TypeDef
Serial Peripheral Interface (SPI)
typedef struct TIM1_struct | TIM1_TypeDef
16-bit timer with complementary PWM outputs (TIM1)
typedef struct TIM2_struct | TIM2_TypeDef
16-bit timer (TIM2)
typedef struct TIM3_struct | TIM3_TypeDef
16-bit timer (TIM3)
typedef struct TIM4_struct | TIM4_TypeDef
8-bit system timer (TIM4)
typedef struct TIM5_struct | TIM5_TypeDef
16-bit timer with synchro module (TIM5)
typedef struct TIM6_struct | TIM6_TypeDef
8-bit system timer with synchro module(TIM6)
typedef uint16_t | u16
typedef uint32_t | u32
typedef uint8_t | u8
typedef struct UART1_struct | UART1_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter (UART1)
typedef struct UART2_struct | UART2_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter (UART2)
typedef struct UART3_struct | UART3_TypeDef
LIN Universal Asynchronous Receiver Transmitter (UART3)
typedef unsigned short | uint16_t
typedef unsigned long | uint32_t
typedef unsigned char | uint8_t
typedef struct WWDG_struct | WWDG_TypeDef
Window Watchdog (WWDG)

Enumerations

enum | bool { FALSE = 0, TRUE = !FALSE }
enum | ErrorStatus { ERROR = 0, SUCCESS = !ERROR }
enum | FlagStatus { RESET = 0, SET = !RESET }
enum | FunctionalState { DISABLE = 0, ENABLE = !DISABLE }

Detailed Description

This file contains all HW registers definitions and memory mapping.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s.h.

Define Documentation

#define AffBit | ( | VAR,
 |  | Place,
 |  | Value
 | ) |
Value:
((Value) ? \
                                   ((VAR) |= ((uint8_t)1<<(Place))) : \
                                   ((VAR) &= (((uint8_t)1<<(Place))^(uint8_t)255)))

Definition at line 2793 of file stm8s.h.

#define AREA 0x00

Definition at line 2819 of file stm8s.h.

#define AWU ((AWU_TypeDef *) AWU_BaseAddress)

Definition at line 2611 of file stm8s.h.

Referenced by AWU_Cmd(), AWU_DeInit(), AWU_GetFlagStatus(), AWU_IdleModeEnable(), AWU_Init(), and AWU_LSICalibrationConfig().

#define BEEP ((BEEP_TypeDef *) BEEP_BaseAddress)

Definition at line 2613 of file stm8s.h.

Referenced by BEEP_Cmd(), BEEP_DeInit(), BEEP_Init(), and BEEP_LSICalibrationConfig().

#define BitClr ( BIT ) ( *((unsigned char *) (AREA+(BIT)/8)) &= (~(1<<(7-(BIT)%8))) )

Definition at line 2821 of file stm8s.h.

#define BitSet ( BIT ) ( *((unsigned char *) (AREA+(BIT)/8)) |= (1<<(7-(BIT)%8)) )

Definition at line 2822 of file stm8s.h.

#define BitVal ( BIT ) ( *((unsigned char *) (AREA+(BIT)/8)) & (1<<(7-(BIT)%8)) )

Definition at line 2823 of file stm8s.h.

#define BYTE_0 ( n ) ((uint8_t)((n) & (uint8_t)0xFF))

Returns the low byte of the 32-bit value

Definition at line 2800 of file stm8s.h.

#define BYTE_1 ( n ) ((uint8_t)(BYTE_0((n) >> (uint8_t)8)))

Returns the second byte of the 32-bit value

Definition at line 2801 of file stm8s.h.

#define BYTE_2 ( n ) ((uint8_t)(BYTE_0((n) >> (uint8_t)16)))

Returns the third byte of the 32-bit value

Definition at line 2802 of file stm8s.h.

#define BYTE_3 ( n ) ((uint8_t)(BYTE_0((n) >> (uint8_t)24)))

Returns the high byte of the 32-bit value

Definition at line 2803 of file stm8s.h.

#define CFG ((CFG_TypeDef *) CFG_BaseAddress)

Definition at line 2702 of file stm8s.h.

#define ChgBit | ( | VAR,
 |  | Place
 | ) | ( (VAR) ^= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) )

Definition at line 2792 of file stm8s.h.

#define CLK ((CLK_TypeDef *) CLK_BaseAddress)

Definition at line 2619 of file stm8s.h.

Referenced by CLK_AdjustHSICalibrationValue(), CLK_CCOCmd(), CLK_CCOConfig(), CLK_ClearITPendingBit(), CLK_ClockSecuritySystemEnable(), CLK_ClockSwitchCmd(), CLK_ClockSwitchConfig(), CLK_DeInit(), CLK_FastHaltWakeUpCmd(), CLK_GetClockFreq(), CLK_GetFlagStatus(), CLK_GetITStatus(), CLK_GetSYSCLKSource(), CLK_HSECmd(), CLK_HSICmd(), CLK_HSIPrescalerConfig(), CLK_ITConfig(), CLK_LSICmd(), CLK_PeripheralClockConfig(), CLK_SlowActiveHaltWakeUpCmd(), CLK_SWIMConfig(), CLK_SYSCLKConfig(), and CLK_SYSCLKEmergencyClear().

#define ClrBit | ( | VAR,
 |  | Place
 | ) | ( (VAR) &= (uint8_t)((uint8_t)((uint8_t)1<<(uint8_t)(Place))^(uint8_t)255) )

Definition at line 2790 of file stm8s.h.

#define disableInterrupts ( ) __disable_interrupt()

Definition at line 2736 of file stm8s.h.

#define DM ((DM_TypeDef *) DM_BaseAddress)

Definition at line 2704 of file stm8s.h.

#define enableInterrupts ( ) __enable_interrupt()

Definition at line 2735 of file stm8s.h.

#define EXTI ((EXTI_TypeDef *) EXTI_BaseAddress)

Definition at line 2621 of file stm8s.h.

Referenced by EXTI_DeInit(), EXTI_GetExtIntSensitivity(), EXTI_GetTLISensitivity(), EXTI_SetExtIntSensitivity(), and EXTI_SetTLISensitivity().

#define FLASH ((FLASH_TypeDef *) FLASH_BaseAddress)

Definition at line 2623 of file stm8s.h.

Referenced by FLASH_DeInit(), FLASH_EraseOptionByte(), FLASH_GetBootSize(), FLASH_GetFlagStatus(), FLASH_GetLowPowerMode(), FLASH_GetProgrammingTime(), FLASH_ITConfig(), FLASH_Lock(), FLASH_ProgramOptionByte(), FLASH_ProgramWord(), FLASH_SetLowPowerMode(), FLASH_SetProgrammingTime(), and FLASH_Unlock().

#define GPIOA ((GPIO_TypeDef *) GPIOA_BaseAddress)

Definition at line 2627 of file stm8s.h.

#define GPIOB ((GPIO_TypeDef *) GPIOB_BaseAddress)

Definition at line 2629 of file stm8s.h.

#define GPIOC ((GPIO_TypeDef *) GPIOC_BaseAddress)

Definition at line 2631 of file stm8s.h.

#define GPIOD ((GPIO_TypeDef *) GPIOD_BaseAddress)

Definition at line 2633 of file stm8s.h.

#define GPIOE ((GPIO_TypeDef *) GPIOE_BaseAddress)

Definition at line 2635 of file stm8s.h.

#define GPIOF ((GPIO_TypeDef *) GPIOF_BaseAddress)

Definition at line 2637 of file stm8s.h.

#define halt ( ) __halt()

Definition at line 2742 of file stm8s.h.

#define I2C ((I2C_TypeDef *) I2C_BaseAddress)

Definition at line 2656 of file stm8s.h.

Referenced by I2C_AcknowledgeConfig(), I2C_CheckEvent(), I2C_ClearFlag(), I2C_ClearITPendingBit(), I2C_Cmd(), I2C_DeInit(), I2C_FastModeDutyCycleConfig(), I2C_GeneralCallCmd(), I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_GetFlagStatus(), I2C_GetITStatus(), I2C_GetLastEvent(), I2C_Init(), I2C_ITConfig(), I2C_ReceiveData(), I2C_Send7bitAddress(), I2C_SendData(), I2C_SoftwareResetCmd(), and I2C_StretchClockCmd().

#define IS_STATE_VALUE_OK ( SensitivityValue )
Value:
(((SensitivityValue) == ENABLE) || \
   ((SensitivityValue) == DISABLE))

Definition at line 2806 of file stm8s.h.

#define ITC ((ITC_TypeDef *) ITC_BaseAddress)

Definition at line 2700 of file stm8s.h.

Referenced by ITC_DeInit(), ITC_GetSoftwarePriority(), and ITC_SetSoftwarePriority().

#define IWDG ((IWDG_TypeDef *) IWDG_BaseAddress)

Definition at line 2653 of file stm8s.h.

Referenced by IWDG_Enable(), IWDG_ReloadCounter(), IWDG_SetPrescaler(), IWDG_SetReload(), and IWDG_WriteAccessCmd().

#define MskBit | ( | Dest,
 |  | Msk,
 |  | Src
 | ) | ( (Dest) = ((Msk) & (Src)) | ((~(Msk)) & (Dest)) )

Definition at line 2796 of file stm8s.h.

#define nop ( ) __no_operation()

Definition at line 2739 of file stm8s.h.

#define OPT ((OPT_TypeDef *) OPT_BaseAddress)

Definition at line 2625 of file stm8s.h.

#define rim ( ) __enable_interrupt()

Definition at line 2737 of file stm8s.h.

#define RST ((RST_TypeDef *) RST_BaseAddress)

Definition at line 2650 of file stm8s.h.

Referenced by RST_ClearFlag(), and RST_GetFlagStatus().

#define SetBit | ( | VAR,
 |  | Place
 | ) | ( (VAR) |= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) )

Definition at line 2789 of file stm8s.h.

#define sim ( ) __disable_interrupt()

Definition at line 2738 of file stm8s.h.

#define SPI ((SPI_TypeDef *) SPI_BaseAddress)

Definition at line 2655 of file stm8s.h.

Referenced by SPI_BiDirectionalLineConfig(), SPI_CalculateCRCCmd(), SPI_ClearFlag(), SPI_ClearITPendingBit(), SPI_Cmd(), SPI_DeInit(), SPI_GetCRC(), SPI_GetCRCPolynomial(), SPI_GetFlagStatus(), SPI_GetITStatus(), SPI_Init(), SPI_ITConfig(), SPI_NSSInternalSoftwareCmd(), SPI_ReceiveData(), SPI_SendData(), and SPI_TransmitCRC().

#define TIM1 ((TIM1_TypeDef *) TIM1_BaseAddress)

Definition at line 2676 of file stm8s.h.

Referenced by TI1_Config(), TI2_Config(), TI3_Config(), TI4_Config(), TIM1_ARRPreloadConfig(), TIM1_BDTRConfig(), TIM1_CCPreloadControl(), TIM1_CCxCmd(), TIM1_CCxNCmd(), TIM1_ClearFlag(), TIM1_ClearITPendingBit(), TIM1_Cmd(), TIM1_CounterModeConfig(), TIM1_CtrlPWMOutputs(), TIM1_DeInit(), TIM1_EncoderInterfaceConfig(), TIM1_ETRClockMode1Config(), TIM1_ETRClockMode2Config(), TIM1_ETRConfig(), TIM1_ForcedOC1Config(), TIM1_ForcedOC2Config(), TIM1_ForcedOC3Config(), TIM1_ForcedOC4Config(), TIM1_GenerateEvent(), TIM1_GetCapture1(), TIM1_GetCapture2(), TIM1_GetCapture3(), TIM1_GetCapture4(), TIM1_GetCounter(), TIM1_GetFlagStatus(), TIM1_GetITStatus(), TIM1_GetPrescaler(), TIM1_InternalClockConfig(), TIM1_ITConfig(), TIM1_OC1FastConfig(), TIM1_OC1Init(), TIM1_OC1NPolarityConfig(), TIM1_OC1PolarityConfig(), TIM1_OC1PreloadConfig(), TIM1_OC2FastConfig(), TIM1_OC2Init(), TIM1_OC2NPolarityConfig(), TIM1_OC2PolarityConfig(), TIM1_OC2PreloadConfig(), TIM1_OC3FastConfig(), TIM1_OC3Init(), TIM1_OC3NPolarityConfig(), TIM1_OC3PolarityConfig(), TIM1_OC3PreloadConfig(), TIM1_OC4FastConfig(), TIM1_OC4Init(), TIM1_OC4PolarityConfig(), TIM1_OC4PreloadConfig(), TIM1_PrescalerConfig(), TIM1_SelectCOM(), TIM1_SelectHallSensor(), TIM1_SelectInputTrigger(), TIM1_SelectMasterSlaveMode(), TIM1_SelectOCxM(), TIM1_SelectOnePulseMode(), TIM1_SelectOutputTrigger(), TIM1_SelectSlaveMode(), TIM1_SetAutoreload(), TIM1_SetCompare1(), TIM1_SetCompare2(), TIM1_SetCompare3(), TIM1_SetCompare4(), TIM1_SetCounter(), TIM1_SetIC1Prescaler(), TIM1_SetIC2Prescaler(), TIM1_SetIC3Prescaler(), TIM1_SetIC4Prescaler(), TIM1_TimeBaseInit(), TIM1_TIxExternalClockConfig(), TIM1_UpdateDisableConfig(), and TIM1_UpdateRequestConfig().

#define trap ( ) __trap()

Definition at line 2740 of file stm8s.h.

#define ValBit | ( | VAR,
 |  | Place
 | ) | ((uint8_t)(VAR) & (uint8_t)((uint8_t)1<<(uint8_t)(Place)))

Definition at line 2798 of file stm8s.h.

#define wfi ( ) __wait_for_interrupt()

Definition at line 2741 of file stm8s.h.

#define WWDG ((WWDG_TypeDef *) WWDG_BaseAddress)

Definition at line 2652 of file stm8s.h.

Referenced by WWDG_GetCounter(), WWDG_Init(), WWDG_SetCounter(), WWDG_SetWindowValue(), and WWDG_SWReset().

Typedef Documentation

typedef struct AWU_struct AWU_TypeDef

Auto Wake Up (AWU) peripheral registers.

typedef struct BEEP_struct BEEP_TypeDef

Beeper (BEEP) peripheral registers.

typedef struct CFG_struct CFG_TypeDef

Configuration Registers (CFG)

typedef struct CLK_struct CLK_TypeDef

Clock Controller (CLK)

typedef struct EXTI_struct EXTI_TypeDef

External Interrupt Controller (EXTI)

typedef struct FLASH_struct FLASH_TypeDef

FLASH program and Data memory (FLASH)

typedef struct I2C_struct I2C_TypeDef

Inter-Integrated Circuit (I2C)

typedef struct ITC_struct ITC_TypeDef

Interrupt Controller (ITC)

typedef struct IWDG_struct IWDG_TypeDef

Independent Watchdog (IWDG)

typedef struct OPT_struct OPT_TypeDef

Option Bytes (OPT)

typedef struct RST_struct RST_TypeDef

Reset Controller (RST)

typedef struct SPI_struct SPI_TypeDef

Serial Peripheral Interface (SPI)

typedef struct TIM1_struct TIM1_TypeDef

16-bit timer with complementary PWM outputs (TIM1)

typedef struct TIM2_struct TIM2_TypeDef

16-bit timer (TIM2)

typedef struct TIM3_struct TIM3_TypeDef

16-bit timer (TIM3)

typedef struct TIM4_struct TIM4_TypeDef

8-bit system timer (TIM4)

typedef struct TIM5_struct TIM5_TypeDef

16-bit timer with synchro module (TIM5)

typedef struct TIM6_struct TIM6_TypeDef

8-bit system timer with synchro module(TIM6)

typedef struct UART1_struct UART1_TypeDef

Universal Synchronous Asynchronous Receiver Transmitter (UART1)

typedef struct UART2_struct UART2_TypeDef

Universal Synchronous Asynchronous Receiver Transmitter (UART2)

typedef struct UART3_struct UART3_TypeDef

LIN Universal Asynchronous Receiver Transmitter (UART3)

typedef struct WWDG_struct WWDG_TypeDef

Window Watchdog (WWDG)


STM8S/A Standard Peripherals Drivers: stm8s_adc1.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions
stm8s_adc1.c File Reference

This file contains all the functions/macros for the ADC1 peripheral. More...

#include "stm8s_adc1.h"

Go to the source code of this file.

Functions

void | ADC1_AWDChannelConfig (ADC1_Channel_TypeDef Channel, FunctionalState NewState)
Enables or disables the analog watchdog for the given channel.
void | ADC1_ClearFlag (ADC1_Flag_TypeDef Flag)
Clear the specified ADC1 Flag.
void | ADC1_ClearITPendingBit (ADC1_IT_TypeDef ITPendingBit)
Clear the ADC1 End of Conversion pending bit.
void | ADC1_Cmd (FunctionalState NewState)
Enables or Disables the ADC1 peripheral.
void | ADC1_ConversionConfig (ADC1_ConvMode_TypeDef ADC1_ConversionMode, ADC1_Channel_TypeDef ADC1_Channel, ADC1_Align_TypeDef ADC1_Align)
Configure the ADC1 conversion on selected channel.
void | ADC1_DataBufferCmd (FunctionalState NewState)
Enables or Disables the ADC1 data store into the Data Buffer registers rather than in the Data Register.
void | ADC1_DeInit (void)
Deinitializes the ADC1 peripheral registers to their default reset values.
void | ADC1_ExternalTriggerConfig (ADC1_ExtTrig_TypeDef ADC1_ExtTrigger, FunctionalState NewState)
Configure the ADC1 conversion on external trigger event.
FlagStatus | ADC1_GetAWDChannelStatus (ADC1_Channel_TypeDef Channel)
Checks the specified analog watchdog channel status.
uint16_t | ADC1_GetBufferValue (uint8_t Buffer)
Get one sample of measured signal.
uint16_t | ADC1_GetConversionValue (void)
Get one sample of measured signal.
FlagStatus | ADC1_GetFlagStatus (ADC1_Flag_TypeDef Flag)
Checks the specified ADC1 flag status.
ITStatus | ADC1_GetITStatus (ADC1_IT_TypeDef ITPendingBit)
Returns the specified pending bit status.
void | ADC1_Init (ADC1_ConvMode_TypeDef ADC1_ConversionMode, ADC1_Channel_TypeDef ADC1_Channel, ADC1_PresSel_TypeDef ADC1_PrescalerSelection, ADC1_ExtTrig_TypeDef ADC1_ExtTrigger, FunctionalState ADC1_ExtTriggerState, ADC1_Align_TypeDef ADC1_Align, ADC1_SchmittTrigg_TypeDef ADC1_SchmittTriggerChannel, FunctionalState ADC1_SchmittTriggerState)
Initializes the ADC1 peripheral according to the specified parameters.
void | ADC1_ITConfig (ADC1_IT_TypeDef ADC1_IT, FunctionalState NewState)
Enables or disables the ADC1 interrupt.
void | ADC1_PrescalerConfig (ADC1_PresSel_TypeDef ADC1_Prescaler)
Configure the ADC1 prescaler division factor.
void | ADC1_ScanModeCmd (FunctionalState NewState)
Enables or Disables the ADC1 scan mode.
void | ADC1_SchmittTriggerConfig (ADC1_SchmittTrigg_TypeDef ADC1_SchmittTriggerChannel, FunctionalState NewState)
Enables or disables the ADC1 Schmitt Trigger on a selected channel.
void | ADC1_SetHighThreshold (uint16_t Threshold)
Sets the high threshold of the analog watchdog.
void | ADC1_SetLowThreshold (uint16_t Threshold)
Sets the low threshold of the analog watchdog.
void | ADC1_StartConversion (void)
Start ADC1 conversion.

Detailed Description

This file contains all the functions/macros for the ADC1 peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_adc1.c.


STM8S/A Standard Peripherals Drivers: stm8s_adc1.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions
stm8s_adc1.h File Reference

This file contains all the prototypes/macros for the ADC1 peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_ADC1_ALIGN_OK(ALIGN)
Macro used by the assert function to check the different alignment modes.
#define | IS_ADC1_BUFFER_OK(BUFFER) ((BUFFER) <= (uint8_t)0x09)
Macro used by the assert function to check the possible buffer values.
#define | IS_ADC1_CHANNEL_OK(CHANNEL)
Macro used by the assert function to check the different channels values.
#define | IS_ADC1_CONVERSIONMODE_OK(MODE)
Macro used by the assert function to check the different conversion modes.
#define | IS_ADC1_EXTTRIG_OK(EXTRIG)
Macro used by the assert function to check the different external trigger values.
#define | IS_ADC1_FLAG_OK(FLAG)
Macro used by the assert function to check the ADC1 Flag.
#define | IS_ADC1_IT_OK(IT)
Macro used by the assert function to check the Interrupt source.
#define | IS_ADC1_ITPENDINGBIT_OK(ITPENDINGBIT)
Macro used by the assert function to check the ADC1 pending bits.
#define | IS_ADC1_PRESSEL_OK(PRESCALER)
Macro used by the assert function to check the different prescaler's values.
#define | IS_ADC1_SCHMITTTRIG_OK(SCHMITTTRIG)
Macro used by the assert function to check the different schmitt trigger values.

Enumerations

enum | ADC1_Align_TypeDef { ADC1_ALIGN_LEFT = (uint8_t)0x00, ADC1_ALIGN_RIGHT = (uint8_t)0x08 }
ADC1 data alignment. More...
enum ADC1_Channel_TypeDef {
ADC1_CHANNEL_0 = (uint8_t)0x00, ADC1_CHANNEL_1 = (uint8_t)0x01, ADC1_CHANNEL_2 = (uint8_t)0x02, ADC1_CHANNEL_3 = (uint8_t)0x03,
ADC1_CHANNEL_4 = (uint8_t)0x04, ADC1_CHANNEL_5 = (uint8_t)0x05, ADC1_CHANNEL_6 = (uint8_t)0x06, ADC1_CHANNEL_7 = (uint8_t)0x07,
ADC1_CHANNEL_8 = (uint8_t)0x08, ADC1_CHANNEL_9 = (uint8_t)0x09, ADC1_CHANNEL_12 = (uint8_t)0x0C
}
ADC1 analog channel selection. More...
enum | ADC1_ConvMode_TypeDef { ADC1_CONVERSIONMODE_SINGLE = (uint8_t)0x00, ADC1_CONVERSIONMODE_CONTINUOUS = (uint8_t)0x01 }
ADC1 conversion mode selection. More...
enum | ADC1_ExtTrig_TypeDef { ADC1_EXTTRIG_TIM = (uint8_t)0x00, ADC1_EXTTRIG_GPIO = (uint8_t)0x10 }
ADC1 External conversion trigger event selection. More...
enum ADC1_Flag_TypeDef {
ADC1_FLAG_OVR = (uint8_t)0x41, ADC1_FLAG_AWD = (uint8_t)0x40, ADC1_FLAG_AWS0 = (uint8_t)0x10, ADC1_FLAG_AWS1 = (uint8_t)0x11,
ADC1_FLAG_AWS2 = (uint8_t)0x12, ADC1_FLAG_AWS3 = (uint8_t)0x13, ADC1_FLAG_AWS4 = (uint8_t)0x14, ADC1_FLAG_AWS5 = (uint8_t)0x15,
ADC1_FLAG_AWS6 = (uint8_t)0x16, ADC1_FLAG_AWS7 = (uint8_t)0x17, ADC1_FLAG_AWS8 = (uint8_t)0x18, ADC1_FLAG_AWS9 = (uint8_t)0x19,
ADC1_FLAG_AWS12 = (uint8_t)0x1C, ADC1_FLAG_EOC = (uint8_t)0x80
}
ADC1 Flags. More...
enum ADC1_IT_TypeDef {
ADC1_IT_AWDIE = (uint16_t)0x010, ADC1_IT_EOCIE = (uint16_t)0x020, ADC1_IT_AWD = (uint16_t)0x140, ADC1_IT_AWS0 = (uint16_t)0x110,
ADC1_IT_AWS1 = (uint16_t)0x111, ADC1_IT_AWS2 = (uint16_t)0x112, ADC1_IT_AWS3 = (uint16_t)0x113, ADC1_IT_AWS4 = (uint16_t)0x114,
ADC1_IT_AWS5 = (uint16_t)0x115, ADC1_IT_AWS6 = (uint16_t)0x116, ADC1_IT_AWS7 = (uint16_t)0x117, ADC1_IT_AWS8 = (uint16_t)0x118,
ADC1_IT_AWS9 = (uint16_t)0x119, ADC1_IT_AWS12 = (uint16_t)0x11C, ADC1_IT_EOC = (uint16_t)0x080
}
ADC1 Interrupt source. More...
enum ADC1_PresSel_TypeDef {
ADC1_PRESSEL_FCPU_D2 = (uint8_t)0x00, ADC1_PRESSEL_FCPU_D3 = (uint8_t)0x10, ADC1_PRESSEL_FCPU_D4 = (uint8_t)0x20, ADC1_PRESSEL_FCPU_D6 = (uint8_t)0x30,
ADC1_PRESSEL_FCPU_D8 = (uint8_t)0x40, ADC1_PRESSEL_FCPU_D10 = (uint8_t)0x50, ADC1_PRESSEL_FCPU_D12 = (uint8_t)0x60, ADC1_PRESSEL_FCPU_D18 = (uint8_t)0x70
}
ADC1 clock prescaler selection. More...
enum ADC1_SchmittTrigg_TypeDef {
ADC1_SCHMITTTRIG_CHANNEL0 = (uint8_t)0x00, ADC1_SCHMITTTRIG_CHANNEL1 = (uint8_t)0x01, ADC1_SCHMITTTRIG_CHANNEL2 = (uint8_t)0x02, ADC1_SCHMITTTRIG_CHANNEL3 = (uint8_t)0x03,
ADC1_SCHMITTTRIG_CHANNEL4 = (uint8_t)0x04, ADC1_SCHMITTTRIG_CHANNEL5 = (uint8_t)0x05, ADC1_SCHMITTTRIG_CHANNEL6 = (uint8_t)0x06, ADC1_SCHMITTTRIG_CHANNEL7 = (uint8_t)0x07,
ADC1_SCHMITTTRIG_CHANNEL8 = (uint8_t)0x08, ADC1_SCHMITTTRIG_CHANNEL9 = (uint8_t)0x09, ADC1_SCHMITTTRIG_CHANNEL12 = (uint8_t)0x0C, ADC1_SCHMITTTRIG_ALL = (uint8_t)0xFF
}
ADC1 schmitt Trigger. More...

Functions

void | ADC1_AWDChannelConfig (ADC1_Channel_TypeDef Channel, FunctionalState NewState)
Enables or disables the analog watchdog for the given channel.
void | ADC1_ClearFlag (ADC1_Flag_TypeDef Flag)
Clear the specified ADC1 Flag.
void | ADC1_ClearITPendingBit (ADC1_IT_TypeDef ITPendingBit)
Clear the ADC1 End of Conversion pending bit.
void | ADC1_Cmd (FunctionalState NewState)
Enables or Disables the ADC1 peripheral.
void | ADC1_ConversionConfig (ADC1_ConvMode_TypeDef ADC1_ConversionMode, ADC1_Channel_TypeDef ADC1_Channel, ADC1_Align_TypeDef ADC1_Align)
Configure the ADC1 conversion on selected channel.
void | ADC1_DataBufferCmd (FunctionalState NewState)
Enables or Disables the ADC1 data store into the Data Buffer registers rather than in the Data Register.
void | ADC1_DeInit (void)
Deinitializes the ADC1 peripheral registers to their default reset values.
void | ADC1_ExternalTriggerConfig (ADC1_ExtTrig_TypeDef ADC1_ExtTrigger, FunctionalState NewState)
Configure the ADC1 conversion on external trigger event.
FlagStatus | ADC1_GetAWDChannelStatus (ADC1_Channel_TypeDef Channel)
Checks the specified analog watchdog channel status.
uint16_t | ADC1_GetBufferValue (uint8_t Buffer)
Get one sample of measured signal.
uint16_t | ADC1_GetConversionValue (void)
Get one sample of measured signal.
FlagStatus | ADC1_GetFlagStatus (ADC1_Flag_TypeDef Flag)
Checks the specified ADC1 flag status.
ITStatus | ADC1_GetITStatus (ADC1_IT_TypeDef ITPendingBit)
Returns the specified pending bit status.
void | ADC1_Init (ADC1_ConvMode_TypeDef ADC1_ConversionMode, ADC1_Channel_TypeDef ADC1_Channel, ADC1_PresSel_TypeDef ADC1_PrescalerSelection, ADC1_ExtTrig_TypeDef ADC1_ExtTrigger, FunctionalState ADC1_ExtTriggerState, ADC1_Align_TypeDef ADC1_Align, ADC1_SchmittTrigg_TypeDef ADC1_SchmittTriggerChannel, FunctionalState ADC1_SchmittTriggerState)
Initializes the ADC1 peripheral according to the specified parameters.
void | ADC1_ITConfig (ADC1_IT_TypeDef ADC1_IT, FunctionalState NewState)
Enables or disables the ADC1 interrupt.
void | ADC1_PrescalerConfig (ADC1_PresSel_TypeDef ADC1_Prescaler)
Configure the ADC1 prescaler division factor.
void | ADC1_ScanModeCmd (FunctionalState NewState)
Enables or Disables the ADC1 scan mode.
void | ADC1_SchmittTriggerConfig (ADC1_SchmittTrigg_TypeDef ADC1_SchmittTriggerChannel, FunctionalState NewState)
Enables or disables the ADC1 Schmitt Trigger on a selected channel.
void | ADC1_SetHighThreshold (uint16_t Threshold)
Sets the high threshold of the analog watchdog.
void | ADC1_SetLowThreshold (uint16_t Threshold)
Sets the low threshold of the analog watchdog.
void | ADC1_StartConversion (void)
Start ADC1 conversion.

Detailed Description

This file contains all the prototypes/macros for the ADC1 peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_adc1.h.


STM8S/A Standard Peripherals Drivers: stm8s_adc2.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions
stm8s_adc2.c File Reference

This file contains all the functions/macros for the ADC2 peripheral. More...

#include "stm8s_adc2.h"

Go to the source code of this file.

Functions

void | ADC2_ClearFlag (void)
Clear the ADC2 EOC Flag.
void | ADC2_ClearITPendingBit (void)
Clear the ADC2 End of Conversion pending bit.
void | ADC2_Cmd (FunctionalState NewState)
Enables or Disables the ADC2 peripheral.
void | ADC2_ConversionConfig (ADC2_ConvMode_TypeDef ADC2_ConversionMode, ADC2_Channel_TypeDef ADC2_Channel, ADC2_Align_TypeDef ADC2_Align)
Configure the ADC2 conversion on selected channel.
void | ADC2_DeInit (void)
Deinitializes the ADC2 peripheral registers to their default reset values.
void | ADC2_ExternalTriggerConfig (ADC2_ExtTrig_TypeDef ADC2_ExtTrigger, FunctionalState NewState)
Configure the ADC2 conversion on external trigger event.
uint16_t | ADC2_GetConversionValue (void)
Get one sample of measured signal.
FlagStatus | ADC2_GetFlagStatus (void)
Checks the ADC2 EOC flag status.
ITStatus | ADC2_GetITStatus (void)
Returns the EOC pending bit status.
void | ADC2_Init (ADC2_ConvMode_TypeDef ADC2_ConversionMode, ADC2_Channel_TypeDef ADC2_Channel, ADC2_PresSel_TypeDef ADC2_PrescalerSelection, ADC2_ExtTrig_TypeDef ADC2_ExtTrigger, FunctionalState ADC2_ExtTriggerState, ADC2_Align_TypeDef ADC2_Align, ADC2_SchmittTrigg_TypeDef ADC2_SchmittTriggerChannel, FunctionalState ADC2_SchmittTriggerState)
Initializes the ADC2 peripheral according to the specified parameters.
void | ADC2_ITConfig (FunctionalState NewState)
Enables or disables the ADC2 interrupt.
void | ADC2_PrescalerConfig (ADC2_PresSel_TypeDef ADC2_Prescaler)
Configure the ADC2 prescaler division factor.
void | ADC2_SchmittTriggerConfig (ADC2_SchmittTrigg_TypeDef ADC2_SchmittTriggerChannel, FunctionalState NewState)
Enables or disables the ADC2 Schmitt Trigger on a selected channel.
void | ADC2_StartConversion (void)
Start ADC2 conversion.

Detailed Description

This file contains all the functions/macros for the ADC2 peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_adc2.c.


STM8S/A Standard Peripherals Drivers: stm8s_adc2.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions
stm8s_adc2.h File Reference

This file contains all the prototypes/macros for the ADC2 peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_ADC2_ALIGN_OK(ALIGN)
Macro used by the assert function to check the different alignment modes.
#define | IS_ADC2_CHANNEL_OK(CHANNEL)
Macro used by the assert function to check the different channels values.
#define | IS_ADC2_CONVERSIONMODE_OK(MODE)
Macro used by the assert function to check the different conversion modes.
#define | IS_ADC2_EXTTRIG_OK(EXTRIG)
Macro used by the assert function to check the different external trigger values.
#define | IS_ADC2_PRESSEL_OK(PRESCALER)
Macro used by the assert function to check the different prescaler's values.
#define | IS_ADC2_SCHMITTTRIG_OK(SCHMITTTRIG)
Macro used by the assert function to check the different schmitt trigger values.

Enumerations

enum | ADC2_Align_TypeDef { ADC2_ALIGN_LEFT = (uint8_t)0x00, ADC2_ALIGN_RIGHT = (uint8_t)0x08 }
ADC2 data alignment. More...
enum ADC2_Channel_TypeDef {
ADC2_CHANNEL_0 = (uint8_t)0x00, ADC2_CHANNEL_1 = (uint8_t)0x01, ADC2_CHANNEL_2 = (uint8_t)0x02, ADC2_CHANNEL_3 = (uint8_t)0x03,
ADC2_CHANNEL_4 = (uint8_t)0x04, ADC2_CHANNEL_5 = (uint8_t)0x05, ADC2_CHANNEL_6 = (uint8_t)0x06, ADC2_CHANNEL_7 = (uint8_t)0x07,
ADC2_CHANNEL_8 = (uint8_t)0x08, ADC2_CHANNEL_9 = (uint8_t)0x09, ADC2_CHANNEL_10 = (uint8_t)0x0A, ADC2_CHANNEL_11 = (uint8_t)0x0B,
ADC2_CHANNEL_12 = (uint8_t)0x0C, ADC2_CHANNEL_13 = (uint8_t)0x0D, ADC2_CHANNEL_14 = (uint8_t)0x0E, ADC2_CHANNEL_15 = (uint8_t)0x0F
}
ADC2 analog channel selection. More...
enum | ADC2_ConvMode_TypeDef { ADC2_CONVERSIONMODE_SINGLE = (uint8_t)0x00, ADC2_CONVERSIONMODE_CONTINUOUS = (uint8_t)0x01 }
ADC2 conversion mode selection. More...
enum | ADC2_ExtTrig_TypeDef { ADC2_EXTTRIG_TIM = (uint8_t)0x00, ADC2_EXTTRIG_GPIO = (uint8_t)0x01 }
ADC2 External conversion trigger event selection. More...
enum ADC2_PresSel_TypeDef {
ADC2_PRESSEL_FCPU_D2 = (uint8_t)0x00, ADC2_PRESSEL_FCPU_D3 = (uint8_t)0x10, ADC2_PRESSEL_FCPU_D4 = (uint8_t)0x20, ADC2_PRESSEL_FCPU_D6 = (uint8_t)0x30,
ADC2_PRESSEL_FCPU_D8 = (uint8_t)0x40, ADC2_PRESSEL_FCPU_D10 = (uint8_t)0x50, ADC2_PRESSEL_FCPU_D12 = (uint8_t)0x60, ADC2_PRESSEL_FCPU_D18 = (uint8_t)0x70
}
ADC2 clock prescaler selection. More...
enum ADC2_SchmittTrigg_TypeDef {
ADC2_SCHMITTTRIG_CHANNEL0 = (uint8_t)0x00, ADC2_SCHMITTTRIG_CHANNEL1 = (uint8_t)0x01, ADC2_SCHMITTTRIG_CHANNEL2 = (uint8_t)0x02, ADC2_SCHMITTTRIG_CHANNEL3 = (uint8_t)0x03,
ADC2_SCHMITTTRIG_CHANNEL4 = (uint8_t)0x04, ADC2_SCHMITTTRIG_CHANNEL5 = (uint8_t)0x05, ADC2_SCHMITTTRIG_CHANNEL6 = (uint8_t)0x06, ADC2_SCHMITTTRIG_CHANNEL7 = (uint8_t)0x07,
ADC2_SCHMITTTRIG_CHANNEL8 = (uint8_t)0x08, ADC2_SCHMITTTRIG_CHANNEL9 = (uint8_t)0x09, ADC2_SCHMITTTRIG_CHANNEL10 = (uint8_t)0x0A, ADC2_SCHMITTTRIG_CHANNEL11 = (uint8_t)0x0B,
ADC2_SCHMITTTRIG_CHANNEL12 = (uint8_t)0x0C, ADC2_SCHMITTTRIG_CHANNEL13 = (uint8_t)0x0D, ADC2_SCHMITTTRIG_CHANNEL14 = (uint8_t)0x0E, ADC2_SCHMITTTRIG_CHANNEL15 = (uint8_t)0x0F,
ADC2_SCHMITTTRIG_ALL = (uint8_t)0x1F
}
ADC2 schmitt Trigger. More...

Functions

void | ADC2_ClearFlag (void)
Clear the ADC2 EOC Flag.
void | ADC2_ClearITPendingBit (void)
Clear the ADC2 End of Conversion pending bit.
void | ADC2_Cmd (FunctionalState NewState)
Enables or Disables the ADC2 peripheral.
void | ADC2_ConversionConfig (ADC2_ConvMode_TypeDef ADC2_ConversionMode, ADC2_Channel_TypeDef ADC2_Channel, ADC2_Align_TypeDef ADC2_Align)
Configure the ADC2 conversion on selected channel.
void | ADC2_DeInit (void)
Deinitializes the ADC2 peripheral registers to their default reset values.
void | ADC2_ExternalTriggerConfig (ADC2_ExtTrig_TypeDef ADC2_ExtTrigger, FunctionalState NewState)
Configure the ADC2 conversion on external trigger event.
uint16_t | ADC2_GetConversionValue (void)
Get one sample of measured signal.
FlagStatus | ADC2_GetFlagStatus (void)
Checks the ADC2 EOC flag status.
ITStatus | ADC2_GetITStatus (void)
Returns the EOC pending bit status.
void | ADC2_Init (ADC2_ConvMode_TypeDef ADC2_ConversionMode, ADC2_Channel_TypeDef ADC2_Channel, ADC2_PresSel_TypeDef ADC2_PrescalerSelection, ADC2_ExtTrig_TypeDef ADC2_ExtTrigger, FunctionalState ADC2_ExtTriggerState, ADC2_Align_TypeDef ADC2_Align, ADC2_SchmittTrigg_TypeDef ADC2_SchmittTriggerChannel, FunctionalState ADC2_SchmittTriggerState)
Initializes the ADC2 peripheral according to the specified parameters.
void | ADC2_ITConfig (FunctionalState NewState)
Enables or disables the ADC2 interrupt.
void | ADC2_PrescalerConfig (ADC2_PresSel_TypeDef ADC2_Prescaler)
Configure the ADC2 prescaler division factor.
void | ADC2_SchmittTriggerConfig (ADC2_SchmittTrigg_TypeDef ADC2_SchmittTriggerChannel, FunctionalState NewState)
Enables or disables the ADC2 Schmitt Trigger on a selected channel.
void | ADC2_StartConversion (void)
Start ADC2 conversion.

Detailed Description

This file contains all the prototypes/macros for the ADC2 peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_adc2.h.


STM8S/A Standard Peripherals Drivers: stm8s_awu.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions | Variables
stm8s_awu.c File Reference

This file contains all the functions for the AWU peripheral. More...

#include "stm8s_awu.h"

Go to the source code of this file.

Functions

void | AWU_Cmd (FunctionalState NewState)
Enable or disable the AWU peripheral.
void | AWU_DeInit (void)
Deinitializes the AWU peripheral registers to their default reset values.
FlagStatus | AWU_GetFlagStatus (void)
Returns status of the AWU peripheral flag.
void | AWU_IdleModeEnable (void)
Configures AWU in Idle mode to reduce power consumption.
void | AWU_Init (AWU_Timebase_TypeDef AWU_TimeBase)
Initializes the AWU peripheral according to the specified parameters.
void | AWU_LSICalibrationConfig (uint32_t LSIFreqHz)
Update APR register with the measured LSI frequency.

Variables

CONST uint8_t | APR_Array [17]
Contains the different values to write in the APR register (used by AWU_Init function)
CONST uint8_t | TBR_Array [17]
Contains the different values to write in the TBR register (used by AWU_Init function)

Detailed Description

This file contains all the functions for the AWU peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_awu.c.


STM8S/A Standard Peripherals Drivers: stm8s_awu.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions
stm8s_awu.h File Reference

This file contains all functions prototype and macros for the AWU peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_AWU_TIMEBASE_OK(TB)
Macro used by the assert function to check the different functions parameters.
#define | IS_LSI_FREQUENCY_OK(FREQ)
Macro used by the assert function to check the LSI frequency (in Hz)
#define | LSI_FREQUENCY_MAX ((uint32_t)150000)
#define | LSI_FREQUENCY_MIN ((uint32_t)110000)

Enumerations

enum AWU_Timebase_TypeDef {
AWU_TIMEBASE_NO_IT = (uint8_t)0, AWU_TIMEBASE_250US = (uint8_t)1, AWU_TIMEBASE_500US = (uint8_t)2, AWU_TIMEBASE_1MS = (uint8_t)3,
AWU_TIMEBASE_2MS = (uint8_t)4, AWU_TIMEBASE_4MS = (uint8_t)5, AWU_TIMEBASE_8MS = (uint8_t)6, AWU_TIMEBASE_16MS = (uint8_t)7,
AWU_TIMEBASE_32MS = (uint8_t)8, AWU_TIMEBASE_64MS = (uint8_t)9, AWU_TIMEBASE_128MS = (uint8_t)10, AWU_TIMEBASE_256MS = (uint8_t)11,
AWU_TIMEBASE_512MS = (uint8_t)12, AWU_TIMEBASE_1S = (uint8_t)13, AWU_TIMEBASE_2S = (uint8_t)14, AWU_TIMEBASE_12S = (uint8_t)15,
AWU_TIMEBASE_30S = (uint8_t)16
}
AWU TimeBase selection. More...

Functions

void | AWU_Cmd (FunctionalState NewState)
Enable or disable the AWU peripheral.
void | AWU_DeInit (void)
Deinitializes the AWU peripheral registers to their default reset values.
FlagStatus | AWU_GetFlagStatus (void)
Returns status of the AWU peripheral flag.
void | AWU_IdleModeEnable (void)
Configures AWU in Idle mode to reduce power consumption.
void | AWU_Init (AWU_Timebase_TypeDef AWU_TimeBase)
Initializes the AWU peripheral according to the specified parameters.
void | AWU_LSICalibrationConfig (uint32_t LSIFreqHz)
Update APR register with the measured LSI frequency.

Detailed Description

This file contains all functions prototype and macros for the AWU peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_awu.h.


STM8S/A Standard Peripherals Drivers: stm8s_beep.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions
stm8s_beep.c File Reference

This file contains all the functions for the BEEP peripheral. More...

#include "stm8s_beep.h"

Go to the source code of this file.

Functions

void | BEEP_Cmd (FunctionalState NewState)
Enable or disable the BEEP function.
void | BEEP_DeInit (void)
Deinitializes the BEEP peripheral registers to their default reset values.
void | BEEP_Init (BEEP_Frequency_TypeDef BEEP_Frequency)
Initializes the BEEP function according to the specified parameters.
void | BEEP_LSICalibrationConfig (uint32_t LSIFreqHz)
Update CSR register with the measured LSI frequency.

Detailed Description

This file contains all the functions for the BEEP peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_beep.c.


STM8S/A Standard Peripherals Drivers: stm8s_beep.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions
stm8s_beep.h File Reference

This file contains all functions prototype and macros for the BEEP peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | BEEP_CALIBRATION_DEFAULT ((uint8_t)0x0B)
#define | IS_BEEP_FREQUENCY_OK(FREQ)
Macro used by the assert function to check the different functions parameters.
#define | IS_LSI_FREQUENCY_OK(FREQ)
Macro used by the assert function to check the LSI frequency (in Hz).
#define | LSI_FREQUENCY_MAX ((uint32_t)150000)
#define | LSI_FREQUENCY_MIN ((uint32_t)110000)

Enumerations

enum | BEEP_Frequency_TypeDef { BEEP_FREQUENCY_1KHZ = (uint8_t)0x00, BEEP_FREQUENCY_2KHZ = (uint8_t)0x40, BEEP_FREQUENCY_4KHZ = (uint8_t)0x80 }
BEEP Frequency selection. More...

Functions

void | BEEP_Cmd (FunctionalState NewState)
Enable or disable the BEEP function.
void | BEEP_DeInit (void)
Deinitializes the BEEP peripheral registers to their default reset values.
void | BEEP_Init (BEEP_Frequency_TypeDef BEEP_Frequency)
Initializes the BEEP function according to the specified parameters.
void | BEEP_LSICalibrationConfig (uint32_t LSIFreqHz)
Update CSR register with the measured LSI frequency.

Detailed Description

This file contains all functions prototype and macros for the BEEP peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_beep.h.


STM8S/A Standard Peripherals Drivers: stm8s_can.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Defines | Functions | Variables
stm8s_can.c File Reference

This file contains all the functions for the CAN peripheral. More...

#include "stm8s_can.h"

Go to the source code of this file.

Defines

#define | CAN_ACKNOWLEDGE_TIMEOUT ((uint16_t)0xFFFF)
#define | CAN_IDLIST_IDMASK_MASK ((uint8_t) 0x55)
#define | CAN_IDMASK_IDLIST_MASK ((uint8_t) 0xAA)
#define | CAN_MODE_MASK ((uint8_t) 0x03)

Functions

void | CAN_CancelTransmit (CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox)
Cancels a transmit request.
void | CAN_ClearFlag (CAN_FLAG_TypeDef CAN_Flag)
Clears the CAN's pending flags.
void | CAN_ClearITPendingBit (CAN_IT_TypeDef CAN_IT)
Clears the CAN’s interrupt pending bits.
void | CAN_DeInit (void)
Deinitializes the CAN peripheral registers to their default reset values.
void | CAN_FIFORelease (void)
Releases the CAN FIFO.
void | CAN_FilterInit (CAN_FilterNumber_TypeDef CAN_FilterNumber, FunctionalState CAN_FilterActivation, CAN_FilterMode_TypeDef CAN_FilterMode, CAN_FilterScale_TypeDef CAN_FilterScale, uint8_t CAN_FilterID1, uint8_t CAN_FilterID2, uint8_t CAN_FilterID3, uint8_t CAN_FilterID4, uint8_t CAN_FilterIDMask1, uint8_t CAN_FilterIDMask2, uint8_t CAN_FilterIDMask3, uint8_t CAN_FilterIDMask4)
Initializes the CAN peripheral Filter according to the specified parameters.
FlagStatus | CAN_GetFlagStatus (CAN_FLAG_TypeDef CAN_Flag)
Checks whether the specified CAN flag is set or not.
ITStatus | CAN_GetITStatus (CAN_IT_TypeDef CAN_IT)
Checks whether the specified CAN interrupt has occurred or not.
CAN_ErrorCode_TypeDef | CAN_GetLastErrorCode (void)
Gets the Last Error Code.
uint16_t | CAN_GetMessageTimeStamp (void)
Returns the Received time stamp.
uint8_t | CAN_GetReceivedData (uint8_t CAN_DataIndex)
Gets the CAN Data of the received message.
uint8_t | CAN_GetReceivedDLC (void)
Gets the CAN DLC of the received message.
uint8_t | CAN_GetReceivedFMI (void)
Gets the CAN FMI of the received message.
uint32_t | CAN_GetReceivedId (void)
Gets the CAN Id of the received message.
CAN_Id_TypeDef | CAN_GetReceivedIDE (void)
Gets the CAN IDE of the received message.
CAN_RTR_TypeDef | CAN_GetReceivedRTR (void)
Gets the CAN RTR of the received message.
CAN_Page_TypeDef | CAN_GetSelectedPage (void)
Gets the selected registers page.
CAN_InitStatus_TypeDef | CAN_Init (CAN_MasterCtrl_TypeDef CAN_MasterCtrl, CAN_Mode_TypeDef CAN_Mode, CAN_SynJumpWidth_TypeDef CAN_SynJumpWidth, CAN_BitSeg1_TypeDef CAN_BitSeg1, CAN_BitSeg2_TypeDef CAN_BitSeg2, uint8_t CAN_Prescaler)
Initializes the CAN peripheral according to the specified parameters.
void | CAN_ITConfig (CAN_IT_TypeDef CAN_IT, FunctionalState NewState)
Enables or disables the specified CAN interrupts.
CAN_NbrPendingMessage_TypeDef | CAN_MessagePending (void)
Returns the number of pending messages.
CAN_ModeStatus_TypeDef | CAN_OperatingModeRequest (CAN_OperatingMode_TypeDef CAN_OperatingMode)
Select the CAN Operation mode.
void | CAN_Receive (void)
Receives a message which contains CAN Id, IDE, RTR DLC, data and FMI number.
void | CAN_SelectPage (CAN_Page_TypeDef CAN_Page)
Sets the registers page to be selected.
CAN_Sleep_TypeDef | CAN_Sleep (void)
Enters the Sleep low power mode.
void | CAN_ST7CompatibilityCmd (CAN_ST7Compatibility_TypeDef CAN_ST7Compatibility)
Enables or Disables the ST7 CAN Compatibility.
CAN_TxStatus_TypeDef | CAN_Transmit (uint32_t CAN_Id, CAN_Id_TypeDef CAN_IDE, CAN_RTR_TypeDef CAN_RTR, uint8_t CAN_DLC, uint8_t *CAN_Data)
Initiates the transmission of a message.
CAN_TxStatus_TypeDef | CAN_TransmitStatus (CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox)
Checks the transmission of a message.
void | CAN_TTComModeCmd (FunctionalState NewState)
Enables or disables the CAN Time TriggerOperation communication mode.
CAN_WakeUp_TypeDef | CAN_WakeUp (void)
Wakes the CAN up.
static ITStatus | CheckITStatus (uint8_t CAN_Reg, uint8_t It_Bit)
Checks whether the CAN interrupt has occurred or not.

Variables

__IO uint8_t | _Data [8] = {0}
__IO uint8_t | _DLC = 0
__IO uint8_t | _FMI = 0
__IO uint32_t | _Id = 0
__IO uint8_t | _IDE = 0
__IO uint8_t | _RTR = 0

Detailed Description

This file contains all the functions for the CAN peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_can.c.


STM8S/A Standard Peripherals Drivers: stm8s_can.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions
stm8s_can.h File Reference

This file contains all the functions for the CAN peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | CAN_DLC_MAX ((uint8_t)0x08)
#define | CAN_EXTID_SIZE ((uint32_t)0x1FFFFFFF)
#define | CAN_IT_CONFIG_MASK ~(uint16_t)(CAN_IT_TME|CAN_IT_FMP|CAN_IT_FF|CAN_IT_FOV|CAN_IT_WKU|CAN_IT_EWG|CAN_IT_EPV|CAN_IT_BOF|CAN_IT_LEC|CAN_IT_ERR)
Macro used by the assert function in order to check the CAN Configuration interrupts.
#define | CAN_STDID_SIZE ((uint16_t)0x07FF)
#define | IS_CAN_BITSEG1_OK(BS1) ((BS1) <= CAN_BitSeg1_16TimeQuantum)
Macro used by the assert function in order to check time quantum in bit segment 1 .
#define | IS_CAN_BITSEG2_OK(BS2) ((((BS2) >= CAN_BitSeg2_2TimeQuantum) && ((BS2) <= CAN_BitSeg2_8TimeQuantum))|| ((BS2) == CAN_BitSeg2_1TimeQuantum))
Macro used by the assert function in order to check time quantum in bit segment 2.
#define | IS_CAN_DLC_OK(DLC) ((DLC) <= CAN_DLC_MAX)
Macro used by the assert function in order to check the DLC to be sent.
#define | IS_CAN_EXTID_OK(EXTID) ((EXTID) <= ((uint32_t)CAN_EXTID_SIZE))
Macro used by the assert function in order to check the Extended ID to be sent.
#define | IS_CAN_FILTER_MODE_OK(MODE)
Macro used by the assert function in order to check CAN filter mode.
#define | IS_CAN_FILTER_NUMBER_OK(NUMBER)
Macro used by the assert function in order to check CAN filter number.
#define | IS_CAN_FILTER_SCALE_OK(SCALE)
Macro used by the assert function in order to check CAN filter scale.
#define | IS_CAN_FLAG_CLEAR_OK(FLAG)
Macro used by the assert function in order to check CAN flags which can be cleared by CAN_ClearFlag.
#define | IS_CAN_FLAG_STATUS_OK(FLAG)
Macro used by the assert function in order to check CAN flags which can be got by CAN_GetFlagStatus.
#define | IS_CAN_IDTYPE_OK(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || ((IDTYPE) == CAN_Id_Extended))
Macro used by the assert function in order to check the type of the ID to be sent.
#define | IS_CAN_IT_CONFIG_OK(IT) (((IT) != 0x0000) && ((uint16_t)((uint16_t)(IT) & (uint16_t)CAN_IT_CONFIG_MASK) == 0x0000))
#define | IS_CAN_IT_PENDING_BIT_OK(IT)
Macro used by the assert function in order to check the CAN Pending bit interrupts.
#define | IS_CAN_IT_STATUS_OK(IT)
Macro used by the assert function in order to check the CAN status interrupts.
#define | IS_CAN_LAST_ERROR_CODE_OK(CODE) (((CODE) & 0x8F) == 0x00)
Macro used by the assert function in order to check the Last Error Code.
#define | IS_CAN_MASTERCTRL_OK(MODE)
Macro used by the assert function in order to check CAN Time Triggered Communication mode.
#define | IS_CAN_MODE_OK(MODE)
Macro used by the assert function in order to check CAN mode options .
#define | IS_CAN_OPERATINGMODE_OK(MODE)
Macro used by the assert function in order to check CAN operating mode.
#define | IS_CAN_PRESCALER_OK(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 64))
Macro used by the assert function in order to check CAN clock prescaler.
#define | IS_CAN_RTR_OK(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
Macro used by the assert function in order to check CAN transmission Frame Type.
#define | IS_CAN_ST7_COMPATIBILITY_OK(STATE) (((STATE) == CAN_ST7Compatibility_Enable) || ((STATE) == CAN_ST7Compatibility_Disable))
Macro used by the assert function in order to check the CAN ST7 Compatibility parameters.
#define | IS_CAN_STDID_OK(STDID) ((STDID) <= ((uint16_t)CAN_STDID_SIZE))
Macro used by the assert function in order to check the Standard ID to be sent.
#define | IS_CAN_SYNJUMPWIDTH_OK(SJW)
Macro used by the assert function in order to check the CAN synchronisation jump width (SJW).
#define | IS_CAN_TRANSMITMAILBOX_OK(TRANSMITMAILBOX)
Macro used by the assert function in order to check CAN Tx mailboxes.

Enumerations

enum CAN_BitSeg1_TypeDef {
CAN_BitSeg1_1TimeQuantum = ((uint8_t)0x00), CAN_BitSeg1_2TimeQuantum = ((uint8_t)0x01), CAN_BitSeg1_3TimeQuantum = ((uint8_t)0x02), CAN_BitSeg1_4TimeQuantum = ((uint8_t)0x03),
CAN_BitSeg1_5TimeQuantum = ((uint8_t)0x04), CAN_BitSeg1_6TimeQuantum = ((uint8_t)0x05), CAN_BitSeg1_7TimeQuantum = ((uint8_t)0x06), CAN_BitSeg1_8TimeQuantum = ((uint8_t)0x07),
CAN_BitSeg1_9TimeQuantum = ((uint8_t)0x08), CAN_BitSeg1_10TimeQuantum = ((uint8_t)0x09), CAN_BitSeg1_11TimeQuantum = ((uint8_t)0x0A), CAN_BitSeg1_12TimeQuantum = ((uint8_t)0x0B),
CAN_BitSeg1_13TimeQuantum = ((uint8_t)0x0C), CAN_BitSeg1_14TimeQuantum = ((uint8_t)0x0D), CAN_BitSeg1_15TimeQuantum = ((uint8_t)0x0E), CAN_BitSeg1_16TimeQuantum = ((uint8_t)0x0F)
}
time quantum in bit segment 1 More...
enum CAN_BitSeg2_TypeDef {
CAN_BitSeg2_1TimeQuantum = ((uint8_t)0x00), CAN_BitSeg2_2TimeQuantum = ((uint8_t)0x10), CAN_BitSeg2_3TimeQuantum = ((uint8_t)0x20), CAN_BitSeg2_4TimeQuantum = ((uint8_t)0x30),
CAN_BitSeg2_5TimeQuantum = ((uint8_t)0x40), CAN_BitSeg2_6TimeQuantum = ((uint8_t)0x50), CAN_BitSeg2_7TimeQuantum = ((uint8_t)0x60), CAN_BitSeg2_8TimeQuantum = ((uint8_t)0x70)
}
time quantum in bit segment 2 More...
enum CAN_ErrorCode_TypeDef {
CAN_ErrorCode_NoErr = ((uint8_t)0x00), CAN_ErrorCode_StuffErr = ((uint8_t)0x10), CAN_ErrorCode_FormErr = ((uint8_t)0x20), CAN_ErrorCode_ACKErr = ((uint8_t)0x30),
CAN_ErrorCode_BitRecessiveErr = ((uint8_t)0x40), CAN_ErrorCode_BitDominantErr = ((uint8_t)0x50), CAN_ErrorCode_CRCErr = ((uint8_t)0x60), CAN_ErrorCode_SoftwareSetErr = ((uint8_t)0x70)
}
CAN Error Code description. More...
enum | CAN_FilterMode_TypeDef { CAN_FilterMode_IdMask = ((uint8_t)0x00), CAN_FilterMode_IdMask_IdList = ((uint8_t)0x10), CAN_FilterMode_IdList_IdMask = ((uint8_t)0x11), CAN_FilterMode_IdList = ((uint8_t)0x01) }
CAN filter mode. More...
enum CAN_FilterNumber_TypeDef {
CAN_FilterNumber_0 = ((uint8_t)0x00), CAN_FilterNumber_1 = ((uint8_t)0x01), CAN_FilterNumber_2 = ((uint8_t)0x02), CAN_FilterNumber_3 = ((uint8_t)0x03),
CAN_FilterNumber_4 = ((uint8_t)0x04), CAN_FilterNumber_5 = ((uint8_t)0x05)
}
CAN filter number. More...
enum | CAN_FilterScale_TypeDef { CAN_FilterScale_8Bit = ((uint8_t)0x00), CAN_FilterScale_16_8Bit = ((uint8_t)0x02), CAN_FilterScale_16Bit = ((uint8_t)0x04), CAN_FilterScale_32Bit = ((uint8_t)0x06) }
CAN filter scale. More...
enum CAN_FLAG_TypeDef {
CAN_FLAG_RQCP0 = ((uint16_t)0x3401), CAN_FLAG_RQCP1 = ((uint16_t)0x3402), CAN_FLAG_RQCP2 = ((uint16_t)0x3404), CAN_FLAG_FMP = ((uint16_t)0x1203),
CAN_FLAG_FF = ((uint16_t)0x3208), CAN_FLAG_FOV = ((uint16_t)0x3210), CAN_FLAG_WKU = ((uint16_t)0x3108), CAN_FLAG_EWG = ((uint16_t)0x1001),
CAN_FLAG_EPV = ((uint16_t)0x1002), CAN_FLAG_BOF = ((uint16_t)0x1004), CAN_FLAG_LEC = ((uint16_t)0x3070)
}
CAN flags. More...
enum | CAN_Id_TypeDef { CAN_Id_Standard = ((uint8_t)0x00), CAN_Id_Extended = ((uint8_t)0x40) }
CAN identifier type. More...
enum | CAN_InitStatus_TypeDef { CAN_InitStatus_Failed = 0, CAN_InitStatus_Success = ! CAN_InitStatus_Failed }
CAN sleep constants. More...
enum CAN_IT_TypeDef {
CAN_IT_TME = ((uint16_t)0x0001), CAN_IT_FMP = ((uint16_t)0x0002), CAN_IT_FF = ((uint16_t)0x0004), CAN_IT_FOV = ((uint16_t)0x0008),
CAN_IT_WKU = ((uint16_t)0x0080), CAN_IT_ERR = ((uint16_t)0x4000), CAN_IT_EWG = ((uint16_t)0x0100), CAN_IT_EPV = ((uint16_t)0x0200),
CAN_IT_BOF = ((uint16_t)0x0400), CAN_IT_LEC = ((uint16_t)0x0800)
}
CAN interrupts. More...
enum CAN_MasterCtrl_TypeDef {
CAN_MasterCtrl_AllDisabled = ((uint8_t)0x00), CAN_MasterCtrl_AllEnabled = ((uint8_t)0xFC), CAN_MasterCtrl_TimeTriggerCOMMode = ((uint8_t)0x80), CAN_MasterCtrl_AutoBusOffManagement = ((uint8_t)0x40),
CAN_MasterCtrl_AutoWakeUpMode = ((uint8_t)0x20), CAN_MasterCtrl_NoAutoReTx = ((uint8_t)0x10), CAN_MasterCtrl_RxFifoLockedMode = ((uint8_t)0x08), CAN_MasterCtrl_TxFifoPriority = ((uint8_t)0x04)
}
CAN Time Triggered Communication mode. More...
enum | CAN_Mode_TypeDef { CAN_Mode_Normal = ((uint8_t)0x00), CAN_Mode_LoopBack = ((uint8_t)0x01), CAN_Mode_Silent = ((uint8_t)0x02), CAN_Mode_Silent_LoopBack = ((uint8_t)0x03) }
CAN mode options. More...
enum | CAN_ModeStatus_TypeDef { CAN_ModeStatus_Failed = ((uint8_t)0x00), CAN_ModeStatus_Success = ! CAN_ModeStatus_Failed }
CAN operating mode status. More...
enum | CAN_NbrPendingMessage_TypeDef { CAN_NbrPendingMessage_0 = ((uint8_t)0x00), CAN_NbrPendingMessage_1 = ((uint8_t)0x01), CAN_NbrPendingMessage_2 = ((uint8_t)0x02), CAN_NbrPendingMessage_3 = ((uint8_t)0x03) }
CAN Pending Messages number. More...
enum | CAN_OperatingMode_TypeDef { CAN_OperatingMode_Initialization = ((uint8_t)0x00), CAN_OperatingMode_Normal = ((uint8_t)0x01), CAN_OperatingMode_Sleep = ((uint8_t)0x02) }
CAN operating mode. More...
enum CAN_Page_TypeDef {
CAN_Page_TxMailBox0 = ((uint8_t) 0), CAN_Page_TxMailBox1 = ((uint8_t) 1), CAN_Page_TxMailBox2 = ((uint8_t) 5), CAN_Page_Filter01 = ((uint8_t) 2),
CAN_Page_Filter23 = ((uint8_t) 3), CAN_Page_Filter45 = ((uint8_t) 4), CAN_Page_Config = ((uint8_t) 6), CAN_Page_RxFifo = ((uint8_t) 7)
}
CAN Page Mapping. More...
enum | CAN_RTR_TypeDef { CAN_RTR_Data = ((uint8_t)0x00), CAN_RTR_Remote = ((uint8_t)0x20) }
CAN remote transmission request. More...
enum | CAN_Sleep_TypeDef { CAN_Sleep_Failed = ((uint8_t)0x00), CAN_Sleep_Ok = ((uint8_t)0x01) }
CAN sleep Status. More...
enum | CAN_ST7Compatibility_TypeDef { CAN_ST7Compatibility_Enable = ((uint8_t)0x00), CAN_ST7Compatibility_Disable = ((uint8_t)0x10) }
CAN ST7 Compatibility. More...
enum | CAN_SynJumpWidth_TypeDef { CAN_SynJumpWidth_1TimeQuantum = ((uint8_t)0x00), CAN_SynJumpWidth_2TimeQuantum = ((uint8_t)0x40), CAN_SynJumpWidth_3TimeQuantum = ((uint8_t)0x80), CAN_SynJumpWidth_4TimeQuantum = ((uint8_t)0xC0) }
CAN synchronisation jump width (SJW) More...
enum | CAN_TransmitMailBox_TypeDef { CAN_TransmitMailBox_0 = ((uint8_t) 0x00), CAN_TransmitMailBox_1 = ((uint8_t) 0x01), CAN_TransmitMailBox_2 = ((uint8_t) 0x05) }
CAN Tx mailboxes. More...
enum CAN_TxStatus_TypeDef {
CAN_TxStatus_Failed = ((uint8_t)0xF0), CAN_TxStatus_Ok = ((uint8_t)0xF1), CAN_TxStatus_Pending = ((uint8_t)0xF2), CAN_TxStatus_NoMailBox = ((uint8_t)0xF4),
CAN_TxStatus_MailBoxEmpty = ((uint8_t)0xF5), CAN_TxStatus_MailBox0Ok = ((uint8_t)0x00), CAN_TxStatus_MailBox1Ok = ((uint8_t)0x01), CAN_TxStatus_MailBox2Ok = ((uint8_t)0x05)
}
CAN transmit Status. More...
enum | CAN_WakeUp_TypeDef { CAN_WakeUp_Failed = ((uint8_t)0x00), CAN_WakeUp_Ok = ((uint8_t)0x01) }
CAN wake up status. More...

Functions

void | CAN_CancelTransmit (CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox)
Cancels a transmit request.
void | CAN_ClearFlag (CAN_FLAG_TypeDef CAN_Flag)
Clears the CAN's pending flags.
void | CAN_ClearITPendingBit (CAN_IT_TypeDef CAN_IT)
Clears the CAN’s interrupt pending bits.
void | CAN_DeInit (void)
Deinitializes the CAN peripheral registers to their default reset values.
void | CAN_FIFORelease (void)
Releases the CAN FIFO.
void | CAN_FilterInit (CAN_FilterNumber_TypeDef CAN_FilterNumber, FunctionalState CAN_FilterActivation, CAN_FilterMode_TypeDef CAN_FilterMode, CAN_FilterScale_TypeDef CAN_FilterScale, uint8_t CAN_FilterID1, uint8_t CAN_FilterID2, uint8_t CAN_FilterID3, uint8_t CAN_FilterID4, uint8_t CAN_FilterIDMask1, uint8_t CAN_FilterIDMask2, uint8_t CAN_FilterIDMask3, uint8_t CAN_FilterIDMask4)
Initializes the CAN peripheral Filter according to the specified parameters.
FlagStatus | CAN_GetFlagStatus (CAN_FLAG_TypeDef CAN_Flag)
Checks whether the specified CAN flag is set or not.
ITStatus | CAN_GetITStatus (CAN_IT_TypeDef CAN_IT)
Checks whether the specified CAN interrupt has occurred or not.
CAN_ErrorCode_TypeDef | CAN_GetLastErrorCode (void)
Gets the Last Error Code.
uint16_t | CAN_GetMessageTimeStamp (void)
Returns the Received time stamp.
uint8_t | CAN_GetReceivedData (uint8_t CAN_DataIndex)
Gets the CAN Data of the received message.
uint8_t | CAN_GetReceivedDLC (void)
Gets the CAN DLC of the received message.
uint8_t | CAN_GetReceivedFMI (void)
Gets the CAN FMI of the received message.
uint32_t | CAN_GetReceivedId (void)
Gets the CAN Id of the received message.
CAN_Id_TypeDef | CAN_GetReceivedIDE (void)
Gets the CAN IDE of the received message.
CAN_RTR_TypeDef | CAN_GetReceivedRTR (void)
Gets the CAN RTR of the received message.
CAN_Page_TypeDef | CAN_GetSelectedPage (void)
Gets the selected registers page.
CAN_InitStatus_TypeDef | CAN_Init (CAN_MasterCtrl_TypeDef CAN_MasterCtrl, CAN_Mode_TypeDef CAN_Mode, CAN_SynJumpWidth_TypeDef CAN_SynJumpWidth, CAN_BitSeg1_TypeDef CAN_BitSeg1, CAN_BitSeg2_TypeDef CAN_BitSeg2, uint8_t CAN_Prescaler)
Initializes the CAN peripheral according to the specified parameters.
void | CAN_ITConfig (CAN_IT_TypeDef CAN_IT, FunctionalState NewState)
Enables or disables the specified CAN interrupts.
CAN_NbrPendingMessage_TypeDef | CAN_MessagePending (void)
Returns the number of pending messages.
CAN_ModeStatus_TypeDef | CAN_OperatingModeRequest (CAN_OperatingMode_TypeDef CAN_OperatingMode)
Select the CAN Operation mode.
void | CAN_Receive (void)
Receives a message which contains CAN Id, IDE, RTR DLC, data and FMI number.
void | CAN_SelectPage (CAN_Page_TypeDef CAN_Page)
Sets the registers page to be selected.
CAN_Sleep_TypeDef | CAN_Sleep (void)
Enters the Sleep low power mode.
void | CAN_ST7CompatibilityCmd (CAN_ST7Compatibility_TypeDef CAN_ST7Compatibility)
Enables or Disables the ST7 CAN Compatibility.
CAN_TxStatus_TypeDef | CAN_Transmit (uint32_t CAN_Id, CAN_Id_TypeDef CAN_IDE, CAN_RTR_TypeDef CAN_RTR, uint8_t CAN_DLC, uint8_t *CAN_Data)
Initiates the transmission of a message.
CAN_TxStatus_TypeDef | CAN_TransmitStatus (CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox)
Checks the transmission of a message.
void | CAN_TTComModeCmd (FunctionalState NewState)
Enables or disables the CAN Time TriggerOperation communication mode.
CAN_WakeUp_TypeDef | CAN_WakeUp (void)
Wakes the CAN up.

Detailed Description

This file contains all the functions for the CAN peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_can.h.

Define Documentation

#define CAN_DLC_MAX ((uint8_t)0x08)

Definition at line 38 of file stm8s_can.h.

#define CAN_EXTID_SIZE ((uint32_t)0x1FFFFFFF)

Definition at line 37 of file stm8s_can.h.

Referenced by CAN_Receive(), and CAN_Transmit().

#define CAN_STDID_SIZE ((uint16_t)0x07FF)

Definition at line 36 of file stm8s_can.h.

Referenced by CAN_Receive(), and CAN_Transmit().


STM8S/A Standard Peripherals Drivers: stm8s_clk.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions | Variables
stm8s_clk.c File Reference

This file contains all the functions for the CLK peripheral. More...

#include "stm8s_clk.h"

Go to the source code of this file.

Functions

void | CLK_AdjustHSICalibrationValue (CLK_HSITrimValue_TypeDef CLK_HSICalibrationValue)
Adjusts the Internal High Speed oscillator (HSI) calibration value.
void | CLK_CCOCmd (FunctionalState NewState)
Enables or disablle the Configurable Clock Output (CCO).
void | CLK_CCOConfig (CLK_Output_TypeDef CLK_CCO)
Output the selected clock on a dedicated I/O pin.
void | CLK_ClearITPendingBit (CLK_IT_TypeDef CLK_IT)
Clears the CLK’s interrupt pending bits.
void | CLK_ClockSecuritySystemEnable (void)
Enables the Clock Security System.
void | CLK_ClockSwitchCmd (FunctionalState NewState)
Starts or Stops manually the clock switch execution.
ErrorStatus | CLK_ClockSwitchConfig (CLK_SwitchMode_TypeDef CLK_SwitchMode, CLK_Source_TypeDef CLK_NewClock, FunctionalState ITState, CLK_CurrentClockState_TypeDef CLK_CurrentClockState)
configures the Switch from one clock to another
void | CLK_DeInit (void)
Deinitializes the CLK peripheral registers to their default reset values.
void | CLK_FastHaltWakeUpCmd (FunctionalState NewState)
Configures the High Speed Internal oscillator (HSI).
uint32_t | CLK_GetClockFreq (void)
This function returns the frequencies of different on chip clocks.
FlagStatus | CLK_GetFlagStatus (CLK_Flag_TypeDef CLK_FLAG)
Checks whether the specified CLK flag is set or not.
ITStatus | CLK_GetITStatus (CLK_IT_TypeDef CLK_IT)
Checks whether the specified CLK interrupt has is enabled or not.
CLK_Source_TypeDef | CLK_GetSYSCLKSource (void)
Returns the clock source used as system clock.
void | CLK_HSECmd (FunctionalState NewState)
Enable or Disable the External High Speed oscillator (HSE).
void | CLK_HSICmd (FunctionalState NewState)
Enables or disables the Internal High Speed oscillator (HSI).
void | CLK_HSIPrescalerConfig (CLK_Prescaler_TypeDef HSIPrescaler)
Configures the HSI clock dividers.
void | CLK_ITConfig (CLK_IT_TypeDef CLK_IT, FunctionalState NewState)
Enables or disables the specified CLK interrupts.
void | CLK_LSICmd (FunctionalState NewState)
Enables or disables the Internal Low Speed oscillator (LSI).
void | CLK_PeripheralClockConfig (CLK_Peripheral_TypeDef CLK_Peripheral, FunctionalState NewState)
Enables or disables the specified peripheral CLK.
void | CLK_SlowActiveHaltWakeUpCmd (FunctionalState NewState)
Configures the slow active halt wake up.
void | CLK_SWIMConfig (CLK_SWIMDivider_TypeDef CLK_SWIMDivider)
Configures the SWIM clock frequency on the fly.
void | CLK_SYSCLKConfig (CLK_Prescaler_TypeDef CLK_Prescaler)
Configures the HSI and CPU clock dividers.
void | CLK_SYSCLKEmergencyClear (void)
Reset the SWBSY flag (SWICR Register)

Variables

CONST uint8_t | CLKPrescTable [8] = {1, 2, 4, 8, 10, 16, 20, 40}
CONST uint8_t | HSIDivFactor [4] = {1, 2, 4, 8}

Detailed Description

This file contains all the functions for the CLK peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_clk.c.


STM8S/A Standard Peripherals Drivers: stm8s_clk.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions
stm8s_clk.h File Reference

This file contains all functions prototype and macros for the CLK peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | CLK_TIMEOUT ((uint16_t)0xFFFF)
#define | IS_CLK_CSSCONFIG_OK(CSSVALUE)
Macros used by the assert function in order to check the CSS configuration.
#define | IS_CLK_CURRENTCLOCKSTATE_OK(STATE)
Macros used by the assert function in order to check the current clock state.
#define | IS_CLK_FLAG_OK(FLAG)
Macros used by the assert function in order to check the different clock flags.
#define | IS_CLK_HSIPRESCALER_OK(PRESCALER)
Macros used by the assert function in order to check the different HSI prescaler values.
#define | IS_CLK_HSITRIMVALUE_OK(TRIMVALUE)
Macros used by the assert function in order to check the different HSI trimming values.
#define | IS_CLK_IT_OK(IT) (((IT) == CLK_IT_CSSD) || ((IT) == CLK_IT_SWIF))
Macros used by the assert function in order to check the different clock IT pending bits.
#define | IS_CLK_OUTPUT_OK(OUTPUT)
Macros used by the assert function in order to check the different clocks to output.
#define | IS_CLK_PERIPHERAL_OK(PERIPHERAL)
Macros used by the assert function in order to check the different peripheral's clock.
#define | IS_CLK_PRESCALER_OK(PRESCALER)
Macros used by the assert function in order to check the different clock prescaler values.
#define | IS_CLK_SOURCE_OK(SOURCE)
Macros used by the assert function in order to check the different clock sources.
#define | IS_CLK_SWIMDIVIDER_OK(SWIMDIVIDER) (((SWIMDIVIDER) == CLK_SWIMDIVIDER_2) || ((SWIMDIVIDER) == CLK_SWIMDIVIDER_OTHER))
Macros used by the assert function in order to check the different SWIM dividers values.
#define | IS_CLK_SWITCHMODE_OK(MODE) (((MODE) == CLK_SWITCHMODE_MANUAL) || ((MODE) == CLK_SWITCHMODE_AUTO))
Macros used by the assert function in order to check the different functions parameters.

Enumerations

enum | CLK_CSSConfig_TypeDef { CLK_CSSCONFIG_ENABLEWITHIT = (uint8_t)0x05, CLK_CSSCONFIG_ENABLE = (uint8_t)0x01, CLK_CSSCONFIG_DISABLE = (uint8_t)0x00 }
Clock security system configuration. More...
enum | CLK_CurrentClockState_TypeDef { CLK_CURRENTCLOCKSTATE_DISABLE = (uint8_t)0x00, CLK_CURRENTCLOCKSTATE_ENABLE = (uint8_t)0x01 }
Current Clock State. More...
enum CLK_Flag_TypeDef {
CLK_FLAG_LSIRDY = (uint16_t)0x0110, CLK_FLAG_HSIRDY = (uint16_t)0x0102, CLK_FLAG_HSERDY = (uint16_t)0x0202, CLK_FLAG_SWIF = (uint16_t)0x0308,
CLK_FLAG_SWBSY = (uint16_t)0x0301, CLK_FLAG_CSSD = (uint16_t)0x0408, CLK_FLAG_AUX = (uint16_t)0x0402, CLK_FLAG_CCOBSY = (uint16_t)0x0504,
CLK_FLAG_CCORDY = (uint16_t)0x0502
}
CLK Flags. More...
enum CLK_HSITrimValue_TypeDef {
CLK_HSITRIMVALUE_0 = (uint8_t)0x00, CLK_HSITRIMVALUE_1 = (uint8_t)0x01, CLK_HSITRIMVALUE_2 = (uint8_t)0x02, CLK_HSITRIMVALUE_3 = (uint8_t)0x03,
CLK_HSITRIMVALUE_4 = (uint8_t)0x04, CLK_HSITRIMVALUE_5 = (uint8_t)0x05, CLK_HSITRIMVALUE_6 = (uint8_t)0x06, CLK_HSITRIMVALUE_7 = (uint8_t)0x07
}
CLK HSI Calibration Value. More...
enum | CLK_IT_TypeDef { CLK_IT_CSSD = (uint8_t)0x0C, CLK_IT_SWIF = (uint8_t)0x1C }
CLK interrupt configuration and Flags cleared by software. More...
enum CLK_Output_TypeDef {
CLK_OUTPUT_HSI = (uint8_t)0x00, CLK_OUTPUT_LSI = (uint8_t)0x02, CLK_OUTPUT_HSE = (uint8_t)0x04, CLK_OUTPUT_CPU = (uint8_t)0x08,
CLK_OUTPUT_CPUDIV2 = (uint8_t)0x0A, CLK_OUTPUT_CPUDIV4 = (uint8_t)0x0C, CLK_OUTPUT_CPUDIV8 = (uint8_t)0x0E, CLK_OUTPUT_CPUDIV16 = (uint8_t)0x10,
CLK_OUTPUT_CPUDIV32 = (uint8_t)0x12, CLK_OUTPUT_CPUDIV64 = (uint8_t)0x14, CLK_OUTPUT_HSIRC = (uint8_t)0x16, CLK_OUTPUT_MASTER = (uint8_t)0x18,
CLK_OUTPUT_OTHERS = (uint8_t)0x1A
}
CLK Clock Output. More...
enum CLK_Peripheral_TypeDef {
CLK_PERIPHERAL_I2C = (uint8_t)0x00, CLK_PERIPHERAL_SPI = (uint8_t)0x01, CLK_PERIPHERAL_UART1 = (uint8_t)0x03, CLK_PERIPHERAL_UART2 = (uint8_t)0x03,
CLK_PERIPHERAL_UART3 = (uint8_t)0x03, CLK_PERIPHERAL_TIMER6 = (uint8_t)0x04, CLK_PERIPHERAL_TIMER4 = (uint8_t)0x04, CLK_PERIPHERAL_TIMER5 = (uint8_t)0x05,
CLK_PERIPHERAL_TIMER2 = (uint8_t)0x05, CLK_PERIPHERAL_TIMER3 = (uint8_t)0x06, CLK_PERIPHERAL_TIMER1 = (uint8_t)0x07, CLK_PERIPHERAL_AWU = (uint8_t)0x12,
CLK_PERIPHERAL_ADC = (uint8_t)0x13, CLK_PERIPHERAL_CAN = (uint8_t)0x17
}
CLK Enable peripheral. More...
enum CLK_Prescaler_TypeDef {
CLK_PRESCALER_HSIDIV1 = (uint8_t)0x00, CLK_PRESCALER_HSIDIV2 = (uint8_t)0x08, CLK_PRESCALER_HSIDIV4 = (uint8_t)0x10, CLK_PRESCALER_HSIDIV8 = (uint8_t)0x18,
CLK_PRESCALER_CPUDIV1 = (uint8_t)0x80, CLK_PRESCALER_CPUDIV2 = (uint8_t)0x81, CLK_PRESCALER_CPUDIV4 = (uint8_t)0x82, CLK_PRESCALER_CPUDIV8 = (uint8_t)0x83,
CLK_PRESCALER_CPUDIV16 = (uint8_t)0x84, CLK_PRESCALER_CPUDIV32 = (uint8_t)0x85, CLK_PRESCALER_CPUDIV64 = (uint8_t)0x86, CLK_PRESCALER_CPUDIV128 = (uint8_t)0x87
}
CLK Clock Divisor. More...
enum | CLK_Source_TypeDef { CLK_SOURCE_HSI = (uint8_t)0xE1, CLK_SOURCE_LSI = (uint8_t)0xD2, CLK_SOURCE_HSE = (uint8_t)0xB4 }
CLK Clock Source. More...
enum | CLK_SWIMDivider_TypeDef { CLK_SWIMDIVIDER_2 = (uint8_t)0x00, CLK_SWIMDIVIDER_OTHER = (uint8_t)0x01 }
SWIM Clock divider. More...
enum | CLK_SwitchMode_TypeDef { CLK_SWITCHMODE_MANUAL = (uint8_t)0x00, CLK_SWITCHMODE_AUTO = (uint8_t)0x01 }
Switch Mode Auto, Manual. More...

Functions

void | CLK_AdjustHSICalibrationValue (CLK_HSITrimValue_TypeDef CLK_HSICalibrationValue)
Adjusts the Internal High Speed oscillator (HSI) calibration value.
void | CLK_CCOCmd (FunctionalState NewState)
Enables or disablle the Configurable Clock Output (CCO).
void | CLK_CCOConfig (CLK_Output_TypeDef CLK_CCO)
Output the selected clock on a dedicated I/O pin.
void | CLK_ClearITPendingBit (CLK_IT_TypeDef CLK_IT)
Clears the CLK’s interrupt pending bits.
void | CLK_ClockSecuritySystemEnable (void)
Enables the Clock Security System.
void | CLK_ClockSwitchCmd (FunctionalState NewState)
Starts or Stops manually the clock switch execution.
ErrorStatus | CLK_ClockSwitchConfig (CLK_SwitchMode_TypeDef CLK_SwitchMode, CLK_Source_TypeDef CLK_NewClock, FunctionalState ITState, CLK_CurrentClockState_TypeDef CLK_CurrentClockState)
configures the Switch from one clock to another
void | CLK_DeInit (void)
Deinitializes the CLK peripheral registers to their default reset values.
void | CLK_FastHaltWakeUpCmd (FunctionalState NewState)
Configures the High Speed Internal oscillator (HSI).
uint32_t | CLK_GetClockFreq (void)
This function returns the frequencies of different on chip clocks.
FlagStatus | CLK_GetFlagStatus (CLK_Flag_TypeDef CLK_FLAG)
Checks whether the specified CLK flag is set or not.
ITStatus | CLK_GetITStatus (CLK_IT_TypeDef CLK_IT)
Checks whether the specified CLK interrupt has is enabled or not.
CLK_Source_TypeDef | CLK_GetSYSCLKSource (void)
Returns the clock source used as system clock.
void | CLK_HSECmd (FunctionalState NewState)
Enable or Disable the External High Speed oscillator (HSE).
void | CLK_HSICmd (FunctionalState NewState)
Enables or disables the Internal High Speed oscillator (HSI).
void | CLK_HSIPrescalerConfig (CLK_Prescaler_TypeDef HSIPrescaler)
Configures the HSI clock dividers.
void | CLK_ITConfig (CLK_IT_TypeDef CLK_IT, FunctionalState NewState)
Enables or disables the specified CLK interrupts.
void | CLK_LSICmd (FunctionalState NewState)
Enables or disables the Internal Low Speed oscillator (LSI).
void | CLK_PeripheralClockConfig (CLK_Peripheral_TypeDef CLK_Peripheral, FunctionalState NewState)
Enables or disables the specified peripheral CLK.
void | CLK_SlowActiveHaltWakeUpCmd (FunctionalState NewState)
Configures the slow active halt wake up.
void | CLK_SWIMConfig (CLK_SWIMDivider_TypeDef CLK_SWIMDivider)
Configures the SWIM clock frequency on the fly.
void | CLK_SYSCLKConfig (CLK_Prescaler_TypeDef CLK_Prescaler)
Configures the HSI and CPU clock dividers.
void | CLK_SYSCLKEmergencyClear (void)
Reset the SWBSY flag (SWICR Register)

Detailed Description

This file contains all functions prototype and macros for the CLK peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_clk.h.


STM8S/A Standard Peripherals Drivers: stm8s_exti.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions
stm8s_exti.c File Reference

This file contains all the functions for the EXTI peripheral. More...

#include "stm8s_exti.h"

Go to the source code of this file.

Functions

void | EXTI_DeInit (void)
Deinitializes the external interrupt control registers to their default reset value.
EXTI_Sensitivity_TypeDef | EXTI_GetExtIntSensitivity (EXTI_Port_TypeDef Port)
Get the external interrupt sensitivity of the selected port.
EXTI_TLISensitivity_TypeDef | EXTI_GetTLISensitivity (void)
Get the TLI interrupt sensitivity.
void | EXTI_SetExtIntSensitivity (EXTI_Port_TypeDef Port, EXTI_Sensitivity_TypeDef SensitivityValue)
Set the external interrupt sensitivity of the selected port.
void | EXTI_SetTLISensitivity (EXTI_TLISensitivity_TypeDef SensitivityValue)
Set the TLI interrupt sensitivity.

Detailed Description

This file contains all the functions for the EXTI peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_exti.c.


STM8S/A Standard Peripherals Drivers: stm8s_exti.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions
stm8s_exti.h File Reference

This file contains all functions prototype and macros for the EXTI peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_EXTI_PINMASK_OK(PinMask) ((((PinMask) & (uint8_t)0x00) == (uint8_t)0x00) && ((PinMask) != (uint8_t)0x00))
Macro used by the assert function in order to check the different values of the EXTI PinMask.
#define | IS_EXTI_PORT_OK(PORT)
Macro used by the assert function in order to check the different Port values.
#define | IS_EXTI_SENSITIVITY_OK(SensitivityValue)
Macro used by the assert function in order to check the different sensitivity values for PORTA to PORTE.
#define | IS_EXTI_TLISENSITIVITY_OK(SensitivityValue)
Macro used by the assert function in order to check the different sensitivity values for TLI.

Enumerations

enum EXTI_Port_TypeDef {
EXTI_PORT_GPIOA = (uint8_t)0x00, EXTI_PORT_GPIOB = (uint8_t)0x01, EXTI_PORT_GPIOC = (uint8_t)0x02, EXTI_PORT_GPIOD = (uint8_t)0x03,
EXTI_PORT_GPIOE = (uint8_t)0x04
}
EXTI PortNum possible values. More...
enum | EXTI_Sensitivity_TypeDef { EXTI_SENSITIVITY_FALL_LOW = (uint8_t)0x00, EXTI_SENSITIVITY_RISE_ONLY = (uint8_t)0x01, EXTI_SENSITIVITY_FALL_ONLY = (uint8_t)0x02, EXTI_SENSITIVITY_RISE_FALL = (uint8_t)0x03 }
EXTI Sensitivity values for PORTA to PORTE. More...
enum | EXTI_TLISensitivity_TypeDef { EXTI_TLISENSITIVITY_FALL_ONLY = (uint8_t)0x00, EXTI_TLISENSITIVITY_RISE_ONLY = (uint8_t)0x04 }
EXTI Sensitivity values for TLI. More...

Functions

void | EXTI_DeInit (void)
Deinitializes the external interrupt control registers to their default reset value.
EXTI_Sensitivity_TypeDef | EXTI_GetExtIntSensitivity (EXTI_Port_TypeDef Port)
Get the external interrupt sensitivity of the selected port.
EXTI_TLISensitivity_TypeDef | EXTI_GetTLISensitivity (void)
Get the TLI interrupt sensitivity.
void | EXTI_SetExtIntSensitivity (EXTI_Port_TypeDef Port, EXTI_Sensitivity_TypeDef SensitivityValue)
Set the external interrupt sensitivity of the selected port.
void | EXTI_SetTLISensitivity (EXTI_TLISensitivity_TypeDef SensitivityValue)
Set the TLI interrupt sensitivity.

Detailed Description

This file contains all functions prototype and macros for the EXTI peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_exti.h.


STM8S/A Standard Peripherals Drivers: stm8s_flash.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Defines | Functions
stm8s_flash.c File Reference

This file contains all the functions for the FLASH peripheral. More...

#include "stm8s_flash.h"

Go to the source code of this file.

Defines

#define | FLASH_CLEAR_BYTE ((uint8_t)0x00)
#define | FLASH_SET_BYTE ((uint8_t)0xFF)
#define | OPERATION_TIMEOUT ((uint16_t)0xFFFF)

Functions

void | FLASH_DeInit (void)
DeInitializes the FLASH registers to their default reset values.
void | FLASH_EraseByte (uint32_t Address)
Erases one byte in the program or data EEPROM memory.
void | FLASH_EraseOptionByte (uint16_t Address)
Erases option byte.
uint32_t | FLASH_GetBootSize (void)
Returns the Boot memory size in bytes.
FlagStatus | FLASH_GetFlagStatus (FLASH_Flag_TypeDef FLASH_FLAG)
Checks whether the specified SPI flag is set or not.
FLASH_LPMode_TypeDef | FLASH_GetLowPowerMode (void)
Returns the Flash behaviour type in low power mode.
FLASH_ProgramTime_TypeDef | FLASH_GetProgrammingTime (void)
Returns the fixed programming time.
void | FLASH_ITConfig (FunctionalState NewState)
Enables or Disables the Flash interrupt mode.
void | FLASH_Lock (FLASH_MemType_TypeDef FLASH_MemType)
Locks the program or data EEPROM memory.
void | FLASH_ProgramByte (uint32_t Address, uint8_t Data)
Programs one byte in program or data EEPROM memory.
void | FLASH_ProgramOptionByte (uint16_t Address, uint8_t Data)
Programs option byte.
void | FLASH_ProgramWord (uint32_t Address, uint32_t Data)
Programs one word (4 bytes) in program or data EEPROM memory.
uint8_t | FLASH_ReadByte (uint32_t Address)
Reads any byte from flash memory.
uint16_t | FLASH_ReadOptionByte (uint16_t Address)
Reads one option byte.
void | FLASH_SetLowPowerMode (FLASH_LPMode_TypeDef FLASH_LPMode)
Select the Flash behaviour in low power mode.
void | FLASH_SetProgrammingTime (FLASH_ProgramTime_TypeDef FLASH_ProgTime)
Sets the fixed programming time.
void | FLASH_Unlock (FLASH_MemType_TypeDef FLASH_MemType)
Unlocks the program or data EEPROM memory.

Detailed Description

This file contains all the functions for the FLASH peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_flash.c.


STM8S/A Standard Peripherals Drivers: stm8s_flash.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions
stm8s_flash.h File Reference

This file contains all functions prototype and macros for the FLASH peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | FLASH_OPTIONBYTE_ERROR ((uint16_t)0x5555)
#define | FLASH_PROG_START_PHYSICAL_ADDRESS ((uint32_t)0x008000)
#define | FLASH_RASS_KEY1 ((uint8_t)0x56)
#define | FLASH_RASS_KEY2 ((uint8_t)0xAE)
#define | IS_FLASH_ADDRESS_OK(ADDRESS)
Macro used by the assert function in order to check the different sensitivity values for the data eeprom and flash program Address.
#define | IS_FLASH_DATA_ADDRESS_OK(ADDRESS)
Macro used by the assert function in order to check the different sensitivity values for the data eeprom Address.
#define | IS_FLASH_DATA_BLOCK_NUMBER_OK(BLOCKNUM) ((BLOCKNUM) < FLASH_DATA_BLOCKS_NUMBER)
Macro used by the assert function in order to check the different sensitivity values for the data eeprom Block number.
#define | IS_FLASH_FLAGS_OK(FLAG)
Macro used by the assert function in order to check the different flags values.
#define | IS_FLASH_LOW_POWER_MODE_OK(LPMODE)
Macro used by the assert function in order to check the different sensitivity values for the low power mode.
#define | IS_FLASH_PROG_ADDRESS_OK(ADDRESS)
Macro used by the assert function in order to check the different sensitivity values for the flash program Address.
#define | IS_FLASH_PROG_BLOCK_NUMBER_OK(BLOCKNUM) ((BLOCKNUM) < FLASH_PROG_BLOCKS_NUMBER)
Macro used by the assert function in order to check the different sensitivity values for the flash program Block number.
#define | IS_FLASH_PROGRAM_MODE_OK(MODE)
Macro used by the assert function in order to check the different sensitivity values for the flash program mode.
#define | IS_FLASH_PROGRAM_TIME_OK(TIME)
Macro used by the assert function in order to check the program time mode.
#define | IS_MEMORY_TYPE_OK(MEMTYPE)
Macro used by the assert function in order to check the different sensitivity values for the flash memory type.
#define | IS_OPTION_BYTE_ADDRESS_OK(ADDRESS)
Macro used by the assert function in order to check the different sensitivity values for the option bytes Address.
#define | OPTION_BYTE_END_PHYSICAL_ADDRESS ((uint16_t)0x487F)
#define | OPTION_BYTE_START_PHYSICAL_ADDRESS ((uint16_t)0x4800)

Enumerations

enum | FLASH_Flag_TypeDef { FLASH_FLAG_DUL = (uint8_t)0x08, FLASH_FLAG_EOP = (uint8_t)0x04, FLASH_FLAG_PUL = (uint8_t)0x02, FLASH_FLAG_WR_PG_DIS = (uint8_t)0x01 }
FLASH flags definition. More...
enum | FLASH_LPMode_TypeDef { FLASH_LPMODE_POWERDOWN = (uint8_t)0x04, FLASH_LPMODE_STANDBY = (uint8_t)0x08, FLASH_LPMODE_POWERDOWN_STANDBY = (uint8_t)0x00, FLASH_LPMODE_STANDBY_POWERDOWN = (uint8_t)0x0C }
FLASH Low Power mode select. More...
enum | FLASH_MemType_TypeDef { FLASH_MEMTYPE_PROG = (uint8_t)0xFD, FLASH_MEMTYPE_DATA = (uint8_t)0xF7 }
FLASH Memory types. More...
enum | FLASH_ProgramMode_TypeDef { FLASH_PROGRAMMODE_STANDARD = (uint8_t)0x00, FLASH_PROGRAMMODE_FAST = (uint8_t)0x10 }
FLASH programming modes. More...
enum | FLASH_ProgramTime_TypeDef { FLASH_PROGRAMTIME_STANDARD = (uint8_t)0x00, FLASH_PROGRAMTIME_TPROG = (uint8_t)0x01 }
FLASH fixed programming time. More...
enum | FLASH_Status_TypeDef { FLASH_STATUS_SUCCESSFUL_OPERATION = (uint8_t)0x04, FLASH_STATUS_TIMEOUT = (uint8_t)0x02, FLASH_STATUS_WRITE_PROTECTION_ERROR = (uint8_t)0x01 }
FLASH status of the last operation. More...

Functions

void | FLASH_DeInit (void)
DeInitializes the FLASH registers to their default reset values.
void | FLASH_EraseByte (uint32_t Address)
Erases one byte in the program or data EEPROM memory.
void | FLASH_EraseOptionByte (uint16_t Address)
Erases option byte.
uint32_t | FLASH_GetBootSize (void)
Returns the Boot memory size in bytes.
FlagStatus | FLASH_GetFlagStatus (FLASH_Flag_TypeDef FLASH_FLAG)
Checks whether the specified SPI flag is set or not.
FLASH_LPMode_TypeDef | FLASH_GetLowPowerMode (void)
Returns the Flash behaviour type in low power mode.
FLASH_ProgramTime_TypeDef | FLASH_GetProgrammingTime (void)
Returns the fixed programming time.
void | FLASH_ITConfig (FunctionalState NewState)
Enables or Disables the Flash interrupt mode.
void | FLASH_Lock (FLASH_MemType_TypeDef FLASH_MemType)
Locks the program or data EEPROM memory.
void | FLASH_ProgramByte (uint32_t Address, uint8_t Data)
Programs one byte in program or data EEPROM memory.
void | FLASH_ProgramOptionByte (uint16_t Address, uint8_t Data)
Programs option byte.
void | FLASH_ProgramWord (uint32_t Address, uint32_t Data)
Programs one word (4 bytes) in program or data EEPROM memory.
uint8_t | FLASH_ReadByte (uint32_t Address)
Reads any byte from flash memory.
uint16_t | FLASH_ReadOptionByte (uint16_t Address)
Reads one option byte.
void | FLASH_SetLowPowerMode (FLASH_LPMode_TypeDef FLASH_LPMode)
Select the Flash behaviour in low power mode.
void | FLASH_SetProgrammingTime (FLASH_ProgramTime_TypeDef FLASH_ProgTime)
Sets the fixed programming time.
void | FLASH_Unlock (FLASH_MemType_TypeDef FLASH_MemType)
Unlocks the program or data EEPROM memory.
IN_RAM (void FLASH_EraseBlock(uint16_t BlockNum, FLASH_MemType_TypeDef FLASH_MemType))
IN_RAM (void FLASH_ProgramBlock(uint16_t BlockNum, FLASH_MemType_TypeDef FLASH_MemType, FLASH_ProgramMode_TypeDef FLASH_ProgMode, uint8_t *Buffer))
IN_RAM (FLASH_Status_TypeDef FLASH_WaitForLastOperation(FLASH_MemType_TypeDef FLASH_MemType))

Detailed Description

This file contains all functions prototype and macros for the FLASH peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_flash.h.


STM8S/A Standard Peripherals Drivers: stm8s_gpio.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions
stm8s_gpio.c File Reference

This file contains all the functions for the GPIO peripheral. More...

#include "stm8s_gpio.h"

Go to the source code of this file.

Functions

void | GPIO_DeInit (GPIO_TypeDef *GPIOx)
Deinitializes the GPIOx peripheral registers to their default reset values.
void | GPIO_ExternalPullUpConfig (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef GPIO_Pin, FunctionalState NewState)
Configures the external pull-up on GPIOx pins.
void | GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef GPIO_Pin, GPIO_Mode_TypeDef GPIO_Mode)
Initializes the GPIOx according to the specified parameters.
uint8_t | GPIO_ReadInputData (GPIO_TypeDef *GPIOx)
Reads the specified GPIO input data port.
BitStatus | GPIO_ReadInputPin (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
Reads the specified GPIO input data pin.
uint8_t | GPIO_ReadOutputData (GPIO_TypeDef *GPIOx)
Reads the specified GPIO output data port.
void | GPIO_Write (GPIO_TypeDef *GPIOx, uint8_t PortVal)
Writes data to the specified GPIO data port.
void | GPIO_WriteHigh (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef PortPins)
Writes high level to the specified GPIO pins.
void | GPIO_WriteLow (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef PortPins)
Writes low level to the specified GPIO pins.
void | GPIO_WriteReverse (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef PortPins)
Writes reverse level to the specified GPIO pins.

Detailed Description

This file contains all the functions for the GPIO peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_gpio.c.


STM8S/A Standard Peripherals Drivers: stm8s_gpio.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions
stm8s_gpio.h File Reference

This file contains all functions prototype and macros for the GPIO peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_GPIO_MODE_OK(MODE)
Macro used by the assert function to check the different functions parameters.
#define | IS_GPIO_PIN_OK(PIN) ((PIN) != (uint8_t)0x00)
Macro used by the assert function in order to check the different values of GPIO_Pins.

Enumerations

enum GPIO_Mode_TypeDef {
GPIO_MODE_IN_FL_NO_IT = (uint8_t)0x00, GPIO_MODE_IN_PU_NO_IT = (uint8_t)0x40, GPIO_MODE_IN_FL_IT = (uint8_t)0x20, GPIO_MODE_IN_PU_IT = (uint8_t)0x60,
GPIO_MODE_OUT_OD_LOW_FAST = (uint8_t)0xA0, GPIO_MODE_OUT_PP_LOW_FAST = (uint8_t)0xE0, GPIO_MODE_OUT_OD_LOW_SLOW = (uint8_t)0x80, GPIO_MODE_OUT_PP_LOW_SLOW = (uint8_t)0xC0,
GPIO_MODE_OUT_OD_HIZ_FAST = (uint8_t)0xB0, GPIO_MODE_OUT_PP_HIGH_FAST = (uint8_t)0xF0, GPIO_MODE_OUT_OD_HIZ_SLOW = (uint8_t)0x90, GPIO_MODE_OUT_PP_HIGH_SLOW = (uint8_t)0xD0
}
GPIO modes. More...
enum GPIO_Pin_TypeDef {
GPIO_PIN_0 = ((uint8_t)0x01), GPIO_PIN_1 = ((uint8_t)0x02), GPIO_PIN_2 = ((uint8_t)0x04), GPIO_PIN_3 = ((uint8_t)0x08),
GPIO_PIN_4 = ((uint8_t)0x10), GPIO_PIN_5 = ((uint8_t)0x20), GPIO_PIN_6 = ((uint8_t)0x40), GPIO_PIN_7 = ((uint8_t)0x80),
GPIO_PIN_LNIB = ((uint8_t)0x0F), GPIO_PIN_HNIB = ((uint8_t)0xF0), GPIO_PIN_ALL = ((uint8_t)0xFF)
}
Definition of the GPIO pins. More...

Functions

void | GPIO_DeInit (GPIO_TypeDef *GPIOx)
Deinitializes the GPIOx peripheral registers to their default reset values.
void | GPIO_ExternalPullUpConfig (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef GPIO_Pin, FunctionalState NewState)
Configures the external pull-up on GPIOx pins.
void | GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef GPIO_Pin, GPIO_Mode_TypeDef GPIO_Mode)
Initializes the GPIOx according to the specified parameters.
uint8_t | GPIO_ReadInputData (GPIO_TypeDef *GPIOx)
Reads the specified GPIO input data port.
BitStatus | GPIO_ReadInputPin (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
Reads the specified GPIO input data pin.
uint8_t | GPIO_ReadOutputData (GPIO_TypeDef *GPIOx)
Reads the specified GPIO output data port.
void | GPIO_Write (GPIO_TypeDef *GPIOx, uint8_t PortVal)
Writes data to the specified GPIO data port.
void | GPIO_WriteHigh (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef PortPins)
Writes high level to the specified GPIO pins.
void | GPIO_WriteLow (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef PortPins)
Writes low level to the specified GPIO pins.
void | GPIO_WriteReverse (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef PortPins)
Writes reverse level to the specified GPIO pins.

Detailed Description

This file contains all functions prototype and macros for the GPIO peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_gpio.h.


STM8S/A Standard Peripherals Drivers: stm8s_i2c.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Defines | Functions
stm8s_i2c.c File Reference

This file contains all the functions for the I2C peripheral. More...

#include "stm8s_i2c.h"

Go to the source code of this file.

Defines

#define | FLAG_Mask ((uint16_t)0x00FF)
#define | ITEN_Mask ((uint16_t)0x0700)
#define | REGISTER_Mask ((uint16_t)0x3000)
#define | REGISTER_SR1_Index ((uint16_t)0x0100)
#define | REGISTER_SR2_Index ((uint16_t)0x0200)

Functions

void | I2C_AcknowledgeConfig (I2C_Ack_TypeDef Ack)
Enable or Disable the I2C acknowledge and position acknowledge feature.
ErrorStatus | I2C_CheckEvent (I2C_Event_TypeDef I2C_Event)
I2C State Monitoring Functions.
void | I2C_ClearFlag (I2C_Flag_TypeDef I2C_FLAG)
Clear flags.
void | I2C_ClearITPendingBit (I2C_ITPendingBit_TypeDef I2C_ITPendingBit)
Clear IT pending bit.
void | I2C_Cmd (FunctionalState NewState)
Enables or disables the I2C peripheral.
void | I2C_DeInit (void)
Deinitializes the I2C peripheral registers to their default reset values.
void | I2C_FastModeDutyCycleConfig (I2C_DutyCycle_TypeDef I2C_DutyCycle)
Selects the specified I2C fast mode duty cycle.
void | I2C_GeneralCallCmd (FunctionalState NewState)
Enables or disables the I2C General Call feature.
void | I2C_GenerateSTART (FunctionalState NewState)
Generates I2C communication START condition.
void | I2C_GenerateSTOP (FunctionalState NewState)
Generates I2C communication STOP condition.
FlagStatus | I2C_GetFlagStatus (I2C_Flag_TypeDef I2C_Flag)
3) Flag-based state monitoring
ITStatus | I2C_GetITStatus (I2C_ITPendingBit_TypeDef I2C_ITPendingBit)
Checks whether the specified I2C interrupt has occurred or not.
I2C_Event_TypeDef | I2C_GetLastEvent (void)
2) Advanced state monitoring
void | I2C_Init (uint32_t OutputClockFrequencyHz, uint16_t OwnAddress, I2C_DutyCycle_TypeDef I2C_DutyCycle, I2C_Ack_TypeDef Ack, I2C_AddMode_TypeDef AddMode, uint8_t InputClockFrequencyMHz)
Initializes the I2C according to the specified parameters in standard or fast mode.
void | I2C_ITConfig (I2C_IT_TypeDef I2C_IT, FunctionalState NewState)
Enables or disables the specified I2C interrupt.
uint8_t | I2C_ReceiveData (void)
Returns the most recent received data.
void | I2C_Send7bitAddress (uint8_t Address, I2C_Direction_TypeDef Direction)
Transmits the 7-bit address (to select the) slave device.
void | I2C_SendData (uint8_t Data)
Send a byte by writing in the DR register.
void | I2C_SoftwareResetCmd (FunctionalState NewState)
Enables or disables I2C software reset.
void | I2C_StretchClockCmd (FunctionalState NewState)
Enables or disables the I2C clock stretching.

Detailed Description

This file contains all the functions for the I2C peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_i2c.c.


STM8S/A Standard Peripherals Drivers: stm8s_i2c.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions
stm8s_i2c.h File Reference

This file contains all functions prototype and macros for the I2C peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | I2C_MAX_FAST_FREQ ((uint32_t)400000)
#define | I2C_MAX_INPUT_FREQ ((uint8_t)16)
#define | I2C_MAX_STANDARD_FREQ ((uint32_t)100000)
#define | IS_I2C_ACK_OK(ACK)
Macro used by the assert function to check the different acknowledgement configuration.
#define | IS_I2C_ADDMODE_OK(ADDMODE)
Macro used by the assert function to check the different I2C addressing modes.
#define | IS_I2C_ADDRESS_OK(ADD) (((ADD) & (uint8_t)0x01) == (uint8_t)0x00)
#define | IS_I2C_CLEAR_FLAG_OK(FLAG)
Macro used by the assert function to check the I2C flags to clear.
#define | IS_I2C_CLEAR_ITPENDINGBIT_OK(ITPENDINGBIT)
Macro used by the assert function to check the different I2C possible pending bits to clear by writing 0.
#define | IS_I2C_DIRECTION_OK(DIR)
Macro used by the assert function to check the different I2C communcation direction.
#define | IS_I2C_DUTYCYCLE_OK(DUTY)
Macro used by the assert function to check the different functions parameters.
#define | IS_I2C_EVENT_OK(EVENT)
Macro used by the assert function to check the different I2C possible events.
#define | IS_I2C_FLAG_OK(FLAG)
Macro used by the assert function to check the different I2C flags.
#define | IS_I2C_INPUT_CLOCK_FREQ_OK(FREQ) (((FREQ) >= (uint8_t)1) && ((FREQ) <= I2C_MAX_INPUT_FREQ))
Macro used by the assert function to check that I2C Input clock frequency must be between 1MHz and 50MHz.
#define | IS_I2C_INTERRUPT_OK(IT)
Macro used by the assert function to check the different I2C interrupt types.
#define | IS_I2C_ITPENDINGBIT_OK(ITPENDINGBIT)
Macro used by the assert function to check the different I2C possible pending bits.
#define | IS_I2C_OUTPUT_CLOCK_FREQ_OK(FREQ) (((FREQ) >= (uint8_t)1) && ((FREQ) <= I2C_MAX_FAST_FREQ))
Macro used by the assert function to check that I2C Output clock frequency must be between 1Hz and 400kHz.
#define | IS_I2C_OWN_ADDRESS_OK(ADDRESS) ((ADDRESS) <= (uint16_t)0x03FF)
Macro used by the assert function to check the different I2C possible own address.

Enumerations

enum | I2C_Ack_TypeDef { I2C_ACK_NONE = (uint8_t)0x00, I2C_ACK_CURR = (uint8_t)0x01, I2C_ACK_NEXT = (uint8_t)0x02 }
I2C Acknowledgement configuration. More...
enum | I2C_AddMode_TypeDef { I2C_ADDMODE_7BIT = (uint8_t)0x00, I2C_ADDMODE_10BIT = (uint8_t)0x80 }
I2C Addressing Mode (slave mode only) More...
enum | I2C_Direction_TypeDef { I2C_DIRECTION_TX = (uint8_t)0x00, I2C_DIRECTION_RX = (uint8_t)0x01 }
I2C transfer direction Warning: the values correspond to the ADD0 bit position in the OARL register. More...
enum | I2C_DutyCycle_TypeDef { I2C_DUTYCYCLE_2 = (uint8_t)0x00, I2C_DUTYCYCLE_16_9 = (uint8_t)0x40 }
I2C duty cycle (fast mode only) More...
enum I2C_Event_TypeDef {
I2C_EVENT_MASTER_MODE_SELECT = (uint16_t)0x0301, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED = (uint16_t)0x0782, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED = (uint16_t)0x0302, I2C_EVENT_MASTER_MODE_ADDRESS10 = (uint16_t)0x0308,
I2C_EVENT_MASTER_BYTE_RECEIVED = (uint16_t)0x0340, I2C_EVENT_MASTER_BYTE_TRANSMITTING = (uint16_t)0x0780, I2C_EVENT_MASTER_BYTE_TRANSMITTED = (uint16_t)0x0784, I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED = (uint16_t)0x0202,
I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED = (uint16_t)0x0682, I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED = (uint16_t)0x1200, I2C_EVENT_SLAVE_BYTE_RECEIVED = (uint16_t)0x0240, I2C_EVENT_SLAVE_STOP_DETECTED = (uint16_t)0x0010,
I2C_EVENT_SLAVE_BYTE_TRANSMITTED = (uint16_t)0x0684, I2C_EVENT_SLAVE_BYTE_TRANSMITTING = (uint16_t)0x0680, I2C_EVENT_SLAVE_ACK_FAILURE = (uint16_t)0x0004
}
I2C possible events Values convention: 0xXXYY XX = Event SR3 corresponding value YY = Event SR1 corresponding value. More...
enum I2C_Flag_TypeDef {
I2C_FLAG_TXEMPTY = (uint16_t)0x0180, I2C_FLAG_RXNOTEMPTY = (uint16_t)0x0140, I2C_FLAG_STOPDETECTION = (uint16_t)0x0110, I2C_FLAG_HEADERSENT = (uint16_t)0x0108,
I2C_FLAG_TRANSFERFINISHED = (uint16_t)0x0104, I2C_FLAG_ADDRESSSENTMATCHED = (uint16_t)0x0102, I2C_FLAG_STARTDETECTION = (uint16_t)0x0101, I2C_FLAG_WAKEUPFROMHALT = (uint16_t)0x0220,
I2C_FLAG_OVERRUNUNDERRUN = (uint16_t)0x0208, I2C_FLAG_ACKNOWLEDGEFAILURE = (uint16_t)0x0204, I2C_FLAG_ARBITRATIONLOSS = (uint16_t)0x0202, I2C_FLAG_BUSERROR = (uint16_t)0x0201,
I2C_FLAG_GENERALCALL = (uint16_t)0x0310, I2C_FLAG_TRANSMITTERRECEIVER = (uint16_t)0x0304, I2C_FLAG_BUSBUSY = (uint16_t)0x0302, I2C_FLAG_MASTERSLAVE = (uint16_t)0x0301
}
I2C Flags. More...
enum | I2C_IT_TypeDef { I2C_IT_ERR = (uint8_t)0x01, I2C_IT_EVT = (uint8_t)0x02, I2C_IT_BUF = (uint8_t)0x04 }
I2C Interrupt sources Warning: the values correspond to the bit position in the ITR register. More...
enum I2C_ITPendingBit_TypeDef {
I2C_ITPENDINGBIT_TXEMPTY = (uint16_t)0x1680, I2C_ITPENDINGBIT_RXNOTEMPTY = (uint16_t)0x1640, I2C_ITPENDINGBIT_STOPDETECTION = (uint16_t)0x1210, I2C_ITPENDINGBIT_HEADERSENT = (uint16_t)0x1208,
I2C_ITPENDINGBIT_TRANSFERFINISHED = (uint16_t)0x1204, I2C_ITPENDINGBIT_ADDRESSSENTMATCHED = (uint16_t)0x1202, I2C_ITPENDINGBIT_STARTDETECTION = (uint16_t)0x1201, I2C_ITPENDINGBIT_WAKEUPFROMHALT = (uint16_t)0x2220,
I2C_ITPENDINGBIT_OVERRUNUNDERRUN = (uint16_t)0x2108, I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE = (uint16_t)0x2104, I2C_ITPENDINGBIT_ARBITRATIONLOSS = (uint16_t)0x2102, I2C_ITPENDINGBIT_BUSERROR = (uint16_t)0x2101
}
I2C Pending bits Elements values convention: 0xXYZZ X = SRx registers index X = 1 : SR1 X = 2 : SR2 Y = Position of the corresponding Interrupt ZZ = flag mask in the dedicated register(X register) More...

Functions

void | I2C_AcknowledgeConfig (I2C_Ack_TypeDef Ack)
Enable or Disable the I2C acknowledge and position acknowledge feature.
ErrorStatus | I2C_CheckEvent (I2C_Event_TypeDef I2C_Event)
I2C State Monitoring Functions.
void | I2C_ClearFlag (I2C_Flag_TypeDef I2C_FLAG)
Clear flags.
void | I2C_ClearITPendingBit (I2C_ITPendingBit_TypeDef I2C_ITPendingBit)
Clear IT pending bit.
void | I2C_Cmd (FunctionalState NewState)
Enables or disables the I2C peripheral.
void | I2C_DeInit (void)
Deinitializes the I2C peripheral registers to their default reset values.
void | I2C_FastModeDutyCycleConfig (I2C_DutyCycle_TypeDef I2C_DutyCycle)
Selects the specified I2C fast mode duty cycle.
void | I2C_GeneralCallCmd (FunctionalState NewState)
Enables or disables the I2C General Call feature.
void | I2C_GenerateSTART (FunctionalState NewState)
Generates I2C communication START condition.
void | I2C_GenerateSTOP (FunctionalState NewState)
Generates I2C communication STOP condition.
FlagStatus | I2C_GetFlagStatus (I2C_Flag_TypeDef I2C_Flag)
3) Flag-based state monitoring
ITStatus | I2C_GetITStatus (I2C_ITPendingBit_TypeDef I2C_ITPendingBit)
Checks whether the specified I2C interrupt has occurred or not.
I2C_Event_TypeDef | I2C_GetLastEvent (void)
2) Advanced state monitoring
void | I2C_Init (uint32_t OutputClockFrequencyHz, uint16_t OwnAddress, I2C_DutyCycle_TypeDef I2C_DutyCycle, I2C_Ack_TypeDef Ack, I2C_AddMode_TypeDef AddMode, uint8_t InputClockFrequencyMHz)
Initializes the I2C according to the specified parameters in standard or fast mode.
void | I2C_ITConfig (I2C_IT_TypeDef I2C_IT, FunctionalState NewState)
Enables or disables the specified I2C interrupt.
uint8_t | I2C_ReceiveData (void)
Returns the most recent received data.
void | I2C_Send7bitAddress (uint8_t Address, I2C_Direction_TypeDef Direction)
Transmits the 7-bit address (to select the) slave device.
void | I2C_SendData (uint8_t Data)
Send a byte by writing in the DR register.
void | I2C_SoftwareResetCmd (FunctionalState NewState)
Enables or disables I2C software reset.
void | I2C_StretchClockCmd (FunctionalState NewState)
Enables or disables the I2C clock stretching.

Detailed Description

This file contains all functions prototype and macros for the I2C peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_i2c.h.


STM8S/A Standard Peripherals Drivers: stm8s_itc.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions
stm8s_itc.c File Reference

This file contains all the functions for the ITC peripheral. More...

#include "stm8s_itc.h"

Go to the source code of this file.

Functions

void | ITC_DeInit (void)
Deinitializes the ITC registers to their default reset value.
uint8_t | ITC_GetCPUCC (void)
Utility function used to read CC register.
uint8_t | ITC_GetSoftIntStatus (void)
Gets the interrupt software priority bits (I1, I0) value from CPU CC register.
ITC_PriorityLevel_TypeDef | ITC_GetSoftwarePriority (ITC_Irq_TypeDef IrqNum)
Gets the software priority of the specified interrupt source.
void | ITC_SetSoftwarePriority (ITC_Irq_TypeDef IrqNum, ITC_PriorityLevel_TypeDef PriorityValue)
Sets the software priority of the specified interrupt source.

Detailed Description

This file contains all the functions for the ITC peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_itc.c.


STM8S/A Standard Peripherals Drivers: stm8s_itc.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions
stm8s_itc.h File Reference

This file contains all functions prototype and macros for the ITC peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | CPU_SOFT_INT_DISABLED ((uint8_t)0x28)
#define | IS_ITC_INTERRUPTS_DISABLED (ITC_GetSoftIntStatus() == CPU_SOFT_INT_DISABLED)
#define | IS_ITC_IRQ_OK(IRQ) ((IRQ) <= (uint8_t)24)
#define | IS_ITC_PRIORITY_OK(PriorityValue)

Enumerations

enum ITC_Irq_TypeDef {
ITC_IRQ_TLI = (uint8_t)0, ITC_IRQ_AWU = (uint8_t)1, ITC_IRQ_CLK = (uint8_t)2, ITC_IRQ_PORTA = (uint8_t)3,
ITC_IRQ_PORTB = (uint8_t)4, ITC_IRQ_PORTC = (uint8_t)5, ITC_IRQ_PORTD = (uint8_t)6, ITC_IRQ_PORTE = (uint8_t)7,
ITC_IRQ_SPI = (uint8_t)10, ITC_IRQ_TIM1_OVF = (uint8_t)11, ITC_IRQ_TIM1_CAPCOM = (uint8_t)12, ITC_IRQ_TIM2_OVF = (uint8_t)13,
ITC_IRQ_TIM2_CAPCOM = (uint8_t)14, ITC_IRQ_TIM3_OVF = (uint8_t)15, ITC_IRQ_TIM3_CAPCOM = (uint8_t)16, ITC_IRQ_I2C = (uint8_t)19,
ITC_IRQ_TIM4_OVF = (uint8_t)23, ITC_IRQ_EEPROM_EEC = (uint8_t)24
}
ITC Interrupt Lines selection. More...
enum | ITC_PriorityLevel_TypeDef { ITC_PRIORITYLEVEL_0 = (uint8_t)0x02, ITC_PRIORITYLEVEL_1 = (uint8_t)0x01, ITC_PRIORITYLEVEL_2 = (uint8_t)0x00, ITC_PRIORITYLEVEL_3 = (uint8_t)0x03 }
ITC Priority Levels selection. More...

Functions

void | ITC_DeInit (void)
Deinitializes the ITC registers to their default reset value.
uint8_t | ITC_GetCPUCC (void)
Utility function used to read CC register.
uint8_t | ITC_GetSoftIntStatus (void)
Gets the interrupt software priority bits (I1, I0) value from CPU CC register.
ITC_PriorityLevel_TypeDef | ITC_GetSoftwarePriority (ITC_Irq_TypeDef IrqNum)
Gets the software priority of the specified interrupt source.
void | ITC_SetSoftwarePriority (ITC_Irq_TypeDef IrqNum, ITC_PriorityLevel_TypeDef PriorityValue)
Sets the software priority of the specified interrupt source.

Detailed Description

This file contains all functions prototype and macros for the ITC peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_itc.h.


STM8S/A Standard Peripherals Drivers: stm8s_iwdg.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions
stm8s_iwdg.c File Reference

This file contains all the functions for the IWDG peripheral. More...

#include "stm8s_iwdg.h"

Go to the source code of this file.

Functions

void | IWDG_Enable (void)
Enables IWDG.
void | IWDG_ReloadCounter (void)
Reloads IWDG counter.
void | IWDG_SetPrescaler (IWDG_Prescaler_TypeDef IWDG_Prescaler)
Sets IWDG Prescaler value.
void | IWDG_SetReload (uint8_t IWDG_Reload)
Sets IWDG Reload value.
void | IWDG_WriteAccessCmd (IWDG_WriteAccess_TypeDef IWDG_WriteAccess)
Enables or disables write access to Prescaler and Reload registers.

Detailed Description

This file contains all the functions for the IWDG peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_iwdg.c.


STM8S/A Standard Peripherals Drivers: stm8s_iwdg.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions
stm8s_iwdg.h File Reference

This file contains all functions prototypes and macros for the IWDG peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_IWDG_PRESCALER_OK(VALUE)
Macro used by the assert function in order to check the different values of the prescaler.
#define | IS_IWDG_WRITEACCESS_MODE_OK(MODE) (((MODE) == IWDG_WriteAccess_Enable) || ((MODE) == IWDG_WriteAccess_Disable))
Macro used by the assert function in order to check the different values of the counter register.
#define | IWDG_KEY_ENABLE ((uint8_t)0xCC)
Define used to start the watchdog counter down.
#define | IWDG_KEY_REFRESH ((uint8_t)0xAA)
Define used to prevent watchdog reset.

Enumerations

enum IWDG_Prescaler_TypeDef {
IWDG_Prescaler_4 = (uint8_t)0x00, IWDG_Prescaler_8 = (uint8_t)0x01, IWDG_Prescaler_16 = (uint8_t)0x02, IWDG_Prescaler_32 = (uint8_t)0x03,
IWDG_Prescaler_64 = (uint8_t)0x04, IWDG_Prescaler_128 = (uint8_t)0x05, IWDG_Prescaler_256 = (uint8_t)0x06
}
IWDG prescaler enumaration. More...
enum | IWDG_WriteAccess_TypeDef { IWDG_WriteAccess_Enable = (uint8_t)0x55, IWDG_WriteAccess_Disable = (uint8_t)0x00 }
IWDG write access enumeration. More...

Functions

void | IWDG_Enable (void)
Enables IWDG.
void | IWDG_ReloadCounter (void)
Reloads IWDG counter.
void | IWDG_SetPrescaler (IWDG_Prescaler_TypeDef IWDG_Prescaler)
Sets IWDG Prescaler value.
void | IWDG_SetReload (uint8_t IWDG_Reload)
Sets IWDG Reload value.
void | IWDG_WriteAccessCmd (IWDG_WriteAccess_TypeDef IWDG_WriteAccess)
Enables or disables write access to Prescaler and Reload registers.

Detailed Description

This file contains all functions prototypes and macros for the IWDG peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_iwdg.h.


STM8S/A Standard Peripherals Drivers: stm8s_rst.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions
stm8s_rst.c File Reference

This file contains all the functions for the RST peripheral. More...

#include "stm8s_rst.h"

Go to the source code of this file.

Functions

void | RST_ClearFlag (RST_Flag_TypeDef RST_Flag)
Clears the specified RST flag.
FlagStatus | RST_GetFlagStatus (RST_Flag_TypeDef RST_Flag)
Checks whether the specified RST flag is set or not.

Detailed Description

This file contains all the functions for the RST peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_rst.c.


STM8S/A Standard Peripherals Drivers: stm8s_rst.h File Reference

  • File List
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  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions
stm8s_rst.h File Reference

This file contains all functions prototype and macros for the RST peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_RST_FLAG_OK(FLAG)
Macro used by the assert function to check the different functions parameters.

Enumerations

enum RST_Flag_TypeDef {
RST_FLAG_EMCF = (uint8_t)0x10, RST_FLAG_SWIMF = (uint8_t)0x08, RST_FLAG_ILLOPF = (uint8_t)0x04, RST_FLAG_IWDGF = (uint8_t)0x02,
RST_FLAG_WWDGF = (uint8_t)0x01
}

Functions

void | RST_ClearFlag (RST_Flag_TypeDef RST_Flag)
Clears the specified RST flag.
FlagStatus | RST_GetFlagStatus (RST_Flag_TypeDef RST_Flag)
Checks whether the specified RST flag is set or not.

Detailed Description

This file contains all functions prototype and macros for the RST peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_rst.h.


STM8S/A Standard Peripherals Drivers: stm8s_spi.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions
stm8s_spi.c File Reference

This file contains all the functions for the SPI peripheral. More...

#include "stm8s_spi.h"

Go to the source code of this file.

Functions

void | SPI_BiDirectionalLineConfig (SPI_Direction_TypeDef SPI_Direction)
Selects the data transfer direction in bi-directional mode.
void | SPI_CalculateCRCCmd (FunctionalState NewState)
Enables or disables the CRC value calculation of the transferred bytes.
void | SPI_ClearFlag (SPI_Flag_TypeDef SPI_FLAG)
Clears the SPI flags.
void | SPI_ClearITPendingBit (SPI_IT_TypeDef SPI_IT)
Clears the interrupt pending bits.
void | SPI_Cmd (FunctionalState NewState)
Enables or disables the SPI peripheral.
void | SPI_DeInit (void)
Deinitializes the SPI peripheral registers to their default reset values.
uint8_t | SPI_GetCRC (SPI_CRC_TypeDef SPI_CRC)
Returns the transmit or the receive CRC register value.
uint8_t | SPI_GetCRCPolynomial (void)
Returns the CRC Polynomial register value.
FlagStatus | SPI_GetFlagStatus (SPI_Flag_TypeDef SPI_FLAG)
Checks whether the specified SPI flag is set or not.
ITStatus | SPI_GetITStatus (SPI_IT_TypeDef SPI_IT)
Checks whether the specified interrupt has occurred or not.
void | SPI_Init (SPI_FirstBit_TypeDef FirstBit, SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, SPI_Mode_TypeDef Mode, SPI_ClockPolarity_TypeDef ClockPolarity, SPI_ClockPhase_TypeDef ClockPhase, SPI_DataDirection_TypeDef Data_Direction, SPI_NSS_TypeDef Slave_Management, uint8_t CRCPolynomial)
Initializes the SPI according to the specified parameters.
void | SPI_ITConfig (SPI_IT_TypeDef SPI_IT, FunctionalState NewState)
Enables or disables the specified interrupts.
void | SPI_NSSInternalSoftwareCmd (FunctionalState NewState)
Configures internally by software the NSS pin.
uint8_t | SPI_ReceiveData (void)
Returns the most recent received data by the SPI peripheral.
void | SPI_ResetCRC (void)
Reset the Rx CRCR and Tx CRCR registers.
void | SPI_SendData (uint8_t Data)
Transmits a Data through the SPI peripheral.
void | SPI_TransmitCRC (void)
Enables the transmit of the CRC value.

Detailed Description

This file contains all the functions for the SPI peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_spi.c.


STM8S/A Standard Peripherals Drivers: stm8s_spi.h File Reference

  • File List
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  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions
stm8s_spi.h File Reference

This file contains all functions prototype and macros for the SPI peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_SPI_BAUDRATE_PRESCALER_OK(PRESCALER)
Macro used by the assert_param function in order to check the baudrate values.
#define | IS_SPI_CLEAR_FLAGS_OK(FLAG)
Macro used by the assert_param function in order to check the different sensitivity values for the flag that can be cleared by writing 0.
#define | IS_SPI_CLEAR_IT_OK(ITPendingBit)
Macro used by the assert_param function in order to check the different sensitivity values for the pending bit that can be cleared by writing 0.
#define | IS_SPI_CONFIG_IT_OK(Interrupt)
Macro used by the assert_param function in order to check the different sensitivity values for the Interrupts.
#define | IS_SPI_CRC_OK(CRC)
Macro used by the assert_param function in order to check the CRC Transmit/Receive.
#define | IS_SPI_CRC_POLYNOMIAL_OK(POLYNOMIAL) ((POLYNOMIAL) > (uint8_t)0x00)
Macro used by the assert_param function in order to check the different sensitivity values for the CRC polynomial.
#define | IS_SPI_DATA_DIRECTION_OK(MODE)
Macro used by the assert_param function in order to check the data direction mode values.
#define | IS_SPI_DIRECTION_OK(DIRECTION)
Macro used by the assert_param function in order to check the mode half duplex data direction values.
#define | IS_SPI_FIRSTBIT_OK(BIT)
Macro used by the assert_param function in order to check the first bit to be transmited values.
#define | IS_SPI_FLAGS_OK(FLAG)
Macro used by the assert_param function in order to check the different flags values.
#define | IS_SPI_GET_IT_OK(ITPendingBit)
Macro used by the assert_param function in order to check the different sensitivity values for the pending bit.
#define | IS_SPI_MODE_OK(MODE)
Macro used by the assert_param function in order to check the SPI Mode values.
#define | IS_SPI_PHASE_OK(CLKPHA)
Macro used by the assert_param function in order to check the phase values.
#define | IS_SPI_POLARITY_OK(CLKPOL)
Macro used by the assert_param function in order to check the polarity values.
#define | IS_SPI_SLAVEMANAGEMENT_OK(NSS)
Macro used by the assert_param function in order to check the NSS management values.

Enumerations

enum SPI_BaudRatePrescaler_TypeDef {
SPI_BAUDRATEPRESCALER_2 = (uint8_t)0x00, SPI_BAUDRATEPRESCALER_4 = (uint8_t)0x08, SPI_BAUDRATEPRESCALER_8 = (uint8_t)0x10, SPI_BAUDRATEPRESCALER_16 = (uint8_t)0x18,
SPI_BAUDRATEPRESCALER_32 = (uint8_t)0x20, SPI_BAUDRATEPRESCALER_64 = (uint8_t)0x28, SPI_BAUDRATEPRESCALER_128 = (uint8_t)0x30, SPI_BAUDRATEPRESCALER_256 = (uint8_t)0x38
}
SPI BaudRate Prescaler Warning: element values correspond to BR bits position. More...
enum | SPI_ClockPhase_TypeDef { SPI_CLOCKPHASE_1EDGE = (uint8_t)0x00, SPI_CLOCKPHASE_2EDGE = (uint8_t)0x01 }
SPI Clock Phase Warning: element values correspond to CPHA bit position. More...
enum | SPI_ClockPolarity_TypeDef { SPI_CLOCKPOLARITY_LOW = (uint8_t)0x00, SPI_CLOCKPOLARITY_HIGH = (uint8_t)0x02 }
SPI Clock Polarity Warning: element values correspond to CPOL bit position. More...
enum | SPI_CRC_TypeDef { SPI_CRC_RX = (uint8_t)0x00, SPI_CRC_TX = (uint8_t)0x01 }
SPI CRC Transmit/Receive. More...
enum | SPI_DataDirection_TypeDef { SPI_DATADIRECTION_2LINES_FULLDUPLEX = (uint8_t)0x00, SPI_DATADIRECTION_2LINES_RXONLY = (uint8_t)0x04, SPI_DATADIRECTION_1LINE_RX = (uint8_t)0x80, SPI_DATADIRECTION_1LINE_TX = (uint8_t)0xC0 }
SPI data direction mode Warning: element values correspond to BDM, BDOE, RXONLY bits position. More...
enum | SPI_Direction_TypeDef { SPI_DIRECTION_RX = (uint8_t)0x00, SPI_DIRECTION_TX = (uint8_t)0x01 }
SPI direction transmit/receive. More...
enum | SPI_FirstBit_TypeDef { SPI_FIRSTBIT_MSB = (uint8_t)0x00, SPI_FIRSTBIT_LSB = (uint8_t)0x80 }
SPI Frame Format: MSB or LSB transmitted first Warning: element values correspond to LSBFIRST bit position. More...
enum SPI_Flag_TypeDef {
SPI_FLAG_BSY = (uint8_t)0x80, SPI_FLAG_OVR = (uint8_t)0x40, SPI_FLAG_MODF = (uint8_t)0x20, SPI_FLAG_CRCERR = (uint8_t)0x10,
SPI_FLAG_WKUP = (uint8_t)0x08, SPI_FLAG_TXE = (uint8_t)0x02, SPI_FLAG_RXNE = (uint8_t)0x01
}
SPI flags definition - Warning : FLAG value = mapping position register. More...
enum SPI_IT_TypeDef {
SPI_IT_WKUP = (uint8_t)0x34, SPI_IT_OVR = (uint8_t)0x65, SPI_IT_MODF = (uint8_t)0x55, SPI_IT_CRCERR = (uint8_t)0x45,
SPI_IT_TXE = (uint8_t)0x17, SPI_IT_RXNE = (uint8_t)0x06, SPI_IT_ERR = (uint8_t)0x05
}
SPI_IT possible values Elements values convention: 0xYX X: Position of the corresponding Interrupt Y: ITPENDINGBIT position. More...
enum | SPI_Mode_TypeDef { SPI_MODE_MASTER = (uint8_t)0x04, SPI_MODE_SLAVE = (uint8_t)0x00 }
SPI master/slave mode Warning: element values correspond to MSTR bit position. More...
enum | SPI_NSS_TypeDef { SPI_NSS_SOFT = (uint8_t)0x02, SPI_NSS_HARD = (uint8_t)0x00 }
SPI Slave Select management Warning: element values correspond to LSBFIRST bit position. More...

Functions

void | SPI_BiDirectionalLineConfig (SPI_Direction_TypeDef SPI_Direction)
Selects the data transfer direction in bi-directional mode.
void | SPI_CalculateCRCCmd (FunctionalState NewState)
Enables or disables the CRC value calculation of the transferred bytes.
void | SPI_ClearFlag (SPI_Flag_TypeDef SPI_FLAG)
Clears the SPI flags.
void | SPI_ClearITPendingBit (SPI_IT_TypeDef SPI_IT)
Clears the interrupt pending bits.
void | SPI_Cmd (FunctionalState NewState)
Enables or disables the SPI peripheral.
void | SPI_DeInit (void)
Deinitializes the SPI peripheral registers to their default reset values.
uint8_t | SPI_GetCRC (SPI_CRC_TypeDef SPI_CRC)
Returns the transmit or the receive CRC register value.
uint8_t | SPI_GetCRCPolynomial (void)
Returns the CRC Polynomial register value.
FlagStatus | SPI_GetFlagStatus (SPI_Flag_TypeDef SPI_FLAG)
Checks whether the specified SPI flag is set or not.
ITStatus | SPI_GetITStatus (SPI_IT_TypeDef SPI_IT)
Checks whether the specified interrupt has occurred or not.
void | SPI_Init (SPI_FirstBit_TypeDef FirstBit, SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, SPI_Mode_TypeDef Mode, SPI_ClockPolarity_TypeDef ClockPolarity, SPI_ClockPhase_TypeDef ClockPhase, SPI_DataDirection_TypeDef Data_Direction, SPI_NSS_TypeDef Slave_Management, uint8_t CRCPolynomial)
Initializes the SPI according to the specified parameters.
void | SPI_ITConfig (SPI_IT_TypeDef SPI_IT, FunctionalState NewState)
Enables or disables the specified interrupts.
void | SPI_NSSInternalSoftwareCmd (FunctionalState NewState)
Configures internally by software the NSS pin.
uint8_t | SPI_ReceiveData (void)
Returns the most recent received data by the SPI peripheral.
void | SPI_ResetCRC (void)
Reset the Rx CRCR and Tx CRCR registers.
void | SPI_SendData (uint8_t Data)
Transmits a Data through the SPI peripheral.
void | SPI_TransmitCRC (void)
Enables the transmit of the CRC value.

Detailed Description

This file contains all functions prototype and macros for the SPI peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_spi.h.


STM8S/A Standard Peripherals Drivers: stm8s_tim1.c File Reference

  • File List
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  • STM8S_StdPeriph_Driver
  • src
Functions
stm8s_tim1.c File Reference

This file contains all the functions for the TIM1 peripheral. More...

#include "stm8s_tim1.h"

Go to the source code of this file.

Functions

static void | TI1_Config (uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
Configure the TI1 as Input.
static void | TI2_Config (uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
Configure the TI2 as Input.
static void | TI3_Config (uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
Configure the TI3 as Input.
static void | TI4_Config (uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
Configure the TI4 as Input.
void | TIM1_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM1 peripheral Preload register on ARR.
void | TIM1_BDTRConfig (TIM1_OSSIState_TypeDef TIM1_OSSIState, TIM1_LockLevel_TypeDef TIM1_LockLevel, uint8_t TIM1_DeadTime, TIM1_BreakState_TypeDef TIM1_Break, TIM1_BreakPolarity_TypeDef TIM1_BreakPolarity, TIM1_AutomaticOutput_TypeDef TIM1_AutomaticOutput)
Configures the Break feature, dead time, Lock level, the OSSI, and the AOE(automatic output enable).
void | TIM1_CCPreloadControl (FunctionalState NewState)
Sets or Resets the TIM1 peripheral Capture Compare Preload Control bit.
void | TIM1_CCxCmd (TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState)
Enables or disables the TIM1 Capture Compare Channel x (x=1,..,4).
void | TIM1_CCxNCmd (TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState)
Enables or disables the TIM1 Capture Compare Channel xN (xN=1,..,3).
void | TIM1_ClearFlag (TIM1_FLAG_TypeDef TIM1_FLAG)
Clears the TIM1’s pending flags.
void | TIM1_ClearITPendingBit (TIM1_IT_TypeDef TIM1_IT)
Clears the TIM1's interrupt pending bits.
void | TIM1_Cmd (FunctionalState NewState)
Enables or disables the TIM1 peripheral.
void | TIM1_CounterModeConfig (TIM1_CounterMode_TypeDef TIM1_CounterMode)
Specifies the TIM1 Counter Mode to be used.
void | TIM1_CtrlPWMOutputs (FunctionalState NewState)
Enables or disables the TIM1 peripheral Main Outputs.
void | TIM1_DeInit (void)
Deinitializes the TIM1 peripheral registers to their default reset values.
void | TIM1_EncoderInterfaceConfig (TIM1_EncoderMode_TypeDef TIM1_EncoderMode, TIM1_ICPolarity_TypeDef TIM1_IC1Polarity, TIM1_ICPolarity_TypeDef TIM1_IC2Polarity)
Configures the TIM1 Encoder Interface.
void | TIM1_ETRClockMode1Config (TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, uint8_t ExtTRGFilter)
Configures the TIM1 External clock Mode1.
void | TIM1_ETRClockMode2Config (TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, uint8_t ExtTRGFilter)
Configures the TIM1 External clock Mode2.
void | TIM1_ETRConfig (TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, uint8_t ExtTRGFilter)
Configures the TIM1 External Trigger.
void | TIM1_ForcedOC1Config (TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
Forces the TIM1 Channel1 output waveform to active or inactive level.
void | TIM1_ForcedOC2Config (TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
Forces the TIM1 Channel2 output waveform to active or inactive level.
void | TIM1_ForcedOC3Config (TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
Forces the TIM1 Channel3 output waveform to active or inactive level.
void | TIM1_ForcedOC4Config (TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
Forces the TIM1 Channel4 output waveform to active or inactive level.
void | TIM1_GenerateEvent (TIM1_EventSource_TypeDef TIM1_EventSource)
Configures the TIM1 event to be generated by software.
uint16_t | TIM1_GetCapture1 (void)
Gets the TIM1 Input Capture 1 value.
uint16_t | TIM1_GetCapture2 (void)
Gets the TIM1 Input Capture 2 value.
uint16_t | TIM1_GetCapture3 (void)
Gets the TIM1 Input Capture 3 value.
uint16_t | TIM1_GetCapture4 (void)
Gets the TIM1 Input Capture 4 value.
uint16_t | TIM1_GetCounter (void)
Gets the TIM1 Counter value.
FlagStatus | TIM1_GetFlagStatus (TIM1_FLAG_TypeDef TIM1_FLAG)
Checks whether the specified TIM1 flag is set or not.
ITStatus | TIM1_GetITStatus (TIM1_IT_TypeDef TIM1_IT)
Checks whether the TIM1 interrupt has occurred or not.
uint16_t | TIM1_GetPrescaler (void)
Gets the TIM1 Prescaler value.
void | TIM1_ICInit (TIM1_Channel_TypeDef TIM1_Channel, TIM1_ICPolarity_TypeDef TIM1_ICPolarity, TIM1_ICSelection_TypeDef TIM1_ICSelection, TIM1_ICPSC_TypeDef TIM1_ICPrescaler, uint8_t TIM1_ICFilter)
Initializes the TIM1 peripheral according to the specified parameters.
void | TIM1_InternalClockConfig (void)
Configures the TIM1 internal Clock.
void | TIM1_ITConfig (TIM1_IT_TypeDef TIM1_IT, FunctionalState NewState)
Enables or disables the specified TIM1 interrupts.
void | TIM1_OC1FastConfig (FunctionalState NewState)
Configures the TIM1 Capture Compare 1 Fast feature.
void | TIM1_OC1Init (TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, TIM1_OutputNState_TypeDef TIM1_OutputNState, uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState, TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
Initializes the TIM1 Channel1 according to the specified parameters.
void | TIM1_OC1NPolarityConfig (TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
Configures the TIM1 Channel 1N polarity.
void | TIM1_OC1PolarityConfig (TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
Configures the TIM1 Channel 1 polarity.
void | TIM1_OC1PreloadConfig (FunctionalState NewState)
Enables or disables the TIM1 peripheral Preload Register on CCR1.
void | TIM1_OC2FastConfig (FunctionalState NewState)
Configures the TIM1 Capture Compare 2 Fast feature.
void | TIM1_OC2Init (TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, TIM1_OutputNState_TypeDef TIM1_OutputNState, uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState, TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
Initializes the TIM1 Channel2 according to the specified parameters.
void | TIM1_OC2NPolarityConfig (TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
Configures the TIM1 Channel 2N polarity.
void | TIM1_OC2PolarityConfig (TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
Configures the TIM1 Channel 2 polarity.
void | TIM1_OC2PreloadConfig (FunctionalState NewState)
Enables or disables the TIM1 peripheral Preload Register on CCR2.
void | TIM1_OC3FastConfig (FunctionalState NewState)
Configures the TIM1 Capture Compare 3 Fast feature.
void | TIM1_OC3Init (TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, TIM1_OutputNState_TypeDef TIM1_OutputNState, uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState, TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
Initializes the TIM1 Channel3 according to the specified parameters.
void | TIM1_OC3NPolarityConfig (TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
Configures the TIM1 Channel 3N polarity.
void | TIM1_OC3PolarityConfig (TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
Configures the TIM1 Channel 3 polarity.
void | TIM1_OC3PreloadConfig (FunctionalState NewState)
Enables or disables the TIM1 peripheral Preload Register on CCR3.
void | TIM1_OC4FastConfig (FunctionalState NewState)
Configures the TIM1 Capture Compare 4 Fast feature.
void | TIM1_OC4Init (TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState)
Initializes the TIM1 Channel4 according to the specified parameters.
void | TIM1_OC4PolarityConfig (TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
Configures the TIM1 Channel 4 polarity.
void | TIM1_OC4PreloadConfig (FunctionalState NewState)
Enables or disables the TIM1 peripheral Preload Register on CCR4.
void | TIM1_PrescalerConfig (uint16_t Prescaler, TIM1_PSCReloadMode_TypeDef TIM1_PSCReloadMode)
Configures the TIM1 Prescaler.
void | TIM1_PWMIConfig (TIM1_Channel_TypeDef TIM1_Channel, TIM1_ICPolarity_TypeDef TIM1_ICPolarity, TIM1_ICSelection_TypeDef TIM1_ICSelection, TIM1_ICPSC_TypeDef TIM1_ICPrescaler, uint8_t TIM1_ICFilter)
Configures the TIM1 peripheral in PWM Input Mode according to the specified parameters.
void | TIM1_SelectCOM (FunctionalState NewState)
Selects the TIM1 peripheral Commutation event.
void | TIM1_SelectHallSensor (FunctionalState NewState)
Enables or Disables the TIM1’s Hall sensor interface.
void | TIM1_SelectInputTrigger (TIM1_TS_TypeDef TIM1_InputTriggerSource)
Selects the TIM1 Input Trigger source.
void | TIM1_SelectMasterSlaveMode (FunctionalState NewState)
Sets or Resets the TIM1 Master/Slave Mode.
void | TIM1_SelectOCxM (TIM1_Channel_TypeDef TIM1_Channel, TIM1_OCMode_TypeDef TIM1_OCMode)
Selects the TIM1 Output Compare Mode.
void | TIM1_SelectOnePulseMode (TIM1_OPMode_TypeDef TIM1_OPMode)
Selects the TIM1’s One Pulse Mode.
void | TIM1_SelectOutputTrigger (TIM1_TRGOSource_TypeDef TIM1_TRGOSource)
Selects the TIM1 Trigger Output Mode.
void | TIM1_SelectSlaveMode (TIM1_SlaveMode_TypeDef TIM1_SlaveMode)
Selects the TIM1 Slave Mode.
void | TIM1_SetAutoreload (uint16_t Autoreload)
Sets the TIM1 Autoreload Register value.
void | TIM1_SetCompare1 (uint16_t Compare1)
Sets the TIM1 Capture Compare1 Register value.
void | TIM1_SetCompare2 (uint16_t Compare2)
Sets the TIM1 Capture Compare2 Register value.
void | TIM1_SetCompare3 (uint16_t Compare3)
Sets the TIM1 Capture Compare3 Register value.
void | TIM1_SetCompare4 (uint16_t Compare4)
Sets the TIM1 Capture Compare4 Register value.
void | TIM1_SetCounter (uint16_t Counter)
Sets the TIM1 Counter Register value.
void | TIM1_SetIC1Prescaler (TIM1_ICPSC_TypeDef TIM1_IC1Prescaler)
Sets the TIM1 Input Capture 1 prescaler.
void | TIM1_SetIC2Prescaler (TIM1_ICPSC_TypeDef TIM1_IC2Prescaler)
Sets the TIM1 Input Capture 2 prescaler.
void | TIM1_SetIC3Prescaler (TIM1_ICPSC_TypeDef TIM1_IC3Prescaler)
Sets the TIM1 Input Capture 3 prescaler.
void | TIM1_SetIC4Prescaler (TIM1_ICPSC_TypeDef TIM1_IC4Prescaler)
Sets the TIM1 Input Capture 4 prescaler.
void | TIM1_TimeBaseInit (uint16_t TIM1_Prescaler, TIM1_CounterMode_TypeDef TIM1_CounterMode, uint16_t TIM1_Period, uint8_t TIM1_RepetitionCounter)
Initializes the TIM1 Time Base Unit according to the specified parameters.
void | TIM1_TIxExternalClockConfig (TIM1_TIxExternalCLK1Source_TypeDef TIM1_TIxExternalCLKSource, TIM1_ICPolarity_TypeDef TIM1_ICPolarity, uint8_t ICFilter)
Configures the TIM1 Trigger as External Clock.
void | TIM1_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM1 Update event.
void | TIM1_UpdateRequestConfig (TIM1_UpdateSource_TypeDef TIM1_UpdateSource)
Selects the TIM1 Update Request Interrupt source.

Detailed Description

This file contains all the functions for the TIM1 peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_tim1.c.


STM8S/A Standard Peripherals Drivers: stm8s_tim1.h File Reference

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Defines | Enumerations | Functions
stm8s_tim1.h File Reference

This file contains all functions prototype and macros for the TIM1 peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_TIM1_AUTOMATIC_OUTPUT_STATE_OK(STATE)
#define | IS_TIM1_BREAK_POLARITY_OK(POLARITY)
#define | IS_TIM1_BREAK_STATE_OK(STATE)
#define | IS_TIM1_CHANNEL_OK(CHANNEL)
#define | IS_TIM1_CLEAR_FLAG_OK(FLAG) ((((uint16_t)(FLAG) & (uint16_t)0xE100) == 0x0000) && ((FLAG) != 0x0000))
#define | IS_TIM1_COMPLEMENTARY_CHANNEL_OK(CHANNEL)
#define | IS_TIM1_COUNTER_MODE_OK(MODE)
#define | IS_TIM1_ENCODER_MODE_OK(MODE)
#define | IS_TIM1_EVENT_SOURCE_OK(SOURCE) ((SOURCE) != 0x00)
#define | IS_TIM1_EXT_POLARITY_OK(POLARITY)
#define | IS_TIM1_EXT_PRESCALER_OK(PRESCALER)
#define | IS_TIM1_EXT_TRG_FILTER_OK(FILTER) ((FILTER) <= 0x0F)
TIM1 External Trigger Filer Value.
#define | IS_TIM1_FORCED_ACTION_OK(ACTION)
#define | IS_TIM1_GET_FLAG_OK(FLAG)
#define | IS_TIM1_GET_IT_OK(IT)
#define | IS_TIM1_IC_FILTER_OK(ICFILTER) ((ICFILTER) <= 0x0F)
TIM1 Input Capture Filer Value.
#define | IS_TIM1_IC_POLARITY_OK(POLARITY)
#define | IS_TIM1_IC_PRESCALER_OK(PRESCALER)
#define | IS_TIM1_IC_SELECTION_OK(SELECTION)
#define | IS_TIM1_IT_OK(IT) ((IT) != 0x00)
#define | IS_TIM1_LOCK_LEVEL_OK(LEVEL)
#define | IS_TIM1_OC_MODE_OK(MODE)
#define | IS_TIM1_OC_POLARITY_OK(POLARITY)
#define | IS_TIM1_OCIDLE_STATE_OK(STATE)
#define | IS_TIM1_OCM_OK(MODE)
#define | IS_TIM1_OCN_POLARITY_OK(POLARITY)
#define | IS_TIM1_OCNIDLE_STATE_OK(STATE)
#define | IS_TIM1_OPM_MODE_OK(MODE)
#define | IS_TIM1_OSSI_STATE_OK(STATE)
#define | IS_TIM1_OUTPUT_STATE_OK(STATE)
#define | IS_TIM1_OUTPUTN_STATE_OK(STATE)
#define | IS_TIM1_PRESCALER_RELOAD_OK(RELOAD)
#define | IS_TIM1_PWMI_CHANNEL_OK(CHANNEL)
#define | IS_TIM1_SLAVE_MODE_OK(MODE)
#define | IS_TIM1_TIX_TRIGGER_SELECTION_OK(SELECTION)
#define | IS_TIM1_TIXCLK_SOURCE_OK(SOURCE)
#define | IS_TIM1_TRGO_SOURCE_OK(SOURCE)
#define | IS_TIM1_TRIGGER_SELECTION_OK(SELECTION)
#define | IS_TIM1_UPDATE_SOURCE_OK(SOURCE)

Enumerations

enum | TIM1_AutomaticOutput_TypeDef { TIM1_AUTOMATICOUTPUT_ENABLE = ((uint8_t)0x40), TIM1_AUTOMATICOUTPUT_DISABLE = ((uint8_t)0x00) }
TIM1 AOE Bit Set/Reset. More...
enum | TIM1_BreakPolarity_TypeDef { TIM1_BREAKPOLARITY_LOW = ((uint8_t)0x00), TIM1_BREAKPOLARITY_HIGH = ((uint8_t)0x20) }
TIM1 Break Polarity. More...
enum | TIM1_BreakState_TypeDef { TIM1_BREAK_ENABLE = ((uint8_t)0x10), TIM1_BREAK_DISABLE = ((uint8_t)0x00) }
TIM1 Break Input enable/disable. More...
enum | TIM1_Channel_TypeDef { TIM1_CHANNEL_1 = ((uint8_t)0x00), TIM1_CHANNEL_2 = ((uint8_t)0x01), TIM1_CHANNEL_3 = ((uint8_t)0x02), TIM1_CHANNEL_4 = ((uint8_t)0x03) }
TIM1 Channel. More...
enum TIM1_CounterMode_TypeDef {
TIM1_COUNTERMODE_UP = ((uint8_t)0x00), TIM1_COUNTERMODE_DOWN = ((uint8_t)0x10), TIM1_COUNTERMODE_CENTERALIGNED1 = ((uint8_t)0x20), TIM1_COUNTERMODE_CENTERALIGNED2 = ((uint8_t)0x40),
TIM1_COUNTERMODE_CENTERALIGNED3 = ((uint8_t)0x60)
}
TIM1 Counter Mode. More...
enum | TIM1_EncoderMode_TypeDef { TIM1_ENCODERMODE_TI1 = ((uint8_t)0x01), TIM1_ENCODERMODE_TI2 = ((uint8_t)0x02), TIM1_ENCODERMODE_TI12 = ((uint8_t)0x03) }
TIM1 Encoder Mode. More...
enum TIM1_EventSource_TypeDef {
TIM1_EVENTSOURCE_UPDATE = ((uint8_t)0x01), TIM1_EVENTSOURCE_CC1 = ((uint8_t)0x02), TIM1_EVENTSOURCE_CC2 = ((uint8_t)0x04), TIM1_EVENTSOURCE_CC3 = ((uint8_t)0x08),
TIM1_EVENTSOURCE_CC4 = ((uint8_t)0x10), TIM1_EVENTSOURCE_COM = ((uint8_t)0x20), TIM1_EVENTSOURCE_TRIGGER = ((uint8_t)0x40), TIM1_EVENTSOURCE_BREAK = ((uint8_t)0x80)
}
TIM1 Event Source. More...
enum | TIM1_ExtTRGPolarity_TypeDef { TIM1_EXTTRGPOLARITY_INVERTED = ((uint8_t)0x80), TIM1_EXTTRGPOLARITY_NONINVERTED = ((uint8_t)0x00) }
TIM1 External Trigger Polarity. More...
enum | TIM1_ExtTRGPSC_TypeDef { TIM1_EXTTRGPSC_OFF = ((uint8_t)0x00), TIM1_EXTTRGPSC_DIV2 = ((uint8_t)0x10), TIM1_EXTTRGPSC_DIV4 = ((uint8_t)0x20), TIM1_EXTTRGPSC_DIV8 = ((uint8_t)0x30) }
TIM1 External Trigger Prescaler. More...
enum TIM1_FLAG_TypeDef {
TIM1_FLAG_UPDATE = ((uint16_t)0x0001), TIM1_FLAG_CC1 = ((uint16_t)0x0002), TIM1_FLAG_CC2 = ((uint16_t)0x0004), TIM1_FLAG_CC3 = ((uint16_t)0x0008),
TIM1_FLAG_CC4 = ((uint16_t)0x0010), TIM1_FLAG_COM = ((uint16_t)0x0020), TIM1_FLAG_TRIGGER = ((uint16_t)0x0040), TIM1_FLAG_BREAK = ((uint16_t)0x0080),
TIM1_FLAG_CC1OF = ((uint16_t)0x0200), TIM1_FLAG_CC2OF = ((uint16_t)0x0400), TIM1_FLAG_CC3OF = ((uint16_t)0x0800), TIM1_FLAG_CC4OF = ((uint16_t)0x1000)
}
TIM1 Flags. More...
enum | TIM1_ForcedAction_TypeDef { TIM1_FORCEDACTION_ACTIVE = ((uint8_t)0x50), TIM1_FORCEDACTION_INACTIVE = ((uint8_t)0x40) }
TIM1 Forced Action. More...
enum | TIM1_ICPolarity_TypeDef { TIM1_ICPOLARITY_RISING = ((uint8_t)0x00), TIM1_ICPOLARITY_FALLING = ((uint8_t)0x01) }
TIM1 Input Capture Polarity. More...
enum | TIM1_ICPSC_TypeDef { TIM1_ICPSC_DIV1 = ((uint8_t)0x00), TIM1_ICPSC_DIV2 = ((uint8_t)0x04), TIM1_ICPSC_DIV4 = ((uint8_t)0x08), TIM1_ICPSC_DIV8 = ((uint8_t)0x0C) }
TIM1 Input Capture Prescaler. More...
enum | TIM1_ICSelection_TypeDef { TIM1_ICSELECTION_DIRECTTI = ((uint8_t)0x01), TIM1_ICSELECTION_INDIRECTTI = ((uint8_t)0x02), TIM1_ICSELECTION_TRGI = ((uint8_t)0x03) }
TIM1 Input Capture Selection. More...
enum TIM1_IT_TypeDef {
TIM1_IT_UPDATE = ((uint8_t)0x01), TIM1_IT_CC1 = ((uint8_t)0x02), TIM1_IT_CC2 = ((uint8_t)0x04), TIM1_IT_CC3 = ((uint8_t)0x08),
TIM1_IT_CC4 = ((uint8_t)0x10), TIM1_IT_COM = ((uint8_t)0x20), TIM1_IT_TRIGGER = ((uint8_t)0x40), TIM1_IT_BREAK = ((uint8_t)0x80)
}
TIM1 interrupt sources. More...
enum | TIM1_LockLevel_TypeDef { TIM1_LOCKLEVEL_OFF = ((uint8_t)0x00), TIM1_LOCKLEVEL_1 = ((uint8_t)0x01), TIM1_LOCKLEVEL_2 = ((uint8_t)0x02), TIM1_LOCKLEVEL_3 = ((uint8_t)0x03) }
TIM1 Lock levels. More...
enum | TIM1_OCIdleState_TypeDef { TIM1_OCIDLESTATE_SET = ((uint8_t)0x55), TIM1_OCIDLESTATE_RESET = ((uint8_t)0x00) }
TIM1 Output Compare Idle State. More...
enum TIM1_OCMode_TypeDef {
TIM1_OCMODE_TIMING = ((uint8_t)0x00), TIM1_OCMODE_ACTIVE = ((uint8_t)0x10), TIM1_OCMODE_INACTIVE = ((uint8_t)0x20), TIM1_OCMODE_TOGGLE = ((uint8_t)0x30),
TIM1_OCMODE_PWM1 = ((uint8_t)0x60), TIM1_OCMODE_PWM2 = ((uint8_t)0x70)
}
TIM1 Output Compare and PWM modes. More...
enum | TIM1_OCNIdleState_TypeDef { TIM1_OCNIDLESTATE_SET = ((uint8_t)0x2A), TIM1_OCNIDLESTATE_RESET = ((uint8_t)0x00) }
TIM1 Output Compare N Idle State. More...
enum | TIM1_OCNPolarity_TypeDef { TIM1_OCNPOLARITY_HIGH = ((uint8_t)0x00), TIM1_OCNPOLARITY_LOW = ((uint8_t)0x88) }
TIM1 Output Compare N Polarity. More...
enum | TIM1_OCPolarity_TypeDef { TIM1_OCPOLARITY_HIGH = ((uint8_t)0x00), TIM1_OCPOLARITY_LOW = ((uint8_t)0x22) }
TIM1 Output Compare Polarity. More...
enum | TIM1_OPMode_TypeDef { TIM1_OPMODE_SINGLE = ((uint8_t)0x01), TIM1_OPMODE_REPETITIVE = ((uint8_t)0x00) }
TIM1 One Pulse Mode. More...
enum | TIM1_OSSIState_TypeDef { TIM1_OSSISTATE_ENABLE = ((uint8_t)0x04), TIM1_OSSISTATE_DISABLE = ((uint8_t)0x00) }
TIM1 OSSI: Off-State Selection for Idle mode states. More...
enum | TIM1_OutputNState_TypeDef { TIM1_OUTPUTNSTATE_DISABLE = ((uint8_t)0x00), TIM1_OUTPUTNSTATE_ENABLE = ((uint8_t)0x44) }
TIM1 Output Compare N States. More...
enum | TIM1_OutputState_TypeDef { TIM1_OUTPUTSTATE_DISABLE = ((uint8_t)0x00), TIM1_OUTPUTSTATE_ENABLE = ((uint8_t)0x11) }
TIM1 Output Compare states. More...
enum | TIM1_PSCReloadMode_TypeDef { TIM1_PSCRELOADMODE_UPDATE = ((uint8_t)0x00), TIM1_PSCRELOADMODE_IMMEDIATE = ((uint8_t)0x01) }
TIM1 Prescaler Reload Mode. More...
enum | TIM1_SlaveMode_TypeDef { TIM1_SLAVEMODE_RESET = ((uint8_t)0x04), TIM1_SLAVEMODE_GATED = ((uint8_t)0x05), TIM1_SLAVEMODE_TRIGGER = ((uint8_t)0x06), TIM1_SLAVEMODE_EXTERNAL1 = ((uint8_t)0x07) }
TIM1 Slave Mode. More...
enum | TIM1_TIxExternalCLK1Source_TypeDef { TIM1_TIXEXTERNALCLK1SOURCE_TI1ED = ((uint8_t)0x40), TIM1_TIXEXTERNALCLK1SOURCE_TI1 = ((uint8_t)0x50), TIM1_TIXEXTERNALCLK1SOURCE_TI2 = ((uint8_t)0x60) }
TIM1 TIx External Clock Source. More...
enum TIM1_TRGOSource_TypeDef {
TIM1_TRGOSOURCE_RESET = ((uint8_t)0x00), TIM1_TRGOSOURCE_ENABLE = ((uint8_t)0x10), TIM1_TRGOSOURCE_UPDATE = ((uint8_t)0x20), TIM1_TRGOSource_OC1 = ((uint8_t)0x30),
TIM1_TRGOSOURCE_OC1REF = ((uint8_t)0x40), TIM1_TRGOSOURCE_OC2REF = ((uint8_t)0x50), TIM1_TRGOSOURCE_OC3REF = ((uint8_t)0x60)
}
TIM1 Trigger Output Source. More...
enum TIM1_TS_TypeDef {
TIM1_TS_TIM6 = ((uint8_t)0x00), TIM1_TS_TIM5 = ((uint8_t)0x30), TIM1_TS_TI1F_ED = ((uint8_t)0x40), TIM1_TS_TI1FP1 = ((uint8_t)0x50),
TIM1_TS_TI2FP2 = ((uint8_t)0x60), TIM1_TS_ETRF = ((uint8_t)0x70)
}
TIM1 Internal Trigger Selection. More...
enum | TIM1_UpdateSource_TypeDef { TIM1_UPDATESOURCE_GLOBAL = ((uint8_t)0x00), TIM1_UPDATESOURCE_REGULAR = ((uint8_t)0x01) }
TIM1 Update Source. More...

Functions

void | TIM1_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM1 peripheral Preload register on ARR.
void | TIM1_BDTRConfig (TIM1_OSSIState_TypeDef TIM1_OSSIState, TIM1_LockLevel_TypeDef TIM1_LockLevel, uint8_t TIM1_DeadTime, TIM1_BreakState_TypeDef TIM1_Break, TIM1_BreakPolarity_TypeDef TIM1_BreakPolarity, TIM1_AutomaticOutput_TypeDef TIM1_AutomaticOutput)
Configures the Break feature, dead time, Lock level, the OSSI, and the AOE(automatic output enable).
void | TIM1_CCPreloadControl (FunctionalState NewState)
Sets or Resets the TIM1 peripheral Capture Compare Preload Control bit.
void | TIM1_CCxCmd (TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState)
Enables or disables the TIM1 Capture Compare Channel x (x=1,..,4).
void | TIM1_CCxNCmd (TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState)
Enables or disables the TIM1 Capture Compare Channel xN (xN=1,..,3).
void | TIM1_ClearFlag (TIM1_FLAG_TypeDef TIM1_FLAG)
Clears the TIM1’s pending flags.
void | TIM1_ClearITPendingBit (TIM1_IT_TypeDef TIM1_IT)
Clears the TIM1's interrupt pending bits.
void | TIM1_Cmd (FunctionalState NewState)
Enables or disables the TIM1 peripheral.
void | TIM1_CounterModeConfig (TIM1_CounterMode_TypeDef TIM1_CounterMode)
Specifies the TIM1 Counter Mode to be used.
void | TIM1_CtrlPWMOutputs (FunctionalState NewState)
Enables or disables the TIM1 peripheral Main Outputs.
void | TIM1_DeInit (void)
Deinitializes the TIM1 peripheral registers to their default reset values.
void | TIM1_EncoderInterfaceConfig (TIM1_EncoderMode_TypeDef TIM1_EncoderMode, TIM1_ICPolarity_TypeDef TIM1_IC1Polarity, TIM1_ICPolarity_TypeDef TIM1_IC2Polarity)
Configures the TIM1 Encoder Interface.
void | TIM1_ETRClockMode1Config (TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, uint8_t ExtTRGFilter)
Configures the TIM1 External clock Mode1.
void | TIM1_ETRClockMode2Config (TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, uint8_t ExtTRGFilter)
Configures the TIM1 External clock Mode2.
void | TIM1_ETRConfig (TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, uint8_t ExtTRGFilter)
Configures the TIM1 External Trigger.
void | TIM1_ForcedOC1Config (TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
Forces the TIM1 Channel1 output waveform to active or inactive level.
void | TIM1_ForcedOC2Config (TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
Forces the TIM1 Channel2 output waveform to active or inactive level.
void | TIM1_ForcedOC3Config (TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
Forces the TIM1 Channel3 output waveform to active or inactive level.
void | TIM1_ForcedOC4Config (TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
Forces the TIM1 Channel4 output waveform to active or inactive level.
void | TIM1_GenerateEvent (TIM1_EventSource_TypeDef TIM1_EventSource)
Configures the TIM1 event to be generated by software.
uint16_t | TIM1_GetCapture1 (void)
Gets the TIM1 Input Capture 1 value.
uint16_t | TIM1_GetCapture2 (void)
Gets the TIM1 Input Capture 2 value.
uint16_t | TIM1_GetCapture3 (void)
Gets the TIM1 Input Capture 3 value.
uint16_t | TIM1_GetCapture4 (void)
Gets the TIM1 Input Capture 4 value.
uint16_t | TIM1_GetCounter (void)
Gets the TIM1 Counter value.
FlagStatus | TIM1_GetFlagStatus (TIM1_FLAG_TypeDef TIM1_FLAG)
Checks whether the specified TIM1 flag is set or not.
ITStatus | TIM1_GetITStatus (TIM1_IT_TypeDef TIM1_IT)
Checks whether the TIM1 interrupt has occurred or not.
uint16_t | TIM1_GetPrescaler (void)
Gets the TIM1 Prescaler value.
void | TIM1_ICInit (TIM1_Channel_TypeDef TIM1_Channel, TIM1_ICPolarity_TypeDef TIM1_ICPolarity, TIM1_ICSelection_TypeDef TIM1_ICSelection, TIM1_ICPSC_TypeDef TIM1_ICPrescaler, uint8_t TIM1_ICFilter)
Initializes the TIM1 peripheral according to the specified parameters.
void | TIM1_InternalClockConfig (void)
Configures the TIM1 internal Clock.
void | TIM1_ITConfig (TIM1_IT_TypeDef TIM1_IT, FunctionalState NewState)
Enables or disables the specified TIM1 interrupts.
void | TIM1_OC1FastConfig (FunctionalState NewState)
Configures the TIM1 Capture Compare 1 Fast feature.
void | TIM1_OC1Init (TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, TIM1_OutputNState_TypeDef TIM1_OutputNState, uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState, TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
Initializes the TIM1 Channel1 according to the specified parameters.
void | TIM1_OC1NPolarityConfig (TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
Configures the TIM1 Channel 1N polarity.
void | TIM1_OC1PolarityConfig (TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
Configures the TIM1 Channel 1 polarity.
void | TIM1_OC1PreloadConfig (FunctionalState NewState)
Enables or disables the TIM1 peripheral Preload Register on CCR1.
void | TIM1_OC2FastConfig (FunctionalState NewState)
Configures the TIM1 Capture Compare 2 Fast feature.
void | TIM1_OC2Init (TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, TIM1_OutputNState_TypeDef TIM1_OutputNState, uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState, TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
Initializes the TIM1 Channel2 according to the specified parameters.
void | TIM1_OC2NPolarityConfig (TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
Configures the TIM1 Channel 2N polarity.
void | TIM1_OC2PolarityConfig (TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
Configures the TIM1 Channel 2 polarity.
void | TIM1_OC2PreloadConfig (FunctionalState NewState)
Enables or disables the TIM1 peripheral Preload Register on CCR2.
void | TIM1_OC3FastConfig (FunctionalState NewState)
Configures the TIM1 Capture Compare 3 Fast feature.
void | TIM1_OC3Init (TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, TIM1_OutputNState_TypeDef TIM1_OutputNState, uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState, TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
Initializes the TIM1 Channel3 according to the specified parameters.
void | TIM1_OC3NPolarityConfig (TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
Configures the TIM1 Channel 3N polarity.
void | TIM1_OC3PolarityConfig (TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
Configures the TIM1 Channel 3 polarity.
void | TIM1_OC3PreloadConfig (FunctionalState NewState)
Enables or disables the TIM1 peripheral Preload Register on CCR3.
void | TIM1_OC4FastConfig (FunctionalState NewState)
Configures the TIM1 Capture Compare 4 Fast feature.
void | TIM1_OC4Init (TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState)
Initializes the TIM1 Channel4 according to the specified parameters.
void | TIM1_OC4PolarityConfig (TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
Configures the TIM1 Channel 4 polarity.
void | TIM1_OC4PreloadConfig (FunctionalState NewState)
Enables or disables the TIM1 peripheral Preload Register on CCR4.
void | TIM1_PrescalerConfig (uint16_t Prescaler, TIM1_PSCReloadMode_TypeDef TIM1_PSCReloadMode)
Configures the TIM1 Prescaler.
void | TIM1_PWMIConfig (TIM1_Channel_TypeDef TIM1_Channel, TIM1_ICPolarity_TypeDef TIM1_ICPolarity, TIM1_ICSelection_TypeDef TIM1_ICSelection, TIM1_ICPSC_TypeDef TIM1_ICPrescaler, uint8_t TIM1_ICFilter)
Configures the TIM1 peripheral in PWM Input Mode according to the specified parameters.
void | TIM1_SelectCOM (FunctionalState NewState)
Selects the TIM1 peripheral Commutation event.
void | TIM1_SelectHallSensor (FunctionalState NewState)
Enables or Disables the TIM1’s Hall sensor interface.
void | TIM1_SelectInputTrigger (TIM1_TS_TypeDef TIM1_InputTriggerSource)
Selects the TIM1 Input Trigger source.
void | TIM1_SelectMasterSlaveMode (FunctionalState NewState)
Sets or Resets the TIM1 Master/Slave Mode.
void | TIM1_SelectOCxM (TIM1_Channel_TypeDef TIM1_Channel, TIM1_OCMode_TypeDef TIM1_OCMode)
Selects the TIM1 Output Compare Mode.
void | TIM1_SelectOnePulseMode (TIM1_OPMode_TypeDef TIM1_OPMode)
Selects the TIM1’s One Pulse Mode.
void | TIM1_SelectOutputTrigger (TIM1_TRGOSource_TypeDef TIM1_TRGOSource)
Selects the TIM1 Trigger Output Mode.
void | TIM1_SelectSlaveMode (TIM1_SlaveMode_TypeDef TIM1_SlaveMode)
Selects the TIM1 Slave Mode.
void | TIM1_SetAutoreload (uint16_t Autoreload)
Sets the TIM1 Autoreload Register value.
void | TIM1_SetCompare1 (uint16_t Compare1)
Sets the TIM1 Capture Compare1 Register value.
void | TIM1_SetCompare2 (uint16_t Compare2)
Sets the TIM1 Capture Compare2 Register value.
void | TIM1_SetCompare3 (uint16_t Compare3)
Sets the TIM1 Capture Compare3 Register value.
void | TIM1_SetCompare4 (uint16_t Compare4)
Sets the TIM1 Capture Compare4 Register value.
void | TIM1_SetCounter (uint16_t Counter)
Sets the TIM1 Counter Register value.
void | TIM1_SetIC1Prescaler (TIM1_ICPSC_TypeDef TIM1_IC1Prescaler)
Sets the TIM1 Input Capture 1 prescaler.
void | TIM1_SetIC2Prescaler (TIM1_ICPSC_TypeDef TIM1_IC2Prescaler)
Sets the TIM1 Input Capture 2 prescaler.
void | TIM1_SetIC3Prescaler (TIM1_ICPSC_TypeDef TIM1_IC3Prescaler)
Sets the TIM1 Input Capture 3 prescaler.
void | TIM1_SetIC4Prescaler (TIM1_ICPSC_TypeDef TIM1_IC4Prescaler)
Sets the TIM1 Input Capture 4 prescaler.
void | TIM1_TimeBaseInit (uint16_t TIM1_Prescaler, TIM1_CounterMode_TypeDef TIM1_CounterMode, uint16_t TIM1_Period, uint8_t TIM1_RepetitionCounter)
Initializes the TIM1 Time Base Unit according to the specified parameters.
void | TIM1_TIxExternalClockConfig (TIM1_TIxExternalCLK1Source_TypeDef TIM1_TIxExternalCLKSource, TIM1_ICPolarity_TypeDef TIM1_ICPolarity, uint8_t ICFilter)
Configures the TIM1 Trigger as External Clock.
void | TIM1_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM1 Update event.
void | TIM1_UpdateRequestConfig (TIM1_UpdateSource_TypeDef TIM1_UpdateSource)
Selects the TIM1 Update Request Interrupt source.

Detailed Description

This file contains all functions prototype and macros for the TIM1 peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_tim1.h.


STM8S/A Standard Peripherals Drivers: stm8s_tim2.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions
stm8s_tim2.c File Reference

This file contains all the functions for the TIM2 peripheral. More...

#include "stm8s_tim2.h"

Go to the source code of this file.

Functions

static void | TI1_Config (uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
Configure the TI1 as Input.
static void | TI1_Config (uint8_t TIM2_ICPolarity, uint8_t TIM2_ICSelection, uint8_t TIM2_ICFilter)
Configure the TI1 as Input.
static void | TI2_Config (uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
Configure the TI2 as Input.
static void | TI2_Config (uint8_t TIM2_ICPolarity, uint8_t TIM2_ICSelection, uint8_t TIM2_ICFilter)
Configure the TI2 as Input.
static void | TI3_Config (uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
Configure the TI3 as Input.
static void | TI3_Config (uint8_t TIM2_ICPolarity, uint8_t TIM2_ICSelection, uint8_t TIM2_ICFilter)
Configure the TI3 as Input.
void | TIM2_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM2 peripheral Preload register on ARR.
void | TIM2_CCxCmd (TIM2_Channel_TypeDef TIM2_Channel, FunctionalState NewState)
Enables or disables the TIM2 Capture Compare Channel x.
void | TIM2_ClearFlag (TIM2_FLAG_TypeDef TIM2_FLAG)
Clears the TIM2’s pending flags.
void | TIM2_ClearITPendingBit (TIM2_IT_TypeDef TIM2_IT)
Clears the TIM2's interrupt pending bits.
void | TIM2_Cmd (FunctionalState NewState)
Enables or disables the TIM2 peripheral.
void | TIM2_DeInit (void)
Deinitializes the TIM2 peripheral registers to their default reset values.
void | TIM2_ForcedOC1Config (TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
Forces the TIM2 Channel1 output waveform to active or inactive level.
void | TIM2_ForcedOC2Config (TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
Forces the TIM2 Channel2 output waveform to active or inactive level.
void | TIM2_ForcedOC3Config (TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
Forces the TIM2 Channel3 output waveform to active or inactive level.
void | TIM2_GenerateEvent (TIM2_EventSource_TypeDef TIM2_EventSource)
Configures the TIM2 event to be generated by software.
uint16_t | TIM2_GetCapture1 (void)
Gets the TIM2 Input Capture 1 value.
uint16_t | TIM2_GetCapture2 (void)
Gets the TIM2 Input Capture 2 value.
uint16_t | TIM2_GetCapture3 (void)
Gets the TIM2 Input Capture 3 value.
uint16_t | TIM2_GetCounter (void)
Gets the TIM2 Counter value.
FlagStatus | TIM2_GetFlagStatus (TIM2_FLAG_TypeDef TIM2_FLAG)
Checks whether the specified TIM2 flag is set or not.
ITStatus | TIM2_GetITStatus (TIM2_IT_TypeDef TIM2_IT)
Checks whether the TIM2 interrupt has occurred or not.
TIM2_Prescaler_TypeDef | TIM2_GetPrescaler (void)
Gets the TIM2 Prescaler value.
void | TIM2_ICInit (TIM2_Channel_TypeDef TIM2_Channel, TIM2_ICPolarity_TypeDef TIM2_ICPolarity, TIM2_ICSelection_TypeDef TIM2_ICSelection, TIM2_ICPSC_TypeDef TIM2_ICPrescaler, uint8_t TIM2_ICFilter)
Initializes the TIM2 peripheral according to the specified parameters.
void | TIM2_ITConfig (TIM2_IT_TypeDef TIM2_IT, FunctionalState NewState)
Enables or disables the specified TIM2 interrupts.
void | TIM2_OC1Init (TIM2_OCMode_TypeDef TIM2_OCMode, TIM2_OutputState_TypeDef TIM2_OutputState, uint16_t TIM2_Pulse, TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Initializes the TIM2 Channel1 according to the specified parameters.
void | TIM2_OC1PolarityConfig (TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Configures the TIM2 Channel 1 polarity.
void | TIM2_OC1PreloadConfig (FunctionalState NewState)
Enables or disables the TIM2 peripheral Preload Register on CCR1.
void | TIM2_OC2Init (TIM2_OCMode_TypeDef TIM2_OCMode, TIM2_OutputState_TypeDef TIM2_OutputState, uint16_t TIM2_Pulse, TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Initializes the TIM2 Channel2 according to the specified parameters.
void | TIM2_OC2PolarityConfig (TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Configures the TIM2 Channel 2 polarity.
void | TIM2_OC2PreloadConfig (FunctionalState NewState)
Enables or disables the TIM2 peripheral Preload Register on CCR2.
void | TIM2_OC3Init (TIM2_OCMode_TypeDef TIM2_OCMode, TIM2_OutputState_TypeDef TIM2_OutputState, uint16_t TIM2_Pulse, TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Initializes the TIM2 Channel3 according to the specified parameters.
void | TIM2_OC3PolarityConfig (TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Configures the TIM2 Channel 3 polarity.
void | TIM2_OC3PreloadConfig (FunctionalState NewState)
Enables or disables the TIM2 peripheral Preload Register on CCR3.
void | TIM2_PrescalerConfig (TIM2_Prescaler_TypeDef Prescaler, TIM2_PSCReloadMode_TypeDef TIM2_PSCReloadMode)
Configures the TIM2 Prescaler.
void | TIM2_PWMIConfig (TIM2_Channel_TypeDef TIM2_Channel, TIM2_ICPolarity_TypeDef TIM2_ICPolarity, TIM2_ICSelection_TypeDef TIM2_ICSelection, TIM2_ICPSC_TypeDef TIM2_ICPrescaler, uint8_t TIM2_ICFilter)
Configures the TIM2 peripheral in PWM Input Mode according to the specified parameters.
void | TIM2_SelectOCxM (TIM2_Channel_TypeDef TIM2_Channel, TIM2_OCMode_TypeDef TIM2_OCMode)
Selects the TIM2 Output Compare Mode.
void | TIM2_SelectOnePulseMode (TIM2_OPMode_TypeDef TIM2_OPMode)
Selects the TIM2’s One Pulse Mode.
void | TIM2_SetAutoreload (uint16_t Autoreload)
Sets the TIM2 Autoreload Register value.
void | TIM2_SetCompare1 (uint16_t Compare1)
Sets the TIM2 Capture Compare1 Register value.
void | TIM2_SetCompare2 (uint16_t Compare2)
Sets the TIM2 Capture Compare2 Register value.
void | TIM2_SetCompare3 (uint16_t Compare3)
Sets the TIM2 Capture Compare3 Register value.
void | TIM2_SetCounter (uint16_t Counter)
Sets the TIM2 Counter Register value.
void | TIM2_SetIC1Prescaler (TIM2_ICPSC_TypeDef TIM2_IC1Prescaler)
Sets the TIM2 Input Capture 1 Prescaler.
void | TIM2_SetIC2Prescaler (TIM2_ICPSC_TypeDef TIM2_IC2Prescaler)
Sets the TIM2 Input Capture 2 prescaler.
void | TIM2_SetIC3Prescaler (TIM2_ICPSC_TypeDef TIM2_IC3Prescaler)
Sets the TIM2 Input Capture 3 prescaler.
void | TIM2_TimeBaseInit (TIM2_Prescaler_TypeDef TIM2_Prescaler, uint16_t TIM2_Period)
Initializes the TIM2 Time Base Unit according to the specified parameters.
void | TIM2_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM2 Update event.
void | TIM2_UpdateRequestConfig (TIM2_UpdateSource_TypeDef TIM2_UpdateSource)
Selects the TIM2 Update Request Interrupt source.

Detailed Description

This file contains all the functions for the TIM2 peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_tim2.c.


STM8S/A Standard Peripherals Drivers: stm8s_tim2.h File Reference

  • File List
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  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions
stm8s_tim2.h File Reference

This file contains all functions prototype and macros for the TIM2 peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_TIM2_CHANNEL_OK(CHANNEL)
#define | IS_TIM2_CLEAR_FLAG_OK(FLAG) ((((uint16_t)(FLAG) & 0xF1F0) == 0x0000) && ((uint16_t)(FLAG) != 0x0000))
#define | IS_TIM2_EVENT_SOURCE_OK(SOURCE) (((SOURCE) != 0x00))
#define | IS_TIM2_FORCED_ACTION_OK(ACTION)
#define | IS_TIM2_GET_FLAG_OK(FLAG)
#define | IS_TIM2_GET_IT_OK(IT)
#define | IS_TIM2_IC_FILTER_OK(ICFILTER) ((ICFILTER) <= 0x0F)
TIM2 Input Capture Filer Value.
#define | IS_TIM2_IC_POLARITY_OK(POLARITY)
#define | IS_TIM2_IC_PRESCALER_OK(PRESCALER)
#define | IS_TIM2_IC_SELECTION1_OK(SELECTION)
#define | IS_TIM2_IC_SELECTION_OK(SELECTION)
#define | IS_TIM2_IT_OK(IT) (((IT) != 0x00) && ((IT) <= 0x0F))
#define | IS_TIM2_OC_MODE_OK(MODE)
#define | IS_TIM2_OC_POLARITY_OK(POLARITY)
#define | IS_TIM2_OCM_OK(MODE)
#define | IS_TIM2_OPM_MODE_OK(MODE)
#define | IS_TIM2_OUTPUT_STATE_OK(STATE)
#define | IS_TIM2_PRESCALER_OK(PRESCALER)
#define | IS_TIM2_PRESCALER_RELOAD_OK(RELOAD)
#define | IS_TIM2_PWMI_CHANNEL_OK(CHANNEL)
#define | IS_TIM2_UPDATE_SOURCE_OK(SOURCE)

Enumerations

enum | TIM2_Channel_TypeDef { TIM2_CHANNEL_1 = ((uint8_t)0x00), TIM2_CHANNEL_2 = ((uint8_t)0x01), TIM2_CHANNEL_3 = ((uint8_t)0x02) }
TIM2 Channel. More...
enum | TIM2_EventSource_TypeDef { TIM2_EVENTSOURCE_UPDATE = ((uint8_t)0x01), TIM2_EVENTSOURCE_CC1 = ((uint8_t)0x02), TIM2_EVENTSOURCE_CC2 = ((uint8_t)0x04), TIM2_EVENTSOURCE_CC3 = ((uint8_t)0x08) }
TIM2 Event Source. More...
enum TIM2_FLAG_TypeDef {
TIM2_FLAG_UPDATE = ((uint16_t)0x0001), TIM2_FLAG_CC1 = ((uint16_t)0x0002), TIM2_FLAG_CC2 = ((uint16_t)0x0004), TIM2_FLAG_CC3 = ((uint16_t)0x0008),
TIM2_FLAG_CC1OF = ((uint16_t)0x0200), TIM2_FLAG_CC2OF = ((uint16_t)0x0400), TIM2_FLAG_CC3OF = ((uint16_t)0x0800)
}
TIM2 Flags. More...
enum | TIM2_ForcedAction_TypeDef { TIM2_FORCEDACTION_ACTIVE = ((uint8_t)0x50), TIM2_FORCEDACTION_INACTIVE = ((uint8_t)0x40) }
TIM2 Forced Action. More...
enum | TIM2_ICPolarity_TypeDef { TIM2_ICPOLARITY_RISING = ((uint8_t)0x00), TIM2_ICPOLARITY_FALLING = ((uint8_t)0x44) }
TIM2 Input Capture Polarity. More...
enum | TIM2_ICPSC_TypeDef { TIM2_ICPSC_DIV1 = ((uint8_t)0x00), TIM2_ICPSC_DIV2 = ((uint8_t)0x04), TIM2_ICPSC_DIV4 = ((uint8_t)0x08), TIM2_ICPSC_DIV8 = ((uint8_t)0x0C) }
TIM2 Input Capture Prescaler. More...
enum | TIM2_ICSelection_TypeDef { TIM2_ICSELECTION_DIRECTTI = ((uint8_t)0x01), TIM2_ICSELECTION_INDIRECTTI = ((uint8_t)0x02), TIM2_ICSELECTION_TRGI = ((uint8_t)0x03) }
TIM2 Input Capture Selection. More...
enum | TIM2_IT_TypeDef { TIM2_IT_UPDATE = ((uint8_t)0x01), TIM2_IT_CC1 = ((uint8_t)0x02), TIM2_IT_CC2 = ((uint8_t)0x04), TIM2_IT_CC3 = ((uint8_t)0x08) }
TIM2 interrupt sources. More...
enum TIM2_OCMode_TypeDef {
TIM2_OCMODE_TIMING = ((uint8_t)0x00), TIM2_OCMODE_ACTIVE = ((uint8_t)0x10), TIM2_OCMODE_INACTIVE = ((uint8_t)0x20), TIM2_OCMODE_TOGGLE = ((uint8_t)0x30),
TIM2_OCMODE_PWM1 = ((uint8_t)0x60), TIM2_OCMODE_PWM2 = ((uint8_t)0x70)
}
TIM2 Output Compare and PWM modes. More...
enum | TIM2_OCPolarity_TypeDef { TIM2_OCPOLARITY_HIGH = ((uint8_t)0x00), TIM2_OCPOLARITY_LOW = ((uint8_t)0x22) }
TIM2 Output Compare Polarity. More...
enum | TIM2_OPMode_TypeDef { TIM2_OPMODE_SINGLE = ((uint8_t)0x01), TIM2_OPMODE_REPETITIVE = ((uint8_t)0x00) }
TIM2 One Pulse Mode. More...
enum | TIM2_OutputState_TypeDef { TIM2_OUTPUTSTATE_DISABLE = ((uint8_t)0x00), TIM2_OUTPUTSTATE_ENABLE = ((uint8_t)0x11) }
TIM2 Output Compare states. More...
enum TIM2_Prescaler_TypeDef {
TIM2_PRESCALER_1 = ((uint8_t)0x00), TIM2_PRESCALER_2 = ((uint8_t)0x01), TIM2_PRESCALER_4 = ((uint8_t)0x02), TIM2_PRESCALER_8 = ((uint8_t)0x03),
TIM2_PRESCALER_16 = ((uint8_t)0x04), TIM2_PRESCALER_32 = ((uint8_t)0x05), TIM2_PRESCALER_64 = ((uint8_t)0x06), TIM2_PRESCALER_128 = ((uint8_t)0x07),
TIM2_PRESCALER_256 = ((uint8_t)0x08), TIM2_PRESCALER_512 = ((uint8_t)0x09), TIM2_PRESCALER_1024 = ((uint8_t)0x0A), TIM2_PRESCALER_2048 = ((uint8_t)0x0B),
TIM2_PRESCALER_4096 = ((uint8_t)0x0C), TIM2_PRESCALER_8192 = ((uint8_t)0x0D), TIM2_PRESCALER_16384 = ((uint8_t)0x0E), TIM2_PRESCALER_32768 = ((uint8_t)0x0F)
}
TIM2 Prescaler. More...
enum | TIM2_PSCReloadMode_TypeDef { TIM2_PSCRELOADMODE_UPDATE = ((uint8_t)0x00), TIM2_PSCRELOADMODE_IMMEDIATE = ((uint8_t)0x01) }
TIM2 Prescaler Reload Mode. More...
enum | TIM2_UpdateSource_TypeDef { TIM2_UPDATESOURCE_GLOBAL = ((uint8_t)0x00), TIM2_UPDATESOURCE_REGULAR = ((uint8_t)0x01) }
TIM2 Update Source. More...

Functions

void | TIM2_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM2 peripheral Preload register on ARR.
void | TIM2_CCPreloadControl (FunctionalState NewState)
void | TIM2_CCxCmd (TIM2_Channel_TypeDef TIM2_Channel, FunctionalState NewState)
Enables or disables the TIM2 Capture Compare Channel x.
void | TIM2_ClearFlag (TIM2_FLAG_TypeDef TIM2_FLAG)
Clears the TIM2’s pending flags.
void | TIM2_ClearITPendingBit (TIM2_IT_TypeDef TIM2_IT)
Clears the TIM2's interrupt pending bits.
void | TIM2_Cmd (FunctionalState NewState)
Enables or disables the TIM2 peripheral.
void | TIM2_DeInit (void)
Deinitializes the TIM2 peripheral registers to their default reset values.
void | TIM2_ForcedOC1Config (TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
Forces the TIM2 Channel1 output waveform to active or inactive level.
void | TIM2_ForcedOC2Config (TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
Forces the TIM2 Channel2 output waveform to active or inactive level.
void | TIM2_ForcedOC3Config (TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
Forces the TIM2 Channel3 output waveform to active or inactive level.
void | TIM2_GenerateEvent (TIM2_EventSource_TypeDef TIM2_EventSource)
Configures the TIM2 event to be generated by software.
uint16_t | TIM2_GetCapture1 (void)
Gets the TIM2 Input Capture 1 value.
uint16_t | TIM2_GetCapture2 (void)
Gets the TIM2 Input Capture 2 value.
uint16_t | TIM2_GetCapture3 (void)
Gets the TIM2 Input Capture 3 value.
uint16_t | TIM2_GetCounter (void)
Gets the TIM2 Counter value.
FlagStatus | TIM2_GetFlagStatus (TIM2_FLAG_TypeDef TIM2_FLAG)
Checks whether the specified TIM2 flag is set or not.
ITStatus | TIM2_GetITStatus (TIM2_IT_TypeDef TIM2_IT)
Checks whether the TIM2 interrupt has occurred or not.
TIM2_Prescaler_TypeDef | TIM2_GetPrescaler (void)
Gets the TIM2 Prescaler value.
void | TIM2_ICInit (TIM2_Channel_TypeDef TIM2_Channel, TIM2_ICPolarity_TypeDef TIM2_ICPolarity, TIM2_ICSelection_TypeDef TIM2_ICSelection, TIM2_ICPSC_TypeDef TIM2_ICPrescaler, uint8_t TIM2_ICFilter)
Initializes the TIM2 peripheral according to the specified parameters.
void | TIM2_InternalClockConfig (void)
void | TIM2_ITConfig (TIM2_IT_TypeDef TIM2_IT, FunctionalState NewState)
Enables or disables the specified TIM2 interrupts.
void | TIM2_OC1Init (TIM2_OCMode_TypeDef TIM2_OCMode, TIM2_OutputState_TypeDef TIM2_OutputState, uint16_t TIM2_Pulse, TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Initializes the TIM2 Channel1 according to the specified parameters.
void | TIM2_OC1PolarityConfig (TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Configures the TIM2 Channel 1 polarity.
void | TIM2_OC1PreloadConfig (FunctionalState NewState)
Enables or disables the TIM2 peripheral Preload Register on CCR1.
void | TIM2_OC2Init (TIM2_OCMode_TypeDef TIM2_OCMode, TIM2_OutputState_TypeDef TIM2_OutputState, uint16_t TIM2_Pulse, TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Initializes the TIM2 Channel2 according to the specified parameters.
void | TIM2_OC2PolarityConfig (TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Configures the TIM2 Channel 2 polarity.
void | TIM2_OC2PreloadConfig (FunctionalState NewState)
Enables or disables the TIM2 peripheral Preload Register on CCR2.
void | TIM2_OC3Init (TIM2_OCMode_TypeDef TIM2_OCMode, TIM2_OutputState_TypeDef TIM2_OutputState, uint16_t TIM2_Pulse, TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Initializes the TIM2 Channel3 according to the specified parameters.
void | TIM2_OC3PolarityConfig (TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Configures the TIM2 Channel 3 polarity.
void | TIM2_OC3PreloadConfig (FunctionalState NewState)
Enables or disables the TIM2 peripheral Preload Register on CCR3.
void | TIM2_PrescalerConfig (TIM2_Prescaler_TypeDef Prescaler, TIM2_PSCReloadMode_TypeDef TIM2_PSCReloadMode)
Configures the TIM2 Prescaler.
void | TIM2_PWMIConfig (TIM2_Channel_TypeDef TIM2_Channel, TIM2_ICPolarity_TypeDef TIM2_ICPolarity, TIM2_ICSelection_TypeDef TIM2_ICSelection, TIM2_ICPSC_TypeDef TIM2_ICPrescaler, uint8_t TIM2_ICFilter)
Configures the TIM2 peripheral in PWM Input Mode according to the specified parameters.
void | TIM2_SelectOCxM (TIM2_Channel_TypeDef TIM2_Channel, TIM2_OCMode_TypeDef TIM2_OCMode)
Selects the TIM2 Output Compare Mode.
void | TIM2_SelectOnePulseMode (TIM2_OPMode_TypeDef TIM2_OPMode)
Selects the TIM2’s One Pulse Mode.
void | TIM2_SetAutoreload (uint16_t Autoreload)
Sets the TIM2 Autoreload Register value.
void | TIM2_SetCompare1 (uint16_t Compare1)
Sets the TIM2 Capture Compare1 Register value.
void | TIM2_SetCompare2 (uint16_t Compare2)
Sets the TIM2 Capture Compare2 Register value.
void | TIM2_SetCompare3 (uint16_t Compare3)
Sets the TIM2 Capture Compare3 Register value.
void | TIM2_SetCounter (uint16_t Counter)
Sets the TIM2 Counter Register value.
void | TIM2_SetIC1Prescaler (TIM2_ICPSC_TypeDef TIM2_IC1Prescaler)
Sets the TIM2 Input Capture 1 Prescaler.
void | TIM2_SetIC2Prescaler (TIM2_ICPSC_TypeDef TIM2_IC2Prescaler)
Sets the TIM2 Input Capture 2 prescaler.
void | TIM2_SetIC3Prescaler (TIM2_ICPSC_TypeDef TIM2_IC3Prescaler)
Sets the TIM2 Input Capture 3 prescaler.
void | TIM2_TimeBaseInit (TIM2_Prescaler_TypeDef TIM2_Prescaler, uint16_t TIM2_Period)
Initializes the TIM2 Time Base Unit according to the specified parameters.
void | TIM2_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM2 Update event.
void | TIM2_UpdateRequestConfig (TIM2_UpdateSource_TypeDef TIM2_UpdateSource)
Selects the TIM2 Update Request Interrupt source.

Detailed Description

This file contains all functions prototype and macros for the TIM2 peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_tim2.h.


STM8S/A Standard Peripherals Drivers: stm8s_tim3.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions
stm8s_tim3.c File Reference

This file contains all the functions for the TIM3 peripheral. More...

#include "stm8s_tim3.h"

Go to the source code of this file.

Functions

static void | TI1_Config (uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
Configure the TI1 as Input.
static void | TI1_Config (uint8_t TIM3_ICPolarity, uint8_t TIM3_ICSelection, uint8_t TIM3_ICFilter)
Configure the TI1 as Input.
static void | TI2_Config (uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
Configure the TI2 as Input.
static void | TI2_Config (uint8_t TIM3_ICPolarity, uint8_t TIM3_ICSelection, uint8_t TIM3_ICFilter)
Configure the TI2 as Input.
void | TIM3_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM3 peripheral Preload register on ARR.
void | TIM3_CCxCmd (TIM3_Channel_TypeDef TIM3_Channel, FunctionalState NewState)
Enables or disables the TIM3 Capture Compare Channel x.
void | TIM3_ClearFlag (TIM3_FLAG_TypeDef TIM3_FLAG)
Clears the TIM3’s pending flags.
void | TIM3_ClearITPendingBit (TIM3_IT_TypeDef TIM3_IT)
Clears the TIM3's interrupt pending bits.
void | TIM3_Cmd (FunctionalState NewState)
Enables or disables the TIM3 peripheral.
void | TIM3_DeInit (void)
Deinitializes the TIM3 peripheral registers to their default reset values.
void | TIM3_ForcedOC1Config (TIM3_ForcedAction_TypeDef TIM3_ForcedAction)
Forces the TIM3 Channel1 output waveform to active or inactive level.
void | TIM3_ForcedOC2Config (TIM3_ForcedAction_TypeDef TIM3_ForcedAction)
Forces the TIM3 Channel2 output waveform to active or inactive level.
void | TIM3_GenerateEvent (TIM3_EventSource_TypeDef TIM3_EventSource)
Configures the TIM3 event to be generated by software.
uint16_t | TIM3_GetCapture1 (void)
Gets the TIM3 Input Capture 1 value.
uint16_t | TIM3_GetCapture2 (void)
Gets the TIM3 Input Capture 2 value.
uint16_t | TIM3_GetCounter (void)
Gets the TIM3 Counter value.
FlagStatus | TIM3_GetFlagStatus (TIM3_FLAG_TypeDef TIM3_FLAG)
Checks whether the specified TIM3 flag is set or not.
ITStatus | TIM3_GetITStatus (TIM3_IT_TypeDef TIM3_IT)
Checks whether the TIM3 interrupt has occurred or not.
TIM3_Prescaler_TypeDef | TIM3_GetPrescaler (void)
Gets the TIM3 Prescaler value.
void | TIM3_ICInit (TIM3_Channel_TypeDef TIM3_Channel, TIM3_ICPolarity_TypeDef TIM3_ICPolarity, TIM3_ICSelection_TypeDef TIM3_ICSelection, TIM3_ICPSC_TypeDef TIM3_ICPrescaler, uint8_t TIM3_ICFilter)
Initializes the TIM3 peripheral according to the specified parameters.
void | TIM3_ITConfig (TIM3_IT_TypeDef TIM3_IT, FunctionalState NewState)
Enables or disables the specified TIM3 interrupts.
void | TIM3_OC1Init (TIM3_OCMode_TypeDef TIM3_OCMode, TIM3_OutputState_TypeDef TIM3_OutputState, uint16_t TIM3_Pulse, TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
Initializes the TIM3 Channel1 according to the specified parameters.
void | TIM3_OC1PolarityConfig (TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
Configures the TIM3 Channel 1 polarity.
void | TIM3_OC1PreloadConfig (FunctionalState NewState)
Enables or disables the TIM3 peripheral Preload Register on CCR1.
void | TIM3_OC2Init (TIM3_OCMode_TypeDef TIM3_OCMode, TIM3_OutputState_TypeDef TIM3_OutputState, uint16_t TIM3_Pulse, TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
Initializes the TIM3 Channel2 according to the specified parameters.
void | TIM3_OC2PolarityConfig (TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
Configures the TIM3 Channel 2 polarity.
void | TIM3_OC2PreloadConfig (FunctionalState NewState)
Enables or disables the TIM3 peripheral Preload Register on CCR2.
void | TIM3_PrescalerConfig (TIM3_Prescaler_TypeDef Prescaler, TIM3_PSCReloadMode_TypeDef TIM3_PSCReloadMode)
Configures the TIM3 Prescaler.
void | TIM3_PWMIConfig (TIM3_Channel_TypeDef TIM3_Channel, TIM3_ICPolarity_TypeDef TIM3_ICPolarity, TIM3_ICSelection_TypeDef TIM3_ICSelection, TIM3_ICPSC_TypeDef TIM3_ICPrescaler, uint8_t TIM3_ICFilter)
Configures the TIM3 peripheral in PWM Input Mode according to the specified parameters.
void | TIM3_SelectOCxM (TIM3_Channel_TypeDef TIM3_Channel, TIM3_OCMode_TypeDef TIM3_OCMode)
Selects the TIM3 Output Compare Mode.
void | TIM3_SelectOnePulseMode (TIM3_OPMode_TypeDef TIM3_OPMode)
Selects the TIM3’s One Pulse Mode.
void | TIM3_SetAutoreload (uint16_t Autoreload)
Sets the TIM3 Autoreload Register value.
void | TIM3_SetCompare1 (uint16_t Compare1)
Sets the TIM3 Capture Compare1 Register value.
void | TIM3_SetCompare2 (uint16_t Compare2)
Sets the TIM3 Capture Compare2 Register value.
void | TIM3_SetCounter (uint16_t Counter)
Sets the TIM3 Counter Register value.
void | TIM3_SetIC1Prescaler (TIM3_ICPSC_TypeDef TIM3_IC1Prescaler)
Sets the TIM3 Input Capture 1 prescaler.
void | TIM3_SetIC2Prescaler (TIM3_ICPSC_TypeDef TIM3_IC2Prescaler)
Sets the TIM3 Input Capture 2 prescaler.
void | TIM3_TimeBaseInit (TIM3_Prescaler_TypeDef TIM3_Prescaler, uint16_t TIM3_Period)
Initializes the TIM3 Time Base Unit according to the specified parameters.
void | TIM3_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM3 Update event.
void | TIM3_UpdateRequestConfig (TIM3_UpdateSource_TypeDef TIM3_UpdateSource)
Selects the TIM3 Update Request Interrupt source.

Detailed Description

This file contains all the functions for the TIM3 peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_tim3.c.


STM8S/A Standard Peripherals Drivers: stm8s_tim3.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions
stm8s_tim3.h File Reference

This file contains all functions prototype and macros for the TIM3 peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_TIM3_CHANNEL_OK(CHANNEL)
#define | IS_TIM3_CLEAR_FLAG_OK(FLAG) ((((uint16_t)(FLAG) & 0xF9F8) == 0x0000) && ((uint16_t)(FLAG)!= 0x0000))
#define | IS_TIM3_EVENT_SOURCE_OK(SOURCE) (((SOURCE) != 0x00))
#define | IS_TIM3_FORCED_ACTION_OK(ACTION)
#define | IS_TIM3_GET_FLAG_OK(FLAG)
#define | IS_TIM3_GET_IT_OK(IT)
#define | IS_TIM3_IC_FILTER_OK(ICFILTER) ((ICFILTER) <= 0x0F)
TIM3 Input Capture Filer Value.
#define | IS_TIM3_IC_POLARITY_OK(POLARITY)
#define | IS_TIM3_IC_PRESCALER_OK(PRESCALER)
#define | IS_TIM3_IC_SELECTION_OK(SELECTION)
#define | IS_TIM3_IT_OK(IT) (((IT) != 0x00) && ((IT) <= 0x07))
#define | IS_TIM3_OC_MODE_OK(MODE)
#define | IS_TIM3_OC_POLARITY_OK(POLARITY)
#define | IS_TIM3_OCM_OK(MODE)
#define | IS_TIM3_OPM_MODE_OK(MODE)
#define | IS_TIM3_OUTPUT_STATE_OK(STATE)
#define | IS_TIM3_PRESCALER_OK(PRESCALER)
#define | IS_TIM3_PRESCALER_RELOAD_OK(RELOAD)
#define | IS_TIM3_PWMI_CHANNEL_OK(CHANNEL)
#define | IS_TIM3_UPDATE_SOURCE_OK(SOURCE)

Enumerations

enum | TIM3_Channel_TypeDef { TIM3_CHANNEL_1 = ((uint8_t)0x00), TIM3_CHANNEL_2 = ((uint8_t)0x01) }
TIM3 Channel. More...
enum | TIM3_EventSource_TypeDef { TIM3_EVENTSOURCE_UPDATE = ((uint8_t)0x01), TIM3_EVENTSOURCE_CC1 = ((uint8_t)0x02), TIM3_EVENTSOURCE_CC2 = ((uint8_t)0x04) }
TIM3 Event Source. More...
enum TIM3_FLAG_TypeDef {
TIM3_FLAG_UPDATE = ((uint16_t)0x0001), TIM3_FLAG_CC1 = ((uint16_t)0x0002), TIM3_FLAG_CC2 = ((uint16_t)0x0004), TIM3_FLAG_CC1OF = ((uint16_t)0x0200),
TIM3_FLAG_CC2OF = ((uint16_t)0x0400)
}
TIM3 Flags. More...
enum | TIM3_ForcedAction_TypeDef { TIM3_FORCEDACTION_ACTIVE = ((uint8_t)0x50), TIM3_FORCEDACTION_INACTIVE = ((uint8_t)0x40) }
TIM3 Forced Action. More...
enum | TIM3_ICPolarity_TypeDef { TIM3_ICPOLARITY_RISING = ((uint8_t)0x00), TIM3_ICPOLARITY_FALLING = ((uint8_t)0x44) }
TIM3 Input Capture Polarity. More...
enum | TIM3_ICPSC_TypeDef { TIM3_ICPSC_DIV1 = ((uint8_t)0x00), TIM3_ICPSC_DIV2 = ((uint8_t)0x04), TIM3_ICPSC_DIV4 = ((uint8_t)0x08), TIM3_ICPSC_DIV8 = ((uint8_t)0x0C) }
TIM3 Input Capture Prescaler. More...
enum | TIM3_ICSelection_TypeDef { TIM3_ICSELECTION_DIRECTTI = ((uint8_t)0x01), TIM3_ICSELECTION_INDIRECTTI = ((uint8_t)0x02), TIM3_ICSELECTION_TRGI = ((uint8_t)0x03) }
TIM3 Input Capture Selection. More...
enum | TIM3_IT_TypeDef { TIM3_IT_UPDATE = ((uint8_t)0x01), TIM3_IT_CC1 = ((uint8_t)0x02), TIM3_IT_CC2 = ((uint8_t)0x04) }
TIM3 interrupt sources. More...
enum TIM3_OCMode_TypeDef {
TIM3_OCMODE_TIMING = ((uint8_t)0x00), TIM3_OCMODE_ACTIVE = ((uint8_t)0x10), TIM3_OCMODE_INACTIVE = ((uint8_t)0x20), TIM3_OCMODE_TOGGLE = ((uint8_t)0x30),
TIM3_OCMODE_PWM1 = ((uint8_t)0x60), TIM3_OCMODE_PWM2 = ((uint8_t)0x70)
}
TIM3 Output Compare and PWM modes. More...
enum | TIM3_OCPolarity_TypeDef { TIM3_OCPOLARITY_HIGH = ((uint8_t)0x00), TIM3_OCPOLARITY_LOW = ((uint8_t)0x22) }
TIM3 Output Compare Polarity. More...
enum | TIM3_OPMode_TypeDef { TIM3_OPMODE_SINGLE = ((uint8_t)0x01), TIM3_OPMODE_REPETITIVE = ((uint8_t)0x00) }
TIM3 One Pulse Mode. More...
enum | TIM3_OutputState_TypeDef { TIM3_OUTPUTSTATE_DISABLE = ((uint8_t)0x00), TIM3_OUTPUTSTATE_ENABLE = ((uint8_t)0x11) }
TIM3 Output Compare states. More...
enum TIM3_Prescaler_TypeDef {
TIM3_PRESCALER_1 = ((uint8_t)0x00), TIM3_PRESCALER_2 = ((uint8_t)0x01), TIM3_PRESCALER_4 = ((uint8_t)0x02), TIM3_PRESCALER_8 = ((uint8_t)0x03),
TIM3_PRESCALER_16 = ((uint8_t)0x04), TIM3_PRESCALER_32 = ((uint8_t)0x05), TIM3_PRESCALER_64 = ((uint8_t)0x06), TIM3_PRESCALER_128 = ((uint8_t)0x07),
TIM3_PRESCALER_256 = ((uint8_t)0x08), TIM3_PRESCALER_512 = ((uint8_t)0x09), TIM3_PRESCALER_1024 = ((uint8_t)0x0A), TIM3_PRESCALER_2048 = ((uint8_t)0x0B),
TIM3_PRESCALER_4096 = ((uint8_t)0x0C), TIM3_PRESCALER_8192 = ((uint8_t)0x0D), TIM3_PRESCALER_16384 = ((uint8_t)0x0E), TIM3_PRESCALER_32768 = ((uint8_t)0x0F)
}
TIM3 Prescaler. More...
enum | TIM3_PSCReloadMode_TypeDef { TIM3_PSCRELOADMODE_UPDATE = ((uint8_t)0x00), TIM3_PSCRELOADMODE_IMMEDIATE = ((uint8_t)0x01) }
TIM3 Prescaler Reload Mode. More...
enum | TIM3_UpdateSource_TypeDef { TIM3_UPDATESOURCE_GLOBAL = ((uint8_t)0x00), TIM3_UPDATESOURCE_REGULAR = ((uint8_t)0x01) }
TIM3 Update Source. More...

Functions

void | TIM3_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM3 peripheral Preload register on ARR.
void | TIM3_CCPreloadControl (FunctionalState NewState)
void | TIM3_CCxCmd (TIM3_Channel_TypeDef TIM3_Channel, FunctionalState NewState)
Enables or disables the TIM3 Capture Compare Channel x.
void | TIM3_ClearFlag (TIM3_FLAG_TypeDef TIM3_FLAG)
Clears the TIM3’s pending flags.
void | TIM3_ClearITPendingBit (TIM3_IT_TypeDef TIM3_IT)
Clears the TIM3's interrupt pending bits.
void | TIM3_Cmd (FunctionalState NewState)
Enables or disables the TIM3 peripheral.
void | TIM3_DeInit (void)
Deinitializes the TIM3 peripheral registers to their default reset values.
void | TIM3_ForcedOC1Config (TIM3_ForcedAction_TypeDef TIM3_ForcedAction)
Forces the TIM3 Channel1 output waveform to active or inactive level.
void | TIM3_ForcedOC2Config (TIM3_ForcedAction_TypeDef TIM3_ForcedAction)
Forces the TIM3 Channel2 output waveform to active or inactive level.
void | TIM3_GenerateEvent (TIM3_EventSource_TypeDef TIM3_EventSource)
Configures the TIM3 event to be generated by software.
uint16_t | TIM3_GetCapture1 (void)
Gets the TIM3 Input Capture 1 value.
uint16_t | TIM3_GetCapture2 (void)
Gets the TIM3 Input Capture 2 value.
uint16_t | TIM3_GetCounter (void)
Gets the TIM3 Counter value.
FlagStatus | TIM3_GetFlagStatus (TIM3_FLAG_TypeDef TIM3_FLAG)
Checks whether the specified TIM3 flag is set or not.
ITStatus | TIM3_GetITStatus (TIM3_IT_TypeDef TIM3_IT)
Checks whether the TIM3 interrupt has occurred or not.
TIM3_Prescaler_TypeDef | TIM3_GetPrescaler (void)
Gets the TIM3 Prescaler value.
void | TIM3_ICInit (TIM3_Channel_TypeDef TIM3_Channel, TIM3_ICPolarity_TypeDef TIM3_ICPolarity, TIM3_ICSelection_TypeDef TIM3_ICSelection, TIM3_ICPSC_TypeDef TIM3_ICPrescaler, uint8_t TIM3_ICFilter)
Initializes the TIM3 peripheral according to the specified parameters.
void | TIM3_InternalClockConfig (void)
void | TIM3_ITConfig (TIM3_IT_TypeDef TIM3_IT, FunctionalState NewState)
Enables or disables the specified TIM3 interrupts.
void | TIM3_OC1Init (TIM3_OCMode_TypeDef TIM3_OCMode, TIM3_OutputState_TypeDef TIM3_OutputState, uint16_t TIM3_Pulse, TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
Initializes the TIM3 Channel1 according to the specified parameters.
void | TIM3_OC1PolarityConfig (TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
Configures the TIM3 Channel 1 polarity.
void | TIM3_OC1PreloadConfig (FunctionalState NewState)
Enables or disables the TIM3 peripheral Preload Register on CCR1.
void | TIM3_OC2Init (TIM3_OCMode_TypeDef TIM3_OCMode, TIM3_OutputState_TypeDef TIM3_OutputState, uint16_t TIM3_Pulse, TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
Initializes the TIM3 Channel2 according to the specified parameters.
void | TIM3_OC2PolarityConfig (TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
Configures the TIM3 Channel 2 polarity.
void | TIM3_OC2PreloadConfig (FunctionalState NewState)
Enables or disables the TIM3 peripheral Preload Register on CCR2.
void | TIM3_PrescalerConfig (TIM3_Prescaler_TypeDef Prescaler, TIM3_PSCReloadMode_TypeDef TIM3_PSCReloadMode)
Configures the TIM3 Prescaler.
void | TIM3_PWMIConfig (TIM3_Channel_TypeDef TIM3_Channel, TIM3_ICPolarity_TypeDef TIM3_ICPolarity, TIM3_ICSelection_TypeDef TIM3_ICSelection, TIM3_ICPSC_TypeDef TIM3_ICPrescaler, uint8_t TIM3_ICFilter)
Configures the TIM3 peripheral in PWM Input Mode according to the specified parameters.
void | TIM3_SelectOCxM (TIM3_Channel_TypeDef TIM3_Channel, TIM3_OCMode_TypeDef TIM3_OCMode)
Selects the TIM3 Output Compare Mode.
void | TIM3_SelectOnePulseMode (TIM3_OPMode_TypeDef TIM3_OPMode)
Selects the TIM3’s One Pulse Mode.
void | TIM3_SetAutoreload (uint16_t Autoreload)
Sets the TIM3 Autoreload Register value.
void | TIM3_SetCompare1 (uint16_t Compare1)
Sets the TIM3 Capture Compare1 Register value.
void | TIM3_SetCompare2 (uint16_t Compare2)
Sets the TIM3 Capture Compare2 Register value.
void | TIM3_SetCounter (uint16_t Counter)
Sets the TIM3 Counter Register value.
void | TIM3_SetIC1Prescaler (TIM3_ICPSC_TypeDef TIM3_IC1Prescaler)
Sets the TIM3 Input Capture 1 prescaler.
void | TIM3_SetIC2Prescaler (TIM3_ICPSC_TypeDef TIM3_IC2Prescaler)
Sets the TIM3 Input Capture 2 prescaler.
void | TIM3_TimeBaseInit (TIM3_Prescaler_TypeDef TIM3_Prescaler, uint16_t TIM3_Period)
Initializes the TIM3 Time Base Unit according to the specified parameters.
void | TIM3_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM3 Update event.
void | TIM3_UpdateRequestConfig (TIM3_UpdateSource_TypeDef TIM3_UpdateSource)
Selects the TIM3 Update Request Interrupt source.

Detailed Description

This file contains all functions prototype and macros for the TIM3 peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_tim3.h.


STM8S/A Standard Peripherals Drivers: stm8s_tim4.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions
stm8s_tim4.c File Reference

This file contains all the functions for the TIM4 peripheral. More...

#include "stm8s_tim4.h"

Go to the source code of this file.

Functions

void | TIM4_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM4 peripheral Preload register on ARR.
void | TIM4_ClearFlag (TIM4_FLAG_TypeDef TIM4_FLAG)
Clears the TIM4’s pending flags.
void | TIM4_ClearITPendingBit (TIM4_IT_TypeDef TIM4_IT)
Clears the TIM4's interrupt pending bits.
void | TIM4_Cmd (FunctionalState NewState)
Enables or disables the TIM4 peripheral.
void | TIM4_DeInit (void)
Deinitializes the TIM4 peripheral registers to their default reset values.
void | TIM4_GenerateEvent (TIM4_EventSource_TypeDef TIM4_EventSource)
Configures the TIM4 event to be generated by software.
uint8_t | TIM4_GetCounter (void)
Gets the TIM4 Counter value.
FlagStatus | TIM4_GetFlagStatus (TIM4_FLAG_TypeDef TIM4_FLAG)
Checks whether the specified TIM4 flag is set or not.
ITStatus | TIM4_GetITStatus (TIM4_IT_TypeDef TIM4_IT)
Checks whether the TIM4 interrupt has occurred or not.
TIM4_Prescaler_TypeDef | TIM4_GetPrescaler (void)
Gets the TIM4 Prescaler value.
void | TIM4_ITConfig (TIM4_IT_TypeDef TIM4_IT, FunctionalState NewState)
Enables or disables the specified TIM4 interrupts.
void | TIM4_PrescalerConfig (TIM4_Prescaler_TypeDef Prescaler, TIM4_PSCReloadMode_TypeDef TIM4_PSCReloadMode)
Configures the TIM4 Prescaler.
void | TIM4_SelectOnePulseMode (TIM4_OPMode_TypeDef TIM4_OPMode)
Selects the TIM4’s One Pulse Mode.
void | TIM4_SetAutoreload (uint8_t Autoreload)
Sets the TIM4 Autoreload Register value.
void | TIM4_SetCounter (uint8_t Counter)
Sets the TIM4 Counter Register value.
void | TIM4_TimeBaseInit (TIM4_Prescaler_TypeDef TIM4_Prescaler, uint8_t TIM4_Period)
Initializes the TIM4 Time Base Unit according to the specified parameters.
void | TIM4_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM4 Update event.
void | TIM4_UpdateRequestConfig (TIM4_UpdateSource_TypeDef TIM4_UpdateSource)
Selects the TIM4 Update Request Interrupt source.

Detailed Description

This file contains all the functions for the TIM4 peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_tim4.c.


STM8S/A Standard Peripherals Drivers: stm8s_tim4.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions
stm8s_tim4.h File Reference

This file contains all functions prototype and macros for the TIM4 peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_TIM4_EVENT_SOURCE_OK(SOURCE) (((SOURCE) == 0x01))
#define | IS_TIM4_GET_FLAG_OK(FLAG) ((FLAG) == TIM4_FLAG_UPDATE)
#define | IS_TIM4_IT_OK(IT) ((IT) == TIM4_IT_UPDATE)
#define | IS_TIM4_OPM_MODE_OK(MODE)
#define | IS_TIM4_PRESCALER_OK(PRESCALER)
#define | IS_TIM4_PRESCALER_RELOAD_OK(RELOAD)
#define | IS_TIM4_UPDATE_SOURCE_OK(SOURCE)

Enumerations

enum | TIM4_EventSource_TypeDef { TIM4_EVENTSOURCE_UPDATE = ((uint8_t)0x01) }
TIM4 Event Source. More...
enum | TIM4_FLAG_TypeDef { TIM4_FLAG_UPDATE = ((uint8_t)0x01) }
TIM4 Flags. More...
enum | TIM4_IT_TypeDef { TIM4_IT_UPDATE = ((uint8_t)0x01) }
TIM4 interrupt sources. More...
enum | TIM4_OPMode_TypeDef { TIM4_OPMODE_SINGLE = ((uint8_t)0x01), TIM4_OPMODE_REPETITIVE = ((uint8_t)0x00) }
TIM4 One Pulse Mode. More...
enum TIM4_Prescaler_TypeDef {
TIM4_PRESCALER_1 = ((uint8_t)0x00), TIM4_PRESCALER_2 = ((uint8_t)0x01), TIM4_PRESCALER_4 = ((uint8_t)0x02), TIM4_PRESCALER_8 = ((uint8_t)0x03),
TIM4_PRESCALER_16 = ((uint8_t)0x04), TIM4_PRESCALER_32 = ((uint8_t)0x05), TIM4_PRESCALER_64 = ((uint8_t)0x06), TIM4_PRESCALER_128 = ((uint8_t)0x07)
}
TIM4 Prescaler. More...
enum | TIM4_PSCReloadMode_TypeDef { TIM4_PSCRELOADMODE_UPDATE = ((uint8_t)0x00), TIM4_PSCRELOADMODE_IMMEDIATE = ((uint8_t)0x01) }
TIM4 Prescaler Reload Mode. More...
enum | TIM4_UpdateSource_TypeDef { TIM4_UPDATESOURCE_GLOBAL = ((uint8_t)0x00), TIM4_UPDATESOURCE_REGULAR = ((uint8_t)0x01) }
TIM4 Update Source. More...

Functions

void | TIM4_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM4 peripheral Preload register on ARR.
void | TIM4_ClearFlag (TIM4_FLAG_TypeDef TIM4_FLAG)
Clears the TIM4’s pending flags.
void | TIM4_ClearITPendingBit (TIM4_IT_TypeDef TIM4_IT)
Clears the TIM4's interrupt pending bits.
void | TIM4_Cmd (FunctionalState NewState)
Enables or disables the TIM4 peripheral.
void | TIM4_DeInit (void)
Deinitializes the TIM4 peripheral registers to their default reset values.
void | TIM4_GenerateEvent (TIM4_EventSource_TypeDef TIM4_EventSource)
Configures the TIM4 event to be generated by software.
uint8_t | TIM4_GetCounter (void)
Gets the TIM4 Counter value.
FlagStatus | TIM4_GetFlagStatus (TIM4_FLAG_TypeDef TIM4_FLAG)
Checks whether the specified TIM4 flag is set or not.
ITStatus | TIM4_GetITStatus (TIM4_IT_TypeDef TIM4_IT)
Checks whether the TIM4 interrupt has occurred or not.
TIM4_Prescaler_TypeDef | TIM4_GetPrescaler (void)
Gets the TIM4 Prescaler value.
void | TIM4_ITConfig (TIM4_IT_TypeDef TIM4_IT, FunctionalState NewState)
Enables or disables the specified TIM4 interrupts.
void | TIM4_PrescalerConfig (TIM4_Prescaler_TypeDef Prescaler, TIM4_PSCReloadMode_TypeDef TIM4_PSCReloadMode)
Configures the TIM4 Prescaler.
void | TIM4_SelectOnePulseMode (TIM4_OPMode_TypeDef TIM4_OPMode)
Selects the TIM4’s One Pulse Mode.
void | TIM4_SetAutoreload (uint8_t Autoreload)
Sets the TIM4 Autoreload Register value.
void | TIM4_SetCounter (uint8_t Counter)
Sets the TIM4 Counter Register value.
void | TIM4_TimeBaseInit (TIM4_Prescaler_TypeDef TIM4_Prescaler, uint8_t TIM4_Period)
Initializes the TIM4 Time Base Unit according to the specified parameters.
void | TIM4_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM4 Update event.
void | TIM4_UpdateRequestConfig (TIM4_UpdateSource_TypeDef TIM4_UpdateSource)
Selects the TIM4 Update Request Interrupt source.

Detailed Description

This file contains all functions prototype and macros for the TIM4 peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_tim4.h.


STM8S/A Standard Peripherals Drivers: stm8s_tim5.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions
stm8s_tim5.c File Reference

This file contains all the functions for the TIM5 peripheral. More...

#include "stm8s_tim5.h"

Go to the source code of this file.

Functions

static void | TI1_Config (uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
Configure the TI1 as Input.
static void | TI1_Config (uint8_t TIM5_ICPolarity, uint8_t TIM5_ICSelection, uint8_t TIM5_ICFilter)
Configure the TI1 as Input.
static void | TI2_Config (uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
Configure the TI2 as Input.
static void | TI2_Config (uint8_t TIM5_ICPolarity, uint8_t TIM5_ICSelection, uint8_t TIM5_ICFilter)
Configure the TI2 as Input.
static void | TI3_Config (uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
Configure the TI3 as Input.
static void | TI3_Config (uint8_t TIM5_ICPolarity, uint8_t TIM5_ICSelection, uint8_t TIM5_ICFilter)
Configure the TI3 as Input.
void | TIM5_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM5 peripheral Preload register on ARR.
void | TIM5_CCxCmd (TIM5_Channel_TypeDef TIM5_Channel, FunctionalState NewState)
Enables or disables the TIM5 Capture Compare Channel x.
void | TIM5_ClearFlag (TIM5_FLAG_TypeDef TIM5_FLAG)
Clears the TIM5’s pending flags.
void | TIM5_ClearITPendingBit (TIM5_IT_TypeDef TIM5_IT)
Clears the TIM5's interrupt pending bits.
void | TIM5_Cmd (FunctionalState NewState)
Enables or disables the TIM5 peripheral.
void | TIM5_DeInit (void)
Deinitializes the TIM5 peripheral registers to their default reset values.
void | TIM5_EncoderInterfaceConfig (TIM5_EncoderMode_TypeDef TIM5_EncoderMode, TIM5_ICPolarity_TypeDef TIM5_IC1Polarity, TIM5_ICPolarity_TypeDef TIM5_IC2Polarity)
Configures the TIM5 Encoder Interface.
void | TIM5_ForcedOC1Config (TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
Forces the TIM5 Channel1 output waveform to active or inactive level.
void | TIM5_ForcedOC2Config (TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
Forces the TIM5 Channel2 output waveform to active or inactive level.
void | TIM5_ForcedOC3Config (TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
Forces the TIM5 Channel3 output waveform to active or inactive level.
void | TIM5_GenerateEvent (TIM5_EventSource_TypeDef TIM5_EventSource)
Configures the TIM5 event to be generated by software.
uint16_t | TIM5_GetCapture1 (void)
Gets the TIM5 Input Capture 1 value.
uint16_t | TIM5_GetCapture2 (void)
Gets the TIM5 Input Capture 2 value.
uint16_t | TIM5_GetCapture3 (void)
Gets the TIM5 Input Capture 3 value.
uint16_t | TIM5_GetCounter (void)
Gets the TIM5 Counter value.
FlagStatus | TIM5_GetFlagStatus (TIM5_FLAG_TypeDef TIM5_FLAG)
Checks whether the specified TIM5 flag is set or not.
ITStatus | TIM5_GetITStatus (TIM5_IT_TypeDef TIM5_IT)
Checks whether the TIM5 interrupt has occurred or not.
TIM5_Prescaler_TypeDef | TIM5_GetPrescaler (void)
Gets the TIM5 Prescaler value.
void | TIM5_ICInit (TIM5_Channel_TypeDef TIM5_Channel, TIM5_ICPolarity_TypeDef TIM5_ICPolarity, TIM5_ICSelection_TypeDef TIM5_ICSelection, TIM5_ICPSC_TypeDef TIM5_ICPrescaler, uint8_t TIM5_ICFilter)
Initializes the TIM5 peripheral according to the specified parameters.
void | TIM5_InternalClockConfig (void)
Enables the TIM5 internal Clock.
void | TIM5_ITConfig (TIM5_IT_TypeDef TIM5_IT, FunctionalState NewState)
Enables or disables the specified TIM5 interrupts.
void | TIM5_OC1Init (TIM5_OCMode_TypeDef TIM5_OCMode, TIM5_OutputState_TypeDef TIM5_OutputState, uint16_t TIM5_Pulse, TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Initializes the TIM5 Channel1 according to the specified parameters.
void | TIM5_OC1PolarityConfig (TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Configures the TIM5 Channel 1 polarity.
void | TIM5_OC1PreloadConfig (FunctionalState NewState)
Enables or disables the TIM5 peripheral Preload Register on CCR1.
void | TIM5_OC2Init (TIM5_OCMode_TypeDef TIM5_OCMode, TIM5_OutputState_TypeDef TIM5_OutputState, uint16_t TIM5_Pulse, TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Initializes the TIM5 Channel2 according to the specified parameters.
void | TIM5_OC2PolarityConfig (TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Configures the TIM5 Channel 2 polarity.
void | TIM5_OC2PreloadConfig (FunctionalState NewState)
Enables or disables the TIM5 peripheral Preload Register on CCR2.
void | TIM5_OC3Init (TIM5_OCMode_TypeDef TIM5_OCMode, TIM5_OutputState_TypeDef TIM5_OutputState, uint16_t TIM5_Pulse, TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Initializes the TIM5 Channel3 according to the specified parameters.
void | TIM5_OC3PolarityConfig (TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Configures the TIM5 Channel 3 polarity.
void | TIM5_OC3PreloadConfig (FunctionalState NewState)
Enables or disables the TIM5 peripheral Preload Register on CCR3.
void | TIM5_PrescalerConfig (TIM5_Prescaler_TypeDef Prescaler, TIM5_PSCReloadMode_TypeDef TIM5_PSCReloadMode)
Configures the TIM5 Prescaler.
void | TIM5_PWMIConfig (TIM5_Channel_TypeDef TIM5_Channel, TIM5_ICPolarity_TypeDef TIM5_ICPolarity, TIM5_ICSelection_TypeDef TIM5_ICSelection, TIM5_ICPSC_TypeDef TIM5_ICPrescaler, uint8_t TIM5_ICFilter)
Configures the TIM5 peripheral in PWM Input Mode according to the specified parameters.
void | TIM5_SelectInputTrigger (TIM5_TS_TypeDef TIM5_InputTriggerSource)
Selects the TIM5 Input Trigger source.
void | TIM5_SelectOCxM (TIM5_Channel_TypeDef TIM5_Channel, TIM5_OCMode_TypeDef TIM5_OCMode)
Selects the TIM5 Output Compare Mode.
void | TIM5_SelectOnePulseMode (TIM5_OPMode_TypeDef TIM5_OPMode)
Selects the TIM5’s One Pulse Mode.
void | TIM5_SelectOutputTrigger (TIM5_TRGOSource_TypeDef TIM5_TRGOSource)
Selects the TIM5 Trigger Output Mode.
void | TIM5_SelectSlaveMode (TIM5_SlaveMode_TypeDef TIM5_SlaveMode)
Selects the TIM5 Slave Mode.
void | TIM5_SetAutoreload (uint16_t Autoreload)
Sets the TIM5 Autoreload Register value.
void | TIM5_SetCompare1 (uint16_t Compare1)
Sets the TIM5 Capture Compare1 Register value.
void | TIM5_SetCompare2 (uint16_t Compare2)
Sets the TIM5 Capture Compare2 Register value.
void | TIM5_SetCompare3 (uint16_t Compare3)
Sets the TIM5 Capture Compare3 Register value.
void | TIM5_SetCounter (uint16_t Counter)
Sets the TIM5 Counter Register value.
void | TIM5_SetIC1Prescaler (TIM5_ICPSC_TypeDef TIM5_IC1Prescaler)
Sets the TIM5 Input Capture 1 prescaler.
void | TIM5_SetIC2Prescaler (TIM5_ICPSC_TypeDef TIM5_IC2Prescaler)
Sets the TIM5 Input Capture 2 prescaler.
void | TIM5_SetIC3Prescaler (TIM5_ICPSC_TypeDef TIM5_IC3Prescaler)
Sets the TIM5 Input Capture 3 prescaler.
void | TIM5_TimeBaseInit (TIM5_Prescaler_TypeDef TIM5_Prescaler, uint16_t TIM5_Period)
Initializes the TIM5 Time Base Unit according to the specified parameters.
void | TIM5_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM5 Update event.
void | TIM5_UpdateRequestConfig (TIM5_UpdateSource_TypeDef TIM5_UpdateSource)
Selects the TIM5 Update Request Interrupt source.

Detailed Description

This file contains all the functions for the TIM5 peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_tim5.c.


STM8S/A Standard Peripherals Drivers: stm8s_tim5.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions
stm8s_tim5.h File Reference

This file contains all functions prototype and macros for the TIM5 peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_TIM5_CHANNEL_OK(CHANNEL)
#define | IS_TIM5_CLEAR_FLAG_OK(FLAG) ((((uint16_t)(FLAG) & 0xF1F0) == 0x0000) && ((uint16_t)(FLAG) != 0x0000))
#define | IS_TIM5_ENCODER_MODE_OK(MODE)
Macro TIM5 encoder mode.
#define | IS_TIM5_EVENT_SOURCE_OK(SOURCE) (((SOURCE) != 0x00))
#define | IS_TIM5_EXT_FILTER_OK(EXTFILTER) ((EXTFILTER) <= 0x0F)
Macro TIM5 External Trigger Filter.
#define | IS_TIM5_EXT_POLARITY_OK(POLARITY)
Macro TIM5 Trigger Polarity.
#define | IS_TIM5_EXT_PRESCALER_OK(PRESCALER)
Macro TIM5 external trigger prescaler.
#define | IS_TIM5_FORCED_ACTION_OK(ACTION)
#define | IS_TIM5_GET_FLAG_OK(FLAG)
#define | IS_TIM5_GET_IT_OK(IT)
#define | IS_TIM5_IC_FILTER_OK(ICFILTER) ((ICFILTER) <= 0x0F)
TIM5 Input Capture Filer Value.
#define | IS_TIM5_IC_POLARITY_OK(POLARITY)
#define | IS_TIM5_IC_PRESCALER_OK(PRESCALER)
#define | IS_TIM5_IC_SELECTION1_OK(SELECTION)
#define | IS_TIM5_IC_SELECTION_OK(SELECTION)
#define | IS_TIM5_IT_OK(IT) (((IT) != 0x00) && ((IT) <= 0x4F))
#define | IS_TIM5_OC_MODE_OK(MODE)
#define | IS_TIM5_OC_POLARITY_OK(POLARITY)
#define | IS_TIM5_OCM_OK(MODE)
#define | IS_TIM5_OPM_MODE_OK(MODE)
#define | IS_TIM5_OUTPUT_STATE_OK(STATE)
#define | IS_TIM5_PRESCALER_OK(PRESCALER)
#define | IS_TIM5_PRESCALER_RELOAD_OK(RELOAD)
#define | IS_TIM5_PWMI_CHANNEL_OK(CHANNEL)
#define | IS_TIM5_SLAVE_MODE_OK(MODE)
Macro TIM5 Slave mode.
#define | IS_TIM5_TIX_TRIGGER_SELECTION_OK(SELECTION)
#define | IS_TIM5_TRGO_SOURCE_OK(SOURCE)
Macro TIM5 TRGO source.
#define | IS_TIM5_TRIGGER_SELECTION_OK(SELECTION)
Macro TIM5 Trigger Selection.
#define | IS_TIM5_UPDATE_SOURCE_OK(SOURCE)

Enumerations

enum | TIM5_Channel_TypeDef { TIM5_CHANNEL_1 = ((uint8_t)0x00), TIM5_CHANNEL_2 = ((uint8_t)0x01), TIM5_CHANNEL_3 = ((uint8_t)0x02) }
TIM5 Channel. More...
enum | TIM5_EncoderMode_TypeDef { TIM5_ENCODERMODE_TI1 = ((uint8_t)0x01), TIM5_ENCODERMODE_TI2 = ((uint8_t)0x02), TIM5_ENCODERMODE_TI12 = ((uint8_t)0x03) }
TIM5 Encoder Mode. More...
enum TIM5_EventSource_TypeDef {
TIM5_EVENTSOURCE_UPDATE = ((uint8_t)0x01), TIM5_EVENTSOURCE_CC1 = ((uint8_t)0x02), TIM5_EVENTSOURCE_CC2 = ((uint8_t)0x04), TIM5_EVENTSOURCE_CC3 = ((uint8_t)0x08),
TIM5_EVENTSOURCE_TRIGGER = ((uint8_t)0x40)
}
TIM5 Event Source. More...
enum | TIM5_ExtTRGPolarity_TypeDef { TIM5_EXTTRGPOLARITY_INVERTED = ((uint8_t)0x80), TIM5_EXTTRGPOLARITY_NONINVERTED = ((uint8_t)0x00) }
TIM5 External Trigger Polarity. More...
enum | TIM5_ExtTRGPSC_TypeDef { TIM5_EXTTRGPSC_OFF = ((uint8_t)0x00), TIM5_EXTTRGPSC_DIV2 = ((uint8_t)0x10), TIM5_EXTTRGPSC_DIV4 = ((uint8_t)0x20), TIM5_EXTTRGPSC_DIV8 = ((uint8_t)0x30) }
TIM5 External Trigger Prescaler. More...
enum TIM5_FLAG_TypeDef {
TIM5_FLAG_UPDATE = ((uint16_t)0x0001), TIM5_FLAG_CC1 = ((uint16_t)0x0002), TIM5_FLAG_CC2 = ((uint16_t)0x0004), TIM5_FLAG_CC3 = ((uint16_t)0x0008),
TIM5_FLAG_TRIGGER = ((uint16_t)0x0040), TIM5_FLAG_CC1OF = ((uint16_t)0x0200), TIM5_FLAG_CC2OF = ((uint16_t)0x0400), TIM5_FLAG_CC3OF = ((uint16_t)0x0800)
}
TIM5 Flags. More...
enum | TIM5_ForcedAction_TypeDef { TIM5_FORCEDACTION_ACTIVE = ((uint8_t)0x50), TIM5_FORCEDACTION_INACTIVE = ((uint8_t)0x40) }
TIM5 Forced Action. More...
enum | TIM5_ICPolarity_TypeDef { TIM5_ICPOLARITY_RISING = ((uint8_t)0x00), TIM5_ICPOLARITY_FALLING = ((uint8_t)0x44) }
TIM5 Input Capture Polarity. More...
enum | TIM5_ICPSC_TypeDef { TIM5_ICPSC_DIV1 = ((uint8_t)0x00), TIM5_ICPSC_DIV2 = ((uint8_t)0x04), TIM5_ICPSC_DIV4 = ((uint8_t)0x08), TIM5_ICPSC_DIV8 = ((uint8_t)0x0C) }
TIM5 Input Capture Prescaler. More...
enum | TIM5_ICSelection_TypeDef { TIM5_ICSELECTION_DIRECTTI = ((uint8_t)0x01), TIM5_ICSELECTION_INDIRECTTI = ((uint8_t)0x02), TIM5_ICSELECTION_TRGI = ((uint8_t)0x03) }
TIM5 Input Capture Selection. More...
enum TIM5_IT_TypeDef {
TIM5_IT_UPDATE = ((uint8_t)0x01), TIM5_IT_CC1 = ((uint8_t)0x02), TIM5_IT_CC2 = ((uint8_t)0x04), TIM5_IT_CC3 = ((uint8_t)0x08),
TIM5_IT_TRIGGER = ((uint8_t)0x40)
}
TIM5 interrupt sources. More...
enum TIM5_OCMode_TypeDef {
TIM5_OCMODE_TIMING = ((uint8_t)0x00), TIM5_OCMODE_ACTIVE = ((uint8_t)0x10), TIM5_OCMODE_INACTIVE = ((uint8_t)0x20), TIM5_OCMODE_TOGGLE = ((uint8_t)0x30),
TIM5_OCMODE_PWM1 = ((uint8_t)0x60), TIM5_OCMODE_PWM2 = ((uint8_t)0x70)
}
TIM5 Output Compare and PWM modes. More...
enum | TIM5_OCPolarity_TypeDef { TIM5_OCPOLARITY_HIGH = ((uint8_t)0x00), TIM5_OCPOLARITY_LOW = ((uint8_t)0x22) }
TIM5 Output Compare Polarity. More...
enum | TIM5_OPMode_TypeDef { TIM5_OPMODE_SINGLE = ((uint8_t)0x01), TIM5_OPMODE_REPETITIVE = ((uint8_t)0x00) }
TIM5 One Pulse Mode. More...
enum | TIM5_OutputState_TypeDef { TIM5_OUTPUTSTATE_DISABLE = ((uint8_t)0x00), TIM5_OUTPUTSTATE_ENABLE = ((uint8_t)0x11) }
TIM5 Output Compare states. More...
enum TIM5_Prescaler_TypeDef {
TIM5_PRESCALER_1 = ((uint8_t)0x00), TIM5_PRESCALER_2 = ((uint8_t)0x01), TIM5_PRESCALER_4 = ((uint8_t)0x02), TIM5_PRESCALER_8 = ((uint8_t)0x03),
TIM5_PRESCALER_16 = ((uint8_t)0x04), TIM5_PRESCALER_32 = ((uint8_t)0x05), TIM5_PRESCALER_64 = ((uint8_t)0x06), TIM5_PRESCALER_128 = ((uint8_t)0x07),
TIM5_PRESCALER_256 = ((uint8_t)0x08), TIM5_PRESCALER_512 = ((uint8_t)0x09), TIM5_PRESCALER_1024 = ((uint8_t)0x0A), TIM5_PRESCALER_2048 = ((uint8_t)0x0B),
TIM5_PRESCALER_4096 = ((uint8_t)0x0C), TIM5_PRESCALER_8192 = ((uint8_t)0x0D), TIM5_PRESCALER_16384 = ((uint8_t)0x0E), TIM5_PRESCALER_32768 = ((uint8_t)0x0F)
}
TIM5 Prescaler. More...
enum | TIM5_PSCReloadMode_TypeDef { TIM5_PSCRELOADMODE_UPDATE = ((uint8_t)0x00), TIM5_PSCRELOADMODE_IMMEDIATE = ((uint8_t)0x01) }
TIM5 Prescaler Reload Mode. More...
enum | TIM5_SlaveMode_TypeDef { TIM5_SLAVEMODE_RESET = ((uint8_t)0x04), TIM5_SLAVEMODE_GATED = ((uint8_t)0x05), TIM5_SLAVEMODE_TRIGGER = ((uint8_t)0x06), TIM5_SLAVEMODE_EXTERNAL1 = ((uint8_t)0x07) }
TIM5 Slave Mode. More...
enum TIM5_TRGOSource_TypeDef {
TIM5_TRGOSOURCE_RESET = ((uint8_t)0x00), TIM5_TRGOSOURCE_ENABLE = ((uint8_t)0x10), TIM5_TRGOSOURCE_UPDATE = ((uint8_t)0x20), TIM5_TRGOSOURCE_OC1 = ((uint8_t)0x30),
TIM5_TRGOSOURCE_OC1REF = ((uint8_t)0x40), TIM5_TRGOSOURCE_OC2REF = ((uint8_t)0x50)
}
TIM5 Trigger Output Source. More...
enum | TIM5_TS_TypeDef { TIM5_TS_TIM6 = ((uint8_t)0x00), TIM5_TS_TIM1 = ((uint8_t)0x03) }
TIM5 Internal Trigger Selection. More...
enum | TIM5_UpdateSource_TypeDef { TIM5_UPDATESOURCE_GLOBAL = ((uint8_t)0x00), TIM5_UPDATESOURCE_REGULAR = ((uint8_t)0x01) }
TIM5 Update Source. More...

Functions

void | TIM5_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM5 peripheral Preload register on ARR.
void | TIM5_CCPreloadControl (FunctionalState NewState)
void | TIM5_CCxCmd (TIM5_Channel_TypeDef TIM5_Channel, FunctionalState NewState)
Enables or disables the TIM5 Capture Compare Channel x.
void | TIM5_ClearFlag (TIM5_FLAG_TypeDef TIM5_FLAG)
Clears the TIM5’s pending flags.
void | TIM5_ClearITPendingBit (TIM5_IT_TypeDef TIM5_IT)
Clears the TIM5's interrupt pending bits.
void | TIM5_Cmd (FunctionalState NewState)
Enables or disables the TIM5 peripheral.
void | TIM5_DeInit (void)
Deinitializes the TIM5 peripheral registers to their default reset values.
void | TIM5_EncoderInterfaceConfig (TIM5_EncoderMode_TypeDef TIM5_EncoderMode, TIM5_ICPolarity_TypeDef TIM5_IC1Polarity, TIM5_ICPolarity_TypeDef TIM5_IC2Polarity)
Configures the TIM5 Encoder Interface.
void | TIM5_ForcedOC1Config (TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
Forces the TIM5 Channel1 output waveform to active or inactive level.
void | TIM5_ForcedOC2Config (TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
Forces the TIM5 Channel2 output waveform to active or inactive level.
void | TIM5_ForcedOC3Config (TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
Forces the TIM5 Channel3 output waveform to active or inactive level.
void | TIM5_GenerateEvent (TIM5_EventSource_TypeDef TIM5_EventSource)
Configures the TIM5 event to be generated by software.
uint16_t | TIM5_GetCapture1 (void)
Gets the TIM5 Input Capture 1 value.
uint16_t | TIM5_GetCapture2 (void)
Gets the TIM5 Input Capture 2 value.
uint16_t | TIM5_GetCapture3 (void)
Gets the TIM5 Input Capture 3 value.
uint16_t | TIM5_GetCounter (void)
Gets the TIM5 Counter value.
FlagStatus | TIM5_GetFlagStatus (TIM5_FLAG_TypeDef TIM5_FLAG)
Checks whether the specified TIM5 flag is set or not.
ITStatus | TIM5_GetITStatus (TIM5_IT_TypeDef TIM5_IT)
Checks whether the TIM5 interrupt has occurred or not.
TIM5_Prescaler_TypeDef | TIM5_GetPrescaler (void)
Gets the TIM5 Prescaler value.
void | TIM5_ICInit (TIM5_Channel_TypeDef TIM5_Channel, TIM5_ICPolarity_TypeDef TIM5_ICPolarity, TIM5_ICSelection_TypeDef TIM5_ICSelection, TIM5_ICPSC_TypeDef TIM5_ICPrescaler, uint8_t TIM5_ICFilter)
Initializes the TIM5 peripheral according to the specified parameters.
void | TIM5_InternalClockConfig (void)
Enables the TIM5 internal Clock.
void | TIM5_ITConfig (TIM5_IT_TypeDef TIM5_IT, FunctionalState NewState)
Enables or disables the specified TIM5 interrupts.
void | TIM5_OC1Init (TIM5_OCMode_TypeDef TIM5_OCMode, TIM5_OutputState_TypeDef TIM5_OutputState, uint16_t TIM5_Pulse, TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Initializes the TIM5 Channel1 according to the specified parameters.
void | TIM5_OC1PolarityConfig (TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Configures the TIM5 Channel 1 polarity.
void | TIM5_OC1PreloadConfig (FunctionalState NewState)
Enables or disables the TIM5 peripheral Preload Register on CCR1.
void | TIM5_OC2Init (TIM5_OCMode_TypeDef TIM5_OCMode, TIM5_OutputState_TypeDef TIM5_OutputState, uint16_t TIM5_Pulse, TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Initializes the TIM5 Channel2 according to the specified parameters.
void | TIM5_OC2PolarityConfig (TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Configures the TIM5 Channel 2 polarity.
void | TIM5_OC2PreloadConfig (FunctionalState NewState)
Enables or disables the TIM5 peripheral Preload Register on CCR2.
void | TIM5_OC3Init (TIM5_OCMode_TypeDef TIM5_OCMode, TIM5_OutputState_TypeDef TIM5_OutputState, uint16_t TIM5_Pulse, TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Initializes the TIM5 Channel3 according to the specified parameters.
void | TIM5_OC3PolarityConfig (TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Configures the TIM5 Channel 3 polarity.
void | TIM5_OC3PreloadConfig (FunctionalState NewState)
Enables or disables the TIM5 peripheral Preload Register on CCR3.
void | TIM5_PrescalerConfig (TIM5_Prescaler_TypeDef Prescaler, TIM5_PSCReloadMode_TypeDef TIM5_PSCReloadMode)
Configures the TIM5 Prescaler.
void | TIM5_PWMIConfig (TIM5_Channel_TypeDef TIM5_Channel, TIM5_ICPolarity_TypeDef TIM5_ICPolarity, TIM5_ICSelection_TypeDef TIM5_ICSelection, TIM5_ICPSC_TypeDef TIM5_ICPrescaler, uint8_t TIM5_ICFilter)
Configures the TIM5 peripheral in PWM Input Mode according to the specified parameters.
void | TIM5_SelectInputTrigger (TIM5_TS_TypeDef TIM5_InputTriggerSource)
Selects the TIM5 Input Trigger source.
void | TIM5_SelectOCxM (TIM5_Channel_TypeDef TIM5_Channel, TIM5_OCMode_TypeDef TIM5_OCMode)
Selects the TIM5 Output Compare Mode.
void | TIM5_SelectOnePulseMode (TIM5_OPMode_TypeDef TIM5_OPMode)
Selects the TIM5’s One Pulse Mode.
void | TIM5_SelectOutputTrigger (TIM5_TRGOSource_TypeDef TIM5_TRGOSource)
Selects the TIM5 Trigger Output Mode.
void | TIM5_SelectSlaveMode (TIM5_SlaveMode_TypeDef TIM5_SlaveMode)
Selects the TIM5 Slave Mode.
void | TIM5_SetAutoreload (uint16_t Autoreload)
Sets the TIM5 Autoreload Register value.
void | TIM5_SetCompare1 (uint16_t Compare1)
Sets the TIM5 Capture Compare1 Register value.
void | TIM5_SetCompare2 (uint16_t Compare2)
Sets the TIM5 Capture Compare2 Register value.
void | TIM5_SetCompare3 (uint16_t Compare3)
Sets the TIM5 Capture Compare3 Register value.
void | TIM5_SetCounter (uint16_t Counter)
Sets the TIM5 Counter Register value.
void | TIM5_SetIC1Prescaler (TIM5_ICPSC_TypeDef TIM5_IC1Prescaler)
Sets the TIM5 Input Capture 1 prescaler.
void | TIM5_SetIC2Prescaler (TIM5_ICPSC_TypeDef TIM5_IC2Prescaler)
Sets the TIM5 Input Capture 2 prescaler.
void | TIM5_SetIC3Prescaler (TIM5_ICPSC_TypeDef TIM5_IC3Prescaler)
Sets the TIM5 Input Capture 3 prescaler.
void | TIM5_TimeBaseInit (TIM5_Prescaler_TypeDef TIM5_Prescaler, uint16_t TIM5_Period)
Initializes the TIM5 Time Base Unit according to the specified parameters.
void | TIM5_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM5 Update event.
void | TIM5_UpdateRequestConfig (TIM5_UpdateSource_TypeDef TIM5_UpdateSource)
Selects the TIM5 Update Request Interrupt source.

Detailed Description

This file contains all functions prototype and macros for the TIM5 peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_tim5.h.


STM8S/A Standard Peripherals Drivers: stm8s_tim6.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions
stm8s_tim6.c File Reference

This file contains all the functions for the TIM6 peripheral. More...

#include "stm8s_tim6.h"

Go to the source code of this file.

Functions

void | TIM6_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM6 peripheral Preload register on ARR.
void | TIM6_ClearFlag (TIM6_FLAG_TypeDef TIM6_FLAG)
Clears the TIM’s pending flags.
void | TIM6_ClearITPendingBit (TIM6_IT_TypeDef TIM6_IT)
Clears the TIM6's interrupt pending bits.
void | TIM6_Cmd (FunctionalState NewState)
Enables or disables the TIM6 peripheral.
void | TIM6_DeInit (void)
Deinitializes the TIM6 peripheral registers to their default reset values.
void | TIM6_GenerateEvent (TIM6_EventSource_TypeDef TIM6_EventSource)
Configures the TIM6 event to be generated by software.
uint8_t | TIM6_GetCounter (void)
Gets the TIM6 Counter value.
FlagStatus | TIM6_GetFlagStatus (TIM6_FLAG_TypeDef TIM6_FLAG)
Checks whether the specified TIM6 flag is set or not.
ITStatus | TIM6_GetITStatus (TIM6_IT_TypeDef TIM6_IT)
Checks whether the TIM6 interrupt has occurred or not.
TIM6_Prescaler_TypeDef | TIM6_GetPrescaler (void)
Gets the TIM6 Prescaler value.
void | TIM6_InternalClockConfig (void)
Enables the TIM6 internal Clock.
void | TIM6_ITConfig (TIM6_IT_TypeDef TIM6_IT, FunctionalState NewState)
Enables or disables the specified TIM6 interrupts.
void | TIM6_PrescalerConfig (TIM6_Prescaler_TypeDef Prescaler, TIM6_PSCReloadMode_TypeDef TIM6_PSCReloadMode)
Configures the TIM6 Prescaler.
void | TIM6_SelectInputTrigger (TIM6_TS_TypeDef TIM6_InputTriggerSource)
Selects the TIM6 Input Trigger source.
void | TIM6_SelectMasterSlaveMode (FunctionalState NewState)
Sets or Resets the TIM6 Master/Slave Mode.
void | TIM6_SelectOnePulseMode (TIM6_OPMode_TypeDef TIM6_OPMode)
Selects the TIM6’s One Pulse Mode.
void | TIM6_SelectOutputTrigger (TIM6_TRGOSource_TypeDef TIM6_TRGOSource)
Selects the TIM6 Trigger Output Mode.
void | TIM6_SelectSlaveMode (TIM6_SlaveMode_TypeDef TIM6_SlaveMode)
Selects the TIM6 Slave Mode.
void | TIM6_SetAutoreload (uint8_t Autoreload)
Sets the TIM6 Autoreload Register value.
void | TIM6_SetCounter (uint8_t Counter)
Sets the TIM6 Counter Register value.
void | TIM6_TimeBaseInit (TIM6_Prescaler_TypeDef TIM6_Prescaler, uint8_t TIM6_Period)
Initializes the TIM6 Time Base Unit according to the specified parameters.
void | TIM6_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM6 Update event.
void | TIM6_UpdateRequestConfig (TIM6_UpdateSource_TypeDef TIM6_UpdateSource)
Selects the TIM6 Update Request Interrupt source.

Detailed Description

This file contains all the functions for the TIM6 peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_tim6.c.


STM8S/A Standard Peripherals Drivers: stm8s_tim6.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions
stm8s_tim6.h File Reference

This file contains all functions prototype and macros for the TIM6 peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_TIM6_CLEAR_FLAG_OK(FLAG) ((((FLAG) & (uint8_t)0xBE) == 0x00) && ((FLAG) != 0x00))
#define | IS_TIM6_EVENT_SOURCE_OK(SOURCE)
Macro TIM6 Event source.
#define | IS_TIM6_GET_FLAG_OK(FLAG)
Macro TIM6 Flags.
#define | IS_TIM6_GET_IT_OK(IT)
#define | IS_TIM6_IT_OK(IT)
Macro TIM6 interrupts.
#define | IS_TIM6_OPM_MODE_OK(MODE)
Macro TIM6 One Pulse Mode.
#define | IS_TIM6_PRESCALER_OK(PRESCALER)
Macro used by the assert function to check the different functions parameters.
#define | IS_TIM6_PRESCALER_RELOAD_OK(RELOAD)
Macro TIM6 Prescaler reload.
#define | IS_TIM6_SLAVE_MODE_OK(MODE)
Macro TIM6 Slave mode.
#define | IS_TIM6_TRGO_SOURCE_OK(SOURCE)
Macro TIM6 TRGO source.
#define | IS_TIM6_TRIGGER_SELECTION_OK(SELECTION)
Macro TIM6 Trigger selection.
#define | IS_TIM6_UPDATE_SOURCE_OK(SOURCE)
Macro TIM6 Update source.

Enumerations

enum | TIM6_EventSource_TypeDef { TIM6_EVENTSOURCE_UPDATE = ((uint8_t)0x01), TIM6_EVENTSOURCE_TRIGGER = ((uint8_t)0x40) }
TIM6 Event Source. More...
enum | TIM6_FLAG_TypeDef { TIM6_FLAG_UPDATE = ((uint8_t)0x01), TIM6_FLAG_TRIGGER = ((uint8_t)0x40) }
TIM6 Flags. More...
enum | TIM6_IT_TypeDef { TIM6_IT_UPDATE = ((uint8_t)0x01), TIM6_IT_TRIGGER = ((uint8_t)0x40) }
TIM6 interrupt sources. More...
enum | TIM6_OPMode_TypeDef { TIM6_OPMODE_SINGLE = ((uint8_t)0x01), TIM6_OPMODE_REPETITIVE = ((uint8_t)0x00) }
TIM6 One Pulse Mode. More...
enum TIM6_Prescaler_TypeDef {
TIM6_PRESCALER_1 = ((uint8_t)0x00), TIM6_PRESCALER_2 = ((uint8_t)0x01), TIM6_PRESCALER_4 = ((uint8_t)0x02), TIM6_PRESCALER_8 = ((uint8_t)0x03),
TIM6_PRESCALER_16 = ((uint8_t)0x04), TIM6_PRESCALER_32 = ((uint8_t)0x05), TIM6_PRESCALER_64 = ((uint8_t)0x06), TIM6_PRESCALER_128 = ((uint8_t)0x07)
}
TIM6 Prescaler. More...
enum | TIM6_PSCReloadMode_TypeDef { TIM6_PSCRELOADMODE_UPDATE = ((uint8_t)0x00), TIM6_PSCRELOADMODE_IMMEDIATE = ((uint8_t)0x01) }
TIM6 Prescaler Reload Mode. More...
enum TIM6_SlaveMode_TypeDef {
TIM6_SLAVEMODE_DISABLE = ((uint8_t)0x00), TIM6_SLAVEMODE_RESET = ((uint8_t)0x04), TIM6_SLAVEMODE_GATED = ((uint8_t)0x05), TIM6_SLAVEMODE_TRIGGER = ((uint8_t)0x06),
TIM6_SLAVEMODE_EXTERNAL1 = ((uint8_t)0x07)
}
TIM6 Slave Mode. More...
enum | TIM6_TRGOSource_TypeDef { TIM6_TRGOSOURCE_RESET = ((uint8_t)0x00), TIM6_TRGOSOURCE_ENABLE = ((uint8_t)0x10), TIM6_TRGOSOURCE_UPDATE = ((uint8_t)0x20) }
TIM6 Trigger Output Source. More...
enum | TIM6_TS_TypeDef { TIM6_TS_TIM1 = ((uint8_t)0x20), TIM6_TS_TIM5 = ((uint8_t)0x30) }
TIM6 Internal Trigger Selection. More...
enum | TIM6_UpdateSource_TypeDef { TIM6_UPDATESOURCE_GLOBAL = ((uint8_t)0x00), TIM6_UPDATESOURCE_REGULAR = ((uint8_t)0x01) }
TIM6 Update Source. More...

Functions

void | TIM6_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM6 peripheral Preload register on ARR.
void | TIM6_ClearFlag (TIM6_FLAG_TypeDef TIM6_FLAG)
Clears the TIM’s pending flags.
void | TIM6_ClearITPendingBit (TIM6_IT_TypeDef TIM6_IT)
Clears the TIM6's interrupt pending bits.
void | TIM6_Cmd (FunctionalState NewState)
Enables or disables the TIM6 peripheral.
void | TIM6_DeInit (void)
Deinitializes the TIM6 peripheral registers to their default reset values.
void | TIM6_GenerateEvent (TIM6_EventSource_TypeDef TIM6_EventSource)
Configures the TIM6 event to be generated by software.
uint8_t | TIM6_GetCounter (void)
Gets the TIM6 Counter value.
FlagStatus | TIM6_GetFlagStatus (TIM6_FLAG_TypeDef TIM6_FLAG)
Checks whether the specified TIM6 flag is set or not.
ITStatus | TIM6_GetITStatus (TIM6_IT_TypeDef TIM6_IT)
Checks whether the TIM6 interrupt has occurred or not.
TIM6_Prescaler_TypeDef | TIM6_GetPrescaler (void)
Gets the TIM6 Prescaler value.
void | TIM6_InternalClockConfig (void)
Enables the TIM6 internal Clock.
void | TIM6_ITConfig (TIM6_IT_TypeDef TIM6_IT, FunctionalState NewState)
Enables or disables the specified TIM6 interrupts.
void | TIM6_PrescalerConfig (TIM6_Prescaler_TypeDef Prescaler, TIM6_PSCReloadMode_TypeDef TIM6_PSCReloadMode)
Configures the TIM6 Prescaler.
void | TIM6_SelectInputTrigger (TIM6_TS_TypeDef TIM6_InputTriggerSource)
Selects the TIM6 Input Trigger source.
void | TIM6_SelectMasterSlaveMode (FunctionalState NewState)
Sets or Resets the TIM6 Master/Slave Mode.
void | TIM6_SelectOnePulseMode (TIM6_OPMode_TypeDef TIM6_OPMode)
Selects the TIM6’s One Pulse Mode.
void | TIM6_SelectOutputTrigger (TIM6_TRGOSource_TypeDef TIM6_TRGOSource)
Selects the TIM6 Trigger Output Mode.
void | TIM6_SelectSlaveMode (TIM6_SlaveMode_TypeDef TIM6_SlaveMode)
Selects the TIM6 Slave Mode.
void | TIM6_SetAutoreload (uint8_t Autoreload)
Sets the TIM6 Autoreload Register value.
void | TIM6_SetCounter (uint8_t Counter)
Sets the TIM6 Counter Register value.
void | TIM6_TimeBaseInit (TIM6_Prescaler_TypeDef TIM6_Prescaler, uint8_t TIM6_Period)
Initializes the TIM6 Time Base Unit according to the specified parameters.
void | TIM6_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM6 Update event.
void | TIM6_UpdateRequestConfig (TIM6_UpdateSource_TypeDef TIM6_UpdateSource)
Selects the TIM6 Update Request Interrupt source.

Detailed Description

This file contains all functions prototype and macros for the TIM6 peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_tim6.h.


STM8S/A Standard Peripherals Drivers: stm8s_uart1.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions
stm8s_uart1.c File Reference

This file contains all the functions for the UART1 peripheral. More...

#include "stm8s_uart1.h"

Go to the source code of this file.

Functions

void | UART1_ClearFlag (UART1_Flag_TypeDef UART1_FLAG)
Clears the UART1 flags.
void | UART1_ClearITPendingBit (UART1_IT_TypeDef UART1_IT)
Clears the UART1 pending flags.
void | UART1_Cmd (FunctionalState NewState)
Enable the UART1 peripheral.
void | UART1_DeInit (void)
Deinitializes the UART peripheral.
FlagStatus | UART1_GetFlagStatus (UART1_Flag_TypeDef UART1_FLAG)
Checks whether the specified UART1 flag is set or not.
ITStatus | UART1_GetITStatus (UART1_IT_TypeDef UART1_IT)
Checks whether the specified UART1 interrupt has occurred or not.
void | UART1_HalfDuplexCmd (FunctionalState NewState)
Enables or disables the UART’s Half Duplex communication.
void | UART1_Init (uint32_t BaudRate, UART1_WordLength_TypeDef WordLength, UART1_StopBits_TypeDef StopBits, UART1_Parity_TypeDef Parity, UART1_SyncMode_TypeDef SyncMode, UART1_Mode_TypeDef Mode)
Initializes the UART1 according to the specified parameters.
void | UART1_IrDACmd (FunctionalState NewState)
Enables or disables the UART’s IrDA interface.
void | UART1_IrDAConfig (UART1_IrDAMode_TypeDef UART1_IrDAMode)
Configures the UART’s IrDA interface.
void | UART1_ITConfig (UART1_IT_TypeDef UART1_IT, FunctionalState NewState)
Enables or disables the specified USART interrupts.
void | UART1_LINBreakDetectionConfig (UART1_LINBreakDetectionLength_TypeDef UART1_LINBreakDetectionLength)
Sets the UART1 LIN Break detection length.
void | UART1_LINCmd (FunctionalState NewState)
Enables or disables the UART1’s LIN mode.
uint8_t | UART1_ReceiveData8 (void)
Returns the most recent received data by the UART1 peripheral.
uint16_t | UART1_ReceiveData9 (void)
Returns the most recent received data by the UART1 peripheral.
void | UART1_ReceiverWakeUpCmd (FunctionalState NewState)
Determines if the UART1 is in mute mode or not.
void | UART1_SendBreak (void)
Transmits break characters.
void | UART1_SendData8 (uint8_t Data)
Transmits 8 bit data through the UART1 peripheral.
void | UART1_SendData9 (uint16_t Data)
Transmits 9 bit data through the UART peripheral.
void | UART1_SetAddress (uint8_t UART1_Address)
Sets the address of the UART1 node.
void | UART1_SetGuardTime (uint8_t UART1_GuardTime)
Sets the specified UART guard time.
void | UART1_SetPrescaler (uint8_t UART1_Prescaler)
Sets the system clock prescaler.
void | UART1_SmartCardCmd (FunctionalState NewState)
Enables or disables the UART1 Smart Card mode.
void | UART1_SmartCardNACKCmd (FunctionalState NewState)
Enables or disables NACK transmission.
void | UART1_WakeUpConfig (UART1_WakeUp_TypeDef UART1_WakeUp)
Selects the UART1 WakeUp method.

Detailed Description

This file contains all the functions for the UART1 peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_uart1.c.


STM8S/A Standard Peripherals Drivers: stm8s_uart1.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions
stm8s_uart1.h File Reference

This file contains all functions prototypes and macros for the UART1 peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_UART1_ADDRESS_OK(node) ((node) < UART1_ADDRESS_MAX )
#define | IS_UART1_BAUDRATE_OK(NUM) ((NUM) <= (uint32_t)625000)
Macro used by the assert_param function in order to check the maximum baudrate value.
#define | IS_UART1_CLEAR_FLAG_OK(Flag)
Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs that can be cleared by writing 0.
#define | IS_UART1_CLEAR_IT_OK(ITPendingBit)
Macro used by the assert function in order to check the different sensitivity values for the pending bit that can be cleared by writing 0.
#define | IS_UART1_CONFIG_IT_OK(Interrupt)
Macro used by the assert_param function in order to check the different sensitivity values for the Interrupts.
#define | IS_UART1_FLAG_OK(Flag)
Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs.
#define | IS_UART1_GET_IT_OK(ITPendingBit)
Macro used by the assert function in order to check the different sensitivity values for the pending bit.
#define | IS_UART1_IRDAMODE_OK(IrDAMode)
Macro used by the assert_param function in order to check the different sensitivity values for the IrDAModes.
#define | IS_UART1_LINBREAKDETECTIONLENGTH_OK(LINBreakDetectionLength)
Macro used by the assert_param function in order to check the different sensitivity values for the LINBreakDetectionLengths.
#define | IS_UART1_MODE_OK(Mode)
Macro used by the assert function to check the different functions parameters.
#define | IS_UART1_PARITY_OK(Parity)
Macro used by the assert_param function in order to check the different sensitivity values for the Parity.
#define | IS_UART1_STOPBITS_OK(StopBit)
Macro used by the assert_param function in order to check the different sensitivity values for the UART1_StopBits.
#define | IS_UART1_SYNCMODE_OK(SyncMode)
Macro used by the assert_param function in order to check the different sensitivity values for the SyncModes; it should exclude values such as UART1_CLOCK_ENABLE|UART1_CLOCK_DISABLE.
#define | IS_UART1_WAKEUP_OK(WakeUp)
Macro used by the assert_param function in order to check the different sensitivity values for the WakeUps.
#define | IS_UART1_WORDLENGTH_OK(WordLength)
Macro used by the assert_param function in order to check the different sensitivity values for the WordLengths.
#define | UART1_ADDRESS_MAX ((uint8_t)16)
Macro used by the assert_param function in order to check the address of the UART1 or UART node.

Enumerations

enum UART1_Flag_TypeDef {
UART1_FLAG_TXE = (uint16_t)0x0080, UART1_FLAG_TC = (uint16_t)0x0040, UART1_FLAG_RXNE = (uint16_t)0x0020, UART1_FLAG_IDLE = (uint16_t)0x0010,
UART1_FLAG_OR = (uint16_t)0x0008, UART1_FLAG_NF = (uint16_t)0x0004, UART1_FLAG_FE = (uint16_t)0x0002, UART1_FLAG_PE = (uint16_t)0x0001,
UART1_FLAG_LBDF = (uint16_t)0x0210, UART1_FLAG_SBK = (uint16_t)0x0101
}
UART1 Flag possible values. More...
enum | UART1_IrDAMode_TypeDef { UART1_IRDAMODE_NORMAL = (uint8_t)0x00, UART1_IRDAMODE_LOWPOWER = (uint8_t)0x01 }
UART1 Irda Modes. More...
enum UART1_IT_TypeDef {
UART1_IT_TXE = (uint16_t)0x0277, UART1_IT_TC = (uint16_t)0x0266, UART1_IT_RXNE = (uint16_t)0x0255, UART1_IT_IDLE = (uint16_t)0x0244,
UART1_IT_OR = (uint16_t)0x0235, UART1_IT_PE = (uint16_t)0x0100, UART1_IT_LBDF = (uint16_t)0x0346, UART1_IT_RXNE_OR = (uint16_t)0x0205
}
UART1 Interrupt definition UART1_IT possible values Elements values convention: 0xZYX X: Position of the corresponding Interrupt. More...
enum | UART1_LINBreakDetectionLength_TypeDef { UART1_LINBREAKDETECTIONLENGTH_10BITS = (uint8_t)0x00, UART1_LINBREAKDETECTIONLENGTH_11BITS = (uint8_t)0x01 }
UART1 LIN Break detection length possible values. More...
enum UART1_Mode_TypeDef {
UART1_MODE_RX_ENABLE = (uint8_t)0x08, UART1_MODE_TX_ENABLE = (uint8_t)0x04, UART1_MODE_TX_DISABLE = (uint8_t)0x80, UART1_MODE_RX_DISABLE = (uint8_t)0x40,
UART1_MODE_TXRX_ENABLE = (uint8_t)0x0C
}
UART1 Mode possible values. More...
enum | UART1_Parity_TypeDef { UART1_PARITY_NO = (uint8_t)0x00, UART1_PARITY_EVEN = (uint8_t)0x04, UART1_PARITY_ODD = (uint8_t)0x06 }
UART1 parity possible values. More...
enum | UART1_StopBits_TypeDef { UART1_STOPBITS_1 = (uint8_t)0x00, UART1_STOPBITS_0_5 = (uint8_t)0x10, UART1_STOPBITS_2 = (uint8_t)0x20, UART1_STOPBITS_1_5 = (uint8_t)0x30 }
UART1 stop bits possible values. More...
enum UART1_SyncMode_TypeDef {
UART1_SYNCMODE_CLOCK_DISABLE = (uint8_t)0x80, UART1_SYNCMODE_CLOCK_ENABLE = (uint8_t)0x08, UART1_SYNCMODE_CPOL_LOW = (uint8_t)0x40, UART1_SYNCMODE_CPOL_HIGH = (uint8_t)0x04,
UART1_SYNCMODE_CPHA_MIDDLE = (uint8_t)0x20, UART1_SYNCMODE_CPHA_BEGINING = (uint8_t)0x02, UART1_SYNCMODE_LASTBIT_DISABLE = (uint8_t)0x10, UART1_SYNCMODE_LASTBIT_ENABLE = (uint8_t)0x01
}
UART1 Synchrone modes. More...
enum | UART1_WakeUp_TypeDef { UART1_WAKEUP_IDLELINE = (uint8_t)0x00, UART1_WAKEUP_ADDRESSMARK = (uint8_t)0x08 }
UART1 WakeUP Modes. More...
enum | UART1_WordLength_TypeDef { UART1_WORDLENGTH_8D = (uint8_t)0x00, UART1_WORDLENGTH_9D = (uint8_t)0x10 }
UART1 Word length possible values. More...

Functions

void | UART1_ClearFlag (UART1_Flag_TypeDef UART1_FLAG)
Clears the UART1 flags.
void | UART1_ClearITPendingBit (UART1_IT_TypeDef UART1_IT)
Clears the UART1 pending flags.
void | UART1_Cmd (FunctionalState NewState)
Enable the UART1 peripheral.
void | UART1_DeInit (void)
Deinitializes the UART peripheral.
FlagStatus | UART1_GetFlagStatus (UART1_Flag_TypeDef UART1_FLAG)
Checks whether the specified UART1 flag is set or not.
ITStatus | UART1_GetITStatus (UART1_IT_TypeDef UART1_IT)
Checks whether the specified UART1 interrupt has occurred or not.
void | UART1_HalfDuplexCmd (FunctionalState NewState)
Enables or disables the UART’s Half Duplex communication.
void | UART1_Init (uint32_t BaudRate, UART1_WordLength_TypeDef WordLength, UART1_StopBits_TypeDef StopBits, UART1_Parity_TypeDef Parity, UART1_SyncMode_TypeDef SyncMode, UART1_Mode_TypeDef Mode)
Initializes the UART1 according to the specified parameters.
void | UART1_IrDACmd (FunctionalState NewState)
Enables or disables the UART’s IrDA interface.
void | UART1_IrDAConfig (UART1_IrDAMode_TypeDef UART1_IrDAMode)
Configures the UART’s IrDA interface.
void | UART1_ITConfig (UART1_IT_TypeDef UART1_IT, FunctionalState NewState)
Enables or disables the specified USART interrupts.
void | UART1_LINBreakDetectionConfig (UART1_LINBreakDetectionLength_TypeDef UART1_LINBreakDetectionLength)
Sets the UART1 LIN Break detection length.
void | UART1_LINCmd (FunctionalState NewState)
Enables or disables the UART1’s LIN mode.
uint8_t | UART1_ReceiveData8 (void)
Returns the most recent received data by the UART1 peripheral.
uint16_t | UART1_ReceiveData9 (void)
Returns the most recent received data by the UART1 peripheral.
void | UART1_ReceiverWakeUpCmd (FunctionalState NewState)
Determines if the UART1 is in mute mode or not.
void | UART1_SendBreak (void)
Transmits break characters.
void | UART1_SendData8 (uint8_t Data)
Transmits 8 bit data through the UART1 peripheral.
void | UART1_SendData9 (uint16_t Data)
Transmits 9 bit data through the UART peripheral.
void | UART1_SetAddress (uint8_t UART1_Address)
Sets the address of the UART1 node.
void | UART1_SetGuardTime (uint8_t UART1_GuardTime)
Sets the specified UART guard time.
void | UART1_SetPrescaler (uint8_t UART1_Prescaler)
Sets the system clock prescaler.
void | UART1_SmartCardCmd (FunctionalState NewState)
Enables or disables the UART1 Smart Card mode.
void | UART1_SmartCardNACKCmd (FunctionalState NewState)
Enables or disables NACK transmission.
void | UART1_WakeUpConfig (UART1_WakeUp_TypeDef UART1_WakeUp)
Selects the UART1 WakeUp method.

Detailed Description

This file contains all functions prototypes and macros for the UART1 peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_uart1.h.


STM8S/A Standard Peripherals Drivers: stm8s_uart2.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions
stm8s_uart2.c File Reference

This file contains all the functions for the UART2 peripheral. More...

#include "stm8s_uart2.h"

Go to the source code of this file.

Functions

void | UART2_ClearFlag (UART2_Flag_TypeDef UART2_FLAG)
Clears the UART2 flags.
void | UART2_ClearITPendingBit (UART2_IT_TypeDef UART2_IT)
Clears the UART2 pending flags.
void | UART2_Cmd (FunctionalState NewState)
Enable the UART2 peripheral.
void | UART2_DeInit (void)
Deinitializes the UART peripheral.
FlagStatus | UART2_GetFlagStatus (UART2_Flag_TypeDef UART2_FLAG)
Checks whether the specified UART2 flag is set or not.
ITStatus | UART2_GetITStatus (UART2_IT_TypeDef UART2_IT)
Checks whether the specified UART2 interrupt has occurred or not.
void | UART2_Init (uint32_t BaudRate, UART2_WordLength_TypeDef WordLength, UART2_StopBits_TypeDef StopBits, UART2_Parity_TypeDef Parity, UART2_SyncMode_TypeDef SyncMode, UART2_Mode_TypeDef Mode)
Initializes the UART2 according to the specified parameters.
void | UART2_IrDACmd (FunctionalState NewState)
Enables or disables the UART2’s IrDA interface.
void | UART2_IrDAConfig (UART2_IrDAMode_TypeDef UART2_IrDAMode)
Configures the UART2’s IrDA interface.
void | UART2_ITConfig (UART2_IT_TypeDef UART2_IT, FunctionalState NewState)
Enables or disables the specified UART2 interrupts.
void | UART2_LINBreakDetectionConfig (UART2_LINBreakDetectionLength_TypeDef UART2_LINBreakDetectionLength)
Sets the UART2 LIN Break detection length.
void | UART2_LINCmd (FunctionalState NewState)
Enables or disables the UART2 LIN mode.
void | UART2_LINConfig (UART2_LinMode_TypeDef UART2_Mode, UART2_LinAutosync_TypeDef UART2_Autosync, UART2_LinDivUp_TypeDef UART2_DivUp)
Configure the UART2 peripheral.
uint8_t | UART2_ReceiveData8 (void)
Returns the most recent received data by the UART2 peripheral.
uint16_t | UART2_ReceiveData9 (void)
Returns the most recent received data by the UART2 peripheral.
void | UART2_ReceiverWakeUpCmd (FunctionalState NewState)
Determines if the UART2 is in mute mode or not.
void | UART2_SendBreak (void)
Transmits break characters.
void | UART2_SendData8 (uint8_t Data)
Transmits 8 bit data through the UART2 peripheral.
void | UART2_SendData9 (uint16_t Data)
Transmits 9 bit data through the UART2 peripheral.
void | UART2_SetAddress (uint8_t UART2_Address)
Sets the address of the UART2 node.
void | UART2_SetGuardTime (uint8_t UART2_GuardTime)
Sets the specified UART2 guard time.
void | UART2_SetPrescaler (uint8_t UART2_Prescaler)
Sets the system clock prescaler.
void | UART2_SmartCardCmd (FunctionalState NewState)
Enables or disables the UART2 Smart Card mode.
void | UART2_SmartCardNACKCmd (FunctionalState NewState)
Enables or disables NACK transmission.
void | UART2_WakeUpConfig (UART2_WakeUp_TypeDef UART2_WakeUp)
Selects the UART2 WakeUp method.

Detailed Description

This file contains all the functions for the UART2 peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_uart2.c.


STM8S/A Standard Peripherals Drivers: stm8s_uart2.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions
stm8s_uart2.h File Reference

This file contains all functions prototypes and macros for the UART2 peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_UART2_ADDRESS_OK(node) ((node) < UART2_ADDRESS_MAX )
#define | IS_UART2_AUTOSYNC_OK(AutosyncMode)
Macro used by the assert_param function in order to check the LIN automatic resynchronization mode.
#define | IS_UART2_BAUDRATE_OK(NUM) ((NUM) <= (uint32_t)625000)
Macro used by the assert_param function in order to check the maximum baudrate value.
#define | IS_UART2_CLEAR_FLAG_OK(Flag)
Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs that can be cleared by writing 0.
#define | IS_UART2_CLEAR_IT_OK(ITPendingBit)
Macro used by the assert function in order to check the different sensitivity values for the pending bit that can be cleared by writing 0.
#define | IS_UART2_CONFIG_IT_OK(Interrupt)
Macro used by the assert_param function in order to check the different sensitivity values for the Interrupts.
#define | IS_UART2_DIVUP_OK(DivupMethod)
Macro used by the assert_param function in order to check the LIN divider update method.
#define | IS_UART2_FLAG_OK(Flag)
Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs.
#define | IS_UART2_GET_IT_OK(ITPendingBit)
Macro used by the assert function in order to check the different sensitivity values for the pending bit.
#define | IS_UART2_IRDAMODE_OK(IrDAMode)
Macro used by the assert_param function in order to check the different sensitivity values for the IrDAModes.
#define | IS_UART2_LINBREAKDETECTIONLENGTH_OK(LINBreakDetectionLength)
Macro used by the assert_param function in order to check the different sensitivity values for the LINBreakDetectionLengths.
#define | IS_UART2_MODE_OK(Mode)
Macro used by the assert function to check the different functions parameters.
#define | IS_UART2_PARITY_OK(Parity)
Macro used by the assert_param function in order to check the different sensitivity values for the Paritys.
#define | IS_UART2_SLAVE_OK(Mode)
Macro used by the assert_param function in order to check the LIN mode.
#define | IS_UART2_STOPBITS_OK(StopBit)
Macro used by the assert_param function in order to check the different sensitivity values for the UART2_StopBits.
#define | IS_UART2_SYNCMODE_OK(SyncMode)
Macro used by the assert_param function in order to check the different sensitivity values for the SyncModes; it should exclude values such as UART2_CLOCK_ENABLE|UART2_CLOCK_DISABLE.
#define | IS_UART2_WAKEUP_OK(WakeUp)
Macro used by the assert_param function in order to check the different sensitivity values for the WakeUps.
#define | IS_UART2_WORDLENGTH_OK(WordLength)
Macro used by the assert_param function in order to check the different sensitivity values for the WordLengths.
#define | UART2_ADDRESS_MAX ((uint8_t)16)
Macro used by the assert_param function in order to check the address of the UART2 or UART node.

Enumerations

enum UART2_Flag_TypeDef {
UART2_FLAG_TXE = (uint16_t)0x0080, UART2_FLAG_TC = (uint16_t)0x0040, UART2_FLAG_RXNE = (uint16_t)0x0020, UART2_FLAG_IDLE = (uint16_t)0x0010,
UART2_FLAG_OR_LHE = (uint16_t)0x0008, UART2_FLAG_NF = (uint16_t)0x0004, UART2_FLAG_FE = (uint16_t)0x0002, UART2_FLAG_PE = (uint16_t)0x0001,
UART2_FLAG_SBK = (uint16_t)0x0101, UART2_FLAG_LBDF = (uint16_t)0x0210, UART2_FLAG_LHDF = (uint16_t)0x0302, UART2_FLAG_LSF = (uint16_t)0x0301
}
UART2 Flag possible values. More...
enum | UART2_IrDAMode_TypeDef { UART2_IRDAMODE_NORMAL = (uint8_t)0x00, UART2_IRDAMODE_LOWPOWER = (uint8_t)0x01 }
UART2 Irda Modes. More...
enum UART2_IT_TypeDef {
UART2_IT_TXE = (uint16_t)0x0277, UART2_IT_TC = (uint16_t)0x0266, UART2_IT_RXNE = (uint16_t)0x0255, UART2_IT_IDLE = (uint16_t)0x0244,
UART2_IT_OR = (uint16_t)0x0235, UART2_IT_PE = (uint16_t)0x0100, UART2_IT_LBDF = (uint16_t)0x0346, UART2_IT_LHDF = (uint16_t)0x0412,
UART2_IT_RXNE_OR = (uint16_t)0x0205
}
UART2 Interrupt definition UART2_IT possible values Elements values convention: 0xZYX X: Position of the corresponding Interrupt. More...
enum | UART2_LinAutosync_TypeDef { UART2_LIN_AUTOSYNC_DISABLE = (uint8_t)0x00, UART2_LIN_AUTOSYNC_ENABLE = (uint8_t)0x01 }
UART2 automatic resynchronisation possible values. More...
enum | UART2_LINBreakDetectionLength_TypeDef { UART2_LINBREAKDETECTIONLENGTH_10BITS = (uint8_t)0x00, UART2_LINBREAKDETECTIONLENGTH_11BITS = (uint8_t)0x01 }
UART2 LIN Break detection length possible values. More...
enum | UART2_LinDivUp_TypeDef { UART2_LIN_DIVUP_LBRR1 = (uint8_t)0x00, UART2_LIN_DIVUP_NEXTRXNE = (uint8_t)0x01 }
UART2 Divider Update Method possible values. More...
enum | UART2_LinMode_TypeDef { UART2_LIN_MODE_MASTER = (uint8_t)0x00, UART2_LIN_MODE_SLAVE = (uint8_t)0x01 }
UART2 Mode possible values. More...
enum UART2_Mode_TypeDef {
UART2_MODE_RX_ENABLE = (uint8_t)0x08, UART2_MODE_TX_ENABLE = (uint8_t)0x04, UART2_MODE_TX_DISABLE = (uint8_t)0x80, UART2_MODE_RX_DISABLE = (uint8_t)0x40,
UART2_MODE_TXRX_ENABLE = (uint8_t)0x0C
}
UART2 Mode possible values. More...
enum | UART2_Parity_TypeDef { UART2_PARITY_NO = (uint8_t)0x00, UART2_PARITY_EVEN = (uint8_t)0x04, UART2_PARITY_ODD = (uint8_t)0x06 }
UART2 parity possible values. More...
enum | UART2_StopBits_TypeDef { UART2_STOPBITS_1 = (uint8_t)0x00, UART2_STOPBITS_0_5 = (uint8_t)0x10, UART2_STOPBITS_2 = (uint8_t)0x20, UART2_STOPBITS_1_5 = (uint8_t)0x30 }
UART2 stop bits possible values. More...
enum UART2_SyncMode_TypeDef {
UART2_SYNCMODE_CLOCK_DISABLE = (uint8_t)0x80, UART2_SYNCMODE_CLOCK_ENABLE = (uint8_t)0x08, UART2_SYNCMODE_CPOL_LOW = (uint8_t)0x40, UART2_SYNCMODE_CPOL_HIGH = (uint8_t)0x04,
UART2_SYNCMODE_CPHA_MIDDLE = (uint8_t)0x20, UART2_SYNCMODE_CPHA_BEGINING = (uint8_t)0x02, UART2_SYNCMODE_LASTBIT_DISABLE = (uint8_t)0x10, UART2_SYNCMODE_LASTBIT_ENABLE = (uint8_t)0x01
}
UART2 Synchrone modes. More...
enum | UART2_WakeUp_TypeDef { UART2_WAKEUP_IDLELINE = (uint8_t)0x00, UART2_WAKEUP_ADDRESSMARK = (uint8_t)0x08 }
UART2 WakeUP Modes. More...
enum | UART2_WordLength_TypeDef { UART2_WORDLENGTH_8D = (uint8_t)0x00, UART2_WORDLENGTH_9D = (uint8_t)0x10 }
UART2 Word length possible values. More...

Functions

void | UART2_ClearFlag (UART2_Flag_TypeDef UART2_FLAG)
Clears the UART2 flags.
void | UART2_ClearITPendingBit (UART2_IT_TypeDef UART2_IT)
Clears the UART2 pending flags.
void | UART2_Cmd (FunctionalState NewState)
Enable the UART2 peripheral.
void | UART2_DeInit (void)
Deinitializes the UART peripheral.
FlagStatus | UART2_GetFlagStatus (UART2_Flag_TypeDef UART2_FLAG)
Checks whether the specified UART2 flag is set or not.
ITStatus | UART2_GetITStatus (UART2_IT_TypeDef UART2_IT)
Checks whether the specified UART2 interrupt has occurred or not.
void | UART2_HalfDuplexCmd (FunctionalState NewState)
void | UART2_Init (uint32_t BaudRate, UART2_WordLength_TypeDef WordLength, UART2_StopBits_TypeDef StopBits, UART2_Parity_TypeDef Parity, UART2_SyncMode_TypeDef SyncMode, UART2_Mode_TypeDef Mode)
Initializes the UART2 according to the specified parameters.
void | UART2_IrDACmd (FunctionalState NewState)
Enables or disables the UART2’s IrDA interface.
void | UART2_IrDAConfig (UART2_IrDAMode_TypeDef UART2_IrDAMode)
Configures the UART2’s IrDA interface.
void | UART2_ITConfig (UART2_IT_TypeDef UART2_IT, FunctionalState NewState)
Enables or disables the specified UART2 interrupts.
void | UART2_LINBreakDetectionConfig (UART2_LINBreakDetectionLength_TypeDef UART2_LINBreakDetectionLength)
Sets the UART2 LIN Break detection length.
void | UART2_LINCmd (FunctionalState NewState)
Enables or disables the UART2 LIN mode.
void | UART2_LINConfig (UART2_LinMode_TypeDef UART2_Mode, UART2_LinAutosync_TypeDef UART2_Autosync, UART2_LinDivUp_TypeDef UART2_DivUp)
Configure the UART2 peripheral.
uint8_t | UART2_ReceiveData8 (void)
Returns the most recent received data by the UART2 peripheral.
uint16_t | UART2_ReceiveData9 (void)
Returns the most recent received data by the UART2 peripheral.
void | UART2_ReceiverWakeUpCmd (FunctionalState NewState)
Determines if the UART2 is in mute mode or not.
void | UART2_SendBreak (void)
Transmits break characters.
void | UART2_SendData8 (uint8_t Data)
Transmits 8 bit data through the UART2 peripheral.
void | UART2_SendData9 (uint16_t Data)
Transmits 9 bit data through the UART2 peripheral.
void | UART2_SetAddress (uint8_t UART2_Address)
Sets the address of the UART2 node.
void | UART2_SetGuardTime (uint8_t UART2_GuardTime)
Sets the specified UART2 guard time.
void | UART2_SetPrescaler (uint8_t UART2_Prescaler)
Sets the system clock prescaler.
void | UART2_SmartCardCmd (FunctionalState NewState)
Enables or disables the UART2 Smart Card mode.
void | UART2_SmartCardNACKCmd (FunctionalState NewState)
Enables or disables NACK transmission.
void | UART2_WakeUpConfig (UART2_WakeUp_TypeDef UART2_WakeUp)
Selects the UART2 WakeUp method.

Detailed Description

This file contains all functions prototypes and macros for the UART2 peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_uart2.h.


STM8S/A Standard Peripherals Drivers: stm8s_uart3.c File Reference

  • File List
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  • STM8S_StdPeriph_Driver
  • src
Functions
stm8s_uart3.c File Reference

This file contains all the functions for the uart3 peripheral. More...

#include "stm8s_uart3.h"

Go to the source code of this file.

Functions

void | UART3_ClearFlag (UART3_Flag_TypeDef UART3_FLAG)
Clears the UART3 flags.
void | UART3_ClearITPendingBit (UART3_IT_TypeDef UART3_IT)
Clears the UART3 pending flags.
void | UART3_Cmd (FunctionalState NewState)
Enable the UART1 peripheral.
void | UART3_DeInit (void)
Deinitializes the UART peripheral.
FlagStatus | UART3_GetFlagStatus (UART3_Flag_TypeDef UART3_FLAG)
Checks whether the specified UART3 flag is set or not.
ITStatus | UART3_GetITStatus (UART3_IT_TypeDef UART3_IT)
Checks whether the specified UART3 interrupt has occurred or not.
void | UART3_Init (uint32_t BaudRate, UART3_WordLength_TypeDef WordLength, UART3_StopBits_TypeDef StopBits, UART3_Parity_TypeDef Parity, UART3_Mode_TypeDef Mode)
Initializes the UART3 according to the specified parameters.
void | UART3_ITConfig (UART3_IT_TypeDef UART3_IT, FunctionalState NewState)
Enables or disables the specified UART3 interrupts.
void | UART3_LINBreakDetectionConfig (UART3_LINBreakDetectionLength_TypeDef UART3_LINBreakDetectionLength)
Sets the UART3 LIN Break detection length.
void | UART3_LINCmd (FunctionalState NewState)
Enables or disables the UART3 LIN mode.
void | UART3_LINConfig (UART3_LinMode_TypeDef UART3_Mode, UART3_LinAutosync_TypeDef UART3_Autosync, UART3_LinDivUp_TypeDef UART3_DivUp)
Configure the UART3 peripheral.
uint8_t | UART3_ReceiveData8 (void)
Returns the most recent received data by the UART3 peripheral.
uint16_t | UART3_ReceiveData9 (void)
Returns the most recent received data by the UART3 peripheral.
void | UART3_ReceiverWakeUpCmd (FunctionalState NewState)
Determines if the UART3 is in mute mode or not.
void | UART3_SendBreak (void)
Transmits break characters.
void | UART3_SendData8 (uint8_t Data)
Transmits 8 bit data through the UART3 peripheral.
void | UART3_SendData9 (uint16_t Data)
Transmits 9 bit data through the UART3 peripheral.
void | UART3_SetAddress (uint8_t UART3_Address)
Sets the address of the UART3 node.
void | UART3_WakeUpConfig (UART3_WakeUp_TypeDef UART3_WakeUp)
Selects the UART3 WakeUp method.

Detailed Description

This file contains all the functions for the uart3 peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_uart3.c.


STM8S/A Standard Peripherals Drivers: stm8s_uart3.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions
stm8s_uart3.h File Reference

This file contains all functions prototypes and macros for the UART3 peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_UART3_ADDRESS_OK(Node) ((Node) < UART3_ADDRESS_MAX)
#define | IS_UART3_AUTOSYNC_OK(AutosyncMode)
Macro used by the assert_param function in order to check the LIN automatic resynchronization mode.
#define | IS_UART3_BAUDRATE_OK(NUM) ((NUM) <= (uint32_t)625000)
Macro used by the assert_param function in order to check the maximum baudrate value.
#define | IS_UART3_CLEAR_FLAG_OK(Flag)
Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs that can be cleared by writing 0.
#define | IS_UART3_CLEAR_IT_OK(ITPendingBit)
Macro used by the assert function in order to check the different sensitivity values for the pending bit that can be cleared by writing 0.
#define | IS_UART3_CONFIG_IT_OK(Interrupt)
Macro used by the assert_param function in order to check the different sensitivity values for the Interrupts.
#define | IS_UART3_DIVUP_OK(DivupMethod)
Macro used by the assert_param function in order to check the LIN divider update method.
#define | IS_UART3_FLAG_OK(Flag)
Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs.
#define | IS_UART3_GET_IT_OK(ITPendingBit)
Macro used by the assert function in order to check the different sensitivity values for the pending bit.
#define | IS_UART3_LINBREAKDETECTIONLENGTH_OK(LINBreakDetectionLengths)
Macro used by the assert_param function in order to check the different sensitivity values for the LINBreakDetectionLengths.
#define | IS_UART3_MODE_OK(Mode)
Macro used by the assert_param function in order to check the different sensitivity values for the MODEs.
#define | IS_UART3_PARITY_OK(Parity)
Macro used by the assert_param function in order to check the different sensitivity values for the Parity.
#define | IS_UART3_SLAVE_OK(Mode)
Macro used by the assert_param function in order to check the LIN mode.
#define | IS_UART3_STOPBITS_OK(StopBit)
Macro used by the assert_param function in order to check the different sensitivity values for the UART3_StopBits.
#define | IS_UART3_WAKEUP_OK(WakeUpMode)
Macro used by the assert_param function in order to check the different sensitivity values for the WakeUps.
#define | IS_UART3_WORDLENGTH_OK(WordLength)
Macro used by the assert_param function in order to check the different sensitivity values for the WordLengths.
#define | UART3_ADDRESS_MAX ((uint8_t)16)
Macro used by the assert_param function in order to check the address of the UART3 or UART node.

Enumerations

enum UART3_Flag_TypeDef {
UART3_FLAG_TXE = (uint16_t)0x0080, UART3_FLAG_TC = (uint16_t)0x0040, UART3_FLAG_RXNE = (uint16_t)0x0020, UART3_FLAG_IDLE = (uint16_t)0x0010,
UART3_FLAG_OR_LHE = (uint16_t)0x0008, UART3_FLAG_NF = (uint16_t)0x0004, UART3_FLAG_FE = (uint16_t)0x0002, UART3_FLAG_PE = (uint16_t)0x0001,
UART3_FLAG_SBK = (uint16_t)0x0101, UART3_FLAG_LBDF = (uint16_t)0x0210, UART3_FLAG_LHDF = (uint16_t)0x0302, UART3_FLAG_LSF = (uint16_t)0x0301
}
UART3 Flag possible values. More...
enum UART3_IT_TypeDef {
UART3_IT_TXE = (uint16_t)0x0277, UART3_IT_TC = (uint16_t)0x0266, UART3_IT_RXNE = (uint16_t)0x0255, UART3_IT_IDLE = (uint16_t)0x0244,
UART3_IT_OR = (uint16_t)0x0235, UART3_IT_PE = (uint16_t)0x0100, UART3_IT_LBDF = (uint16_t)0x0346, UART3_IT_LHDF = (uint16_t)0x0412,
UART3_IT_RXNE_OR = (uint16_t)0x0205
}
UART3 Interrupt definition UART3_IT possible values Elements values convention: 0xZYX X: Position of the corresponding Interrupt. More...
enum | UART3_LinAutosync_TypeDef { UART3_LIN_AUTOSYNC_DISABLE = (uint8_t)0x00, UART3_LIN_AUTOSYNC_ENABLE = (uint8_t)0x01 }
UART3 automatic resynchronisation possible values. More...
enum | UART3_LINBreakDetectionLength_TypeDef { UART3_LINBREAKDETECTIONLENGTH_10BITS = (uint8_t)0x00, UART3_LINBREAKDETECTIONLENGTH_11BITS = (uint8_t)0x01 }
UART3 LIN Break detection length possible values. More...
enum | UART3_LinDivUp_TypeDef { UART3_LIN_DIVUP_LBRR1 = (uint8_t)0x00, UART3_LIN_DIVUP_NEXTRXNE = (uint8_t)0x01 }
UART3 Divider Update Method possible values. More...
enum | UART3_LinMode_TypeDef { UART3_LIN_MODE_MASTER = (uint8_t)0x00, UART3_LIN_MODE_SLAVE = (uint8_t)0x01 }
UART3 Mode possible values. More...
enum UART3_Mode_TypeDef {
UART3_MODE_RX_ENABLE = (uint8_t)0x08, UART3_MODE_TX_ENABLE = (uint8_t)0x04, UART3_MODE_TX_DISABLE = (uint8_t)0x80, UART3_MODE_RX_DISABLE = (uint8_t)0x40,
UART3_MODE_TXRX_ENABLE = (uint8_t)0x0C
}
UART3 Mode Transmit/Receive possible values. More...
enum | UART3_Parity_TypeDef { UART3_PARITY_NO = (uint8_t)0x00, UART3_PARITY_EVEN = (uint8_t)0x04, UART3_PARITY_ODD = (uint8_t)0x06 }
UART3 parity possible values. More...
enum | UART3_StopBits_TypeDef { UART3_STOPBITS_1 = (uint8_t)0x00, UART3_STOPBITS_2 = (uint8_t)0x20 }
UART3 stop bits possible values. More...
enum | UART3_WakeUp_TypeDef { UART3_WAKEUP_IDLELINE = (uint8_t)0x00, UART3_WAKEUP_ADDRESSMARK = (uint8_t)0x08 }
UART3 WakeUP Modes. More...
enum | UART3_WordLength_TypeDef { UART3_WORDLENGTH_8D = (uint8_t)0x00, UART3_WORDLENGTH_9D = (uint8_t)0x10 }
UART3 Word length possible values. More...

Functions

void | UART3_ClearFlag (UART3_Flag_TypeDef UART3_FLAG)
Clears the UART3 flags.
void | UART3_ClearITPendingBit (UART3_IT_TypeDef UART3_IT)
Clears the UART3 pending flags.
void | UART3_Cmd (FunctionalState NewState)
Enable the UART1 peripheral.
void | UART3_DeInit (void)
Deinitializes the UART peripheral.
FlagStatus | UART3_GetFlagStatus (UART3_Flag_TypeDef UART3_FLAG)
Checks whether the specified UART3 flag is set or not.
ITStatus | UART3_GetITStatus (UART3_IT_TypeDef UART3_IT)
Checks whether the specified UART3 interrupt has occurred or not.
void | UART3_Init (uint32_t BaudRate, UART3_WordLength_TypeDef WordLength, UART3_StopBits_TypeDef StopBits, UART3_Parity_TypeDef Parity, UART3_Mode_TypeDef Mode)
Initializes the UART3 according to the specified parameters.
void | UART3_ITConfig (UART3_IT_TypeDef UART3_IT, FunctionalState NewState)
Enables or disables the specified UART3 interrupts.
void | UART3_LINBreakDetectionConfig (UART3_LINBreakDetectionLength_TypeDef UART3_LINBreakDetectionLength)
Sets the UART3 LIN Break detection length.
void | UART3_LINCmd (FunctionalState NewState)
Enables or disables the UART3 LIN mode.
void | UART3_LINConfig (UART3_LinMode_TypeDef UART3_Mode, UART3_LinAutosync_TypeDef UART3_Autosync, UART3_LinDivUp_TypeDef UART3_DivUp)
Configure the UART3 peripheral.
uint8_t | UART3_ReceiveData8 (void)
Returns the most recent received data by the UART3 peripheral.
uint16_t | UART3_ReceiveData9 (void)
Returns the most recent received data by the UART3 peripheral.
void | UART3_ReceiverWakeUpCmd (FunctionalState NewState)
Determines if the UART3 is in mute mode or not.
void | UART3_SendBreak (void)
Transmits break characters.
void | UART3_SendData8 (uint8_t Data)
Transmits 8 bit data through the UART3 peripheral.
void | UART3_SendData9 (uint16_t Data)
Transmits 9 bit data through the UART3 peripheral.
void | UART3_SetAddress (uint8_t UART3_Address)
Sets the address of the UART3 node.
void | UART3_WakeUpConfig (UART3_WakeUp_TypeDef UART3_WakeUp)
Selects the UART3 WakeUp method.

Detailed Description

This file contains all functions prototypes and macros for the UART3 peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_uart3.h.


STM8S/A Standard Peripherals Drivers: stm8s_uart4.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions
stm8s_uart4.c File Reference

This file contains all the functions for the UART4 peripheral. More...

#include "stm8s_uart4.h"

Go to the source code of this file.

Functions

void | UART4_ClearFlag (UART4_Flag_TypeDef UART4_FLAG)
Clears the UART4 flags.
void | UART4_ClearITPendingBit (UART4_IT_TypeDef UART4_IT)
Clears the UART4 pending flags.
void | UART4_Cmd (FunctionalState NewState)
Enable the UART4 peripheral.
void | UART4_DeInit (void)
Deinitializes the UART peripheral.
FlagStatus | UART4_GetFlagStatus (UART4_Flag_TypeDef UART4_FLAG)
Checks whether the specified UART4 flag is set or not.
ITStatus | UART4_GetITStatus (UART4_IT_TypeDef UART4_IT)
Checks whether the specified UART4 interrupt has occurred or not.
void | UART4_HalfDuplexCmd (FunctionalState NewState)
Enables or disables the UART’s Half Duplex communication.
void | UART4_Init (uint32_t BaudRate, UART4_WordLength_TypeDef WordLength, UART4_StopBits_TypeDef StopBits, UART4_Parity_TypeDef Parity, UART4_SyncMode_TypeDef SyncMode, UART4_Mode_TypeDef Mode)
Initializes the UART4 according to the specified parameters.
void | UART4_IrDACmd (FunctionalState NewState)
Enables or disables the UART4’s IrDA interface.
void | UART4_IrDAConfig (UART4_IrDAMode_TypeDef UART4_IrDAMode)
Configures the UART4’s IrDA interface.
void | UART4_ITConfig (UART4_IT_TypeDef UART4_IT, FunctionalState NewState)
Enables or disables the specified UART4 interrupts.
void | UART4_LINBreakDetectionConfig (UART4_LINBreakDetectionLength_TypeDef UART4_LINBreakDetectionLength)
Sets the UART4 LIN Break detection length.
void | UART4_LINCmd (FunctionalState NewState)
Enables or disables the UART4 LIN mode.
void | UART4_LINConfig (UART4_LinMode_TypeDef UART4_Mode, UART4_LinAutosync_TypeDef UART4_Autosync, UART4_LinDivUp_TypeDef UART4_DivUp)
Configure the UART4 peripheral.
uint8_t | UART4_ReceiveData8 (void)
Returns the most recent received data by the UART4 peripheral.
uint16_t | UART4_ReceiveData9 (void)
Returns the most recent received data by the UART4 peripheral.
void | UART4_ReceiverWakeUpCmd (FunctionalState NewState)
Determines if the UART4 is in mute mode or not.
void | UART4_SendBreak (void)
Transmits break characters.
void | UART4_SendData8 (uint8_t Data)
Transmits 8 bit data through the UART4 peripheral.
void | UART4_SendData9 (uint16_t Data)
Transmits 9 bit data through the UART4 peripheral.
void | UART4_SetAddress (uint8_t UART4_Address)
Sets the address of the UART4 node.
void | UART4_SetGuardTime (uint8_t UART4_GuardTime)
Sets the specified UART4 guard time.
void | UART4_SetPrescaler (uint8_t UART4_Prescaler)
Sets the system clock prescaler.
void | UART4_SmartCardCmd (FunctionalState NewState)
Enables or disables the UART4 Smart Card mode.
void | UART4_SmartCardNACKCmd (FunctionalState NewState)
Enables or disables NACK transmission.
void | UART4_WakeUpConfig (UART4_WakeUp_TypeDef UART4_WakeUp)
Selects the UART4 WakeUp method.

Detailed Description

This file contains all the functions for the UART4 peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_uart4.c.


STM8S/A Standard Peripherals Drivers: stm8s_uart4.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions
stm8s_uart4.h File Reference

This file contains all functions prototypes and macros for the UART4 peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_UART4_ADDRESS_OK(node) ((node) < UART4_ADDRESS_MAX )
#define | IS_UART4_AUTOSYNC_OK(AutosyncMode)
Macro used by the assert_param function in order to check the LIN automatic resynchronization mode.
#define | IS_UART4_BAUDRATE_OK(NUM) ((NUM) <= (uint32_t)625000)
Macro used by the assert_param function in order to check the maximum baudrate value.
#define | IS_UART4_CLEAR_FLAG_OK(Flag)
Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs that can be cleared by writing 0.
#define | IS_UART4_CLEAR_IT_OK(ITPendingBit)
Macro used by the assert function in order to check the different sensitivity values for the pending bit that can be cleared by writing 0.
#define | IS_UART4_CONFIG_IT_OK(Interrupt)
Macro used by the assert_param function in order to check the different sensitivity values for the Interrupts.
#define | IS_UART4_DIVUP_OK(DivupMethod)
Macro used by the assert_param function in order to check the LIN divider update method.
#define | IS_UART4_FLAG_OK(Flag)
Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs.
#define | IS_UART4_GET_IT_OK(ITPendingBit)
Macro used by the assert function in order to check the different sensitivity values for the pending bit.
#define | IS_UART4_IRDAMODE_OK(IrDAMode)
Macro used by the assert_param function in order to check the different sensitivity values for the IrDAModes.
#define | IS_UART4_LINBREAKDETECTIONLENGTH_OK(LINBreakDetectionLength)
Macro used by the assert_param function in order to check the different sensitivity values for the LINBreakDetectionLengths.
#define | IS_UART4_MODE_OK(Mode)
Macro used by the assert function to check the different functions parameters.
#define | IS_UART4_PARITY_OK(Parity)
Macro used by the assert_param function in order to check the different sensitivity values for the Paritys.
#define | IS_UART4_SLAVE_OK(Mode)
Macro used by the assert_param function in order to check the LIN mode.
#define | IS_UART4_STOPBITS_OK(StopBit)
Macro used by the assert_param function in order to check the different sensitivity values for the UART4_StopBits.
#define | IS_UART4_SYNCMODE_OK(SyncMode)
Macro used by the assert_param function in order to check the different sensitivity values for the SyncModes; it should exclude values such as UART4_CLOCK_ENABLE|UART4_CLOCK_DISABLE.
#define | IS_UART4_WAKEUP_OK(WakeUp)
Macro used by the assert_param function in order to check the different sensitivity values for the WakeUps.
#define | IS_UART4_WORDLENGTH_OK(WordLength)
Macro used by the assert_param function in order to check the different sensitivity values for the WordLengths.
#define | UART4_ADDRESS_MAX ((uint8_t)16)
Macro used by the assert_param function in order to check the address of the UART4 or UART node.

Enumerations

enum UART4_Flag_TypeDef {
UART4_FLAG_TXE = (uint16_t)0x0080, UART4_FLAG_TC = (uint16_t)0x0040, UART4_FLAG_RXNE = (uint16_t)0x0020, UART4_FLAG_IDLE = (uint16_t)0x0010,
UART4_FLAG_OR_LHE = (uint16_t)0x0008, UART4_FLAG_NF = (uint16_t)0x0004, UART4_FLAG_FE = (uint16_t)0x0002, UART4_FLAG_PE = (uint16_t)0x0001,
UART4_FLAG_SBK = (uint16_t)0x0101, UART4_FLAG_LBDF = (uint16_t)0x0210, UART4_FLAG_LHDF = (uint16_t)0x0302, UART4_FLAG_LSF = (uint16_t)0x0301
}
UART4 Flag possible values. More...
enum | UART4_IrDAMode_TypeDef { UART4_IRDAMODE_NORMAL = (uint8_t)0x00, UART4_IRDAMODE_LOWPOWER = (uint8_t)0x01 }
UART4 Irda Modes. More...
enum UART4_IT_TypeDef {
UART4_IT_TXE = (uint16_t)0x0277, UART4_IT_TC = (uint16_t)0x0266, UART4_IT_RXNE = (uint16_t)0x0255, UART4_IT_IDLE = (uint16_t)0x0244,
UART4_IT_OR = (uint16_t)0x0235, UART4_IT_PE = (uint16_t)0x0100, UART4_IT_LBDF = (uint16_t)0x0346, UART4_IT_LHDF = (uint16_t)0x0412,
UART4_IT_RXNE_OR = (uint16_t)0x0205
}
UART4 Interrupt definition UART4_IT possible values Elements values convention: 0xZYX X: Position of the corresponding Interrupt. More...
enum | UART4_LinAutosync_TypeDef { UART4_LIN_AUTOSYNC_DISABLE = (uint8_t)0x00, UART4_LIN_AUTOSYNC_ENABLE = (uint8_t)0x01 }
UART4 automatic resynchronisation possible values. More...
enum | UART4_LINBreakDetectionLength_TypeDef { UART4_LINBREAKDETECTIONLENGTH_10BITS = (uint8_t)0x00, UART4_LINBREAKDETECTIONLENGTH_11BITS = (uint8_t)0x01 }
UART4 LIN Break detection length possible values. More...
enum | UART4_LinDivUp_TypeDef { UART4_LIN_DIVUP_LBRR1 = (uint8_t)0x00, UART4_LIN_DIVUP_NEXTRXNE = (uint8_t)0x01 }
UART4 Divider Update Method possible values. More...
enum | UART4_LinMode_TypeDef { UART4_LIN_MODE_MASTER = (uint8_t)0x00, UART4_LIN_MODE_SLAVE = (uint8_t)0x01 }
UART4 Mode possible values. More...
enum UART4_Mode_TypeDef {
UART4_MODE_RX_ENABLE = (uint8_t)0x08, UART4_MODE_TX_ENABLE = (uint8_t)0x04, UART4_MODE_TX_DISABLE = (uint8_t)0x80, UART4_MODE_RX_DISABLE = (uint8_t)0x40,
UART4_MODE_TXRX_ENABLE = (uint8_t)0x0C
}
UART4 Mode possible values. More...
enum | UART4_Parity_TypeDef { UART4_PARITY_NO = (uint8_t)0x00, UART4_PARITY_EVEN = (uint8_t)0x04, UART4_PARITY_ODD = (uint8_t)0x06 }
UART4 parity possible values. More...
enum | UART4_StopBits_TypeDef { UART4_STOPBITS_1 = (uint8_t)0x00, UART4_STOPBITS_0_5 = (uint8_t)0x10, UART4_STOPBITS_2 = (uint8_t)0x20, UART4_STOPBITS_1_5 = (uint8_t)0x30 }
UART4 stop bits possible values. More...
enum UART4_SyncMode_TypeDef {
UART4_SYNCMODE_CLOCK_DISABLE = (uint8_t)0x80, UART4_SYNCMODE_CLOCK_ENABLE = (uint8_t)0x08, UART4_SYNCMODE_CPOL_LOW = (uint8_t)0x40, UART4_SYNCMODE_CPOL_HIGH = (uint8_t)0x04,
UART4_SYNCMODE_CPHA_MIDDLE = (uint8_t)0x20, UART4_SYNCMODE_CPHA_BEGINING = (uint8_t)0x02, UART4_SYNCMODE_LASTBIT_DISABLE = (uint8_t)0x10, UART4_SYNCMODE_LASTBIT_ENABLE = (uint8_t)0x01
}
UART4 Synchrone modes. More...
enum | UART4_WakeUp_TypeDef { UART4_WAKEUP_IDLELINE = (uint8_t)0x00, UART4_WAKEUP_ADDRESSMARK = (uint8_t)0x08 }
UART4 WakeUP Modes. More...
enum | UART4_WordLength_TypeDef { UART4_WORDLENGTH_8D = (uint8_t)0x00, UART4_WORDLENGTH_9D = (uint8_t)0x10 }
UART4 Word length possible values. More...

Functions

void | UART4_ClearFlag (UART4_Flag_TypeDef UART4_FLAG)
Clears the UART4 flags.
void | UART4_ClearITPendingBit (UART4_IT_TypeDef UART4_IT)
Clears the UART4 pending flags.
void | UART4_Cmd (FunctionalState NewState)
Enable the UART4 peripheral.
void | UART4_DeInit (void)
Deinitializes the UART peripheral.
FlagStatus | UART4_GetFlagStatus (UART4_Flag_TypeDef UART4_FLAG)
Checks whether the specified UART4 flag is set or not.
ITStatus | UART4_GetITStatus (UART4_IT_TypeDef UART4_IT)
Checks whether the specified UART4 interrupt has occurred or not.
void | UART4_HalfDuplexCmd (FunctionalState NewState)
Enables or disables the UART’s Half Duplex communication.
void | UART4_Init (uint32_t BaudRate, UART4_WordLength_TypeDef WordLength, UART4_StopBits_TypeDef StopBits, UART4_Parity_TypeDef Parity, UART4_SyncMode_TypeDef SyncMode, UART4_Mode_TypeDef Mode)
Initializes the UART4 according to the specified parameters.
void | UART4_IrDACmd (FunctionalState NewState)
Enables or disables the UART4’s IrDA interface.
void | UART4_IrDAConfig (UART4_IrDAMode_TypeDef UART4_IrDAMode)
Configures the UART4’s IrDA interface.
void | UART4_ITConfig (UART4_IT_TypeDef UART4_IT, FunctionalState NewState)
Enables or disables the specified UART4 interrupts.
void | UART4_LINBreakDetectionConfig (UART4_LINBreakDetectionLength_TypeDef UART4_LINBreakDetectionLength)
Sets the UART4 LIN Break detection length.
void | UART4_LINCmd (FunctionalState NewState)
Enables or disables the UART4 LIN mode.
void | UART4_LINConfig (UART4_LinMode_TypeDef UART4_Mode, UART4_LinAutosync_TypeDef UART4_Autosync, UART4_LinDivUp_TypeDef UART4_DivUp)
Configure the UART4 peripheral.
uint8_t | UART4_ReceiveData8 (void)
Returns the most recent received data by the UART4 peripheral.
uint16_t | UART4_ReceiveData9 (void)
Returns the most recent received data by the UART4 peripheral.
void | UART4_ReceiverWakeUpCmd (FunctionalState NewState)
Determines if the UART4 is in mute mode or not.
void | UART4_SendBreak (void)
Transmits break characters.
void | UART4_SendData8 (uint8_t Data)
Transmits 8 bit data through the UART4 peripheral.
void | UART4_SendData9 (uint16_t Data)
Transmits 9 bit data through the UART4 peripheral.
void | UART4_SetAddress (uint8_t UART4_Address)
Sets the address of the UART4 node.
void | UART4_SetGuardTime (uint8_t UART4_GuardTime)
Sets the specified UART4 guard time.
void | UART4_SetPrescaler (uint8_t UART4_Prescaler)
Sets the system clock prescaler.
void | UART4_SmartCardCmd (FunctionalState NewState)
Enables or disables the UART4 Smart Card mode.
void | UART4_SmartCardNACKCmd (FunctionalState NewState)
Enables or disables NACK transmission.
void | UART4_WakeUpConfig (UART4_WakeUp_TypeDef UART4_WakeUp)
Selects the UART4 WakeUp method.

Detailed Description

This file contains all functions prototypes and macros for the UART4 peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_uart4.h.


STM8S/A Standard Peripherals Drivers: stm8s_wwdg.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Defines | Functions
stm8s_wwdg.c File Reference

This file contains all the functions for the WWDG peripheral. More...

#include "stm8s_wwdg.h"

Go to the source code of this file.

Defines

#define | BIT_MASK ((uint8_t)0x7F)

Functions

uint8_t | WWDG_GetCounter (void)
Gets the WWDG Counter Value.
void | WWDG_Init (uint8_t Counter, uint8_t WindowValue)
Initializes the WWDG peripheral.
void | WWDG_SetCounter (uint8_t Counter)
Refreshes the WWDG peripheral.
void | WWDG_SetWindowValue (uint8_t WindowValue)
Sets the WWDG window value.
void | WWDG_SWReset (void)
Generates immediate WWDG RESET.

Detailed Description

This file contains all the functions for the WWDG peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_wwdg.c.


STM8S/A Standard Peripherals Drivers: stm8s_wwdg.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Functions
stm8s_wwdg.h File Reference

This file contains all functions prototype and macros for the WWDG peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_WWDG_COUNTERVALUE_OK(CounterValue) ((CounterValue) <= 0x7F)
Macro used by the assert function in order to check the different values of the counter register.
#define | IS_WWDG_WINDOWLIMITVALUE_OK(WindowLimitValue) ((WindowLimitValue) <= 0x7F)
Macro used by the assert function in order to check the values of the window register.

Functions

uint8_t | WWDG_GetCounter (void)
Gets the WWDG Counter Value.
void | WWDG_Init (uint8_t Counter, uint8_t WindowValue)
Initializes the WWDG peripheral.
void | WWDG_SetCounter (uint8_t Counter)
Refreshes the WWDG peripheral.
void | WWDG_SetWindowValue (uint8_t WindowValue)
Sets the WWDG window value.
void | WWDG_SWReset (void)
Generates immediate WWDG RESET.

Detailed Description

This file contains all functions prototype and macros for the WWDG peripheral.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s_wwdg.h.


STM8S/A Standard Peripherals Drivers: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- _ -

  • __I : stm8s.h
  • __IO : stm8s.h
  • __O : stm8s.h
  • __STM8S_STDPERIPH_VERSION : stm8s.h
  • __STM8S_STDPERIPH_VERSION_MAIN : stm8s.h
  • __STM8S_STDPERIPH_VERSION_RC : stm8s.h
  • __STM8S_STDPERIPH_VERSION_SUB1 : stm8s.h
  • __STM8S_STDPERIPH_VERSION_SUB2 : stm8s.h
  • _Data : stm8s_can.c
  • _DLC : stm8s_can.c
  • _FMI : stm8s_can.c
  • _Id : stm8s_can.c
  • _IDE : stm8s_can.c
  • _RTR : stm8s_can.c


STM8S/A Standard Peripherals Drivers: Data Structures

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Structures
Here are the data structures with brief descriptions:
AWU_struct | Auto Wake Up (AWU) peripheral registers
BEEP_struct | Beeper (BEEP) peripheral registers
CAN_TypeDef | Controller Area Network (CAN)
CFG_struct | Configuration Registers (CFG)
CLK_struct | Clock Controller (CLK)
EXTI_struct | External Interrupt Controller (EXTI)
FLASH_struct | FLASH program and Data memory (FLASH)
GPIO_struct | General Purpose I/Os (GPIO)
I2C_struct | Inter-Integrated Circuit (I2C)
ITC_struct | Interrupt Controller (ITC)
IWDG_struct | Independent Watchdog (IWDG)
OPT_struct | Option Bytes (OPT)
RST_struct | Reset Controller (RST)
SPI_struct | Serial Peripheral Interface (SPI)
TIM1_struct | 16-bit timer with complementary PWM outputs (TIM1)
TIM2_struct | 16-bit timer (TIM2)
TIM3_struct | 16-bit timer (TIM3)
TIM4_struct | 8-bit system timer (TIM4)
TIM5_struct | 16-bit timer with synchro module (TIM5)
TIM6_struct | 8-bit system timer with synchro module(TIM6)
UART1_struct | Universal Synchronous Asynchronous Receiver Transmitter (UART1)
UART2_struct | Universal Synchronous Asynchronous Receiver Transmitter (UART2)
UART3_struct | LIN Universal Asynchronous Receiver Transmitter (UART3)
WWDG_struct | Window Watchdog (WWDG)


STM8S/A Standard Peripherals Drivers: Data Structure Index

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Structure Index
A | B | C | E | F | G | I | O | R | S | T | U | W
A
C
CLK_struct
F
I
IWDG_struct
R
T
TIM3_struct
U
UART3_struct
E
O
TIM4_struct
W
AWU_struct CAN_TypeDef FLASH_struct I2C_struct RST_struct TIM1_struct TIM5_struct UART1_struct
B
CFG_struct EXTI_struct
G
ITC_struct OPT_struct
S
TIM2_struct TIM6_struct UART2_struct WWDG_struct


STM8S/A Standard Peripherals Drivers: C:/STM8S_Release/STM8S_StdPeriph_Driver/inc/ Directory Reference

  • STM8S_StdPeriph_Driver
  • inc
inc Directory Reference

Files

file | stm8s.h [code]

This file contains all HW registers definitions and memory mapping.

file | stm8s_adc1.h [code]

This file contains all the prototypes/macros for the ADC1 peripheral.

file | stm8s_adc2.h [code]

This file contains all the prototypes/macros for the ADC2 peripheral.

file | stm8s_awu.h [code]

This file contains all functions prototype and macros for the AWU peripheral.

file | stm8s_beep.h [code]

This file contains all functions prototype and macros for the BEEP peripheral.

file | stm8s_can.h [code]

This file contains all the functions for the CAN peripheral.

file | stm8s_clk.h [code]

This file contains all functions prototype and macros for the CLK peripheral.

file | stm8s_exti.h [code]

This file contains all functions prototype and macros for the EXTI peripheral.

file | stm8s_flash.h [code]

This file contains all functions prototype and macros for the FLASH peripheral.

file | stm8s_gpio.h [code]

This file contains all functions prototype and macros for the GPIO peripheral.

file | stm8s_i2c.h [code]

This file contains all functions prototype and macros for the I2C peripheral.

file | stm8s_itc.h [code]

This file contains all functions prototype and macros for the ITC peripheral.

file | stm8s_iwdg.h [code]

This file contains all functions prototypes and macros for the IWDG peripheral.

file | stm8s_rst.h [code]

This file contains all functions prototype and macros for the RST peripheral.

file | stm8s_spi.h [code]

This file contains all functions prototype and macros for the SPI peripheral.

file | stm8s_tim1.h [code]

This file contains all functions prototype and macros for the TIM1 peripheral.

file | stm8s_tim2.h [code]

This file contains all functions prototype and macros for the TIM2 peripheral.

file | stm8s_tim3.h [code]

This file contains all functions prototype and macros for the TIM3 peripheral.

file | stm8s_tim4.h [code]

This file contains all functions prototype and macros for the TIM4 peripheral.

file | stm8s_tim5.h [code]

This file contains all functions prototype and macros for the TIM5 peripheral.

file | stm8s_tim6.h [code]

This file contains all functions prototype and macros for the TIM6 peripheral.

file | stm8s_uart1.h [code]

This file contains all functions prototypes and macros for the UART1 peripheral.

file | stm8s_uart2.h [code]

This file contains all functions prototypes and macros for the UART2 peripheral.

file | stm8s_uart3.h [code]

This file contains all functions prototypes and macros for the UART3 peripheral.

file | stm8s_uart4.h [code]

This file contains all functions prototypes and macros for the UART4 peripheral.

file | stm8s_wwdg.h [code]

This file contains all functions prototype and macros for the WWDG peripheral.


STM8S/A Standard Peripherals Drivers: C:/STM8S_Release/STM8S_StdPeriph_Driver/ Directory Reference

  • STM8S_StdPeriph_Driver
STM8S_StdPeriph_Driver Directory Reference

Directories

directory | inc
directory | src


STM8S/A Standard Peripherals Drivers: C:/STM8S_Release/STM8S_StdPeriph_Driver/src/ Directory Reference

  • STM8S_StdPeriph_Driver
  • src
src Directory Reference

Files

file | stm8s_adc1.c [code]

This file contains all the functions/macros for the ADC1 peripheral.

file | stm8s_adc2.c [code]

This file contains all the functions/macros for the ADC2 peripheral.

file | stm8s_awu.c [code]

This file contains all the functions for the AWU peripheral.

file | stm8s_beep.c [code]

This file contains all the functions for the BEEP peripheral.

file | stm8s_can.c [code]

This file contains all the functions for the CAN peripheral.

file | stm8s_clk.c [code]

This file contains all the functions for the CLK peripheral.

file | stm8s_exti.c [code]

This file contains all the functions for the EXTI peripheral.

file | stm8s_flash.c [code]

This file contains all the functions for the FLASH peripheral.

file | stm8s_gpio.c [code]

This file contains all the functions for the GPIO peripheral.

file | stm8s_i2c.c [code]

This file contains all the functions for the I2C peripheral.

file | stm8s_itc.c [code]

This file contains all the functions for the ITC peripheral.

file | stm8s_iwdg.c [code]

This file contains all the functions for the IWDG peripheral.

file | stm8s_rst.c [code]

This file contains all the functions for the RST peripheral.

file | stm8s_spi.c [code]

This file contains all the functions for the SPI peripheral.

file | stm8s_tim1.c [code]

This file contains all the functions for the TIM1 peripheral.

file | stm8s_tim2.c [code]

This file contains all the functions for the TIM2 peripheral.

file | stm8s_tim3.c [code]

This file contains all the functions for the TIM3 peripheral.

file | stm8s_tim4.c [code]

This file contains all the functions for the TIM4 peripheral.

file | stm8s_tim5.c [code]

This file contains all the functions for the TIM5 peripheral.

file | stm8s_tim6.c [code]

This file contains all the functions for the TIM6 peripheral.

file | stm8s_uart1.c [code]

This file contains all the functions for the UART1 peripheral.

file | stm8s_uart2.c [code]

This file contains all the functions for the UART2 peripheral.

file | stm8s_uart3.c [code]

This file contains all the functions for the uart3 peripheral.

file | stm8s_uart4.c [code]

This file contains all the functions for the UART4 peripheral.

file | stm8s_wwdg.c [code]

This file contains all the functions for the WWDG peripheral.


STM8S/A Standard Peripherals Drivers: Directories

Directories
This directory hierarchy is sorted roughly, but not completely, alphabetically:
  • STM8S_StdPeriph_Driver
    • inc
    • src


STM8S/A Standard Peripherals Drivers: File List

  • File List
  • Globals
File List
Here is a list of all files with brief descriptions:
stm8s.h [code] | This file contains all HW registers definitions and memory mapping
stm8s_adc1.c [code] | This file contains all the functions/macros for the ADC1 peripheral
stm8s_adc1.h [code] | This file contains all the prototypes/macros for the ADC1 peripheral
stm8s_adc2.c [code] | This file contains all the functions/macros for the ADC2 peripheral
stm8s_adc2.h [code] | This file contains all the prototypes/macros for the ADC2 peripheral
stm8s_awu.c [code] | This file contains all the functions for the AWU peripheral
stm8s_awu.h [code] | This file contains all functions prototype and macros for the AWU peripheral
stm8s_beep.c [code] | This file contains all the functions for the BEEP peripheral
stm8s_beep.h [code] | This file contains all functions prototype and macros for the BEEP peripheral
stm8s_can.c [code] | This file contains all the functions for the CAN peripheral
stm8s_can.h [code] | This file contains all the functions for the CAN peripheral
stm8s_clk.c [code] | This file contains all the functions for the CLK peripheral
stm8s_clk.h [code] | This file contains all functions prototype and macros for the CLK peripheral
stm8s_exti.c [code] | This file contains all the functions for the EXTI peripheral
stm8s_exti.h [code] | This file contains all functions prototype and macros for the EXTI peripheral
stm8s_flash.c [code] | This file contains all the functions for the FLASH peripheral
stm8s_flash.h [code] | This file contains all functions prototype and macros for the FLASH peripheral
stm8s_gpio.c [code] | This file contains all the functions for the GPIO peripheral
stm8s_gpio.h [code] | This file contains all functions prototype and macros for the GPIO peripheral
stm8s_i2c.c [code] | This file contains all the functions for the I2C peripheral
stm8s_i2c.h [code] | This file contains all functions prototype and macros for the I2C peripheral
stm8s_itc.c [code] | This file contains all the functions for the ITC peripheral
stm8s_itc.h [code] | This file contains all functions prototype and macros for the ITC peripheral
stm8s_iwdg.c [code] | This file contains all the functions for the IWDG peripheral
stm8s_iwdg.h [code] | This file contains all functions prototypes and macros for the IWDG peripheral
stm8s_rst.c [code] | This file contains all the functions for the RST peripheral
stm8s_rst.h [code] | This file contains all functions prototype and macros for the RST peripheral
stm8s_spi.c [code] | This file contains all the functions for the SPI peripheral
stm8s_spi.h [code] | This file contains all functions prototype and macros for the SPI peripheral
stm8s_tim1.c [code] | This file contains all the functions for the TIM1 peripheral
stm8s_tim1.h [code] | This file contains all functions prototype and macros for the TIM1 peripheral
stm8s_tim2.c [code] | This file contains all the functions for the TIM2 peripheral
stm8s_tim2.h [code] | This file contains all functions prototype and macros for the TIM2 peripheral
stm8s_tim3.c [code] | This file contains all the functions for the TIM3 peripheral
stm8s_tim3.h [code] | This file contains all functions prototype and macros for the TIM3 peripheral
stm8s_tim4.c [code] | This file contains all the functions for the TIM4 peripheral
stm8s_tim4.h [code] | This file contains all functions prototype and macros for the TIM4 peripheral
stm8s_tim5.c [code] | This file contains all the functions for the TIM5 peripheral
stm8s_tim5.h [code] | This file contains all functions prototype and macros for the TIM5 peripheral
stm8s_tim6.c [code] | This file contains all the functions for the TIM6 peripheral
stm8s_tim6.h [code] | This file contains all functions prototype and macros for the TIM6 peripheral
stm8s_uart1.c [code] | This file contains all the functions for the UART1 peripheral
stm8s_uart1.h [code] | This file contains all functions prototypes and macros for the UART1 peripheral
stm8s_uart2.c [code] | This file contains all the functions for the UART2 peripheral
stm8s_uart2.h [code] | This file contains all functions prototypes and macros for the UART2 peripheral
stm8s_uart3.c [code] | This file contains all the functions for the uart3 peripheral
stm8s_uart3.h [code] | This file contains all functions prototypes and macros for the UART3 peripheral
stm8s_uart4.c [code] | This file contains all the functions for the UART4 peripheral
stm8s_uart4.h [code] | This file contains all functions prototypes and macros for the UART4 peripheral
stm8s_wwdg.c [code] | This file contains all the functions for the WWDG peripheral
stm8s_wwdg.h [code] | This file contains all functions prototype and macros for the WWDG peripheral


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • k
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • w
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- k -

  • KR : IWDG_struct


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • k
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • w
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- m -

  • MCR : CAN_TypeDef
  • MCSR : CAN_TypeDef
  • MDAR1 : CAN_TypeDef
  • MDAR2 : CAN_TypeDef
  • MDAR3 : CAN_TypeDef
  • MDAR4 : CAN_TypeDef
  • MDAR5 : CAN_TypeDef
  • MDAR6 : CAN_TypeDef
  • MDAR7 : CAN_TypeDef
  • MDAR8 : CAN_TypeDef
  • MDLCR : CAN_TypeDef
  • MFMI : CAN_TypeDef
  • MIDR1 : CAN_TypeDef
  • MIDR2 : CAN_TypeDef
  • MIDR3 : CAN_TypeDef
  • MIDR4 : CAN_TypeDef
  • MSR : CAN_TypeDef
  • MTSRH : CAN_TypeDef
  • MTSRL : CAN_TypeDef


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • k
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • w
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- n -

  • NCR2 : FLASH_struct
  • NFPR : FLASH_struct
  • NOPT1 : OPT_struct
  • NOPT2 : OPT_struct
  • NOPT3 : OPT_struct
  • NOPT4 : OPT_struct
  • NOPT5 : OPT_struct
  • NOPT7 : OPT_struct


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • k
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • w
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- o -

  • OARH : I2C_struct
  • OARL : I2C_struct
  • ODR : GPIO_struct
  • OISR : TIM1_struct
  • OPT0 : OPT_struct
  • OPT1 : OPT_struct
  • OPT2 : OPT_struct
  • OPT3 : OPT_struct
  • OPT4 : OPT_struct
  • OPT5 : OPT_struct
  • OPT7 : OPT_struct


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • k
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • w
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- b -

  • BKR : TIM1_struct
  • BRR1 : UART1_struct , UART3_struct , UART2_struct
  • BRR2 : UART2_struct , UART1_struct , UART3_struct
  • BTR1 : CAN_TypeDef
  • BTR2 : CAN_TypeDef


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • k
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • w
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- c -

  • CCER1 : TIM1_struct , TIM2_struct , TIM5_struct , TIM3_struct
  • CCER2 : TIM1_struct , TIM2_struct , TIM5_struct
  • CCMR1 : TIM1_struct , TIM2_struct , TIM3_struct , TIM5_struct
  • CCMR2 : TIM1_struct , TIM2_struct , TIM3_struct , TIM5_struct
  • CCMR3 : TIM1_struct , TIM2_struct , TIM5_struct
  • CCMR4 : TIM1_struct
  • CCOR : CLK_struct
  • CCR1H : TIM1_struct , TIM2_struct , TIM3_struct , TIM5_struct
  • CCR1L : TIM1_struct , TIM2_struct , TIM3_struct , TIM5_struct
  • CCR2H : TIM5_struct , TIM1_struct , TIM2_struct , TIM3_struct
  • CCR2L : TIM1_struct , TIM2_struct , TIM3_struct , TIM5_struct
  • CCR3H : TIM1_struct , TIM2_struct , TIM5_struct
  • CCR3L : TIM1_struct , TIM2_struct , TIM5_struct
  • CCR4H : TIM1_struct
  • CCR4L : TIM1_struct
  • CCRH : I2C_struct
  • CCRL : I2C_struct
  • CKDIVR : CLK_struct
  • CMSR : CLK_struct
  • CNTR : TIM4_struct , TIM6_struct
  • CNTRH : TIM1_struct , TIM2_struct , TIM3_struct , TIM5_struct
  • CNTRL : TIM1_struct , TIM2_struct , TIM3_struct , TIM5_struct
  • Config : CAN_TypeDef
  • CR : WWDG_struct
  • CR1 : TIM2_struct , TIM3_struct , TIM4_struct , UART3_struct , TIM5_struct , I2C_struct , EXTI_struct , FLASH_struct , TIM6_struct , UART1_struct , GPIO_struct , TIM1_struct , SPI_struct , UART2_struct
  • CR2 : EXTI_struct , UART1_struct , UART3_struct , FLASH_struct , I2C_struct , UART2_struct , TIM5_struct , GPIO_struct , TIM1_struct , TIM6_struct , SPI_struct
  • CR3 : UART2_struct , UART3_struct , UART1_struct
  • CR4 : UART2_struct , UART3_struct , UART1_struct
  • CR5 : UART2_struct , UART1_struct
  • CR6 : UART3_struct , UART2_struct
  • CRCPR : SPI_struct
  • CSR : AWU_struct , BEEP_struct
  • CSSR : CLK_struct


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • k
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • w
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- d -

  • DDR : GPIO_struct
  • DGR : CAN_TypeDef
  • DR : SPI_struct , UART3_struct , UART2_struct , UART1_struct , I2C_struct
  • DTR : TIM1_struct
  • DUKR : FLASH_struct


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • k
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • w
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- e -

  • ECKR : CLK_struct
  • EGR : TIM1_struct , TIM3_struct , TIM4_struct , TIM6_struct , TIM5_struct , TIM2_struct
  • EIER : CAN_TypeDef
  • ESR : CAN_TypeDef
  • ETR : TIM1_struct


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • k
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • w
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- f -

  • F0R1 : CAN_TypeDef
  • F0R2 : CAN_TypeDef
  • F0R3 : CAN_TypeDef
  • F0R4 : CAN_TypeDef
  • F0R5 : CAN_TypeDef
  • F0R6 : CAN_TypeDef
  • F0R7 : CAN_TypeDef
  • F0R8 : CAN_TypeDef
  • F1R1 : CAN_TypeDef
  • F1R2 : CAN_TypeDef
  • F1R3 : CAN_TypeDef
  • F1R4 : CAN_TypeDef
  • F1R5 : CAN_TypeDef
  • F1R6 : CAN_TypeDef
  • F1R7 : CAN_TypeDef
  • F1R8 : CAN_TypeDef
  • F2R1 : CAN_TypeDef
  • F2R2 : CAN_TypeDef
  • F2R3 : CAN_TypeDef
  • F2R4 : CAN_TypeDef
  • F2R5 : CAN_TypeDef
  • F2R6 : CAN_TypeDef
  • F2R7 : CAN_TypeDef
  • F2R8 : CAN_TypeDef
  • F3R1 : CAN_TypeDef
  • F3R2 : CAN_TypeDef
  • F3R3 : CAN_TypeDef
  • F3R4 : CAN_TypeDef
  • F3R5 : CAN_TypeDef
  • F3R6 : CAN_TypeDef
  • F3R7 : CAN_TypeDef
  • F3R8 : CAN_TypeDef
  • F4R1 : CAN_TypeDef
  • F4R2 : CAN_TypeDef
  • F4R3 : CAN_TypeDef
  • F4R4 : CAN_TypeDef
  • F4R5 : CAN_TypeDef
  • F4R6 : CAN_TypeDef
  • F4R7 : CAN_TypeDef
  • F4R8 : CAN_TypeDef
  • F5R1 : CAN_TypeDef
  • F5R2 : CAN_TypeDef
  • F5R3 : CAN_TypeDef
  • F5R4 : CAN_TypeDef
  • F5R5 : CAN_TypeDef
  • F5R6 : CAN_TypeDef
  • F5R7 : CAN_TypeDef
  • F5R8 : CAN_TypeDef
  • FCR1 : CAN_TypeDef
  • FCR2 : CAN_TypeDef
  • FCR3 : CAN_TypeDef
  • Filter : CAN_TypeDef
  • Filter01 : CAN_TypeDef
  • Filter23 : CAN_TypeDef
  • Filter45 : CAN_TypeDef
  • FMR1 : CAN_TypeDef
  • FMR2 : CAN_TypeDef
  • FPR : FLASH_struct
  • FR01 : CAN_TypeDef
  • FR02 : CAN_TypeDef
  • FR03 : CAN_TypeDef
  • FR04 : CAN_TypeDef
  • FR05 : CAN_TypeDef
  • FR06 : CAN_TypeDef
  • FR07 : CAN_TypeDef
  • FR08 : CAN_TypeDef
  • FR09 : CAN_TypeDef
  • FR10 : CAN_TypeDef
  • FR11 : CAN_TypeDef
  • FR12 : CAN_TypeDef
  • FR13 : CAN_TypeDef
  • FR14 : CAN_TypeDef
  • FR15 : CAN_TypeDef
  • FR16 : CAN_TypeDef
  • FREQR : I2C_struct


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
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  • Variables
  • a
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- g -

  • GCR : CFG_struct
  • GTR : UART2_struct , UART1_struct


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- h -

  • HSITRIMR : CLK_struct


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
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  • Variables
  • a
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- i -

  • IAPSR : FLASH_struct
  • ICKR : CLK_struct
  • ICR : SPI_struct
  • IDR : GPIO_struct
  • IER : TIM4_struct , TIM5_struct , TIM1_struct , TIM6_struct , CAN_TypeDef , TIM2_struct , TIM3_struct
  • ISPR1 : ITC_struct
  • ISPR2 : ITC_struct
  • ISPR3 : ITC_struct
  • ISPR4 : ITC_struct
  • ISPR5 : ITC_struct
  • ISPR6 : ITC_struct
  • ISPR7 : ITC_struct
  • ISPR8 : ITC_struct
  • ITR : I2C_struct


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- p -

  • Page : CAN_TypeDef
  • PCKENR1 : CLK_struct
  • PCKENR2 : CLK_struct
  • PR : IWDG_struct
  • PSCR : TIM5_struct , UART2_struct , UART1_struct , TIM6_struct , TIM2_struct , TIM4_struct , TIM3_struct
  • PSCRH : TIM1_struct
  • PSCRL : TIM1_struct
  • PSR : CAN_TypeDef
  • PUKR : FLASH_struct


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- r -

  • RCR : TIM1_struct
  • RECR : CAN_TypeDef
  • RESERVED : UART3_struct , CLK_struct
  • RESERVED1 : OPT_struct
  • Reserved1 : CAN_TypeDef
  • RESERVED1 : CLK_struct , I2C_struct , FLASH_struct
  • RESERVED2 : OPT_struct
  • Reserved2 : CAN_TypeDef
  • RESERVED2 : I2C_struct , FLASH_struct
  • RESERVED3 : FLASH_struct
  • RFR : CAN_TypeDef
  • RLR : IWDG_struct
  • RXCRCR : SPI_struct
  • RxFIFO : CAN_TypeDef


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
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  • w
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- s -

  • SMCR : TIM1_struct , TIM5_struct , TIM6_struct
  • SR : RST_struct , UART3_struct , SPI_struct , UART1_struct , UART2_struct
  • SR1 : TIM1_struct , TIM2_struct , I2C_struct , TIM3_struct , TIM4_struct , TIM5_struct , TIM6_struct
  • SR2 : TIM5_struct , TIM3_struct , TIM1_struct , TIM2_struct , I2C_struct
  • SR3 : I2C_struct
  • SWCR : CLK_struct
  • SWIMCCR : CLK_struct
  • SWR : CLK_struct


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
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  • a
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  • r
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  • t
  • w
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- t -

  • TBR : AWU_struct
  • TECR : CAN_TypeDef
  • TPR : CAN_TypeDef
  • TRISER : I2C_struct
  • TSR : CAN_TypeDef
  • TXCRCR : SPI_struct
  • TxMailbox : CAN_TypeDef


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
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  • Variables
  • a
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  • d
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  • w
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- w -

  • WR : WWDG_struct


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
  • Data Structure Index
  • Data Fields
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  • w

- a -

  • APR : AWU_struct
  • ARR : TIM4_struct , TIM6_struct
  • ARRH : TIM1_struct , TIM2_struct , TIM5_struct , TIM3_struct
  • ARRL : TIM2_struct , TIM5_struct , TIM3_struct , TIM1_struct


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
  • Data Structure Index
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- k -

  • KR : IWDG_struct


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
  • Data Structure Index
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- m -

  • MCR : CAN_TypeDef
  • MCSR : CAN_TypeDef
  • MDAR1 : CAN_TypeDef
  • MDAR2 : CAN_TypeDef
  • MDAR3 : CAN_TypeDef
  • MDAR4 : CAN_TypeDef
  • MDAR5 : CAN_TypeDef
  • MDAR6 : CAN_TypeDef
  • MDAR7 : CAN_TypeDef
  • MDAR8 : CAN_TypeDef
  • MDLCR : CAN_TypeDef
  • MFMI : CAN_TypeDef
  • MIDR1 : CAN_TypeDef
  • MIDR2 : CAN_TypeDef
  • MIDR3 : CAN_TypeDef
  • MIDR4 : CAN_TypeDef
  • MSR : CAN_TypeDef
  • MTSRH : CAN_TypeDef
  • MTSRL : CAN_TypeDef


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
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- n -

  • NCR2 : FLASH_struct
  • NFPR : FLASH_struct
  • NOPT1 : OPT_struct
  • NOPT2 : OPT_struct
  • NOPT3 : OPT_struct
  • NOPT4 : OPT_struct
  • NOPT5 : OPT_struct
  • NOPT7 : OPT_struct


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
  • Data Structure Index
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- o -

  • OARH : I2C_struct
  • OARL : I2C_struct
  • ODR : GPIO_struct
  • OISR : TIM1_struct
  • OPT0 : OPT_struct
  • OPT1 : OPT_struct
  • OPT2 : OPT_struct
  • OPT3 : OPT_struct
  • OPT4 : OPT_struct
  • OPT5 : OPT_struct
  • OPT7 : OPT_struct


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
  • Data Structure Index
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  • w

- b -

  • BKR : TIM1_struct
  • BRR1 : UART1_struct , UART3_struct , UART2_struct
  • BRR2 : UART2_struct , UART1_struct , UART3_struct
  • BTR1 : CAN_TypeDef
  • BTR2 : CAN_TypeDef


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
  • Data Structure Index
  • Data Fields
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- c -

  • CCER1 : TIM1_struct , TIM2_struct , TIM5_struct , TIM3_struct
  • CCER2 : TIM1_struct , TIM2_struct , TIM5_struct
  • CCMR1 : TIM1_struct , TIM2_struct , TIM3_struct , TIM5_struct
  • CCMR2 : TIM1_struct , TIM2_struct , TIM3_struct , TIM5_struct
  • CCMR3 : TIM1_struct , TIM2_struct , TIM5_struct
  • CCMR4 : TIM1_struct
  • CCOR : CLK_struct
  • CCR1H : TIM1_struct , TIM2_struct , TIM3_struct , TIM5_struct
  • CCR1L : TIM1_struct , TIM2_struct , TIM3_struct , TIM5_struct
  • CCR2H : TIM5_struct , TIM1_struct , TIM2_struct , TIM3_struct
  • CCR2L : TIM1_struct , TIM2_struct , TIM3_struct , TIM5_struct
  • CCR3H : TIM1_struct , TIM2_struct , TIM5_struct
  • CCR3L : TIM1_struct , TIM2_struct , TIM5_struct
  • CCR4H : TIM1_struct
  • CCR4L : TIM1_struct
  • CCRH : I2C_struct
  • CCRL : I2C_struct
  • CKDIVR : CLK_struct
  • CMSR : CLK_struct
  • CNTR : TIM4_struct , TIM6_struct
  • CNTRH : TIM1_struct , TIM2_struct , TIM3_struct , TIM5_struct
  • CNTRL : TIM1_struct , TIM2_struct , TIM3_struct , TIM5_struct
  • Config : CAN_TypeDef
  • CR : WWDG_struct
  • CR1 : TIM2_struct , TIM3_struct , TIM4_struct , UART3_struct , TIM5_struct , I2C_struct , EXTI_struct , FLASH_struct , TIM6_struct , UART1_struct , GPIO_struct , TIM1_struct , SPI_struct , UART2_struct
  • CR2 : EXTI_struct , UART1_struct , UART3_struct , FLASH_struct , I2C_struct , UART2_struct , TIM5_struct , GPIO_struct , TIM1_struct , TIM6_struct , SPI_struct
  • CR3 : UART2_struct , UART3_struct , UART1_struct
  • CR4 : UART2_struct , UART3_struct , UART1_struct
  • CR5 : UART2_struct , UART1_struct
  • CR6 : UART3_struct , UART2_struct
  • CRCPR : SPI_struct
  • CSR : AWU_struct , BEEP_struct
  • CSSR : CLK_struct


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
  • Data Structure Index
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  • w

- d -

  • DDR : GPIO_struct
  • DGR : CAN_TypeDef
  • DR : SPI_struct , UART3_struct , UART2_struct , UART1_struct , I2C_struct
  • DTR : TIM1_struct
  • DUKR : FLASH_struct


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
  • Data Structure Index
  • Data Fields
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  • a
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- e -

  • ECKR : CLK_struct
  • EGR : TIM1_struct , TIM3_struct , TIM4_struct , TIM6_struct , TIM5_struct , TIM2_struct
  • EIER : CAN_TypeDef
  • ESR : CAN_TypeDef
  • ETR : TIM1_struct


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
  • Data Structure Index
  • Data Fields
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  • a
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- f -

  • F0R1 : CAN_TypeDef
  • F0R2 : CAN_TypeDef
  • F0R3 : CAN_TypeDef
  • F0R4 : CAN_TypeDef
  • F0R5 : CAN_TypeDef
  • F0R6 : CAN_TypeDef
  • F0R7 : CAN_TypeDef
  • F0R8 : CAN_TypeDef
  • F1R1 : CAN_TypeDef
  • F1R2 : CAN_TypeDef
  • F1R3 : CAN_TypeDef
  • F1R4 : CAN_TypeDef
  • F1R5 : CAN_TypeDef
  • F1R6 : CAN_TypeDef
  • F1R7 : CAN_TypeDef
  • F1R8 : CAN_TypeDef
  • F2R1 : CAN_TypeDef
  • F2R2 : CAN_TypeDef
  • F2R3 : CAN_TypeDef
  • F2R4 : CAN_TypeDef
  • F2R5 : CAN_TypeDef
  • F2R6 : CAN_TypeDef
  • F2R7 : CAN_TypeDef
  • F2R8 : CAN_TypeDef
  • F3R1 : CAN_TypeDef
  • F3R2 : CAN_TypeDef
  • F3R3 : CAN_TypeDef
  • F3R4 : CAN_TypeDef
  • F3R5 : CAN_TypeDef
  • F3R6 : CAN_TypeDef
  • F3R7 : CAN_TypeDef
  • F3R8 : CAN_TypeDef
  • F4R1 : CAN_TypeDef
  • F4R2 : CAN_TypeDef
  • F4R3 : CAN_TypeDef
  • F4R4 : CAN_TypeDef
  • F4R5 : CAN_TypeDef
  • F4R6 : CAN_TypeDef
  • F4R7 : CAN_TypeDef
  • F4R8 : CAN_TypeDef
  • F5R1 : CAN_TypeDef
  • F5R2 : CAN_TypeDef
  • F5R3 : CAN_TypeDef
  • F5R4 : CAN_TypeDef
  • F5R5 : CAN_TypeDef
  • F5R6 : CAN_TypeDef
  • F5R7 : CAN_TypeDef
  • F5R8 : CAN_TypeDef
  • FCR1 : CAN_TypeDef
  • FCR2 : CAN_TypeDef
  • FCR3 : CAN_TypeDef
  • Filter : CAN_TypeDef
  • Filter01 : CAN_TypeDef
  • Filter23 : CAN_TypeDef
  • Filter45 : CAN_TypeDef
  • FMR1 : CAN_TypeDef
  • FMR2 : CAN_TypeDef
  • FPR : FLASH_struct
  • FR01 : CAN_TypeDef
  • FR02 : CAN_TypeDef
  • FR03 : CAN_TypeDef
  • FR04 : CAN_TypeDef
  • FR05 : CAN_TypeDef
  • FR06 : CAN_TypeDef
  • FR07 : CAN_TypeDef
  • FR08 : CAN_TypeDef
  • FR09 : CAN_TypeDef
  • FR10 : CAN_TypeDef
  • FR11 : CAN_TypeDef
  • FR12 : CAN_TypeDef
  • FR13 : CAN_TypeDef
  • FR14 : CAN_TypeDef
  • FR15 : CAN_TypeDef
  • FR16 : CAN_TypeDef
  • FREQR : I2C_struct


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
  • Data Structure Index
  • Data Fields
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  • Variables
  • a
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- g -

  • GCR : CFG_struct
  • GTR : UART2_struct , UART1_struct


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
  • Data Structure Index
  • Data Fields
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  • Variables
  • a
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- h -

  • HSITRIMR : CLK_struct


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
  • Data Structure Index
  • Data Fields
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  • a
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- i -

  • IAPSR : FLASH_struct
  • ICKR : CLK_struct
  • ICR : SPI_struct
  • IDR : GPIO_struct
  • IER : TIM4_struct , TIM5_struct , TIM1_struct , TIM6_struct , CAN_TypeDef , TIM2_struct , TIM3_struct
  • ISPR1 : ITC_struct
  • ISPR2 : ITC_struct
  • ISPR3 : ITC_struct
  • ISPR4 : ITC_struct
  • ISPR5 : ITC_struct
  • ISPR6 : ITC_struct
  • ISPR7 : ITC_struct
  • ISPR8 : ITC_struct
  • ITR : I2C_struct


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
  • Data Structure Index
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  • a
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  • t
  • w

- p -

  • Page : CAN_TypeDef
  • PCKENR1 : CLK_struct
  • PCKENR2 : CLK_struct
  • PR : IWDG_struct
  • PSCR : TIM5_struct , UART2_struct , UART1_struct , TIM6_struct , TIM2_struct , TIM4_struct , TIM3_struct
  • PSCRH : TIM1_struct
  • PSCRL : TIM1_struct
  • PSR : CAN_TypeDef
  • PUKR : FLASH_struct


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
  • Data Structure Index
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  • a
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- r -

  • RCR : TIM1_struct
  • RECR : CAN_TypeDef
  • RESERVED : UART3_struct , CLK_struct
  • RESERVED1 : OPT_struct
  • Reserved1 : CAN_TypeDef
  • RESERVED1 : CLK_struct , I2C_struct , FLASH_struct
  • RESERVED2 : OPT_struct
  • Reserved2 : CAN_TypeDef
  • RESERVED2 : I2C_struct , FLASH_struct
  • RESERVED3 : FLASH_struct
  • RFR : CAN_TypeDef
  • RLR : IWDG_struct
  • RXCRCR : SPI_struct
  • RxFIFO : CAN_TypeDef


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
  • Data Structure Index
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  • a
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  • w

- s -

  • SMCR : TIM1_struct , TIM5_struct , TIM6_struct
  • SR : RST_struct , UART3_struct , SPI_struct , UART1_struct , UART2_struct
  • SR1 : TIM1_struct , TIM2_struct , I2C_struct , TIM3_struct , TIM4_struct , TIM5_struct , TIM6_struct
  • SR2 : TIM5_struct , TIM3_struct , TIM1_struct , TIM2_struct , I2C_struct
  • SR3 : I2C_struct
  • SWCR : CLK_struct
  • SWIMCCR : CLK_struct
  • SWR : CLK_struct


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
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  • w

- t -

  • TBR : AWU_struct
  • TECR : CAN_TypeDef
  • TPR : CAN_TypeDef
  • TRISER : I2C_struct
  • TSR : CAN_TypeDef
  • TXCRCR : SPI_struct
  • TxMailbox : CAN_TypeDef


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
  • Data Structure Index
  • Data Fields
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  • Variables
  • a
  • b
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- w -

  • WR : WWDG_struct


STM8S/A Standard Peripherals Drivers: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
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  • g
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  • i
  • l
  • m
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  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- l -

  • LSI_FREQUENCY_MAX : stm8s_awu.h , stm8s_beep.h
  • LSI_FREQUENCY_MIN : stm8s_beep.h , stm8s_awu.h
  • LSI_VALUE : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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  • Globals
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- m -

  • MemoryAddressCast : stm8s.h
  • MskBit : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- n -

  • NEAR : stm8s.h
  • nop : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

  • File List
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- o -

  • OPERATION_TIMEOUT : stm8s_flash.c
  • OPT : stm8s.h
  • OPT_BaseAddress : stm8s.h
  • OPT_TypeDef : stm8s.h
  • OPTION_BYTE_END_PHYSICAL_ADDRESS : stm8s_flash.h
  • OPTION_BYTE_START_PHYSICAL_ADDRESS : stm8s_flash.h


STM8S/A Standard Peripherals Drivers: Globals

  • File List
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- a -

  • ADC1_ALIGN_LEFT : stm8s_adc1.h
  • ADC1_ALIGN_RIGHT : stm8s_adc1.h
  • ADC1_Align_TypeDef : stm8s_adc1.h
  • ADC1_AWDChannelConfig() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_BaseAddress : stm8s.h
  • ADC1_CHANNEL_0 : stm8s_adc1.h
  • ADC1_CHANNEL_1 : stm8s_adc1.h
  • ADC1_CHANNEL_12 : stm8s_adc1.h
  • ADC1_CHANNEL_2 : stm8s_adc1.h
  • ADC1_CHANNEL_3 : stm8s_adc1.h
  • ADC1_CHANNEL_4 : stm8s_adc1.h
  • ADC1_CHANNEL_5 : stm8s_adc1.h
  • ADC1_CHANNEL_6 : stm8s_adc1.h
  • ADC1_CHANNEL_7 : stm8s_adc1.h
  • ADC1_CHANNEL_8 : stm8s_adc1.h
  • ADC1_CHANNEL_9 : stm8s_adc1.h
  • ADC1_Channel_TypeDef : stm8s_adc1.h
  • ADC1_ClearFlag() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_ClearITPendingBit() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_Cmd() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_ConversionConfig() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_CONVERSIONMODE_CONTINUOUS : stm8s_adc1.h
  • ADC1_CONVERSIONMODE_SINGLE : stm8s_adc1.h
  • ADC1_ConvMode_TypeDef : stm8s_adc1.h
  • ADC1_DataBufferCmd() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_DeInit() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_ExternalTriggerConfig() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_EXTTRIG_GPIO : stm8s_adc1.h
  • ADC1_EXTTRIG_TIM : stm8s_adc1.h
  • ADC1_ExtTrig_TypeDef : stm8s_adc1.h
  • ADC1_FLAG_AWD : stm8s_adc1.h
  • ADC1_FLAG_AWS0 : stm8s_adc1.h
  • ADC1_FLAG_AWS1 : stm8s_adc1.h
  • ADC1_FLAG_AWS12 : stm8s_adc1.h
  • ADC1_FLAG_AWS2 : stm8s_adc1.h
  • ADC1_FLAG_AWS3 : stm8s_adc1.h
  • ADC1_FLAG_AWS4 : stm8s_adc1.h
  • ADC1_FLAG_AWS5 : stm8s_adc1.h
  • ADC1_FLAG_AWS6 : stm8s_adc1.h
  • ADC1_FLAG_AWS7 : stm8s_adc1.h
  • ADC1_FLAG_AWS8 : stm8s_adc1.h
  • ADC1_FLAG_AWS9 : stm8s_adc1.h
  • ADC1_FLAG_EOC : stm8s_adc1.h
  • ADC1_FLAG_OVR : stm8s_adc1.h
  • ADC1_Flag_TypeDef : stm8s_adc1.h
  • ADC1_GetAWDChannelStatus() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_GetBufferValue() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_GetConversionValue() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_GetFlagStatus() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_GetITStatus() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_Init() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_IT_AWD : stm8s_adc1.h
  • ADC1_IT_AWDIE : stm8s_adc1.h
  • ADC1_IT_AWS0 : stm8s_adc1.h
  • ADC1_IT_AWS1 : stm8s_adc1.h
  • ADC1_IT_AWS12 : stm8s_adc1.h
  • ADC1_IT_AWS2 : stm8s_adc1.h
  • ADC1_IT_AWS3 : stm8s_adc1.h
  • ADC1_IT_AWS4 : stm8s_adc1.h
  • ADC1_IT_AWS5 : stm8s_adc1.h
  • ADC1_IT_AWS6 : stm8s_adc1.h
  • ADC1_IT_AWS7 : stm8s_adc1.h
  • ADC1_IT_AWS8 : stm8s_adc1.h
  • ADC1_IT_AWS9 : stm8s_adc1.h
  • ADC1_IT_EOC : stm8s_adc1.h
  • ADC1_IT_EOCIE : stm8s_adc1.h
  • ADC1_IT_TypeDef : stm8s_adc1.h
  • ADC1_ITConfig() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_PrescalerConfig() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_PRESSEL_FCPU_D10 : stm8s_adc1.h
  • ADC1_PRESSEL_FCPU_D12 : stm8s_adc1.h
  • ADC1_PRESSEL_FCPU_D18 : stm8s_adc1.h
  • ADC1_PRESSEL_FCPU_D2 : stm8s_adc1.h
  • ADC1_PRESSEL_FCPU_D3 : stm8s_adc1.h
  • ADC1_PRESSEL_FCPU_D4 : stm8s_adc1.h
  • ADC1_PRESSEL_FCPU_D6 : stm8s_adc1.h
  • ADC1_PRESSEL_FCPU_D8 : stm8s_adc1.h
  • ADC1_PresSel_TypeDef : stm8s_adc1.h
  • ADC1_ScanModeCmd() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_SCHMITTTRIG_ALL : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL0 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL1 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL12 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL2 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL3 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL4 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL5 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL6 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL7 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL8 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL9 : stm8s_adc1.h
  • ADC1_SchmittTrigg_TypeDef : stm8s_adc1.h
  • ADC1_SchmittTriggerConfig() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_SetHighThreshold() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_SetLowThreshold() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_StartConversion() : stm8s_adc1.h , stm8s_adc1.c
  • ADC2_ALIGN_LEFT : stm8s_adc2.h
  • ADC2_ALIGN_RIGHT : stm8s_adc2.h
  • ADC2_Align_TypeDef : stm8s_adc2.h
  • ADC2_BaseAddress : stm8s.h
  • ADC2_CHANNEL_0 : stm8s_adc2.h
  • ADC2_CHANNEL_1 : stm8s_adc2.h
  • ADC2_CHANNEL_10 : stm8s_adc2.h
  • ADC2_CHANNEL_11 : stm8s_adc2.h
  • ADC2_CHANNEL_12 : stm8s_adc2.h
  • ADC2_CHANNEL_13 : stm8s_adc2.h
  • ADC2_CHANNEL_14 : stm8s_adc2.h
  • ADC2_CHANNEL_15 : stm8s_adc2.h
  • ADC2_CHANNEL_2 : stm8s_adc2.h
  • ADC2_CHANNEL_3 : stm8s_adc2.h
  • ADC2_CHANNEL_4 : stm8s_adc2.h
  • ADC2_CHANNEL_5 : stm8s_adc2.h
  • ADC2_CHANNEL_6 : stm8s_adc2.h
  • ADC2_CHANNEL_7 : stm8s_adc2.h
  • ADC2_CHANNEL_8 : stm8s_adc2.h
  • ADC2_CHANNEL_9 : stm8s_adc2.h
  • ADC2_Channel_TypeDef : stm8s_adc2.h
  • ADC2_ClearFlag() : stm8s_adc2.c , stm8s_adc2.h
  • ADC2_ClearITPendingBit() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_Cmd() : stm8s_adc2.c , stm8s_adc2.h
  • ADC2_ConversionConfig() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_CONVERSIONMODE_CONTINUOUS : stm8s_adc2.h
  • ADC2_CONVERSIONMODE_SINGLE : stm8s_adc2.h
  • ADC2_ConvMode_TypeDef : stm8s_adc2.h
  • ADC2_DeInit() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_ExternalTriggerConfig() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_EXTTRIG_GPIO : stm8s_adc2.h
  • ADC2_EXTTRIG_TIM : stm8s_adc2.h
  • ADC2_ExtTrig_TypeDef : stm8s_adc2.h
  • ADC2_GetConversionValue() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_GetFlagStatus() : stm8s_adc2.c , stm8s_adc2.h
  • ADC2_GetITStatus() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_Init() : stm8s_adc2.c , stm8s_adc2.h
  • ADC2_ITConfig() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_PrescalerConfig() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_PRESSEL_FCPU_D10 : stm8s_adc2.h
  • ADC2_PRESSEL_FCPU_D12 : stm8s_adc2.h
  • ADC2_PRESSEL_FCPU_D18 : stm8s_adc2.h
  • ADC2_PRESSEL_FCPU_D2 : stm8s_adc2.h
  • ADC2_PRESSEL_FCPU_D3 : stm8s_adc2.h
  • ADC2_PRESSEL_FCPU_D4 : stm8s_adc2.h
  • ADC2_PRESSEL_FCPU_D6 : stm8s_adc2.h
  • ADC2_PRESSEL_FCPU_D8 : stm8s_adc2.h
  • ADC2_PresSel_TypeDef : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_ALL : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL0 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL1 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL10 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL11 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL12 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL13 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL14 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL15 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL2 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL3 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL4 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL5 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL6 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL7 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL8 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL9 : stm8s_adc2.h
  • ADC2_SchmittTrigg_TypeDef : stm8s_adc2.h
  • ADC2_SchmittTriggerConfig() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_StartConversion() : stm8s_adc2.c , stm8s_adc2.h
  • AffBit : stm8s.h
  • APR_Array : stm8s_awu.c
  • AREA : stm8s.h
  • AWU : stm8s.h
  • AWU_APR_APR : stm8s.h
  • AWU_APR_RESET_VALUE : stm8s.h
  • AWU_BaseAddress : stm8s.h
  • AWU_Cmd() : stm8s_awu.h , stm8s_awu.c
  • AWU_CSR_AWUEN : stm8s.h
  • AWU_CSR_AWUF : stm8s.h
  • AWU_CSR_MSR : stm8s.h
  • AWU_CSR_RESET_VALUE : stm8s.h
  • AWU_DeInit() : stm8s_awu.c , stm8s_awu.h
  • AWU_GetFlagStatus() : stm8s_awu.h , stm8s_awu.c
  • AWU_IdleModeEnable() : stm8s_awu.c , stm8s_awu.h
  • AWU_Init() : stm8s_awu.h , stm8s_awu.c
  • AWU_LSICalibrationConfig() : stm8s_awu.c , stm8s_awu.h
  • AWU_TBR_AWUTB : stm8s.h
  • AWU_TBR_RESET_VALUE : stm8s.h
  • AWU_TIMEBASE_128MS : stm8s_awu.h
  • AWU_TIMEBASE_12S : stm8s_awu.h
  • AWU_TIMEBASE_16MS : stm8s_awu.h
  • AWU_TIMEBASE_1MS : stm8s_awu.h
  • AWU_TIMEBASE_1S : stm8s_awu.h
  • AWU_TIMEBASE_250US : stm8s_awu.h
  • AWU_TIMEBASE_256MS : stm8s_awu.h
  • AWU_TIMEBASE_2MS : stm8s_awu.h
  • AWU_TIMEBASE_2S : stm8s_awu.h
  • AWU_TIMEBASE_30S : stm8s_awu.h
  • AWU_TIMEBASE_32MS : stm8s_awu.h
  • AWU_TIMEBASE_4MS : stm8s_awu.h
  • AWU_TIMEBASE_500US : stm8s_awu.h
  • AWU_TIMEBASE_512MS : stm8s_awu.h
  • AWU_TIMEBASE_64MS : stm8s_awu.h
  • AWU_TIMEBASE_8MS : stm8s_awu.h
  • AWU_TIMEBASE_NO_IT : stm8s_awu.h
  • AWU_Timebase_TypeDef : stm8s_awu.h
  • AWU_TypeDef : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- b -

  • BEEP : stm8s.h
  • BEEP_BaseAddress : stm8s.h
  • BEEP_CALIBRATION_DEFAULT : stm8s_beep.h
  • BEEP_Cmd() : stm8s_beep.h , stm8s_beep.c
  • BEEP_CSR_BEEPDIV : stm8s.h
  • BEEP_CSR_BEEPEN : stm8s.h
  • BEEP_CSR_BEEPSEL : stm8s.h
  • BEEP_CSR_RESET_VALUE : stm8s.h
  • BEEP_DeInit() : stm8s_beep.h , stm8s_beep.c
  • BEEP_FREQUENCY_1KHZ : stm8s_beep.h
  • BEEP_FREQUENCY_2KHZ : stm8s_beep.h
  • BEEP_FREQUENCY_4KHZ : stm8s_beep.h
  • BEEP_Frequency_TypeDef : stm8s_beep.h
  • BEEP_Init() : stm8s_beep.h , stm8s_beep.c
  • BEEP_LSICalibrationConfig() : stm8s_beep.h , stm8s_beep.c
  • BEEP_TypeDef : stm8s.h
  • BIT_MASK : stm8s_wwdg.c
  • BitAction : stm8s.h
  • BitClr : stm8s.h
  • BitSet : stm8s.h
  • BitStatus : stm8s.h
  • BitVal : stm8s.h
  • bool : stm8s.h
  • BYTE_0 : stm8s.h
  • BYTE_1 : stm8s.h
  • BYTE_2 : stm8s.h
  • BYTE_3 : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
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  • Defines
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  • a
  • b
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  • g
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- c -

  • CAN_ACKNOWLEDGE_TIMEOUT : stm8s_can.c
  • CAN_BaseAddress : stm8s.h
  • CAN_BitSeg1_10TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_11TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_12TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_13TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_14TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_15TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_16TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_1TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_2TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_3TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_4TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_5TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_6TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_7TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_8TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_9TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_TypeDef : stm8s_can.h
  • CAN_BitSeg2_1TimeQuantum : stm8s_can.h
  • CAN_BitSeg2_2TimeQuantum : stm8s_can.h
  • CAN_BitSeg2_3TimeQuantum : stm8s_can.h
  • CAN_BitSeg2_4TimeQuantum : stm8s_can.h
  • CAN_BitSeg2_5TimeQuantum : stm8s_can.h
  • CAN_BitSeg2_6TimeQuantum : stm8s_can.h
  • CAN_BitSeg2_7TimeQuantum : stm8s_can.h
  • CAN_BitSeg2_8TimeQuantum : stm8s_can.h
  • CAN_BitSeg2_TypeDef : stm8s_can.h
  • CAN_BTR1_RESET_VALUE : stm8s.h
  • CAN_BTR2_RESET_VALUE : stm8s.h
  • CAN_CancelTransmit() : stm8s_can.c , stm8s_can.h
  • CAN_ClearFlag() : stm8s_can.h , stm8s_can.c
  • CAN_ClearITPendingBit() : stm8s_can.h , stm8s_can.c
  • CAN_DeInit() : stm8s_can.h , stm8s_can.c
  • CAN_DGR_LBKM : stm8s.h
  • CAN_DGR_RESET_VALUE : stm8s.h
  • CAN_DGR_RX : stm8s.h
  • CAN_DGR_SAMP : stm8s.h
  • CAN_DGR_SLIM : stm8s.h
  • CAN_DGR_TXM2E : stm8s.h
  • CAN_DLC_MAX : stm8s_can.h
  • CAN_EIER_BOFIE : stm8s.h
  • CAN_EIER_EPVIE : stm8s.h
  • CAN_EIER_ERRIE : stm8s.h
  • CAN_EIER_EWGIE : stm8s.h
  • CAN_EIER_LECIE : stm8s.h
  • CAN_EIER_RESET_VALUE : stm8s.h
  • CAN_ErrorCode_ACKErr : stm8s_can.h
  • CAN_ErrorCode_BitDominantErr : stm8s_can.h
  • CAN_ErrorCode_BitRecessiveErr : stm8s_can.h
  • CAN_ErrorCode_CRCErr : stm8s_can.h
  • CAN_ErrorCode_FormErr : stm8s_can.h
  • CAN_ErrorCode_NoErr : stm8s_can.h
  • CAN_ErrorCode_SoftwareSetErr : stm8s_can.h
  • CAN_ErrorCode_StuffErr : stm8s_can.h
  • CAN_ErrorCode_TypeDef : stm8s_can.h
  • CAN_ESR_BOFF : stm8s.h
  • CAN_ESR_EPVF : stm8s.h
  • CAN_ESR_EWGF : stm8s.h
  • CAN_ESR_LEC : stm8s.h
  • CAN_ESR_LEC0 : stm8s.h
  • CAN_ESR_LEC1 : stm8s.h
  • CAN_ESR_LEC2 : stm8s.h
  • CAN_ESR_RESET_VALUE : stm8s.h
  • CAN_EXTID_SIZE : stm8s_can.h
  • CAN_FCR1_FACT0 : stm8s.h
  • CAN_FCR1_FACT1 : stm8s.h
  • CAN_FCR1_FSC00 : stm8s.h
  • CAN_FCR1_FSC01 : stm8s.h
  • CAN_FCR1_FSC10 : stm8s.h
  • CAN_FCR1_FSC11 : stm8s.h
  • CAN_FCR2_FACT2 : stm8s.h
  • CAN_FCR2_FACT3 : stm8s.h
  • CAN_FCR2_FSC20 : stm8s.h
  • CAN_FCR2_FSC21 : stm8s.h
  • CAN_FCR2_FSC30 : stm8s.h
  • CAN_FCR2_FSC31 : stm8s.h
  • CAN_FCR3_FACT4 : stm8s.h
  • CAN_FCR3_FACT5 : stm8s.h
  • CAN_FCR3_FSC40 : stm8s.h
  • CAN_FCR3_FSC41 : stm8s.h
  • CAN_FCR3_FSC50 : stm8s.h
  • CAN_FCR3_FSC51 : stm8s.h
  • CAN_FCR_RESET_VALUE : stm8s.h
  • CAN_FIFORelease() : stm8s_can.h , stm8s_can.c
  • CAN_FilterInit() : stm8s_can.h , stm8s_can.c
  • CAN_FilterMode_IdList : stm8s_can.h
  • CAN_FilterMode_IdList_IdMask : stm8s_can.h
  • CAN_FilterMode_IdMask : stm8s_can.h
  • CAN_FilterMode_IdMask_IdList : stm8s_can.h
  • CAN_FilterMode_TypeDef : stm8s_can.h
  • CAN_FilterNumber_0 : stm8s_can.h
  • CAN_FilterNumber_1 : stm8s_can.h
  • CAN_FilterNumber_2 : stm8s_can.h
  • CAN_FilterNumber_3 : stm8s_can.h
  • CAN_FilterNumber_4 : stm8s_can.h
  • CAN_FilterNumber_5 : stm8s_can.h
  • CAN_FilterNumber_TypeDef : stm8s_can.h
  • CAN_FilterScale_16_8Bit : stm8s_can.h
  • CAN_FilterScale_16Bit : stm8s_can.h
  • CAN_FilterScale_32Bit : stm8s_can.h
  • CAN_FilterScale_8Bit : stm8s_can.h
  • CAN_FilterScale_TypeDef : stm8s_can.h
  • CAN_FLAG_BOF : stm8s_can.h
  • CAN_FLAG_EPV : stm8s_can.h
  • CAN_FLAG_EWG : stm8s_can.h
  • CAN_FLAG_FF : stm8s_can.h
  • CAN_FLAG_FMP : stm8s_can.h
  • CAN_FLAG_FOV : stm8s_can.h
  • CAN_FLAG_LEC : stm8s_can.h
  • CAN_FLAG_RQCP0 : stm8s_can.h
  • CAN_FLAG_RQCP1 : stm8s_can.h
  • CAN_FLAG_RQCP2 : stm8s_can.h
  • CAN_FLAG_TypeDef : stm8s_can.h
  • CAN_FLAG_WKU : stm8s_can.h
  • CAN_FMR1_FMH0 : stm8s.h
  • CAN_FMR1_FMH1 : stm8s.h
  • CAN_FMR1_FMH2 : stm8s.h
  • CAN_FMR1_FMH3 : stm8s.h
  • CAN_FMR1_FML0 : stm8s.h
  • CAN_FMR1_FML1 : stm8s.h
  • CAN_FMR1_FML2 : stm8s.h
  • CAN_FMR1_FML3 : stm8s.h
  • CAN_FMR1_RESET_VALUE : stm8s.h
  • CAN_FMR2_FMH4 : stm8s.h
  • CAN_FMR2_FMH5 : stm8s.h
  • CAN_FMR2_FML4 : stm8s.h
  • CAN_FMR2_FML5 : stm8s.h
  • CAN_FMR2_RESET_VALUE : stm8s.h
  • CAN_GetFlagStatus() : stm8s_can.h , stm8s_can.c
  • CAN_GetITStatus() : stm8s_can.h , stm8s_can.c
  • CAN_GetLastErrorCode() : stm8s_can.h , stm8s_can.c
  • CAN_GetMessageTimeStamp() : stm8s_can.h , stm8s_can.c
  • CAN_GetReceivedData() : stm8s_can.h , stm8s_can.c
  • CAN_GetReceivedDLC() : stm8s_can.h , stm8s_can.c
  • CAN_GetReceivedFMI() : stm8s_can.h , stm8s_can.c
  • CAN_GetReceivedId() : stm8s_can.h , stm8s_can.c
  • CAN_GetReceivedIDE() : stm8s_can.h , stm8s_can.c
  • CAN_GetReceivedRTR() : stm8s_can.h , stm8s_can.c
  • CAN_GetSelectedPage() : stm8s_can.h , stm8s_can.c
  • CAN_Id_Extended : stm8s_can.h
  • CAN_Id_Standard : stm8s_can.h
  • CAN_Id_TypeDef : stm8s_can.h
  • CAN_IDLIST_IDMASK_MASK : stm8s_can.c
  • CAN_IDMASK_IDLIST_MASK : stm8s_can.c
  • CAN_IER_FFIE : stm8s.h
  • CAN_IER_FMPIE : stm8s.h
  • CAN_IER_FOVIE : stm8s.h
  • CAN_IER_RESET_VALUE : stm8s.h
  • CAN_IER_TMEIE : stm8s.h
  • CAN_IER_WKUIE : stm8s.h
  • CAN_Init() : stm8s_can.h , stm8s_can.c
  • CAN_InitStatus_Failed : stm8s_can.h
  • CAN_InitStatus_Success : stm8s_can.h
  • CAN_InitStatus_TypeDef : stm8s_can.h
  • CAN_IT_BOF : stm8s_can.h
  • CAN_IT_CONFIG_MASK : stm8s_can.h
  • CAN_IT_EPV : stm8s_can.h
  • CAN_IT_ERR : stm8s_can.h
  • CAN_IT_EWG : stm8s_can.h
  • CAN_IT_FF : stm8s_can.h
  • CAN_IT_FMP : stm8s_can.h
  • CAN_IT_FOV : stm8s_can.h
  • CAN_IT_LEC : stm8s_can.h
  • CAN_IT_TME : stm8s_can.h
  • CAN_IT_TypeDef : stm8s_can.h
  • CAN_IT_WKU : stm8s_can.h
  • CAN_ITConfig() : stm8s_can.h , stm8s_can.c
  • CAN_MasterCtrl_AllDisabled : stm8s_can.h
  • CAN_MasterCtrl_AllEnabled : stm8s_can.h
  • CAN_MasterCtrl_AutoBusOffManagement : stm8s_can.h
  • CAN_MasterCtrl_AutoWakeUpMode : stm8s_can.h
  • CAN_MasterCtrl_NoAutoReTx : stm8s_can.h
  • CAN_MasterCtrl_RxFifoLockedMode : stm8s_can.h
  • CAN_MasterCtrl_TimeTriggerCOMMode : stm8s_can.h
  • CAN_MasterCtrl_TxFifoPriority : stm8s_can.h
  • CAN_MasterCtrl_TypeDef : stm8s_can.h
  • CAN_MCR_ABOM : stm8s.h
  • CAN_MCR_AWUM : stm8s.h
  • CAN_MCR_INRQ : stm8s.h
  • CAN_MCR_NART : stm8s.h
  • CAN_MCR_RESET_VALUE : stm8s.h
  • CAN_MCR_RFLM : stm8s.h
  • CAN_MCR_SLEEP : stm8s.h
  • CAN_MCR_TTCM : stm8s.h
  • CAN_MCR_TXFP : stm8s.h
  • CAN_MCSR_ABRQ : stm8s.h
  • CAN_MCSR_ALST : stm8s.h
  • CAN_MCSR_RESET_VALUE : stm8s.h
  • CAN_MCSR_RQCP : stm8s.h
  • CAN_MCSR_TERR : stm8s.h
  • CAN_MCSR_TXOK : stm8s.h
  • CAN_MCSR_TXRQ : stm8s.h
  • CAN_MDLC_RESET_VALUE : stm8s.h
  • CAN_MDLCR_DLC : stm8s.h
  • CAN_MDLCR_TGT : stm8s.h
  • CAN_MessagePending() : stm8s_can.h , stm8s_can.c
  • CAN_MFMI_RESET_VALUE : stm8s.h
  • CAN_MIDR1_IDE : stm8s.h
  • CAN_MIDR1_RTR : stm8s.h
  • CAN_Mode_LoopBack : stm8s_can.h
  • CAN_MODE_MASK : stm8s_can.c
  • CAN_Mode_Normal : stm8s_can.h
  • CAN_Mode_Silent : stm8s_can.h
  • CAN_Mode_Silent_LoopBack : stm8s_can.h
  • CAN_Mode_TypeDef : stm8s_can.h
  • CAN_ModeStatus_Failed : stm8s_can.h
  • CAN_ModeStatus_Success : stm8s_can.h
  • CAN_ModeStatus_TypeDef : stm8s_can.h
  • CAN_MSR_ERRI : stm8s.h
  • CAN_MSR_INAK : stm8s.h
  • CAN_MSR_RESET_VALUE : stm8s.h
  • CAN_MSR_RX : stm8s.h
  • CAN_MSR_SLAK : stm8s.h
  • CAN_MSR_TX : stm8s.h
  • CAN_MSR_WKUI : stm8s.h
  • CAN_NbrPendingMessage_0 : stm8s_can.h
  • CAN_NbrPendingMessage_1 : stm8s_can.h
  • CAN_NbrPendingMessage_2 : stm8s_can.h
  • CAN_NbrPendingMessage_3 : stm8s_can.h
  • CAN_NbrPendingMessage_TypeDef : stm8s_can.h
  • CAN_OperatingMode_Initialization : stm8s_can.h
  • CAN_OperatingMode_Normal : stm8s_can.h
  • CAN_OperatingMode_Sleep : stm8s_can.h
  • CAN_OperatingMode_TypeDef : stm8s_can.h
  • CAN_OperatingModeRequest() : stm8s_can.h , stm8s_can.c
  • CAN_Page_Config : stm8s_can.h
  • CAN_Page_Filter01 : stm8s_can.h
  • CAN_Page_Filter23 : stm8s_can.h
  • CAN_Page_Filter45 : stm8s_can.h
  • CAN_Page_RxFifo : stm8s_can.h
  • CAN_Page_TxMailBox0 : stm8s_can.h
  • CAN_Page_TxMailBox1 : stm8s_can.h
  • CAN_Page_TxMailBox2 : stm8s_can.h
  • CAN_Page_TypeDef : stm8s_can.h
  • CAN_PSR_PS0 : stm8s.h
  • CAN_PSR_PS1 : stm8s.h
  • CAN_PSR_PS2 : stm8s.h
  • CAN_PSR_RESET_VALUE : stm8s.h
  • CAN_Receive() : stm8s_can.h , stm8s_can.c
  • CAN_RECR_REC0 : stm8s.h
  • CAN_RECR_REC1 : stm8s.h
  • CAN_RECR_REC2 : stm8s.h
  • CAN_RECR_REC3 : stm8s.h
  • CAN_RECR_REC4 : stm8s.h
  • CAN_RECR_REC5 : stm8s.h
  • CAN_RECR_REC6 : stm8s.h
  • CAN_RECR_REC7 : stm8s.h
  • CAN_RECR_RESET_VALUE : stm8s.h
  • CAN_RFR_FMP01 : stm8s.h
  • CAN_RFR_FOVR : stm8s.h
  • CAN_RFR_FULL : stm8s.h
  • CAN_RFR_RESET_VALUE : stm8s.h
  • CAN_RFR_RFOM : stm8s.h
  • CAN_RTR_Data : stm8s_can.h
  • CAN_RTR_Remote : stm8s_can.h
  • CAN_RTR_TypeDef : stm8s_can.h
  • CAN_SelectPage() : stm8s_can.h , stm8s_can.c
  • CAN_Sleep() : stm8s_can.c , stm8s_can.h
  • CAN_Sleep_Failed : stm8s_can.h
  • CAN_Sleep_Ok : stm8s_can.h
  • CAN_Sleep_TypeDef : stm8s_can.h
  • CAN_ST7Compatibility_Disable : stm8s_can.h
  • CAN_ST7Compatibility_Enable : stm8s_can.h
  • CAN_ST7Compatibility_TypeDef : stm8s_can.h
  • CAN_ST7CompatibilityCmd() : stm8s_can.h , stm8s_can.c
  • CAN_STDID_SIZE : stm8s_can.h
  • CAN_SynJumpWidth_1TimeQuantum : stm8s_can.h
  • CAN_SynJumpWidth_2TimeQuantum : stm8s_can.h
  • CAN_SynJumpWidth_3TimeQuantum : stm8s_can.h
  • CAN_SynJumpWidth_4TimeQuantum : stm8s_can.h
  • CAN_SynJumpWidth_TypeDef : stm8s_can.h
  • CAN_TECR_RESET_VALUE : stm8s.h
  • CAN_TECR_TEC0 : stm8s.h
  • CAN_TECR_TEC1 : stm8s.h
  • CAN_TECR_TEC2 : stm8s.h
  • CAN_TECR_TEC3 : stm8s.h
  • CAN_TECR_TEC4 : stm8s.h
  • CAN_TECR_TEC5 : stm8s.h
  • CAN_TECR_TEC6 : stm8s.h
  • CAN_TECR_TEC7 : stm8s.h
  • CAN_TPR_CODE0 : stm8s.h
  • CAN_TPR_LOW0 : stm8s.h
  • CAN_TPR_LOW1 : stm8s.h
  • CAN_TPR_LOW2 : stm8s.h
  • CAN_TPR_RESET_VALUE : stm8s.h
  • CAN_TPR_TME0 : stm8s.h
  • CAN_TPR_TME1 : stm8s.h
  • CAN_TPR_TME2 : stm8s.h
  • CAN_Transmit() : stm8s_can.c , stm8s_can.h
  • CAN_TransmitMailBox_0 : stm8s_can.h
  • CAN_TransmitMailBox_1 : stm8s_can.h
  • CAN_TransmitMailBox_2 : stm8s_can.h
  • CAN_TransmitMailBox_TypeDef : stm8s_can.h
  • CAN_TransmitStatus() : stm8s_can.h , stm8s_can.c
  • CAN_TSR_RESET_VALUE : stm8s.h
  • CAN_TSR_RQCP0 : stm8s.h
  • CAN_TSR_RQCP012 : stm8s.h
  • CAN_TSR_RQCP1 : stm8s.h
  • CAN_TSR_RQCP2 : stm8s.h
  • CAN_TSR_TXOK0 : stm8s.h
  • CAN_TSR_TXOK1 : stm8s.h
  • CAN_TSR_TXOK2 : stm8s.h
  • CAN_TTComModeCmd() : stm8s_can.c , stm8s_can.h
  • CAN_TxStatus_Failed : stm8s_can.h
  • CAN_TxStatus_MailBox0Ok : stm8s_can.h
  • CAN_TxStatus_MailBox1Ok : stm8s_can.h
  • CAN_TxStatus_MailBox2Ok : stm8s_can.h
  • CAN_TxStatus_MailBoxEmpty : stm8s_can.h
  • CAN_TxStatus_NoMailBox : stm8s_can.h
  • CAN_TxStatus_Ok : stm8s_can.h
  • CAN_TxStatus_Pending : stm8s_can.h
  • CAN_TxStatus_TypeDef : stm8s_can.h
  • CAN_WakeUp() : stm8s_can.h , stm8s_can.c
  • CAN_WakeUp_Failed : stm8s_can.h
  • CAN_WakeUp_Ok : stm8s_can.h
  • CAN_WakeUp_TypeDef : stm8s_can.h
  • CCMR_TIxDirect_Set : stm8s.h
  • CFG : stm8s.h
  • CFG_BaseAddress : stm8s.h
  • CFG_GCR_AL : stm8s.h
  • CFG_GCR_RESET_VALUE : stm8s.h
  • CFG_GCR_SWD : stm8s.h
  • CFG_TypeDef : stm8s.h
  • CheckITStatus() : stm8s_can.c
  • ChgBit : stm8s.h
  • CLK : stm8s.h
  • CLK_AdjustHSICalibrationValue() : stm8s_clk.h , stm8s_clk.c
  • CLK_BaseAddress : stm8s.h
  • CLK_CCOCmd() : stm8s_clk.h , stm8s_clk.c
  • CLK_CCOConfig() : stm8s_clk.h , stm8s_clk.c
  • CLK_CCOR_CCOBSY : stm8s.h
  • CLK_CCOR_CCOEN : stm8s.h
  • CLK_CCOR_CCORDY : stm8s.h
  • CLK_CCOR_CCOSEL : stm8s.h
  • CLK_CCOR_RESET_VALUE : stm8s.h
  • CLK_CKDIVR_CPUDIV : stm8s.h
  • CLK_CKDIVR_HSIDIV : stm8s.h
  • CLK_CKDIVR_RESET_VALUE : stm8s.h
  • CLK_ClearITPendingBit() : stm8s_clk.h , stm8s_clk.c
  • CLK_ClockSecuritySystemEnable() : stm8s_clk.h , stm8s_clk.c
  • CLK_ClockSwitchCmd() : stm8s_clk.h , stm8s_clk.c
  • CLK_ClockSwitchConfig() : stm8s_clk.h , stm8s_clk.c
  • CLK_CMSR_CKM : stm8s.h
  • CLK_CMSR_RESET_VALUE : stm8s.h
  • CLK_CSSCONFIG_DISABLE : stm8s_clk.h
  • CLK_CSSCONFIG_ENABLE : stm8s_clk.h
  • CLK_CSSCONFIG_ENABLEWITHIT : stm8s_clk.h
  • CLK_CSSConfig_TypeDef : stm8s_clk.h
  • CLK_CSSR_AUX : stm8s.h
  • CLK_CSSR_CSSD : stm8s.h
  • CLK_CSSR_CSSDIE : stm8s.h
  • CLK_CSSR_CSSEN : stm8s.h
  • CLK_CSSR_RESET_VALUE : stm8s.h
  • CLK_CURRENTCLOCKSTATE_DISABLE : stm8s_clk.h
  • CLK_CURRENTCLOCKSTATE_ENABLE : stm8s_clk.h
  • CLK_CurrentClockState_TypeDef : stm8s_clk.h
  • CLK_DeInit() : stm8s_clk.h , stm8s_clk.c
  • CLK_ECKR_HSEEN : stm8s.h
  • CLK_ECKR_HSERDY : stm8s.h
  • CLK_ECKR_RESET_VALUE : stm8s.h
  • CLK_FastHaltWakeUpCmd() : stm8s_clk.c , stm8s_clk.h
  • CLK_FLAG_AUX : stm8s_clk.h
  • CLK_FLAG_CCOBSY : stm8s_clk.h
  • CLK_FLAG_CCORDY : stm8s_clk.h
  • CLK_FLAG_CSSD : stm8s_clk.h
  • CLK_FLAG_HSERDY : stm8s_clk.h
  • CLK_FLAG_HSIRDY : stm8s_clk.h
  • CLK_FLAG_LSIRDY : stm8s_clk.h
  • CLK_FLAG_SWBSY : stm8s_clk.h
  • CLK_FLAG_SWIF : stm8s_clk.h
  • CLK_Flag_TypeDef : stm8s_clk.h
  • CLK_GetClockFreq() : stm8s_clk.h , stm8s_clk.c
  • CLK_GetFlagStatus() : stm8s_clk.h , stm8s_clk.c
  • CLK_GetITStatus() : stm8s_clk.h , stm8s_clk.c
  • CLK_GetSYSCLKSource() : stm8s_clk.c , stm8s_clk.h
  • CLK_HSECmd() : stm8s_clk.c , stm8s_clk.h
  • CLK_HSICmd() : stm8s_clk.c , stm8s_clk.h
  • CLK_HSIPrescalerConfig() : stm8s_clk.c , stm8s_clk.h
  • CLK_HSITRIMR_HSITRIM : stm8s.h
  • CLK_HSITRIMR_RESET_VALUE : stm8s.h
  • CLK_HSITRIMVALUE_0 : stm8s_clk.h
  • CLK_HSITRIMVALUE_1 : stm8s_clk.h
  • CLK_HSITRIMVALUE_2 : stm8s_clk.h
  • CLK_HSITRIMVALUE_3 : stm8s_clk.h
  • CLK_HSITRIMVALUE_4 : stm8s_clk.h
  • CLK_HSITRIMVALUE_5 : stm8s_clk.h
  • CLK_HSITRIMVALUE_6 : stm8s_clk.h
  • CLK_HSITRIMVALUE_7 : stm8s_clk.h
  • CLK_HSITrimValue_TypeDef : stm8s_clk.h
  • CLK_ICKR_FHWU : stm8s.h
  • CLK_ICKR_HSIEN : stm8s.h
  • CLK_ICKR_HSIRDY : stm8s.h
  • CLK_ICKR_LSIEN : stm8s.h
  • CLK_ICKR_LSIRDY : stm8s.h
  • CLK_ICKR_RESET_VALUE : stm8s.h
  • CLK_ICKR_SWUAH : stm8s.h
  • CLK_IT_CSSD : stm8s_clk.h
  • CLK_IT_SWIF : stm8s_clk.h
  • CLK_IT_TypeDef : stm8s_clk.h
  • CLK_ITConfig() : stm8s_clk.c , stm8s_clk.h
  • CLK_LSICmd() : stm8s_clk.c , stm8s_clk.h
  • CLK_OUTPUT_CPU : stm8s_clk.h
  • CLK_OUTPUT_CPUDIV16 : stm8s_clk.h
  • CLK_OUTPUT_CPUDIV2 : stm8s_clk.h
  • CLK_OUTPUT_CPUDIV32 : stm8s_clk.h
  • CLK_OUTPUT_CPUDIV4 : stm8s_clk.h
  • CLK_OUTPUT_CPUDIV64 : stm8s_clk.h
  • CLK_OUTPUT_CPUDIV8 : stm8s_clk.h
  • CLK_OUTPUT_HSE : stm8s_clk.h
  • CLK_OUTPUT_HSI : stm8s_clk.h
  • CLK_OUTPUT_HSIRC : stm8s_clk.h
  • CLK_OUTPUT_LSI : stm8s_clk.h
  • CLK_OUTPUT_MASTER : stm8s_clk.h
  • CLK_OUTPUT_OTHERS : stm8s_clk.h
  • CLK_Output_TypeDef : stm8s_clk.h
  • CLK_PCKENR1_I2C : stm8s.h
  • CLK_PCKENR1_RESET_VALUE : stm8s.h
  • CLK_PCKENR1_SPI : stm8s.h
  • CLK_PCKENR1_TIM1 : stm8s.h
  • CLK_PCKENR1_TIM2 : stm8s.h
  • CLK_PCKENR1_TIM3 : stm8s.h
  • CLK_PCKENR1_TIM4 : stm8s.h
  • CLK_PCKENR1_TIM5 : stm8s.h
  • CLK_PCKENR1_TIM6 : stm8s.h
  • CLK_PCKENR1_UART1 : stm8s.h
  • CLK_PCKENR1_UART2 : stm8s.h
  • CLK_PCKENR1_UART3 : stm8s.h
  • CLK_PCKENR2_ADC : stm8s.h
  • CLK_PCKENR2_AWU : stm8s.h
  • CLK_PCKENR2_CAN : stm8s.h
  • CLK_PCKENR2_RESET_VALUE : stm8s.h
  • CLK_PERIPHERAL_ADC : stm8s_clk.h
  • CLK_PERIPHERAL_AWU : stm8s_clk.h
  • CLK_PERIPHERAL_CAN : stm8s_clk.h
  • CLK_PERIPHERAL_I2C : stm8s_clk.h
  • CLK_PERIPHERAL_SPI : stm8s_clk.h
  • CLK_PERIPHERAL_TIMER1 : stm8s_clk.h
  • CLK_PERIPHERAL_TIMER2 : stm8s_clk.h
  • CLK_PERIPHERAL_TIMER3 : stm8s_clk.h
  • CLK_PERIPHERAL_TIMER4 : stm8s_clk.h
  • CLK_PERIPHERAL_TIMER5 : stm8s_clk.h
  • CLK_PERIPHERAL_TIMER6 : stm8s_clk.h
  • CLK_Peripheral_TypeDef : stm8s_clk.h
  • CLK_PERIPHERAL_UART1 : stm8s_clk.h
  • CLK_PERIPHERAL_UART2 : stm8s_clk.h
  • CLK_PERIPHERAL_UART3 : stm8s_clk.h
  • CLK_PeripheralClockConfig() : stm8s_clk.c , stm8s_clk.h
  • CLK_PRESCALER_CPUDIV1 : stm8s_clk.h
  • CLK_PRESCALER_CPUDIV128 : stm8s_clk.h
  • CLK_PRESCALER_CPUDIV16 : stm8s_clk.h
  • CLK_PRESCALER_CPUDIV2 : stm8s_clk.h
  • CLK_PRESCALER_CPUDIV32 : stm8s_clk.h
  • CLK_PRESCALER_CPUDIV4 : stm8s_clk.h
  • CLK_PRESCALER_CPUDIV64 : stm8s_clk.h
  • CLK_PRESCALER_CPUDIV8 : stm8s_clk.h
  • CLK_PRESCALER_HSIDIV1 : stm8s_clk.h
  • CLK_PRESCALER_HSIDIV2 : stm8s_clk.h
  • CLK_PRESCALER_HSIDIV4 : stm8s_clk.h
  • CLK_PRESCALER_HSIDIV8 : stm8s_clk.h
  • CLK_Prescaler_TypeDef : stm8s_clk.h
  • CLK_SlowActiveHaltWakeUpCmd() : stm8s_clk.h , stm8s_clk.c
  • CLK_SOURCE_HSE : stm8s_clk.h
  • CLK_SOURCE_HSI : stm8s_clk.h
  • CLK_SOURCE_LSI : stm8s_clk.h
  • CLK_Source_TypeDef : stm8s_clk.h
  • CLK_SWCR_RESET_VALUE : stm8s.h
  • CLK_SWCR_SWBSY : stm8s.h
  • CLK_SWCR_SWEN : stm8s.h
  • CLK_SWCR_SWIEN : stm8s.h
  • CLK_SWCR_SWIF : stm8s.h
  • CLK_SWIMCCR_RESET_VALUE : stm8s.h
  • CLK_SWIMCCR_SWIMDIV : stm8s.h
  • CLK_SWIMConfig() : stm8s_clk.h , stm8s_clk.c
  • CLK_SWIMDIVIDER_2 : stm8s_clk.h
  • CLK_SWIMDIVIDER_OTHER : stm8s_clk.h
  • CLK_SWIMDivider_TypeDef : stm8s_clk.h
  • CLK_SWITCHMODE_AUTO : stm8s_clk.h
  • CLK_SWITCHMODE_MANUAL : stm8s_clk.h
  • CLK_SwitchMode_TypeDef : stm8s_clk.h
  • CLK_SWR_RESET_VALUE : stm8s.h
  • CLK_SWR_SWI : stm8s.h
  • CLK_SYSCLKConfig() : stm8s_clk.h , stm8s_clk.c
  • CLK_SYSCLKEmergencyClear() : stm8s_clk.c , stm8s_clk.h
  • CLK_TIMEOUT : stm8s_clk.h
  • CLK_TypeDef : stm8s.h
  • CLKPrescTable : stm8s_clk.c
  • ClrBit : stm8s.h
  • CONST : stm8s.h
  • CPU_CC_I1I0 : stm8s.h
  • CPU_SOFT_INT_DISABLED : stm8s_itc.h


STM8S/A Standard Peripherals Drivers: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- d -

  • DISABLE : stm8s.h
  • disableInterrupts : stm8s.h
  • DM : stm8s.h
  • DM_BaseAddress : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- e -

  • EEPROM : stm8s.h
  • ENABLE : stm8s.h
  • enableInterrupts : stm8s.h
  • ERROR : stm8s.h
  • ErrorStatus : stm8s.h
  • EXTI : stm8s.h
  • EXTI_BaseAddress : stm8s.h
  • EXTI_CR1_PAIS : stm8s.h
  • EXTI_CR1_PBIS : stm8s.h
  • EXTI_CR1_PCIS : stm8s.h
  • EXTI_CR1_PDIS : stm8s.h
  • EXTI_CR1_RESET_VALUE : stm8s.h
  • EXTI_CR2_PEIS : stm8s.h
  • EXTI_CR2_RESET_VALUE : stm8s.h
  • EXTI_CR2_TLIS : stm8s.h
  • EXTI_DeInit() : stm8s_exti.h , stm8s_exti.c
  • EXTI_GetExtIntSensitivity() : stm8s_exti.h , stm8s_exti.c
  • EXTI_GetTLISensitivity() : stm8s_exti.h , stm8s_exti.c
  • EXTI_PORT_GPIOA : stm8s_exti.h
  • EXTI_PORT_GPIOB : stm8s_exti.h
  • EXTI_PORT_GPIOC : stm8s_exti.h
  • EXTI_PORT_GPIOD : stm8s_exti.h
  • EXTI_PORT_GPIOE : stm8s_exti.h
  • EXTI_Port_TypeDef : stm8s_exti.h
  • EXTI_SENSITIVITY_FALL_LOW : stm8s_exti.h
  • EXTI_SENSITIVITY_FALL_ONLY : stm8s_exti.h
  • EXTI_SENSITIVITY_RISE_FALL : stm8s_exti.h
  • EXTI_SENSITIVITY_RISE_ONLY : stm8s_exti.h
  • EXTI_Sensitivity_TypeDef : stm8s_exti.h
  • EXTI_SetExtIntSensitivity() : stm8s_exti.h , stm8s_exti.c
  • EXTI_SetTLISensitivity() : stm8s_exti.c , stm8s_exti.h
  • EXTI_TLISENSITIVITY_FALL_ONLY : stm8s_exti.h
  • EXTI_TLISENSITIVITY_RISE_ONLY : stm8s_exti.h
  • EXTI_TLISensitivity_TypeDef : stm8s_exti.h
  • EXTI_TypeDef : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- f -

  • FALSE : stm8s.h
  • FAR : stm8s.h
  • FLAG_Mask : stm8s_i2c.c
  • FlagStatus : stm8s.h
  • FLASH : stm8s.h
  • FLASH_BaseAddress : stm8s.h
  • FLASH_CLEAR_BYTE : stm8s_flash.c
  • FLASH_CR1_AHALT : stm8s.h
  • FLASH_CR1_FIX : stm8s.h
  • FLASH_CR1_HALT : stm8s.h
  • FLASH_CR1_IE : stm8s.h
  • FLASH_CR1_RESET_VALUE : stm8s.h
  • FLASH_CR2_ERASE : stm8s.h
  • FLASH_CR2_FPRG : stm8s.h
  • FLASH_CR2_OPT : stm8s.h
  • FLASH_CR2_PRG : stm8s.h
  • FLASH_CR2_RESET_VALUE : stm8s.h
  • FLASH_CR2_WPRG : stm8s.h
  • FLASH_DeInit() : stm8s_flash.h , stm8s_flash.c
  • FLASH_DUKR_DUK : stm8s.h
  • FLASH_DUKR_RESET_VALUE : stm8s.h
  • FLASH_EraseByte() : stm8s_flash.h , stm8s_flash.c
  • FLASH_EraseOptionByte() : stm8s_flash.h , stm8s_flash.c
  • FLASH_FLAG_DUL : stm8s_flash.h
  • FLASH_FLAG_EOP : stm8s_flash.h
  • FLASH_FLAG_PUL : stm8s_flash.h
  • FLASH_Flag_TypeDef : stm8s_flash.h
  • FLASH_FLAG_WR_PG_DIS : stm8s_flash.h
  • FLASH_GetBootSize() : stm8s_flash.h , stm8s_flash.c
  • FLASH_GetFlagStatus() : stm8s_flash.h , stm8s_flash.c
  • FLASH_GetLowPowerMode() : stm8s_flash.h , stm8s_flash.c
  • FLASH_GetProgrammingTime() : stm8s_flash.h , stm8s_flash.c
  • FLASH_IAPSR_DUL : stm8s.h
  • FLASH_IAPSR_EOP : stm8s.h
  • FLASH_IAPSR_HVOFF : stm8s.h
  • FLASH_IAPSR_PUL : stm8s.h
  • FLASH_IAPSR_RESET_VALUE : stm8s.h
  • FLASH_IAPSR_WR_PG_DIS : stm8s.h
  • FLASH_ITConfig() : stm8s_flash.h , stm8s_flash.c
  • FLASH_Lock() : stm8s_flash.h , stm8s_flash.c
  • FLASH_LPMODE_POWERDOWN : stm8s_flash.h
  • FLASH_LPMODE_POWERDOWN_STANDBY : stm8s_flash.h
  • FLASH_LPMODE_STANDBY : stm8s_flash.h
  • FLASH_LPMODE_STANDBY_POWERDOWN : stm8s_flash.h
  • FLASH_LPMode_TypeDef : stm8s_flash.h
  • FLASH_MEMTYPE_DATA : stm8s_flash.h
  • FLASH_MEMTYPE_PROG : stm8s_flash.h
  • FLASH_MemType_TypeDef : stm8s_flash.h
  • FLASH_NCR2_NERASE : stm8s.h
  • FLASH_NCR2_NFPRG : stm8s.h
  • FLASH_NCR2_NOPT : stm8s.h
  • FLASH_NCR2_NPRG : stm8s.h
  • FLASH_NCR2_NWPRG : stm8s.h
  • FLASH_NCR2_RESET_VALUE : stm8s.h
  • FLASH_OPTIONBYTE_ERROR : stm8s_flash.h
  • FLASH_PROG_START_PHYSICAL_ADDRESS : stm8s_flash.h
  • FLASH_ProgramByte() : stm8s_flash.c , stm8s_flash.h
  • FLASH_PROGRAMMODE_FAST : stm8s_flash.h
  • FLASH_PROGRAMMODE_STANDARD : stm8s_flash.h
  • FLASH_ProgramMode_TypeDef : stm8s_flash.h
  • FLASH_ProgramOptionByte() : stm8s_flash.c , stm8s_flash.h
  • FLASH_PROGRAMTIME_STANDARD : stm8s_flash.h
  • FLASH_PROGRAMTIME_TPROG : stm8s_flash.h
  • FLASH_ProgramTime_TypeDef : stm8s_flash.h
  • FLASH_ProgramWord() : stm8s_flash.h , stm8s_flash.c
  • FLASH_PUKR_PUK : stm8s.h
  • FLASH_PUKR_RESET_VALUE : stm8s.h
  • FLASH_RASS_KEY1 : stm8s_flash.h
  • FLASH_RASS_KEY2 : stm8s_flash.h
  • FLASH_ReadByte() : stm8s_flash.c , stm8s_flash.h
  • FLASH_ReadOptionByte() : stm8s_flash.h , stm8s_flash.c
  • FLASH_SET_BYTE : stm8s_flash.c
  • FLASH_SetLowPowerMode() : stm8s_flash.c , stm8s_flash.h
  • FLASH_SetProgrammingTime() : stm8s_flash.h , stm8s_flash.c
  • FLASH_STATUS_SUCCESSFUL_OPERATION : stm8s_flash.h
  • FLASH_STATUS_TIMEOUT : stm8s_flash.h
  • FLASH_Status_TypeDef : stm8s_flash.h
  • FLASH_STATUS_WRITE_PROTECTION_ERROR : stm8s_flash.h
  • FLASH_TypeDef : stm8s.h
  • FLASH_Unlock() : stm8s_flash.c , stm8s_flash.h
  • FunctionalState : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- g -

  • GPIO_CR1_RESET_VALUE : stm8s.h
  • GPIO_CR2_RESET_VALUE : stm8s.h
  • GPIO_DDR_RESET_VALUE : stm8s.h
  • GPIO_DeInit() : stm8s_gpio.h , stm8s_gpio.c
  • GPIO_ExternalPullUpConfig() : stm8s_gpio.h , stm8s_gpio.c
  • GPIO_Init() : stm8s_gpio.h , stm8s_gpio.c
  • GPIO_MODE_IN_FL_IT : stm8s_gpio.h
  • GPIO_MODE_IN_FL_NO_IT : stm8s_gpio.h
  • GPIO_MODE_IN_PU_IT : stm8s_gpio.h
  • GPIO_MODE_IN_PU_NO_IT : stm8s_gpio.h
  • GPIO_MODE_OUT_OD_HIZ_FAST : stm8s_gpio.h
  • GPIO_MODE_OUT_OD_HIZ_SLOW : stm8s_gpio.h
  • GPIO_MODE_OUT_OD_LOW_FAST : stm8s_gpio.h
  • GPIO_MODE_OUT_OD_LOW_SLOW : stm8s_gpio.h
  • GPIO_MODE_OUT_PP_HIGH_FAST : stm8s_gpio.h
  • GPIO_MODE_OUT_PP_HIGH_SLOW : stm8s_gpio.h
  • GPIO_MODE_OUT_PP_LOW_FAST : stm8s_gpio.h
  • GPIO_MODE_OUT_PP_LOW_SLOW : stm8s_gpio.h
  • GPIO_Mode_TypeDef : stm8s_gpio.h
  • GPIO_ODR_RESET_VALUE : stm8s.h
  • GPIO_PIN_0 : stm8s_gpio.h
  • GPIO_PIN_1 : stm8s_gpio.h
  • GPIO_PIN_2 : stm8s_gpio.h
  • GPIO_PIN_3 : stm8s_gpio.h
  • GPIO_PIN_4 : stm8s_gpio.h
  • GPIO_PIN_5 : stm8s_gpio.h
  • GPIO_PIN_6 : stm8s_gpio.h
  • GPIO_PIN_7 : stm8s_gpio.h
  • GPIO_PIN_ALL : stm8s_gpio.h
  • GPIO_PIN_HNIB : stm8s_gpio.h
  • GPIO_PIN_LNIB : stm8s_gpio.h
  • GPIO_Pin_TypeDef : stm8s_gpio.h
  • GPIO_ReadInputData() : stm8s_gpio.h , stm8s_gpio.c
  • GPIO_ReadInputPin() : stm8s_gpio.h , stm8s_gpio.c
  • GPIO_ReadOutputData() : stm8s_gpio.h , stm8s_gpio.c
  • GPIO_TypeDef : stm8s.h
  • GPIO_Write() : stm8s_gpio.c , stm8s_gpio.h
  • GPIO_WriteHigh() : stm8s_gpio.h , stm8s_gpio.c
  • GPIO_WriteLow() : stm8s_gpio.h , stm8s_gpio.c
  • GPIO_WriteReverse() : stm8s_gpio.c , stm8s_gpio.h
  • GPIOA : stm8s.h
  • GPIOA_BaseAddress : stm8s.h
  • GPIOB : stm8s.h
  • GPIOB_BaseAddress : stm8s.h
  • GPIOC : stm8s.h
  • GPIOC_BaseAddress : stm8s.h
  • GPIOD : stm8s.h
  • GPIOD_BaseAddress : stm8s.h
  • GPIOE : stm8s.h
  • GPIOE_BaseAddress : stm8s.h
  • GPIOF : stm8s.h
  • GPIOF_BaseAddress : stm8s.h
  • GPIOG_BaseAddress : stm8s.h
  • GPIOH_BaseAddress : stm8s.h
  • GPIOI_BaseAddress : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

  • File List
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- h -

  • halt : stm8s.h
  • HSE_VALUE : stm8s.h
  • HSI_VALUE : stm8s.h
  • HSIDivFactor : stm8s_clk.c


STM8S/A Standard Peripherals Drivers: Globals

  • File List
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  • Variables
  • Typedefs
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- i -

  • I2C : stm8s.h
  • I2C_ACK_CURR : stm8s_i2c.h
  • I2C_ACK_NEXT : stm8s_i2c.h
  • I2C_ACK_NONE : stm8s_i2c.h
  • I2C_Ack_TypeDef : stm8s_i2c.h
  • I2C_AcknowledgeConfig() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_ADDMODE_10BIT : stm8s_i2c.h
  • I2C_ADDMODE_7BIT : stm8s_i2c.h
  • I2C_AddMode_TypeDef : stm8s_i2c.h
  • I2C_BaseAddress : stm8s.h
  • I2C_CCRH_CCR : stm8s.h
  • I2C_CCRH_DUTY : stm8s.h
  • I2C_CCRH_FS : stm8s.h
  • I2C_CCRH_RESET_VALUE : stm8s.h
  • I2C_CCRL_CCR : stm8s.h
  • I2C_CCRL_RESET_VALUE : stm8s.h
  • I2C_CheckEvent() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_ClearFlag() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_ClearITPendingBit() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_Cmd() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_CR1_ENGC : stm8s.h
  • I2C_CR1_NOSTRETCH : stm8s.h
  • I2C_CR1_PE : stm8s.h
  • I2C_CR1_RESET_VALUE : stm8s.h
  • I2C_CR2_ACK : stm8s.h
  • I2C_CR2_POS : stm8s.h
  • I2C_CR2_RESET_VALUE : stm8s.h
  • I2C_CR2_START : stm8s.h
  • I2C_CR2_STOP : stm8s.h
  • I2C_CR2_SWRST : stm8s.h
  • I2C_DeInit() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_DIRECTION_RX : stm8s_i2c.h
  • I2C_DIRECTION_TX : stm8s_i2c.h
  • I2C_Direction_TypeDef : stm8s_i2c.h
  • I2C_DR_DR : stm8s.h
  • I2C_DR_RESET_VALUE : stm8s.h
  • I2C_DUTYCYCLE_16_9 : stm8s_i2c.h
  • I2C_DUTYCYCLE_2 : stm8s_i2c.h
  • I2C_DutyCycle_TypeDef : stm8s_i2c.h
  • I2C_EVENT_MASTER_BYTE_RECEIVED : stm8s_i2c.h
  • I2C_EVENT_MASTER_BYTE_TRANSMITTED : stm8s_i2c.h
  • I2C_EVENT_MASTER_BYTE_TRANSMITTING : stm8s_i2c.h
  • I2C_EVENT_MASTER_MODE_ADDRESS10 : stm8s_i2c.h
  • I2C_EVENT_MASTER_MODE_SELECT : stm8s_i2c.h
  • I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : stm8s_i2c.h
  • I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : stm8s_i2c.h
  • I2C_EVENT_SLAVE_ACK_FAILURE : stm8s_i2c.h
  • I2C_EVENT_SLAVE_BYTE_RECEIVED : stm8s_i2c.h
  • I2C_EVENT_SLAVE_BYTE_TRANSMITTED : stm8s_i2c.h
  • I2C_EVENT_SLAVE_BYTE_TRANSMITTING : stm8s_i2c.h
  • I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : stm8s_i2c.h
  • I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : stm8s_i2c.h
  • I2C_EVENT_SLAVE_STOP_DETECTED : stm8s_i2c.h
  • I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : stm8s_i2c.h
  • I2C_Event_TypeDef : stm8s_i2c.h
  • I2C_FastModeDutyCycleConfig() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_FLAG_ACKNOWLEDGEFAILURE : stm8s_i2c.h
  • I2C_FLAG_ADDRESSSENTMATCHED : stm8s_i2c.h
  • I2C_FLAG_ARBITRATIONLOSS : stm8s_i2c.h
  • I2C_FLAG_BUSBUSY : stm8s_i2c.h
  • I2C_FLAG_BUSERROR : stm8s_i2c.h
  • I2C_FLAG_GENERALCALL : stm8s_i2c.h
  • I2C_FLAG_HEADERSENT : stm8s_i2c.h
  • I2C_FLAG_MASTERSLAVE : stm8s_i2c.h
  • I2C_FLAG_OVERRUNUNDERRUN : stm8s_i2c.h
  • I2C_FLAG_RXNOTEMPTY : stm8s_i2c.h
  • I2C_FLAG_STARTDETECTION : stm8s_i2c.h
  • I2C_FLAG_STOPDETECTION : stm8s_i2c.h
  • I2C_FLAG_TRANSFERFINISHED : stm8s_i2c.h
  • I2C_FLAG_TRANSMITTERRECEIVER : stm8s_i2c.h
  • I2C_FLAG_TXEMPTY : stm8s_i2c.h
  • I2C_Flag_TypeDef : stm8s_i2c.h
  • I2C_FLAG_WAKEUPFROMHALT : stm8s_i2c.h
  • I2C_FREQR_FREQ : stm8s.h
  • I2C_FREQR_RESET_VALUE : stm8s.h
  • I2C_GeneralCallCmd() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_GenerateSTART() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_GenerateSTOP() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_GetFlagStatus() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_GetITStatus() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_GetLastEvent() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_Init() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_IT_BUF : stm8s_i2c.h
  • I2C_IT_ERR : stm8s_i2c.h
  • I2C_IT_EVT : stm8s_i2c.h
  • I2C_IT_TypeDef : stm8s_i2c.h
  • I2C_ITConfig() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE : stm8s_i2c.h
  • I2C_ITPENDINGBIT_ADDRESSSENTMATCHED : stm8s_i2c.h
  • I2C_ITPENDINGBIT_ARBITRATIONLOSS : stm8s_i2c.h
  • I2C_ITPENDINGBIT_BUSERROR : stm8s_i2c.h
  • I2C_ITPENDINGBIT_HEADERSENT : stm8s_i2c.h
  • I2C_ITPENDINGBIT_OVERRUNUNDERRUN : stm8s_i2c.h
  • I2C_ITPENDINGBIT_RXNOTEMPTY : stm8s_i2c.h
  • I2C_ITPENDINGBIT_STARTDETECTION : stm8s_i2c.h
  • I2C_ITPENDINGBIT_STOPDETECTION : stm8s_i2c.h
  • I2C_ITPENDINGBIT_TRANSFERFINISHED : stm8s_i2c.h
  • I2C_ITPENDINGBIT_TXEMPTY : stm8s_i2c.h
  • I2C_ITPendingBit_TypeDef : stm8s_i2c.h
  • I2C_ITPENDINGBIT_WAKEUPFROMHALT : stm8s_i2c.h
  • I2C_ITR_ITBUFEN : stm8s.h
  • I2C_ITR_ITERREN : stm8s.h
  • I2C_ITR_ITEVTEN : stm8s.h
  • I2C_ITR_RESET_VALUE : stm8s.h
  • I2C_MAX_FAST_FREQ : stm8s_i2c.h
  • I2C_MAX_INPUT_FREQ : stm8s_i2c.h
  • I2C_MAX_STANDARD_FREQ : stm8s_i2c.h
  • I2C_OARH_ADD : stm8s.h
  • I2C_OARH_ADDCONF : stm8s.h
  • I2C_OARH_ADDMODE : stm8s.h
  • I2C_OARH_RESET_VALUE : stm8s.h
  • I2C_OARL_ADD : stm8s.h
  • I2C_OARL_ADD0 : stm8s.h
  • I2C_OARL_RESET_VALUE : stm8s.h
  • I2C_ReceiveData() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_Send7bitAddress() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_SendData() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_SoftwareResetCmd() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_SR1_ADD10 : stm8s.h
  • I2C_SR1_ADDR : stm8s.h
  • I2C_SR1_BTF : stm8s.h
  • I2C_SR1_RESET_VALUE : stm8s.h
  • I2C_SR1_RXNE : stm8s.h
  • I2C_SR1_SB : stm8s.h
  • I2C_SR1_STOPF : stm8s.h
  • I2C_SR1_TXE : stm8s.h
  • I2C_SR2_AF : stm8s.h
  • I2C_SR2_ARLO : stm8s.h
  • I2C_SR2_BERR : stm8s.h
  • I2C_SR2_OVR : stm8s.h
  • I2C_SR2_RESET_VALUE : stm8s.h
  • I2C_SR2_WUFH : stm8s.h
  • I2C_SR3_BUSY : stm8s.h
  • I2C_SR3_GENCALL : stm8s.h
  • I2C_SR3_MSL : stm8s.h
  • I2C_SR3_RESET_VALUE : stm8s.h
  • I2C_SR3_TRA : stm8s.h
  • I2C_StretchClockCmd() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_TRISER_RESET_VALUE : stm8s.h
  • I2C_TRISER_TRISE : stm8s.h
  • I2C_TypeDef : stm8s.h
  • IN_RAM : stm8s.h , stm8s_flash.h
  • int16_t : stm8s.h
  • int32_t : stm8s.h
  • int8_t : stm8s.h
  • IS_ADC1_ALIGN_OK : stm8s_adc1.h
  • IS_ADC1_BUFFER_OK : stm8s_adc1.h
  • IS_ADC1_CHANNEL_OK : stm8s_adc1.h
  • IS_ADC1_CONVERSIONMODE_OK : stm8s_adc1.h
  • IS_ADC1_EXTTRIG_OK : stm8s_adc1.h
  • IS_ADC1_FLAG_OK : stm8s_adc1.h
  • IS_ADC1_IT_OK : stm8s_adc1.h
  • IS_ADC1_ITPENDINGBIT_OK : stm8s_adc1.h
  • IS_ADC1_PRESSEL_OK : stm8s_adc1.h
  • IS_ADC1_SCHMITTTRIG_OK : stm8s_adc1.h
  • IS_ADC2_ALIGN_OK : stm8s_adc2.h
  • IS_ADC2_CHANNEL_OK : stm8s_adc2.h
  • IS_ADC2_CONVERSIONMODE_OK : stm8s_adc2.h
  • IS_ADC2_EXTTRIG_OK : stm8s_adc2.h
  • IS_ADC2_PRESSEL_OK : stm8s_adc2.h
  • IS_ADC2_SCHMITTTRIG_OK : stm8s_adc2.h
  • IS_AWU_TIMEBASE_OK : stm8s_awu.h
  • IS_BEEP_FREQUENCY_OK : stm8s_beep.h
  • IS_CAN_BITSEG1_OK : stm8s_can.h
  • IS_CAN_BITSEG2_OK : stm8s_can.h
  • IS_CAN_DLC_OK : stm8s_can.h
  • IS_CAN_EXTID_OK : stm8s_can.h
  • IS_CAN_FILTER_MODE_OK : stm8s_can.h
  • IS_CAN_FILTER_NUMBER_OK : stm8s_can.h
  • IS_CAN_FILTER_SCALE_OK : stm8s_can.h
  • IS_CAN_FLAG_CLEAR_OK : stm8s_can.h
  • IS_CAN_FLAG_STATUS_OK : stm8s_can.h
  • IS_CAN_IDTYPE_OK : stm8s_can.h
  • IS_CAN_IT_CONFIG_OK : stm8s_can.h
  • IS_CAN_IT_PENDING_BIT_OK : stm8s_can.h
  • IS_CAN_IT_STATUS_OK : stm8s_can.h
  • IS_CAN_LAST_ERROR_CODE_OK : stm8s_can.h
  • IS_CAN_MASTERCTRL_OK : stm8s_can.h
  • IS_CAN_MODE_OK : stm8s_can.h
  • IS_CAN_OPERATINGMODE_OK : stm8s_can.h
  • IS_CAN_PRESCALER_OK : stm8s_can.h
  • IS_CAN_RTR_OK : stm8s_can.h
  • IS_CAN_ST7_COMPATIBILITY_OK : stm8s_can.h
  • IS_CAN_STDID_OK : stm8s_can.h
  • IS_CAN_SYNJUMPWIDTH_OK : stm8s_can.h
  • IS_CAN_TRANSMITMAILBOX_OK : stm8s_can.h
  • IS_CLK_CSSCONFIG_OK : stm8s_clk.h
  • IS_CLK_CURRENTCLOCKSTATE_OK : stm8s_clk.h
  • IS_CLK_FLAG_OK : stm8s_clk.h
  • IS_CLK_HSIPRESCALER_OK : stm8s_clk.h
  • IS_CLK_HSITRIMVALUE_OK : stm8s_clk.h
  • IS_CLK_IT_OK : stm8s_clk.h
  • IS_CLK_OUTPUT_OK : stm8s_clk.h
  • IS_CLK_PERIPHERAL_OK : stm8s_clk.h
  • IS_CLK_PRESCALER_OK : stm8s_clk.h
  • IS_CLK_SOURCE_OK : stm8s_clk.h
  • IS_CLK_SWIMDIVIDER_OK : stm8s_clk.h
  • IS_CLK_SWITCHMODE_OK : stm8s_clk.h
  • IS_EXTI_PINMASK_OK : stm8s_exti.h
  • IS_EXTI_PORT_OK : stm8s_exti.h
  • IS_EXTI_SENSITIVITY_OK : stm8s_exti.h
  • IS_EXTI_TLISENSITIVITY_OK : stm8s_exti.h
  • IS_FLASH_ADDRESS_OK : stm8s_flash.h
  • IS_FLASH_DATA_ADDRESS_OK : stm8s_flash.h
  • IS_FLASH_DATA_BLOCK_NUMBER_OK : stm8s_flash.h
  • IS_FLASH_FLAGS_OK : stm8s_flash.h
  • IS_FLASH_LOW_POWER_MODE_OK : stm8s_flash.h
  • IS_FLASH_PROG_ADDRESS_OK : stm8s_flash.h
  • IS_FLASH_PROG_BLOCK_NUMBER_OK : stm8s_flash.h
  • IS_FLASH_PROGRAM_MODE_OK : stm8s_flash.h
  • IS_FLASH_PROGRAM_TIME_OK : stm8s_flash.h
  • IS_FUNCTIONALSTATE_OK : stm8s.h
  • IS_GPIO_MODE_OK : stm8s_gpio.h
  • IS_GPIO_PIN_OK : stm8s_gpio.h
  • IS_I2C_ACK_OK : stm8s_i2c.h
  • IS_I2C_ADDMODE_OK : stm8s_i2c.h
  • IS_I2C_ADDRESS_OK : stm8s_i2c.h
  • IS_I2C_CLEAR_FLAG_OK : stm8s_i2c.h
  • IS_I2C_CLEAR_ITPENDINGBIT_OK : stm8s_i2c.h
  • IS_I2C_DIRECTION_OK : stm8s_i2c.h
  • IS_I2C_DUTYCYCLE_OK : stm8s_i2c.h
  • IS_I2C_EVENT_OK : stm8s_i2c.h
  • IS_I2C_FLAG_OK : stm8s_i2c.h
  • IS_I2C_INPUT_CLOCK_FREQ_OK : stm8s_i2c.h
  • IS_I2C_INTERRUPT_OK : stm8s_i2c.h
  • IS_I2C_ITPENDINGBIT_OK : stm8s_i2c.h
  • IS_I2C_OUTPUT_CLOCK_FREQ_OK : stm8s_i2c.h
  • IS_I2C_OWN_ADDRESS_OK : stm8s_i2c.h
  • IS_ITC_INTERRUPTS_DISABLED : stm8s_itc.h
  • IS_ITC_IRQ_OK : stm8s_itc.h
  • IS_ITC_PRIORITY_OK : stm8s_itc.h
  • IS_IWDG_PRESCALER_OK : stm8s_iwdg.h
  • IS_IWDG_WRITEACCESS_MODE_OK : stm8s_iwdg.h
  • IS_LSI_FREQUENCY_OK : stm8s_awu.h , stm8s_beep.h
  • IS_MEMORY_TYPE_OK : stm8s_flash.h
  • IS_OPTION_BYTE_ADDRESS_OK : stm8s_flash.h
  • IS_RST_FLAG_OK : stm8s_rst.h
  • IS_SPI_BAUDRATE_PRESCALER_OK : stm8s_spi.h
  • IS_SPI_CLEAR_FLAGS_OK : stm8s_spi.h
  • IS_SPI_CLEAR_IT_OK : stm8s_spi.h
  • IS_SPI_CONFIG_IT_OK : stm8s_spi.h
  • IS_SPI_CRC_OK : stm8s_spi.h
  • IS_SPI_CRC_POLYNOMIAL_OK : stm8s_spi.h
  • IS_SPI_DATA_DIRECTION_OK : stm8s_spi.h
  • IS_SPI_DIRECTION_OK : stm8s_spi.h
  • IS_SPI_FIRSTBIT_OK : stm8s_spi.h
  • IS_SPI_FLAGS_OK : stm8s_spi.h
  • IS_SPI_GET_IT_OK : stm8s_spi.h
  • IS_SPI_MODE_OK : stm8s_spi.h
  • IS_SPI_PHASE_OK : stm8s_spi.h
  • IS_SPI_POLARITY_OK : stm8s_spi.h
  • IS_SPI_SLAVEMANAGEMENT_OK : stm8s_spi.h
  • IS_STATE_VALUE_OK : stm8s.h
  • IS_TIM1_AUTOMATIC_OUTPUT_STATE_OK : stm8s_tim1.h
  • IS_TIM1_BREAK_POLARITY_OK : stm8s_tim1.h
  • IS_TIM1_BREAK_STATE_OK : stm8s_tim1.h
  • IS_TIM1_CHANNEL_OK : stm8s_tim1.h
  • IS_TIM1_CLEAR_FLAG_OK : stm8s_tim1.h
  • IS_TIM1_COMPLEMENTARY_CHANNEL_OK : stm8s_tim1.h
  • IS_TIM1_COUNTER_MODE_OK : stm8s_tim1.h
  • IS_TIM1_ENCODER_MODE_OK : stm8s_tim1.h
  • IS_TIM1_EVENT_SOURCE_OK : stm8s_tim1.h
  • IS_TIM1_EXT_POLARITY_OK : stm8s_tim1.h
  • IS_TIM1_EXT_PRESCALER_OK : stm8s_tim1.h
  • IS_TIM1_EXT_TRG_FILTER_OK : stm8s_tim1.h
  • IS_TIM1_FORCED_ACTION_OK : stm8s_tim1.h
  • IS_TIM1_GET_FLAG_OK : stm8s_tim1.h
  • IS_TIM1_GET_IT_OK : stm8s_tim1.h
  • IS_TIM1_IC_FILTER_OK : stm8s_tim1.h
  • IS_TIM1_IC_POLARITY_OK : stm8s_tim1.h
  • IS_TIM1_IC_PRESCALER_OK : stm8s_tim1.h
  • IS_TIM1_IC_SELECTION_OK : stm8s_tim1.h
  • IS_TIM1_IT_OK : stm8s_tim1.h
  • IS_TIM1_LOCK_LEVEL_OK : stm8s_tim1.h
  • IS_TIM1_OC_MODE_OK : stm8s_tim1.h
  • IS_TIM1_OC_POLARITY_OK : stm8s_tim1.h
  • IS_TIM1_OCIDLE_STATE_OK : stm8s_tim1.h
  • IS_TIM1_OCM_OK : stm8s_tim1.h
  • IS_TIM1_OCN_POLARITY_OK : stm8s_tim1.h
  • IS_TIM1_OCNIDLE_STATE_OK : stm8s_tim1.h
  • IS_TIM1_OPM_MODE_OK : stm8s_tim1.h
  • IS_TIM1_OSSI_STATE_OK : stm8s_tim1.h
  • IS_TIM1_OUTPUT_STATE_OK : stm8s_tim1.h
  • IS_TIM1_OUTPUTN_STATE_OK : stm8s_tim1.h
  • IS_TIM1_PRESCALER_RELOAD_OK : stm8s_tim1.h
  • IS_TIM1_PWMI_CHANNEL_OK : stm8s_tim1.h
  • IS_TIM1_SLAVE_MODE_OK : stm8s_tim1.h
  • IS_TIM1_TIX_TRIGGER_SELECTION_OK : stm8s_tim1.h
  • IS_TIM1_TIXCLK_SOURCE_OK : stm8s_tim1.h
  • IS_TIM1_TRGO_SOURCE_OK : stm8s_tim1.h
  • IS_TIM1_TRIGGER_SELECTION_OK : stm8s_tim1.h
  • IS_TIM1_UPDATE_SOURCE_OK : stm8s_tim1.h
  • IS_TIM2_CHANNEL_OK : stm8s_tim2.h
  • IS_TIM2_CLEAR_FLAG_OK : stm8s_tim2.h
  • IS_TIM2_EVENT_SOURCE_OK : stm8s_tim2.h
  • IS_TIM2_FORCED_ACTION_OK : stm8s_tim2.h
  • IS_TIM2_GET_FLAG_OK : stm8s_tim2.h
  • IS_TIM2_GET_IT_OK : stm8s_tim2.h
  • IS_TIM2_IC_FILTER_OK : stm8s_tim2.h
  • IS_TIM2_IC_POLARITY_OK : stm8s_tim2.h
  • IS_TIM2_IC_PRESCALER_OK : stm8s_tim2.h
  • IS_TIM2_IC_SELECTION1_OK : stm8s_tim2.h
  • IS_TIM2_IC_SELECTION_OK : stm8s_tim2.h
  • IS_TIM2_IT_OK : stm8s_tim2.h
  • IS_TIM2_OC_MODE_OK : stm8s_tim2.h
  • IS_TIM2_OC_POLARITY_OK : stm8s_tim2.h
  • IS_TIM2_OCM_OK : stm8s_tim2.h
  • IS_TIM2_OPM_MODE_OK : stm8s_tim2.h
  • IS_TIM2_OUTPUT_STATE_OK : stm8s_tim2.h
  • IS_TIM2_PRESCALER_OK : stm8s_tim2.h
  • IS_TIM2_PRESCALER_RELOAD_OK : stm8s_tim2.h
  • IS_TIM2_PWMI_CHANNEL_OK : stm8s_tim2.h
  • IS_TIM2_UPDATE_SOURCE_OK : stm8s_tim2.h
  • IS_TIM3_CHANNEL_OK : stm8s_tim3.h
  • IS_TIM3_CLEAR_FLAG_OK : stm8s_tim3.h
  • IS_TIM3_EVENT_SOURCE_OK : stm8s_tim3.h
  • IS_TIM3_FORCED_ACTION_OK : stm8s_tim3.h
  • IS_TIM3_GET_FLAG_OK : stm8s_tim3.h
  • IS_TIM3_GET_IT_OK : stm8s_tim3.h
  • IS_TIM3_IC_FILTER_OK : stm8s_tim3.h
  • IS_TIM3_IC_POLARITY_OK : stm8s_tim3.h
  • IS_TIM3_IC_PRESCALER_OK : stm8s_tim3.h
  • IS_TIM3_IC_SELECTION_OK : stm8s_tim3.h
  • IS_TIM3_IT_OK : stm8s_tim3.h
  • IS_TIM3_OC_MODE_OK : stm8s_tim3.h
  • IS_TIM3_OC_POLARITY_OK : stm8s_tim3.h
  • IS_TIM3_OCM_OK : stm8s_tim3.h
  • IS_TIM3_OPM_MODE_OK : stm8s_tim3.h
  • IS_TIM3_OUTPUT_STATE_OK : stm8s_tim3.h
  • IS_TIM3_PRESCALER_OK : stm8s_tim3.h
  • IS_TIM3_PRESCALER_RELOAD_OK : stm8s_tim3.h
  • IS_TIM3_PWMI_CHANNEL_OK : stm8s_tim3.h
  • IS_TIM3_UPDATE_SOURCE_OK : stm8s_tim3.h
  • IS_TIM4_EVENT_SOURCE_OK : stm8s_tim4.h
  • IS_TIM4_GET_FLAG_OK : stm8s_tim4.h
  • IS_TIM4_IT_OK : stm8s_tim4.h
  • IS_TIM4_OPM_MODE_OK : stm8s_tim4.h
  • IS_TIM4_PRESCALER_OK : stm8s_tim4.h
  • IS_TIM4_PRESCALER_RELOAD_OK : stm8s_tim4.h
  • IS_TIM4_UPDATE_SOURCE_OK : stm8s_tim4.h
  • IS_TIM5_CHANNEL_OK : stm8s_tim5.h
  • IS_TIM5_CLEAR_FLAG_OK : stm8s_tim5.h
  • IS_TIM5_ENCODER_MODE_OK : stm8s_tim5.h
  • IS_TIM5_EVENT_SOURCE_OK : stm8s_tim5.h
  • IS_TIM5_EXT_FILTER_OK : stm8s_tim5.h
  • IS_TIM5_EXT_POLARITY_OK : stm8s_tim5.h
  • IS_TIM5_EXT_PRESCALER_OK : stm8s_tim5.h
  • IS_TIM5_FORCED_ACTION_OK : stm8s_tim5.h
  • IS_TIM5_GET_FLAG_OK : stm8s_tim5.h
  • IS_TIM5_GET_IT_OK : stm8s_tim5.h
  • IS_TIM5_IC_FILTER_OK : stm8s_tim5.h
  • IS_TIM5_IC_POLARITY_OK : stm8s_tim5.h
  • IS_TIM5_IC_PRESCALER_OK : stm8s_tim5.h
  • IS_TIM5_IC_SELECTION1_OK : stm8s_tim5.h
  • IS_TIM5_IC_SELECTION_OK : stm8s_tim5.h
  • IS_TIM5_IT_OK : stm8s_tim5.h
  • IS_TIM5_OC_MODE_OK : stm8s_tim5.h
  • IS_TIM5_OC_POLARITY_OK : stm8s_tim5.h
  • IS_TIM5_OCM_OK : stm8s_tim5.h
  • IS_TIM5_OPM_MODE_OK : stm8s_tim5.h
  • IS_TIM5_OUTPUT_STATE_OK : stm8s_tim5.h
  • IS_TIM5_PRESCALER_OK : stm8s_tim5.h
  • IS_TIM5_PRESCALER_RELOAD_OK : stm8s_tim5.h
  • IS_TIM5_PWMI_CHANNEL_OK : stm8s_tim5.h
  • IS_TIM5_SLAVE_MODE_OK : stm8s_tim5.h
  • IS_TIM5_TIX_TRIGGER_SELECTION_OK : stm8s_tim5.h
  • IS_TIM5_TRGO_SOURCE_OK : stm8s_tim5.h
  • IS_TIM5_TRIGGER_SELECTION_OK : stm8s_tim5.h
  • IS_TIM5_UPDATE_SOURCE_OK : stm8s_tim5.h
  • IS_TIM6_CLEAR_FLAG_OK : stm8s_tim6.h
  • IS_TIM6_EVENT_SOURCE_OK : stm8s_tim6.h
  • IS_TIM6_GET_FLAG_OK : stm8s_tim6.h
  • IS_TIM6_GET_IT_OK : stm8s_tim6.h
  • IS_TIM6_IT_OK : stm8s_tim6.h
  • IS_TIM6_OPM_MODE_OK : stm8s_tim6.h
  • IS_TIM6_PRESCALER_OK : stm8s_tim6.h
  • IS_TIM6_PRESCALER_RELOAD_OK : stm8s_tim6.h
  • IS_TIM6_SLAVE_MODE_OK : stm8s_tim6.h
  • IS_TIM6_TRGO_SOURCE_OK : stm8s_tim6.h
  • IS_TIM6_TRIGGER_SELECTION_OK : stm8s_tim6.h
  • IS_TIM6_UPDATE_SOURCE_OK : stm8s_tim6.h
  • IS_UART1_ADDRESS_OK : stm8s_uart1.h
  • IS_UART1_BAUDRATE_OK : stm8s_uart1.h
  • IS_UART1_CLEAR_FLAG_OK : stm8s_uart1.h
  • IS_UART1_CLEAR_IT_OK : stm8s_uart1.h
  • IS_UART1_CONFIG_IT_OK : stm8s_uart1.h
  • IS_UART1_FLAG_OK : stm8s_uart1.h
  • IS_UART1_GET_IT_OK : stm8s_uart1.h
  • IS_UART1_IRDAMODE_OK : stm8s_uart1.h
  • IS_UART1_LINBREAKDETECTIONLENGTH_OK : stm8s_uart1.h
  • IS_UART1_MODE_OK : stm8s_uart1.h
  • IS_UART1_PARITY_OK : stm8s_uart1.h
  • IS_UART1_STOPBITS_OK : stm8s_uart1.h
  • IS_UART1_SYNCMODE_OK : stm8s_uart1.h
  • IS_UART1_WAKEUP_OK : stm8s_uart1.h
  • IS_UART1_WORDLENGTH_OK : stm8s_uart1.h
  • IS_UART2_ADDRESS_OK : stm8s_uart2.h
  • IS_UART2_AUTOSYNC_OK : stm8s_uart2.h
  • IS_UART2_BAUDRATE_OK : stm8s_uart2.h
  • IS_UART2_CLEAR_FLAG_OK : stm8s_uart2.h
  • IS_UART2_CLEAR_IT_OK : stm8s_uart2.h
  • IS_UART2_CONFIG_IT_OK : stm8s_uart2.h
  • IS_UART2_DIVUP_OK : stm8s_uart2.h
  • IS_UART2_FLAG_OK : stm8s_uart2.h
  • IS_UART2_GET_IT_OK : stm8s_uart2.h
  • IS_UART2_IRDAMODE_OK : stm8s_uart2.h
  • IS_UART2_LINBREAKDETECTIONLENGTH_OK : stm8s_uart2.h
  • IS_UART2_MODE_OK : stm8s_uart2.h
  • IS_UART2_PARITY_OK : stm8s_uart2.h
  • IS_UART2_SLAVE_OK : stm8s_uart2.h
  • IS_UART2_STOPBITS_OK : stm8s_uart2.h
  • IS_UART2_SYNCMODE_OK : stm8s_uart2.h
  • IS_UART2_WAKEUP_OK : stm8s_uart2.h
  • IS_UART2_WORDLENGTH_OK : stm8s_uart2.h
  • IS_UART3_ADDRESS_OK : stm8s_uart3.h
  • IS_UART3_AUTOSYNC_OK : stm8s_uart3.h
  • IS_UART3_BAUDRATE_OK : stm8s_uart3.h
  • IS_UART3_CLEAR_FLAG_OK : stm8s_uart3.h
  • IS_UART3_CLEAR_IT_OK : stm8s_uart3.h
  • IS_UART3_CONFIG_IT_OK : stm8s_uart3.h
  • IS_UART3_DIVUP_OK : stm8s_uart3.h
  • IS_UART3_FLAG_OK : stm8s_uart3.h
  • IS_UART3_GET_IT_OK : stm8s_uart3.h
  • IS_UART3_LINBREAKDETECTIONLENGTH_OK : stm8s_uart3.h
  • IS_UART3_MODE_OK : stm8s_uart3.h
  • IS_UART3_PARITY_OK : stm8s_uart3.h
  • IS_UART3_SLAVE_OK : stm8s_uart3.h
  • IS_UART3_STOPBITS_OK : stm8s_uart3.h
  • IS_UART3_WAKEUP_OK : stm8s_uart3.h
  • IS_UART3_WORDLENGTH_OK : stm8s_uart3.h
  • IS_UART4_ADDRESS_OK : stm8s_uart4.h
  • IS_UART4_AUTOSYNC_OK : stm8s_uart4.h
  • IS_UART4_BAUDRATE_OK : stm8s_uart4.h
  • IS_UART4_CLEAR_FLAG_OK : stm8s_uart4.h
  • IS_UART4_CLEAR_IT_OK : stm8s_uart4.h
  • IS_UART4_CONFIG_IT_OK : stm8s_uart4.h
  • IS_UART4_DIVUP_OK : stm8s_uart4.h
  • IS_UART4_FLAG_OK : stm8s_uart4.h
  • IS_UART4_GET_IT_OK : stm8s_uart4.h
  • IS_UART4_IRDAMODE_OK : stm8s_uart4.h
  • IS_UART4_LINBREAKDETECTIONLENGTH_OK : stm8s_uart4.h
  • IS_UART4_MODE_OK : stm8s_uart4.h
  • IS_UART4_PARITY_OK : stm8s_uart4.h
  • IS_UART4_SLAVE_OK : stm8s_uart4.h
  • IS_UART4_STOPBITS_OK : stm8s_uart4.h
  • IS_UART4_SYNCMODE_OK : stm8s_uart4.h
  • IS_UART4_WAKEUP_OK : stm8s_uart4.h
  • IS_UART4_WORDLENGTH_OK : stm8s_uart4.h
  • IS_WWDG_COUNTERVALUE_OK : stm8s_wwdg.h
  • IS_WWDG_WINDOWLIMITVALUE_OK : stm8s_wwdg.h
  • ITC : stm8s.h
  • ITC_BaseAddress : stm8s.h
  • ITC_DeInit() : stm8s_itc.h , stm8s_itc.c
  • ITC_GetCPUCC() : stm8s_itc.h , stm8s_itc.c
  • ITC_GetSoftIntStatus() : stm8s_itc.c , stm8s_itc.h
  • ITC_GetSoftwarePriority() : stm8s_itc.c , stm8s_itc.h
  • ITC_IRQ_AWU : stm8s_itc.h
  • ITC_IRQ_CLK : stm8s_itc.h
  • ITC_IRQ_EEPROM_EEC : stm8s_itc.h
  • ITC_IRQ_I2C : stm8s_itc.h
  • ITC_IRQ_PORTA : stm8s_itc.h
  • ITC_IRQ_PORTB : stm8s_itc.h
  • ITC_IRQ_PORTC : stm8s_itc.h
  • ITC_IRQ_PORTD : stm8s_itc.h
  • ITC_IRQ_PORTE : stm8s_itc.h
  • ITC_IRQ_SPI : stm8s_itc.h
  • ITC_IRQ_TIM1_CAPCOM : stm8s_itc.h
  • ITC_IRQ_TIM1_OVF : stm8s_itc.h
  • ITC_IRQ_TIM2_CAPCOM : stm8s_itc.h
  • ITC_IRQ_TIM2_OVF : stm8s_itc.h
  • ITC_IRQ_TIM3_CAPCOM : stm8s_itc.h
  • ITC_IRQ_TIM3_OVF : stm8s_itc.h
  • ITC_IRQ_TIM4_OVF : stm8s_itc.h
  • ITC_IRQ_TLI : stm8s_itc.h
  • ITC_Irq_TypeDef : stm8s_itc.h
  • ITC_PRIORITYLEVEL_0 : stm8s_itc.h
  • ITC_PRIORITYLEVEL_1 : stm8s_itc.h
  • ITC_PRIORITYLEVEL_2 : stm8s_itc.h
  • ITC_PRIORITYLEVEL_3 : stm8s_itc.h
  • ITC_PriorityLevel_TypeDef : stm8s_itc.h
  • ITC_SetSoftwarePriority() : stm8s_itc.h , stm8s_itc.c
  • ITC_SPRX_RESET_VALUE : stm8s.h
  • ITC_TypeDef : stm8s.h
  • ITEN_Mask : stm8s_i2c.c
  • ITStatus : stm8s.h
  • IWDG : stm8s.h
  • IWDG_BaseAddress : stm8s.h
  • IWDG_Enable() : stm8s_iwdg.h , stm8s_iwdg.c
  • IWDG_KEY_ENABLE : stm8s_iwdg.h
  • IWDG_KEY_REFRESH : stm8s_iwdg.h
  • IWDG_PR_RESET_VALUE : stm8s.h
  • IWDG_Prescaler_128 : stm8s_iwdg.h
  • IWDG_Prescaler_16 : stm8s_iwdg.h
  • IWDG_Prescaler_256 : stm8s_iwdg.h
  • IWDG_Prescaler_32 : stm8s_iwdg.h
  • IWDG_Prescaler_4 : stm8s_iwdg.h
  • IWDG_Prescaler_64 : stm8s_iwdg.h
  • IWDG_Prescaler_8 : stm8s_iwdg.h
  • IWDG_Prescaler_TypeDef : stm8s_iwdg.h
  • IWDG_ReloadCounter() : stm8s_iwdg.h , stm8s_iwdg.c
  • IWDG_RLR_RESET_VALUE : stm8s.h
  • IWDG_SetPrescaler() : stm8s_iwdg.c , stm8s_iwdg.h
  • IWDG_SetReload() : stm8s_iwdg.h , stm8s_iwdg.c
  • IWDG_TypeDef : stm8s.h
  • IWDG_WriteAccess_Disable : stm8s_iwdg.h
  • IWDG_WriteAccess_Enable : stm8s_iwdg.h
  • IWDG_WriteAccess_TypeDef : stm8s_iwdg.h
  • IWDG_WriteAccessCmd() : stm8s_iwdg.c , stm8s_iwdg.h


STM8S/A Standard Peripherals Drivers: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- p -

  • PointerAttr : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- r -

  • REGISTER_Mask : stm8s_i2c.c
  • REGISTER_SR1_Index : stm8s_i2c.c
  • REGISTER_SR2_Index : stm8s_i2c.c
  • RESET : stm8s.h
  • rim : stm8s.h
  • RST : stm8s.h
  • RST_BaseAddress : stm8s.h
  • RST_ClearFlag() : stm8s_rst.h , stm8s_rst.c
  • RST_FLAG_EMCF : stm8s_rst.h
  • RST_FLAG_ILLOPF : stm8s_rst.h
  • RST_FLAG_IWDGF : stm8s_rst.h
  • RST_FLAG_SWIMF : stm8s_rst.h
  • RST_Flag_TypeDef : stm8s_rst.h
  • RST_FLAG_WWDGF : stm8s_rst.h
  • RST_GetFlagStatus() : stm8s_rst.c , stm8s_rst.h
  • RST_SR_EMCF : stm8s.h
  • RST_SR_ILLOPF : stm8s.h
  • RST_SR_IWDGF : stm8s.h
  • RST_SR_SWIMF : stm8s.h
  • RST_SR_WWDGF : stm8s.h
  • RST_TypeDef : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- s -

  • s16 : stm8s.h
  • S16_MAX : stm8s.h
  • S16_MIN : stm8s.h
  • s32 : stm8s.h
  • S32_MAX : stm8s.h
  • S32_MIN : stm8s.h
  • s8 : stm8s.h
  • S8_MAX : stm8s.h
  • S8_MIN : stm8s.h
  • SET : stm8s.h
  • SetBit : stm8s.h
  • sim : stm8s.h
  • SPI : stm8s.h
  • SPI_BaseAddress : stm8s.h
  • SPI_BAUDRATEPRESCALER_128 : stm8s_spi.h
  • SPI_BAUDRATEPRESCALER_16 : stm8s_spi.h
  • SPI_BAUDRATEPRESCALER_2 : stm8s_spi.h
  • SPI_BAUDRATEPRESCALER_256 : stm8s_spi.h
  • SPI_BAUDRATEPRESCALER_32 : stm8s_spi.h
  • SPI_BAUDRATEPRESCALER_4 : stm8s_spi.h
  • SPI_BAUDRATEPRESCALER_64 : stm8s_spi.h
  • SPI_BAUDRATEPRESCALER_8 : stm8s_spi.h
  • SPI_BaudRatePrescaler_TypeDef : stm8s_spi.h
  • SPI_BiDirectionalLineConfig() : stm8s_spi.h , stm8s_spi.c
  • SPI_CalculateCRCCmd() : stm8s_spi.h , stm8s_spi.c
  • SPI_ClearFlag() : stm8s_spi.h , stm8s_spi.c
  • SPI_ClearITPendingBit() : stm8s_spi.h , stm8s_spi.c
  • SPI_CLOCKPHASE_1EDGE : stm8s_spi.h
  • SPI_CLOCKPHASE_2EDGE : stm8s_spi.h
  • SPI_ClockPhase_TypeDef : stm8s_spi.h
  • SPI_CLOCKPOLARITY_HIGH : stm8s_spi.h
  • SPI_CLOCKPOLARITY_LOW : stm8s_spi.h
  • SPI_ClockPolarity_TypeDef : stm8s_spi.h
  • SPI_Cmd() : stm8s_spi.h , stm8s_spi.c
  • SPI_CR1_BR : stm8s.h
  • SPI_CR1_CPHA : stm8s.h
  • SPI_CR1_CPOL : stm8s.h
  • SPI_CR1_LSBFIRST : stm8s.h
  • SPI_CR1_MSTR : stm8s.h
  • SPI_CR1_RESET_VALUE : stm8s.h
  • SPI_CR1_SPE : stm8s.h
  • SPI_CR2_BDM : stm8s.h
  • SPI_CR2_BDOE : stm8s.h
  • SPI_CR2_CRCEN : stm8s.h
  • SPI_CR2_CRCNEXT : stm8s.h
  • SPI_CR2_RESET_VALUE : stm8s.h
  • SPI_CR2_RXONLY : stm8s.h
  • SPI_CR2_SSI : stm8s.h
  • SPI_CR2_SSM : stm8s.h
  • SPI_CRC_RX : stm8s_spi.h
  • SPI_CRC_TX : stm8s_spi.h
  • SPI_CRC_TypeDef : stm8s_spi.h
  • SPI_CRCPR_RESET_VALUE : stm8s.h
  • SPI_DATADIRECTION_1LINE_RX : stm8s_spi.h
  • SPI_DATADIRECTION_1LINE_TX : stm8s_spi.h
  • SPI_DATADIRECTION_2LINES_FULLDUPLEX : stm8s_spi.h
  • SPI_DATADIRECTION_2LINES_RXONLY : stm8s_spi.h
  • SPI_DataDirection_TypeDef : stm8s_spi.h
  • SPI_DeInit() : stm8s_spi.h , stm8s_spi.c
  • SPI_DIRECTION_RX : stm8s_spi.h
  • SPI_DIRECTION_TX : stm8s_spi.h
  • SPI_Direction_TypeDef : stm8s_spi.h
  • SPI_DR_RESET_VALUE : stm8s.h
  • SPI_FIRSTBIT_LSB : stm8s_spi.h
  • SPI_FIRSTBIT_MSB : stm8s_spi.h
  • SPI_FirstBit_TypeDef : stm8s_spi.h
  • SPI_FLAG_BSY : stm8s_spi.h
  • SPI_FLAG_CRCERR : stm8s_spi.h
  • SPI_FLAG_MODF : stm8s_spi.h
  • SPI_FLAG_OVR : stm8s_spi.h
  • SPI_FLAG_RXNE : stm8s_spi.h
  • SPI_FLAG_TXE : stm8s_spi.h
  • SPI_Flag_TypeDef : stm8s_spi.h
  • SPI_FLAG_WKUP : stm8s_spi.h
  • SPI_GetCRC() : stm8s_spi.h , stm8s_spi.c
  • SPI_GetCRCPolynomial() : stm8s_spi.h , stm8s_spi.c
  • SPI_GetFlagStatus() : stm8s_spi.h , stm8s_spi.c
  • SPI_GetITStatus() : stm8s_spi.c , stm8s_spi.h
  • SPI_ICR_ERRIE : stm8s.h
  • SPI_ICR_RESET_VALUE : stm8s.h
  • SPI_ICR_RXEI : stm8s.h
  • SPI_ICR_TXEI : stm8s.h
  • SPI_ICR_WKIE : stm8s.h
  • SPI_Init() : stm8s_spi.h , stm8s_spi.c
  • SPI_IT_CRCERR : stm8s_spi.h
  • SPI_IT_ERR : stm8s_spi.h
  • SPI_IT_MODF : stm8s_spi.h
  • SPI_IT_OVR : stm8s_spi.h
  • SPI_IT_RXNE : stm8s_spi.h
  • SPI_IT_TXE : stm8s_spi.h
  • SPI_IT_TypeDef : stm8s_spi.h
  • SPI_IT_WKUP : stm8s_spi.h
  • SPI_ITConfig() : stm8s_spi.h , stm8s_spi.c
  • SPI_MODE_MASTER : stm8s_spi.h
  • SPI_MODE_SLAVE : stm8s_spi.h
  • SPI_Mode_TypeDef : stm8s_spi.h
  • SPI_NSS_HARD : stm8s_spi.h
  • SPI_NSS_SOFT : stm8s_spi.h
  • SPI_NSS_TypeDef : stm8s_spi.h
  • SPI_NSSInternalSoftwareCmd() : stm8s_spi.h , stm8s_spi.c
  • SPI_ReceiveData() : stm8s_spi.h , stm8s_spi.c
  • SPI_ResetCRC() : stm8s_spi.c , stm8s_spi.h
  • SPI_RXCRCR_RESET_VALUE : stm8s.h
  • SPI_SendData() : stm8s_spi.h , stm8s_spi.c
  • SPI_SR_BSY : stm8s.h
  • SPI_SR_CRCERR : stm8s.h
  • SPI_SR_MODF : stm8s.h
  • SPI_SR_OVR : stm8s.h
  • SPI_SR_RESET_VALUE : stm8s.h
  • SPI_SR_RXNE : stm8s.h
  • SPI_SR_TXE : stm8s.h
  • SPI_SR_WKUP : stm8s.h
  • SPI_TransmitCRC() : stm8s_spi.h , stm8s_spi.c
  • SPI_TXCRCR_RESET_VALUE : stm8s.h
  • SPI_TypeDef : stm8s.h
  • SUCCESS : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- t -

  • TBR_Array : stm8s_awu.c
  • TI1_Config() : stm8s_tim1.c , stm8s_tim3.c , stm8s_tim5.c , stm8s_tim2.c
  • TI2_Config() : stm8s_tim3.c , stm8s_tim5.c , stm8s_tim1.c , stm8s_tim2.c
  • TI3_Config() : stm8s_tim1.c , stm8s_tim2.c , stm8s_tim5.c
  • TI4_Config() : stm8s_tim1.c
  • TIM1 : stm8s.h
  • TIM1_ARRH_ARR : stm8s.h
  • TIM1_ARRH_RESET_VALUE : stm8s.h
  • TIM1_ARRL_ARR : stm8s.h
  • TIM1_ARRL_RESET_VALUE : stm8s.h
  • TIM1_ARRPreloadConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_AUTOMATICOUTPUT_DISABLE : stm8s_tim1.h
  • TIM1_AUTOMATICOUTPUT_ENABLE : stm8s_tim1.h
  • TIM1_AutomaticOutput_TypeDef : stm8s_tim1.h
  • TIM1_BaseAddress : stm8s.h
  • TIM1_BDTRConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_BKR_AOE : stm8s.h
  • TIM1_BKR_BKE : stm8s.h
  • TIM1_BKR_BKP : stm8s.h
  • TIM1_BKR_LOCK : stm8s.h
  • TIM1_BKR_MOE : stm8s.h
  • TIM1_BKR_OSSI : stm8s.h
  • TIM1_BKR_OSSR : stm8s.h
  • TIM1_BKR_RESET_VALUE : stm8s.h
  • TIM1_BREAK_DISABLE : stm8s_tim1.h
  • TIM1_BREAK_ENABLE : stm8s_tim1.h
  • TIM1_BREAKPOLARITY_HIGH : stm8s_tim1.h
  • TIM1_BREAKPOLARITY_LOW : stm8s_tim1.h
  • TIM1_BreakPolarity_TypeDef : stm8s_tim1.h
  • TIM1_BreakState_TypeDef : stm8s_tim1.h
  • TIM1_CCER1_CC1E : stm8s.h
  • TIM1_CCER1_CC1NE : stm8s.h
  • TIM1_CCER1_CC1NP : stm8s.h
  • TIM1_CCER1_CC1P : stm8s.h
  • TIM1_CCER1_CC2E : stm8s.h
  • TIM1_CCER1_CC2NE : stm8s.h
  • TIM1_CCER1_CC2NP : stm8s.h
  • TIM1_CCER1_CC2P : stm8s.h
  • TIM1_CCER1_RESET_VALUE : stm8s.h
  • TIM1_CCER2_CC3E : stm8s.h
  • TIM1_CCER2_CC3NE : stm8s.h
  • TIM1_CCER2_CC3NP : stm8s.h
  • TIM1_CCER2_CC3P : stm8s.h
  • TIM1_CCER2_CC4E : stm8s.h
  • TIM1_CCER2_CC4P : stm8s.h
  • TIM1_CCER2_RESET_VALUE : stm8s.h
  • TIM1_CCMR1_RESET_VALUE : stm8s.h
  • TIM1_CCMR2_RESET_VALUE : stm8s.h
  • TIM1_CCMR3_RESET_VALUE : stm8s.h
  • TIM1_CCMR4_RESET_VALUE : stm8s.h
  • TIM1_CCMR_CCxS : stm8s.h
  • TIM1_CCMR_ICxF : stm8s.h
  • TIM1_CCMR_ICxPSC : stm8s.h
  • TIM1_CCMR_OCM : stm8s.h
  • TIM1_CCMR_OCxFE : stm8s.h
  • TIM1_CCMR_OCxPE : stm8s.h
  • TIM1_CCPreloadControl() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_CCR1H_CCR1 : stm8s.h
  • TIM1_CCR1H_RESET_VALUE : stm8s.h
  • TIM1_CCR1L_CCR1 : stm8s.h
  • TIM1_CCR1L_RESET_VALUE : stm8s.h
  • TIM1_CCR2H_CCR2 : stm8s.h
  • TIM1_CCR2H_RESET_VALUE : stm8s.h
  • TIM1_CCR2L_CCR2 : stm8s.h
  • TIM1_CCR2L_RESET_VALUE : stm8s.h
  • TIM1_CCR3H_CCR3 : stm8s.h
  • TIM1_CCR3H_RESET_VALUE : stm8s.h
  • TIM1_CCR3L_CCR3 : stm8s.h
  • TIM1_CCR3L_RESET_VALUE : stm8s.h
  • TIM1_CCR4H_CCR4 : stm8s.h
  • TIM1_CCR4H_RESET_VALUE : stm8s.h
  • TIM1_CCR4L_CCR4 : stm8s.h
  • TIM1_CCR4L_RESET_VALUE : stm8s.h
  • TIM1_CCxCmd() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_CCxNCmd() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_CHANNEL_1 : stm8s_tim1.h
  • TIM1_CHANNEL_2 : stm8s_tim1.h
  • TIM1_CHANNEL_3 : stm8s_tim1.h
  • TIM1_CHANNEL_4 : stm8s_tim1.h
  • TIM1_Channel_TypeDef : stm8s_tim1.h
  • TIM1_ClearFlag() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ClearITPendingBit() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_Cmd() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_CNTRH_CNT : stm8s.h
  • TIM1_CNTRH_RESET_VALUE : stm8s.h
  • TIM1_CNTRL_CNT : stm8s.h
  • TIM1_CNTRL_RESET_VALUE : stm8s.h
  • TIM1_COUNTERMODE_CENTERALIGNED1 : stm8s_tim1.h
  • TIM1_COUNTERMODE_CENTERALIGNED2 : stm8s_tim1.h
  • TIM1_COUNTERMODE_CENTERALIGNED3 : stm8s_tim1.h
  • TIM1_COUNTERMODE_DOWN : stm8s_tim1.h
  • TIM1_CounterMode_TypeDef : stm8s_tim1.h
  • TIM1_COUNTERMODE_UP : stm8s_tim1.h
  • TIM1_CounterModeConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_CR1_ARPE : stm8s.h
  • TIM1_CR1_CEN : stm8s.h
  • TIM1_CR1_CMS : stm8s.h
  • TIM1_CR1_DIR : stm8s.h
  • TIM1_CR1_OPM : stm8s.h
  • TIM1_CR1_RESET_VALUE : stm8s.h
  • TIM1_CR1_UDIS : stm8s.h
  • TIM1_CR1_URS : stm8s.h
  • TIM1_CR2_CCPC : stm8s.h
  • TIM1_CR2_COMS : stm8s.h
  • TIM1_CR2_MMS : stm8s.h
  • TIM1_CR2_RESET_VALUE : stm8s.h
  • TIM1_CR2_TI1S : stm8s.h
  • TIM1_CtrlPWMOutputs() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_DeInit() : stm8s_tim1.c , stm8s_tim1.h
  • TIM1_DTR_DTG : stm8s.h
  • TIM1_DTR_RESET_VALUE : stm8s.h
  • TIM1_EGR_BG : stm8s.h
  • TIM1_EGR_CC1G : stm8s.h
  • TIM1_EGR_CC2G : stm8s.h
  • TIM1_EGR_CC3G : stm8s.h
  • TIM1_EGR_CC4G : stm8s.h
  • TIM1_EGR_COMG : stm8s.h
  • TIM1_EGR_RESET_VALUE : stm8s.h
  • TIM1_EGR_TG : stm8s.h
  • TIM1_EGR_UG : stm8s.h
  • TIM1_EncoderInterfaceConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ENCODERMODE_TI1 : stm8s_tim1.h
  • TIM1_ENCODERMODE_TI12 : stm8s_tim1.h
  • TIM1_ENCODERMODE_TI2 : stm8s_tim1.h
  • TIM1_EncoderMode_TypeDef : stm8s_tim1.h
  • TIM1_ETR_ECE : stm8s.h
  • TIM1_ETR_ETF : stm8s.h
  • TIM1_ETR_ETP : stm8s.h
  • TIM1_ETR_ETPS : stm8s.h
  • TIM1_ETR_RESET_VALUE : stm8s.h
  • TIM1_ETRClockMode1Config() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ETRClockMode2Config() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ETRConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_EVENTSOURCE_BREAK : stm8s_tim1.h
  • TIM1_EVENTSOURCE_CC1 : stm8s_tim1.h
  • TIM1_EVENTSOURCE_CC2 : stm8s_tim1.h
  • TIM1_EVENTSOURCE_CC3 : stm8s_tim1.h
  • TIM1_EVENTSOURCE_CC4 : stm8s_tim1.h
  • TIM1_EVENTSOURCE_COM : stm8s_tim1.h
  • TIM1_EVENTSOURCE_TRIGGER : stm8s_tim1.h
  • TIM1_EventSource_TypeDef : stm8s_tim1.h
  • TIM1_EVENTSOURCE_UPDATE : stm8s_tim1.h
  • TIM1_EXTTRGPOLARITY_INVERTED : stm8s_tim1.h
  • TIM1_EXTTRGPOLARITY_NONINVERTED : stm8s_tim1.h
  • TIM1_ExtTRGPolarity_TypeDef : stm8s_tim1.h
  • TIM1_EXTTRGPSC_DIV2 : stm8s_tim1.h
  • TIM1_EXTTRGPSC_DIV4 : stm8s_tim1.h
  • TIM1_EXTTRGPSC_DIV8 : stm8s_tim1.h
  • TIM1_EXTTRGPSC_OFF : stm8s_tim1.h
  • TIM1_ExtTRGPSC_TypeDef : stm8s_tim1.h
  • TIM1_FLAG_BREAK : stm8s_tim1.h
  • TIM1_FLAG_CC1 : stm8s_tim1.h
  • TIM1_FLAG_CC1OF : stm8s_tim1.h
  • TIM1_FLAG_CC2 : stm8s_tim1.h
  • TIM1_FLAG_CC2OF : stm8s_tim1.h
  • TIM1_FLAG_CC3 : stm8s_tim1.h
  • TIM1_FLAG_CC3OF : stm8s_tim1.h
  • TIM1_FLAG_CC4 : stm8s_tim1.h
  • TIM1_FLAG_CC4OF : stm8s_tim1.h
  • TIM1_FLAG_COM : stm8s_tim1.h
  • TIM1_FLAG_TRIGGER : stm8s_tim1.h
  • TIM1_FLAG_TypeDef : stm8s_tim1.h
  • TIM1_FLAG_UPDATE : stm8s_tim1.h
  • TIM1_FORCEDACTION_ACTIVE : stm8s_tim1.h
  • TIM1_FORCEDACTION_INACTIVE : stm8s_tim1.h
  • TIM1_ForcedAction_TypeDef : stm8s_tim1.h
  • TIM1_ForcedOC1Config() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ForcedOC2Config() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ForcedOC3Config() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ForcedOC4Config() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GenerateEvent() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GetCapture1() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GetCapture2() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GetCapture3() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GetCapture4() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GetCounter() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GetFlagStatus() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GetITStatus() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GetPrescaler() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ICInit() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ICPOLARITY_FALLING : stm8s_tim1.h
  • TIM1_ICPOLARITY_RISING : stm8s_tim1.h
  • TIM1_ICPolarity_TypeDef : stm8s_tim1.h
  • TIM1_ICPSC_DIV1 : stm8s_tim1.h
  • TIM1_ICPSC_DIV2 : stm8s_tim1.h
  • TIM1_ICPSC_DIV4 : stm8s_tim1.h
  • TIM1_ICPSC_DIV8 : stm8s_tim1.h
  • TIM1_ICPSC_TypeDef : stm8s_tim1.h
  • TIM1_ICSELECTION_DIRECTTI : stm8s_tim1.h
  • TIM1_ICSELECTION_INDIRECTTI : stm8s_tim1.h
  • TIM1_ICSELECTION_TRGI : stm8s_tim1.h
  • TIM1_ICSelection_TypeDef : stm8s_tim1.h
  • TIM1_IER_BIE : stm8s.h
  • TIM1_IER_CC1IE : stm8s.h
  • TIM1_IER_CC2IE : stm8s.h
  • TIM1_IER_CC3IE : stm8s.h
  • TIM1_IER_CC4IE : stm8s.h
  • TIM1_IER_COMIE : stm8s.h
  • TIM1_IER_RESET_VALUE : stm8s.h
  • TIM1_IER_TIE : stm8s.h
  • TIM1_IER_UIE : stm8s.h
  • TIM1_InternalClockConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_IT_BREAK : stm8s_tim1.h
  • TIM1_IT_CC1 : stm8s_tim1.h
  • TIM1_IT_CC2 : stm8s_tim1.h
  • TIM1_IT_CC3 : stm8s_tim1.h
  • TIM1_IT_CC4 : stm8s_tim1.h
  • TIM1_IT_COM : stm8s_tim1.h
  • TIM1_IT_TRIGGER : stm8s_tim1.h
  • TIM1_IT_TypeDef : stm8s_tim1.h
  • TIM1_IT_UPDATE : stm8s_tim1.h
  • TIM1_ITConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_LOCKLEVEL_1 : stm8s_tim1.h
  • TIM1_LOCKLEVEL_2 : stm8s_tim1.h
  • TIM1_LOCKLEVEL_3 : stm8s_tim1.h
  • TIM1_LOCKLEVEL_OFF : stm8s_tim1.h
  • TIM1_LockLevel_TypeDef : stm8s_tim1.h
  • TIM1_OC1FastConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC1Init() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC1NPolarityConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC1PolarityConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC1PreloadConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC2FastConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC2Init() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC2NPolarityConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC2PolarityConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC2PreloadConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC3FastConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC3Init() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC3NPolarityConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC3PolarityConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC3PreloadConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC4FastConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC4Init() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC4PolarityConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC4PreloadConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OCIDLESTATE_RESET : stm8s_tim1.h
  • TIM1_OCIDLESTATE_SET : stm8s_tim1.h
  • TIM1_OCIdleState_TypeDef : stm8s_tim1.h
  • TIM1_OCMODE_ACTIVE : stm8s_tim1.h
  • TIM1_OCMODE_INACTIVE : stm8s_tim1.h
  • TIM1_OCMODE_PWM1 : stm8s_tim1.h
  • TIM1_OCMODE_PWM2 : stm8s_tim1.h
  • TIM1_OCMODE_TIMING : stm8s_tim1.h
  • TIM1_OCMODE_TOGGLE : stm8s_tim1.h
  • TIM1_OCMode_TypeDef : stm8s_tim1.h
  • TIM1_OCNIDLESTATE_RESET : stm8s_tim1.h
  • TIM1_OCNIDLESTATE_SET : stm8s_tim1.h
  • TIM1_OCNIdleState_TypeDef : stm8s_tim1.h
  • TIM1_OCNPOLARITY_HIGH : stm8s_tim1.h
  • TIM1_OCNPOLARITY_LOW : stm8s_tim1.h
  • TIM1_OCNPolarity_TypeDef : stm8s_tim1.h
  • TIM1_OCPOLARITY_HIGH : stm8s_tim1.h
  • TIM1_OCPOLARITY_LOW : stm8s_tim1.h
  • TIM1_OCPolarity_TypeDef : stm8s_tim1.h
  • TIM1_OISR_OIS1 : stm8s.h
  • TIM1_OISR_OIS1N : stm8s.h
  • TIM1_OISR_OIS2 : stm8s.h
  • TIM1_OISR_OIS2N : stm8s.h
  • TIM1_OISR_OIS3 : stm8s.h
  • TIM1_OISR_OIS3N : stm8s.h
  • TIM1_OISR_OIS4 : stm8s.h
  • TIM1_OISR_RESET_VALUE : stm8s.h
  • TIM1_OPMODE_REPETITIVE : stm8s_tim1.h
  • TIM1_OPMODE_SINGLE : stm8s_tim1.h
  • TIM1_OPMode_TypeDef : stm8s_tim1.h
  • TIM1_OSSISTATE_DISABLE : stm8s_tim1.h
  • TIM1_OSSISTATE_ENABLE : stm8s_tim1.h
  • TIM1_OSSIState_TypeDef : stm8s_tim1.h
  • TIM1_OUTPUTNSTATE_DISABLE : stm8s_tim1.h
  • TIM1_OUTPUTNSTATE_ENABLE : stm8s_tim1.h
  • TIM1_OutputNState_TypeDef : stm8s_tim1.h
  • TIM1_OUTPUTSTATE_DISABLE : stm8s_tim1.h
  • TIM1_OUTPUTSTATE_ENABLE : stm8s_tim1.h
  • TIM1_OutputState_TypeDef : stm8s_tim1.h
  • TIM1_PrescalerConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_PSCH_PSC : stm8s.h
  • TIM1_PSCL_PSC : stm8s.h
  • TIM1_PSCRELOADMODE_IMMEDIATE : stm8s_tim1.h
  • TIM1_PSCReloadMode_TypeDef : stm8s_tim1.h
  • TIM1_PSCRELOADMODE_UPDATE : stm8s_tim1.h
  • TIM1_PSCRH_RESET_VALUE : stm8s.h
  • TIM1_PSCRL_RESET_VALUE : stm8s.h
  • TIM1_PWMIConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_RCR_REP : stm8s.h
  • TIM1_RCR_RESET_VALUE : stm8s.h
  • TIM1_SelectCOM() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SelectHallSensor() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SelectInputTrigger() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SelectMasterSlaveMode() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SelectOCxM() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SelectOnePulseMode() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SelectOutputTrigger() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SelectSlaveMode() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetAutoreload() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetCompare1() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetCompare2() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetCompare3() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetCompare4() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetCounter() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetIC1Prescaler() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetIC2Prescaler() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetIC3Prescaler() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetIC4Prescaler() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SLAVEMODE_EXTERNAL1 : stm8s_tim1.h
  • TIM1_SLAVEMODE_GATED : stm8s_tim1.h
  • TIM1_SLAVEMODE_RESET : stm8s_tim1.h
  • TIM1_SLAVEMODE_TRIGGER : stm8s_tim1.h
  • TIM1_SlaveMode_TypeDef : stm8s_tim1.h
  • TIM1_SMCR_MSM : stm8s.h
  • TIM1_SMCR_RESET_VALUE : stm8s.h
  • TIM1_SMCR_SMS : stm8s.h
  • TIM1_SMCR_TS : stm8s.h
  • TIM1_SR1_BIF : stm8s.h
  • TIM1_SR1_CC1IF : stm8s.h
  • TIM1_SR1_CC2IF : stm8s.h
  • TIM1_SR1_CC3IF : stm8s.h
  • TIM1_SR1_CC4IF : stm8s.h
  • TIM1_SR1_COMIF : stm8s.h
  • TIM1_SR1_RESET_VALUE : stm8s.h
  • TIM1_SR1_TIF : stm8s.h
  • TIM1_SR1_UIF : stm8s.h
  • TIM1_SR2_CC1OF : stm8s.h
  • TIM1_SR2_CC2OF : stm8s.h
  • TIM1_SR2_CC3OF : stm8s.h
  • TIM1_SR2_CC4OF : stm8s.h
  • TIM1_SR2_RESET_VALUE : stm8s.h
  • TIM1_TimeBaseInit() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_TIXEXTERNALCLK1SOURCE_TI1 : stm8s_tim1.h
  • TIM1_TIXEXTERNALCLK1SOURCE_TI1ED : stm8s_tim1.h
  • TIM1_TIXEXTERNALCLK1SOURCE_TI2 : stm8s_tim1.h
  • TIM1_TIxExternalCLK1Source_TypeDef : stm8s_tim1.h
  • TIM1_TIxExternalClockConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_TRGOSOURCE_ENABLE : stm8s_tim1.h
  • TIM1_TRGOSource_OC1 : stm8s_tim1.h
  • TIM1_TRGOSOURCE_OC1REF : stm8s_tim1.h
  • TIM1_TRGOSOURCE_OC2REF : stm8s_tim1.h
  • TIM1_TRGOSOURCE_OC3REF : stm8s_tim1.h
  • TIM1_TRGOSOURCE_RESET : stm8s_tim1.h
  • TIM1_TRGOSource_TypeDef : stm8s_tim1.h
  • TIM1_TRGOSOURCE_UPDATE : stm8s_tim1.h
  • TIM1_TS_ETRF : stm8s_tim1.h
  • TIM1_TS_TI1F_ED : stm8s_tim1.h
  • TIM1_TS_TI1FP1 : stm8s_tim1.h
  • TIM1_TS_TI2FP2 : stm8s_tim1.h
  • TIM1_TS_TIM5 : stm8s_tim1.h
  • TIM1_TS_TIM6 : stm8s_tim1.h
  • TIM1_TS_TypeDef : stm8s_tim1.h
  • TIM1_TypeDef : stm8s.h
  • TIM1_UpdateDisableConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_UpdateRequestConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_UPDATESOURCE_GLOBAL : stm8s_tim1.h
  • TIM1_UPDATESOURCE_REGULAR : stm8s_tim1.h
  • TIM1_UpdateSource_TypeDef : stm8s_tim1.h
  • TIM2_ARRH_ARR : stm8s.h
  • TIM2_ARRH_RESET_VALUE : stm8s.h
  • TIM2_ARRL_ARR : stm8s.h
  • TIM2_ARRL_RESET_VALUE : stm8s.h
  • TIM2_ARRPreloadConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_BaseAddress : stm8s.h
  • TIM2_CCER1_CC1E : stm8s.h
  • TIM2_CCER1_CC1P : stm8s.h
  • TIM2_CCER1_CC2E : stm8s.h
  • TIM2_CCER1_CC2P : stm8s.h
  • TIM2_CCER1_RESET_VALUE : stm8s.h
  • TIM2_CCER2_CC3E : stm8s.h
  • TIM2_CCER2_CC3P : stm8s.h
  • TIM2_CCER2_RESET_VALUE : stm8s.h
  • TIM2_CCMR1_RESET_VALUE : stm8s.h
  • TIM2_CCMR2_RESET_VALUE : stm8s.h
  • TIM2_CCMR3_RESET_VALUE : stm8s.h
  • TIM2_CCMR_CCxS : stm8s.h
  • TIM2_CCMR_ICxF : stm8s.h
  • TIM2_CCMR_ICxPSC : stm8s.h
  • TIM2_CCMR_OCM : stm8s.h
  • TIM2_CCMR_OCxPE : stm8s.h
  • TIM2_CCPreloadControl() : stm8s_tim2.h
  • TIM2_CCR1H_CCR1 : stm8s.h
  • TIM2_CCR1H_RESET_VALUE : stm8s.h
  • TIM2_CCR1L_CCR1 : stm8s.h
  • TIM2_CCR1L_RESET_VALUE : stm8s.h
  • TIM2_CCR2H_CCR2 : stm8s.h
  • TIM2_CCR2H_RESET_VALUE : stm8s.h
  • TIM2_CCR2L_CCR2 : stm8s.h
  • TIM2_CCR2L_RESET_VALUE : stm8s.h
  • TIM2_CCR3H_CCR3 : stm8s.h
  • TIM2_CCR3H_RESET_VALUE : stm8s.h
  • TIM2_CCR3L_CCR3 : stm8s.h
  • TIM2_CCR3L_RESET_VALUE : stm8s.h
  • TIM2_CCxCmd() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_CHANNEL_1 : stm8s_tim2.h
  • TIM2_CHANNEL_2 : stm8s_tim2.h
  • TIM2_CHANNEL_3 : stm8s_tim2.h
  • TIM2_Channel_TypeDef : stm8s_tim2.h
  • TIM2_ClearFlag() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_ClearITPendingBit() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_Cmd() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_CNTRH_CNT : stm8s.h
  • TIM2_CNTRH_RESET_VALUE : stm8s.h
  • TIM2_CNTRL_CNT : stm8s.h
  • TIM2_CNTRL_RESET_VALUE : stm8s.h
  • TIM2_CR1_ARPE : stm8s.h
  • TIM2_CR1_CEN : stm8s.h
  • TIM2_CR1_OPM : stm8s.h
  • TIM2_CR1_RESET_VALUE : stm8s.h
  • TIM2_CR1_UDIS : stm8s.h
  • TIM2_CR1_URS : stm8s.h
  • TIM2_DeInit() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_EGR_CC1G : stm8s.h
  • TIM2_EGR_CC2G : stm8s.h
  • TIM2_EGR_CC3G : stm8s.h
  • TIM2_EGR_RESET_VALUE : stm8s.h
  • TIM2_EGR_UG : stm8s.h
  • TIM2_EVENTSOURCE_CC1 : stm8s_tim2.h
  • TIM2_EVENTSOURCE_CC2 : stm8s_tim2.h
  • TIM2_EVENTSOURCE_CC3 : stm8s_tim2.h
  • TIM2_EventSource_TypeDef : stm8s_tim2.h
  • TIM2_EVENTSOURCE_UPDATE : stm8s_tim2.h
  • TIM2_FLAG_CC1 : stm8s_tim2.h
  • TIM2_FLAG_CC1OF : stm8s_tim2.h
  • TIM2_FLAG_CC2 : stm8s_tim2.h
  • TIM2_FLAG_CC2OF : stm8s_tim2.h
  • TIM2_FLAG_CC3 : stm8s_tim2.h
  • TIM2_FLAG_CC3OF : stm8s_tim2.h
  • TIM2_FLAG_TypeDef : stm8s_tim2.h
  • TIM2_FLAG_UPDATE : stm8s_tim2.h
  • TIM2_FORCEDACTION_ACTIVE : stm8s_tim2.h
  • TIM2_FORCEDACTION_INACTIVE : stm8s_tim2.h
  • TIM2_ForcedAction_TypeDef : stm8s_tim2.h
  • TIM2_ForcedOC1Config() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_ForcedOC2Config() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_ForcedOC3Config() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_GenerateEvent() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_GetCapture1() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_GetCapture2() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_GetCapture3() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_GetCounter() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_GetFlagStatus() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_GetITStatus() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_GetPrescaler() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_ICInit() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_ICPOLARITY_FALLING : stm8s_tim2.h
  • TIM2_ICPOLARITY_RISING : stm8s_tim2.h
  • TIM2_ICPolarity_TypeDef : stm8s_tim2.h
  • TIM2_ICPSC_DIV1 : stm8s_tim2.h
  • TIM2_ICPSC_DIV2 : stm8s_tim2.h
  • TIM2_ICPSC_DIV4 : stm8s_tim2.h
  • TIM2_ICPSC_DIV8 : stm8s_tim2.h
  • TIM2_ICPSC_TypeDef : stm8s_tim2.h
  • TIM2_ICSELECTION_DIRECTTI : stm8s_tim2.h
  • TIM2_ICSELECTION_INDIRECTTI : stm8s_tim2.h
  • TIM2_ICSELECTION_TRGI : stm8s_tim2.h
  • TIM2_ICSelection_TypeDef : stm8s_tim2.h
  • TIM2_IER_CC1IE : stm8s.h
  • TIM2_IER_CC2IE : stm8s.h
  • TIM2_IER_CC3IE : stm8s.h
  • TIM2_IER_RESET_VALUE : stm8s.h
  • TIM2_IER_UIE : stm8s.h
  • TIM2_InternalClockConfig() : stm8s_tim2.h
  • TIM2_IT_CC1 : stm8s_tim2.h
  • TIM2_IT_CC2 : stm8s_tim2.h
  • TIM2_IT_CC3 : stm8s_tim2.h
  • TIM2_IT_TypeDef : stm8s_tim2.h
  • TIM2_IT_UPDATE : stm8s_tim2.h
  • TIM2_ITConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC1Init() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC1PolarityConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC1PreloadConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC2Init() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC2PolarityConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC2PreloadConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC3Init() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC3PolarityConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC3PreloadConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OCMODE_ACTIVE : stm8s_tim2.h
  • TIM2_OCMODE_INACTIVE : stm8s_tim2.h
  • TIM2_OCMODE_PWM1 : stm8s_tim2.h
  • TIM2_OCMODE_PWM2 : stm8s_tim2.h
  • TIM2_OCMODE_TIMING : stm8s_tim2.h
  • TIM2_OCMODE_TOGGLE : stm8s_tim2.h
  • TIM2_OCMode_TypeDef : stm8s_tim2.h
  • TIM2_OCPOLARITY_HIGH : stm8s_tim2.h
  • TIM2_OCPOLARITY_LOW : stm8s_tim2.h
  • TIM2_OCPolarity_TypeDef : stm8s_tim2.h
  • TIM2_OPMODE_REPETITIVE : stm8s_tim2.h
  • TIM2_OPMODE_SINGLE : stm8s_tim2.h
  • TIM2_OPMode_TypeDef : stm8s_tim2.h
  • TIM2_OUTPUTSTATE_DISABLE : stm8s_tim2.h
  • TIM2_OUTPUTSTATE_ENABLE : stm8s_tim2.h
  • TIM2_OutputState_TypeDef : stm8s_tim2.h
  • TIM2_PRESCALER_1 : stm8s_tim2.h
  • TIM2_PRESCALER_1024 : stm8s_tim2.h
  • TIM2_PRESCALER_128 : stm8s_tim2.h
  • TIM2_PRESCALER_16 : stm8s_tim2.h
  • TIM2_PRESCALER_16384 : stm8s_tim2.h
  • TIM2_PRESCALER_2 : stm8s_tim2.h
  • TIM2_PRESCALER_2048 : stm8s_tim2.h
  • TIM2_PRESCALER_256 : stm8s_tim2.h
  • TIM2_PRESCALER_32 : stm8s_tim2.h
  • TIM2_PRESCALER_32768 : stm8s_tim2.h
  • TIM2_PRESCALER_4 : stm8s_tim2.h
  • TIM2_PRESCALER_4096 : stm8s_tim2.h
  • TIM2_PRESCALER_512 : stm8s_tim2.h
  • TIM2_PRESCALER_64 : stm8s_tim2.h
  • TIM2_PRESCALER_8 : stm8s_tim2.h
  • TIM2_PRESCALER_8192 : stm8s_tim2.h
  • TIM2_Prescaler_TypeDef : stm8s_tim2.h
  • TIM2_PrescalerConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_PSCR_PSC : stm8s.h
  • TIM2_PSCR_RESET_VALUE : stm8s.h
  • TIM2_PSCRELOADMODE_IMMEDIATE : stm8s_tim2.h
  • TIM2_PSCReloadMode_TypeDef : stm8s_tim2.h
  • TIM2_PSCRELOADMODE_UPDATE : stm8s_tim2.h
  • TIM2_PWMIConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SelectOCxM() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SelectOnePulseMode() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SetAutoreload() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SetCompare1() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SetCompare2() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SetCompare3() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SetCounter() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SetIC1Prescaler() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SetIC2Prescaler() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SetIC3Prescaler() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SR1_CC1IF : stm8s.h
  • TIM2_SR1_CC2IF : stm8s.h
  • TIM2_SR1_CC3IF : stm8s.h
  • TIM2_SR1_RESET_VALUE : stm8s.h
  • TIM2_SR1_UIF : stm8s.h
  • TIM2_SR2_CC1OF : stm8s.h
  • TIM2_SR2_CC2OF : stm8s.h
  • TIM2_SR2_CC3OF : stm8s.h
  • TIM2_SR2_RESET_VALUE : stm8s.h
  • TIM2_TimeBaseInit() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_TypeDef : stm8s.h
  • TIM2_UpdateDisableConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_UpdateRequestConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_UPDATESOURCE_GLOBAL : stm8s_tim2.h
  • TIM2_UPDATESOURCE_REGULAR : stm8s_tim2.h
  • TIM2_UpdateSource_TypeDef : stm8s_tim2.h
  • TIM3_ARRH_ARR : stm8s.h
  • TIM3_ARRH_RESET_VALUE : stm8s.h
  • TIM3_ARRL_ARR : stm8s.h
  • TIM3_ARRL_RESET_VALUE : stm8s.h
  • TIM3_ARRPreloadConfig() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_BaseAddress : stm8s.h
  • TIM3_CCER1_CC1E : stm8s.h
  • TIM3_CCER1_CC1P : stm8s.h
  • TIM3_CCER1_CC2E : stm8s.h
  • TIM3_CCER1_CC2P : stm8s.h
  • TIM3_CCER1_RESET_VALUE : stm8s.h
  • TIM3_CCMR1_RESET_VALUE : stm8s.h
  • TIM3_CCMR2_RESET_VALUE : stm8s.h
  • TIM3_CCMR_CCxS : stm8s.h
  • TIM3_CCMR_ICxF : stm8s.h
  • TIM3_CCMR_ICxPSC : stm8s.h
  • TIM3_CCMR_OCM : stm8s.h
  • TIM3_CCMR_OCxPE : stm8s.h
  • TIM3_CCPreloadControl() : stm8s_tim3.h
  • TIM3_CCR1H_CCR1 : stm8s.h
  • TIM3_CCR1H_RESET_VALUE : stm8s.h
  • TIM3_CCR1L_CCR1 : stm8s.h
  • TIM3_CCR1L_RESET_VALUE : stm8s.h
  • TIM3_CCR2H_CCR2 : stm8s.h
  • TIM3_CCR2H_RESET_VALUE : stm8s.h
  • TIM3_CCR2L_CCR2 : stm8s.h
  • TIM3_CCR2L_RESET_VALUE : stm8s.h
  • TIM3_CCxCmd() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_CHANNEL_1 : stm8s_tim3.h
  • TIM3_CHANNEL_2 : stm8s_tim3.h
  • TIM3_Channel_TypeDef : stm8s_tim3.h
  • TIM3_ClearFlag() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_ClearITPendingBit() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_Cmd() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_CNTRH_CNT : stm8s.h
  • TIM3_CNTRH_RESET_VALUE : stm8s.h
  • TIM3_CNTRL_CNT : stm8s.h
  • TIM3_CNTRL_RESET_VALUE : stm8s.h
  • TIM3_CR1_ARPE : stm8s.h
  • TIM3_CR1_CEN : stm8s.h
  • TIM3_CR1_OPM : stm8s.h
  • TIM3_CR1_RESET_VALUE : stm8s.h
  • TIM3_CR1_UDIS : stm8s.h
  • TIM3_CR1_URS : stm8s.h
  • TIM3_DeInit() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_EGR_CC1G : stm8s.h
  • TIM3_EGR_CC2G : stm8s.h
  • TIM3_EGR_RESET_VALUE : stm8s.h
  • TIM3_EGR_UG : stm8s.h
  • TIM3_EVENTSOURCE_CC1 : stm8s_tim3.h
  • TIM3_EVENTSOURCE_CC2 : stm8s_tim3.h
  • TIM3_EventSource_TypeDef : stm8s_tim3.h
  • TIM3_EVENTSOURCE_UPDATE : stm8s_tim3.h
  • TIM3_FLAG_CC1 : stm8s_tim3.h
  • TIM3_FLAG_CC1OF : stm8s_tim3.h
  • TIM3_FLAG_CC2 : stm8s_tim3.h
  • TIM3_FLAG_CC2OF : stm8s_tim3.h
  • TIM3_FLAG_TypeDef : stm8s_tim3.h
  • TIM3_FLAG_UPDATE : stm8s_tim3.h
  • TIM3_FORCEDACTION_ACTIVE : stm8s_tim3.h
  • TIM3_FORCEDACTION_INACTIVE : stm8s_tim3.h
  • TIM3_ForcedAction_TypeDef : stm8s_tim3.h
  • TIM3_ForcedOC1Config() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_ForcedOC2Config() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_GenerateEvent() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_GetCapture1() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_GetCapture2() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_GetCounter() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_GetFlagStatus() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_GetITStatus() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_GetPrescaler() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_ICInit() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_ICPOLARITY_FALLING : stm8s_tim3.h
  • TIM3_ICPOLARITY_RISING : stm8s_tim3.h
  • TIM3_ICPolarity_TypeDef : stm8s_tim3.h
  • TIM3_ICPSC_DIV1 : stm8s_tim3.h
  • TIM3_ICPSC_DIV2 : stm8s_tim3.h
  • TIM3_ICPSC_DIV4 : stm8s_tim3.h
  • TIM3_ICPSC_DIV8 : stm8s_tim3.h
  • TIM3_ICPSC_TypeDef : stm8s_tim3.h
  • TIM3_ICSELECTION_DIRECTTI : stm8s_tim3.h
  • TIM3_ICSELECTION_INDIRECTTI : stm8s_tim3.h
  • TIM3_ICSELECTION_TRGI : stm8s_tim3.h
  • TIM3_ICSelection_TypeDef : stm8s_tim3.h
  • TIM3_IER_CC1IE : stm8s.h
  • TIM3_IER_CC2IE : stm8s.h
  • TIM3_IER_RESET_VALUE : stm8s.h
  • TIM3_IER_UIE : stm8s.h
  • TIM3_InternalClockConfig() : stm8s_tim3.h
  • TIM3_IT_CC1 : stm8s_tim3.h
  • TIM3_IT_CC2 : stm8s_tim3.h
  • TIM3_IT_TypeDef : stm8s_tim3.h
  • TIM3_IT_UPDATE : stm8s_tim3.h
  • TIM3_ITConfig() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_OC1Init() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_OC1PolarityConfig() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_OC1PreloadConfig() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_OC2Init() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_OC2PolarityConfig() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_OC2PreloadConfig() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_OCMODE_ACTIVE : stm8s_tim3.h
  • TIM3_OCMODE_INACTIVE : stm8s_tim3.h
  • TIM3_OCMODE_PWM1 : stm8s_tim3.h
  • TIM3_OCMODE_PWM2 : stm8s_tim3.h
  • TIM3_OCMODE_TIMING : stm8s_tim3.h
  • TIM3_OCMODE_TOGGLE : stm8s_tim3.h
  • TIM3_OCMode_TypeDef : stm8s_tim3.h
  • TIM3_OCPOLARITY_HIGH : stm8s_tim3.h
  • TIM3_OCPOLARITY_LOW : stm8s_tim3.h
  • TIM3_OCPolarity_TypeDef : stm8s_tim3.h
  • TIM3_OPMODE_REPETITIVE : stm8s_tim3.h
  • TIM3_OPMODE_SINGLE : stm8s_tim3.h
  • TIM3_OPMode_TypeDef : stm8s_tim3.h
  • TIM3_OUTPUTSTATE_DISABLE : stm8s_tim3.h
  • TIM3_OUTPUTSTATE_ENABLE : stm8s_tim3.h
  • TIM3_OutputState_TypeDef : stm8s_tim3.h
  • TIM3_PRESCALER_1 : stm8s_tim3.h
  • TIM3_PRESCALER_1024 : stm8s_tim3.h
  • TIM3_PRESCALER_128 : stm8s_tim3.h
  • TIM3_PRESCALER_16 : stm8s_tim3.h
  • TIM3_PRESCALER_16384 : stm8s_tim3.h
  • TIM3_PRESCALER_2 : stm8s_tim3.h
  • TIM3_PRESCALER_2048 : stm8s_tim3.h
  • TIM3_PRESCALER_256 : stm8s_tim3.h
  • TIM3_PRESCALER_32 : stm8s_tim3.h
  • TIM3_PRESCALER_32768 : stm8s_tim3.h
  • TIM3_PRESCALER_4 : stm8s_tim3.h
  • TIM3_PRESCALER_4096 : stm8s_tim3.h
  • TIM3_PRESCALER_512 : stm8s_tim3.h
  • TIM3_PRESCALER_64 : stm8s_tim3.h
  • TIM3_PRESCALER_8 : stm8s_tim3.h
  • TIM3_PRESCALER_8192 : stm8s_tim3.h
  • TIM3_Prescaler_TypeDef : stm8s_tim3.h
  • TIM3_PrescalerConfig() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_PSCR_PSC : stm8s.h
  • TIM3_PSCR_RESET_VALUE : stm8s.h
  • TIM3_PSCRELOADMODE_IMMEDIATE : stm8s_tim3.h
  • TIM3_PSCReloadMode_TypeDef : stm8s_tim3.h
  • TIM3_PSCRELOADMODE_UPDATE : stm8s_tim3.h
  • TIM3_PWMIConfig() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_SelectOCxM() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_SelectOnePulseMode() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_SetAutoreload() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_SetCompare1() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_SetCompare2() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_SetCounter() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_SetIC1Prescaler() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_SetIC2Prescaler() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_SR1_CC1IF : stm8s.h
  • TIM3_SR1_CC2IF : stm8s.h
  • TIM3_SR1_RESET_VALUE : stm8s.h
  • TIM3_SR1_UIF : stm8s.h
  • TIM3_SR2_CC1OF : stm8s.h
  • TIM3_SR2_CC2OF : stm8s.h
  • TIM3_SR2_RESET_VALUE : stm8s.h
  • TIM3_TimeBaseInit() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_TypeDef : stm8s.h
  • TIM3_UpdateDisableConfig() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_UpdateRequestConfig() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_UPDATESOURCE_GLOBAL : stm8s_tim3.h
  • TIM3_UPDATESOURCE_REGULAR : stm8s_tim3.h
  • TIM3_UpdateSource_TypeDef : stm8s_tim3.h
  • TIM4_ARR_ARR : stm8s.h
  • TIM4_ARR_RESET_VALUE : stm8s.h
  • TIM4_ARRPreloadConfig() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_BaseAddress : stm8s.h
  • TIM4_ClearFlag() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_ClearITPendingBit() : stm8s_tim4.c , stm8s_tim4.h
  • TIM4_Cmd() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_CNTR_CNT : stm8s.h
  • TIM4_CNTR_RESET_VALUE : stm8s.h
  • TIM4_CR1_ARPE : stm8s.h
  • TIM4_CR1_CEN : stm8s.h
  • TIM4_CR1_OPM : stm8s.h
  • TIM4_CR1_RESET_VALUE : stm8s.h
  • TIM4_CR1_UDIS : stm8s.h
  • TIM4_CR1_URS : stm8s.h
  • TIM4_DeInit() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_EGR_RESET_VALUE : stm8s.h
  • TIM4_EGR_UG : stm8s.h
  • TIM4_EventSource_TypeDef : stm8s_tim4.h
  • TIM4_EVENTSOURCE_UPDATE : stm8s_tim4.h
  • TIM4_FLAG_TypeDef : stm8s_tim4.h
  • TIM4_FLAG_UPDATE : stm8s_tim4.h
  • TIM4_GenerateEvent() : stm8s_tim4.c , stm8s_tim4.h
  • TIM4_GetCounter() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_GetFlagStatus() : stm8s_tim4.c , stm8s_tim4.h
  • TIM4_GetITStatus() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_GetPrescaler() : stm8s_tim4.c , stm8s_tim4.h
  • TIM4_IER_RESET_VALUE : stm8s.h
  • TIM4_IER_UIE : stm8s.h
  • TIM4_IT_TypeDef : stm8s_tim4.h
  • TIM4_IT_UPDATE : stm8s_tim4.h
  • TIM4_ITConfig() : stm8s_tim4.c , stm8s_tim4.h
  • TIM4_OPMODE_REPETITIVE : stm8s_tim4.h
  • TIM4_OPMODE_SINGLE : stm8s_tim4.h
  • TIM4_OPMode_TypeDef : stm8s_tim4.h
  • TIM4_PRESCALER_1 : stm8s_tim4.h
  • TIM4_PRESCALER_128 : stm8s_tim4.h
  • TIM4_PRESCALER_16 : stm8s_tim4.h
  • TIM4_PRESCALER_2 : stm8s_tim4.h
  • TIM4_PRESCALER_32 : stm8s_tim4.h
  • TIM4_PRESCALER_4 : stm8s_tim4.h
  • TIM4_PRESCALER_64 : stm8s_tim4.h
  • TIM4_PRESCALER_8 : stm8s_tim4.h
  • TIM4_Prescaler_TypeDef : stm8s_tim4.h
  • TIM4_PrescalerConfig() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_PSCR_PSC : stm8s.h
  • TIM4_PSCR_RESET_VALUE : stm8s.h
  • TIM4_PSCRELOADMODE_IMMEDIATE : stm8s_tim4.h
  • TIM4_PSCReloadMode_TypeDef : stm8s_tim4.h
  • TIM4_PSCRELOADMODE_UPDATE : stm8s_tim4.h
  • TIM4_SelectOnePulseMode() : stm8s_tim4.c , stm8s_tim4.h
  • TIM4_SetAutoreload() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_SetCounter() : stm8s_tim4.c , stm8s_tim4.h
  • TIM4_SR1_RESET_VALUE : stm8s.h
  • TIM4_SR1_UIF : stm8s.h
  • TIM4_TimeBaseInit() : stm8s_tim4.c , stm8s_tim4.h
  • TIM4_TypeDef : stm8s.h
  • TIM4_UpdateDisableConfig() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_UpdateRequestConfig() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_UPDATESOURCE_GLOBAL : stm8s_tim4.h
  • TIM4_UPDATESOURCE_REGULAR : stm8s_tim4.h
  • TIM4_UpdateSource_TypeDef : stm8s_tim4.h
  • TIM5_ARRH_ARR : stm8s.h
  • TIM5_ARRH_RESET_VALUE : stm8s.h
  • TIM5_ARRL_ARR : stm8s.h
  • TIM5_ARRL_RESET_VALUE : stm8s.h
  • TIM5_ARRPreloadConfig() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_BaseAddress : stm8s.h
  • TIM5_CCER1_CC1E : stm8s.h
  • TIM5_CCER1_CC1P : stm8s.h
  • TIM5_CCER1_CC2E : stm8s.h
  • TIM5_CCER1_CC2P : stm8s.h
  • TIM5_CCER1_RESET_VALUE : stm8s.h
  • TIM5_CCER2_CC3E : stm8s.h
  • TIM5_CCER2_CC3P : stm8s.h
  • TIM5_CCER2_RESET_VALUE : stm8s.h
  • TIM5_CCMR1_RESET_VALUE : stm8s.h
  • TIM5_CCMR2_RESET_VALUE : stm8s.h
  • TIM5_CCMR3_RESET_VALUE : stm8s.h
  • TIM5_CCMR_CCxS : stm8s.h
  • TIM5_CCMR_ICxF : stm8s.h
  • TIM5_CCMR_ICxPSC : stm8s.h
  • TIM5_CCMR_OCM : stm8s.h
  • TIM5_CCMR_OCxPE : stm8s.h
  • TIM5_CCMR_TIxDirect_Set : stm8s.h
  • TIM5_CCPreloadControl() : stm8s_tim5.h
  • TIM5_CCR1H_CCR1 : stm8s.h
  • TIM5_CCR1H_RESET_VALUE : stm8s.h
  • TIM5_CCR1L_CCR1 : stm8s.h
  • TIM5_CCR1L_RESET_VALUE : stm8s.h
  • TIM5_CCR2H_CCR2 : stm8s.h
  • TIM5_CCR2H_RESET_VALUE : stm8s.h
  • TIM5_CCR2L_CCR2 : stm8s.h
  • TIM5_CCR2L_RESET_VALUE : stm8s.h
  • TIM5_CCR3H_CCR3 : stm8s.h
  • TIM5_CCR3H_RESET_VALUE : stm8s.h
  • TIM5_CCR3L_CCR3 : stm8s.h
  • TIM5_CCR3L_RESET_VALUE : stm8s.h
  • TIM5_CCxCmd() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_CHANNEL_1 : stm8s_tim5.h
  • TIM5_CHANNEL_2 : stm8s_tim5.h
  • TIM5_CHANNEL_3 : stm8s_tim5.h
  • TIM5_Channel_TypeDef : stm8s_tim5.h
  • TIM5_ClearFlag() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_ClearITPendingBit() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_Cmd() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_CNTRH_CNT : stm8s.h
  • TIM5_CNTRH_RESET_VALUE : stm8s.h
  • TIM5_CNTRL_CNT : stm8s.h
  • TIM5_CNTRL_RESET_VALUE : stm8s.h
  • TIM5_CR1_ARPE : stm8s.h
  • TIM5_CR1_CEN : stm8s.h
  • TIM5_CR1_OPM : stm8s.h
  • TIM5_CR1_RESET_VALUE : stm8s.h
  • TIM5_CR1_UDIS : stm8s.h
  • TIM5_CR1_URS : stm8s.h
  • TIM5_CR2_MMS : stm8s.h
  • TIM5_CR2_RESET_VALUE : stm8s.h
  • TIM5_CR2_TI1S : stm8s.h
  • TIM5_DeInit() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_EGR_CC1G : stm8s.h
  • TIM5_EGR_CC2G : stm8s.h
  • TIM5_EGR_CC3G : stm8s.h
  • TIM5_EGR_RESET_VALUE : stm8s.h
  • TIM5_EGR_TG : stm8s.h
  • TIM5_EGR_UG : stm8s.h
  • TIM5_EncoderInterfaceConfig() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_ENCODERMODE_TI1 : stm8s_tim5.h
  • TIM5_ENCODERMODE_TI12 : stm8s_tim5.h
  • TIM5_ENCODERMODE_TI2 : stm8s_tim5.h
  • TIM5_EncoderMode_TypeDef : stm8s_tim5.h
  • TIM5_EVENTSOURCE_CC1 : stm8s_tim5.h
  • TIM5_EVENTSOURCE_CC2 : stm8s_tim5.h
  • TIM5_EVENTSOURCE_CC3 : stm8s_tim5.h
  • TIM5_EVENTSOURCE_TRIGGER : stm8s_tim5.h
  • TIM5_EventSource_TypeDef : stm8s_tim5.h
  • TIM5_EVENTSOURCE_UPDATE : stm8s_tim5.h
  • TIM5_EXTTRGPOLARITY_INVERTED : stm8s_tim5.h
  • TIM5_EXTTRGPOLARITY_NONINVERTED : stm8s_tim5.h
  • TIM5_ExtTRGPolarity_TypeDef : stm8s_tim5.h
  • TIM5_EXTTRGPSC_DIV2 : stm8s_tim5.h
  • TIM5_EXTTRGPSC_DIV4 : stm8s_tim5.h
  • TIM5_EXTTRGPSC_DIV8 : stm8s_tim5.h
  • TIM5_EXTTRGPSC_OFF : stm8s_tim5.h
  • TIM5_ExtTRGPSC_TypeDef : stm8s_tim5.h
  • TIM5_FLAG_CC1 : stm8s_tim5.h
  • TIM5_FLAG_CC1OF : stm8s_tim5.h
  • TIM5_FLAG_CC2 : stm8s_tim5.h
  • TIM5_FLAG_CC2OF : stm8s_tim5.h
  • TIM5_FLAG_CC3 : stm8s_tim5.h
  • TIM5_FLAG_CC3OF : stm8s_tim5.h
  • TIM5_FLAG_TRIGGER : stm8s_tim5.h
  • TIM5_FLAG_TypeDef : stm8s_tim5.h
  • TIM5_FLAG_UPDATE : stm8s_tim5.h
  • TIM5_FORCEDACTION_ACTIVE : stm8s_tim5.h
  • TIM5_FORCEDACTION_INACTIVE : stm8s_tim5.h
  • TIM5_ForcedAction_TypeDef : stm8s_tim5.h
  • TIM5_ForcedOC1Config() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_ForcedOC2Config() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_ForcedOC3Config() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_GenerateEvent() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_GetCapture1() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_GetCapture2() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_GetCapture3() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_GetCounter() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_GetFlagStatus() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_GetITStatus() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_GetPrescaler() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_ICInit() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_ICPOLARITY_FALLING : stm8s_tim5.h
  • TIM5_ICPOLARITY_RISING : stm8s_tim5.h
  • TIM5_ICPolarity_TypeDef : stm8s_tim5.h
  • TIM5_ICPSC_DIV1 : stm8s_tim5.h
  • TIM5_ICPSC_DIV2 : stm8s_tim5.h
  • TIM5_ICPSC_DIV4 : stm8s_tim5.h
  • TIM5_ICPSC_DIV8 : stm8s_tim5.h
  • TIM5_ICPSC_TypeDef : stm8s_tim5.h
  • TIM5_ICSELECTION_DIRECTTI : stm8s_tim5.h
  • TIM5_ICSELECTION_INDIRECTTI : stm8s_tim5.h
  • TIM5_ICSELECTION_TRGI : stm8s_tim5.h
  • TIM5_ICSelection_TypeDef : stm8s_tim5.h
  • TIM5_IER_CC1IE : stm8s.h
  • TIM5_IER_CC2IE : stm8s.h
  • TIM5_IER_CC3IE : stm8s.h
  • TIM5_IER_RESET_VALUE : stm8s.h
  • TIM5_IER_TIE : stm8s.h
  • TIM5_IER_UIE : stm8s.h
  • TIM5_InternalClockConfig() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_IT_CC1 : stm8s_tim5.h
  • TIM5_IT_CC2 : stm8s_tim5.h
  • TIM5_IT_CC3 : stm8s_tim5.h
  • TIM5_IT_TRIGGER : stm8s_tim5.h
  • TIM5_IT_TypeDef : stm8s_tim5.h
  • TIM5_IT_UPDATE : stm8s_tim5.h
  • TIM5_ITConfig() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_OC1Init() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_OC1PolarityConfig() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_OC1PreloadConfig() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_OC2Init() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_OC2PolarityConfig() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_OC2PreloadConfig() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_OC3Init() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_OC3PolarityConfig() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_OC3PreloadConfig() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_OCMODE_ACTIVE : stm8s_tim5.h
  • TIM5_OCMODE_INACTIVE : stm8s_tim5.h
  • TIM5_OCMODE_PWM1 : stm8s_tim5.h
  • TIM5_OCMODE_PWM2 : stm8s_tim5.h
  • TIM5_OCMODE_TIMING : stm8s_tim5.h
  • TIM5_OCMODE_TOGGLE : stm8s_tim5.h
  • TIM5_OCMode_TypeDef : stm8s_tim5.h
  • TIM5_OCPOLARITY_HIGH : stm8s_tim5.h
  • TIM5_OCPOLARITY_LOW : stm8s_tim5.h
  • TIM5_OCPolarity_TypeDef : stm8s_tim5.h
  • TIM5_OPMODE_REPETITIVE : stm8s_tim5.h
  • TIM5_OPMODE_SINGLE : stm8s_tim5.h
  • TIM5_OPMode_TypeDef : stm8s_tim5.h
  • TIM5_OUTPUTSTATE_DISABLE : stm8s_tim5.h
  • TIM5_OUTPUTSTATE_ENABLE : stm8s_tim5.h
  • TIM5_OutputState_TypeDef : stm8s_tim5.h
  • TIM5_PRESCALER_1 : stm8s_tim5.h
  • TIM5_PRESCALER_1024 : stm8s_tim5.h
  • TIM5_PRESCALER_128 : stm8s_tim5.h
  • TIM5_PRESCALER_16 : stm8s_tim5.h
  • TIM5_PRESCALER_16384 : stm8s_tim5.h
  • TIM5_PRESCALER_2 : stm8s_tim5.h
  • TIM5_PRESCALER_2048 : stm8s_tim5.h
  • TIM5_PRESCALER_256 : stm8s_tim5.h
  • TIM5_PRESCALER_32 : stm8s_tim5.h
  • TIM5_PRESCALER_32768 : stm8s_tim5.h
  • TIM5_PRESCALER_4 : stm8s_tim5.h
  • TIM5_PRESCALER_4096 : stm8s_tim5.h
  • TIM5_PRESCALER_512 : stm8s_tim5.h
  • TIM5_PRESCALER_64 : stm8s_tim5.h
  • TIM5_PRESCALER_8 : stm8s_tim5.h
  • TIM5_PRESCALER_8192 : stm8s_tim5.h
  • TIM5_Prescaler_TypeDef : stm8s_tim5.h
  • TIM5_PrescalerConfig() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_PSCR_PSC : stm8s.h
  • TIM5_PSCR_RESET_VALUE : stm8s.h
  • TIM5_PSCRELOADMODE_IMMEDIATE : stm8s_tim5.h
  • TIM5_PSCReloadMode_TypeDef : stm8s_tim5.h
  • TIM5_PSCRELOADMODE_UPDATE : stm8s_tim5.h
  • TIM5_PWMIConfig() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_SelectInputTrigger() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_SelectOCxM() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_SelectOnePulseMode() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_SelectOutputTrigger() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_SelectSlaveMode() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_SetAutoreload() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_SetCompare1() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_SetCompare2() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_SetCompare3() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_SetCounter() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_SetIC1Prescaler() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_SetIC2Prescaler() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_SetIC3Prescaler() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_SLAVEMODE_EXTERNAL1 : stm8s_tim5.h
  • TIM5_SLAVEMODE_GATED : stm8s_tim5.h
  • TIM5_SLAVEMODE_RESET : stm8s_tim5.h
  • TIM5_SLAVEMODE_TRIGGER : stm8s_tim5.h
  • TIM5_SlaveMode_TypeDef : stm8s_tim5.h
  • TIM5_SMCR_MSM : stm8s.h
  • TIM5_SMCR_RESET_VALUE : stm8s.h
  • TIM5_SMCR_SMS : stm8s.h
  • TIM5_SMCR_TS : stm8s.h
  • TIM5_SR1_CC1IF : stm8s.h
  • TIM5_SR1_CC2IF : stm8s.h
  • TIM5_SR1_CC3IF : stm8s.h
  • TIM5_SR1_RESET_VALUE : stm8s.h
  • TIM5_SR1_TIF : stm8s.h
  • TIM5_SR1_UIF : stm8s.h
  • TIM5_SR2_CC1OF : stm8s.h
  • TIM5_SR2_CC2OF : stm8s.h
  • TIM5_SR2_CC3OF : stm8s.h
  • TIM5_SR2_RESET_VALUE : stm8s.h
  • TIM5_TimeBaseInit() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_TRGOSOURCE_ENABLE : stm8s_tim5.h
  • TIM5_TRGOSOURCE_OC1 : stm8s_tim5.h
  • TIM5_TRGOSOURCE_OC1REF : stm8s_tim5.h
  • TIM5_TRGOSOURCE_OC2REF : stm8s_tim5.h
  • TIM5_TRGOSOURCE_RESET : stm8s_tim5.h
  • TIM5_TRGOSource_TypeDef : stm8s_tim5.h
  • TIM5_TRGOSOURCE_UPDATE : stm8s_tim5.h
  • TIM5_TS_TIM1 : stm8s_tim5.h
  • TIM5_TS_TIM6 : stm8s_tim5.h
  • TIM5_TS_TypeDef : stm8s_tim5.h
  • TIM5_TypeDef : stm8s.h
  • TIM5_UpdateDisableConfig() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_UpdateRequestConfig() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_UPDATESOURCE_GLOBAL : stm8s_tim5.h
  • TIM5_UPDATESOURCE_REGULAR : stm8s_tim5.h
  • TIM5_UpdateSource_TypeDef : stm8s_tim5.h
  • TIM6_ARR_ARR : stm8s.h
  • TIM6_ARR_RESET_VALUE : stm8s.h
  • TIM6_ARRPreloadConfig() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_BaseAddress : stm8s.h
  • TIM6_ClearFlag() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_ClearITPendingBit() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_Cmd() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_CNTR_CNT : stm8s.h
  • TIM6_CNTR_RESET_VALUE : stm8s.h
  • TIM6_CR1_ARPE : stm8s.h
  • TIM6_CR1_CEN : stm8s.h
  • TIM6_CR1_OPM : stm8s.h
  • TIM6_CR1_RESET_VALUE : stm8s.h
  • TIM6_CR1_UDIS : stm8s.h
  • TIM6_CR1_URS : stm8s.h
  • TIM6_CR2_MMS : stm8s.h
  • TIM6_CR2_RESET_VALUE : stm8s.h
  • TIM6_DeInit() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_EGR_RESET_VALUE : stm8s.h
  • TIM6_EGR_TG : stm8s.h
  • TIM6_EGR_UG : stm8s.h
  • TIM6_EVENTSOURCE_TRIGGER : stm8s_tim6.h
  • TIM6_EventSource_TypeDef : stm8s_tim6.h
  • TIM6_EVENTSOURCE_UPDATE : stm8s_tim6.h
  • TIM6_FLAG_TRIGGER : stm8s_tim6.h
  • TIM6_FLAG_TypeDef : stm8s_tim6.h
  • TIM6_FLAG_UPDATE : stm8s_tim6.h
  • TIM6_GenerateEvent() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_GetCounter() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_GetFlagStatus() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_GetITStatus() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_GetPrescaler() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_IER_RESET_VALUE : stm8s.h
  • TIM6_IER_TIE : stm8s.h
  • TIM6_IER_UIE : stm8s.h
  • TIM6_InternalClockConfig() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_IT_TRIGGER : stm8s_tim6.h
  • TIM6_IT_TypeDef : stm8s_tim6.h
  • TIM6_IT_UPDATE : stm8s_tim6.h
  • TIM6_ITConfig() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_OPMODE_REPETITIVE : stm8s_tim6.h
  • TIM6_OPMODE_SINGLE : stm8s_tim6.h
  • TIM6_OPMode_TypeDef : stm8s_tim6.h
  • TIM6_PRESCALER_1 : stm8s_tim6.h
  • TIM6_PRESCALER_128 : stm8s_tim6.h
  • TIM6_PRESCALER_16 : stm8s_tim6.h
  • TIM6_PRESCALER_2 : stm8s_tim6.h
  • TIM6_PRESCALER_32 : stm8s_tim6.h
  • TIM6_PRESCALER_4 : stm8s_tim6.h
  • TIM6_PRESCALER_64 : stm8s_tim6.h
  • TIM6_PRESCALER_8 : stm8s_tim6.h
  • TIM6_Prescaler_TypeDef : stm8s_tim6.h
  • TIM6_PrescalerConfig() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_PSCR_PSC : stm8s.h
  • TIM6_PSCR_RESET_VALUE : stm8s.h
  • TIM6_PSCRELOADMODE_IMMEDIATE : stm8s_tim6.h
  • TIM6_PSCReloadMode_TypeDef : stm8s_tim6.h
  • TIM6_PSCRELOADMODE_UPDATE : stm8s_tim6.h
  • TIM6_SelectInputTrigger() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_SelectMasterSlaveMode() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_SelectOnePulseMode() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_SelectOutputTrigger() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_SelectSlaveMode() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_SetAutoreload() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_SetCounter() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_SLAVEMODE_DISABLE : stm8s_tim6.h
  • TIM6_SLAVEMODE_EXTERNAL1 : stm8s_tim6.h
  • TIM6_SLAVEMODE_GATED : stm8s_tim6.h
  • TIM6_SLAVEMODE_RESET : stm8s_tim6.h
  • TIM6_SLAVEMODE_TRIGGER : stm8s_tim6.h
  • TIM6_SlaveMode_TypeDef : stm8s_tim6.h
  • TIM6_SMCR_MSM : stm8s.h
  • TIM6_SMCR_RESET_VALUE : stm8s.h
  • TIM6_SMCR_SMS : stm8s.h
  • TIM6_SMCR_TS : stm8s.h
  • TIM6_SR1_RESET_VALUE : stm8s.h
  • TIM6_SR1_TIF : stm8s.h
  • TIM6_SR1_UIF : stm8s.h
  • TIM6_TimeBaseInit() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_TRGOSOURCE_ENABLE : stm8s_tim6.h
  • TIM6_TRGOSOURCE_RESET : stm8s_tim6.h
  • TIM6_TRGOSource_TypeDef : stm8s_tim6.h
  • TIM6_TRGOSOURCE_UPDATE : stm8s_tim6.h
  • TIM6_TS_TIM1 : stm8s_tim6.h
  • TIM6_TS_TIM5 : stm8s_tim6.h
  • TIM6_TS_TypeDef : stm8s_tim6.h
  • TIM6_TypeDef : stm8s.h
  • TIM6_UpdateDisableConfig() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_UpdateRequestConfig() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_UPDATESOURCE_GLOBAL : stm8s_tim6.h
  • TIM6_UPDATESOURCE_REGULAR : stm8s_tim6.h
  • TIM6_UpdateSource_TypeDef : stm8s_tim6.h
  • TINY : stm8s.h
  • trap : stm8s.h
  • TRUE : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
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  • c
  • d
  • e
  • f
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  • h
  • i
  • l
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  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- u -

  • u16 : stm8s.h
  • U16_MAX : stm8s.h
  • u32 : stm8s.h
  • U32_MAX : stm8s.h
  • u8 : stm8s.h
  • U8_MAX : stm8s.h
  • UART1_ADDRESS_MAX : stm8s_uart1.h
  • UART1_BaseAddress : stm8s.h
  • UART1_BRR1_DIVM : stm8s.h
  • UART1_BRR1_RESET_VALUE : stm8s.h
  • UART1_BRR2_DIVF : stm8s.h
  • UART1_BRR2_DIVM : stm8s.h
  • UART1_BRR2_RESET_VALUE : stm8s.h
  • UART1_ClearFlag() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_ClearITPendingBit() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_Cmd() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_CR1_M : stm8s.h
  • UART1_CR1_PCEN : stm8s.h
  • UART1_CR1_PIEN : stm8s.h
  • UART1_CR1_PS : stm8s.h
  • UART1_CR1_R8 : stm8s.h
  • UART1_CR1_RESET_VALUE : stm8s.h
  • UART1_CR1_T8 : stm8s.h
  • UART1_CR1_UARTD : stm8s.h
  • UART1_CR1_WAKE : stm8s.h
  • UART1_CR2_ILIEN : stm8s.h
  • UART1_CR2_REN : stm8s.h
  • UART1_CR2_RESET_VALUE : stm8s.h
  • UART1_CR2_RIEN : stm8s.h
  • UART1_CR2_RWU : stm8s.h
  • UART1_CR2_SBK : stm8s.h
  • UART1_CR2_TCIEN : stm8s.h
  • UART1_CR2_TEN : stm8s.h
  • UART1_CR2_TIEN : stm8s.h
  • UART1_CR3_CKEN : stm8s.h
  • UART1_CR3_CPHA : stm8s.h
  • UART1_CR3_CPOL : stm8s.h
  • UART1_CR3_LBCL : stm8s.h
  • UART1_CR3_LINEN : stm8s.h
  • UART1_CR3_RESET_VALUE : stm8s.h
  • UART1_CR3_STOP : stm8s.h
  • UART1_CR4_ADD : stm8s.h
  • UART1_CR4_LBDF : stm8s.h
  • UART1_CR4_LBDIEN : stm8s.h
  • UART1_CR4_LBDL : stm8s.h
  • UART1_CR4_RESET_VALUE : stm8s.h
  • UART1_CR5_HDSEL : stm8s.h
  • UART1_CR5_IREN : stm8s.h
  • UART1_CR5_IRLP : stm8s.h
  • UART1_CR5_NACK : stm8s.h
  • UART1_CR5_RESET_VALUE : stm8s.h
  • UART1_CR5_SCEN : stm8s.h
  • UART1_DeInit() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_FLAG_FE : stm8s_uart1.h
  • UART1_FLAG_IDLE : stm8s_uart1.h
  • UART1_FLAG_LBDF : stm8s_uart1.h
  • UART1_FLAG_NF : stm8s_uart1.h
  • UART1_FLAG_OR : stm8s_uart1.h
  • UART1_FLAG_PE : stm8s_uart1.h
  • UART1_FLAG_RXNE : stm8s_uart1.h
  • UART1_FLAG_SBK : stm8s_uart1.h
  • UART1_FLAG_TC : stm8s_uart1.h
  • UART1_FLAG_TXE : stm8s_uart1.h
  • UART1_Flag_TypeDef : stm8s_uart1.h
  • UART1_GetFlagStatus() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_GetITStatus() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_GTR_RESET_VALUE : stm8s.h
  • UART1_HalfDuplexCmd() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_Init() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_IrDACmd() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_IrDAConfig() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_IRDAMODE_LOWPOWER : stm8s_uart1.h
  • UART1_IRDAMODE_NORMAL : stm8s_uart1.h
  • UART1_IrDAMode_TypeDef : stm8s_uart1.h
  • UART1_IT_IDLE : stm8s_uart1.h
  • UART1_IT_LBDF : stm8s_uart1.h
  • UART1_IT_OR : stm8s_uart1.h
  • UART1_IT_PE : stm8s_uart1.h
  • UART1_IT_RXNE : stm8s_uart1.h
  • UART1_IT_RXNE_OR : stm8s_uart1.h
  • UART1_IT_TC : stm8s_uart1.h
  • UART1_IT_TXE : stm8s_uart1.h
  • UART1_IT_TypeDef : stm8s_uart1.h
  • UART1_ITConfig() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_LINBreakDetectionConfig() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_LINBREAKDETECTIONLENGTH_10BITS : stm8s_uart1.h
  • UART1_LINBREAKDETECTIONLENGTH_11BITS : stm8s_uart1.h
  • UART1_LINBreakDetectionLength_TypeDef : stm8s_uart1.h
  • UART1_LINCmd() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_MODE_RX_DISABLE : stm8s_uart1.h
  • UART1_MODE_RX_ENABLE : stm8s_uart1.h
  • UART1_MODE_TX_DISABLE : stm8s_uart1.h
  • UART1_MODE_TX_ENABLE : stm8s_uart1.h
  • UART1_MODE_TXRX_ENABLE : stm8s_uart1.h
  • UART1_Mode_TypeDef : stm8s_uart1.h
  • UART1_PARITY_EVEN : stm8s_uart1.h
  • UART1_PARITY_NO : stm8s_uart1.h
  • UART1_PARITY_ODD : stm8s_uart1.h
  • UART1_Parity_TypeDef : stm8s_uart1.h
  • UART1_PSCR_RESET_VALUE : stm8s.h
  • UART1_ReceiveData8() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_ReceiveData9() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_ReceiverWakeUpCmd() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_SendBreak() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_SendData8() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_SendData9() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_SetAddress() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_SetGuardTime() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_SetPrescaler() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_SmartCardCmd() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_SmartCardNACKCmd() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_SR_FE : stm8s.h
  • UART1_SR_IDLE : stm8s.h
  • UART1_SR_NF : stm8s.h
  • UART1_SR_OR : stm8s.h
  • UART1_SR_PE : stm8s.h
  • UART1_SR_RESET_VALUE : stm8s.h
  • UART1_SR_RXNE : stm8s.h
  • UART1_SR_TC : stm8s.h
  • UART1_SR_TXE : stm8s.h
  • UART1_STOPBITS_0_5 : stm8s_uart1.h
  • UART1_STOPBITS_1 : stm8s_uart1.h
  • UART1_STOPBITS_1_5 : stm8s_uart1.h
  • UART1_STOPBITS_2 : stm8s_uart1.h
  • UART1_StopBits_TypeDef : stm8s_uart1.h
  • UART1_SYNCMODE_CLOCK_DISABLE : stm8s_uart1.h
  • UART1_SYNCMODE_CLOCK_ENABLE : stm8s_uart1.h
  • UART1_SYNCMODE_CPHA_BEGINING : stm8s_uart1.h
  • UART1_SYNCMODE_CPHA_MIDDLE : stm8s_uart1.h
  • UART1_SYNCMODE_CPOL_HIGH : stm8s_uart1.h
  • UART1_SYNCMODE_CPOL_LOW : stm8s_uart1.h
  • UART1_SYNCMODE_LASTBIT_DISABLE : stm8s_uart1.h
  • UART1_SYNCMODE_LASTBIT_ENABLE : stm8s_uart1.h
  • UART1_SyncMode_TypeDef : stm8s_uart1.h
  • UART1_TypeDef : stm8s.h
  • UART1_WAKEUP_ADDRESSMARK : stm8s_uart1.h
  • UART1_WAKEUP_IDLELINE : stm8s_uart1.h
  • UART1_WakeUp_TypeDef : stm8s_uart1.h
  • UART1_WakeUpConfig() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_WORDLENGTH_8D : stm8s_uart1.h
  • UART1_WORDLENGTH_9D : stm8s_uart1.h
  • UART1_WordLength_TypeDef : stm8s_uart1.h
  • UART2_ADDRESS_MAX : stm8s_uart2.h
  • UART2_BaseAddress : stm8s.h
  • UART2_BRR1_DIVM : stm8s.h
  • UART2_BRR1_RESET_VALUE : stm8s.h
  • UART2_BRR2_DIVF : stm8s.h
  • UART2_BRR2_DIVM : stm8s.h
  • UART2_BRR2_RESET_VALUE : stm8s.h
  • UART2_ClearFlag() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_ClearITPendingBit() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_Cmd() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_CR1_M : stm8s.h
  • UART2_CR1_PCEN : stm8s.h
  • UART2_CR1_PIEN : stm8s.h
  • UART2_CR1_PS : stm8s.h
  • UART2_CR1_R8 : stm8s.h
  • UART2_CR1_RESET_VALUE : stm8s.h
  • UART2_CR1_T8 : stm8s.h
  • UART2_CR1_UARTD : stm8s.h
  • UART2_CR1_WAKE : stm8s.h
  • UART2_CR2_ILIEN : stm8s.h
  • UART2_CR2_REN : stm8s.h
  • UART2_CR2_RESET_VALUE : stm8s.h
  • UART2_CR2_RIEN : stm8s.h
  • UART2_CR2_RWU : stm8s.h
  • UART2_CR2_SBK : stm8s.h
  • UART2_CR2_TCIEN : stm8s.h
  • UART2_CR2_TEN : stm8s.h
  • UART2_CR2_TIEN : stm8s.h
  • UART2_CR3_CKEN : stm8s.h
  • UART2_CR3_CPHA : stm8s.h
  • UART2_CR3_CPOL : stm8s.h
  • UART2_CR3_LBCL : stm8s.h
  • UART2_CR3_LINEN : stm8s.h
  • UART2_CR3_RESET_VALUE : stm8s.h
  • UART2_CR3_STOP : stm8s.h
  • UART2_CR4_ADD : stm8s.h
  • UART2_CR4_LBDF : stm8s.h
  • UART2_CR4_LBDIEN : stm8s.h
  • UART2_CR4_LBDL : stm8s.h
  • UART2_CR4_RESET_VALUE : stm8s.h
  • UART2_CR5_IREN : stm8s.h
  • UART2_CR5_IRLP : stm8s.h
  • UART2_CR5_NACK : stm8s.h
  • UART2_CR5_RESET_VALUE : stm8s.h
  • UART2_CR5_SCEN : stm8s.h
  • UART2_CR6_LASE : stm8s.h
  • UART2_CR6_LDUM : stm8s.h
  • UART2_CR6_LHDF : stm8s.h
  • UART2_CR6_LHDIEN : stm8s.h
  • UART2_CR6_LSF : stm8s.h
  • UART2_CR6_LSLV : stm8s.h
  • UART2_CR6_RESET_VALUE : stm8s.h
  • UART2_DeInit() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_FLAG_FE : stm8s_uart2.h
  • UART2_FLAG_IDLE : stm8s_uart2.h
  • UART2_FLAG_LBDF : stm8s_uart2.h
  • UART2_FLAG_LHDF : stm8s_uart2.h
  • UART2_FLAG_LSF : stm8s_uart2.h
  • UART2_FLAG_NF : stm8s_uart2.h
  • UART2_FLAG_OR_LHE : stm8s_uart2.h
  • UART2_FLAG_PE : stm8s_uart2.h
  • UART2_FLAG_RXNE : stm8s_uart2.h
  • UART2_FLAG_SBK : stm8s_uart2.h
  • UART2_FLAG_TC : stm8s_uart2.h
  • UART2_FLAG_TXE : stm8s_uart2.h
  • UART2_Flag_TypeDef : stm8s_uart2.h
  • UART2_GetFlagStatus() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_GetITStatus() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_GTR_RESET_VALUE : stm8s.h
  • UART2_HalfDuplexCmd() : stm8s_uart2.h
  • UART2_Init() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_IrDACmd() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_IrDAConfig() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_IRDAMODE_LOWPOWER : stm8s_uart2.h
  • UART2_IRDAMODE_NORMAL : stm8s_uart2.h
  • UART2_IrDAMode_TypeDef : stm8s_uart2.h
  • UART2_IT_IDLE : stm8s_uart2.h
  • UART2_IT_LBDF : stm8s_uart2.h
  • UART2_IT_LHDF : stm8s_uart2.h
  • UART2_IT_OR : stm8s_uart2.h
  • UART2_IT_PE : stm8s_uart2.h
  • UART2_IT_RXNE : stm8s_uart2.h
  • UART2_IT_RXNE_OR : stm8s_uart2.h
  • UART2_IT_TC : stm8s_uart2.h
  • UART2_IT_TXE : stm8s_uart2.h
  • UART2_IT_TypeDef : stm8s_uart2.h
  • UART2_ITConfig() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_LIN_AUTOSYNC_DISABLE : stm8s_uart2.h
  • UART2_LIN_AUTOSYNC_ENABLE : stm8s_uart2.h
  • UART2_LIN_DIVUP_LBRR1 : stm8s_uart2.h
  • UART2_LIN_DIVUP_NEXTRXNE : stm8s_uart2.h
  • UART2_LIN_MODE_MASTER : stm8s_uart2.h
  • UART2_LIN_MODE_SLAVE : stm8s_uart2.h
  • UART2_LinAutosync_TypeDef : stm8s_uart2.h
  • UART2_LINBreakDetectionConfig() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_LINBREAKDETECTIONLENGTH_10BITS : stm8s_uart2.h
  • UART2_LINBREAKDETECTIONLENGTH_11BITS : stm8s_uart2.h
  • UART2_LINBreakDetectionLength_TypeDef : stm8s_uart2.h
  • UART2_LINCmd() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_LINConfig() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_LinDivUp_TypeDef : stm8s_uart2.h
  • UART2_LinMode_TypeDef : stm8s_uart2.h
  • UART2_MODE_RX_DISABLE : stm8s_uart2.h
  • UART2_MODE_RX_ENABLE : stm8s_uart2.h
  • UART2_MODE_TX_DISABLE : stm8s_uart2.h
  • UART2_MODE_TX_ENABLE : stm8s_uart2.h
  • UART2_MODE_TXRX_ENABLE : stm8s_uart2.h
  • UART2_Mode_TypeDef : stm8s_uart2.h
  • UART2_PARITY_EVEN : stm8s_uart2.h
  • UART2_PARITY_NO : stm8s_uart2.h
  • UART2_PARITY_ODD : stm8s_uart2.h
  • UART2_Parity_TypeDef : stm8s_uart2.h
  • UART2_PSCR_RESET_VALUE : stm8s.h
  • UART2_ReceiveData8() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_ReceiveData9() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_ReceiverWakeUpCmd() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_SendBreak() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_SendData8() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_SendData9() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_SetAddress() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_SetGuardTime() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_SetPrescaler() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_SmartCardCmd() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_SmartCardNACKCmd() : stm8s_uart2.c , stm8s_uart2.h
  • UART2_SR_FE : stm8s.h
  • UART2_SR_IDLE : stm8s.h
  • UART2_SR_NF : stm8s.h
  • UART2_SR_OR : stm8s.h
  • UART2_SR_PE : stm8s.h
  • UART2_SR_RESET_VALUE : stm8s.h
  • UART2_SR_RXNE : stm8s.h
  • UART2_SR_TC : stm8s.h
  • UART2_SR_TXE : stm8s.h
  • UART2_STOPBITS_0_5 : stm8s_uart2.h
  • UART2_STOPBITS_1 : stm8s_uart2.h
  • UART2_STOPBITS_1_5 : stm8s_uart2.h
  • UART2_STOPBITS_2 : stm8s_uart2.h
  • UART2_StopBits_TypeDef : stm8s_uart2.h
  • UART2_SYNCMODE_CLOCK_DISABLE : stm8s_uart2.h
  • UART2_SYNCMODE_CLOCK_ENABLE : stm8s_uart2.h
  • UART2_SYNCMODE_CPHA_BEGINING : stm8s_uart2.h
  • UART2_SYNCMODE_CPHA_MIDDLE : stm8s_uart2.h
  • UART2_SYNCMODE_CPOL_HIGH : stm8s_uart2.h
  • UART2_SYNCMODE_CPOL_LOW : stm8s_uart2.h
  • UART2_SYNCMODE_LASTBIT_DISABLE : stm8s_uart2.h
  • UART2_SYNCMODE_LASTBIT_ENABLE : stm8s_uart2.h
  • UART2_SyncMode_TypeDef : stm8s_uart2.h
  • UART2_TypeDef : stm8s.h
  • UART2_WAKEUP_ADDRESSMARK : stm8s_uart2.h
  • UART2_WAKEUP_IDLELINE : stm8s_uart2.h
  • UART2_WakeUp_TypeDef : stm8s_uart2.h
  • UART2_WakeUpConfig() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_WORDLENGTH_8D : stm8s_uart2.h
  • UART2_WORDLENGTH_9D : stm8s_uart2.h
  • UART2_WordLength_TypeDef : stm8s_uart2.h
  • UART3_ADDRESS_MAX : stm8s_uart3.h
  • UART3_BaseAddress : stm8s.h
  • UART3_BRR1_DIVM : stm8s.h
  • UART3_BRR1_RESET_VALUE : stm8s.h
  • UART3_BRR2_DIVF : stm8s.h
  • UART3_BRR2_DIVM : stm8s.h
  • UART3_BRR2_RESET_VALUE : stm8s.h
  • UART3_ClearFlag() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_ClearITPendingBit() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_Cmd() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_CR1_M : stm8s.h
  • UART3_CR1_PCEN : stm8s.h
  • UART3_CR1_PIEN : stm8s.h
  • UART3_CR1_PS : stm8s.h
  • UART3_CR1_R8 : stm8s.h
  • UART3_CR1_RESET_VALUE : stm8s.h
  • UART3_CR1_T8 : stm8s.h
  • UART3_CR1_UARTD : stm8s.h
  • UART3_CR1_WAKE : stm8s.h
  • UART3_CR2_ILIEN : stm8s.h
  • UART3_CR2_REN : stm8s.h
  • UART3_CR2_RESET_VALUE : stm8s.h
  • UART3_CR2_RIEN : stm8s.h
  • UART3_CR2_RWU : stm8s.h
  • UART3_CR2_SBK : stm8s.h
  • UART3_CR2_TCIEN : stm8s.h
  • UART3_CR2_TEN : stm8s.h
  • UART3_CR2_TIEN : stm8s.h
  • UART3_CR3_LINEN : stm8s.h
  • UART3_CR3_RESET_VALUE : stm8s.h
  • UART3_CR3_STOP : stm8s.h
  • UART3_CR4_ADD : stm8s.h
  • UART3_CR4_LBDF : stm8s.h
  • UART3_CR4_LBDIEN : stm8s.h
  • UART3_CR4_LBDL : stm8s.h
  • UART3_CR4_RESET_VALUE : stm8s.h
  • UART3_CR6_LASE : stm8s.h
  • UART3_CR6_LDUM : stm8s.h
  • UART3_CR6_LHDF : stm8s.h
  • UART3_CR6_LHDIEN : stm8s.h
  • UART3_CR6_LSF : stm8s.h
  • UART3_CR6_LSLV : stm8s.h
  • UART3_CR6_RESET_VALUE : stm8s.h
  • UART3_DeInit() : stm8s_uart3.c , stm8s_uart3.h
  • UART3_FLAG_FE : stm8s_uart3.h
  • UART3_FLAG_IDLE : stm8s_uart3.h
  • UART3_FLAG_LBDF : stm8s_uart3.h
  • UART3_FLAG_LHDF : stm8s_uart3.h
  • UART3_FLAG_LSF : stm8s_uart3.h
  • UART3_FLAG_NF : stm8s_uart3.h
  • UART3_FLAG_OR_LHE : stm8s_uart3.h
  • UART3_FLAG_PE : stm8s_uart3.h
  • UART3_FLAG_RXNE : stm8s_uart3.h
  • UART3_FLAG_SBK : stm8s_uart3.h
  • UART3_FLAG_TC : stm8s_uart3.h
  • UART3_FLAG_TXE : stm8s_uart3.h
  • UART3_Flag_TypeDef : stm8s_uart3.h
  • UART3_GetFlagStatus() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_GetITStatus() : stm8s_uart3.c , stm8s_uart3.h
  • UART3_Init() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_IT_IDLE : stm8s_uart3.h
  • UART3_IT_LBDF : stm8s_uart3.h
  • UART3_IT_LHDF : stm8s_uart3.h
  • UART3_IT_OR : stm8s_uart3.h
  • UART3_IT_PE : stm8s_uart3.h
  • UART3_IT_RXNE : stm8s_uart3.h
  • UART3_IT_RXNE_OR : stm8s_uart3.h
  • UART3_IT_TC : stm8s_uart3.h
  • UART3_IT_TXE : stm8s_uart3.h
  • UART3_IT_TypeDef : stm8s_uart3.h
  • UART3_ITConfig() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_LIN_AUTOSYNC_DISABLE : stm8s_uart3.h
  • UART3_LIN_AUTOSYNC_ENABLE : stm8s_uart3.h
  • UART3_LIN_DIVUP_LBRR1 : stm8s_uart3.h
  • UART3_LIN_DIVUP_NEXTRXNE : stm8s_uart3.h
  • UART3_LIN_MODE_MASTER : stm8s_uart3.h
  • UART3_LIN_MODE_SLAVE : stm8s_uart3.h
  • UART3_LinAutosync_TypeDef : stm8s_uart3.h
  • UART3_LINBreakDetectionConfig() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_LINBREAKDETECTIONLENGTH_10BITS : stm8s_uart3.h
  • UART3_LINBREAKDETECTIONLENGTH_11BITS : stm8s_uart3.h
  • UART3_LINBreakDetectionLength_TypeDef : stm8s_uart3.h
  • UART3_LINCmd() : stm8s_uart3.c , stm8s_uart3.h
  • UART3_LINConfig() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_LinDivUp_TypeDef : stm8s_uart3.h
  • UART3_LinMode_TypeDef : stm8s_uart3.h
  • UART3_MODE_RX_DISABLE : stm8s_uart3.h
  • UART3_MODE_RX_ENABLE : stm8s_uart3.h
  • UART3_MODE_TX_DISABLE : stm8s_uart3.h
  • UART3_MODE_TX_ENABLE : stm8s_uart3.h
  • UART3_MODE_TXRX_ENABLE : stm8s_uart3.h
  • UART3_Mode_TypeDef : stm8s_uart3.h
  • UART3_PARITY_EVEN : stm8s_uart3.h
  • UART3_PARITY_NO : stm8s_uart3.h
  • UART3_PARITY_ODD : stm8s_uart3.h
  • UART3_Parity_TypeDef : stm8s_uart3.h
  • UART3_ReceiveData8() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_ReceiveData9() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_ReceiverWakeUpCmd() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_SendBreak() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_SendData8() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_SendData9() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_SetAddress() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_SR_FE : stm8s.h
  • UART3_SR_IDLE : stm8s.h
  • UART3_SR_NF : stm8s.h
  • UART3_SR_OR : stm8s.h
  • UART3_SR_PE : stm8s.h
  • UART3_SR_RESET_VALUE : stm8s.h
  • UART3_SR_RXNE : stm8s.h
  • UART3_SR_TC : stm8s.h
  • UART3_SR_TXE : stm8s.h
  • UART3_STOPBITS_1 : stm8s_uart3.h
  • UART3_STOPBITS_2 : stm8s_uart3.h
  • UART3_StopBits_TypeDef : stm8s_uart3.h
  • UART3_TypeDef : stm8s.h
  • UART3_WAKEUP_ADDRESSMARK : stm8s_uart3.h
  • UART3_WAKEUP_IDLELINE : stm8s_uart3.h
  • UART3_WakeUp_TypeDef : stm8s_uart3.h
  • UART3_WakeUpConfig() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_WORDLENGTH_8D : stm8s_uart3.h
  • UART3_WORDLENGTH_9D : stm8s_uart3.h
  • UART3_WordLength_TypeDef : stm8s_uart3.h
  • UART4_ADDRESS_MAX : stm8s_uart4.h
  • UART4_BaseAddress : stm8s.h
  • UART4_ClearFlag() : stm8s_uart4.h , stm8s_uart4.c
  • UART4_ClearITPendingBit() : stm8s_uart4.h , stm8s_uart4.c
  • UART4_Cmd() : stm8s_uart4.c , stm8s_uart4.h
  • UART4_DeInit() : stm8s_uart4.c , stm8s_uart4.h
  • UART4_FLAG_FE : stm8s_uart4.h
  • UART4_FLAG_IDLE : stm8s_uart4.h
  • UART4_FLAG_LBDF : stm8s_uart4.h
  • UART4_FLAG_LHDF : stm8s_uart4.h
  • UART4_FLAG_LSF : stm8s_uart4.h
  • UART4_FLAG_NF : stm8s_uart4.h
  • UART4_FLAG_OR_LHE : stm8s_uart4.h
  • UART4_FLAG_PE : stm8s_uart4.h
  • UART4_FLAG_RXNE : stm8s_uart4.h
  • UART4_FLAG_SBK : stm8s_uart4.h
  • UART4_FLAG_TC : stm8s_uart4.h
  • UART4_FLAG_TXE : stm8s_uart4.h
  • UART4_Flag_TypeDef : stm8s_uart4.h
  • UART4_GetFlagStatus() : stm8s_uart4.h , stm8s_uart4.c
  • UART4_GetITStatus() : stm8s_uart4.h , stm8s_uart4.c
  • UART4_HalfDuplexCmd() : stm8s_uart4.c , stm8s_uart4.h
  • UART4_Init() : stm8s_uart4.c , stm8s_uart4.h
  • UART4_IrDACmd() : stm8s_uart4.c , stm8s_uart4.h
  • UART4_IrDAConfig() : stm8s_uart4.c , stm8s_uart4.h
  • UART4_IRDAMODE_LOWPOWER : stm8s_uart4.h
  • UART4_IRDAMODE_NORMAL : stm8s_uart4.h
  • UART4_IrDAMode_TypeDef : stm8s_uart4.h
  • UART4_IT_IDLE : stm8s_uart4.h
  • UART4_IT_LBDF : stm8s_uart4.h
  • UART4_IT_LHDF : stm8s_uart4.h
  • UART4_IT_OR : stm8s_uart4.h
  • UART4_IT_PE : stm8s_uart4.h
  • UART4_IT_RXNE : stm8s_uart4.h
  • UART4_IT_RXNE_OR : stm8s_uart4.h
  • UART4_IT_TC : stm8s_uart4.h
  • UART4_IT_TXE : stm8s_uart4.h
  • UART4_IT_TypeDef : stm8s_uart4.h
  • UART4_ITConfig() : stm8s_uart4.h , stm8s_uart4.c
  • UART4_LIN_AUTOSYNC_DISABLE : stm8s_uart4.h
  • UART4_LIN_AUTOSYNC_ENABLE : stm8s_uart4.h
  • UART4_LIN_DIVUP_LBRR1 : stm8s_uart4.h
  • UART4_LIN_DIVUP_NEXTRXNE : stm8s_uart4.h
  • UART4_LIN_MODE_MASTER : stm8s_uart4.h
  • UART4_LIN_MODE_SLAVE : stm8s_uart4.h
  • UART4_LinAutosync_TypeDef : stm8s_uart4.h
  • UART4_LINBreakDetectionConfig() : stm8s_uart4.h , stm8s_uart4.c
  • UART4_LINBREAKDETECTIONLENGTH_10BITS : stm8s_uart4.h
  • UART4_LINBREAKDETECTIONLENGTH_11BITS : stm8s_uart4.h
  • UART4_LINBreakDetectionLength_TypeDef : stm8s_uart4.h
  • UART4_LINCmd() : stm8s_uart4.h , stm8s_uart4.c
  • UART4_LINConfig() : stm8s_uart4.h , stm8s_uart4.c
  • UART4_LinDivUp_TypeDef : stm8s_uart4.h
  • UART4_LinMode_TypeDef : stm8s_uart4.h
  • UART4_MODE_RX_DISABLE : stm8s_uart4.h
  • UART4_MODE_RX_ENABLE : stm8s_uart4.h
  • UART4_MODE_TX_DISABLE : stm8s_uart4.h
  • UART4_MODE_TX_ENABLE : stm8s_uart4.h
  • UART4_MODE_TXRX_ENABLE : stm8s_uart4.h
  • UART4_Mode_TypeDef : stm8s_uart4.h
  • UART4_PARITY_EVEN : stm8s_uart4.h
  • UART4_PARITY_NO : stm8s_uart4.h
  • UART4_PARITY_ODD : stm8s_uart4.h
  • UART4_Parity_TypeDef : stm8s_uart4.h
  • UART4_ReceiveData8() : stm8s_uart4.h , stm8s_uart4.c
  • UART4_ReceiveData9() : stm8s_uart4.h , stm8s_uart4.c
  • UART4_ReceiverWakeUpCmd() : stm8s_uart4.h , stm8s_uart4.c
  • UART4_SendBreak() : stm8s_uart4.c , stm8s_uart4.h
  • UART4_SendData8() : stm8s_uart4.c , stm8s_uart4.h
  • UART4_SendData9() : stm8s_uart4.h , stm8s_uart4.c
  • UART4_SetAddress() : stm8s_uart4.h , stm8s_uart4.c
  • UART4_SetGuardTime() : stm8s_uart4.c , stm8s_uart4.h
  • UART4_SetPrescaler() : stm8s_uart4.h , stm8s_uart4.c
  • UART4_SmartCardCmd() : stm8s_uart4.c , stm8s_uart4.h
  • UART4_SmartCardNACKCmd() : stm8s_uart4.c , stm8s_uart4.h
  • UART4_STOPBITS_0_5 : stm8s_uart4.h
  • UART4_STOPBITS_1 : stm8s_uart4.h
  • UART4_STOPBITS_1_5 : stm8s_uart4.h
  • UART4_STOPBITS_2 : stm8s_uart4.h
  • UART4_StopBits_TypeDef : stm8s_uart4.h
  • UART4_SYNCMODE_CLOCK_DISABLE : stm8s_uart4.h
  • UART4_SYNCMODE_CLOCK_ENABLE : stm8s_uart4.h
  • UART4_SYNCMODE_CPHA_BEGINING : stm8s_uart4.h
  • UART4_SYNCMODE_CPHA_MIDDLE : stm8s_uart4.h
  • UART4_SYNCMODE_CPOL_HIGH : stm8s_uart4.h
  • UART4_SYNCMODE_CPOL_LOW : stm8s_uart4.h
  • UART4_SYNCMODE_LASTBIT_DISABLE : stm8s_uart4.h
  • UART4_SYNCMODE_LASTBIT_ENABLE : stm8s_uart4.h
  • UART4_SyncMode_TypeDef : stm8s_uart4.h
  • UART4_WAKEUP_ADDRESSMARK : stm8s_uart4.h
  • UART4_WAKEUP_IDLELINE : stm8s_uart4.h
  • UART4_WakeUp_TypeDef : stm8s_uart4.h
  • UART4_WakeUpConfig() : stm8s_uart4.c , stm8s_uart4.h
  • UART4_WORDLENGTH_8D : stm8s_uart4.h
  • UART4_WORDLENGTH_9D : stm8s_uart4.h
  • UART4_WordLength_TypeDef : stm8s_uart4.h
  • uint16_t : stm8s.h
  • uint32_t : stm8s.h
  • uint8_t : stm8s.h
  • USE_STDPERIPH_DRIVER : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- v -

  • ValBit : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- w -

  • wfi : stm8s.h
  • WWDG : stm8s.h
  • WWDG_BaseAddress : stm8s.h
  • WWDG_CR_RESET_VALUE : stm8s.h
  • WWDG_CR_T : stm8s.h
  • WWDG_CR_T6 : stm8s.h
  • WWDG_CR_WDGA : stm8s.h
  • WWDG_GetCounter() : stm8s_wwdg.h , stm8s_wwdg.c
  • WWDG_Init() : stm8s_wwdg.h , stm8s_wwdg.c
  • WWDG_SetCounter() : stm8s_wwdg.h , stm8s_wwdg.c
  • WWDG_SetWindowValue() : stm8s_wwdg.c , stm8s_wwdg.h
  • WWDG_SWReset() : stm8s_wwdg.h , stm8s_wwdg.c
  • WWDG_TypeDef : stm8s.h
  • WWDG_WR_MSB : stm8s.h
  • WWDG_WR_RESET_VALUE : stm8s.h
  • WWDG_WR_W : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- _ -

  • __I : stm8s.h
  • __IO : stm8s.h
  • __O : stm8s.h
  • __STM8S_STDPERIPH_VERSION : stm8s.h
  • __STM8S_STDPERIPH_VERSION_MAIN : stm8s.h
  • __STM8S_STDPERIPH_VERSION_RC : stm8s.h
  • __STM8S_STDPERIPH_VERSION_SUB1 : stm8s.h
  • __STM8S_STDPERIPH_VERSION_SUB2 : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- l -

  • LSI_FREQUENCY_MAX : stm8s_awu.h , stm8s_beep.h
  • LSI_FREQUENCY_MIN : stm8s_beep.h , stm8s_awu.h
  • LSI_VALUE : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- m -

  • MemoryAddressCast : stm8s.h
  • MskBit : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- n -

  • NEAR : stm8s.h
  • nop : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- o -

  • OPERATION_TIMEOUT : stm8s_flash.c
  • OPT : stm8s.h
  • OPT_BaseAddress : stm8s.h
  • OPTION_BYTE_END_PHYSICAL_ADDRESS : stm8s_flash.h
  • OPTION_BYTE_START_PHYSICAL_ADDRESS : stm8s_flash.h


STM8S/A Standard Peripherals Drivers: Globals

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- a -

  • ADC1_BaseAddress : stm8s.h
  • ADC2_BaseAddress : stm8s.h
  • AffBit : stm8s.h
  • AREA : stm8s.h
  • AWU : stm8s.h
  • AWU_APR_APR : stm8s.h
  • AWU_APR_RESET_VALUE : stm8s.h
  • AWU_BaseAddress : stm8s.h
  • AWU_CSR_AWUEN : stm8s.h
  • AWU_CSR_AWUF : stm8s.h
  • AWU_CSR_MSR : stm8s.h
  • AWU_CSR_RESET_VALUE : stm8s.h
  • AWU_TBR_AWUTB : stm8s.h
  • AWU_TBR_RESET_VALUE : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- b -

  • BEEP : stm8s.h
  • BEEP_BaseAddress : stm8s.h
  • BEEP_CALIBRATION_DEFAULT : stm8s_beep.h
  • BEEP_CSR_BEEPDIV : stm8s.h
  • BEEP_CSR_BEEPEN : stm8s.h
  • BEEP_CSR_BEEPSEL : stm8s.h
  • BEEP_CSR_RESET_VALUE : stm8s.h
  • BIT_MASK : stm8s_wwdg.c
  • BitClr : stm8s.h
  • BitSet : stm8s.h
  • BitVal : stm8s.h
  • BYTE_0 : stm8s.h
  • BYTE_1 : stm8s.h
  • BYTE_2 : stm8s.h
  • BYTE_3 : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- c -

  • CAN_ACKNOWLEDGE_TIMEOUT : stm8s_can.c
  • CAN_BaseAddress : stm8s.h
  • CAN_BTR1_RESET_VALUE : stm8s.h
  • CAN_BTR2_RESET_VALUE : stm8s.h
  • CAN_DGR_LBKM : stm8s.h
  • CAN_DGR_RESET_VALUE : stm8s.h
  • CAN_DGR_RX : stm8s.h
  • CAN_DGR_SAMP : stm8s.h
  • CAN_DGR_SLIM : stm8s.h
  • CAN_DGR_TXM2E : stm8s.h
  • CAN_DLC_MAX : stm8s_can.h
  • CAN_EIER_BOFIE : stm8s.h
  • CAN_EIER_EPVIE : stm8s.h
  • CAN_EIER_ERRIE : stm8s.h
  • CAN_EIER_EWGIE : stm8s.h
  • CAN_EIER_LECIE : stm8s.h
  • CAN_EIER_RESET_VALUE : stm8s.h
  • CAN_ESR_BOFF : stm8s.h
  • CAN_ESR_EPVF : stm8s.h
  • CAN_ESR_EWGF : stm8s.h
  • CAN_ESR_LEC : stm8s.h
  • CAN_ESR_LEC0 : stm8s.h
  • CAN_ESR_LEC1 : stm8s.h
  • CAN_ESR_LEC2 : stm8s.h
  • CAN_ESR_RESET_VALUE : stm8s.h
  • CAN_EXTID_SIZE : stm8s_can.h
  • CAN_FCR1_FACT0 : stm8s.h
  • CAN_FCR1_FACT1 : stm8s.h
  • CAN_FCR1_FSC00 : stm8s.h
  • CAN_FCR1_FSC01 : stm8s.h
  • CAN_FCR1_FSC10 : stm8s.h
  • CAN_FCR1_FSC11 : stm8s.h
  • CAN_FCR2_FACT2 : stm8s.h
  • CAN_FCR2_FACT3 : stm8s.h
  • CAN_FCR2_FSC20 : stm8s.h
  • CAN_FCR2_FSC21 : stm8s.h
  • CAN_FCR2_FSC30 : stm8s.h
  • CAN_FCR2_FSC31 : stm8s.h
  • CAN_FCR3_FACT4 : stm8s.h
  • CAN_FCR3_FACT5 : stm8s.h
  • CAN_FCR3_FSC40 : stm8s.h
  • CAN_FCR3_FSC41 : stm8s.h
  • CAN_FCR3_FSC50 : stm8s.h
  • CAN_FCR3_FSC51 : stm8s.h
  • CAN_FCR_RESET_VALUE : stm8s.h
  • CAN_FMR1_FMH0 : stm8s.h
  • CAN_FMR1_FMH1 : stm8s.h
  • CAN_FMR1_FMH2 : stm8s.h
  • CAN_FMR1_FMH3 : stm8s.h
  • CAN_FMR1_FML0 : stm8s.h
  • CAN_FMR1_FML1 : stm8s.h
  • CAN_FMR1_FML2 : stm8s.h
  • CAN_FMR1_FML3 : stm8s.h
  • CAN_FMR1_RESET_VALUE : stm8s.h
  • CAN_FMR2_FMH4 : stm8s.h
  • CAN_FMR2_FMH5 : stm8s.h
  • CAN_FMR2_FML4 : stm8s.h
  • CAN_FMR2_FML5 : stm8s.h
  • CAN_FMR2_RESET_VALUE : stm8s.h
  • CAN_IDLIST_IDMASK_MASK : stm8s_can.c
  • CAN_IDMASK_IDLIST_MASK : stm8s_can.c
  • CAN_IER_FFIE : stm8s.h
  • CAN_IER_FMPIE : stm8s.h
  • CAN_IER_FOVIE : stm8s.h
  • CAN_IER_RESET_VALUE : stm8s.h
  • CAN_IER_TMEIE : stm8s.h
  • CAN_IER_WKUIE : stm8s.h
  • CAN_IT_CONFIG_MASK : stm8s_can.h
  • CAN_MCR_ABOM : stm8s.h
  • CAN_MCR_AWUM : stm8s.h
  • CAN_MCR_INRQ : stm8s.h
  • CAN_MCR_NART : stm8s.h
  • CAN_MCR_RESET_VALUE : stm8s.h
  • CAN_MCR_RFLM : stm8s.h
  • CAN_MCR_SLEEP : stm8s.h
  • CAN_MCR_TTCM : stm8s.h
  • CAN_MCR_TXFP : stm8s.h
  • CAN_MCSR_ABRQ : stm8s.h
  • CAN_MCSR_ALST : stm8s.h
  • CAN_MCSR_RESET_VALUE : stm8s.h
  • CAN_MCSR_RQCP : stm8s.h
  • CAN_MCSR_TERR : stm8s.h
  • CAN_MCSR_TXOK : stm8s.h
  • CAN_MCSR_TXRQ : stm8s.h
  • CAN_MDLC_RESET_VALUE : stm8s.h
  • CAN_MDLCR_DLC : stm8s.h
  • CAN_MDLCR_TGT : stm8s.h
  • CAN_MFMI_RESET_VALUE : stm8s.h
  • CAN_MIDR1_IDE : stm8s.h
  • CAN_MIDR1_RTR : stm8s.h
  • CAN_MODE_MASK : stm8s_can.c
  • CAN_MSR_ERRI : stm8s.h
  • CAN_MSR_INAK : stm8s.h
  • CAN_MSR_RESET_VALUE : stm8s.h
  • CAN_MSR_RX : stm8s.h
  • CAN_MSR_SLAK : stm8s.h
  • CAN_MSR_TX : stm8s.h
  • CAN_MSR_WKUI : stm8s.h
  • CAN_PSR_PS0 : stm8s.h
  • CAN_PSR_PS1 : stm8s.h
  • CAN_PSR_PS2 : stm8s.h
  • CAN_PSR_RESET_VALUE : stm8s.h
  • CAN_RECR_REC0 : stm8s.h
  • CAN_RECR_REC1 : stm8s.h
  • CAN_RECR_REC2 : stm8s.h
  • CAN_RECR_REC3 : stm8s.h
  • CAN_RECR_REC4 : stm8s.h
  • CAN_RECR_REC5 : stm8s.h
  • CAN_RECR_REC6 : stm8s.h
  • CAN_RECR_REC7 : stm8s.h
  • CAN_RECR_RESET_VALUE : stm8s.h
  • CAN_RFR_FMP01 : stm8s.h
  • CAN_RFR_FOVR : stm8s.h
  • CAN_RFR_FULL : stm8s.h
  • CAN_RFR_RESET_VALUE : stm8s.h
  • CAN_RFR_RFOM : stm8s.h
  • CAN_STDID_SIZE : stm8s_can.h
  • CAN_TECR_RESET_VALUE : stm8s.h
  • CAN_TECR_TEC0 : stm8s.h
  • CAN_TECR_TEC1 : stm8s.h
  • CAN_TECR_TEC2 : stm8s.h
  • CAN_TECR_TEC3 : stm8s.h
  • CAN_TECR_TEC4 : stm8s.h
  • CAN_TECR_TEC5 : stm8s.h
  • CAN_TECR_TEC6 : stm8s.h
  • CAN_TECR_TEC7 : stm8s.h
  • CAN_TPR_CODE0 : stm8s.h
  • CAN_TPR_LOW0 : stm8s.h
  • CAN_TPR_LOW1 : stm8s.h
  • CAN_TPR_LOW2 : stm8s.h
  • CAN_TPR_RESET_VALUE : stm8s.h
  • CAN_TPR_TME0 : stm8s.h
  • CAN_TPR_TME1 : stm8s.h
  • CAN_TPR_TME2 : stm8s.h
  • CAN_TSR_RESET_VALUE : stm8s.h
  • CAN_TSR_RQCP0 : stm8s.h
  • CAN_TSR_RQCP012 : stm8s.h
  • CAN_TSR_RQCP1 : stm8s.h
  • CAN_TSR_RQCP2 : stm8s.h
  • CAN_TSR_TXOK0 : stm8s.h
  • CAN_TSR_TXOK1 : stm8s.h
  • CAN_TSR_TXOK2 : stm8s.h
  • CCMR_TIxDirect_Set : stm8s.h
  • CFG : stm8s.h
  • CFG_BaseAddress : stm8s.h
  • CFG_GCR_AL : stm8s.h
  • CFG_GCR_RESET_VALUE : stm8s.h
  • CFG_GCR_SWD : stm8s.h
  • ChgBit : stm8s.h
  • CLK : stm8s.h
  • CLK_BaseAddress : stm8s.h
  • CLK_CCOR_CCOBSY : stm8s.h
  • CLK_CCOR_CCOEN : stm8s.h
  • CLK_CCOR_CCORDY : stm8s.h
  • CLK_CCOR_CCOSEL : stm8s.h
  • CLK_CCOR_RESET_VALUE : stm8s.h
  • CLK_CKDIVR_CPUDIV : stm8s.h
  • CLK_CKDIVR_HSIDIV : stm8s.h
  • CLK_CKDIVR_RESET_VALUE : stm8s.h
  • CLK_CMSR_CKM : stm8s.h
  • CLK_CMSR_RESET_VALUE : stm8s.h
  • CLK_CSSR_AUX : stm8s.h
  • CLK_CSSR_CSSD : stm8s.h
  • CLK_CSSR_CSSDIE : stm8s.h
  • CLK_CSSR_CSSEN : stm8s.h
  • CLK_CSSR_RESET_VALUE : stm8s.h
  • CLK_ECKR_HSEEN : stm8s.h
  • CLK_ECKR_HSERDY : stm8s.h
  • CLK_ECKR_RESET_VALUE : stm8s.h
  • CLK_HSITRIMR_HSITRIM : stm8s.h
  • CLK_HSITRIMR_RESET_VALUE : stm8s.h
  • CLK_ICKR_FHWU : stm8s.h
  • CLK_ICKR_HSIEN : stm8s.h
  • CLK_ICKR_HSIRDY : stm8s.h
  • CLK_ICKR_LSIEN : stm8s.h
  • CLK_ICKR_LSIRDY : stm8s.h
  • CLK_ICKR_RESET_VALUE : stm8s.h
  • CLK_ICKR_SWUAH : stm8s.h
  • CLK_PCKENR1_I2C : stm8s.h
  • CLK_PCKENR1_RESET_VALUE : stm8s.h
  • CLK_PCKENR1_SPI : stm8s.h
  • CLK_PCKENR1_TIM1 : stm8s.h
  • CLK_PCKENR1_TIM2 : stm8s.h
  • CLK_PCKENR1_TIM3 : stm8s.h
  • CLK_PCKENR1_TIM4 : stm8s.h
  • CLK_PCKENR1_TIM5 : stm8s.h
  • CLK_PCKENR1_TIM6 : stm8s.h
  • CLK_PCKENR1_UART1 : stm8s.h
  • CLK_PCKENR1_UART2 : stm8s.h
  • CLK_PCKENR1_UART3 : stm8s.h
  • CLK_PCKENR2_ADC : stm8s.h
  • CLK_PCKENR2_AWU : stm8s.h
  • CLK_PCKENR2_CAN : stm8s.h
  • CLK_PCKENR2_RESET_VALUE : stm8s.h
  • CLK_SWCR_RESET_VALUE : stm8s.h
  • CLK_SWCR_SWBSY : stm8s.h
  • CLK_SWCR_SWEN : stm8s.h
  • CLK_SWCR_SWIEN : stm8s.h
  • CLK_SWCR_SWIF : stm8s.h
  • CLK_SWIMCCR_RESET_VALUE : stm8s.h
  • CLK_SWIMCCR_SWIMDIV : stm8s.h
  • CLK_SWR_RESET_VALUE : stm8s.h
  • CLK_SWR_SWI : stm8s.h
  • CLK_TIMEOUT : stm8s_clk.h
  • ClrBit : stm8s.h
  • CONST : stm8s.h
  • CPU_CC_I1I0 : stm8s.h
  • CPU_SOFT_INT_DISABLED : stm8s_itc.h


STM8S/A Standard Peripherals Drivers: Globals

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- d -

  • disableInterrupts : stm8s.h
  • DM : stm8s.h
  • DM_BaseAddress : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- e -

  • EEPROM : stm8s.h
  • enableInterrupts : stm8s.h
  • EXTI : stm8s.h
  • EXTI_BaseAddress : stm8s.h
  • EXTI_CR1_PAIS : stm8s.h
  • EXTI_CR1_PBIS : stm8s.h
  • EXTI_CR1_PCIS : stm8s.h
  • EXTI_CR1_PDIS : stm8s.h
  • EXTI_CR1_RESET_VALUE : stm8s.h
  • EXTI_CR2_PEIS : stm8s.h
  • EXTI_CR2_RESET_VALUE : stm8s.h
  • EXTI_CR2_TLIS : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- f -

  • FAR : stm8s.h
  • FLAG_Mask : stm8s_i2c.c
  • FLASH : stm8s.h
  • FLASH_BaseAddress : stm8s.h
  • FLASH_CLEAR_BYTE : stm8s_flash.c
  • FLASH_CR1_AHALT : stm8s.h
  • FLASH_CR1_FIX : stm8s.h
  • FLASH_CR1_HALT : stm8s.h
  • FLASH_CR1_IE : stm8s.h
  • FLASH_CR1_RESET_VALUE : stm8s.h
  • FLASH_CR2_ERASE : stm8s.h
  • FLASH_CR2_FPRG : stm8s.h
  • FLASH_CR2_OPT : stm8s.h
  • FLASH_CR2_PRG : stm8s.h
  • FLASH_CR2_RESET_VALUE : stm8s.h
  • FLASH_CR2_WPRG : stm8s.h
  • FLASH_DUKR_DUK : stm8s.h
  • FLASH_DUKR_RESET_VALUE : stm8s.h
  • FLASH_IAPSR_DUL : stm8s.h
  • FLASH_IAPSR_EOP : stm8s.h
  • FLASH_IAPSR_HVOFF : stm8s.h
  • FLASH_IAPSR_PUL : stm8s.h
  • FLASH_IAPSR_RESET_VALUE : stm8s.h
  • FLASH_IAPSR_WR_PG_DIS : stm8s.h
  • FLASH_NCR2_NERASE : stm8s.h
  • FLASH_NCR2_NFPRG : stm8s.h
  • FLASH_NCR2_NOPT : stm8s.h
  • FLASH_NCR2_NPRG : stm8s.h
  • FLASH_NCR2_NWPRG : stm8s.h
  • FLASH_NCR2_RESET_VALUE : stm8s.h
  • FLASH_OPTIONBYTE_ERROR : stm8s_flash.h
  • FLASH_PROG_START_PHYSICAL_ADDRESS : stm8s_flash.h
  • FLASH_PUKR_PUK : stm8s.h
  • FLASH_PUKR_RESET_VALUE : stm8s.h
  • FLASH_RASS_KEY1 : stm8s_flash.h
  • FLASH_RASS_KEY2 : stm8s_flash.h
  • FLASH_SET_BYTE : stm8s_flash.c


STM8S/A Standard Peripherals Drivers: Globals

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- g -

  • GPIO_CR1_RESET_VALUE : stm8s.h
  • GPIO_CR2_RESET_VALUE : stm8s.h
  • GPIO_DDR_RESET_VALUE : stm8s.h
  • GPIO_ODR_RESET_VALUE : stm8s.h
  • GPIOA : stm8s.h
  • GPIOA_BaseAddress : stm8s.h
  • GPIOB : stm8s.h
  • GPIOB_BaseAddress : stm8s.h
  • GPIOC : stm8s.h
  • GPIOC_BaseAddress : stm8s.h
  • GPIOD : stm8s.h
  • GPIOD_BaseAddress : stm8s.h
  • GPIOE : stm8s.h
  • GPIOE_BaseAddress : stm8s.h
  • GPIOF : stm8s.h
  • GPIOF_BaseAddress : stm8s.h
  • GPIOG_BaseAddress : stm8s.h
  • GPIOH_BaseAddress : stm8s.h
  • GPIOI_BaseAddress : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- h -

  • halt : stm8s.h
  • HSE_VALUE : stm8s.h
  • HSI_VALUE : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

  • File List
  • Globals
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  • Variables
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- i -

  • I2C : stm8s.h
  • I2C_BaseAddress : stm8s.h
  • I2C_CCRH_CCR : stm8s.h
  • I2C_CCRH_DUTY : stm8s.h
  • I2C_CCRH_FS : stm8s.h
  • I2C_CCRH_RESET_VALUE : stm8s.h
  • I2C_CCRL_CCR : stm8s.h
  • I2C_CCRL_RESET_VALUE : stm8s.h
  • I2C_CR1_ENGC : stm8s.h
  • I2C_CR1_NOSTRETCH : stm8s.h
  • I2C_CR1_PE : stm8s.h
  • I2C_CR1_RESET_VALUE : stm8s.h
  • I2C_CR2_ACK : stm8s.h
  • I2C_CR2_POS : stm8s.h
  • I2C_CR2_RESET_VALUE : stm8s.h
  • I2C_CR2_START : stm8s.h
  • I2C_CR2_STOP : stm8s.h
  • I2C_CR2_SWRST : stm8s.h
  • I2C_DR_DR : stm8s.h
  • I2C_DR_RESET_VALUE : stm8s.h
  • I2C_FREQR_FREQ : stm8s.h
  • I2C_FREQR_RESET_VALUE : stm8s.h
  • I2C_ITR_ITBUFEN : stm8s.h
  • I2C_ITR_ITERREN : stm8s.h
  • I2C_ITR_ITEVTEN : stm8s.h
  • I2C_ITR_RESET_VALUE : stm8s.h
  • I2C_MAX_FAST_FREQ : stm8s_i2c.h
  • I2C_MAX_INPUT_FREQ : stm8s_i2c.h
  • I2C_MAX_STANDARD_FREQ : stm8s_i2c.h
  • I2C_OARH_ADD : stm8s.h
  • I2C_OARH_ADDCONF : stm8s.h
  • I2C_OARH_ADDMODE : stm8s.h
  • I2C_OARH_RESET_VALUE : stm8s.h
  • I2C_OARL_ADD : stm8s.h
  • I2C_OARL_ADD0 : stm8s.h
  • I2C_OARL_RESET_VALUE : stm8s.h
  • I2C_SR1_ADD10 : stm8s.h
  • I2C_SR1_ADDR : stm8s.h
  • I2C_SR1_BTF : stm8s.h
  • I2C_SR1_RESET_VALUE : stm8s.h
  • I2C_SR1_RXNE : stm8s.h
  • I2C_SR1_SB : stm8s.h
  • I2C_SR1_STOPF : stm8s.h
  • I2C_SR1_TXE : stm8s.h
  • I2C_SR2_AF : stm8s.h
  • I2C_SR2_ARLO : stm8s.h
  • I2C_SR2_BERR : stm8s.h
  • I2C_SR2_OVR : stm8s.h
  • I2C_SR2_RESET_VALUE : stm8s.h
  • I2C_SR2_WUFH : stm8s.h
  • I2C_SR3_BUSY : stm8s.h
  • I2C_SR3_GENCALL : stm8s.h
  • I2C_SR3_MSL : stm8s.h
  • I2C_SR3_RESET_VALUE : stm8s.h
  • I2C_SR3_TRA : stm8s.h
  • I2C_TRISER_RESET_VALUE : stm8s.h
  • I2C_TRISER_TRISE : stm8s.h
  • IN_RAM : stm8s.h
  • IS_ADC1_ALIGN_OK : stm8s_adc1.h
  • IS_ADC1_BUFFER_OK : stm8s_adc1.h
  • IS_ADC1_CHANNEL_OK : stm8s_adc1.h
  • IS_ADC1_CONVERSIONMODE_OK : stm8s_adc1.h
  • IS_ADC1_EXTTRIG_OK : stm8s_adc1.h
  • IS_ADC1_FLAG_OK : stm8s_adc1.h
  • IS_ADC1_IT_OK : stm8s_adc1.h
  • IS_ADC1_ITPENDINGBIT_OK : stm8s_adc1.h
  • IS_ADC1_PRESSEL_OK : stm8s_adc1.h
  • IS_ADC1_SCHMITTTRIG_OK : stm8s_adc1.h
  • IS_ADC2_ALIGN_OK : stm8s_adc2.h
  • IS_ADC2_CHANNEL_OK : stm8s_adc2.h
  • IS_ADC2_CONVERSIONMODE_OK : stm8s_adc2.h
  • IS_ADC2_EXTTRIG_OK : stm8s_adc2.h
  • IS_ADC2_PRESSEL_OK : stm8s_adc2.h
  • IS_ADC2_SCHMITTTRIG_OK : stm8s_adc2.h
  • IS_AWU_TIMEBASE_OK : stm8s_awu.h
  • IS_BEEP_FREQUENCY_OK : stm8s_beep.h
  • IS_CAN_BITSEG1_OK : stm8s_can.h
  • IS_CAN_BITSEG2_OK : stm8s_can.h
  • IS_CAN_DLC_OK : stm8s_can.h
  • IS_CAN_EXTID_OK : stm8s_can.h
  • IS_CAN_FILTER_MODE_OK : stm8s_can.h
  • IS_CAN_FILTER_NUMBER_OK : stm8s_can.h
  • IS_CAN_FILTER_SCALE_OK : stm8s_can.h
  • IS_CAN_FLAG_CLEAR_OK : stm8s_can.h
  • IS_CAN_FLAG_STATUS_OK : stm8s_can.h
  • IS_CAN_IDTYPE_OK : stm8s_can.h
  • IS_CAN_IT_CONFIG_OK : stm8s_can.h
  • IS_CAN_IT_PENDING_BIT_OK : stm8s_can.h
  • IS_CAN_IT_STATUS_OK : stm8s_can.h
  • IS_CAN_LAST_ERROR_CODE_OK : stm8s_can.h
  • IS_CAN_MASTERCTRL_OK : stm8s_can.h
  • IS_CAN_MODE_OK : stm8s_can.h
  • IS_CAN_OPERATINGMODE_OK : stm8s_can.h
  • IS_CAN_PRESCALER_OK : stm8s_can.h
  • IS_CAN_RTR_OK : stm8s_can.h
  • IS_CAN_ST7_COMPATIBILITY_OK : stm8s_can.h
  • IS_CAN_STDID_OK : stm8s_can.h
  • IS_CAN_SYNJUMPWIDTH_OK : stm8s_can.h
  • IS_CAN_TRANSMITMAILBOX_OK : stm8s_can.h
  • IS_CLK_CSSCONFIG_OK : stm8s_clk.h
  • IS_CLK_CURRENTCLOCKSTATE_OK : stm8s_clk.h
  • IS_CLK_FLAG_OK : stm8s_clk.h
  • IS_CLK_HSIPRESCALER_OK : stm8s_clk.h
  • IS_CLK_HSITRIMVALUE_OK : stm8s_clk.h
  • IS_CLK_IT_OK : stm8s_clk.h
  • IS_CLK_OUTPUT_OK : stm8s_clk.h
  • IS_CLK_PERIPHERAL_OK : stm8s_clk.h
  • IS_CLK_PRESCALER_OK : stm8s_clk.h
  • IS_CLK_SOURCE_OK : stm8s_clk.h
  • IS_CLK_SWIMDIVIDER_OK : stm8s_clk.h
  • IS_CLK_SWITCHMODE_OK : stm8s_clk.h
  • IS_EXTI_PINMASK_OK : stm8s_exti.h
  • IS_EXTI_PORT_OK : stm8s_exti.h
  • IS_EXTI_SENSITIVITY_OK : stm8s_exti.h
  • IS_EXTI_TLISENSITIVITY_OK : stm8s_exti.h
  • IS_FLASH_ADDRESS_OK : stm8s_flash.h
  • IS_FLASH_DATA_ADDRESS_OK : stm8s_flash.h
  • IS_FLASH_DATA_BLOCK_NUMBER_OK : stm8s_flash.h
  • IS_FLASH_FLAGS_OK : stm8s_flash.h
  • IS_FLASH_LOW_POWER_MODE_OK : stm8s_flash.h
  • IS_FLASH_PROG_ADDRESS_OK : stm8s_flash.h
  • IS_FLASH_PROG_BLOCK_NUMBER_OK : stm8s_flash.h
  • IS_FLASH_PROGRAM_MODE_OK : stm8s_flash.h
  • IS_FLASH_PROGRAM_TIME_OK : stm8s_flash.h
  • IS_FUNCTIONALSTATE_OK : stm8s.h
  • IS_GPIO_MODE_OK : stm8s_gpio.h
  • IS_GPIO_PIN_OK : stm8s_gpio.h
  • IS_I2C_ACK_OK : stm8s_i2c.h
  • IS_I2C_ADDMODE_OK : stm8s_i2c.h
  • IS_I2C_ADDRESS_OK : stm8s_i2c.h
  • IS_I2C_CLEAR_FLAG_OK : stm8s_i2c.h
  • IS_I2C_CLEAR_ITPENDINGBIT_OK : stm8s_i2c.h
  • IS_I2C_DIRECTION_OK : stm8s_i2c.h
  • IS_I2C_DUTYCYCLE_OK : stm8s_i2c.h
  • IS_I2C_EVENT_OK : stm8s_i2c.h
  • IS_I2C_FLAG_OK : stm8s_i2c.h
  • IS_I2C_INPUT_CLOCK_FREQ_OK : stm8s_i2c.h
  • IS_I2C_INTERRUPT_OK : stm8s_i2c.h
  • IS_I2C_ITPENDINGBIT_OK : stm8s_i2c.h
  • IS_I2C_OUTPUT_CLOCK_FREQ_OK : stm8s_i2c.h
  • IS_I2C_OWN_ADDRESS_OK : stm8s_i2c.h
  • IS_ITC_INTERRUPTS_DISABLED : stm8s_itc.h
  • IS_ITC_IRQ_OK : stm8s_itc.h
  • IS_ITC_PRIORITY_OK : stm8s_itc.h
  • IS_IWDG_PRESCALER_OK : stm8s_iwdg.h
  • IS_IWDG_WRITEACCESS_MODE_OK : stm8s_iwdg.h
  • IS_LSI_FREQUENCY_OK : stm8s_awu.h , stm8s_beep.h
  • IS_MEMORY_TYPE_OK : stm8s_flash.h
  • IS_OPTION_BYTE_ADDRESS_OK : stm8s_flash.h
  • IS_RST_FLAG_OK : stm8s_rst.h
  • IS_SPI_BAUDRATE_PRESCALER_OK : stm8s_spi.h
  • IS_SPI_CLEAR_FLAGS_OK : stm8s_spi.h
  • IS_SPI_CLEAR_IT_OK : stm8s_spi.h
  • IS_SPI_CONFIG_IT_OK : stm8s_spi.h
  • IS_SPI_CRC_OK : stm8s_spi.h
  • IS_SPI_CRC_POLYNOMIAL_OK : stm8s_spi.h
  • IS_SPI_DATA_DIRECTION_OK : stm8s_spi.h
  • IS_SPI_DIRECTION_OK : stm8s_spi.h
  • IS_SPI_FIRSTBIT_OK : stm8s_spi.h
  • IS_SPI_FLAGS_OK : stm8s_spi.h
  • IS_SPI_GET_IT_OK : stm8s_spi.h
  • IS_SPI_MODE_OK : stm8s_spi.h
  • IS_SPI_PHASE_OK : stm8s_spi.h
  • IS_SPI_POLARITY_OK : stm8s_spi.h
  • IS_SPI_SLAVEMANAGEMENT_OK : stm8s_spi.h
  • IS_STATE_VALUE_OK : stm8s.h
  • IS_TIM1_AUTOMATIC_OUTPUT_STATE_OK : stm8s_tim1.h
  • IS_TIM1_BREAK_POLARITY_OK : stm8s_tim1.h
  • IS_TIM1_BREAK_STATE_OK : stm8s_tim1.h
  • IS_TIM1_CHANNEL_OK : stm8s_tim1.h
  • IS_TIM1_CLEAR_FLAG_OK : stm8s_tim1.h
  • IS_TIM1_COMPLEMENTARY_CHANNEL_OK : stm8s_tim1.h
  • IS_TIM1_COUNTER_MODE_OK : stm8s_tim1.h
  • IS_TIM1_ENCODER_MODE_OK : stm8s_tim1.h
  • IS_TIM1_EVENT_SOURCE_OK : stm8s_tim1.h
  • IS_TIM1_EXT_POLARITY_OK : stm8s_tim1.h
  • IS_TIM1_EXT_PRESCALER_OK : stm8s_tim1.h
  • IS_TIM1_EXT_TRG_FILTER_OK : stm8s_tim1.h
  • IS_TIM1_FORCED_ACTION_OK : stm8s_tim1.h
  • IS_TIM1_GET_FLAG_OK : stm8s_tim1.h
  • IS_TIM1_GET_IT_OK : stm8s_tim1.h
  • IS_TIM1_IC_FILTER_OK : stm8s_tim1.h
  • IS_TIM1_IC_POLARITY_OK : stm8s_tim1.h
  • IS_TIM1_IC_PRESCALER_OK : stm8s_tim1.h
  • IS_TIM1_IC_SELECTION_OK : stm8s_tim1.h
  • IS_TIM1_IT_OK : stm8s_tim1.h
  • IS_TIM1_LOCK_LEVEL_OK : stm8s_tim1.h
  • IS_TIM1_OC_MODE_OK : stm8s_tim1.h
  • IS_TIM1_OC_POLARITY_OK : stm8s_tim1.h
  • IS_TIM1_OCIDLE_STATE_OK : stm8s_tim1.h
  • IS_TIM1_OCM_OK : stm8s_tim1.h
  • IS_TIM1_OCN_POLARITY_OK : stm8s_tim1.h
  • IS_TIM1_OCNIDLE_STATE_OK : stm8s_tim1.h
  • IS_TIM1_OPM_MODE_OK : stm8s_tim1.h
  • IS_TIM1_OSSI_STATE_OK : stm8s_tim1.h
  • IS_TIM1_OUTPUT_STATE_OK : stm8s_tim1.h
  • IS_TIM1_OUTPUTN_STATE_OK : stm8s_tim1.h
  • IS_TIM1_PRESCALER_RELOAD_OK : stm8s_tim1.h
  • IS_TIM1_PWMI_CHANNEL_OK : stm8s_tim1.h
  • IS_TIM1_SLAVE_MODE_OK : stm8s_tim1.h
  • IS_TIM1_TIX_TRIGGER_SELECTION_OK : stm8s_tim1.h
  • IS_TIM1_TIXCLK_SOURCE_OK : stm8s_tim1.h
  • IS_TIM1_TRGO_SOURCE_OK : stm8s_tim1.h
  • IS_TIM1_TRIGGER_SELECTION_OK : stm8s_tim1.h
  • IS_TIM1_UPDATE_SOURCE_OK : stm8s_tim1.h
  • IS_TIM2_CHANNEL_OK : stm8s_tim2.h
  • IS_TIM2_CLEAR_FLAG_OK : stm8s_tim2.h
  • IS_TIM2_EVENT_SOURCE_OK : stm8s_tim2.h
  • IS_TIM2_FORCED_ACTION_OK : stm8s_tim2.h
  • IS_TIM2_GET_FLAG_OK : stm8s_tim2.h
  • IS_TIM2_GET_IT_OK : stm8s_tim2.h
  • IS_TIM2_IC_FILTER_OK : stm8s_tim2.h
  • IS_TIM2_IC_POLARITY_OK : stm8s_tim2.h
  • IS_TIM2_IC_PRESCALER_OK : stm8s_tim2.h
  • IS_TIM2_IC_SELECTION1_OK : stm8s_tim2.h
  • IS_TIM2_IC_SELECTION_OK : stm8s_tim2.h
  • IS_TIM2_IT_OK : stm8s_tim2.h
  • IS_TIM2_OC_MODE_OK : stm8s_tim2.h
  • IS_TIM2_OC_POLARITY_OK : stm8s_tim2.h
  • IS_TIM2_OCM_OK : stm8s_tim2.h
  • IS_TIM2_OPM_MODE_OK : stm8s_tim2.h
  • IS_TIM2_OUTPUT_STATE_OK : stm8s_tim2.h
  • IS_TIM2_PRESCALER_OK : stm8s_tim2.h
  • IS_TIM2_PRESCALER_RELOAD_OK : stm8s_tim2.h
  • IS_TIM2_PWMI_CHANNEL_OK : stm8s_tim2.h
  • IS_TIM2_UPDATE_SOURCE_OK : stm8s_tim2.h
  • IS_TIM3_CHANNEL_OK : stm8s_tim3.h
  • IS_TIM3_CLEAR_FLAG_OK : stm8s_tim3.h
  • IS_TIM3_EVENT_SOURCE_OK : stm8s_tim3.h
  • IS_TIM3_FORCED_ACTION_OK : stm8s_tim3.h
  • IS_TIM3_GET_FLAG_OK : stm8s_tim3.h
  • IS_TIM3_GET_IT_OK : stm8s_tim3.h
  • IS_TIM3_IC_FILTER_OK : stm8s_tim3.h
  • IS_TIM3_IC_POLARITY_OK : stm8s_tim3.h
  • IS_TIM3_IC_PRESCALER_OK : stm8s_tim3.h
  • IS_TIM3_IC_SELECTION_OK : stm8s_tim3.h
  • IS_TIM3_IT_OK : stm8s_tim3.h
  • IS_TIM3_OC_MODE_OK : stm8s_tim3.h
  • IS_TIM3_OC_POLARITY_OK : stm8s_tim3.h
  • IS_TIM3_OCM_OK : stm8s_tim3.h
  • IS_TIM3_OPM_MODE_OK : stm8s_tim3.h
  • IS_TIM3_OUTPUT_STATE_OK : stm8s_tim3.h
  • IS_TIM3_PRESCALER_OK : stm8s_tim3.h
  • IS_TIM3_PRESCALER_RELOAD_OK : stm8s_tim3.h
  • IS_TIM3_PWMI_CHANNEL_OK : stm8s_tim3.h
  • IS_TIM3_UPDATE_SOURCE_OK : stm8s_tim3.h
  • IS_TIM4_EVENT_SOURCE_OK : stm8s_tim4.h
  • IS_TIM4_GET_FLAG_OK : stm8s_tim4.h
  • IS_TIM4_IT_OK : stm8s_tim4.h
  • IS_TIM4_OPM_MODE_OK : stm8s_tim4.h
  • IS_TIM4_PRESCALER_OK : stm8s_tim4.h
  • IS_TIM4_PRESCALER_RELOAD_OK : stm8s_tim4.h
  • IS_TIM4_UPDATE_SOURCE_OK : stm8s_tim4.h
  • IS_TIM5_CHANNEL_OK : stm8s_tim5.h
  • IS_TIM5_CLEAR_FLAG_OK : stm8s_tim5.h
  • IS_TIM5_ENCODER_MODE_OK : stm8s_tim5.h
  • IS_TIM5_EVENT_SOURCE_OK : stm8s_tim5.h
  • IS_TIM5_EXT_FILTER_OK : stm8s_tim5.h
  • IS_TIM5_EXT_POLARITY_OK : stm8s_tim5.h
  • IS_TIM5_EXT_PRESCALER_OK : stm8s_tim5.h
  • IS_TIM5_FORCED_ACTION_OK : stm8s_tim5.h
  • IS_TIM5_GET_FLAG_OK : stm8s_tim5.h
  • IS_TIM5_GET_IT_OK : stm8s_tim5.h
  • IS_TIM5_IC_FILTER_OK : stm8s_tim5.h
  • IS_TIM5_IC_POLARITY_OK : stm8s_tim5.h
  • IS_TIM5_IC_PRESCALER_OK : stm8s_tim5.h
  • IS_TIM5_IC_SELECTION1_OK : stm8s_tim5.h
  • IS_TIM5_IC_SELECTION_OK : stm8s_tim5.h
  • IS_TIM5_IT_OK : stm8s_tim5.h
  • IS_TIM5_OC_MODE_OK : stm8s_tim5.h
  • IS_TIM5_OC_POLARITY_OK : stm8s_tim5.h
  • IS_TIM5_OCM_OK : stm8s_tim5.h
  • IS_TIM5_OPM_MODE_OK : stm8s_tim5.h
  • IS_TIM5_OUTPUT_STATE_OK : stm8s_tim5.h
  • IS_TIM5_PRESCALER_OK : stm8s_tim5.h
  • IS_TIM5_PRESCALER_RELOAD_OK : stm8s_tim5.h
  • IS_TIM5_PWMI_CHANNEL_OK : stm8s_tim5.h
  • IS_TIM5_SLAVE_MODE_OK : stm8s_tim5.h
  • IS_TIM5_TIX_TRIGGER_SELECTION_OK : stm8s_tim5.h
  • IS_TIM5_TRGO_SOURCE_OK : stm8s_tim5.h
  • IS_TIM5_TRIGGER_SELECTION_OK : stm8s_tim5.h
  • IS_TIM5_UPDATE_SOURCE_OK : stm8s_tim5.h
  • IS_TIM6_CLEAR_FLAG_OK : stm8s_tim6.h
  • IS_TIM6_EVENT_SOURCE_OK : stm8s_tim6.h
  • IS_TIM6_GET_FLAG_OK : stm8s_tim6.h
  • IS_TIM6_GET_IT_OK : stm8s_tim6.h
  • IS_TIM6_IT_OK : stm8s_tim6.h
  • IS_TIM6_OPM_MODE_OK : stm8s_tim6.h
  • IS_TIM6_PRESCALER_OK : stm8s_tim6.h
  • IS_TIM6_PRESCALER_RELOAD_OK : stm8s_tim6.h
  • IS_TIM6_SLAVE_MODE_OK : stm8s_tim6.h
  • IS_TIM6_TRGO_SOURCE_OK : stm8s_tim6.h
  • IS_TIM6_TRIGGER_SELECTION_OK : stm8s_tim6.h
  • IS_TIM6_UPDATE_SOURCE_OK : stm8s_tim6.h
  • IS_UART1_ADDRESS_OK : stm8s_uart1.h
  • IS_UART1_BAUDRATE_OK : stm8s_uart1.h
  • IS_UART1_CLEAR_FLAG_OK : stm8s_uart1.h
  • IS_UART1_CLEAR_IT_OK : stm8s_uart1.h
  • IS_UART1_CONFIG_IT_OK : stm8s_uart1.h
  • IS_UART1_FLAG_OK : stm8s_uart1.h
  • IS_UART1_GET_IT_OK : stm8s_uart1.h
  • IS_UART1_IRDAMODE_OK : stm8s_uart1.h
  • IS_UART1_LINBREAKDETECTIONLENGTH_OK : stm8s_uart1.h
  • IS_UART1_MODE_OK : stm8s_uart1.h
  • IS_UART1_PARITY_OK : stm8s_uart1.h
  • IS_UART1_STOPBITS_OK : stm8s_uart1.h
  • IS_UART1_SYNCMODE_OK : stm8s_uart1.h
  • IS_UART1_WAKEUP_OK : stm8s_uart1.h
  • IS_UART1_WORDLENGTH_OK : stm8s_uart1.h
  • IS_UART2_ADDRESS_OK : stm8s_uart2.h
  • IS_UART2_AUTOSYNC_OK : stm8s_uart2.h
  • IS_UART2_BAUDRATE_OK : stm8s_uart2.h
  • IS_UART2_CLEAR_FLAG_OK : stm8s_uart2.h
  • IS_UART2_CLEAR_IT_OK : stm8s_uart2.h
  • IS_UART2_CONFIG_IT_OK : stm8s_uart2.h
  • IS_UART2_DIVUP_OK : stm8s_uart2.h
  • IS_UART2_FLAG_OK : stm8s_uart2.h
  • IS_UART2_GET_IT_OK : stm8s_uart2.h
  • IS_UART2_IRDAMODE_OK : stm8s_uart2.h
  • IS_UART2_LINBREAKDETECTIONLENGTH_OK : stm8s_uart2.h
  • IS_UART2_MODE_OK : stm8s_uart2.h
  • IS_UART2_PARITY_OK : stm8s_uart2.h
  • IS_UART2_SLAVE_OK : stm8s_uart2.h
  • IS_UART2_STOPBITS_OK : stm8s_uart2.h
  • IS_UART2_SYNCMODE_OK : stm8s_uart2.h
  • IS_UART2_WAKEUP_OK : stm8s_uart2.h
  • IS_UART2_WORDLENGTH_OK : stm8s_uart2.h
  • IS_UART3_ADDRESS_OK : stm8s_uart3.h
  • IS_UART3_AUTOSYNC_OK : stm8s_uart3.h
  • IS_UART3_BAUDRATE_OK : stm8s_uart3.h
  • IS_UART3_CLEAR_FLAG_OK : stm8s_uart3.h
  • IS_UART3_CLEAR_IT_OK : stm8s_uart3.h
  • IS_UART3_CONFIG_IT_OK : stm8s_uart3.h
  • IS_UART3_DIVUP_OK : stm8s_uart3.h
  • IS_UART3_FLAG_OK : stm8s_uart3.h
  • IS_UART3_GET_IT_OK : stm8s_uart3.h
  • IS_UART3_LINBREAKDETECTIONLENGTH_OK : stm8s_uart3.h
  • IS_UART3_MODE_OK : stm8s_uart3.h
  • IS_UART3_PARITY_OK : stm8s_uart3.h
  • IS_UART3_SLAVE_OK : stm8s_uart3.h
  • IS_UART3_STOPBITS_OK : stm8s_uart3.h
  • IS_UART3_WAKEUP_OK : stm8s_uart3.h
  • IS_UART3_WORDLENGTH_OK : stm8s_uart3.h
  • IS_UART4_ADDRESS_OK : stm8s_uart4.h
  • IS_UART4_AUTOSYNC_OK : stm8s_uart4.h
  • IS_UART4_BAUDRATE_OK : stm8s_uart4.h
  • IS_UART4_CLEAR_FLAG_OK : stm8s_uart4.h
  • IS_UART4_CLEAR_IT_OK : stm8s_uart4.h
  • IS_UART4_CONFIG_IT_OK : stm8s_uart4.h
  • IS_UART4_DIVUP_OK : stm8s_uart4.h
  • IS_UART4_FLAG_OK : stm8s_uart4.h
  • IS_UART4_GET_IT_OK : stm8s_uart4.h
  • IS_UART4_IRDAMODE_OK : stm8s_uart4.h
  • IS_UART4_LINBREAKDETECTIONLENGTH_OK : stm8s_uart4.h
  • IS_UART4_MODE_OK : stm8s_uart4.h
  • IS_UART4_PARITY_OK : stm8s_uart4.h
  • IS_UART4_SLAVE_OK : stm8s_uart4.h
  • IS_UART4_STOPBITS_OK : stm8s_uart4.h
  • IS_UART4_SYNCMODE_OK : stm8s_uart4.h
  • IS_UART4_WAKEUP_OK : stm8s_uart4.h
  • IS_UART4_WORDLENGTH_OK : stm8s_uart4.h
  • IS_WWDG_COUNTERVALUE_OK : stm8s_wwdg.h
  • IS_WWDG_WINDOWLIMITVALUE_OK : stm8s_wwdg.h
  • ITC : stm8s.h
  • ITC_BaseAddress : stm8s.h
  • ITC_SPRX_RESET_VALUE : stm8s.h
  • ITEN_Mask : stm8s_i2c.c
  • IWDG : stm8s.h
  • IWDG_BaseAddress : stm8s.h
  • IWDG_KEY_ENABLE : stm8s_iwdg.h
  • IWDG_KEY_REFRESH : stm8s_iwdg.h
  • IWDG_PR_RESET_VALUE : stm8s.h
  • IWDG_RLR_RESET_VALUE : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- p -

  • PointerAttr : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- r -

  • REGISTER_Mask : stm8s_i2c.c
  • REGISTER_SR1_Index : stm8s_i2c.c
  • REGISTER_SR2_Index : stm8s_i2c.c
  • rim : stm8s.h
  • RST : stm8s.h
  • RST_BaseAddress : stm8s.h
  • RST_SR_EMCF : stm8s.h
  • RST_SR_ILLOPF : stm8s.h
  • RST_SR_IWDGF : stm8s.h
  • RST_SR_SWIMF : stm8s.h
  • RST_SR_WWDGF : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- s -

  • S16_MAX : stm8s.h
  • S16_MIN : stm8s.h
  • S32_MAX : stm8s.h
  • S32_MIN : stm8s.h
  • S8_MAX : stm8s.h
  • S8_MIN : stm8s.h
  • SetBit : stm8s.h
  • sim : stm8s.h
  • SPI : stm8s.h
  • SPI_BaseAddress : stm8s.h
  • SPI_CR1_BR : stm8s.h
  • SPI_CR1_CPHA : stm8s.h
  • SPI_CR1_CPOL : stm8s.h
  • SPI_CR1_LSBFIRST : stm8s.h
  • SPI_CR1_MSTR : stm8s.h
  • SPI_CR1_RESET_VALUE : stm8s.h
  • SPI_CR1_SPE : stm8s.h
  • SPI_CR2_BDM : stm8s.h
  • SPI_CR2_BDOE : stm8s.h
  • SPI_CR2_CRCEN : stm8s.h
  • SPI_CR2_CRCNEXT : stm8s.h
  • SPI_CR2_RESET_VALUE : stm8s.h
  • SPI_CR2_RXONLY : stm8s.h
  • SPI_CR2_SSI : stm8s.h
  • SPI_CR2_SSM : stm8s.h
  • SPI_CRCPR_RESET_VALUE : stm8s.h
  • SPI_DR_RESET_VALUE : stm8s.h
  • SPI_ICR_ERRIE : stm8s.h
  • SPI_ICR_RESET_VALUE : stm8s.h
  • SPI_ICR_RXEI : stm8s.h
  • SPI_ICR_TXEI : stm8s.h
  • SPI_ICR_WKIE : stm8s.h
  • SPI_RXCRCR_RESET_VALUE : stm8s.h
  • SPI_SR_BSY : stm8s.h
  • SPI_SR_CRCERR : stm8s.h
  • SPI_SR_MODF : stm8s.h
  • SPI_SR_OVR : stm8s.h
  • SPI_SR_RESET_VALUE : stm8s.h
  • SPI_SR_RXNE : stm8s.h
  • SPI_SR_TXE : stm8s.h
  • SPI_SR_WKUP : stm8s.h
  • SPI_TXCRCR_RESET_VALUE : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

  • File List
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- t -

  • TIM1 : stm8s.h
  • TIM1_ARRH_ARR : stm8s.h
  • TIM1_ARRH_RESET_VALUE : stm8s.h
  • TIM1_ARRL_ARR : stm8s.h
  • TIM1_ARRL_RESET_VALUE : stm8s.h
  • TIM1_BaseAddress : stm8s.h
  • TIM1_BKR_AOE : stm8s.h
  • TIM1_BKR_BKE : stm8s.h
  • TIM1_BKR_BKP : stm8s.h
  • TIM1_BKR_LOCK : stm8s.h
  • TIM1_BKR_MOE : stm8s.h
  • TIM1_BKR_OSSI : stm8s.h
  • TIM1_BKR_OSSR : stm8s.h
  • TIM1_BKR_RESET_VALUE : stm8s.h
  • TIM1_CCER1_CC1E : stm8s.h
  • TIM1_CCER1_CC1NE : stm8s.h
  • TIM1_CCER1_CC1NP : stm8s.h
  • TIM1_CCER1_CC1P : stm8s.h
  • TIM1_CCER1_CC2E : stm8s.h
  • TIM1_CCER1_CC2NE : stm8s.h
  • TIM1_CCER1_CC2NP : stm8s.h
  • TIM1_CCER1_CC2P : stm8s.h
  • TIM1_CCER1_RESET_VALUE : stm8s.h
  • TIM1_CCER2_CC3E : stm8s.h
  • TIM1_CCER2_CC3NE : stm8s.h
  • TIM1_CCER2_CC3NP : stm8s.h
  • TIM1_CCER2_CC3P : stm8s.h
  • TIM1_CCER2_CC4E : stm8s.h
  • TIM1_CCER2_CC4P : stm8s.h
  • TIM1_CCER2_RESET_VALUE : stm8s.h
  • TIM1_CCMR1_RESET_VALUE : stm8s.h
  • TIM1_CCMR2_RESET_VALUE : stm8s.h
  • TIM1_CCMR3_RESET_VALUE : stm8s.h
  • TIM1_CCMR4_RESET_VALUE : stm8s.h
  • TIM1_CCMR_CCxS : stm8s.h
  • TIM1_CCMR_ICxF : stm8s.h
  • TIM1_CCMR_ICxPSC : stm8s.h
  • TIM1_CCMR_OCM : stm8s.h
  • TIM1_CCMR_OCxFE : stm8s.h
  • TIM1_CCMR_OCxPE : stm8s.h
  • TIM1_CCR1H_CCR1 : stm8s.h
  • TIM1_CCR1H_RESET_VALUE : stm8s.h
  • TIM1_CCR1L_CCR1 : stm8s.h
  • TIM1_CCR1L_RESET_VALUE : stm8s.h
  • TIM1_CCR2H_CCR2 : stm8s.h
  • TIM1_CCR2H_RESET_VALUE : stm8s.h
  • TIM1_CCR2L_CCR2 : stm8s.h
  • TIM1_CCR2L_RESET_VALUE : stm8s.h
  • TIM1_CCR3H_CCR3 : stm8s.h
  • TIM1_CCR3H_RESET_VALUE : stm8s.h
  • TIM1_CCR3L_CCR3 : stm8s.h
  • TIM1_CCR3L_RESET_VALUE : stm8s.h
  • TIM1_CCR4H_CCR4 : stm8s.h
  • TIM1_CCR4H_RESET_VALUE : stm8s.h
  • TIM1_CCR4L_CCR4 : stm8s.h
  • TIM1_CCR4L_RESET_VALUE : stm8s.h
  • TIM1_CNTRH_CNT : stm8s.h
  • TIM1_CNTRH_RESET_VALUE : stm8s.h
  • TIM1_CNTRL_CNT : stm8s.h
  • TIM1_CNTRL_RESET_VALUE : stm8s.h
  • TIM1_CR1_ARPE : stm8s.h
  • TIM1_CR1_CEN : stm8s.h
  • TIM1_CR1_CMS : stm8s.h
  • TIM1_CR1_DIR : stm8s.h
  • TIM1_CR1_OPM : stm8s.h
  • TIM1_CR1_RESET_VALUE : stm8s.h
  • TIM1_CR1_UDIS : stm8s.h
  • TIM1_CR1_URS : stm8s.h
  • TIM1_CR2_CCPC : stm8s.h
  • TIM1_CR2_COMS : stm8s.h
  • TIM1_CR2_MMS : stm8s.h
  • TIM1_CR2_RESET_VALUE : stm8s.h
  • TIM1_CR2_TI1S : stm8s.h
  • TIM1_DTR_DTG : stm8s.h
  • TIM1_DTR_RESET_VALUE : stm8s.h
  • TIM1_EGR_BG : stm8s.h
  • TIM1_EGR_CC1G : stm8s.h
  • TIM1_EGR_CC2G : stm8s.h
  • TIM1_EGR_CC3G : stm8s.h
  • TIM1_EGR_CC4G : stm8s.h
  • TIM1_EGR_COMG : stm8s.h
  • TIM1_EGR_RESET_VALUE : stm8s.h
  • TIM1_EGR_TG : stm8s.h
  • TIM1_EGR_UG : stm8s.h
  • TIM1_ETR_ECE : stm8s.h
  • TIM1_ETR_ETF : stm8s.h
  • TIM1_ETR_ETP : stm8s.h
  • TIM1_ETR_ETPS : stm8s.h
  • TIM1_ETR_RESET_VALUE : stm8s.h
  • TIM1_IER_BIE : stm8s.h
  • TIM1_IER_CC1IE : stm8s.h
  • TIM1_IER_CC2IE : stm8s.h
  • TIM1_IER_CC3IE : stm8s.h
  • TIM1_IER_CC4IE : stm8s.h
  • TIM1_IER_COMIE : stm8s.h
  • TIM1_IER_RESET_VALUE : stm8s.h
  • TIM1_IER_TIE : stm8s.h
  • TIM1_IER_UIE : stm8s.h
  • TIM1_OISR_OIS1 : stm8s.h
  • TIM1_OISR_OIS1N : stm8s.h
  • TIM1_OISR_OIS2 : stm8s.h
  • TIM1_OISR_OIS2N : stm8s.h
  • TIM1_OISR_OIS3 : stm8s.h
  • TIM1_OISR_OIS3N : stm8s.h
  • TIM1_OISR_OIS4 : stm8s.h
  • TIM1_OISR_RESET_VALUE : stm8s.h
  • TIM1_PSCH_PSC : stm8s.h
  • TIM1_PSCL_PSC : stm8s.h
  • TIM1_PSCRH_RESET_VALUE : stm8s.h
  • TIM1_PSCRL_RESET_VALUE : stm8s.h
  • TIM1_RCR_REP : stm8s.h
  • TIM1_RCR_RESET_VALUE : stm8s.h
  • TIM1_SMCR_MSM : stm8s.h
  • TIM1_SMCR_RESET_VALUE : stm8s.h
  • TIM1_SMCR_SMS : stm8s.h
  • TIM1_SMCR_TS : stm8s.h
  • TIM1_SR1_BIF : stm8s.h
  • TIM1_SR1_CC1IF : stm8s.h
  • TIM1_SR1_CC2IF : stm8s.h
  • TIM1_SR1_CC3IF : stm8s.h
  • TIM1_SR1_CC4IF : stm8s.h
  • TIM1_SR1_COMIF : stm8s.h
  • TIM1_SR1_RESET_VALUE : stm8s.h
  • TIM1_SR1_TIF : stm8s.h
  • TIM1_SR1_UIF : stm8s.h
  • TIM1_SR2_CC1OF : stm8s.h
  • TIM1_SR2_CC2OF : stm8s.h
  • TIM1_SR2_CC3OF : stm8s.h
  • TIM1_SR2_CC4OF : stm8s.h
  • TIM1_SR2_RESET_VALUE : stm8s.h
  • TIM2_ARRH_ARR : stm8s.h
  • TIM2_ARRH_RESET_VALUE : stm8s.h
  • TIM2_ARRL_ARR : stm8s.h
  • TIM2_ARRL_RESET_VALUE : stm8s.h
  • TIM2_BaseAddress : stm8s.h
  • TIM2_CCER1_CC1E : stm8s.h
  • TIM2_CCER1_CC1P : stm8s.h
  • TIM2_CCER1_CC2E : stm8s.h
  • TIM2_CCER1_CC2P : stm8s.h
  • TIM2_CCER1_RESET_VALUE : stm8s.h
  • TIM2_CCER2_CC3E : stm8s.h
  • TIM2_CCER2_CC3P : stm8s.h
  • TIM2_CCER2_RESET_VALUE : stm8s.h
  • TIM2_CCMR1_RESET_VALUE : stm8s.h
  • TIM2_CCMR2_RESET_VALUE : stm8s.h
  • TIM2_CCMR3_RESET_VALUE : stm8s.h
  • TIM2_CCMR_CCxS : stm8s.h
  • TIM2_CCMR_ICxF : stm8s.h
  • TIM2_CCMR_ICxPSC : stm8s.h
  • TIM2_CCMR_OCM : stm8s.h
  • TIM2_CCMR_OCxPE : stm8s.h
  • TIM2_CCR1H_CCR1 : stm8s.h
  • TIM2_CCR1H_RESET_VALUE : stm8s.h
  • TIM2_CCR1L_CCR1 : stm8s.h
  • TIM2_CCR1L_RESET_VALUE : stm8s.h
  • TIM2_CCR2H_CCR2 : stm8s.h
  • TIM2_CCR2H_RESET_VALUE : stm8s.h
  • TIM2_CCR2L_CCR2 : stm8s.h
  • TIM2_CCR2L_RESET_VALUE : stm8s.h
  • TIM2_CCR3H_CCR3 : stm8s.h
  • TIM2_CCR3H_RESET_VALUE : stm8s.h
  • TIM2_CCR3L_CCR3 : stm8s.h
  • TIM2_CCR3L_RESET_VALUE : stm8s.h
  • TIM2_CNTRH_CNT : stm8s.h
  • TIM2_CNTRH_RESET_VALUE : stm8s.h
  • TIM2_CNTRL_CNT : stm8s.h
  • TIM2_CNTRL_RESET_VALUE : stm8s.h
  • TIM2_CR1_ARPE : stm8s.h
  • TIM2_CR1_CEN : stm8s.h
  • TIM2_CR1_OPM : stm8s.h
  • TIM2_CR1_RESET_VALUE : stm8s.h
  • TIM2_CR1_UDIS : stm8s.h
  • TIM2_CR1_URS : stm8s.h
  • TIM2_EGR_CC1G : stm8s.h
  • TIM2_EGR_CC2G : stm8s.h
  • TIM2_EGR_CC3G : stm8s.h
  • TIM2_EGR_RESET_VALUE : stm8s.h
  • TIM2_EGR_UG : stm8s.h
  • TIM2_IER_CC1IE : stm8s.h
  • TIM2_IER_CC2IE : stm8s.h
  • TIM2_IER_CC3IE : stm8s.h
  • TIM2_IER_RESET_VALUE : stm8s.h
  • TIM2_IER_UIE : stm8s.h
  • TIM2_PSCR_PSC : stm8s.h
  • TIM2_PSCR_RESET_VALUE : stm8s.h
  • TIM2_SR1_CC1IF : stm8s.h
  • TIM2_SR1_CC2IF : stm8s.h
  • TIM2_SR1_CC3IF : stm8s.h
  • TIM2_SR1_RESET_VALUE : stm8s.h
  • TIM2_SR1_UIF : stm8s.h
  • TIM2_SR2_CC1OF : stm8s.h
  • TIM2_SR2_CC2OF : stm8s.h
  • TIM2_SR2_CC3OF : stm8s.h
  • TIM2_SR2_RESET_VALUE : stm8s.h
  • TIM3_ARRH_ARR : stm8s.h
  • TIM3_ARRH_RESET_VALUE : stm8s.h
  • TIM3_ARRL_ARR : stm8s.h
  • TIM3_ARRL_RESET_VALUE : stm8s.h
  • TIM3_BaseAddress : stm8s.h
  • TIM3_CCER1_CC1E : stm8s.h
  • TIM3_CCER1_CC1P : stm8s.h
  • TIM3_CCER1_CC2E : stm8s.h
  • TIM3_CCER1_CC2P : stm8s.h
  • TIM3_CCER1_RESET_VALUE : stm8s.h
  • TIM3_CCMR1_RESET_VALUE : stm8s.h
  • TIM3_CCMR2_RESET_VALUE : stm8s.h
  • TIM3_CCMR_CCxS : stm8s.h
  • TIM3_CCMR_ICxF : stm8s.h
  • TIM3_CCMR_ICxPSC : stm8s.h
  • TIM3_CCMR_OCM : stm8s.h
  • TIM3_CCMR_OCxPE : stm8s.h
  • TIM3_CCR1H_CCR1 : stm8s.h
  • TIM3_CCR1H_RESET_VALUE : stm8s.h
  • TIM3_CCR1L_CCR1 : stm8s.h
  • TIM3_CCR1L_RESET_VALUE : stm8s.h
  • TIM3_CCR2H_CCR2 : stm8s.h
  • TIM3_CCR2H_RESET_VALUE : stm8s.h
  • TIM3_CCR2L_CCR2 : stm8s.h
  • TIM3_CCR2L_RESET_VALUE : stm8s.h
  • TIM3_CNTRH_CNT : stm8s.h
  • TIM3_CNTRH_RESET_VALUE : stm8s.h
  • TIM3_CNTRL_CNT : stm8s.h
  • TIM3_CNTRL_RESET_VALUE : stm8s.h
  • TIM3_CR1_ARPE : stm8s.h
  • TIM3_CR1_CEN : stm8s.h
  • TIM3_CR1_OPM : stm8s.h
  • TIM3_CR1_RESET_VALUE : stm8s.h
  • TIM3_CR1_UDIS : stm8s.h
  • TIM3_CR1_URS : stm8s.h
  • TIM3_EGR_CC1G : stm8s.h
  • TIM3_EGR_CC2G : stm8s.h
  • TIM3_EGR_RESET_VALUE : stm8s.h
  • TIM3_EGR_UG : stm8s.h
  • TIM3_IER_CC1IE : stm8s.h
  • TIM3_IER_CC2IE : stm8s.h
  • TIM3_IER_RESET_VALUE : stm8s.h
  • TIM3_IER_UIE : stm8s.h
  • TIM3_PSCR_PSC : stm8s.h
  • TIM3_PSCR_RESET_VALUE : stm8s.h
  • TIM3_SR1_CC1IF : stm8s.h
  • TIM3_SR1_CC2IF : stm8s.h
  • TIM3_SR1_RESET_VALUE : stm8s.h
  • TIM3_SR1_UIF : stm8s.h
  • TIM3_SR2_CC1OF : stm8s.h
  • TIM3_SR2_CC2OF : stm8s.h
  • TIM3_SR2_RESET_VALUE : stm8s.h
  • TIM4_ARR_ARR : stm8s.h
  • TIM4_ARR_RESET_VALUE : stm8s.h
  • TIM4_BaseAddress : stm8s.h
  • TIM4_CNTR_CNT : stm8s.h
  • TIM4_CNTR_RESET_VALUE : stm8s.h
  • TIM4_CR1_ARPE : stm8s.h
  • TIM4_CR1_CEN : stm8s.h
  • TIM4_CR1_OPM : stm8s.h
  • TIM4_CR1_RESET_VALUE : stm8s.h
  • TIM4_CR1_UDIS : stm8s.h
  • TIM4_CR1_URS : stm8s.h
  • TIM4_EGR_RESET_VALUE : stm8s.h
  • TIM4_EGR_UG : stm8s.h
  • TIM4_IER_RESET_VALUE : stm8s.h
  • TIM4_IER_UIE : stm8s.h
  • TIM4_PSCR_PSC : stm8s.h
  • TIM4_PSCR_RESET_VALUE : stm8s.h
  • TIM4_SR1_RESET_VALUE : stm8s.h
  • TIM4_SR1_UIF : stm8s.h
  • TIM5_ARRH_ARR : stm8s.h
  • TIM5_ARRH_RESET_VALUE : stm8s.h
  • TIM5_ARRL_ARR : stm8s.h
  • TIM5_ARRL_RESET_VALUE : stm8s.h
  • TIM5_BaseAddress : stm8s.h
  • TIM5_CCER1_CC1E : stm8s.h
  • TIM5_CCER1_CC1P : stm8s.h
  • TIM5_CCER1_CC2E : stm8s.h
  • TIM5_CCER1_CC2P : stm8s.h
  • TIM5_CCER1_RESET_VALUE : stm8s.h
  • TIM5_CCER2_CC3E : stm8s.h
  • TIM5_CCER2_CC3P : stm8s.h
  • TIM5_CCER2_RESET_VALUE : stm8s.h
  • TIM5_CCMR1_RESET_VALUE : stm8s.h
  • TIM5_CCMR2_RESET_VALUE : stm8s.h
  • TIM5_CCMR3_RESET_VALUE : stm8s.h
  • TIM5_CCMR_CCxS : stm8s.h
  • TIM5_CCMR_ICxF : stm8s.h
  • TIM5_CCMR_ICxPSC : stm8s.h
  • TIM5_CCMR_OCM : stm8s.h
  • TIM5_CCMR_OCxPE : stm8s.h
  • TIM5_CCMR_TIxDirect_Set : stm8s.h
  • TIM5_CCR1H_CCR1 : stm8s.h
  • TIM5_CCR1H_RESET_VALUE : stm8s.h
  • TIM5_CCR1L_CCR1 : stm8s.h
  • TIM5_CCR1L_RESET_VALUE : stm8s.h
  • TIM5_CCR2H_CCR2 : stm8s.h
  • TIM5_CCR2H_RESET_VALUE : stm8s.h
  • TIM5_CCR2L_CCR2 : stm8s.h
  • TIM5_CCR2L_RESET_VALUE : stm8s.h
  • TIM5_CCR3H_CCR3 : stm8s.h
  • TIM5_CCR3H_RESET_VALUE : stm8s.h
  • TIM5_CCR3L_CCR3 : stm8s.h
  • TIM5_CCR3L_RESET_VALUE : stm8s.h
  • TIM5_CNTRH_CNT : stm8s.h
  • TIM5_CNTRH_RESET_VALUE : stm8s.h
  • TIM5_CNTRL_CNT : stm8s.h
  • TIM5_CNTRL_RESET_VALUE : stm8s.h
  • TIM5_CR1_ARPE : stm8s.h
  • TIM5_CR1_CEN : stm8s.h
  • TIM5_CR1_OPM : stm8s.h
  • TIM5_CR1_RESET_VALUE : stm8s.h
  • TIM5_CR1_UDIS : stm8s.h
  • TIM5_CR1_URS : stm8s.h
  • TIM5_CR2_MMS : stm8s.h
  • TIM5_CR2_RESET_VALUE : stm8s.h
  • TIM5_CR2_TI1S : stm8s.h
  • TIM5_EGR_CC1G : stm8s.h
  • TIM5_EGR_CC2G : stm8s.h
  • TIM5_EGR_CC3G : stm8s.h
  • TIM5_EGR_RESET_VALUE : stm8s.h
  • TIM5_EGR_TG : stm8s.h
  • TIM5_EGR_UG : stm8s.h
  • TIM5_IER_CC1IE : stm8s.h
  • TIM5_IER_CC2IE : stm8s.h
  • TIM5_IER_CC3IE : stm8s.h
  • TIM5_IER_RESET_VALUE : stm8s.h
  • TIM5_IER_TIE : stm8s.h
  • TIM5_IER_UIE : stm8s.h
  • TIM5_PSCR_PSC : stm8s.h
  • TIM5_PSCR_RESET_VALUE : stm8s.h
  • TIM5_SMCR_MSM : stm8s.h
  • TIM5_SMCR_RESET_VALUE : stm8s.h
  • TIM5_SMCR_SMS : stm8s.h
  • TIM5_SMCR_TS : stm8s.h
  • TIM5_SR1_CC1IF : stm8s.h
  • TIM5_SR1_CC2IF : stm8s.h
  • TIM5_SR1_CC3IF : stm8s.h
  • TIM5_SR1_RESET_VALUE : stm8s.h
  • TIM5_SR1_TIF : stm8s.h
  • TIM5_SR1_UIF : stm8s.h
  • TIM5_SR2_CC1OF : stm8s.h
  • TIM5_SR2_CC2OF : stm8s.h
  • TIM5_SR2_CC3OF : stm8s.h
  • TIM5_SR2_RESET_VALUE : stm8s.h
  • TIM6_ARR_ARR : stm8s.h
  • TIM6_ARR_RESET_VALUE : stm8s.h
  • TIM6_BaseAddress : stm8s.h
  • TIM6_CNTR_CNT : stm8s.h
  • TIM6_CNTR_RESET_VALUE : stm8s.h
  • TIM6_CR1_ARPE : stm8s.h
  • TIM6_CR1_CEN : stm8s.h
  • TIM6_CR1_OPM : stm8s.h
  • TIM6_CR1_RESET_VALUE : stm8s.h
  • TIM6_CR1_UDIS : stm8s.h
  • TIM6_CR1_URS : stm8s.h
  • TIM6_CR2_MMS : stm8s.h
  • TIM6_CR2_RESET_VALUE : stm8s.h
  • TIM6_EGR_RESET_VALUE : stm8s.h
  • TIM6_EGR_TG : stm8s.h
  • TIM6_EGR_UG : stm8s.h
  • TIM6_IER_RESET_VALUE : stm8s.h
  • TIM6_IER_TIE : stm8s.h
  • TIM6_IER_UIE : stm8s.h
  • TIM6_PSCR_PSC : stm8s.h
  • TIM6_PSCR_RESET_VALUE : stm8s.h
  • TIM6_SMCR_MSM : stm8s.h
  • TIM6_SMCR_RESET_VALUE : stm8s.h
  • TIM6_SMCR_SMS : stm8s.h
  • TIM6_SMCR_TS : stm8s.h
  • TIM6_SR1_RESET_VALUE : stm8s.h
  • TIM6_SR1_TIF : stm8s.h
  • TIM6_SR1_UIF : stm8s.h
  • TINY : stm8s.h
  • trap : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
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  • u
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- u -

  • U16_MAX : stm8s.h
  • U32_MAX : stm8s.h
  • U8_MAX : stm8s.h
  • UART1_ADDRESS_MAX : stm8s_uart1.h
  • UART1_BaseAddress : stm8s.h
  • UART1_BRR1_DIVM : stm8s.h
  • UART1_BRR1_RESET_VALUE : stm8s.h
  • UART1_BRR2_DIVF : stm8s.h
  • UART1_BRR2_DIVM : stm8s.h
  • UART1_BRR2_RESET_VALUE : stm8s.h
  • UART1_CR1_M : stm8s.h
  • UART1_CR1_PCEN : stm8s.h
  • UART1_CR1_PIEN : stm8s.h
  • UART1_CR1_PS : stm8s.h
  • UART1_CR1_R8 : stm8s.h
  • UART1_CR1_RESET_VALUE : stm8s.h
  • UART1_CR1_T8 : stm8s.h
  • UART1_CR1_UARTD : stm8s.h
  • UART1_CR1_WAKE : stm8s.h
  • UART1_CR2_ILIEN : stm8s.h
  • UART1_CR2_REN : stm8s.h
  • UART1_CR2_RESET_VALUE : stm8s.h
  • UART1_CR2_RIEN : stm8s.h
  • UART1_CR2_RWU : stm8s.h
  • UART1_CR2_SBK : stm8s.h
  • UART1_CR2_TCIEN : stm8s.h
  • UART1_CR2_TEN : stm8s.h
  • UART1_CR2_TIEN : stm8s.h
  • UART1_CR3_CKEN : stm8s.h
  • UART1_CR3_CPHA : stm8s.h
  • UART1_CR3_CPOL : stm8s.h
  • UART1_CR3_LBCL : stm8s.h
  • UART1_CR3_LINEN : stm8s.h
  • UART1_CR3_RESET_VALUE : stm8s.h
  • UART1_CR3_STOP : stm8s.h
  • UART1_CR4_ADD : stm8s.h
  • UART1_CR4_LBDF : stm8s.h
  • UART1_CR4_LBDIEN : stm8s.h
  • UART1_CR4_LBDL : stm8s.h
  • UART1_CR4_RESET_VALUE : stm8s.h
  • UART1_CR5_HDSEL : stm8s.h
  • UART1_CR5_IREN : stm8s.h
  • UART1_CR5_IRLP : stm8s.h
  • UART1_CR5_NACK : stm8s.h
  • UART1_CR5_RESET_VALUE : stm8s.h
  • UART1_CR5_SCEN : stm8s.h
  • UART1_GTR_RESET_VALUE : stm8s.h
  • UART1_PSCR_RESET_VALUE : stm8s.h
  • UART1_SR_FE : stm8s.h
  • UART1_SR_IDLE : stm8s.h
  • UART1_SR_NF : stm8s.h
  • UART1_SR_OR : stm8s.h
  • UART1_SR_PE : stm8s.h
  • UART1_SR_RESET_VALUE : stm8s.h
  • UART1_SR_RXNE : stm8s.h
  • UART1_SR_TC : stm8s.h
  • UART1_SR_TXE : stm8s.h
  • UART2_ADDRESS_MAX : stm8s_uart2.h
  • UART2_BaseAddress : stm8s.h
  • UART2_BRR1_DIVM : stm8s.h
  • UART2_BRR1_RESET_VALUE : stm8s.h
  • UART2_BRR2_DIVF : stm8s.h
  • UART2_BRR2_DIVM : stm8s.h
  • UART2_BRR2_RESET_VALUE : stm8s.h
  • UART2_CR1_M : stm8s.h
  • UART2_CR1_PCEN : stm8s.h
  • UART2_CR1_PIEN : stm8s.h
  • UART2_CR1_PS : stm8s.h
  • UART2_CR1_R8 : stm8s.h
  • UART2_CR1_RESET_VALUE : stm8s.h
  • UART2_CR1_T8 : stm8s.h
  • UART2_CR1_UARTD : stm8s.h
  • UART2_CR1_WAKE : stm8s.h
  • UART2_CR2_ILIEN : stm8s.h
  • UART2_CR2_REN : stm8s.h
  • UART2_CR2_RESET_VALUE : stm8s.h
  • UART2_CR2_RIEN : stm8s.h
  • UART2_CR2_RWU : stm8s.h
  • UART2_CR2_SBK : stm8s.h
  • UART2_CR2_TCIEN : stm8s.h
  • UART2_CR2_TEN : stm8s.h
  • UART2_CR2_TIEN : stm8s.h
  • UART2_CR3_CKEN : stm8s.h
  • UART2_CR3_CPHA : stm8s.h
  • UART2_CR3_CPOL : stm8s.h
  • UART2_CR3_LBCL : stm8s.h
  • UART2_CR3_LINEN : stm8s.h
  • UART2_CR3_RESET_VALUE : stm8s.h
  • UART2_CR3_STOP : stm8s.h
  • UART2_CR4_ADD : stm8s.h
  • UART2_CR4_LBDF : stm8s.h
  • UART2_CR4_LBDIEN : stm8s.h
  • UART2_CR4_LBDL : stm8s.h
  • UART2_CR4_RESET_VALUE : stm8s.h
  • UART2_CR5_IREN : stm8s.h
  • UART2_CR5_IRLP : stm8s.h
  • UART2_CR5_NACK : stm8s.h
  • UART2_CR5_RESET_VALUE : stm8s.h
  • UART2_CR5_SCEN : stm8s.h
  • UART2_CR6_LASE : stm8s.h
  • UART2_CR6_LDUM : stm8s.h
  • UART2_CR6_LHDF : stm8s.h
  • UART2_CR6_LHDIEN : stm8s.h
  • UART2_CR6_LSF : stm8s.h
  • UART2_CR6_LSLV : stm8s.h
  • UART2_CR6_RESET_VALUE : stm8s.h
  • UART2_GTR_RESET_VALUE : stm8s.h
  • UART2_PSCR_RESET_VALUE : stm8s.h
  • UART2_SR_FE : stm8s.h
  • UART2_SR_IDLE : stm8s.h
  • UART2_SR_NF : stm8s.h
  • UART2_SR_OR : stm8s.h
  • UART2_SR_PE : stm8s.h
  • UART2_SR_RESET_VALUE : stm8s.h
  • UART2_SR_RXNE : stm8s.h
  • UART2_SR_TC : stm8s.h
  • UART2_SR_TXE : stm8s.h
  • UART3_ADDRESS_MAX : stm8s_uart3.h
  • UART3_BaseAddress : stm8s.h
  • UART3_BRR1_DIVM : stm8s.h
  • UART3_BRR1_RESET_VALUE : stm8s.h
  • UART3_BRR2_DIVF : stm8s.h
  • UART3_BRR2_DIVM : stm8s.h
  • UART3_BRR2_RESET_VALUE : stm8s.h
  • UART3_CR1_M : stm8s.h
  • UART3_CR1_PCEN : stm8s.h
  • UART3_CR1_PIEN : stm8s.h
  • UART3_CR1_PS : stm8s.h
  • UART3_CR1_R8 : stm8s.h
  • UART3_CR1_RESET_VALUE : stm8s.h
  • UART3_CR1_T8 : stm8s.h
  • UART3_CR1_UARTD : stm8s.h
  • UART3_CR1_WAKE : stm8s.h
  • UART3_CR2_ILIEN : stm8s.h
  • UART3_CR2_REN : stm8s.h
  • UART3_CR2_RESET_VALUE : stm8s.h
  • UART3_CR2_RIEN : stm8s.h
  • UART3_CR2_RWU : stm8s.h
  • UART3_CR2_SBK : stm8s.h
  • UART3_CR2_TCIEN : stm8s.h
  • UART3_CR2_TEN : stm8s.h
  • UART3_CR2_TIEN : stm8s.h
  • UART3_CR3_LINEN : stm8s.h
  • UART3_CR3_RESET_VALUE : stm8s.h
  • UART3_CR3_STOP : stm8s.h
  • UART3_CR4_ADD : stm8s.h
  • UART3_CR4_LBDF : stm8s.h
  • UART3_CR4_LBDIEN : stm8s.h
  • UART3_CR4_LBDL : stm8s.h
  • UART3_CR4_RESET_VALUE : stm8s.h
  • UART3_CR6_LASE : stm8s.h
  • UART3_CR6_LDUM : stm8s.h
  • UART3_CR6_LHDF : stm8s.h
  • UART3_CR6_LHDIEN : stm8s.h
  • UART3_CR6_LSF : stm8s.h
  • UART3_CR6_LSLV : stm8s.h
  • UART3_CR6_RESET_VALUE : stm8s.h
  • UART3_SR_FE : stm8s.h
  • UART3_SR_IDLE : stm8s.h
  • UART3_SR_NF : stm8s.h
  • UART3_SR_OR : stm8s.h
  • UART3_SR_PE : stm8s.h
  • UART3_SR_RESET_VALUE : stm8s.h
  • UART3_SR_RXNE : stm8s.h
  • UART3_SR_TC : stm8s.h
  • UART3_SR_TXE : stm8s.h
  • UART4_ADDRESS_MAX : stm8s_uart4.h
  • UART4_BaseAddress : stm8s.h
  • USE_STDPERIPH_DRIVER : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- v -

  • ValBit : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- w -

  • wfi : stm8s.h
  • WWDG : stm8s.h
  • WWDG_BaseAddress : stm8s.h
  • WWDG_CR_RESET_VALUE : stm8s.h
  • WWDG_CR_T : stm8s.h
  • WWDG_CR_T6 : stm8s.h
  • WWDG_CR_WDGA : stm8s.h
  • WWDG_WR_MSB : stm8s.h
  • WWDG_WR_RESET_VALUE : stm8s.h
  • WWDG_WR_W : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- a -

  • ADC1_Align_TypeDef : stm8s_adc1.h
  • ADC1_Channel_TypeDef : stm8s_adc1.h
  • ADC1_ConvMode_TypeDef : stm8s_adc1.h
  • ADC1_ExtTrig_TypeDef : stm8s_adc1.h
  • ADC1_Flag_TypeDef : stm8s_adc1.h
  • ADC1_IT_TypeDef : stm8s_adc1.h
  • ADC1_PresSel_TypeDef : stm8s_adc1.h
  • ADC1_SchmittTrigg_TypeDef : stm8s_adc1.h
  • ADC2_Align_TypeDef : stm8s_adc2.h
  • ADC2_Channel_TypeDef : stm8s_adc2.h
  • ADC2_ConvMode_TypeDef : stm8s_adc2.h
  • ADC2_ExtTrig_TypeDef : stm8s_adc2.h
  • ADC2_PresSel_TypeDef : stm8s_adc2.h
  • ADC2_SchmittTrigg_TypeDef : stm8s_adc2.h
  • AWU_Timebase_TypeDef : stm8s_awu.h


STM8S/A Standard Peripherals Drivers: Globals

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- b -

  • BEEP_Frequency_TypeDef : stm8s_beep.h
  • bool : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- c -

  • CAN_BitSeg1_TypeDef : stm8s_can.h
  • CAN_BitSeg2_TypeDef : stm8s_can.h
  • CAN_ErrorCode_TypeDef : stm8s_can.h
  • CAN_FilterMode_TypeDef : stm8s_can.h
  • CAN_FilterNumber_TypeDef : stm8s_can.h
  • CAN_FilterScale_TypeDef : stm8s_can.h
  • CAN_FLAG_TypeDef : stm8s_can.h
  • CAN_Id_TypeDef : stm8s_can.h
  • CAN_InitStatus_TypeDef : stm8s_can.h
  • CAN_IT_TypeDef : stm8s_can.h
  • CAN_MasterCtrl_TypeDef : stm8s_can.h
  • CAN_Mode_TypeDef : stm8s_can.h
  • CAN_ModeStatus_TypeDef : stm8s_can.h
  • CAN_NbrPendingMessage_TypeDef : stm8s_can.h
  • CAN_OperatingMode_TypeDef : stm8s_can.h
  • CAN_Page_TypeDef : stm8s_can.h
  • CAN_RTR_TypeDef : stm8s_can.h
  • CAN_Sleep_TypeDef : stm8s_can.h
  • CAN_ST7Compatibility_TypeDef : stm8s_can.h
  • CAN_SynJumpWidth_TypeDef : stm8s_can.h
  • CAN_TransmitMailBox_TypeDef : stm8s_can.h
  • CAN_TxStatus_TypeDef : stm8s_can.h
  • CAN_WakeUp_TypeDef : stm8s_can.h
  • CLK_CSSConfig_TypeDef : stm8s_clk.h
  • CLK_CurrentClockState_TypeDef : stm8s_clk.h
  • CLK_Flag_TypeDef : stm8s_clk.h
  • CLK_HSITrimValue_TypeDef : stm8s_clk.h
  • CLK_IT_TypeDef : stm8s_clk.h
  • CLK_Output_TypeDef : stm8s_clk.h
  • CLK_Peripheral_TypeDef : stm8s_clk.h
  • CLK_Prescaler_TypeDef : stm8s_clk.h
  • CLK_Source_TypeDef : stm8s_clk.h
  • CLK_SWIMDivider_TypeDef : stm8s_clk.h
  • CLK_SwitchMode_TypeDef : stm8s_clk.h


STM8S/A Standard Peripherals Drivers: Globals

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- e -

  • ErrorStatus : stm8s.h
  • EXTI_Port_TypeDef : stm8s_exti.h
  • EXTI_Sensitivity_TypeDef : stm8s_exti.h
  • EXTI_TLISensitivity_TypeDef : stm8s_exti.h


STM8S/A Standard Peripherals Drivers: Globals

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- f -

  • FlagStatus : stm8s.h
  • FLASH_Flag_TypeDef : stm8s_flash.h
  • FLASH_LPMode_TypeDef : stm8s_flash.h
  • FLASH_MemType_TypeDef : stm8s_flash.h
  • FLASH_ProgramMode_TypeDef : stm8s_flash.h
  • FLASH_ProgramTime_TypeDef : stm8s_flash.h
  • FLASH_Status_TypeDef : stm8s_flash.h
  • FunctionalState : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- g -

  • GPIO_Mode_TypeDef : stm8s_gpio.h
  • GPIO_Pin_TypeDef : stm8s_gpio.h


STM8S/A Standard Peripherals Drivers: Globals

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- i -

  • I2C_Ack_TypeDef : stm8s_i2c.h
  • I2C_AddMode_TypeDef : stm8s_i2c.h
  • I2C_Direction_TypeDef : stm8s_i2c.h
  • I2C_DutyCycle_TypeDef : stm8s_i2c.h
  • I2C_Event_TypeDef : stm8s_i2c.h
  • I2C_Flag_TypeDef : stm8s_i2c.h
  • I2C_IT_TypeDef : stm8s_i2c.h
  • I2C_ITPendingBit_TypeDef : stm8s_i2c.h
  • ITC_Irq_TypeDef : stm8s_itc.h
  • ITC_PriorityLevel_TypeDef : stm8s_itc.h
  • IWDG_Prescaler_TypeDef : stm8s_iwdg.h
  • IWDG_WriteAccess_TypeDef : stm8s_iwdg.h


STM8S/A Standard Peripherals Drivers: Globals

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- r -

  • RST_Flag_TypeDef : stm8s_rst.h


STM8S/A Standard Peripherals Drivers: Globals

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- s -

  • SPI_BaudRatePrescaler_TypeDef : stm8s_spi.h
  • SPI_ClockPhase_TypeDef : stm8s_spi.h
  • SPI_ClockPolarity_TypeDef : stm8s_spi.h
  • SPI_CRC_TypeDef : stm8s_spi.h
  • SPI_DataDirection_TypeDef : stm8s_spi.h
  • SPI_Direction_TypeDef : stm8s_spi.h
  • SPI_FirstBit_TypeDef : stm8s_spi.h
  • SPI_Flag_TypeDef : stm8s_spi.h
  • SPI_IT_TypeDef : stm8s_spi.h
  • SPI_Mode_TypeDef : stm8s_spi.h
  • SPI_NSS_TypeDef : stm8s_spi.h


STM8S/A Standard Peripherals Drivers: Globals

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- t -

  • TIM1_AutomaticOutput_TypeDef : stm8s_tim1.h
  • TIM1_BreakPolarity_TypeDef : stm8s_tim1.h
  • TIM1_BreakState_TypeDef : stm8s_tim1.h
  • TIM1_Channel_TypeDef : stm8s_tim1.h
  • TIM1_CounterMode_TypeDef : stm8s_tim1.h
  • TIM1_EncoderMode_TypeDef : stm8s_tim1.h
  • TIM1_EventSource_TypeDef : stm8s_tim1.h
  • TIM1_ExtTRGPolarity_TypeDef : stm8s_tim1.h
  • TIM1_ExtTRGPSC_TypeDef : stm8s_tim1.h
  • TIM1_FLAG_TypeDef : stm8s_tim1.h
  • TIM1_ForcedAction_TypeDef : stm8s_tim1.h
  • TIM1_ICPolarity_TypeDef : stm8s_tim1.h
  • TIM1_ICPSC_TypeDef : stm8s_tim1.h
  • TIM1_ICSelection_TypeDef : stm8s_tim1.h
  • TIM1_IT_TypeDef : stm8s_tim1.h
  • TIM1_LockLevel_TypeDef : stm8s_tim1.h
  • TIM1_OCIdleState_TypeDef : stm8s_tim1.h
  • TIM1_OCMode_TypeDef : stm8s_tim1.h
  • TIM1_OCNIdleState_TypeDef : stm8s_tim1.h
  • TIM1_OCNPolarity_TypeDef : stm8s_tim1.h
  • TIM1_OCPolarity_TypeDef : stm8s_tim1.h
  • TIM1_OPMode_TypeDef : stm8s_tim1.h
  • TIM1_OSSIState_TypeDef : stm8s_tim1.h
  • TIM1_OutputNState_TypeDef : stm8s_tim1.h
  • TIM1_OutputState_TypeDef : stm8s_tim1.h
  • TIM1_PSCReloadMode_TypeDef : stm8s_tim1.h
  • TIM1_SlaveMode_TypeDef : stm8s_tim1.h
  • TIM1_TIxExternalCLK1Source_TypeDef : stm8s_tim1.h
  • TIM1_TRGOSource_TypeDef : stm8s_tim1.h
  • TIM1_TS_TypeDef : stm8s_tim1.h
  • TIM1_UpdateSource_TypeDef : stm8s_tim1.h
  • TIM2_Channel_TypeDef : stm8s_tim2.h
  • TIM2_EventSource_TypeDef : stm8s_tim2.h
  • TIM2_FLAG_TypeDef : stm8s_tim2.h
  • TIM2_ForcedAction_TypeDef : stm8s_tim2.h
  • TIM2_ICPolarity_TypeDef : stm8s_tim2.h
  • TIM2_ICPSC_TypeDef : stm8s_tim2.h
  • TIM2_ICSelection_TypeDef : stm8s_tim2.h
  • TIM2_IT_TypeDef : stm8s_tim2.h
  • TIM2_OCMode_TypeDef : stm8s_tim2.h
  • TIM2_OCPolarity_TypeDef : stm8s_tim2.h
  • TIM2_OPMode_TypeDef : stm8s_tim2.h
  • TIM2_OutputState_TypeDef : stm8s_tim2.h
  • TIM2_Prescaler_TypeDef : stm8s_tim2.h
  • TIM2_PSCReloadMode_TypeDef : stm8s_tim2.h
  • TIM2_UpdateSource_TypeDef : stm8s_tim2.h
  • TIM3_Channel_TypeDef : stm8s_tim3.h
  • TIM3_EventSource_TypeDef : stm8s_tim3.h
  • TIM3_FLAG_TypeDef : stm8s_tim3.h
  • TIM3_ForcedAction_TypeDef : stm8s_tim3.h
  • TIM3_ICPolarity_TypeDef : stm8s_tim3.h
  • TIM3_ICPSC_TypeDef : stm8s_tim3.h
  • TIM3_ICSelection_TypeDef : stm8s_tim3.h
  • TIM3_IT_TypeDef : stm8s_tim3.h
  • TIM3_OCMode_TypeDef : stm8s_tim3.h
  • TIM3_OCPolarity_TypeDef : stm8s_tim3.h
  • TIM3_OPMode_TypeDef : stm8s_tim3.h
  • TIM3_OutputState_TypeDef : stm8s_tim3.h
  • TIM3_Prescaler_TypeDef : stm8s_tim3.h
  • TIM3_PSCReloadMode_TypeDef : stm8s_tim3.h
  • TIM3_UpdateSource_TypeDef : stm8s_tim3.h
  • TIM4_EventSource_TypeDef : stm8s_tim4.h
  • TIM4_FLAG_TypeDef : stm8s_tim4.h
  • TIM4_IT_TypeDef : stm8s_tim4.h
  • TIM4_OPMode_TypeDef : stm8s_tim4.h
  • TIM4_Prescaler_TypeDef : stm8s_tim4.h
  • TIM4_PSCReloadMode_TypeDef : stm8s_tim4.h
  • TIM4_UpdateSource_TypeDef : stm8s_tim4.h
  • TIM5_Channel_TypeDef : stm8s_tim5.h
  • TIM5_EncoderMode_TypeDef : stm8s_tim5.h
  • TIM5_EventSource_TypeDef : stm8s_tim5.h
  • TIM5_ExtTRGPolarity_TypeDef : stm8s_tim5.h
  • TIM5_ExtTRGPSC_TypeDef : stm8s_tim5.h
  • TIM5_FLAG_TypeDef : stm8s_tim5.h
  • TIM5_ForcedAction_TypeDef : stm8s_tim5.h
  • TIM5_ICPolarity_TypeDef : stm8s_tim5.h
  • TIM5_ICPSC_TypeDef : stm8s_tim5.h
  • TIM5_ICSelection_TypeDef : stm8s_tim5.h
  • TIM5_IT_TypeDef : stm8s_tim5.h
  • TIM5_OCMode_TypeDef : stm8s_tim5.h
  • TIM5_OCPolarity_TypeDef : stm8s_tim5.h
  • TIM5_OPMode_TypeDef : stm8s_tim5.h
  • TIM5_OutputState_TypeDef : stm8s_tim5.h
  • TIM5_Prescaler_TypeDef : stm8s_tim5.h
  • TIM5_PSCReloadMode_TypeDef : stm8s_tim5.h
  • TIM5_SlaveMode_TypeDef : stm8s_tim5.h
  • TIM5_TRGOSource_TypeDef : stm8s_tim5.h
  • TIM5_TS_TypeDef : stm8s_tim5.h
  • TIM5_UpdateSource_TypeDef : stm8s_tim5.h
  • TIM6_EventSource_TypeDef : stm8s_tim6.h
  • TIM6_FLAG_TypeDef : stm8s_tim6.h
  • TIM6_IT_TypeDef : stm8s_tim6.h
  • TIM6_OPMode_TypeDef : stm8s_tim6.h
  • TIM6_Prescaler_TypeDef : stm8s_tim6.h
  • TIM6_PSCReloadMode_TypeDef : stm8s_tim6.h
  • TIM6_SlaveMode_TypeDef : stm8s_tim6.h
  • TIM6_TRGOSource_TypeDef : stm8s_tim6.h
  • TIM6_TS_TypeDef : stm8s_tim6.h
  • TIM6_UpdateSource_TypeDef : stm8s_tim6.h


STM8S/A Standard Peripherals Drivers: Globals

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- u -

  • UART1_Flag_TypeDef : stm8s_uart1.h
  • UART1_IrDAMode_TypeDef : stm8s_uart1.h
  • UART1_IT_TypeDef : stm8s_uart1.h
  • UART1_LINBreakDetectionLength_TypeDef : stm8s_uart1.h
  • UART1_Mode_TypeDef : stm8s_uart1.h
  • UART1_Parity_TypeDef : stm8s_uart1.h
  • UART1_StopBits_TypeDef : stm8s_uart1.h
  • UART1_SyncMode_TypeDef : stm8s_uart1.h
  • UART1_WakeUp_TypeDef : stm8s_uart1.h
  • UART1_WordLength_TypeDef : stm8s_uart1.h
  • UART2_Flag_TypeDef : stm8s_uart2.h
  • UART2_IrDAMode_TypeDef : stm8s_uart2.h
  • UART2_IT_TypeDef : stm8s_uart2.h
  • UART2_LinAutosync_TypeDef : stm8s_uart2.h
  • UART2_LINBreakDetectionLength_TypeDef : stm8s_uart2.h
  • UART2_LinDivUp_TypeDef : stm8s_uart2.h
  • UART2_LinMode_TypeDef : stm8s_uart2.h
  • UART2_Mode_TypeDef : stm8s_uart2.h
  • UART2_Parity_TypeDef : stm8s_uart2.h
  • UART2_StopBits_TypeDef : stm8s_uart2.h
  • UART2_SyncMode_TypeDef : stm8s_uart2.h
  • UART2_WakeUp_TypeDef : stm8s_uart2.h
  • UART2_WordLength_TypeDef : stm8s_uart2.h
  • UART3_Flag_TypeDef : stm8s_uart3.h
  • UART3_IT_TypeDef : stm8s_uart3.h
  • UART3_LinAutosync_TypeDef : stm8s_uart3.h
  • UART3_LINBreakDetectionLength_TypeDef : stm8s_uart3.h
  • UART3_LinDivUp_TypeDef : stm8s_uart3.h
  • UART3_LinMode_TypeDef : stm8s_uart3.h
  • UART3_Mode_TypeDef : stm8s_uart3.h
  • UART3_Parity_TypeDef : stm8s_uart3.h
  • UART3_StopBits_TypeDef : stm8s_uart3.h
  • UART3_WakeUp_TypeDef : stm8s_uart3.h
  • UART3_WordLength_TypeDef : stm8s_uart3.h
  • UART4_Flag_TypeDef : stm8s_uart4.h
  • UART4_IrDAMode_TypeDef : stm8s_uart4.h
  • UART4_IT_TypeDef : stm8s_uart4.h
  • UART4_LinAutosync_TypeDef : stm8s_uart4.h
  • UART4_LINBreakDetectionLength_TypeDef : stm8s_uart4.h
  • UART4_LinDivUp_TypeDef : stm8s_uart4.h
  • UART4_LinMode_TypeDef : stm8s_uart4.h
  • UART4_Mode_TypeDef : stm8s_uart4.h
  • UART4_Parity_TypeDef : stm8s_uart4.h
  • UART4_StopBits_TypeDef : stm8s_uart4.h
  • UART4_SyncMode_TypeDef : stm8s_uart4.h
  • UART4_WakeUp_TypeDef : stm8s_uart4.h
  • UART4_WordLength_TypeDef : stm8s_uart4.h


STM8S/A Standard Peripherals Drivers: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • i
  • r
  • s
  • t
  • u

- a -

  • ADC1_ALIGN_LEFT : stm8s_adc1.h
  • ADC1_ALIGN_RIGHT : stm8s_adc1.h
  • ADC1_CHANNEL_0 : stm8s_adc1.h
  • ADC1_CHANNEL_1 : stm8s_adc1.h
  • ADC1_CHANNEL_12 : stm8s_adc1.h
  • ADC1_CHANNEL_2 : stm8s_adc1.h
  • ADC1_CHANNEL_3 : stm8s_adc1.h
  • ADC1_CHANNEL_4 : stm8s_adc1.h
  • ADC1_CHANNEL_5 : stm8s_adc1.h
  • ADC1_CHANNEL_6 : stm8s_adc1.h
  • ADC1_CHANNEL_7 : stm8s_adc1.h
  • ADC1_CHANNEL_8 : stm8s_adc1.h
  • ADC1_CHANNEL_9 : stm8s_adc1.h
  • ADC1_CONVERSIONMODE_CONTINUOUS : stm8s_adc1.h
  • ADC1_CONVERSIONMODE_SINGLE : stm8s_adc1.h
  • ADC1_EXTTRIG_GPIO : stm8s_adc1.h
  • ADC1_EXTTRIG_TIM : stm8s_adc1.h
  • ADC1_FLAG_AWD : stm8s_adc1.h
  • ADC1_FLAG_AWS0 : stm8s_adc1.h
  • ADC1_FLAG_AWS1 : stm8s_adc1.h
  • ADC1_FLAG_AWS12 : stm8s_adc1.h
  • ADC1_FLAG_AWS2 : stm8s_adc1.h
  • ADC1_FLAG_AWS3 : stm8s_adc1.h
  • ADC1_FLAG_AWS4 : stm8s_adc1.h
  • ADC1_FLAG_AWS5 : stm8s_adc1.h
  • ADC1_FLAG_AWS6 : stm8s_adc1.h
  • ADC1_FLAG_AWS7 : stm8s_adc1.h
  • ADC1_FLAG_AWS8 : stm8s_adc1.h
  • ADC1_FLAG_AWS9 : stm8s_adc1.h
  • ADC1_FLAG_EOC : stm8s_adc1.h
  • ADC1_FLAG_OVR : stm8s_adc1.h
  • ADC1_IT_AWD : stm8s_adc1.h
  • ADC1_IT_AWDIE : stm8s_adc1.h
  • ADC1_IT_AWS0 : stm8s_adc1.h
  • ADC1_IT_AWS1 : stm8s_adc1.h
  • ADC1_IT_AWS12 : stm8s_adc1.h
  • ADC1_IT_AWS2 : stm8s_adc1.h
  • ADC1_IT_AWS3 : stm8s_adc1.h
  • ADC1_IT_AWS4 : stm8s_adc1.h
  • ADC1_IT_AWS5 : stm8s_adc1.h
  • ADC1_IT_AWS6 : stm8s_adc1.h
  • ADC1_IT_AWS7 : stm8s_adc1.h
  • ADC1_IT_AWS8 : stm8s_adc1.h
  • ADC1_IT_AWS9 : stm8s_adc1.h
  • ADC1_IT_EOC : stm8s_adc1.h
  • ADC1_IT_EOCIE : stm8s_adc1.h
  • ADC1_PRESSEL_FCPU_D10 : stm8s_adc1.h
  • ADC1_PRESSEL_FCPU_D12 : stm8s_adc1.h
  • ADC1_PRESSEL_FCPU_D18 : stm8s_adc1.h
  • ADC1_PRESSEL_FCPU_D2 : stm8s_adc1.h
  • ADC1_PRESSEL_FCPU_D3 : stm8s_adc1.h
  • ADC1_PRESSEL_FCPU_D4 : stm8s_adc1.h
  • ADC1_PRESSEL_FCPU_D6 : stm8s_adc1.h
  • ADC1_PRESSEL_FCPU_D8 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_ALL : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL0 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL1 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL12 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL2 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL3 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL4 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL5 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL6 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL7 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL8 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL9 : stm8s_adc1.h
  • ADC2_ALIGN_LEFT : stm8s_adc2.h
  • ADC2_ALIGN_RIGHT : stm8s_adc2.h
  • ADC2_CHANNEL_0 : stm8s_adc2.h
  • ADC2_CHANNEL_1 : stm8s_adc2.h
  • ADC2_CHANNEL_10 : stm8s_adc2.h
  • ADC2_CHANNEL_11 : stm8s_adc2.h
  • ADC2_CHANNEL_12 : stm8s_adc2.h
  • ADC2_CHANNEL_13 : stm8s_adc2.h
  • ADC2_CHANNEL_14 : stm8s_adc2.h
  • ADC2_CHANNEL_15 : stm8s_adc2.h
  • ADC2_CHANNEL_2 : stm8s_adc2.h
  • ADC2_CHANNEL_3 : stm8s_adc2.h
  • ADC2_CHANNEL_4 : stm8s_adc2.h
  • ADC2_CHANNEL_5 : stm8s_adc2.h
  • ADC2_CHANNEL_6 : stm8s_adc2.h
  • ADC2_CHANNEL_7 : stm8s_adc2.h
  • ADC2_CHANNEL_8 : stm8s_adc2.h
  • ADC2_CHANNEL_9 : stm8s_adc2.h
  • ADC2_CONVERSIONMODE_CONTINUOUS : stm8s_adc2.h
  • ADC2_CONVERSIONMODE_SINGLE : stm8s_adc2.h
  • ADC2_EXTTRIG_GPIO : stm8s_adc2.h
  • ADC2_EXTTRIG_TIM : stm8s_adc2.h
  • ADC2_PRESSEL_FCPU_D10 : stm8s_adc2.h
  • ADC2_PRESSEL_FCPU_D12 : stm8s_adc2.h
  • ADC2_PRESSEL_FCPU_D18 : stm8s_adc2.h
  • ADC2_PRESSEL_FCPU_D2 : stm8s_adc2.h
  • ADC2_PRESSEL_FCPU_D3 : stm8s_adc2.h
  • ADC2_PRESSEL_FCPU_D4 : stm8s_adc2.h
  • ADC2_PRESSEL_FCPU_D6 : stm8s_adc2.h
  • ADC2_PRESSEL_FCPU_D8 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_ALL : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL0 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL1 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL10 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL11 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL12 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL13 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL14 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL15 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL2 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL3 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL4 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL5 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL6 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL7 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL8 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL9 : stm8s_adc2.h
  • AWU_TIMEBASE_128MS : stm8s_awu.h
  • AWU_TIMEBASE_12S : stm8s_awu.h
  • AWU_TIMEBASE_16MS : stm8s_awu.h
  • AWU_TIMEBASE_1MS : stm8s_awu.h
  • AWU_TIMEBASE_1S : stm8s_awu.h
  • AWU_TIMEBASE_250US : stm8s_awu.h
  • AWU_TIMEBASE_256MS : stm8s_awu.h
  • AWU_TIMEBASE_2MS : stm8s_awu.h
  • AWU_TIMEBASE_2S : stm8s_awu.h
  • AWU_TIMEBASE_30S : stm8s_awu.h
  • AWU_TIMEBASE_32MS : stm8s_awu.h
  • AWU_TIMEBASE_4MS : stm8s_awu.h
  • AWU_TIMEBASE_500US : stm8s_awu.h
  • AWU_TIMEBASE_512MS : stm8s_awu.h
  • AWU_TIMEBASE_64MS : stm8s_awu.h
  • AWU_TIMEBASE_8MS : stm8s_awu.h
  • AWU_TIMEBASE_NO_IT : stm8s_awu.h


STM8S/A Standard Peripherals Drivers: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • i
  • r
  • s
  • t
  • u

- b -

  • BEEP_FREQUENCY_1KHZ : stm8s_beep.h
  • BEEP_FREQUENCY_2KHZ : stm8s_beep.h
  • BEEP_FREQUENCY_4KHZ : stm8s_beep.h


STM8S/A Standard Peripherals Drivers: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • i
  • r
  • s
  • t
  • u

- c -

  • CAN_BitSeg1_10TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_11TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_12TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_13TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_14TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_15TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_16TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_1TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_2TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_3TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_4TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_5TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_6TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_7TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_8TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_9TimeQuantum : stm8s_can.h
  • CAN_BitSeg2_1TimeQuantum : stm8s_can.h
  • CAN_BitSeg2_2TimeQuantum : stm8s_can.h
  • CAN_BitSeg2_3TimeQuantum : stm8s_can.h
  • CAN_BitSeg2_4TimeQuantum : stm8s_can.h
  • CAN_BitSeg2_5TimeQuantum : stm8s_can.h
  • CAN_BitSeg2_6TimeQuantum : stm8s_can.h
  • CAN_BitSeg2_7TimeQuantum : stm8s_can.h
  • CAN_BitSeg2_8TimeQuantum : stm8s_can.h
  • CAN_ErrorCode_ACKErr : stm8s_can.h
  • CAN_ErrorCode_BitDominantErr : stm8s_can.h
  • CAN_ErrorCode_BitRecessiveErr : stm8s_can.h
  • CAN_ErrorCode_CRCErr : stm8s_can.h
  • CAN_ErrorCode_FormErr : stm8s_can.h
  • CAN_ErrorCode_NoErr : stm8s_can.h
  • CAN_ErrorCode_SoftwareSetErr : stm8s_can.h
  • CAN_ErrorCode_StuffErr : stm8s_can.h
  • CAN_FilterMode_IdList : stm8s_can.h
  • CAN_FilterMode_IdList_IdMask : stm8s_can.h
  • CAN_FilterMode_IdMask : stm8s_can.h
  • CAN_FilterMode_IdMask_IdList : stm8s_can.h
  • CAN_FilterNumber_0 : stm8s_can.h
  • CAN_FilterNumber_1 : stm8s_can.h
  • CAN_FilterNumber_2 : stm8s_can.h
  • CAN_FilterNumber_3 : stm8s_can.h
  • CAN_FilterNumber_4 : stm8s_can.h
  • CAN_FilterNumber_5 : stm8s_can.h
  • CAN_FilterScale_16_8Bit : stm8s_can.h
  • CAN_FilterScale_16Bit : stm8s_can.h
  • CAN_FilterScale_32Bit : stm8s_can.h
  • CAN_FilterScale_8Bit : stm8s_can.h
  • CAN_FLAG_BOF : stm8s_can.h
  • CAN_FLAG_EPV : stm8s_can.h
  • CAN_FLAG_EWG : stm8s_can.h
  • CAN_FLAG_FF : stm8s_can.h
  • CAN_FLAG_FMP : stm8s_can.h
  • CAN_FLAG_FOV : stm8s_can.h
  • CAN_FLAG_LEC : stm8s_can.h
  • CAN_FLAG_RQCP0 : stm8s_can.h
  • CAN_FLAG_RQCP1 : stm8s_can.h
  • CAN_FLAG_RQCP2 : stm8s_can.h
  • CAN_FLAG_WKU : stm8s_can.h
  • CAN_Id_Extended : stm8s_can.h
  • CAN_Id_Standard : stm8s_can.h
  • CAN_InitStatus_Failed : stm8s_can.h
  • CAN_InitStatus_Success : stm8s_can.h
  • CAN_IT_BOF : stm8s_can.h
  • CAN_IT_EPV : stm8s_can.h
  • CAN_IT_ERR : stm8s_can.h
  • CAN_IT_EWG : stm8s_can.h
  • CAN_IT_FF : stm8s_can.h
  • CAN_IT_FMP : stm8s_can.h
  • CAN_IT_FOV : stm8s_can.h
  • CAN_IT_LEC : stm8s_can.h
  • CAN_IT_TME : stm8s_can.h
  • CAN_IT_WKU : stm8s_can.h
  • CAN_MasterCtrl_AllDisabled : stm8s_can.h
  • CAN_MasterCtrl_AllEnabled : stm8s_can.h
  • CAN_MasterCtrl_AutoBusOffManagement : stm8s_can.h
  • CAN_MasterCtrl_AutoWakeUpMode : stm8s_can.h
  • CAN_MasterCtrl_NoAutoReTx : stm8s_can.h
  • CAN_MasterCtrl_RxFifoLockedMode : stm8s_can.h
  • CAN_MasterCtrl_TimeTriggerCOMMode : stm8s_can.h
  • CAN_MasterCtrl_TxFifoPriority : stm8s_can.h
  • CAN_Mode_LoopBack : stm8s_can.h
  • CAN_Mode_Normal : stm8s_can.h
  • CAN_Mode_Silent : stm8s_can.h
  • CAN_Mode_Silent_LoopBack : stm8s_can.h
  • CAN_ModeStatus_Failed : stm8s_can.h
  • CAN_ModeStatus_Success : stm8s_can.h
  • CAN_NbrPendingMessage_0 : stm8s_can.h
  • CAN_NbrPendingMessage_1 : stm8s_can.h
  • CAN_NbrPendingMessage_2 : stm8s_can.h
  • CAN_NbrPendingMessage_3 : stm8s_can.h
  • CAN_OperatingMode_Initialization : stm8s_can.h
  • CAN_OperatingMode_Normal : stm8s_can.h
  • CAN_OperatingMode_Sleep : stm8s_can.h
  • CAN_Page_Config : stm8s_can.h
  • CAN_Page_Filter01 : stm8s_can.h
  • CAN_Page_Filter23 : stm8s_can.h
  • CAN_Page_Filter45 : stm8s_can.h
  • CAN_Page_RxFifo : stm8s_can.h
  • CAN_Page_TxMailBox0 : stm8s_can.h
  • CAN_Page_TxMailBox1 : stm8s_can.h
  • CAN_Page_TxMailBox2 : stm8s_can.h
  • CAN_RTR_Data : stm8s_can.h
  • CAN_RTR_Remote : stm8s_can.h
  • CAN_Sleep_Failed : stm8s_can.h
  • CAN_Sleep_Ok : stm8s_can.h
  • CAN_ST7Compatibility_Disable : stm8s_can.h
  • CAN_ST7Compatibility_Enable : stm8s_can.h
  • CAN_SynJumpWidth_1TimeQuantum : stm8s_can.h
  • CAN_SynJumpWidth_2TimeQuantum : stm8s_can.h
  • CAN_SynJumpWidth_3TimeQuantum : stm8s_can.h
  • CAN_SynJumpWidth_4TimeQuantum : stm8s_can.h
  • CAN_TransmitMailBox_0 : stm8s_can.h
  • CAN_TransmitMailBox_1 : stm8s_can.h
  • CAN_TransmitMailBox_2 : stm8s_can.h
  • CAN_TxStatus_Failed : stm8s_can.h
  • CAN_TxStatus_MailBox0Ok : stm8s_can.h
  • CAN_TxStatus_MailBox1Ok : stm8s_can.h
  • CAN_TxStatus_MailBox2Ok : stm8s_can.h
  • CAN_TxStatus_MailBoxEmpty : stm8s_can.h
  • CAN_TxStatus_NoMailBox : stm8s_can.h
  • CAN_TxStatus_Ok : stm8s_can.h
  • CAN_TxStatus_Pending : stm8s_can.h
  • CAN_WakeUp_Failed : stm8s_can.h
  • CAN_WakeUp_Ok : stm8s_can.h
  • CLK_CSSCONFIG_DISABLE : stm8s_clk.h
  • CLK_CSSCONFIG_ENABLE : stm8s_clk.h
  • CLK_CSSCONFIG_ENABLEWITHIT : stm8s_clk.h
  • CLK_CURRENTCLOCKSTATE_DISABLE : stm8s_clk.h
  • CLK_CURRENTCLOCKSTATE_ENABLE : stm8s_clk.h
  • CLK_FLAG_AUX : stm8s_clk.h
  • CLK_FLAG_CCOBSY : stm8s_clk.h
  • CLK_FLAG_CCORDY : stm8s_clk.h
  • CLK_FLAG_CSSD : stm8s_clk.h
  • CLK_FLAG_HSERDY : stm8s_clk.h
  • CLK_FLAG_HSIRDY : stm8s_clk.h
  • CLK_FLAG_LSIRDY : stm8s_clk.h
  • CLK_FLAG_SWBSY : stm8s_clk.h
  • CLK_FLAG_SWIF : stm8s_clk.h
  • CLK_HSITRIMVALUE_0 : stm8s_clk.h
  • CLK_HSITRIMVALUE_1 : stm8s_clk.h
  • CLK_HSITRIMVALUE_2 : stm8s_clk.h
  • CLK_HSITRIMVALUE_3 : stm8s_clk.h
  • CLK_HSITRIMVALUE_4 : stm8s_clk.h
  • CLK_HSITRIMVALUE_5 : stm8s_clk.h
  • CLK_HSITRIMVALUE_6 : stm8s_clk.h
  • CLK_HSITRIMVALUE_7 : stm8s_clk.h
  • CLK_IT_CSSD : stm8s_clk.h
  • CLK_IT_SWIF : stm8s_clk.h
  • CLK_OUTPUT_CPU : stm8s_clk.h
  • CLK_OUTPUT_CPUDIV16 : stm8s_clk.h
  • CLK_OUTPUT_CPUDIV2 : stm8s_clk.h
  • CLK_OUTPUT_CPUDIV32 : stm8s_clk.h
  • CLK_OUTPUT_CPUDIV4 : stm8s_clk.h
  • CLK_OUTPUT_CPUDIV64 : stm8s_clk.h
  • CLK_OUTPUT_CPUDIV8 : stm8s_clk.h
  • CLK_OUTPUT_HSE : stm8s_clk.h
  • CLK_OUTPUT_HSI : stm8s_clk.h
  • CLK_OUTPUT_HSIRC : stm8s_clk.h
  • CLK_OUTPUT_LSI : stm8s_clk.h
  • CLK_OUTPUT_MASTER : stm8s_clk.h
  • CLK_OUTPUT_OTHERS : stm8s_clk.h
  • CLK_PERIPHERAL_ADC : stm8s_clk.h
  • CLK_PERIPHERAL_AWU : stm8s_clk.h
  • CLK_PERIPHERAL_CAN : stm8s_clk.h
  • CLK_PERIPHERAL_I2C : stm8s_clk.h
  • CLK_PERIPHERAL_SPI : stm8s_clk.h
  • CLK_PERIPHERAL_TIMER1 : stm8s_clk.h
  • CLK_PERIPHERAL_TIMER2 : stm8s_clk.h
  • CLK_PERIPHERAL_TIMER3 : stm8s_clk.h
  • CLK_PERIPHERAL_TIMER4 : stm8s_clk.h
  • CLK_PERIPHERAL_TIMER5 : stm8s_clk.h
  • CLK_PERIPHERAL_TIMER6 : stm8s_clk.h
  • CLK_PERIPHERAL_UART1 : stm8s_clk.h
  • CLK_PERIPHERAL_UART2 : stm8s_clk.h
  • CLK_PERIPHERAL_UART3 : stm8s_clk.h
  • CLK_PRESCALER_CPUDIV1 : stm8s_clk.h
  • CLK_PRESCALER_CPUDIV128 : stm8s_clk.h
  • CLK_PRESCALER_CPUDIV16 : stm8s_clk.h
  • CLK_PRESCALER_CPUDIV2 : stm8s_clk.h
  • CLK_PRESCALER_CPUDIV32 : stm8s_clk.h
  • CLK_PRESCALER_CPUDIV4 : stm8s_clk.h
  • CLK_PRESCALER_CPUDIV64 : stm8s_clk.h
  • CLK_PRESCALER_CPUDIV8 : stm8s_clk.h
  • CLK_PRESCALER_HSIDIV1 : stm8s_clk.h
  • CLK_PRESCALER_HSIDIV2 : stm8s_clk.h
  • CLK_PRESCALER_HSIDIV4 : stm8s_clk.h
  • CLK_PRESCALER_HSIDIV8 : stm8s_clk.h
  • CLK_SOURCE_HSE : stm8s_clk.h
  • CLK_SOURCE_HSI : stm8s_clk.h
  • CLK_SOURCE_LSI : stm8s_clk.h
  • CLK_SWIMDIVIDER_2 : stm8s_clk.h
  • CLK_SWIMDIVIDER_OTHER : stm8s_clk.h
  • CLK_SWITCHMODE_AUTO : stm8s_clk.h
  • CLK_SWITCHMODE_MANUAL : stm8s_clk.h


STM8S/A Standard Peripherals Drivers: Globals

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- d -

  • DISABLE : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- e -

  • ENABLE : stm8s.h
  • ERROR : stm8s.h
  • EXTI_PORT_GPIOA : stm8s_exti.h
  • EXTI_PORT_GPIOB : stm8s_exti.h
  • EXTI_PORT_GPIOC : stm8s_exti.h
  • EXTI_PORT_GPIOD : stm8s_exti.h
  • EXTI_PORT_GPIOE : stm8s_exti.h
  • EXTI_SENSITIVITY_FALL_LOW : stm8s_exti.h
  • EXTI_SENSITIVITY_FALL_ONLY : stm8s_exti.h
  • EXTI_SENSITIVITY_RISE_FALL : stm8s_exti.h
  • EXTI_SENSITIVITY_RISE_ONLY : stm8s_exti.h
  • EXTI_TLISENSITIVITY_FALL_ONLY : stm8s_exti.h
  • EXTI_TLISENSITIVITY_RISE_ONLY : stm8s_exti.h


STM8S/A Standard Peripherals Drivers: Globals

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- f -

  • FALSE : stm8s.h
  • FLASH_FLAG_DUL : stm8s_flash.h
  • FLASH_FLAG_EOP : stm8s_flash.h
  • FLASH_FLAG_PUL : stm8s_flash.h
  • FLASH_FLAG_WR_PG_DIS : stm8s_flash.h
  • FLASH_LPMODE_POWERDOWN : stm8s_flash.h
  • FLASH_LPMODE_POWERDOWN_STANDBY : stm8s_flash.h
  • FLASH_LPMODE_STANDBY : stm8s_flash.h
  • FLASH_LPMODE_STANDBY_POWERDOWN : stm8s_flash.h
  • FLASH_MEMTYPE_DATA : stm8s_flash.h
  • FLASH_MEMTYPE_PROG : stm8s_flash.h
  • FLASH_PROGRAMMODE_FAST : stm8s_flash.h
  • FLASH_PROGRAMMODE_STANDARD : stm8s_flash.h
  • FLASH_PROGRAMTIME_STANDARD : stm8s_flash.h
  • FLASH_PROGRAMTIME_TPROG : stm8s_flash.h
  • FLASH_STATUS_SUCCESSFUL_OPERATION : stm8s_flash.h
  • FLASH_STATUS_TIMEOUT : stm8s_flash.h
  • FLASH_STATUS_WRITE_PROTECTION_ERROR : stm8s_flash.h


STM8S/A Standard Peripherals Drivers: Globals

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- g -

  • GPIO_MODE_IN_FL_IT : stm8s_gpio.h
  • GPIO_MODE_IN_FL_NO_IT : stm8s_gpio.h
  • GPIO_MODE_IN_PU_IT : stm8s_gpio.h
  • GPIO_MODE_IN_PU_NO_IT : stm8s_gpio.h
  • GPIO_MODE_OUT_OD_HIZ_FAST : stm8s_gpio.h
  • GPIO_MODE_OUT_OD_HIZ_SLOW : stm8s_gpio.h
  • GPIO_MODE_OUT_OD_LOW_FAST : stm8s_gpio.h
  • GPIO_MODE_OUT_OD_LOW_SLOW : stm8s_gpio.h
  • GPIO_MODE_OUT_PP_HIGH_FAST : stm8s_gpio.h
  • GPIO_MODE_OUT_PP_HIGH_SLOW : stm8s_gpio.h
  • GPIO_MODE_OUT_PP_LOW_FAST : stm8s_gpio.h
  • GPIO_MODE_OUT_PP_LOW_SLOW : stm8s_gpio.h
  • GPIO_PIN_0 : stm8s_gpio.h
  • GPIO_PIN_1 : stm8s_gpio.h
  • GPIO_PIN_2 : stm8s_gpio.h
  • GPIO_PIN_3 : stm8s_gpio.h
  • GPIO_PIN_4 : stm8s_gpio.h
  • GPIO_PIN_5 : stm8s_gpio.h
  • GPIO_PIN_6 : stm8s_gpio.h
  • GPIO_PIN_7 : stm8s_gpio.h
  • GPIO_PIN_ALL : stm8s_gpio.h
  • GPIO_PIN_HNIB : stm8s_gpio.h
  • GPIO_PIN_LNIB : stm8s_gpio.h


STM8S/A Standard Peripherals Drivers: Globals

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- i -

  • I2C_ACK_CURR : stm8s_i2c.h
  • I2C_ACK_NEXT : stm8s_i2c.h
  • I2C_ACK_NONE : stm8s_i2c.h
  • I2C_ADDMODE_10BIT : stm8s_i2c.h
  • I2C_ADDMODE_7BIT : stm8s_i2c.h
  • I2C_DIRECTION_RX : stm8s_i2c.h
  • I2C_DIRECTION_TX : stm8s_i2c.h
  • I2C_DUTYCYCLE_16_9 : stm8s_i2c.h
  • I2C_DUTYCYCLE_2 : stm8s_i2c.h
  • I2C_EVENT_MASTER_BYTE_RECEIVED : stm8s_i2c.h
  • I2C_EVENT_MASTER_BYTE_TRANSMITTED : stm8s_i2c.h
  • I2C_EVENT_MASTER_BYTE_TRANSMITTING : stm8s_i2c.h
  • I2C_EVENT_MASTER_MODE_ADDRESS10 : stm8s_i2c.h
  • I2C_EVENT_MASTER_MODE_SELECT : stm8s_i2c.h
  • I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : stm8s_i2c.h
  • I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : stm8s_i2c.h
  • I2C_EVENT_SLAVE_ACK_FAILURE : stm8s_i2c.h
  • I2C_EVENT_SLAVE_BYTE_RECEIVED : stm8s_i2c.h
  • I2C_EVENT_SLAVE_BYTE_TRANSMITTED : stm8s_i2c.h
  • I2C_EVENT_SLAVE_BYTE_TRANSMITTING : stm8s_i2c.h
  • I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : stm8s_i2c.h
  • I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : stm8s_i2c.h
  • I2C_EVENT_SLAVE_STOP_DETECTED : stm8s_i2c.h
  • I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : stm8s_i2c.h
  • I2C_FLAG_ACKNOWLEDGEFAILURE : stm8s_i2c.h
  • I2C_FLAG_ADDRESSSENTMATCHED : stm8s_i2c.h
  • I2C_FLAG_ARBITRATIONLOSS : stm8s_i2c.h
  • I2C_FLAG_BUSBUSY : stm8s_i2c.h
  • I2C_FLAG_BUSERROR : stm8s_i2c.h
  • I2C_FLAG_GENERALCALL : stm8s_i2c.h
  • I2C_FLAG_HEADERSENT : stm8s_i2c.h
  • I2C_FLAG_MASTERSLAVE : stm8s_i2c.h
  • I2C_FLAG_OVERRUNUNDERRUN : stm8s_i2c.h
  • I2C_FLAG_RXNOTEMPTY : stm8s_i2c.h
  • I2C_FLAG_STARTDETECTION : stm8s_i2c.h
  • I2C_FLAG_STOPDETECTION : stm8s_i2c.h
  • I2C_FLAG_TRANSFERFINISHED : stm8s_i2c.h
  • I2C_FLAG_TRANSMITTERRECEIVER : stm8s_i2c.h
  • I2C_FLAG_TXEMPTY : stm8s_i2c.h
  • I2C_FLAG_WAKEUPFROMHALT : stm8s_i2c.h
  • I2C_IT_BUF : stm8s_i2c.h
  • I2C_IT_ERR : stm8s_i2c.h
  • I2C_IT_EVT : stm8s_i2c.h
  • I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE : stm8s_i2c.h
  • I2C_ITPENDINGBIT_ADDRESSSENTMATCHED : stm8s_i2c.h
  • I2C_ITPENDINGBIT_ARBITRATIONLOSS : stm8s_i2c.h
  • I2C_ITPENDINGBIT_BUSERROR : stm8s_i2c.h
  • I2C_ITPENDINGBIT_HEADERSENT : stm8s_i2c.h
  • I2C_ITPENDINGBIT_OVERRUNUNDERRUN : stm8s_i2c.h
  • I2C_ITPENDINGBIT_RXNOTEMPTY : stm8s_i2c.h
  • I2C_ITPENDINGBIT_STARTDETECTION : stm8s_i2c.h
  • I2C_ITPENDINGBIT_STOPDETECTION : stm8s_i2c.h
  • I2C_ITPENDINGBIT_TRANSFERFINISHED : stm8s_i2c.h
  • I2C_ITPENDINGBIT_TXEMPTY : stm8s_i2c.h
  • I2C_ITPENDINGBIT_WAKEUPFROMHALT : stm8s_i2c.h
  • ITC_IRQ_AWU : stm8s_itc.h
  • ITC_IRQ_CLK : stm8s_itc.h
  • ITC_IRQ_EEPROM_EEC : stm8s_itc.h
  • ITC_IRQ_I2C : stm8s_itc.h
  • ITC_IRQ_PORTA : stm8s_itc.h
  • ITC_IRQ_PORTB : stm8s_itc.h
  • ITC_IRQ_PORTC : stm8s_itc.h
  • ITC_IRQ_PORTD : stm8s_itc.h
  • ITC_IRQ_PORTE : stm8s_itc.h
  • ITC_IRQ_SPI : stm8s_itc.h
  • ITC_IRQ_TIM1_CAPCOM : stm8s_itc.h
  • ITC_IRQ_TIM1_OVF : stm8s_itc.h
  • ITC_IRQ_TIM2_CAPCOM : stm8s_itc.h
  • ITC_IRQ_TIM2_OVF : stm8s_itc.h
  • ITC_IRQ_TIM3_CAPCOM : stm8s_itc.h
  • ITC_IRQ_TIM3_OVF : stm8s_itc.h
  • ITC_IRQ_TIM4_OVF : stm8s_itc.h
  • ITC_IRQ_TLI : stm8s_itc.h
  • ITC_PRIORITYLEVEL_0 : stm8s_itc.h
  • ITC_PRIORITYLEVEL_1 : stm8s_itc.h
  • ITC_PRIORITYLEVEL_2 : stm8s_itc.h
  • ITC_PRIORITYLEVEL_3 : stm8s_itc.h
  • IWDG_Prescaler_128 : stm8s_iwdg.h
  • IWDG_Prescaler_16 : stm8s_iwdg.h
  • IWDG_Prescaler_256 : stm8s_iwdg.h
  • IWDG_Prescaler_32 : stm8s_iwdg.h
  • IWDG_Prescaler_4 : stm8s_iwdg.h
  • IWDG_Prescaler_64 : stm8s_iwdg.h
  • IWDG_Prescaler_8 : stm8s_iwdg.h
  • IWDG_WriteAccess_Disable : stm8s_iwdg.h
  • IWDG_WriteAccess_Enable : stm8s_iwdg.h


STM8S/A Standard Peripherals Drivers: Globals

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- r -

  • RESET : stm8s.h
  • RST_FLAG_EMCF : stm8s_rst.h
  • RST_FLAG_ILLOPF : stm8s_rst.h
  • RST_FLAG_IWDGF : stm8s_rst.h
  • RST_FLAG_SWIMF : stm8s_rst.h
  • RST_FLAG_WWDGF : stm8s_rst.h


STM8S/A Standard Peripherals Drivers: Globals

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- s -

  • SET : stm8s.h
  • SPI_BAUDRATEPRESCALER_128 : stm8s_spi.h
  • SPI_BAUDRATEPRESCALER_16 : stm8s_spi.h
  • SPI_BAUDRATEPRESCALER_2 : stm8s_spi.h
  • SPI_BAUDRATEPRESCALER_256 : stm8s_spi.h
  • SPI_BAUDRATEPRESCALER_32 : stm8s_spi.h
  • SPI_BAUDRATEPRESCALER_4 : stm8s_spi.h
  • SPI_BAUDRATEPRESCALER_64 : stm8s_spi.h
  • SPI_BAUDRATEPRESCALER_8 : stm8s_spi.h
  • SPI_CLOCKPHASE_1EDGE : stm8s_spi.h
  • SPI_CLOCKPHASE_2EDGE : stm8s_spi.h
  • SPI_CLOCKPOLARITY_HIGH : stm8s_spi.h
  • SPI_CLOCKPOLARITY_LOW : stm8s_spi.h
  • SPI_CRC_RX : stm8s_spi.h
  • SPI_CRC_TX : stm8s_spi.h
  • SPI_DATADIRECTION_1LINE_RX : stm8s_spi.h
  • SPI_DATADIRECTION_1LINE_TX : stm8s_spi.h
  • SPI_DATADIRECTION_2LINES_FULLDUPLEX : stm8s_spi.h
  • SPI_DATADIRECTION_2LINES_RXONLY : stm8s_spi.h
  • SPI_DIRECTION_RX : stm8s_spi.h
  • SPI_DIRECTION_TX : stm8s_spi.h
  • SPI_FIRSTBIT_LSB : stm8s_spi.h
  • SPI_FIRSTBIT_MSB : stm8s_spi.h
  • SPI_FLAG_BSY : stm8s_spi.h
  • SPI_FLAG_CRCERR : stm8s_spi.h
  • SPI_FLAG_MODF : stm8s_spi.h
  • SPI_FLAG_OVR : stm8s_spi.h
  • SPI_FLAG_RXNE : stm8s_spi.h
  • SPI_FLAG_TXE : stm8s_spi.h
  • SPI_FLAG_WKUP : stm8s_spi.h
  • SPI_IT_CRCERR : stm8s_spi.h
  • SPI_IT_ERR : stm8s_spi.h
  • SPI_IT_MODF : stm8s_spi.h
  • SPI_IT_OVR : stm8s_spi.h
  • SPI_IT_RXNE : stm8s_spi.h
  • SPI_IT_TXE : stm8s_spi.h
  • SPI_IT_WKUP : stm8s_spi.h
  • SPI_MODE_MASTER : stm8s_spi.h
  • SPI_MODE_SLAVE : stm8s_spi.h
  • SPI_NSS_HARD : stm8s_spi.h
  • SPI_NSS_SOFT : stm8s_spi.h
  • SUCCESS : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- t -

  • TIM1_AUTOMATICOUTPUT_DISABLE : stm8s_tim1.h
  • TIM1_AUTOMATICOUTPUT_ENABLE : stm8s_tim1.h
  • TIM1_BREAK_DISABLE : stm8s_tim1.h
  • TIM1_BREAK_ENABLE : stm8s_tim1.h
  • TIM1_BREAKPOLARITY_HIGH : stm8s_tim1.h
  • TIM1_BREAKPOLARITY_LOW : stm8s_tim1.h
  • TIM1_CHANNEL_1 : stm8s_tim1.h
  • TIM1_CHANNEL_2 : stm8s_tim1.h
  • TIM1_CHANNEL_3 : stm8s_tim1.h
  • TIM1_CHANNEL_4 : stm8s_tim1.h
  • TIM1_COUNTERMODE_CENTERALIGNED1 : stm8s_tim1.h
  • TIM1_COUNTERMODE_CENTERALIGNED2 : stm8s_tim1.h
  • TIM1_COUNTERMODE_CENTERALIGNED3 : stm8s_tim1.h
  • TIM1_COUNTERMODE_DOWN : stm8s_tim1.h
  • TIM1_COUNTERMODE_UP : stm8s_tim1.h
  • TIM1_ENCODERMODE_TI1 : stm8s_tim1.h
  • TIM1_ENCODERMODE_TI12 : stm8s_tim1.h
  • TIM1_ENCODERMODE_TI2 : stm8s_tim1.h
  • TIM1_EVENTSOURCE_BREAK : stm8s_tim1.h
  • TIM1_EVENTSOURCE_CC1 : stm8s_tim1.h
  • TIM1_EVENTSOURCE_CC2 : stm8s_tim1.h
  • TIM1_EVENTSOURCE_CC3 : stm8s_tim1.h
  • TIM1_EVENTSOURCE_CC4 : stm8s_tim1.h
  • TIM1_EVENTSOURCE_COM : stm8s_tim1.h
  • TIM1_EVENTSOURCE_TRIGGER : stm8s_tim1.h
  • TIM1_EVENTSOURCE_UPDATE : stm8s_tim1.h
  • TIM1_EXTTRGPOLARITY_INVERTED : stm8s_tim1.h
  • TIM1_EXTTRGPOLARITY_NONINVERTED : stm8s_tim1.h
  • TIM1_EXTTRGPSC_DIV2 : stm8s_tim1.h
  • TIM1_EXTTRGPSC_DIV4 : stm8s_tim1.h
  • TIM1_EXTTRGPSC_DIV8 : stm8s_tim1.h
  • TIM1_EXTTRGPSC_OFF : stm8s_tim1.h
  • TIM1_FLAG_BREAK : stm8s_tim1.h
  • TIM1_FLAG_CC1 : stm8s_tim1.h
  • TIM1_FLAG_CC1OF : stm8s_tim1.h
  • TIM1_FLAG_CC2 : stm8s_tim1.h
  • TIM1_FLAG_CC2OF : stm8s_tim1.h
  • TIM1_FLAG_CC3 : stm8s_tim1.h
  • TIM1_FLAG_CC3OF : stm8s_tim1.h
  • TIM1_FLAG_CC4 : stm8s_tim1.h
  • TIM1_FLAG_CC4OF : stm8s_tim1.h
  • TIM1_FLAG_COM : stm8s_tim1.h
  • TIM1_FLAG_TRIGGER : stm8s_tim1.h
  • TIM1_FLAG_UPDATE : stm8s_tim1.h
  • TIM1_FORCEDACTION_ACTIVE : stm8s_tim1.h
  • TIM1_FORCEDACTION_INACTIVE : stm8s_tim1.h
  • TIM1_ICPOLARITY_FALLING : stm8s_tim1.h
  • TIM1_ICPOLARITY_RISING : stm8s_tim1.h
  • TIM1_ICPSC_DIV1 : stm8s_tim1.h
  • TIM1_ICPSC_DIV2 : stm8s_tim1.h
  • TIM1_ICPSC_DIV4 : stm8s_tim1.h
  • TIM1_ICPSC_DIV8 : stm8s_tim1.h
  • TIM1_ICSELECTION_DIRECTTI : stm8s_tim1.h
  • TIM1_ICSELECTION_INDIRECTTI : stm8s_tim1.h
  • TIM1_ICSELECTION_TRGI : stm8s_tim1.h
  • TIM1_IT_BREAK : stm8s_tim1.h
  • TIM1_IT_CC1 : stm8s_tim1.h
  • TIM1_IT_CC2 : stm8s_tim1.h
  • TIM1_IT_CC3 : stm8s_tim1.h
  • TIM1_IT_CC4 : stm8s_tim1.h
  • TIM1_IT_COM : stm8s_tim1.h
  • TIM1_IT_TRIGGER : stm8s_tim1.h
  • TIM1_IT_UPDATE : stm8s_tim1.h
  • TIM1_LOCKLEVEL_1 : stm8s_tim1.h
  • TIM1_LOCKLEVEL_2 : stm8s_tim1.h
  • TIM1_LOCKLEVEL_3 : stm8s_tim1.h
  • TIM1_LOCKLEVEL_OFF : stm8s_tim1.h
  • TIM1_OCIDLESTATE_RESET : stm8s_tim1.h
  • TIM1_OCIDLESTATE_SET : stm8s_tim1.h
  • TIM1_OCMODE_ACTIVE : stm8s_tim1.h
  • TIM1_OCMODE_INACTIVE : stm8s_tim1.h
  • TIM1_OCMODE_PWM1 : stm8s_tim1.h
  • TIM1_OCMODE_PWM2 : stm8s_tim1.h
  • TIM1_OCMODE_TIMING : stm8s_tim1.h
  • TIM1_OCMODE_TOGGLE : stm8s_tim1.h
  • TIM1_OCNIDLESTATE_RESET : stm8s_tim1.h
  • TIM1_OCNIDLESTATE_SET : stm8s_tim1.h
  • TIM1_OCNPOLARITY_HIGH : stm8s_tim1.h
  • TIM1_OCNPOLARITY_LOW : stm8s_tim1.h
  • TIM1_OCPOLARITY_HIGH : stm8s_tim1.h
  • TIM1_OCPOLARITY_LOW : stm8s_tim1.h
  • TIM1_OPMODE_REPETITIVE : stm8s_tim1.h
  • TIM1_OPMODE_SINGLE : stm8s_tim1.h
  • TIM1_OSSISTATE_DISABLE : stm8s_tim1.h
  • TIM1_OSSISTATE_ENABLE : stm8s_tim1.h
  • TIM1_OUTPUTNSTATE_DISABLE : stm8s_tim1.h
  • TIM1_OUTPUTNSTATE_ENABLE : stm8s_tim1.h
  • TIM1_OUTPUTSTATE_DISABLE : stm8s_tim1.h
  • TIM1_OUTPUTSTATE_ENABLE : stm8s_tim1.h
  • TIM1_PSCRELOADMODE_IMMEDIATE : stm8s_tim1.h
  • TIM1_PSCRELOADMODE_UPDATE : stm8s_tim1.h
  • TIM1_SLAVEMODE_EXTERNAL1 : stm8s_tim1.h
  • TIM1_SLAVEMODE_GATED : stm8s_tim1.h
  • TIM1_SLAVEMODE_RESET : stm8s_tim1.h
  • TIM1_SLAVEMODE_TRIGGER : stm8s_tim1.h
  • TIM1_TIXEXTERNALCLK1SOURCE_TI1 : stm8s_tim1.h
  • TIM1_TIXEXTERNALCLK1SOURCE_TI1ED : stm8s_tim1.h
  • TIM1_TIXEXTERNALCLK1SOURCE_TI2 : stm8s_tim1.h
  • TIM1_TRGOSOURCE_ENABLE : stm8s_tim1.h
  • TIM1_TRGOSource_OC1 : stm8s_tim1.h
  • TIM1_TRGOSOURCE_OC1REF : stm8s_tim1.h
  • TIM1_TRGOSOURCE_OC2REF : stm8s_tim1.h
  • TIM1_TRGOSOURCE_OC3REF : stm8s_tim1.h
  • TIM1_TRGOSOURCE_RESET : stm8s_tim1.h
  • TIM1_TRGOSOURCE_UPDATE : stm8s_tim1.h
  • TIM1_TS_ETRF : stm8s_tim1.h
  • TIM1_TS_TI1F_ED : stm8s_tim1.h
  • TIM1_TS_TI1FP1 : stm8s_tim1.h
  • TIM1_TS_TI2FP2 : stm8s_tim1.h
  • TIM1_TS_TIM5 : stm8s_tim1.h
  • TIM1_TS_TIM6 : stm8s_tim1.h
  • TIM1_UPDATESOURCE_GLOBAL : stm8s_tim1.h
  • TIM1_UPDATESOURCE_REGULAR : stm8s_tim1.h
  • TIM2_CHANNEL_1 : stm8s_tim2.h
  • TIM2_CHANNEL_2 : stm8s_tim2.h
  • TIM2_CHANNEL_3 : stm8s_tim2.h
  • TIM2_EVENTSOURCE_CC1 : stm8s_tim2.h
  • TIM2_EVENTSOURCE_CC2 : stm8s_tim2.h
  • TIM2_EVENTSOURCE_CC3 : stm8s_tim2.h
  • TIM2_EVENTSOURCE_UPDATE : stm8s_tim2.h
  • TIM2_FLAG_CC1 : stm8s_tim2.h
  • TIM2_FLAG_CC1OF : stm8s_tim2.h
  • TIM2_FLAG_CC2 : stm8s_tim2.h
  • TIM2_FLAG_CC2OF : stm8s_tim2.h
  • TIM2_FLAG_CC3 : stm8s_tim2.h
  • TIM2_FLAG_CC3OF : stm8s_tim2.h
  • TIM2_FLAG_UPDATE : stm8s_tim2.h
  • TIM2_FORCEDACTION_ACTIVE : stm8s_tim2.h
  • TIM2_FORCEDACTION_INACTIVE : stm8s_tim2.h
  • TIM2_ICPOLARITY_FALLING : stm8s_tim2.h
  • TIM2_ICPOLARITY_RISING : stm8s_tim2.h
  • TIM2_ICPSC_DIV1 : stm8s_tim2.h
  • TIM2_ICPSC_DIV2 : stm8s_tim2.h
  • TIM2_ICPSC_DIV4 : stm8s_tim2.h
  • TIM2_ICPSC_DIV8 : stm8s_tim2.h
  • TIM2_ICSELECTION_DIRECTTI : stm8s_tim2.h
  • TIM2_ICSELECTION_INDIRECTTI : stm8s_tim2.h
  • TIM2_ICSELECTION_TRGI : stm8s_tim2.h
  • TIM2_IT_CC1 : stm8s_tim2.h
  • TIM2_IT_CC2 : stm8s_tim2.h
  • TIM2_IT_CC3 : stm8s_tim2.h
  • TIM2_IT_UPDATE : stm8s_tim2.h
  • TIM2_OCMODE_ACTIVE : stm8s_tim2.h
  • TIM2_OCMODE_INACTIVE : stm8s_tim2.h
  • TIM2_OCMODE_PWM1 : stm8s_tim2.h
  • TIM2_OCMODE_PWM2 : stm8s_tim2.h
  • TIM2_OCMODE_TIMING : stm8s_tim2.h
  • TIM2_OCMODE_TOGGLE : stm8s_tim2.h
  • TIM2_OCPOLARITY_HIGH : stm8s_tim2.h
  • TIM2_OCPOLARITY_LOW : stm8s_tim2.h
  • TIM2_OPMODE_REPETITIVE : stm8s_tim2.h
  • TIM2_OPMODE_SINGLE : stm8s_tim2.h
  • TIM2_OUTPUTSTATE_DISABLE : stm8s_tim2.h
  • TIM2_OUTPUTSTATE_ENABLE : stm8s_tim2.h
  • TIM2_PRESCALER_1 : stm8s_tim2.h
  • TIM2_PRESCALER_1024 : stm8s_tim2.h
  • TIM2_PRESCALER_128 : stm8s_tim2.h
  • TIM2_PRESCALER_16 : stm8s_tim2.h
  • TIM2_PRESCALER_16384 : stm8s_tim2.h
  • TIM2_PRESCALER_2 : stm8s_tim2.h
  • TIM2_PRESCALER_2048 : stm8s_tim2.h
  • TIM2_PRESCALER_256 : stm8s_tim2.h
  • TIM2_PRESCALER_32 : stm8s_tim2.h
  • TIM2_PRESCALER_32768 : stm8s_tim2.h
  • TIM2_PRESCALER_4 : stm8s_tim2.h
  • TIM2_PRESCALER_4096 : stm8s_tim2.h
  • TIM2_PRESCALER_512 : stm8s_tim2.h
  • TIM2_PRESCALER_64 : stm8s_tim2.h
  • TIM2_PRESCALER_8 : stm8s_tim2.h
  • TIM2_PRESCALER_8192 : stm8s_tim2.h
  • TIM2_PSCRELOADMODE_IMMEDIATE : stm8s_tim2.h
  • TIM2_PSCRELOADMODE_UPDATE : stm8s_tim2.h
  • TIM2_UPDATESOURCE_GLOBAL : stm8s_tim2.h
  • TIM2_UPDATESOURCE_REGULAR : stm8s_tim2.h
  • TIM3_CHANNEL_1 : stm8s_tim3.h
  • TIM3_CHANNEL_2 : stm8s_tim3.h
  • TIM3_EVENTSOURCE_CC1 : stm8s_tim3.h
  • TIM3_EVENTSOURCE_CC2 : stm8s_tim3.h
  • TIM3_EVENTSOURCE_UPDATE : stm8s_tim3.h
  • TIM3_FLAG_CC1 : stm8s_tim3.h
  • TIM3_FLAG_CC1OF : stm8s_tim3.h
  • TIM3_FLAG_CC2 : stm8s_tim3.h
  • TIM3_FLAG_CC2OF : stm8s_tim3.h
  • TIM3_FLAG_UPDATE : stm8s_tim3.h
  • TIM3_FORCEDACTION_ACTIVE : stm8s_tim3.h
  • TIM3_FORCEDACTION_INACTIVE : stm8s_tim3.h
  • TIM3_ICPOLARITY_FALLING : stm8s_tim3.h
  • TIM3_ICPOLARITY_RISING : stm8s_tim3.h
  • TIM3_ICPSC_DIV1 : stm8s_tim3.h
  • TIM3_ICPSC_DIV2 : stm8s_tim3.h
  • TIM3_ICPSC_DIV4 : stm8s_tim3.h
  • TIM3_ICPSC_DIV8 : stm8s_tim3.h
  • TIM3_ICSELECTION_DIRECTTI : stm8s_tim3.h
  • TIM3_ICSELECTION_INDIRECTTI : stm8s_tim3.h
  • TIM3_ICSELECTION_TRGI : stm8s_tim3.h
  • TIM3_IT_CC1 : stm8s_tim3.h
  • TIM3_IT_CC2 : stm8s_tim3.h
  • TIM3_IT_UPDATE : stm8s_tim3.h
  • TIM3_OCMODE_ACTIVE : stm8s_tim3.h
  • TIM3_OCMODE_INACTIVE : stm8s_tim3.h
  • TIM3_OCMODE_PWM1 : stm8s_tim3.h
  • TIM3_OCMODE_PWM2 : stm8s_tim3.h
  • TIM3_OCMODE_TIMING : stm8s_tim3.h
  • TIM3_OCMODE_TOGGLE : stm8s_tim3.h
  • TIM3_OCPOLARITY_HIGH : stm8s_tim3.h
  • TIM3_OCPOLARITY_LOW : stm8s_tim3.h
  • TIM3_OPMODE_REPETITIVE : stm8s_tim3.h
  • TIM3_OPMODE_SINGLE : stm8s_tim3.h
  • TIM3_OUTPUTSTATE_DISABLE : stm8s_tim3.h
  • TIM3_OUTPUTSTATE_ENABLE : stm8s_tim3.h
  • TIM3_PRESCALER_1 : stm8s_tim3.h
  • TIM3_PRESCALER_1024 : stm8s_tim3.h
  • TIM3_PRESCALER_128 : stm8s_tim3.h
  • TIM3_PRESCALER_16 : stm8s_tim3.h
  • TIM3_PRESCALER_16384 : stm8s_tim3.h
  • TIM3_PRESCALER_2 : stm8s_tim3.h
  • TIM3_PRESCALER_2048 : stm8s_tim3.h
  • TIM3_PRESCALER_256 : stm8s_tim3.h
  • TIM3_PRESCALER_32 : stm8s_tim3.h
  • TIM3_PRESCALER_32768 : stm8s_tim3.h
  • TIM3_PRESCALER_4 : stm8s_tim3.h
  • TIM3_PRESCALER_4096 : stm8s_tim3.h
  • TIM3_PRESCALER_512 : stm8s_tim3.h
  • TIM3_PRESCALER_64 : stm8s_tim3.h
  • TIM3_PRESCALER_8 : stm8s_tim3.h
  • TIM3_PRESCALER_8192 : stm8s_tim3.h
  • TIM3_PSCRELOADMODE_IMMEDIATE : stm8s_tim3.h
  • TIM3_PSCRELOADMODE_UPDATE : stm8s_tim3.h
  • TIM3_UPDATESOURCE_GLOBAL : stm8s_tim3.h
  • TIM3_UPDATESOURCE_REGULAR : stm8s_tim3.h
  • TIM4_EVENTSOURCE_UPDATE : stm8s_tim4.h
  • TIM4_FLAG_UPDATE : stm8s_tim4.h
  • TIM4_IT_UPDATE : stm8s_tim4.h
  • TIM4_OPMODE_REPETITIVE : stm8s_tim4.h
  • TIM4_OPMODE_SINGLE : stm8s_tim4.h
  • TIM4_PRESCALER_1 : stm8s_tim4.h
  • TIM4_PRESCALER_128 : stm8s_tim4.h
  • TIM4_PRESCALER_16 : stm8s_tim4.h
  • TIM4_PRESCALER_2 : stm8s_tim4.h
  • TIM4_PRESCALER_32 : stm8s_tim4.h
  • TIM4_PRESCALER_4 : stm8s_tim4.h
  • TIM4_PRESCALER_64 : stm8s_tim4.h
  • TIM4_PRESCALER_8 : stm8s_tim4.h
  • TIM4_PSCRELOADMODE_IMMEDIATE : stm8s_tim4.h
  • TIM4_PSCRELOADMODE_UPDATE : stm8s_tim4.h
  • TIM4_UPDATESOURCE_GLOBAL : stm8s_tim4.h
  • TIM4_UPDATESOURCE_REGULAR : stm8s_tim4.h
  • TIM5_CHANNEL_1 : stm8s_tim5.h
  • TIM5_CHANNEL_2 : stm8s_tim5.h
  • TIM5_CHANNEL_3 : stm8s_tim5.h
  • TIM5_ENCODERMODE_TI1 : stm8s_tim5.h
  • TIM5_ENCODERMODE_TI12 : stm8s_tim5.h
  • TIM5_ENCODERMODE_TI2 : stm8s_tim5.h
  • TIM5_EVENTSOURCE_CC1 : stm8s_tim5.h
  • TIM5_EVENTSOURCE_CC2 : stm8s_tim5.h
  • TIM5_EVENTSOURCE_CC3 : stm8s_tim5.h
  • TIM5_EVENTSOURCE_TRIGGER : stm8s_tim5.h
  • TIM5_EVENTSOURCE_UPDATE : stm8s_tim5.h
  • TIM5_EXTTRGPOLARITY_INVERTED : stm8s_tim5.h
  • TIM5_EXTTRGPOLARITY_NONINVERTED : stm8s_tim5.h
  • TIM5_EXTTRGPSC_DIV2 : stm8s_tim5.h
  • TIM5_EXTTRGPSC_DIV4 : stm8s_tim5.h
  • TIM5_EXTTRGPSC_DIV8 : stm8s_tim5.h
  • TIM5_EXTTRGPSC_OFF : stm8s_tim5.h
  • TIM5_FLAG_CC1 : stm8s_tim5.h
  • TIM5_FLAG_CC1OF : stm8s_tim5.h
  • TIM5_FLAG_CC2 : stm8s_tim5.h
  • TIM5_FLAG_CC2OF : stm8s_tim5.h
  • TIM5_FLAG_CC3 : stm8s_tim5.h
  • TIM5_FLAG_CC3OF : stm8s_tim5.h
  • TIM5_FLAG_TRIGGER : stm8s_tim5.h
  • TIM5_FLAG_UPDATE : stm8s_tim5.h
  • TIM5_FORCEDACTION_ACTIVE : stm8s_tim5.h
  • TIM5_FORCEDACTION_INACTIVE : stm8s_tim5.h
  • TIM5_ICPOLARITY_FALLING : stm8s_tim5.h
  • TIM5_ICPOLARITY_RISING : stm8s_tim5.h
  • TIM5_ICPSC_DIV1 : stm8s_tim5.h
  • TIM5_ICPSC_DIV2 : stm8s_tim5.h
  • TIM5_ICPSC_DIV4 : stm8s_tim5.h
  • TIM5_ICPSC_DIV8 : stm8s_tim5.h
  • TIM5_ICSELECTION_DIRECTTI : stm8s_tim5.h
  • TIM5_ICSELECTION_INDIRECTTI : stm8s_tim5.h
  • TIM5_ICSELECTION_TRGI : stm8s_tim5.h
  • TIM5_IT_CC1 : stm8s_tim5.h
  • TIM5_IT_CC2 : stm8s_tim5.h
  • TIM5_IT_CC3 : stm8s_tim5.h
  • TIM5_IT_TRIGGER : stm8s_tim5.h
  • TIM5_IT_UPDATE : stm8s_tim5.h
  • TIM5_OCMODE_ACTIVE : stm8s_tim5.h
  • TIM5_OCMODE_INACTIVE : stm8s_tim5.h
  • TIM5_OCMODE_PWM1 : stm8s_tim5.h
  • TIM5_OCMODE_PWM2 : stm8s_tim5.h
  • TIM5_OCMODE_TIMING : stm8s_tim5.h
  • TIM5_OCMODE_TOGGLE : stm8s_tim5.h
  • TIM5_OCPOLARITY_HIGH : stm8s_tim5.h
  • TIM5_OCPOLARITY_LOW : stm8s_tim5.h
  • TIM5_OPMODE_REPETITIVE : stm8s_tim5.h
  • TIM5_OPMODE_SINGLE : stm8s_tim5.h
  • TIM5_OUTPUTSTATE_DISABLE : stm8s_tim5.h
  • TIM5_OUTPUTSTATE_ENABLE : stm8s_tim5.h
  • TIM5_PRESCALER_1 : stm8s_tim5.h
  • TIM5_PRESCALER_1024 : stm8s_tim5.h
  • TIM5_PRESCALER_128 : stm8s_tim5.h
  • TIM5_PRESCALER_16 : stm8s_tim5.h
  • TIM5_PRESCALER_16384 : stm8s_tim5.h
  • TIM5_PRESCALER_2 : stm8s_tim5.h
  • TIM5_PRESCALER_2048 : stm8s_tim5.h
  • TIM5_PRESCALER_256 : stm8s_tim5.h
  • TIM5_PRESCALER_32 : stm8s_tim5.h
  • TIM5_PRESCALER_32768 : stm8s_tim5.h
  • TIM5_PRESCALER_4 : stm8s_tim5.h
  • TIM5_PRESCALER_4096 : stm8s_tim5.h
  • TIM5_PRESCALER_512 : stm8s_tim5.h
  • TIM5_PRESCALER_64 : stm8s_tim5.h
  • TIM5_PRESCALER_8 : stm8s_tim5.h
  • TIM5_PRESCALER_8192 : stm8s_tim5.h
  • TIM5_PSCRELOADMODE_IMMEDIATE : stm8s_tim5.h
  • TIM5_PSCRELOADMODE_UPDATE : stm8s_tim5.h
  • TIM5_SLAVEMODE_EXTERNAL1 : stm8s_tim5.h
  • TIM5_SLAVEMODE_GATED : stm8s_tim5.h
  • TIM5_SLAVEMODE_RESET : stm8s_tim5.h
  • TIM5_SLAVEMODE_TRIGGER : stm8s_tim5.h
  • TIM5_TRGOSOURCE_ENABLE : stm8s_tim5.h
  • TIM5_TRGOSOURCE_OC1 : stm8s_tim5.h
  • TIM5_TRGOSOURCE_OC1REF : stm8s_tim5.h
  • TIM5_TRGOSOURCE_OC2REF : stm8s_tim5.h
  • TIM5_TRGOSOURCE_RESET : stm8s_tim5.h
  • TIM5_TRGOSOURCE_UPDATE : stm8s_tim5.h
  • TIM5_TS_TIM1 : stm8s_tim5.h
  • TIM5_TS_TIM6 : stm8s_tim5.h
  • TIM5_UPDATESOURCE_GLOBAL : stm8s_tim5.h
  • TIM5_UPDATESOURCE_REGULAR : stm8s_tim5.h
  • TIM6_EVENTSOURCE_TRIGGER : stm8s_tim6.h
  • TIM6_EVENTSOURCE_UPDATE : stm8s_tim6.h
  • TIM6_FLAG_TRIGGER : stm8s_tim6.h
  • TIM6_FLAG_UPDATE : stm8s_tim6.h
  • TIM6_IT_TRIGGER : stm8s_tim6.h
  • TIM6_IT_UPDATE : stm8s_tim6.h
  • TIM6_OPMODE_REPETITIVE : stm8s_tim6.h
  • TIM6_OPMODE_SINGLE : stm8s_tim6.h
  • TIM6_PRESCALER_1 : stm8s_tim6.h
  • TIM6_PRESCALER_128 : stm8s_tim6.h
  • TIM6_PRESCALER_16 : stm8s_tim6.h
  • TIM6_PRESCALER_2 : stm8s_tim6.h
  • TIM6_PRESCALER_32 : stm8s_tim6.h
  • TIM6_PRESCALER_4 : stm8s_tim6.h
  • TIM6_PRESCALER_64 : stm8s_tim6.h
  • TIM6_PRESCALER_8 : stm8s_tim6.h
  • TIM6_PSCRELOADMODE_IMMEDIATE : stm8s_tim6.h
  • TIM6_PSCRELOADMODE_UPDATE : stm8s_tim6.h
  • TIM6_SLAVEMODE_DISABLE : stm8s_tim6.h
  • TIM6_SLAVEMODE_EXTERNAL1 : stm8s_tim6.h
  • TIM6_SLAVEMODE_GATED : stm8s_tim6.h
  • TIM6_SLAVEMODE_RESET : stm8s_tim6.h
  • TIM6_SLAVEMODE_TRIGGER : stm8s_tim6.h
  • TIM6_TRGOSOURCE_ENABLE : stm8s_tim6.h
  • TIM6_TRGOSOURCE_RESET : stm8s_tim6.h
  • TIM6_TRGOSOURCE_UPDATE : stm8s_tim6.h
  • TIM6_TS_TIM1 : stm8s_tim6.h
  • TIM6_TS_TIM5 : stm8s_tim6.h
  • TIM6_UPDATESOURCE_GLOBAL : stm8s_tim6.h
  • TIM6_UPDATESOURCE_REGULAR : stm8s_tim6.h
  • TRUE : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • i
  • r
  • s
  • t
  • u

- u -

  • UART1_FLAG_FE : stm8s_uart1.h
  • UART1_FLAG_IDLE : stm8s_uart1.h
  • UART1_FLAG_LBDF : stm8s_uart1.h
  • UART1_FLAG_NF : stm8s_uart1.h
  • UART1_FLAG_OR : stm8s_uart1.h
  • UART1_FLAG_PE : stm8s_uart1.h
  • UART1_FLAG_RXNE : stm8s_uart1.h
  • UART1_FLAG_SBK : stm8s_uart1.h
  • UART1_FLAG_TC : stm8s_uart1.h
  • UART1_FLAG_TXE : stm8s_uart1.h
  • UART1_IRDAMODE_LOWPOWER : stm8s_uart1.h
  • UART1_IRDAMODE_NORMAL : stm8s_uart1.h
  • UART1_IT_IDLE : stm8s_uart1.h
  • UART1_IT_LBDF : stm8s_uart1.h
  • UART1_IT_OR : stm8s_uart1.h
  • UART1_IT_PE : stm8s_uart1.h
  • UART1_IT_RXNE : stm8s_uart1.h
  • UART1_IT_RXNE_OR : stm8s_uart1.h
  • UART1_IT_TC : stm8s_uart1.h
  • UART1_IT_TXE : stm8s_uart1.h
  • UART1_LINBREAKDETECTIONLENGTH_10BITS : stm8s_uart1.h
  • UART1_LINBREAKDETECTIONLENGTH_11BITS : stm8s_uart1.h
  • UART1_MODE_RX_DISABLE : stm8s_uart1.h
  • UART1_MODE_RX_ENABLE : stm8s_uart1.h
  • UART1_MODE_TX_DISABLE : stm8s_uart1.h
  • UART1_MODE_TX_ENABLE : stm8s_uart1.h
  • UART1_MODE_TXRX_ENABLE : stm8s_uart1.h
  • UART1_PARITY_EVEN : stm8s_uart1.h
  • UART1_PARITY_NO : stm8s_uart1.h
  • UART1_PARITY_ODD : stm8s_uart1.h
  • UART1_STOPBITS_0_5 : stm8s_uart1.h
  • UART1_STOPBITS_1 : stm8s_uart1.h
  • UART1_STOPBITS_1_5 : stm8s_uart1.h
  • UART1_STOPBITS_2 : stm8s_uart1.h
  • UART1_SYNCMODE_CLOCK_DISABLE : stm8s_uart1.h
  • UART1_SYNCMODE_CLOCK_ENABLE : stm8s_uart1.h
  • UART1_SYNCMODE_CPHA_BEGINING : stm8s_uart1.h
  • UART1_SYNCMODE_CPHA_MIDDLE : stm8s_uart1.h
  • UART1_SYNCMODE_CPOL_HIGH : stm8s_uart1.h
  • UART1_SYNCMODE_CPOL_LOW : stm8s_uart1.h
  • UART1_SYNCMODE_LASTBIT_DISABLE : stm8s_uart1.h
  • UART1_SYNCMODE_LASTBIT_ENABLE : stm8s_uart1.h
  • UART1_WAKEUP_ADDRESSMARK : stm8s_uart1.h
  • UART1_WAKEUP_IDLELINE : stm8s_uart1.h
  • UART1_WORDLENGTH_8D : stm8s_uart1.h
  • UART1_WORDLENGTH_9D : stm8s_uart1.h
  • UART2_FLAG_FE : stm8s_uart2.h
  • UART2_FLAG_IDLE : stm8s_uart2.h
  • UART2_FLAG_LBDF : stm8s_uart2.h
  • UART2_FLAG_LHDF : stm8s_uart2.h
  • UART2_FLAG_LSF : stm8s_uart2.h
  • UART2_FLAG_NF : stm8s_uart2.h
  • UART2_FLAG_OR_LHE : stm8s_uart2.h
  • UART2_FLAG_PE : stm8s_uart2.h
  • UART2_FLAG_RXNE : stm8s_uart2.h
  • UART2_FLAG_SBK : stm8s_uart2.h
  • UART2_FLAG_TC : stm8s_uart2.h
  • UART2_FLAG_TXE : stm8s_uart2.h
  • UART2_IRDAMODE_LOWPOWER : stm8s_uart2.h
  • UART2_IRDAMODE_NORMAL : stm8s_uart2.h
  • UART2_IT_IDLE : stm8s_uart2.h
  • UART2_IT_LBDF : stm8s_uart2.h
  • UART2_IT_LHDF : stm8s_uart2.h
  • UART2_IT_OR : stm8s_uart2.h
  • UART2_IT_PE : stm8s_uart2.h
  • UART2_IT_RXNE : stm8s_uart2.h
  • UART2_IT_RXNE_OR : stm8s_uart2.h
  • UART2_IT_TC : stm8s_uart2.h
  • UART2_IT_TXE : stm8s_uart2.h
  • UART2_LIN_AUTOSYNC_DISABLE : stm8s_uart2.h
  • UART2_LIN_AUTOSYNC_ENABLE : stm8s_uart2.h
  • UART2_LIN_DIVUP_LBRR1 : stm8s_uart2.h
  • UART2_LIN_DIVUP_NEXTRXNE : stm8s_uart2.h
  • UART2_LIN_MODE_MASTER : stm8s_uart2.h
  • UART2_LIN_MODE_SLAVE : stm8s_uart2.h
  • UART2_LINBREAKDETECTIONLENGTH_10BITS : stm8s_uart2.h
  • UART2_LINBREAKDETECTIONLENGTH_11BITS : stm8s_uart2.h
  • UART2_MODE_RX_DISABLE : stm8s_uart2.h
  • UART2_MODE_RX_ENABLE : stm8s_uart2.h
  • UART2_MODE_TX_DISABLE : stm8s_uart2.h
  • UART2_MODE_TX_ENABLE : stm8s_uart2.h
  • UART2_MODE_TXRX_ENABLE : stm8s_uart2.h
  • UART2_PARITY_EVEN : stm8s_uart2.h
  • UART2_PARITY_NO : stm8s_uart2.h
  • UART2_PARITY_ODD : stm8s_uart2.h
  • UART2_STOPBITS_0_5 : stm8s_uart2.h
  • UART2_STOPBITS_1 : stm8s_uart2.h
  • UART2_STOPBITS_1_5 : stm8s_uart2.h
  • UART2_STOPBITS_2 : stm8s_uart2.h
  • UART2_SYNCMODE_CLOCK_DISABLE : stm8s_uart2.h
  • UART2_SYNCMODE_CLOCK_ENABLE : stm8s_uart2.h
  • UART2_SYNCMODE_CPHA_BEGINING : stm8s_uart2.h
  • UART2_SYNCMODE_CPHA_MIDDLE : stm8s_uart2.h
  • UART2_SYNCMODE_CPOL_HIGH : stm8s_uart2.h
  • UART2_SYNCMODE_CPOL_LOW : stm8s_uart2.h
  • UART2_SYNCMODE_LASTBIT_DISABLE : stm8s_uart2.h
  • UART2_SYNCMODE_LASTBIT_ENABLE : stm8s_uart2.h
  • UART2_WAKEUP_ADDRESSMARK : stm8s_uart2.h
  • UART2_WAKEUP_IDLELINE : stm8s_uart2.h
  • UART2_WORDLENGTH_8D : stm8s_uart2.h
  • UART2_WORDLENGTH_9D : stm8s_uart2.h
  • UART3_FLAG_FE : stm8s_uart3.h
  • UART3_FLAG_IDLE : stm8s_uart3.h
  • UART3_FLAG_LBDF : stm8s_uart3.h
  • UART3_FLAG_LHDF : stm8s_uart3.h
  • UART3_FLAG_LSF : stm8s_uart3.h
  • UART3_FLAG_NF : stm8s_uart3.h
  • UART3_FLAG_OR_LHE : stm8s_uart3.h
  • UART3_FLAG_PE : stm8s_uart3.h
  • UART3_FLAG_RXNE : stm8s_uart3.h
  • UART3_FLAG_SBK : stm8s_uart3.h
  • UART3_FLAG_TC : stm8s_uart3.h
  • UART3_FLAG_TXE : stm8s_uart3.h
  • UART3_IT_IDLE : stm8s_uart3.h
  • UART3_IT_LBDF : stm8s_uart3.h
  • UART3_IT_LHDF : stm8s_uart3.h
  • UART3_IT_OR : stm8s_uart3.h
  • UART3_IT_PE : stm8s_uart3.h
  • UART3_IT_RXNE : stm8s_uart3.h
  • UART3_IT_RXNE_OR : stm8s_uart3.h
  • UART3_IT_TC : stm8s_uart3.h
  • UART3_IT_TXE : stm8s_uart3.h
  • UART3_LIN_AUTOSYNC_DISABLE : stm8s_uart3.h
  • UART3_LIN_AUTOSYNC_ENABLE : stm8s_uart3.h
  • UART3_LIN_DIVUP_LBRR1 : stm8s_uart3.h
  • UART3_LIN_DIVUP_NEXTRXNE : stm8s_uart3.h
  • UART3_LIN_MODE_MASTER : stm8s_uart3.h
  • UART3_LIN_MODE_SLAVE : stm8s_uart3.h
  • UART3_LINBREAKDETECTIONLENGTH_10BITS : stm8s_uart3.h
  • UART3_LINBREAKDETECTIONLENGTH_11BITS : stm8s_uart3.h
  • UART3_MODE_RX_DISABLE : stm8s_uart3.h
  • UART3_MODE_RX_ENABLE : stm8s_uart3.h
  • UART3_MODE_TX_DISABLE : stm8s_uart3.h
  • UART3_MODE_TX_ENABLE : stm8s_uart3.h
  • UART3_MODE_TXRX_ENABLE : stm8s_uart3.h
  • UART3_PARITY_EVEN : stm8s_uart3.h
  • UART3_PARITY_NO : stm8s_uart3.h
  • UART3_PARITY_ODD : stm8s_uart3.h
  • UART3_STOPBITS_1 : stm8s_uart3.h
  • UART3_STOPBITS_2 : stm8s_uart3.h
  • UART3_WAKEUP_ADDRESSMARK : stm8s_uart3.h
  • UART3_WAKEUP_IDLELINE : stm8s_uart3.h
  • UART3_WORDLENGTH_8D : stm8s_uart3.h
  • UART3_WORDLENGTH_9D : stm8s_uart3.h
  • UART4_FLAG_FE : stm8s_uart4.h
  • UART4_FLAG_IDLE : stm8s_uart4.h
  • UART4_FLAG_LBDF : stm8s_uart4.h
  • UART4_FLAG_LHDF : stm8s_uart4.h
  • UART4_FLAG_LSF : stm8s_uart4.h
  • UART4_FLAG_NF : stm8s_uart4.h
  • UART4_FLAG_OR_LHE : stm8s_uart4.h
  • UART4_FLAG_PE : stm8s_uart4.h
  • UART4_FLAG_RXNE : stm8s_uart4.h
  • UART4_FLAG_SBK : stm8s_uart4.h
  • UART4_FLAG_TC : stm8s_uart4.h
  • UART4_FLAG_TXE : stm8s_uart4.h
  • UART4_IRDAMODE_LOWPOWER : stm8s_uart4.h
  • UART4_IRDAMODE_NORMAL : stm8s_uart4.h
  • UART4_IT_IDLE : stm8s_uart4.h
  • UART4_IT_LBDF : stm8s_uart4.h
  • UART4_IT_LHDF : stm8s_uart4.h
  • UART4_IT_OR : stm8s_uart4.h
  • UART4_IT_PE : stm8s_uart4.h
  • UART4_IT_RXNE : stm8s_uart4.h
  • UART4_IT_RXNE_OR : stm8s_uart4.h
  • UART4_IT_TC : stm8s_uart4.h
  • UART4_IT_TXE : stm8s_uart4.h
  • UART4_LIN_AUTOSYNC_DISABLE : stm8s_uart4.h
  • UART4_LIN_AUTOSYNC_ENABLE : stm8s_uart4.h
  • UART4_LIN_DIVUP_LBRR1 : stm8s_uart4.h
  • UART4_LIN_DIVUP_NEXTRXNE : stm8s_uart4.h
  • UART4_LIN_MODE_MASTER : stm8s_uart4.h
  • UART4_LIN_MODE_SLAVE : stm8s_uart4.h
  • UART4_LINBREAKDETECTIONLENGTH_10BITS : stm8s_uart4.h
  • UART4_LINBREAKDETECTIONLENGTH_11BITS : stm8s_uart4.h
  • UART4_MODE_RX_DISABLE : stm8s_uart4.h
  • UART4_MODE_RX_ENABLE : stm8s_uart4.h
  • UART4_MODE_TX_DISABLE : stm8s_uart4.h
  • UART4_MODE_TX_ENABLE : stm8s_uart4.h
  • UART4_MODE_TXRX_ENABLE : stm8s_uart4.h
  • UART4_PARITY_EVEN : stm8s_uart4.h
  • UART4_PARITY_NO : stm8s_uart4.h
  • UART4_PARITY_ODD : stm8s_uart4.h
  • UART4_STOPBITS_0_5 : stm8s_uart4.h
  • UART4_STOPBITS_1 : stm8s_uart4.h
  • UART4_STOPBITS_1_5 : stm8s_uart4.h
  • UART4_STOPBITS_2 : stm8s_uart4.h
  • UART4_SYNCMODE_CLOCK_DISABLE : stm8s_uart4.h
  • UART4_SYNCMODE_CLOCK_ENABLE : stm8s_uart4.h
  • UART4_SYNCMODE_CPHA_BEGINING : stm8s_uart4.h
  • UART4_SYNCMODE_CPHA_MIDDLE : stm8s_uart4.h
  • UART4_SYNCMODE_CPOL_HIGH : stm8s_uart4.h
  • UART4_SYNCMODE_CPOL_LOW : stm8s_uart4.h
  • UART4_SYNCMODE_LASTBIT_DISABLE : stm8s_uart4.h
  • UART4_SYNCMODE_LASTBIT_ENABLE : stm8s_uart4.h
  • UART4_WAKEUP_ADDRESSMARK : stm8s_uart4.h
  • UART4_WAKEUP_IDLELINE : stm8s_uart4.h
  • UART4_WORDLENGTH_8D : stm8s_uart4.h
  • UART4_WORDLENGTH_9D : stm8s_uart4.h


STM8S/A Standard Peripherals Drivers: Globals

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- a -

  • ADC1_AWDChannelConfig() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_ClearFlag() : stm8s_adc1.c , stm8s_adc1.h
  • ADC1_ClearITPendingBit() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_Cmd() : stm8s_adc1.c , stm8s_adc1.h
  • ADC1_ConversionConfig() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_DataBufferCmd() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_DeInit() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_ExternalTriggerConfig() : stm8s_adc1.c , stm8s_adc1.h
  • ADC1_GetAWDChannelStatus() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_GetBufferValue() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_GetConversionValue() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_GetFlagStatus() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_GetITStatus() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_Init() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_ITConfig() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_PrescalerConfig() : stm8s_adc1.c , stm8s_adc1.h
  • ADC1_ScanModeCmd() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_SchmittTriggerConfig() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_SetHighThreshold() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_SetLowThreshold() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_StartConversion() : stm8s_adc1.h , stm8s_adc1.c
  • ADC2_ClearFlag() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_ClearITPendingBit() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_Cmd() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_ConversionConfig() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_DeInit() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_ExternalTriggerConfig() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_GetConversionValue() : stm8s_adc2.c , stm8s_adc2.h
  • ADC2_GetFlagStatus() : stm8s_adc2.c , stm8s_adc2.h
  • ADC2_GetITStatus() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_Init() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_ITConfig() : stm8s_adc2.c , stm8s_adc2.h
  • ADC2_PrescalerConfig() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_SchmittTriggerConfig() : stm8s_adc2.c , stm8s_adc2.h
  • ADC2_StartConversion() : stm8s_adc2.h , stm8s_adc2.c
  • AWU_Cmd() : stm8s_awu.c , stm8s_awu.h
  • AWU_DeInit() : stm8s_awu.h , stm8s_awu.c
  • AWU_GetFlagStatus() : stm8s_awu.h , stm8s_awu.c
  • AWU_IdleModeEnable() : stm8s_awu.h , stm8s_awu.c
  • AWU_Init() : stm8s_awu.h , stm8s_awu.c
  • AWU_LSICalibrationConfig() : stm8s_awu.h , stm8s_awu.c


STM8S/A Standard Peripherals Drivers: Globals

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- b -

  • BEEP_Cmd() : stm8s_beep.h , stm8s_beep.c
  • BEEP_DeInit() : stm8s_beep.c , stm8s_beep.h
  • BEEP_Init() : stm8s_beep.h , stm8s_beep.c
  • BEEP_LSICalibrationConfig() : stm8s_beep.c , stm8s_beep.h


STM8S/A Standard Peripherals Drivers: Globals

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- c -

  • CAN_CancelTransmit() : stm8s_can.h , stm8s_can.c
  • CAN_ClearFlag() : stm8s_can.c , stm8s_can.h
  • CAN_ClearITPendingBit() : stm8s_can.h , stm8s_can.c
  • CAN_DeInit() : stm8s_can.c , stm8s_can.h
  • CAN_FIFORelease() : stm8s_can.h , stm8s_can.c
  • CAN_FilterInit() : stm8s_can.h , stm8s_can.c
  • CAN_GetFlagStatus() : stm8s_can.h , stm8s_can.c
  • CAN_GetITStatus() : stm8s_can.c , stm8s_can.h
  • CAN_GetLastErrorCode() : stm8s_can.h , stm8s_can.c
  • CAN_GetMessageTimeStamp() : stm8s_can.h , stm8s_can.c
  • CAN_GetReceivedData() : stm8s_can.h , stm8s_can.c
  • CAN_GetReceivedDLC() : stm8s_can.h , stm8s_can.c
  • CAN_GetReceivedFMI() : stm8s_can.h , stm8s_can.c
  • CAN_GetReceivedId() : stm8s_can.h , stm8s_can.c
  • CAN_GetReceivedIDE() : stm8s_can.h , stm8s_can.c
  • CAN_GetReceivedRTR() : stm8s_can.c , stm8s_can.h
  • CAN_GetSelectedPage() : stm8s_can.h , stm8s_can.c
  • CAN_Init() : stm8s_can.h , stm8s_can.c
  • CAN_ITConfig() : stm8s_can.h , stm8s_can.c
  • CAN_MessagePending() : stm8s_can.h , stm8s_can.c
  • CAN_OperatingModeRequest() : stm8s_can.h , stm8s_can.c
  • CAN_Receive() : stm8s_can.h , stm8s_can.c
  • CAN_SelectPage() : stm8s_can.h , stm8s_can.c
  • CAN_Sleep() : stm8s_can.h , stm8s_can.c
  • CAN_ST7CompatibilityCmd() : stm8s_can.h , stm8s_can.c
  • CAN_Transmit() : stm8s_can.h , stm8s_can.c
  • CAN_TransmitStatus() : stm8s_can.h , stm8s_can.c
  • CAN_TTComModeCmd() : stm8s_can.h , stm8s_can.c
  • CAN_WakeUp() : stm8s_can.h , stm8s_can.c
  • CheckITStatus() : stm8s_can.c
  • CLK_AdjustHSICalibrationValue() : stm8s_clk.h , stm8s_clk.c
  • CLK_CCOCmd() : stm8s_clk.c , stm8s_clk.h
  • CLK_CCOConfig() : stm8s_clk.h , stm8s_clk.c
  • CLK_ClearITPendingBit() : stm8s_clk.h , stm8s_clk.c
  • CLK_ClockSecuritySystemEnable() : stm8s_clk.h , stm8s_clk.c
  • CLK_ClockSwitchCmd() : stm8s_clk.h , stm8s_clk.c
  • CLK_ClockSwitchConfig() : stm8s_clk.c , stm8s_clk.h
  • CLK_DeInit() : stm8s_clk.h , stm8s_clk.c
  • CLK_FastHaltWakeUpCmd() : stm8s_clk.h , stm8s_clk.c
  • CLK_GetClockFreq() : stm8s_clk.h , stm8s_clk.c
  • CLK_GetFlagStatus() : stm8s_clk.h , stm8s_clk.c
  • CLK_GetITStatus() : stm8s_clk.h , stm8s_clk.c
  • CLK_GetSYSCLKSource() : stm8s_clk.h , stm8s_clk.c
  • CLK_HSECmd() : stm8s_clk.h , stm8s_clk.c
  • CLK_HSICmd() : stm8s_clk.c , stm8s_clk.h
  • CLK_HSIPrescalerConfig() : stm8s_clk.h , stm8s_clk.c
  • CLK_ITConfig() : stm8s_clk.h , stm8s_clk.c
  • CLK_LSICmd() : stm8s_clk.h , stm8s_clk.c
  • CLK_PeripheralClockConfig() : stm8s_clk.c , stm8s_clk.h
  • CLK_SlowActiveHaltWakeUpCmd() : stm8s_clk.h , stm8s_clk.c
  • CLK_SWIMConfig() : stm8s_clk.h , stm8s_clk.c
  • CLK_SYSCLKConfig() : stm8s_clk.h , stm8s_clk.c
  • CLK_SYSCLKEmergencyClear() : stm8s_clk.h , stm8s_clk.c


STM8S/A Standard Peripherals Drivers: Globals

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- e -

  • EXTI_DeInit() : stm8s_exti.h , stm8s_exti.c
  • EXTI_GetExtIntSensitivity() : stm8s_exti.c , stm8s_exti.h
  • EXTI_GetTLISensitivity() : stm8s_exti.h , stm8s_exti.c
  • EXTI_SetExtIntSensitivity() : stm8s_exti.h , stm8s_exti.c
  • EXTI_SetTLISensitivity() : stm8s_exti.c , stm8s_exti.h


STM8S/A Standard Peripherals Drivers: Globals

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- f -

  • FLASH_DeInit() : stm8s_flash.h , stm8s_flash.c
  • FLASH_EraseByte() : stm8s_flash.c , stm8s_flash.h
  • FLASH_EraseOptionByte() : stm8s_flash.h , stm8s_flash.c
  • FLASH_GetBootSize() : stm8s_flash.c , stm8s_flash.h
  • FLASH_GetFlagStatus() : stm8s_flash.h , stm8s_flash.c
  • FLASH_GetLowPowerMode() : stm8s_flash.h , stm8s_flash.c
  • FLASH_GetProgrammingTime() : stm8s_flash.h , stm8s_flash.c
  • FLASH_ITConfig() : stm8s_flash.c , stm8s_flash.h
  • FLASH_Lock() : stm8s_flash.h , stm8s_flash.c
  • FLASH_ProgramByte() : stm8s_flash.h , stm8s_flash.c
  • FLASH_ProgramOptionByte() : stm8s_flash.h , stm8s_flash.c
  • FLASH_ProgramWord() : stm8s_flash.c , stm8s_flash.h
  • FLASH_ReadByte() : stm8s_flash.h , stm8s_flash.c
  • FLASH_ReadOptionByte() : stm8s_flash.c , stm8s_flash.h
  • FLASH_SetLowPowerMode() : stm8s_flash.h , stm8s_flash.c
  • FLASH_SetProgrammingTime() : stm8s_flash.c , stm8s_flash.h
  • FLASH_Unlock() : stm8s_flash.c , stm8s_flash.h


STM8S/A Standard Peripherals Drivers: Globals

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- g -

  • GPIO_DeInit() : stm8s_gpio.h , stm8s_gpio.c
  • GPIO_ExternalPullUpConfig() : stm8s_gpio.c , stm8s_gpio.h
  • GPIO_Init() : stm8s_gpio.h , stm8s_gpio.c
  • GPIO_ReadInputData() : stm8s_gpio.c , stm8s_gpio.h
  • GPIO_ReadInputPin() : stm8s_gpio.h , stm8s_gpio.c
  • GPIO_ReadOutputData() : stm8s_gpio.h , stm8s_gpio.c
  • GPIO_Write() : stm8s_gpio.h , stm8s_gpio.c
  • GPIO_WriteHigh() : stm8s_gpio.h , stm8s_gpio.c
  • GPIO_WriteLow() : stm8s_gpio.c , stm8s_gpio.h
  • GPIO_WriteReverse() : stm8s_gpio.c , stm8s_gpio.h


STM8S/A Standard Peripherals Drivers: Globals

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- i -

  • I2C_AcknowledgeConfig() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_CheckEvent() : stm8s_i2c.c , stm8s_i2c.h
  • I2C_ClearFlag() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_ClearITPendingBit() : stm8s_i2c.c , stm8s_i2c.h
  • I2C_Cmd() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_DeInit() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_FastModeDutyCycleConfig() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_GeneralCallCmd() : stm8s_i2c.c , stm8s_i2c.h
  • I2C_GenerateSTART() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_GenerateSTOP() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_GetFlagStatus() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_GetITStatus() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_GetLastEvent() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_Init() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_ITConfig() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_ReceiveData() : stm8s_i2c.c , stm8s_i2c.h
  • I2C_Send7bitAddress() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_SendData() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_SoftwareResetCmd() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_StretchClockCmd() : stm8s_i2c.c , stm8s_i2c.h
  • IN_RAM() : stm8s_flash.h
  • ITC_DeInit() : stm8s_itc.c , stm8s_itc.h
  • ITC_GetCPUCC() : stm8s_itc.c , stm8s_itc.h
  • ITC_GetSoftIntStatus() : stm8s_itc.c , stm8s_itc.h
  • ITC_GetSoftwarePriority() : stm8s_itc.h , stm8s_itc.c
  • ITC_SetSoftwarePriority() : stm8s_itc.h , stm8s_itc.c
  • IWDG_Enable() : stm8s_iwdg.c , stm8s_iwdg.h
  • IWDG_ReloadCounter() : stm8s_iwdg.c , stm8s_iwdg.h
  • IWDG_SetPrescaler() : stm8s_iwdg.c , stm8s_iwdg.h
  • IWDG_SetReload() : stm8s_iwdg.h , stm8s_iwdg.c
  • IWDG_WriteAccessCmd() : stm8s_iwdg.h , stm8s_iwdg.c


STM8S/A Standard Peripherals Drivers: Globals

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- r -

  • RST_ClearFlag() : stm8s_rst.h , stm8s_rst.c
  • RST_GetFlagStatus() : stm8s_rst.h , stm8s_rst.c


STM8S/A Standard Peripherals Drivers: Globals

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- s -

  • SPI_BiDirectionalLineConfig() : stm8s_spi.h , stm8s_spi.c
  • SPI_CalculateCRCCmd() : stm8s_spi.c , stm8s_spi.h
  • SPI_ClearFlag() : stm8s_spi.h , stm8s_spi.c
  • SPI_ClearITPendingBit() : stm8s_spi.c , stm8s_spi.h
  • SPI_Cmd() : stm8s_spi.h , stm8s_spi.c
  • SPI_DeInit() : stm8s_spi.h , stm8s_spi.c
  • SPI_GetCRC() : stm8s_spi.h , stm8s_spi.c
  • SPI_GetCRCPolynomial() : stm8s_spi.c , stm8s_spi.h
  • SPI_GetFlagStatus() : stm8s_spi.h , stm8s_spi.c
  • SPI_GetITStatus() : stm8s_spi.h , stm8s_spi.c
  • SPI_Init() : stm8s_spi.h , stm8s_spi.c
  • SPI_ITConfig() : stm8s_spi.c , stm8s_spi.h
  • SPI_NSSInternalSoftwareCmd() : stm8s_spi.h , stm8s_spi.c
  • SPI_ReceiveData() : stm8s_spi.c , stm8s_spi.h
  • SPI_ResetCRC() : stm8s_spi.h , stm8s_spi.c
  • SPI_SendData() : stm8s_spi.c , stm8s_spi.h
  • SPI_TransmitCRC() : stm8s_spi.c , stm8s_spi.h


STM8S/A Standard Peripherals Drivers: Globals

  • File List
  • Globals
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- t -

  • TI1_Config() : stm8s_tim1.c , stm8s_tim2.c , stm8s_tim5.c , stm8s_tim3.c
  • TI2_Config() : stm8s_tim5.c , stm8s_tim1.c , stm8s_tim2.c , stm8s_tim3.c
  • TI3_Config() : stm8s_tim1.c , stm8s_tim2.c , stm8s_tim5.c
  • TI4_Config() : stm8s_tim1.c
  • TIM1_ARRPreloadConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_BDTRConfig() : stm8s_tim1.c , stm8s_tim1.h
  • TIM1_CCPreloadControl() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_CCxCmd() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_CCxNCmd() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ClearFlag() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ClearITPendingBit() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_Cmd() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_CounterModeConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_CtrlPWMOutputs() : stm8s_tim1.c , stm8s_tim1.h
  • TIM1_DeInit() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_EncoderInterfaceConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ETRClockMode1Config() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ETRClockMode2Config() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ETRConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ForcedOC1Config() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ForcedOC2Config() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ForcedOC3Config() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ForcedOC4Config() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GenerateEvent() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GetCapture1() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GetCapture2() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GetCapture3() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GetCapture4() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GetCounter() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GetFlagStatus() : stm8s_tim1.c , stm8s_tim1.h
  • TIM1_GetITStatus() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GetPrescaler() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ICInit() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_InternalClockConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ITConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC1FastConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC1Init() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC1NPolarityConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC1PolarityConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC1PreloadConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC2FastConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC2Init() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC2NPolarityConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC2PolarityConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC2PreloadConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC3FastConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC3Init() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC3NPolarityConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC3PolarityConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC3PreloadConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC4FastConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC4Init() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC4PolarityConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC4PreloadConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_PrescalerConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_PWMIConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SelectCOM() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SelectHallSensor() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SelectInputTrigger() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SelectMasterSlaveMode() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SelectOCxM() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SelectOnePulseMode() : stm8s_tim1.c , stm8s_tim1.h
  • TIM1_SelectOutputTrigger() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SelectSlaveMode() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetAutoreload() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetCompare1() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetCompare2() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetCompare3() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetCompare4() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetCounter() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetIC1Prescaler() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetIC2Prescaler() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetIC3Prescaler() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetIC4Prescaler() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_TimeBaseInit() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_TIxExternalClockConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_UpdateDisableConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_UpdateRequestConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM2_ARRPreloadConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_CCPreloadControl() : stm8s_tim2.h
  • TIM2_CCxCmd() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_ClearFlag() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_ClearITPendingBit() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_Cmd() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_DeInit() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_ForcedOC1Config() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_ForcedOC2Config() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_ForcedOC3Config() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_GenerateEvent() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_GetCapture1() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_GetCapture2() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_GetCapture3() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_GetCounter() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_GetFlagStatus() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_GetITStatus() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_GetPrescaler() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_ICInit() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_InternalClockConfig() : stm8s_tim2.h
  • TIM2_ITConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC1Init() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC1PolarityConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC1PreloadConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC2Init() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC2PolarityConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC2PreloadConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC3Init() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC3PolarityConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC3PreloadConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_PrescalerConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_PWMIConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SelectOCxM() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SelectOnePulseMode() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SetAutoreload() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SetCompare1() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SetCompare2() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SetCompare3() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SetCounter() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SetIC1Prescaler() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SetIC2Prescaler() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SetIC3Prescaler() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_TimeBaseInit() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_UpdateDisableConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_UpdateRequestConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM3_ARRPreloadConfig() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_CCPreloadControl() : stm8s_tim3.h
  • TIM3_CCxCmd() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_ClearFlag() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_ClearITPendingBit() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_Cmd() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_DeInit() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_ForcedOC1Config() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_ForcedOC2Config() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_GenerateEvent() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_GetCapture1() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_GetCapture2() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_GetCounter() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_GetFlagStatus() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_GetITStatus() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_GetPrescaler() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_ICInit() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_InternalClockConfig() : stm8s_tim3.h
  • TIM3_ITConfig() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_OC1Init() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_OC1PolarityConfig() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_OC1PreloadConfig() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_OC2Init() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_OC2PolarityConfig() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_OC2PreloadConfig() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_PrescalerConfig() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_PWMIConfig() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_SelectOCxM() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_SelectOnePulseMode() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_SetAutoreload() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_SetCompare1() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_SetCompare2() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_SetCounter() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_SetIC1Prescaler() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_SetIC2Prescaler() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_TimeBaseInit() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_UpdateDisableConfig() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_UpdateRequestConfig() : stm8s_tim3.h , stm8s_tim3.c
  • TIM4_ARRPreloadConfig() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_ClearFlag() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_ClearITPendingBit() : stm8s_tim4.c , stm8s_tim4.h
  • TIM4_Cmd() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_DeInit() : stm8s_tim4.c , stm8s_tim4.h
  • TIM4_GenerateEvent() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_GetCounter() : stm8s_tim4.c , stm8s_tim4.h
  • TIM4_GetFlagStatus() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_GetITStatus() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_GetPrescaler() : stm8s_tim4.c , stm8s_tim4.h
  • TIM4_ITConfig() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_PrescalerConfig() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_SelectOnePulseMode() : stm8s_tim4.c , stm8s_tim4.h
  • TIM4_SetAutoreload() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_SetCounter() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_TimeBaseInit() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_UpdateDisableConfig() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_UpdateRequestConfig() : stm8s_tim4.c , stm8s_tim4.h
  • TIM5_ARRPreloadConfig() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_CCPreloadControl() : stm8s_tim5.h
  • TIM5_CCxCmd() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_ClearFlag() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_ClearITPendingBit() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_Cmd() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_DeInit() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_EncoderInterfaceConfig() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_ForcedOC1Config() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_ForcedOC2Config() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_ForcedOC3Config() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_GenerateEvent() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_GetCapture1() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_GetCapture2() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_GetCapture3() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_GetCounter() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_GetFlagStatus() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_GetITStatus() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_GetPrescaler() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_ICInit() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_InternalClockConfig() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_ITConfig() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_OC1Init() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_OC1PolarityConfig() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_OC1PreloadConfig() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_OC2Init() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_OC2PolarityConfig() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_OC2PreloadConfig() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_OC3Init() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_OC3PolarityConfig() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_OC3PreloadConfig() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_PrescalerConfig() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_PWMIConfig() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_SelectInputTrigger() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_SelectOCxM() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_SelectOnePulseMode() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_SelectOutputTrigger() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_SelectSlaveMode() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_SetAutoreload() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_SetCompare1() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_SetCompare2() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_SetCompare3() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_SetCounter() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_SetIC1Prescaler() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_SetIC2Prescaler() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_SetIC3Prescaler() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_TimeBaseInit() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_UpdateDisableConfig() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_UpdateRequestConfig() : stm8s_tim5.c , stm8s_tim5.h
  • TIM6_ARRPreloadConfig() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_ClearFlag() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_ClearITPendingBit() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_Cmd() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_DeInit() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_GenerateEvent() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_GetCounter() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_GetFlagStatus() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_GetITStatus() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_GetPrescaler() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_InternalClockConfig() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_ITConfig() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_PrescalerConfig() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_SelectInputTrigger() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_SelectMasterSlaveMode() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_SelectOnePulseMode() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_SelectOutputTrigger() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_SelectSlaveMode() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_SetAutoreload() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_SetCounter() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_TimeBaseInit() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_UpdateDisableConfig() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_UpdateRequestConfig() : stm8s_tim6.c , stm8s_tim6.h


STM8S/A Standard Peripherals Drivers: Globals

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  • a
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  • t
  • u
  • w

- u -

  • UART1_ClearFlag() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_ClearITPendingBit() : stm8s_uart1.c , stm8s_uart1.h
  • UART1_Cmd() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_DeInit() : stm8s_uart1.c , stm8s_uart1.h
  • UART1_GetFlagStatus() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_GetITStatus() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_HalfDuplexCmd() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_Init() : stm8s_uart1.c , stm8s_uart1.h
  • UART1_IrDACmd() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_IrDAConfig() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_ITConfig() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_LINBreakDetectionConfig() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_LINCmd() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_ReceiveData8() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_ReceiveData9() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_ReceiverWakeUpCmd() : stm8s_uart1.c , stm8s_uart1.h
  • UART1_SendBreak() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_SendData8() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_SendData9() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_SetAddress() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_SetGuardTime() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_SetPrescaler() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_SmartCardCmd() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_SmartCardNACKCmd() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_WakeUpConfig() : stm8s_uart1.h , stm8s_uart1.c
  • UART2_ClearFlag() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_ClearITPendingBit() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_Cmd() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_DeInit() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_GetFlagStatus() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_GetITStatus() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_HalfDuplexCmd() : stm8s_uart2.h
  • UART2_Init() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_IrDACmd() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_IrDAConfig() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_ITConfig() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_LINBreakDetectionConfig() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_LINCmd() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_LINConfig() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_ReceiveData8() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_ReceiveData9() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_ReceiverWakeUpCmd() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_SendBreak() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_SendData8() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_SendData9() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_SetAddress() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_SetGuardTime() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_SetPrescaler() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_SmartCardCmd() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_SmartCardNACKCmd() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_WakeUpConfig() : stm8s_uart2.h , stm8s_uart2.c
  • UART3_ClearFlag() : stm8s_uart3.c , stm8s_uart3.h
  • UART3_ClearITPendingBit() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_Cmd() : stm8s_uart3.c , stm8s_uart3.h
  • UART3_DeInit() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_GetFlagStatus() : stm8s_uart3.c , stm8s_uart3.h
  • UART3_GetITStatus() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_Init() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_ITConfig() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_LINBreakDetectionConfig() : stm8s_uart3.c , stm8s_uart3.h
  • UART3_LINCmd() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_LINConfig() : stm8s_uart3.c , stm8s_uart3.h
  • UART3_ReceiveData8() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_ReceiveData9() : stm8s_uart3.c , stm8s_uart3.h
  • UART3_ReceiverWakeUpCmd() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_SendBreak() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_SendData8() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_SendData9() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_SetAddress() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_WakeUpConfig() : stm8s_uart3.h , stm8s_uart3.c
  • UART4_ClearFlag() : stm8s_uart4.h , stm8s_uart4.c
  • UART4_ClearITPendingBit() : stm8s_uart4.h , stm8s_uart4.c
  • UART4_Cmd() : stm8s_uart4.h , stm8s_uart4.c
  • UART4_DeInit() : stm8s_uart4.c , stm8s_uart4.h
  • UART4_GetFlagStatus() : stm8s_uart4.h , stm8s_uart4.c
  • UART4_GetITStatus() : stm8s_uart4.c , stm8s_uart4.h
  • UART4_HalfDuplexCmd() : stm8s_uart4.h , stm8s_uart4.c
  • UART4_Init() : stm8s_uart4.c , stm8s_uart4.h
  • UART4_IrDACmd() : stm8s_uart4.h , stm8s_uart4.c
  • UART4_IrDAConfig() : stm8s_uart4.h , stm8s_uart4.c
  • UART4_ITConfig() : stm8s_uart4.h , stm8s_uart4.c
  • UART4_LINBreakDetectionConfig() : stm8s_uart4.c , stm8s_uart4.h
  • UART4_LINCmd() : stm8s_uart4.h , stm8s_uart4.c
  • UART4_LINConfig() : stm8s_uart4.h , stm8s_uart4.c
  • UART4_ReceiveData8() : stm8s_uart4.c , stm8s_uart4.h
  • UART4_ReceiveData9() : stm8s_uart4.h , stm8s_uart4.c
  • UART4_ReceiverWakeUpCmd() : stm8s_uart4.h , stm8s_uart4.c
  • UART4_SendBreak() : stm8s_uart4.h , stm8s_uart4.c
  • UART4_SendData8() : stm8s_uart4.c , stm8s_uart4.h
  • UART4_SendData9() : stm8s_uart4.c , stm8s_uart4.h
  • UART4_SetAddress() : stm8s_uart4.h , stm8s_uart4.c
  • UART4_SetGuardTime() : stm8s_uart4.h , stm8s_uart4.c
  • UART4_SetPrescaler() : stm8s_uart4.c , stm8s_uart4.h
  • UART4_SmartCardCmd() : stm8s_uart4.c , stm8s_uart4.h
  • UART4_SmartCardNACKCmd() : stm8s_uart4.c , stm8s_uart4.h
  • UART4_WakeUpConfig() : stm8s_uart4.h , stm8s_uart4.c


STM8S/A Standard Peripherals Drivers: Globals

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- w -

  • WWDG_GetCounter() : stm8s_wwdg.h , stm8s_wwdg.c
  • WWDG_Init() : stm8s_wwdg.c , stm8s_wwdg.h
  • WWDG_SetCounter() : stm8s_wwdg.h , stm8s_wwdg.c
  • WWDG_SetWindowValue() : stm8s_wwdg.h , stm8s_wwdg.c
  • WWDG_SWReset() : stm8s_wwdg.c , stm8s_wwdg.h


STM8S/A Standard Peripherals Drivers: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
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- a -

  • AWU_TypeDef : stm8s.h

- b -

  • BEEP_TypeDef : stm8s.h
  • BitAction : stm8s.h
  • BitStatus : stm8s.h

- c -

  • CFG_TypeDef : stm8s.h
  • CLK_TypeDef : stm8s.h

- e -

  • EXTI_TypeDef : stm8s.h

- f -

  • FLASH_TypeDef : stm8s.h

- g -

  • GPIO_TypeDef : stm8s.h

- i -

  • I2C_TypeDef : stm8s.h
  • int16_t : stm8s.h
  • int32_t : stm8s.h
  • int8_t : stm8s.h
  • ITC_TypeDef : stm8s.h
  • ITStatus : stm8s.h
  • IWDG_TypeDef : stm8s.h

- o -

  • OPT_TypeDef : stm8s.h

- r -

  • RST_TypeDef : stm8s.h

- s -

  • s16 : stm8s.h
  • s32 : stm8s.h
  • s8 : stm8s.h
  • SPI_TypeDef : stm8s.h

- t -

  • TIM1_TypeDef : stm8s.h
  • TIM2_TypeDef : stm8s.h
  • TIM3_TypeDef : stm8s.h
  • TIM4_TypeDef : stm8s.h
  • TIM5_TypeDef : stm8s.h
  • TIM6_TypeDef : stm8s.h

- u -

  • u16 : stm8s.h
  • u32 : stm8s.h
  • u8 : stm8s.h
  • UART1_TypeDef : stm8s.h
  • UART2_TypeDef : stm8s.h
  • UART3_TypeDef : stm8s.h
  • uint16_t : stm8s.h
  • uint32_t : stm8s.h
  • uint8_t : stm8s.h

- w -

  • WWDG_TypeDef : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

  • File List
  • Globals
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  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _Data : stm8s_can.c
  • _DLC : stm8s_can.c
  • _FMI : stm8s_can.c
  • _Id : stm8s_can.c
  • _IDE : stm8s_can.c
  • _RTR : stm8s_can.c
  • APR_Array : stm8s_awu.c
  • CLKPrescTable : stm8s_clk.c
  • HSIDivFactor : stm8s_clk.c
  • TBR_Array : stm8s_awu.c


STM8S/A Standard Peripherals Library: Supported devices and toolchains

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STM8S/A Standard Peripherals Library

Supported devices and toolchains

Copyright 2014 STMicroelectronics

STM8S/A devices peripherals Overview

The following table presents the available peripherals set for each STM8S/A devices.
Glossary
  • High-Density STM8A devices are the STM8AF52xx STM8AF6269/8x/Ax,STM8AF51xx, and STM8AF6169/7x/8x/9x/Ax microcontrollers where the Flash memory density ranges between 32 to 128 Kbytes
  • Medium-Density STM8A devices are the STM8AF622x/4x, STM8AF6266/68, STM8AF612x/4x, and STM8AF6166/68 microcontrollers where the Flash memory density ranges between 8 to 32 Kbytes
  • High-Density STM8S devices are the STM8S207xx, STM8S007x and STM8S208xx microcontrollers where the Flash memory density ranges between 32 to 128 Kbytes.
  • Medium-Density STM8S devices are the STM8S105x and STM8S005x microcontrollers where the Flash memory density ranges between 16 to 32-Kbytes.
  • Low-Density STM8S devices are the STM8S103x, STM8S003x , STM8S001x and STM8S903xx microcontrollers where the Flash density is 8 Kbytes.
  • Low-Density STM8A devices are the STM8AF622x microcontrollers where the Flash density is 8 Kbytes.

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Supported STM8S/A devices

The Standard Peripherals Library supports all STM8S and STM8A family products devices. By using this library it becomes straightforward to move the application firmware from one STM8S/A device to another.

User has only to select which device he will use by controlling preprocessor define declared in stm8s.h file (No selected device by default) then the library will be configured accordingly:

stm8s.h

...

/* Uncomment the line below according to the target STM8S or STM8A device used in your
application. */

/* #define STM8S208 */ /*!< STM8S High density devices with CAN */
/* #define STM8S207 */ /*!< STM8S High density devices without CAN */
 /* #define STM8S007 */ /*!< STM8S Value Line High density devices without CAN */
/* #define STM8AF52Ax */ /*!< STM8A High density devices with CAN */
/* #define STM8AF62Ax */ /*!< STM8A High density devices without CAN */
/* #define STM8S105 */ /*!< STM8S Medium density devices */
 /* #define STM8S005 */ /*!< STM8S Value Line Medium density devices */
/* #define STM8AF626x */ /*!< STM8A Medium density devices */
 /* #define STM8AF622x*/ /*!< STM8A Low density devices */
/* #define STM8S103 */ /*!< STM8S Low density devices */
 /* #define STM8S003 */ /*!< STM8S Value Line Low density devices */
 /* #define STM8S001 */ /*!< STM8S Value Line Low density devices */
/* #define STM8S903 */ /*!< STM8S Low density devices */

/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.

...

In the provided template projects within the Standard Peripherals Library package, the appropriate device is preconfigured and defined in the toolchain compiler preprocessor.

This define will control the declaration of the following part of the Standard Peripherals library:

IRQ channel definition

Peripheral memory mapping and physical registers address definition

Peripheral pointer declaration and driver header file inclusion

Product miscellaneous configuration: external quartz (HSE) value…

Peripheral with Features w/ different/incompatible implementation across the family

Notes: These defines impact essentially the following files:

FLASH driver (stm8s_flash.c/.h files) and ITC driver (stm8s_itc.c/.h files)

stm8s_it.c/.h files as the Interrupt sources are device dependent.

stm8s_conf.h: this file allows library configuration with the appropriate peripheral drivers inclusion according to the selected device.

Per default and in the given file template, headers for all peripheral drivers are uncommented and conditionned by the appropriate device define

Howvever user may choose to don't use some periheral drivers in his application, he only has to comment its related header in the stm8s_conf.h file.

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Supported toolchains

The Standard Peripherals Library supports the following toolchains:

ST Visual Develop STVD
 Embedded Workbench for STM8 EWSTM8

Raisonance Integrated Development Environment RIDE

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For complete documentation on STM8S 8-bit Microcontrollers platform visit www.st.com


STM8S/A Standard Peripherals Library: Peripheral’s Drivers Description

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STM8S/A Standard Peripherals Library

Peripheral’s Drivers Description

Copyright 2014 STMicroelectronics

STM8S/A Standard Peripheral's Library Architecture

The following figure provides a global view of the STM8S/A Standard Peripherals Library usage and interaction with other firmware conponents.

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Description of the STM8S/A Standard Peripheral's Drivers files

The Standard Peripherals library file inclusions relationship is shown in the following figure:

Each peripheral has a source code file stm8s_ppp.c and a header file stm8s_ppp.h. The stm8s_ppp.c file contains all the firmware functions required to use the PPP peripheral.
A single memory mapping file, stm8s.h, is supplied for all peripherals. It contains all the register declarations and bits definition. This is the only file that needs to be included in the user application to interface with the library.
The stm8s_conf.h file is used to specify the set of parameters to interface with the library drivers before running any application.

The table bellow lists and describes the different files used by the Standard Peripherals library:

File name | Description
stm8s_conf.h | Peripheral’s drivers configuration file The user can enable or disable peripheral header file inclusion by using the template This file can also be used to enable or disable the Library run-time failure detection before compiling the firmware library drivers, through the preprocessor define USE_FULL_ASSERT
stm8s_ppp.h | Header file of PPP peripheral This file includes the PPP peripheral function and variable definitions used within these functions.
stm8s_ppp.c | Driver source code file of PPP peripheral written in C language
stm8s_it.h | Header file including all interrupt handlers prototypes
stm8s_it.c | Template source file containing the interrupt service routine (ISR) for CortexM3 exceptions. User can add additional ISR(s) for the used peripheral(s) (for the available peripheral interrupt handler's name, please refer to the startup file startup_stm8s_md.s).

stm8s.h

STM8S/A devices peripheral access layer header file.

The file is the unique include file that the application programmer is using in the C source code, usually in main.c. This file contains:

  • configuration section that allows to select:

- the device used in the target application

- to use or not the peripheral’s drivers in application code (i.e. code will be based on direct
access to peripheral’s registers rather than drivers API) , this option is controlled by the
#define USE_STDPERIPH_DRIVER
- to change few application-specific parameters such as the HSE crystal frequency

  • data structures and the address mapping for all peripherals
  • peripheral's registers declarations and bits definition
  • macros to access peripheral’s registers hardware

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For complete documentation on STM8S 8-bit Microcontrollers platform visit www.st.com


STM8S/A Standard Peripherals Drivers MISRA-C 2004 Compliance

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STM8S/A Standard Peripherals Drivers MISRA-C 2004 Compliance

Copyright 2014 STMicroelectronics

The C programming language is growing in importance and use for embedded systems, but when it comes to developing code for safety-critical systems, the language has many drawbacks. There are several unspecified, implementation-defined, and undefined aspects of the C language that make it unsuited for use when developing safety-critical systems.
The Motor Industry Software Reliability Association’s Guidelines for the use of the C language in critical systems MISRA-C 2004 [1] describe a subset of C, suited for use when developing safety-critical systems.
The STM8S/A Standard Peripherals Drivers (STM8S_StdPeriph_Driver) has been developed to be MISRA-C 2004 compliant.

The following section details how the StdPeriph_Driver complies with MISRA-C 2004 (as described in section 4.4 Claiming compliance of the standard [1]):

  • A compliance matrix has been completed to shows how compliance has been enforced.
  • All the STM8S_StdPeriph_Driver C code is compliant with the rules of MISRA-C 2004 or subject documented deviations.
  • A list of all instances of rules not being followed is being maintained, and for each instance there is an appropriately signed-off deviation.
  • All issues listed in the section "4.2 The programming language and coding context of the standard" [1], that has to be checked during the phase of the firmware development process, have been addressed during the development of the STM8S/A Standard Peripherals Drivers and appropriate measures have been taken.

Contents

  1. STM8S/A Standard Peripherals Drivers Compliance
  2. How to check your code for MISRA-C 2004 Compliance?

STM8S/A Standard Peripherals Drivers Compliance

The STM8S/A Standard Peripherals Drivers (STM8S_StdPeriph_Driver) has been checked for MISRA-C 2004 compliance using the IAR C/C++ Compiler for STM8. MISRA compliancy applies only to STM8S/A Standard Peripherals Drivers source file, examples and project files are not MISRA compliant.

For the checking tool two options are available:

  • The compiler: IAR C/C++ Compiler for STM8
  • Manual Checking (code review)

The following table lists the MISRA-C 2004 rules that are violated frequently in the code.

MISRA-C 2004 Rule No | Required/Advisory | Summary | Reason
1.1 | Required | Compiler is configured to allow extensions - all code shall conform to ISO 9899 standard C, with no extensions permitted | IAR compiler extensions are enabled.
5.1 | Required | Identifiers (internal and external) shall not rely on significance of more than 31 characters | Some long parameters names are defined for code readability.
5.4 | Required | Enumerated type mixed with another type - the use of a tag shall agree with its declaration. |
10.1 | Required | The value of an expression of integer type shall not be implicitly converted to a different underlying type. | Complexity
10.6 | Required | A 'U' suffix shall be applied to all constants of 'unsigned' type | The "stdint.h" defined types are used to be compatible w/ STM32.
11.2 | Required | Conversions shall not be performed between a pointer to object and any type other than an integral type, another pointer to object type or a pointer to void. | Needed when addressing memory mapped registers
11.3 | Advisory | A cast should not be performed between a pointer type and an integral type. | Needed when addressing memory mapped registers
11.4 | Advisory | A cast should not be performed between a pointer to object type and a different pointer to object type, | Avoid complexity in Flash driver
16.7 | Advisory | A pointer parameter in a function prototype should be declared as pointer to const if the pointer is not used to modify the addressed object. | Avoid complexity in Flash driver
17.4 | Required | Array indexing shall be the only allowed form of pointer arithmetic | Avoid complexity in Flash driver
19.1 | Advisory | #include statements in a file shall only be preceded by other preprocessor directives or comments | This rule was violated to be inline with STM32.
19.13 | Advisory | # and ## preprosso operators shouldn't be used | Needed for EWSTM8 macro interrupt routine definition

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How to check your code for MISRA-C 2004 Compliance?

The default IAR project template provided with the STM8S/A Standard Peripherals Library is already pre-configured for MISRA-C 2004 Compliance. Then, user has to enable the MISRA-C 2004 checker if needed.

To enable the IAR MISRA-C 2004 Checker, go to Project->Options (ALT+F7) and then in "General Options" Category select the "MISRA-C:2004" tab and check the "Enable MISRA-C" box. With the default EWSTM8 project template, all violated rules described above are unchecked.

To check your code for MISRA-C 2004 compliance using the IAR MISRA-C Checker, please follow the following steps

Enable the IAR MISRA-C 2004 Checker

Uncomment the "USE_FULL_ASSERT" inside the stm8s_conf.h file

Note: Only the STM8S/A Standard Peripherals Drivers are MISRA-C 2004 Compliant.

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[1] MISRA-C 2004 Guidelines for the use of the C language in critical systems, Motor Industry Software Reliability Association, October 2004

For complete documentation on STM8S 8-bit microcontrollers platform visit www.st.com


STM8S/A Standard Peripherals Library: Overview

Copyright 2014 STMicroelectronics

The STM8S/A Standard Peripherals library covers 3 abstraction levels, and includes:

A complete register address mapping with all bits, bit fields and registers declared in C. This avoids a cumbersome task and more important, it brings the benefits of a bug free reference mapping file, speeding up the early project phase.

A collection of routines and data structures which covers all peripheral functions (drivers with common API). It can directly be used as a reference framework, since it also includes macros for supporting core-related intrinsic features and common constants and data types definition.

A set of examples covering all available peripherals with template projects for the most common development toolchains. With the appropriate hardware evaluation board, this allows to get started with a brand new micro within few hours.

Each driver consists of a set of functions covering all peripheral functionalities. The development of each driver is driven by a common API (application programming interface) which standardizes the driver structure, the functions and the parameter names.
The driver source code is developed in ‘Strict ANSI-C’ (relaxed ANSI-C for projects and example files). It is fully documented and is MISRA-C 2004 compliant (the compliancy matrix is available upon request). Writing the whole library in ‘Strict ANSI-C’ makes it independent from the software toolchain. Only the start-up files depend on the toolchain.

The Standard Peripherals Library implements run-time failure detection by checking the input values for all library functions. Such dynamic checking contributes towards enhancing the robustness of the software. Run-time detection is suitable for user application development and debugging. It adds an overhead which can be removed from the final application code to minimize code size and execution speed. For more details refer to Section Run-time checking.

Since the Standard Peripherals Library is generic and covers all peripheral functionalities, the size and/or execution speed of the application code may not be optimized. For many applications, the library may be used as is. However, for applications having tough constraints in terms of code size and/or execution speed, the library drivers should be used as a reference on how to configure the peripheral and tailor them to specific application requirements.

Note: The performance of application code, in terms of size and/or speed, depends also from the C compiler optimization settings. To help make the application code smaller, faster or balanced between size and speed you should consider fine-tuning the optimizations according to your application needs. For more information please refer to your C compiler documentation.

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For complete documentation on STM8S 8-bit microcontrollers platform visit www.st.com


STM8S/A Standard Peripherals Library: Coding rules and conventions

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STM8S/A Standard Peripherals Library: Coding rules and conventions

Copyright © 2014 STMicroelectronics

The Standard Peripherals Library uses rules and conventions described in the sections below.

Acronyms

The Table below describes the acronyms used in the Standard Peripherals Library.

Acronym | Peripheral/unit
ADC | Analog to digital converter
BEEP | Beeper
CLK | Clock controller
CAN | CAN
EXTI | External interrupt/event controller
FLASH | Flash memory
GPIO | General purpose I/O
I2C | Inter-integrated circuit
ITC | Interrupt controller
IWDG | Independent watchdog
RST | Reset controller
SPI | Serial peripheral interface
TIM1 | 16-bit advanced control timer
TIM2, TIM3, TIM5, TIM6 | 16-bit general purpose timers
TIM4 | 8-bit basic timer
UART | Universal asynchronous receiver transmitter
WWDG | Window watchdog

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Naming conventions

The Standard Peripherals Library uses the following naming conventions:

  • PPP refers to any peripheral acronym, for example TIM2 and TIM3.
  • System and source/header file names are preceded by the prefix ‘stm8s_’.
  • Constants used in one file are defined within this file. A constant used in more than one file is defined in a header file. All constants are written in upper case.
  • Registers are considered as constants. Their names are in upper case. In most cases, the same acronyms as in the product reference manual document are used.
  • Names of peripheral functions are preceded by the corresponding peripheral acronym in upper case followed by an underscore. The first letter in each word is in upper case, for example SPI_SendData. Only one underscore is allowed in a function name to separate the peripheral acronym from the rest of the function name.
  • Functions used to initialize the PPP peripheral according to parameters specified in the header file are named PPP_Init, for example TIM2_Init.
  • Functions used to reset the PPP peripheral registers to their default values are named PPP_DeInit, for example TIM2_DeInit.
  • Functions used to enable or disable the specified PPP peripheral are named PPP_Cmd, for example SPI_Cmd.
  • Functions used to enable or disable an interrupt source of the specified PPP peripheral are named PPP_ITConfig, for example SPI_ITConfig.
  • Functions used to configure a peripheral function always end with the string ‘Config’, for example TIM2_ETRConfig
  • Functions used to check whether the specified PPP flag is set or reset are named PPP_GetFlagStatus, for example I2C_GetFlagStatus.
  • Functions used to clear a PPP flag are named PPP_ClearFlag, for example I2C_ClearFlag.
  • Functions used to check whether the specified PPP interrupt has occurred or not are named PPP_GetITStatus, for example TIM2_GetITStatus.
  • Functions used to clear a PPP interrupt pending bit are named PPP_ClearITPendingBit, for example TIM2_ClearITPendingBit.

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Coding rules

This section describes the coding rules used in the Standard Peripherals Library.

Variable types

Specific variable types are already defined with a fixed type and size. These types are defined in the file stm8s.h

#define
    __I     volatile
    const
    /*!< defines 'read only' permissions      */
#define     __O
    volatile
    /*!< defines 'write only' permissions     */
#define     __IO
    volatile
    /*!< defines 'read / write' permissions   */

/*!< Constant qualifier */
#ifdef _COSMIC_
#define __CONST  const
#else /* _RAISONANCE_*/
#define __CONST  code
#endif /*_COSMIC_*/

/*!< Signed integer types  */
typedef   signed char     int8_t;
typedef   signed short    int16_t;
typedef   signed long     int32_t;

/*!< Unsigned integer types  */
typedef unsigned char     uint8_t;
typedef unsigned short    uint16_t;
typedef unsigned long     uint32_t;

typedef enum {FALSE = 0, TRUE = !FALSE} bool;

typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, BitStatus, BitAction;

typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;

typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;

Peripheral registers

Peripheral registers are accessed through a pointer of structure. Each peripheral has its own structure and pointer. All the structures and declarations are defined in the stm8s.h file.

Registers structure
The example below illustrates the Serial Peripheral Interface (SPI) registers structure declaration:

typedef struct SPI_struct
{
    __IO uint8_t CR1;    /*!< SPI control register 1 */
    __IO uint8_t CR2;    /*!< SPI control register 2 */
    __IO uint8_t CR3;    /*!< SPI DMA and interrupt control register */
    __IO uint8_t SR;     /*!< SPI status register */
    __IO uint8_t DR;     /*!< SPI data I/O register */
    __IO uint8_t CRCPR;  /*!< SPI CRC polynomial register */
    __IO uint8_t RXCRCR; /*!< SPI Rx CRC register */
    __IO uint8_t TXCRCR; /*!< SPI Tx CRC register */
}
SPI_TypeDef;

Register names are the register acronyms written in upper case for each peripheral.
RESERVEDi indicates a reserved field (i being an integer that indexes the reserved field).

Peripheral declaration
The following example shows the declaration of the SPI peripheral:

#define SPI1_BaseAddress      (uint16_t)0x5200
...
#define SPI1 ((SPI_TypeDef *) SPI1_BaseAddress)

The peripheral registers are accessed as follows:

SPI1->CR1 = 0x01;

Each peripheral has several dedicated registers which contain different flags. Registers are defined within a dedicated structure for each peripheral. Flags are defined as acronyms written in upper case and preceded by ‘PPP_FLAG_’. Flag definition is adapted to each peripheral case and defined in stm8l15x_ppp.h file.

Registers reset values
The reset values of all peripheral registers are defined as constants in the stm8s.h file. They are defined as acronyms written in upper-case into the form:

PPP_<register_name>_RESET_VALUE

Example:

#define SPI_CR1_RESET_VALUE    ((uint8_t)0x00) /*!< Control Register 1 reset value */
#define SPI_CR2_RESET_VALUE    ((uint8_t)0x00) /*!< Control Register 2 reset value */
#define SPI_CR3_RESET_VALUE    ((uint8_t)0x00) /*!< DMA and Interrupt Control Register reset value */
#define SPI_SR_RESET_VALUE     ((uint8_t)0x02) /*!< Status Register reset value */
#define SPI_DR_RESET_VALUE     ((uint8_t)0x00) /*!< Data Register reset value */
#define SPI_CRCPR_RESET_VALUE  ((uint8_t)0x07) /*!< Polynomial Register reset value */
#define SPI_RXCRCR_RESET_VALUE ((uint8_t)0x00) /*!< RX CRC Register reset value */
#define SPI_TXCRCR_RESET_VALUE ((uint8_t)0x00) /*!< TX CRC Register reset value */

Registers bits
All the peripheral registers bits are defined as constants in the stm8s.h file. They are defined as acronyms written in upper-case into the form:

PPP_<register_name>_<bit_name>

Example:

#define SPI_CR1_LSBFIRST ((uint8_t)0x80) /*!< Frame format mask */
#define SPI_CR1_SPE      ((uint8_t)0x40) /*!< Enable bits mask */
#define SPI_CR1_BR       ((uint8_t)0x38) /*!< Baud rate control mask */
#define SPI_CR1_MSTR     ((uint8_t)0x04) /*!< Master Selection mask */
#define SPI_CR1_CPOL     ((uint8_t)0x02) /*!< Clock Polarity mask */
#define SPI_CR1_CPHA     ((uint8_t)0x01) /*!< Clock Phase mask */

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Run-time checking

The Standard Peripherals Library implements run-time failure detection by checking the input values of all library functions. The run-time checking is achieved by using an assert_param macro. This macro is used in all library functions which have at least an input parameter. It allows the user to check that the input value lies within the defined parameter values.

BEEP_Init function example

stm8s_beep.c
void BEEP_Init(BEEP_Frequency_TypeDef BEEP_Frequency)
{
 /* Check parameter */
  assert_param(IS_BEEP_FREQUENCY(BEEP_Frequency));
...
}

stm8s_beep.h
#define IS_BEEP_FREQUENCY(FREQ) \
  (((FREQ) == BEEP_Frequency_1KHz) || \
   ((FREQ) == BEEP_Frequency_2KHz) || \
   ((FREQ) == BEEP_Frequency_4KHz))

If the expression passed to the assert_param macro is false, the assert_failed function is called, otherwise nothing happens.

Two implementation of assert_failed function are provided, depending on FULL_ASSERT define (declared in stm8l15x_conf.h file).

  • #define FULL_ASSERT (1) line is uncommented, if the expression passed to the assert_param macro is false, the assert_failed function will have as input the name of the source file and the source line number of the call that failed.
  • #define FULL_ASSERT (1) line is commented, if the expression passed to the assert_param macro is true, the assert_failed function will have takes no does not returns the name of the source file and the source line number of the call that failed.

The assert_param macro is implemented in stm8l15x_conf.h as follows:

#ifdef  USE_FULL_ASSERT

/**
  * @brief  The assert_param macro is used for function's parameters check.
  * @param expr: If expr is false, it calls assert_failed function
  *   which reports the name of the source file and the source
  *   line number of the call that failed.
  *   If expr is true, it returns no value.
  * @retval : None
  */
  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
  void assert_failed(uint8_t* file, uint32_t line);
#else
  #define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */

The assert_failed function is implemented in the main.c file or in any other user C files and can be modified by the user in order to take action when an error occurs.

#ifdef  USE_FULL_ASSERT

/**
  * @brief  Reports the name of the source file and the source line number
  *   where the assert_param error has occurred.
  * @param file: pointer to the source file name
  * @param line: assert_param error line source number
  * @retval : None
  */
void assert_failed(uint8_t* file, uint32_t line)
{
  /* User can add his own implementation to report the file name and line number,
     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */

  /* Infinite loop */
  while (1)
  {
  }
}
#endif

It is recommended to use run-time checking during application code development and debugging, and to remove it from the final application to improve code size and speed (because of the overhead it introduces).
However if the user wants to keep this functionality in his final application, he can re-use the assert_param macro defined within the library to test the parameter values before calling the library functions.

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For complete documentation on STM8S 8-bit microcontrollers platform visit www.st.com


STM8S/A Standard Peripherals Drivers: main_page.txt File Reference

  • File List
  • Globals
main_page.txt File Reference


STM8S/A Standard Peripherals Drivers: Modules

Modules
Here is a list of all modules:
  • STM8S_StdPeriph_Driver
    • Exported_types
    • MAP_FILE_Exported_Types_and_Constants
    • GPIO_Registers_Reset_Value
    • IWDG_Private_Define
    • IWDG_Private_Macros
    • IWDG_Exported_Types
    • IWDG_Exported_Functions
    • RST_Exported_Types
    • RST_Private_Macros
    • RST_Exported_functions
    • SPI_Exported_Types
    • SPI_Private_Macros
    • SPI_Exported_Functions
    • TIM1_Exported_Types
    • TIM1_Exported_Functions
    • TIM3_Exported_Types
    • TIM3_Exported_Functions
    • TIM4_Exported_Types
    • TIM4_Exported_Functions
    • TIM6_Exported_Types
    • TIM6_Private_Macros
    • TIM6_Exported_Functions
    • UART1_Exported_Types
    • UART1_Private_Macros
    • UART1_Exported_Functions
    • UART2_Exported_Types
    • UART2_Private_Macros
    • UART2_Exported_Functions
    • UART3_Exported_Types
    • UART3_Private_Macros
    • UART3_Exported_Functions
    • UART4_Exported_Types
    • UART4_Private_Macros
    • UART4_Exported_Functions
    • WWDG_Private_Macros
    • WWDG_Exported_Functions
    • ADC1_Public_Functions
    • ADC2_Public_Functions
    • AWU_Public_Functions
    • BEEP_Public_Functions
    • CAN_Public_Functions
    • CLK_Private_Constants
    • CLK_Public_Functions
    • EXTI_Public_Functions
    • FLASH_Public_functions
    • GPIO_Public_Functions
    • I2C_Private_Defines
    • I2C_Public_Functions
    • ITC_Private_Functions
    • ITC_Public_Functions
    • RST_Public_Functions
    • SPI_Public_Functions
    • TIM1_Public_Functions
    • TIM2_Public_Functions
    • TIM3_Public_Functions
    • TIM4_Public_Functions
    • TIM5_Public_Functions
    • TIM6_Public_Functions
    • UART1_Public_Functions
    • UART2_Public_Functions
    • UART3_Public_Functions
    • UART4_Public_Functions
    • WWDG_Public_Functions
  • AWU_Registers_Reset_Value
  • AWU_Registers_Bits_Definition
  • BEEP_Registers_Reset_Value
  • BEEP_Registers_Bits_Definition
  • CLK_Registers_Reset_Value
  • CLK_Registers_Bits_Definition
  • TIM1_Registers_Reset_Value
  • TIM1_Registers_Bits_Definition
  • TIM2_Registers_Reset_Value
  • TIM2_Registers_Bits_Definition
  • TIM3_Registers_Reset_Value
  • TIM3_Registers_Bits_Definition
  • TIM4_Registers_Reset_Value
  • TIM4_Registers_Bits_Definition
  • TIM5_Registers_Reset_Value
  • TIM5_Registers_Bits_Definition
  • TIM6_Registers_Reset_Value
  • TIM6_Registers_Bits_Definition
  • I2C_Registers_Reset_Value
  • I2C_Registers_Bits_Definition
  • ITC_Registers_Reset_Value
  • CPU_Registers_Bits_Definition
  • EXTI_Registers_Reset_Value
  • EXTI_Registers_Bits_Definition
  • FLASH_Registers_Reset_Value
  • FLASH_Registers_Bits_Definition
  • IWDG_Registers_Reset_Value
  • WWDG_Registers_Reset_Value
  • WWDG_Registers_Bits_Definition
  • RST_Registers_Bits_Definition
  • SPI_Registers_Reset_Value
  • SPI_Registers_Bits_Definition
  • UART1_Registers_Reset_Value
  • UART1_Registers_Bits_Definition
  • UART2_Registers_Reset_Value
  • UART2_Registers_Bits_Definition
  • UART3_Registers_Reset_Value
  • UART3_Registers_Bits_Definition
  • CAN_Registers_Bits_Definition
  • CAN_Registers_Reset_Value
  • CFG_Registers_Reset_Value
  • CFG_Registers_Bits_Definition
  • MAP_FILE_Base_Addresses
  • ADC1_Exported_Types
  • ADC1_Private_Macros
  • ADC1_Exported_Functions
  • ADC2_Exported_Types
  • ADC2_Private_Macros
  • ADC2_Exported_Functions
  • AWU_Exported_Types
  • AWU_Exported_Constants
  • AWU_Private_Macros
  • AWU_Exported_Functions
  • BEEP_Exported_Types
  • BEEP_Exported_Constants
  • BEEP_Private_Macros
  • BEEP_Exported_Functions
  • CAN_Exported_Types
  • CAN_Private_Macros
  • CAN_Exported_Functions
  • CLK_Exported_Types
  • CLK_Exported_Constants
  • CLK_Private_Macros
  • CLK_Exported_functions
  • EXTI_Exported_Types
  • EXTI_Private_Macros
  • EXTI_Exported_Functions
  • FLASH_Exported_Constants
  • FLASH_Exported_Types
  • FLASH_Private_Macros
  • FLASH_Exported_Functions
  • GPIO_Exported_Types
  • GPIO_Private_Macros
  • GPIO_Exported_Functions
  • I2C_Exported_Types
  • I2C_Exported_Constants
  • I2C_Private_Macros
  • I2C_Exported_Functions
  • ITC_Exported_Types
  • ITC_Exported_Constants
  • ITC_Private_Macros
  • ITC_Exported_Functions
  • TIM2_Exported_Functions
  • TIM5_Exported_Functions
  • IWDG_Public_Functions


STM8S/A Standard Peripherals Drivers: Related Pages

Related Pages
Here is a list of all related documentation pages:
  • STM8S/A Standard Peripheral's Drivers


STM8S/A Standard Peripherals Drivers: stdperiphlib_drivers.txt File Reference

  • File List
  • Globals
stdperiphlib_drivers.txt File Reference


STM8S/A Standard Peripherals Drivers: stm8s.h Source File

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
stm8s.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm8s.h
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all HW registers definitions and memory mapping.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Define to prevent recursive inclusion -------------------------------------*/
00029 #ifndef __STM8S_H
00030 #define __STM8S_H
00031
00032 /** @addtogroup STM8S_StdPeriph_Driver
00033   * @{
00034   */
00035
00036 /* Uncomment the line below according to the target STM8S or STM8A device used in your
00037    application. */
00038
00039  /* #define STM8S208 */      /*!< STM8S High density devices with CAN */
00040  /* #define STM8S207 */      /*!< STM8S High density devices without CAN */
00041  /* #define STM8S007 */      /*!< STM8S Value Line High density devices */
00042  /* #define STM8AF52Ax */    /*!< STM8A High density devices with CAN */
00043  /* #define STM8AF62Ax */    /*!< STM8A High density devices without CAN */
00044  /* #define STM8S105 */      /*!< STM8S Medium density devices */
00045  /* #define STM8S005 */      /*!< STM8S Value Line Medium density devices */
00046  /* #define STM8AF626x */    /*!< STM8A Medium density devices */
00047  /* #define STM8AF622x */    /*!< STM8A Low density devices */
00048  /* #define STM8S103 */      /*!< STM8S Low density devices */
00049  /* #define STM8S003 */      /*!< STM8S Value Line Low density devices */
00050  /* #define STM8S903 */      /*!< STM8S Low density devices */
00051  /* #define STM8S001 */      /*!< STM8S Value Line Low denisty devices */
00052
00053 /*   Tip: To avoid modifying this file each time you need to switch between these
00054         devices, you can define the device in your toolchain compiler preprocessor.
00055
00056   - High-Density STM8A devices are the STM8AF52xx STM8AF6269/8x/Ax,
00057     STM8AF51xx, and STM8AF6169/7x/8x/9x/Ax microcontrollers where the Flash memory
00058     density ranges between 32 to 128 Kbytes
00059   - Medium-Density STM8A devices are the STM8AF622x/4x, STM8AF6266/68,
00060     STM8AF612x/4x, and STM8AF6166/68 microcontrollers where the Flash memory
00061     density ranges between 8 to 32 Kbytes
00062   - High-Density STM8S devices are the STM8S207xx, STM8S007 and STM8S208xx microcontrollers
00063     where the Flash memory density ranges between 32 to 128 Kbytes.
00064   - Medium-Density STM8S devices are the STM8S105x and STM8S005 microcontrollers
00065     where the Flash memory density ranges between 16 to 32-Kbytes.
00066   - Low-Density STM8A devices are the STM8AF622x microcontrollers where the Flash
00067     density is 8 Kbytes.
00068   - Low-Density STM8S devices are the STM8S103xx, STM8S003, STM8S903xx and STM8S001 microcontrollers
00069     where the Flash density is 8 Kbytes. */
00070
00071 #if !defined (STM8S208) && !defined (STM8S207) && !defined (STM8S105) && \
00072     !defined (STM8S103) && !defined (STM8S903) && !defined (STM8AF52Ax) && \
00073     !defined (STM8AF62Ax) && !defined (STM8AF626x) && !defined (STM8S007) && \
00074     !defined (STM8S003)&& !defined (STM8S005) && !defined(STM8S001) && !defined (STM8AF622x)
00075  #error "Please select first the target STM8S/A device used in your application (in stm8s.h file)"
00076 #endif
00077
00078 /******************************************************************************/
00079 /*                   Library configuration section                            */
00080 /******************************************************************************/
00081 /* Check the used compiler */
00082 #if defined(__CSMC__)
00083  #define _COSMIC_
00084 #elif defined(__RCST7__)
00085  #define _RAISONANCE_
00086 #elif defined(__ICCSTM8__)
00087  #define _IAR_
00088 #else
00089  #error "Unsupported Compiler!"          /* Compiler defines not found */
00090 #endif
00091
00092 #if !defined  USE_STDPERIPH_DRIVER
00093 /* Comment the line below if you will not use the peripherals drivers.
00094    In this case, these drivers will not be included and the application code will be
00095    based on direct access to peripherals registers */
00096  #define USE_STDPERIPH_DRIVER
00097 #endif
00098
00099 /**
00100   * @brief  In the following line adjust the value of External High Speed oscillator (HSE)
00101    used in your application
00102
00103    Tip: To avoid modifying this file each time you need to use different HSE, you
00104         can define the HSE value in your toolchain compiler preprocessor.
00105   */
00106 #if !defined  HSE_Value
00107  #if defined (STM8S208) || defined (STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \
00108      defined (STM8AF62Ax) || defined (STM8AF622x)
00109   #define HSE_VALUE ((uint32_t)24000000) /* Value of the External oscillator in Hz*/
00110  #else
00111   #define HSE_VALUE ((uint32_t)16000000) /* Value of the External oscillator in Hz*/
00112  #endif /* STM8S208 || STM8S207 || STM8S007 || STM8AF62Ax || STM8AF52Ax || STM8AF622x */
00113 #endif /* HSE_Value */
00114
00115 /**
00116   * @brief  Definition of Device on-chip RC oscillator frequencies
00117   */
00118 #define HSI_VALUE   ((uint32_t)16000000) /*!< Typical Value of the HSI in Hz */
00119 #define LSI_VALUE   ((uint32_t)128000)   /*!< Typical Value of the LSI in Hz */
00120
00121 #ifdef _COSMIC_
00122  #define FAR  @far
00123  #define NEAR @near
00124  #define TINY @tiny
00125  #define EEPROM @eeprom
00126  #define CONST  const
00127 #elif defined (_RAISONANCE_) /* __RCST7__ */
00128  #define FAR  far
00129  #define NEAR data
00130  #define TINY page0
00131  #define EEPROM eeprom
00132  #define CONST  code
00133  #if defined (STM8S208) || defined (STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \
00134      defined (STM8AF62Ax)
00135    /*!< Used with memory Models for code higher than 64K */
00136   #define MEMCPY fmemcpy
00137  #else /* STM8S903, STM8S103, STM8S001, STM8S003, STM8S105, STM8AF626x, STM8AF622x */
00138   /*!< Used with memory Models for code less than 64K */
00139   #define MEMCPY memcpy
00140  #endif /* STM8S208 or STM8S207 or STM8S007 or STM8AF62Ax or STM8AF52Ax */
00141 #else /*_IAR_*/
00142  #define FAR  __far
00143  #define NEAR __near
00144  #define TINY __tiny
00145  #define EEPROM __eeprom
00146  #define CONST  const
00147 #endif /* __CSMC__ */
00148
00149 /* For FLASH routines, select whether pointer will be declared as near (2 bytes,
00150    to handle code smaller than 64KB) or far (3 bytes, to handle code larger
00151    than 64K) */
00152
00153 #if defined (STM8S105) || defined (STM8S005) || defined (STM8S103) || defined (STM8S003) || \
00154     defined (STM8S001) || defined (STM8S903) || defined (STM8AF626x) || defined (STM8AF622x)
00155 /*!< Used with memory Models for code smaller than 64K */
00156  #define PointerAttr NEAR
00157  #define MemoryAddressCast uint16_t
00158 #else /* STM8S208 or STM8S207 or STM8AF62Ax or STM8AF52Ax */
00159 /*!< Used with memory Models for code higher than 64K */
00160  #define PointerAttr FAR
00161  #define MemoryAddressCast uint32_t
00162 #endif /* STM8S105 or STM8S103 or STM8S003 or STM8S001 or STM8S903 or STM8AF626x or STM8AF622x */
00163
00164 /* Uncomment the line below to enable the FLASH functions execution from RAM */
00165 #if !defined (RAM_EXECUTION)
00166 /* #define RAM_EXECUTION  (1) */
00167 #endif /* RAM_EXECUTION */
00168
00169 #ifdef RAM_EXECUTION
00170  #ifdef _COSMIC_
00171    #define IN_RAM(a) a
00172  #elif defined (_RAISONANCE_) /* __RCST7__ */
00173    #define IN_RAM(a) a inram
00174  #else /*_IAR_*/
00175   #define IN_RAM(a) __ramfunc a
00176  #endif /* _COSMIC_ */
00177 #else
00178   #define IN_RAM(a) a
00179 #endif /* RAM_EXECUTION */
00180
00181 /*!< [31:16] STM8S Standard Peripheral Library main version V2.3.0*/
00182 #define __STM8S_STDPERIPH_VERSION_MAIN   ((uint8_t)0x02) /*!< [31:24] main version */
00183 #define __STM8S_STDPERIPH_VERSION_SUB1   ((uint8_t)0x03) /*!< [23:16] sub1 version */
00184 #define __STM8S_STDPERIPH_VERSION_SUB2   ((uint8_t)0x00) /*!< [15:8]  sub2 version */
00185 #define __STM8S_STDPERIPH_VERSION_RC     ((uint8_t)0x00) /*!< [7:0]  release candidate */
00186 #define __STM8S_STDPERIPH_VERSION       ( (__STM8S_STDPERIPH_VERSION_MAIN << 24)\
00187                                           |(__STM8S_STDPERIPH_VERSION_SUB1 << 16)\
00188                                           |(__STM8S_STDPERIPH_VERSION_SUB2 << 8)\
00189                                           |(__STM8S_STDPERIPH_VERSION_RC))
00190
00191 /******************************************************************************/
00192
00193 /* Includes ------------------------------------------------------------------*/
00194
00195 /* Exported types and constants ----------------------------------------------*/
00196
00197 /** @addtogroup Exported_types
00198   * @{
00199   */
00200
00201 /**
00202  * IO definitions
00203  *
00204  * define access restrictions to peripheral registers
00205  */
00206 #define     __I     volatile const   /*!< defines 'read only' permissions     */
00207 #define     __O     volatile         /*!< defines 'write only' permissions    */
00208 #define     __IO    volatile         /*!< defines 'read / write' permissions  */
00209
00210 /*!< Signed integer types  */
00211 typedef   signed char     int8_t;
00212 typedef   signed short    int16_t;
00213 typedef   signed long     int32_t;
00214
00215 /*!< Unsigned integer types  */
00216 typedef unsigned char     uint8_t;
00217 typedef unsigned short    uint16_t;
00218 typedef unsigned long     uint32_t;
00219
00220 /*!< STM8 Standard Peripheral Library old types (maintained for legacy purpose) */
00221
00222 typedef int32_t  s32;
00223 typedef int16_t s16;
00224 typedef int8_t  s8;
00225
00226 typedef uint32_t  u32;
00227 typedef uint16_t u16;
00228 typedef uint8_t  u8;
00229
00230
00231 typedef enum {FALSE = 0, TRUE = !FALSE} bool;
00232
00233 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, BitStatus, BitAction;
00234
00235 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
00236 #define IS_FUNCTIONALSTATE_OK(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
00237
00238 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
00239
00240 #define U8_MAX     (255)
00241 #define S8_MAX     (127)
00242 #define S8_MIN     (-128)
00243 #define U16_MAX    (65535u)
00244 #define S16_MAX    (32767)
00245 #define S16_MIN    (-32768)
00246 #define U32_MAX    (4294967295uL)
00247 #define S32_MAX    (2147483647)
00248 #define S32_MIN    (-2147483648uL)
00249
00250 /**
00251   * @}
00252   */
00253
00254 /** @addtogroup MAP_FILE_Exported_Types_and_Constants
00255   * @{
00256   */
00257
00258 /******************************************************************************/
00259 /*                          IP registers structures                           */
00260 /******************************************************************************/
00261
00262 /**
00263   * @brief  General Purpose I/Os (GPIO)
00264   */
00265 typedef struct GPIO_struct
00266 {
00267   __IO uint8_t ODR; /*!< Output Data Register */
00268   __IO uint8_t IDR; /*!< Input Data Register */
00269   __IO uint8_t DDR; /*!< Data Direction Register */
00270   __IO uint8_t CR1; /*!< Configuration Register 1 */
00271   __IO uint8_t CR2; /*!< Configuration Register 2 */
00272 }
00273 GPIO_TypeDef;
00274
00275 /**
00276   * @}
00277   */
00278
00279 /** @addtogroup GPIO_Registers_Reset_Value
00280   * @{
00281   */
00282
00283 #define GPIO_ODR_RESET_VALUE ((uint8_t)0x00)
00284 #define GPIO_DDR_RESET_VALUE ((uint8_t)0x00)
00285 #define GPIO_CR1_RESET_VALUE ((uint8_t)0x00)
00286 #define GPIO_CR2_RESET_VALUE ((uint8_t)0x00)
00287
00288 /**
00289   * @}
00290   */
00291
00292 /*----------------------------------------------------------------------------*/
00293 #if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \
00294     defined(STM8S001) || defined(STM8S903) || defined(STM8AF626x) || defined(STM8AF622x)
00295 /**
00296   * @brief  Analog to Digital Converter (ADC1)
00297   */
00298  typedef struct ADC1_struct
00299  {
00300   __IO uint8_t DB0RH;         /*!< ADC1 Data Buffer Register (MSB)  */
00301   __IO uint8_t DB0RL;         /*!< ADC1 Data Buffer Register (LSB)  */
00302   __IO uint8_t DB1RH;         /*!< ADC1 Data Buffer Register (MSB)  */
00303   __IO uint8_t DB1RL;         /*!< ADC1 Data Buffer Register (LSB)  */
00304   __IO uint8_t DB2RH;         /*!< ADC1 Data Buffer Register (MSB)  */
00305   __IO uint8_t DB2RL;         /*!< ADC1 Data Buffer Register (LSB)  */
00306   __IO uint8_t DB3RH;         /*!< ADC1 Data Buffer Register (MSB)  */
00307   __IO uint8_t DB3RL;         /*!< ADC1 Data Buffer Register (LSB)  */
00308   __IO uint8_t DB4RH;         /*!< ADC1 Data Buffer Register (MSB)  */
00309   __IO uint8_t DB4RL;         /*!< ADC1 Data Buffer Register (LSB)  */
00310   __IO uint8_t DB5RH;         /*!< ADC1 Data Buffer Register (MSB)  */
00311   __IO uint8_t DB5RL;         /*!< ADC1 Data Buffer Register (LSB)  */
00312   __IO uint8_t DB6RH;         /*!< ADC1 Data Buffer Register (MSB)  */
00313   __IO uint8_t DB6RL;         /*!< ADC1 Data Buffer Register (LSB)  */
00314   __IO uint8_t DB7RH;         /*!< ADC1 Data Buffer Register (MSB)  */
00315   __IO uint8_t DB7RL;         /*!< ADC1 Data Buffer Register (LSB)  */
00316   __IO uint8_t DB8RH;         /*!< ADC1 Data Buffer Register (MSB)  */
00317   __IO uint8_t DB8RL;         /*!< ADC1 Data Buffer Register (LSB)  */
00318   __IO uint8_t DB9RH;         /*!< ADC1 Data Buffer Register (MSB)  */
00319   __IO uint8_t DB9RL;         /*!< ADC1 Data Buffer Register (LSB)  */
00320   uint8_t RESERVED[12];       /*!< Reserved byte */
00321   __IO uint8_t CSR;           /*!< ADC1 control status register */
00322   __IO uint8_t CR1;           /*!< ADC1 configuration register 1 */
00323   __IO uint8_t CR2;           /*!< ADC1 configuration register 2 */
00324   __IO uint8_t CR3;           /*!< ADC1 configuration register 3  */
00325   __IO uint8_t DRH;           /*!< ADC1 Data high */
00326   __IO uint8_t DRL;           /*!< ADC1 Data low */
00327   __IO uint8_t TDRH;          /*!< ADC1 Schmitt trigger disable register high */
00328   __IO uint8_t TDRL;          /*!< ADC1 Schmitt trigger disable register low */
00329   __IO uint8_t HTRH;          /*!< ADC1 high threshold register High*/
00330   __IO uint8_t HTRL;          /*!< ADC1 high threshold register Low*/
00331   __IO uint8_t LTRH;          /*!< ADC1 low threshold register high */
00332   __IO uint8_t LTRL;          /*!< ADC1 low threshold register low */
00333   __IO uint8_t AWSRH;         /*!< ADC1 watchdog status register high */
00334   __IO uint8_t AWSRL;         /*!< ADC1 watchdog status register low */
00335   __IO uint8_t AWCRH;         /*!< ADC1 watchdog control register high */
00336   __IO uint8_t AWCRL;         /*!< ADC1 watchdog control register low */
00337  }
00338  ADC1_TypeDef;
00339
00340 /** @addtogroup ADC1_Registers_Reset_Value
00341   * @{
00342   */
00343  #define  ADC1_CSR_RESET_VALUE    ((uint8_t)0x00)
00344  #define  ADC1_CR1_RESET_VALUE    ((uint8_t)0x00)
00345  #define  ADC1_CR2_RESET_VALUE    ((uint8_t)0x00)
00346  #define  ADC1_CR3_RESET_VALUE    ((uint8_t)0x00)
00347  #define  ADC1_TDRL_RESET_VALUE   ((uint8_t)0x00)
00348  #define  ADC1_TDRH_RESET_VALUE   ((uint8_t)0x00)
00349  #define  ADC1_HTRL_RESET_VALUE   ((uint8_t)0x03)
00350  #define  ADC1_HTRH_RESET_VALUE   ((uint8_t)0xFF)
00351  #define  ADC1_LTRH_RESET_VALUE   ((uint8_t)0x00)
00352  #define  ADC1_LTRL_RESET_VALUE   ((uint8_t)0x00)
00353  #define  ADC1_AWCRH_RESET_VALUE  ((uint8_t)0x00)
00354  #define  ADC1_AWCRL_RESET_VALUE  ((uint8_t)0x00)
00355 /**
00356   * @}
00357   */
00358
00359 /** @addtogroup ADC1_Registers_Bits_Definition
00360   * @{
00361   */
00362  #define ADC1_CSR_EOC     ((uint8_t)0x80) /*!< End of Conversion mask */
00363  #define ADC1_CSR_AWD     ((uint8_t)0x40) /*!< Analog Watch Dog Status mask */
00364  #define ADC1_CSR_EOCIE   ((uint8_t)0x20) /*!< Interrupt Enable for EOC mask */
00365  #define ADC1_CSR_AWDIE   ((uint8_t)0x10) /*!< Analog Watchdog interrupt enable mask */
00366  #define ADC1_CSR_CH      ((uint8_t)0x0F) /*!< Channel selection bits mask */
00367
00368  #define ADC1_CR1_SPSEL   ((uint8_t)0x70) /*!< Prescaler selection mask */
00369  #define ADC1_CR1_CONT    ((uint8_t)0x02) /*!< Continuous conversion mask */
00370  #define ADC1_CR1_ADON    ((uint8_t)0x01) /*!< A/D Converter on/off mask */
00371
00372  #define ADC1_CR2_EXTTRIG ((uint8_t)0x40) /*!< External trigger enable mask */
00373  #define ADC1_CR2_EXTSEL  ((uint8_t)0x30) /*!< External event selection mask */
00374  #define ADC1_CR2_ALIGN   ((uint8_t)0x08) /*!< Data Alignment mask */
00375  #define ADC1_CR2_SCAN    ((uint8_t)0x02) /*!< Scan mode mask */
00376
00377  #define ADC1_CR3_DBUF    ((uint8_t)0x80) /*!< Data Buffer Enable mask */
00378  #define ADC1_CR3_OVR     ((uint8_t)0x40) /*!< Overrun Status Flag mask */
00379
00380 #endif /* (STM8S105) ||(STM8S103) || (STM8S005) ||(STM8S003) || (STM8S001) || (STM8S903) || (STM8AF626x) || (STM8AF622x) */
00381 /**
00382   * @}
00383   */
00384
00385 /*----------------------------------------------------------------------------*/
00386 /**
00387   * @brief  Analog to Digital Converter (ADC2)
00388   */
00389 #if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || defined (STM8AF62Ax)
00390  typedef struct ADC2_struct
00391  {
00392   __IO uint8_t CSR;        /*!< ADC2 control status register */
00393   __IO uint8_t CR1;        /*!< ADC2 configuration register 1 */
00394   __IO uint8_t CR2;        /*!< ADC2 configuration register 2 */
00395   uint8_t RESERVED;        /*!< Reserved byte */
00396   __IO uint8_t DRH;        /*!< ADC2 Data high */
00397   __IO uint8_t DRL;        /*!< ADC2 Data low */
00398   __IO uint8_t TDRH;       /*!< ADC2 Schmitt trigger disable register high  */
00399   __IO uint8_t TDRL;       /*!< ADC2 Schmitt trigger disable register low */
00400  }
00401  ADC2_TypeDef;
00402
00403 /** @addtogroup ADC2_Registers_Reset_Value
00404   * @{
00405   */
00406  #define  ADC2_CSR_RESET_VALUE  ((uint8_t)0x00)
00407  #define  ADC2_CR1_RESET_VALUE  ((uint8_t)0x00)
00408  #define  ADC2_CR2_RESET_VALUE  ((uint8_t)0x00)
00409  #define  ADC2_TDRL_RESET_VALUE ((uint8_t)0x00)
00410  #define  ADC2_TDRH_RESET_VALUE ((uint8_t)0x00)
00411 /**
00412   * @}
00413   */
00414
00415 /** @addtogroup ADC2_Registers_Bits_Definition
00416   * @{
00417   */
00418  #define ADC2_CSR_EOC     ((uint8_t)0x80) /*!< End of Conversion mask */
00419  #define ADC2_CSR_EOCIE   ((uint8_t)0x20) /*!< Interrupt Enable for EOC mask */
00420  #define ADC2_CSR_CH      ((uint8_t)0x0F) /*!< Channel selection bits mask */
00421
00422  #define ADC2_CR1_SPSEL   ((uint8_t)0x70) /*!< Prescaler selection mask */
00423  #define ADC2_CR1_CONT    ((uint8_t)0x02) /*!< Continuous conversion mask */
00424  #define ADC2_CR1_ADON    ((uint8_t)0x01) /*!< A/D Converter on/off mask */
00425
00426  #define ADC2_CR2_EXTTRIG ((uint8_t)0x40) /*!< External trigger enable mask */
00427  #define ADC2_CR2_EXTSEL  ((uint8_t)0x30) /*!< External event selection mask */
00428  #define ADC2_CR2_ALIGN   ((uint8_t)0x08) /*!< Data Alignment mask */
00429
00430 #endif /* (STM8S208) ||(STM8S207) || defined (STM8S007) || (STM8AF62Ax) || (STM8AF52Ax) */
00431 /**
00432   * @}
00433   */
00434
00435 /*----------------------------------------------------------------------------*/
00436
00437 /**
00438   * @brief  Auto Wake Up (AWU) peripheral registers.
00439   */
00440 typedef struct AWU_struct
00441 {
00442   __IO uint8_t CSR; /*!< AWU Control status register */
00443   __IO uint8_t APR; /*!< AWU Asynchronous prescaler buffer */
00444   __IO uint8_t TBR; /*!< AWU Time base selection register */
00445 }
00446 AWU_TypeDef;
00447
00448 /** @addtogroup AWU_Registers_Reset_Value
00449   * @{
00450   */
00451 #define AWU_CSR_RESET_VALUE ((uint8_t)0x00)
00452 #define AWU_APR_RESET_VALUE ((uint8_t)0x3F)
00453 #define AWU_TBR_RESET_VALUE ((uint8_t)0x00)
00454
00455 /**
00456   * @}
00457   */
00458
00459 /** @addtogroup AWU_Registers_Bits_Definition
00460   * @{
00461   */
00462
00463 #define AWU_CSR_AWUF    ((uint8_t)0x20) /*!< Interrupt flag mask */
00464 #define AWU_CSR_AWUEN   ((uint8_t)0x10) /*!< Auto Wake-up enable mask */
00465 #define AWU_CSR_MSR     ((uint8_t)0x01) /*!< LSI Measurement enable mask */
00466
00467 #define AWU_APR_APR     ((uint8_t)0x3F) /*!< Asynchronous Prescaler divider mask */
00468
00469 #define AWU_TBR_AWUTB   ((uint8_t)0x0F) /*!< Timebase selection mask */
00470
00471 /**
00472   * @}
00473   */
00474
00475 /*----------------------------------------------------------------------------*/
00476 /**
00477   * @brief  Beeper (BEEP) peripheral registers.
00478   */
00479
00480 typedef struct BEEP_struct
00481 {
00482   __IO uint8_t CSR; /*!< BEEP Control status register */
00483 }
00484 BEEP_TypeDef;
00485
00486 /** @addtogroup BEEP_Registers_Reset_Value
00487   * @{
00488   */
00489 #define BEEP_CSR_RESET_VALUE ((uint8_t)0x1F)
00490 /**
00491   * @}
00492   */
00493
00494 /** @addtogroup BEEP_Registers_Bits_Definition
00495   * @{
00496   */
00497 #define BEEP_CSR_BEEPSEL ((uint8_t)0xC0) /*!< Beeper frequency selection mask */
00498 #define BEEP_CSR_BEEPEN  ((uint8_t)0x20) /*!< Beeper enable mask */
00499 #define BEEP_CSR_BEEPDIV ((uint8_t)0x1F) /*!< Beeper Divider prescalar mask */
00500 /**
00501   * @}
00502   */
00503
00504 /*----------------------------------------------------------------------------*/
00505 /**
00506   * @brief  Clock Controller (CLK)
00507   */
00508 typedef struct CLK_struct
00509 {
00510   __IO uint8_t ICKR;     /*!< Internal Clocks Control Register */
00511   __IO uint8_t ECKR;     /*!< External Clocks Control Register */
00512   uint8_t RESERVED;      /*!< Reserved byte */
00513   __IO uint8_t CMSR;     /*!< Clock Master Status Register */
00514   __IO uint8_t SWR;      /*!< Clock Master Switch Register */
00515   __IO uint8_t SWCR;     /*!< Switch Control Register */
00516   __IO uint8_t CKDIVR;   /*!< Clock Divider Register */
00517   __IO uint8_t PCKENR1;  /*!< Peripheral Clock Gating Register 1 */
00518   __IO uint8_t CSSR;     /*!< Clock Security System Register */
00519   __IO uint8_t CCOR;     /*!< Configurable Clock Output Register */
00520   __IO uint8_t PCKENR2;  /*!< Peripheral Clock Gating Register 2 */
00521   uint8_t RESERVED1;     /*!< Reserved byte */
00522   __IO uint8_t HSITRIMR; /*!< HSI Calibration Trimmer Register */
00523   __IO uint8_t SWIMCCR;  /*!< SWIM clock control register */
00524 }
00525 CLK_TypeDef;
00526
00527 /** @addtogroup CLK_Registers_Reset_Value
00528   * @{
00529   */
00530
00531 #define CLK_ICKR_RESET_VALUE     ((uint8_t)0x01)
00532 #define CLK_ECKR_RESET_VALUE     ((uint8_t)0x00)
00533 #define CLK_CMSR_RESET_VALUE     ((uint8_t)0xE1)
00534 #define CLK_SWR_RESET_VALUE      ((uint8_t)0xE1)
00535 #define CLK_SWCR_RESET_VALUE     ((uint8_t)0x00)
00536 #define CLK_CKDIVR_RESET_VALUE   ((uint8_t)0x18)
00537 #define CLK_PCKENR1_RESET_VALUE  ((uint8_t)0xFF)
00538 #define CLK_PCKENR2_RESET_VALUE  ((uint8_t)0xFF)
00539 #define CLK_CSSR_RESET_VALUE     ((uint8_t)0x00)
00540 #define CLK_CCOR_RESET_VALUE     ((uint8_t)0x00)
00541 #define CLK_HSITRIMR_RESET_VALUE ((uint8_t)0x00)
00542 #define CLK_SWIMCCR_RESET_VALUE  ((uint8_t)0x00)
00543
00544 /**
00545   * @}
00546   */
00547
00548 /** @addtogroup CLK_Registers_Bits_Definition
00549   * @{
00550   */
00551 #define CLK_ICKR_SWUAH       ((uint8_t)0x20) /*!< Slow Wake-up from Active Halt/Halt modes */
00552 #define CLK_ICKR_LSIRDY      ((uint8_t)0x10) /*!< Low speed internal oscillator ready */
00553 #define CLK_ICKR_LSIEN       ((uint8_t)0x08) /*!< Low speed internal RC oscillator enable */
00554 #define CLK_ICKR_FHWU        ((uint8_t)0x04) /*!< Fast Wake-up from Active Halt/Halt mode */
00555 #define CLK_ICKR_HSIRDY      ((uint8_t)0x02) /*!< High speed internal RC oscillator ready */
00556 #define CLK_ICKR_HSIEN       ((uint8_t)0x01) /*!< High speed internal RC oscillator enable */
00557
00558 #define CLK_ECKR_HSERDY      ((uint8_t)0x02) /*!< High speed external crystal oscillator ready */
00559 #define CLK_ECKR_HSEEN       ((uint8_t)0x01) /*!< High speed external crystal oscillator enable */
00560
00561 #define CLK_CMSR_CKM         ((uint8_t)0xFF) /*!< Clock master status bits */
00562
00563 #define CLK_SWR_SWI          ((uint8_t)0xFF) /*!< Clock master selection bits */
00564
00565 #define CLK_SWCR_SWIF        ((uint8_t)0x08) /*!< Clock switch interrupt flag */
00566 #define CLK_SWCR_SWIEN       ((uint8_t)0x04) /*!< Clock switch interrupt enable */
00567 #define CLK_SWCR_SWEN        ((uint8_t)0x02) /*!< Switch start/stop */
00568 #define CLK_SWCR_SWBSY       ((uint8_t)0x01) /*!< Switch busy flag*/
00569
00570 #define CLK_CKDIVR_HSIDIV    ((uint8_t)0x18) /*!< High speed internal clock prescaler */
00571 #define CLK_CKDIVR_CPUDIV    ((uint8_t)0x07) /*!< CPU clock prescaler */
00572
00573 #define CLK_PCKENR1_TIM1     ((uint8_t)0x80) /*!< Timer 1 clock enable */
00574 #define CLK_PCKENR1_TIM3     ((uint8_t)0x40) /*!< Timer 3 clock enable */
00575 #define CLK_PCKENR1_TIM2     ((uint8_t)0x20) /*!< Timer 2 clock enable */
00576 #define CLK_PCKENR1_TIM5     ((uint8_t)0x20) /*!< Timer 5 clock enable */
00577 #define CLK_PCKENR1_TIM4     ((uint8_t)0x10) /*!< Timer 4 clock enable */
00578 #define CLK_PCKENR1_TIM6     ((uint8_t)0x10) /*!< Timer 6 clock enable */
00579 #define CLK_PCKENR1_UART3    ((uint8_t)0x08) /*!< UART3 clock enable */
00580 #define CLK_PCKENR1_UART2    ((uint8_t)0x08) /*!< UART2 clock enable */
00581 #define CLK_PCKENR1_UART1    ((uint8_t)0x04) /*!< UART1 clock enable */
00582 #define CLK_PCKENR1_SPI      ((uint8_t)0x02) /*!< SPI clock enable */
00583 #define CLK_PCKENR1_I2C      ((uint8_t)0x01) /*!< I2C clock enable */
00584
00585 #define CLK_PCKENR2_CAN      ((uint8_t)0x80) /*!< CAN clock enable */
00586 #define CLK_PCKENR2_ADC      ((uint8_t)0x08) /*!< ADC clock enable */
00587 #define CLK_PCKENR2_AWU      ((uint8_t)0x04) /*!< AWU clock enable */
00588
00589 #define CLK_CSSR_CSSD        ((uint8_t)0x08) /*!< Clock security system detection */
00590 #define CLK_CSSR_CSSDIE      ((uint8_t)0x04) /*!< Clock security system detection interrupt enable */
00591 #define CLK_CSSR_AUX         ((uint8_t)0x02) /*!< Auxiliary oscillator connected to master clock */
00592 #define CLK_CSSR_CSSEN       ((uint8_t)0x01) /*!< Clock security system enable */
00593
00594 #define CLK_CCOR_CCOBSY      ((uint8_t)0x40) /*!< Configurable clock output busy */
00595 #define CLK_CCOR_CCORDY      ((uint8_t)0x20) /*!< Configurable clock output ready */
00596 #define CLK_CCOR_CCOSEL      ((uint8_t)0x1E) /*!< Configurable clock output selection */
00597 #define CLK_CCOR_CCOEN       ((uint8_t)0x01) /*!< Configurable clock output enable */
00598
00599 #define CLK_HSITRIMR_HSITRIM ((uint8_t)0x07) /*!< High speed internal oscillator trimmer */
00600
00601 #define CLK_SWIMCCR_SWIMDIV  ((uint8_t)0x01) /*!< SWIM Clock Dividing Factor */
00602
00603 /**
00604   * @}
00605   */
00606
00607 /*----------------------------------------------------------------------------*/
00608 /**
00609   * @brief  16-bit timer with complementary PWM outputs (TIM1)
00610   */
00611
00612 typedef struct TIM1_struct
00613 {
00614   __IO uint8_t CR1;   /*!< control register 1 */
00615   __IO uint8_t CR2;   /*!< control register 2 */
00616   __IO uint8_t SMCR;  /*!< Synchro mode control register */
00617   __IO uint8_t ETR;   /*!< external trigger register */
00618   __IO uint8_t IER;   /*!< interrupt enable register*/
00619   __IO uint8_t SR1;   /*!< status register 1 */
00620   __IO uint8_t SR2;   /*!< status register 2 */
00621   __IO uint8_t EGR;   /*!< event generation register */
00622   __IO uint8_t CCMR1; /*!< CC mode register 1 */
00623   __IO uint8_t CCMR2; /*!< CC mode register 2 */
00624   __IO uint8_t CCMR3; /*!< CC mode register 3 */
00625   __IO uint8_t CCMR4; /*!< CC mode register 4 */
00626   __IO uint8_t CCER1; /*!< CC enable register 1 */
00627   __IO uint8_t CCER2; /*!< CC enable register 2 */
00628   __IO uint8_t CNTRH; /*!< counter high */
00629   __IO uint8_t CNTRL; /*!< counter low */
00630   __IO uint8_t PSCRH; /*!< prescaler high */
00631   __IO uint8_t PSCRL; /*!< prescaler low */
00632   __IO uint8_t ARRH;  /*!< auto-reload register high */
00633   __IO uint8_t ARRL;  /*!< auto-reload register low */
00634   __IO uint8_t RCR;   /*!< Repetition Counter register */
00635   __IO uint8_t CCR1H; /*!< capture/compare register 1 high */
00636   __IO uint8_t CCR1L; /*!< capture/compare register 1 low */
00637   __IO uint8_t CCR2H; /*!< capture/compare register 2 high */
00638   __IO uint8_t CCR2L; /*!< capture/compare register 2 low */
00639   __IO uint8_t CCR3H; /*!< capture/compare register 3 high */
00640   __IO uint8_t CCR3L; /*!< capture/compare register 3 low */
00641   __IO uint8_t CCR4H; /*!< capture/compare register 3 high */
00642   __IO uint8_t CCR4L; /*!< capture/compare register 3 low */
00643   __IO uint8_t BKR;   /*!< Break Register */
00644   __IO uint8_t DTR;   /*!< dead-time register */
00645   __IO uint8_t OISR;  /*!< Output idle register */
00646 }
00647 TIM1_TypeDef;
00648
00649 /** @addtogroup TIM1_Registers_Reset_Value
00650   * @{
00651   */
00652
00653 #define TIM1_CR1_RESET_VALUE   ((uint8_t)0x00)
00654 #define TIM1_CR2_RESET_VALUE   ((uint8_t)0x00)
00655 #define TIM1_SMCR_RESET_VALUE  ((uint8_t)0x00)
00656 #define TIM1_ETR_RESET_VALUE   ((uint8_t)0x00)
00657 #define TIM1_IER_RESET_VALUE   ((uint8_t)0x00)
00658 #define TIM1_SR1_RESET_VALUE   ((uint8_t)0x00)
00659 #define TIM1_SR2_RESET_VALUE   ((uint8_t)0x00)
00660 #define TIM1_EGR_RESET_VALUE   ((uint8_t)0x00)
00661 #define TIM1_CCMR1_RESET_VALUE ((uint8_t)0x00)
00662 #define TIM1_CCMR2_RESET_VALUE ((uint8_t)0x00)
00663 #define TIM1_CCMR3_RESET_VALUE ((uint8_t)0x00)
00664 #define TIM1_CCMR4_RESET_VALUE ((uint8_t)0x00)
00665 #define TIM1_CCER1_RESET_VALUE ((uint8_t)0x00)
00666 #define TIM1_CCER2_RESET_VALUE ((uint8_t)0x00)
00667 #define TIM1_CNTRH_RESET_VALUE ((uint8_t)0x00)
00668 #define TIM1_CNTRL_RESET_VALUE ((uint8_t)0x00)
00669 #define TIM1_PSCRH_RESET_VALUE ((uint8_t)0x00)
00670 #define TIM1_PSCRL_RESET_VALUE ((uint8_t)0x00)
00671 #define TIM1_ARRH_RESET_VALUE  ((uint8_t)0xFF)
00672 #define TIM1_ARRL_RESET_VALUE  ((uint8_t)0xFF)
00673 #define TIM1_RCR_RESET_VALUE   ((uint8_t)0x00)
00674 #define TIM1_CCR1H_RESET_VALUE ((uint8_t)0x00)
00675 #define TIM1_CCR1L_RESET_VALUE ((uint8_t)0x00)
00676 #define TIM1_CCR2H_RESET_VALUE ((uint8_t)0x00)
00677 #define TIM1_CCR2L_RESET_VALUE ((uint8_t)0x00)
00678 #define TIM1_CCR3H_RESET_VALUE ((uint8_t)0x00)
00679 #define TIM1_CCR3L_RESET_VALUE ((uint8_t)0x00)
00680 #define TIM1_CCR4H_RESET_VALUE ((uint8_t)0x00)
00681 #define TIM1_CCR4L_RESET_VALUE ((uint8_t)0x00)
00682 #define TIM1_BKR_RESET_VALUE   ((uint8_t)0x00)
00683 #define TIM1_DTR_RESET_VALUE   ((uint8_t)0x00)
00684 #define TIM1_OISR_RESET_VALUE  ((uint8_t)0x00)
00685
00686 /**
00687   * @}
00688   */
00689
00690 /** @addtogroup TIM1_Registers_Bits_Definition
00691   * @{
00692   */
00693 /* CR1*/
00694 #define TIM1_CR1_ARPE    ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */
00695 #define TIM1_CR1_CMS     ((uint8_t)0x60) /*!< Center-aligned Mode Selection mask. */
00696 #define TIM1_CR1_DIR     ((uint8_t)0x10) /*!< Direction mask. */
00697 #define TIM1_CR1_OPM     ((uint8_t)0x08) /*!< One Pulse Mode mask. */
00698 #define TIM1_CR1_URS     ((uint8_t)0x04) /*!< Update Request Source mask. */
00699 #define TIM1_CR1_UDIS    ((uint8_t)0x02) /*!< Update DIsable mask. */
00700 #define TIM1_CR1_CEN     ((uint8_t)0x01) /*!< Counter Enable mask. */
00701 /* CR2*/
00702 #define TIM1_CR2_TI1S    ((uint8_t)0x80) /*!< TI1S Selection mask. */
00703 #define TIM1_CR2_MMS     ((uint8_t)0x70) /*!< MMS Selection mask. */
00704 #define TIM1_CR2_COMS    ((uint8_t)0x04) /*!< Capture/Compare Control Update Selection mask. */
00705 #define TIM1_CR2_CCPC    ((uint8_t)0x01) /*!< Capture/Compare Preloaded Control mask. */
00706 /* SMCR*/
00707 #define TIM1_SMCR_MSM    ((uint8_t)0x80) /*!< Master/Slave Mode mask. */
00708 #define TIM1_SMCR_TS     ((uint8_t)0x70) /*!< Trigger Selection mask. */
00709 #define TIM1_SMCR_SMS    ((uint8_t)0x07) /*!< Slave Mode Selection mask. */
00710 /*ETR*/
00711 #define TIM1_ETR_ETP     ((uint8_t)0x80) /*!< External Trigger Polarity mask. */
00712 #define TIM1_ETR_ECE     ((uint8_t)0x40)/*!< External Clock mask. */
00713 #define TIM1_ETR_ETPS    ((uint8_t)0x30) /*!< External Trigger Prescaler mask. */
00714 #define TIM1_ETR_ETF     ((uint8_t)0x0F) /*!< External Trigger Filter mask. */
00715 /*IER*/
00716 #define TIM1_IER_BIE     ((uint8_t)0x80) /*!< Break Interrupt Enable mask. */
00717 #define TIM1_IER_TIE     ((uint8_t)0x40) /*!< Trigger Interrupt Enable mask. */
00718 #define TIM1_IER_COMIE   ((uint8_t)0x20) /*!<  Commutation Interrupt Enable mask.*/
00719 #define TIM1_IER_CC4IE   ((uint8_t)0x10) /*!< Capture/Compare 4 Interrupt Enable mask. */
00720 #define TIM1_IER_CC3IE   ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */
00721 #define TIM1_IER_CC2IE   ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */
00722 #define TIM1_IER_CC1IE   ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */
00723 #define TIM1_IER_UIE     ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */
00724 /*SR1*/
00725 #define TIM1_SR1_BIF     ((uint8_t)0x80) /*!< Break Interrupt Flag mask. */
00726 #define TIM1_SR1_TIF     ((uint8_t)0x40) /*!< Trigger Interrupt Flag mask. */
00727 #define TIM1_SR1_COMIF   ((uint8_t)0x20) /*!< Commutation Interrupt Flag mask. */
00728 #define TIM1_SR1_CC4IF   ((uint8_t)0x10) /*!< Capture/Compare 4 Interrupt Flag mask. */
00729 #define TIM1_SR1_CC3IF   ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */
00730 #define TIM1_SR1_CC2IF   ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */
00731 #define TIM1_SR1_CC1IF   ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */
00732 #define TIM1_SR1_UIF     ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */
00733 /*SR2*/
00734 #define TIM1_SR2_CC4OF   ((uint8_t)0x10) /*!< Capture/Compare 4 Overcapture Flag mask. */
00735 #define TIM1_SR2_CC3OF   ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */
00736 #define TIM1_SR2_CC2OF   ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */
00737 #define TIM1_SR2_CC1OF   ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */
00738 /*EGR*/
00739 #define TIM1_EGR_BG      ((uint8_t)0x80) /*!< Break Generation mask. */
00740 #define TIM1_EGR_TG      ((uint8_t)0x40) /*!< Trigger Generation mask. */
00741 #define TIM1_EGR_COMG    ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation mask. */
00742 #define TIM1_EGR_CC4G    ((uint8_t)0x10) /*!< Capture/Compare 4 Generation mask. */
00743 #define TIM1_EGR_CC3G    ((uint8_t)0x08) /*!< Capture/Compare 3 Generation mask. */
00744 #define TIM1_EGR_CC2G    ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */
00745 #define TIM1_EGR_CC1G    ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */
00746 #define TIM1_EGR_UG      ((uint8_t)0x01) /*!< Update Generation mask. */
00747 /*CCMR*/
00748 #define TIM1_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */
00749 #define TIM1_CCMR_ICxF   ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */
00750 #define TIM1_CCMR_OCM    ((uint8_t)0x70) /*!< Output Compare x Mode mask. */
00751 #define TIM1_CCMR_OCxPE  ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */
00752 #define TIM1_CCMR_OCxFE  ((uint8_t)0x04) /*!< Output Compare x Fast Enable mask. */
00753 #define TIM1_CCMR_CCxS   ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */
00754
00755 #define CCMR_TIxDirect_Set ((uint8_t)0x01)
00756 /*CCER1*/
00757 #define TIM1_CCER1_CC2NP ((uint8_t)0x80) /*!< Capture/Compare 2 Complementary output Polarity mask. */
00758 #define TIM1_CCER1_CC2NE ((uint8_t)0x40) /*!< Capture/Compare 2 Complementary output enable mask. */
00759 #define TIM1_CCER1_CC2P  ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */
00760 #define TIM1_CCER1_CC2E  ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */
00761 #define TIM1_CCER1_CC1NP ((uint8_t)0x08) /*!< Capture/Compare 1 Complementary output Polarity mask. */
00762 #define TIM1_CCER1_CC1NE ((uint8_t)0x04) /*!< Capture/Compare 1 Complementary output enable mask. */
00763 #define TIM1_CCER1_CC1P  ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */
00764 #define TIM1_CCER1_CC1E  ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */
00765 /*CCER2*/
00766 #define TIM1_CCER2_CC4P  ((uint8_t)0x20) /*!< Capture/Compare 4 output Polarity mask. */
00767 #define TIM1_CCER2_CC4E  ((uint8_t)0x10) /*!< Capture/Compare 4 output enable mask. */
00768 #define TIM1_CCER2_CC3NP ((uint8_t)0x08) /*!< Capture/Compare 3 Complementary output Polarity mask. */
00769 #define TIM1_CCER2_CC3NE ((uint8_t)0x04) /*!< Capture/Compare 3 Complementary output enable mask. */
00770 #define TIM1_CCER2_CC3P  ((uint8_t)0x02) /*!< Capture/Compare 3 output Polarity mask. */
00771 #define TIM1_CCER2_CC3E  ((uint8_t)0x01) /*!< Capture/Compare 3 output enable mask. */
00772 /*CNTRH*/
00773 #define TIM1_CNTRH_CNT   ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */
00774 /*CNTRL*/
00775 #define TIM1_CNTRL_CNT   ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */
00776 /*PSCH*/
00777 #define TIM1_PSCH_PSC    ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */
00778 /*PSCL*/
00779 #define TIM1_PSCL_PSC    ((uint8_t)0xFF) /*!< Prescaler Value (LSB) mask. */
00780 /*ARR*/
00781 #define TIM1_ARRH_ARR    ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */
00782 #define TIM1_ARRL_ARR    ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */
00783 /*RCR*/
00784 #define TIM1_RCR_REP     ((uint8_t)0xFF) /*!< Repetition Counter Value mask. */
00785 /*CCR1*/
00786 #define TIM1_CCR1H_CCR1  ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */
00787 #define TIM1_CCR1L_CCR1  ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */
00788 /*CCR2*/
00789 #define TIM1_CCR2H_CCR2  ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */
00790 #define TIM1_CCR2L_CCR2  ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */
00791 /*CCR3*/
00792 #define TIM1_CCR3H_CCR3  ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */
00793 #define TIM1_CCR3L_CCR3  ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */
00794 /*CCR4*/
00795 #define TIM1_CCR4H_CCR4  ((uint8_t)0xFF) /*!< Capture/Compare 4 Value (MSB) mask. */
00796 #define TIM1_CCR4L_CCR4  ((uint8_t)0xFF) /*!< Capture/Compare 4 Value (LSB) mask. */
00797 /*BKR*/
00798 #define TIM1_BKR_MOE     ((uint8_t)0x80) /*!< Main Output Enable mask. */
00799 #define TIM1_BKR_AOE     ((uint8_t)0x40) /*!< Automatic Output Enable mask. */
00800 #define TIM1_BKR_BKP     ((uint8_t)0x20) /*!< Break Polarity mask. */
00801 #define TIM1_BKR_BKE     ((uint8_t)0x10) /*!< Break Enable mask. */
00802 #define TIM1_BKR_OSSR    ((uint8_t)0x08) /*!< Off-State Selection for Run mode mask. */
00803 #define TIM1_BKR_OSSI    ((uint8_t)0x04) /*!< Off-State Selection for Idle mode mask. */
00804 #define TIM1_BKR_LOCK    ((uint8_t)0x03) /*!< Lock Configuration mask. */
00805 /*DTR*/
00806 #define TIM1_DTR_DTG     ((uint8_t)0xFF) /*!< Dead-Time Generator set-up mask. */
00807 /*OISR*/
00808 #define TIM1_OISR_OIS4   ((uint8_t)0x40) /*!< Output Idle state 4 (OC4 output) mask. */
00809 #define TIM1_OISR_OIS3N  ((uint8_t)0x20) /*!< Output Idle state 3 (OC3N output) mask. */
00810 #define TIM1_OISR_OIS3   ((uint8_t)0x10) /*!< Output Idle state 3 (OC3 output) mask. */
00811 #define TIM1_OISR_OIS2N  ((uint8_t)0x08) /*!< Output Idle state 2 (OC2N output) mask. */
00812 #define TIM1_OISR_OIS2   ((uint8_t)0x04) /*!< Output Idle state 2 (OC2 output) mask. */
00813 #define TIM1_OISR_OIS1N  ((uint8_t)0x02) /*!< Output Idle state 1 (OC1N output) mask. */
00814 #define TIM1_OISR_OIS1   ((uint8_t)0x01) /*!< Output Idle state 1 (OC1 output) mask. */
00815 /**
00816   * @}
00817   */
00818
00819 /*----------------------------------------------------------------------------*/
00820 /**
00821   * @brief  16-bit timer (TIM2)
00822   */
00823
00824 typedef struct TIM2_struct
00825 {
00826   __IO uint8_t CR1;   /*!< control register 1 */
00827 #if defined(STM8S103) || defined(STM8S003) || defined(STM8S001)
00828         uint8_t RESERVED1; /*!< Reserved register */
00829         uint8_t RESERVED2; /*!< Reserved register */
00830 #endif
00831   __IO uint8_t IER;   /*!< interrupt enable register */
00832   __IO uint8_t SR1;   /*!< status register 1 */
00833   __IO uint8_t SR2;   /*!< status register 2 */
00834   __IO uint8_t EGR;   /*!< event generation register */
00835   __IO uint8_t CCMR1; /*!< CC mode register 1 */
00836   __IO uint8_t CCMR2; /*!< CC mode register 2 */
00837   __IO uint8_t CCMR3; /*!< CC mode register 3 */
00838   __IO uint8_t CCER1; /*!< CC enable register 1 */
00839   __IO uint8_t CCER2; /*!< CC enable register 2 */
00840   __IO uint8_t CNTRH; /*!< counter high */
00841   __IO uint8_t CNTRL; /*!< counter low */
00842   __IO uint8_t PSCR;  /*!< prescaler register */
00843   __IO uint8_t ARRH;  /*!< auto-reload register high */
00844   __IO uint8_t ARRL;  /*!< auto-reload register low */
00845   __IO uint8_t CCR1H; /*!< capture/compare register 1 high */
00846   __IO uint8_t CCR1L; /*!< capture/compare register 1 low */
00847   __IO uint8_t CCR2H; /*!< capture/compare register 2 high */
00848   __IO uint8_t CCR2L; /*!< capture/compare register 2 low */
00849   __IO uint8_t CCR3H; /*!< capture/compare register 3 high */
00850   __IO uint8_t CCR3L; /*!< capture/compare register 3 low */
00851 }
00852 TIM2_TypeDef;
00853
00854 /** @addtogroup TIM2_Registers_Reset_Value
00855   * @{
00856   */
00857
00858 #define TIM2_CR1_RESET_VALUE   ((uint8_t)0x00)
00859 #define TIM2_IER_RESET_VALUE   ((uint8_t)0x00)
00860 #define TIM2_SR1_RESET_VALUE   ((uint8_t)0x00)
00861 #define TIM2_SR2_RESET_VALUE   ((uint8_t)0x00)
00862 #define TIM2_EGR_RESET_VALUE   ((uint8_t)0x00)
00863 #define TIM2_CCMR1_RESET_VALUE ((uint8_t)0x00)
00864 #define TIM2_CCMR2_RESET_VALUE ((uint8_t)0x00)
00865 #define TIM2_CCMR3_RESET_VALUE ((uint8_t)0x00)
00866 #define TIM2_CCER1_RESET_VALUE ((uint8_t)0x00)
00867 #define TIM2_CCER2_RESET_VALUE ((uint8_t)0x00)
00868 #define TIM2_CNTRH_RESET_VALUE ((uint8_t)0x00)
00869 #define TIM2_CNTRL_RESET_VALUE ((uint8_t)0x00)
00870 #define TIM2_PSCR_RESET_VALUE  ((uint8_t)0x00)
00871 #define TIM2_ARRH_RESET_VALUE  ((uint8_t)0xFF)
00872 #define TIM2_ARRL_RESET_VALUE  ((uint8_t)0xFF)
00873 #define TIM2_CCR1H_RESET_VALUE ((uint8_t)0x00)
00874 #define TIM2_CCR1L_RESET_VALUE ((uint8_t)0x00)
00875 #define TIM2_CCR2H_RESET_VALUE ((uint8_t)0x00)
00876 #define TIM2_CCR2L_RESET_VALUE ((uint8_t)0x00)
00877 #define TIM2_CCR3H_RESET_VALUE ((uint8_t)0x00)
00878 #define TIM2_CCR3L_RESET_VALUE ((uint8_t)0x00)
00879
00880 /**
00881   * @}
00882   */
00883
00884 /** @addtogroup TIM2_Registers_Bits_Definition
00885   * @{
00886   */
00887 /*CR1*/
00888 #define TIM2_CR1_ARPE    ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */
00889 #define TIM2_CR1_OPM     ((uint8_t)0x08) /*!< One Pulse Mode mask. */
00890 #define TIM2_CR1_URS     ((uint8_t)0x04) /*!< Update Request Source mask. */
00891 #define TIM2_CR1_UDIS    ((uint8_t)0x02) /*!< Update DIsable mask. */
00892 #define TIM2_CR1_CEN     ((uint8_t)0x01) /*!< Counter Enable mask. */
00893 /*IER*/
00894 #define TIM2_IER_CC3IE   ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */
00895 #define TIM2_IER_CC2IE   ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */
00896 #define TIM2_IER_CC1IE   ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */
00897 #define TIM2_IER_UIE     ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */
00898 /*SR1*/
00899 #define TIM2_SR1_CC3IF   ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */
00900 #define TIM2_SR1_CC2IF   ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */
00901 #define TIM2_SR1_CC1IF   ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */
00902 #define TIM2_SR1_UIF     ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */
00903 /*SR2*/
00904 #define TIM2_SR2_CC3OF   ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */
00905 #define TIM2_SR2_CC2OF   ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */
00906 #define TIM2_SR2_CC1OF   ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */
00907 /*EGR*/
00908 #define TIM2_EGR_CC3G    ((uint8_t)0x08) /*!< Capture/Compare 3 Generation mask. */
00909 #define TIM2_EGR_CC2G    ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */
00910 #define TIM2_EGR_CC1G    ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */
00911 #define TIM2_EGR_UG      ((uint8_t)0x01) /*!< Update Generation mask. */
00912 /*CCMR*/
00913 #define TIM2_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */
00914 #define TIM2_CCMR_ICxF   ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */
00915 #define TIM2_CCMR_OCM    ((uint8_t)0x70) /*!< Output Compare x Mode mask. */
00916 #define TIM2_CCMR_OCxPE  ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */
00917 #define TIM2_CCMR_CCxS   ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */
00918 /*CCER1*/
00919 #define TIM2_CCER1_CC2P  ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */
00920 #define TIM2_CCER1_CC2E  ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */
00921 #define TIM2_CCER1_CC1P  ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */
00922 #define TIM2_CCER1_CC1E  ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */
00923 /*CCER2*/
00924 #define TIM2_CCER2_CC3P  ((uint8_t)0x02) /*!< Capture/Compare 3 output Polarity mask. */
00925 #define TIM2_CCER2_CC3E  ((uint8_t)0x01) /*!< Capture/Compare 3 output enable mask. */
00926 /*CNTR*/
00927 #define TIM2_CNTRH_CNT   ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */
00928 #define TIM2_CNTRL_CNT   ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */
00929 /*PSCR*/
00930 #define TIM2_PSCR_PSC    ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */
00931 /*ARR*/
00932 #define TIM2_ARRH_ARR    ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */
00933 #define TIM2_ARRL_ARR    ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */
00934 /*CCR1*/
00935 #define TIM2_CCR1H_CCR1  ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */
00936 #define TIM2_CCR1L_CCR1  ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */
00937 /*CCR2*/
00938 #define TIM2_CCR2H_CCR2  ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */
00939 #define TIM2_CCR2L_CCR2  ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */
00940 /*CCR3*/
00941 #define TIM2_CCR3H_CCR3  ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */
00942 #define TIM2_CCR3L_CCR3  ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */
00943
00944 /**
00945   * @}
00946   */
00947
00948 /*----------------------------------------------------------------------------*/
00949 /**
00950   * @brief  16-bit timer (TIM3)
00951   */
00952 typedef struct TIM3_struct
00953 {
00954   __IO uint8_t CR1;   /*!< control register 1 */
00955   __IO uint8_t IER;   /*!< interrupt enable register */
00956   __IO uint8_t SR1;   /*!< status register 1 */
00957   __IO uint8_t SR2;   /*!< status register 2 */
00958   __IO uint8_t EGR;   /*!< event generation register */
00959   __IO uint8_t CCMR1; /*!< CC mode register 1 */
00960   __IO uint8_t CCMR2; /*!< CC mode register 2 */
00961   __IO uint8_t CCER1; /*!< CC enable register 1 */
00962   __IO uint8_t CNTRH; /*!< counter high */
00963   __IO uint8_t CNTRL; /*!< counter low */
00964   __IO uint8_t PSCR;  /*!< prescaler register */
00965   __IO uint8_t ARRH;  /*!< auto-reload register high */
00966   __IO uint8_t ARRL;  /*!< auto-reload register low */
00967   __IO uint8_t CCR1H; /*!< capture/compare register 1 high */
00968   __IO uint8_t CCR1L; /*!< capture/compare register 1 low */
00969   __IO uint8_t CCR2H; /*!< capture/compare register 2 high */
00970   __IO uint8_t CCR2L; /*!< capture/compare register 2 low */
00971 }
00972 TIM3_TypeDef;
00973
00974 /** @addtogroup TIM3_Registers_Reset_Value
00975   * @{
00976   */
00977
00978 #define TIM3_CR1_RESET_VALUE   ((uint8_t)0x00)
00979 #define TIM3_IER_RESET_VALUE   ((uint8_t)0x00)
00980 #define TIM3_SR1_RESET_VALUE   ((uint8_t)0x00)
00981 #define TIM3_SR2_RESET_VALUE   ((uint8_t)0x00)
00982 #define TIM3_EGR_RESET_VALUE   ((uint8_t)0x00)
00983 #define TIM3_CCMR1_RESET_VALUE ((uint8_t)0x00)
00984 #define TIM3_CCMR2_RESET_VALUE ((uint8_t)0x00)
00985 #define TIM3_CCER1_RESET_VALUE ((uint8_t)0x00)
00986 #define TIM3_CNTRH_RESET_VALUE ((uint8_t)0x00)
00987 #define TIM3_CNTRL_RESET_VALUE ((uint8_t)0x00)
00988 #define TIM3_PSCR_RESET_VALUE  ((uint8_t)0x00)
00989 #define TIM3_ARRH_RESET_VALUE  ((uint8_t)0xFF)
00990 #define TIM3_ARRL_RESET_VALUE  ((uint8_t)0xFF)
00991 #define TIM3_CCR1H_RESET_VALUE ((uint8_t)0x00)
00992 #define TIM3_CCR1L_RESET_VALUE ((uint8_t)0x00)
00993 #define TIM3_CCR2H_RESET_VALUE ((uint8_t)0x00)
00994 #define TIM3_CCR2L_RESET_VALUE ((uint8_t)0x00)
00995
00996 /**
00997   * @}
00998   */
00999
01000 /** @addtogroup TIM3_Registers_Bits_Definition
01001   * @{
01002   */
01003 /*CR1*/
01004 #define TIM3_CR1_ARPE    ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */
01005 #define TIM3_CR1_OPM     ((uint8_t)0x08) /*!< One Pulse Mode mask. */
01006 #define TIM3_CR1_URS     ((uint8_t)0x04) /*!< Update Request Source mask. */
01007 #define TIM3_CR1_UDIS    ((uint8_t)0x02) /*!< Update DIsable mask. */
01008 #define TIM3_CR1_CEN     ((uint8_t)0x01) /*!< Counter Enable mask. */
01009 /*IER*/
01010 #define TIM3_IER_CC2IE   ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */
01011 #define TIM3_IER_CC1IE   ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */
01012 #define TIM3_IER_UIE     ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */
01013 /*SR1*/
01014 #define TIM3_SR1_CC2IF   ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */
01015 #define TIM3_SR1_CC1IF   ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */
01016 #define TIM3_SR1_UIF     ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */
01017 /*SR2*/
01018 #define TIM3_SR2_CC2OF   ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */
01019 #define TIM3_SR2_CC1OF   ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */
01020 /*EGR*/
01021 #define TIM3_EGR_CC2G    ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */
01022 #define TIM3_EGR_CC1G    ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */
01023 #define TIM3_EGR_UG      ((uint8_t)0x01) /*!< Update Generation mask. */
01024 /*CCMR*/
01025 #define TIM3_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */
01026 #define TIM3_CCMR_ICxF   ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */
01027 #define TIM3_CCMR_OCM    ((uint8_t)0x70) /*!< Output Compare x Mode mask. */
01028 #define TIM3_CCMR_OCxPE  ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */
01029 #define TIM3_CCMR_CCxS   ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */
01030 /*CCER1*/
01031 #define TIM3_CCER1_CC2P  ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */
01032 #define TIM3_CCER1_CC2E  ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */
01033 #define TIM3_CCER1_CC1P  ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */
01034 #define TIM3_CCER1_CC1E  ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */
01035 /*CNTR*/
01036 #define TIM3_CNTRH_CNT   ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */
01037 #define TIM3_CNTRL_CNT   ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */
01038 /*PSCR*/
01039 #define TIM3_PSCR_PSC    ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */
01040 /*ARR*/
01041 #define TIM3_ARRH_ARR    ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */
01042 #define TIM3_ARRL_ARR    ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */
01043 /*CCR1*/
01044 #define TIM3_CCR1H_CCR1  ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */
01045 #define TIM3_CCR1L_CCR1  ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */
01046 /*CCR2*/
01047 #define TIM3_CCR2H_CCR2  ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */
01048 #define TIM3_CCR2L_CCR2  ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */
01049 /**
01050   * @}
01051   */
01052
01053 /*----------------------------------------------------------------------------*/
01054 /**
01055   * @brief  8-bit system timer (TIM4)
01056   */
01057
01058 typedef struct TIM4_struct
01059 {
01060   __IO uint8_t CR1;  /*!< control register 1 */
01061 #if defined(STM8S103) || defined(STM8S003) || defined(STM8S001)
01062         uint8_t RESERVED1; /*!< Reserved register */
01063         uint8_t RESERVED2; /*!< Reserved register */
01064 #endif
01065   __IO uint8_t IER;  /*!< interrupt enable register */
01066   __IO uint8_t SR1;  /*!< status register 1 */
01067   __IO uint8_t EGR;  /*!< event generation register */
01068   __IO uint8_t CNTR; /*!< counter register */
01069   __IO uint8_t PSCR; /*!< prescaler register */
01070   __IO uint8_t ARR;  /*!< auto-reload register */
01071 }
01072 TIM4_TypeDef;
01073
01074 /** @addtogroup TIM4_Registers_Reset_Value
01075   * @{
01076   */
01077
01078 #define TIM4_CR1_RESET_VALUE  ((uint8_t)0x00)
01079 #define TIM4_IER_RESET_VALUE  ((uint8_t)0x00)
01080 #define TIM4_SR1_RESET_VALUE  ((uint8_t)0x00)
01081 #define TIM4_EGR_RESET_VALUE  ((uint8_t)0x00)
01082 #define TIM4_CNTR_RESET_VALUE ((uint8_t)0x00)
01083 #define TIM4_PSCR_RESET_VALUE ((uint8_t)0x00)
01084 #define TIM4_ARR_RESET_VALUE  ((uint8_t)0xFF)
01085
01086 /**
01087   * @}
01088   */
01089
01090 /** @addtogroup TIM4_Registers_Bits_Definition
01091   * @{
01092   */
01093 /*CR1*/
01094 #define TIM4_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */
01095 #define TIM4_CR1_OPM  ((uint8_t)0x08) /*!< One Pulse Mode mask. */
01096 #define TIM4_CR1_URS  ((uint8_t)0x04) /*!< Update Request Source mask. */
01097 #define TIM4_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */
01098 #define TIM4_CR1_CEN  ((uint8_t)0x01) /*!< Counter Enable mask. */
01099 /*IER*/
01100 #define TIM4_IER_UIE  ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */
01101 /*SR1*/
01102 #define TIM4_SR1_UIF  ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */
01103 /*EGR*/
01104 #define TIM4_EGR_UG   ((uint8_t)0x01) /*!< Update Generation mask. */
01105 /*CNTR*/
01106 #define TIM4_CNTR_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */
01107 /*PSCR*/
01108 #define TIM4_PSCR_PSC ((uint8_t)0x07) /*!< Prescaler Value  mask. */
01109 /*ARR*/
01110 #define TIM4_ARR_ARR  ((uint8_t)0xFF) /*!< Autoreload Value mask. */
01111
01112 /**
01113   * @}
01114   */
01115
01116 /*----------------------------------------------------------------------------*/
01117 /**
01118   * @brief  16-bit timer with synchro module (TIM5)
01119   */
01120
01121 typedef struct TIM5_struct
01122 {
01123   __IO uint8_t CR1;       /*!<TIM5 Control Register 1                */
01124   __IO uint8_t CR2;       /*!<TIM5 Control Register 2                */
01125   __IO uint8_t SMCR;      /*!<TIM5 Slave Mode Control Register       */
01126   __IO uint8_t IER;       /*!<TIM5 Interrupt Enable Register         */
01127   __IO uint8_t SR1;       /*!<TIM5 Status Register 1                 */
01128   __IO uint8_t SR2;       /*!<TIM5 Status Register 2                 */
01129   __IO uint8_t EGR;       /*!<TIM5 Event Generation Register         */
01130   __IO uint8_t CCMR1;     /*!<TIM5 Capture/Compare Mode Register 1   */
01131   __IO uint8_t CCMR2;     /*!<TIM5 Capture/Compare Mode Register 2   */
01132   __IO uint8_t CCMR3;     /*!<TIM5 Capture/Compare Mode Register 3   */
01133   __IO uint8_t CCER1;     /*!<TIM5 Capture/Compare Enable Register 1 */
01134   __IO uint8_t CCER2;     /*!<TIM5 Capture/Compare Enable Register 2 */
01135   __IO uint8_t CNTRH;     /*!<TIM5 Counter High                      */
01136   __IO uint8_t CNTRL;     /*!<TIM5 Counter Low                       */
01137   __IO uint8_t PSCR;      /*!<TIM5 Prescaler Register                */
01138   __IO uint8_t ARRH;      /*!<TIM5 Auto-Reload Register High         */
01139   __IO uint8_t ARRL;      /*!<TIM5 Auto-Reload Register Low          */
01140   __IO uint8_t CCR1H;     /*!<TIM5 Capture/Compare Register 1 High   */
01141   __IO uint8_t CCR1L;     /*!<TIM5 Capture/Compare Register 1 Low    */
01142   __IO uint8_t CCR2H;     /*!<TIM5 Capture/Compare Register 2 High   */
01143   __IO uint8_t CCR2L;     /*!<TIM5 Capture/Compare Register 2 Low    */
01144   __IO uint8_t CCR3H;     /*!<TIM5 Capture/Compare Register 3 High   */
01145   __IO uint8_t CCR3L;     /*!<TIM5 Capture/Compare Register 3 Low    */
01146 }TIM5_TypeDef;
01147
01148 /** @addtogroup TIM5_Registers_Reset_Value
01149   * @{
01150   */
01151
01152 #define TIM5_CR1_RESET_VALUE   ((uint8_t)0x00)
01153 #define TIM5_CR2_RESET_VALUE     ((uint8_t)0x00)
01154 #define TIM5_SMCR_RESET_VALUE    ((uint8_t)0x00)
01155 #define TIM5_IER_RESET_VALUE   ((uint8_t)0x00)
01156 #define TIM5_SR1_RESET_VALUE   ((uint8_t)0x00)
01157 #define TIM5_SR2_RESET_VALUE   ((uint8_t)0x00)
01158 #define TIM5_EGR_RESET_VALUE   ((uint8_t)0x00)
01159 #define TIM5_CCMR1_RESET_VALUE ((uint8_t)0x00)
01160 #define TIM5_CCMR2_RESET_VALUE ((uint8_t)0x00)
01161 #define TIM5_CCMR3_RESET_VALUE ((uint8_t)0x00)
01162 #define TIM5_CCER1_RESET_VALUE ((uint8_t)0x00)
01163 #define TIM5_CCER2_RESET_VALUE ((uint8_t)0x00)
01164 #define TIM5_CNTRH_RESET_VALUE ((uint8_t)0x00)
01165 #define TIM5_CNTRL_RESET_VALUE ((uint8_t)0x00)
01166 #define TIM5_PSCR_RESET_VALUE  ((uint8_t)0x00)
01167 #define TIM5_ARRH_RESET_VALUE  ((uint8_t)0xFF)
01168 #define TIM5_ARRL_RESET_VALUE  ((uint8_t)0xFF)
01169 #define TIM5_CCR1H_RESET_VALUE ((uint8_t)0x00)
01170 #define TIM5_CCR1L_RESET_VALUE ((uint8_t)0x00)
01171 #define TIM5_CCR2H_RESET_VALUE ((uint8_t)0x00)
01172 #define TIM5_CCR2L_RESET_VALUE ((uint8_t)0x00)
01173 #define TIM5_CCR3H_RESET_VALUE ((uint8_t)0x00)
01174 #define TIM5_CCR3L_RESET_VALUE ((uint8_t)0x00)
01175
01176 /**
01177   * @}
01178   */
01179
01180 /** @addtogroup TIM5_Registers_Bits_Definition
01181   * @{
01182   */
01183 /* CR1*/
01184 #define TIM5_CR1_ARPE           ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */
01185 #define TIM5_CR1_OPM            ((uint8_t)0x08) /*!< One Pulse Mode mask. */
01186 #define TIM5_CR1_URS            ((uint8_t)0x04) /*!< Update Request Source mask. */
01187 #define TIM5_CR1_UDIS           ((uint8_t)0x02) /*!< Update DIsable mask. */
01188 #define TIM5_CR1_CEN            ((uint8_t)0x01) /*!< Counter Enable mask. */
01189 /* CR2*/
01190 #define TIM5_CR2_TI1S           ((uint8_t)0x80) /*!< TI1S Selection Mask. */
01191 #define TIM5_CR2_MMS              ((uint8_t)0x70) /*!< MMS Selection Mask. */
01192 /* SMCR*/
01193 #define TIM5_SMCR_MSM           ((uint8_t)0x80) /*!< Master/Slave Mode Mask. */
01194 #define TIM5_SMCR_TS            ((uint8_t)0x70) /*!< Trigger Selection Mask. */
01195 #define TIM5_SMCR_SMS           ((uint8_t)0x07) /*!< Slave Mode Selection Mask. */
01196 /*IER*/
01197 #define TIM5_IER_TIE            ((uint8_t)0x40) /*!< Trigger Interrupt Enable mask. */
01198 #define TIM5_IER_CC3IE          ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */
01199 #define TIM5_IER_CC2IE          ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */
01200 #define TIM5_IER_CC1IE          ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */
01201 #define TIM5_IER_UIE            ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */
01202 /*SR1*/
01203 #define TIM5_SR1_TIF            ((uint8_t)0x40) /*!< Trigger Interrupt Flag mask. */
01204 #define TIM5_SR1_CC3IF          ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */
01205 #define TIM5_SR1_CC2IF          ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */
01206 #define TIM5_SR1_CC1IF          ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */
01207 #define TIM5_SR1_UIF            ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */
01208 /*SR2*/
01209 #define TIM5_SR2_CC3OF          ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */
01210 #define TIM5_SR2_CC2OF          ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */
01211 #define TIM5_SR2_CC1OF          ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */
01212 /*EGR*/
01213 #define TIM5_EGR_TG             ((uint8_t)0x40) /*!< Trigger Generation mask. */
01214 #define TIM5_EGR_CC3G           ((uint8_t)0x08) /*!< Capture/Compare 3 Generation mask. */
01215 #define TIM5_EGR_CC2G           ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */
01216 #define TIM5_EGR_CC1G           ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */
01217 #define TIM5_EGR_UG             ((uint8_t)0x01) /*!< Update Generation mask. */
01218 /*CCMR*/
01219 #define TIM5_CCMR_ICxPSC        ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */
01220 #define TIM5_CCMR_ICxF          ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */
01221 #define TIM5_CCMR_OCM           ((uint8_t)0x70) /*!< Output Compare x Mode mask. */
01222 #define TIM5_CCMR_OCxPE         ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */
01223 #define TIM5_CCMR_CCxS          ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */
01224 /*CCER1*/
01225 #define TIM5_CCER1_CC2P         ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */
01226 #define TIM5_CCER1_CC2E         ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */
01227 #define TIM5_CCER1_CC1P         ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */
01228 #define TIM5_CCER1_CC1E         ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */
01229 /*CCER2*/
01230 #define TIM5_CCER2_CC3P         ((uint8_t)0x02) /*!< Capture/Compare 3 output Polarity mask. */
01231 #define TIM5_CCER2_CC3E         ((uint8_t)0x01) /*!< Capture/Compare 3 output enable mask. */
01232 /*CNTR*/
01233 #define TIM5_CNTRH_CNT          ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */
01234 #define TIM5_CNTRL_CNT          ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */
01235 /*PSCR*/
01236 #define TIM5_PSCR_PSC           ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */
01237 /*ARR*/
01238 #define TIM5_ARRH_ARR           ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */
01239 #define TIM5_ARRL_ARR           ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */
01240 /*CCR1*/
01241 #define TIM5_CCR1H_CCR1         ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */
01242 #define TIM5_CCR1L_CCR1         ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */
01243 /*CCR2*/
01244 #define TIM5_CCR2H_CCR2         ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */
01245 #define TIM5_CCR2L_CCR2         ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */
01246 /*CCR3*/
01247 #define TIM5_CCR3H_CCR3         ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */
01248 #define TIM5_CCR3L_CCR3         ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */
01249 /*CCMR*/
01250 #define TIM5_CCMR_TIxDirect_Set ((uint8_t)0x01)
01251 /**
01252   * @}
01253   */
01254
01255 /*----------------------------------------------------------------------------*/
01256 /**
01257   * @brief  8-bit system timer  with synchro module(TIM6)
01258   */
01259
01260 typedef struct TIM6_struct
01261 {
01262     __IO uint8_t CR1;   /*!< control register 1 */
01263     __IO uint8_t CR2;   /*!< control register 2 */
01264     __IO uint8_t SMCR;  /*!< Synchro mode control register */
01265     __IO uint8_t IER;   /*!< interrupt enable register  */
01266     __IO uint8_t SR1;   /*!< status register 1    */
01267     __IO uint8_t EGR;   /*!< event generation register */
01268     __IO uint8_t CNTR;  /*!< counter register  */
01269     __IO uint8_t PSCR;  /*!< prescaler register */
01270     __IO uint8_t ARR;   /*!< auto-reload register */
01271 }
01272 TIM6_TypeDef;
01273 /** @addtogroup TIM6_Registers_Reset_Value
01274   * @{
01275   */
01276 #define TIM6_CR1_RESET_VALUE    ((uint8_t)0x00)
01277 #define TIM6_CR2_RESET_VALUE    ((uint8_t)0x00)
01278 #define TIM6_SMCR_RESET_VALUE   ((uint8_t)0x00)
01279 #define TIM6_IER_RESET_VALUE    ((uint8_t)0x00)
01280 #define TIM6_SR1_RESET_VALUE    ((uint8_t)0x00)
01281 #define TIM6_EGR_RESET_VALUE    ((uint8_t)0x00)
01282 #define TIM6_CNTR_RESET_VALUE   ((uint8_t)0x00)
01283 #define TIM6_PSCR_RESET_VALUE   ((uint8_t)0x00)
01284 #define TIM6_ARR_RESET_VALUE    ((uint8_t)0xFF)
01285
01286 /**
01287 * @}
01288 */
01289
01290 /** @addtogroup TIM6_Registers_Bits_Definition
01291   * @{
01292   */
01293 /* CR1*/
01294 #define TIM6_CR1_ARPE    ((uint8_t)0x80) /*!< Auto-Reload Preload Enable Mask. */
01295 #define TIM6_CR1_OPM     ((uint8_t)0x08) /*!< One Pulse Mode Mask. */
01296 #define TIM6_CR1_URS     ((uint8_t)0x04) /*!< Update Request Source Mask. */
01297 #define TIM6_CR1_UDIS    ((uint8_t)0x02) /*!< Update DIsable Mask. */
01298 #define TIM6_CR1_CEN     ((uint8_t)0x01) /*!< Counter Enable Mask. */
01299 /* CR2*/
01300 #define TIM6_CR2_MMS       ((uint8_t)0x70) /*!< MMS Selection Mask. */
01301 /* SMCR*/
01302 #define TIM6_SMCR_MSM    ((uint8_t)0x80) /*!< Master/Slave Mode Mask. */
01303 #define TIM6_SMCR_TS     ((uint8_t)0x70) /*!< Trigger Selection Mask. */
01304 #define TIM6_SMCR_SMS    ((uint8_t)0x07) /*!< Slave Mode Selection Mask. */
01305 /* IER*/
01306 #define TIM6_IER_TIE     ((uint8_t)0x40) /*!< Trigger Interrupt Enable Mask. */
01307 #define TIM6_IER_UIE     ((uint8_t)0x01) /*!< Update Interrupt Enable Mask. */
01308 /* SR1*/
01309 #define TIM6_SR1_TIF     ((uint8_t)0x40) /*!< Trigger Interrupt Flag mask. */
01310 #define TIM6_SR1_UIF     ((uint8_t)0x01) /*!< Update Interrupt Flag Mask. */
01311 /* EGR*/
01312 #define TIM6_EGR_TG      ((uint8_t)0x40) /*!< Trigger Generation mask. */
01313 #define TIM6_EGR_UG      ((uint8_t)0x01) /*!< Update Generation Mask. */
01314 /* CNTR*/
01315 #define TIM6_CNTR_CNT    ((uint8_t)0xFF) /*!<Counter Value (LSB) Mask. */
01316 /* PSCR*/
01317 #define TIM6_PSCR_PSC    ((uint8_t)0x07) /*!<Prescaler Value  Mask. */
01318
01319 #define TIM6_ARR_ARR       ((uint8_t)0xFF) /*!<Autoreload Value Mask. */
01320 /**
01321   * @}
01322   */
01323 /*----------------------------------------------------------------------------*/
01324 /**
01325   * @brief  Inter-Integrated Circuit (I2C)
01326   */
01327
01328 typedef struct I2C_struct
01329 {
01330   __IO uint8_t CR1;       /*!< I2C control register 1 */
01331   __IO uint8_t CR2;       /*!< I2C control register 2 */
01332   __IO uint8_t FREQR;     /*!< I2C frequency register */
01333   __IO uint8_t OARL;      /*!< I2C own address register LSB */
01334   __IO uint8_t OARH;      /*!< I2C own address register MSB */
01335   uint8_t RESERVED1;      /*!< Reserved byte */
01336   __IO uint8_t DR;        /*!< I2C data register */
01337   __IO uint8_t SR1;       /*!< I2C status register 1 */
01338   __IO uint8_t SR2;       /*!< I2C status register 2 */
01339   __IO uint8_t SR3;       /*!< I2C status register 3 */
01340   __IO uint8_t ITR;       /*!< I2C interrupt register */
01341   __IO uint8_t CCRL;      /*!< I2C clock control register low */
01342   __IO uint8_t CCRH;      /*!< I2C clock control register high */
01343   __IO uint8_t TRISER;    /*!< I2C maximum rise time register */
01344   uint8_t RESERVED2;      /*!< Reserved byte */
01345 }
01346 I2C_TypeDef;
01347
01348 /** @addtogroup I2C_Registers_Reset_Value
01349   * @{
01350   */
01351
01352 #define I2C_CR1_RESET_VALUE    ((uint8_t)0x00)
01353 #define I2C_CR2_RESET_VALUE    ((uint8_t)0x00)
01354 #define I2C_FREQR_RESET_VALUE  ((uint8_t)0x00)
01355 #define I2C_OARL_RESET_VALUE   ((uint8_t)0x00)
01356 #define I2C_OARH_RESET_VALUE   ((uint8_t)0x00)
01357 #define I2C_DR_RESET_VALUE     ((uint8_t)0x00)
01358 #define I2C_SR1_RESET_VALUE    ((uint8_t)0x00)
01359 #define I2C_SR2_RESET_VALUE    ((uint8_t)0x00)
01360 #define I2C_SR3_RESET_VALUE    ((uint8_t)0x00)
01361 #define I2C_ITR_RESET_VALUE    ((uint8_t)0x00)
01362 #define I2C_CCRL_RESET_VALUE   ((uint8_t)0x00)
01363 #define I2C_CCRH_RESET_VALUE   ((uint8_t)0x00)
01364 #define I2C_TRISER_RESET_VALUE ((uint8_t)0x02)
01365
01366 /**
01367   * @}
01368   */
01369
01370 /** @addtogroup I2C_Registers_Bits_Definition
01371   * @{
01372   */
01373
01374 #define I2C_CR1_NOSTRETCH ((uint8_t)0x80) /*!< Clock Stretching Disable (Slave mode) */
01375 #define I2C_CR1_ENGC      ((uint8_t)0x40) /*!< General Call Enable */
01376 #define I2C_CR1_PE        ((uint8_t)0x01) /*!< Peripheral Enable */
01377
01378 #define I2C_CR2_SWRST ((uint8_t)0x80)     /*!< Software Reset */
01379 #define I2C_CR2_POS   ((uint8_t)0x08)     /*!< Acknowledge */
01380 #define I2C_CR2_ACK   ((uint8_t)0x04)     /*!< Acknowledge Enable */
01381 #define I2C_CR2_STOP  ((uint8_t)0x02)     /*!< Stop Generation */
01382 #define I2C_CR2_START ((uint8_t)0x01)     /*!< Start Generation */
01383
01384 #define I2C_FREQR_FREQ ((uint8_t)0x3F)    /*!< Peripheral Clock Frequency */
01385
01386 #define I2C_OARL_ADD  ((uint8_t)0xFE)     /*!< Interface Address bits [7..1] */
01387 #define I2C_OARL_ADD0 ((uint8_t)0x01)     /*!< Interface Address bit0 */
01388
01389 #define I2C_OARH_ADDMODE ((uint8_t)0x80)  /*!< Addressing Mode (Slave mode) */
01390 #define I2C_OARH_ADDCONF ((uint8_t)0x40)  /*!< Address Mode Configuration */
01391 #define I2C_OARH_ADD     ((uint8_t)0x06)  /*!< Interface Address bits [9..8] */
01392
01393 #define I2C_DR_DR        ((uint8_t)0xFF)  /*!< Data Register */
01394
01395 #define I2C_SR1_TXE      ((uint8_t)0x80)  /*!< Data Register Empty (transmitters) */
01396 #define I2C_SR1_RXNE     ((uint8_t)0x40)  /*!< Data Register not Empty (receivers) */
01397 #define I2C_SR1_STOPF    ((uint8_t)0x10)  /*!< Stop detection (Slave mode) */
01398 #define I2C_SR1_ADD10    ((uint8_t)0x08)  /*!< 10-bit header sent (Master mode) */
01399 #define I2C_SR1_BTF      ((uint8_t)0x04)  /*!< Byte Transfer Finished */
01400 #define I2C_SR1_ADDR     ((uint8_t)0x02)  /*!< Address sent (master mode)/matched (slave mode) */
01401 #define I2C_SR1_SB       ((uint8_t)0x01)  /*!< Start Bit (Master mode) */
01402
01403 #define I2C_SR2_WUFH     ((uint8_t)0x20)  /*!< Wake-up from Halt */
01404 #define I2C_SR2_OVR      ((uint8_t)0x08)  /*!< Overrun/Underrun */
01405 #define I2C_SR2_AF       ((uint8_t)0x04)  /*!< Acknowledge Failure */
01406 #define I2C_SR2_ARLO     ((uint8_t)0x02)  /*!< Arbitration Lost (master mode) */
01407 #define I2C_SR2_BERR     ((uint8_t)0x01)  /*!< Bus Error */
01408
01409 #define I2C_SR3_GENCALL  ((uint8_t)0x10)  /*!< General Call Header (Slave mode) */
01410 #define I2C_SR3_TRA      ((uint8_t)0x04)  /*!< Transmitter/Receiver */
01411 #define I2C_SR3_BUSY     ((uint8_t)0x02)  /*!< Bus Busy */
01412 #define I2C_SR3_MSL      ((uint8_t)0x01)  /*!< Master/Slave */
01413
01414 #define I2C_ITR_ITBUFEN  ((uint8_t)0x04)  /*!< Buffer Interrupt Enable */
01415 #define I2C_ITR_ITEVTEN  ((uint8_t)0x02)  /*!< Event Interrupt Enable */
01416 #define I2C_ITR_ITERREN  ((uint8_t)0x01)  /*!< Error Interrupt Enable */
01417
01418 #define I2C_CCRL_CCR     ((uint8_t)0xFF)  /*!< Clock Control Register (Master mode) */
01419
01420 #define I2C_CCRH_FS      ((uint8_t)0x80)  /*!< Master Mode Selection */
01421 #define I2C_CCRH_DUTY    ((uint8_t)0x40)  /*!< Fast Mode Duty Cycle */
01422 #define I2C_CCRH_CCR     ((uint8_t)0x0F)  /*!< Clock Control Register in Fast/Standard mode (Master mode) bits [11..8] */
01423
01424 #define I2C_TRISER_TRISE ((uint8_t)0x3F)  /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
01425
01426 /**
01427   * @}
01428   */
01429
01430 /*----------------------------------------------------------------------------*/
01431 /**
01432   * @brief  Interrupt Controller (ITC)
01433   */
01434
01435 typedef struct ITC_struct
01436 {
01437   __IO uint8_t ISPR1; /*!< Interrupt Software Priority register 1 */
01438   __IO uint8_t ISPR2; /*!< Interrupt Software Priority register 2 */
01439   __IO uint8_t ISPR3; /*!< Interrupt Software Priority register 3 */
01440   __IO uint8_t ISPR4; /*!< Interrupt Software Priority register 4 */
01441   __IO uint8_t ISPR5; /*!< Interrupt Software Priority register 5 */
01442   __IO uint8_t ISPR6; /*!< Interrupt Software Priority register 6 */
01443   __IO uint8_t ISPR7; /*!< Interrupt Software Priority register 7 */
01444   __IO uint8_t ISPR8; /*!< Interrupt Software Priority register 8 */
01445 }
01446 ITC_TypeDef;
01447
01448 /** @addtogroup ITC_Registers_Reset_Value
01449   * @{
01450   */
01451
01452 #define ITC_SPRX_RESET_VALUE ((uint8_t)0xFF) /*!< Reset value of Software Priority registers */
01453
01454 /**
01455   * @}
01456   */
01457
01458 /** @addtogroup CPU_Registers_Bits_Definition
01459   * @{
01460   */
01461
01462 #define CPU_CC_I1I0 ((uint8_t)0x28) /*!< Condition Code register, I1 and I0 bits mask */
01463
01464 /**
01465   * @}
01466   */
01467
01468 /*----------------------------------------------------------------------------*/
01469 /**
01470   * @brief  External Interrupt Controller (EXTI)
01471   */
01472
01473 typedef struct EXTI_struct
01474 {
01475   __IO uint8_t CR1; /*!< External Interrupt Control Register for PORTA to PORTD */
01476   __IO uint8_t CR2; /*!< External Interrupt Control Register for PORTE and TLI */
01477 }
01478 EXTI_TypeDef;
01479
01480 /** @addtogroup EXTI_Registers_Reset_Value
01481   * @{
01482   */
01483
01484 #define EXTI_CR1_RESET_VALUE ((uint8_t)0x00)
01485 #define EXTI_CR2_RESET_VALUE ((uint8_t)0x00)
01486
01487 /**
01488   * @}
01489   */
01490
01491 /** @addtogroup EXTI_Registers_Bits_Definition
01492   * @{
01493   */
01494
01495 #define EXTI_CR1_PDIS ((uint8_t)0xC0) /*!< PORTD external interrupt sensitivity bits mask */
01496 #define EXTI_CR1_PCIS ((uint8_t)0x30) /*!< PORTC external interrupt sensitivity bits mask */
01497 #define EXTI_CR1_PBIS ((uint8_t)0x0C) /*!< PORTB external interrupt sensitivity bits mask */
01498 #define EXTI_CR1_PAIS ((uint8_t)0x03) /*!< PORTA external interrupt sensitivity bits mask */
01499
01500 #define EXTI_CR2_TLIS ((uint8_t)0x04) /*!< Top level interrupt sensitivity bit mask */
01501 #define EXTI_CR2_PEIS ((uint8_t)0x03) /*!< PORTE external interrupt sensitivity bits mask */
01502
01503 /**
01504   * @}
01505   */
01506
01507
01508
01509 /*----------------------------------------------------------------------------*/
01510 /**
01511   * @brief  FLASH program and Data memory (FLASH)
01512   */
01513
01514 typedef struct FLASH_struct
01515 {
01516   __IO uint8_t CR1;       /*!< Flash control register 1 */
01517   __IO uint8_t CR2;       /*!< Flash control register 2 */
01518   __IO uint8_t NCR2;      /*!< Flash complementary control register 2 */
01519   __IO uint8_t FPR;       /*!< Flash protection register */
01520   __IO uint8_t NFPR;      /*!< Flash complementary protection register */
01521   __IO uint8_t IAPSR;     /*!< Flash in-application programming status register */
01522   uint8_t RESERVED1;      /*!< Reserved byte */
01523   uint8_t RESERVED2;      /*!< Reserved byte */
01524   __IO uint8_t PUKR;      /*!< Flash program memory unprotection register */
01525   uint8_t RESERVED3;      /*!< Reserved byte */
01526   __IO uint8_t DUKR;      /*!< Data EEPROM unprotection register */
01527 }
01528 FLASH_TypeDef;
01529
01530 /** @addtogroup FLASH_Registers_Reset_Value
01531   * @{
01532   */
01533
01534 #define FLASH_CR1_RESET_VALUE   ((uint8_t)0x00)
01535 #define FLASH_CR2_RESET_VALUE   ((uint8_t)0x00)
01536 #define FLASH_NCR2_RESET_VALUE  ((uint8_t)0xFF)
01537 #define FLASH_IAPSR_RESET_VALUE ((uint8_t)0x40)
01538 #define FLASH_PUKR_RESET_VALUE  ((uint8_t)0x00)
01539 #define FLASH_DUKR_RESET_VALUE  ((uint8_t)0x00)
01540
01541 /**
01542   * @}
01543   */
01544
01545 /** @addtogroup FLASH_Registers_Bits_Definition
01546   * @{
01547   */
01548
01549 #define FLASH_CR1_HALT        ((uint8_t)0x08) /*!< Standby in Halt mode mask */
01550 #define FLASH_CR1_AHALT       ((uint8_t)0x04) /*!< Standby in Active Halt mode mask */
01551 #define FLASH_CR1_IE          ((uint8_t)0x02) /*!< Flash Interrupt enable mask */
01552 #define FLASH_CR1_FIX         ((uint8_t)0x01) /*!< Fix programming time mask */
01553
01554 #define FLASH_CR2_OPT         ((uint8_t)0x80) /*!< Select option byte mask */
01555 #define FLASH_CR2_WPRG        ((uint8_t)0x40) /*!< Word Programming mask */
01556 #define FLASH_CR2_ERASE       ((uint8_t)0x20) /*!< Erase block mask */
01557 #define FLASH_CR2_FPRG        ((uint8_t)0x10) /*!< Fast programming mode mask */
01558 #define FLASH_CR2_PRG         ((uint8_t)0x01) /*!< Program block mask */
01559
01560 #define FLASH_NCR2_NOPT       ((uint8_t)0x80) /*!< Select option byte mask */
01561 #define FLASH_NCR2_NWPRG      ((uint8_t)0x40) /*!< Word Programming mask */
01562 #define FLASH_NCR2_NERASE     ((uint8_t)0x20) /*!< Erase block mask */
01563 #define FLASH_NCR2_NFPRG      ((uint8_t)0x10) /*!< Fast programming mode mask */
01564 #define FLASH_NCR2_NPRG       ((uint8_t)0x01) /*!< Program block mask */
01565
01566 #define FLASH_IAPSR_HVOFF     ((uint8_t)0x40) /*!< End of high voltage flag mask */
01567 #define FLASH_IAPSR_DUL       ((uint8_t)0x08) /*!< Data EEPROM unlocked flag mask */
01568 #define FLASH_IAPSR_EOP       ((uint8_t)0x04) /*!< End of operation flag mask */
01569 #define FLASH_IAPSR_PUL       ((uint8_t)0x02) /*!< Flash Program memory unlocked flag mask */
01570 #define FLASH_IAPSR_WR_PG_DIS ((uint8_t)0x01) /*!< Write attempted to protected page mask */
01571
01572 #define FLASH_PUKR_PUK        ((uint8_t)0xFF) /*!< Flash Program memory unprotection mask */
01573
01574 #define FLASH_DUKR_DUK        ((uint8_t)0xFF) /*!< Data EEPROM unprotection mask */
01575
01576 /**
01577   * @}
01578   */
01579
01580 /*----------------------------------------------------------------------------*/
01581 /**
01582   * @brief  Option Bytes (OPT)
01583   */
01584 typedef struct OPT_struct
01585 {
01586   __IO uint8_t OPT0;  /*!< Option byte 0: Read-out protection (not accessible in IAP mode) */
01587   __IO uint8_t OPT1;  /*!< Option byte 1: User boot code */
01588   __IO uint8_t NOPT1; /*!< Complementary Option byte 1 */
01589   __IO uint8_t OPT2;  /*!< Option byte 2: Alternate function remapping */
01590   __IO uint8_t NOPT2; /*!< Complementary Option byte 2 */
01591   __IO uint8_t OPT3;  /*!< Option byte 3: Watchdog option */
01592   __IO uint8_t NOPT3; /*!< Complementary Option byte 3 */
01593   __IO uint8_t OPT4;  /*!< Option byte 4: Clock option */
01594   __IO uint8_t NOPT4; /*!< Complementary Option byte 4 */
01595   __IO uint8_t OPT5;  /*!< Option byte 5: HSE clock startup */
01596   __IO uint8_t NOPT5; /*!< Complementary Option byte 5 */
01597   uint8_t RESERVED1;  /*!< Reserved Option byte*/
01598   uint8_t RESERVED2; /*!< Reserved Option byte*/
01599   __IO uint8_t OPT7;  /*!< Option byte 7: flash wait states */
01600   __IO uint8_t NOPT7; /*!< Complementary Option byte 7 */
01601 }
01602 OPT_TypeDef;
01603
01604 /*----------------------------------------------------------------------------*/
01605 /**
01606   * @brief  Independent Watchdog (IWDG)
01607   */
01608
01609 typedef struct IWDG_struct
01610 {
01611   __IO uint8_t KR;  /*!< Key Register */
01612   __IO uint8_t PR;  /*!< Prescaler Register */
01613   __IO uint8_t RLR; /*!< Reload Register */
01614 }
01615 IWDG_TypeDef;
01616
01617 /** @addtogroup IWDG_Registers_Reset_Value
01618   * @{
01619   */
01620
01621 #define IWDG_PR_RESET_VALUE  ((uint8_t)0x00)
01622 #define IWDG_RLR_RESET_VALUE ((uint8_t)0xFF)
01623
01624 /**
01625   * @}
01626   */
01627
01628 /*----------------------------------------------------------------------------*/
01629 /**
01630   * @brief  Window Watchdog (WWDG)
01631   */
01632
01633 typedef struct WWDG_struct
01634 {
01635   __IO uint8_t CR; /*!< Control Register */
01636   __IO uint8_t WR; /*!< Window Register */
01637 }
01638 WWDG_TypeDef;
01639
01640 /** @addtogroup WWDG_Registers_Reset_Value
01641   * @{
01642   */
01643
01644 #define WWDG_CR_RESET_VALUE ((uint8_t)0x7F)
01645 #define WWDG_WR_RESET_VALUE ((uint8_t)0x7F)
01646
01647 /**
01648   * @}
01649   */
01650
01651 /** @addtogroup WWDG_Registers_Bits_Definition
01652   * @{
01653   */
01654
01655 #define WWDG_CR_WDGA ((uint8_t)0x80) /*!< WDGA bit mask */
01656 #define WWDG_CR_T6   ((uint8_t)0x40) /*!< T6 bit mask */
01657 #define WWDG_CR_T    ((uint8_t)0x7F) /*!< T bits mask */
01658
01659 #define WWDG_WR_MSB  ((uint8_t)0x80) /*!< MSB bit mask */
01660 #define WWDG_WR_W    ((uint8_t)0x7F) /*!< W bits mask */
01661
01662 /**
01663   * @}
01664   */
01665
01666 /*----------------------------------------------------------------------------*/
01667 /**
01668   * @brief  Reset Controller (RST)
01669   */
01670
01671 typedef struct RST_struct
01672 {
01673   __IO uint8_t SR; /*!< Reset status register */
01674 }
01675 RST_TypeDef;
01676
01677 /** @addtogroup RST_Registers_Bits_Definition
01678   * @{
01679   */
01680
01681 #define RST_SR_EMCF   ((uint8_t)0x10) /*!< EMC reset flag bit mask */
01682 #define RST_SR_SWIMF  ((uint8_t)0x08) /*!< SWIM reset flag bit mask */
01683 #define RST_SR_ILLOPF ((uint8_t)0x04) /*!< Illegal opcode reset flag bit mask */
01684 #define RST_SR_IWDGF  ((uint8_t)0x02) /*!< IWDG reset flag bit mask */
01685 #define RST_SR_WWDGF  ((uint8_t)0x01) /*!< WWDG reset flag bit mask */
01686
01687 /**
01688   * @}
01689   */
01690
01691 /*----------------------------------------------------------------------------*/
01692 /**
01693   * @brief  Serial Peripheral Interface (SPI)
01694   */
01695
01696 typedef struct SPI_struct
01697 {
01698   __IO uint8_t CR1;    /*!< SPI control register 1 */
01699   __IO uint8_t CR2;    /*!< SPI control register 2 */
01700   __IO uint8_t ICR;    /*!< SPI interrupt control register */
01701   __IO uint8_t SR;     /*!< SPI status register */
01702   __IO uint8_t DR;     /*!< SPI data I/O register */
01703   __IO uint8_t CRCPR;  /*!< SPI CRC polynomial register */
01704   __IO uint8_t RXCRCR; /*!< SPI Rx CRC register */
01705   __IO uint8_t TXCRCR; /*!< SPI Tx CRC register */
01706 }
01707 SPI_TypeDef;
01708
01709 /** @addtogroup SPI_Registers_Reset_Value
01710   * @{
01711   */
01712
01713 #define SPI_CR1_RESET_VALUE    ((uint8_t)0x00) /*!< Control Register 1 reset value */
01714 #define SPI_CR2_RESET_VALUE    ((uint8_t)0x00) /*!< Control Register 2 reset value */
01715 #define SPI_ICR_RESET_VALUE    ((uint8_t)0x00) /*!< Interrupt Control Register reset value */
01716 #define SPI_SR_RESET_VALUE     ((uint8_t)0x02) /*!< Status Register reset value */
01717 #define SPI_DR_RESET_VALUE     ((uint8_t)0x00) /*!< Data Register reset value */
01718 #define SPI_CRCPR_RESET_VALUE  ((uint8_t)0x07) /*!< Polynomial Register reset value */
01719 #define SPI_RXCRCR_RESET_VALUE ((uint8_t)0x00) /*!< RX CRC Register reset value */
01720 #define SPI_TXCRCR_RESET_VALUE ((uint8_t)0x00) /*!< TX CRC Register reset value */
01721
01722 /**
01723   * @}
01724   */
01725
01726 /** @addtogroup SPI_Registers_Bits_Definition
01727   * @{
01728   */
01729
01730 #define SPI_CR1_LSBFIRST ((uint8_t)0x80) /*!< Frame format mask */
01731 #define SPI_CR1_SPE      ((uint8_t)0x40) /*!< Enable bits mask */
01732 #define SPI_CR1_BR       ((uint8_t)0x38) /*!< Baud rate control mask */
01733 #define SPI_CR1_MSTR     ((uint8_t)0x04) /*!< Master Selection mask */
01734 #define SPI_CR1_CPOL     ((uint8_t)0x02) /*!< Clock Polarity mask */
01735 #define SPI_CR1_CPHA     ((uint8_t)0x01) /*!< Clock Phase mask */
01736
01737 #define SPI_CR2_BDM      ((uint8_t)0x80) /*!< Bi-directional data mode enable mask */
01738 #define SPI_CR2_BDOE     ((uint8_t)0x40) /*!< Output enable in bi-directional mode mask */
01739 #define SPI_CR2_CRCEN    ((uint8_t)0x20) /*!< Hardware CRC calculation enable mask */
01740 #define SPI_CR2_CRCNEXT  ((uint8_t)0x10) /*!< Transmit CRC next mask */
01741 #define SPI_CR2_RXONLY   ((uint8_t)0x04) /*!< Receive only mask */
01742 #define SPI_CR2_SSM      ((uint8_t)0x02) /*!< Software slave management mask */
01743 #define SPI_CR2_SSI      ((uint8_t)0x01) /*!< Internal slave select mask */
01744
01745 #define SPI_ICR_TXEI     ((uint8_t)0x80) /*!< Tx buffer empty interrupt enable mask */
01746 #define SPI_ICR_RXEI     ((uint8_t)0x40) /*!< Rx buffer empty interrupt enable mask */
01747 #define SPI_ICR_ERRIE    ((uint8_t)0x20) /*!< Error interrupt enable mask */
01748 #define SPI_ICR_WKIE     ((uint8_t)0x10) /*!< Wake-up interrupt enable mask */
01749
01750 #define SPI_SR_BSY       ((uint8_t)0x80) /*!< Busy flag */
01751 #define SPI_SR_OVR       ((uint8_t)0x40) /*!< Overrun flag */
01752 #define SPI_SR_MODF      ((uint8_t)0x20) /*!< Mode fault */
01753 #define SPI_SR_CRCERR    ((uint8_t)0x10) /*!< CRC error flag */
01754 #define SPI_SR_WKUP      ((uint8_t)0x08) /*!< Wake-Up flag */
01755 #define SPI_SR_TXE       ((uint8_t)0x02) /*!< Transmit buffer empty */
01756 #define SPI_SR_RXNE      ((uint8_t)0x01) /*!< Receive buffer not empty */
01757
01758 /**
01759   * @}
01760   */
01761
01762 /*----------------------------------------------------------------------------*/
01763 /**
01764   * @brief  Universal Synchronous Asynchronous Receiver Transmitter (UART1)
01765   */
01766
01767 typedef struct UART1_struct
01768 {
01769   __IO uint8_t SR;   /*!< UART1 status register */
01770   __IO uint8_t DR;   /*!< UART1 data register */
01771   __IO uint8_t BRR1; /*!< UART1 baud rate register */
01772   __IO uint8_t BRR2; /*!< UART1 DIV mantissa[11:8] SCIDIV fraction */
01773   __IO uint8_t CR1;  /*!< UART1 control register 1 */
01774   __IO uint8_t CR2;  /*!< UART1 control register 2 */
01775   __IO uint8_t CR3;  /*!< UART1 control register 3 */
01776   __IO uint8_t CR4;  /*!< UART1 control register 4 */
01777   __IO uint8_t CR5;  /*!< UART1 control register 5 */
01778   __IO uint8_t GTR;  /*!< UART1 guard time register */
01779   __IO uint8_t PSCR; /*!< UART1 prescaler register */
01780 }
01781 UART1_TypeDef;
01782
01783 /** @addtogroup UART1_Registers_Reset_Value
01784   * @{
01785   */
01786
01787 #define UART1_SR_RESET_VALUE   ((uint8_t)0xC0)
01788 #define UART1_BRR1_RESET_VALUE ((uint8_t)0x00)
01789 #define UART1_BRR2_RESET_VALUE ((uint8_t)0x00)
01790 #define UART1_CR1_RESET_VALUE  ((uint8_t)0x00)
01791 #define UART1_CR2_RESET_VALUE  ((uint8_t)0x00)
01792 #define UART1_CR3_RESET_VALUE  ((uint8_t)0x00)
01793 #define UART1_CR4_RESET_VALUE  ((uint8_t)0x00)
01794 #define UART1_CR5_RESET_VALUE  ((uint8_t)0x00)
01795 #define UART1_GTR_RESET_VALUE  ((uint8_t)0x00)
01796 #define UART1_PSCR_RESET_VALUE ((uint8_t)0x00)
01797
01798 /**
01799   * @}
01800   */
01801
01802 /** @addtogroup UART1_Registers_Bits_Definition
01803   * @{
01804   */
01805
01806 #define UART1_SR_TXE   ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */
01807 #define UART1_SR_TC    ((uint8_t)0x40) /*!< Transmission Complete mask */
01808 #define UART1_SR_RXNE  ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */
01809 #define UART1_SR_IDLE  ((uint8_t)0x10) /*!< IDLE line detected mask */
01810 #define UART1_SR_OR   ((uint8_t)0x08) /*!< OverRun error mask */
01811 #define UART1_SR_NF    ((uint8_t)0x04) /*!< Noise Flag mask */
01812 #define UART1_SR_FE    ((uint8_t)0x02) /*!< Framing Error mask */
01813 #define UART1_SR_PE    ((uint8_t)0x01) /*!< Parity Error mask */
01814
01815 #define UART1_BRR1_DIVM  ((uint8_t)0xFF) /*!< LSB mantissa of UART1DIV [7:0] mask */
01816
01817 #define UART1_BRR2_DIVM  ((uint8_t)0xF0) /*!< MSB mantissa of UART1DIV [11:8] mask */
01818 #define UART1_BRR2_DIVF  ((uint8_t)0x0F) /*!< Fraction bits of UART1DIV [3:0] mask */
01819
01820 #define UART1_CR1_R8      ((uint8_t)0x80) /*!< Receive Data bit 8 */
01821 #define UART1_CR1_T8      ((uint8_t)0x40) /*!< Transmit data bit 8 */
01822 #define UART1_CR1_UARTD   ((uint8_t)0x20) /*!< UART1 Disable (for low power consumption) */
01823 #define UART1_CR1_M       ((uint8_t)0x10) /*!< Word length mask */
01824 #define UART1_CR1_WAKE    ((uint8_t)0x08) /*!< Wake-up method mask */
01825 #define UART1_CR1_PCEN    ((uint8_t)0x04) /*!< Parity Control Enable mask */
01826 #define UART1_CR1_PS      ((uint8_t)0x02) /*!< UART1 Parity Selection */
01827 #define UART1_CR1_PIEN    ((uint8_t)0x01) /*!< UART1 Parity Interrupt Enable mask */
01828
01829 #define UART1_CR2_TIEN    ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */
01830 #define UART1_CR2_TCIEN   ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable mask */
01831 #define UART1_CR2_RIEN    ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */
01832 #define UART1_CR2_ILIEN   ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */
01833 #define UART1_CR2_TEN     ((uint8_t)0x08) /*!< Transmitter Enable mask */
01834 #define UART1_CR2_REN     ((uint8_t)0x04) /*!< Receiver Enable mask */
01835 #define UART1_CR2_RWU     ((uint8_t)0x02) /*!< Receiver Wake-Up mask */
01836 #define UART1_CR2_SBK     ((uint8_t)0x01) /*!< Send Break mask */
01837
01838 #define UART1_CR3_LINEN   ((uint8_t)0x40) /*!< Alternate Function output mask */
01839 #define UART1_CR3_STOP    ((uint8_t)0x30) /*!< STOP bits [1:0] mask */
01840 #define UART1_CR3_CKEN    ((uint8_t)0x08) /*!< Clock Enable mask */
01841 #define UART1_CR3_CPOL    ((uint8_t)0x04) /*!< Clock Polarity mask */
01842 #define UART1_CR3_CPHA    ((uint8_t)0x02) /*!< Clock Phase mask */
01843 #define UART1_CR3_LBCL    ((uint8_t)0x01) /*!< Last Bit Clock pulse mask */
01844
01845 #define UART1_CR4_LBDIEN  ((uint8_t)0x40) /*!< LIN Break Detection Interrupt Enable mask */
01846 #define UART1_CR4_LBDL    ((uint8_t)0x20) /*!< LIN Break Detection Length mask */
01847 #define UART1_CR4_LBDF    ((uint8_t)0x10) /*!< LIN Break Detection Flag mask */
01848 #define UART1_CR4_ADD     ((uint8_t)0x0F) /*!< Address of the UART1 node mask */
01849
01850 #define UART1_CR5_SCEN    ((uint8_t)0x20) /*!< Smart Card Enable mask */
01851 #define UART1_CR5_NACK    ((uint8_t)0x10) /*!< Smart Card Nack Enable mask */
01852 #define UART1_CR5_HDSEL   ((uint8_t)0x08) /*!< Half-Duplex Selection mask */
01853 #define UART1_CR5_IRLP    ((uint8_t)0x04) /*!< Irda Low Power Selection mask */
01854 #define UART1_CR5_IREN    ((uint8_t)0x02) /*!< Irda Enable mask */
01855
01856 /**
01857   * @}
01858   */
01859
01860 /*----------------------------------------------------------------------------*/
01861 /**
01862   * @brief  Universal Synchronous Asynchronous Receiver Transmitter (UART2)
01863   */
01864
01865 typedef struct UART2_struct
01866 {
01867   __IO uint8_t SR;   /*!< UART1 status register */
01868   __IO uint8_t DR;   /*!< UART1 data register */
01869   __IO uint8_t BRR1; /*!< UART1 baud rate register */
01870   __IO uint8_t BRR2; /*!< UART1 DIV mantissa[11:8] SCIDIV fraction */
01871   __IO uint8_t CR1;  /*!< UART1 control register 1 */
01872   __IO uint8_t CR2;  /*!< UART1 control register 2 */
01873   __IO uint8_t CR3;  /*!< UART1 control register 3 */
01874   __IO uint8_t CR4;  /*!< UART1 control register 4 */
01875   __IO uint8_t CR5;  /*!< UART1 control register 5 */
01876         __IO uint8_t CR6;  /*!< UART1 control register 6 */
01877   __IO uint8_t GTR;  /*!< UART1 guard time register */
01878   __IO uint8_t PSCR; /*!< UART1 prescaler register */
01879 }
01880 UART2_TypeDef;
01881
01882 /** @addtogroup UART2_Registers_Reset_Value
01883   * @{
01884   */
01885
01886 #define UART2_SR_RESET_VALUE   ((uint8_t)0xC0)
01887 #define UART2_BRR1_RESET_VALUE ((uint8_t)0x00)
01888 #define UART2_BRR2_RESET_VALUE ((uint8_t)0x00)
01889 #define UART2_CR1_RESET_VALUE  ((uint8_t)0x00)
01890 #define UART2_CR2_RESET_VALUE  ((uint8_t)0x00)
01891 #define UART2_CR3_RESET_VALUE  ((uint8_t)0x00)
01892 #define UART2_CR4_RESET_VALUE  ((uint8_t)0x00)
01893 #define UART2_CR5_RESET_VALUE  ((uint8_t)0x00)
01894 #define UART2_CR6_RESET_VALUE  ((uint8_t)0x00)
01895 #define UART2_GTR_RESET_VALUE  ((uint8_t)0x00)
01896 #define UART2_PSCR_RESET_VALUE ((uint8_t)0x00)
01897
01898 /**
01899   * @}
01900   */
01901
01902 /** @addtogroup UART2_Registers_Bits_Definition
01903   * @{
01904   */
01905
01906 #define UART2_SR_TXE   ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */
01907 #define UART2_SR_TC    ((uint8_t)0x40) /*!< Transmission Complete mask */
01908 #define UART2_SR_RXNE  ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */
01909 #define UART2_SR_IDLE  ((uint8_t)0x10) /*!< IDLE line detected mask */
01910 #define UART2_SR_OR    ((uint8_t)0x08) /*!< OverRun error mask */
01911 #define UART2_SR_NF    ((uint8_t)0x04) /*!< Noise Flag mask */
01912 #define UART2_SR_FE    ((uint8_t)0x02) /*!< Framing Error mask */
01913 #define UART2_SR_PE    ((uint8_t)0x01) /*!< Parity Error mask */
01914
01915 #define UART2_BRR1_DIVM  ((uint8_t)0xFF) /*!< LSB mantissa of UART2DIV [7:0] mask */
01916
01917 #define UART2_BRR2_DIVM  ((uint8_t)0xF0) /*!< MSB mantissa of UART2DIV [11:8] mask */
01918 #define UART2_BRR2_DIVF  ((uint8_t)0x0F) /*!< Fraction bits of UART2DIV [3:0] mask */
01919
01920 #define UART2_CR1_R8      ((uint8_t)0x80) /*!< Receive Data bit 8 */
01921 #define UART2_CR1_T8      ((uint8_t)0x40) /*!< Transmit data bit 8 */
01922 #define UART2_CR1_UARTD   ((uint8_t)0x20) /*!< UART2 Disable (for low power consumption) */
01923 #define UART2_CR1_M       ((uint8_t)0x10) /*!< Word length mask */
01924 #define UART2_CR1_WAKE    ((uint8_t)0x08) /*!< Wake-up method mask */
01925 #define UART2_CR1_PCEN    ((uint8_t)0x04) /*!< Parity Control Enable mask */
01926 #define UART2_CR1_PS      ((uint8_t)0x02) /*!< UART2 Parity Selection */
01927 #define UART2_CR1_PIEN    ((uint8_t)0x01) /*!< UART2 Parity Interrupt Enable mask */
01928
01929 #define UART2_CR2_TIEN    ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */
01930 #define UART2_CR2_TCIEN   ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable mask */
01931 #define UART2_CR2_RIEN    ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */
01932 #define UART2_CR2_ILIEN   ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */
01933 #define UART2_CR2_TEN     ((uint8_t)0x08) /*!< Transmitter Enable mask */
01934 #define UART2_CR2_REN     ((uint8_t)0x04) /*!< Receiver Enable mask */
01935 #define UART2_CR2_RWU     ((uint8_t)0x02) /*!< Receiver Wake-Up mask */
01936 #define UART2_CR2_SBK     ((uint8_t)0x01) /*!< Send Break mask */
01937
01938 #define UART2_CR3_LINEN   ((uint8_t)0x40) /*!< Alternate Function output mask */
01939 #define UART2_CR3_STOP    ((uint8_t)0x30) /*!< STOP bits [1:0] mask */
01940 #define UART2_CR3_CKEN    ((uint8_t)0x08) /*!< Clock Enable mask */
01941 #define UART2_CR3_CPOL    ((uint8_t)0x04) /*!< Clock Polarity mask */
01942 #define UART2_CR3_CPHA    ((uint8_t)0x02) /*!< Clock Phase mask */
01943 #define UART2_CR3_LBCL    ((uint8_t)0x01) /*!< Last Bit Clock pulse mask */
01944
01945 #define UART2_CR4_LBDIEN  ((uint8_t)0x40) /*!< LIN Break Detection Interrupt Enable mask */
01946 #define UART2_CR4_LBDL    ((uint8_t)0x20) /*!< LIN Break Detection Length mask */
01947 #define UART2_CR4_LBDF    ((uint8_t)0x10) /*!< LIN Break Detection Flag mask */
01948 #define UART2_CR4_ADD     ((uint8_t)0x0F) /*!< Address of the UART2 node mask */
01949
01950 #define UART2_CR5_SCEN    ((uint8_t)0x20) /*!< Smart Card Enable mask */
01951 #define UART2_CR5_NACK    ((uint8_t)0x10) /*!< Smart Card Nack Enable mask */
01952 #define UART2_CR5_IRLP    ((uint8_t)0x04) /*!< Irda Low Power Selection mask */
01953 #define UART2_CR5_IREN    ((uint8_t)0x02) /*!< Irda Enable mask */
01954
01955 #define UART2_CR6_LDUM    ((uint8_t)0x80) /*!< LIN Divider Update Method */
01956 #define UART2_CR6_LSLV    ((uint8_t)0x20) /*!< LIN Slave Enable */
01957 #define UART2_CR6_LASE    ((uint8_t)0x10) /*!< LIN Auto synchronization Enable */
01958 #define UART2_CR6_LHDIEN  ((uint8_t)0x04) /*!< LIN Header Detection Interrupt Enable */
01959 #define UART2_CR6_LHDF    ((uint8_t)0x02) /*!< LIN Header Detection Flag */
01960 #define UART2_CR6_LSF     ((uint8_t)0x01) /*!< LIN Synch Field */
01961
01962 /**
01963   * @}
01964   */
01965
01966
01967 /*----------------------------------------------------------------------------*/
01968 /**
01969   * @brief  LIN Universal Asynchronous Receiver Transmitter (UART3)
01970   */
01971
01972 typedef struct UART3_struct
01973 {
01974   __IO uint8_t SR;       /*!< status register */
01975   __IO uint8_t DR;       /*!< data register */
01976   __IO uint8_t BRR1;     /*!< baud rate register */
01977   __IO uint8_t BRR2;     /*!< DIV mantissa[11:8] SCIDIV fraction */
01978   __IO uint8_t CR1;      /*!< control register 1 */
01979   __IO uint8_t CR2;      /*!< control register 2 */
01980   __IO uint8_t CR3;      /*!< control register 3 */
01981   __IO uint8_t CR4;      /*!< control register 4 */
01982   uint8_t RESERVED; /*!< Reserved byte */
01983   __IO uint8_t CR6;      /*!< control register 5 */
01984 }
01985 UART3_TypeDef;
01986
01987 /** @addtogroup UART3_Registers_Reset_Value
01988   * @{
01989   */
01990
01991 #define UART3_SR_RESET_VALUE   ((uint8_t)0xC0)
01992 #define UART3_BRR1_RESET_VALUE ((uint8_t)0x00)
01993 #define UART3_BRR2_RESET_VALUE ((uint8_t)0x00)
01994 #define UART3_CR1_RESET_VALUE  ((uint8_t)0x00)
01995 #define UART3_CR2_RESET_VALUE  ((uint8_t)0x00)
01996 #define UART3_CR3_RESET_VALUE  ((uint8_t)0x00)
01997 #define UART3_CR4_RESET_VALUE  ((uint8_t)0x00)
01998 #define UART3_CR6_RESET_VALUE  ((uint8_t)0x00)
01999
02000 /**
02001   * @}
02002   */
02003
02004 /** @addtogroup UART3_Registers_Bits_Definition
02005   * @{
02006   */
02007
02008 #define UART3_SR_TXE      ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */
02009 #define UART3_SR_TC       ((uint8_t)0x40) /*!< Transmission Complete mask */
02010 #define UART3_SR_RXNE     ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */
02011 #define UART3_SR_IDLE     ((uint8_t)0x10) /*!< IDLE line detected mask */
02012 #define UART3_SR_OR       ((uint8_t)0x08) /*!< OverRun error mask */
02013 #define UART3_SR_NF       ((uint8_t)0x04) /*!< Noise Flag mask */
02014 #define UART3_SR_FE       ((uint8_t)0x02) /*!< Framing Error mask */
02015 #define UART3_SR_PE       ((uint8_t)0x01) /*!< Parity Error mask */
02016
02017 #define UART3_BRR1_DIVM   ((uint8_t)0xFF) /*!< LSB mantissa of UARTDIV [7:0] mask */
02018
02019 #define UART3_BRR2_DIVM   ((uint8_t)0xF0) /*!< MSB mantissa of UARTDIV [11:8] mask */
02020 #define UART3_BRR2_DIVF   ((uint8_t)0x0F) /*!< Fraction bits of UARTDIV [3:0] mask */
02021
02022 #define UART3_CR1_R8      ((uint8_t)0x80) /*!< Receive Data bit 8 */
02023 #define UART3_CR1_T8      ((uint8_t)0x40) /*!< Transmit data bit 8 */
02024 #define UART3_CR1_UARTD   ((uint8_t)0x20) /*!< UART Disable (for low power consumption) */
02025 #define UART3_CR1_M       ((uint8_t)0x10) /*!< Word length mask */
02026 #define UART3_CR1_WAKE    ((uint8_t)0x08) /*!< Wake-up method mask */
02027 #define UART3_CR1_PCEN    ((uint8_t)0x04) /*!< Parity control enable mask */
02028 #define UART3_CR1_PS      ((uint8_t)0x02) /*!< Parity selection bit mask */
02029 #define UART3_CR1_PIEN    ((uint8_t)0x01) /*!< Parity interrupt enable bit mask */
02030
02031 #define UART3_CR2_TIEN    ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */
02032 #define UART3_CR2_TCIEN   ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable mask */
02033 #define UART3_CR2_RIEN    ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */
02034 #define UART3_CR2_ILIEN   ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */
02035 #define UART3_CR2_TEN     ((uint8_t)0x08) /*!< Transmitter Enable mask */
02036 #define UART3_CR2_REN     ((uint8_t)0x04) /*!< Receiver Enable mask */
02037 #define UART3_CR2_RWU     ((uint8_t)0x02) /*!< Receiver Wake-Up mask */
02038 #define UART3_CR2_SBK     ((uint8_t)0x01) /*!< Send Break mask */
02039
02040 #define UART3_CR3_LINEN   ((uint8_t)0x40) /*!< Alternate Function output mask */
02041 #define UART3_CR3_STOP    ((uint8_t)0x30) /*!< STOP bits [1:0] mask */
02042
02043 #define UART3_CR4_LBDIEN  ((uint8_t)0x40) /*!< LIN Break Detection Interrupt Enable mask */
02044 #define UART3_CR4_LBDL    ((uint8_t)0x20) /*!< LIN Break Detection Length mask */
02045 #define UART3_CR4_LBDF    ((uint8_t)0x10) /*!< LIN Break Detection Flag mask */
02046 #define UART3_CR4_ADD     ((uint8_t)0x0F) /*!< Address of the UART3 node mask */
02047
02048 #define UART3_CR6_LDUM    ((uint8_t)0x80) /*!< LIN Divider Update Method */
02049 #define UART3_CR6_LSLV    ((uint8_t)0x20) /*!< LIN Slave Enable */
02050 #define UART3_CR6_LASE    ((uint8_t)0x10) /*!< LIN Auto synchronization Enable */
02051 #define UART3_CR6_LHDIEN  ((uint8_t)0x04) /*!< LIN Header Detection Interrupt Enable */
02052 #define UART3_CR6_LHDF    ((uint8_t)0x02) /*!< LIN Header Detection Flag */
02053 #define UART3_CR6_LSF     ((uint8_t)0x01) /*!< LIN Synch Field */
02054
02055 /**
02056   * @}
02057   */
02058
02059 /*----------------------------------------------------------------------------*/
02060 /**
02061   * @brief Universal Synchronous Asynchronous Receiver Transmitter (UART4)
02062   */
02063 #if defined(STM8AF622x)
02064 typedef struct UART4_struct
02065 {
02066   __IO uint8_t SR;   /*!< UART4 status register */
02067   __IO uint8_t DR;   /*!< UART4 data register */
02068   __IO uint8_t BRR1; /*!< UART4 baud rate register */
02069   __IO uint8_t BRR2; /*!< UART4 DIV mantissa[11:8] SCIDIV fraction */
02070   __IO uint8_t CR1;  /*!< UART4 control register 1 */
02071   __IO uint8_t CR2;  /*!< UART4 control register 2 */
02072   __IO uint8_t CR3;  /*!< UART4 control register 3 */
02073   __IO uint8_t CR4;  /*!< UART4 control register 4 */
02074   __IO uint8_t CR5;  /*!< UART4 control register 5 */
02075   __IO uint8_t CR6;  /*!< UART4 control register 6 */
02076   __IO uint8_t GTR;  /*!< UART4 guard time register */
02077   __IO uint8_t PSCR; /*!< UART4 prescaler register */
02078 }
02079 UART4_TypeDef;
02080
02081 /** @addtogroup UART4_Registers_Reset_Value
02082   * @{
02083   */
02084
02085 #define UART4_SR_RESET_VALUE   ((uint8_t)0xC0)
02086 #define UART4_BRR1_RESET_VALUE ((uint8_t)0x00)
02087 #define UART4_BRR2_RESET_VALUE ((uint8_t)0x00)
02088 #define UART4_CR1_RESET_VALUE  ((uint8_t)0x00)
02089 #define UART4_CR2_RESET_VALUE  ((uint8_t)0x00)
02090 #define UART4_CR3_RESET_VALUE  ((uint8_t)0x00)
02091 #define UART4_CR4_RESET_VALUE  ((uint8_t)0x00)
02092 #define UART4_CR5_RESET_VALUE  ((uint8_t)0x00)
02093 #define UART4_CR6_RESET_VALUE  ((uint8_t)0x00)
02094 #define UART4_GTR_RESET_VALUE  ((uint8_t)0x00)
02095 #define UART4_PSCR_RESET_VALUE ((uint8_t)0x00)
02096
02097 /**
02098   * @}
02099   */
02100
02101 /** @addtogroup UART4_Registers_Bits_Definition
02102   * @{
02103   */
02104
02105 #define UART4_SR_TXE   ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */
02106 #define UART4_SR_TC    ((uint8_t)0x40) /*!< Transmission Complete mask */
02107 #define UART4_SR_RXNE  ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */
02108 #define UART4_SR_IDLE  ((uint8_t)0x10) /*!< IDLE line detected mask */
02109 #define UART4_SR_OR    ((uint8_t)0x08) /*!< OverRun error mask */
02110 #define UART4_SR_NF    ((uint8_t)0x04) /*!< Noise Flag mask */
02111 #define UART4_SR_FE    ((uint8_t)0x02) /*!< Framing Error mask */
02112 #define UART4_SR_PE    ((uint8_t)0x01) /*!< Parity Error mask */
02113
02114 #define UART4_BRR1_DIVM  ((uint8_t)0xFF) /*!< LSB mantissa of UART4DIV [7:0] mask */
02115
02116 #define UART4_BRR2_DIVM  ((uint8_t)0xF0) /*!< MSB mantissa of UART4DIV [11:8] mask */
02117 #define UART4_BRR2_DIVF  ((uint8_t)0x0F) /*!< Fraction bits of UART4DIV [3:0] mask */
02118
02119 #define UART4_CR1_R8      ((uint8_t)0x80) /*!< Receive Data bit 8 */
02120 #define UART4_CR1_T8      ((uint8_t)0x40) /*!< Transmit data bit 8 */
02121 #define UART4_CR1_UARTD   ((uint8_t)0x20) /*!< UART4 Disable (for low power consumption) */
02122 #define UART4_CR1_M       ((uint8_t)0x10) /*!< Word length mask */
02123 #define UART4_CR1_WAKE    ((uint8_t)0x08) /*!< Wake-up method mask */
02124 #define UART4_CR1_PCEN    ((uint8_t)0x04) /*!< Parity Control Enable mask */
02125 #define UART4_CR1_PS      ((uint8_t)0x02) /*!< UART4 Parity Selection */
02126 #define UART4_CR1_PIEN    ((uint8_t)0x01) /*!< UART4 Parity Interrupt Enable mask */
02127
02128 #define UART4_CR2_TIEN    ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */
02129 #define UART4_CR2_TCIEN   ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable mask */
02130 #define UART4_CR2_RIEN    ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */
02131 #define UART4_CR2_ILIEN   ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */
02132 #define UART4_CR2_TEN     ((uint8_t)0x08) /*!< Transmitter Enable mask */
02133 #define UART4_CR2_REN     ((uint8_t)0x04) /*!< Receiver Enable mask */
02134 #define UART4_CR2_RWU     ((uint8_t)0x02) /*!< Receiver Wake-Up mask */
02135 #define UART4_CR2_SBK     ((uint8_t)0x01) /*!< Send Break mask */
02136
02137 #define UART4_CR3_LINEN   ((uint8_t)0x40) /*!< Alternate Function output mask */
02138 #define UART4_CR3_STOP    ((uint8_t)0x30) /*!< STOP bits [1:0] mask */
02139 #define UART4_CR3_CKEN    ((uint8_t)0x08) /*!< Clock Enable mask */
02140 #define UART4_CR3_CPOL    ((uint8_t)0x04) /*!< Clock Polarity mask */
02141 #define UART4_CR3_CPHA    ((uint8_t)0x02) /*!< Clock Phase mask */
02142 #define UART4_CR3_LBCL    ((uint8_t)0x01) /*!< Last Bit Clock pulse mask */
02143
02144 #define UART4_CR4_LBDIEN  ((uint8_t)0x40) /*!< LIN Break Detection Interrupt Enable mask */
02145 #define UART4_CR4_LBDL    ((uint8_t)0x20) /*!< LIN Break Detection Length mask */
02146 #define UART4_CR4_LBDF    ((uint8_t)0x10) /*!< LIN Break Detection Flag mask */
02147 #define UART4_CR4_ADD     ((uint8_t)0x0F) /*!< Address of the UART4 node mask */
02148
02149 #define UART4_CR5_SCEN    ((uint8_t)0x20) /*!< Smart Card Enable mask */
02150 #define UART4_CR5_NACK    ((uint8_t)0x10) /*!< Smart Card Nack Enable mask */
02151 #define UART4_CR5_HDSEL   ((uint8_t)0x08) /*!< Half-Duplex Selection mask */
02152 #define UART4_CR5_IRLP    ((uint8_t)0x04) /*!< Irda Low Power Selection mask */
02153 #define UART4_CR5_IREN    ((uint8_t)0x02) /*!< Irda Enable mask */
02154
02155 #define UART4_CR6_LDUM    ((uint8_t)0x80) /*!< LIN Divider Update Method */
02156 #define UART4_CR6_LSLV    ((uint8_t)0x20) /*!< LIN Slave Enable */
02157 #define UART4_CR6_LASE    ((uint8_t)0x10) /*!< LIN Auto synchronization Enable */
02158 #define UART4_CR6_LHDIEN  ((uint8_t)0x04) /*!< LIN Header Detection Interrupt Enable */
02159 #define UART4_CR6_LHDF    ((uint8_t)0x02) /*!< LIN Header Detection Flag */
02160 #define UART4_CR6_LSF     ((uint8_t)0x01) /*!< LIN Synch Field */
02161 #endif /* STM8AF622x */
02162
02163 /**
02164   * @}
02165   */
02166
02167 /*----------------------------------------------------------------------------*/
02168
02169 /*----------------------------------------------------------------------------*/
02170 /**
02171   * @brief  Controller Area Network  (CAN)
02172   */
02173
02174 typedef struct
02175 {
02176   __IO uint8_t MCR;    /*!< CAN master control register */
02177   __IO uint8_t MSR;    /*!< CAN master status register */
02178   __IO uint8_t TSR;    /*!< CAN transmit status register */
02179   __IO uint8_t TPR;    /*!< CAN transmit priority register */
02180   __IO uint8_t RFR;    /*!< CAN receive FIFO register */
02181   __IO uint8_t IER;    /*!< CAN interrupt enable register */
02182   __IO uint8_t DGR;    /*!< CAN diagnosis register */
02183   __IO uint8_t PSR;    /*!< CAN page selection register */
02184
02185   union
02186   {
02187     struct
02188     {
02189       __IO uint8_t MCSR;
02190       __IO uint8_t MDLCR;
02191       __IO uint8_t MIDR1;
02192       __IO uint8_t MIDR2;
02193       __IO uint8_t MIDR3;
02194       __IO uint8_t MIDR4;
02195       __IO uint8_t MDAR1;
02196       __IO uint8_t MDAR2;
02197       __IO uint8_t MDAR3;
02198       __IO uint8_t MDAR4;
02199       __IO uint8_t MDAR5;
02200       __IO uint8_t MDAR6;
02201       __IO uint8_t MDAR7;
02202       __IO uint8_t MDAR8;
02203       __IO uint8_t MTSRL;
02204       __IO uint8_t MTSRH;
02205     }TxMailbox;
02206
02207     struct
02208     {
02209       __IO uint8_t FR01;
02210       __IO uint8_t FR02;
02211       __IO uint8_t FR03;
02212       __IO uint8_t FR04;
02213       __IO uint8_t FR05;
02214       __IO uint8_t FR06;
02215       __IO uint8_t FR07;
02216       __IO uint8_t FR08;
02217
02218       __IO uint8_t FR09;
02219       __IO uint8_t FR10;
02220       __IO uint8_t FR11;
02221       __IO uint8_t FR12;
02222       __IO uint8_t FR13;
02223       __IO uint8_t FR14;
02224       __IO uint8_t FR15;
02225       __IO uint8_t FR16;
02226     }Filter;
02227
02228     struct
02229     {
02230       __IO uint8_t F0R1;
02231       __IO uint8_t F0R2;
02232       __IO uint8_t F0R3;
02233       __IO uint8_t F0R4;
02234       __IO uint8_t F0R5;
02235       __IO uint8_t F0R6;
02236       __IO uint8_t F0R7;
02237       __IO uint8_t F0R8;
02238
02239       __IO uint8_t F1R1;
02240       __IO uint8_t F1R2;
02241       __IO uint8_t F1R3;
02242       __IO uint8_t F1R4;
02243       __IO uint8_t F1R5;
02244       __IO uint8_t F1R6;
02245       __IO uint8_t F1R7;
02246       __IO uint8_t F1R8;
02247     }Filter01;
02248
02249     struct
02250     {
02251       __IO uint8_t F2R1;
02252       __IO uint8_t F2R2;
02253       __IO uint8_t F2R3;
02254       __IO uint8_t F2R4;
02255       __IO uint8_t F2R5;
02256       __IO uint8_t F2R6;
02257       __IO uint8_t F2R7;
02258       __IO uint8_t F2R8;
02259
02260       __IO uint8_t F3R1;
02261       __IO uint8_t F3R2;
02262       __IO uint8_t F3R3;
02263       __IO uint8_t F3R4;
02264       __IO uint8_t F3R5;
02265       __IO uint8_t F3R6;
02266       __IO uint8_t F3R7;
02267       __IO uint8_t F3R8;
02268     }Filter23;
02269
02270     struct
02271     {
02272       __IO uint8_t F4R1;
02273       __IO uint8_t F4R2;
02274       __IO uint8_t F4R3;
02275       __IO uint8_t F4R4;
02276       __IO uint8_t F4R5;
02277       __IO uint8_t F4R6;
02278       __IO uint8_t F4R7;
02279       __IO uint8_t F4R8;
02280
02281       __IO uint8_t F5R1;
02282       __IO uint8_t F5R2;
02283       __IO uint8_t F5R3;
02284       __IO uint8_t F5R4;
02285       __IO uint8_t F5R5;
02286       __IO uint8_t F5R6;
02287       __IO uint8_t F5R7;
02288       __IO uint8_t F5R8;
02289     } Filter45;
02290
02291     struct
02292     {
02293       __IO uint8_t ESR;
02294       __IO uint8_t EIER;
02295       __IO uint8_t TECR;
02296       __IO uint8_t RECR;
02297       __IO uint8_t BTR1;
02298       __IO uint8_t BTR2;
02299       uint8_t Reserved1[2];
02300       __IO uint8_t FMR1;
02301       __IO uint8_t FMR2;
02302       __IO uint8_t FCR1;
02303       __IO uint8_t FCR2;
02304       __IO uint8_t FCR3;
02305       uint8_t Reserved2[3];
02306     }Config;
02307
02308     struct
02309     {
02310       __IO uint8_t MFMI;
02311       __IO uint8_t MDLCR;
02312       __IO uint8_t MIDR1;
02313       __IO uint8_t MIDR2;
02314       __IO uint8_t MIDR3;
02315       __IO uint8_t MIDR4;
02316       __IO uint8_t MDAR1;
02317       __IO uint8_t MDAR2;
02318       __IO uint8_t MDAR3;
02319       __IO uint8_t MDAR4;
02320       __IO uint8_t MDAR5;
02321       __IO uint8_t MDAR6;
02322       __IO uint8_t MDAR7;
02323       __IO uint8_t MDAR8;
02324       __IO uint8_t MTSRL;
02325       __IO uint8_t MTSRH;
02326     }RxFIFO;
02327   }Page;
02328 } CAN_TypeDef;
02329
02330 /** @addtogroup CAN_Registers_Bits_Definition
02331   * @{
02332   */
02333 /******************************* Common ***************************************/
02334 /* CAN Master Control Register bits */
02335 #define CAN_MCR_INRQ     ((uint8_t)0x01)
02336 #define CAN_MCR_SLEEP    ((uint8_t)0x02)
02337 #define CAN_MCR_TXFP     ((uint8_t)0x04)
02338 #define CAN_MCR_RFLM     ((uint8_t)0x08)
02339 #define CAN_MCR_NART     ((uint8_t)0x10)
02340 #define CAN_MCR_AWUM     ((uint8_t)0x20)
02341 #define CAN_MCR_ABOM     ((uint8_t)0x40)
02342 #define CAN_MCR_TTCM     ((uint8_t)0x80)
02343
02344 /* CAN Master Status Register bits */
02345 #define CAN_MSR_INAK     ((uint8_t)0x01)
02346 #define CAN_MSR_SLAK     ((uint8_t)0x02)
02347 #define CAN_MSR_ERRI     ((uint8_t)0x04)
02348 #define CAN_MSR_WKUI     ((uint8_t)0x08)
02349 #define CAN_MSR_TX       ((uint8_t)0x10)
02350 #define CAN_MSR_RX       ((uint8_t)0x20)
02351
02352 /* CAN Transmit Status Register bits */
02353 #define CAN_TSR_RQCP0    ((uint8_t)0x01)
02354 #define CAN_TSR_RQCP1    ((uint8_t)0x02)
02355 #define CAN_TSR_RQCP2    ((uint8_t)0x04)
02356 #define CAN_TSR_RQCP012  ((uint8_t)0x07)
02357 #define CAN_TSR_TXOK0    ((uint8_t)0x10)
02358 #define CAN_TSR_TXOK1    ((uint8_t)0x20)
02359 #define CAN_TSR_TXOK2    ((uint8_t)0x40)
02360
02361 #define CAN_TPR_CODE0    ((uint8_t)0x01)
02362 #define CAN_TPR_TME0     ((uint8_t)0x04)
02363 #define CAN_TPR_TME1     ((uint8_t)0x08)
02364 #define CAN_TPR_TME2     ((uint8_t)0x10)
02365 #define CAN_TPR_LOW0     ((uint8_t)0x20)
02366 #define CAN_TPR_LOW1     ((uint8_t)0x40)
02367 #define CAN_TPR_LOW2     ((uint8_t)0x80)
02368 /* CAN Receive FIFO Register bits */
02369 #define CAN_RFR_FMP01  ((uint8_t)0x03)
02370 #define CAN_RFR_FULL   ((uint8_t)0x08)
02371 #define CAN_RFR_FOVR   ((uint8_t)0x10)
02372 #define CAN_RFR_RFOM   ((uint8_t)0x20)
02373
02374 /* CAN Interrupt Register bits */
02375 #define CAN_IER_TMEIE  ((uint8_t)0x01)
02376 #define CAN_IER_FMPIE  ((uint8_t)0x02)
02377 #define CAN_IER_FFIE   ((uint8_t)0x04)
02378 #define CAN_IER_FOVIE  ((uint8_t)0x08)
02379 #define CAN_IER_WKUIE  ((uint8_t)0x80)
02380
02381
02382 /* CAN diagnostic Register bits */
02383 #define CAN_DGR_LBKM  ((uint8_t)0x01)
02384 #define CAN_DGR_SLIM  ((uint8_t)0x02)
02385 #define CAN_DGR_SAMP  ((uint8_t)0x04)
02386 #define CAN_DGR_RX    ((uint8_t)0x08)
02387 #define CAN_DGR_TXM2E ((uint8_t)0x10)
02388
02389
02390 /* CAN page select Register bits */
02391 #define CAN_PSR_PS0  ((uint8_t)0x01)
02392 #define CAN_PSR_PS1  ((uint8_t)0x02)
02393 #define CAN_PSR_PS2  ((uint8_t)0x04)
02394
02395 /******************** Tx MailBox & Fifo Page common bits **********************/
02396 #define CAN_MCSR_TXRQ    ((uint8_t)0x01)
02397 #define CAN_MCSR_ABRQ    ((uint8_t)0x02)
02398 #define CAN_MCSR_RQCP    ((uint8_t)0x04)
02399 #define CAN_MCSR_TXOK    ((uint8_t)0x08)
02400 #define CAN_MCSR_ALST    ((uint8_t)0x10)
02401 #define CAN_MCSR_TERR    ((uint8_t)0x20)
02402
02403 #define CAN_MDLCR_DLC    ((uint8_t)0x0F)
02404 #define CAN_MDLCR_TGT    ((uint8_t)0x80)
02405
02406 #define CAN_MIDR1_RTR    ((uint8_t)0x20)
02407 #define CAN_MIDR1_IDE    ((uint8_t)0x40)
02408
02409
02410 /************************* Filter Page ****************************************/
02411
02412 /* CAN Error Status Register bits */
02413 #define CAN_ESR_EWGF     ((uint8_t)0x01)
02414 #define CAN_ESR_EPVF     ((uint8_t)0x02)
02415 #define CAN_ESR_BOFF     ((uint8_t)0x04)
02416 #define CAN_ESR_LEC0     ((uint8_t)0x10)
02417 #define CAN_ESR_LEC1     ((uint8_t)0x20)
02418 #define CAN_ESR_LEC2     ((uint8_t)0x40)
02419 #define CAN_ESR_LEC      ((uint8_t)0x70)
02420
02421 /* CAN Error Status Register bits */
02422 #define CAN_EIER_EWGIE    ((uint8_t)0x01)
02423 #define CAN_EIER_EPVIE    ((uint8_t)0x02)
02424 #define CAN_EIER_BOFIE    ((uint8_t)0x04)
02425 #define CAN_EIER_LECIE    ((uint8_t)0x10)
02426 #define CAN_EIER_ERRIE    ((uint8_t)0x80)
02427
02428 /* CAN transmit error counter Register bits(CAN_TECR) */
02429 #define CAN_TECR_TEC0     ((uint8_t)0x01)
02430 #define CAN_TECR_TEC1     ((uint8_t)0x02)
02431 #define CAN_TECR_TEC2     ((uint8_t)0x04)
02432 #define CAN_TECR_TEC3     ((uint8_t)0x08)
02433 #define CAN_TECR_TEC4     ((uint8_t)0x10)
02434 #define CAN_TECR_TEC5     ((uint8_t)0x20)
02435 #define CAN_TECR_TEC6     ((uint8_t)0x40)
02436 #define CAN_TECR_TEC7     ((uint8_t)0x80)
02437
02438 /* CAN RECEIVE error counter Register bits(CAN_TECR) */
02439 #define CAN_RECR_REC0     ((uint8_t)0x01)
02440 #define CAN_RECR_REC1     ((uint8_t)0x02)
02441 #define CAN_RECR_REC2     ((uint8_t)0x04)
02442 #define CAN_RECR_REC3     ((uint8_t)0x08)
02443 #define CAN_RECR_REC4     ((uint8_t)0x10)
02444 #define CAN_RECR_REC5     ((uint8_t)0x20)
02445 #define CAN_RECR_REC6     ((uint8_t)0x40)
02446 #define CAN_RECR_REC7     ((uint8_t)0x80)
02447
02448 /* CAN filter mode register bits (CAN_FMR) */
02449 #define CAN_FMR1_FML0     ((uint8_t)0x01)
02450 #define CAN_FMR1_FMH0     ((uint8_t)0x02)
02451 #define CAN_FMR1_FML1     ((uint8_t)0x04)
02452 #define CAN_FMR1_FMH1     ((uint8_t)0x08)
02453 #define CAN_FMR1_FML2     ((uint8_t)0x10)
02454 #define CAN_FMR1_FMH2     ((uint8_t)0x20)
02455 #define CAN_FMR1_FML3     ((uint8_t)0x40)
02456 #define CAN_FMR1_FMH3     ((uint8_t)0x80)
02457
02458 #define CAN_FMR2_FML4     ((uint8_t)0x01)
02459 #define CAN_FMR2_FMH4     ((uint8_t)0x02)
02460 #define CAN_FMR2_FML5     ((uint8_t)0x04)
02461 #define CAN_FMR2_FMH5     ((uint8_t)0x08)
02462
02463 /* CAN filter Config register bits (CAN_FCR) */
02464 #define CAN_FCR1_FACT0     ((uint8_t)0x01)
02465 #define CAN_FCR1_FACT1     ((uint8_t)0x10)
02466 #define CAN_FCR2_FACT2     ((uint8_t)0x01)
02467 #define CAN_FCR2_FACT3     ((uint8_t)0x10)
02468 #define CAN_FCR3_FACT4     ((uint8_t)0x01)
02469 #define CAN_FCR3_FACT5     ((uint8_t)0x10)
02470
02471 #define CAN_FCR1_FSC00     ((uint8_t)0x02)
02472 #define CAN_FCR1_FSC01     ((uint8_t)0x04)
02473 #define CAN_FCR1_FSC10     ((uint8_t)0x20)
02474 #define CAN_FCR1_FSC11     ((uint8_t)0x40)
02475 #define CAN_FCR2_FSC20     ((uint8_t)0x02)
02476 #define CAN_FCR2_FSC21     ((uint8_t)0x04)
02477 #define CAN_FCR2_FSC30     ((uint8_t)0x20)
02478 #define CAN_FCR2_FSC31     ((uint8_t)0x40)
02479 #define CAN_FCR3_FSC40     ((uint8_t)0x02)
02480 #define CAN_FCR3_FSC41     ((uint8_t)0x04)
02481 #define CAN_FCR3_FSC50     ((uint8_t)0x20)
02482 #define CAN_FCR3_FSC51     ((uint8_t)0x40)
02483
02484 /**
02485   * @}
02486   */
02487
02488 /** @addtogroup CAN_Registers_Reset_Value
02489   * @{
02490   */
02491 #define         CAN_MCR_RESET_VALUE                     ((uint8_t)0x02)
02492 #define         CAN_MSR_RESET_VALUE                     ((uint8_t)0x02)
02493 #define         CAN_TSR_RESET_VALUE                     ((uint8_t)0x00)
02494 #define         CAN_TPR_RESET_VALUE                     ((uint8_t)0x0C)
02495 #define         CAN_RFR_RESET_VALUE                     ((uint8_t)0x00)
02496 #define         CAN_IER_RESET_VALUE                     ((uint8_t)0x00)
02497 #define         CAN_DGR_RESET_VALUE                     ((uint8_t)0x0C)
02498 #define         CAN_PSR_RESET_VALUE                     ((uint8_t)0x00)
02499
02500 #define         CAN_ESR_RESET_VALUE                     ((uint8_t)0x00)
02501 #define         CAN_EIER_RESET_VALUE                    ((uint8_t)0x00)
02502 #define         CAN_TECR_RESET_VALUE                    ((uint8_t)0x00)
02503 #define         CAN_RECR_RESET_VALUE                    ((uint8_t)0x00)
02504 #define         CAN_BTR1_RESET_VALUE                    ((uint8_t)0x40)
02505 #define         CAN_BTR2_RESET_VALUE                    ((uint8_t)0x23)
02506 #define         CAN_FMR1_RESET_VALUE                    ((uint8_t)0x00)
02507 #define         CAN_FMR2_RESET_VALUE                    ((uint8_t)0x00)
02508 #define         CAN_FCR_RESET_VALUE                     ((uint8_t)0x00)
02509
02510 #define         CAN_MFMI_RESET_VALUE                    ((uint8_t)0x00)
02511 #define         CAN_MDLC_RESET_VALUE                    ((uint8_t)0x00)
02512 #define         CAN_MCSR_RESET_VALUE                    ((uint8_t)0x00)
02513
02514 /**
02515   * @}
02516   */
02517
02518 /**
02519   * @brief  Configuration Registers (CFG)
02520   */
02521
02522 typedef struct CFG_struct
02523 {
02524   __IO uint8_t GCR; /*!< Global Configuration register */
02525 }
02526 CFG_TypeDef;
02527
02528 /** @addtogroup CFG_Registers_Reset_Value
02529   * @{
02530   */
02531
02532 #define CFG_GCR_RESET_VALUE ((uint8_t)0x00)
02533
02534 /**
02535   * @}
02536   */
02537
02538 /** @addtogroup CFG_Registers_Bits_Definition
02539   * @{
02540   */
02541
02542 #define CFG_GCR_SWD ((uint8_t)0x01) /*!< Swim disable bit mask */
02543 #define CFG_GCR_AL  ((uint8_t)0x02) /*!< Activation Level bit mask */
02544
02545 /**
02546   * @}
02547   */
02548
02549 /******************************************************************************/
02550 /*                          Peripherals Base Address                          */
02551 /******************************************************************************/
02552
02553 /** @addtogroup MAP_FILE_Base_Addresses
02554   * @{
02555   */
02556 #define OPT_BaseAddress         0x4800
02557 #define GPIOA_BaseAddress       0x5000
02558 #define GPIOB_BaseAddress       0x5005
02559 #define GPIOC_BaseAddress       0x500A
02560 #define GPIOD_BaseAddress       0x500F
02561 #define GPIOE_BaseAddress       0x5014
02562 #define GPIOF_BaseAddress       0x5019
02563 #define GPIOG_BaseAddress       0x501E
02564 #define GPIOH_BaseAddress       0x5023
02565 #define GPIOI_BaseAddress       0x5028
02566 #define FLASH_BaseAddress       0x505A
02567 #define EXTI_BaseAddress        0x50A0
02568 #define RST_BaseAddress         0x50B3
02569 #define CLK_BaseAddress         0x50C0
02570 #define WWDG_BaseAddress        0x50D1
02571 #define IWDG_BaseAddress        0x50E0
02572 #define AWU_BaseAddress         0x50F0
02573 #define BEEP_BaseAddress        0x50F3
02574 #define SPI_BaseAddress         0x5200
02575 #define I2C_BaseAddress         0x5210
02576 #define UART1_BaseAddress       0x5230
02577 #define UART2_BaseAddress       0x5240
02578 #define UART3_BaseAddress       0x5240
02579 #define UART4_BaseAddress       0x5230
02580 #define TIM1_BaseAddress        0x5250
02581 #define TIM2_BaseAddress        0x5300
02582 #define TIM3_BaseAddress        0x5320
02583 #define TIM4_BaseAddress        0x5340
02584 #define TIM5_BaseAddress        0x5300
02585 #define TIM6_BaseAddress        0x5340
02586 #define ADC1_BaseAddress        0x53E0
02587 #define ADC2_BaseAddress        0x5400
02588 #define CAN_BaseAddress         0x5420
02589 #define CFG_BaseAddress         0x7F60
02590 #define ITC_BaseAddress         0x7F70
02591 #define DM_BaseAddress          0x7F90
02592
02593 /**
02594   * @}
02595   */
02596
02597 /******************************************************************************/
02598 /*                          Peripherals declarations                          */
02599 /******************************************************************************/
02600
02601 #if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \
02602     defined(STM8S001) || defined(STM8S903) || defined(STM8AF626x) || defined(STM8AF622x)
02603  #define ADC1 ((ADC1_TypeDef *) ADC1_BaseAddress)
02604 #endif /* (STM8S105)||(STM8S103)||(STM8S005)||(STM8S003)||(STM8S001)||(STM8S903)||(STM8AF626x)||(STM8AF622x)*/
02605
02606 #if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \
02607     defined (STM8AF62Ax)
02608 #define ADC2 ((ADC2_TypeDef *) ADC2_BaseAddress)
02609 #endif /* (STM8S208) ||(STM8S207) || (STM8S007) || (STM8AF52Ax) || (STM8AF62Ax) */
02610
02611 #define AWU ((AWU_TypeDef *) AWU_BaseAddress)
02612
02613 #define BEEP ((BEEP_TypeDef *) BEEP_BaseAddress)
02614
02615 #if defined (STM8S208) || defined (STM8AF52Ax)
02616  #define CAN ((CAN_TypeDef *) CAN_BaseAddress)
02617 #endif /* (STM8S208) || (STM8AF52Ax) */
02618
02619 #define CLK ((CLK_TypeDef *) CLK_BaseAddress)
02620
02621 #define EXTI ((EXTI_TypeDef *) EXTI_BaseAddress)
02622
02623 #define FLASH ((FLASH_TypeDef *) FLASH_BaseAddress)
02624
02625 #define OPT ((OPT_TypeDef *) OPT_BaseAddress)
02626
02627 #define GPIOA ((GPIO_TypeDef *) GPIOA_BaseAddress)
02628
02629 #define GPIOB ((GPIO_TypeDef *) GPIOB_BaseAddress)
02630
02631 #define GPIOC ((GPIO_TypeDef *) GPIOC_BaseAddress)
02632
02633 #define GPIOD ((GPIO_TypeDef *) GPIOD_BaseAddress)
02634
02635 #define GPIOE ((GPIO_TypeDef *) GPIOE_BaseAddress)
02636
02637 #define GPIOF ((GPIO_TypeDef *) GPIOF_BaseAddress)
02638
02639 #if defined(STM8S207) || defined (STM8S007) || defined(STM8S208) || defined(STM8S105) || \
02640     defined(STM8S005) || defined (STM8AF52Ax) || defined (STM8AF62Ax) || defined (STM8AF626x)
02641  #define GPIOG ((GPIO_TypeDef *) GPIOG_BaseAddress)
02642 #endif /* (STM8S208) ||(STM8S207)  || (STM8S105) || (STM8AF52Ax) || (STM8AF62Ax) || (STM8AF626x) */
02643
02644 #if defined(STM8S207) || defined (STM8S007) || defined(STM8S208) || defined (STM8AF52Ax) || \
02645     defined (STM8AF62Ax)
02646  #define GPIOH ((GPIO_TypeDef *) GPIOH_BaseAddress)
02647  #define GPIOI ((GPIO_TypeDef *) GPIOI_BaseAddress)
02648 #endif /* (STM8S208) ||(STM8S207) || (STM8AF62Ax) || (STM8AF52Ax) */
02649
02650 #define RST ((RST_TypeDef *) RST_BaseAddress)
02651
02652 #define WWDG ((WWDG_TypeDef *) WWDG_BaseAddress)
02653 #define IWDG ((IWDG_TypeDef *) IWDG_BaseAddress)
02654
02655 #define SPI ((SPI_TypeDef *) SPI_BaseAddress)
02656 #define I2C ((I2C_TypeDef *) I2C_BaseAddress)
02657
02658 #if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined(STM8S103) || \
02659     defined(STM8S003) || defined(STM8S001) || defined(STM8S903) || defined (STM8AF52Ax) || defined (STM8AF62Ax)
02660  #define UART1 ((UART1_TypeDef *) UART1_BaseAddress)
02661 #endif /* (STM8S208) ||(STM8S207)  || (STM8S103) || (STM8S001) || (STM8S903) || (STM8AF52Ax) || (STM8AF62Ax) */
02662
02663 #if defined (STM8S105) || defined (STM8S005) || defined (STM8AF626x)
02664  #define UART2 ((UART2_TypeDef *) UART2_BaseAddress)
02665 #endif /* STM8S105 || STM8S005 || STM8AF626x */
02666
02667 #if defined(STM8S208) ||defined(STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \
02668     defined (STM8AF62Ax)
02669  #define UART3 ((UART3_TypeDef *) UART3_BaseAddress)
02670 #endif /* (STM8S208) ||(STM8S207) || (STM8AF62Ax) || (STM8AF52Ax) */
02671
02672 #if defined(STM8AF622x)
02673  #define UART4 ((UART4_TypeDef *) UART4_BaseAddress)
02674 #endif /* (STM8AF622x) */
02675
02676 #define TIM1 ((TIM1_TypeDef *) TIM1_BaseAddress)
02677
02678 #if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined(STM8S103) || \
02679     defined(STM8S003) || defined(STM8S001) || defined(STM8S105) || defined(STM8S005) || defined (STM8AF52Ax) || \
02680     defined (STM8AF62Ax) || defined (STM8AF626x)
02681  #define TIM2 ((TIM2_TypeDef *) TIM2_BaseAddress)
02682 #endif /* (STM8S208) ||(STM8S207)  || (STM8S103) || (STM8S001) || (STM8S105) || (STM8AF52Ax) || (STM8AF62Ax) || (STM8AF626x)*/
02683
02684 #if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined(STM8S105) || \
02685     defined(STM8S005) || defined (STM8AF52Ax) || defined (STM8AF62Ax) || defined (STM8AF626x)
02686  #define TIM3 ((TIM3_TypeDef *) TIM3_BaseAddress)
02687 #endif /* (STM8S208) ||(STM8S207)  || (STM8S105) || (STM8AF62Ax) || (STM8AF52Ax) || (STM8AF626x)*/
02688
02689 #if defined(STM8S208) ||defined(STM8S207) || defined (STM8S007) || defined(STM8S103) || \
02690     defined(STM8S003) || defined(STM8S001) || defined(STM8S105) || defined(STM8S005) || defined (STM8AF52Ax) || \
02691     defined (STM8AF62Ax) || defined (STM8AF626x)
02692  #define TIM4 ((TIM4_TypeDef *) TIM4_BaseAddress)
02693 #endif /* (STM8S208) ||(STM8S207)  || (STM8S103) || (STM8S001) || (STM8S105) || (STM8AF52Ax) || (STM8AF62Ax) || (STM8AF626x)*/
02694
02695 #if defined (STM8S903) || defined (STM8AF622x)
02696  #define TIM5 ((TIM5_TypeDef *) TIM5_BaseAddress)
02697  #define TIM6 ((TIM6_TypeDef *) TIM6_BaseAddress)
02698 #endif /* (STM8S903) || (STM8AF622x) */
02699
02700 #define ITC ((ITC_TypeDef *) ITC_BaseAddress)
02701
02702 #define CFG ((CFG_TypeDef *) CFG_BaseAddress)
02703
02704 #define DM ((DM_TypeDef *) DM_BaseAddress)
02705
02706
02707 #ifdef USE_STDPERIPH_DRIVER
02708  #include "stm8s_conf.h"
02709 #endif
02710
02711 /* Exported macro --------------------------------------------------------------*/
02712
02713 /*============================== Interrupts ====================================*/
02714 #ifdef _RAISONANCE_
02715  #include <intrins.h>
02716  #define enableInterrupts()    _rim_()  /* enable interrupts */
02717  #define disableInterrupts()   _sim_()  /* disable interrupts */
02718  #define rim()                 _rim_()  /* enable interrupts */
02719  #define sim()                 _sim_()  /* disable interrupts */
02720  #define nop()                 _nop_()  /* No Operation */
02721  #define trap()                _trap_() /* Trap (soft IT) */
02722  #define wfi()                 _wfi_()  /* Wait For Interrupt */
02723  #define halt()                _halt_() /* Halt */
02724 #elif defined(_COSMIC_)
02725  #define enableInterrupts()    {_asm("rim\n");}  /* enable interrupts */
02726  #define disableInterrupts()   {_asm("sim\n");}  /* disable interrupts */
02727  #define rim()                 {_asm("rim\n");}  /* enable interrupts */
02728  #define sim()                 {_asm("sim\n");}  /* disable interrupts */
02729  #define nop()                 {_asm("nop\n");}  /* No Operation */
02730  #define trap()                {_asm("trap\n");} /* Trap (soft IT) */
02731  #define wfi()                 {_asm("wfi\n");}  /* Wait For Interrupt */
02732  #define halt()                {_asm("halt\n");} /* Halt */
02733 #else /*_IAR_*/
02734  #include <intrinsics.h>
02735  #define enableInterrupts()    __enable_interrupt()   /* enable interrupts */
02736  #define disableInterrupts()   __disable_interrupt()  /* disable interrupts */
02737  #define rim()                 __enable_interrupt()   /* enable interrupts */
02738  #define sim()                 __disable_interrupt()  /* disable interrupts */
02739  #define nop()                 __no_operation()       /* No Operation */
02740  #define trap()                __trap()               /* Trap (soft IT) */
02741  #define wfi()                 __wait_for_interrupt() /* Wait For Interrupt */
02742  #define halt()                __halt()               /* Halt */
02743 #endif /*_RAISONANCE_*/
02744
02745 /*============================== Interrupt vector Handling ========================*/
02746
02747 #ifdef _COSMIC_
02748  #define INTERRUPT_HANDLER(a,b) @far @interrupt void a(void)
02749  #define INTERRUPT_HANDLER_TRAP(a) void @far @interrupt a(void)
02750 #endif /* _COSMIC_ */
02751
02752 #ifdef _RAISONANCE_
02753  #define INTERRUPT_HANDLER(a,b) void a(void) interrupt b
02754  #define INTERRUPT_HANDLER_TRAP(a) void a(void) trap
02755 #endif /* _RAISONANCE_ */
02756
02757 #ifdef _IAR_
02758  #define STRINGVECTOR(x) #x
02759  #define VECTOR_ID(x) STRINGVECTOR( vector = (x) )
02760  #define INTERRUPT_HANDLER( a, b )  \
02761  _Pragma( VECTOR_ID( (b)+2 ) )        \
02762  __interrupt void (a)( void )
02763  #define INTERRUPT_HANDLER_TRAP(a) \
02764  _Pragma( VECTOR_ID( 1 ) ) \
02765  __interrupt void (a) (void)
02766 #endif /* _IAR_ */
02767
02768 /*============================== Interrupt Handler declaration ========================*/
02769 #ifdef _COSMIC_
02770  #define INTERRUPT @far @interrupt
02771 #elif defined(_IAR_)
02772  #define INTERRUPT __interrupt
02773 #endif /* _COSMIC_ */
02774
02775 /*============================== Handling bits ====================================*/
02776 /*-----------------------------------------------------------------------------
02777 Method : I
02778 Description : Handle the bit from the character variables.
02779 Comments :    The different parameters of commands are
02780               - VAR : Name of the character variable where the bit is located.
02781               - Place : Bit position in the variable (7 6 5 4 3 2 1 0)
02782               - Value : Can be 0 (reset bit) or not 0 (set bit)
02783               The "MskBit" command allows to select some bits in a source
02784               variables and copy it in a destination var (return the value).
02785               The "ValBit" command returns the value of a bit in a char
02786               variable: the bit is reset if it returns 0 else the bit is set.
02787               This method generates not an optimised code yet.
02788 -----------------------------------------------------------------------------*/
02789 #define SetBit(VAR,Place)         ( (VAR) |= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) )
02790 #define ClrBit(VAR,Place)         ( (VAR) &= (uint8_t)((uint8_t)((uint8_t)1<<(uint8_t)(Place))^(uint8_t)255) )
02791
02792 #define ChgBit(VAR,Place)         ( (VAR) ^= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) )
02793 #define AffBit(VAR,Place,Value)   ((Value) ? \
02794                                    ((VAR) |= ((uint8_t)1<<(Place))) : \
02795                                    ((VAR) &= (((uint8_t)1<<(Place))^(uint8_t)255)))
02796 #define MskBit(Dest,Msk,Src)      ( (Dest) = ((Msk) & (Src)) | ((~(Msk)) & (Dest)) )
02797
02798 #define ValBit(VAR,Place)         ((uint8_t)(VAR) & (uint8_t)((uint8_t)1<<(uint8_t)(Place)))
02799
02800 #define BYTE_0(n)                 ((uint8_t)((n) & (uint8_t)0xFF))        /*!< Returns the low byte of the 32-bit value */
02801 #define BYTE_1(n)                 ((uint8_t)(BYTE_0((n) >> (uint8_t)8)))  /*!< Returns the second byte of the 32-bit value */
02802 #define BYTE_2(n)                 ((uint8_t)(BYTE_0((n) >> (uint8_t)16))) /*!< Returns the third byte of the 32-bit value */
02803 #define BYTE_3(n)                 ((uint8_t)(BYTE_0((n) >> (uint8_t)24))) /*!< Returns the high byte of the 32-bit value */
02804
02805 /*============================== Assert Macros ====================================*/
02806 #define IS_STATE_VALUE_OK(SensitivityValue) \
02807   (((SensitivityValue) == ENABLE) || \
02808    ((SensitivityValue) == DISABLE))
02809
02810 /*-----------------------------------------------------------------------------
02811 Method : II
02812 Description : Handle directly the bit.
02813 Comments :    The idea is to handle directly with the bit name. For that, it is
02814               necessary to have RAM area descriptions (example: HW register...)
02815               and the following command line for each area.
02816               This method generates the most optimized code.
02817 -----------------------------------------------------------------------------*/
02818
02819 #define AREA 0x00     /* The area of bits begins at address 0x10. */
02820
02821 #define BitClr(BIT)  ( *((unsigned char *) (AREA+(BIT)/8)) &= (~(1<<(7-(BIT)%8))) )
02822 #define BitSet(BIT)  ( *((unsigned char *) (AREA+(BIT)/8)) |= (1<<(7-(BIT)%8)) )
02823 #define BitVal(BIT)  ( *((unsigned char *) (AREA+(BIT)/8)) & (1<<(7-(BIT)%8)) )
02824
02825 /* Exported functions ------------------------------------------------------- */
02826
02827 #endif /* __STM8S_H */
02828
02829 /**
02830   * @}
02831   */
02832
02833 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_adc1.c Source File

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stm8s_adc1.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_adc1.c
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all the functions/macros for the ADC1 peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm8s_adc1.h"
00030
00031 /** @addtogroup STM8S_StdPeriph_Driver
00032   * @{
00033   */
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 /* Private macro -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038 /* Private function prototypes -----------------------------------------------*/
00039 /* Private functions ---------------------------------------------------------*/
00040 /* Public functions ----------------------------------------------------------*/
00041
00042 /**
00043   * @addtogroup ADC1_Public_Functions
00044   * @{
00045   */
00046
00047 /**
00048   * @brief  Deinitializes the ADC1 peripheral registers to their default reset values.
00049   * @param  None
00050   * @retval None
00051   */
00052 void ADC1_DeInit(void)
00053 {
00054   ADC1->CSR  = ADC1_CSR_RESET_VALUE;
00055   ADC1->CR1  = ADC1_CR1_RESET_VALUE;
00056   ADC1->CR2  = ADC1_CR2_RESET_VALUE;
00057   ADC1->CR3  = ADC1_CR3_RESET_VALUE;
00058   ADC1->TDRH = ADC1_TDRH_RESET_VALUE;
00059   ADC1->TDRL = ADC1_TDRL_RESET_VALUE;
00060   ADC1->HTRH = ADC1_HTRH_RESET_VALUE;
00061   ADC1->HTRL = ADC1_HTRL_RESET_VALUE;
00062   ADC1->LTRH = ADC1_LTRH_RESET_VALUE;
00063   ADC1->LTRL = ADC1_LTRL_RESET_VALUE;
00064   ADC1->AWCRH = ADC1_AWCRH_RESET_VALUE;
00065   ADC1->AWCRL = ADC1_AWCRL_RESET_VALUE;
00066 }
00067
00068 /**
00069   * @brief  Initializes the ADC1 peripheral according to the specified parameters
00070   * @param   ADC1_ConversionMode: specifies the conversion mode
00071   * can be one of the values of @ref ADC1_ConvMode_TypeDef.
00072   * @param   ADC1_Channel: specifies the channel to convert
00073   * can be one of the values of @ref ADC1_Channel_TypeDef.
00074   * @param   ADC1_PrescalerSelection: specifies the ADC1 prescaler
00075   * can be one of the values of @ref ADC1_PresSel_TypeDef.
00076   * @param   ADC1_ExtTrigger: specifies the external trigger
00077   * can be one of the values of @ref ADC1_ExtTrig_TypeDef.
00078   * @param   ADC1_ExtTriggerState: specifies the external trigger new state
00079   * can be one of the values of @ref FunctionalState.
00080   * @param   ADC1_Align: specifies the converted data alignment
00081   * can be one of the values of @ref ADC1_Align_TypeDef.
00082   * @param   ADC1_SchmittTriggerChannel: specifies the schmitt trigger channel
00083   * can be one of the values of @ref ADC1_SchmittTrigg_TypeDef.
00084   * @param   ADC1_SchmittTriggerState: specifies the schmitt trigger state
00085   * can be one of the values of @ref FunctionalState.
00086   * @retval None
00087   */
00088 void ADC1_Init(ADC1_ConvMode_TypeDef ADC1_ConversionMode, ADC1_Channel_TypeDef ADC1_Channel, ADC1_PresSel_TypeDef ADC1_PrescalerSelection, ADC1_ExtTrig_TypeDef ADC1_ExtTrigger, FunctionalState ADC1_ExtTriggerState, ADC1_Align_TypeDef ADC1_Align, ADC1_SchmittTrigg_TypeDef ADC1_SchmittTriggerChannel, FunctionalState ADC1_SchmittTriggerState)
00089 {
00090   /* Check the parameters */
00091   assert_param(IS_ADC1_CONVERSIONMODE_OK(ADC1_ConversionMode));
00092   assert_param(IS_ADC1_CHANNEL_OK(ADC1_Channel));
00093   assert_param(IS_ADC1_PRESSEL_OK(ADC1_PrescalerSelection));
00094   assert_param(IS_ADC1_EXTTRIG_OK(ADC1_ExtTrigger));
00095   assert_param(IS_FUNCTIONALSTATE_OK(((ADC1_ExtTriggerState))));
00096   assert_param(IS_ADC1_ALIGN_OK(ADC1_Align));
00097   assert_param(IS_ADC1_SCHMITTTRIG_OK(ADC1_SchmittTriggerChannel));
00098   assert_param(IS_FUNCTIONALSTATE_OK(ADC1_SchmittTriggerState));
00099
00100   /*-----------------CR1 & CSR configuration --------------------*/
00101   /* Configure the conversion mode and the channel to convert
00102   respectively according to ADC1_ConversionMode & ADC1_Channel values  &  ADC1_Align values */
00103   ADC1_ConversionConfig(ADC1_ConversionMode, ADC1_Channel, ADC1_Align);
00104   /* Select the prescaler division factor according to ADC1_PrescalerSelection values */
00105   ADC1_PrescalerConfig(ADC1_PrescalerSelection);
00106
00107   /*-----------------CR2 configuration --------------------*/
00108   /* Configure the external trigger state and event respectively
00109   according to NewState, ADC1_ExtTrigger */
00110   ADC1_ExternalTriggerConfig(ADC1_ExtTrigger, ADC1_ExtTriggerState);
00111
00112   /*------------------TDR configuration ---------------------------*/
00113   /* Configure the schmitt trigger channel and state respectively
00114   according to ADC1_SchmittTriggerChannel & ADC1_SchmittTriggerNewState  values */
00115   ADC1_SchmittTriggerConfig(ADC1_SchmittTriggerChannel, ADC1_SchmittTriggerState);
00116
00117   /* Enable the ADC1 peripheral */
00118   ADC1->CR1 |= ADC1_CR1_ADON;
00119 }
00120
00121 /**
00122   * @brief  Enables or Disables the ADC1 peripheral.
00123   * @param  NewState: specifies the peripheral enabled or disabled state.
00124   * @retval None
00125   */
00126 void ADC1_Cmd(FunctionalState NewState)
00127 {
00128   /* Check the parameters */
00129   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00130
00131   if (NewState != DISABLE)
00132   {
00133     ADC1->CR1 |= ADC1_CR1_ADON;
00134   }
00135   else /* NewState == DISABLE */
00136   {
00137     ADC1->CR1 &= (uint8_t)(~ADC1_CR1_ADON);
00138   }
00139 }
00140
00141 /**
00142   * @brief  Enables or Disables the ADC1 scan mode.
00143   * @param  NewState: specifies the selected mode enabled or disabled state.
00144   * @retval None
00145   */
00146 void ADC1_ScanModeCmd(FunctionalState NewState)
00147 {
00148   /* Check the parameters */
00149   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00150
00151   if (NewState != DISABLE)
00152   {
00153     ADC1->CR2 |= ADC1_CR2_SCAN;
00154   }
00155   else /* NewState == DISABLE */
00156   {
00157     ADC1->CR2 &= (uint8_t)(~ADC1_CR2_SCAN);
00158   }
00159 }
00160
00161 /**
00162   * @brief  Enables or Disables the ADC1 data store into the Data Buffer registers rather than in the Data Register
00163   * @param   NewState: specifies the selected mode enabled or disabled state.
00164   * @retval None
00165   */
00166 void ADC1_DataBufferCmd(FunctionalState NewState)
00167 {
00168   /* Check the parameters */
00169   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00170
00171   if (NewState != DISABLE)
00172   {
00173     ADC1->CR3 |= ADC1_CR3_DBUF;
00174   }
00175   else /* NewState == DISABLE */
00176   {
00177     ADC1->CR3 &= (uint8_t)(~ADC1_CR3_DBUF);
00178   }
00179 }
00180
00181 /**
00182   * @brief  Enables or disables the ADC1 interrupt.
00183   * @param   ADC1_IT specifies the name of the interrupt to enable or disable.
00184   * This parameter can be one of the following values:
00185   *    - ADC1_IT_AWDITEN : Analog WDG interrupt enable
00186   *    - ADC1_IT_EOCITEN  : EOC iterrupt enable
00187   * @param   NewState specifies the state of the interrupt to apply.
00188   * @retval None
00189   */
00190 void ADC1_ITConfig(ADC1_IT_TypeDef ADC1_IT, FunctionalState NewState)
00191 {
00192   /* Check the parameters */
00193   assert_param(IS_ADC1_IT_OK(ADC1_IT));
00194   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00195
00196   if (NewState != DISABLE)
00197   {
00198     /* Enable the ADC1 interrupts */
00199     ADC1->CSR |= (uint8_t)ADC1_IT;
00200   }
00201   else  /* NewState == DISABLE */
00202   {
00203     /* Disable the ADC1 interrupts */
00204     ADC1->CSR &= (uint8_t)((uint16_t)~(uint16_t)ADC1_IT);
00205   }
00206 }
00207
00208 /**
00209   * @brief  Configure the ADC1 prescaler division factor.
00210   * @param   ADC1_Prescaler: the selected precaler.
00211   * It can be one of the values of @ref ADC1_PresSel_TypeDef.
00212   * @retval None
00213   */
00214 void ADC1_PrescalerConfig(ADC1_PresSel_TypeDef ADC1_Prescaler)
00215 {
00216   /* Check the parameter */
00217   assert_param(IS_ADC1_PRESSEL_OK(ADC1_Prescaler));
00218
00219   /* Clear the SPSEL bits */
00220   ADC1->CR1 &= (uint8_t)(~ADC1_CR1_SPSEL);
00221   /* Select the prescaler division factor according to ADC1_PrescalerSelection values */
00222   ADC1->CR1 |= (uint8_t)(ADC1_Prescaler);
00223 }
00224
00225 /**
00226   * @brief  Enables or disables the ADC1 Schmitt Trigger on a selected channel.
00227   * @param   ADC1_SchmittTriggerChannel specifies the desired Channel.
00228   * It can be set of the values of @ref ADC1_SchmittTrigg_TypeDef.
00229   * @param   NewState specifies Channel new status.
00230   * can have one of the values of @ref FunctionalState.
00231   * @retval None
00232   */
00233 void ADC1_SchmittTriggerConfig(ADC1_SchmittTrigg_TypeDef ADC1_SchmittTriggerChannel, FunctionalState NewState)
00234 {
00235   /* Check the parameters */
00236   assert_param(IS_ADC1_SCHMITTTRIG_OK(ADC1_SchmittTriggerChannel));
00237   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00238
00239   if (ADC1_SchmittTriggerChannel == ADC1_SCHMITTTRIG_ALL)
00240   {
00241     if (NewState != DISABLE)
00242     {
00243       ADC1->TDRL &= (uint8_t)0x0;
00244       ADC1->TDRH &= (uint8_t)0x0;
00245     }
00246     else /* NewState == DISABLE */
00247     {
00248       ADC1->TDRL |= (uint8_t)0xFF;
00249       ADC1->TDRH |= (uint8_t)0xFF;
00250     }
00251   }
00252   else if (ADC1_SchmittTriggerChannel < ADC1_SCHMITTTRIG_CHANNEL8)
00253   {
00254     if (NewState != DISABLE)
00255     {
00256       ADC1->TDRL &= (uint8_t)(~(uint8_t)((uint8_t)0x01 << (uint8_t)ADC1_SchmittTriggerChannel));
00257     }
00258     else /* NewState == DISABLE */
00259     {
00260       ADC1->TDRL |= (uint8_t)((uint8_t)0x01 << (uint8_t)ADC1_SchmittTriggerChannel);
00261     }
00262   }
00263   else /* ADC1_SchmittTriggerChannel >= ADC1_SCHMITTTRIG_CHANNEL8 */
00264   {
00265     if (NewState != DISABLE)
00266     {
00267       ADC1->TDRH &= (uint8_t)(~(uint8_t)((uint8_t)0x01 << ((uint8_t)ADC1_SchmittTriggerChannel - (uint8_t)8)));
00268     }
00269     else /* NewState == DISABLE */
00270     {
00271       ADC1->TDRH |= (uint8_t)((uint8_t)0x01 << ((uint8_t)ADC1_SchmittTriggerChannel - (uint8_t)8));
00272     }
00273   }
00274 }
00275
00276 /**
00277   * @brief  Configure the ADC1 conversion on selected channel.
00278   * @param   ADC1_ConversionMode Specifies the conversion type.
00279   * It can be set of the values of @ref ADC1_ConvMode_TypeDef
00280   * @param   ADC1_Channel specifies the ADC1 Channel.
00281   * It can be set of the values of @ref ADC1_Channel_TypeDef
00282   * @param   ADC1_Align specifies the converted data alignment.
00283   * It can be set of the values of @ref ADC1_Align_TypeDef
00284   * @retval None
00285   */
00286 void ADC1_ConversionConfig(ADC1_ConvMode_TypeDef ADC1_ConversionMode, ADC1_Channel_TypeDef ADC1_Channel, ADC1_Align_TypeDef ADC1_Align)
00287 {
00288   /* Check the parameters */
00289   assert_param(IS_ADC1_CONVERSIONMODE_OK(ADC1_ConversionMode));
00290   assert_param(IS_ADC1_CHANNEL_OK(ADC1_Channel));
00291   assert_param(IS_ADC1_ALIGN_OK(ADC1_Align));
00292
00293   /* Clear the align bit */
00294   ADC1->CR2 &= (uint8_t)(~ADC1_CR2_ALIGN);
00295   /* Configure the data alignment */
00296   ADC1->CR2 |= (uint8_t)(ADC1_Align);
00297
00298   if (ADC1_ConversionMode == ADC1_CONVERSIONMODE_CONTINUOUS)
00299   {
00300     /* Set the continuous conversion mode */
00301     ADC1->CR1 |= ADC1_CR1_CONT;
00302   }
00303   else /* ADC1_ConversionMode == ADC1_CONVERSIONMODE_SINGLE */
00304   {
00305     /* Set the single conversion mode */
00306     ADC1->CR1 &= (uint8_t)(~ADC1_CR1_CONT);
00307   }
00308
00309   /* Clear the ADC1 channels */
00310   ADC1->CSR &= (uint8_t)(~ADC1_CSR_CH);
00311   /* Select the ADC1 channel */
00312   ADC1->CSR |= (uint8_t)(ADC1_Channel);
00313 }
00314
00315 /**
00316   * @brief  Configure the ADC1 conversion on external trigger event.
00317   * @par Full description:
00318   * The selected external trigger event can be enabled or disabled.
00319   * @param   ADC1_ExtTrigger to select the External trigger event.
00320   * can have one of the values of @ref ADC1_ExtTrig_TypeDef.
00321   * @param   NewState to enable/disable the selected external trigger
00322   * can have one of the values of @ref FunctionalState.
00323   * @retval None
00324   */
00325 void ADC1_ExternalTriggerConfig(ADC1_ExtTrig_TypeDef ADC1_ExtTrigger, FunctionalState NewState)
00326 {
00327   /* Check the parameters */
00328   assert_param(IS_ADC1_EXTTRIG_OK(ADC1_ExtTrigger));
00329   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00330
00331   /* Clear the external trigger selection bits */
00332   ADC1->CR2 &= (uint8_t)(~ADC1_CR2_EXTSEL);
00333
00334   if (NewState != DISABLE)
00335   {
00336     /* Enable the selected external Trigger */
00337     ADC1->CR2 |= (uint8_t)(ADC1_CR2_EXTTRIG);
00338   }
00339   else /* NewState == DISABLE */
00340   {
00341     /* Disable the selected external trigger */
00342     ADC1->CR2 &= (uint8_t)(~ADC1_CR2_EXTTRIG);
00343   }
00344
00345   /* Set the selected external trigger */
00346   ADC1->CR2 |= (uint8_t)(ADC1_ExtTrigger);
00347 }
00348
00349 /**
00350   * @brief  Start ADC1 conversion
00351   * @par Full description:
00352   * This function  triggers the start of conversion, after ADC1 configuration.
00353   * @param  None
00354   * @retval None
00355   * @par Required preconditions:
00356   * Enable the ADC1 peripheral before calling this function
00357   */
00358 void ADC1_StartConversion(void)
00359 {
00360   ADC1->CR1 |= ADC1_CR1_ADON;
00361 }
00362
00363 /**
00364   * @brief  Get one sample of measured signal.
00365   * @param  None
00366   * @retval ConversionValue:  value of the measured signal.
00367   * @par Required preconditions:
00368   * ADC1 conversion finished.
00369   */
00370 uint16_t ADC1_GetConversionValue(void)
00371 {
00372   uint16_t temph = 0;
00373   uint8_t templ = 0;
00374
00375   if ((ADC1->CR2 & ADC1_CR2_ALIGN) != 0) /* Right alignment */
00376   {
00377     /* Read LSB first */
00378     templ = ADC1->DRL;
00379     /* Then read MSB */
00380     temph = ADC1->DRH;
00381
00382     temph = (uint16_t)(templ | (uint16_t)(temph << (uint8_t)8));
00383   }
00384   else /* Left alignment */
00385   {
00386     /* Read MSB first*/
00387     temph = ADC1->DRH;
00388     /* Then read LSB */
00389     templ = ADC1->DRL;
00390
00391     temph = (uint16_t)((uint16_t)((uint16_t)templ << 6) | (uint16_t)((uint16_t)temph << 8));
00392   }
00393
00394   return ((uint16_t)temph);
00395 }
00396
00397 /**
00398   * @brief  Enables or disables the analog watchdog for the given channel.
00399   * @param   Channel specifies the desired Channel.
00400   * It can be set of the values of @ref ADC1_Channel_TypeDef.
00401   * @param   NewState specifies the analog watchdog new state.
00402   * can have one of the values of @ref FunctionalState.
00403   * @retval None
00404   */
00405 void ADC1_AWDChannelConfig(ADC1_Channel_TypeDef Channel, FunctionalState NewState)
00406 {
00407   /* Check the parameters */
00408   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00409   assert_param(IS_ADC1_CHANNEL_OK(Channel));
00410
00411   if (Channel < (uint8_t)8)
00412   {
00413     if (NewState != DISABLE)
00414     {
00415       ADC1->AWCRL |= (uint8_t)((uint8_t)1 << Channel);
00416     }
00417     else /* NewState == DISABLE */
00418     {
00419       ADC1->AWCRL &= (uint8_t)~(uint8_t)((uint8_t)1 << Channel);
00420     }
00421   }
00422   else
00423   {
00424     if (NewState != DISABLE)
00425     {
00426       ADC1->AWCRH |= (uint8_t)((uint8_t)1 << (Channel - (uint8_t)8));
00427     }
00428     else /* NewState == DISABLE */
00429     {
00430       ADC1->AWCRH &= (uint8_t)~(uint8_t)((uint8_t)1 << (uint8_t)(Channel - (uint8_t)8));
00431     }
00432   }
00433 }
00434
00435 /**
00436   * @brief  Sets the high threshold of the analog watchdog.
00437   * @param   Threshold specifies the high threshold value.
00438   * this value depends on the reference voltage range.
00439   * @retval None
00440   */
00441 void ADC1_SetHighThreshold(uint16_t Threshold)
00442 {
00443   ADC1->HTRH = (uint8_t)(Threshold >> (uint8_t)2);
00444   ADC1->HTRL = (uint8_t)Threshold;
00445 }
00446
00447 /**
00448   * @brief  Sets the low threshold of the analog watchdog.
00449   * @param   Threshold specifies the low threshold value.
00450   * this value depends on the reference voltage range.
00451   * @retval None
00452   */
00453 void ADC1_SetLowThreshold(uint16_t Threshold)
00454 {
00455   ADC1->LTRL = (uint8_t)Threshold;
00456   ADC1->LTRH = (uint8_t)(Threshold >> (uint8_t)2);
00457 }
00458
00459 /**
00460   * @brief  Get one sample of measured signal.
00461   * @param   Buffer specifies the buffer to read.
00462   * @retval BufferValue:  value read from the given buffer.
00463   * @par Required preconditions:
00464   * ADC1 conversion finished.
00465   */
00466 uint16_t ADC1_GetBufferValue(uint8_t Buffer)
00467 {
00468   uint16_t temph = 0;
00469   uint8_t templ = 0;
00470
00471   /* Check the parameters */
00472   assert_param(IS_ADC1_BUFFER_OK(Buffer));
00473
00474   if ((ADC1->CR2 & ADC1_CR2_ALIGN) != 0) /* Right alignment */
00475   {
00476     /* Read LSB first */
00477     templ = *(uint8_t*)(uint16_t)((uint16_t)ADC1_BaseAddress + (uint8_t)(Buffer << 1) + 1);
00478     /* Then read MSB */
00479     temph = *(uint8_t*)(uint16_t)((uint16_t)ADC1_BaseAddress + (uint8_t)(Buffer << 1));
00480
00481     temph = (uint16_t)(templ | (uint16_t)(temph << (uint8_t)8));
00482   }
00483   else /* Left alignment */
00484   {
00485     /* Read MSB first*/
00486     temph = *(uint8_t*)(uint16_t)((uint16_t)ADC1_BaseAddress + (uint8_t)(Buffer << 1));
00487     /* Then read LSB */
00488     templ = *(uint8_t*)(uint16_t)((uint16_t)ADC1_BaseAddress + (uint8_t)(Buffer << 1) + 1);
00489
00490     temph = (uint16_t)((uint16_t)((uint16_t)templ << 6) | (uint16_t)(temph << 8));
00491   }
00492
00493   return ((uint16_t)temph);
00494 }
00495
00496 /**
00497   * @brief  Checks the specified analog watchdog channel status.
00498   * @param   Channel: specify the channel of which to check the analog watchdog
00499   * can be one of the values of @ref ADC1_Channel_TypeDef.
00500   * @retval FlagStatus Status of the analog watchdog.
00501   */
00502 FlagStatus ADC1_GetAWDChannelStatus(ADC1_Channel_TypeDef Channel)
00503 {
00504   uint8_t status = 0;
00505
00506   /* Check the parameters */
00507   assert_param(IS_ADC1_CHANNEL_OK(Channel));
00508
00509   if (Channel < (uint8_t)8)
00510   {
00511     status = (uint8_t)(ADC1->AWSRL & (uint8_t)((uint8_t)1 << Channel));
00512   }
00513   else /* Channel = 8 | 9 */
00514   {
00515     status = (uint8_t)(ADC1->AWSRH & (uint8_t)((uint8_t)1 << (Channel - (uint8_t)8)));
00516   }
00517
00518   return ((FlagStatus)status);
00519 }
00520
00521 /**
00522   * @brief  Checks the specified ADC1 flag status.
00523   * @param   Flag: ADC1 flag.
00524   * can be one of the values of @ref ADC1_Flag_TypeDef.
00525   * @retval FlagStatus Status of the ADC1 flag.
00526   */
00527 FlagStatus ADC1_GetFlagStatus(ADC1_Flag_TypeDef Flag)
00528 {
00529   uint8_t flagstatus = 0;
00530   uint8_t temp = 0;
00531
00532   /* Check the parameters */
00533   assert_param(IS_ADC1_FLAG_OK(Flag));
00534
00535   if ((Flag & 0x0F) == 0x01)
00536   {
00537     /* Get OVR flag status */
00538     flagstatus = (uint8_t)(ADC1->CR3 & ADC1_CR3_OVR);
00539   }
00540   else if ((Flag & 0xF0) == 0x10)
00541   {
00542     /* Get analog watchdog channel status */
00543     temp = (uint8_t)(Flag & (uint8_t)0x0F);
00544     if (temp < 8)
00545     {
00546       flagstatus = (uint8_t)(ADC1->AWSRL & (uint8_t)((uint8_t)1 << temp));
00547     }
00548     else
00549     {
00550       flagstatus = (uint8_t)(ADC1->AWSRH & (uint8_t)((uint8_t)1 << (temp - 8)));
00551     }
00552   }
00553   else  /* Get EOC | AWD flag status */
00554   {
00555     flagstatus = (uint8_t)(ADC1->CSR & Flag);
00556   }
00557   return ((FlagStatus)flagstatus);
00558
00559 }
00560
00561 /**
00562   * @brief  Clear the specified ADC1 Flag.
00563   * @param   Flag: ADC1 flag.
00564   * can be one of the values of @ref ADC1_Flag_TypeDef.
00565   * @retval None
00566   */
00567 void ADC1_ClearFlag(ADC1_Flag_TypeDef Flag)
00568 {
00569   uint8_t temp = 0;
00570
00571   /* Check the parameters */
00572   assert_param(IS_ADC1_FLAG_OK(Flag));
00573
00574   if ((Flag & 0x0F) == 0x01)
00575   {
00576     /* Clear OVR flag status */
00577     ADC1->CR3 &= (uint8_t)(~ADC1_CR3_OVR);
00578   }
00579   else if ((Flag & 0xF0) == 0x10)
00580   {
00581     /* Clear analog watchdog channel status */
00582     temp = (uint8_t)(Flag & (uint8_t)0x0F);
00583     if (temp < 8)
00584     {
00585       ADC1->AWSRL &= (uint8_t)~(uint8_t)((uint8_t)1 << temp);
00586     }
00587     else
00588     {
00589       ADC1->AWSRH &= (uint8_t)~(uint8_t)((uint8_t)1 << (temp - 8));
00590     }
00591   }
00592   else  /* Clear EOC | AWD flag status */
00593   {
00594     ADC1->CSR &= (uint8_t) (~Flag);
00595   }
00596 }
00597
00598 /**
00599   * @brief  Returns the specified pending bit status
00600   * @param   ITPendingBit : the IT pending bit to check.
00601   * This parameter can be one of the following values:
00602   *    - ADC1_IT_AWD   : Analog WDG IT status
00603   *    - ADC1_IT_AWS0 : Analog channel 0 IT status
00604   *    - ADC1_IT_AWS1 : Analog channel 1 IT status
00605   *    - ADC1_IT_AWS2 : Analog channel 2 IT status
00606   *    - ADC1_IT_AWS3 : Analog channel 3 IT status
00607   *    - ADC1_IT_AWS4 : Analog channel 4 IT status
00608   *    - ADC1_IT_AWS5 : Analog channel 5 IT status
00609   *    - ADC1_IT_AWS6 : Analog channel 6 IT status
00610   *    - ADC1_IT_AWS7 : Analog channel 7 IT status
00611   *    - ADC1_IT_AWS8 : Analog channel 8 IT status
00612   *    - ADC1_IT_AWS9 : Analog channel 9 IT status
00613   *    - ADC1_IT_EOC    : EOC pending bit
00614   * @retval ITStatus: status of the specified pending bit.
00615   */
00616 ITStatus ADC1_GetITStatus(ADC1_IT_TypeDef ITPendingBit)
00617 {
00618   ITStatus itstatus = RESET;
00619   uint8_t temp = 0;
00620
00621   /* Check the parameters */
00622   assert_param(IS_ADC1_ITPENDINGBIT_OK(ITPendingBit));
00623
00624   if (((uint16_t)ITPendingBit & 0xF0) == 0x10)
00625   {
00626     /* Get analog watchdog channel status */
00627     temp = (uint8_t)((uint16_t)ITPendingBit & 0x0F);
00628     if (temp < 8)
00629     {
00630       itstatus = (ITStatus)(ADC1->AWSRL & (uint8_t)((uint8_t)1 << temp));
00631     }
00632     else
00633     {
00634       itstatus = (ITStatus)(ADC1->AWSRH & (uint8_t)((uint8_t)1 << (temp - 8)));
00635     }
00636   }
00637   else  /* Get EOC | AWD flag status */
00638   {
00639     itstatus = (ITStatus)(ADC1->CSR & (uint8_t)ITPendingBit);
00640   }
00641   return ((ITStatus)itstatus);
00642 }
00643
00644 /**
00645   * @brief  Clear the ADC1 End of Conversion pending bit.
00646   * @param   ITPendingBit : the IT pending bit to clear.
00647   * This parameter can be one of the following values:
00648   *    - ADC1_IT_AWD   : Analog WDG IT status
00649   *    - ADC1_IT_AWS0 : Analog channel 0 IT status
00650   *    - ADC1_IT_AWS1 : Analog channel 1 IT status
00651   *    - ADC1_IT_AWS2 : Analog channel 2 IT status
00652   *    - ADC1_IT_AWS3 : Analog channel 3 IT status
00653   *    - ADC1_IT_AWS4 : Analog channel 4 IT status
00654   *    - ADC1_IT_AWS5 : Analog channel 5 IT status
00655   *    - ADC1_IT_AWS6 : Analog channel 6 IT status
00656   *    - ADC1_IT_AWS7 : Analog channel 7 IT status
00657   *    - ADC1_IT_AWS8 : Analog channel 8 IT status
00658   *    - ADC1_IT_AWS9 : Analog channel 9 IT status
00659   *    - ADC1_IT_EOC  : EOC pending bit
00660   * @retval None
00661   */
00662 void ADC1_ClearITPendingBit(ADC1_IT_TypeDef ITPendingBit)
00663 {
00664   uint8_t temp = 0;
00665
00666   /* Check the parameters */
00667   assert_param(IS_ADC1_ITPENDINGBIT_OK(ITPendingBit));
00668
00669   if (((uint16_t)ITPendingBit & 0xF0) == 0x10)
00670   {
00671     /* Clear analog watchdog channel status */
00672     temp = (uint8_t)((uint16_t)ITPendingBit & 0x0F);
00673     if (temp < 8)
00674     {
00675       ADC1->AWSRL &= (uint8_t)~(uint8_t)((uint8_t)1 << temp);
00676     }
00677     else
00678     {
00679       ADC1->AWSRH &= (uint8_t)~(uint8_t)((uint8_t)1 << (temp - 8));
00680     }
00681   }
00682   else  /* Clear EOC | AWD flag status */
00683   {
00684     ADC1->CSR &= (uint8_t)((uint16_t)~(uint16_t)ITPendingBit);
00685   }
00686 }
00687
00688 /**
00689   * @}
00690   */
00691
00692 /**
00693   * @}
00694   */
00695
00696
00697 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_adc1.h Source File

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stm8s_adc1.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_adc1.h
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all the prototypes/macros for the ADC1 peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027 /* Define to prevent recursive inclusion -------------------------------------*/
00028 #ifndef __STM8S_ADC1_H
00029 #define __STM8S_ADC1_H
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm8s.h"
00033
00034 /* Exported types ------------------------------------------------------------*/
00035
00036 /** @addtogroup ADC1_Exported_Types
00037   * @{
00038   */
00039
00040 /**
00041   * @brief  ADC1 clock prescaler selection
00042   */
00043
00044 typedef enum
00045 {
00046   ADC1_PRESSEL_FCPU_D2  = (uint8_t)0x00, /**< Prescaler selection fADC1 = fcpu/2 */
00047   ADC1_PRESSEL_FCPU_D3  = (uint8_t)0x10, /**< Prescaler selection fADC1 = fcpu/3 */
00048   ADC1_PRESSEL_FCPU_D4  = (uint8_t)0x20, /**< Prescaler selection fADC1 = fcpu/4 */
00049   ADC1_PRESSEL_FCPU_D6  = (uint8_t)0x30, /**< Prescaler selection fADC1 = fcpu/6 */
00050   ADC1_PRESSEL_FCPU_D8  = (uint8_t)0x40, /**< Prescaler selection fADC1 = fcpu/8 */
00051   ADC1_PRESSEL_FCPU_D10 = (uint8_t)0x50, /**< Prescaler selection fADC1 = fcpu/10 */
00052   ADC1_PRESSEL_FCPU_D12 = (uint8_t)0x60, /**< Prescaler selection fADC1 = fcpu/12 */
00053   ADC1_PRESSEL_FCPU_D18 = (uint8_t)0x70  /**< Prescaler selection fADC1 = fcpu/18 */
00054 } ADC1_PresSel_TypeDef;
00055
00056 /**
00057   * @brief   ADC1 External conversion trigger event selection
00058   */
00059 typedef enum
00060 {
00061   ADC1_EXTTRIG_TIM   = (uint8_t)0x00, /**< Conversion from Internal TIM1 TRGO event */
00062   ADC1_EXTTRIG_GPIO  = (uint8_t)0x10  /**< Conversion from External interrupt on ADC_ETR pin*/
00063 } ADC1_ExtTrig_TypeDef;
00064
00065 /**
00066   * @brief  ADC1 data alignment
00067   */
00068 typedef enum
00069 {
00070   ADC1_ALIGN_LEFT  = (uint8_t)0x00, /**< Data alignment left */
00071   ADC1_ALIGN_RIGHT = (uint8_t)0x08  /**< Data alignment right */
00072 } ADC1_Align_TypeDef;
00073
00074 /**
00075   * @brief  ADC1 Interrupt source
00076   */
00077 typedef enum
00078 {
00079   ADC1_IT_AWDIE = (uint16_t)0x010, /**< Analog WDG interrupt enable */
00080   ADC1_IT_EOCIE = (uint16_t)0x020, /**< EOC interrupt enable */
00081   ADC1_IT_AWD   = (uint16_t)0x140, /**< Analog WDG status */
00082   ADC1_IT_AWS0  = (uint16_t)0x110, /**< Analog channel 0 status */
00083   ADC1_IT_AWS1  = (uint16_t)0x111, /**< Analog channel 1 status */
00084   ADC1_IT_AWS2  = (uint16_t)0x112, /**< Analog channel 2 status */
00085   ADC1_IT_AWS3  = (uint16_t)0x113, /**< Analog channel 3 status */
00086   ADC1_IT_AWS4  = (uint16_t)0x114, /**< Analog channel 4 status */
00087   ADC1_IT_AWS5  = (uint16_t)0x115, /**< Analog channel 5 status */
00088   ADC1_IT_AWS6  = (uint16_t)0x116, /**< Analog channel 6 status */
00089   ADC1_IT_AWS7  = (uint16_t)0x117, /**< Analog channel 7 status */
00090   ADC1_IT_AWS8  = (uint16_t)0x118, /**< Analog channel 8 status */
00091   ADC1_IT_AWS9  = (uint16_t)0x119, /**< Analog channel 9 status */
00092   ADC1_IT_AWS12 = (uint16_t)0x11C, /**< Analog channel 12 status */
00093                                    /* refer to product datasheet for channel 12 availability */
00094   ADC1_IT_EOC   = (uint16_t)0x080  /**< EOC pending bit */
00095
00096 } ADC1_IT_TypeDef;
00097
00098 /**
00099   * @brief  ADC1 Flags
00100   */
00101 typedef enum
00102 {
00103   ADC1_FLAG_OVR   = (uint8_t)0x41, /**< Overrun status flag */
00104   ADC1_FLAG_AWD   = (uint8_t)0x40, /**< Analog WDG status */
00105   ADC1_FLAG_AWS0  = (uint8_t)0x10, /**< Analog channel 0 status */
00106   ADC1_FLAG_AWS1  = (uint8_t)0x11, /**< Analog channel 1 status */
00107   ADC1_FLAG_AWS2  = (uint8_t)0x12, /**< Analog channel 2 status */
00108   ADC1_FLAG_AWS3  = (uint8_t)0x13, /**< Analog channel 3 status */
00109   ADC1_FLAG_AWS4  = (uint8_t)0x14, /**< Analog channel 4 status */
00110   ADC1_FLAG_AWS5  = (uint8_t)0x15, /**< Analog channel 5 status */
00111   ADC1_FLAG_AWS6  = (uint8_t)0x16, /**< Analog channel 6 status */
00112   ADC1_FLAG_AWS7  = (uint8_t)0x17, /**< Analog channel 7 status */
00113   ADC1_FLAG_AWS8  = (uint8_t)0x18, /**< Analog channel 8  status*/
00114   ADC1_FLAG_AWS9  = (uint8_t)0x19, /**< Analog channel 9 status */
00115   ADC1_FLAG_AWS12 = (uint8_t)0x1C, /**< Analog channel 12 status */
00116                                   /* refer to product datasheet for channel 12 availability */
00117   ADC1_FLAG_EOC   = (uint8_t)0x80  /**< EOC falg */
00118 }ADC1_Flag_TypeDef;
00119
00120
00121 /**
00122   * @brief  ADC1 schmitt Trigger
00123   */
00124 typedef enum
00125 {
00126   ADC1_SCHMITTTRIG_CHANNEL0  = (uint8_t)0x00, /**< Schmitt trigger disable on AIN0 */
00127   ADC1_SCHMITTTRIG_CHANNEL1  = (uint8_t)0x01, /**< Schmitt trigger disable on AIN1 */
00128   ADC1_SCHMITTTRIG_CHANNEL2  = (uint8_t)0x02, /**< Schmitt trigger disable on AIN2 */
00129   ADC1_SCHMITTTRIG_CHANNEL3  = (uint8_t)0x03, /**< Schmitt trigger disable on AIN3 */
00130   ADC1_SCHMITTTRIG_CHANNEL4  = (uint8_t)0x04, /**< Schmitt trigger disable on AIN4 */
00131   ADC1_SCHMITTTRIG_CHANNEL5  = (uint8_t)0x05, /**< Schmitt trigger disable on AIN5 */
00132   ADC1_SCHMITTTRIG_CHANNEL6  = (uint8_t)0x06, /**< Schmitt trigger disable on AIN6 */
00133   ADC1_SCHMITTTRIG_CHANNEL7  = (uint8_t)0x07, /**< Schmitt trigger disable on AIN7 */
00134   ADC1_SCHMITTTRIG_CHANNEL8  = (uint8_t)0x08, /**< Schmitt trigger disable on AIN8 */
00135   ADC1_SCHMITTTRIG_CHANNEL9  = (uint8_t)0x09, /**< Schmitt trigger disable on AIN9 */
00136   ADC1_SCHMITTTRIG_CHANNEL12 = (uint8_t)0x0C, /**< Schmitt trigger disable on AIN12 */
00137                                               /* refer to product datasheet for channel 12 availability */
00138   ADC1_SCHMITTTRIG_ALL       = (uint8_t)0xFF /**< Schmitt trigger disable on All channels */
00139 } ADC1_SchmittTrigg_TypeDef;
00140
00141 /**
00142   * @brief  ADC1 conversion mode selection
00143   */
00144
00145 typedef enum
00146 {
00147   ADC1_CONVERSIONMODE_SINGLE     = (uint8_t)0x00, /**< Single conversion mode */
00148   ADC1_CONVERSIONMODE_CONTINUOUS = (uint8_t)0x01  /**< Continuous conversion mode */
00149 } ADC1_ConvMode_TypeDef;
00150
00151 /**
00152   * @brief  ADC1 analog channel selection
00153   */
00154
00155 typedef enum
00156 {
00157   ADC1_CHANNEL_0  = (uint8_t)0x00, /**< Analog channel 0 */
00158   ADC1_CHANNEL_1  = (uint8_t)0x01, /**< Analog channel 1 */
00159   ADC1_CHANNEL_2  = (uint8_t)0x02, /**< Analog channel 2 */
00160   ADC1_CHANNEL_3  = (uint8_t)0x03, /**< Analog channel 3 */
00161   ADC1_CHANNEL_4  = (uint8_t)0x04, /**< Analog channel 4 */
00162   ADC1_CHANNEL_5  = (uint8_t)0x05, /**< Analog channel 5 */
00163   ADC1_CHANNEL_6  = (uint8_t)0x06, /**< Analog channel 6 */
00164   ADC1_CHANNEL_7  = (uint8_t)0x07, /**< Analog channel 7 */
00165   ADC1_CHANNEL_8  = (uint8_t)0x08, /**< Analog channel 8 */
00166   ADC1_CHANNEL_9  = (uint8_t)0x09, /**< Analog channel 9 */
00167   ADC1_CHANNEL_12 = (uint8_t)0x0C /**< Analog channel 12 */
00168                  /* refer to product datasheet for channel 12 availability */
00169 } ADC1_Channel_TypeDef;
00170
00171 /**
00172   * @}
00173   */
00174
00175 /* Exported constants --------------------------------------------------------*/
00176
00177 /* Exported macros ------------------------------------------------------------*/
00178
00179 /* Private macros ------------------------------------------------------------*/
00180
00181 /** @addtogroup ADC1_Private_Macros
00182   * @brief  Macros used by the assert function to check the different functions parameters.
00183   * @{
00184   */
00185
00186 /**
00187   * @brief  Macro used by the assert function to check the different prescaler's values.
00188   */
00189 #define IS_ADC1_PRESSEL_OK(PRESCALER) (((PRESCALER) == ADC1_PRESSEL_FCPU_D2) || \
00190                                       ((PRESCALER) == ADC1_PRESSEL_FCPU_D3) || \
00191                                       ((PRESCALER) == ADC1_PRESSEL_FCPU_D4) || \
00192                                       ((PRESCALER) == ADC1_PRESSEL_FCPU_D6) || \
00193                                       ((PRESCALER) == ADC1_PRESSEL_FCPU_D8) || \
00194                                       ((PRESCALER) == ADC1_PRESSEL_FCPU_D10) || \
00195                                       ((PRESCALER) == ADC1_PRESSEL_FCPU_D12) || \
00196                                       ((PRESCALER) == ADC1_PRESSEL_FCPU_D18))
00197
00198 /**
00199   * @brief  Macro used by the assert function to check the different external trigger values.
00200   */
00201 #define IS_ADC1_EXTTRIG_OK(EXTRIG) (((EXTRIG) == ADC1_EXTTRIG_TIM) || \
00202                                    ((EXTRIG) == ADC1_EXTTRIG_GPIO))
00203
00204 /**
00205   * @brief  Macro used by the assert function to check the different alignment modes.
00206   */
00207 #define IS_ADC1_ALIGN_OK(ALIGN) (((ALIGN) == ADC1_ALIGN_LEFT) || \
00208                                 ((ALIGN) == ADC1_ALIGN_RIGHT))
00209
00210 /**
00211   * @brief  Macro used by the assert function to check the Interrupt source.
00212   */
00213 #define IS_ADC1_IT_OK(IT) (((IT) == ADC1_IT_EOCIE) || \
00214                           ((IT) == ADC1_IT_AWDIE))
00215
00216 /**
00217   * @brief  Macro used by the assert function to check the ADC1 Flag.
00218   */
00219 #define IS_ADC1_FLAG_OK(FLAG) (((FLAG) == ADC1_FLAG_EOC)|| \
00220                               ((FLAG) == ADC1_FLAG_OVR) || \
00221                               ((FLAG) == ADC1_FLAG_AWD) || \
00222                               ((FLAG) == ADC1_FLAG_AWS0) || \
00223                               ((FLAG) == ADC1_FLAG_AWS1) || \
00224                               ((FLAG) == ADC1_FLAG_AWS2) || \
00225                               ((FLAG) == ADC1_FLAG_AWS3) || \
00226                               ((FLAG) == ADC1_FLAG_AWS4) || \
00227                               ((FLAG) == ADC1_FLAG_AWS5) || \
00228                               ((FLAG) == ADC1_FLAG_AWS6) || \
00229                               ((FLAG) == ADC1_FLAG_AWS7) || \
00230                               ((FLAG) == ADC1_FLAG_AWS8) || \
00231                               ((FLAG) == ADC1_FLAG_AWS9))
00232
00233 /**
00234   * @brief  Macro used by the assert function to check the ADC1 pending bits.
00235   */
00236 #define IS_ADC1_ITPENDINGBIT_OK(ITPENDINGBIT) (((ITPENDINGBIT) == ADC1_IT_EOC) || \
00237     ((ITPENDINGBIT) == ADC1_IT_AWD) || \
00238     ((ITPENDINGBIT) == ADC1_IT_AWS0) || \
00239     ((ITPENDINGBIT) == ADC1_IT_AWS1) || \
00240     ((ITPENDINGBIT) == ADC1_IT_AWS2) || \
00241     ((ITPENDINGBIT) == ADC1_IT_AWS3) || \
00242     ((ITPENDINGBIT) == ADC1_IT_AWS4) || \
00243     ((ITPENDINGBIT) == ADC1_IT_AWS5) || \
00244     ((ITPENDINGBIT) == ADC1_IT_AWS6) || \
00245     ((ITPENDINGBIT) == ADC1_IT_AWS7) || \
00246     ((ITPENDINGBIT) == ADC1_IT_AWS8) || \
00247     ((ITPENDINGBIT) == ADC1_IT_AWS12) || \
00248     ((ITPENDINGBIT) == ADC1_IT_AWS9))
00249
00250 /**
00251   * @brief  Macro used by the assert function to check the different schmitt trigger values.
00252   */
00253 #define IS_ADC1_SCHMITTTRIG_OK(SCHMITTTRIG) (((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL0) || \
00254     ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL1) || \
00255     ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL2) || \
00256     ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL3) || \
00257     ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL4) || \
00258     ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL5) || \
00259     ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL6) || \
00260     ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL7) || \
00261     ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL8) || \
00262     ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL12) || \
00263     ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_ALL) || \
00264     ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL9))
00265
00266 /**
00267   * @brief  Macro used by the assert function to check the different conversion modes.
00268   */
00269 #define IS_ADC1_CONVERSIONMODE_OK(MODE) (((MODE) == ADC1_CONVERSIONMODE_SINGLE) || \
00270                                         ((MODE) == ADC1_CONVERSIONMODE_CONTINUOUS))
00271
00272 /**
00273   * @brief  Macro used by the assert function to check the different channels values.
00274   */
00275 #define IS_ADC1_CHANNEL_OK(CHANNEL) (((CHANNEL) == ADC1_CHANNEL_0) || \
00276                                     ((CHANNEL) == ADC1_CHANNEL_1) || \
00277                                     ((CHANNEL) == ADC1_CHANNEL_2) || \
00278                                     ((CHANNEL) == ADC1_CHANNEL_3) || \
00279                                     ((CHANNEL) == ADC1_CHANNEL_4) || \
00280                                     ((CHANNEL) == ADC1_CHANNEL_5) || \
00281                                     ((CHANNEL) == ADC1_CHANNEL_6) || \
00282                                     ((CHANNEL) == ADC1_CHANNEL_7) || \
00283                                     ((CHANNEL) == ADC1_CHANNEL_8) || \
00284                                     ((CHANNEL) == ADC1_CHANNEL_12) || \
00285                                     ((CHANNEL) == ADC1_CHANNEL_9))
00286
00287 /**
00288   * @brief  Macro used by the assert function to check the possible buffer values.
00289   */
00290 #define IS_ADC1_BUFFER_OK(BUFFER) ((BUFFER) <= (uint8_t)0x09)
00291
00292 /**
00293   * @}
00294   */
00295
00296 /* Exported functions ------------------------------------------------------- */
00297
00298 /** @addtogroup ADC1_Exported_Functions
00299   * @{
00300   */
00301 void ADC1_DeInit(void);
00302 void ADC1_Init(ADC1_ConvMode_TypeDef ADC1_ConversionMode,
00303                ADC1_Channel_TypeDef ADC1_Channel,
00304                ADC1_PresSel_TypeDef ADC1_PrescalerSelection,
00305                ADC1_ExtTrig_TypeDef ADC1_ExtTrigger,
00306                FunctionalState ADC1_ExtTriggerState, ADC1_Align_TypeDef ADC1_Align,
00307                ADC1_SchmittTrigg_TypeDef ADC1_SchmittTriggerChannel,
00308                FunctionalState ADC1_SchmittTriggerState);
00309 void ADC1_Cmd(FunctionalState NewState);
00310 void ADC1_ScanModeCmd(FunctionalState NewState);
00311 void ADC1_DataBufferCmd(FunctionalState NewState);
00312 void ADC1_ITConfig(ADC1_IT_TypeDef ADC1_IT, FunctionalState NewState);
00313 void ADC1_PrescalerConfig(ADC1_PresSel_TypeDef ADC1_Prescaler);
00314 void ADC1_SchmittTriggerConfig(ADC1_SchmittTrigg_TypeDef ADC1_SchmittTriggerChannel,
00315                               FunctionalState NewState);
00316 void ADC1_ConversionConfig(ADC1_ConvMode_TypeDef ADC1_ConversionMode,
00317                            ADC1_Channel_TypeDef ADC1_Channel,
00318                            ADC1_Align_TypeDef ADC1_Align);
00319 void ADC1_ExternalTriggerConfig(ADC1_ExtTrig_TypeDef ADC1_ExtTrigger, FunctionalState NewState);
00320 void ADC1_AWDChannelConfig(ADC1_Channel_TypeDef Channel, FunctionalState NewState);
00321 void ADC1_StartConversion(void);
00322 uint16_t ADC1_GetConversionValue(void);
00323 void ADC1_SetHighThreshold(uint16_t Threshold);
00324 void ADC1_SetLowThreshold(uint16_t Threshold);
00325 uint16_t ADC1_GetBufferValue(uint8_t Buffer);
00326 FlagStatus ADC1_GetAWDChannelStatus(ADC1_Channel_TypeDef Channel);
00327 FlagStatus ADC1_GetFlagStatus(ADC1_Flag_TypeDef Flag);
00328 void ADC1_ClearFlag(ADC1_Flag_TypeDef Flag);
00329 ITStatus ADC1_GetITStatus(ADC1_IT_TypeDef ITPendingBit);
00330 void ADC1_ClearITPendingBit(ADC1_IT_TypeDef ITPendingBit);
00331 /**
00332   * @}
00333   */
00334
00335 #endif /* __STM8S_ADC1_H */
00336
00337
00338 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_adc2.c Source File

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stm8s_adc2.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_adc2.c
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all the functions/macros for the ADC2 peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm8s_adc2.h"
00030
00031 /** @addtogroup STM8S_StdPeriph_Driver
00032   * @{
00033   */
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 /* Private macro -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038 /* Private function prototypes -----------------------------------------------*/
00039 /* Private functions ---------------------------------------------------------*/
00040
00041 /* Public functions ----------------------------------------------------------*/
00042
00043 /**
00044   * @addtogroup ADC2_Public_Functions
00045   * @{
00046   */
00047
00048 /**
00049   * @brief  Deinitializes the ADC2 peripheral registers to their default reset
00050   * values.
00051   * @param  None
00052   * @retval None
00053   */
00054 void ADC2_DeInit(void)
00055 {
00056   ADC2->CSR  = ADC2_CSR_RESET_VALUE;
00057   ADC2->CR1  = ADC2_CR1_RESET_VALUE;
00058   ADC2->CR2  = ADC2_CR2_RESET_VALUE;
00059   ADC2->TDRH = ADC2_TDRH_RESET_VALUE;
00060   ADC2->TDRL = ADC2_TDRL_RESET_VALUE;
00061 }
00062
00063 /**
00064   * @brief  Initializes the ADC2 peripheral according to the specified parameters
00065   * @param   ADC2_ConversionMode: specifies the conversion mode
00066   * can be one of the values of @ref ADC2_ConvMode_TypeDef.
00067   * @param   ADC2_Channel: specifies the channel to convert
00068   * can be one of the values of @ref ADC2_Channel_TypeDef.
00069   * @param   ADC2_PrescalerSelection: specifies the ADC2 prescaler
00070   * can be one of the values of @ref ADC2_PresSel_TypeDef.
00071   * @param   ADC2_ExtTrigger: specifies the external trigger
00072   * can be one of the values of @ref ADC2_ExtTrig_TypeDef.
00073   * @param   ADC2_ExtTriggerState: specifies the external trigger new state
00074   * can be one of the values of @ref FunctionalState.
00075   * @param   ADC2_Align: specifies the converted data alignment
00076   * can be one of the values of @ref ADC2_Align_TypeDef.
00077   * @param   ADC2_SchmittTriggerChannel: specifies the schmitt trigger channel
00078   * can be one of the values of @ref ADC2_SchmittTrigg_TypeDef.
00079   * @param   ADC2_SchmittTriggerState: specifies the schmitt trigger state
00080   * can be one of the values of @ref FunctionalState.
00081   * @retval None
00082   */
00083 void ADC2_Init(ADC2_ConvMode_TypeDef ADC2_ConversionMode, ADC2_Channel_TypeDef ADC2_Channel, ADC2_PresSel_TypeDef ADC2_PrescalerSelection, ADC2_ExtTrig_TypeDef ADC2_ExtTrigger, FunctionalState ADC2_ExtTriggerState, ADC2_Align_TypeDef ADC2_Align, ADC2_SchmittTrigg_TypeDef ADC2_SchmittTriggerChannel, FunctionalState ADC2_SchmittTriggerState)
00084 {
00085   /* Check the parameters */
00086   assert_param(IS_ADC2_CONVERSIONMODE_OK(ADC2_ConversionMode));
00087   assert_param(IS_ADC2_CHANNEL_OK(ADC2_Channel));
00088   assert_param(IS_ADC2_PRESSEL_OK(ADC2_PrescalerSelection));
00089   assert_param(IS_ADC2_EXTTRIG_OK(ADC2_ExtTrigger));
00090   assert_param(IS_FUNCTIONALSTATE_OK(((ADC2_ExtTriggerState))));
00091   assert_param(IS_ADC2_ALIGN_OK(ADC2_Align));
00092   assert_param(IS_ADC2_SCHMITTTRIG_OK(ADC2_SchmittTriggerChannel));
00093   assert_param(IS_FUNCTIONALSTATE_OK(ADC2_SchmittTriggerState));
00094
00095   /*-----------------CR1 & CSR configuration --------------------*/
00096   /* Configure the conversion mode and the channel to convert
00097   respectively according to ADC2_ConversionMode & ADC2_Channel values  &  ADC2_Align values */
00098   ADC2_ConversionConfig(ADC2_ConversionMode, ADC2_Channel, ADC2_Align);
00099   /* Select the prescaler division factor according to ADC2_PrescalerSelection values */
00100   ADC2_PrescalerConfig(ADC2_PrescalerSelection);
00101
00102   /*-----------------CR2 configuration --------------------*/
00103   /* Configure the external trigger state and event respectively
00104   according to ADC2_ExtTrigStatus, ADC2_ExtTrigger */
00105   ADC2_ExternalTriggerConfig(ADC2_ExtTrigger, ADC2_ExtTriggerState);
00106
00107   /*------------------TDR configuration ---------------------------*/
00108   /* Configure the schmitt trigger channel and state respectively
00109   according to ADC2_SchmittTriggerChannel & ADC2_SchmittTriggerNewState  values */
00110   ADC2_SchmittTriggerConfig(ADC2_SchmittTriggerChannel, ADC2_SchmittTriggerState);
00111
00112   /* Enable the ADC2 peripheral */
00113   ADC2->CR1 |= ADC2_CR1_ADON;
00114 }
00115
00116 /**
00117   * @brief  Enables or Disables the ADC2 peripheral.
00118   * @param   NewState: specifies the peripheral enabled or disabled state.
00119   * @retval None
00120   */
00121 void ADC2_Cmd(FunctionalState NewState)
00122 {
00123   /* Check the parameters */
00124   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00125
00126   if (NewState != DISABLE)
00127   {
00128     ADC2->CR1 |= ADC2_CR1_ADON;
00129   }
00130   else /* NewState == DISABLE */
00131   {
00132     ADC2->CR1 &= (uint8_t)(~ADC2_CR1_ADON);
00133   }
00134 }
00135
00136 /**
00137   * @brief  Enables or disables the ADC2 interrupt.
00138   * @param   NewState specifies the state of ADC2 interrupt.
00139   * @retval None
00140   */
00141 void ADC2_ITConfig(FunctionalState NewState)
00142 {
00143   /* Check the parameters */
00144   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00145
00146   if (NewState != DISABLE)
00147   {
00148     /* Enable the ADC2 interrupts */
00149     ADC2->CSR |= (uint8_t)ADC2_CSR_EOCIE;
00150   }
00151   else  /*NewState == DISABLE */
00152   {
00153     /* Disable the ADC2 interrupts */
00154     ADC2->CSR &= (uint8_t)(~ADC2_CSR_EOCIE);
00155   }
00156 }
00157
00158 /**
00159   * @brief  Configure the ADC2 prescaler division factor.
00160   * @param   ADC2_Prescaler: the selected prescaler.
00161   * It can be one of the values of @ref ADC2_PresSel_TypeDef.
00162   * @retval None
00163   */
00164 void ADC2_PrescalerConfig(ADC2_PresSel_TypeDef ADC2_Prescaler)
00165 {
00166   /* Check the parameter */
00167   assert_param(IS_ADC2_PRESSEL_OK(ADC2_Prescaler));
00168
00169   /* Clear the SPSEL bits */
00170   ADC2->CR1 &= (uint8_t)(~ADC2_CR1_SPSEL);
00171   /* Select the prescaler division factor according to ADC2_PrescalerSelection values */
00172   ADC2->CR1 |= (uint8_t)(ADC2_Prescaler);
00173 }
00174
00175 /**
00176   * @brief  Enables or disables the ADC2 Schmitt Trigger on a selected channel.
00177   * @param   ADC2_SchmittTriggerChannel specifies the desired Channel.
00178   * It can be set of the values of @ref ADC2_SchmittTrigg_TypeDef.
00179   * @param   NewState specifies the Channel  ADC2 Schmitt Trigger new status.
00180   * can have one of the values of @ref FunctionalState.
00181   * @retval None
00182   */
00183 void ADC2_SchmittTriggerConfig(ADC2_SchmittTrigg_TypeDef ADC2_SchmittTriggerChannel, FunctionalState NewState)
00184 {
00185   /* Check the parameters */
00186   assert_param(IS_ADC2_SCHMITTTRIG_OK(ADC2_SchmittTriggerChannel));
00187   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00188
00189   if (ADC2_SchmittTriggerChannel == ADC2_SCHMITTTRIG_ALL)
00190   {
00191     if (NewState != DISABLE)
00192     {
00193       ADC2->TDRL &= (uint8_t)0x0;
00194       ADC2->TDRH &= (uint8_t)0x0;
00195     }
00196     else /* NewState == DISABLE */
00197     {
00198       ADC2->TDRL |= (uint8_t)0xFF;
00199       ADC2->TDRH |= (uint8_t)0xFF;
00200     }
00201   }
00202   else if (ADC2_SchmittTriggerChannel < ADC2_SCHMITTTRIG_CHANNEL8)
00203   {
00204     if (NewState != DISABLE)
00205     {
00206       ADC2->TDRL &= (uint8_t)(~(uint8_t)((uint8_t)0x01 << (uint8_t)ADC2_SchmittTriggerChannel));
00207     }
00208     else /* NewState == DISABLE */
00209     {
00210       ADC2->TDRL |= (uint8_t)((uint8_t)0x01 << (uint8_t)ADC2_SchmittTriggerChannel);
00211     }
00212   }
00213   else /* ADC2_SchmittTriggerChannel >= ADC2_SCHMITTTRIG_CHANNEL8 */
00214   {
00215     if (NewState != DISABLE)
00216     {
00217       ADC2->TDRH &= (uint8_t)(~(uint8_t)((uint8_t)0x01 << ((uint8_t)ADC2_SchmittTriggerChannel - (uint8_t)8)));
00218     }
00219     else /* NewState == DISABLE */
00220     {
00221       ADC2->TDRH |= (uint8_t)((uint8_t)0x01 << ((uint8_t)ADC2_SchmittTriggerChannel - (uint8_t)8));
00222     }
00223   }
00224 }
00225
00226 /**
00227   * @brief  Configure the ADC2 conversion on selected channel.
00228   * @param   ADC2_ConversionMode Specifies the conversion type.
00229   * It can be set of the values of @ref ADC2_ConvMode_TypeDef
00230   * @param   ADC2_Channel specifies the ADC2 Channel.
00231   * It can be set of the values of @ref ADC2_Channel_TypeDef
00232   * @param   ADC2_Align specifies the converted data alignment.
00233   * It can be set of the values of @ref ADC2_Align_TypeDef
00234   * @retval None
00235   */
00236 void ADC2_ConversionConfig(ADC2_ConvMode_TypeDef ADC2_ConversionMode, ADC2_Channel_TypeDef ADC2_Channel, ADC2_Align_TypeDef ADC2_Align)
00237 {
00238   /* Check the parameters */
00239   assert_param(IS_ADC2_CONVERSIONMODE_OK(ADC2_ConversionMode));
00240   assert_param(IS_ADC2_CHANNEL_OK(ADC2_Channel));
00241   assert_param(IS_ADC2_ALIGN_OK(ADC2_Align));
00242
00243   /* Clear the align bit */
00244   ADC2->CR2 &= (uint8_t)(~ADC2_CR2_ALIGN);
00245   /* Configure the data alignment */
00246   ADC2->CR2 |= (uint8_t)(ADC2_Align);
00247
00248   if (ADC2_ConversionMode == ADC2_CONVERSIONMODE_CONTINUOUS)
00249   {
00250     /* Set the continuous conversion mode */
00251     ADC2->CR1 |= ADC2_CR1_CONT;
00252   }
00253   else /* ADC2_ConversionMode == ADC2_CONVERSIONMODE_SINGLE */
00254   {
00255     /* Set the single conversion mode */
00256     ADC2->CR1 &= (uint8_t)(~ADC2_CR1_CONT);
00257   }
00258
00259   /* Clear the ADC2 channels */
00260   ADC2->CSR &= (uint8_t)(~ADC2_CSR_CH);
00261   /* Select the ADC2 channel */
00262   ADC2->CSR |= (uint8_t)(ADC2_Channel);
00263 }
00264
00265 /**
00266   * @brief  Configure the ADC2 conversion on external trigger event.
00267   * @par Full description:
00268   * The selected external trigger event can be enabled or disabled.
00269   * @param   ADC2_ExtTrigger to select the External trigger event.
00270   * can have one of the values of @ref ADC2_ExtTrig_TypeDef.
00271   * @param   NewState to enable/disable the selected external trigger
00272   * can have one of the values of @ref FunctionalState.
00273   * @retval None
00274   */
00275 void ADC2_ExternalTriggerConfig(ADC2_ExtTrig_TypeDef ADC2_ExtTrigger, FunctionalState NewState)
00276 {
00277   /* Check the parameters */
00278   assert_param(IS_ADC2_EXTTRIG_OK(ADC2_ExtTrigger));
00279   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00280
00281   /* Clear the external trigger selection bits */
00282   ADC2->CR2 &= (uint8_t)(~ADC2_CR2_EXTSEL);
00283
00284   if (NewState != DISABLE)
00285   {
00286     /* Enable the selected external Trigger */
00287     ADC2->CR2 |= (uint8_t)(ADC2_CR2_EXTTRIG);
00288   }
00289   else /* NewState == DISABLE */
00290   {
00291     /* Disable the selected external trigger */
00292     ADC2->CR2 &= (uint8_t)(~ADC2_CR2_EXTTRIG);
00293   }
00294
00295   /* Set the selected external trigger */
00296   ADC2->CR2 |= (uint8_t)(ADC2_ExtTrigger);
00297 }
00298
00299 /**
00300   * @brief  Start ADC2 conversion
00301   * @par Full description:
00302   * This function  triggers the start of conversion, after ADC2 configuration.
00303   * @param  None
00304   * @retval None
00305   * @par Required preconditions:
00306   * Enable the ADC2 peripheral before calling this function
00307   */
00308 void ADC2_StartConversion(void)
00309 {
00310   ADC2->CR1 |= ADC2_CR1_ADON;
00311 }
00312
00313 /**
00314   * @brief  Get one sample of measured signal.
00315   * @param  None
00316   * @retval ConversionValue:  value of the measured signal.
00317   * @par Required preconditions:
00318   * ADC2 conversion finished.
00319   */
00320 uint16_t ADC2_GetConversionValue(void)
00321 {
00322   uint16_t temph = 0;
00323   uint8_t templ = 0;
00324
00325   if ((ADC2->CR2 & ADC2_CR2_ALIGN) != 0) /* Right alignment */
00326   {
00327     /* Read LSB first */
00328     templ = ADC2->DRL;
00329     /* Then read MSB */
00330     temph = ADC2->DRH;
00331
00332     temph = (uint16_t)(templ | (uint16_t)(temph << (uint8_t)8));
00333   }
00334   else /* Left alignment */
00335   {
00336     /* Read MSB first*/
00337     temph = ADC2->DRH;
00338     /* Then read LSB */
00339     templ = ADC2->DRL;
00340
00341     temph = (uint16_t)((uint16_t)((uint16_t)templ << 6) | (uint16_t)((uint16_t)temph << 8));
00342   }
00343
00344   return ((uint16_t)temph);
00345 }
00346
00347 /**
00348   * @brief  Checks the ADC2 EOC flag status.
00349   * @param  None
00350   * @retval FlagStatus Status of the ADC2 EOC flag.
00351   */
00352 FlagStatus ADC2_GetFlagStatus(void)
00353 {
00354   /* Get EOC  flag status */
00355   return (FlagStatus)(ADC2->CSR & ADC2_CSR_EOC);
00356 }
00357
00358 /**
00359   * @brief  Clear the ADC2 EOC Flag.
00360   * @param  None
00361   * @retval None
00362   */
00363 void ADC2_ClearFlag(void)
00364 {
00365   ADC2->CSR &= (uint8_t)(~ADC2_CSR_EOC);
00366 }
00367
00368 /**
00369   * @brief  Returns the EOC  pending bit status
00370  * @par Parameters:
00371   * None
00372   * @retval FlagStatus: status of the EOC pending bit.
00373   */
00374 ITStatus ADC2_GetITStatus(void)
00375 {
00376   return (ITStatus)(ADC2->CSR & ADC2_CSR_EOC);
00377 }
00378
00379 /**
00380   * @brief  Clear the ADC2 End of Conversion pending bit.
00381   * @param  None
00382   * @retval None
00383   */
00384 void ADC2_ClearITPendingBit(void)
00385 {
00386   ADC2->CSR &= (uint8_t)(~ADC2_CSR_EOC);
00387 }
00388
00389 /**
00390   * @}
00391   */
00392
00393 /**
00394   * @}
00395   */
00396
00397
00398 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_adc2.h Source File

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  • Globals
  • STM8S_StdPeriph_Driver
  • inc
stm8s_adc2.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_adc2.h
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all the prototypes/macros for the ADC2 peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028
00029 /* Define to prevent recursive inclusion -------------------------------------*/
00030 #ifndef __STM8S_ADC2_H
00031 #define __STM8S_ADC2_H
00032
00033 /* Includes ------------------------------------------------------------------*/
00034 #include "stm8s.h"
00035
00036 /* Exported types ------------------------------------------------------------*/
00037
00038 /** @addtogroup ADC2_Exported_Types
00039   * @{
00040   */
00041
00042 /**
00043   * @brief  ADC2 clock prescaler selection
00044   */
00045
00046 typedef enum {
00047   ADC2_PRESSEL_FCPU_D2  = (uint8_t)0x00, /**< Prescaler selection fADC2 = fcpu/2 */
00048   ADC2_PRESSEL_FCPU_D3  = (uint8_t)0x10, /**< Prescaler selection fADC2 = fcpu/3 */
00049   ADC2_PRESSEL_FCPU_D4  = (uint8_t)0x20, /**< Prescaler selection fADC2 = fcpu/4 */
00050   ADC2_PRESSEL_FCPU_D6  = (uint8_t)0x30, /**< Prescaler selection fADC2 = fcpu/6 */
00051   ADC2_PRESSEL_FCPU_D8  = (uint8_t)0x40, /**< Prescaler selection fADC2 = fcpu/8 */
00052   ADC2_PRESSEL_FCPU_D10 = (uint8_t)0x50, /**< Prescaler selection fADC2 = fcpu/10 */
00053   ADC2_PRESSEL_FCPU_D12 = (uint8_t)0x60, /**< Prescaler selection fADC2 = fcpu/12 */
00054   ADC2_PRESSEL_FCPU_D18 = (uint8_t)0x70  /**< Prescaler selection fADC2 = fcpu/18 */
00055 } ADC2_PresSel_TypeDef;
00056
00057 /**
00058   * @brief   ADC2 External conversion trigger event selection
00059   */
00060 typedef enum {
00061   ADC2_EXTTRIG_TIM   = (uint8_t)0x00, /**< Conversion from Internal TIM TRGO event */
00062   ADC2_EXTTRIG_GPIO  = (uint8_t)0x01  /**< Conversion from External interrupt on ADC_ETR pin*/
00063 } ADC2_ExtTrig_TypeDef;
00064
00065 /**
00066   * @brief  ADC2 data alignment
00067   */
00068 typedef enum {
00069   ADC2_ALIGN_LEFT  = (uint8_t)0x00, /**< Data alignment left */
00070   ADC2_ALIGN_RIGHT = (uint8_t)0x08  /**< Data alignment right */
00071 } ADC2_Align_TypeDef;
00072
00073 /**
00074   * @brief  ADC2 schmitt Trigger
00075   */
00076 typedef enum {
00077   ADC2_SCHMITTTRIG_CHANNEL0  = (uint8_t)0x00, /**< Schmitt trigger disable on AIN0 */
00078   ADC2_SCHMITTTRIG_CHANNEL1  = (uint8_t)0x01, /**< Schmitt trigger disable on AIN1 */
00079   ADC2_SCHMITTTRIG_CHANNEL2  = (uint8_t)0x02, /**< Schmitt trigger disable on AIN2 */
00080   ADC2_SCHMITTTRIG_CHANNEL3  = (uint8_t)0x03, /**< Schmitt trigger disable on AIN3 */
00081   ADC2_SCHMITTTRIG_CHANNEL4  = (uint8_t)0x04, /**< Schmitt trigger disable on AIN4 */
00082   ADC2_SCHMITTTRIG_CHANNEL5  = (uint8_t)0x05, /**< Schmitt trigger disable on AIN5 */
00083   ADC2_SCHMITTTRIG_CHANNEL6  = (uint8_t)0x06, /**< Schmitt trigger disable on AIN6 */
00084   ADC2_SCHMITTTRIG_CHANNEL7  = (uint8_t)0x07, /**< Schmitt trigger disable on AIN7 */
00085   ADC2_SCHMITTTRIG_CHANNEL8  = (uint8_t)0x08, /**< Schmitt trigger disable on AIN8 */
00086   ADC2_SCHMITTTRIG_CHANNEL9  = (uint8_t)0x09, /**< Schmitt trigger disable on AIN9 */
00087   ADC2_SCHMITTTRIG_CHANNEL10 = (uint8_t)0x0A, /**< Schmitt trigger disable on AIN10 */
00088   ADC2_SCHMITTTRIG_CHANNEL11 = (uint8_t)0x0B, /**< Schmitt trigger disable on AIN11 */
00089   ADC2_SCHMITTTRIG_CHANNEL12 = (uint8_t)0x0C, /**< Schmitt trigger disable on AIN12 */
00090   ADC2_SCHMITTTRIG_CHANNEL13 = (uint8_t)0x0D, /**< Schmitt trigger disable on AIN13 */
00091   ADC2_SCHMITTTRIG_CHANNEL14 = (uint8_t)0x0E, /**< Schmitt trigger disable on AIN14 */
00092   ADC2_SCHMITTTRIG_CHANNEL15 = (uint8_t)0x0F, /**< Schmitt trigger disable on AIN15 */
00093   ADC2_SCHMITTTRIG_ALL       = (uint8_t)0x1F /**< Schmitt trigger disable on all channels */
00094
00095 } ADC2_SchmittTrigg_TypeDef;
00096
00097 /**
00098   * @brief  ADC2 conversion mode selection
00099   */
00100
00101 typedef enum {
00102   ADC2_CONVERSIONMODE_SINGLE     = (uint8_t)0x00, /**< Single conversion mode */
00103   ADC2_CONVERSIONMODE_CONTINUOUS = (uint8_t)0x01  /**< Continuous conversion mode */
00104 } ADC2_ConvMode_TypeDef;
00105
00106 /**
00107   * @brief  ADC2 analog channel selection
00108   */
00109
00110 typedef enum {
00111   ADC2_CHANNEL_0  = (uint8_t)0x00, /**< Analog channel 0 */
00112   ADC2_CHANNEL_1  = (uint8_t)0x01, /**< Analog channel 1 */
00113   ADC2_CHANNEL_2  = (uint8_t)0x02, /**< Analog channel 2 */
00114   ADC2_CHANNEL_3  = (uint8_t)0x03, /**< Analog channel 3 */
00115   ADC2_CHANNEL_4  = (uint8_t)0x04, /**< Analog channel 4 */
00116   ADC2_CHANNEL_5  = (uint8_t)0x05, /**< Analog channel 5 */
00117   ADC2_CHANNEL_6  = (uint8_t)0x06, /**< Analog channel 6 */
00118   ADC2_CHANNEL_7  = (uint8_t)0x07, /**< Analog channel 7 */
00119   ADC2_CHANNEL_8  = (uint8_t)0x08, /**< Analog channel 8 */
00120   ADC2_CHANNEL_9  = (uint8_t)0x09, /**< Analog channel 9 */
00121   ADC2_CHANNEL_10 = (uint8_t)0x0A, /**< Analog channel 10 */
00122   ADC2_CHANNEL_11 = (uint8_t)0x0B, /**< Analog channel 11 */
00123   ADC2_CHANNEL_12 = (uint8_t)0x0C, /**< Analog channel 12 */
00124   ADC2_CHANNEL_13 = (uint8_t)0x0D, /**< Analog channel 13 */
00125   ADC2_CHANNEL_14 = (uint8_t)0x0E, /**< Analog channel 14 */
00126   ADC2_CHANNEL_15 = (uint8_t)0x0F  /**< Analog channel 15 */
00127 } ADC2_Channel_TypeDef;
00128
00129 /**
00130   * @}
00131   */
00132
00133 /* Exported constants --------------------------------------------------------*/
00134
00135 /* Exported macros ------------------------------------------------------------*/
00136
00137 /* Private macros ------------------------------------------------------------*/
00138
00139 /** @addtogroup ADC2_Private_Macros
00140   * @brief  Macros used by the assert function to check the different functions parameters.
00141   * @{
00142   */
00143
00144 /**
00145   * @brief  Macro used by the assert function to check the different prescaler's values.
00146   */
00147 #define IS_ADC2_PRESSEL_OK(PRESCALER) (((PRESCALER) == ADC2_PRESSEL_FCPU_D2) || \
00148                                       ((PRESCALER) == ADC2_PRESSEL_FCPU_D3) || \
00149                                       ((PRESCALER) == ADC2_PRESSEL_FCPU_D4) || \
00150                                       ((PRESCALER) == ADC2_PRESSEL_FCPU_D6) || \
00151                                       ((PRESCALER) == ADC2_PRESSEL_FCPU_D8) || \
00152                                       ((PRESCALER) == ADC2_PRESSEL_FCPU_D10) || \
00153                                       ((PRESCALER) == ADC2_PRESSEL_FCPU_D12) || \
00154                                       ((PRESCALER) == ADC2_PRESSEL_FCPU_D18))
00155
00156 /**
00157   * @brief  Macro used by the assert function to check the different external trigger values.
00158   */
00159 #define IS_ADC2_EXTTRIG_OK(EXTRIG) (((EXTRIG) == ADC2_EXTTRIG_TIM) || \
00160                                                                    ((EXTRIG) == ADC2_EXTTRIG_GPIO))
00161
00162 /**
00163   * @brief  Macro used by the assert function to check the different alignment modes.
00164   */
00165 #define IS_ADC2_ALIGN_OK(ALIGN) (((ALIGN) == ADC2_ALIGN_LEFT) || \
00166                                 ((ALIGN) == ADC2_ALIGN_RIGHT))
00167
00168
00169 /**
00170   * @brief  Macro used by the assert function to check the different schmitt trigger values.
00171   */
00172 #define IS_ADC2_SCHMITTTRIG_OK(SCHMITTTRIG) (((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL0) || \
00173     ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL1) || \
00174     ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL2) || \
00175     ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL3) || \
00176     ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL4) || \
00177     ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL5) || \
00178     ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL6) || \
00179     ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL7) || \
00180     ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL8) || \
00181     ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL9) || \
00182     ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL10) || \
00183     ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL11) || \
00184     ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL12) || \
00185     ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL13) || \
00186     ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL14) || \
00187     ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL15) || \
00188     ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_ALL))
00189
00190 /**
00191   * @brief  Macro used by the assert function to check the different conversion modes.
00192   */
00193 #define IS_ADC2_CONVERSIONMODE_OK(MODE) (((MODE) == ADC2_CONVERSIONMODE_SINGLE) || \
00194                                         ((MODE) == ADC2_CONVERSIONMODE_CONTINUOUS))
00195
00196 /**
00197   * @brief  Macro used by the assert function to check the different channels values.
00198   */
00199 #define IS_ADC2_CHANNEL_OK(CHANNEL) (((CHANNEL) == ADC2_CHANNEL_0) || \
00200                                     ((CHANNEL) == ADC2_CHANNEL_1) || \
00201                                     ((CHANNEL) == ADC2_CHANNEL_2) || \
00202                                     ((CHANNEL) == ADC2_CHANNEL_3) || \
00203                                     ((CHANNEL) == ADC2_CHANNEL_4) || \
00204                                     ((CHANNEL) == ADC2_CHANNEL_5) || \
00205                                     ((CHANNEL) == ADC2_CHANNEL_6) || \
00206                                     ((CHANNEL) == ADC2_CHANNEL_7) || \
00207                                     ((CHANNEL) == ADC2_CHANNEL_8) || \
00208                                     ((CHANNEL) == ADC2_CHANNEL_9) || \
00209                                     ((CHANNEL) == ADC2_CHANNEL_10) || \
00210                                     ((CHANNEL) == ADC2_CHANNEL_11) || \
00211                                     ((CHANNEL) == ADC2_CHANNEL_12) || \
00212                                     ((CHANNEL) == ADC2_CHANNEL_13) || \
00213                                     ((CHANNEL) == ADC2_CHANNEL_14) || \
00214                                     ((CHANNEL) == ADC2_CHANNEL_15))
00215
00216 /**
00217   * @}
00218   */
00219
00220 /* Exported functions ------------------------------------------------------- */
00221
00222 /** @addtogroup ADC2_Exported_Functions
00223   * @{
00224   */
00225 void ADC2_DeInit(void);
00226 void ADC2_Init(ADC2_ConvMode_TypeDef ADC2_ConversionMode,
00227                ADC2_Channel_TypeDef ADC2_Channel,
00228                ADC2_PresSel_TypeDef ADC2_PrescalerSelection,
00229                ADC2_ExtTrig_TypeDef ADC2_ExtTrigger,
00230                FunctionalState ADC2_ExtTriggerState,
00231                ADC2_Align_TypeDef ADC2_Align,
00232                ADC2_SchmittTrigg_TypeDef ADC2_SchmittTriggerChannel,
00233                FunctionalState ADC2_SchmittTriggerState);
00234 void ADC2_Cmd(FunctionalState NewState);
00235 void ADC2_ITConfig(FunctionalState NewState);
00236 void ADC2_PrescalerConfig(ADC2_PresSel_TypeDef ADC2_Prescaler);
00237 void ADC2_SchmittTriggerConfig(ADC2_SchmittTrigg_TypeDef ADC2_SchmittTriggerChannel,
00238                               FunctionalState NewState);
00239 void ADC2_ConversionConfig(ADC2_ConvMode_TypeDef ADC2_ConversionMode,
00240                            ADC2_Channel_TypeDef ADC2_Channel,
00241                            ADC2_Align_TypeDef ADC2_Align);
00242 void ADC2_ExternalTriggerConfig(ADC2_ExtTrig_TypeDef ADC2_ExtTrigger, FunctionalState NewState);
00243 void ADC2_StartConversion(void);
00244 uint16_t ADC2_GetConversionValue(void);
00245 FlagStatus ADC2_GetFlagStatus(void);
00246 void ADC2_ClearFlag(void);
00247 ITStatus ADC2_GetITStatus(void);
00248 void ADC2_ClearITPendingBit(void);
00249 /**
00250   * @}
00251   */
00252
00253 #endif /* __STM8S_ADC2_H */
00254
00255
00256 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_awu.c Source File

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  • Globals
  • STM8S_StdPeriph_Driver
  • src
stm8s_awu.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_awu.c
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all the functions for the AWU peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm8s_awu.h"
00030
00031 /** @addtogroup STM8S_StdPeriph_Driver
00032   * @{
00033   */
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 /* Private macro -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038 /* Private function prototypes -----------------------------------------------*/
00039 /* Private functions ---------------------------------------------------------*/
00040
00041 /* See also AWU_Timebase_TypeDef structure in stm8s_awu.h file :
00042                           N   2   5   1   2   4   8   1   3   6   1   2   5   1   2   1   3
00043                           O   5   0   m   m   m   m   6   2   4   2   5   1   s   s   2   0
00044                           I   0   0   s   s   s   s   m   m   m   8   6   2           s   s
00045                           T   u   u                   s   s   s   m   m   m
00046                               s   s                               s   s   s
00047 */
00048 /** Contains the different values to write in the APR register (used by AWU_Init function) */
00049 CONST uint8_t APR_Array[17] =
00050     {
00051         0, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 61, 23, 23, 62
00052     };
00053
00054 /** Contains the different values to write in the TBR register (used by AWU_Init function) */
00055 CONST uint8_t TBR_Array[17] =
00056     {
00057         0,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 12, 14, 15, 15
00058     };
00059
00060 /* Public functions ----------------------------------------------------------*/
00061
00062 /**
00063   * @addtogroup AWU_Public_Functions
00064   * @{
00065   */
00066
00067 /**
00068   * @brief  Deinitializes the AWU peripheral registers to their default reset
00069   * values.
00070   * @param  None
00071   * @retval None
00072   */
00073 void AWU_DeInit(void)
00074 {
00075   AWU->CSR = AWU_CSR_RESET_VALUE;
00076   AWU->APR = AWU_APR_RESET_VALUE;
00077   AWU->TBR = AWU_TBR_RESET_VALUE;
00078 }
00079
00080 /**
00081   * @brief  Initializes the AWU peripheral according to the specified parameters.
00082   * @param   AWU_TimeBase : Time base selection (interval between AWU interrupts).
00083   * can be one of the values of @ref AWU_Timebase_TypeDef.
00084   * @retval None
00085   * @par Required preconditions:
00086   * The LS RC calibration must be performed before calling this function.
00087   */
00088 void AWU_Init(AWU_Timebase_TypeDef AWU_TimeBase)
00089 {
00090   /* Check parameter */
00091   assert_param(IS_AWU_TIMEBASE_OK(AWU_TimeBase));
00092
00093   /* Enable the AWU peripheral */
00094   AWU->CSR |= AWU_CSR_AWUEN;
00095
00096   /* Set the TimeBase */
00097   AWU->TBR &= (uint8_t)(~AWU_TBR_AWUTB);
00098   AWU->TBR |= TBR_Array[(uint8_t)AWU_TimeBase];
00099
00100   /* Set the APR divider */
00101   AWU->APR &= (uint8_t)(~AWU_APR_APR);
00102   AWU->APR |= APR_Array[(uint8_t)AWU_TimeBase];
00103 }
00104
00105 /**
00106   * @brief  Enable or disable the AWU peripheral.
00107   * @param   NewState Indicates the new state of the AWU peripheral.
00108   * @retval None
00109   * @par Required preconditions:
00110   * Initialisation of AWU and LS RC calibration must be done before.
00111   */
00112 void AWU_Cmd(FunctionalState NewState)
00113 {
00114   if (NewState != DISABLE)
00115   {
00116     /* Enable the AWU peripheral */
00117     AWU->CSR |= AWU_CSR_AWUEN;
00118   }
00119   else
00120   {
00121     /* Disable the AWU peripheral */
00122     AWU->CSR &= (uint8_t)(~AWU_CSR_AWUEN);
00123   }
00124 }
00125
00126 /**
00127   * @brief  Update APR register with the measured LSI frequency.
00128   * @par Note on the APR calculation:
00129   * A is the integer part of lsifreqkhz/4 and x the decimal part.
00130   * x <= A/(1+2A) is equivalent to A >= x(1+2A) and also to 4A >= 4x(1+2A) [F1]
00131   * but we know that A + x = lsifreqkhz/4 ==> 4x = lsifreqkhz-4A
00132   * so [F1] can be written :
00133   * 4A >= (lsifreqkhz-4A)(1+2A)
00134   * @param   LSIFreqHz Low Speed RC frequency measured by timer (in Hz).
00135   * @retval None
00136   * @par Required preconditions:
00137   * - AWU must be disabled to avoid unwanted interrupts.
00138   */
00139 void AWU_LSICalibrationConfig(uint32_t LSIFreqHz)
00140 {
00141   uint16_t lsifreqkhz = 0x0;
00142   uint16_t A = 0x0;
00143
00144   /* Check parameter */
00145   assert_param(IS_LSI_FREQUENCY_OK(LSIFreqHz));
00146
00147   lsifreqkhz = (uint16_t)(LSIFreqHz / 1000); /* Converts value in kHz */
00148
00149   /* Calculation of AWU calibration value */
00150
00151   A = (uint16_t)(lsifreqkhz >> 2U); /* Division by 4, keep integer part only */
00152
00153   if ((4U * A) >= ((lsifreqkhz - (4U * A)) * (1U + (2U * A))))
00154   {
00155     AWU->APR = (uint8_t)(A - 2U);
00156   }
00157   else
00158   {
00159     AWU->APR = (uint8_t)(A - 1U);
00160   }
00161 }
00162
00163 /**
00164   * @brief  Configures AWU in Idle mode to reduce power consumption.
00165   * @param  None
00166   * @retval None
00167   */
00168 void AWU_IdleModeEnable(void)
00169 {
00170   /* Disable AWU peripheral */
00171   AWU->CSR &= (uint8_t)(~AWU_CSR_AWUEN);
00172
00173   /* No AWU timebase */
00174   AWU->TBR = (uint8_t)(~AWU_TBR_AWUTB);
00175 }
00176
00177 /**
00178   * @brief  Returns status of the AWU peripheral flag.
00179   * @param  None
00180   * @retval FlagStatus : Status of the AWU flag.
00181   * This parameter can be any of the @ref FlagStatus enumeration.
00182   */
00183 FlagStatus AWU_GetFlagStatus(void)
00184 {
00185   return((FlagStatus)(((uint8_t)(AWU->CSR & AWU_CSR_AWUF) == (uint8_t)0x00) ? RESET : SET));
00186 }
00187
00188
00189 /**
00190   * @}
00191   */
00192
00193 /**
00194   * @}
00195   */
00196
00197
00198 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_awu.h Source File

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  • Globals
  • STM8S_StdPeriph_Driver
  • inc
stm8s_awu.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_awu.h
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all functions prototype and macros for the AWU peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Define to prevent recursive inclusion -------------------------------------*/
00029 #ifndef __STM8S_AWU_H
00030 #define __STM8S_AWU_H
00031
00032 /* Includes ------------------------------------------------------------------*/
00033 #include "stm8s.h"
00034
00035 /* Exported types ------------------------------------------------------------*/
00036
00037 /** @addtogroup AWU_Exported_Types
00038   * @{
00039   */
00040
00041 /**
00042   * @brief  AWU TimeBase selection
00043   */
00044
00045 typedef enum
00046 {
00047   AWU_TIMEBASE_NO_IT  = (uint8_t)0,    /*!< No AWU interrupt selected */
00048   AWU_TIMEBASE_250US  = (uint8_t)1,    /*!< AWU Timebase equals 0.25 ms */
00049   AWU_TIMEBASE_500US  = (uint8_t)2,    /*!< AWU Timebase equals 0.5 ms */
00050   AWU_TIMEBASE_1MS    = (uint8_t)3,    /*!< AWU Timebase equals 1 ms */
00051   AWU_TIMEBASE_2MS    = (uint8_t)4,    /*!< AWU Timebase equals 2 ms */
00052   AWU_TIMEBASE_4MS    = (uint8_t)5,    /*!< AWU Timebase equals 4 ms */
00053   AWU_TIMEBASE_8MS    = (uint8_t)6,    /*!< AWU Timebase equals 8 ms */
00054   AWU_TIMEBASE_16MS   = (uint8_t)7,    /*!< AWU Timebase equals 16 ms */
00055   AWU_TIMEBASE_32MS   = (uint8_t)8,    /*!< AWU Timebase equals 32 ms */
00056   AWU_TIMEBASE_64MS   = (uint8_t)9,    /*!< AWU Timebase equals 64 ms */
00057   AWU_TIMEBASE_128MS  = (uint8_t)10,   /*!< AWU Timebase equals 128 ms */
00058   AWU_TIMEBASE_256MS  = (uint8_t)11,   /*!< AWU Timebase equals 256 ms */
00059   AWU_TIMEBASE_512MS  = (uint8_t)12,   /*!< AWU Timebase equals 512 ms */
00060   AWU_TIMEBASE_1S     = (uint8_t)13,   /*!< AWU Timebase equals 1 s */
00061   AWU_TIMEBASE_2S     = (uint8_t)14,   /*!< AWU Timebase equals 2 s */
00062   AWU_TIMEBASE_12S    = (uint8_t)15,   /*!< AWU Timebase equals 12 s */
00063   AWU_TIMEBASE_30S    = (uint8_t)16    /*!< AWU Timebase equals 30 s */
00064 } AWU_Timebase_TypeDef;
00065
00066 /**
00067   * @}
00068   */
00069
00070 /* Exported constants --------------------------------------------------------*/
00071
00072 /** @addtogroup AWU_Exported_Constants
00073   * @{
00074   */
00075
00076 #define LSI_FREQUENCY_MIN ((uint32_t)110000) /*!< LSI minimum value in Hertz */
00077 #define LSI_FREQUENCY_MAX ((uint32_t)150000) /*!< LSI maximum value in Hertz */
00078
00079 /**
00080   * @}
00081   */
00082
00083 /* Exported macros ------------------------------------------------------------*/
00084
00085 /* Private macros ------------------------------------------------------------*/
00086
00087 /** @addtogroup AWU_Private_Macros
00088   * @{
00089   */
00090
00091 /**
00092   * @brief  Macro used by the assert function to check the different functions parameters.
00093   */
00094
00095 /**
00096   * @brief   Macro used by the assert function to check the AWU timebases
00097   */
00098 #define IS_AWU_TIMEBASE_OK(TB) \
00099   (((TB) == AWU_TIMEBASE_NO_IT) || \
00100    ((TB) == AWU_TIMEBASE_250US) || \
00101    ((TB) == AWU_TIMEBASE_500US) || \
00102    ((TB) == AWU_TIMEBASE_1MS)   || \
00103    ((TB) == AWU_TIMEBASE_2MS)   || \
00104    ((TB) == AWU_TIMEBASE_4MS)   || \
00105    ((TB) == AWU_TIMEBASE_8MS)   || \
00106    ((TB) == AWU_TIMEBASE_16MS)  || \
00107    ((TB) == AWU_TIMEBASE_32MS)  || \
00108    ((TB) == AWU_TIMEBASE_64MS)  || \
00109    ((TB) == AWU_TIMEBASE_128MS) || \
00110    ((TB) == AWU_TIMEBASE_256MS) || \
00111    ((TB) == AWU_TIMEBASE_512MS) || \
00112    ((TB) == AWU_TIMEBASE_1S)    || \
00113    ((TB) == AWU_TIMEBASE_2S)    || \
00114    ((TB) == AWU_TIMEBASE_12S)   || \
00115    ((TB) == AWU_TIMEBASE_30S))
00116
00117 /**
00118   * @brief    Macro used by the assert function to check the LSI frequency (in Hz)
00119   */
00120 #define IS_LSI_FREQUENCY_OK(FREQ) \
00121   (((FREQ) >= LSI_FREQUENCY_MIN) && \
00122    ((FREQ) <= LSI_FREQUENCY_MAX))
00123
00124 /**
00125   * @}
00126   */
00127
00128 /* Exported functions ------------------------------------------------------- */
00129
00130 /** @addtogroup AWU_Exported_Functions
00131   * @{
00132   */
00133 void AWU_DeInit(void);
00134 void AWU_Init(AWU_Timebase_TypeDef AWU_TimeBase);
00135 void AWU_Cmd(FunctionalState NewState);
00136 void AWU_LSICalibrationConfig(uint32_t LSIFreqHz);
00137 void AWU_IdleModeEnable(void);
00138 FlagStatus AWU_GetFlagStatus(void);
00139
00140 /**
00141   * @}
00142   */
00143
00144 #endif /* __STM8S_AWU_H */
00145
00146
00147 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_beep.c Source File

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  • STM8S_StdPeriph_Driver
  • src
stm8s_beep.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_beep.c
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all the functions for the BEEP peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm8s_beep.h"
00030
00031 /** @addtogroup STM8S_StdPeriph_Driver
00032   * @{
00033   */
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 /* Private macro -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038 /* Private function prototypes -----------------------------------------------*/
00039 /* Private functions ---------------------------------------------------------*/
00040
00041 /* Public functions ----------------------------------------------------------*/
00042
00043 /**
00044   * @addtogroup BEEP_Public_Functions
00045   * @{
00046   */
00047
00048 /**
00049   * @brief  Deinitializes the BEEP peripheral registers to their default reset
00050   * values.
00051   * @param  None
00052   * @retval None
00053   */
00054 void BEEP_DeInit(void)
00055 {
00056   BEEP->CSR = BEEP_CSR_RESET_VALUE;
00057 }
00058
00059 /**
00060   * @brief  Initializes the BEEP function according to the specified parameters.
00061   * @param   BEEP_Frequency Frequency selection.
00062   * can be one of the values of @ref BEEP_Frequency_TypeDef.
00063   * @retval None
00064   * @par Required preconditions:
00065   * The LS RC calibration must be performed before calling this function.
00066   */
00067 void BEEP_Init(BEEP_Frequency_TypeDef BEEP_Frequency)
00068 {
00069   /* Check parameter */
00070   assert_param(IS_BEEP_FREQUENCY_OK(BEEP_Frequency));
00071
00072   /* Set a default calibration value if no calibration is done */
00073   if ((BEEP->CSR & BEEP_CSR_BEEPDIV) == BEEP_CSR_BEEPDIV)
00074   {
00075     BEEP->CSR &= (uint8_t)(~BEEP_CSR_BEEPDIV); /* Clear bits */
00076     BEEP->CSR |= BEEP_CALIBRATION_DEFAULT;
00077   }
00078
00079   /* Select the output frequency */
00080   BEEP->CSR &= (uint8_t)(~BEEP_CSR_BEEPSEL);
00081   BEEP->CSR |= (uint8_t)(BEEP_Frequency);
00082 }
00083
00084 /**
00085   * @brief  Enable or disable the BEEP function.
00086   * @param   NewState Indicates the new state of the BEEP function.
00087   * @retval None
00088   * @par Required preconditions:
00089   * Initialisation of BEEP and LS RC calibration must be done before.
00090   */
00091 void BEEP_Cmd(FunctionalState NewState)
00092 {
00093   if (NewState != DISABLE)
00094   {
00095     /* Enable the BEEP peripheral */
00096     BEEP->CSR |= BEEP_CSR_BEEPEN;
00097   }
00098   else
00099   {
00100     /* Disable the BEEP peripheral */
00101     BEEP->CSR &= (uint8_t)(~BEEP_CSR_BEEPEN);
00102   }
00103 }
00104
00105 /**
00106   * @brief  Update CSR register with the measured LSI frequency.
00107   * @par Note on the APR calculation:
00108   * A is the integer part of LSIFreqkHz/4 and x the decimal part.
00109   * x <= A/(1+2A) is equivalent to A >= x(1+2A) and also to 4A >= 4x(1+2A) [F1]
00110   * but we know that A + x = LSIFreqkHz/4 ==> 4x = LSIFreqkHz-4A
00111   * so [F1] can be written :
00112   * 4A >= (LSIFreqkHz-4A)(1+2A)
00113   * @param   LSIFreqHz Low Speed RC frequency measured by timer (in Hz).
00114   * @retval None
00115   * @par Required preconditions:
00116   * - BEEP must be disabled to avoid unwanted interrupts.
00117   */
00118 void BEEP_LSICalibrationConfig(uint32_t LSIFreqHz)
00119 {
00120   uint16_t lsifreqkhz;
00121   uint16_t A;
00122
00123   /* Check parameter */
00124   assert_param(IS_LSI_FREQUENCY_OK(LSIFreqHz));
00125
00126   lsifreqkhz = (uint16_t)(LSIFreqHz / 1000); /* Converts value in kHz */
00127
00128   /* Calculation of BEEPER calibration value */
00129
00130   BEEP->CSR &= (uint8_t)(~BEEP_CSR_BEEPDIV); /* Clear bits */
00131
00132   A = (uint16_t)(lsifreqkhz >> 3U); /* Division by 8, keep integer part only */
00133
00134   if ((8U * A) >= ((lsifreqkhz - (8U * A)) * (1U + (2U * A))))
00135   {
00136     BEEP->CSR |= (uint8_t)(A - 2U);
00137   }
00138   else
00139   {
00140     BEEP->CSR |= (uint8_t)(A - 1U);
00141   }
00142 }
00143
00144 /**
00145   * @}
00146   */
00147
00148 /**
00149   * @}
00150   */
00151
00152
00153 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_beep.h Source File

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  • STM8S_StdPeriph_Driver
  • inc
stm8s_beep.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_beep.h
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all functions prototype and macros for the BEEP peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028
00029 /* Define to prevent recursive inclusion -------------------------------------*/
00030 #ifndef __STM8S_BEEP_H
00031 #define __STM8S_BEEP_H
00032
00033 /* Includes ------------------------------------------------------------------*/
00034 #include "stm8s.h"
00035
00036 /* Exported types ------------------------------------------------------------*/
00037
00038 /** @addtogroup BEEP_Exported_Types
00039   * @{
00040   */
00041
00042 /**
00043   * @brief  BEEP Frequency selection
00044   */
00045 typedef enum {
00046   BEEP_FREQUENCY_1KHZ = (uint8_t)0x00,  /*!< Beep signal output frequency equals to 1 KHz */
00047   BEEP_FREQUENCY_2KHZ = (uint8_t)0x40,  /*!< Beep signal output frequency equals to 2 KHz */
00048   BEEP_FREQUENCY_4KHZ = (uint8_t)0x80   /*!< Beep signal output frequency equals to 4 KHz */
00049 } BEEP_Frequency_TypeDef;
00050
00051 /**
00052   * @}
00053   */
00054
00055 /* Exported constants --------------------------------------------------------*/
00056
00057 /** @addtogroup BEEP_Exported_Constants
00058   * @{
00059   */
00060
00061 #define BEEP_CALIBRATION_DEFAULT ((uint8_t)0x0B) /*!< Default value when calibration is not done */
00062
00063 #define LSI_FREQUENCY_MIN ((uint32_t)110000) /*!< LSI minimum value in Hertz */
00064 #define LSI_FREQUENCY_MAX ((uint32_t)150000) /*!< LSI maximum value in Hertz */
00065
00066 /**
00067   * @}
00068   */
00069
00070 /* Exported macros -----------------------------------------------------------*/
00071 /* Private macros ------------------------------------------------------------*/
00072
00073 /** @addtogroup BEEP_Private_Macros
00074   * @{
00075   */
00076
00077 /**
00078   * @brief  Macro used by the assert function to check the different functions parameters.
00079   */
00080
00081 /**
00082   * @brief  Macro used by the assert function to check the BEEP frequencies.
00083   */
00084 #define IS_BEEP_FREQUENCY_OK(FREQ) \
00085   (((FREQ) == BEEP_FREQUENCY_1KHZ) || \
00086    ((FREQ) == BEEP_FREQUENCY_2KHZ) || \
00087    ((FREQ) == BEEP_FREQUENCY_4KHZ))
00088
00089 /**
00090   * @brief   Macro used by the assert function to check the LSI frequency (in Hz).
00091   */
00092 #define IS_LSI_FREQUENCY_OK(FREQ) \
00093   (((FREQ) >= LSI_FREQUENCY_MIN) && \
00094    ((FREQ) <= LSI_FREQUENCY_MAX))
00095
00096 /**
00097   * @}
00098   */
00099
00100 /* Exported functions ------------------------------------------------------- */
00101
00102 /** @addtogroup BEEP_Exported_Functions
00103   * @{
00104   */
00105
00106 void BEEP_DeInit(void);
00107 void BEEP_Init(BEEP_Frequency_TypeDef BEEP_Frequency);
00108 void BEEP_Cmd(FunctionalState NewState);
00109 void BEEP_LSICalibrationConfig(uint32_t LSIFreqHz);
00110
00111
00112 /**
00113   * @}
00114   */
00115
00116 #endif /* __STM8S_BEEP_H */
00117
00118
00119 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_can.c Source File

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  • STM8S_StdPeriph_Driver
  • src
stm8s_can.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_can.c
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all the functions for the CAN peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm8s_can.h"
00030
00031 /** @addtogroup STM8S_StdPeriph_Driver
00032   * @{
00033   */
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 #define CAN_IDLIST_IDMASK_MASK ((uint8_t) 0x55)
00037 #define CAN_IDMASK_IDLIST_MASK ((uint8_t) 0xAA)
00038 #define CAN_MODE_MASK ((uint8_t) 0x03)
00039 #define CAN_ACKNOWLEDGE_TIMEOUT ((uint16_t)0xFFFF)
00040 /* Private macro -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 __IO uint32_t _Id = 0;
00043 __IO uint8_t _IDE = 0;
00044 __IO uint8_t _RTR = 0;
00045 __IO uint8_t _DLC = 0;
00046 __IO uint8_t _Data[8] = {0};
00047 __IO uint8_t _FMI = 0;
00048 /* Private function prototypes -----------------------------------------------*/
00049 static ITStatus CheckITStatus(uint8_t CAN_Reg, uint8_t It_Bit);
00050
00051 /* Private functions ---------------------------------------------------------*/
00052 /**
00053   * @addtogroup CAN_Public_Functions
00054   * @{
00055   */
00056
00057 /**
00058   * @brief  Deinitializes the CAN peripheral registers to their default reset values.
00059   * @param  None
00060   * @retval None
00061   */
00062 void CAN_DeInit(void)
00063 {
00064   /* Request initialisation */
00065   CAN->MCR = CAN_MCR_INRQ;
00066   CAN->PSR = CAN_Page_Config;
00067   CAN_OperatingModeRequest(CAN_OperatingMode_Initialization);
00068   CAN->Page.Config.ESR = CAN_ESR_RESET_VALUE;
00069   CAN->Page.Config.EIER = CAN_EIER_RESET_VALUE;
00070   CAN->Page.Config.BTR1 = CAN_BTR1_RESET_VALUE;
00071   CAN->Page.Config.BTR2 = CAN_BTR2_RESET_VALUE;
00072   CAN->Page.Config.FMR1 = CAN_FMR1_RESET_VALUE;
00073   CAN->Page.Config.FMR2 = CAN_FMR2_RESET_VALUE;
00074   CAN->Page.Config.FCR1 = CAN_FCR_RESET_VALUE;
00075   CAN->Page.Config.FCR2 = CAN_FCR_RESET_VALUE;
00076   CAN->Page.Config.FCR3 = CAN_FCR_RESET_VALUE;
00077   CAN_OperatingModeRequest(CAN_OperatingMode_Normal);
00078   CAN->PSR = CAN_Page_RxFifo;
00079   CAN->Page.RxFIFO.MDLCR = CAN_MDLC_RESET_VALUE;
00080   CAN->PSR = CAN_Page_TxMailBox0;
00081   CAN->Page.TxMailbox.MDLCR = CAN_MDLC_RESET_VALUE;
00082   CAN->PSR = CAN_Page_TxMailBox1;
00083   CAN->Page.TxMailbox.MDLCR = CAN_MDLC_RESET_VALUE;
00084   CAN->PSR = CAN_Page_TxMailBox2;
00085   CAN->Page.TxMailbox.MDLCR = CAN_MDLC_RESET_VALUE;
00086
00087   CAN->MCR = CAN_MCR_RESET_VALUE;
00088   CAN->MSR = (uint8_t)(~CAN_MSR_RESET_VALUE);/* rc_w1 */
00089   CAN->TSR = (uint8_t)(~CAN_TSR_RESET_VALUE);/* rc_w1 */
00090   CAN->RFR = (uint8_t)(~CAN_RFR_RESET_VALUE);/* rc_w1 */
00091   CAN->IER = CAN_IER_RESET_VALUE;
00092   CAN->DGR = CAN_DGR_RESET_VALUE;
00093   CAN->PSR = CAN_PSR_RESET_VALUE;
00094 }
00095
00096 /**
00097   * @brief  Initializes the CAN peripheral according to the specified parameters.
00098   * @param   CAN_MasterCtrl : Master control option, can be one or a combination of @ref CAN_MasterCtrl_TypeDef.
00099   * @param   CAN_Mode : CAN mode , can be one of @ref CAN_Mode_TypeDef.
00100   * @param   CAN_SynJumpWidth : CAN Synchronisation Jump Width , can be one of @ref CAN_SynJumpWidth_TypeDef.
00101   * @param   CAN_BitSeg1 : CAN bit segment 1 , can be one of @ref CAN_BitSeg1_TypeDef.
00102   * @param   CAN_BitSeg2 : CAN bit segment 2 , can be one of @ref CAN_BitSeg2_TypeDef.
00103   * @param   CAN_Prescaler : CAN Baud Rate Prescaler , can be a value from 0x01 to 0xFF.
00104   * @retval Indicates if initialization is succeed. it can be one of @ref CAN_InitStatus_TypeDef enumeration.
00105   */
00106 CAN_InitStatus_TypeDef CAN_Init(CAN_MasterCtrl_TypeDef CAN_MasterCtrl,
00107                                 CAN_Mode_TypeDef CAN_Mode,
00108                                 CAN_SynJumpWidth_TypeDef CAN_SynJumpWidth,
00109                                 CAN_BitSeg1_TypeDef CAN_BitSeg1,
00110                                 CAN_BitSeg2_TypeDef CAN_BitSeg2,
00111                                 uint8_t CAN_Prescaler)
00112 {
00113   CAN_InitStatus_TypeDef InitStatus =  CAN_InitStatus_Failed;
00114   uint16_t timeout = CAN_ACKNOWLEDGE_TIMEOUT;
00115   CAN_Page_TypeDef can_page = CAN_GetSelectedPage();
00116
00117
00118   /* Check the parameters */
00119   assert_param(IS_CAN_MASTERCTRL_OK(CAN_MasterCtrl));
00120   assert_param(IS_CAN_MODE_OK(CAN_Mode));
00121   assert_param(IS_CAN_SYNJUMPWIDTH_OK(CAN_SynJumpWidth));
00122   assert_param(IS_CAN_BITSEG1_OK(CAN_BitSeg1));
00123   assert_param(IS_CAN_BITSEG2_OK(CAN_BitSeg2));
00124   assert_param(IS_CAN_PRESCALER_OK(CAN_Prescaler));
00125
00126   /* Request initialisation */
00127   CAN->MCR = CAN_MCR_INRQ;
00128   /* Wait the acknowledge */
00129   while (((uint8_t)(CAN->MSR & CAN_MSR_INAK) != 0x01) && ((uint16_t)timeout != 0))
00130   {
00131     timeout--;
00132   }
00133
00134   /* Check acknowledged */
00135   if ((CAN->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
00136   {
00137
00138     InitStatus =  CAN_InitStatus_Failed;
00139
00140   }
00141   else
00142   {
00143     /* Set the time triggered communication mode  &  Set the automatic bus-off management  &   Set the automatic wake-up mode
00144     &     Set the no automatic retransmission & Set the receive FIFO locked mode & Set the transmit FIFO priority */
00145     CAN->MCR |= (uint8_t)CAN_MasterCtrl;
00146
00147     /* Set the bit timing register */
00148     CAN->DGR |= (uint8_t)CAN_Mode ;
00149     CAN->PSR = CAN_Page_Config;
00150     CAN->Page.Config.BTR1 = (uint8_t)((uint8_t)(CAN_Prescaler - (uint8_t)1) | CAN_SynJumpWidth);
00151     CAN->Page.Config.BTR2 = (uint8_t)(CAN_BitSeg1 | (uint8_t)CAN_BitSeg2);
00152
00153     /* Request leave initialisation */
00154     CAN->MCR &= (uint8_t)(~CAN_MCR_INRQ);
00155     /* Wait the acknowledge */
00156     timeout = 0xFFFF;
00157     while ((((uint8_t)(CAN->MSR & CAN_MSR_INAK) == 0x01))&&(timeout != 0))
00158     {
00159       timeout--;
00160     }
00161     /* Check acknowledged */
00162     if ((CAN->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
00163     {
00164       InitStatus = CAN_InitStatus_Failed;
00165     }
00166     else
00167     {
00168       InitStatus = CAN_InitStatus_Success;
00169     }
00170   }
00171   /*Restore Last Page*/
00172   CAN_SelectPage(can_page);
00173
00174   /* Return the status of initialization */
00175   return (CAN_InitStatus_TypeDef)InitStatus;
00176 }
00177
00178 /**
00179   * @brief  Initializes the CAN peripheral Filter according to the specified parameters.
00180   * @param   CAN_FilterNumber : CAN Filter number , can be one of @ref CAN_FilterNumber_TypeDef
00181   * @param   CAN_FilterActivation : CAN Filter Activation state , can be one of @ref FunctionalState
00182   * @param   CAN_FilterMode : CAN Filter Mode , can be one of @ref CAN_FilterMode_TypeDef
00183   * @param   CAN_FilterScale : CAN Filter Scale , can be one of @ref CAN_FilterScale_TypeDef
00184   * @param   CAN_FilterID1 : CAN Filter ID 1 , can be a value from 0x00 to 0xFF
00185   * @param   CAN_FilterID2 : CAN Filter ID 2 , can be a value from 0x00 to 0xFF
00186   * @param   CAN_FilterID3 : CAN Filter ID 3 , can be a value from 0x00 to 0xFF
00187   * @param   CAN_FilterID4 : CAN Filter ID 4 , can be a value from 0x00 to 0xFF
00188   * @param   CAN_FilterIDMask1 : CAN Filter ID 1/ Mask 1  , can be a value from 0x00 to 0xFF depending of CAN_FilterMode parameter
00189   * @param   CAN_FilterIDMask2 : CAN Filter ID 2/ Mask 2 , can be a value from 0x00 to 0xFF depending of CAN_FilterMode parameter
00190   * @param   CAN_FilterIDMask3 : CAN Filter ID 3/ Mask 3 , can be a value from 0x00 to 0xFF depending of CAN_FilterMode parameter
00191   * @param   CAN_FilterIDMask4 : CAN Filter ID 4/ Mask 4 , can be a value from 0x00 to 0xFF depending of CAN_FilterMode parameter
00192   * @retval None
00193   */
00194 void CAN_FilterInit(CAN_FilterNumber_TypeDef CAN_FilterNumber,
00195                     FunctionalState CAN_FilterActivation,
00196                     CAN_FilterMode_TypeDef CAN_FilterMode,
00197                     CAN_FilterScale_TypeDef CAN_FilterScale,
00198                     uint8_t CAN_FilterID1,
00199                     uint8_t CAN_FilterID2,
00200                     uint8_t CAN_FilterID3,
00201                     uint8_t CAN_FilterID4,
00202                     uint8_t CAN_FilterIDMask1,
00203                     uint8_t CAN_FilterIDMask2,
00204                     uint8_t CAN_FilterIDMask3,
00205                     uint8_t CAN_FilterIDMask4)
00206 {
00207   uint8_t fact = 0;
00208   uint8_t fsc  = 0;
00209   uint8_t fmhl = 0;
00210
00211   CAN_Page_TypeDef can_page_filter = CAN_Page_Filter01;
00212   CAN_Page_TypeDef can_page = CAN_GetSelectedPage();
00213
00214   /* Check the parameters */
00215   assert_param(IS_CAN_FILTER_NUMBER_OK(CAN_FilterNumber));
00216   assert_param(IS_FUNCTIONALSTATE_OK(CAN_FilterActivation));
00217   assert_param(IS_CAN_FILTER_MODE_OK(CAN_FilterMode));
00218   assert_param(IS_CAN_FILTER_SCALE_OK(CAN_FilterScale));
00219
00220
00221   if (CAN_FilterNumber == CAN_FilterNumber_0)
00222   {
00223     fact = 0x01;
00224     fsc  = 0x00;
00225     fmhl = 0x03;
00226
00227     can_page_filter = CAN_Page_Filter01;
00228   }
00229   else if (CAN_FilterNumber == CAN_FilterNumber_1)
00230   {
00231     fact = 0x10;
00232     fsc  = 0x04;
00233     fmhl = 0x0C;
00234
00235     can_page_filter = CAN_Page_Filter01;
00236   }
00237   else if (CAN_FilterNumber == CAN_FilterNumber_2)
00238   {
00239     fact = 0x01;
00240     fsc  = 0x00;
00241     fmhl = 0x30;
00242
00243     can_page_filter = CAN_Page_Filter23;
00244   }
00245   else if (CAN_FilterNumber == CAN_FilterNumber_3)
00246   {
00247     fact = 0x10;
00248     fsc  = 0x04;
00249     fmhl = 0xC0;
00250
00251     can_page_filter = CAN_Page_Filter23;
00252   }
00253   else if (CAN_FilterNumber == CAN_FilterNumber_4)
00254   {
00255     fact = 0x01;
00256     fsc  = 0x00;
00257     fmhl = 0x03;
00258
00259     can_page_filter = CAN_Page_Filter45;
00260   }
00261   else /*if (CAN_FilterNumber == CAN_FilterNumber_5)*/
00262   {
00263     fact = 0x10;
00264     fsc  = 0x04;
00265     fmhl = 0x0C;
00266
00267     can_page_filter = CAN_Page_Filter45;
00268   }
00269
00270
00271   CAN_OperatingModeRequest(CAN_OperatingMode_Initialization);
00272
00273   CAN->PSR = CAN_Page_Config;
00274   /*---------------------------------------------------------*/
00275   /*Configuration of Filter Scale                            */
00276   /*---------------------------------------------------------*/
00277
00278   if (can_page_filter == CAN_Page_Filter01) /* FCR1 */
00279   {
00280     /* Filter Deactivation  & Reset the Filter Scale */
00281     CAN->Page.Config.FCR1 &= (uint8_t)(~(uint8_t)(fact | (uint8_t)((uint8_t)(CAN_FCR1_FSC00|CAN_FCR1_FSC01) << fsc )));
00282     /* Set the new Filter Scale */
00283     CAN->Page.Config.FCR1 |= (uint8_t)(CAN_FilterScale << fsc);
00284   }
00285   else if (can_page_filter == CAN_Page_Filter23) /* FCR2*/
00286   {
00287     /* Filter Deactivation  & Reset the Filter Scale */
00288     CAN->Page.Config.FCR2 &= (uint8_t)~(uint8_t)( fact | (uint8_t)((uint8_t)(CAN_FCR1_FSC00|CAN_FCR1_FSC01) << fsc ));
00289
00290     /* Set the new Filter Scale */
00291     CAN->Page.Config.FCR2 |= (uint8_t)(CAN_FilterScale << fsc);
00292
00293   }
00294   else /*if(can_page_filter == CAN_Page_Filter45)*/ /* FCR3*/
00295   {
00296     /* Filter Deactivation  & Reset the Filter Scale */
00297     CAN->Page.Config.FCR3 &= (uint8_t)~(uint8_t)( fact | (uint8_t)((uint8_t)(CAN_FCR1_FSC00|CAN_FCR1_FSC01) << fsc ));
00298
00299     /* Set the new Filter Scale */
00300     CAN->Page.Config.FCR3 |= (uint8_t)(CAN_FilterScale << fsc);
00301   }
00302
00303   /*---------------------------------------------------------*/
00304   /*Configuration of Filter Mode                             */
00305   /*---------------------------------------------------------*/
00306   if (can_page_filter != CAN_Page_Filter45) /* FMR1*/
00307   {
00308     /* Filter Mode */
00309     if (CAN_FilterMode == CAN_FilterMode_IdMask)
00310     {
00311       /*Id/Mask mode for the filter*/
00312       CAN->Page.Config.FMR1 &= (uint8_t)~(fmhl);
00313     }
00314     else if ( CAN_FilterMode == CAN_FilterMode_IdList)
00315     {
00316       /*Identifier list mode for the filter*/
00317       CAN->Page.Config.FMR1 |= (uint8_t)(fmhl);
00318     }
00319     else if ( CAN_FilterMode == CAN_FilterMode_IdList_IdMask)
00320     {
00321       /*Identifier list mode is first  for the filter*/
00322       CAN->Page.Config.FMR1 |= (uint8_t)(fmhl & CAN_IDLIST_IDMASK_MASK);
00323     }
00324     else /* ( CAN_FilterMode == CAN_FilterMode_IdMask_IdList)*/
00325     {
00326       /*Id Mask mode is first  for the filter*/
00327       CAN->Page.Config.FMR1 |= (uint8_t)(fmhl & CAN_IDMASK_IDLIST_MASK);
00328     }
00329
00330
00331   }
00332   else /* FMR2 */
00333   {
00334
00335     /* Filter Mode */
00336     if (CAN_FilterMode == CAN_FilterMode_IdMask)
00337     {
00338       /*Id/Mask mode for the filter*/
00339       CAN->Page.Config.FMR2 &= (uint8_t)~(fmhl);
00340     }
00341     else if ( CAN_FilterMode == CAN_FilterMode_IdList)
00342     {
00343       /*Identifier list mode for the filter*/
00344       CAN->Page.Config.FMR2 |= (uint8_t)(fmhl);
00345     }
00346     else if ( CAN_FilterMode == CAN_FilterMode_IdList_IdMask)
00347     {
00348       /*Identifier list mode is first  for the filter*/
00349       CAN->Page.Config.FMR2 |= (uint8_t)(fmhl & CAN_IDLIST_IDMASK_MASK);
00350     }
00351     else /* ( CAN_FilterMode == CAN_FilterMode_IdMask_IdList)*/
00352     {
00353       /*Id Mask mode is first  for the filter*/
00354       CAN->Page.Config.FMR2 |= (uint8_t)(fmhl & CAN_IDMASK_IDLIST_MASK);
00355     }
00356   }
00357   /*---------------------------------------------------------*/
00358   /*Configuration of Filter IDs                              */
00359   /*---------------------------------------------------------*/
00360   CAN->PSR = (uint8_t)can_page_filter;
00361   if (fsc != 0)
00362   {
00363     /* Filter Scale */
00364     if (CAN_FilterScale == CAN_FilterScale_8Bit)
00365     {
00366       CAN->Page.Filter.FR09 = CAN_FilterID1;
00367       CAN->Page.Filter.FR10 = CAN_FilterIDMask1;
00368       CAN->Page.Filter.FR11 = CAN_FilterID2;
00369       CAN->Page.Filter.FR12 = CAN_FilterIDMask2;
00370       CAN->Page.Filter.FR13 = CAN_FilterID3;
00371       CAN->Page.Filter.FR14 = CAN_FilterIDMask3;
00372       CAN->Page.Filter.FR15 = CAN_FilterID4;
00373       CAN->Page.Filter.FR16 = CAN_FilterIDMask4;
00374     }
00375     else if (CAN_FilterScale == CAN_FilterScale_16_8Bit)
00376     {
00377       CAN->Page.Filter.FR09 = CAN_FilterID1;
00378       CAN->Page.Filter.FR10 = CAN_FilterID2;
00379       CAN->Page.Filter.FR11 = CAN_FilterIDMask1;
00380       CAN->Page.Filter.FR12 = CAN_FilterIDMask2;
00381       CAN->Page.Filter.FR13 = CAN_FilterID3;
00382       CAN->Page.Filter.FR14 = CAN_FilterIDMask3;
00383       CAN->Page.Filter.FR15 = CAN_FilterID4;
00384       CAN->Page.Filter.FR16 = CAN_FilterIDMask4;
00385     }
00386     else if (CAN_FilterScale == CAN_FilterScale_16Bit)
00387     {
00388       CAN->Page.Filter.FR09 = CAN_FilterID1;
00389       CAN->Page.Filter.FR10 = CAN_FilterID2;
00390       CAN->Page.Filter.FR11 = CAN_FilterIDMask1;
00391       CAN->Page.Filter.FR12 = CAN_FilterIDMask2;
00392       CAN->Page.Filter.FR13 = CAN_FilterID3;
00393       CAN->Page.Filter.FR14 = CAN_FilterID4;
00394       CAN->Page.Filter.FR15 = CAN_FilterIDMask3;
00395       CAN->Page.Filter.FR16 = CAN_FilterIDMask4;
00396     }
00397     else if (CAN_FilterScale == CAN_FilterScale_32Bit)
00398     {
00399       CAN->Page.Filter.FR09 = CAN_FilterID1;
00400       CAN->Page.Filter.FR10 = CAN_FilterID2;
00401       CAN->Page.Filter.FR11 = CAN_FilterID3;
00402       CAN->Page.Filter.FR12 = CAN_FilterID4;
00403       CAN->Page.Filter.FR13 = CAN_FilterIDMask1;
00404       CAN->Page.Filter.FR14 = CAN_FilterIDMask2;
00405       CAN->Page.Filter.FR15 = CAN_FilterIDMask3;
00406       CAN->Page.Filter.FR16 = CAN_FilterIDMask4;
00407     }
00408   }
00409   else
00410   {
00411     /* Filter Scale */
00412     if (CAN_FilterScale == CAN_FilterScale_8Bit)
00413     {
00414       CAN->Page.Filter.FR01 = CAN_FilterID1;
00415       CAN->Page.Filter.FR02 = CAN_FilterIDMask1;
00416       CAN->Page.Filter.FR03 = CAN_FilterID2;
00417       CAN->Page.Filter.FR04 = CAN_FilterIDMask2;
00418       CAN->Page.Filter.FR05 = CAN_FilterID3;
00419       CAN->Page.Filter.FR06 = CAN_FilterIDMask3;
00420       CAN->Page.Filter.FR07 = CAN_FilterID4;
00421       CAN->Page.Filter.FR08 = CAN_FilterIDMask4;
00422     }
00423     else if (CAN_FilterScale == CAN_FilterScale_16_8Bit)
00424     {
00425       CAN->Page.Filter.FR01 = CAN_FilterID1;
00426       CAN->Page.Filter.FR02 = CAN_FilterID2;
00427       CAN->Page.Filter.FR03 = CAN_FilterIDMask1;
00428       CAN->Page.Filter.FR04 = CAN_FilterIDMask2;
00429       CAN->Page.Filter.FR05 = CAN_FilterID3;
00430       CAN->Page.Filter.FR06 = CAN_FilterIDMask3;
00431       CAN->Page.Filter.FR07 = CAN_FilterID4;
00432       CAN->Page.Filter.FR08 = CAN_FilterIDMask4;
00433     }
00434     else if (CAN_FilterScale == CAN_FilterScale_16Bit)
00435     {
00436       CAN->Page.Filter.FR01 = CAN_FilterID1;
00437       CAN->Page.Filter.FR02 = CAN_FilterID2;
00438       CAN->Page.Filter.FR03 = CAN_FilterIDMask1;
00439       CAN->Page.Filter.FR04 = CAN_FilterIDMask2;
00440       CAN->Page.Filter.FR05 = CAN_FilterID3;
00441       CAN->Page.Filter.FR06 = CAN_FilterID4;
00442       CAN->Page.Filter.FR07 = CAN_FilterIDMask3;
00443       CAN->Page.Filter.FR08 = CAN_FilterIDMask4;
00444     }
00445     else if (CAN_FilterScale == CAN_FilterScale_32Bit)
00446     {
00447       CAN->Page.Filter.FR01 = CAN_FilterID1;
00448       CAN->Page.Filter.FR02 = CAN_FilterID2;
00449       CAN->Page.Filter.FR03 = CAN_FilterID3;
00450       CAN->Page.Filter.FR04 = CAN_FilterID4;
00451       CAN->Page.Filter.FR05 = CAN_FilterIDMask1;
00452       CAN->Page.Filter.FR06 = CAN_FilterIDMask2;
00453       CAN->Page.Filter.FR07 = CAN_FilterIDMask3;
00454       CAN->Page.Filter.FR08 = CAN_FilterIDMask4;
00455     }
00456   }
00457
00458
00459   /*---------------------------------------------------------*/
00460   /*Configuration of Filter Activation                       */
00461   /*---------------------------------------------------------*/
00462   /* Filter activation */
00463   CAN->PSR = CAN_Page_Config;
00464   if (CAN_FilterActivation != DISABLE)
00465   {
00466     if ((CAN_FilterNumber & 0x06) == 0x00) /* FCR1*/
00467     {   CAN->Page.Config.FCR1 |= (uint8_t)fact;
00468     }
00469     else if ((CAN_FilterNumber & 0x06) == 0x02) /*FCR2*/
00470     { CAN->Page.Config.FCR2 |= (uint8_t)fact;
00471     }
00472     else /*if((CAN_FilterNumber & 0x06) == 0x04)*/ /*FCR3*/
00473     { CAN->Page.Config.FCR3 |= (uint8_t)fact;
00474     }
00475   }
00476   CAN_OperatingModeRequest(CAN_OperatingMode_Normal);
00477   /*Restore Last Page*/
00478   CAN_SelectPage(can_page);
00479 }
00480
00481 /**
00482   * @brief   Enables or disables the specified CAN interrupts.
00483   * @param    CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.
00484   * @param   NewState : CAN_IT new state , can be one of @ref FunctionalState
00485   * @retval None
00486   */
00487 void CAN_ITConfig(CAN_IT_TypeDef CAN_IT, FunctionalState NewState)
00488 {
00489   uint8_t tmperrorinterrupt = 0;
00490   CAN_Page_TypeDef can_page = CAN_GetSelectedPage();
00491
00492
00493   /* Check the parameters */
00494   assert_param(IS_CAN_IT_CONFIG_OK(CAN_IT));
00495   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00496
00497   tmperrorinterrupt = (uint8_t)(((uint16_t)CAN_IT) >>7);
00498   tmperrorinterrupt = (uint8_t)((uint8_t)((uint16_t)tmperrorinterrupt & 0xF0) |
00499                                 (uint8_t)((uint8_t)((uint16_t)tmperrorinterrupt & 0x0F) >>1));
00500
00501   CAN->PSR = CAN_Page_Config;
00502   if (NewState != DISABLE)
00503   {
00504     /* Enable the selected CAN interrupt */
00505     CAN->IER |= (uint8_t)(CAN_IT);
00506     CAN->Page.Config.EIER |= (uint8_t)(tmperrorinterrupt);
00507   }
00508   else
00509   {
00510     /* Disable the selected CAN interrupt */
00511     CAN->IER &= (uint8_t)~(uint8_t)((uint16_t)CAN_IT);
00512     CAN->Page.Config.EIER &= (uint8_t)~(tmperrorinterrupt);
00513   }
00514   /*Restore Last Page*/
00515   CAN_SelectPage(can_page);
00516 }
00517
00518 /**
00519   * @brief   Enables or Disables the ST7 CAN Compatibility.
00520   * if the ST7 compatibility is Enabled, CAN provides only 2 mailboxes.
00521   * if the ST7 compatibility is Disabled, CAN provides 3 mailboxes.
00522   * @param   CAN_ST7Compatibility : CAN ST7 Compatibility , this parameter can be one of @ref CAN_ST7Compatibility_TypeDef enumeration.
00523   * @retval None
00524   */
00525 void CAN_ST7CompatibilityCmd(CAN_ST7Compatibility_TypeDef CAN_ST7Compatibility)
00526 {
00527   /* Check the parameters */
00528   assert_param(IS_CAN_ST7_COMPATIBILITY_OK(CAN_ST7Compatibility));
00529   /*Reset the old configuration of TXM2E */
00530   CAN->DGR &= (uint8_t)(~CAN_DGR_TXM2E);
00531
00532   /*Set the old configuration of TXM2E */
00533   CAN->DGR |= (uint8_t)CAN_ST7Compatibility;
00534 }
00535
00536 /**
00537   * @brief  Enables or disables the CAN Time TriggerOperation communication mode.
00538   * @param   NewState : Mode new state , can be one of @ref FunctionalState
00539   * @retval None
00540   */
00541 void CAN_TTComModeCmd(FunctionalState NewState)
00542 {
00543   CAN_Page_TypeDef can_page = CAN_GetSelectedPage();
00544   /* Check the parameters */
00545   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00546   if (NewState != DISABLE)
00547   {
00548     /*Enable the TTCM mode */
00549     CAN->MCR |= CAN_MCR_TTCM;
00550     /*Set TGT bits setting in Tx and FIFO pages*/
00551     CAN->PSR = CAN_Page_TxMailBox0;
00552     CAN->Page.TxMailbox.MDLCR |= CAN_MDLCR_TGT;
00553     CAN->PSR = CAN_Page_TxMailBox1;
00554     CAN->Page.TxMailbox.MDLCR |= CAN_MDLCR_TGT;
00555     CAN->PSR = CAN_Page_TxMailBox2;
00556     CAN->Page.TxMailbox.MDLCR |= CAN_MDLCR_TGT;
00557     CAN->PSR = CAN_Page_RxFifo;
00558     CAN->Page.RxFIFO.MDLCR |= CAN_MDLCR_TGT;
00559   }
00560   else
00561   {
00562     /*Disable the TTCM mode */
00563     CAN->MCR &= ((uint8_t)~CAN_MCR_TTCM);
00564     /*Reset TGT bits setting in Tx and FIFO pages*/
00565     CAN->PSR = CAN_Page_TxMailBox0;
00566     CAN->Page.TxMailbox.MDLCR &= ((uint8_t)~CAN_MDLCR_TGT);
00567     CAN->PSR = CAN_Page_TxMailBox1;
00568     CAN->Page.TxMailbox.MDLCR &= ((uint8_t)~CAN_MDLCR_TGT);
00569     CAN->PSR = CAN_Page_TxMailBox2;
00570     CAN->Page.TxMailbox.MDLCR &= ((uint8_t)~CAN_MDLCR_TGT);
00571     CAN->PSR = CAN_Page_RxFifo;
00572     CAN->Page.RxFIFO.MDLCR &= ((uint8_t)~CAN_MDLCR_TGT);
00573   }
00574   /*Restore Last Page*/
00575   CAN_SelectPage(can_page);
00576 }
00577
00578 /**
00579   * @brief  Initiates the transmission of a message.
00580   * @param  CAN_Id the ID number of the message, its size depends on CAN_IDE value.
00581   * @param[in] CAN_IDE the ID type of the message, this parameter can be one of the @ref CAN_Id_TypeDef enumeration.
00582   * @param[in] CAN_RTR the message type, this parameter can be one of the @ref CAN_RTR_TypeDef enumeration.
00583   * @param[in] CAN_DLC the number of data in the message type, this parameter can be a value between 0 to 7.
00584   * @param[in] CAN_Data pointer to a the @ref uint8_t table which contains data to sent.
00585   * @retval Transmit Status, this returned value can be one of the @ref CAN_TxStatus_TypeDef enumeration.
00586   */
00587 CAN_TxStatus_TypeDef CAN_Transmit(uint32_t CAN_Id,
00588                                   CAN_Id_TypeDef CAN_IDE,
00589                                   CAN_RTR_TypeDef CAN_RTR,
00590                                   uint8_t CAN_DLC,
00591                                   uint8_t *CAN_Data)
00592 {
00593   CAN_TxStatus_TypeDef CAN_TxStatus = CAN_TxStatus_NoMailBox;
00594   CAN_Page_TypeDef can_page = CAN_GetSelectedPage();
00595   /* Check the parameters */
00596   assert_param(IS_CAN_IDTYPE_OK(CAN_IDE));
00597   if (CAN_IDE != CAN_Id_Standard)
00598   {
00599     assert_param(IS_CAN_EXTID_OK(CAN_Id));
00600   }
00601   else
00602   {
00603     assert_param(IS_CAN_STDID_OK(CAN_Id));
00604   }
00605   assert_param(IS_CAN_RTR_OK(CAN_RTR));
00606   assert_param(IS_CAN_DLC_OK(CAN_DLC));
00607   /* Select one empty transmit mailbox */
00608   if ((CAN->TPR & CAN_TPR_TME0) == CAN_TPR_TME0)
00609   {
00610     CAN_TxStatus = CAN_TxStatus_MailBox0Ok;
00611   }
00612   else if ((CAN->TPR & CAN_TPR_TME1) == CAN_TPR_TME1)
00613   {
00614     CAN_TxStatus = CAN_TxStatus_MailBox1Ok;
00615   }
00616   else if ((CAN->TPR & CAN_TPR_TME2) == CAN_TPR_TME2)
00617   {
00618     CAN_TxStatus = CAN_TxStatus_MailBox2Ok;
00619   }
00620   else
00621   {
00622     CAN_TxStatus = CAN_TxStatus_NoMailBox;
00623   }
00624   if (CAN_TxStatus != CAN_TxStatus_NoMailBox)
00625   {
00626     CAN->PSR = (uint8_t)CAN_TxStatus;
00627     /* Set up the Id */
00628     if (CAN_IDE != CAN_Id_Standard)
00629     {
00630       CAN_Id &= (uint32_t)CAN_EXTID_SIZE;
00631       CAN->Page.TxMailbox.MIDR4 = (uint8_t)(CAN_Id);
00632       CAN_Id = CAN_Id>>8;
00633       CAN->Page.TxMailbox.MIDR3 = (uint8_t)(CAN_Id);
00634       CAN_Id = CAN_Id>>8;
00635       CAN->Page.TxMailbox.MIDR2 = (uint8_t)(CAN_Id);
00636       CAN_Id = CAN_Id>>8;
00637       CAN->Page.TxMailbox.MIDR1 = (uint8_t)(CAN_Id |CAN_IDE | CAN_RTR);
00638     }
00639     else
00640     {
00641       CAN_Id &= (uint16_t)CAN_STDID_SIZE;
00642       CAN->Page.TxMailbox.MIDR1 = (uint8_t)((CAN_Id>>6) | (CAN_RTR)) ;
00643       CAN->Page.TxMailbox.MIDR2 = (uint8_t)(CAN_Id<<2);
00644     }
00645     /* Set up the DLC                 */
00646     /*clear old DLC value*/
00647     CAN->Page.TxMailbox.MDLCR &= (uint8_t)0xF0;
00648     /*set the new value of DLC*/
00649     CAN->Page.TxMailbox.MDLCR |= CAN_DLC;
00650     /* Set up the data field */
00651     CAN->Page.TxMailbox.MDAR1 = CAN_Data[0];
00652     CAN->Page.TxMailbox.MDAR2 = CAN_Data[1];
00653     CAN->Page.TxMailbox.MDAR3 = CAN_Data[2];
00654     CAN->Page.TxMailbox.MDAR4 = CAN_Data[3];
00655     CAN->Page.TxMailbox.MDAR5 = CAN_Data[4];
00656     CAN->Page.TxMailbox.MDAR6 = CAN_Data[5];
00657     CAN->Page.TxMailbox.MDAR7 = CAN_Data[6];
00658     CAN->Page.TxMailbox.MDAR8 = CAN_Data[7];
00659     /* Request transmission */
00660     CAN->Page.TxMailbox.MCSR |= CAN_MCSR_TXRQ;
00661   }
00662   /*Restore Last Page*/
00663   CAN_SelectPage(can_page);
00664   return (CAN_TxStatus_TypeDef)CAN_TxStatus;
00665 }
00666
00667 /**
00668   * @brief  Checks the transmission of a message.
00669   * @param  CAN_TransmitMailbox : the number of the mailbox that is used for transmission, can be on of  @ref CAN_TransmitMailBox_TypeDef.
00670   * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, CAN_TxStatus_Failed in an other case.
00671   */
00672 CAN_TxStatus_TypeDef CAN_TransmitStatus(CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox)
00673 {
00674   /* RQCP, TXOK and TME bits */
00675   CAN_TxStatus_TypeDef tstate = CAN_TxStatus_Failed;
00676   uint8_t tmpstate=0;
00677
00678   /* Check the parameters */
00679   assert_param(IS_CAN_TRANSMITMAILBOX_OK(CAN_TransmitMailbox));
00680
00681   switch (CAN_TransmitMailbox)
00682   {
00683   case (CAN_TransmitMailBox_0): tmpstate = (uint8_t)((CAN->TSR & (uint8_t)(CAN_TSR_RQCP0|CAN_TSR_TXOK0)));
00684   tmpstate |= (uint8_t)((CAN->TPR & CAN_TPR_TME0));
00685   break;
00686   case (CAN_TransmitMailBox_1): tmpstate = (uint8_t)((uint8_t)(CAN->TSR & (uint8_t)(CAN_TSR_RQCP1|CAN_TSR_TXOK1))>>1);
00687   tmpstate |= (uint8_t)((uint8_t)(CAN->TPR & CAN_TPR_TME1) >> 1);
00688   break;
00689   case (CAN_TransmitMailBox_2): tmpstate = (uint8_t)((uint8_t)(CAN->TSR & (uint8_t)(CAN_TSR_RQCP2|CAN_TSR_TXOK2))>>2);
00690   tmpstate |= (uint8_t)((uint8_t)(CAN->TPR & CAN_TPR_TME2) >> 2);
00691   break;
00692   default:
00693     tstate = CAN_TxStatus_Failed;
00694     break;
00695   }
00696
00697   switch (tmpstate)
00698   {
00699     /*transmit pending  */
00700   case (0x00): tstate = CAN_TxStatus_Pending;
00701   break;
00702   /* transmit failed  */
00703   case (0x05): tstate = CAN_TxStatus_Failed;
00704   break;
00705   /* transmit succeeded */
00706   case (0x15): tstate = CAN_TxStatus_Ok;
00707   break;
00708   /* transmit mailbox is empty : no activity on this TX mail box */
00709   case (0x04): tstate = CAN_TxStatus_MailBoxEmpty;
00710   break;
00711   default:
00712     tstate = CAN_TxStatus_Failed;
00713     break;
00714   }
00715
00716   return (CAN_TxStatus_TypeDef)tstate;
00717 }
00718
00719 /**
00720   * @brief  Cancels a transmit request.
00721   * @param  CAN_TransmitMailbox : the Transmission mailbox, can be one of CAN_TransmitMailBox_TypeDef
00722   * @retval None
00723   */
00724 void CAN_CancelTransmit(CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox)
00725 {
00726   CAN_Page_TypeDef can_page = CAN_GetSelectedPage();
00727   /* Check the parameters */
00728   assert_param(IS_CAN_TRANSMITMAILBOX_OK(CAN_TransmitMailbox));
00729   /*switch to the specific page */
00730   CAN->PSR = (uint8_t)CAN_TransmitMailbox;
00731   /* abort transmission */
00732   CAN->Page.TxMailbox.MCSR |= CAN_MCSR_ABRQ;
00733   /*Restore Last Page*/
00734   CAN_SelectPage(can_page);
00735 }
00736
00737 /**
00738   * @brief   Releases the CAN FIFO.
00739   * @param  None
00740   * @retval None
00741   */
00742 void CAN_FIFORelease(void)
00743 {
00744   /* Release FIFO*/
00745   CAN->RFR = CAN_RFR_RFOM; /*rc-w1*/
00746 }
00747
00748 /**
00749   * @brief  Returns the number of pending messages.
00750   * @retval Number of pending messages.
00751   */
00752 CAN_NbrPendingMessage_TypeDef CAN_MessagePending(void)
00753 {
00754   CAN_NbrPendingMessage_TypeDef msgpending = CAN_NbrPendingMessage_0;
00755   msgpending = (CAN_NbrPendingMessage_TypeDef)(CAN->RFR & CAN_RFR_FMP01);
00756   return (CAN_NbrPendingMessage_TypeDef)msgpending;
00757 }
00758
00759 /**
00760   * @brief   Receives a message which contains CAN Id, IDE, RTR
00761   * DLC, data and FMI number.
00762   * In order to get these data, use CAN_GetReceivedId(), CAN_GetReceivedIDE(), CAN_GetReceivedRTR(),
00763   * CAN_GetReceivedDLC(), CAN_GetReceivedFMI() and CAN_GetReceivedData() functions.
00764   * @param  None
00765   * @retval None
00766   */
00767 void CAN_Receive(void)
00768 {
00769   CAN_Page_TypeDef can_page = CAN_GetSelectedPage();
00770   uint32_t temp1 = 0, temp2 = 0, temp3 = 0;
00771
00772   /* select Fifo page*/
00773   CAN->PSR = CAN_Page_RxFifo;
00774
00775   /* Get the Id */
00776   _IDE = (uint8_t)(CAN->Page.RxFIFO.MIDR1 & CAN_Id_Extended);
00777   if (_IDE != CAN_Id_Standard)
00778   {
00779     temp1 = ((uint32_t)((uint32_t)CAN->Page.RxFIFO.MIDR3) << 8);
00780     temp2 = ((uint32_t)((uint32_t)CAN->Page.RxFIFO.MIDR2) << 16);
00781     temp3 = ((uint32_t)((uint32_t)CAN->Page.RxFIFO.MIDR1 & 0x1F) << 24);
00782
00783     _Id = (uint32_t)CAN_EXTID_SIZE & ((CAN->Page.RxFIFO.MIDR4) | temp1 | temp2 | temp3 );
00784   }
00785   else
00786   {
00787     temp1 = (uint16_t)((uint16_t)((uint16_t)((uint16_t)CAN->Page.RxFIFO.MIDR1 & 0x1F) << 6));
00788     temp2 = (uint16_t)((uint16_t)((uint16_t)CAN->Page.RxFIFO.MIDR2 >> 2)&0x3F);
00789
00790     _Id = (uint16_t)CAN_STDID_SIZE & (temp1 | temp2 );
00791   }
00792
00793   _RTR = (uint8_t)((uint8_t)0x20 & CAN->Page.RxFIFO.MIDR1);
00794
00795   /* Get the DLC */
00796   _DLC = (uint8_t)(CAN->Page.RxFIFO.MDLCR & (uint8_t)0x0F);
00797
00798   /* Get the FMI */
00799   _FMI = CAN->Page.RxFIFO.MFMI;
00800
00801   /* Get the data field */
00802   _Data[0] = CAN->Page.RxFIFO.MDAR1;
00803   _Data[1] = CAN->Page.RxFIFO.MDAR2;
00804   _Data[2] = CAN->Page.RxFIFO.MDAR3;
00805   _Data[3] = CAN->Page.RxFIFO.MDAR4;
00806   _Data[4] = CAN->Page.RxFIFO.MDAR5;
00807   _Data[5] = CAN->Page.RxFIFO.MDAR6;
00808   _Data[6] = CAN->Page.RxFIFO.MDAR7;
00809   _Data[7] = CAN->Page.RxFIFO.MDAR8;
00810
00811   /* Release the FIFO */
00812   CAN_FIFORelease();
00813   /*Restore Last Page*/
00814   CAN_SelectPage(can_page);
00815 }
00816
00817 /**
00818   * @brief  Gets the  CAN Id of the received message.
00819   * @param  None
00820   * @retval the received CAN message Id.
00821   * @par Required preconditions:
00822   * This function is used to get data loaded by CAN_Receive function.
00823   * Before using this function, CAN_Receive function must be called.
00824   */
00825 uint32_t CAN_GetReceivedId(void)
00826 {
00827   return (_Id);
00828 }
00829
00830 /**
00831   * @brief  Gets the  CAN IDE of the received message.
00832   * @param  None
00833   * @retval the received CAN message IDE.
00834   * @par Required preconditions:
00835   * This function is used to get data loaded by CAN_Receive function.
00836   * Before using this function, CAN_Receive function must be called.
00837   */
00838 CAN_Id_TypeDef CAN_GetReceivedIDE(void)
00839 {
00840   return (CAN_Id_TypeDef)(_IDE);
00841 }
00842
00843 /**
00844   * @brief  Gets the  CAN RTR of the received message.
00845   * @param  None
00846   * @retval the received CAN message RTR.
00847   * @par Required preconditions:
00848   * This function is used to get data loaded by CAN_Receive function.
00849   * Before using this function, CAN_Receive function must be called.
00850   */
00851 CAN_RTR_TypeDef CAN_GetReceivedRTR(void)
00852 {
00853   return (CAN_RTR_TypeDef)(_RTR);
00854 }
00855
00856 /**
00857   * @brief  Gets the  CAN DLC of the received message.
00858   * @param  None
00859   * @retval the received CAN message DLC.
00860   * @par Required preconditions:
00861   * This function is used to get data loaded by CAN_Receive function.
00862   * Before using this function, CAN_Receive function must be called.
00863   */
00864 uint8_t CAN_GetReceivedDLC(void)
00865 {
00866   return (_DLC);
00867 }
00868
00869 /**
00870   * @brief  Gets the  CAN Data of the received message.
00871   * @param  CAN_DataIndex : number of the received Data, it can
00872   *  be an integer between 0 to 7.
00873   * @retval the received CAN message ith Data.
00874   * @par Required preconditions:
00875   * This function is used to get data loaded by CAN_Receive function.
00876   * Before using this function, CAN_Receive function must be called.
00877   */
00878 uint8_t CAN_GetReceivedData(uint8_t CAN_DataIndex)
00879 {
00880   assert_param(IS_CAN_DLC_OK(CAN_DataIndex));
00881   return (_Data[CAN_DataIndex]);
00882 }
00883
00884 /**
00885   * @brief  Gets the  CAN FMI of the received message.
00886   * @param  None
00887   * @retval the received CAN message FMI.
00888   * @par Required preconditions:
00889   * This function is used to get data loaded by CAN_Receive function.
00890   * Before using this function, CAN_Receive function must be called.
00891   */
00892 uint8_t CAN_GetReceivedFMI(void)
00893 {
00894   return (_FMI);
00895 }
00896
00897 /**
00898   * @brief  Returns the Received time stamp.
00899   * @param  None
00900   * @retval uint16_t the received  time stamp.
00901   */
00902 uint16_t CAN_GetMessageTimeStamp(void)
00903 {
00904   uint16_t timestamp = 0;
00905   CAN_Page_TypeDef can_page = CAN_GetSelectedPage();
00906
00907   /*switch to the specific page */
00908   CAN->PSR = CAN_Page_RxFifo;
00909   /* Get the Received Time stamp */
00910   timestamp = CAN->Page.RxFIFO.MTSRL;
00911   timestamp |= (uint16_t)(((uint16_t)CAN->Page.RxFIFO.MTSRH)<<8);
00912
00913   /*Restore Last Page*/
00914   CAN_SelectPage(can_page);
00915
00916   return (uint16_t)(timestamp);
00917 }
00918
00919 /**
00920   * @brief  Enters the Sleep low power mode.
00921   * @param  None
00922   * @retval  CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed in an other case.
00923   */
00924 CAN_Sleep_TypeDef CAN_Sleep(void)
00925 {
00926   CAN_Sleep_TypeDef sleepstatus = CAN_Sleep_Failed;
00927
00928   /* Request Sleep mode */
00929   CAN->MCR = (uint8_t)((uint8_t)(CAN->MCR & (uint8_t)(~CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
00930
00931   /* Sleep mode status */
00932   if ((CAN->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)
00933   {
00934     /* Sleep mode not entered */
00935     sleepstatus =  CAN_Sleep_Ok;
00936   }
00937
00938   /* At this step, sleep mode status */
00939   return (CAN_Sleep_TypeDef) sleepstatus;
00940 }
00941
00942 /**
00943   * @brief  Wakes the CAN up.
00944   * @param  None
00945   * @retval CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed in an other  case.
00946   */
00947 CAN_WakeUp_TypeDef CAN_WakeUp(void)
00948 {
00949   CAN_WakeUp_TypeDef wakeupstatus = CAN_WakeUp_Failed;
00950
00951   /* Wake up request */
00952   CAN->MCR &= (uint8_t)(~CAN_MCR_SLEEP);
00953
00954   /* Sleep mode status */
00955   if ((CAN->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)
00956   {
00957     /* Sleep mode exited */
00958     wakeupstatus = CAN_WakeUp_Ok;
00959   }
00960
00961   /* At this step, sleep mode status */
00962   return (CAN_WakeUp_TypeDef)wakeupstatus;
00963 }
00964
00965 /**
00966   * @brief  Select the CAN Operation mode.
00967   * @param  CAN_OperatingMode CAN Operating Mode ,
00968   *         this parameter can be one of @ref CAN_OperatingMode_TypeDef enumeration.
00969   * @retval the status of the requested mode which can be
00970   *         - CAN_ModeStatus_Failed    CAN failed entering the specific mode
00971   *         - CAN_ModeStatus_Success  CAN Succeed entering the specific mode
00972
00973   */
00974 CAN_ModeStatus_TypeDef CAN_OperatingModeRequest(CAN_OperatingMode_TypeDef CAN_OperatingMode)
00975 {
00976   uint16_t timeout = CAN_ACKNOWLEDGE_TIMEOUT;
00977   uint8_t modestatus = 0;
00978
00979   assert_param(IS_CAN_OPERATINGMODE_OK(CAN_OperatingMode));
00980
00981   if (CAN_OperatingMode == CAN_OperatingMode_Initialization)
00982   {
00983     /* Request initialisation */
00984     CAN->MCR = (uint8_t)((uint8_t)(CAN->MCR & (uint8_t)(~CAN_MCR_SLEEP)) | CAN_MCR_INRQ);
00985
00986     /* Wait the acknowledge */
00987     while (((CAN->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0))
00988     {
00989       timeout--;
00990     }
00991     if ((CAN->MSR & CAN_MODE_MASK) != CAN_MSR_INAK)
00992     {
00993       modestatus = CAN_ModeStatus_Failed;
00994     }
00995     else
00996     {
00997       modestatus = CAN_ModeStatus_Success;
00998     }
00999
01000   }
01001   else  if (CAN_OperatingMode == CAN_OperatingMode_Normal)
01002   {
01003     /* Request leave initialisation and sleep mode  and enter Normal mode */
01004     CAN->MCR &= (uint8_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ));
01005
01006     /* Wait the acknowledge */
01007     while (((CAN->MSR & CAN_MODE_MASK) != 0) && (timeout!=0))
01008     {
01009       timeout--;
01010     }
01011     if ((CAN->MSR & CAN_MODE_MASK) != 0)
01012     {
01013       modestatus = CAN_ModeStatus_Failed;
01014     }
01015     else
01016     {
01017       modestatus = CAN_ModeStatus_Success;
01018     }
01019   }
01020   else  if (CAN_OperatingMode == CAN_OperatingMode_Sleep)
01021   {
01022     /* Request Sleep mode */
01023     CAN->MCR = (uint8_t)((uint8_t)(CAN->MCR & (uint8_t)(~CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
01024
01025     /* Wait the acknowledge */
01026     while (((CAN->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0))
01027     {
01028       timeout--;
01029     }
01030     if ((CAN->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK)
01031     {
01032       modestatus = CAN_ModeStatus_Failed;
01033     }
01034     else
01035     {
01036       modestatus = CAN_ModeStatus_Success;
01037     }
01038   }
01039   else
01040   {
01041     modestatus = CAN_ModeStatus_Failed;
01042   }
01043   return (CAN_ModeStatus_TypeDef)(modestatus);
01044 }
01045
01046 /**
01047   * @brief  Gets the  Last Error Code.
01048   * @param  None
01049   * @retval Error Code.
01050   */
01051 CAN_ErrorCode_TypeDef CAN_GetLastErrorCode(void)
01052 {
01053   CAN_ErrorCode_TypeDef errcode = CAN_ErrorCode_NoErr;
01054   CAN_Page_TypeDef can_page = CAN_GetSelectedPage();
01055
01056   CAN->PSR = CAN_Page_Config;
01057   errcode = (CAN_ErrorCode_TypeDef)((CAN->Page.Config.ESR) & (CAN_ESR_LEC));
01058
01059   /*Restore Last Page*/
01060   CAN_SelectPage(can_page);
01061
01062   return (CAN_ErrorCode_TypeDef)(errcode);
01063 }
01064
01065 /**
01066   * @brief  Clears the CAN's pending flags.
01067   * @param   CAN_Flag : Flag to be cleared, can be one of the following parameters:
01068   *          CAN_FLAG_RQCP0            Request MailBox0  Flag
01069   *          CAN_FLAG_RQCP1            Request MailBox1  Flag
01070   *          CAN_FLAG_RQCP2            Request MailBox2  Flag
01071   *          CAN_FLAG_FF               FIFO Full  Flag
01072   *          CAN_FLAG_FOV              FIFO Overrun  Flag
01073   *          CAN_FLAG_WKU              wake up  Flag
01074   *          CAN_FLAG_LEC              Last error code Flag
01075   * @retval None
01076   */
01077 void CAN_ClearFlag(CAN_FLAG_TypeDef CAN_Flag)
01078 {
01079   CAN_Page_TypeDef can_page = (CAN_Page_TypeDef)0;
01080   /* Check the parameters */
01081   assert_param(IS_CAN_FLAG_CLEAR_OK(CAN_Flag));
01082   if (((uint16_t)CAN_Flag & 0x0700)!= RESET)
01083   {
01084     if (((uint16_t)CAN_Flag & 0x020B)!= RESET)
01085     {
01086       /*Receive Flags*/
01087       CAN->RFR = (uint8_t)(CAN_Flag);
01088     }
01089     else if (((uint16_t)CAN_Flag & 0x0403)!= RESET)
01090     {
01091       /*Transmit Flags*/
01092       CAN->TSR = (uint8_t)(CAN_Flag);
01093     }
01094     else /*if((CAN_Flag & 0x0108)!=(uint16_t)RESET)*/
01095     {
01096       /*wake up Flags*/
01097       CAN->MSR = (uint8_t)(CAN_Flag);
01098     }
01099   }
01100   else
01101   {
01102     /*Error Flags*/
01103     can_page = CAN_GetSelectedPage();
01104
01105     /* Clear the selected CAN flags */
01106     CAN->PSR = CAN_Page_Config;
01107     CAN->Page.Config.ESR = (uint8_t)RESET;
01108
01109     /*Restore Last Page*/
01110     CAN_SelectPage(can_page);
01111   }
01112 }
01113
01114 /**
01115   * @brief  Checks whether the specified CAN flag is set or not.
01116   * @param  CAN_Flag : specifies the flag to check, can be one of @ref CAN_FLAG_TypeDef enumeration.
01117   * @retval The new state of CAN_FLAG which can be one of @ref FlagStatus.
01118   */
01119 FlagStatus CAN_GetFlagStatus(CAN_FLAG_TypeDef CAN_Flag)
01120 {
01121   FlagStatus bitstatus = RESET;
01122   CAN_Page_TypeDef can_page = (CAN_Page_TypeDef)0;
01123
01124   /* Check the parameters */
01125   assert_param(IS_CAN_FLAG_STATUS_OK(CAN_Flag));
01126
01127   if (((uint16_t)CAN_Flag & 0x0700)!= RESET)
01128   {
01129     if (((uint16_t)CAN_Flag & 0x020B)!= RESET)
01130     {
01131       /*Receive Flags*/
01132       if ((CAN->RFR & (uint16_t)CAN_Flag )!= RESET)
01133       {
01134         /* CAN_FLAG is set */
01135         bitstatus = SET;
01136       }
01137       else
01138       {
01139         /* CAN_FLAG is reset */
01140         bitstatus = RESET;
01141       }
01142
01143     }
01144     else if (((uint16_t)CAN_Flag & 0x0403)!= RESET)
01145     {
01146       /*Transmit Flags*/
01147       if ((CAN->TSR & (uint16_t)CAN_Flag )!= RESET)
01148       {
01149         /* CAN_FLAG is set */
01150         bitstatus = SET;
01151       }
01152       else
01153       {
01154         /* CAN_FLAG is reset */
01155         bitstatus = RESET;
01156       }
01157     }
01158     else /*if((CAN_Flag & 0x0108)!=(uint16_t)RESET)*/
01159     {
01160       /*wake up Flags*/
01161       if ((CAN->MSR & (uint16_t)CAN_Flag )!= RESET)
01162       {
01163         /* CAN_FLAG is set */
01164         bitstatus = SET;
01165       }
01166       else
01167       {
01168         /* CAN_FLAG is reset */
01169         bitstatus = RESET;
01170       }
01171     }
01172   }
01173   else
01174   {
01175     /*Error Flags*/
01176     can_page = CAN_GetSelectedPage();
01177
01178     CAN->PSR = CAN_Page_Config;
01179     if ((CAN->Page.Config.ESR & (uint16_t)CAN_Flag) != RESET)
01180     {
01181       /* CAN_FLAG is set */
01182       bitstatus = SET;
01183     }
01184     else
01185     {
01186       /* CAN_FLAG is reset */
01187       bitstatus = RESET;
01188     }
01189     /*Restore Last Page*/
01190     CAN_SelectPage(can_page);
01191   }
01192
01193
01194   /* Return the CAN_FLAG status */
01195   return  (FlagStatus)bitstatus;
01196 }
01197
01198 /**
01199   * @brief  Checks whether the specified CAN interrupt has occurred or not.
01200   * @param   CAN_IT: specifies the CAN interrupt source to check, can be one of @ref CAN_IT_TypeDef.
01201   * @retval The new state of CAN_IT, which can be one of @ref ITStatus.
01202   */
01203 ITStatus CAN_GetITStatus(CAN_IT_TypeDef CAN_IT)
01204 {
01205   ITStatus pendingbitstatus = RESET;
01206   CAN_Page_TypeDef can_page = CAN_GetSelectedPage();
01207
01208   /* Check the parameters */
01209   assert_param(IS_CAN_IT_STATUS_OK(CAN_IT));
01210
01211
01212   switch (CAN_IT)
01213   {
01214   case CAN_IT_TME:
01215     if ((CAN->IER & CAN_IER_TMEIE) !=RESET)
01216     {
01217       pendingbitstatus = CheckITStatus(CAN->TSR, CAN_TSR_RQCP012);
01218     }
01219     else
01220     {
01221       pendingbitstatus = RESET;
01222     }
01223     break;
01224
01225   case CAN_IT_FMP:
01226     if ((CAN->IER & CAN_IER_FMPIE) !=RESET)
01227     {
01228       pendingbitstatus = CheckITStatus(CAN->RFR, CAN_RFR_FMP01);
01229     }
01230     else
01231     {
01232       pendingbitstatus = RESET;
01233     }
01234     break;
01235   case CAN_IT_FF:
01236     if ((CAN->IER & CAN_IER_FFIE) !=RESET)
01237     {
01238       pendingbitstatus = CheckITStatus(CAN->RFR, CAN_RFR_FULL);
01239     }
01240     else
01241     {
01242       pendingbitstatus = RESET;
01243     }
01244     break;
01245   case CAN_IT_FOV:
01246     if ((CAN->IER & CAN_IER_FOVIE) !=RESET)
01247     {
01248       pendingbitstatus = CheckITStatus(CAN->RFR, CAN_RFR_FOVR);
01249     }
01250     else
01251     {
01252       pendingbitstatus = RESET;
01253     }
01254     break;
01255   case CAN_IT_WKU:
01256     if ((CAN->IER & CAN_IER_WKUIE) !=RESET)
01257     {
01258       pendingbitstatus = CheckITStatus(CAN->MSR, CAN_MSR_WKUI);
01259     }
01260     else
01261     {
01262       pendingbitstatus = RESET;
01263     }
01264     break;
01265
01266   case CAN_IT_ERR:
01267     CAN->PSR = CAN_Page_Config;
01268     if ((CAN->Page.Config.EIER & CAN_EIER_ERRIE) !=RESET)
01269     {
01270       pendingbitstatus = CheckITStatus(CAN->Page.Config.ESR, CAN_ESR_EWGF|CAN_ESR_EPVF|CAN_ESR_BOFF|CAN_ESR_LEC);
01271     }
01272     else
01273     {
01274       pendingbitstatus = RESET;
01275     }
01276     break;
01277
01278   case CAN_IT_EWG:
01279     CAN->PSR = CAN_Page_Config;
01280     if ((CAN->Page.Config.EIER & CAN_EIER_EWGIE) !=RESET)
01281     {
01282       pendingbitstatus = CheckITStatus(CAN->Page.Config.ESR, CAN_ESR_EWGF);
01283     }
01284     else
01285     {
01286       pendingbitstatus = RESET;
01287     }
01288     break;
01289
01290   case CAN_IT_EPV:
01291     CAN->PSR = CAN_Page_Config;
01292     if ((CAN->Page.Config.EIER & CAN_EIER_EPVIE) !=RESET)
01293     {
01294       pendingbitstatus = CheckITStatus(CAN->Page.Config.ESR, CAN_ESR_EPVF);
01295     }
01296     else
01297     {
01298       pendingbitstatus = RESET;
01299     }
01300     break;
01301   case CAN_IT_BOF:
01302     CAN->PSR = CAN_Page_Config;
01303     if ((CAN->Page.Config.EIER & CAN_EIER_BOFIE) !=RESET)
01304     {
01305       pendingbitstatus = CheckITStatus(CAN->Page.Config.ESR, CAN_ESR_BOFF);
01306     }
01307     else
01308     {
01309       pendingbitstatus = RESET;
01310     }
01311     break;
01312   case CAN_IT_LEC:
01313     CAN->PSR = CAN_Page_Config;
01314     if ((CAN->Page.Config.EIER & CAN_EIER_LECIE) !=RESET)
01315     {
01316       pendingbitstatus = CheckITStatus(CAN->Page.Config.ESR, CAN_ESR_LEC);
01317     }
01318     else
01319     {
01320       pendingbitstatus = RESET;
01321     }
01322     break;
01323   default :
01324     pendingbitstatus = RESET;
01325     break;
01326   }
01327   /*Restore Last Page*/
01328   CAN_SelectPage(can_page);
01329   /* Return the CAN_IT status */
01330   return  (ITStatus)pendingbitstatus;
01331 }
01332
01333 /**
01334   * @brief   Clears the CAN’s interrupt pending bits.
01335   * @param   CAN_IT: specifies the interrupt pending bit to clear,
01336   *  can be one of the following parameters:
01337   *                            CAN_IT_TME = Transmit mailbox empty interrupt
01338   *                             CAN_IT_FF =FIFO  full    interrupt
01339   *                            CAN_IT_FOV =FIFO  overrun  interrupt
01340   *                             CAN_IT_WKU =Wake-up interrupt
01341   *                             CAN_IT_ERR =General Error interrupt
01342   *                             CAN_IT_EWG =Error warning interrupt
01343   *                             CAN_IT_EPV  =Error passive  interrupt
01344   *                             CAN_IT_BOF = Bus-off   interrupt
01345   *                             CAN_IT_LEC  =Last error code interrupt
01346   * @retval None
01347   */
01348 void CAN_ClearITPendingBit(CAN_IT_TypeDef CAN_IT)
01349 {
01350   CAN_Page_TypeDef can_page = CAN_GetSelectedPage();
01351   /* Check the parameters */
01352   assert_param(IS_CAN_IT_PENDING_BIT_OK(CAN_IT));
01353
01354   switch (CAN_IT)
01355   {
01356   case CAN_IT_TME:
01357     CAN->TSR = CAN_TSR_RQCP012;/* rc_w1*/
01358     break;
01359
01360   case CAN_IT_FF:
01361     CAN->RFR = CAN_RFR_FULL; /* rc_w1*/
01362     break;
01363
01364   case CAN_IT_FOV:
01365     CAN->RFR = CAN_RFR_FOVR; /* rc_w1*/
01366     break;
01367
01368   case CAN_IT_WKU:
01369     CAN->MSR = CAN_MSR_WKUI;  /* rc_w1*/
01370     break;
01371
01372   case CAN_IT_ERR:
01373     CAN->PSR = CAN_Page_Config;
01374     CAN->Page.Config.ESR = (uint8_t)CAN_ESR_RESET_VALUE;
01375     CAN->MSR = CAN_MSR_ERRI;
01376     break;
01377
01378   case CAN_IT_EWG:
01379     CAN->MSR = CAN_MSR_ERRI;
01380     break;
01381
01382   case CAN_IT_EPV:
01383     CAN->MSR = CAN_MSR_ERRI;
01384     break;
01385
01386   case CAN_IT_BOF:
01387     CAN->MSR = CAN_MSR_ERRI;
01388     break;
01389
01390   case CAN_IT_LEC:
01391     CAN->PSR = CAN_Page_Config;
01392     CAN->Page.Config.ESR = (uint8_t)CAN_ESR_RESET_VALUE;
01393     break;
01394
01395   default :
01396     break;
01397   }
01398   /*Restore Last Page*/
01399   CAN_SelectPage(can_page);
01400 }
01401
01402 /**
01403   * @brief  Gets the selected registers page.
01404   * @param  None
01405   * @retval the selected page which can be one of the @ref CAN_Page_TypeDef.
01406   */
01407 CAN_Page_TypeDef CAN_GetSelectedPage(void)
01408 {
01409   return (CAN_Page_TypeDef)(CAN->PSR);
01410 }
01411
01412 /**
01413   * @brief  Sets the registers page to be selected.
01414   * @param  CAN_Page: the selected page which can be one of the @ref CAN_Page_TypeDef.
01415   * @retval None
01416   */
01417 void CAN_SelectPage(CAN_Page_TypeDef CAN_Page)
01418 {
01419   CAN->PSR = (uint8_t)CAN_Page;
01420 }
01421
01422 /**
01423   * @brief  Checks whether the CAN interrupt has occurred or not.
01424   * @param   CAN_Reg: specifies the CAN interrupt register to check.
01425   * @param   It_Bit: specifies the interrupt source bit to check.
01426   * @retval The new state of the CAN Interrupt, which can be one of ITStatus.
01427   */
01428 static ITStatus CheckITStatus(uint8_t CAN_Reg, uint8_t It_Bit)
01429 {
01430   ITStatus pendingbitstatus = RESET;
01431   if ((CAN_Reg & It_Bit) != (uint8_t)RESET)
01432   {
01433     /* CAN_IT is set */
01434     pendingbitstatus = SET;
01435   }
01436   else
01437   {
01438     /* CAN_IT is reset */
01439     pendingbitstatus = RESET;
01440   }
01441   return (ITStatus)pendingbitstatus;
01442 }
01443
01444 /**
01445   * @}
01446   */
01447
01448 /**
01449   * @}
01450   */
01451
01452 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_can.h Source File

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stm8s_can.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_can.h
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all the functions for the CAN peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Define to prevent recursive inclusion -------------------------------------*/
00029 #ifndef __STM8S_CAN_H
00030 #define __STM8S_CAN_H
00031
00032 /* Includes ------------------------------------------------------------------*/
00033 #include "stm8s.h"
00034
00035 /* Exported constants --------------------------------------------------------*/
00036 #define CAN_STDID_SIZE ((uint16_t)0x07FF)
00037 #define CAN_EXTID_SIZE ((uint32_t)0x1FFFFFFF)
00038 #define CAN_DLC_MAX ((uint8_t)0x08)
00039
00040
00041 /** @addtogroup CAN_Exported_Types
00042   * @{
00043   */
00044
00045
00046 /**
00047   * @brief  CAN Page Mapping
00048  */
00049 typedef enum
00050 {
00051  CAN_Page_TxMailBox0  = ((uint8_t) 0), /*!< CAN TX mailbox 0 reg page */
00052  CAN_Page_TxMailBox1  = ((uint8_t) 1), /*!< CAN TX mailbox 1 reg page */
00053  CAN_Page_TxMailBox2  = ((uint8_t) 5), /*!< CAN TX mailbox 2 reg page */
00054  CAN_Page_Filter01    = ((uint8_t) 2), /*!< CAN Filters 0 & 1 reg page*/
00055  CAN_Page_Filter23    = ((uint8_t) 3), /*!< CAN Filters 2 & 3 reg page*/
00056  CAN_Page_Filter45    = ((uint8_t) 4), /*!< CAN Filters 4 & 5 reg page*/
00057  CAN_Page_Config      = ((uint8_t) 6), /*!< CAN Configuration control/status reg page*/
00058  CAN_Page_RxFifo      = ((uint8_t) 7) /*!< CAN RX FIFO registers page */
00059 }CAN_Page_TypeDef;
00060
00061
00062
00063 /**
00064   * @brief   CAN sleep constants
00065  */
00066 typedef enum {
00067   CAN_InitStatus_Failed =0,                        /*!< CAN initialization failed */
00068   CAN_InitStatus_Success =! CAN_InitStatus_Failed  /*!< CAN initialization OK*/
00069 } CAN_InitStatus_TypeDef;
00070
00071
00072  /**
00073   * @brief  CAN operating mode */
00074  typedef enum
00075 {
00076   CAN_OperatingMode_Initialization    =((uint8_t)0x00),    /*!< Initialization mode */
00077   CAN_OperatingMode_Normal            =((uint8_t)0x01),    /*!< Normal mode */
00078   CAN_OperatingMode_Sleep             =((uint8_t)0x02)    /*!< sleep mode */
00079 }CAN_OperatingMode_TypeDef;
00080
00081  /**
00082   * @brief  CAN operating mode status */
00083  typedef enum
00084 {
00085   CAN_ModeStatus_Failed    = ((uint8_t)0x00),          /*!< CAN entering the specific mode failed */
00086   CAN_ModeStatus_Success    =! CAN_ModeStatus_Failed   /*!< CAN entering the specific mode Succeed */
00087 }CAN_ModeStatus_TypeDef;
00088
00089  /**
00090   * @brief   CAN Time Triggered Communication mode
00091   */
00092 typedef enum
00093 {
00094  CAN_MasterCtrl_AllDisabled          =((uint8_t)0x00),  /*!<  CAN  ALL Master Control Option are DISABLED */
00095  CAN_MasterCtrl_AllEnabled           =((uint8_t)0xFC),  /*!<  CAN  ALL Master Control Option are DISABLED */
00096  CAN_MasterCtrl_TimeTriggerCOMMode   =((uint8_t)0x80),  /*!<  CAN Time Triggered Communication mode ENABLED */
00097  CAN_MasterCtrl_AutoBusOffManagement =((uint8_t)0x40),  /*!<  CAN Auto Bus Off Management ENABLED */
00098  CAN_MasterCtrl_AutoWakeUpMode       =((uint8_t)0x20),  /*!<  CAN Automatic WakeUp Mode ENABLED , sleep mode is left automatically by hardware  */
00099  CAN_MasterCtrl_NoAutoReTx           =((uint8_t)0x10),  /*!<  CAN Non Automatic Retransmission ENABLED, MSG  will be transmitted only once */
00100  CAN_MasterCtrl_RxFifoLockedMode     =((uint8_t)0x08),  /*!<  CAN Receive FIFO Locked  against overrun ENABLED */
00101  CAN_MasterCtrl_TxFifoPriority       =((uint8_t)0x04)   /*!<  CAN Transmit FIFO Priority  driven by the request order (not by the identifier of the MSG) */
00102  }CAN_MasterCtrl_TypeDef;
00103
00104 /**
00105   * @brief   CAN  mode options */
00106 typedef enum
00107 {
00108   CAN_Mode_Normal             =((uint8_t)0x00),  /*!< normal mode */
00109   CAN_Mode_LoopBack           =((uint8_t)0x01),  /*!< loopback mode */
00110   CAN_Mode_Silent             =((uint8_t)0x02),  /*!< silent mode */
00111   CAN_Mode_Silent_LoopBack    =((uint8_t)0x03)  /*!< loopback combined with silent mode */
00112 }CAN_Mode_TypeDef;
00113
00114 /**
00115   * @brief  CAN synchronisation jump width (SJW)*/
00116 typedef enum
00117 {
00118   CAN_SynJumpWidth_1TimeQuantum                 =((uint8_t)0x00),  /*!< 1 time quantum */
00119   CAN_SynJumpWidth_2TimeQuantum                 =((uint8_t)0x40),  /*!< 2 time quantum */
00120   CAN_SynJumpWidth_3TimeQuantum                 =((uint8_t)0x80),  /*!< 3 time quantum */
00121   CAN_SynJumpWidth_4TimeQuantum                 =((uint8_t)0xC0)  /*!< 4 time quantum */
00122 }CAN_SynJumpWidth_TypeDef;
00123
00124 /**
00125   * @brief   time quantum in bit segment 1 */
00126 typedef enum
00127 {
00128   CAN_BitSeg1_1TimeQuantum                 =((uint8_t)0x00),  /*!< 1 time quantum */
00129   CAN_BitSeg1_2TimeQuantum                 =((uint8_t)0x01),  /*!< 2 time quantum */
00130   CAN_BitSeg1_3TimeQuantum                 =((uint8_t)0x02),  /*!< 3 time quantum */
00131   CAN_BitSeg1_4TimeQuantum                 =((uint8_t)0x03) , /*!< 4 time quantum */
00132   CAN_BitSeg1_5TimeQuantum                 =((uint8_t)0x04) , /*!< 5 time quantum */
00133   CAN_BitSeg1_6TimeQuantum                 =((uint8_t)0x05) , /*!< 6 time quantum */
00134   CAN_BitSeg1_7TimeQuantum                 =((uint8_t)0x06) , /*!< 7 time quantum */
00135   CAN_BitSeg1_8TimeQuantum                 =((uint8_t)0x07),  /*!< 8 time quantum */
00136   CAN_BitSeg1_9TimeQuantum                 =((uint8_t)0x08),  /*!< 9 time quantum */
00137   CAN_BitSeg1_10TimeQuantum                =((uint8_t)0x09),  /*!< 10 time quantum */
00138   CAN_BitSeg1_11TimeQuantum                =((uint8_t)0x0A),  /*!< 11 time quantum */
00139   CAN_BitSeg1_12TimeQuantum                =((uint8_t)0x0B),  /*!< 12 time quantum */
00140   CAN_BitSeg1_13TimeQuantum                =((uint8_t)0x0C),  /*!< 13 time quantum */
00141   CAN_BitSeg1_14TimeQuantum                =((uint8_t)0x0D),  /*!< 14 time quantum */
00142   CAN_BitSeg1_15TimeQuantum                =((uint8_t)0x0E),  /*!< 15 time quantum */
00143   CAN_BitSeg1_16TimeQuantum                =((uint8_t)0x0F)  /*!< 16 time quantum */
00144 }CAN_BitSeg1_TypeDef;
00145
00146 /**
00147   * @brief   time quantum in bit segment 2 */
00148 typedef enum
00149 {
00150   CAN_BitSeg2_1TimeQuantum                = ((uint8_t)0x00),  /*!< 1 time quantum */
00151   CAN_BitSeg2_2TimeQuantum                = ((uint8_t)0x10),  /*!< 2 time quantum */
00152   CAN_BitSeg2_3TimeQuantum                = ((uint8_t)0x20),  /*!< 3 time quantum */
00153   CAN_BitSeg2_4TimeQuantum                = ((uint8_t)0x30),  /*!< 4 time quantum */
00154   CAN_BitSeg2_5TimeQuantum                = ((uint8_t)0x40),  /*!< 5 time quantum */
00155   CAN_BitSeg2_6TimeQuantum                = ((uint8_t)0x50),  /*!< 6 time quantum */
00156   CAN_BitSeg2_7TimeQuantum                = ((uint8_t)0x60),  /*!< 7 time quantum */
00157   CAN_BitSeg2_8TimeQuantum                = ((uint8_t)0x70)   /*!< 8 time quantum */
00158 }CAN_BitSeg2_TypeDef;
00159
00160
00161 /**
00162   * @brief   CAN filter number */
00163 typedef enum
00164 {
00165   CAN_FilterNumber_0                = ((uint8_t)0x00),  /*!< Filter number 0 */
00166   CAN_FilterNumber_1                = ((uint8_t)0x01),  /*!< Filter number 1 */
00167   CAN_FilterNumber_2                = ((uint8_t)0x02),  /*!< Filter number 2 */
00168   CAN_FilterNumber_3                = ((uint8_t)0x03),  /*!< Filter number 3 */
00169   CAN_FilterNumber_4                = ((uint8_t)0x04),  /*!< Filter number 4 */
00170   CAN_FilterNumber_5                = ((uint8_t)0x05)   /*!< Filter number 5 */
00171 }CAN_FilterNumber_TypeDef;
00172
00173 /**
00174   * @brief   CAN filter mode */
00175 typedef enum
00176 {
00177   CAN_FilterMode_IdMask                  =  ((uint8_t)0x00),    /*!< id/mask mode */
00178   CAN_FilterMode_IdMask_IdList           =  ((uint8_t)0x10),    /*!< Id/Mask mode First and IdList mode second */
00179   CAN_FilterMode_IdList_IdMask           =  ((uint8_t)0x11),    /*!< IdList mode First and IdMask mode second */
00180   CAN_FilterMode_IdList                  =  ((uint8_t)0x01)     /*!< identifier list mode */
00181 }CAN_FilterMode_TypeDef;
00182
00183 /**
00184   * @brief   CAN filter scale */
00185 typedef enum
00186 {
00187   CAN_FilterScale_8Bit       =((uint8_t)0x00), /*!< 8-bit filter scale */
00188   CAN_FilterScale_16_8Bit    =((uint8_t)0x02), /*!< 16/8-bit filter scale */
00189   CAN_FilterScale_16Bit      =((uint8_t)0x04), /*!< 16-bit filter scale */
00190   CAN_FilterScale_32Bit      =((uint8_t)0x06)  /*!< 32-bit filter scale */
00191 }CAN_FilterScale_TypeDef;
00192
00193
00194 /**
00195   * @brief   CAN Tx mailboxes*/
00196 typedef enum
00197 {
00198  CAN_TransmitMailBox_0       = ((uint8_t) 0x00),  /*!< CAN TX mailbox 0 reg page */
00199  CAN_TransmitMailBox_1       = ((uint8_t) 0x01),  /*!< CAN TX mailbox 1 reg page */
00200  CAN_TransmitMailBox_2       = ((uint8_t) 0x05)   /*!< CAN TX mailbox 2 reg page */
00201 }CAN_TransmitMailBox_TypeDef;
00202
00203 /**
00204   * @brief   CAN Pending Messages number*/
00205 typedef enum
00206 {
00207   CAN_NbrPendingMessage_0     =  ((uint8_t)0x00),  /*!< No Msg Pending */
00208   CAN_NbrPendingMessage_1     =  ((uint8_t)0x01),  /*!< 1 Msg Pending */
00209   CAN_NbrPendingMessage_2     =  ((uint8_t)0x02),  /*!< 2 Msg Pending */
00210   CAN_NbrPendingMessage_3     =  ((uint8_t)0x03)  /*!< 3 Msg Pending */
00211 }CAN_NbrPendingMessage_TypeDef;
00212
00213 /**
00214   * @brief   CAN identifier type */
00215 typedef enum
00216 {
00217   CAN_Id_Standard                 =((uint8_t)0x00),  /*!< Standard Id */
00218   CAN_Id_Extended                 =((uint8_t)0x40)  /*!< Extended Id */
00219 }CAN_Id_TypeDef;
00220
00221 /**
00222   * @brief   CAN remote transmission request */
00223 typedef enum
00224 {
00225   CAN_RTR_Data               = ((uint8_t)0x00),  /*!< Data frame */
00226   CAN_RTR_Remote             = ((uint8_t)0x20)  /*!< Remote frame */
00227 }CAN_RTR_TypeDef;
00228
00229 /**
00230   * @brief   CAN transmit Status */
00231 typedef enum
00232 {
00233   CAN_TxStatus_Failed                 =((uint8_t)0xF0), /*!< CAN transmission failed */
00234   CAN_TxStatus_Ok                     =((uint8_t)0xF1), /*!< CAN transmission succeeded */
00235   CAN_TxStatus_Pending                =((uint8_t)0xF2), /*!< CAN transmission pending */
00236   CAN_TxStatus_NoMailBox              =((uint8_t)0xF4), /*!< CAN cell did not provide an empty mailbox */
00237   CAN_TxStatus_MailBoxEmpty           =((uint8_t)0xF5), /*!< CAN Tx mailbox is Empty */
00238   CAN_TxStatus_MailBox0Ok             =((uint8_t)0x00), /*!< CAN transmission succeeded by mail box 1*/
00239   CAN_TxStatus_MailBox1Ok             =((uint8_t)0x01), /*!< CAN transmission succeeded by mail box 2*/
00240   CAN_TxStatus_MailBox2Ok             =((uint8_t)0x05) /*!< CAN transmission succeeded by mail box 3*/
00241 }CAN_TxStatus_TypeDef;
00242
00243 /**
00244   * @brief   CAN sleep Status */
00245 typedef enum
00246 {
00247   CAN_Sleep_Failed             = ((uint8_t)0x00), /*!< CAN did not enter the sleep mode */
00248   CAN_Sleep_Ok                 = ((uint8_t)0x01) /*!< CAN entered the sleep mode */
00249 }CAN_Sleep_TypeDef;
00250 /**
00251   * @brief   CAN wake up status */
00252 typedef enum
00253 {
00254  CAN_WakeUp_Failed          =   ((uint8_t)0x00), /*!< CAN did not leave the sleep mode */
00255  CAN_WakeUp_Ok              =   ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
00256 }CAN_WakeUp_TypeDef;
00257
00258 /**
00259   * @brief   CAN flags */
00260 typedef enum
00261 {
00262   /* if the flag is 0x3XXX, it means that it can be got (CAN_GetFlagStatus) and Cleared (CAN_ClearFlag) */
00263   /* if the flag is 0x1XXX, it means that it can only be got (CAN_GetFlagStatus)  */
00264   /*Transmit Flags*/
00265   CAN_FLAG_RQCP0            =((uint16_t)0x3401), /*!< Request MailBox0  Flag */
00266   CAN_FLAG_RQCP1            =((uint16_t)0x3402), /*!< Request MailBox1  Flag */
00267   CAN_FLAG_RQCP2            =((uint16_t)0x3404), /*!< Request MailBox2  Flag */
00268   /*Receive Flags*/
00269   CAN_FLAG_FMP              =((uint16_t)0x1203), /*!< FIFO Message Pending Flag */
00270   CAN_FLAG_FF               =((uint16_t)0x3208), /*!< FIFO Full  Flag */
00271   CAN_FLAG_FOV              =((uint16_t)0x3210), /*!< FIFO Overrun  Flag */
00272   /*Wake up Flag*/
00273   CAN_FLAG_WKU              =((uint16_t)0x3108), /*!< wake up   Flag */
00274   /*Error Flags*/
00275   CAN_FLAG_EWG              =((uint16_t)0x1001), /*!< Error Warning Flag */
00276   CAN_FLAG_EPV              =((uint16_t)0x1002), /*!< Error Passive Flag */
00277   CAN_FLAG_BOF              =((uint16_t)0x1004), /*!< Bus-Off Flag */
00278   CAN_FLAG_LEC              =((uint16_t)0x3070) /*!< Last error code Flag */
00279 }CAN_FLAG_TypeDef;
00280
00281 /**
00282   * @brief   CAN interrupts */
00283 typedef enum
00284 {
00285   /*Transmit Interruption*/
00286   CAN_IT_TME                  =((uint16_t)0x0001), /*!< Transmit mailbox empty interrupt */
00287   /*Receive Interruptions*/
00288   CAN_IT_FMP                  =((uint16_t)0x0002), /*!< FIFO  message pending interrupt   */
00289   CAN_IT_FF                   =((uint16_t)0x0004), /*!< FIFO  full    interrupt                    */
00290   CAN_IT_FOV                  =((uint16_t)0x0008), /*!< FIFO  overrun  interrupt               */
00291   /*Wake Up Interruption*/
00292   CAN_IT_WKU                  =((uint16_t)0x0080), /*!< Wake-up interrupt                         */
00293   /*Error Interruptions*/
00294   CAN_IT_ERR                  =((uint16_t)0x4000), /*!< Genaral Error interrupt                 */
00295   CAN_IT_EWG                  =((uint16_t)0x0100), /*!< Error warning interrupt                */
00296   CAN_IT_EPV                  =((uint16_t)0x0200), /*!< Error passive  interrupt                */
00297   CAN_IT_BOF                  =((uint16_t)0x0400), /*!< Bus-off   interrupt                        */
00298   CAN_IT_LEC                  =((uint16_t)0x0800)  /*!< Last error code interrupt              */
00299 } CAN_IT_TypeDef;
00300
00301 /**
00302   * @brief   CAN ST7 Compatibility*/
00303 typedef enum
00304 {
00305   CAN_ST7Compatibility_Enable     =  ((uint8_t)0x00), /*!< CAN is compatible with ST7 beCAN (only 2 mailboxes are available)*/
00306   CAN_ST7Compatibility_Disable    =  ((uint8_t)0x10)  /*!< CAN is not compatible with ST7 beCAN ( 3 mailboxes are available)*/
00307 }CAN_ST7Compatibility_TypeDef;
00308
00309 /**
00310   * @brief   CAN Error Code description */
00311 typedef enum
00312 {
00313   CAN_ErrorCode_NoErr                 = ((uint8_t)0x00),  /*!< No Error  */
00314   CAN_ErrorCode_StuffErr              = ((uint8_t)0x10),  /*!< Stuff Error  */
00315   CAN_ErrorCode_FormErr               = ((uint8_t)0x20),  /*!< Form Error  */
00316   CAN_ErrorCode_ACKErr                = ((uint8_t)0x30),  /*!< Acknowledgment Error  */
00317   CAN_ErrorCode_BitRecessiveErr       = ((uint8_t)0x40),  /*!< Bit Recessive Error  */
00318   CAN_ErrorCode_BitDominantErr        = ((uint8_t)0x50),  /*!< Bit Dominant Error  */
00319   CAN_ErrorCode_CRCErr                = ((uint8_t)0x60),  /*!< CRC Error  */
00320   CAN_ErrorCode_SoftwareSetErr        = ((uint8_t)0x70)  /*!< Software Set Error  */
00321 }CAN_ErrorCode_TypeDef;
00322 /**
00323   * @}
00324   */
00325 /* Private macros ------------------------------------------------------------*/
00326 /** @addtogroup CAN_Private_Macros
00327   * @{
00328   */
00329 /**
00330   * @brief  Macro used by the assert function in order to check the CAN ST7 Compatibility parameters.
00331   */
00332 #define IS_CAN_ST7_COMPATIBILITY_OK(STATE) (((STATE) == CAN_ST7Compatibility_Enable) || ((STATE) == CAN_ST7Compatibility_Disable))
00333 /**
00334   * @brief  Macro used by the assert function in order to check  CAN operating mode.
00335   */
00336 #define IS_CAN_OPERATINGMODE_OK(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
00337                                     ((MODE) == CAN_OperatingMode_Normal)|| \
00338                         ((MODE) == CAN_OperatingMode_Sleep))
00339 /**
00340   * @brief  Macro used by the assert function in order to check CAN Time Triggered Communication mode.
00341   */
00342 #define IS_CAN_MASTERCTRL_OK(MODE) (((MODE) == CAN_MasterCtrl_AllDisabled) || \
00343                                     (((MODE) <= CAN_MasterCtrl_AllEnabled) && ((MODE) >= CAN_MasterCtrl_TxFifoPriority)))
00344 /**
00345   * @brief  Macro used by the assert function in order to check   CAN  mode options .
00346   */
00347 #define IS_CAN_MODE_OK(MODE) (((MODE) == CAN_Mode_Normal) || ((MODE) == CAN_Mode_LoopBack)|| \
00348                            ((MODE) == CAN_Mode_Silent) || ((MODE) == CAN_Mode_Silent_LoopBack))
00349 /**
00350   * @brief  Macro used by the assert function in order to check the CAN synchronisation jump width (SJW).
00351   */
00352 #define IS_CAN_SYNJUMPWIDTH_OK(SJW) (((SJW) == CAN_SynJumpWidth_1TimeQuantum) || ((SJW) == CAN_SynJumpWidth_2TimeQuantum)|| \
00353                          ((SJW) == CAN_SynJumpWidth_3TimeQuantum) || ((SJW) == CAN_SynJumpWidth_4TimeQuantum))
00354 /**
00355   * @brief  Macro used by the assert function in order to check time quantum in bit segment 1 .
00356   */
00357 #define IS_CAN_BITSEG1_OK(BS1) ((BS1) <= CAN_BitSeg1_16TimeQuantum)
00358 /**
00359   * @brief  Macro used by the assert function in order to check time quantum in bit segment 2.
00360   */
00361 #define IS_CAN_BITSEG2_OK(BS2) ((((BS2) >= CAN_BitSeg2_2TimeQuantum) && ((BS2) <= CAN_BitSeg2_8TimeQuantum))|| ((BS2) == CAN_BitSeg2_1TimeQuantum))
00362 /**
00363   * @brief  Macro used by the assert function in order to check CAN clock prescaler.
00364   */
00365 #define IS_CAN_PRESCALER_OK(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 64))
00366 /**
00367   * @brief  Macro used by the assert function in order to check CAN filter number.
00368   */
00369 #define IS_CAN_FILTER_NUMBER_OK(NUMBER) (((NUMBER) == CAN_FilterNumber_0) || \
00370                                        ((NUMBER) == CAN_FilterNumber_1) || \
00371                                        ((NUMBER) == CAN_FilterNumber_2) || \
00372                                        ((NUMBER) == CAN_FilterNumber_3) || \
00373                                        ((NUMBER) == CAN_FilterNumber_4) || \
00374                                        ((NUMBER) == CAN_FilterNumber_5))
00375 /**
00376   * @brief  Macro used by the assert function in order to check  CAN filter mode.
00377   */
00378 #define IS_CAN_FILTER_MODE_OK(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
00379                                      ((MODE) == CAN_FilterMode_IdMask_IdList) || \
00380                                      ((MODE) == CAN_FilterMode_IdList_IdMask) || \
00381                                   ((MODE) == CAN_FilterMode_IdList))
00382 /**
00383   * @brief  Macro used by the assert function in order to check CAN filter scale.
00384   */
00385 #define IS_CAN_FILTER_SCALE_OK(SCALE) (((SCALE) == CAN_FilterScale_8Bit)|| \
00386                                     ((SCALE) == CAN_FilterScale_16_8Bit) ||\
00387                                     ((SCALE) == CAN_FilterScale_16Bit  )||\
00388                                     ((SCALE) == CAN_FilterScale_32Bit))
00389 /**
00390   * @brief  Macro used by the assert function in order to check CAN Tx mailboxes.
00391   */
00392 #define IS_CAN_TRANSMITMAILBOX_OK(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TransmitMailBox_0) || \
00393                                                  ((TRANSMITMAILBOX) == CAN_TransmitMailBox_1) || \
00394                                                  ((TRANSMITMAILBOX) == CAN_TransmitMailBox_2))
00395 /**
00396   * @brief  Macro used by the assert function in order to check the Standard ID to be sent.
00397   */
00398 #define IS_CAN_STDID_OK(STDID)   ((STDID) <= ((uint16_t)CAN_STDID_SIZE))
00399 /**
00400   * @brief  Macro used by the assert function in order to check the Extended ID to be sent.
00401   */
00402 #define IS_CAN_EXTID_OK(EXTID)   ((EXTID) <= ((uint32_t)CAN_EXTID_SIZE))
00403 /**
00404   * @brief  Macro used by the assert function in order to check the DLC to be sent.
00405   */
00406 #define IS_CAN_DLC_OK(DLC)       ((DLC) <= CAN_DLC_MAX)
00407 /**
00408   * @brief  Macro used by the assert function in order to check the type of the ID to be sent.
00409   */
00410 #define IS_CAN_IDTYPE_OK(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || ((IDTYPE) == CAN_Id_Extended))
00411 /**
00412   * @brief  Macro used by the assert function in order to check CAN  transmission  Frame Type.
00413   */
00414 #define IS_CAN_RTR_OK(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
00415
00416 /**
00417   * @brief  Macro used by the assert function in order to check  CAN flags which can be got by @ref CAN_GetFlagStatus
00418   */
00419 #define IS_CAN_FLAG_STATUS_OK(FLAG) (((FLAG) == CAN_FLAG_RQCP0) || ((FLAG) == CAN_FLAG_RQCP1) ||\
00420                                   ((FLAG) == CAN_FLAG_RQCP2) || ((FLAG) == CAN_FLAG_FMP) ||\
00421                                   ((FLAG) == CAN_FLAG_FF) || ((FLAG) == CAN_FLAG_FOV) ||\
00422                                   ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_EWG) ||\
00423                                   ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_BOF) ||\
00424                                   ((FLAG) == CAN_FLAG_LEC))
00425 /**
00426   * @brief  Macro used by the assert function in order to check  CAN flags which can be cleared by @ref CAN_ClearFlag
00427   */
00428 #define IS_CAN_FLAG_CLEAR_OK(FLAG) (((FLAG) == CAN_FLAG_RQCP0) || ((FLAG) == CAN_FLAG_RQCP1) ||\
00429                                     ((FLAG) == CAN_FLAG_RQCP2) ||  ((FLAG) == CAN_FLAG_FF)   ||\
00430                                     ((FLAG) == CAN_FLAG_FOV)  ||  ((FLAG) == CAN_FLAG_WKU) ||\
00431                                     ((FLAG) == CAN_FLAG_LEC))
00432 /**
00433   * @brief  Macro used by the assert function in order to check the  CAN Configuration interrupts.
00434   */
00435 #define CAN_IT_CONFIG_MASK  ~(uint16_t)(CAN_IT_TME|CAN_IT_FMP|CAN_IT_FF|CAN_IT_FOV|CAN_IT_WKU|CAN_IT_EWG|CAN_IT_EPV|CAN_IT_BOF|CAN_IT_LEC|CAN_IT_ERR)
00436 #define IS_CAN_IT_CONFIG_OK(IT) (((IT) != 0x0000) && ((uint16_t)((uint16_t)(IT) & (uint16_t)CAN_IT_CONFIG_MASK) == 0x0000))
00437 /**
00438   * @brief  Macro used by the assert function in order to check the  CAN status interrupts.
00439   */
00440 #define IS_CAN_IT_STATUS_OK(IT) (((IT) == CAN_IT_TME)   || ((IT) == CAN_IT_FMP) ||\
00441                              ((IT) == CAN_IT_FF)    || ((IT) == CAN_IT_FOV) || \
00442                              ((IT) == CAN_IT_WKU)   || ((IT) == CAN_IT_ERR)  || \
00443                              ((IT) == CAN_IT_EWG)   || ((IT) == CAN_IT_EPV)  || \
00444                              ((IT) == CAN_IT_BOF)   || ((IT) == CAN_IT_LEC)  )
00445 /**
00446   * @brief  Macro used by the assert function in order to check the  CAN Pending bit interrupts.
00447   */
00448 #define IS_CAN_IT_PENDING_BIT_OK(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF)  ||\
00449                                       ((IT) == CAN_IT_FOV)  || ((IT) == CAN_IT_WKU) ||\
00450                                       ((IT) == CAN_IT_ERR)  || ((IT) == CAN_IT_EWG) ||\
00451                                       ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF)||\
00452                                       ((IT) == CAN_IT_LEC))
00453 /**
00454   * @brief  Macro used by the assert function in order to check the Last Error Code.
00455   */
00456 #define IS_CAN_LAST_ERROR_CODE_OK(CODE)  (((CODE) & 0x8F) == 0x00)
00457 /**
00458   * @}
00459   */
00460
00461 /* Exported function prototypes --------------------------------------------- */
00462 /** @addtogroup CAN_Exported_Functions
00463   * @{
00464   */
00465 void CAN_DeInit(void);
00466 CAN_InitStatus_TypeDef CAN_Init(CAN_MasterCtrl_TypeDef CAN_MasterCtrl,
00467                                 CAN_Mode_TypeDef CAN_Mode,
00468                                 CAN_SynJumpWidth_TypeDef CAN_SynJumpWidth,
00469                                 CAN_BitSeg1_TypeDef CAN_BitSeg1,
00470                                 CAN_BitSeg2_TypeDef CAN_BitSeg2,
00471                                 uint8_t CAN_Prescaler);
00472
00473 void CAN_FilterInit(CAN_FilterNumber_TypeDef CAN_FilterNumber,
00474                     FunctionalState CAN_FilterActivation,
00475                     CAN_FilterMode_TypeDef CAN_FilterMode,
00476                     CAN_FilterScale_TypeDef CAN_FilterScale,
00477                     uint8_t CAN_FilterID1,
00478                     uint8_t CAN_FilterID2,
00479                     uint8_t CAN_FilterID3,
00480                      uint8_t CAN_FilterID4,
00481                     uint8_t CAN_FilterIDMask1,
00482                      uint8_t CAN_FilterIDMask2,
00483                     uint8_t CAN_FilterIDMask3,
00484                     uint8_t CAN_FilterIDMask4);
00485 void CAN_ITConfig(CAN_IT_TypeDef CAN_IT, FunctionalState NewState);
00486 void CAN_ST7CompatibilityCmd(CAN_ST7Compatibility_TypeDef CAN_ST7Compatibility);
00487 CAN_TxStatus_TypeDef CAN_Transmit( uint32_t CAN_Id,
00488                                    CAN_Id_TypeDef CAN_IDE,
00489                                    CAN_RTR_TypeDef CAN_RTR,
00490                                    uint8_t CAN_DLC,
00491                                    uint8_t *CAN_Data);
00492 void CAN_TTComModeCmd(FunctionalState NewState);
00493 CAN_TxStatus_TypeDef CAN_TransmitStatus(CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox);
00494 void CAN_CancelTransmit(CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox);
00495 void CAN_FIFORelease(void);
00496 CAN_NbrPendingMessage_TypeDef CAN_MessagePending(void);
00497 void CAN_Receive(void);
00498 uint32_t CAN_GetReceivedId(void);
00499 CAN_Id_TypeDef CAN_GetReceivedIDE(void);
00500 CAN_RTR_TypeDef CAN_GetReceivedRTR(void);
00501 uint8_t CAN_GetReceivedDLC(void);
00502 uint8_t CAN_GetReceivedData(uint8_t CAN_DataIndex);
00503 uint8_t CAN_GetReceivedFMI(void);
00504 uint16_t CAN_GetMessageTimeStamp(void);
00505 CAN_Sleep_TypeDef CAN_Sleep(void);
00506 CAN_WakeUp_TypeDef CAN_WakeUp(void);
00507 CAN_ModeStatus_TypeDef CAN_OperatingModeRequest(CAN_OperatingMode_TypeDef CAN_OperatingMode);
00508 CAN_ErrorCode_TypeDef CAN_GetLastErrorCode(void);
00509 CAN_Page_TypeDef CAN_GetSelectedPage(void);
00510 void CAN_SelectPage(CAN_Page_TypeDef CAN_Page);
00511 FlagStatus CAN_GetFlagStatus(CAN_FLAG_TypeDef CAN_Flag);
00512 void CAN_ClearFlag(CAN_FLAG_TypeDef CAN_Flag);
00513 ITStatus CAN_GetITStatus(CAN_IT_TypeDef CAN_IT);
00514 void CAN_ClearITPendingBit(CAN_IT_TypeDef CAN_IT);
00515 /**
00516   * @}
00517   */
00518 #endif /* __STM8S_CAN_H */
00519
00520
00521 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_clk.c Source File

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stm8s_clk.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_clk.c
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all the functions for the CLK peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Includes ------------------------------------------------------------------*/
00029
00030 #include "stm8s_clk.h"
00031
00032 /** @addtogroup STM8S_StdPeriph_Driver
00033   * @{
00034   */
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040
00041 /* Private Constants ---------------------------------------------------------*/
00042
00043 /**
00044   * @addtogroup CLK_Private_Constants
00045   * @{
00046   */
00047
00048 CONST uint8_t HSIDivFactor[4] = {1, 2, 4, 8}; /*!< Holds the different HSI Divider factors */
00049 CONST uint8_t CLKPrescTable[8] = {1, 2, 4, 8, 10, 16, 20, 40}; /*!< Holds the different CLK prescaler values */
00050
00051 /**
00052   * @}
00053   */
00054
00055 /* Public functions ----------------------------------------------------------*/
00056 /**
00057   * @addtogroup CLK_Public_Functions
00058   * @{
00059   */
00060
00061 /**
00062   * @brief  Deinitializes the CLK peripheral registers to their default reset
00063   * values.
00064   * @param  None
00065   * @retval None
00066   * @par Warning:
00067   * Resetting the CCOR register: \n
00068   * When the CCOEN bit is set, the reset of the CCOR register require
00069   * two consecutive write instructions in order to reset first the CCOEN bit
00070   * and the second one is to reset the CCOSEL bits.
00071   */
00072 void CLK_DeInit(void)
00073 {
00074   CLK->ICKR = CLK_ICKR_RESET_VALUE;
00075   CLK->ECKR = CLK_ECKR_RESET_VALUE;
00076   CLK->SWR  = CLK_SWR_RESET_VALUE;
00077   CLK->SWCR = CLK_SWCR_RESET_VALUE;
00078   CLK->CKDIVR = CLK_CKDIVR_RESET_VALUE;
00079   CLK->PCKENR1 = CLK_PCKENR1_RESET_VALUE;
00080   CLK->PCKENR2 = CLK_PCKENR2_RESET_VALUE;
00081   CLK->CSSR = CLK_CSSR_RESET_VALUE;
00082   CLK->CCOR = CLK_CCOR_RESET_VALUE;
00083   while ((CLK->CCOR & CLK_CCOR_CCOEN)!= 0)
00084   {}
00085   CLK->CCOR = CLK_CCOR_RESET_VALUE;
00086   CLK->HSITRIMR = CLK_HSITRIMR_RESET_VALUE;
00087   CLK->SWIMCCR = CLK_SWIMCCR_RESET_VALUE;
00088 }
00089
00090 /**
00091   * @brief   Configures the High Speed Internal oscillator (HSI).
00092   * @par Full description:
00093   * If CLK_FastHaltWakeup is enabled, HSI oscillator is automatically
00094   * switched-on (HSIEN=1) and selected as next clock master
00095   * (CKM=SWI=HSI) when resuming from HALT/ActiveHalt modes.\n
00096   * @param   NewState this parameter is the Wake-up Mode state.
00097   * @retval None
00098   */
00099 void CLK_FastHaltWakeUpCmd(FunctionalState NewState)
00100 {
00101   /* check the parameters */
00102   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00103
00104   if (NewState != DISABLE)
00105   {
00106     /* Set FHWU bit (HSI oscillator is automatically switched-on) */
00107     CLK->ICKR |= CLK_ICKR_FHWU;
00108   }
00109   else  /* FastHaltWakeup = DISABLE */
00110   {
00111     /* Reset FHWU bit */
00112     CLK->ICKR &= (uint8_t)(~CLK_ICKR_FHWU);
00113   }
00114 }
00115
00116 /**
00117   * @brief  Enable or Disable the External High Speed oscillator (HSE).
00118   * @param   NewState new state of HSEEN, value accepted ENABLE, DISABLE.
00119   * @retval None
00120   */
00121 void CLK_HSECmd(FunctionalState NewState)
00122 {
00123   /* Check the parameters */
00124   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00125
00126   if (NewState != DISABLE)
00127   {
00128     /* Set HSEEN bit */
00129     CLK->ECKR |= CLK_ECKR_HSEEN;
00130   }
00131   else
00132   {
00133     /* Reset HSEEN bit */
00134     CLK->ECKR &= (uint8_t)(~CLK_ECKR_HSEEN);
00135   }
00136 }
00137
00138 /**
00139   * @brief  Enables or disables the Internal High Speed oscillator (HSI).
00140   * @param   NewState new state of HSIEN, value accepted ENABLE, DISABLE.
00141   * @retval None
00142   */
00143 void CLK_HSICmd(FunctionalState NewState)
00144 {
00145   /* Check the parameters */
00146   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00147
00148   if (NewState != DISABLE)
00149   {
00150     /* Set HSIEN bit */
00151     CLK->ICKR |= CLK_ICKR_HSIEN;
00152   }
00153   else
00154   {
00155     /* Reset HSIEN bit */
00156     CLK->ICKR &= (uint8_t)(~CLK_ICKR_HSIEN);
00157   }
00158 }
00159
00160 /**
00161   * @brief  Enables or disables the Internal Low Speed oscillator (LSI).
00162   * @param  NewState new state of LSIEN, value accepted ENABLE, DISABLE.
00163   * @note   Before using the LSI clock you have to enable the option bytes (LSI_EN option bit is set).
00164   * @retval None
00165   */
00166 void CLK_LSICmd(FunctionalState NewState)
00167 {
00168   /* Check the parameters */
00169   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00170
00171   if (NewState != DISABLE)
00172   {
00173     /* Set LSIEN bit */
00174     CLK->ICKR |= CLK_ICKR_LSIEN;
00175   }
00176   else
00177   {
00178     /* Reset LSIEN bit */
00179     CLK->ICKR &= (uint8_t)(~CLK_ICKR_LSIEN);
00180   }
00181 }
00182
00183 /**
00184   * @brief  Enables or disablle the Configurable Clock Output (CCO).
00185   * @param   NewState : New state of CCEN bit (CCO register).
00186   * This parameter can be any of the @ref FunctionalState enumeration.
00187   * @retval None
00188   */
00189 void CLK_CCOCmd(FunctionalState NewState)
00190 {
00191   /* Check the parameters */
00192   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00193
00194   if (NewState != DISABLE)
00195   {
00196     /* Set CCOEN bit */
00197     CLK->CCOR |= CLK_CCOR_CCOEN;
00198   }
00199   else
00200   {
00201     /* Reset CCOEN bit */
00202     CLK->CCOR &= (uint8_t)(~CLK_CCOR_CCOEN);
00203   }
00204 }
00205
00206 /**
00207   * @brief  Starts or Stops manually the clock switch execution.
00208   * @par Full description:
00209   * NewState parameter set the SWEN.
00210   * @param   NewState new state of SWEN, value accepted ENABLE, DISABLE.
00211   * @retval None
00212   */
00213 void CLK_ClockSwitchCmd(FunctionalState NewState)
00214 {
00215   /* Check the parameters */
00216   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00217
00218   if (NewState != DISABLE )
00219   {
00220     /* Enable the Clock Switch */
00221     CLK->SWCR |= CLK_SWCR_SWEN;
00222   }
00223   else
00224   {
00225     /* Disable the Clock Switch */
00226     CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWEN);
00227   }
00228 }
00229
00230 /**
00231   * @brief  Configures the slow active halt wake up
00232   * @param   NewState: specifies the Slow Active Halt wake up state.
00233   * can be set of the following values:
00234   * - DISABLE: Slow Active Halt mode disabled;
00235   * - ENABLE:  Slow Active Halt mode enabled.
00236   * @retval None
00237   */
00238 void CLK_SlowActiveHaltWakeUpCmd(FunctionalState NewState)
00239 {
00240   /* check the parameters */
00241   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00242
00243   if (NewState != DISABLE)
00244   {
00245     /* Set S_ACTHALT bit */
00246     CLK->ICKR |= CLK_ICKR_SWUAH;
00247   }
00248   else
00249   {
00250     /* Reset S_ACTHALT bit */
00251     CLK->ICKR &= (uint8_t)(~CLK_ICKR_SWUAH);
00252   }
00253 }
00254
00255 /**
00256   * @brief   Enables or disables the specified peripheral CLK.
00257   * @param   CLK_Peripheral : This parameter specifies the peripheral clock to gate.
00258   * This parameter can be any of the  @ref CLK_Peripheral_TypeDef enumeration.
00259   * @param   NewState : New state of specified peripheral clock.
00260   * This parameter can be any of the @ref FunctionalState enumeration.
00261   * @retval None
00262   */
00263 void CLK_PeripheralClockConfig(CLK_Peripheral_TypeDef CLK_Peripheral, FunctionalState NewState)
00264 {
00265   /* Check the parameters */
00266   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00267   assert_param(IS_CLK_PERIPHERAL_OK(CLK_Peripheral));
00268
00269   if (((uint8_t)CLK_Peripheral & (uint8_t)0x10) == 0x00)
00270   {
00271     if (NewState != DISABLE)
00272     {
00273       /* Enable the peripheral Clock */
00274       CLK->PCKENR1 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));
00275     }
00276     else
00277     {
00278       /* Disable the peripheral Clock */
00279       CLK->PCKENR1 &= (uint8_t)(~(uint8_t)(((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F))));
00280     }
00281   }
00282   else
00283   {
00284     if (NewState != DISABLE)
00285     {
00286       /* Enable the peripheral Clock */
00287       CLK->PCKENR2 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));
00288     }
00289     else
00290     {
00291       /* Disable the peripheral Clock */
00292       CLK->PCKENR2 &= (uint8_t)(~(uint8_t)(((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F))));
00293     }
00294   }
00295 }
00296
00297 /**
00298   * @brief  configures the Switch from one clock to another
00299   * @param   CLK_SwitchMode select the clock switch mode.
00300   * It can be set of the values of @ref CLK_SwitchMode_TypeDef
00301   * @param   CLK_NewClock choice of the future clock.
00302   * It can be set of the values of @ref CLK_Source_TypeDef
00303   * @param   ITState Enable or Disable the Clock Switch interrupt.
00304   * @param   CLK_CurrentClockState current clock to switch OFF or to keep ON.
00305   * It can be set of the values of @ref CLK_CurrentClockState_TypeDef
00306   * @note LSI selected as master clock source only if LSI_EN option bit is set.
00307   * @retval ErrorStatus this shows the clock switch status (ERROR/SUCCESS).
00308   */
00309 ErrorStatus CLK_ClockSwitchConfig(CLK_SwitchMode_TypeDef CLK_SwitchMode, CLK_Source_TypeDef CLK_NewClock, FunctionalState ITState, CLK_CurrentClockState_TypeDef CLK_CurrentClockState)
00310 {
00311   CLK_Source_TypeDef clock_master;
00312   uint16_t DownCounter = CLK_TIMEOUT;
00313   ErrorStatus Swif = ERROR;
00314
00315   /* Check the parameters */
00316   assert_param(IS_CLK_SOURCE_OK(CLK_NewClock));
00317   assert_param(IS_CLK_SWITCHMODE_OK(CLK_SwitchMode));
00318   assert_param(IS_FUNCTIONALSTATE_OK(ITState));
00319   assert_param(IS_CLK_CURRENTCLOCKSTATE_OK(CLK_CurrentClockState));
00320
00321   /* Current clock master saving */
00322   clock_master = (CLK_Source_TypeDef)CLK->CMSR;
00323
00324   /* Automatic switch mode management */
00325   if (CLK_SwitchMode == CLK_SWITCHMODE_AUTO)
00326   {
00327     /* Enables Clock switch */
00328     CLK->SWCR |= CLK_SWCR_SWEN;
00329
00330     /* Enables or Disables Switch interrupt */
00331     if (ITState != DISABLE)
00332     {
00333       CLK->SWCR |= CLK_SWCR_SWIEN;
00334     }
00335     else
00336     {
00337       CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWIEN);
00338     }
00339
00340     /* Selection of the target clock source */
00341     CLK->SWR = (uint8_t)CLK_NewClock;
00342
00343     /* Wait until the target clock source is ready */
00344     while((((CLK->SWCR & CLK_SWCR_SWBSY) != 0 )&& (DownCounter != 0)))
00345     {
00346       DownCounter--;
00347     }
00348
00349     if(DownCounter != 0)
00350     {
00351       Swif = SUCCESS;
00352     }
00353     else
00354     {
00355       Swif = ERROR;
00356     }
00357   }
00358   else /* CLK_SwitchMode == CLK_SWITCHMODE_MANUAL */
00359   {
00360     /* Enables or Disables Switch interrupt  if required  */
00361     if (ITState != DISABLE)
00362     {
00363       CLK->SWCR |= CLK_SWCR_SWIEN;
00364     }
00365     else
00366     {
00367       CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWIEN);
00368     }
00369
00370     /* Selection of the target clock source */
00371     CLK->SWR = (uint8_t)CLK_NewClock;
00372
00373     /* Wait until the target clock source is ready */
00374     while((((CLK->SWCR & CLK_SWCR_SWIF) != 0 ) && (DownCounter != 0)))
00375     {
00376       DownCounter--;
00377     }
00378
00379     if(DownCounter != 0)
00380     {
00381       /* Enables Clock switch */
00382       CLK->SWCR |= CLK_SWCR_SWEN;
00383       Swif = SUCCESS;
00384     }
00385     else
00386     {
00387       Swif = ERROR;
00388     }
00389   }
00390   if(Swif != ERROR)
00391   {
00392     /* Switch OFF current clock if required */
00393     if((CLK_CurrentClockState == CLK_CURRENTCLOCKSTATE_DISABLE) && ( clock_master == CLK_SOURCE_HSI))
00394     {
00395       CLK->ICKR &= (uint8_t)(~CLK_ICKR_HSIEN);
00396     }
00397     else if((CLK_CurrentClockState == CLK_CURRENTCLOCKSTATE_DISABLE) && ( clock_master == CLK_SOURCE_LSI))
00398     {
00399       CLK->ICKR &= (uint8_t)(~CLK_ICKR_LSIEN);
00400     }
00401     else if ((CLK_CurrentClockState == CLK_CURRENTCLOCKSTATE_DISABLE) && ( clock_master == CLK_SOURCE_HSE))
00402     {
00403       CLK->ECKR &= (uint8_t)(~CLK_ECKR_HSEEN);
00404     }
00405   }
00406   return(Swif);
00407 }
00408
00409 /**
00410   * @brief  Configures the HSI clock dividers.
00411   * @param   HSIPrescaler : Specifies the HSI clock divider to apply.
00412   * This parameter can be any of the @ref CLK_Prescaler_TypeDef enumeration.
00413   * @retval None
00414   */
00415 void CLK_HSIPrescalerConfig(CLK_Prescaler_TypeDef HSIPrescaler)
00416 {
00417   /* check the parameters */
00418   assert_param(IS_CLK_HSIPRESCALER_OK(HSIPrescaler));
00419
00420   /* Clear High speed internal clock prescaler */
00421   CLK->CKDIVR &= (uint8_t)(~CLK_CKDIVR_HSIDIV);
00422
00423   /* Set High speed internal clock prescaler */
00424   CLK->CKDIVR |= (uint8_t)HSIPrescaler;
00425 }
00426
00427 /**
00428   * @brief  Output the selected clock on a dedicated I/O pin.
00429   * @param   CLK_CCO : Specifies the clock source.
00430   * This parameter can be any of the  @ref CLK_Output_TypeDef enumeration.
00431   * @retval None
00432   * @par Required preconditions:
00433   * The dedicated I/O pin must be set at 1 in the corresponding Px_CR1 register \n
00434   * to be set as input with pull-up or push-pull output.
00435   */
00436 void CLK_CCOConfig(CLK_Output_TypeDef CLK_CCO)
00437 {
00438   /* check the parameters */
00439   assert_param(IS_CLK_OUTPUT_OK(CLK_CCO));
00440
00441   /* Clears of the CCO type bits part */
00442   CLK->CCOR &= (uint8_t)(~CLK_CCOR_CCOSEL);
00443
00444   /* Selects the source provided on cco_ck output */
00445   CLK->CCOR |= (uint8_t)CLK_CCO;
00446
00447   /* Enable the clock output */
00448   CLK->CCOR |= CLK_CCOR_CCOEN;
00449 }
00450
00451 /**
00452   * @brief   Enables or disables the specified CLK interrupts.
00453   * @param   CLK_IT This parameter specifies the interrupt sources.
00454   * It can be one of the values of @ref CLK_IT_TypeDef.
00455   * @param   NewState New state of the Interrupt.
00456   * Value accepted ENABLE, DISABLE.
00457   * @retval None
00458   */
00459 void CLK_ITConfig(CLK_IT_TypeDef CLK_IT, FunctionalState NewState)
00460 {
00461   /* check the parameters */
00462   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00463   assert_param(IS_CLK_IT_OK(CLK_IT));
00464
00465   if (NewState != DISABLE)
00466   {
00467     switch (CLK_IT)
00468     {
00469     case CLK_IT_SWIF: /* Enable the clock switch interrupt */
00470       CLK->SWCR |= CLK_SWCR_SWIEN;
00471       break;
00472     case CLK_IT_CSSD: /* Enable the clock security system detection interrupt */
00473       CLK->CSSR |= CLK_CSSR_CSSDIE;
00474       break;
00475     default:
00476       break;
00477     }
00478   }
00479   else  /*(NewState == DISABLE)*/
00480   {
00481     switch (CLK_IT)
00482     {
00483     case CLK_IT_SWIF: /* Disable the clock switch interrupt */
00484       CLK->SWCR  &= (uint8_t)(~CLK_SWCR_SWIEN);
00485       break;
00486     case CLK_IT_CSSD: /* Disable the clock security system detection interrupt */
00487       CLK->CSSR &= (uint8_t)(~CLK_CSSR_CSSDIE);
00488       break;
00489     default:
00490       break;
00491     }
00492   }
00493 }
00494
00495 /**
00496   * @brief  Configures the HSI and CPU clock dividers.
00497   * @param  CLK_Prescaler Specifies the HSI or CPU clock divider to apply.
00498   * @retval None
00499   */
00500 void CLK_SYSCLKConfig(CLK_Prescaler_TypeDef CLK_Prescaler)
00501 {
00502   /* check the parameters */
00503   assert_param(IS_CLK_PRESCALER_OK(CLK_Prescaler));
00504
00505   if (((uint8_t)CLK_Prescaler & (uint8_t)0x80) == 0x00) /* Bit7 = 0 means HSI divider */
00506   {
00507     CLK->CKDIVR &= (uint8_t)(~CLK_CKDIVR_HSIDIV);
00508     CLK->CKDIVR |= (uint8_t)((uint8_t)CLK_Prescaler & (uint8_t)CLK_CKDIVR_HSIDIV);
00509   }
00510   else /* Bit7 = 1 means CPU divider */
00511   {
00512     CLK->CKDIVR &= (uint8_t)(~CLK_CKDIVR_CPUDIV);
00513     CLK->CKDIVR |= (uint8_t)((uint8_t)CLK_Prescaler & (uint8_t)CLK_CKDIVR_CPUDIV);
00514   }
00515 }
00516
00517 /**
00518   * @brief  Configures the SWIM clock frequency on the fly.
00519   * @param   CLK_SWIMDivider Specifies the SWIM clock divider to apply.
00520   * can be one of the value of @ref CLK_SWIMDivider_TypeDef
00521   * @retval None
00522   */
00523 void CLK_SWIMConfig(CLK_SWIMDivider_TypeDef CLK_SWIMDivider)
00524 {
00525   /* check the parameters */
00526   assert_param(IS_CLK_SWIMDIVIDER_OK(CLK_SWIMDivider));
00527
00528   if (CLK_SWIMDivider != CLK_SWIMDIVIDER_2)
00529   {
00530     /* SWIM clock is not divided by 2 */
00531     CLK->SWIMCCR |= CLK_SWIMCCR_SWIMDIV;
00532   }
00533   else /* CLK_SWIMDivider == CLK_SWIMDIVIDER_2 */
00534   {
00535     /* SWIM clock is divided by 2 */
00536     CLK->SWIMCCR &= (uint8_t)(~CLK_SWIMCCR_SWIMDIV);
00537   }
00538 }
00539
00540 /**
00541   * @brief  Enables the Clock Security System.
00542   * @par Full description:
00543   * once CSS is enabled it cannot be disabled until the next reset.
00544   * @param  None
00545   * @retval None
00546   */
00547 void CLK_ClockSecuritySystemEnable(void)
00548 {
00549   /* Set CSSEN bit */
00550   CLK->CSSR |= CLK_CSSR_CSSEN;
00551 }
00552
00553 /**
00554   * @brief  Returns the clock source used as system clock.
00555   * @param  None
00556   * @retval  Clock source used.
00557   * can be one of the values of @ref CLK_Source_TypeDef
00558   */
00559 CLK_Source_TypeDef CLK_GetSYSCLKSource(void)
00560 {
00561   return((CLK_Source_TypeDef)CLK->CMSR);
00562 }
00563
00564 /**
00565   * @brief  This function returns the frequencies of different on chip clocks.
00566   * @param  None
00567   * @retval the master clock frequency
00568   */
00569 uint32_t CLK_GetClockFreq(void)
00570 {
00571   uint32_t clockfrequency = 0;
00572   CLK_Source_TypeDef clocksource = CLK_SOURCE_HSI;
00573   uint8_t tmp = 0, presc = 0;
00574
00575   /* Get CLK source. */
00576   clocksource = (CLK_Source_TypeDef)CLK->CMSR;
00577
00578   if (clocksource == CLK_SOURCE_HSI)
00579   {
00580     tmp = (uint8_t)(CLK->CKDIVR & CLK_CKDIVR_HSIDIV);
00581     tmp = (uint8_t)(tmp >> 3);
00582     presc = HSIDivFactor[tmp];
00583     clockfrequency = HSI_VALUE / presc;
00584   }
00585   else if ( clocksource == CLK_SOURCE_LSI)
00586   {
00587     clockfrequency = LSI_VALUE;
00588   }
00589   else
00590   {
00591     clockfrequency = HSE_VALUE;
00592   }
00593
00594   return((uint32_t)clockfrequency);
00595 }
00596
00597 /**
00598   * @brief  Adjusts the Internal High Speed oscillator (HSI) calibration value.
00599   * @par Full description:
00600   * @param   CLK_HSICalibrationValue calibration trimming value.
00601   * can be one of the values of @ref CLK_HSITrimValue_TypeDef
00602   * @retval None
00603   */
00604 void CLK_AdjustHSICalibrationValue(CLK_HSITrimValue_TypeDef CLK_HSICalibrationValue)
00605 {
00606   /* check the parameters */
00607   assert_param(IS_CLK_HSITRIMVALUE_OK(CLK_HSICalibrationValue));
00608
00609   /* Store the new value */
00610   CLK->HSITRIMR = (uint8_t)( (uint8_t)(CLK->HSITRIMR & (uint8_t)(~CLK_HSITRIMR_HSITRIM))|((uint8_t)CLK_HSICalibrationValue));
00611 }
00612
00613 /**
00614   * @brief  Reset the SWBSY flag (SWICR Register)
00615   * @par Full description:
00616   * This function reset SWBSY flag in order to reset clock switch operations (target
00617   * oscillator is broken, stabilization is longing too much, etc.).  If at the same time \n
00618   * software attempts to set SWEN and clear SWBSY, SWBSY action takes precedence.
00619   * @param  None
00620   * @retval None
00621   */
00622 void CLK_SYSCLKEmergencyClear(void)
00623 {
00624   CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWBSY);
00625 }
00626
00627 /**
00628   * @brief  Checks whether the specified CLK flag is set or not.
00629   * @par Full description:
00630   * @param   CLK_FLAG Flag to check.
00631   * can be one of the values of @ref CLK_Flag_TypeDef
00632   * @retval FlagStatus, status of the checked flag
00633   */
00634 FlagStatus CLK_GetFlagStatus(CLK_Flag_TypeDef CLK_FLAG)
00635 {
00636   uint16_t statusreg = 0;
00637   uint8_t tmpreg = 0;
00638   FlagStatus bitstatus = RESET;
00639
00640   /* check the parameters */
00641   assert_param(IS_CLK_FLAG_OK(CLK_FLAG));
00642
00643   /* Get the CLK register index */
00644   statusreg = (uint16_t)((uint16_t)CLK_FLAG & (uint16_t)0xFF00);
00645
00646
00647   if (statusreg == 0x0100) /* The flag to check is in ICKRregister */
00648   {
00649     tmpreg = CLK->ICKR;
00650   }
00651   else if (statusreg == 0x0200) /* The flag to check is in ECKRregister */
00652   {
00653     tmpreg = CLK->ECKR;
00654   }
00655   else if (statusreg == 0x0300) /* The flag to check is in SWIC register */
00656   {
00657     tmpreg = CLK->SWCR;
00658   }
00659   else if (statusreg == 0x0400) /* The flag to check is in CSS register */
00660   {
00661     tmpreg = CLK->CSSR;
00662   }
00663   else /* The flag to check is in CCO register */
00664   {
00665     tmpreg = CLK->CCOR;
00666   }
00667
00668   if ((tmpreg & (uint8_t)CLK_FLAG) != (uint8_t)RESET)
00669   {
00670     bitstatus = SET;
00671   }
00672   else
00673   {
00674     bitstatus = RESET;
00675   }
00676
00677   /* Return the flag status */
00678   return((FlagStatus)bitstatus);
00679 }
00680
00681 /**
00682   * @brief  Checks whether the specified CLK interrupt has is enabled or not.
00683   * @param   CLK_IT specifies the CLK interrupt.
00684   * can be one of the values of @ref CLK_IT_TypeDef
00685   * @retval ITStatus, new state of CLK_IT (SET or RESET).
00686   */
00687 ITStatus CLK_GetITStatus(CLK_IT_TypeDef CLK_IT)
00688 {
00689   ITStatus bitstatus = RESET;
00690
00691   /* check the parameters */
00692   assert_param(IS_CLK_IT_OK(CLK_IT));
00693
00694   if (CLK_IT == CLK_IT_SWIF)
00695   {
00696     /* Check the status of the clock switch interrupt */
00697     if ((CLK->SWCR & (uint8_t)CLK_IT) == (uint8_t)0x0C)
00698     {
00699       bitstatus = SET;
00700     }
00701     else
00702     {
00703       bitstatus = RESET;
00704     }
00705   }
00706   else /* CLK_IT == CLK_IT_CSSDIE */
00707   {
00708     /* Check the status of the security system detection interrupt */
00709     if ((CLK->CSSR & (uint8_t)CLK_IT) == (uint8_t)0x0C)
00710     {
00711       bitstatus = SET;
00712     }
00713     else
00714     {
00715       bitstatus = RESET;
00716     }
00717   }
00718
00719   /* Return the CLK_IT status */
00720   return bitstatus;
00721 }
00722
00723 /**
00724   * @brief  Clears the CLK’s interrupt pending bits.
00725   * @param   CLK_IT specifies the interrupt pending bits.
00726   * can be one of the values of @ref CLK_IT_TypeDef
00727   * @retval None
00728   */
00729 void CLK_ClearITPendingBit(CLK_IT_TypeDef CLK_IT)
00730 {
00731   /* check the parameters */
00732   assert_param(IS_CLK_IT_OK(CLK_IT));
00733
00734   if (CLK_IT == (uint8_t)CLK_IT_CSSD)
00735   {
00736     /* Clear the status of the security system detection interrupt */
00737     CLK->CSSR &= (uint8_t)(~CLK_CSSR_CSSD);
00738   }
00739   else /* CLK_PendingBit == (uint8_t)CLK_IT_SWIF */
00740   {
00741     /* Clear the status of the clock switch interrupt */
00742     CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWIF);
00743   }
00744
00745 }
00746
00747 /**
00748   * @}
00749   */
00750
00751 /**
00752   * @}
00753   */
00754
00755
00756 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_clk.h Source File

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stm8s_clk.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_clk.h
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all functions prototype and macros for the CLK peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028
00029 /* Define to prevent recursive inclusion -------------------------------------*/
00030 #ifndef __STM8S_CLK_H
00031 #define __STM8S_CLK_H
00032
00033 /* Includes ------------------------------------------------------------------*/
00034 /* Contains the description of all STM8 hardware registers */
00035 #include "stm8s.h"
00036
00037 /* Exported types ------------------------------------------------------------*/
00038 /** @addtogroup CLK_Exported_Types
00039   * @{
00040   */
00041
00042 /**
00043    * @brief  Switch Mode Auto, Manual.
00044    */
00045 typedef enum {
00046   CLK_SWITCHMODE_MANUAL = (uint8_t)0x00, /*!< Enable the manual clock switching mode */
00047   CLK_SWITCHMODE_AUTO   = (uint8_t)0x01  /*!< Enable the automatic clock switching mode */
00048 } CLK_SwitchMode_TypeDef;
00049
00050 /**
00051    * @brief  Current Clock State.
00052    */
00053 typedef enum {
00054   CLK_CURRENTCLOCKSTATE_DISABLE = (uint8_t)0x00, /*!< Current clock disable */
00055   CLK_CURRENTCLOCKSTATE_ENABLE  = (uint8_t)0x01  /*!< Current clock enable */
00056 } CLK_CurrentClockState_TypeDef;
00057
00058 /**
00059    * @brief   Clock security system configuration.
00060    */
00061 typedef enum {
00062   CLK_CSSCONFIG_ENABLEWITHIT = (uint8_t)0x05, /*!< Enable CSS with detection interrupt */
00063   CLK_CSSCONFIG_ENABLE    = (uint8_t)0x01, /*!< Enable CSS without detection interrupt */
00064   CLK_CSSCONFIG_DISABLE      = (uint8_t)0x00  /*!< Leave CSS desactivated (to be used in CLK_Init() function) */
00065 } CLK_CSSConfig_TypeDef;
00066
00067 /**
00068    * @brief   CLK Clock Source.
00069    */
00070 typedef enum {
00071   CLK_SOURCE_HSI    = (uint8_t)0xE1, /*!< Clock Source HSI. */
00072   CLK_SOURCE_LSI    = (uint8_t)0xD2, /*!< Clock Source LSI. */
00073   CLK_SOURCE_HSE    = (uint8_t)0xB4 /*!< Clock Source HSE. */
00074 } CLK_Source_TypeDef;
00075
00076 /**
00077    * @brief   CLK HSI Calibration Value.
00078    */
00079 typedef enum {
00080   CLK_HSITRIMVALUE_0   = (uint8_t)0x00, /*!< HSI Calibration Value 0 */
00081   CLK_HSITRIMVALUE_1   = (uint8_t)0x01, /*!< HSI Calibration Value 1 */
00082   CLK_HSITRIMVALUE_2   = (uint8_t)0x02, /*!< HSI Calibration Value 2 */
00083   CLK_HSITRIMVALUE_3   = (uint8_t)0x03, /*!< HSI Calibration Value 3 */
00084   CLK_HSITRIMVALUE_4   = (uint8_t)0x04, /*!< HSI Calibration Value 4 */
00085   CLK_HSITRIMVALUE_5   = (uint8_t)0x05, /*!< HSI Calibration Value 5 */
00086   CLK_HSITRIMVALUE_6   = (uint8_t)0x06, /*!< HSI Calibration Value 6 */
00087   CLK_HSITRIMVALUE_7   = (uint8_t)0x07  /*!< HSI Calibration Value 7 */
00088 } CLK_HSITrimValue_TypeDef;
00089
00090 /**
00091    * @brief    CLK  Clock Output
00092    */
00093 typedef enum {
00094   CLK_OUTPUT_HSI      = (uint8_t)0x00, /*!< Clock Output HSI */
00095   CLK_OUTPUT_LSI      = (uint8_t)0x02, /*!< Clock Output LSI */
00096   CLK_OUTPUT_HSE      = (uint8_t)0x04, /*!< Clock Output HSE */
00097   CLK_OUTPUT_CPU      = (uint8_t)0x08, /*!< Clock Output CPU */
00098   CLK_OUTPUT_CPUDIV2  = (uint8_t)0x0A, /*!< Clock Output CPU/2 */
00099   CLK_OUTPUT_CPUDIV4  = (uint8_t)0x0C, /*!< Clock Output CPU/4 */
00100   CLK_OUTPUT_CPUDIV8  = (uint8_t)0x0E, /*!< Clock Output CPU/8 */
00101   CLK_OUTPUT_CPUDIV16 = (uint8_t)0x10, /*!< Clock Output CPU/16 */
00102   CLK_OUTPUT_CPUDIV32 = (uint8_t)0x12, /*!< Clock Output CPU/32 */
00103   CLK_OUTPUT_CPUDIV64 = (uint8_t)0x14, /*!< Clock Output CPU/64 */
00104   CLK_OUTPUT_HSIRC    = (uint8_t)0x16, /*!< Clock Output HSI RC */
00105   CLK_OUTPUT_MASTER   = (uint8_t)0x18, /*!< Clock Output Master */
00106   CLK_OUTPUT_OTHERS   = (uint8_t)0x1A  /*!< Clock Output OTHER */
00107 } CLK_Output_TypeDef;
00108
00109 /**
00110    * @brief    CLK Enable peripheral
00111    */
00112 /* Elements values convention: 0xXY
00113     X = choice between the peripheral registers
00114         X = 0 : PCKENR1
00115         X = 1 : PCKENR2
00116     Y = Peripheral position in the register
00117 */
00118 typedef enum {
00119   CLK_PERIPHERAL_I2C     = (uint8_t)0x00, /*!< Peripheral Clock Enable 1, I2C */
00120   CLK_PERIPHERAL_SPI     = (uint8_t)0x01, /*!< Peripheral Clock Enable 1, SPI */
00121 #if defined(STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8AF52Ax) || defined(STM8AF62Ax)
00122   CLK_PERIPHERAL_UART1   = (uint8_t)0x02, /*!< Peripheral Clock Enable 1, UART1 */
00123 #else
00124   CLK_PERIPHERAL_UART1   = (uint8_t)0x03, /*!< Peripheral Clock Enable 1, UART1 */
00125 #endif
00126   CLK_PERIPHERAL_UART2   = (uint8_t)0x03, /*!< Peripheral Clock Enable 1, UART2 */
00127   CLK_PERIPHERAL_UART3   = (uint8_t)0x03, /*!< Peripheral Clock Enable 1, UART3 */
00128   CLK_PERIPHERAL_TIMER6  = (uint8_t)0x04, /*!< Peripheral Clock Enable 1, Timer6 */
00129   CLK_PERIPHERAL_TIMER4  = (uint8_t)0x04, /*!< Peripheral Clock Enable 1, Timer4 */
00130   CLK_PERIPHERAL_TIMER5  = (uint8_t)0x05, /*!< Peripheral Clock Enable 1, Timer5 */
00131   CLK_PERIPHERAL_TIMER2  = (uint8_t)0x05, /*!< Peripheral Clock Enable 1, Timer2 */
00132   CLK_PERIPHERAL_TIMER3  = (uint8_t)0x06, /*!< Peripheral Clock Enable 1, Timer3 */
00133   CLK_PERIPHERAL_TIMER1  = (uint8_t)0x07, /*!< Peripheral Clock Enable 1, Timer1 */
00134   CLK_PERIPHERAL_AWU     = (uint8_t)0x12, /*!< Peripheral Clock Enable 2, AWU */
00135   CLK_PERIPHERAL_ADC     = (uint8_t)0x13, /*!< Peripheral Clock Enable 2, ADC */
00136   CLK_PERIPHERAL_CAN     = (uint8_t)0x17 /*!< Peripheral Clock Enable 2, CAN */
00137 } CLK_Peripheral_TypeDef;
00138
00139 /**
00140    * @brief   CLK Flags.
00141    */
00142 /* Elements values convention: 0xXZZ
00143     X = choice between the flags registers
00144         X = 1 : ICKR
00145         X = 2 : ECKR
00146         X = 3 : SWCR
00147     X = 4 : CSSR
00148  X = 5 : CCOR
00149    ZZ = flag mask in the register (same as map file)
00150 */
00151 typedef enum {
00152   CLK_FLAG_LSIRDY  = (uint16_t)0x0110, /*!< Low speed internal oscillator ready Flag */
00153   CLK_FLAG_HSIRDY  = (uint16_t)0x0102, /*!< High speed internal oscillator ready Flag */
00154   CLK_FLAG_HSERDY  = (uint16_t)0x0202, /*!< High speed external oscillator ready Flag */
00155   CLK_FLAG_SWIF    = (uint16_t)0x0308, /*!< Clock switch interrupt Flag */
00156   CLK_FLAG_SWBSY   = (uint16_t)0x0301, /*!< Switch busy Flag */
00157   CLK_FLAG_CSSD    = (uint16_t)0x0408, /*!< Clock security system detection Flag */
00158   CLK_FLAG_AUX     = (uint16_t)0x0402, /*!< Auxiliary oscillator connected to master clock */
00159   CLK_FLAG_CCOBSY  = (uint16_t)0x0504, /*!< Configurable clock output busy */
00160   CLK_FLAG_CCORDY  = (uint16_t)0x0502 /*!< Configurable clock output ready */
00161 }CLK_Flag_TypeDef;
00162
00163 /**
00164    * @brief  CLK interrupt configuration and Flags cleared by software.
00165    */
00166 typedef enum {
00167   CLK_IT_CSSD = (uint8_t)0x0C, /*!< Clock security system detection Flag */
00168   CLK_IT_SWIF = (uint8_t)0x1C /*!< Clock switch interrupt Flag */
00169 }CLK_IT_TypeDef;
00170
00171 /**
00172    * @brief   CLK Clock Divisor.
00173    */
00174
00175 /* Warning:
00176    0xxxxxx = HSI divider
00177    1xxxxxx = CPU divider
00178    Other bits correspond to the divider's bits mapping
00179 */
00180 typedef enum {
00181   CLK_PRESCALER_HSIDIV1   = (uint8_t)0x00, /*!< High speed internal clock prescaler: 1 */
00182   CLK_PRESCALER_HSIDIV2   = (uint8_t)0x08, /*!< High speed internal clock prescaler: 2 */
00183   CLK_PRESCALER_HSIDIV4   = (uint8_t)0x10, /*!< High speed internal clock prescaler: 4 */
00184   CLK_PRESCALER_HSIDIV8   = (uint8_t)0x18, /*!< High speed internal clock prescaler: 8 */
00185   CLK_PRESCALER_CPUDIV1   = (uint8_t)0x80, /*!< CPU clock division factors 1 */
00186   CLK_PRESCALER_CPUDIV2   = (uint8_t)0x81, /*!< CPU clock division factors 2 */
00187   CLK_PRESCALER_CPUDIV4   = (uint8_t)0x82, /*!< CPU clock division factors 4 */
00188   CLK_PRESCALER_CPUDIV8   = (uint8_t)0x83, /*!< CPU clock division factors 8 */
00189   CLK_PRESCALER_CPUDIV16  = (uint8_t)0x84, /*!< CPU clock division factors 16 */
00190   CLK_PRESCALER_CPUDIV32  = (uint8_t)0x85, /*!< CPU clock division factors 32 */
00191   CLK_PRESCALER_CPUDIV64  = (uint8_t)0x86, /*!< CPU clock division factors 64 */
00192   CLK_PRESCALER_CPUDIV128 = (uint8_t)0x87  /*!< CPU clock division factors 128 */
00193 } CLK_Prescaler_TypeDef;
00194
00195 /**
00196    * @brief   SWIM Clock divider.
00197    */
00198 typedef enum {
00199   CLK_SWIMDIVIDER_2 = (uint8_t)0x00, /*!< SWIM clock is divided by 2 */
00200   CLK_SWIMDIVIDER_OTHER = (uint8_t)0x01 /*!< SWIM clock is not divided by 2 */
00201 }CLK_SWIMDivider_TypeDef;
00202
00203 /**
00204   * @}
00205   */
00206
00207 /* Exported constants --------------------------------------------------------*/
00208
00209 /** @addtogroup CLK_Exported_Constants
00210   * @{
00211   */
00212 #define CLK_TIMEOUT ((uint16_t)0xFFFF) /*!< Max Timeout for the clock switch operation. */
00213 /**
00214   * @}
00215   */
00216
00217 /* Private macros ------------------------------------------------------------*/
00218 /** @addtogroup CLK_Private_Macros
00219   * @{
00220   */
00221
00222 /**
00223   * @brief  Macros used by the assert function in order to check the different functions parameters.
00224   */
00225
00226 /**
00227   * @brief  Macros used by the assert function in order to check the clock switching modes.
00228   */
00229 #define IS_CLK_SWITCHMODE_OK(MODE) (((MODE) == CLK_SWITCHMODE_MANUAL) || ((MODE) == CLK_SWITCHMODE_AUTO))
00230
00231 /**
00232   * @brief  Macros used by the assert function in order to check the current clock state.
00233   */
00234 #define IS_CLK_CURRENTCLOCKSTATE_OK(STATE) (((STATE) == CLK_CURRENTCLOCKSTATE_DISABLE) ||\
00235                                             ((STATE) == CLK_CURRENTCLOCKSTATE_ENABLE))
00236
00237 /**
00238   * @brief  Macros used by the assert function in order to check the CSS configuration.
00239   */
00240 #define IS_CLK_CSSCONFIG_OK(CSSVALUE) (((CSSVALUE) == CLK_CSSCONFIG_ENABLEWITHIT) ||\
00241                                        ((CSSVALUE) == CLK_CSSCONFIG_ENABLE) ||\
00242                                        ((CSSVALUE) == CLK_CSSCONFIG_DISABLE))
00243
00244 /**
00245   * @brief  Macros used by the assert function in order to check the different clock sources.
00246   */
00247 #define IS_CLK_SOURCE_OK(SOURCE) (((SOURCE) == CLK_SOURCE_HSI) ||\
00248                                   ((SOURCE) == CLK_SOURCE_LSI) ||\
00249                                   ((SOURCE) == CLK_SOURCE_HSE))
00250
00251 /**
00252   * @brief  Macros used by the assert function in order to check the different HSI trimming values.
00253   */
00254 #define IS_CLK_HSITRIMVALUE_OK(TRIMVALUE) (((TRIMVALUE) == CLK_HSITRIMVALUE_0) ||\
00255     ((TRIMVALUE) == CLK_HSITRIMVALUE_1) ||\
00256     ((TRIMVALUE) == CLK_HSITRIMVALUE_2) ||\
00257     ((TRIMVALUE) == CLK_HSITRIMVALUE_3) ||\
00258     ((TRIMVALUE) == CLK_HSITRIMVALUE_4) ||\
00259     ((TRIMVALUE) == CLK_HSITRIMVALUE_5) ||\
00260     ((TRIMVALUE) == CLK_HSITRIMVALUE_6) ||\
00261     ((TRIMVALUE) == CLK_HSITRIMVALUE_7))
00262
00263 /**
00264   * @brief  Macros used by the assert function in order to check the different clocks to output.
00265   */
00266 #define IS_CLK_OUTPUT_OK(OUTPUT) (((OUTPUT) == CLK_OUTPUT_HSI) ||\
00267                                   ((OUTPUT) == CLK_OUTPUT_HSE) ||\
00268                                   ((OUTPUT) == CLK_OUTPUT_LSI) ||\
00269                                   ((OUTPUT) == CLK_OUTPUT_CPU) ||\
00270                                   ((OUTPUT) == CLK_OUTPUT_CPUDIV2) ||\
00271                                   ((OUTPUT) == CLK_OUTPUT_CPUDIV4) ||\
00272                                   ((OUTPUT) == CLK_OUTPUT_CPUDIV8) ||\
00273                                   ((OUTPUT) == CLK_OUTPUT_CPUDIV16) ||\
00274                                   ((OUTPUT) == CLK_OUTPUT_CPUDIV32) ||\
00275                                   ((OUTPUT) == CLK_OUTPUT_CPUDIV64) ||\
00276                                   ((OUTPUT) == CLK_OUTPUT_HSIRC) ||\
00277                                   ((OUTPUT) == CLK_OUTPUT_MASTER) ||\
00278                                   ((OUTPUT) == CLK_OUTPUT_OTHERS))
00279
00280 /**
00281   * @brief  Macros used by the assert function in order to check the different peripheral's clock.
00282   */
00283 #define IS_CLK_PERIPHERAL_OK(PERIPHERAL) (((PERIPHERAL) == CLK_PERIPHERAL_I2C) ||\
00284     ((PERIPHERAL) == CLK_PERIPHERAL_SPI) ||\
00285     ((PERIPHERAL) == CLK_PERIPHERAL_UART3) ||\
00286     ((PERIPHERAL) == CLK_PERIPHERAL_UART2) ||\
00287     ((PERIPHERAL) == CLK_PERIPHERAL_UART1) ||\
00288     ((PERIPHERAL) == CLK_PERIPHERAL_TIMER4) ||\
00289     ((PERIPHERAL) == CLK_PERIPHERAL_TIMER2) ||\
00290     ((PERIPHERAL) == CLK_PERIPHERAL_TIMER5) ||\
00291     ((PERIPHERAL) == CLK_PERIPHERAL_TIMER6) ||\
00292     ((PERIPHERAL) == CLK_PERIPHERAL_TIMER3) ||\
00293     ((PERIPHERAL) == CLK_PERIPHERAL_TIMER1) ||\
00294     ((PERIPHERAL) == CLK_PERIPHERAL_CAN) ||\
00295     ((PERIPHERAL) == CLK_PERIPHERAL_ADC) ||\
00296     ((PERIPHERAL) == CLK_PERIPHERAL_AWU))
00297
00298 /**
00299   * @brief  Macros used by the assert function in order to check the different clock flags.
00300   */
00301 #define IS_CLK_FLAG_OK(FLAG) (((FLAG) == CLK_FLAG_LSIRDY) ||\
00302                               ((FLAG) == CLK_FLAG_HSIRDY) ||\
00303                               ((FLAG) == CLK_FLAG_HSERDY) ||\
00304                               ((FLAG) == CLK_FLAG_SWIF) ||\
00305                               ((FLAG) == CLK_FLAG_SWBSY) ||\
00306                               ((FLAG) == CLK_FLAG_CSSD) ||\
00307                               ((FLAG) == CLK_FLAG_AUX) ||\
00308                               ((FLAG) == CLK_FLAG_CCOBSY) ||\
00309                               ((FLAG) == CLK_FLAG_CCORDY))
00310
00311 /**
00312   * @brief  Macros used by the assert function in order to check the different clock IT pending bits.
00313   */
00314 #define IS_CLK_IT_OK(IT) (((IT) == CLK_IT_CSSD) || ((IT) == CLK_IT_SWIF))
00315
00316 /**
00317   * @brief  Macros used by the assert function in order to check the different HSI prescaler values.
00318   */
00319 #define IS_CLK_HSIPRESCALER_OK(PRESCALER) (((PRESCALER) == CLK_PRESCALER_HSIDIV1) ||\
00320     ((PRESCALER) == CLK_PRESCALER_HSIDIV2) ||\
00321     ((PRESCALER) == CLK_PRESCALER_HSIDIV4) ||\
00322     ((PRESCALER) == CLK_PRESCALER_HSIDIV8))
00323
00324 /**
00325   * @brief  Macros used by the assert function in order to check the different clock  prescaler values.
00326   */
00327 #define IS_CLK_PRESCALER_OK(PRESCALER) (((PRESCALER) == CLK_PRESCALER_HSIDIV1) ||\
00328                                         ((PRESCALER) == CLK_PRESCALER_HSIDIV2) ||\
00329                                         ((PRESCALER) == CLK_PRESCALER_HSIDIV4) ||\
00330                                         ((PRESCALER) == CLK_PRESCALER_HSIDIV8) ||\
00331                                         ((PRESCALER) == CLK_PRESCALER_CPUDIV1) ||\
00332                                         ((PRESCALER) == CLK_PRESCALER_CPUDIV2) ||\
00333                                         ((PRESCALER) == CLK_PRESCALER_CPUDIV4) ||\
00334                                         ((PRESCALER) == CLK_PRESCALER_CPUDIV8) ||\
00335                                         ((PRESCALER) == CLK_PRESCALER_CPUDIV16) ||\
00336                                         ((PRESCALER) == CLK_PRESCALER_CPUDIV32) ||\
00337                                         ((PRESCALER) == CLK_PRESCALER_CPUDIV64) ||\
00338                                         ((PRESCALER) == CLK_PRESCALER_CPUDIV128))
00339
00340 /**
00341   * @brief  Macros used by the assert function in order to check the different SWIM dividers values.
00342   */
00343 #define IS_CLK_SWIMDIVIDER_OK(SWIMDIVIDER) (((SWIMDIVIDER) == CLK_SWIMDIVIDER_2) || ((SWIMDIVIDER) == CLK_SWIMDIVIDER_OTHER))
00344
00345 /**
00346   * @}
00347   */
00348
00349 /** @addtogroup CLK_Exported_functions
00350   * @{
00351   */
00352 void CLK_DeInit(void);
00353 void CLK_HSECmd(FunctionalState NewState);
00354 void CLK_HSICmd(FunctionalState NewState);
00355 void CLK_LSICmd(FunctionalState NewState);
00356 void CLK_CCOCmd(FunctionalState NewState);
00357 void CLK_ClockSwitchCmd(FunctionalState NewState);
00358 void CLK_FastHaltWakeUpCmd(FunctionalState NewState);
00359 void CLK_SlowActiveHaltWakeUpCmd(FunctionalState NewState);
00360 void CLK_PeripheralClockConfig(CLK_Peripheral_TypeDef CLK_Peripheral, FunctionalState NewState);
00361 ErrorStatus CLK_ClockSwitchConfig(CLK_SwitchMode_TypeDef CLK_SwitchMode, CLK_Source_TypeDef CLK_NewClock, FunctionalState ITState, CLK_CurrentClockState_TypeDef CLK_CurrentClockState);
00362 void CLK_HSIPrescalerConfig(CLK_Prescaler_TypeDef HSIPrescaler);
00363 void CLK_CCOConfig(CLK_Output_TypeDef CLK_CCO);
00364 void CLK_ITConfig(CLK_IT_TypeDef CLK_IT, FunctionalState NewState);
00365 void CLK_SYSCLKConfig(CLK_Prescaler_TypeDef CLK_Prescaler);
00366 void CLK_SWIMConfig(CLK_SWIMDivider_TypeDef CLK_SWIMDivider);
00367 void CLK_ClockSecuritySystemEnable(void);
00368 void CLK_SYSCLKEmergencyClear(void);
00369 void CLK_AdjustHSICalibrationValue(CLK_HSITrimValue_TypeDef CLK_HSICalibrationValue);
00370 uint32_t CLK_GetClockFreq(void);
00371 CLK_Source_TypeDef CLK_GetSYSCLKSource(void);
00372 FlagStatus CLK_GetFlagStatus(CLK_Flag_TypeDef CLK_FLAG);
00373 ITStatus CLK_GetITStatus(CLK_IT_TypeDef CLK_IT);
00374 void CLK_ClearITPendingBit(CLK_IT_TypeDef CLK_IT);
00375
00376 /**
00377   * @}
00378   */
00379 #endif /* __STM8S_CLK_H */
00380
00381
00382 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_exti.c Source File

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
stm8s_exti.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_exti.c
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all the functions for the EXTI peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm8s_exti.h"
00030
00031 /** @addtogroup STM8S_StdPeriph_Driver
00032   * @{
00033   */
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 /* Private macro -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038 /* Private function prototypes -----------------------------------------------*/
00039 /* Private functions ---------------------------------------------------------*/
00040
00041 /* Public functions ----------------------------------------------------------*/
00042
00043 /**
00044   * @addtogroup EXTI_Public_Functions
00045   * @{
00046   */
00047
00048 /**
00049   * @brief  Deinitializes the external interrupt control registers to their default reset value.
00050   * @param  None
00051   * @retval None
00052   */
00053 void EXTI_DeInit(void)
00054 {
00055   EXTI->CR1 = EXTI_CR1_RESET_VALUE;
00056   EXTI->CR2 = EXTI_CR2_RESET_VALUE;
00057 }
00058
00059 /**
00060   * @brief  Set the external interrupt sensitivity of the selected port.
00061   * @warning
00062   * - The modification of external interrupt sensitivity is only possible when the interrupts are disabled.
00063   * - The normal behavior is to disable the interrupts before calling this function, and re-enable them after.
00064   * @param   Port The port number to access.
00065   * @param   SensitivityValue The external interrupt sensitivity value to set.
00066   * @retval None
00067   * @par Required preconditions:
00068   * Global interrupts must be disabled before calling this function.
00069   */
00070 void EXTI_SetExtIntSensitivity(EXTI_Port_TypeDef Port, EXTI_Sensitivity_TypeDef SensitivityValue)
00071 {
00072   /* Check function parameters */
00073   assert_param(IS_EXTI_PORT_OK(Port));
00074   assert_param(IS_EXTI_SENSITIVITY_OK(SensitivityValue));
00075
00076   /* Set external interrupt sensitivity */
00077   switch (Port)
00078   {
00079   case EXTI_PORT_GPIOA:
00080     EXTI->CR1 &= (uint8_t)(~EXTI_CR1_PAIS);
00081     EXTI->CR1 |= (uint8_t)(SensitivityValue);
00082     break;
00083   case EXTI_PORT_GPIOB:
00084     EXTI->CR1 &= (uint8_t)(~EXTI_CR1_PBIS);
00085     EXTI->CR1 |= (uint8_t)((uint8_t)(SensitivityValue) << 2);
00086     break;
00087   case EXTI_PORT_GPIOC:
00088     EXTI->CR1 &= (uint8_t)(~EXTI_CR1_PCIS);
00089     EXTI->CR1 |= (uint8_t)((uint8_t)(SensitivityValue) << 4);
00090     break;
00091   case EXTI_PORT_GPIOD:
00092     EXTI->CR1 &= (uint8_t)(~EXTI_CR1_PDIS);
00093     EXTI->CR1 |= (uint8_t)((uint8_t)(SensitivityValue) << 6);
00094     break;
00095   case EXTI_PORT_GPIOE:
00096     EXTI->CR2 &= (uint8_t)(~EXTI_CR2_PEIS);
00097     EXTI->CR2 |= (uint8_t)(SensitivityValue);
00098     break;
00099   default:
00100     break;
00101   }
00102 }
00103
00104 /**
00105   * @brief  Set the TLI interrupt sensitivity.
00106   * @param   SensitivityValue The TLI interrupt sensitivity value.
00107   * @retval None
00108   * @par Required preconditions:
00109   * Global interrupts must be disabled before calling this function.
00110   */
00111 void EXTI_SetTLISensitivity(EXTI_TLISensitivity_TypeDef SensitivityValue)
00112 {
00113   /* Check function parameters */
00114   assert_param(IS_EXTI_TLISENSITIVITY_OK(SensitivityValue));
00115
00116   /* Set TLI interrupt sensitivity */
00117   EXTI->CR2 &= (uint8_t)(~EXTI_CR2_TLIS);
00118   EXTI->CR2 |= (uint8_t)(SensitivityValue);
00119 }
00120
00121 /**
00122   * @brief  Get the external interrupt sensitivity of the selected port.
00123   * @param   Port The port number to access.
00124   * @retval EXTI_Sensitivity_TypeDef The external interrupt sensitivity of the selected port.
00125   */
00126 EXTI_Sensitivity_TypeDef EXTI_GetExtIntSensitivity(EXTI_Port_TypeDef Port)
00127 {
00128   uint8_t value = 0;
00129
00130   /* Check function parameters */
00131   assert_param(IS_EXTI_PORT_OK(Port));
00132
00133   switch (Port)
00134   {
00135   case EXTI_PORT_GPIOA:
00136     value = (uint8_t)(EXTI->CR1 & EXTI_CR1_PAIS);
00137     break;
00138   case EXTI_PORT_GPIOB:
00139     value = (uint8_t)((uint8_t)(EXTI->CR1 & EXTI_CR1_PBIS) >> 2);
00140     break;
00141   case EXTI_PORT_GPIOC:
00142     value = (uint8_t)((uint8_t)(EXTI->CR1 & EXTI_CR1_PCIS) >> 4);
00143     break;
00144   case EXTI_PORT_GPIOD:
00145     value = (uint8_t)((uint8_t)(EXTI->CR1 & EXTI_CR1_PDIS) >> 6);
00146     break;
00147   case EXTI_PORT_GPIOE:
00148     value = (uint8_t)(EXTI->CR2 & EXTI_CR2_PEIS);
00149     break;
00150   default:
00151     break;
00152   }
00153
00154   return((EXTI_Sensitivity_TypeDef)value);
00155 }
00156
00157 /**
00158   * @brief  Get the TLI interrupt sensitivity.
00159   * @param  None
00160   * @retval EXTI_TLISensitivity_TypeDef The TLI interrupt sensitivity read.
00161   */
00162 EXTI_TLISensitivity_TypeDef EXTI_GetTLISensitivity(void)
00163 {
00164   uint8_t value = 0;
00165
00166   /* Get TLI interrupt sensitivity */
00167   value = (uint8_t)(EXTI->CR2 & EXTI_CR2_TLIS);
00168
00169   return((EXTI_TLISensitivity_TypeDef)value);
00170 }
00171
00172 /**
00173   * @}
00174   */
00175
00176 /**
00177   * @}
00178   */
00179
00180
00181 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_exti.h Source File

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
stm8s_exti.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_exti.h
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all functions prototype and macros for the EXTI peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Define to prevent recursive inclusion -------------------------------------*/
00029 #ifndef __STM8S_EXTI_H
00030 #define __STM8S_EXTI_H
00031
00032 /* Includes ------------------------------------------------------------------*/
00033 #include "stm8s.h"
00034
00035 /* Exported types ------------------------------------------------------------*/
00036
00037 /** @addtogroup EXTI_Exported_Types
00038   * @{
00039   */
00040
00041 /**
00042   * @brief  EXTI Sensitivity values for PORTA to PORTE
00043   */
00044 typedef enum {
00045   EXTI_SENSITIVITY_FALL_LOW  = (uint8_t)0x00, /*!< Interrupt on Falling edge and Low level */
00046   EXTI_SENSITIVITY_RISE_ONLY = (uint8_t)0x01, /*!< Interrupt on Rising edge only */
00047   EXTI_SENSITIVITY_FALL_ONLY = (uint8_t)0x02, /*!< Interrupt on Falling edge only */
00048   EXTI_SENSITIVITY_RISE_FALL = (uint8_t)0x03  /*!< Interrupt on Rising and Falling edges */
00049 } EXTI_Sensitivity_TypeDef;
00050
00051 /**
00052   * @brief  EXTI Sensitivity values for TLI
00053   */
00054 typedef enum {
00055   EXTI_TLISENSITIVITY_FALL_ONLY = (uint8_t)0x00, /*!< Top Level Interrupt on Falling edge only */
00056   EXTI_TLISENSITIVITY_RISE_ONLY = (uint8_t)0x04  /*!< Top Level Interrupt on Rising edge only */
00057 } EXTI_TLISensitivity_TypeDef;
00058
00059 /**
00060   * @brief  EXTI PortNum possible values
00061   */
00062 typedef enum {
00063   EXTI_PORT_GPIOA = (uint8_t)0x00, /*!< GPIO Port A */
00064   EXTI_PORT_GPIOB = (uint8_t)0x01, /*!< GPIO Port B */
00065   EXTI_PORT_GPIOC = (uint8_t)0x02, /*!< GPIO Port C */
00066   EXTI_PORT_GPIOD = (uint8_t)0x03, /*!< GPIO Port D */
00067   EXTI_PORT_GPIOE = (uint8_t)0x04  /*!< GPIO Port E */
00068 } EXTI_Port_TypeDef;
00069
00070 /**
00071   * @}
00072   */
00073
00074 /* Private macros ------------------------------------------------------------*/
00075
00076 /** @addtogroup EXTI_Private_Macros
00077   * @{
00078   */
00079
00080 /**
00081   * @brief  Macro used by the assert function in order to check the different sensitivity values for PORTA to PORTE.
00082   */
00083 #define IS_EXTI_SENSITIVITY_OK(SensitivityValue) \
00084   (((SensitivityValue) == EXTI_SENSITIVITY_FALL_LOW) || \
00085    ((SensitivityValue) == EXTI_SENSITIVITY_RISE_ONLY) || \
00086    ((SensitivityValue) == EXTI_SENSITIVITY_FALL_ONLY) || \
00087    ((SensitivityValue) == EXTI_SENSITIVITY_RISE_FALL))
00088
00089 /**
00090   * @brief  Macro used by the assert function in order to check the different sensitivity values for TLI.
00091   */
00092 #define IS_EXTI_TLISENSITIVITY_OK(SensitivityValue) \
00093   (((SensitivityValue) == EXTI_TLISENSITIVITY_FALL_ONLY) || \
00094    ((SensitivityValue) == EXTI_TLISENSITIVITY_RISE_ONLY))
00095
00096 /**
00097   * @brief  Macro used by the assert function in order to check the different Port values
00098   */
00099 #define IS_EXTI_PORT_OK(PORT) \
00100   (((PORT) == EXTI_PORT_GPIOA) ||\
00101    ((PORT) == EXTI_PORT_GPIOB) ||\
00102    ((PORT) == EXTI_PORT_GPIOC) ||\
00103    ((PORT) == EXTI_PORT_GPIOD) ||\
00104    ((PORT) == EXTI_PORT_GPIOE))
00105
00106 /**
00107   * @brief  Macro used by the assert function in order to check the different values of the EXTI PinMask
00108   */
00109 #define IS_EXTI_PINMASK_OK(PinMask) ((((PinMask) & (uint8_t)0x00) == (uint8_t)0x00) && ((PinMask) != (uint8_t)0x00))
00110
00111 /**
00112   * @}
00113   */
00114
00115 /* Exported functions ------------------------------------------------------- */
00116
00117 /** @addtogroup EXTI_Exported_Functions
00118   * @{
00119   */
00120
00121 void EXTI_DeInit(void);
00122 void EXTI_SetExtIntSensitivity(EXTI_Port_TypeDef Port, EXTI_Sensitivity_TypeDef SensitivityValue);
00123 void EXTI_SetTLISensitivity(EXTI_TLISensitivity_TypeDef SensitivityValue);
00124 EXTI_Sensitivity_TypeDef EXTI_GetExtIntSensitivity(EXTI_Port_TypeDef Port);
00125 EXTI_TLISensitivity_TypeDef EXTI_GetTLISensitivity(void);
00126
00127 /**
00128   * @}
00129   */
00130
00131 #endif /* __STM8S_EXTI_H */
00132
00133
00134 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_flash.c Source File

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stm8s_flash.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_flash.c
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all the functions for the FLASH peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm8s_flash.h"
00030
00031 /** @addtogroup STM8S_StdPeriph_Driver
00032   * @{
00033   */
00034 /**
00035 @code
00036  This driver provides functions to configure and program the Flash memory of all
00037  STM8S devices.
00038
00039  It includes as well functions that can be either executed from RAM or not, and
00040  other functions that must be executed from RAM otherwise useless.
00041
00042  The table below lists the functions that can be executed from RAM.
00043
00044  +--------------------------------------------------------------------------------|
00045  |   Functions prototypes      |    RAM execution            |     Comments       |
00046  ---------------------------------------------------------------------------------|
00047  |                             | Mandatory in case of block  | Can be executed    |
00048  | FLASH_WaitForLastOperation  | Operation:                  | from Flash in case |
00049  |                             | - Block programming         | of byte and word   |
00050  |                             | - Block erase               | Operations         |
00051  |--------------------------------------------------------------------------------|
00052  | FLASH_ProgramBlock          |       Exclusively           | useless from Flash |
00053  |--------------------------------------------------------------------------------|
00054  | FLASH_EraseBlock            |       Exclusively           | useless from Flash |
00055  |--------------------------------------------------------------------------------|
00056
00057  To be able to execute functions from RAM several steps have to be followed.
00058  These steps may differ from one toolchain to another.
00059  A detailed description is available below within this driver.
00060  You can also refer to the FLASH examples provided within the
00061  STM8S_StdPeriph_Lib package.
00062
00063 @endcode
00064 */
00065
00066
00067 /* Private typedef -----------------------------------------------------------*/
00068 /* Private define ------------------------------------------------------------*/
00069 #define FLASH_CLEAR_BYTE    ((uint8_t)0x00)
00070 #define FLASH_SET_BYTE      ((uint8_t)0xFF)
00071 #define OPERATION_TIMEOUT   ((uint16_t)0xFFFF)
00072 /* Private macro -------------------------------------------------------------*/
00073 /* Private variables ---------------------------------------------------------*/
00074 /* Private function prototypes -----------------------------------------------*/
00075 /* Private Constants ---------------------------------------------------------*/
00076
00077 /** @addtogroup FLASH_Public_functions
00078   * @{
00079   */
00080
00081 /**
00082   * @brief  Unlocks the program or data EEPROM memory
00083   * @param  FLASH_MemType : Memory type to unlock
00084   *         This parameter can be a value of @ref FLASH_MemType_TypeDef
00085   * @retval None
00086   */
00087 void FLASH_Unlock(FLASH_MemType_TypeDef FLASH_MemType)
00088 {
00089   /* Check parameter */
00090   assert_param(IS_MEMORY_TYPE_OK(FLASH_MemType));
00091
00092   /* Unlock program memory */
00093   if(FLASH_MemType == FLASH_MEMTYPE_PROG)
00094   {
00095     FLASH->PUKR = FLASH_RASS_KEY1;
00096     FLASH->PUKR = FLASH_RASS_KEY2;
00097   }
00098   /* Unlock data memory */
00099   else
00100   {
00101     FLASH->DUKR = FLASH_RASS_KEY2; /* Warning: keys are reversed on data memory !!! */
00102     FLASH->DUKR = FLASH_RASS_KEY1;
00103   }
00104 }
00105
00106 /**
00107   * @brief  Locks the program or data EEPROM memory
00108   * @param  FLASH_MemType : Memory type
00109   *         This parameter can be a value of @ref FLASH_MemType_TypeDef
00110   * @retval None
00111   */
00112 void FLASH_Lock(FLASH_MemType_TypeDef FLASH_MemType)
00113 {
00114   /* Check parameter */
00115   assert_param(IS_MEMORY_TYPE_OK(FLASH_MemType));
00116
00117   /* Lock memory */
00118   FLASH->IAPSR &= (uint8_t)FLASH_MemType;
00119 }
00120
00121 /**
00122   * @brief  DeInitializes the FLASH registers to their default reset values.
00123   * @param  None
00124   * @retval None
00125   */
00126 void FLASH_DeInit(void)
00127 {
00128   FLASH->CR1 = FLASH_CR1_RESET_VALUE;
00129   FLASH->CR2 = FLASH_CR2_RESET_VALUE;
00130   FLASH->NCR2 = FLASH_NCR2_RESET_VALUE;
00131   FLASH->IAPSR &= (uint8_t)(~FLASH_IAPSR_DUL);
00132   FLASH->IAPSR &= (uint8_t)(~FLASH_IAPSR_PUL);
00133   (void) FLASH->IAPSR; /* Reading of this register causes the clearing of status flags */
00134 }
00135
00136 /**
00137   * @brief  Enables or Disables the Flash interrupt mode
00138   * @param  NewState : The new state of the flash interrupt mode
00139   *         This parameter can be a value of @ref FunctionalState enumeration.
00140   * @retval None
00141   */
00142 void FLASH_ITConfig(FunctionalState NewState)
00143 {
00144   /* Check parameter */
00145   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00146
00147   if(NewState != DISABLE)
00148   {
00149     FLASH->CR1 |= FLASH_CR1_IE; /* Enables the interrupt sources */
00150   }
00151   else
00152   {
00153     FLASH->CR1 &= (uint8_t)(~FLASH_CR1_IE); /* Disables the interrupt sources */
00154   }
00155 }
00156
00157 /**
00158   * @brief  Erases one byte in the program or data EEPROM memory
00159   * @note   PointerAttr define is declared in the stm8s.h file to select if
00160   *         the pointer will be declared as near (2 bytes) or far (3 bytes).
00161   * @param  Address : Address of the byte to erase
00162   * @retval None
00163   */
00164 void FLASH_EraseByte(uint32_t Address)
00165 {
00166   /* Check parameter */
00167   assert_param(IS_FLASH_ADDRESS_OK(Address));
00168
00169   /* Erase byte */
00170   *(PointerAttr uint8_t*) (MemoryAddressCast)Address = FLASH_CLEAR_BYTE;
00171 }
00172
00173 /**
00174   * @brief  Programs one byte in program or data EEPROM memory
00175   * @note   PointerAttr define is declared in the stm8s.h file to select if
00176   *         the pointer will be declared as near (2 bytes) or far (3 bytes).
00177   * @param  Address : Address where the byte will be programmed
00178   * @param  Data : Value to be programmed
00179   * @retval None
00180   */
00181 void FLASH_ProgramByte(uint32_t Address, uint8_t Data)
00182 {
00183   /* Check parameters */
00184   assert_param(IS_FLASH_ADDRESS_OK(Address));
00185   *(PointerAttr uint8_t*) (MemoryAddressCast)Address = Data;
00186 }
00187
00188 /**
00189   * @brief  Reads any byte from flash memory
00190   * @note   PointerAttr define is declared in the stm8s.h file to select if
00191   *         the pointer will be declared as near (2 bytes) or far (3 bytes).
00192   * @param  Address : Address to read
00193   * @retval Value of the byte
00194   */
00195 uint8_t FLASH_ReadByte(uint32_t Address)
00196 {
00197   /* Check parameter */
00198   assert_param(IS_FLASH_ADDRESS_OK(Address));
00199
00200   /* Read byte */
00201   return(*(PointerAttr uint8_t *) (MemoryAddressCast)Address);
00202 }
00203
00204 /**
00205   * @brief  Programs one word (4 bytes) in program or data EEPROM memory
00206   * @note   PointerAttr define is declared in the stm8s.h file to select if
00207   *         the pointer will be declared as near (2 bytes) or far (3 bytes).
00208   * @param  Address : The address where the data will be programmed
00209   * @param  Data : Value to be programmed
00210   * @retval None
00211   */
00212 void FLASH_ProgramWord(uint32_t Address, uint32_t Data)
00213 {
00214   /* Check parameters */
00215   assert_param(IS_FLASH_ADDRESS_OK(Address));
00216
00217   /* Enable Word Write Once */
00218   FLASH->CR2 |= FLASH_CR2_WPRG;
00219   FLASH->NCR2 &= (uint8_t)(~FLASH_NCR2_NWPRG);
00220
00221   /* Write one byte - from lowest address*/
00222   *((PointerAttr uint8_t*)(MemoryAddressCast)Address)       = *((uint8_t*)(&Data));
00223   /* Write one byte*/
00224   *(((PointerAttr uint8_t*)(MemoryAddressCast)Address) + 1) = *((uint8_t*)(&Data)+1);
00225   /* Write one byte*/
00226   *(((PointerAttr uint8_t*)(MemoryAddressCast)Address) + 2) = *((uint8_t*)(&Data)+2);
00227   /* Write one byte - from higher address*/
00228   *(((PointerAttr uint8_t*)(MemoryAddressCast)Address) + 3) = *((uint8_t*)(&Data)+3);
00229 }
00230
00231 /**
00232   * @brief  Programs option byte
00233   * @param  Address : option byte address to program
00234   * @param  Data : Value to write
00235   * @retval None
00236   */
00237 void FLASH_ProgramOptionByte(uint16_t Address, uint8_t Data)
00238 {
00239   /* Check parameter */
00240   assert_param(IS_OPTION_BYTE_ADDRESS_OK(Address));
00241
00242   /* Enable write access to option bytes */
00243   FLASH->CR2 |= FLASH_CR2_OPT;
00244   FLASH->NCR2 &= (uint8_t)(~FLASH_NCR2_NOPT);
00245
00246   /* check if the option byte to program is ROP*/
00247   if(Address == 0x4800)
00248   {
00249     /* Program option byte*/
00250     *((NEAR uint8_t*)Address) = Data;
00251   }
00252   else
00253   {
00254     /* Program option byte and his complement */
00255     *((NEAR uint8_t*)Address) = Data;
00256     *((NEAR uint8_t*)((uint16_t)(Address + 1))) = (uint8_t)(~Data);
00257   }
00258   FLASH_WaitForLastOperation(FLASH_MEMTYPE_PROG);
00259
00260   /* Disable write access to option bytes */
00261   FLASH->CR2 &= (uint8_t)(~FLASH_CR2_OPT);
00262   FLASH->NCR2 |= FLASH_NCR2_NOPT;
00263 }
00264
00265 /**
00266   * @brief  Erases option byte
00267   * @param  Address : Option byte address to erase
00268   * @retval None
00269   */
00270 void FLASH_EraseOptionByte(uint16_t Address)
00271 {
00272   /* Check parameter */
00273   assert_param(IS_OPTION_BYTE_ADDRESS_OK(Address));
00274
00275   /* Enable write access to option bytes */
00276   FLASH->CR2 |= FLASH_CR2_OPT;
00277   FLASH->NCR2 &= (uint8_t)(~FLASH_NCR2_NOPT);
00278
00279   /* check if the option byte to erase is ROP */
00280   if(Address == 0x4800)
00281   {
00282     /* Erase option byte */
00283     *((NEAR uint8_t*)Address) = FLASH_CLEAR_BYTE;
00284   }
00285   else
00286   {
00287     /* Erase option byte and his complement */
00288     *((NEAR uint8_t*)Address) = FLASH_CLEAR_BYTE;
00289     *((NEAR uint8_t*)((uint16_t)(Address + (uint16_t)1 ))) = FLASH_SET_BYTE;
00290   }
00291   FLASH_WaitForLastOperation(FLASH_MEMTYPE_PROG);
00292
00293   /* Disable write access to option bytes */
00294   FLASH->CR2 &= (uint8_t)(~FLASH_CR2_OPT);
00295   FLASH->NCR2 |= FLASH_NCR2_NOPT;
00296 }
00297
00298 /**
00299   * @brief  Reads one option byte
00300   * @param  Address  option byte address to read.
00301   * @retval Option byte read value + its complement
00302   */
00303 uint16_t FLASH_ReadOptionByte(uint16_t Address)
00304 {
00305   uint8_t value_optbyte, value_optbyte_complement = 0;
00306   uint16_t res_value = 0;
00307
00308   /* Check parameter */
00309   assert_param(IS_OPTION_BYTE_ADDRESS_OK(Address));
00310
00311   value_optbyte = *((NEAR uint8_t*)Address); /* Read option byte */
00312   value_optbyte_complement = *(((NEAR uint8_t*)Address) + 1); /* Read option byte complement */
00313
00314   /* Read-out protection option byte */
00315   if(Address == 0x4800)
00316   {
00317     res_value =  value_optbyte;
00318   }
00319   else
00320   {
00321     if(value_optbyte == (uint8_t)(~value_optbyte_complement))
00322     {
00323       res_value = (uint16_t)((uint16_t)value_optbyte << 8);
00324       res_value = res_value | (uint16_t)value_optbyte_complement;
00325     }
00326     else
00327     {
00328       res_value = FLASH_OPTIONBYTE_ERROR;
00329     }
00330   }
00331   return(res_value);
00332 }
00333
00334 /**
00335   * @brief  Select the Flash behaviour in low power mode
00336   * @param  FLASH_LPMode Low power mode selection
00337   *         This parameter can be any of the @ref FLASH_LPMode_TypeDef values.
00338   * @retval None
00339   */
00340 void FLASH_SetLowPowerMode(FLASH_LPMode_TypeDef FLASH_LPMode)
00341 {
00342   /* Check parameter */
00343   assert_param(IS_FLASH_LOW_POWER_MODE_OK(FLASH_LPMode));
00344
00345   /* Clears the two bits */
00346   FLASH->CR1 &= (uint8_t)(~(FLASH_CR1_HALT | FLASH_CR1_AHALT));
00347
00348   /* Sets the new mode */
00349   FLASH->CR1 |= (uint8_t)FLASH_LPMode;
00350 }
00351
00352 /**
00353   * @brief  Sets the fixed programming time
00354   * @param  FLASH_ProgTime Indicates the programming time to be fixed
00355   *         This parameter can be any of the @ref FLASH_ProgramTime_TypeDef values.
00356   * @retval None
00357   */
00358 void FLASH_SetProgrammingTime(FLASH_ProgramTime_TypeDef FLASH_ProgTime)
00359 {
00360   /* Check parameter */
00361   assert_param(IS_FLASH_PROGRAM_TIME_OK(FLASH_ProgTime));
00362
00363   FLASH->CR1 &= (uint8_t)(~FLASH_CR1_FIX);
00364   FLASH->CR1 |= (uint8_t)FLASH_ProgTime;
00365 }
00366
00367 /**
00368   * @brief  Returns the Flash behaviour type in low power mode
00369   * @param  None
00370   * @retval FLASH_LPMode_TypeDef Flash behaviour type in low power mode
00371   */
00372 FLASH_LPMode_TypeDef FLASH_GetLowPowerMode(void)
00373 {
00374   return((FLASH_LPMode_TypeDef)(FLASH->CR1 & (uint8_t)(FLASH_CR1_HALT | FLASH_CR1_AHALT)));
00375 }
00376
00377 /**
00378   * @brief  Returns the fixed programming time
00379   * @param  None
00380   * @retval FLASH_ProgramTime_TypeDef Fixed programming time value
00381   */
00382 FLASH_ProgramTime_TypeDef FLASH_GetProgrammingTime(void)
00383 {
00384   return((FLASH_ProgramTime_TypeDef)(FLASH->CR1 & FLASH_CR1_FIX));
00385 }
00386
00387 /**
00388   * @brief  Returns the Boot memory size in bytes
00389   * @param  None
00390   * @retval Boot memory size in bytes
00391   */
00392 uint32_t FLASH_GetBootSize(void)
00393 {
00394   uint32_t temp = 0;
00395
00396   /* Calculates the number of bytes */
00397   temp = (uint32_t)((uint32_t)FLASH->FPR * (uint32_t)512);
00398
00399   /* Correction because size of 127.5 kb doesn't exist */
00400   if(FLASH->FPR == 0xFF)
00401   {
00402     temp += 512;
00403   }
00404
00405   /* Return value */
00406   return(temp);
00407 }
00408
00409 /**
00410   * @brief  Checks whether the specified SPI flag is set or not.
00411   * @param  FLASH_FLAG : Specifies the flag to check.
00412   *         This parameter can be any of the @ref FLASH_Flag_TypeDef enumeration.
00413   * @retval FlagStatus : Indicates the state of FLASH_FLAG.
00414   *         This parameter can be any of the @ref FlagStatus enumeration.
00415   * @note   This function can clear the EOP, WR_PG_DIS flags in the IAPSR register.
00416   */
00417 FlagStatus FLASH_GetFlagStatus(FLASH_Flag_TypeDef FLASH_FLAG)
00418 {
00419   FlagStatus status = RESET;
00420   /* Check parameters */
00421   assert_param(IS_FLASH_FLAGS_OK(FLASH_FLAG));
00422
00423   /* Check the status of the specified FLASH flag */
00424   if((FLASH->IAPSR & (uint8_t)FLASH_FLAG) != (uint8_t)RESET)
00425   {
00426     status = SET; /* FLASH_FLAG is set */
00427   }
00428   else
00429   {
00430     status = RESET; /* FLASH_FLAG is reset*/
00431   }
00432
00433   /* Return the FLASH_FLAG status */
00434   return status;
00435 }
00436
00437 /**
00438 @code
00439  All the functions defined below must be executed from RAM exclusively, except
00440  for the FLASH_WaitForLastOperation function which can be executed from Flash.
00441
00442  Steps of the execution from RAM differs from one toolchain to another:
00443  - For Cosmic Compiler:
00444     1- Define a segment FLASH_CODE by the mean of " #pragma section (FLASH_CODE)".
00445     This segment is defined in the stm8s_flash.c file.
00446   2- Uncomment the "#define RAM_EXECUTION  (1)" line in the stm8s.h file,
00447     or define it in Cosmic compiler preprocessor to enable the FLASH_CODE segment
00448    definition.
00449   3- In STVD Select Project\Settings\Linker\Category "input" and in the RAM section
00450     add the FLASH_CODE segment with "-ic" options.
00451   4- In main.c file call the _fctcpy() function with first segment character as
00452     parameter "_fctcpy('F');" to load the declared moveable code segment
00453     (FLASH_CODE) in RAM before execution.
00454   5- By default the _fctcpy function is packaged in the Cosmic machine library,
00455     so the function prototype "int _fctcopy(char name);" must be added in main.c
00456     file.
00457
00458   - For Raisonance Compiler
00459    1- Use the inram keyword in the function declaration to specify that it can be
00460     executed from RAM.
00461     This is done within the stm8s_flash.c file, and it's conditioned by
00462     RAM_EXECUTION definition.
00463    2- Uncomment the "#define RAM_EXECUTION  (1)" line in the stm8s.h file, or
00464    define it in Raisonance compiler preprocessor to enable the access for the
00465    inram functions.
00466    3- An inram function code is copied from Flash to RAM by the C startup code.
00467    In some applications, the RAM area where the code was initially stored may be
00468    erased or corrupted, so it may be desirable to perform the copy again.
00469    Depending on the application memory model, the memcpy() or fmemcpy() functions
00470    should be used to perform the copy.
00471       • In case your project uses the SMALL memory model (code smaller than 64K),
00472        memcpy()function is recommended to perform the copy
00473       • In case your project uses the LARGE memory model, functions can be
00474       everywhere in the 24-bits address space (not limited to the first 64KB of
00475       code), In this case, the use of memcpy() function will not be appropriate,
00476       you need to use the specific fmemcpy() function (which copies objects with
00477       24-bit addresses).
00478       - The linker automatically defines 2 symbols for each inram function:
00479            • __address__functionname is a symbol that holds the Flash address
00480            where the given function code is stored.
00481            • __size__functionname is a symbol that holds the function size in bytes.
00482      And we already have the function address (which is itself a pointer)
00483   4- In main.c file these two steps should be performed for each inram function:
00484      • Import the "__address__functionname" and "__size__functionname" symbols
00485        as global variables:
00486          extern int __address__functionname; // Symbol holding the flash address
00487          extern int __size__functionname;    // Symbol holding the function size
00488      • In case of SMALL memory model use, Call the memcpy() function to copy the
00489       inram function to the RAM destination address:
00490                 memcpy(functionname, // RAM destination address
00491                       (void*)&__address__functionname, // Flash source address
00492                       (int)&__size__functionname); // Code size of the function
00493      • In case of LARGE memory model use, call the fmemcpy() function to copy
00494      the inram function to the RAM destination address:
00495                  memcpy(functionname, // RAM destination address
00496                       (void @far*)&__address__functionname, // Flash source address
00497                       (int)&__size__functionname); // Code size of the function
00498
00499  - For IAR Compiler:
00500     1- Use the __ramfunc keyword in the function declaration to specify that it
00501     can be executed from RAM.
00502     This is done within the stm8s_flash.c file, and it's conditioned by
00503     RAM_EXECUTION definition.
00504     2- Uncomment the "#define RAM_EXECUTION  (1)" line in the stm8s.h file, or
00505    define it in IAR compiler preprocessor to enable the access for the
00506    __ramfunc functions.
00507
00508  - Note:
00509     1- Ignore the IAR compiler warnings, these warnings don't impact the FLASH Program/Erase
00510     operations.
00511     The code performing the Flash Program/erase must be executed from RAM; the variables
00512     initializations don't necessary require the execution from RAM, only CR2/NCR2 registers
00513     configuration and data programing must be executed from RAM.
00514     2- These warnings depends on IAR compiler: as the code generation is made using many
00515     runtime library functions to keep code size to a minimum.
00516     3- It is recommended to use High Speed Optimization with IAR (-Ohs), in order
00517     to reduce the runtime library calls in the generated code.
00518
00519
00520
00521  The FLASH examples given within the STM8S_StdPeriph_Lib package, details all
00522  the steps described above.
00523
00524 @endcode
00525 */
00526
00527 /**
00528   * @brief
00529   *******************************************************************************
00530   *                         Execution from RAM enable
00531   *******************************************************************************
00532   *
00533   * To enable execution from RAM you can either uncomment the following define
00534   * in the stm8s.h file or define it in your toolchain compiler preprocessor
00535   * - #define RAM_EXECUTION  (1)
00536   */
00537
00538 #if defined (_COSMIC_) && defined (RAM_EXECUTION)
00539  #pragma section (FLASH_CODE)
00540 #endif  /* _COSMIC_ && RAM_EXECUTION */
00541 /**
00542   * @brief  Wait for a Flash operation to complete.
00543   * @note   The call and execution of this function must be done from RAM in case
00544   *         of Block operation.
00545   * @param  FLASH_MemType : Memory type
00546   *         This parameter can be a value of @ref FLASH_MemType_TypeDef
00547   * @retval FLASH status
00548   */
00549 IN_RAM(FLASH_Status_TypeDef FLASH_WaitForLastOperation(FLASH_MemType_TypeDef FLASH_MemType))
00550 {
00551   uint8_t flagstatus = 0x00;
00552   uint16_t timeout = OPERATION_TIMEOUT;
00553
00554   /* Wait until operation completion or write protection page occurred */
00555 #if defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8S105) || \
00556     defined (STM8S005) || defined(STM8AF52Ax) || defined(STM8AF62Ax) || defined(STM8AF626x)
00557     if(FLASH_MemType == FLASH_MEMTYPE_PROG)
00558     {
00559       while((flagstatus == 0x00) && (timeout != 0x00))
00560       {
00561         flagstatus = (uint8_t)(FLASH->IAPSR & (uint8_t)(FLASH_IAPSR_EOP |
00562                                                         FLASH_IAPSR_WR_PG_DIS));
00563         timeout--;
00564       }
00565     }
00566     else
00567     {
00568       while((flagstatus == 0x00) && (timeout != 0x00))
00569       {
00570         flagstatus = (uint8_t)(FLASH->IAPSR & (uint8_t)(FLASH_IAPSR_HVOFF |
00571                                                         FLASH_IAPSR_WR_PG_DIS));
00572         timeout--;
00573       }
00574     }
00575 #else /*STM8S103,STM8S001, STM8S903, STM8AF622x */
00576   while((flagstatus == 0x00) && (timeout != 0x00))
00577   {
00578     flagstatus = (uint8_t)(FLASH->IAPSR & (FLASH_IAPSR_EOP | FLASH_IAPSR_WR_PG_DIS));
00579     timeout--;
00580   }
00581 #endif /* STM8S208, STM8S207, STM8S105, STM8AF52Ax, STM8AF62Ax, STM8AF262x */
00582
00583   if(timeout == 0x00 )
00584   {
00585     flagstatus = FLASH_STATUS_TIMEOUT;
00586   }
00587
00588   return((FLASH_Status_TypeDef)flagstatus);
00589 }
00590
00591 /**
00592   * @brief  Erases a block in the program or data memory.
00593   * @note   This function should be executed from RAM.
00594   * @param  FLASH_MemType :  The type of memory to erase
00595   * @param  BlockNum : Indicates the block number to erase
00596   * @retval None.
00597   */
00598 IN_RAM(void FLASH_EraseBlock(uint16_t BlockNum, FLASH_MemType_TypeDef FLASH_MemType))
00599 {
00600   uint32_t startaddress = 0;
00601
00602 #if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \
00603     defined(STM8S001) || defined(STM8S903) || defined (STM8AF626x) || defined (STM8AF622x)
00604     uint32_t PointerAttr  *pwFlash;
00605 #elif defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined (STM8AF62Ax) || defined (STM8AF52Ax)
00606   uint8_t PointerAttr  *pwFlash;
00607 #endif
00608
00609   /* Check parameters */
00610   assert_param(IS_MEMORY_TYPE_OK(FLASH_MemType));
00611   if(FLASH_MemType == FLASH_MEMTYPE_PROG)
00612   {
00613     assert_param(IS_FLASH_PROG_BLOCK_NUMBER_OK(BlockNum));
00614     startaddress = FLASH_PROG_START_PHYSICAL_ADDRESS;
00615   }
00616   else
00617   {
00618     assert_param(IS_FLASH_DATA_BLOCK_NUMBER_OK(BlockNum));
00619     startaddress = FLASH_DATA_START_PHYSICAL_ADDRESS;
00620   }
00621
00622   /* Point to the first block address */
00623 #if defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined (STM8AF62Ax) || defined (STM8AF52Ax)
00624   pwFlash = (PointerAttr uint8_t *)(MemoryAddressCast)(startaddress + ((uint32_t)BlockNum * FLASH_BLOCK_SIZE));
00625 #elif defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \
00626       defined(STM8S001) || defined (STM8S903) || defined (STM8AF626x) || defined (STM8AF622x)
00627     pwFlash = (PointerAttr uint32_t *)(MemoryAddressCast)(startaddress + ((uint32_t)BlockNum * FLASH_BLOCK_SIZE));
00628 #endif  /* STM8S208, STM8S207 */
00629
00630   /* Enable erase block mode */
00631   FLASH->CR2 |= FLASH_CR2_ERASE;
00632   FLASH->NCR2 &= (uint8_t)(~FLASH_NCR2_NERASE);
00633
00634 #if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) ||  \
00635     defined(STM8S001) || defined(STM8S903) || defined (STM8AF626x) || defined (STM8AF622x)
00636     *pwFlash = (uint32_t)0;
00637 #elif defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined (STM8AF62Ax) || \
00638   defined (STM8AF52Ax)
00639     *pwFlash = (uint8_t)0;
00640   *(pwFlash + 1) = (uint8_t)0;
00641   *(pwFlash + 2) = (uint8_t)0;
00642   *(pwFlash + 3) = (uint8_t)0;
00643 #endif
00644 }
00645
00646 /**
00647   * @brief  Programs a memory block
00648   * @note   This function should be executed from RAM.
00649   * @param  FLASH_MemType : The type of memory to program
00650   * @param  BlockNum : The block number
00651   * @param  FLASH_ProgMode : The programming mode.
00652   * @param  Buffer : Pointer to buffer containing source data.
00653   * @retval None.
00654   */
00655 IN_RAM(void FLASH_ProgramBlock(uint16_t BlockNum, FLASH_MemType_TypeDef FLASH_MemType,
00656                         FLASH_ProgramMode_TypeDef FLASH_ProgMode, uint8_t *Buffer))
00657 {
00658   uint16_t Count = 0;
00659   uint32_t startaddress = 0;
00660
00661   /* Check parameters */
00662   assert_param(IS_MEMORY_TYPE_OK(FLASH_MemType));
00663   assert_param(IS_FLASH_PROGRAM_MODE_OK(FLASH_ProgMode));
00664   if(FLASH_MemType == FLASH_MEMTYPE_PROG)
00665   {
00666     assert_param(IS_FLASH_PROG_BLOCK_NUMBER_OK(BlockNum));
00667     startaddress = FLASH_PROG_START_PHYSICAL_ADDRESS;
00668   }
00669   else
00670   {
00671     assert_param(IS_FLASH_DATA_BLOCK_NUMBER_OK(BlockNum));
00672     startaddress = FLASH_DATA_START_PHYSICAL_ADDRESS;
00673   }
00674
00675   /* Point to the first block address */
00676   startaddress = startaddress + ((uint32_t)BlockNum * FLASH_BLOCK_SIZE);
00677
00678   /* Selection of Standard or Fast programming mode */
00679   if(FLASH_ProgMode == FLASH_PROGRAMMODE_STANDARD)
00680   {
00681     /* Standard programming mode */ /*No need in standard mode */
00682     FLASH->CR2 |= FLASH_CR2_PRG;
00683     FLASH->NCR2 &= (uint8_t)(~FLASH_NCR2_NPRG);
00684   }
00685   else
00686   {
00687     /* Fast programming mode */
00688     FLASH->CR2 |= FLASH_CR2_FPRG;
00689     FLASH->NCR2 &= (uint8_t)(~FLASH_NCR2_NFPRG);
00690   }
00691
00692   /* Copy data bytes from RAM to FLASH memory */
00693   for(Count = 0; Count < FLASH_BLOCK_SIZE; Count++)
00694   {
00695     *((PointerAttr uint8_t*) (MemoryAddressCast)startaddress + Count) = ((uint8_t)(Buffer[Count]));
00696   }
00697 }
00698
00699 #if defined (_COSMIC_) && defined (RAM_EXECUTION)
00700  /* End of FLASH_CODE section */
00701  #pragma section ()
00702 #endif /* _COSMIC_ && RAM_EXECUTION */
00703
00704 /**
00705   * @}
00706   */
00707
00708 /**
00709   * @}
00710   */
00711
00712 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_flash.h Source File

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stm8s_flash.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_flash.h
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all functions prototype and macros for the FLASH peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Define to prevent recursive inclusion -------------------------------------*/
00029 #ifndef __STM8S_FLASH_H
00030 #define __STM8S_FLASH_H
00031
00032 /* Includes ------------------------------------------------------------------*/
00033 #include "stm8s.h"
00034
00035 /* Exported constants --------------------------------------------------------*/
00036
00037 /** @addtogroup FLASH_Exported_Constants
00038   * @{
00039   */
00040
00041 #define FLASH_PROG_START_PHYSICAL_ADDRESS ((uint32_t)0x008000) /*!< Program memory: start address */
00042
00043 #if defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined (STM8AF52Ax) || defined (STM8AF62Ax)
00044  #define FLASH_PROG_END_PHYSICAL_ADDRESS   ((uint32_t)0x027FFF) /*!< Program memory: end address */
00045  #define FLASH_PROG_BLOCKS_NUMBER          ((uint16_t)1024)     /*!< Program memory: total number of blocks */
00046  #define FLASH_DATA_START_PHYSICAL_ADDRESS ((uint32_t)0x004000) /*!< Data EEPROM memory: start address */
00047  #define FLASH_DATA_END_PHYSICAL_ADDRESS   ((uint32_t)0x0047FF) /*!< Data EEPROM memory: end address */
00048  #define FLASH_DATA_BLOCKS_NUMBER          ((uint16_t)16)       /*!< Data EEPROM memory: total number of blocks */
00049  #define FLASH_BLOCK_SIZE                  ((uint8_t)128)       /*!< Number of bytes in a block (common for Program and Data memories) */
00050 #endif /* STM8S208, STM8S207, STM8S007, STM8AF52Ax, STM8AF62Ax */
00051
00052 #if defined(STM8S105) || defined(STM8S005) || defined(STM8AF626x)
00053  #define FLASH_PROG_END_PHYSICAL_ADDRESS   ((uint32_t)0xFFFF)   /*!< Program memory: end address */
00054  #define FLASH_PROG_BLOCKS_NUMBER          ((uint16_t)256)      /*!< Program memory: total number of blocks */
00055  #define FLASH_DATA_START_PHYSICAL_ADDRESS ((uint32_t)0x004000) /*!< Data EEPROM memory: start address */
00056  #define FLASH_DATA_END_PHYSICAL_ADDRESS   ((uint32_t)0x0043FF) /*!< Data EEPROM memory: end address */
00057  #define FLASH_DATA_BLOCKS_NUMBER          ((uint16_t)8)        /*!< Data EEPROM memory: total number of blocks */
00058  #define FLASH_BLOCK_SIZE                  ((uint8_t)128)       /*!< Number of bytes in a block (common for Program and Data memories) */
00059 #endif /* STM8S105 or STM8AF626x */
00060
00061 #if defined(STM8S103) || defined(STM8S003) || defined(STM8S001) || defined(STM8S903) || defined(STM8AF622x)
00062  #define FLASH_PROG_END_PHYSICAL_ADDRESS   ((uint32_t)0x9FFF)   /*!< Program memory: end address */
00063  #define FLASH_PROG_BLOCKS_NUMBER          ((uint16_t)128)      /*!< Program memory: total number of blocks */
00064  #define FLASH_DATA_START_PHYSICAL_ADDRESS ((uint32_t)0x004000) /*!< Data EEPROM memory: start address */
00065  #define FLASH_DATA_END_PHYSICAL_ADDRESS   ((uint32_t)0x00427F) /*!< Data EEPROM memory: end address */
00066  #define FLASH_DATA_BLOCKS_NUMBER          ((uint16_t)10)       /*!< Data EEPROM memory: total number of blocks */
00067  #define FLASH_BLOCK_SIZE                  ((uint8_t)64)        /*!< Number of bytes in a block (common for Program and Data memories) */
00068 #endif /* STM8S103 or STM8S003 or STM8S001 or STM8S903 or STM8AF622x*/
00069
00070 #define FLASH_RASS_KEY1 ((uint8_t)0x56) /*!< First RASS key */
00071 #define FLASH_RASS_KEY2 ((uint8_t)0xAE) /*!< Second RASS key */
00072
00073 #define OPTION_BYTE_START_PHYSICAL_ADDRESS  ((uint16_t)0x4800)
00074 #define OPTION_BYTE_END_PHYSICAL_ADDRESS    ((uint16_t)0x487F)
00075 #define FLASH_OPTIONBYTE_ERROR              ((uint16_t)0x5555) /*!< Error code option byte
00076                                                                    (if value read is not equal to complement value read) */
00077 /**
00078   * @}
00079   */
00080
00081 /* Exported types ------------------------------------------------------------*/
00082
00083 /** @addtogroup FLASH_Exported_Types
00084   * @{
00085   */
00086
00087 /**
00088   * @brief  FLASH Memory types
00089   */
00090 typedef enum {
00091     FLASH_MEMTYPE_PROG      = (uint8_t)0xFD, /*!< Program memory */
00092     FLASH_MEMTYPE_DATA      = (uint8_t)0xF7  /*!< Data EEPROM memory */
00093 } FLASH_MemType_TypeDef;
00094
00095 /**
00096   * @brief  FLASH programming modes
00097   */
00098 typedef enum {
00099     FLASH_PROGRAMMODE_STANDARD = (uint8_t)0x00, /*!< Standard programming mode */
00100     FLASH_PROGRAMMODE_FAST     = (uint8_t)0x10  /*!< Fast programming mode */
00101 } FLASH_ProgramMode_TypeDef;
00102
00103 /**
00104   * @brief  FLASH fixed programming time
00105   */
00106 typedef enum {
00107     FLASH_PROGRAMTIME_STANDARD = (uint8_t)0x00, /*!< Standard programming time fixed at 1/2 tprog */
00108     FLASH_PROGRAMTIME_TPROG    = (uint8_t)0x01  /*!< Programming time fixed at tprog */
00109 } FLASH_ProgramTime_TypeDef;
00110
00111 /**
00112   * @brief  FLASH Low Power mode select
00113   */
00114 typedef enum {
00115     FLASH_LPMODE_POWERDOWN         = (uint8_t)0x04, /*!< HALT: Power-Down / ACTIVE-HALT: Power-Down */
00116     FLASH_LPMODE_STANDBY           = (uint8_t)0x08, /*!< HALT: Standby    / ACTIVE-HALT: Standby */
00117     FLASH_LPMODE_POWERDOWN_STANDBY = (uint8_t)0x00, /*!< HALT: Power-Down / ACTIVE-HALT: Standby */
00118     FLASH_LPMODE_STANDBY_POWERDOWN = (uint8_t)0x0C  /*!< HALT: Standby    / ACTIVE-HALT: Power-Down */
00119 }
00120 FLASH_LPMode_TypeDef;
00121
00122 /**
00123   * @brief  FLASH status of the last operation
00124   */
00125 typedef enum {
00126 #if defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8S105) || \
00127     defined(STM8S005) || defined (STM8AF52Ax) || defined (STM8AF62Ax) || defined(STM8AF626x)
00128                 FLASH_STATUS_END_HIGH_VOLTAGE           = (uint8_t)0x40, /*!< End of high voltage */
00129 #endif /* STM8S208, STM8S207, STM8S105, STM8AF62Ax, STM8AF52Ax, STM8AF626x */
00130                 FLASH_STATUS_SUCCESSFUL_OPERATION       = (uint8_t)0x04, /*!< End of operation flag */
00131                 FLASH_STATUS_TIMEOUT = (uint8_t)0x02, /*!< Time out error */
00132     FLASH_STATUS_WRITE_PROTECTION_ERROR     = (uint8_t)0x01 /*!< Write attempted to protected page */
00133 } FLASH_Status_TypeDef;
00134
00135 /**
00136   * @brief  FLASH flags definition
00137  * - Warning : FLAG value = mapping position register
00138   */
00139 typedef enum {
00140 #if defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8S105) || \
00141     defined(STM8S005) || defined (STM8AF52Ax) || defined (STM8AF62Ax) || defined(STM8AF626x)
00142     FLASH_FLAG_HVOFF     = (uint8_t)0x40,     /*!< End of high voltage flag */
00143 #endif /* STM8S208, STM8S207, STM8S105, STM8AF62Ax, STM8AF52Ax, STM8AF626x */
00144     FLASH_FLAG_DUL       = (uint8_t)0x08,     /*!< Data EEPROM unlocked flag */
00145     FLASH_FLAG_EOP       = (uint8_t)0x04,     /*!< End of programming (write or erase operation) flag */
00146     FLASH_FLAG_PUL       = (uint8_t)0x02,     /*!< Flash Program memory unlocked flag */
00147     FLASH_FLAG_WR_PG_DIS = (uint8_t)0x01      /*!< Write attempted to protected page flag */
00148 } FLASH_Flag_TypeDef;
00149
00150 /**
00151   * @}
00152   */
00153
00154 /* Private macros ------------------------------------------------------------*/
00155
00156 /**
00157   * @brief  Macros used by the assert function in order to check the different functions parameters.
00158   * @addtogroup FLASH_Private_Macros
00159   * @{
00160   */
00161
00162 /**
00163   * @brief  Macro used by the assert function in order to check the different sensitivity values for the flash program Address
00164   */
00165
00166 #define IS_FLASH_PROG_ADDRESS_OK(ADDRESS) (((ADDRESS) >= FLASH_PROG_START_PHYSICAL_ADDRESS) && \
00167     ((ADDRESS) <= FLASH_PROG_END_PHYSICAL_ADDRESS))
00168
00169 /**
00170   * @brief  Macro used by the assert function in order to check the different sensitivity values for the data eeprom Address
00171   */
00172
00173 #define IS_FLASH_DATA_ADDRESS_OK(ADDRESS) (((ADDRESS) >= FLASH_DATA_START_PHYSICAL_ADDRESS) && \
00174     ((ADDRESS) <= FLASH_DATA_END_PHYSICAL_ADDRESS))
00175
00176 /**
00177   * @brief  Macro used by the assert function in order to check the different sensitivity values for the data eeprom and flash program Address
00178   */
00179 #define IS_FLASH_ADDRESS_OK(ADDRESS)((((ADDRESS) >= FLASH_PROG_START_PHYSICAL_ADDRESS) && ((ADDRESS) <= FLASH_PROG_END_PHYSICAL_ADDRESS)) || \
00180                                      (((ADDRESS) >= FLASH_DATA_START_PHYSICAL_ADDRESS) && ((ADDRESS) <= FLASH_DATA_END_PHYSICAL_ADDRESS)))
00181
00182 /**
00183   * @brief  Macro used by the assert function in order to check the different sensitivity values for the flash program Block number
00184   */
00185 #define IS_FLASH_PROG_BLOCK_NUMBER_OK(BLOCKNUM) ((BLOCKNUM) < FLASH_PROG_BLOCKS_NUMBER)
00186
00187 /**
00188   * @brief  Macro used by the assert function in order to check the different sensitivity values for the data eeprom Block number
00189   */
00190 #define IS_FLASH_DATA_BLOCK_NUMBER_OK(BLOCKNUM) ((BLOCKNUM) < FLASH_DATA_BLOCKS_NUMBER)
00191
00192 /**
00193   * @brief  Macro used by the assert function in order to check the different sensitivity values for the flash memory type
00194   */
00195
00196 #define IS_MEMORY_TYPE_OK(MEMTYPE) (((MEMTYPE) == FLASH_MEMTYPE_PROG) || \
00197                                     ((MEMTYPE) == FLASH_MEMTYPE_DATA))
00198
00199 /**
00200   * @brief  Macro used by the assert function in order to check the different sensitivity values for the flash program mode
00201   */
00202
00203 #define IS_FLASH_PROGRAM_MODE_OK(MODE) (((MODE) == FLASH_PROGRAMMODE_STANDARD) || \
00204                                         ((MODE) == FLASH_PROGRAMMODE_FAST))
00205
00206 /**
00207   * @brief  Macro used by the assert function in order to check the program time mode
00208   */
00209
00210 #define IS_FLASH_PROGRAM_TIME_OK(TIME) (((TIME) == FLASH_PROGRAMTIME_STANDARD) || \
00211                                         ((TIME) == FLASH_PROGRAMTIME_TPROG))
00212
00213 /**
00214   * @brief  Macro used by the assert function in order to check the different
00215   *         sensitivity values for the low power mode
00216   */
00217
00218 #define IS_FLASH_LOW_POWER_MODE_OK(LPMODE) (((LPMODE) == FLASH_LPMODE_POWERDOWN) || \
00219     ((LPMODE) == FLASH_LPMODE_STANDBY) || \
00220     ((LPMODE) == FLASH_LPMODE_POWERDOWN_STANDBY) || \
00221     ((LPMODE) == FLASH_LPMODE_STANDBY_POWERDOWN))
00222
00223 /**
00224   * @brief  Macro used by the assert function in order to check the different
00225   *         sensitivity values for the option bytes Address
00226   */
00227 #define IS_OPTION_BYTE_ADDRESS_OK(ADDRESS) (((ADDRESS) >= OPTION_BYTE_START_PHYSICAL_ADDRESS) && \
00228     ((ADDRESS) <= OPTION_BYTE_END_PHYSICAL_ADDRESS))
00229
00230
00231 /**
00232   * @brief  Macro used by the assert function in order to check the different flags values
00233   */
00234 #if defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8S105) || \
00235     defined(STM8S005) || defined (STM8AF52Ax) || defined (STM8AF62Ax) || defined(STM8AF626x)
00236  #define IS_FLASH_FLAGS_OK(FLAG) (((FLAG) == FLASH_FLAG_HVOFF) || \
00237                                  ((FLAG) == FLASH_FLAG_DUL) || \
00238                                  ((FLAG) == FLASH_FLAG_EOP) || \
00239                                  ((FLAG) == FLASH_FLAG_PUL) || \
00240                                  ((FLAG) == FLASH_FLAG_WR_PG_DIS))
00241 #else /* STM8S103, STM8S001, STM8S903, STM8AF622x */
00242  #define IS_FLASH_FLAGS_OK(FLAG) (((FLAG) == FLASH_FLAG_DUL) || \
00243                                  ((FLAG) == FLASH_FLAG_EOP) || \
00244                                  ((FLAG) == FLASH_FLAG_PUL) || \
00245                                  ((FLAG) == FLASH_FLAG_WR_PG_DIS))
00246 #endif /* STM8S208, STM8S207, STM8S105, STM8AF62Ax, STM8AF52Ax, STM8AF626x */
00247 /**
00248   * @}
00249   */
00250
00251 /* Exported functions ------------------------------------------------------- */
00252
00253 /** @addtogroup FLASH_Exported_Functions
00254   * @{
00255   */
00256 void FLASH_Unlock(FLASH_MemType_TypeDef FLASH_MemType);
00257 void FLASH_Lock(FLASH_MemType_TypeDef FLASH_MemType);
00258 void FLASH_DeInit(void);
00259 void FLASH_ITConfig(FunctionalState NewState);
00260 void FLASH_EraseByte(uint32_t Address);
00261 void FLASH_ProgramByte(uint32_t Address, uint8_t Data);
00262 uint8_t FLASH_ReadByte(uint32_t Address);
00263 void FLASH_ProgramWord(uint32_t Address, uint32_t Data);
00264 uint16_t FLASH_ReadOptionByte(uint16_t Address);
00265 void FLASH_ProgramOptionByte(uint16_t Address, uint8_t Data);
00266 void FLASH_EraseOptionByte(uint16_t Address);
00267 void FLASH_SetLowPowerMode(FLASH_LPMode_TypeDef FLASH_LPMode);
00268 void FLASH_SetProgrammingTime(FLASH_ProgramTime_TypeDef FLASH_ProgTime);
00269 FLASH_LPMode_TypeDef FLASH_GetLowPowerMode(void);
00270 FLASH_ProgramTime_TypeDef FLASH_GetProgrammingTime(void);
00271 uint32_t FLASH_GetBootSize(void);
00272 FlagStatus FLASH_GetFlagStatus(FLASH_Flag_TypeDef FLASH_FLAG);
00273
00274 /**
00275 @code
00276  All the functions declared below must be executed from RAM exclusively, except
00277  for the FLASH_WaitForLastOperation function which can be executed from Flash.
00278
00279  Steps of the execution from RAM differs from one toolchain to another.
00280  for more details refer to stm8s_flash.c file.
00281
00282  To enable execution from RAM you can either uncomment the following define
00283  in the stm8s.h file or define it in your toolchain compiler preprocessor
00284  - #define RAM_EXECUTION  (1)
00285
00286 @endcode
00287 */
00288 IN_RAM(void FLASH_EraseBlock(uint16_t BlockNum, FLASH_MemType_TypeDef FLASH_MemType));
00289 IN_RAM(void FLASH_ProgramBlock(uint16_t BlockNum, FLASH_MemType_TypeDef FLASH_MemType,
00290                         FLASH_ProgramMode_TypeDef FLASH_ProgMode, uint8_t *Buffer));
00291 IN_RAM(FLASH_Status_TypeDef FLASH_WaitForLastOperation(FLASH_MemType_TypeDef FLASH_MemType));
00292
00293 /**
00294   * @}
00295   */
00296
00297 #endif /*__STM8S_FLASH_H */
00298
00299
00300 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_gpio.c Source File

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
stm8s_gpio.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_gpio.c
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all the functions for the GPIO peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm8s_gpio.h"
00030
00031 /** @addtogroup STM8S_StdPeriph_Driver
00032   * @{
00033   */
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 /* Private macro -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038 /* Private function prototypes -----------------------------------------------*/
00039 /* Private functions ---------------------------------------------------------*/
00040
00041 /* Public functions ----------------------------------------------------------*/
00042
00043 /**
00044   * @addtogroup GPIO_Public_Functions
00045   * @{
00046   */
00047
00048 /**
00049   * @brief  Deinitializes the GPIOx peripheral registers to their default reset values.
00050   * @param  GPIOx: Select the GPIO peripheral number (x = A to I).
00051   * @retval None
00052   */
00053 void GPIO_DeInit(GPIO_TypeDef* GPIOx)
00054 {
00055   GPIOx->ODR = GPIO_ODR_RESET_VALUE; /* Reset Output Data Register */
00056   GPIOx->DDR = GPIO_DDR_RESET_VALUE; /* Reset Data Direction Register */
00057   GPIOx->CR1 = GPIO_CR1_RESET_VALUE; /* Reset Control Register 1 */
00058   GPIOx->CR2 = GPIO_CR2_RESET_VALUE; /* Reset Control Register 2 */
00059 }
00060
00061 /**
00062   * @brief  Initializes the GPIOx according to the specified parameters.
00063   * @param  GPIOx : Select the GPIO peripheral number (x = A to I).
00064   * @param  GPIO_Pin : This parameter contains the pin number, it can be any value
00065   *         of the @ref GPIO_Pin_TypeDef enumeration.
00066   * @param  GPIO_Mode : This parameter can be a value of the
00067   *         @ref GPIO_Mode_TypeDef enumeration.
00068   * @retval None
00069   */
00070
00071 void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin, GPIO_Mode_TypeDef GPIO_Mode)
00072 {
00073   /*----------------------*/
00074   /* Check the parameters */
00075   /*----------------------*/
00076
00077   assert_param(IS_GPIO_MODE_OK(GPIO_Mode));
00078   assert_param(IS_GPIO_PIN_OK(GPIO_Pin));
00079
00080   /* Reset corresponding bit to GPIO_Pin in CR2 register */
00081   GPIOx->CR2 &= (uint8_t)(~(GPIO_Pin));
00082
00083   /*-----------------------------*/
00084   /* Input/Output mode selection */
00085   /*-----------------------------*/
00086
00087   if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x80) != (uint8_t)0x00) /* Output mode */
00088   {
00089     if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x10) != (uint8_t)0x00) /* High level */
00090     {
00091       GPIOx->ODR |= (uint8_t)GPIO_Pin;
00092     }
00093     else /* Low level */
00094     {
00095       GPIOx->ODR &= (uint8_t)(~(GPIO_Pin));
00096     }
00097     /* Set Output mode */
00098     GPIOx->DDR |= (uint8_t)GPIO_Pin;
00099   }
00100   else /* Input mode */
00101   {
00102     /* Set Input mode */
00103     GPIOx->DDR &= (uint8_t)(~(GPIO_Pin));
00104   }
00105
00106   /*------------------------------------------------------------------------*/
00107   /* Pull-Up/Float (Input) or Push-Pull/Open-Drain (Output) modes selection */
00108   /*------------------------------------------------------------------------*/
00109
00110   if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x40) != (uint8_t)0x00) /* Pull-Up or Push-Pull */
00111   {
00112     GPIOx->CR1 |= (uint8_t)GPIO_Pin;
00113   }
00114   else /* Float or Open-Drain */
00115   {
00116     GPIOx->CR1 &= (uint8_t)(~(GPIO_Pin));
00117   }
00118
00119   /*-----------------------------------------------------*/
00120   /* Interrupt (Input) or Slope (Output) modes selection */
00121   /*-----------------------------------------------------*/
00122
00123   if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x20) != (uint8_t)0x00) /* Interrupt or Slow slope */
00124   {
00125     GPIOx->CR2 |= (uint8_t)GPIO_Pin;
00126   }
00127   else /* No external interrupt or No slope control */
00128   {
00129     GPIOx->CR2 &= (uint8_t)(~(GPIO_Pin));
00130   }
00131 }
00132
00133 /**
00134   * @brief  Writes data to the specified GPIO data port.
00135   * @note   The port must be configured in output mode.
00136   * @param  GPIOx : Select the GPIO peripheral number (x = A to I).
00137   * @param  PortVal : Specifies the value to be written to the port output
00138   *         data register.
00139   * @retval None
00140   */
00141 void GPIO_Write(GPIO_TypeDef* GPIOx, uint8_t PortVal)
00142 {
00143   GPIOx->ODR = PortVal;
00144 }
00145
00146 /**
00147   * @brief  Writes high level to the specified GPIO pins.
00148   * @note   The port must be configured in output mode.
00149   * @param  GPIOx : Select the GPIO peripheral number (x = A to I).
00150   * @param  PortPins : Specifies the pins to be turned high to the port output.
00151   *         data register.
00152   * @retval None
00153   */
00154 void GPIO_WriteHigh(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef PortPins)
00155 {
00156   GPIOx->ODR |= (uint8_t)PortPins;
00157 }
00158
00159 /**
00160   * @brief  Writes low level to the specified GPIO pins.
00161   * @note   The port must be configured in output mode.
00162   * @param  GPIOx : Select the GPIO peripheral number (x = A to I).
00163   * @param  PortPins : Specifies the pins to be turned low to the port output.
00164   *         data register.
00165   * @retval None
00166   */
00167 void GPIO_WriteLow(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef PortPins)
00168 {
00169   GPIOx->ODR &= (uint8_t)(~PortPins);
00170 }
00171
00172 /**
00173   * @brief  Writes reverse level to the specified GPIO pins.
00174   * @note   The port must be configured in output mode.
00175   * @param  GPIOx : Select the GPIO peripheral number (x = A to I).
00176   * @param  PortPins : Specifies the pins to be reversed to the port output.
00177   *         data register.
00178   * @retval None
00179   */
00180 void GPIO_WriteReverse(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef PortPins)
00181 {
00182   GPIOx->ODR ^= (uint8_t)PortPins;
00183 }
00184
00185 /**
00186   * @brief  Reads the specified GPIO output data port.
00187   * @note   The port must be configured in input mode.
00188   * @param  GPIOx : Select the GPIO peripheral number (x = A to I).
00189   * @retval GPIO output data port value.
00190   */
00191 uint8_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
00192 {
00193   return ((uint8_t)GPIOx->ODR);
00194 }
00195
00196 /**
00197   * @brief  Reads the specified GPIO input data port.
00198   * @note   The port must be configured in input mode.
00199   * @param  GPIOx : Select the GPIO peripheral number (x = A to I).
00200   * @retval GPIO input data port value.
00201   */
00202 uint8_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
00203 {
00204   return ((uint8_t)GPIOx->IDR);
00205 }
00206
00207 /**
00208   * @brief  Reads the specified GPIO input data pin.
00209   * @param  GPIOx : Select the GPIO peripheral number (x = A to I).
00210   * @param  GPIO_Pin : Specifies the pin number.
00211   * @retval BitStatus : GPIO input pin status.
00212   */
00213 BitStatus GPIO_ReadInputPin(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
00214 {
00215   return ((BitStatus)(GPIOx->IDR & (uint8_t)GPIO_Pin));
00216 }
00217
00218 /**
00219   * @brief  Configures the external pull-up on GPIOx pins.
00220   * @param  GPIOx : Select the GPIO peripheral number (x = A to I).
00221   * @param  GPIO_Pin : Specifies the pin number
00222   * @param  NewState : The new state of the pull up pin.
00223   * @retval None
00224   */
00225 void GPIO_ExternalPullUpConfig(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin, FunctionalState NewState)
00226 {
00227   /* Check the parameters */
00228   assert_param(IS_GPIO_PIN_OK(GPIO_Pin));
00229   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00230
00231   if (NewState != DISABLE) /* External Pull-Up Set*/
00232   {
00233     GPIOx->CR1 |= (uint8_t)GPIO_Pin;
00234   } else /* External Pull-Up Reset*/
00235   {
00236     GPIOx->CR1 &= (uint8_t)(~(GPIO_Pin));
00237   }
00238 }
00239
00240 /**
00241   * @}
00242   */
00243
00244 /**
00245   * @}
00246   */
00247
00248
00249 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_gpio.h Source File

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
stm8s_gpio.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_gpio.h
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all functions prototype and macros for the GPIO peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Define to prevent recursive inclusion -------------------------------------*/
00029 #ifndef __STM8S_GPIO_H
00030 #define __STM8S_GPIO_H
00031
00032 /* Includes ------------------------------------------------------------------*/
00033 #include "stm8s.h"
00034
00035 /* Exported variables ------------------------------------------------------- */
00036 /* Exported types ------------------------------------------------------------*/
00037
00038 /** @addtogroup GPIO_Exported_Types
00039   * @{
00040   */
00041
00042 /**
00043   * @brief  GPIO modes
00044   *
00045   * Bits definitions:
00046   * - Bit 7: 0 = INPUT mode
00047   *          1 = OUTPUT mode
00048   *          1 = PULL-UP (input) or PUSH-PULL (output)
00049   * - Bit 5: 0 = No external interrupt (input) or No slope control (output)
00050   *          1 = External interrupt (input) or Slow control enabled (output)
00051   * - Bit 4: 0 = Low level (output)
00052   *          1 = High level (output push-pull) or HI-Z (output open-drain)
00053   */
00054 typedef enum
00055 {
00056   GPIO_MODE_IN_FL_NO_IT      = (uint8_t)0x00,  /*!< Input floating, no external interrupt */
00057   GPIO_MODE_IN_PU_NO_IT      = (uint8_t)0x40,  /*!< Input pull-up, no external interrupt */
00058   GPIO_MODE_IN_FL_IT         = (uint8_t)0x20,  /*!< Input floating, external interrupt */
00059   GPIO_MODE_IN_PU_IT         = (uint8_t)0x60,  /*!< Input pull-up, external interrupt */
00060   GPIO_MODE_OUT_OD_LOW_FAST  = (uint8_t)0xA0,  /*!< Output open-drain, low level, 10MHz */
00061   GPIO_MODE_OUT_PP_LOW_FAST  = (uint8_t)0xE0,  /*!< Output push-pull, low level, 10MHz */
00062   GPIO_MODE_OUT_OD_LOW_SLOW  = (uint8_t)0x80,  /*!< Output open-drain, low level, 2MHz */
00063   GPIO_MODE_OUT_PP_LOW_SLOW  = (uint8_t)0xC0,  /*!< Output push-pull, low level, 2MHz */
00064   GPIO_MODE_OUT_OD_HIZ_FAST  = (uint8_t)0xB0,  /*!< Output open-drain, high-impedance level,10MHz */
00065   GPIO_MODE_OUT_PP_HIGH_FAST = (uint8_t)0xF0,  /*!< Output push-pull, high level, 10MHz */
00066   GPIO_MODE_OUT_OD_HIZ_SLOW  = (uint8_t)0x90,  /*!< Output open-drain, high-impedance level, 2MHz */
00067   GPIO_MODE_OUT_PP_HIGH_SLOW = (uint8_t)0xD0   /*!< Output push-pull, high level, 2MHz */
00068 }GPIO_Mode_TypeDef;
00069
00070 /**
00071   * @brief  Definition of the GPIO pins. Used by the @ref GPIO_Init function in
00072   * order to select the pins to be initialized.
00073   */
00074
00075 typedef enum
00076 {
00077   GPIO_PIN_0    = ((uint8_t)0x01),  /*!< Pin 0 selected */
00078   GPIO_PIN_1    = ((uint8_t)0x02),  /*!< Pin 1 selected */
00079   GPIO_PIN_2    = ((uint8_t)0x04),  /*!< Pin 2 selected */
00080   GPIO_PIN_3    = ((uint8_t)0x08),   /*!< Pin 3 selected */
00081   GPIO_PIN_4    = ((uint8_t)0x10),  /*!< Pin 4 selected */
00082   GPIO_PIN_5    = ((uint8_t)0x20),  /*!< Pin 5 selected */
00083   GPIO_PIN_6    = ((uint8_t)0x40),  /*!< Pin 6 selected */
00084   GPIO_PIN_7    = ((uint8_t)0x80),  /*!< Pin 7 selected */
00085   GPIO_PIN_LNIB = ((uint8_t)0x0F),  /*!< Low nibble pins selected */
00086   GPIO_PIN_HNIB = ((uint8_t)0xF0),  /*!< High nibble pins selected */
00087   GPIO_PIN_ALL  = ((uint8_t)0xFF)   /*!< All pins selected */
00088 }GPIO_Pin_TypeDef;
00089
00090 /**
00091   * @}
00092   */
00093
00094 /* Exported constants --------------------------------------------------------*/
00095 /* Exported macros -----------------------------------------------------------*/
00096 /* Private macros ------------------------------------------------------------*/
00097
00098 /** @addtogroup GPIO_Private_Macros
00099   * @{
00100   */
00101
00102 /**
00103   * @brief  Macro used by the assert function to check the different functions parameters.
00104   */
00105
00106 /**
00107   * @brief  Macro used by the assert function in order to check the different
00108   * values of GPIOMode_TypeDef.
00109   */
00110 #define IS_GPIO_MODE_OK(MODE) \
00111   (((MODE) == GPIO_MODE_IN_FL_NO_IT)    || \
00112    ((MODE) == GPIO_MODE_IN_PU_NO_IT)    || \
00113    ((MODE) == GPIO_MODE_IN_FL_IT)       || \
00114    ((MODE) == GPIO_MODE_IN_PU_IT)       || \
00115    ((MODE) == GPIO_MODE_OUT_OD_LOW_FAST)  || \
00116    ((MODE) == GPIO_MODE_OUT_PP_LOW_FAST)  || \
00117    ((MODE) == GPIO_MODE_OUT_OD_LOW_SLOW)  || \
00118    ((MODE) == GPIO_MODE_OUT_PP_LOW_SLOW)  || \
00119    ((MODE) == GPIO_MODE_OUT_OD_HIZ_FAST)  || \
00120    ((MODE) == GPIO_MODE_OUT_PP_HIGH_FAST)  || \
00121    ((MODE) == GPIO_MODE_OUT_OD_HIZ_SLOW)  || \
00122    ((MODE) == GPIO_MODE_OUT_PP_HIGH_SLOW))
00123
00124 /**
00125   * @brief  Macro used by the assert function in order to check the different
00126   * values of GPIO_Pins.
00127   */
00128 #define IS_GPIO_PIN_OK(PIN)  ((PIN) != (uint8_t)0x00)
00129
00130 /**
00131   * @}
00132   */
00133
00134 /* Exported functions ------------------------------------------------------- */
00135 /** @addtogroup GPIO_Exported_Functions
00136   * @{
00137   */
00138
00139 void GPIO_DeInit(GPIO_TypeDef* GPIOx);
00140 void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin, GPIO_Mode_TypeDef GPIO_Mode);
00141 void GPIO_Write(GPIO_TypeDef* GPIOx, uint8_t PortVal);
00142 void GPIO_WriteHigh(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef PortPins);
00143 void GPIO_WriteLow(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef PortPins);
00144 void GPIO_WriteReverse(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef PortPins);
00145 uint8_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
00146 uint8_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
00147 BitStatus GPIO_ReadInputPin(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin);
00148 void GPIO_ExternalPullUpConfig(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin, FunctionalState NewState);
00149 /**
00150   * @}
00151   */
00152
00153 #endif /* __STM8L_GPIO_H */
00154
00155
00156 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_i2c.c Source File

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
stm8s_i2c.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_i2c.c
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all the functions for the I2C peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm8s_i2c.h"
00030
00031 /** @addtogroup STM8S_StdPeriph_Driver
00032   * @{
00033   */
00034 /* Private typedef -----------------------------------------------------------*/
00035
00036 /** @addtogroup I2C_Private_Defines
00037   * @{
00038   */
00039 /* I2C register mask */
00040 #define REGISTER_Mask               ((uint16_t)0x3000)
00041 #define REGISTER_SR1_Index          ((uint16_t)0x0100)
00042 #define REGISTER_SR2_Index          ((uint16_t)0x0200)
00043 /* I2C Interrupt Enable mask */
00044 #define ITEN_Mask                   ((uint16_t)0x0700)
00045 /* I2C FLAG mask */
00046 #define FLAG_Mask                   ((uint16_t)0x00FF)
00047 /**
00048   * @}
00049   */
00050
00051 /* Private macro -------------------------------------------------------------*/
00052 /* Private variables ---------------------------------------------------------*/
00053 /* Private function prototypes -----------------------------------------------*/
00054 /* Private functions ---------------------------------------------------------*/
00055
00056
00057 /**
00058   * @addtogroup I2C_Public_Functions
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  Deinitializes the I2C peripheral registers to their default reset values.
00064   * @param  None
00065   * @retval None
00066   */
00067 void I2C_DeInit(void)
00068 {
00069   I2C->CR1 = I2C_CR1_RESET_VALUE;
00070   I2C->CR2 = I2C_CR2_RESET_VALUE;
00071   I2C->FREQR = I2C_FREQR_RESET_VALUE;
00072   I2C->OARL = I2C_OARL_RESET_VALUE;
00073   I2C->OARH = I2C_OARH_RESET_VALUE;
00074   I2C->ITR = I2C_ITR_RESET_VALUE;
00075   I2C->CCRL = I2C_CCRL_RESET_VALUE;
00076   I2C->CCRH = I2C_CCRH_RESET_VALUE;
00077   I2C->TRISER = I2C_TRISER_RESET_VALUE;
00078 }
00079
00080 /**
00081   * @brief  Initializes the I2C according to the specified parameters in standard
00082   *         or fast mode.
00083   * @param  OutputClockFrequencyHz : Specifies the output clock frequency in Hz.
00084   * @param  OwnAddress : Specifies the own address.
00085   * @param  I2C_DutyCycle : Specifies the duty cycle to apply in fast mode.
00086   *         This parameter can be any of the  @ref I2C_DutyCycle_TypeDef enumeration.
00087   * @note   This parameter don't have impact when the OutputClockFrequency lower
00088   *         than 100KHz.
00089   * @param  Ack : Specifies the acknowledge mode to apply.
00090   *         This parameter can be any of the  @ref I2C_Ack_TypeDef enumeration.
00091   * @param  AddMode : Specifies the acknowledge address to apply.
00092   *         This parameter can be any of the  @ref I2C_AddMode_TypeDef enumeration.
00093   * @param  InputClockFrequencyMHz : Specifies the input clock frequency in MHz.
00094   * @retval None
00095   */
00096 void I2C_Init(uint32_t OutputClockFrequencyHz, uint16_t OwnAddress,
00097               I2C_DutyCycle_TypeDef I2C_DutyCycle, I2C_Ack_TypeDef Ack,
00098               I2C_AddMode_TypeDef AddMode, uint8_t InputClockFrequencyMHz )
00099 {
00100   uint16_t result = 0x0004;
00101   uint16_t tmpval = 0;
00102   uint8_t tmpccrh = 0;
00103
00104   /* Check the parameters */
00105   assert_param(IS_I2C_ACK_OK(Ack));
00106   assert_param(IS_I2C_ADDMODE_OK(AddMode));
00107   assert_param(IS_I2C_OWN_ADDRESS_OK(OwnAddress));
00108   assert_param(IS_I2C_DUTYCYCLE_OK(I2C_DutyCycle));
00109   assert_param(IS_I2C_INPUT_CLOCK_FREQ_OK(InputClockFrequencyMHz));
00110   assert_param(IS_I2C_OUTPUT_CLOCK_FREQ_OK(OutputClockFrequencyHz));
00111
00112
00113   /*------------------------- I2C FREQ Configuration ------------------------*/
00114   /* Clear frequency bits */
00115   I2C->FREQR &= (uint8_t)(~I2C_FREQR_FREQ);
00116   /* Write new value */
00117   I2C->FREQR |= InputClockFrequencyMHz;
00118
00119   /*--------------------------- I2C CCR Configuration ------------------------*/
00120   /* Disable I2C to configure TRISER */
00121   I2C->CR1 &= (uint8_t)(~I2C_CR1_PE);
00122
00123   /* Clear CCRH & CCRL */
00124   I2C->CCRH &= (uint8_t)(~(I2C_CCRH_FS | I2C_CCRH_DUTY | I2C_CCRH_CCR));
00125   I2C->CCRL &= (uint8_t)(~I2C_CCRL_CCR);
00126
00127   /* Detect Fast or Standard mode depending on the Output clock frequency selected */
00128   if (OutputClockFrequencyHz > I2C_MAX_STANDARD_FREQ) /* FAST MODE */
00129   {
00130     /* Set F/S bit for fast mode */
00131     tmpccrh = I2C_CCRH_FS;
00132
00133     if (I2C_DutyCycle == I2C_DUTYCYCLE_2)
00134     {
00135       /* Fast mode speed calculate: Tlow/Thigh = 2 */
00136       result = (uint16_t) ((InputClockFrequencyMHz * 1000000) / (OutputClockFrequencyHz * 3));
00137     }
00138     else /* I2C_DUTYCYCLE_16_9 */
00139     {
00140       /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
00141       result = (uint16_t) ((InputClockFrequencyMHz * 1000000) / (OutputClockFrequencyHz * 25));
00142       /* Set DUTY bit */
00143       tmpccrh |= I2C_CCRH_DUTY;
00144     }
00145
00146     /* Verify and correct CCR value if below minimum value */
00147     if (result < (uint16_t)0x01)
00148     {
00149       /* Set the minimum allowed value */
00150       result = (uint16_t)0x0001;
00151     }
00152
00153     /* Set Maximum Rise Time: 300ns max in Fast Mode
00154     = [300ns/(1/InputClockFrequencyMHz.10e6)]+1
00155     = [(InputClockFrequencyMHz * 3)/10]+1 */
00156     tmpval = ((InputClockFrequencyMHz * 3) / 10) + 1;
00157     I2C->TRISER = (uint8_t)tmpval;
00158
00159   }
00160   else /* STANDARD MODE */
00161   {
00162
00163     /* Calculate standard mode speed */
00164     result = (uint16_t)((InputClockFrequencyMHz * 1000000) / (OutputClockFrequencyHz << (uint8_t)1));
00165
00166     /* Verify and correct CCR value if below minimum value */
00167     if (result < (uint16_t)0x0004)
00168     {
00169       /* Set the minimum allowed value */
00170       result = (uint16_t)0x0004;
00171     }
00172
00173     /* Set Maximum Rise Time: 1000ns max in Standard Mode
00174     = [1000ns/(1/InputClockFrequencyMHz.10e6)]+1
00175     = InputClockFrequencyMHz+1 */
00176     I2C->TRISER = (uint8_t)(InputClockFrequencyMHz + (uint8_t)1);
00177
00178   }
00179
00180   /* Write CCR with new calculated value */
00181   I2C->CCRL = (uint8_t)result;
00182   I2C->CCRH = (uint8_t)((uint8_t)((uint8_t)(result >> 8) & I2C_CCRH_CCR) | tmpccrh);
00183
00184   /* Enable I2C */
00185   I2C->CR1 |= I2C_CR1_PE;
00186
00187   /* Configure I2C acknowledgement */
00188   I2C_AcknowledgeConfig(Ack);
00189
00190   /*--------------------------- I2C OAR Configuration ------------------------*/
00191   I2C->OARL = (uint8_t)(OwnAddress);
00192   I2C->OARH = (uint8_t)((uint8_t)(AddMode | I2C_OARH_ADDCONF) |
00193                    (uint8_t)((OwnAddress & (uint16_t)0x0300) >> (uint8_t)7));
00194 }
00195
00196 /**
00197   * @brief  Enables or disables the I2C peripheral.
00198   * @param  NewState : Indicate the new I2C peripheral state.
00199   *         This parameter can be any of the @ref FunctionalState enumeration.
00200   * @retval None
00201   */
00202 void I2C_Cmd(FunctionalState NewState)
00203 {
00204   /* Check function parameters */
00205   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00206
00207   if (NewState != DISABLE)
00208   {
00209     /* Enable I2C peripheral */
00210     I2C->CR1 |= I2C_CR1_PE;
00211   }
00212   else /* NewState == DISABLE */
00213   {
00214     /* Disable I2C peripheral */
00215     I2C->CR1 &= (uint8_t)(~I2C_CR1_PE);
00216   }
00217 }
00218
00219 /**
00220   * @brief  Enables or disables the I2C General Call feature.
00221   * @param  NewState : State of the General Call feature.
00222   *         This parameter can be any of the @ref FunctionalState enumeration.
00223   * @retval None
00224   */
00225 void I2C_GeneralCallCmd(FunctionalState NewState)
00226 {
00227   /* Check function parameters */
00228   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00229
00230   if (NewState != DISABLE)
00231   {
00232     /* Enable General Call */
00233     I2C->CR1 |= I2C_CR1_ENGC;
00234   }
00235   else /* NewState == DISABLE */
00236   {
00237     /* Disable General Call */
00238     I2C->CR1 &= (uint8_t)(~I2C_CR1_ENGC);
00239   }
00240 }
00241
00242 /**
00243   * @brief  Generates I2C communication START condition.
00244   * @note   CCR must be programmed, i.e. I2C_Init function must have been called
00245   *         with a valid I2C_ClockSpeed
00246   * @param  NewState : Enable or disable the start condition.
00247   *         This parameter can be any of the @ref FunctionalState enumeration.
00248   * @retval None
00249   */
00250 void I2C_GenerateSTART(FunctionalState NewState)
00251 {
00252   /* Check function parameters */
00253   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00254
00255   if (NewState != DISABLE)
00256   {
00257     /* Generate a START condition */
00258     I2C->CR2 |= I2C_CR2_START;
00259   }
00260   else /* NewState == DISABLE */
00261   {
00262     /* Disable the START condition generation */
00263     I2C->CR2 &= (uint8_t)(~I2C_CR2_START);
00264   }
00265 }
00266
00267 /**
00268   * @brief  Generates I2C communication STOP condition.
00269   * @param   NewState : Enable or disable the stop condition.
00270   *          This parameter can be any of the @ref FunctionalState enumeration.
00271   * @retval None
00272   */
00273 void I2C_GenerateSTOP(FunctionalState NewState)
00274 {
00275   /* Check function parameters */
00276   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00277
00278   if (NewState != DISABLE)
00279   {
00280     /* Generate a STOP condition */
00281     I2C->CR2 |= I2C_CR2_STOP;
00282   }
00283   else /* NewState == DISABLE */
00284   {
00285     /* Disable the STOP condition generation */
00286     I2C->CR2 &= (uint8_t)(~I2C_CR2_STOP);
00287   }
00288 }
00289
00290 /**
00291   * @brief  Enables or disables I2C software reset.
00292   * @param  NewState : Specifies the new state of the I2C software reset.
00293   *         This parameter can be any of the @ref FunctionalState enumeration.
00294   * @retval None
00295   */
00296 void I2C_SoftwareResetCmd(FunctionalState NewState)
00297 {
00298   /* Check function parameters */
00299   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00300
00301   if (NewState != DISABLE)
00302   {
00303     /* Peripheral under reset */
00304     I2C->CR2 |= I2C_CR2_SWRST;
00305   }
00306   else /* NewState == DISABLE */
00307   {
00308     /* Peripheral not under reset */
00309     I2C->CR2 &= (uint8_t)(~I2C_CR2_SWRST);
00310   }
00311 }
00312
00313 /**
00314   * @brief  Enables or disables the I2C clock stretching.
00315   * @param  NewState : Specifies the new state of the I2C Clock stretching.
00316   *         This parameter can be any of the @ref FunctionalState enumeration.
00317   * @retval None
00318   */
00319
00320 void I2C_StretchClockCmd(FunctionalState NewState)
00321 {
00322   /* Check function parameters */
00323   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00324
00325   if (NewState != DISABLE)
00326   {
00327     /* Clock Stretching Enable */
00328     I2C->CR1 &= (uint8_t)(~I2C_CR1_NOSTRETCH);
00329
00330   }
00331   else /* NewState == DISABLE */
00332   {
00333     /* Clock Stretching Disable (Slave mode) */
00334     I2C->CR1 |= I2C_CR1_NOSTRETCH;
00335   }
00336 }
00337
00338 /**
00339   * @brief  Enable or Disable the I2C acknowledge and position acknowledge feature.
00340   * @note   This function must be called before data reception start
00341   * @param  Ack : Specifies the acknowledge mode to apply.
00342   *         This parameter can be any of the  @ref I2C_Ack_TypeDef enumeration.
00343   * @retval None
00344   */
00345 void I2C_AcknowledgeConfig(I2C_Ack_TypeDef Ack)
00346 {
00347   /* Check function parameters */
00348   assert_param(IS_I2C_ACK_OK(Ack));
00349
00350   if (Ack == I2C_ACK_NONE)
00351   {
00352     /* Disable the acknowledgement */
00353     I2C->CR2 &= (uint8_t)(~I2C_CR2_ACK);
00354   }
00355   else
00356   {
00357     /* Enable the acknowledgement */
00358     I2C->CR2 |= I2C_CR2_ACK;
00359
00360     if (Ack == I2C_ACK_CURR)
00361     {
00362       /* Configure (N)ACK on current byte */
00363       I2C->CR2 &= (uint8_t)(~I2C_CR2_POS);
00364     }
00365     else
00366     {
00367       /* Configure (N)ACK on next byte */
00368       I2C->CR2 |= I2C_CR2_POS;
00369     }
00370   }
00371 }
00372
00373 /**
00374   * @brief  Enables or disables the specified I2C interrupt.
00375   * @param  I2C_IT : Name of the interrupt to enable or disable.
00376   *         This parameter can be any of the  @ref I2C_IT_TypeDef enumeration.
00377   * @param  NewState : State of the interrupt to apply.
00378   *         This parameter can be any of the @ref FunctionalState enumeration.
00379   * @retval None
00380   */
00381 void I2C_ITConfig(I2C_IT_TypeDef I2C_IT, FunctionalState NewState)
00382 {
00383   /* Check functions parameters */
00384   assert_param(IS_I2C_INTERRUPT_OK(I2C_IT));
00385   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00386
00387   if (NewState != DISABLE)
00388   {
00389     /* Enable the selected I2C interrupts */
00390     I2C->ITR |= (uint8_t)I2C_IT;
00391   }
00392   else /* NewState == DISABLE */
00393   {
00394     /* Disable the selected I2C interrupts */
00395     I2C->ITR &= (uint8_t)(~(uint8_t)I2C_IT);
00396   }
00397 }
00398
00399 /**
00400   * @brief  Selects the specified I2C fast mode duty cycle.
00401   * @param  I2C_DutyCycle : Specifies the duty cycle to apply.
00402   *         This parameter can be any of the @ref I2C_DutyCycle_TypeDef enumeration.
00403   * @retval None
00404   */
00405 void I2C_FastModeDutyCycleConfig(I2C_DutyCycle_TypeDef I2C_DutyCycle)
00406 {
00407   /* Check function parameters */
00408   assert_param(IS_I2C_DUTYCYCLE_OK(I2C_DutyCycle));
00409
00410   if (I2C_DutyCycle == I2C_DUTYCYCLE_16_9)
00411   {
00412     /* I2C fast mode Tlow/Thigh = 16/9 */
00413     I2C->CCRH |= I2C_CCRH_DUTY;
00414   }
00415   else /* I2C_DUTYCYCLE_2 */
00416   {
00417     /* I2C fast mode Tlow/Thigh = 2 */
00418     I2C->CCRH &= (uint8_t)(~I2C_CCRH_DUTY);
00419   }
00420 }
00421
00422 /**
00423   * @brief  Returns the most recent received data.
00424   * @param  None
00425   * @retval uint8_t : The value of the received byte data.
00426   */
00427 uint8_t I2C_ReceiveData(void)
00428 {
00429   /* Return the data present in the DR register */
00430   return ((uint8_t)I2C->DR);
00431 }
00432
00433 /**
00434   * @brief  Transmits the 7-bit address (to select the) slave device.
00435   * @param   Address : Specifies the slave address which will be transmitted.
00436   * @param   Direction : Specifies whether the I2C device will be a Transmitter or a Receiver.
00437   * This parameter can be any of the @ref I2C_Direction_TypeDef enumeration.
00438   * @retval None
00439   */
00440 void I2C_Send7bitAddress(uint8_t Address, I2C_Direction_TypeDef Direction)
00441 {
00442   /* Check function parameters */
00443   assert_param(IS_I2C_ADDRESS_OK(Address));
00444   assert_param(IS_I2C_DIRECTION_OK(Direction));
00445
00446   /* Clear bit0 (direction) just in case */
00447   Address &= (uint8_t)0xFE;
00448
00449   /* Send the Address + Direction */
00450   I2C->DR = (uint8_t)(Address | (uint8_t)Direction);
00451 }
00452
00453 /**
00454   * @brief  Send a byte by writing in the DR register.
00455   * @param   Data : Byte to be sent.
00456   * @retval None
00457   */
00458 void I2C_SendData(uint8_t Data)
00459 {
00460   /* Write in the DR register the data to be sent */
00461   I2C->DR = Data;
00462 }
00463
00464 /**
00465  * @brief
00466  ****************************************************************************************
00467  *
00468  *                         I2C State Monitoring Functions
00469  *
00470  ****************************************************************************************
00471  * This I2C driver provides three different ways for I2C state monitoring
00472  *  depending on the application requirements and constraints:
00473  *
00474  *
00475  * 1) Basic state monitoring:
00476  *    Using I2C_CheckEvent() function:
00477  *    It compares the status registers (SR1, SR2 and SR3) content to a given event
00478  *    (can be the combination of one or more flags).
00479  *    It returns SUCCESS if the current status includes the given flags
00480  *    and returns ERROR if one or more flags are missing in the current status.
00481  *    - When to use:
00482  *      - This function is suitable for most applications as well as for startup
00483  *      activity since the events are fully described in the product reference manual
00484  *      (RM0016).
00485  *      - It is also suitable for users who need to define their own events.
00486  *    - Limitations:
00487  *      - If an error occurs (ie. error flags are set besides to the monitored flags),
00488  *        the I2C_CheckEvent() function may return SUCCESS despite the communication
00489  *        hold or corrupted real state.
00490  *        In this case, it is advised to use error interrupts to monitor the error
00491  *        events and handle them in the interrupt IRQ handler.
00492  *
00493  *        @note
00494  *        For error management, it is advised to use the following functions:
00495  *          - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
00496  *          - I2C_IRQHandler() which is called when the I2C interrupts occur.
00497  *          - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the
00498  *           I2C_IRQHandler() function in order to determine which error occurred.
00499  *          - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
00500  *            and/or I2C_GenerateStop() in order to clear the error flag and
00501  *            source and return to correct communication status.
00502  *
00503  *
00504  *  2) Advanced state monitoring:
00505  *     Using the function I2C_GetLastEvent() which returns the image of both SR1
00506  *     & SR3 status registers in a single word (uint16_t) (Status Register 3 value
00507  *     is shifted left by 8 bits and concatenated to Status Register 1).
00508  *     - When to use:
00509  *       - This function is suitable for the same applications above but it allows to
00510  *         overcome the limitations of I2C_GetFlagStatus() function (see below).
00511  *         The returned value could be compared to events already defined in the
00512  *         library (stm8s_i2c.h) or to custom values defined by user.
00513  *       - This function is suitable when multiple flags are monitored at the same time.
00514  *       - At the opposite of I2C_CheckEvent() function, this function allows user to
00515  *         choose when an event is accepted (when all events flags are set and no
00516  *         other flags are set or just when the needed flags are set like
00517  *         I2C_CheckEvent() function).
00518  *     - Limitations:
00519  *       - User may need to define his own events.
00520  *       - Same remark concerning the error management is applicable for this
00521  *         function if user decides to check only regular communication flags (and
00522  *         ignores error flags).
00523  *
00524  *
00525  *  3) Flag-based state monitoring:
00526  *     Using the function I2C_GetFlagStatus() which simply returns the status of
00527  *     one single flag (ie. I2C_FLAG_RXNE ...).
00528  *     - When to use:
00529  *        - This function could be used for specific applications or in debug phase.
00530  *        - It is suitable when only one flag checking is needed (most I2C events
00531  *          are monitored through multiple flags).
00532  *     - Limitations:
00533  *        - When calling this function, the Status register is accessed. Some flags are
00534  *          cleared when the status register is accessed. So checking the status
00535  *          of one Flag, may clear other ones.
00536  *        - Function may need to be called twice or more in order to monitor one
00537  *          single event.
00538  *
00539  *  For detailed description of Events, please refer to section I2C_Events in
00540  *  stm8s_i2c.h file.
00541  *
00542  */
00543 /**
00544  *
00545  *  1) Basic state monitoring
00546  *******************************************************************************
00547  */
00548
00549 /**
00550   * @brief  Checks whether the last I2C Event is equal to the one passed
00551   *   as parameter.
00552   * @param  I2C_Event: specifies the event to be checked.
00553   *   This parameter can be one of the following values:
00554   *     @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED           : EV1
00555   *     @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED              : EV1
00556   *     @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED            : EV1
00557   *     @arg I2C_EVENT_SLAVE_BYTE_RECEIVED                         : EV2
00558   *     @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)    : EV2
00559   *     @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED                      : EV3
00560   *     @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3
00561   *     @arg I2C_EVENT_SLAVE_ACK_FAILURE                           : EV3_2
00562   *     @arg I2C_EVENT_SLAVE_STOP_DETECTED                         : EV4
00563   *     @arg I2C_EVENT_MASTER_MODE_SELECT                          : EV5
00564   *     @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED            : EV6
00565   *     @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED               : EV6
00566   *     @arg I2C_EVENT_MASTER_BYTE_RECEIVED                        : EV7
00567   *     @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING                    : EV8
00568   *     @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED                     : EV8_2
00569   *     @arg I2C_EVENT_MASTER_MODE_ADDRESS10                       : EV9
00570   *
00571   * @note: For detailed description of Events, please refer to section
00572   *    I2C_Events in stm8s_i2c.h file.
00573   *
00574   * @retval An ErrorStatus enumeration value:
00575   * - SUCCESS: Last event is equal to the I2C_EVENT
00576   * - ERROR: Last event is different from the I2C_EVENT
00577   */
00578 ErrorStatus I2C_CheckEvent(I2C_Event_TypeDef I2C_Event)
00579 {
00580   __IO uint16_t lastevent = 0x00;
00581   uint8_t flag1 = 0x00 ;
00582   uint8_t flag2 = 0x00;
00583   ErrorStatus status = ERROR;
00584
00585   /* Check the parameters */
00586   assert_param(IS_I2C_EVENT_OK(I2C_Event));
00587
00588   if (I2C_Event == I2C_EVENT_SLAVE_ACK_FAILURE)
00589   {
00590     lastevent = I2C->SR2 & I2C_SR2_AF;
00591   }
00592   else
00593   {
00594     flag1 = I2C->SR1;
00595     flag2 = I2C->SR3;
00596     lastevent = ((uint16_t)((uint16_t)flag2 << (uint16_t)8) | (uint16_t)flag1);
00597   }
00598   /* Check whether the last event is equal to I2C_EVENT */
00599   if (((uint16_t)lastevent & (uint16_t)I2C_Event) == (uint16_t)I2C_Event)
00600   {
00601     /* SUCCESS: last event is equal to I2C_EVENT */
00602     status = SUCCESS;
00603   }
00604   else
00605   {
00606     /* ERROR: last event is different from I2C_EVENT */
00607     status = ERROR;
00608   }
00609
00610   /* Return status */
00611   return status;
00612 }
00613
00614 /**
00615  *
00616  *  2) Advanced state monitoring
00617  *******************************************************************************
00618  */
00619 /**
00620   * @brief  Returns the last I2C Event.
00621   *
00622   * @note: For detailed description of Events, please refer to section
00623   *    I2C_Events in stm8s_i2c.h file.
00624   *
00625   * @retval The last event
00626   *   This parameter can be any of the  @ref I2C_Event_TypeDef enumeration.
00627   */
00628 I2C_Event_TypeDef I2C_GetLastEvent(void)
00629 {
00630   __IO uint16_t lastevent = 0;
00631   uint16_t flag1 = 0;
00632   uint16_t flag2 = 0;
00633
00634   if ((I2C->SR2 & I2C_SR2_AF) != 0x00)
00635   {
00636     lastevent = I2C_EVENT_SLAVE_ACK_FAILURE;
00637   }
00638   else
00639   {
00640     /* Read the I2C status register */
00641     flag1 = I2C->SR1;
00642     flag2 = I2C->SR3;
00643
00644     /* Get the last event value from I2C status register */
00645     lastevent = ((uint16_t)((uint16_t)flag2 << 8) | (uint16_t)flag1);
00646   }
00647   /* Return status */
00648   return (I2C_Event_TypeDef)lastevent;
00649 }
00650
00651 /**
00652  *
00653  *  3) Flag-based state monitoring
00654  *******************************************************************************
00655  */
00656 /**
00657   * @brief  Checks whether the specified I2C flag is set or not.
00658   * @param  I2C_Flag: specifies the flag to check.
00659   *   This parameter can be one of the following values:
00660   *     @arg I2C_FLAG_GENERALCALL: General call header flag (Slave mode)
00661   *     @arg I2C_FLAG_TRANSMITTERRECEIVER: Transmitter/Receiver flag
00662   *     @arg I2C_FLAG_BUSBUSY: Bus busy flag
00663   *     @arg I2C_FLAG_MASTERSLAVE: Master/Slave flag
00664   *     @arg I2C_FLAG_WAKEUPFROMHALT: Wake up from HALT flag
00665   *     @arg I2C_FLAG_OVERRUNUNDERRUN: Overrun/Underrun flag (Slave mode)
00666   *     @arg I2C_FLAG_ACKNOWLEDGEFAILURE: Acknowledge failure flag
00667   *     @arg I2C_FLAG_ARBITRATIONLOSS: Arbitration lost flag (Master mode)
00668   *     @arg I2C_FLAG_BUSERROR: Bus error flag
00669   *     @arg I2C_FLAG_TXEMPTY: Data register empty flag (Transmitter)
00670   *     @arg I2C_FLAG_RXNOTEMPTY: Data register not empty (Receiver) flag
00671   *     @arg I2C_FLAG_STOPDETECTION: Stop detection flag (Slave mode)
00672   *     @arg I2C_FLAG_HEADERSENT: 10-bit header sent flag (Master mode)
00673   *     @arg I2C_FLAG_TRANSFERFINISHED: Byte transfer finished flag
00674   *     @arg I2C_FLAG_ADDRESSSENTMATCHED: Address sent flag (Master mode) “ADSL”
00675   *   Address matched flag (Slave mode)”ENDAD”
00676   *     @arg I2C_FLAG_STARTDETECTION: Start bit flag (Master mode)
00677   * @retval The new state of I2C_FLAG (SET or RESET).
00678   */
00679 FlagStatus I2C_GetFlagStatus(I2C_Flag_TypeDef I2C_Flag)
00680 {
00681   uint8_t tempreg = 0;
00682   uint8_t regindex = 0;
00683   FlagStatus bitstatus = RESET;
00684
00685   /* Check the parameters */
00686   assert_param(IS_I2C_FLAG_OK(I2C_Flag));
00687
00688   /* Read flag register index */
00689   regindex = (uint8_t)((uint16_t)I2C_Flag >> 8);
00690   /* Check SRx index */
00691   switch (regindex)
00692   {
00693       /* Returns whether the status register to check is SR1 */
00694     case 0x01:
00695       tempreg = (uint8_t)I2C->SR1;
00696       break;
00697
00698       /* Returns whether the status register to check is SR2 */
00699     case 0x02:
00700       tempreg = (uint8_t)I2C->SR2;
00701       break;
00702
00703       /* Returns whether the status register to check is SR3 */
00704     case 0x03:
00705       tempreg = (uint8_t)I2C->SR3;
00706       break;
00707
00708     default:
00709       break;
00710   }
00711
00712   /* Check the status of the specified I2C flag */
00713   if ((tempreg & (uint8_t)I2C_Flag ) != 0)
00714   {
00715     /* Flag is set */
00716     bitstatus = SET;
00717   }
00718   else
00719   {
00720     /* Flag is reset */
00721     bitstatus = RESET;
00722   }
00723   /* Return the flag status */
00724   return bitstatus;
00725 }
00726
00727 /**
00728   * @brief  Clear flags
00729   * @param  I2C_FLAG : Specifies the flag to clear
00730   *   This parameter can be any combination of the following values:
00731   *                       - I2C_FLAG_WAKEUPFROMHALT: Wakeup from Halt
00732   *                       - I2C_FLAG_OVERRUNUNDERRUN: Overrun/Underrun flag (Slave mode)
00733   *                       - I2C_FLAG_ACKNOWLEDGEFAILURE: Acknowledge failure flag
00734   *                       - I2C_FLAG_ARBITRATIONLOSS: Arbitration lost flag (Master mode)
00735   *                       - I2C_FLAG_BUSERROR: Bus error flag.
00736   * @note Notes:
00737   *                       - STOPF (STOP detection) is cleared by software
00738   *                         sequence: a read operation to I2C_SR1 register
00739   *                         (I2C_GetFlagStatus()) followed by a write operation
00740   *                         to I2C_CR2 register.
00741   *                       - ADD10 (10-bit header sent) is cleared by software
00742   *                         sequence: a read operation to I2C_SR1
00743   *                         (I2C_GetFlagStatus()) followed by writing the
00744   *                         second byte of the address in DR register.
00745   *                       - BTF (Byte Transfer Finished) is cleared by software
00746   *                         sequence: a read operation to I2C_SR1 register
00747   *                         (I2C_GetFlagStatus()) followed by a read/write to
00748   *                         I2C_DR register (I2C_SendData()).
00749   *                       - ADDR (Address sent) is cleared by software sequence:
00750   *                         a read operation to I2C_SR1 register
00751   *                         (I2C_GetFlagStatus()) followed by a read operation to
00752   *                         I2C_SR3 register ((void)(I2C->SR3)).
00753   *                       - SB (Start Bit) is cleared software sequence: a read
00754   *                         operation to I2C_SR1 register (I2C_GetFlagStatus())
00755   *                         followed by a write operation to I2C_DR register
00756   *                         (I2C_SendData()).
00757   * @retval None
00758   */
00759 void I2C_ClearFlag(I2C_Flag_TypeDef I2C_FLAG)
00760 {
00761   uint16_t flagpos = 0;
00762   /* Check the parameters */
00763   assert_param(IS_I2C_CLEAR_FLAG_OK(I2C_FLAG));
00764
00765   /* Get the I2C flag position */
00766   flagpos = (uint16_t)I2C_FLAG & FLAG_Mask;
00767   /* Clear the selected I2C flag */
00768   I2C->SR2 = (uint8_t)((uint16_t)(~flagpos));
00769 }
00770
00771 /**
00772   * @brief  Checks whether the specified I2C interrupt has occurred or not.
00773   * @param  I2C_ITPendingBit: specifies the interrupt source to check.
00774   *            This parameter can be one of the following values:
00775   *               - I2C_ITPENDINGBIT_WAKEUPFROMHALT: Wakeup from Halt
00776   *               - I2C_ITPENDINGBIT_OVERRUNUNDERRUN: Overrun/Underrun flag (Slave mode)
00777   *               - I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE: Acknowledge failure flag
00778   *               - I2C_ITPENDINGBIT_ARBITRATIONLOSS: Arbitration lost flag (Master mode)
00779   *               - I2C_ITPENDINGBIT_BUSERROR: Bus error flag
00780   *               - I2C_ITPENDINGBIT_TXEMPTY: Data register empty flag (Transmitter)
00781   *               - I2C_ITPENDINGBIT_RXNOTEMPTY: Data register not empty (Receiver) flag
00782   *               - I2C_ITPENDINGBIT_STOPDETECTION: Stop detection flag (Slave mode)
00783   *               - I2C_ITPENDINGBIT_HEADERSENT: 10-bit header sent flag (Master mode)
00784   *               - I2C_ITPENDINGBIT_TRANSFERFINISHED: Byte transfer finished flag
00785   *               - I2C_ITPENDINGBIT_ADDRESSSENTMATCHED: Address sent flag (Master mode) “ADSL”
00786   *                              Address matched flag (Slave mode)“ENDAD”
00787   *               - I2C_ITPENDINGBIT_STARTDETECTION: Start bit flag (Master mode)
00788   * @retval The new state of I2C_ITPendingBit
00789   *   This parameter can be any of the @ref ITStatus enumeration.
00790   */
00791 ITStatus I2C_GetITStatus(I2C_ITPendingBit_TypeDef I2C_ITPendingBit)
00792 {
00793   ITStatus bitstatus = RESET;
00794   __IO uint8_t enablestatus = 0;
00795   uint16_t tempregister = 0;
00796
00797     /* Check the parameters */
00798     assert_param(IS_I2C_ITPENDINGBIT_OK(I2C_ITPendingBit));
00799
00800   tempregister = (uint8_t)( ((uint16_t)((uint16_t)I2C_ITPendingBit & ITEN_Mask)) >> 8);
00801
00802   /* Check if the interrupt source is enabled or not */
00803   enablestatus = (uint8_t)(I2C->ITR & ( uint8_t)tempregister);
00804
00805   if ((uint16_t)((uint16_t)I2C_ITPendingBit & REGISTER_Mask) == REGISTER_SR1_Index)
00806   {
00807     /* Check the status of the specified I2C flag */
00808     if (((I2C->SR1 & (uint8_t)I2C_ITPendingBit) != RESET) && enablestatus)
00809     {
00810       /* I2C_IT is set */
00811       bitstatus = SET;
00812     }
00813     else
00814     {
00815       /* I2C_IT is reset */
00816       bitstatus = RESET;
00817     }
00818   }
00819   else
00820   {
00821     /* Check the status of the specified I2C flag */
00822     if (((I2C->SR2 & (uint8_t)I2C_ITPendingBit) != RESET) && enablestatus)
00823     {
00824       /* I2C_IT is set */
00825       bitstatus = SET;
00826     }
00827     else
00828     {
00829       /* I2C_IT is reset */
00830       bitstatus = RESET;
00831     }
00832   }
00833   /* Return the I2C_IT status */
00834   return  bitstatus;
00835 }
00836
00837 /**
00838   * @brief  Clear IT pending bit
00839   * @param  I2C_ITPendingBit : specifies the interrupt pending bit to clear.
00840   *            This parameter can be any combination of the following values:
00841   *                 - I2C_ITPENDINGBIT_WAKEUPFROMHALT: Wakeup from Halt
00842   *                 - I2C_ITPENDINGBIT_OVERRUNUNDERRUN: Overrun/Underrun interrupt (Slave mode)
00843   *                 - I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE: Acknowledge failure interrupt
00844   *                 - I2C_ITPENDINGBIT_ARBITRATIONLOSS: Arbitration lost interrupt (Master mode)
00845   *                 - I2C_ITPENDINGBIT_BUSERROR: Bus error interrupt
00846   *
00847   *             Notes:
00848   *                  - STOPF (STOP detection) is cleared by software
00849   *                    sequence: a read operation to I2C_SR1 register
00850   *                    (I2C_GetITStatus()) followed by a write operation to
00851   *                    I2C_CR2 register (I2C_AcknowledgeConfig() to configure
00852   *                    the I2C peripheral Acknowledge).
00853   *                  - ADD10 (10-bit header sent) is cleared by software
00854   *                    sequence: a read operation to I2C_SR1
00855   *                    (I2C_GetITStatus()) followed by writing the second
00856   *                    byte of the address in I2C_DR register.
00857   *                  - BTF (Byte Transfer Finished) is cleared by software
00858   *                    sequence: a read operation to I2C_SR1 register
00859   *                    (I2C_GetITStatus()) followed by a read/write to
00860   *                    I2C_DR register (I2C_SendData()).
00861   *                  - ADDR (Address sent) is cleared by software sequence:
00862   *                    a read operation to I2C_SR1 register (I2C_GetITStatus())
00863   *                    followed by a read operation to I2C_SR3 register
00864   *                    ((void)(I2C->SR3)).
00865   *                  - SB (Start Bit) is cleared by software sequence: a
00866   *                    read operation to I2C_SR1 register (I2C_GetITStatus())
00867   *                    followed by a write operation to I2C_DR register
00868   *                    (I2C_SendData()).
00869   * @retval None
00870   */
00871 void I2C_ClearITPendingBit(I2C_ITPendingBit_TypeDef I2C_ITPendingBit)
00872 {
00873   uint16_t flagpos = 0;
00874
00875   /* Check the parameters */
00876   assert_param(IS_I2C_CLEAR_ITPENDINGBIT_OK(I2C_ITPendingBit));
00877
00878   /* Get the I2C flag position */
00879   flagpos = (uint16_t)I2C_ITPendingBit & FLAG_Mask;
00880
00881   /* Clear the selected I2C flag */
00882   I2C->SR2 = (uint8_t)((uint16_t)~flagpos);
00883 }
00884
00885 /**
00886   * @}
00887   */
00888
00889 /**
00890   * @}
00891   */
00892
00893 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_i2c.h Source File

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stm8s_i2c.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_i2c.h
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief  This file contains all functions prototype and macros for the I2C peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Define to prevent recursive inclusion -------------------------------------*/
00029 #ifndef __STM8S_I2C_H
00030 #define __STM8S_I2C_H
00031
00032 /* Includes ------------------------------------------------------------------*/
00033 #include "stm8s.h"
00034
00035 /* Exported types ------------------------------------------------------------*/
00036
00037 /** @addtogroup I2C_Exported_Types
00038   * @{
00039   */
00040
00041 /**
00042   * @brief  I2C duty cycle (fast mode only)
00043   */
00044 typedef enum
00045 {
00046   I2C_DUTYCYCLE_2    = (uint8_t)0x00,  /*!< Fast mode Tlow/THigh = 2 */
00047   I2C_DUTYCYCLE_16_9 = (uint8_t)0x40   /*!< Fast mode Tlow/Thigh = 16/9 */
00048 } I2C_DutyCycle_TypeDef;
00049
00050 /**
00051   * @brief  I2C Acknowledgement configuration
00052   */
00053 typedef enum
00054 {
00055   I2C_ACK_NONE = (uint8_t)0x00,  /*!< No acknowledge */
00056   I2C_ACK_CURR = (uint8_t)0x01,  /*!< Acknowledge on the current byte */
00057   I2C_ACK_NEXT = (uint8_t)0x02   /*!< Acknowledge on the next byte */
00058 } I2C_Ack_TypeDef;
00059
00060 /**
00061   * @brief  I2C Addressing Mode (slave mode only)
00062   */
00063 typedef enum
00064 {
00065   I2C_ADDMODE_7BIT  = (uint8_t)0x00,  /*!< 7-bit slave address (10-bit address not acknowledged) */
00066   I2C_ADDMODE_10BIT = (uint8_t)0x80   /*!< 10-bit slave address (7-bit address not acknowledged) */
00067 } I2C_AddMode_TypeDef;
00068
00069 /**
00070   * @brief  I2C Interrupt sources
00071   * Warning: the values correspond to the bit position in the ITR register
00072   */
00073 typedef enum
00074 {
00075     I2C_IT_ERR     = (uint8_t)0x01,     /*!< Error Interruption */
00076     I2C_IT_EVT     = (uint8_t)0x02,     /*!< Event Interruption */
00077     I2C_IT_BUF     = (uint8_t)0x04      /*!< Buffer Interruption */
00078 } I2C_IT_TypeDef;
00079
00080 /**
00081   * @brief  I2C transfer direction
00082   * Warning: the values correspond to the ADD0 bit position in the OARL register
00083   */
00084 typedef enum
00085 {
00086   I2C_DIRECTION_TX = (uint8_t)0x00,  /*!< Transmission direction */
00087   I2C_DIRECTION_RX = (uint8_t)0x01   /*!< Reception direction */
00088 } I2C_Direction_TypeDef;
00089
00090 /**
00091   * @brief  I2C Flags
00092   * @brief Elements values convention: 0xXXYY
00093   *  X = SRx registers index
00094   *      X = 1 : SR1
00095   *      X = 2 : SR2
00096   *      X = 3 : SR3
00097   *  Y = Flag mask in the register
00098   */
00099
00100 typedef enum
00101 {
00102   /* SR1 register flags */
00103   I2C_FLAG_TXEMPTY             = (uint16_t)0x0180,  /*!< Transmit Data Register Empty flag */
00104   I2C_FLAG_RXNOTEMPTY          = (uint16_t)0x0140,  /*!< Read Data Register Not Empty flag */
00105   I2C_FLAG_STOPDETECTION       = (uint16_t)0x0110,  /*!< Stop detected flag */
00106   I2C_FLAG_HEADERSENT          = (uint16_t)0x0108,  /*!< 10-bit Header sent flag */
00107   I2C_FLAG_TRANSFERFINISHED    = (uint16_t)0x0104,  /*!< Data Byte Transfer Finished flag */
00108   I2C_FLAG_ADDRESSSENTMATCHED  = (uint16_t)0x0102,  /*!< Address Sent/Matched (master/slave) flag */
00109   I2C_FLAG_STARTDETECTION      = (uint16_t)0x0101,  /*!< Start bit sent flag */
00110
00111   /* SR2 register flags */
00112   I2C_FLAG_WAKEUPFROMHALT      = (uint16_t)0x0220,  /*!< Wake Up From Halt Flag */
00113   I2C_FLAG_OVERRUNUNDERRUN     = (uint16_t)0x0208,  /*!< Overrun/Underrun flag */
00114   I2C_FLAG_ACKNOWLEDGEFAILURE  = (uint16_t)0x0204,  /*!< Acknowledge Failure Flag */
00115   I2C_FLAG_ARBITRATIONLOSS     = (uint16_t)0x0202,  /*!< Arbitration Loss Flag */
00116   I2C_FLAG_BUSERROR            = (uint16_t)0x0201,  /*!< Misplaced Start or Stop condition */
00117
00118   /* SR3 register flags */
00119   I2C_FLAG_GENERALCALL         = (uint16_t)0x0310,  /*!< General Call header received Flag */
00120   I2C_FLAG_TRANSMITTERRECEIVER = (uint16_t)0x0304,  /*!< Transmitter Receiver Flag */
00121   I2C_FLAG_BUSBUSY             = (uint16_t)0x0302,  /*!< Bus Busy Flag */
00122   I2C_FLAG_MASTERSLAVE         = (uint16_t)0x0301   /*!< Master Slave Flag */
00123 } I2C_Flag_TypeDef;
00124
00125 /**
00126   * @brief I2C Pending bits
00127   * Elements values convention: 0xXYZZ
00128   *  X = SRx registers index
00129   *      X = 1 : SR1
00130   *      X = 2 : SR2
00131   *  Y = Position of the corresponding Interrupt
00132   *  ZZ = flag mask in the dedicated register(X register)
00133   */
00134
00135 typedef enum
00136 {
00137     /* SR1 register flags */
00138     I2C_ITPENDINGBIT_TXEMPTY             = (uint16_t)0x1680,    /*!< Transmit Data Register Empty  */
00139     I2C_ITPENDINGBIT_RXNOTEMPTY          = (uint16_t)0x1640,    /*!< Read Data Register Not Empty  */
00140     I2C_ITPENDINGBIT_STOPDETECTION       = (uint16_t)0x1210,    /*!< Stop detected  */
00141     I2C_ITPENDINGBIT_HEADERSENT          = (uint16_t)0x1208,    /*!< 10-bit Header sent */
00142     I2C_ITPENDINGBIT_TRANSFERFINISHED    = (uint16_t)0x1204,    /*!< Data Byte Transfer Finished  */
00143     I2C_ITPENDINGBIT_ADDRESSSENTMATCHED  = (uint16_t)0x1202,    /*!< Address Sent/Matched (master/slave)  */
00144     I2C_ITPENDINGBIT_STARTDETECTION      = (uint16_t)0x1201,    /*!< Start bit sent  */
00145
00146     /* SR2 register flags */
00147     I2C_ITPENDINGBIT_WAKEUPFROMHALT      = (uint16_t)0x2220,    /*!< Wake Up From Halt  */
00148     I2C_ITPENDINGBIT_OVERRUNUNDERRUN     = (uint16_t)0x2108,    /*!< Overrun/Underrun  */
00149     I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE  = (uint16_t)0x2104,    /*!< Acknowledge Failure  */
00150     I2C_ITPENDINGBIT_ARBITRATIONLOSS     = (uint16_t)0x2102,    /*!< Arbitration Loss  */
00151     I2C_ITPENDINGBIT_BUSERROR            = (uint16_t)0x2101     /*!< Misplaced Start or Stop condition */
00152 } I2C_ITPendingBit_TypeDef;
00153
00154 /**
00155   * @brief I2C possible events
00156   * Values convention: 0xXXYY
00157   * XX = Event SR3 corresponding value
00158   * YY = Event SR1 corresponding value
00159   * @note if Event = EV3_2 the rule above does not apply
00160   * YY = Event SR2 corresponding value
00161   */
00162
00163 typedef enum
00164 {
00165   /*========================================
00166
00167                        I2C Master Events (Events grouped in order of communication)
00168                                                           ==========================================*/
00169   /**
00170     * @brief  Communication start
00171     *
00172     * After sending the START condition (I2C_GenerateSTART() function) the master
00173     * has to wait for this event. It means that the Start condition has been correctly
00174     * released on the I2C bus (the bus is free, no other devices is communicating).
00175     *
00176     */
00177   /* --EV5 */
00178   I2C_EVENT_MASTER_MODE_SELECT               = (uint16_t)0x0301,  /*!< BUSY, MSL and SB flag */
00179
00180   /**
00181     * @brief  Address Acknowledge
00182     *
00183     * After checking on EV5 (start condition correctly released on the bus), the
00184     * master sends the address of the slave(s) with which it will communicate
00185     * (I2C_Send7bitAddress() function, it also determines the direction of the communication:
00186     * Master transmitter or Receiver).
00187     * Then the master has to wait that a slave acknowledges his address.
00188     * If an acknowledge is sent on the bus, one of the following events will
00189     * be set:
00190     *
00191     *  1) In case of Master Receiver (7-bit addressing):
00192     *  the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED event is set.
00193     *
00194     *  2) In case of Master Transmitter (7-bit addressing):
00195     *  the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED is set
00196     *
00197     *  3) In case of 10-Bit addressing mode, the master (just after generating the START
00198     *  and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
00199     *  function).
00200     *  Then master should wait on EV9. It means that the 10-bit addressing
00201     *  header has been correctly sent on the bus.
00202     *  Then master should send the second part of the 10-bit address (LSB) using
00203     *  the function I2C_Send7bitAddress(). Then master should wait for event EV6.
00204     *
00205     */
00206   /* --EV6 */
00207   I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED = (uint16_t)0x0782,  /*!< BUSY, MSL, ADDR, TXE and TRA flags */
00208   I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED    = (uint16_t)0x0302,  /*!< BUSY, MSL and ADDR flags */
00209   /* --EV9 */
00210   I2C_EVENT_MASTER_MODE_ADDRESS10            = (uint16_t)0x0308,  /*!< BUSY, MSL and ADD10 flags */
00211
00212   /**
00213     * @brief Communication events
00214     *
00215     * If a communication is established (START condition generated and slave address
00216     * acknowledged) then the master has to check on one of the following events for
00217     * communication procedures:
00218     *
00219     * 1) Master Receiver mode: The master has to wait on the event EV7 then to read
00220     *    the data received from the slave (I2C_ReceiveData() function).
00221     *
00222     * 2) Master Transmitter mode: The master has to send data (I2C_SendData()
00223     *    function) then to wait on event EV8 or EV8_2.
00224     *    These two events are similar:
00225     *     - EV8 means that the data has been written in the data register and is
00226     *       being shifted out.
00227     *     - EV8_2 means that the data has been physically shifted out and output
00228     *       on the bus.
00229     *     In most cases, using EV8 is sufficient for the application.
00230     *     Using EV8_2 leads to a slower communication but ensures more reliable test.
00231     *     EV8_2 is also more suitable than EV8 for testing on the last data transmission
00232     *     (before Stop condition generation).
00233     *
00234     *  @note In case the user software does not guarantee that this event EV7 is
00235     *  managed before the current byte end of transfer, then user may check on EV7
00236     *  and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
00237     *  In this case the communication may be slower.
00238     *
00239     */
00240   /* Master RECEIVER mode -----------------------------*/
00241   /* --EV7 */
00242   I2C_EVENT_MASTER_BYTE_RECEIVED             = (uint16_t)0x0340,  /*!< BUSY, MSL and RXNE flags */
00243
00244   /* Master TRANSMITTER mode --------------------------*/
00245   /* --EV8 */
00246   I2C_EVENT_MASTER_BYTE_TRANSMITTING         = (uint16_t)0x0780,  /*!< TRA, BUSY, MSL, TXE flags */
00247   /* --EV8_2 */
00248
00249   I2C_EVENT_MASTER_BYTE_TRANSMITTED          = (uint16_t)0x0784,  /*!< EV8_2: TRA, BUSY, MSL, TXE and BTF flags */
00250
00251
00252   /*========================================
00253
00254                        I2C Slave Events (Events grouped in order of communication)
00255                                                           ==========================================*/
00256
00257   /**
00258     * @brief  Communication start events
00259     *
00260     * Wait on one of these events at the start of the communication. It means that
00261     * the I2C peripheral detected a Start condition on the bus (generated by master
00262     * device) followed by the peripheral address.
00263     * The peripheral generates an ACK condition on the bus (if the acknowledge
00264     * feature is enabled through function I2C_AcknowledgeConfig()) and the events
00265     * listed above are set :
00266     *
00267     * 1) In normal case (only one address managed by the slave), when the address
00268     *   sent by the master matches the own address of the peripheral (configured by
00269     *   I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
00270     *   (where XXX could be TRANSMITTER or RECEIVER).
00271     *
00272     * 2) In case the address sent by the master is General Call (address 0x00) and
00273     *   if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
00274     *   the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
00275     *
00276     */
00277
00278   /* --EV1  (all the events below are variants of EV1) */
00279   /* 1) Case of One Single Address managed by the slave */
00280   I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED    = (uint16_t)0x0202,  /*!< BUSY and ADDR flags */
00281   I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED = (uint16_t)0x0682,  /*!< TRA, BUSY, TXE and ADDR flags */
00282
00283   /* 2) Case of General Call enabled for the slave */
00284   I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED  = (uint16_t)0x1200,  /*!< EV2: GENCALL and BUSY flags */
00285
00286   /**
00287     * @brief  Communication events
00288     *
00289     * Wait on one of these events when EV1 has already been checked :
00290     *
00291     * - Slave RECEIVER mode:
00292     *     - EV2: When the application is expecting a data byte to be received.
00293     *     - EV4: When the application is expecting the end of the communication:
00294     *       master sends a stop condition and data transmission is stopped.
00295     *
00296     * - Slave Transmitter mode:
00297     *    - EV3: When a byte has been transmitted by the slave and the application
00298     *      is expecting the end of the byte transmission.
00299     *      The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and I2C_EVENT_SLAVE_BYTE_TRANSMITTING
00300     *      are similar. The second one can optionally be used when the user software
00301     *      doesn't guarantee the EV3 is managed before the current byte end of transfer.
00302     *    - EV3_2: When the master sends a NACK in order to tell slave that data transmission
00303     *      shall end (before sending the STOP condition).
00304     *      In this case slave has to stop sending data bytes and expect a Stop
00305     *      condition on the bus.
00306     *
00307     *  @note In case the  user software does not guarantee that the event EV2 is
00308     *  managed before the current byte end of transfer, then user may check on EV2
00309     *  and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
00310     *  In this case the communication may be slower.
00311     *
00312     */
00313   /* Slave RECEIVER mode --------------------------*/
00314   /* --EV2 */
00315   I2C_EVENT_SLAVE_BYTE_RECEIVED              = (uint16_t)0x0240,  /*!< BUSY and RXNE flags */
00316   /* --EV4  */
00317   I2C_EVENT_SLAVE_STOP_DETECTED              = (uint16_t)0x0010,  /*!< STOPF flag */
00318
00319   /* Slave TRANSMITTER mode -----------------------*/
00320   /* --EV3 */
00321   I2C_EVENT_SLAVE_BYTE_TRANSMITTED           = (uint16_t)0x0684,  /*!< TRA, BUSY, TXE and BTF flags */
00322   I2C_EVENT_SLAVE_BYTE_TRANSMITTING          = (uint16_t)0x0680,  /*!< TRA, BUSY and TXE flags */
00323   /* --EV3_2 */
00324   I2C_EVENT_SLAVE_ACK_FAILURE                = (uint16_t)0x0004  /*!< AF flag */
00325 } I2C_Event_TypeDef;
00326
00327 /**
00328   * @}
00329   */
00330
00331 /* Exported constants --------------------------------------------------------*/
00332 /** @addtogroup I2C_Exported_Constants
00333   * @{
00334   */
00335 #define I2C_MAX_STANDARD_FREQ ((uint32_t)100000)
00336 #define I2C_MAX_FAST_FREQ     ((uint32_t)400000)
00337 #if defined(STM8S208) || defined(STM8S207) || defined(STM8S007)
00338  #define I2C_MAX_INPUT_FREQ     ((uint8_t)24)
00339 #else
00340  #define I2C_MAX_INPUT_FREQ     ((uint8_t)16)
00341 #endif
00342
00343 /**
00344   * @}
00345   */
00346
00347 /* Exported macros -----------------------------------------------------------*/
00348 /* Private macros ------------------------------------------------------------*/
00349
00350 /** @addtogroup I2C_Private_Macros
00351   * @{
00352   */
00353
00354 /**
00355   * @brief  Macro used by the assert function to check the different functions parameters.
00356   */
00357
00358 /**
00359   * @brief   Macro used by the assert function to check the different I2C duty cycles.
00360   */
00361 #define IS_I2C_DUTYCYCLE_OK(DUTY) \
00362   (((DUTY) == I2C_DUTYCYCLE_2) || \
00363    ((DUTY) == I2C_DUTYCYCLE_16_9))
00364
00365 /**
00366   * @brief   Macro used by the assert function to check the different acknowledgement configuration
00367   */
00368 #define IS_I2C_ACK_OK(ACK) \
00369   (((ACK) == I2C_ACK_NONE) || \
00370    ((ACK) == I2C_ACK_CURR) || \
00371    ((ACK) == I2C_ACK_NEXT))
00372
00373 /**
00374   * @brief   Macro used by the assert function to check the different I2C addressing modes.
00375   */
00376 #define IS_I2C_ADDMODE_OK(ADDMODE) \
00377   (((ADDMODE) == I2C_ADDMODE_7BIT) || \
00378    ((ADDMODE) == I2C_ADDMODE_10BIT))
00379
00380 /**
00381   * @brief   Macro used by the assert function to check the different I2C interrupt types.
00382   */
00383 #define IS_I2C_INTERRUPT_OK(IT) \
00384   (((IT) == I2C_IT_ERR)     || \
00385    ((IT) == I2C_IT_EVT)     || \
00386    ((IT) == I2C_IT_BUF)     || \
00387    ((IT) == (I2C_IT_ERR | I2C_IT_EVT)) || \
00388    ((IT) == (I2C_IT_ERR | I2C_IT_BUF)) || \
00389    ((IT) == (I2C_IT_EVT | I2C_IT_BUF)) || \
00390    ((IT) == (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR)))
00391 /**
00392   * @brief   Macro used by the assert function to check the different I2C communcation direction.
00393   */
00394 #define IS_I2C_DIRECTION_OK(DIR) \
00395   (((DIR) == I2C_DIRECTION_TX) || \
00396    ((DIR) == I2C_DIRECTION_RX))
00397
00398 /**
00399   * @brief   Macro used by the assert function to check the different I2C flags.
00400   */
00401 #define IS_I2C_FLAG_OK(FLAG) \
00402   (((FLAG) == I2C_FLAG_TXEMPTY)         || \
00403    ((FLAG) == I2C_FLAG_RXNOTEMPTY)       || \
00404    ((FLAG) == I2C_FLAG_STOPDETECTION)      || \
00405    ((FLAG) == I2C_FLAG_HEADERSENT)       || \
00406    ((FLAG) == I2C_FLAG_TRANSFERFINISHED)   || \
00407    ((FLAG) == I2C_FLAG_ADDRESSSENTMATCHED)  || \
00408    ((FLAG) == I2C_FLAG_STARTDETECTION)    || \
00409    ((FLAG) == I2C_FLAG_WAKEUPFROMHALT)    || \
00410    ((FLAG) == I2C_FLAG_OVERRUNUNDERRUN)    || \
00411    ((FLAG) == I2C_FLAG_ACKNOWLEDGEFAILURE)  || \
00412    ((FLAG) == I2C_FLAG_ARBITRATIONLOSS)    || \
00413    ((FLAG) == I2C_FLAG_BUSERROR)       || \
00414    ((FLAG) == I2C_FLAG_GENERALCALL)      || \
00415    ((FLAG) == I2C_FLAG_TRANSMITTERRECEIVER) || \
00416    ((FLAG) == I2C_FLAG_BUSBUSY) || \
00417    ((FLAG) == I2C_FLAG_MASTERSLAVE))
00418 /**
00419   * @brief   Macro used by the assert function to check the I2C flags to clear.
00420   */
00421
00422 #define IS_I2C_CLEAR_FLAG_OK(FLAG) ((((uint16_t)(FLAG) & (uint16_t)0xFD00) == 0x00) \
00423                                      && ((uint16_t)(FLAG) != 0x00))
00424
00425 /**
00426   * @brief   Macro used by the assert function to check the different I2C possible pending bits.
00427   */
00428 #define IS_I2C_ITPENDINGBIT_OK(ITPENDINGBIT) \
00429    (((ITPENDINGBIT) == I2C_ITPENDINGBIT_TXEMPTY)                                        || \
00430     ((ITPENDINGBIT) == I2C_ITPENDINGBIT_RXNOTEMPTY)                             || \
00431     ((ITPENDINGBIT) == I2C_ITPENDINGBIT_STOPDETECTION)                  || \
00432     ((ITPENDINGBIT) == I2C_ITPENDINGBIT_HEADERSENT)                             || \
00433     ((ITPENDINGBIT) == I2C_ITPENDINGBIT_TRANSFERFINISHED)       || \
00434     ((ITPENDINGBIT) == I2C_ITPENDINGBIT_ADDRESSSENTMATCHED) || \
00435     ((ITPENDINGBIT) == I2C_ITPENDINGBIT_STARTDETECTION)                 || \
00436     ((ITPENDINGBIT) == I2C_ITPENDINGBIT_WAKEUPFROMHALT)                 || \
00437     ((ITPENDINGBIT) == I2C_ITPENDINGBIT_OVERRUNUNDERRUN)                || \
00438     ((ITPENDINGBIT) == I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE) || \
00439     ((ITPENDINGBIT) == I2C_ITPENDINGBIT_ARBITRATIONLOSS)                || \
00440     ((ITPENDINGBIT) == I2C_ITPENDINGBIT_BUSERROR))
00441
00442 /**
00443   * @brief  Macro used by the assert function to check the different I2C possible
00444   *   pending bits to clear by writing 0.
00445   */
00446 #define IS_I2C_CLEAR_ITPENDINGBIT_OK(ITPENDINGBIT) \
00447    (((ITPENDINGBIT) == I2C_ITPENDINGBIT_WAKEUPFROMHALT)     || \
00448     ((ITPENDINGBIT) == I2C_ITPENDINGBIT_OVERRUNUNDERRUN)    || \
00449     ((ITPENDINGBIT) == I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE) || \
00450     ((ITPENDINGBIT) == I2C_ITPENDINGBIT_ARBITRATIONLOSS)    || \
00451     ((ITPENDINGBIT) == I2C_ITPENDINGBIT_BUSERROR))
00452
00453 /**
00454   * @brief   Macro used by the assert function to check the different I2C possible events.
00455   */
00456 #define IS_I2C_EVENT_OK(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
00457                              ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
00458                              ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
00459                              ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
00460                              ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | (uint16_t)I2C_FLAG_GENERALCALL)) || \
00461                              ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
00462                              ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | (uint16_t)I2C_FLAG_GENERALCALL)) || \
00463                              ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE) || \
00464                              ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
00465                              ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
00466                              ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
00467                              ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
00468                              ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
00469                              ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
00470                              ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
00471                              ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10))
00472
00473 /**
00474   * @brief   Macro used by the assert function to check the different I2C possible own address.
00475   */
00476 #define IS_I2C_OWN_ADDRESS_OK(ADDRESS) \
00477   ((ADDRESS) <= (uint16_t)0x03FF)
00478
00479 /* The address must be even */
00480 #define IS_I2C_ADDRESS_OK(ADD) \
00481   (((ADD) & (uint8_t)0x01) == (uint8_t)0x00)
00482
00483 /**
00484   * @brief   Macro used by the assert function to check that I2C Input clock frequency must be between 1MHz and 50MHz.
00485   */
00486 #define IS_I2C_INPUT_CLOCK_FREQ_OK(FREQ) \
00487   (((FREQ) >= (uint8_t)1) && ((FREQ) <= I2C_MAX_INPUT_FREQ))
00488
00489
00490 /**
00491   * @brief   Macro used by the assert function to check that I2C Output clock frequency must be between 1Hz and 400kHz.
00492   */
00493 #define IS_I2C_OUTPUT_CLOCK_FREQ_OK(FREQ) \
00494   (((FREQ) >= (uint8_t)1) && ((FREQ) <= I2C_MAX_FAST_FREQ))
00495
00496 /**
00497   * @}
00498   */
00499
00500 /* Exported functions ------------------------------------------------------- */
00501 /** @addtogroup I2C_Exported_Functions
00502   * @{
00503   */
00504
00505 void I2C_DeInit(void);
00506 void I2C_Init(uint32_t OutputClockFrequencyHz, uint16_t OwnAddress,
00507               I2C_DutyCycle_TypeDef I2C_DutyCycle, I2C_Ack_TypeDef Ack,
00508               I2C_AddMode_TypeDef AddMode, uint8_t InputClockFrequencyMHz );
00509 void I2C_Cmd(FunctionalState NewState);
00510 void I2C_GeneralCallCmd(FunctionalState NewState);
00511 void I2C_GenerateSTART(FunctionalState NewState);
00512 void I2C_GenerateSTOP(FunctionalState NewState);
00513 void I2C_SoftwareResetCmd(FunctionalState NewState);
00514 void I2C_StretchClockCmd(FunctionalState NewState);
00515 void I2C_AcknowledgeConfig(I2C_Ack_TypeDef Ack);
00516 void I2C_FastModeDutyCycleConfig(I2C_DutyCycle_TypeDef I2C_DutyCycle);
00517 void I2C_ITConfig(I2C_IT_TypeDef I2C_IT, FunctionalState NewState);
00518 uint8_t I2C_ReceiveData(void);
00519 void I2C_Send7bitAddress(uint8_t Address, I2C_Direction_TypeDef Direction);
00520 void I2C_SendData(uint8_t Data);
00521 /**
00522  * @brief
00523  ****************************************************************************************
00524  *
00525  *                         I2C State Monitoring Functions
00526  *
00527  ****************************************************************************************
00528  * This I2C driver provides three different ways for I2C state monitoring
00529  *  depending on the application requirements and constraints:
00530  *
00531  *
00532  * 1) Basic state monitoring:
00533  *    Using I2C_CheckEvent() function:
00534  *    It compares the status registers (SR1, SR2 and SR3) content to a given event
00535  *    (can be the combination of one or more flags).
00536  *    It returns SUCCESS if the current status includes the given flags
00537  *    and returns ERROR if one or more flags are missing in the current status.
00538  *    - When to use:
00539  *      - This function is suitable for most applications as well as for startup
00540  *      activity since the events are fully described in the product reference manual
00541  *      (RM0016).
00542  *      - It is also suitable for users who need to define their own events.
00543  *    - Limitations:
00544  *      - If an error occurs (ie. error flags are set besides to the monitored flags),
00545  *        the I2C_CheckEvent() function may return SUCCESS despite the communication
00546  *        hold or corrupted real state.
00547  *        In this case, it is advised to use error interrupts to monitor the error
00548  *        events and handle them in the interrupt IRQ handler.
00549  *
00550  *        @note
00551  *        For error management, it is advised to use the following functions:
00552  *          - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
00553  *          - I2C_IRQHandler() which is called when the I2C interrupts occur.
00554  *          - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the
00555  *           I2Cx_IRQHandler() function in order to determine which error occurred.
00556  *          - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
00557  *            and/or I2C_GenerateStop() in order to clear the error flag and
00558  *            source and return to correct communication status.
00559  *
00560  *
00561  *  2) Advanced state monitoring:
00562  *     Using the function I2C_GetLastEvent() which returns the image of both SR1
00563  *     & SR3 status registers in a single word (uint16_t) (Status Register 3 value
00564  *     is shifted left by 8 bits and concatenated to Status Register 1).
00565  *     - When to use:
00566  *       - This function is suitable for the same applications above but it allows to
00567  *         overcome the limitations of I2C_GetFlagStatus() function (see below).
00568  *         The returned value could be compared to events already defined in the
00569  *         library (stm8s_i2c.h) or to custom values defined by user.
00570  *       - This function is suitable when multiple flags are monitored at the same time.
00571  *       - At the opposite of I2C_CheckEvent() function, this function allows user to
00572  *         choose when an event is accepted (when all events flags are set and no
00573  *         other flags are set or just when the needed flags are set like
00574  *         I2C_CheckEvent() function).
00575  *     - Limitations:
00576  *       - User may need to define his own events.
00577  *       - Same remark concerning the error management is applicable for this
00578  *         function if user decides to check only regular communication flags (and
00579  *         ignores error flags).
00580  *
00581  *
00582  *  3) Flag-based state monitoring:
00583  *     Using the function I2C_GetFlagStatus() which simply returns the status of
00584  *     one single flag (ie. I2C_FLAG_RXNE ...).
00585  *     - When to use:
00586  *        - This function could be used for specific applications or in debug phase.
00587  *        - It is suitable when only one flag checking is needed (most I2C events
00588  *          are monitored through multiple flags).
00589  *     - Limitations:
00590  *        - When calling this function, the Status register is accessed. Some flags are
00591  *          cleared when the status register is accessed. So checking the status
00592  *          of one Flag, may clear other ones.
00593  *        - Function may need to be called twice or more in order to monitor one
00594  *          single event.
00595  *
00596  */
00597
00598 /**
00599  *
00600  *  1) Basic state monitoring
00601  *******************************************************************************
00602  */
00603 ErrorStatus I2C_CheckEvent(I2C_Event_TypeDef I2C_Event);
00604 /**
00605  *
00606  *  2) Advanced state monitoring
00607  *******************************************************************************
00608  */
00609 I2C_Event_TypeDef I2C_GetLastEvent(void);
00610 /**
00611  *
00612  *  3) Flag-based state monitoring
00613  *******************************************************************************
00614  */
00615 FlagStatus I2C_GetFlagStatus(I2C_Flag_TypeDef I2C_Flag);
00616 /**
00617  *
00618  *******************************************************************************
00619  */
00620 void I2C_ClearFlag(I2C_Flag_TypeDef I2C_FLAG);
00621 ITStatus I2C_GetITStatus(I2C_ITPendingBit_TypeDef I2C_ITPendingBit);
00622 void I2C_ClearITPendingBit(I2C_ITPendingBit_TypeDef I2C_ITPendingBit);
00623
00624
00625 /**
00626   * @}
00627   */
00628
00629 #endif /* __STM8S_I2C_H */
00630
00631
00632 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_itc.c Source File

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stm8s_itc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_itc.c
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all the functions for the ITC peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm8s_itc.h"
00030
00031 /** @addtogroup STM8S_StdPeriph_Driver
00032   * @{
00033   */
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 /* Private macro -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038 /* Private function prototypes -----------------------------------------------*/
00039 /* Private functions ---------------------------------------------------------*/
00040
00041 /** @addtogroup ITC_Private_Functions
00042   * @{
00043   */
00044
00045 /**
00046   * @brief  Utility function used to read CC register.
00047   * @param  None
00048   * @retval CPU CC register value
00049   */
00050 uint8_t ITC_GetCPUCC(void)
00051 {
00052 #ifdef _COSMIC_
00053   _asm("push cc");
00054   _asm("pop a");
00055   return; /* Ignore compiler warning, the returned value is in A register */
00056 #elif defined _RAISONANCE_ /* _RAISONANCE_ */
00057   return _getCC_();
00058 #else /* _IAR_ */
00059   asm("push cc");
00060   asm("pop a"); /* Ignore compiler warning, the returned value is in A register */
00061 #endif /* _COSMIC_*/
00062 }
00063
00064
00065 /**
00066   * @}
00067   */
00068
00069 /* Public functions ----------------------------------------------------------*/
00070
00071 /** @addtogroup ITC_Public_Functions
00072   * @{
00073   */
00074
00075 /**
00076   * @brief  Deinitializes the ITC registers to their default reset value.
00077   * @param  None
00078   * @retval None
00079   */
00080 void ITC_DeInit(void)
00081 {
00082   ITC->ISPR1 = ITC_SPRX_RESET_VALUE;
00083   ITC->ISPR2 = ITC_SPRX_RESET_VALUE;
00084   ITC->ISPR3 = ITC_SPRX_RESET_VALUE;
00085   ITC->ISPR4 = ITC_SPRX_RESET_VALUE;
00086   ITC->ISPR5 = ITC_SPRX_RESET_VALUE;
00087   ITC->ISPR6 = ITC_SPRX_RESET_VALUE;
00088   ITC->ISPR7 = ITC_SPRX_RESET_VALUE;
00089   ITC->ISPR8 = ITC_SPRX_RESET_VALUE;
00090 }
00091
00092 /**
00093   * @brief  Gets the interrupt software priority bits (I1, I0) value from CPU CC register.
00094   * @param  None
00095   * @retval The interrupt software priority bits value.
00096   */
00097 uint8_t ITC_GetSoftIntStatus(void)
00098 {
00099   return (uint8_t)(ITC_GetCPUCC() & CPU_CC_I1I0);
00100 }
00101
00102 /**
00103   * @brief  Gets the software priority of the specified interrupt source.
00104   * @param  IrqNum : Specifies the peripheral interrupt source.
00105   * @retval ITC_PriorityLevel_TypeDef : Specifies the software priority of the interrupt source.
00106   */
00107 ITC_PriorityLevel_TypeDef ITC_GetSoftwarePriority(ITC_Irq_TypeDef IrqNum)
00108 {
00109   uint8_t Value = 0;
00110   uint8_t Mask = 0;
00111
00112   /* Check function parameters */
00113   assert_param(IS_ITC_IRQ_OK((uint8_t)IrqNum));
00114
00115   /* Define the mask corresponding to the bits position in the SPR register */
00116   Mask = (uint8_t)(0x03U << (((uint8_t)IrqNum % 4U) * 2U));
00117
00118   switch (IrqNum)
00119   {
00120   case ITC_IRQ_TLI: /* TLI software priority can be read but has no meaning */
00121   case ITC_IRQ_AWU:
00122   case ITC_IRQ_CLK:
00123   case ITC_IRQ_PORTA:
00124     Value = (uint8_t)(ITC->ISPR1 & Mask); /* Read software priority */
00125     break;
00126
00127   case ITC_IRQ_PORTB:
00128   case ITC_IRQ_PORTC:
00129   case ITC_IRQ_PORTD:
00130   case ITC_IRQ_PORTE:
00131     Value = (uint8_t)(ITC->ISPR2 & Mask); /* Read software priority */
00132     break;
00133
00134 #if defined(STM8S208) || defined(STM8AF52Ax)
00135   case ITC_IRQ_CAN_RX:
00136   case ITC_IRQ_CAN_TX:
00137 #endif /*STM8S208 or STM8AF52Ax */
00138 #if defined(STM8S903) || defined(STM8AF622x)
00139   case ITC_IRQ_PORTF:
00140 #endif /*STM8S903 or STM8AF622x */
00141   case ITC_IRQ_SPI:
00142   case ITC_IRQ_TIM1_OVF:
00143     Value = (uint8_t)(ITC->ISPR3 & Mask); /* Read software priority */
00144     break;
00145
00146   case ITC_IRQ_TIM1_CAPCOM:
00147 #if defined (STM8S903) || defined (STM8AF622x)
00148   case ITC_IRQ_TIM5_OVFTRI:
00149   case ITC_IRQ_TIM5_CAPCOM:
00150 #else
00151   case ITC_IRQ_TIM2_OVF:
00152   case ITC_IRQ_TIM2_CAPCOM:
00153 #endif /* STM8S903 or STM8AF622x*/
00154   case ITC_IRQ_TIM3_OVF:
00155     Value = (uint8_t)(ITC->ISPR4 & Mask); /* Read software priority */
00156     break;
00157
00158   case ITC_IRQ_TIM3_CAPCOM:
00159 #if defined(STM8S208) ||defined(STM8S207) || defined (STM8S007) || defined(STM8S103) || \
00160     defined(STM8S003) ||defined(STM8S001) || defined (STM8S903) || defined (STM8AF52Ax) || defined (STM8AF62Ax)
00161   case ITC_IRQ_UART1_TX:
00162   case ITC_IRQ_UART1_RX:
00163 #endif /*STM8S208 or STM8S207 or STM8S007 or STM8S103 or STM8S003 or STM8S001 or STM8S903 or STM8AF52Ax or STM8AF62Ax */
00164 #if defined(STM8AF622x)
00165   case ITC_IRQ_UART4_TX:
00166   case ITC_IRQ_UART4_RX:
00167 #endif /*STM8AF622x */
00168   case ITC_IRQ_I2C:
00169     Value = (uint8_t)(ITC->ISPR5 & Mask); /* Read software priority */
00170     break;
00171
00172 #if defined(STM8S105) || defined(STM8S005) || defined(STM8AF626x)
00173   case ITC_IRQ_UART2_TX:
00174   case ITC_IRQ_UART2_RX:
00175 #endif /*STM8S105 or STM8AF626x*/
00176 #if defined(STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8AF52Ax) || \
00177     defined(STM8AF62Ax)
00178   case ITC_IRQ_UART3_TX:
00179   case ITC_IRQ_UART3_RX:
00180   case ITC_IRQ_ADC2:
00181 #endif /*STM8S208 or STM8S207 or STM8AF52Ax or STM8AF62Ax */
00182 #if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \
00183     defined(STM8S001) || defined(STM8S903) || defined(STM8AF626x) || defined(STM8AF622x)
00184   case ITC_IRQ_ADC1:
00185 #endif /*STM8S105, STM8S005, STM8S103 or STM8S003 or STM8S001 or STM8S903 or STM8AF626x or STM8AF622x */
00186 #if defined (STM8S903) || defined (STM8AF622x)
00187   case ITC_IRQ_TIM6_OVFTRI:
00188 #else
00189   case ITC_IRQ_TIM4_OVF:
00190 #endif /*STM8S903 or STM8AF622x */
00191     Value = (uint8_t)(ITC->ISPR6 & Mask); /* Read software priority */
00192     break;
00193
00194   case ITC_IRQ_EEPROM_EEC:
00195     Value = (uint8_t)(ITC->ISPR7 & Mask); /* Read software priority */
00196     break;
00197
00198   default:
00199     break;
00200   }
00201
00202   Value >>= (uint8_t)(((uint8_t)IrqNum % 4u) * 2u);
00203
00204   return((ITC_PriorityLevel_TypeDef)Value);
00205 }
00206
00207 /**
00208   * @brief  Sets the software priority of the specified interrupt source.
00209   * @note   - The modification of the software priority is only possible when
00210   *         the interrupts are disabled.
00211   *         - The normal behavior is to disable the interrupt before calling
00212   *         this function, and re-enable it after.
00213   *         - The priority level 0 cannot be set (see product specification
00214   *         for more details).
00215   * @param  IrqNum : Specifies the peripheral interrupt source.
00216   * @param  PriorityValue : Specifies the software priority value to set,
00217   *         can be a value of @ref  ITC_PriorityLevel_TypeDef .
00218   * @retval None
00219 */
00220 void ITC_SetSoftwarePriority(ITC_Irq_TypeDef IrqNum, ITC_PriorityLevel_TypeDef PriorityValue)
00221 {
00222   uint8_t Mask = 0;
00223   uint8_t NewPriority = 0;
00224
00225   /* Check function parameters */
00226   assert_param(IS_ITC_IRQ_OK((uint8_t)IrqNum));
00227   assert_param(IS_ITC_PRIORITY_OK(PriorityValue));
00228
00229   /* Check if interrupts are disabled */
00230   assert_param(IS_ITC_INTERRUPTS_DISABLED);
00231
00232   /* Define the mask corresponding to the bits position in the SPR register */
00233   /* The mask is reversed in order to clear the 2 bits after more easily */
00234   Mask = (uint8_t)(~(uint8_t)(0x03U << (((uint8_t)IrqNum % 4U) * 2U)));
00235
00236   /* Define the new priority to write */
00237   NewPriority = (uint8_t)((uint8_t)(PriorityValue) << (((uint8_t)IrqNum % 4U) * 2U));
00238
00239   switch (IrqNum)
00240   {
00241   case ITC_IRQ_TLI: /* TLI software priority can be written but has no meaning */
00242   case ITC_IRQ_AWU:
00243   case ITC_IRQ_CLK:
00244   case ITC_IRQ_PORTA:
00245     ITC->ISPR1 &= Mask;
00246     ITC->ISPR1 |= NewPriority;
00247     break;
00248
00249   case ITC_IRQ_PORTB:
00250   case ITC_IRQ_PORTC:
00251   case ITC_IRQ_PORTD:
00252   case ITC_IRQ_PORTE:
00253     ITC->ISPR2 &= Mask;
00254     ITC->ISPR2 |= NewPriority;
00255     break;
00256
00257 #if defined(STM8S208) || defined(STM8AF52Ax)
00258   case ITC_IRQ_CAN_RX:
00259   case ITC_IRQ_CAN_TX:
00260 #endif /*STM8S208 or STM8AF52Ax */
00261 #if defined(STM8S903) || defined(STM8AF622x)
00262   case ITC_IRQ_PORTF:
00263 #endif /*STM8S903 or STM8AF622x */
00264   case ITC_IRQ_SPI:
00265   case ITC_IRQ_TIM1_OVF:
00266     ITC->ISPR3 &= Mask;
00267     ITC->ISPR3 |= NewPriority;
00268     break;
00269
00270   case ITC_IRQ_TIM1_CAPCOM:
00271 #if defined(STM8S903) || defined(STM8AF622x)
00272   case ITC_IRQ_TIM5_OVFTRI:
00273   case ITC_IRQ_TIM5_CAPCOM:
00274 #else
00275   case ITC_IRQ_TIM2_OVF:
00276   case ITC_IRQ_TIM2_CAPCOM:
00277 #endif /*STM8S903 or STM8AF622x */
00278   case ITC_IRQ_TIM3_OVF:
00279     ITC->ISPR4 &= Mask;
00280     ITC->ISPR4 |= NewPriority;
00281     break;
00282
00283   case ITC_IRQ_TIM3_CAPCOM:
00284 #if defined(STM8S208) ||defined(STM8S207) || defined (STM8S007) || defined(STM8S103) || \
00285     defined(STM8S001) ||defined(STM8S003) ||defined(STM8S903) || defined (STM8AF52Ax) || defined (STM8AF62Ax)
00286   case ITC_IRQ_UART1_TX:
00287   case ITC_IRQ_UART1_RX:
00288 #endif /*STM8S208 or STM8S207 or STM8S007 or STM8S103 or STM8S003 or STM8S001 or STM8S903 or STM8AF52Ax or STM8AF62Ax */
00289 #if defined(STM8AF622x)
00290   case ITC_IRQ_UART4_TX:
00291   case ITC_IRQ_UART4_RX:
00292 #endif /*STM8AF622x */
00293   case ITC_IRQ_I2C:
00294     ITC->ISPR5 &= Mask;
00295     ITC->ISPR5 |= NewPriority;
00296     break;
00297
00298 #if defined(STM8S105) || defined(STM8S005) || defined(STM8AF626x)
00299   case ITC_IRQ_UART2_TX:
00300   case ITC_IRQ_UART2_RX:
00301 #endif /*STM8S105 or STM8AF626x */
00302
00303 #if defined(STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8AF52Ax) || \
00304     defined(STM8AF62Ax)
00305   case ITC_IRQ_UART3_TX:
00306   case ITC_IRQ_UART3_RX:
00307   case ITC_IRQ_ADC2:
00308 #endif /*STM8S208 or STM8S207 or STM8AF52Ax or STM8AF62Ax */
00309
00310 #if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \
00311     defined(STM8S001) || defined(STM8S903) || defined(STM8AF626x) || defined (STM8AF622x)
00312   case ITC_IRQ_ADC1:
00313 #endif /*STM8S105, STM8S005, STM8S103 or STM8S003 or STM8S001 or STM8S903 or STM8AF626x or STM8AF622x */
00314
00315 #if defined (STM8S903) || defined (STM8AF622x)
00316   case ITC_IRQ_TIM6_OVFTRI:
00317 #else
00318   case ITC_IRQ_TIM4_OVF:
00319 #endif /* STM8S903 or STM8AF622x */
00320     ITC->ISPR6 &= Mask;
00321     ITC->ISPR6 |= NewPriority;
00322     break;
00323
00324   case ITC_IRQ_EEPROM_EEC:
00325     ITC->ISPR7 &= Mask;
00326     ITC->ISPR7 |= NewPriority;
00327     break;
00328
00329   default:
00330     break;
00331   }
00332 }
00333
00334 /**
00335   * @}
00336   */
00337
00338 /**
00339   * @}
00340   */
00341
00342
00343 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_itc.h Source File

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  • STM8S_StdPeriph_Driver
  • inc
stm8s_itc.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_itc.h
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all functions prototype and macros for the ITC peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Define to prevent recursive inclusion -------------------------------------*/
00029 #ifndef __STM8S_ITC_H
00030 #define __STM8S_ITC_H
00031
00032 /* Includes ------------------------------------------------------------------*/
00033 #include "stm8s.h"
00034
00035 /* Exported types ------------------------------------------------------------*/
00036
00037 /** @addtogroup ITC_Exported_Types
00038   * @{
00039   */
00040
00041 /**
00042   * @brief  ITC Interrupt Lines selection
00043   */
00044 typedef enum {
00045   ITC_IRQ_TLI            = (uint8_t)0,   /*!< Software interrupt */
00046   ITC_IRQ_AWU            = (uint8_t)1,   /*!< Auto wake up from halt interrupt */
00047   ITC_IRQ_CLK            = (uint8_t)2,   /*!< Clock controller interrupt */
00048   ITC_IRQ_PORTA          = (uint8_t)3,   /*!< Port A external interrupts */
00049   ITC_IRQ_PORTB          = (uint8_t)4,   /*!< Port B external interrupts */
00050   ITC_IRQ_PORTC          = (uint8_t)5,   /*!< Port C external interrupts */
00051   ITC_IRQ_PORTD          = (uint8_t)6,   /*!< Port D external interrupts */
00052   ITC_IRQ_PORTE          = (uint8_t)7,   /*!< Port E external interrupts */
00053
00054 #if defined(STM8S208) || defined(STM8AF52Ax)
00055   ITC_IRQ_CAN_RX         = (uint8_t)8,   /*!< beCAN RX interrupt */
00056   ITC_IRQ_CAN_TX         = (uint8_t)9,   /*!< beCAN TX/ER/SC interrupt */
00057 #endif /*STM8S208 or STM8AF52Ax */
00058
00059 #if defined(STM8S903) || defined(STM8AF622x)
00060   ITC_IRQ_PORTF          = (uint8_t)8,   /*!< Port F external interrupts */
00061 #endif /*STM8S903 or STM8AF622x */
00062
00063   ITC_IRQ_SPI            = (uint8_t)10,  /*!< SPI interrupt */
00064   ITC_IRQ_TIM1_OVF       = (uint8_t)11,  /*!< TIM1 update/overflow/underflow/trigger/
00065                                          break interrupt*/
00066   ITC_IRQ_TIM1_CAPCOM    = (uint8_t)12,  /*!< TIM1 capture/compare interrupt */
00067
00068 #if defined(STM8S903) || defined(STM8AF622x)
00069   ITC_IRQ_TIM5_OVFTRI    = (uint8_t)13,  /*!< TIM5 update/overflow/underflow/trigger/
00070                                          interrupt */
00071   ITC_IRQ_TIM5_CAPCOM    = (uint8_t)14,  /*!< TIM5 capture/compare interrupt */
00072 #else
00073   ITC_IRQ_TIM2_OVF       = (uint8_t)13,  /*!< TIM2 update /overflow interrupt */
00074   ITC_IRQ_TIM2_CAPCOM    = (uint8_t)14,  /*!< TIM2 capture/compare interrupt */
00075 #endif /*STM8S903 or STM8AF622x */
00076
00077   ITC_IRQ_TIM3_OVF       = (uint8_t)15,  /*!< TIM3 update /overflow interrupt*/
00078   ITC_IRQ_TIM3_CAPCOM    = (uint8_t)16,  /*!< TIM3 update /overflow interrupt */
00079
00080 #if defined(STM8S208) ||defined(STM8S207) || defined (STM8S007) || defined(STM8S103) || \
00081     defined(STM8S003) || defined(STM8S001) ||defined(STM8S903) || defined (STM8AF52Ax) || defined (STM8AF62Ax)
00082   ITC_IRQ_UART1_TX       = (uint8_t)17,  /*!< UART1 TX interrupt */
00083   ITC_IRQ_UART1_RX       = (uint8_t)18,  /*!< UART1 RX interrupt */
00084 #endif /*STM8S208 or STM8S207 or STM8S007 or STM8S103 or STM8S003 or STM8S001 or STM8S903 or STM8AF52Ax or STM8AF62Ax */
00085 #if defined(STM8AF622x)
00086   ITC_IRQ_UART4_TX       = (uint8_t)17,  /*!< UART4 TX interrupt */
00087   ITC_IRQ_UART4_RX       = (uint8_t)18,  /*!< UART4 RX interrupt */
00088 #endif /*STM8AF622x */
00089
00090   ITC_IRQ_I2C            = (uint8_t)19,  /*!< I2C interrupt */
00091
00092 #if defined(STM8S105) || defined(STM8S005) || defined(STM8AF626x)
00093   ITC_IRQ_UART2_TX       = (uint8_t)20,  /*!< USART2 TX interrupt */
00094   ITC_IRQ_UART2_RX       = (uint8_t)21,  /*!< USART2 RX interrupt */
00095 #endif /*STM8S105 or STM8AF626x */
00096
00097 #if defined(STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8AF52Ax) || defined(STM8AF62Ax)
00098   ITC_IRQ_UART3_TX       = (uint8_t)20,  /*!< USART3 TX interrupt */
00099   ITC_IRQ_UART3_RX       = (uint8_t)21,  /*!< USART3 RX interrupt */
00100   ITC_IRQ_ADC2           = (uint8_t)22,  /*!< ADC2 interrupt */
00101 #endif /*STM8S208 or STM8S207 or STM8AF52Ax or STM8AF62Ax */
00102
00103 #if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || defined(STM8S001) || defined(STM8S903) || defined(STM8AF626x) || defined(STM8AF622x)
00104   ITC_IRQ_ADC1           = (uint8_t)22,  /*!< ADC1 interrupt */
00105 #endif /*STM8S105 or STM8S005 or STM8S003 or STM8S103 or STM8S001 or STM8S903 or STM8AF626x or STM8AF622x */
00106
00107 #if defined(STM8S903) || defined(STM8AF622x)
00108   ITC_IRQ_TIM6_OVFTRI    = (uint8_t)23,  /*!< TIM6 update/overflow/underflow/trigger/
00109                                          interrupt */
00110 #else
00111   ITC_IRQ_TIM4_OVF       = (uint8_t)23,  /*!< TIM4 update /overflow interrupt */
00112 #endif /*STM8S903 or STM8AF622x */
00113
00114   ITC_IRQ_EEPROM_EEC     = (uint8_t)24  /*!< Flash interrupt */
00115 } ITC_Irq_TypeDef;
00116
00117 /**
00118   * @brief  ITC Priority Levels selection
00119   */
00120 typedef enum {
00121   ITC_PRIORITYLEVEL_0 = (uint8_t)0x02, /*!< Software priority level 0 (cannot be written) */
00122   ITC_PRIORITYLEVEL_1 = (uint8_t)0x01, /*!< Software priority level 1 */
00123   ITC_PRIORITYLEVEL_2 = (uint8_t)0x00, /*!< Software priority level 2 */
00124   ITC_PRIORITYLEVEL_3 = (uint8_t)0x03  /*!< Software priority level 3 */
00125 } ITC_PriorityLevel_TypeDef;
00126
00127 /**
00128   * @}
00129   */
00130
00131 /* Exported constants --------------------------------------------------------*/
00132
00133 /** @addtogroup ITC_Exported_Constants
00134   * @{
00135   */
00136 #define CPU_SOFT_INT_DISABLED ((uint8_t)0x28) /*!< Mask for I1 and I0 bits in CPU_CC register */
00137
00138 /**
00139   * @}
00140   */
00141
00142 /* Private macros ------------------------------------------------------------*/
00143
00144 /**
00145   * @brief  Macros used by the assert function in order to check the different functions parameters.
00146   * @addtogroup ITC_Private_Macros
00147   * @{
00148   */
00149
00150 /* Used by assert function */
00151 #define IS_ITC_IRQ_OK(IRQ) ((IRQ) <= (uint8_t)24)
00152
00153 /* Used by assert function */
00154 #define IS_ITC_PRIORITY_OK(PriorityValue) \
00155   (((PriorityValue) == ITC_PRIORITYLEVEL_0) || \
00156    ((PriorityValue) == ITC_PRIORITYLEVEL_1) || \
00157    ((PriorityValue) == ITC_PRIORITYLEVEL_2) || \
00158    ((PriorityValue) == ITC_PRIORITYLEVEL_3))
00159
00160 /* Used by assert function */
00161 #define IS_ITC_INTERRUPTS_DISABLED (ITC_GetSoftIntStatus() == CPU_SOFT_INT_DISABLED)
00162
00163 /**
00164   * @}
00165   */
00166
00167 /* Exported functions ------------------------------------------------------- */
00168
00169 /** @addtogroup ITC_Exported_Functions
00170   * @{
00171   */
00172
00173 uint8_t ITC_GetCPUCC(void);
00174 void ITC_DeInit(void);
00175 uint8_t ITC_GetSoftIntStatus(void);
00176 void ITC_SetSoftwarePriority(ITC_Irq_TypeDef IrqNum, ITC_PriorityLevel_TypeDef PriorityValue);
00177 ITC_PriorityLevel_TypeDef ITC_GetSoftwarePriority(ITC_Irq_TypeDef IrqNum);
00178
00179 /**
00180   * @}
00181   */
00182
00183 #endif /* __STM8S_ITC_H */
00184
00185
00186 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_iwdg.c Source File

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  • Globals
  • STM8S_StdPeriph_Driver
  • src
stm8s_iwdg.c
Go to the documentation of this file.
00001 /**
00002   ********************************************************************************
00003   * @file    stm8s_iwdg.c
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all the functions for the IWDG peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm8s_iwdg.h"
00030
00031 /* Private define ------------------------------------------------------------*/
00032 /* Private macro -------------------------------------------------------------*/
00033 /* Private variables ---------------------------------------------------------*/
00034 /* Private function prototypes -----------------------------------------------*/
00035 /* Private functions ---------------------------------------------------------*/
00036 /* Public functions ----------------------------------------------------------*/
00037
00038 /** @addtogroup IWDG_Public_Functions
00039   * @{
00040   */
00041
00042 /**
00043   * @brief  Enables or disables write access to Prescaler and Reload registers.
00044   * @param  IWDG_WriteAccess : New state of write access to Prescaler and Reload
00045   *         registers.  This parameter can be a value of @ref IWDG_WriteAccess_TypeDef.
00046   * @retval None
00047   */
00048 void IWDG_WriteAccessCmd(IWDG_WriteAccess_TypeDef IWDG_WriteAccess)
00049 {
00050   /* Check the parameters */
00051   assert_param(IS_IWDG_WRITEACCESS_MODE_OK(IWDG_WriteAccess));
00052
00053   IWDG->KR = (uint8_t)IWDG_WriteAccess; /* Write Access */
00054 }
00055
00056 /**
00057   * @brief  Sets IWDG Prescaler value.
00058   * @note   Write access should be enabled
00059   * @param  IWDG_Prescaler : Specifies the IWDG Prescaler value.
00060   *         This parameter can be a value of @ref IWDG_Prescaler_TypeDef.
00061   * @retval None
00062   */
00063 void IWDG_SetPrescaler(IWDG_Prescaler_TypeDef IWDG_Prescaler)
00064 {
00065   /* Check the parameters */
00066   assert_param(IS_IWDG_PRESCALER_OK(IWDG_Prescaler));
00067
00068   IWDG->PR = (uint8_t)IWDG_Prescaler;
00069 }
00070
00071 /**
00072   * @brief  Sets IWDG Reload value.
00073   * @note   Write access should be enabled
00074   * @param  IWDG_Reload : Reload register value.
00075   *         This parameter must be a number between 0 and 0xFF.
00076   * @retval None
00077   */
00078 void IWDG_SetReload(uint8_t IWDG_Reload)
00079 {
00080   IWDG->RLR = IWDG_Reload;
00081 }
00082
00083 /**
00084   * @brief  Reloads IWDG counter
00085   * @note   Write access should be enabled
00086   * @param  None
00087   * @retval None
00088   */
00089 void IWDG_ReloadCounter(void)
00090 {
00091   IWDG->KR = IWDG_KEY_REFRESH;
00092 }
00093
00094 /**
00095   * @brief  Enables IWDG.
00096   * @param  None
00097   * @retval None
00098   */
00099 void IWDG_Enable(void)
00100 {
00101   IWDG->KR = IWDG_KEY_ENABLE;
00102 }
00103
00104 /**
00105   * @}
00106   */
00107
00108 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_iwdg.h Source File

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  • STM8S_StdPeriph_Driver
  • inc
stm8s_iwdg.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_iwdg.h
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all functions prototypes and macros for the IWDG peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Define to prevent recursive inclusion -------------------------------------*/
00029 #ifndef __STM8S_IWDG_H
00030 #define __STM8S_IWDG_H
00031
00032 /* Includes ------------------------------------------------------------------*/
00033 #include "stm8s.h"
00034
00035 /** @addtogroup STM8S_StdPeriph_Driver
00036   * @{
00037   */
00038
00039 /** @addtogroup IWDG_Private_Define
00040   * @{
00041   */
00042
00043 /**
00044   * @brief  Define used to prevent watchdog reset
00045   */
00046 #define IWDG_KEY_REFRESH    ((uint8_t)0xAA)  /*!<  This value written in the Key register prevent the watchdog reset */
00047
00048 /**
00049   * @brief  Define used to start the watchdog counter down
00050   */
00051 #define IWDG_KEY_ENABLE     ((uint8_t)0xCC)  /*!<  This value written in the Key register start the watchdog counting down*/
00052
00053 /**
00054  * @}
00055  */
00056
00057 /** @addtogroup IWDG_Private_Macros
00058   * @{
00059   */
00060
00061 /**
00062   * @brief  Macro used by the assert function in order to check the different
00063   * values of the prescaler.
00064   */
00065 #define IS_IWDG_PRESCALER_OK(VALUE) (((VALUE) == IWDG_Prescaler_4   ) || \
00066                                      ((VALUE) == IWDG_Prescaler_8   ) || \
00067                                      ((VALUE) == IWDG_Prescaler_16  ) || \
00068                                      ((VALUE) == IWDG_Prescaler_32  ) || \
00069                                      ((VALUE) == IWDG_Prescaler_64  ) || \
00070                                      ((VALUE) == IWDG_Prescaler_128 ) || \
00071                                      ((VALUE) == IWDG_Prescaler_256))
00072
00073 /**
00074   * @brief  Macro used by the assert function in order to check the different
00075   * values of the counter register.
00076   */
00077 #define IS_IWDG_WRITEACCESS_MODE_OK(MODE) (((MODE) == IWDG_WriteAccess_Enable) || ((MODE) == IWDG_WriteAccess_Disable))
00078
00079 /**
00080   * @}
00081   */
00082
00083 /** @addtogroup IWDG_Exported_Types
00084   * @{
00085   */
00086
00087 /** IWDG write  access enumeration */
00088 typedef enum
00089 {
00090   IWDG_WriteAccess_Enable  = (uint8_t)0x55, /*!< Code 0x55 in Key register, allow write access to Prescaler and Reload registers */
00091   IWDG_WriteAccess_Disable = (uint8_t)0x00  /*!< Code 0x00 in Key register, not allow write access to Prescaler and Reload registers */
00092 } IWDG_WriteAccess_TypeDef;
00093
00094 /** IWDG prescaler enumaration */
00095 typedef enum
00096 {
00097   IWDG_Prescaler_4   = (uint8_t)0x00, /*!< Used to set prescaler register to 4 */
00098   IWDG_Prescaler_8   = (uint8_t)0x01, /*!< Used to set prescaler register to 8 */
00099   IWDG_Prescaler_16  = (uint8_t)0x02, /*!< Used to set prescaler register to 16 */
00100   IWDG_Prescaler_32  = (uint8_t)0x03, /*!< Used to set prescaler register to 32 */
00101   IWDG_Prescaler_64  = (uint8_t)0x04, /*!< Used to set prescaler register to 64 */
00102   IWDG_Prescaler_128 = (uint8_t)0x05, /*!< Used to set prescaler register to 128 */
00103   IWDG_Prescaler_256 = (uint8_t)0x06  /*!< Used to set prescaler register to 256 */
00104 } IWDG_Prescaler_TypeDef;
00105
00106 /**
00107   * @}
00108   */
00109
00110 /** @addtogroup IWDG_Exported_Functions
00111   * @{
00112   */
00113
00114 void IWDG_WriteAccessCmd(IWDG_WriteAccess_TypeDef IWDG_WriteAccess);
00115 void IWDG_SetPrescaler(IWDG_Prescaler_TypeDef IWDG_Prescaler);
00116 void IWDG_SetReload(uint8_t IWDG_Reload);
00117 void IWDG_ReloadCounter(void);
00118 void IWDG_Enable(void);
00119
00120 /**
00121   * @}
00122   */
00123
00124 #endif /* __STM8S_IWDG_H */
00125
00126 /**
00127   * @}
00128   */
00129
00130
00131 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_rst.c Source File

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  • STM8S_StdPeriph_Driver
  • src
stm8s_rst.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_rst.c
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all the functions for the RST peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Includes ------------------------------------------------------------------*/
00029
00030 #include "stm8s_rst.h"
00031
00032 /** @addtogroup STM8S_StdPeriph_Driver
00033   * @{
00034   */
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private Constants ---------------------------------------------------------*/
00041 /* Public functions ----------------------------------------------------------*/
00042 /**
00043   * @addtogroup RST_Public_Functions
00044   * @{
00045   */
00046
00047
00048 /**
00049   * @brief   Checks whether the specified RST flag is set or not.
00050   * @param   RST_Flag : specify the reset flag to check.
00051   *          This parameter can be a value of @ref RST_Flag_TypeDef.
00052   * @retval  FlagStatus: status of the given RST flag.
00053   */
00054 FlagStatus RST_GetFlagStatus(RST_Flag_TypeDef RST_Flag)
00055 {
00056   /* Check the parameters */
00057   assert_param(IS_RST_FLAG_OK(RST_Flag));
00058
00059   /* Get flag status */
00060   return((FlagStatus)(((uint8_t)(RST->SR & RST_Flag) == (uint8_t)0x00) ? RESET : SET));
00061 }
00062
00063 /**
00064   * @brief  Clears the specified RST flag.
00065   * @param  RST_Flag : specify the reset flag to clear.
00066   *         This parameter can be a value of @ref RST_Flag_TypeDef.
00067   * @retval None
00068   */
00069 void RST_ClearFlag(RST_Flag_TypeDef RST_Flag)
00070 {
00071   /* Check the parameters */
00072   assert_param(IS_RST_FLAG_OK(RST_Flag));
00073
00074   RST->SR = (uint8_t)RST_Flag;
00075 }
00076
00077 /**
00078   * @}
00079   */
00080
00081 /**
00082   * @}
00083   */
00084
00085
00086 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_rst.h Source File

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  • STM8S_StdPeriph_Driver
  • inc
stm8s_rst.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_rst.h
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all functions prototype and macros for the RST peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027 /* Define to prevent recursive inclusion -------------------------------------*/
00028 #ifndef __STM8S_RST_H
00029 #define __STM8S_RST_H
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm8s.h"
00033
00034 /** @addtogroup STM8S_StdPeriph_Driver
00035   * @{
00036   */
00037
00038 /** @addtogroup RST_Exported_Types
00039   * @{
00040   */
00041 typedef enum {
00042   RST_FLAG_EMCF    = (uint8_t)0x10, /*!< EMC reset flag */
00043   RST_FLAG_SWIMF   = (uint8_t)0x08, /*!< SWIM reset flag */
00044   RST_FLAG_ILLOPF  = (uint8_t)0x04, /*!< Illigal opcode reset flag */
00045   RST_FLAG_IWDGF   = (uint8_t)0x02, /*!< Independent watchdog reset flag */
00046   RST_FLAG_WWDGF   = (uint8_t)0x01  /*!< Window watchdog reset flag */
00047 }RST_Flag_TypeDef;
00048
00049 /**
00050   * @}
00051   */
00052
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Exported macros -----------------------------------------------------------*/
00055
00056 /** @addtogroup RST_Private_Macros
00057   * @{
00058   */
00059
00060 /**
00061   * @brief  Macro used by the assert function to check the different functions parameters.
00062   */
00063 /**
00064   * @brief  Macro used by the assert function to check the different RST flags.
00065   */
00066 #define IS_RST_FLAG_OK(FLAG) (((FLAG) == RST_FLAG_EMCF) || \
00067                               ((FLAG) == RST_FLAG_SWIMF)  ||\
00068                               ((FLAG) == RST_FLAG_ILLOPF) ||\
00069                               ((FLAG) == RST_FLAG_IWDGF)  ||\
00070                               ((FLAG) == RST_FLAG_WWDGF))
00071
00072 /**
00073   * @}
00074   */
00075
00076 /** @addtogroup RST_Exported_functions
00077   * @{
00078   */
00079 FlagStatus RST_GetFlagStatus(RST_Flag_TypeDef RST_Flag);
00080 void RST_ClearFlag(RST_Flag_TypeDef RST_Flag);
00081
00082 /**
00083   * @}
00084   */
00085
00086 #endif /* __STM8S_RST_H */
00087
00088 /**
00089   * @}
00090   */
00091
00092 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_spi.c Source File

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  • Globals
  • STM8S_StdPeriph_Driver
  • src
stm8s_spi.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_spi.c
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all the functions for the SPI peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm8s_spi.h"
00030
00031 /** @addtogroup STM8S_StdPeriph_Driver
00032   * @{
00033   */
00034
00035 /* Private define ------------------------------------------------------------*/
00036 /* Private macro -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038 /* Private function prototypes -----------------------------------------------*/
00039 /* Private functions ---------------------------------------------------------*/
00040
00041 /** @addtogroup SPI_Public_Functions
00042   * @{
00043   */
00044
00045 /**
00046   * @brief  Deinitializes the SPI peripheral registers to their default reset values.
00047   * @param  None
00048   * @retval None
00049   */
00050 void SPI_DeInit(void)
00051 {
00052   SPI->CR1    = SPI_CR1_RESET_VALUE;
00053   SPI->CR2    = SPI_CR2_RESET_VALUE;
00054   SPI->ICR    = SPI_ICR_RESET_VALUE;
00055   SPI->SR     = SPI_SR_RESET_VALUE;
00056   SPI->CRCPR  = SPI_CRCPR_RESET_VALUE;
00057 }
00058
00059 /**
00060   * @brief  Initializes the SPI according to the specified parameters.
00061   * @param  FirstBit : This parameter can be any of the
00062   *         @ref SPI_FirstBit_TypeDef enumeration.
00063   * @param  BaudRatePrescaler : This parameter can be any of the
00064   *         @ref SPI_BaudRatePrescaler_TypeDef enumeration.
00065   * @param  Mode : This parameter can be any of the
00066   *         @ref SPI_Mode_TypeDef enumeration.
00067   * @param  ClockPolarity : This parameter can be any of the
00068   *         @ref SPI_ClockPolarity_TypeDef enumeration.
00069   * @param  ClockPhase : This parameter can be any of the
00070   *         @ref SPI_ClockPhase_TypeDef enumeration.
00071   * @param  Data_Direction : This parameter can be any of the
00072   *         @ref SPI_DataDirection_TypeDef enumeration.
00073   * @param  Slave_Management : This parameter can be any of the
00074   *         @ref SPI_NSS_TypeDef enumeration.
00075   * @param  CRCPolynomial : Configures the CRC polynomial.
00076   * @retval None
00077   */
00078 void SPI_Init(SPI_FirstBit_TypeDef FirstBit, SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, SPI_Mode_TypeDef Mode, SPI_ClockPolarity_TypeDef ClockPolarity, SPI_ClockPhase_TypeDef ClockPhase, SPI_DataDirection_TypeDef Data_Direction, SPI_NSS_TypeDef Slave_Management, uint8_t CRCPolynomial)
00079 {
00080   /* Check structure elements */
00081   assert_param(IS_SPI_FIRSTBIT_OK(FirstBit));
00082   assert_param(IS_SPI_BAUDRATE_PRESCALER_OK(BaudRatePrescaler));
00083   assert_param(IS_SPI_MODE_OK(Mode));
00084   assert_param(IS_SPI_POLARITY_OK(ClockPolarity));
00085   assert_param(IS_SPI_PHASE_OK(ClockPhase));
00086   assert_param(IS_SPI_DATA_DIRECTION_OK(Data_Direction));
00087   assert_param(IS_SPI_SLAVEMANAGEMENT_OK(Slave_Management));
00088   assert_param(IS_SPI_CRC_POLYNOMIAL_OK(CRCPolynomial));
00089
00090   /* Frame Format, BaudRate, Clock Polarity and Phase configuration */
00091   SPI->CR1 = (uint8_t)((uint8_t)((uint8_t)FirstBit | BaudRatePrescaler) |
00092                        (uint8_t)((uint8_t)ClockPolarity | ClockPhase));
00093
00094   /* Data direction configuration: BDM, BDOE and RXONLY bits */
00095   SPI->CR2 = (uint8_t)((uint8_t)(Data_Direction) | (uint8_t)(Slave_Management));
00096
00097   if (Mode == SPI_MODE_MASTER)
00098   {
00099     SPI->CR2 |= (uint8_t)SPI_CR2_SSI;
00100   }
00101   else
00102   {
00103     SPI->CR2 &= (uint8_t)~(SPI_CR2_SSI);
00104   }
00105
00106   /* Master/Slave mode configuration */
00107   SPI->CR1 |= (uint8_t)(Mode);
00108
00109   /* CRC configuration */
00110   SPI->CRCPR = (uint8_t)CRCPolynomial;
00111 }
00112
00113 /**
00114   * @brief  Enables or disables the SPI peripheral.
00115   * @param  NewState New state of the SPI peripheral.
00116   *         This parameter can be: ENABLE or DISABLE
00117   * @retval None
00118   */
00119 void SPI_Cmd(FunctionalState NewState)
00120 {
00121   /* Check function parameters */
00122   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00123
00124   if (NewState != DISABLE)
00125   {
00126     SPI->CR1 |= SPI_CR1_SPE; /* Enable the SPI peripheral*/
00127   }
00128   else
00129   {
00130     SPI->CR1 &= (uint8_t)(~SPI_CR1_SPE); /* Disable the SPI peripheral*/
00131   }
00132 }
00133
00134 /**
00135   * @brief  Enables or disables the specified interrupts.
00136   * @param  SPI_IT Specifies the SPI interrupts sources to be enabled or disabled.
00137   * @param  NewState: The new state of the specified SPI interrupts.
00138   *         This parameter can be: ENABLE or DISABLE.
00139   * @retval None
00140   */
00141 void SPI_ITConfig(SPI_IT_TypeDef SPI_IT, FunctionalState NewState)
00142 {
00143   uint8_t itpos = 0;
00144   /* Check function parameters */
00145   assert_param(IS_SPI_CONFIG_IT_OK(SPI_IT));
00146   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00147
00148   /* Get the SPI IT index */
00149   itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)SPI_IT & (uint8_t)0x0F));
00150
00151   if (NewState != DISABLE)
00152   {
00153     SPI->ICR |= itpos; /* Enable interrupt*/
00154   }
00155   else
00156   {
00157     SPI->ICR &= (uint8_t)(~itpos); /* Disable interrupt*/
00158   }
00159 }
00160
00161 /**
00162   * @brief  Transmits a Data through the SPI peripheral.
00163   * @param  Data : Byte to be transmitted.
00164   * @retval None
00165   */
00166 void SPI_SendData(uint8_t Data)
00167 {
00168   SPI->DR = Data; /* Write in the DR register the data to be sent*/
00169 }
00170
00171 /**
00172   * @brief  Returns the most recent received data by the SPI peripheral.
00173   * @param  None
00174   * @retval The value of the received data.
00175   */
00176 uint8_t SPI_ReceiveData(void)
00177 {
00178   return ((uint8_t)SPI->DR); /* Return the data in the DR register*/
00179 }
00180
00181 /**
00182   * @brief  Configures internally by software the NSS pin.
00183   * @param  NewState Indicates the new state of the SPI Software slave management.
00184   *         This parameter can be: ENABLE or DISABLE.
00185   * @retval None
00186   */
00187 void SPI_NSSInternalSoftwareCmd(FunctionalState NewState)
00188 {
00189   /* Check function parameters */
00190   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00191
00192   if (NewState != DISABLE)
00193   {
00194     SPI->CR2 |= SPI_CR2_SSI; /* Set NSS pin internally by software*/
00195   }
00196   else
00197   {
00198     SPI->CR2 &= (uint8_t)(~SPI_CR2_SSI); /* Reset NSS pin internally by software*/
00199   }
00200 }
00201
00202 /**
00203   * @brief  Enables the transmit of the CRC value.
00204   * @param  None
00205   * @retval None
00206   */
00207 void SPI_TransmitCRC(void)
00208 {
00209   SPI->CR2 |= SPI_CR2_CRCNEXT; /* Enable the CRC transmission*/
00210 }
00211
00212 /**
00213   * @brief  Enables or disables the CRC value calculation of the transferred bytes.
00214   * @param  NewState Indicates the new state of the SPI CRC value calculation.
00215   *         This parameter can be: ENABLE or DISABLE.
00216   * @retval None
00217   */
00218 void SPI_CalculateCRCCmd(FunctionalState NewState)
00219 {
00220   /* Check function parameters */
00221   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00222
00223   if (NewState != DISABLE)
00224   {
00225     SPI->CR2 |= SPI_CR2_CRCEN; /* Enable the CRC calculation*/
00226   }
00227   else
00228   {
00229     SPI->CR2 &= (uint8_t)(~SPI_CR2_CRCEN); /* Disable the CRC calculation*/
00230   }
00231 }
00232
00233 /**
00234   * @brief  Returns the transmit or the receive CRC register value.
00235   * @param  SPI_CRC Specifies the CRC register to be read.
00236   * @retval The selected CRC register value.
00237   */
00238 uint8_t SPI_GetCRC(SPI_CRC_TypeDef SPI_CRC)
00239 {
00240   uint8_t crcreg = 0;
00241
00242   /* Check function parameters */
00243   assert_param(IS_SPI_CRC_OK(SPI_CRC));
00244
00245   if (SPI_CRC != SPI_CRC_RX)
00246   {
00247     crcreg = SPI->TXCRCR;  /* Get the Tx CRC register*/
00248   }
00249   else
00250   {
00251     crcreg = SPI->RXCRCR; /* Get the Rx CRC register*/
00252   }
00253
00254   /* Return the selected CRC register status*/
00255   return crcreg;
00256 }
00257
00258 /**
00259   * @brief  Reset the Rx CRCR and Tx CRCR registers.
00260   * @param  None
00261   * @retval None
00262   */
00263 void SPI_ResetCRC(void)
00264 {
00265   /* Rx CRCR & Tx CRCR registers are reset when CRCEN (hardware calculation)
00266   bit in SPI_CR2 is written to 1 (enable) */
00267   SPI_CalculateCRCCmd(ENABLE);
00268
00269   /* Previous function disable the SPI */
00270   SPI_Cmd(ENABLE);
00271 }
00272
00273 /**
00274   * @brief  Returns the CRC Polynomial register value.
00275   * @param  None
00276   * @retval The CRC Polynomial register value.
00277   */
00278 uint8_t SPI_GetCRCPolynomial(void)
00279 {
00280   return SPI->CRCPR; /* Return the CRC polynomial register */
00281 }
00282
00283 /**
00284   * @brief  Selects the data transfer direction in bi-directional mode.
00285   * @param  SPI_Direction Specifies the data transfer direction in bi-directional mode.
00286   * @retval None
00287   */
00288 void SPI_BiDirectionalLineConfig(SPI_Direction_TypeDef SPI_Direction)
00289 {
00290   /* Check function parameters */
00291   assert_param(IS_SPI_DIRECTION_OK(SPI_Direction));
00292
00293   if (SPI_Direction != SPI_DIRECTION_RX)
00294   {
00295     SPI->CR2 |= SPI_CR2_BDOE; /* Set the Tx only mode*/
00296   }
00297   else
00298   {
00299     SPI->CR2 &= (uint8_t)(~SPI_CR2_BDOE); /* Set the Rx only mode*/
00300   }
00301 }
00302
00303 /**
00304   * @brief  Checks whether the specified SPI flag is set or not.
00305   * @param  SPI_FLAG : Specifies the flag to check.
00306   *         This parameter can be any of the @ref SPI_Flag_TypeDef enumeration.
00307   * @retval FlagStatus : Indicates the state of SPI_FLAG.
00308   *         This parameter can be any of the @ref FlagStatus enumeration.
00309   */
00310
00311 FlagStatus SPI_GetFlagStatus(SPI_Flag_TypeDef SPI_FLAG)
00312 {
00313   FlagStatus status = RESET;
00314   /* Check parameters */
00315   assert_param(IS_SPI_FLAGS_OK(SPI_FLAG));
00316
00317   /* Check the status of the specified SPI flag */
00318   if ((SPI->SR & (uint8_t)SPI_FLAG) != (uint8_t)RESET)
00319   {
00320     status = SET; /* SPI_FLAG is set */
00321   }
00322   else
00323   {
00324     status = RESET; /* SPI_FLAG is reset*/
00325   }
00326
00327   /* Return the SPI_FLAG status */
00328   return status;
00329 }
00330
00331 /**
00332   * @brief  Clears the SPI flags.
00333   * @param  SPI_FLAG : Specifies the flag to clear.
00334   *         This parameter can be one of the following values:
00335   *         - SPI_FLAG_CRCERR
00336   *         - SPI_FLAG_WKUP
00337   * @note   - OVR (OverRun Error) interrupt pending bit is cleared by software
00338   *         sequence:
00339   *         a read operation to SPI_DR register (SPI_ReceiveData()) followed by
00340   *         a read operation to SPI_SR register (SPI_GetFlagStatus()).
00341   *         - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
00342   *         a read/write operation to SPI_SR register (SPI_GetFlagStatus()) followed by
00343   *         a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
00344   * @retval None
00345   */
00346 void SPI_ClearFlag(SPI_Flag_TypeDef SPI_FLAG)
00347 {
00348   assert_param(IS_SPI_CLEAR_FLAGS_OK(SPI_FLAG));
00349   /* Clear the flag bit */
00350   SPI->SR = (uint8_t)(~SPI_FLAG);
00351 }
00352
00353 /**
00354   * @brief  Checks whether the specified interrupt has occurred or not.
00355   * @param  SPI_IT: Specifies the SPI interrupt pending bit to check.
00356   *         This parameter can be one of the following values:
00357   *         - SPI_IT_CRCERR
00358   *         - SPI_IT_WKUP
00359   *         - SPI_IT_OVR
00360   *         - SPI_IT_MODF
00361   *         - SPI_IT_RXNE
00362   *         - SPI_IT_TXE
00363   * @retval ITStatus : Indicates the state of the SPI_IT.
00364   *         This parameter can be any of the @ref ITStatus enumeration.
00365   */
00366 ITStatus SPI_GetITStatus(SPI_IT_TypeDef SPI_IT)
00367 {
00368   ITStatus pendingbitstatus = RESET;
00369   uint8_t itpos = 0;
00370   uint8_t itmask1 = 0;
00371   uint8_t itmask2 = 0;
00372   uint8_t enablestatus = 0;
00373   assert_param(IS_SPI_GET_IT_OK(SPI_IT));
00374   /* Get the SPI IT index */
00375   itpos = (uint8_t)((uint8_t)1 << ((uint8_t)SPI_IT & (uint8_t)0x0F));
00376
00377   /* Get the SPI IT mask */
00378   itmask1 = (uint8_t)((uint8_t)SPI_IT >> (uint8_t)4);
00379   /* Set the IT mask */
00380   itmask2 = (uint8_t)((uint8_t)1 << itmask1);
00381   /* Get the SPI_ITPENDINGBIT enable bit status */
00382   enablestatus = (uint8_t)((uint8_t)SPI->SR & itmask2);
00383   /* Check the status of the specified SPI interrupt */
00384   if (((SPI->ICR & itpos) != RESET) && enablestatus)
00385   {
00386     /* SPI_ITPENDINGBIT is set */
00387     pendingbitstatus = SET;
00388   }
00389   else
00390   {
00391     /* SPI_ITPENDINGBIT is reset */
00392     pendingbitstatus = RESET;
00393   }
00394   /* Return the SPI_ITPENDINGBIT status */
00395   return  pendingbitstatus;
00396 }
00397
00398 /**
00399   * @brief  Clears the interrupt pending bits.
00400   * @param  SPI_IT: Specifies the interrupt pending bit to clear.
00401   *         This parameter can be one of the following values:
00402   *         - SPI_IT_CRCERR
00403   *         - SPI_IT_WKUP
00404   * @note   - OVR (OverRun Error) interrupt pending bit is cleared by software sequence:
00405   *         a read operation to SPI_DR register (SPI_ReceiveData()) followed by
00406   *         a read operation to SPI_SR register (SPI_GetITStatus()).
00407   *         - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
00408   *         a read/write operation to SPI_SR register (SPI_GetITStatus()) followed by
00409   *         a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
00410   * @retval None
00411   */
00412 void SPI_ClearITPendingBit(SPI_IT_TypeDef SPI_IT)
00413 {
00414   uint8_t itpos = 0;
00415   assert_param(IS_SPI_CLEAR_IT_OK(SPI_IT));
00416
00417   /* Clear  SPI_IT_CRCERR or SPI_IT_WKUP interrupt pending bits */
00418
00419   /* Get the SPI pending bit index */
00420   itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)(SPI_IT & (uint8_t)0xF0) >> 4));
00421   /* Clear the pending bit */
00422   SPI->SR = (uint8_t)(~itpos);
00423
00424 }
00425
00426 /**
00427   * @}
00428   */
00429
00430 /**
00431   * @}
00432   */
00433
00434
00435 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_spi.h Source File

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  • STM8S_StdPeriph_Driver
  • inc
stm8s_spi.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_spi.h
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all functions prototype and macros for the SPI peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Define to prevent recursive inclusion -------------------------------------*/
00029 #ifndef __STM8S_SPI_H
00030 #define __STM8S_SPI_H
00031
00032 /* Includes ------------------------------------------------------------------*/
00033 #include "stm8s.h"
00034
00035 /** @addtogroup STM8S_StdPeriph_Driver
00036   * @{
00037   */
00038
00039 /** @addtogroup SPI_Exported_Types
00040   * @{
00041   */
00042
00043 /**
00044   * @brief  SPI data direction mode
00045   * Warning: element values correspond to BDM, BDOE, RXONLY bits position
00046   */
00047 typedef enum {
00048   SPI_DATADIRECTION_2LINES_FULLDUPLEX = (uint8_t)0x00, /*!< 2-line uni-directional data mode enable */
00049   SPI_DATADIRECTION_2LINES_RXONLY     = (uint8_t)0x04, /*!< Receiver only in 2 line uni-directional data mode */
00050   SPI_DATADIRECTION_1LINE_RX          = (uint8_t)0x80, /*!< Receiver only in 1 line bi-directional data mode */
00051   SPI_DATADIRECTION_1LINE_TX          = (uint8_t)0xC0  /*!< Transmit only in 1 line bi-directional data mode */
00052 } SPI_DataDirection_TypeDef;
00053
00054 /**
00055   * @brief  SPI Slave Select management
00056   * Warning: element values correspond to LSBFIRST bit position
00057   */
00058 typedef enum
00059 {
00060   SPI_NSS_SOFT  = (uint8_t)0x02, /*!< Software slave management disabled */
00061   SPI_NSS_HARD  = (uint8_t)0x00  /*!< Software slave management enabled */
00062 } SPI_NSS_TypeDef;
00063
00064
00065 /**
00066   * @brief  SPI direction transmit/receive
00067   */
00068
00069 typedef enum {
00070   SPI_DIRECTION_RX = (uint8_t)0x00, /*!< Selects Rx receive direction in bi-directional mode */
00071   SPI_DIRECTION_TX = (uint8_t)0x01  /*!< Selects Tx transmission direction in bi-directional mode */
00072 } SPI_Direction_TypeDef;
00073
00074 /**
00075   * @brief  SPI master/slave mode
00076   * Warning: element values correspond to MSTR bit position
00077   */
00078 typedef enum {
00079   SPI_MODE_MASTER = (uint8_t)0x04, /*!< SPI Master configuration */
00080   SPI_MODE_SLAVE  = (uint8_t)0x00  /*!< SPI Slave configuration */
00081 } SPI_Mode_TypeDef;
00082
00083 /**
00084   * @brief  SPI BaudRate Prescaler
00085   * Warning: element values correspond to BR bits position
00086   */
00087 typedef enum {
00088   SPI_BAUDRATEPRESCALER_2   = (uint8_t)0x00, /*!< SPI frequency = frequency(CPU)/2 */
00089   SPI_BAUDRATEPRESCALER_4   = (uint8_t)0x08, /*!< SPI frequency = frequency(CPU)/4 */
00090   SPI_BAUDRATEPRESCALER_8   = (uint8_t)0x10, /*!< SPI frequency = frequency(CPU)/8 */
00091   SPI_BAUDRATEPRESCALER_16  = (uint8_t)0x18, /*!< SPI frequency = frequency(CPU)/16 */
00092   SPI_BAUDRATEPRESCALER_32  = (uint8_t)0x20, /*!< SPI frequency = frequency(CPU)/32 */
00093   SPI_BAUDRATEPRESCALER_64  = (uint8_t)0x28, /*!< SPI frequency = frequency(CPU)/64 */
00094   SPI_BAUDRATEPRESCALER_128 = (uint8_t)0x30, /*!< SPI frequency = frequency(CPU)/128 */
00095   SPI_BAUDRATEPRESCALER_256 = (uint8_t)0x38  /*!< SPI frequency = frequency(CPU)/256 */
00096 } SPI_BaudRatePrescaler_TypeDef;
00097
00098 /**
00099   * @brief  SPI Clock Polarity
00100   * Warning: element values correspond to CPOL bit position
00101   */
00102 typedef enum {
00103   SPI_CLOCKPOLARITY_LOW  = (uint8_t)0x00, /*!< Clock to 0 when idle */
00104   SPI_CLOCKPOLARITY_HIGH = (uint8_t)0x02  /*!< Clock to 1 when idle */
00105 } SPI_ClockPolarity_TypeDef;
00106
00107 /**
00108   * @brief  SPI Clock Phase
00109   * Warning: element values correspond to CPHA bit position
00110   */
00111 typedef enum {
00112   SPI_CLOCKPHASE_1EDGE = (uint8_t)0x00, /*!< The first clock transition is the first data capture edge */
00113   SPI_CLOCKPHASE_2EDGE = (uint8_t)0x01  /*!< The second clock transition is the first data capture edge */
00114 } SPI_ClockPhase_TypeDef;
00115
00116 /**
00117   * @brief  SPI Frame Format: MSB or LSB transmitted first
00118   * Warning: element values correspond to LSBFIRST bit position
00119   */
00120 typedef enum {
00121   SPI_FIRSTBIT_MSB = (uint8_t)0x00, /*!< MSB bit will be transmitted first */
00122   SPI_FIRSTBIT_LSB = (uint8_t)0x80  /*!< LSB bit will be transmitted first */
00123 } SPI_FirstBit_TypeDef;
00124
00125 /**
00126   * @brief  SPI CRC Transmit/Receive
00127   */
00128 typedef enum {
00129   SPI_CRC_RX = (uint8_t)0x00, /*!< Select Tx CRC register */
00130   SPI_CRC_TX = (uint8_t)0x01  /*!< Select Rx CRC register */
00131 } SPI_CRC_TypeDef;
00132
00133 /**
00134   * @brief  SPI flags definition - Warning : FLAG value = mapping position register
00135   */
00136 typedef enum {
00137   SPI_FLAG_BSY    = (uint8_t)0x80, /*!< Busy flag */
00138   SPI_FLAG_OVR    = (uint8_t)0x40, /*!< Overrun flag */
00139   SPI_FLAG_MODF   = (uint8_t)0x20, /*!< Mode fault */
00140   SPI_FLAG_CRCERR = (uint8_t)0x10, /*!< CRC error flag */
00141   SPI_FLAG_WKUP   = (uint8_t)0x08, /*!< Wake-up flag */
00142   SPI_FLAG_TXE    = (uint8_t)0x02, /*!< Transmit buffer empty */
00143   SPI_FLAG_RXNE   = (uint8_t)0x01  /*!< Receive buffer empty */
00144 } SPI_Flag_TypeDef;
00145
00146 /**
00147   * @brief  SPI_IT possible values
00148   * Elements values convention: 0xYX
00149   *   X: Position of the corresponding Interrupt
00150   *   Y: ITPENDINGBIT position
00151   */
00152 typedef enum
00153 {
00154   SPI_IT_WKUP   = (uint8_t)0x34,  /*!< Wake-up interrupt*/
00155   SPI_IT_OVR   = (uint8_t)0x65,  /*!< Overrun interrupt*/
00156   SPI_IT_MODF   = (uint8_t)0x55,  /*!< Mode fault interrupt*/
00157   SPI_IT_CRCERR = (uint8_t)0x45,  /*!< CRC error interrupt*/
00158   SPI_IT_TXE    = (uint8_t)0x17,  /*!< Transmit buffer empty interrupt*/
00159   SPI_IT_RXNE   = (uint8_t)0x06,   /*!< Receive buffer not empty interrupt*/
00160   SPI_IT_ERR    = (uint8_t)0x05   /*!< Error interrupt*/
00161 } SPI_IT_TypeDef;
00162
00163 /**
00164   * @}
00165   */
00166
00167 /* Private define ------------------------------------------------------------*/
00168
00169 /** @addtogroup SPI_Private_Macros
00170   * @brief  Macros used by the assert_param function to check the different functions parameters.
00171   * @{
00172   */
00173
00174 /**
00175   * @brief  Macro used by the assert_param function in order to check the data direction mode values
00176   */
00177 #define IS_SPI_DATA_DIRECTION_OK(MODE) (((MODE) == SPI_DATADIRECTION_2LINES_FULLDUPLEX) || \
00178                                         ((MODE) == SPI_DATADIRECTION_2LINES_RXONLY) || \
00179                                         ((MODE) == SPI_DATADIRECTION_1LINE_RX) || \
00180                                         ((MODE) == SPI_DATADIRECTION_1LINE_TX))
00181
00182 /**
00183   * @brief  Macro used by the assert_param function in order to check the mode
00184   *         half duplex data direction values
00185   */
00186 #define IS_SPI_DIRECTION_OK(DIRECTION) (((DIRECTION) == SPI_DIRECTION_RX) || \
00187                                         ((DIRECTION) == SPI_DIRECTION_TX))
00188
00189 /**
00190   * @brief  Macro used by the assert_param function in order to check the NSS
00191   *         management values
00192   */
00193 #define IS_SPI_SLAVEMANAGEMENT_OK(NSS) (((NSS) == SPI_NSS_SOFT) || \
00194                                         ((NSS) == SPI_NSS_HARD))
00195
00196
00197 /**
00198   * @brief  Macro used by the assert_param function in order to check the different
00199   *         sensitivity values for the CRC polynomial
00200   */
00201 #define IS_SPI_CRC_POLYNOMIAL_OK(POLYNOMIAL) ((POLYNOMIAL) > (uint8_t)0x00)
00202
00203 /**
00204   * @brief  Macro used by the assert_param function in order to check the SPI Mode values
00205   */
00206 #define IS_SPI_MODE_OK(MODE) (((MODE) == SPI_MODE_MASTER) || \
00207                               ((MODE) == SPI_MODE_SLAVE))
00208
00209 /**
00210   * @brief  Macro used by the assert_param function in order to check the baudrate values
00211   */
00212 #define IS_SPI_BAUDRATE_PRESCALER_OK(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
00213     ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
00214     ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
00215     ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
00216     ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
00217     ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
00218     ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
00219     ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
00220
00221 /**
00222   * @brief  Macro used by the assert_param function in order to check the polarity values
00223   */
00224 #define IS_SPI_POLARITY_OK(CLKPOL) (((CLKPOL) == SPI_CLOCKPOLARITY_LOW) || \
00225                                     ((CLKPOL) == SPI_CLOCKPOLARITY_HIGH))
00226
00227 /**
00228   * @brief  Macro used by the assert_param function in order to check the phase values
00229   */
00230 #define IS_SPI_PHASE_OK(CLKPHA) (((CLKPHA) == SPI_CLOCKPHASE_1EDGE) || \
00231                                  ((CLKPHA) == SPI_CLOCKPHASE_2EDGE))
00232
00233 /**
00234   * @brief  Macro used by the assert_param function in order to check the first
00235   *         bit to be transmited values
00236   */
00237 #define IS_SPI_FIRSTBIT_OK(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
00238                                  ((BIT) == SPI_FIRSTBIT_LSB))
00239
00240 /**
00241   * @brief  Macro used by the assert_param function in order to check the CRC
00242   *         Transmit/Receive
00243   */
00244 #define IS_SPI_CRC_OK(CRC) (((CRC) == SPI_CRC_TX) || \
00245                             ((CRC) == SPI_CRC_RX))
00246
00247 /**
00248   * @brief  Macro used by the assert_param function in order to check the
00249   *         different flags values
00250   */
00251 #define IS_SPI_FLAGS_OK(FLAG) (((FLAG) == SPI_FLAG_OVR) || \
00252                                ((FLAG) == SPI_FLAG_MODF) || \
00253                                ((FLAG) == SPI_FLAG_CRCERR) || \
00254                                ((FLAG) == SPI_FLAG_WKUP) || \
00255                                ((FLAG) == SPI_FLAG_TXE) || \
00256                                ((FLAG) == SPI_FLAG_RXNE) || \
00257                                ((FLAG) == SPI_FLAG_BSY))
00258
00259 /**
00260   * @brief  Macro used by the assert_param function in order to check the
00261   *         different sensitivity values for the flag that can be cleared
00262   *         by writing 0
00263   */
00264 #define IS_SPI_CLEAR_FLAGS_OK(FLAG) (((FLAG) == SPI_FLAG_CRCERR) || \
00265                                      ((FLAG) == SPI_FLAG_WKUP))
00266
00267 /**
00268   * @brief  Macro used by the assert_param function in order to check the
00269   *        different sensitivity values for the Interrupts
00270   */
00271 #define IS_SPI_CONFIG_IT_OK(Interrupt) (((Interrupt) == SPI_IT_TXE)  || \
00272                                         ((Interrupt) == SPI_IT_RXNE)  || \
00273                                         ((Interrupt) == SPI_IT_ERR) || \
00274                                         ((Interrupt) == SPI_IT_WKUP))
00275
00276 /**
00277   * @brief  Macro used by the assert_param function in order to check the
00278   *         different sensitivity values for the pending bit
00279   */
00280 #define IS_SPI_GET_IT_OK(ITPendingBit) (((ITPendingBit) == SPI_IT_OVR)  || \
00281                                         ((ITPendingBit) == SPI_IT_MODF) || \
00282                                         ((ITPendingBit) == SPI_IT_CRCERR) || \
00283                                         ((ITPendingBit) == SPI_IT_WKUP) || \
00284                                         ((ITPendingBit) == SPI_IT_TXE)  || \
00285                                         ((ITPendingBit) == SPI_IT_RXNE))
00286
00287 /**
00288   * @brief  Macro used by the assert_param function in order to check the
00289   *         different sensitivity values for the pending bit that can be cleared
00290   *         by writing 0
00291   */
00292 #define IS_SPI_CLEAR_IT_OK(ITPendingBit) (((ITPendingBit) == SPI_IT_CRCERR) || \
00293     ((ITPendingBit) == SPI_IT_WKUP))
00294
00295 /**
00296   * @}
00297   */
00298
00299 /** @addtogroup SPI_Exported_Functions
00300   * @{
00301   */
00302 void SPI_DeInit(void);
00303 void SPI_Init(SPI_FirstBit_TypeDef FirstBit,
00304               SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler,
00305               SPI_Mode_TypeDef Mode, SPI_ClockPolarity_TypeDef ClockPolarity,
00306               SPI_ClockPhase_TypeDef ClockPhase,
00307               SPI_DataDirection_TypeDef Data_Direction,
00308               SPI_NSS_TypeDef Slave_Management, uint8_t CRCPolynomial);
00309 void SPI_Cmd(FunctionalState NewState);
00310 void SPI_ITConfig(SPI_IT_TypeDef SPI_IT, FunctionalState NewState);
00311 void SPI_SendData(uint8_t Data);
00312 uint8_t SPI_ReceiveData(void);
00313 void SPI_NSSInternalSoftwareCmd(FunctionalState NewState);
00314 void SPI_TransmitCRC(void);
00315 void SPI_CalculateCRCCmd(FunctionalState NewState);
00316 uint8_t SPI_GetCRC(SPI_CRC_TypeDef SPI_CRC);
00317 void SPI_ResetCRC(void);
00318 uint8_t SPI_GetCRCPolynomial(void);
00319 void SPI_BiDirectionalLineConfig(SPI_Direction_TypeDef SPI_Direction);
00320 FlagStatus SPI_GetFlagStatus(SPI_Flag_TypeDef SPI_FLAG);
00321 void SPI_ClearFlag(SPI_Flag_TypeDef SPI_FLAG);
00322 ITStatus SPI_GetITStatus(SPI_IT_TypeDef SPI_IT);
00323 void SPI_ClearITPendingBit(SPI_IT_TypeDef SPI_IT);
00324
00325 /**
00326   * @}
00327   */
00328
00329 #endif /* __STM8S_SPI_H */
00330
00331 /**
00332   * @}
00333   */
00334
00335
00336 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_tim1.c Source File

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  • STM8S_StdPeriph_Driver
  • src
stm8s_tim1.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_tim1.c
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all the functions for the TIM1 peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm8s_tim1.h"
00030
00031 /** @addtogroup STM8S_StdPeriph_Driver
00032   * @{
00033   */
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 /* Private macro -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038 /* Private function prototypes -----------------------------------------------*/
00039 static void TI1_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection,
00040                        uint8_t TIM1_ICFilter);
00041 static void TI2_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection,
00042                        uint8_t TIM1_ICFilter);
00043 static void TI3_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection,
00044                        uint8_t TIM1_ICFilter);
00045 static void TI4_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection,
00046                        uint8_t TIM1_ICFilter);
00047
00048 /**
00049   * @addtogroup TIM1_Public_Functions
00050   * @{
00051   */
00052
00053 /**
00054   * @brief  Deinitializes the TIM1 peripheral registers to their default reset values.
00055   * @param  None
00056   * @retval None
00057   */
00058 void TIM1_DeInit(void)
00059 {
00060   TIM1->CR1  = TIM1_CR1_RESET_VALUE;
00061   TIM1->CR2  = TIM1_CR2_RESET_VALUE;
00062   TIM1->SMCR = TIM1_SMCR_RESET_VALUE;
00063   TIM1->ETR  = TIM1_ETR_RESET_VALUE;
00064   TIM1->IER  = TIM1_IER_RESET_VALUE;
00065   TIM1->SR2  = TIM1_SR2_RESET_VALUE;
00066   /* Disable channels */
00067   TIM1->CCER1 = TIM1_CCER1_RESET_VALUE;
00068   TIM1->CCER2 = TIM1_CCER2_RESET_VALUE;
00069   /* Configure channels as inputs: it is necessary if lock level is equal to 2 or 3 */
00070   TIM1->CCMR1 = 0x01;
00071   TIM1->CCMR2 = 0x01;
00072   TIM1->CCMR3 = 0x01;
00073   TIM1->CCMR4 = 0x01;
00074   /* Then reset channel registers: it also works if lock level is equal to 2 or 3 */
00075   TIM1->CCER1 = TIM1_CCER1_RESET_VALUE;
00076   TIM1->CCER2 = TIM1_CCER2_RESET_VALUE;
00077   TIM1->CCMR1 = TIM1_CCMR1_RESET_VALUE;
00078   TIM1->CCMR2 = TIM1_CCMR2_RESET_VALUE;
00079   TIM1->CCMR3 = TIM1_CCMR3_RESET_VALUE;
00080   TIM1->CCMR4 = TIM1_CCMR4_RESET_VALUE;
00081   TIM1->CNTRH = TIM1_CNTRH_RESET_VALUE;
00082   TIM1->CNTRL = TIM1_CNTRL_RESET_VALUE;
00083   TIM1->PSCRH = TIM1_PSCRH_RESET_VALUE;
00084   TIM1->PSCRL = TIM1_PSCRL_RESET_VALUE;
00085   TIM1->ARRH  = TIM1_ARRH_RESET_VALUE;
00086   TIM1->ARRL  = TIM1_ARRL_RESET_VALUE;
00087   TIM1->CCR1H = TIM1_CCR1H_RESET_VALUE;
00088   TIM1->CCR1L = TIM1_CCR1L_RESET_VALUE;
00089   TIM1->CCR2H = TIM1_CCR2H_RESET_VALUE;
00090   TIM1->CCR2L = TIM1_CCR2L_RESET_VALUE;
00091   TIM1->CCR3H = TIM1_CCR3H_RESET_VALUE;
00092   TIM1->CCR3L = TIM1_CCR3L_RESET_VALUE;
00093   TIM1->CCR4H = TIM1_CCR4H_RESET_VALUE;
00094   TIM1->CCR4L = TIM1_CCR4L_RESET_VALUE;
00095   TIM1->OISR  = TIM1_OISR_RESET_VALUE;
00096   TIM1->EGR   = 0x01; /* TIM1_EGR_UG */
00097   TIM1->DTR   = TIM1_DTR_RESET_VALUE;
00098   TIM1->BKR   = TIM1_BKR_RESET_VALUE;
00099   TIM1->RCR   = TIM1_RCR_RESET_VALUE;
00100   TIM1->SR1   = TIM1_SR1_RESET_VALUE;
00101 }
00102
00103 /**
00104   * @brief  Initializes the TIM1 Time Base Unit according to the specified parameters.
00105   * @param  TIM1_Prescaler specifies the Prescaler value.
00106   * @param  TIM1_CounterMode specifies the counter mode  from @ref TIM1_CounterMode_TypeDef .
00107   * @param  TIM1_Period specifies the Period value.
00108   * @param  TIM1_RepetitionCounter specifies the Repetition counter value
00109   * @retval None
00110   */
00111 void TIM1_TimeBaseInit(uint16_t TIM1_Prescaler,
00112                        TIM1_CounterMode_TypeDef TIM1_CounterMode,
00113                        uint16_t TIM1_Period,
00114                        uint8_t TIM1_RepetitionCounter)
00115 {
00116   /* Check parameters */
00117   assert_param(IS_TIM1_COUNTER_MODE_OK(TIM1_CounterMode));
00118
00119   /* Set the Autoreload value */
00120   TIM1->ARRH = (uint8_t)(TIM1_Period >> 8);
00121   TIM1->ARRL = (uint8_t)(TIM1_Period);
00122
00123   /* Set the Prescaler value */
00124   TIM1->PSCRH = (uint8_t)(TIM1_Prescaler >> 8);
00125   TIM1->PSCRL = (uint8_t)(TIM1_Prescaler);
00126
00127   /* Select the Counter Mode */
00128   TIM1->CR1 = (uint8_t)((uint8_t)(TIM1->CR1 & (uint8_t)(~(TIM1_CR1_CMS | TIM1_CR1_DIR)))
00129                         | (uint8_t)(TIM1_CounterMode));
00130
00131   /* Set the Repetition Counter value */
00132   TIM1->RCR = TIM1_RepetitionCounter;
00133 }
00134
00135 /**
00136   * @brief  Initializes the TIM1 Channel1 according to the specified parameters.
00137   * @param  TIM1_OCMode specifies the Output Compare mode from
00138   *         @ref TIM1_OCMode_TypeDef.
00139   * @param  TIM1_OutputState specifies the Output State from
00140   *         @ref TIM1_OutputState_TypeDef.
00141   * @param  TIM1_OutputNState specifies the Complementary Output State
00142   *         from @ref TIM1_OutputNState_TypeDef.
00143   * @param  TIM1_Pulse specifies the Pulse width value.
00144   * @param  TIM1_OCPolarity specifies the Output Compare Polarity from
00145   *         @ref TIM1_OCPolarity_TypeDef.
00146   * @param  TIM1_OCNPolarity specifies the Complementary Output Compare Polarity
00147   *         from @ref TIM1_OCNPolarity_TypeDef.
00148   * @param  TIM1_OCIdleState specifies the Output Compare Idle State from
00149   *         @ref TIM1_OCIdleState_TypeDef.
00150   * @param  TIM1_OCNIdleState specifies the Complementary Output Compare Idle
00151   *         State from @ref TIM1_OCIdleState_TypeDef.
00152   * @retval None
00153   */
00154 void TIM1_OC1Init(TIM1_OCMode_TypeDef TIM1_OCMode,
00155                   TIM1_OutputState_TypeDef TIM1_OutputState,
00156                   TIM1_OutputNState_TypeDef TIM1_OutputNState,
00157                   uint16_t TIM1_Pulse,
00158                   TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
00159                   TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
00160                   TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
00161                   TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
00162 {
00163   /* Check the parameters */
00164   assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));
00165   assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));
00166   assert_param(IS_TIM1_OUTPUTN_STATE_OK(TIM1_OutputNState));
00167   assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
00168   assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));
00169   assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));
00170   assert_param(IS_TIM1_OCNIDLE_STATE_OK(TIM1_OCNIdleState));
00171
00172   /* Disable the Channel 1: Reset the CCE Bit, Set the Output State ,
00173   the Output N State, the Output Polarity & the Output N Polarity*/
00174   TIM1->CCER1 &= (uint8_t)(~( TIM1_CCER1_CC1E | TIM1_CCER1_CC1NE
00175                              | TIM1_CCER1_CC1P | TIM1_CCER1_CC1NP));
00176   /* Set the Output State & Set the Output N State & Set the Output Polarity &
00177   Set the Output N Polarity */
00178   TIM1->CCER1 |= (uint8_t)((uint8_t)((uint8_t)(TIM1_OutputState & TIM1_CCER1_CC1E)
00179                                      | (uint8_t)(TIM1_OutputNState & TIM1_CCER1_CC1NE))
00180                            | (uint8_t)( (uint8_t)(TIM1_OCPolarity  & TIM1_CCER1_CC1P)
00181                                        | (uint8_t)(TIM1_OCNPolarity & TIM1_CCER1_CC1NP)));
00182
00183   /* Reset the Output Compare Bits & Set the Output Compare Mode */
00184   TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_OCM)) |
00185                           (uint8_t)TIM1_OCMode);
00186
00187   /* Reset the Output Idle state & the Output N Idle state bits */
00188   TIM1->OISR &= (uint8_t)(~(TIM1_OISR_OIS1 | TIM1_OISR_OIS1N));
00189   /* Set the Output Idle state & the Output N Idle state configuration */
00190   TIM1->OISR |= (uint8_t)((uint8_t)( TIM1_OCIdleState & TIM1_OISR_OIS1 ) |
00191                           (uint8_t)( TIM1_OCNIdleState & TIM1_OISR_OIS1N ));
00192
00193   /* Set the Pulse value */
00194   TIM1->CCR1H = (uint8_t)(TIM1_Pulse >> 8);
00195   TIM1->CCR1L = (uint8_t)(TIM1_Pulse);
00196 }
00197
00198 /**
00199   * @brief  Initializes the TIM1 Channel2 according to the specified parameters.
00200   * @param  TIM1_OCMode specifies the Output Compare mode from
00201   *         @ref TIM1_OCMode_TypeDef.
00202   * @param  TIM1_OutputState specifies the Output State from
00203   *         @ref TIM1_OutputState_TypeDef.
00204   * @param  TIM1_OutputNState specifies the Complementary Output State from
00205   *         @ref TIM1_OutputNState_TypeDef.
00206   * @param  TIM1_Pulse specifies the Pulse width value.
00207   * @param  TIM1_OCPolarity specifies the Output Compare Polarity from
00208   *         @ref TIM1_OCPolarity_TypeDef.
00209   * @param  TIM1_OCNPolarity specifies the Complementary Output Compare Polarity
00210   *         from @ref TIM1_OCNPolarity_TypeDef.
00211   * @param  TIM1_OCIdleState specifies the Output Compare Idle State from
00212   *         @ref TIM1_OCIdleState_TypeDef.
00213   * @param  TIM1_OCNIdleState specifies the Complementary Output Compare Idle
00214   *         State from @ref TIM1_OCIdleState_TypeDef.
00215   * @retval None
00216   */
00217 void TIM1_OC2Init(TIM1_OCMode_TypeDef TIM1_OCMode,
00218                   TIM1_OutputState_TypeDef TIM1_OutputState,
00219                   TIM1_OutputNState_TypeDef TIM1_OutputNState,
00220                   uint16_t TIM1_Pulse,
00221                   TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
00222                   TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
00223                   TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
00224                   TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
00225 {
00226   /* Check the parameters */
00227   assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));
00228   assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));
00229   assert_param(IS_TIM1_OUTPUTN_STATE_OK(TIM1_OutputNState));
00230   assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
00231   assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));
00232   assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));
00233   assert_param(IS_TIM1_OCNIDLE_STATE_OK(TIM1_OCNIdleState));
00234
00235   /* Disable the Channel 1: Reset the CCE Bit, Set the Output State ,
00236   the Output N State, the Output Polarity & the Output N Polarity*/
00237   TIM1->CCER1 &= (uint8_t)(~( TIM1_CCER1_CC2E | TIM1_CCER1_CC2NE |
00238                              TIM1_CCER1_CC2P | TIM1_CCER1_CC2NP));
00239
00240   /* Set the Output State & Set the Output N State & Set the Output Polarity &
00241   Set the Output N Polarity */
00242   TIM1->CCER1 |= (uint8_t)((uint8_t)((uint8_t)(TIM1_OutputState & TIM1_CCER1_CC2E  ) |
00243                                      (uint8_t)(TIM1_OutputNState & TIM1_CCER1_CC2NE )) |
00244                            (uint8_t)((uint8_t)(TIM1_OCPolarity  & TIM1_CCER1_CC2P  ) |
00245                                      (uint8_t)(TIM1_OCNPolarity & TIM1_CCER1_CC2NP )));
00246
00247   /* Reset the Output Compare Bits & Set the Output Compare Mode */
00248   TIM1->CCMR2 = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~TIM1_CCMR_OCM)) |
00249                           (uint8_t)TIM1_OCMode);
00250
00251   /* Reset the Output Idle state & the Output N Idle state bits */
00252   TIM1->OISR &= (uint8_t)(~(TIM1_OISR_OIS2 | TIM1_OISR_OIS2N));
00253   /* Set the Output Idle state & the Output N Idle state configuration */
00254   TIM1->OISR |= (uint8_t)((uint8_t)(TIM1_OISR_OIS2 & TIM1_OCIdleState) |
00255                           (uint8_t)(TIM1_OISR_OIS2N & TIM1_OCNIdleState));
00256
00257   /* Set the Pulse value */
00258   TIM1->CCR2H = (uint8_t)(TIM1_Pulse >> 8);
00259   TIM1->CCR2L = (uint8_t)(TIM1_Pulse);
00260 }
00261
00262 /**
00263   * @brief  Initializes the TIM1 Channel3 according to the specified parameters.
00264   * @param  TIM1_OCMode specifies the Output Compare mode  from
00265   *         @ref TIM1_OCMode_TypeDef.
00266   * @param  TIM1_OutputState specifies the Output State
00267   *         from @ref TIM1_OutputState_TypeDef.
00268   * @param  TIM1_OutputNState specifies the Complementary Output State
00269   *         from @ref TIM1_OutputNState_TypeDef.
00270   * @param  TIM1_Pulse specifies the Pulse width value.
00271   * @param  TIM1_OCPolarity specifies the Output Compare Polarity  from
00272   *         @ref TIM1_OCPolarity_TypeDef.
00273   * @param  TIM1_OCNPolarity specifies the Complementary  Output Compare
00274   *         Polarity from @ref TIM1_OCNPolarity_TypeDef.
00275   * @param  TIM1_OCIdleState specifies the Output Compare Idle State
00276   *         from @ref TIM1_OCIdleState_TypeDef.
00277   * @param  TIM1_OCNIdleState specifies the Complementary Output Compare
00278   *         Idle State  from @ref TIM1_OCIdleState_TypeDef.
00279   * @retval None
00280   */
00281 void TIM1_OC3Init(TIM1_OCMode_TypeDef TIM1_OCMode,
00282                   TIM1_OutputState_TypeDef TIM1_OutputState,
00283                   TIM1_OutputNState_TypeDef TIM1_OutputNState,
00284                   uint16_t TIM1_Pulse,
00285                   TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
00286                   TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
00287                   TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
00288                   TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
00289 {
00290   /* Check the parameters */
00291   assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));
00292   assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));
00293   assert_param(IS_TIM1_OUTPUTN_STATE_OK(TIM1_OutputNState));
00294   assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
00295   assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));
00296   assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));
00297   assert_param(IS_TIM1_OCNIDLE_STATE_OK(TIM1_OCNIdleState));
00298
00299   /* Disable the Channel 1: Reset the CCE Bit, Set the Output State ,
00300   the Output N State, the Output Polarity & the Output N Polarity*/
00301   TIM1->CCER2 &= (uint8_t)(~( TIM1_CCER2_CC3E | TIM1_CCER2_CC3NE |
00302                              TIM1_CCER2_CC3P | TIM1_CCER2_CC3NP));
00303   /* Set the Output State & Set the Output N State & Set the Output Polarity &
00304   Set the Output N Polarity */
00305   TIM1->CCER2 |= (uint8_t)((uint8_t)((uint8_t)(TIM1_OutputState  & TIM1_CCER2_CC3E   ) |
00306                                      (uint8_t)(TIM1_OutputNState & TIM1_CCER2_CC3NE  )) |
00307                            (uint8_t)((uint8_t)(TIM1_OCPolarity   & TIM1_CCER2_CC3P   ) |
00308                                      (uint8_t)(TIM1_OCNPolarity  & TIM1_CCER2_CC3NP  )));
00309
00310   /* Reset the Output Compare Bits & Set the Output Compare Mode */
00311   TIM1->CCMR3 = (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~TIM1_CCMR_OCM)) |
00312                           (uint8_t)TIM1_OCMode);
00313
00314   /* Reset the Output Idle state & the Output N Idle state bits */
00315   TIM1->OISR &= (uint8_t)(~(TIM1_OISR_OIS3 | TIM1_OISR_OIS3N));
00316   /* Set the Output Idle state & the Output N Idle state configuration */
00317   TIM1->OISR |= (uint8_t)((uint8_t)(TIM1_OISR_OIS3 & TIM1_OCIdleState) |
00318                           (uint8_t)(TIM1_OISR_OIS3N & TIM1_OCNIdleState));
00319
00320   /* Set the Pulse value */
00321   TIM1->CCR3H = (uint8_t)(TIM1_Pulse >> 8);
00322   TIM1->CCR3L = (uint8_t)(TIM1_Pulse);
00323 }
00324
00325 /**
00326   * @brief  Initializes the TIM1 Channel4 according to the specified parameters.
00327   * @param  TIM1_OCMode specifies the Output Compare mode  from
00328   *         @ref TIM1_OCMode_TypeDef.
00329   * @param  TIM1_OutputState specifies the Output State
00330   *         from @ref TIM1_OutputState_TypeDef.
00331   * @param  TIM1_Pulse specifies the Pulse width  value.
00332   * @param  TIM1_OCPolarity specifies the Output Compare Polarity
00333   *         from @ref TIM1_OCPolarity_TypeDef.
00334   * @param  TIM1_OCIdleState specifies the Output Compare Idle State
00335   *         from @ref TIM1_OCIdleState_TypeDef.
00336   * @retval None
00337   */
00338 void TIM1_OC4Init(TIM1_OCMode_TypeDef TIM1_OCMode,
00339                   TIM1_OutputState_TypeDef TIM1_OutputState,
00340                   uint16_t TIM1_Pulse,
00341                   TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
00342                   TIM1_OCIdleState_TypeDef TIM1_OCIdleState)
00343 {
00344   /* Check the parameters */
00345   assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));
00346   assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));
00347   assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
00348   assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));
00349
00350   /* Disable the Channel 4: Reset the CCE Bit */
00351   TIM1->CCER2 &= (uint8_t)(~(TIM1_CCER2_CC4E | TIM1_CCER2_CC4P));
00352   /* Set the Output State  &  the Output Polarity */
00353   TIM1->CCER2 |= (uint8_t)((uint8_t)(TIM1_OutputState & TIM1_CCER2_CC4E ) |
00354                            (uint8_t)(TIM1_OCPolarity  & TIM1_CCER2_CC4P ));
00355
00356   /* Reset the Output Compare Bit  and Set the Output Compare Mode */
00357   TIM1->CCMR4 = (uint8_t)((uint8_t)(TIM1->CCMR4 & (uint8_t)(~TIM1_CCMR_OCM)) |
00358                           TIM1_OCMode);
00359
00360   /* Set the Output Idle state */
00361   if (TIM1_OCIdleState != TIM1_OCIDLESTATE_RESET)
00362   {
00363     TIM1->OISR |= (uint8_t)(~TIM1_CCER2_CC4P);
00364   }
00365   else
00366   {
00367     TIM1->OISR &= (uint8_t)(~TIM1_OISR_OIS4);
00368   }
00369
00370   /* Set the Pulse value */
00371   TIM1->CCR4H = (uint8_t)(TIM1_Pulse >> 8);
00372   TIM1->CCR4L = (uint8_t)(TIM1_Pulse);
00373 }
00374
00375 /**
00376   * @brief  Configures the Break feature, dead time, Lock level, the OSSI,
00377   *         and the AOE(automatic output enable).
00378   * @param  TIM1_OSSIState specifies the OSSIS State from @ref TIM1_OSSIState_TypeDef.
00379   * @param  TIM1_LockLevel specifies the lock level from @ref TIM1_LockLevel_TypeDef.
00380   * @param  TIM1_DeadTime specifies the dead time value.
00381   * @param  TIM1_Break specifies the Break state @ref TIM1_BreakState_TypeDef.
00382   * @param  TIM1_BreakPolarity specifies the Break polarity from
00383   *         @ref TIM1_BreakPolarity_TypeDef.
00384   * @param  TIM1_AutomaticOutput specifies the Automatic Output configuration
00385   *         from @ref TIM1_AutomaticOutput_TypeDef.
00386   * @retval None
00387   */
00388 void TIM1_BDTRConfig(TIM1_OSSIState_TypeDef TIM1_OSSIState,
00389                      TIM1_LockLevel_TypeDef TIM1_LockLevel,
00390                      uint8_t TIM1_DeadTime,
00391                      TIM1_BreakState_TypeDef TIM1_Break,
00392                      TIM1_BreakPolarity_TypeDef TIM1_BreakPolarity,
00393                      TIM1_AutomaticOutput_TypeDef TIM1_AutomaticOutput)
00394 {
00395   /* Check the parameters */
00396   assert_param(IS_TIM1_OSSI_STATE_OK(TIM1_OSSIState));
00397   assert_param(IS_TIM1_LOCK_LEVEL_OK(TIM1_LockLevel));
00398   assert_param(IS_TIM1_BREAK_STATE_OK(TIM1_Break));
00399   assert_param(IS_TIM1_BREAK_POLARITY_OK(TIM1_BreakPolarity));
00400   assert_param(IS_TIM1_AUTOMATIC_OUTPUT_STATE_OK(TIM1_AutomaticOutput));
00401
00402   TIM1->DTR = (uint8_t)(TIM1_DeadTime);
00403   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSI State,
00404   the dead time value  and the Automatic Output Enable Bit */
00405
00406   TIM1->BKR  =  (uint8_t)((uint8_t)(TIM1_OSSIState | (uint8_t)TIM1_LockLevel)  |
00407                           (uint8_t)((uint8_t)(TIM1_Break | (uint8_t)TIM1_BreakPolarity)  |
00408                           (uint8_t)TIM1_AutomaticOutput));
00409 }
00410
00411 /**
00412   * @brief  Initializes the TIM1 peripheral according to the specified parameters.
00413   * @param  TIM1_Channel specifies the input capture channel from TIM1_Channel_TypeDef.
00414   * @param  TIM1_ICPolarity specifies the Input capture polarity from
00415   *         TIM1_ICPolarity_TypeDef .
00416   * @param  TIM1_ICSelection specifies the Input capture source selection from
00417   *         TIM1_ICSelection_TypeDef.
00418   * @param  TIM1_ICPrescaler specifies the Input capture Prescaler from
00419   *         TIM1_ICPSC_TypeDef.
00420   * @param  TIM1_ICFilter specifies the Input capture filter value.
00421   * @retval None
00422   */
00423 void TIM1_ICInit(TIM1_Channel_TypeDef TIM1_Channel,
00424                  TIM1_ICPolarity_TypeDef TIM1_ICPolarity,
00425                  TIM1_ICSelection_TypeDef TIM1_ICSelection,
00426                  TIM1_ICPSC_TypeDef TIM1_ICPrescaler,
00427                  uint8_t TIM1_ICFilter)
00428 {
00429   /* Check the parameters */
00430   assert_param(IS_TIM1_CHANNEL_OK(TIM1_Channel));
00431   assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_ICPolarity));
00432   assert_param(IS_TIM1_IC_SELECTION_OK(TIM1_ICSelection));
00433   assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_ICPrescaler));
00434   assert_param(IS_TIM1_IC_FILTER_OK(TIM1_ICFilter));
00435
00436   if (TIM1_Channel == TIM1_CHANNEL_1)
00437   {
00438     /* TI1 Configuration */
00439     TI1_Config((uint8_t)TIM1_ICPolarity,
00440                (uint8_t)TIM1_ICSelection,
00441                (uint8_t)TIM1_ICFilter);
00442     /* Set the Input Capture Prescaler value */
00443     TIM1_SetIC1Prescaler(TIM1_ICPrescaler);
00444   }
00445   else if (TIM1_Channel == TIM1_CHANNEL_2)
00446   {
00447     /* TI2 Configuration */
00448     TI2_Config((uint8_t)TIM1_ICPolarity,
00449                (uint8_t)TIM1_ICSelection,
00450                (uint8_t)TIM1_ICFilter);
00451     /* Set the Input Capture Prescaler value */
00452     TIM1_SetIC2Prescaler(TIM1_ICPrescaler);
00453   }
00454   else if (TIM1_Channel == TIM1_CHANNEL_3)
00455   {
00456     /* TI3 Configuration */
00457     TI3_Config((uint8_t)TIM1_ICPolarity,
00458                (uint8_t)TIM1_ICSelection,
00459                (uint8_t)TIM1_ICFilter);
00460     /* Set the Input Capture Prescaler value */
00461     TIM1_SetIC3Prescaler(TIM1_ICPrescaler);
00462   }
00463   else
00464   {
00465     /* TI4 Configuration */
00466     TI4_Config((uint8_t)TIM1_ICPolarity,
00467                (uint8_t)TIM1_ICSelection,
00468                (uint8_t)TIM1_ICFilter);
00469     /* Set the Input Capture Prescaler value */
00470     TIM1_SetIC4Prescaler(TIM1_ICPrescaler);
00471   }
00472 }
00473
00474 /**
00475   * @brief  Configures the TIM1 peripheral in PWM Input Mode according to the
00476   *         specified parameters.
00477   * @param  TIM1_Channel specifies the input capture channel from
00478   *         @ref TIM1_Channel_TypeDef.
00479   * @param  TIM1_ICPolarity specifies the Input capture polarity from
00480   *         @ref TIM1_ICPolarity_TypeDef .
00481   * @param  TIM1_ICSelection specifies the Input capture source selection  from
00482   *         @ref TIM1_ICSelection_TypeDef.
00483   * @param  TIM1_ICPrescaler specifies the Input capture Prescaler from
00484   *         @ref TIM1_ICPSC_TypeDef.
00485   * @param  TIM1_ICFilter specifies the Input capture filter value.
00486   * @retval None
00487   */
00488 void TIM1_PWMIConfig(TIM1_Channel_TypeDef TIM1_Channel,
00489                      TIM1_ICPolarity_TypeDef TIM1_ICPolarity,
00490                      TIM1_ICSelection_TypeDef TIM1_ICSelection,
00491                      TIM1_ICPSC_TypeDef TIM1_ICPrescaler,
00492                      uint8_t TIM1_ICFilter)
00493 {
00494   uint8_t icpolarity = TIM1_ICPOLARITY_RISING;
00495   uint8_t icselection = TIM1_ICSELECTION_DIRECTTI;
00496
00497   /* Check the parameters */
00498   assert_param(IS_TIM1_PWMI_CHANNEL_OK(TIM1_Channel));
00499   assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_ICPolarity));
00500   assert_param(IS_TIM1_IC_SELECTION_OK(TIM1_ICSelection));
00501   assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_ICPrescaler));
00502
00503   /* Select the Opposite Input Polarity */
00504   if (TIM1_ICPolarity != TIM1_ICPOLARITY_FALLING)
00505   {
00506     icpolarity = TIM1_ICPOLARITY_FALLING;
00507   }
00508   else
00509   {
00510     icpolarity = TIM1_ICPOLARITY_RISING;
00511   }
00512
00513   /* Select the Opposite Input */
00514   if (TIM1_ICSelection == TIM1_ICSELECTION_DIRECTTI)
00515   {
00516     icselection = TIM1_ICSELECTION_INDIRECTTI;
00517   }
00518   else
00519   {
00520     icselection = TIM1_ICSELECTION_DIRECTTI;
00521   }
00522
00523   if (TIM1_Channel == TIM1_CHANNEL_1)
00524   {
00525     /* TI1 Configuration */
00526     TI1_Config((uint8_t)TIM1_ICPolarity, (uint8_t)TIM1_ICSelection,
00527                (uint8_t)TIM1_ICFilter);
00528
00529     /* Set the Input Capture Prescaler value */
00530     TIM1_SetIC1Prescaler(TIM1_ICPrescaler);
00531
00532     /* TI2 Configuration */
00533     TI2_Config(icpolarity, icselection, TIM1_ICFilter);
00534
00535     /* Set the Input Capture Prescaler value */
00536     TIM1_SetIC2Prescaler(TIM1_ICPrescaler);
00537   }
00538   else
00539   {
00540     /* TI2 Configuration */
00541     TI2_Config((uint8_t)TIM1_ICPolarity, (uint8_t)TIM1_ICSelection,
00542                (uint8_t)TIM1_ICFilter);
00543
00544     /* Set the Input Capture Prescaler value */
00545     TIM1_SetIC2Prescaler(TIM1_ICPrescaler);
00546
00547     /* TI1 Configuration */
00548     TI1_Config(icpolarity, icselection, TIM1_ICFilter);
00549
00550     /* Set the Input Capture Prescaler value */
00551     TIM1_SetIC1Prescaler(TIM1_ICPrescaler);
00552   }
00553 }
00554
00555 /**
00556   * @brief  Enables or disables the TIM1 peripheral.
00557   * @param  NewState new state of the TIM1 peripheral.
00558   *         This parameter can be ENABLE or DISABLE.
00559   * @retval None
00560   */
00561 void TIM1_Cmd(FunctionalState NewState)
00562 {
00563   /* Check the parameters */
00564   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00565
00566   /* set or Reset the CEN Bit */
00567   if (NewState != DISABLE)
00568   {
00569     TIM1->CR1 |= TIM1_CR1_CEN;
00570   }
00571   else
00572   {
00573     TIM1->CR1 &= (uint8_t)(~TIM1_CR1_CEN);
00574   }
00575 }
00576
00577 /**
00578   * @brief  Enables or disables the TIM1 peripheral Main Outputs.
00579   * @param  NewState new state of the TIM1 peripheral.
00580   *         This parameter can be ENABLE or DISABLE.
00581   * @retval None
00582   */
00583 void TIM1_CtrlPWMOutputs(FunctionalState NewState)
00584 {
00585   /* Check the parameters */
00586   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00587
00588   /* Set or Reset the MOE Bit */
00589
00590   if (NewState != DISABLE)
00591   {
00592     TIM1->BKR |= TIM1_BKR_MOE;
00593   }
00594   else
00595   {
00596     TIM1->BKR &= (uint8_t)(~TIM1_BKR_MOE);
00597   }
00598 }
00599
00600 /**
00601   * @brief  Enables or disables the specified TIM1 interrupts.
00602   * @param  NewState new state of the TIM1 peripheral.
00603   *         This parameter can be: ENABLE or DISABLE.
00604   * @param  TIM1_IT specifies the TIM1 interrupts sources to be enabled or disabled.
00605   *         This parameter can be any combination of the following values:
00606   *           - TIM1_IT_UPDATE: TIM1 update Interrupt source
00607   *           - TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source
00608   *           - TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source
00609   *           - TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source
00610   *           - TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source
00611   *           - TIM1_IT_CCUpdate: TIM1 Capture Compare Update Interrupt source
00612   *           - TIM1_IT_TRIGGER: TIM1 Trigger Interrupt source
00613   *           - TIM1_IT_BREAK: TIM1 Break Interrupt source
00614   * @param  NewState new state of the TIM1 peripheral.
00615   * @retval None
00616   */
00617 void TIM1_ITConfig(TIM1_IT_TypeDef  TIM1_IT, FunctionalState NewState)
00618 {
00619   /* Check the parameters */
00620   assert_param(IS_TIM1_IT_OK(TIM1_IT));
00621   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00622
00623   if (NewState != DISABLE)
00624   {
00625     /* Enable the Interrupt sources */
00626     TIM1->IER |= (uint8_t)TIM1_IT;
00627   }
00628   else
00629   {
00630     /* Disable the Interrupt sources */
00631     TIM1->IER &= (uint8_t)(~(uint8_t)TIM1_IT);
00632   }
00633 }
00634
00635 /**
00636   * @brief  Configures the TIM1 internal Clock.
00637   * @param  None
00638   * @retval None
00639   */
00640 void TIM1_InternalClockConfig(void)
00641 {
00642   /* Disable slave mode to clock the prescaler directly with the internal clock */
00643   TIM1->SMCR &= (uint8_t)(~TIM1_SMCR_SMS);
00644 }
00645
00646 /**
00647   * @brief  Configures the TIM1 External clock Mode1.
00648   * @param  TIM1_ExtTRGPrescaler specifies the external Trigger Prescaler.
00649   *         This parameter can be one of the following values:
00650   *                       - TIM1_EXTTRGPSC_OFF
00651   *                       - TIM1_EXTTRGPSC_DIV2
00652   *                       - TIM1_EXTTRGPSC_DIV4
00653   *                       - TIM1_EXTTRGPSC_DIV8.
00654   * @param  TIM1_ExtTRGPolarity specifies the external Trigger Polarity.
00655   *         This parameter can be one of the following values:
00656   *                       - TIM1_EXTTRGPOLARITY_INVERTED
00657   *                       - TIM1_EXTTRGPOLARITY_NONINVERTED
00658   * @param  ExtTRGFilter specifies the External Trigger Filter.
00659   *         This parameter must be a value between 0x00 and 0x0F
00660   * @retval None
00661   */
00662 void TIM1_ETRClockMode1Config(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler,
00663                               TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity,
00664                               uint8_t ExtTRGFilter)
00665 {
00666   /* Check the parameters */
00667   assert_param(IS_TIM1_EXT_PRESCALER_OK(TIM1_ExtTRGPrescaler));
00668   assert_param(IS_TIM1_EXT_POLARITY_OK(TIM1_ExtTRGPolarity));
00669
00670   /* Configure the ETR Clock source */
00671   TIM1_ETRConfig(TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity, ExtTRGFilter);
00672
00673   /* Select the External clock mode1 & Select the Trigger selection : ETRF */
00674   TIM1->SMCR = (uint8_t)((uint8_t)(TIM1->SMCR & (uint8_t)(~(uint8_t)(TIM1_SMCR_SMS | TIM1_SMCR_TS )))
00675                          | (uint8_t)((uint8_t)TIM1_SLAVEMODE_EXTERNAL1 | TIM1_TS_ETRF ));
00676 }
00677
00678 /**
00679   * @brief  Configures the TIM1 External clock Mode2.
00680   * @param  TIM1_ExtTRGPrescaler specifies the external Trigger Prescaler.
00681   *         This parameter can be one of the following values:
00682   *                       - TIM1_EXTTRGPSC_OFF
00683   *                       - TIM1_EXTTRGPSC_DIV2
00684   *                       - TIM1_EXTTRGPSC_DIV4
00685   *                       - TIM1_EXTTRGPSC_DIV8.
00686   * @param  TIM1_ExtTRGPolarity specifies the external Trigger Polarity.
00687   *         This parameter can be one of the following values:
00688   *                       - TIM1_EXTTRGPOLARITY_INVERTED
00689   *                       - TIM1_EXTTRGPOLARITY_NONINVERTED
00690   * @param  ExtTRGFilter specifies the External Trigger Filter.
00691   *         This parameter must be a value between 0x00 and 0x0F
00692   * @retval None
00693   */
00694 void TIM1_ETRClockMode2Config(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler,
00695                               TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity,
00696                               uint8_t ExtTRGFilter)
00697 {
00698   /* Check the parameters */
00699   assert_param(IS_TIM1_EXT_PRESCALER_OK(TIM1_ExtTRGPrescaler));
00700   assert_param(IS_TIM1_EXT_POLARITY_OK(TIM1_ExtTRGPolarity));
00701
00702   /* Configure the ETR Clock source */
00703   TIM1_ETRConfig(TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity, ExtTRGFilter);
00704
00705   /* Enable the External clock mode2 */
00706   TIM1->ETR |= TIM1_ETR_ECE;
00707 }
00708
00709 /**
00710   * @brief  Configures the TIM1 External Trigger.
00711   * @param  TIM1_ExtTRGPrescaler specifies the external Trigger Prescaler.
00712   *         This parameter can be one of the following values:
00713   *                       - TIM1_EXTTRGPSC_OFF
00714   *                       - TIM1_EXTTRGPSC_DIV2
00715   *                       - TIM1_EXTTRGPSC_DIV4
00716   *                       - TIM1_EXTTRGPSC_DIV8.
00717   * @param  TIM1_ExtTRGPolarity specifies the external Trigger Polarity.
00718   *         This parameter can be one of the following values:
00719   *                       - TIM1_EXTTRGPOLARITY_INVERTED
00720   *                       - TIM1_EXTTRGPOLARITY_NONINVERTED
00721   * @param  ExtTRGFilter specifies the External Trigger Filter.
00722   *         This parameter must be a value between 0x00 and 0x0F
00723   * @retval None
00724   */
00725 void TIM1_ETRConfig(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler,
00726                     TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity,
00727                     uint8_t ExtTRGFilter)
00728 {
00729   /* Check the parameters */
00730   assert_param(IS_TIM1_EXT_TRG_FILTER_OK(ExtTRGFilter));
00731   /* Set the Prescaler, the Filter value and the Polarity */
00732   TIM1->ETR |= (uint8_t)((uint8_t)(TIM1_ExtTRGPrescaler | (uint8_t)TIM1_ExtTRGPolarity )|
00733                          (uint8_t)ExtTRGFilter );
00734 }
00735
00736 /**
00737   * @brief  Configures the TIM1 Trigger as External Clock.
00738   * @param  TIM1_TIxExternalCLKSource specifies Trigger source.
00739   *         This parameter can be one of the following values:
00740   *                     - TIM1_TIXEXTERNALCLK1SOURCE_TI1: TI1 Edge Detector
00741   *                     - TIM1_TIXEXTERNALCLK1SOURCE_TI2: Filtered TIM1 Input 1
00742   *                     - TIM1_TIXEXTERNALCLK1SOURCE_TI1ED: Filtered TIM1 Input 2
00743   * @param  TIM1_ICPolarity specifies the TIx Polarity.
00744   *         This parameter can be:
00745   *                     - TIM1_ICPOLARITY_RISING
00746   *                     - TIM1_ICPOLARITY_FALLING
00747   * @param  ICFilter specifies the filter value.
00748   *         This parameter must be a value between 0x00 and 0x0F
00749   * @retval None
00750   */
00751 void TIM1_TIxExternalClockConfig(TIM1_TIxExternalCLK1Source_TypeDef TIM1_TIxExternalCLKSource,
00752                                  TIM1_ICPolarity_TypeDef TIM1_ICPolarity,
00753                                  uint8_t ICFilter)
00754 {
00755   /* Check the parameters */
00756   assert_param(IS_TIM1_TIXCLK_SOURCE_OK(TIM1_TIxExternalCLKSource));
00757   assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_ICPolarity));
00758   assert_param(IS_TIM1_IC_FILTER_OK(ICFilter));
00759
00760   /* Configure the TIM1 Input Clock Source */
00761   if (TIM1_TIxExternalCLKSource == TIM1_TIXEXTERNALCLK1SOURCE_TI2)
00762   {
00763     TI2_Config((uint8_t)TIM1_ICPolarity, (uint8_t)TIM1_ICSELECTION_DIRECTTI, (uint8_t)ICFilter);
00764   }
00765   else
00766   {
00767     TI1_Config((uint8_t)TIM1_ICPolarity, (uint8_t)TIM1_ICSELECTION_DIRECTTI, (uint8_t)ICFilter);
00768   }
00769
00770   /* Select the Trigger source */
00771   TIM1_SelectInputTrigger((TIM1_TS_TypeDef)TIM1_TIxExternalCLKSource);
00772
00773   /* Select the External clock mode1 */
00774   TIM1->SMCR |= (uint8_t)(TIM1_SLAVEMODE_EXTERNAL1);
00775 }
00776
00777 /**
00778   * @brief  Selects the TIM1 Input Trigger source.
00779   * @param   TIM1_InputTriggerSource specifies Input Trigger source.
00780   * This parameter can be one of the following values:
00781   *                       - TIM1_TS_TI1F_ED: TI1 Edge Detector
00782   *                       - TIM1_TS_TI1FP1: Filtered Timer Input 1
00783   *                       - TIM1_TS_TI2FP2: Filtered Timer Input 2
00784   *                       - TIM1_TS_ETRF: External Trigger input
00785   * @retval None
00786   */
00787 void TIM1_SelectInputTrigger(TIM1_TS_TypeDef TIM1_InputTriggerSource)
00788 {
00789   /* Check the parameters */
00790   assert_param(IS_TIM1_TRIGGER_SELECTION_OK(TIM1_InputTriggerSource));
00791
00792   /* Select the Tgigger Source */
00793   TIM1->SMCR = (uint8_t)((uint8_t)(TIM1->SMCR & (uint8_t)(~TIM1_SMCR_TS)) | (uint8_t)TIM1_InputTriggerSource);
00794 }
00795
00796 /**
00797   * @brief  Enables or Disables the TIM1 Update event.
00798   * @param   NewState new state of the TIM1 peripheral Preload register. This parameter can
00799   * be ENABLE or DISABLE.
00800   * @retval None
00801   */
00802
00803 void TIM1_UpdateDisableConfig(FunctionalState NewState)
00804 {
00805   /* Check the parameters */
00806   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00807
00808   /* Set or Reset the UDIS Bit */
00809   if (NewState != DISABLE)
00810   {
00811     TIM1->CR1 |= TIM1_CR1_UDIS;
00812   }
00813   else
00814   {
00815     TIM1->CR1 &= (uint8_t)(~TIM1_CR1_UDIS);
00816   }
00817 }
00818
00819 /**
00820   * @brief  Selects the TIM1 Update Request Interrupt source.
00821   * @param   TIM1_UpdateSource specifies the Update source.
00822   * This parameter can be one of the following values
00823   *                       - TIM1_UPDATESOURCE_REGULAR
00824   *                       - TIM1_UPDATESOURCE_GLOBAL
00825   * @retval None
00826   */
00827 void TIM1_UpdateRequestConfig(TIM1_UpdateSource_TypeDef TIM1_UpdateSource)
00828 {
00829   /* Check the parameters */
00830   assert_param(IS_TIM1_UPDATE_SOURCE_OK(TIM1_UpdateSource));
00831
00832   /* Set or Reset the URS Bit */
00833   if (TIM1_UpdateSource != TIM1_UPDATESOURCE_GLOBAL)
00834   {
00835     TIM1->CR1 |= TIM1_CR1_URS;
00836   }
00837   else
00838   {
00839     TIM1->CR1 &= (uint8_t)(~TIM1_CR1_URS);
00840   }
00841 }
00842
00843 /**
00844   * @brief  Enables or Disables the TIM1’s Hall sensor interface.
00845   * @param   NewState new state of the TIM1 Hall sensor interface.This parameter can
00846   * be ENABLE or DISABLE.
00847   * @retval None
00848   */
00849 void TIM1_SelectHallSensor(FunctionalState NewState)
00850 {
00851   /* Check the parameters */
00852   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00853
00854   /* Set or Reset the TI1S Bit */
00855   if (NewState != DISABLE)
00856   {
00857     TIM1->CR2 |= TIM1_CR2_TI1S;
00858   }
00859   else
00860   {
00861     TIM1->CR2 &= (uint8_t)(~TIM1_CR2_TI1S);
00862   }
00863 }
00864
00865 /**
00866   * @brief  Selects the TIM1’s One Pulse Mode.
00867   * @param   TIM1_OPMode specifies the OPM Mode to be used.
00868   * This parameter can be one of the following values
00869   *                    - TIM1_OPMODE_SINGLE
00870   *                    - TIM1_OPMODE_REPETITIVE
00871   * @retval None
00872   */
00873 void TIM1_SelectOnePulseMode(TIM1_OPMode_TypeDef TIM1_OPMode)
00874 {
00875   /* Check the parameters */
00876   assert_param(IS_TIM1_OPM_MODE_OK(TIM1_OPMode));
00877
00878   /* Set or Reset the OPM Bit */
00879   if (TIM1_OPMode != TIM1_OPMODE_REPETITIVE)
00880   {
00881     TIM1->CR1 |= TIM1_CR1_OPM;
00882   }
00883   else
00884   {
00885     TIM1->CR1 &= (uint8_t)(~TIM1_CR1_OPM);
00886   }
00887
00888 }
00889
00890 /**
00891   * @brief  Selects the TIM1 Trigger Output Mode.
00892   * @param   TIM1_TRGOSource specifies the Trigger Output source.
00893   * This parameter can be one of the following values
00894   *                       - TIM1_TRGOSOURCE_RESET
00895   *                       - TIM1_TRGOSOURCE_ENABLE
00896   *                       - TIM1_TRGOSOURCE_UPDATE
00897   *                       - TIM1_TRGOSource_OC1
00898   *                       - TIM1_TRGOSOURCE_OC1REF
00899   *                       - TIM1_TRGOSOURCE_OC2REF
00900   *                       - TIM1_TRGOSOURCE_OC3REF
00901   * @retval None
00902   */
00903 void TIM1_SelectOutputTrigger(TIM1_TRGOSource_TypeDef TIM1_TRGOSource)
00904 {
00905   /* Check the parameters */
00906   assert_param(IS_TIM1_TRGO_SOURCE_OK(TIM1_TRGOSource));
00907
00908   /* Reset the MMS Bits & Select the TRGO source */
00909   TIM1->CR2 = (uint8_t)((uint8_t)(TIM1->CR2 & (uint8_t)(~TIM1_CR2_MMS)) |
00910                         (uint8_t) TIM1_TRGOSource);
00911 }
00912
00913 /**
00914   * @brief  Selects the TIM1 Slave Mode.
00915   * @param   TIM1_SlaveMode specifies the TIM1 Slave Mode.
00916   * This parameter can be one of the following values
00917   *                       - TIM1_SLAVEMODE_RESET
00918   *                       - TIM1_SLAVEMODE_GATED
00919   *                       - TIM1_SLAVEMODE_TRIGGER
00920   *                       - TIM1_SLAVEMODE_EXTERNAL1
00921   * @retval None
00922   */
00923 void TIM1_SelectSlaveMode(TIM1_SlaveMode_TypeDef TIM1_SlaveMode)
00924 {
00925   /* Check the parameters */
00926   assert_param(IS_TIM1_SLAVE_MODE_OK(TIM1_SlaveMode));
00927
00928   /* Reset the SMS Bits */ /* Select the Slave Mode */
00929   TIM1->SMCR = (uint8_t)((uint8_t)(TIM1->SMCR & (uint8_t)(~TIM1_SMCR_SMS)) |
00930                          (uint8_t)TIM1_SlaveMode);
00931 }
00932
00933 /**
00934   * @brief  Sets or Resets the TIM1 Master/Slave Mode.
00935   * @param   NewState new state of the synchronization between TIM1 and its slaves
00936   *  (through TRGO). This parameter can be ENABLE or DISABLE.
00937   * @retval None
00938   */
00939 void TIM1_SelectMasterSlaveMode(FunctionalState NewState)
00940 {
00941   /* Check the parameters */
00942   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00943
00944   /* Set or Reset the MSM Bit */
00945   if (NewState != DISABLE)
00946   {
00947     TIM1->SMCR |= TIM1_SMCR_MSM;
00948   }
00949   else
00950   {
00951     TIM1->SMCR &= (uint8_t)(~TIM1_SMCR_MSM);
00952   }
00953 }
00954
00955 /**
00956   * @brief  Configures the TIM1 Encoder Interface.
00957   * @param   TIM1_EncoderMode specifies the TIM1 Encoder Mode.
00958   * This parameter can be one of the following values
00959   * - TIM1_ENCODERMODE_TI1: Counter counts on TI1FP1 edge
00960         * depending on TI2FP2 level.
00961   * - TIM1_ENCODERMODE_TI2: Counter counts on TI2FP2 edge
00962   *     depending on TI1FP1 level.
00963   * - TIM1_ENCODERMODE_TI12: Counter counts on both TI1FP1 and
00964   * TI2FP2 edges depending on the level of the other input.
00965   * @param   TIM1_IC1Polarity specifies the IC1 Polarity.
00966   * This parameter can be one of the following values
00967   *                       - TIM1_ICPOLARITY_FALLING
00968   *                       - TIM1_ICPOLARITY_RISING
00969   * @param   TIM1_IC2Polarity specifies the IC2 Polarity.
00970   * This parameter can be one of the following values
00971   *                       - TIM1_ICPOLARITY_FALLING
00972   *                       - TIM1_ICPOLARITY_RISING
00973   * @retval None
00974   */
00975 void TIM1_EncoderInterfaceConfig(TIM1_EncoderMode_TypeDef TIM1_EncoderMode,
00976                                  TIM1_ICPolarity_TypeDef TIM1_IC1Polarity,
00977                                  TIM1_ICPolarity_TypeDef TIM1_IC2Polarity)
00978 {
00979   /* Check the parameters */
00980   assert_param(IS_TIM1_ENCODER_MODE_OK(TIM1_EncoderMode));
00981   assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_IC1Polarity));
00982   assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_IC2Polarity));
00983
00984   /* Set the TI1 and the TI2 Polarities */
00985   if (TIM1_IC1Polarity != TIM1_ICPOLARITY_RISING)
00986   {
00987     TIM1->CCER1 |= TIM1_CCER1_CC1P;
00988   }
00989   else
00990   {
00991     TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1P);
00992   }
00993
00994   if (TIM1_IC2Polarity != TIM1_ICPOLARITY_RISING)
00995   {
00996     TIM1->CCER1 |= TIM1_CCER1_CC2P;
00997   }
00998   else
00999   {
01000     TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2P);
01001   }
01002   /* Set the encoder Mode */
01003   TIM1->SMCR = (uint8_t)((uint8_t)(TIM1->SMCR & (uint8_t)(TIM1_SMCR_MSM | TIM1_SMCR_TS))
01004                          | (uint8_t) TIM1_EncoderMode);
01005
01006   /* Select the Capture Compare 1 and the Capture Compare 2 as input */
01007   TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_CCxS))
01008                           | (uint8_t) CCMR_TIxDirect_Set);
01009   TIM1->CCMR2 = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~TIM1_CCMR_CCxS))
01010                           | (uint8_t) CCMR_TIxDirect_Set);
01011 }
01012
01013 /**
01014   * @brief  Configures the TIM1 Prescaler.
01015   * @param   Prescaler specifies the Prescaler Register value
01016   * This parameter must be a value between 0x0000 and 0xFFFF
01017   * @param   TIM1_PSCReloadMode specifies the TIM1 Prescaler Reload mode.
01018   * This parameter can be one of the following values
01019   * - TIM1_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded immediately.
01020   * - TIM1_PSCRELOADMODE_UPDATE: The Prescaler is loaded at the update event.
01021   * @retval None
01022   */
01023 void TIM1_PrescalerConfig(uint16_t Prescaler,
01024                           TIM1_PSCReloadMode_TypeDef TIM1_PSCReloadMode)
01025 {
01026   /* Check the parameters */
01027   assert_param(IS_TIM1_PRESCALER_RELOAD_OK(TIM1_PSCReloadMode));
01028
01029   /* Set the Prescaler value */
01030   TIM1->PSCRH = (uint8_t)(Prescaler >> 8);
01031   TIM1->PSCRL = (uint8_t)(Prescaler);
01032
01033   /* Set or reset the UG Bit */
01034   TIM1->EGR = (uint8_t)TIM1_PSCReloadMode;
01035 }
01036
01037 /**
01038   * @brief  Specifies the TIM1 Counter Mode to be used.
01039   * @param   TIM1_CounterMode specifies the Counter Mode to be used
01040   * This parameter can be one of the following values:
01041   * - TIM1_COUNTERMODE_UP: TIM1 Up Counting Mode
01042   * - TIM1_COUNTERMODE_DOWN: TIM1 Down Counting Mode
01043   * - TIM1_COUNTERMODE_CENTERALIGNED1: TIM1 Center Aligned Mode1
01044   * - TIM1_CounterMode_CenterAligned2: TIM1 Center Aligned Mode2
01045   * - TIM1_COUNTERMODE_CENTERALIGNED3: TIM1 Center Aligned Mode3
01046   * @retval None
01047   */
01048 void TIM1_CounterModeConfig(TIM1_CounterMode_TypeDef TIM1_CounterMode)
01049 {
01050   /* Check the parameters */
01051   assert_param(IS_TIM1_COUNTER_MODE_OK(TIM1_CounterMode));
01052
01053
01054   /* Reset the CMS and DIR Bits & Set the Counter Mode */
01055   TIM1->CR1 = (uint8_t)((uint8_t)(TIM1->CR1 & (uint8_t)((uint8_t)(~TIM1_CR1_CMS) & (uint8_t)(~TIM1_CR1_DIR)))
01056                         | (uint8_t)TIM1_CounterMode);
01057 }
01058
01059 /**
01060   * @brief  Forces the TIM1 Channel1 output waveform to active or inactive level.
01061   * @param   TIM1_ForcedAction specifies the forced Action to be set to the output waveform.
01062   * This parameter can be one of the following values:
01063   * - TIM1_FORCEDACTION_ACTIVE: Force active level on OC1REF
01064   * - TIM1_FORCEDACTION_INACTIVE: Force inactive level on OC1REF.
01065   * @retval None
01066   */
01067 void TIM1_ForcedOC1Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
01068 {
01069   /* Check the parameters */
01070   assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));
01071
01072   /* Reset the OCM Bits & Configure the Forced output Mode */
01073   TIM1->CCMR1 =  (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_OCM))|
01074                            (uint8_t)TIM1_ForcedAction);
01075 }
01076
01077 /**
01078   * @brief  Forces the TIM1 Channel2 output waveform to active or inactive level.
01079   * @param   TIM1_ForcedAction specifies the forced Action to be set to the output waveform.
01080   * This parameter can be one of the following values:
01081   * - TIM1_FORCEDACTION_ACTIVE: Force active level on OC2REF
01082   * - TIM1_FORCEDACTION_INACTIVE: Force inactive level on OC2REF.
01083   * @retval None
01084   */
01085 void TIM1_ForcedOC2Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
01086 {
01087   /* Check the parameters */
01088   assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));
01089
01090   /* Reset the OCM Bits & Configure the Forced output Mode */
01091   TIM1->CCMR2  =  (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~TIM1_CCMR_OCM))
01092                             | (uint8_t)TIM1_ForcedAction);
01093 }
01094
01095 /**
01096   * @brief  Forces the TIM1 Channel3 output waveform to active or inactive level.
01097   * @param   TIM1_ForcedAction specifies the forced Action to be set to the output waveform.
01098   * This parameter can be one of the following values:
01099   *                       - TIM1_FORCEDACTION_ACTIVE: Force active level on OC3REF
01100   *                       - TIM1_FORCEDACTION_INACTIVE: Force inactive level on
01101   *                         OC3REF.
01102   * @retval None
01103   */
01104 void TIM1_ForcedOC3Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
01105 {
01106   /* Check the parameters */
01107   assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));
01108
01109   /* Reset the OCM Bits */ /* Configure The Forced output Mode */
01110   TIM1->CCMR3  =  (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~TIM1_CCMR_OCM))
01111                             | (uint8_t)TIM1_ForcedAction);
01112 }
01113
01114 /**
01115   * @brief  Forces the TIM1 Channel4 output waveform to active or inactive level.
01116   * @param   TIM1_ForcedAction specifies the forced Action to be set to the output waveform.
01117   * This parameter can be one of the following values:
01118   *                       - TIM1_FORCEDACTION_ACTIVE: Force active level on OC4REF
01119   *                       - TIM1_FORCEDACTION_INACTIVE: Force inactive level on
01120   *                         OC4REF.
01121   * @retval None
01122   */
01123 void TIM1_ForcedOC4Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
01124 {
01125   /* Check the parameters */
01126   assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));
01127
01128   /* Reset the OCM Bits & Configure the Forced output Mode */
01129   TIM1->CCMR4  =  (uint8_t)((uint8_t)(TIM1->CCMR4 & (uint8_t)(~TIM1_CCMR_OCM))
01130                             | (uint8_t)TIM1_ForcedAction);
01131 }
01132
01133 /**
01134   * @brief  Enables or disables TIM1 peripheral Preload register on ARR.
01135   * @param   NewState new state of the TIM1 peripheral Preload register.
01136   * This parameter can be ENABLE or DISABLE.
01137   * @retval None
01138   */
01139 void TIM1_ARRPreloadConfig(FunctionalState NewState)
01140 {
01141   /* Check the parameters */
01142   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01143
01144   /* Set or Reset the ARPE Bit */
01145   if (NewState != DISABLE)
01146   {
01147     TIM1->CR1 |= TIM1_CR1_ARPE;
01148   }
01149   else
01150   {
01151     TIM1->CR1 &= (uint8_t)(~TIM1_CR1_ARPE);
01152   }
01153 }
01154
01155 /**
01156   * @brief  Selects the TIM1 peripheral Commutation event.
01157   * @param   NewState new state of the Commutation event.
01158   * This parameter can be ENABLE or DISABLE.
01159   * @retval None
01160   */
01161 void TIM1_SelectCOM(FunctionalState NewState)
01162 {
01163   /* Check the parameters */
01164   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01165
01166   /* Set or Reset the COMS Bit */
01167   if (NewState != DISABLE)
01168   {
01169     TIM1->CR2 |= TIM1_CR2_COMS;
01170   }
01171   else
01172   {
01173     TIM1->CR2 &= (uint8_t)(~TIM1_CR2_COMS);
01174   }
01175 }
01176
01177 /**
01178   * @brief  Sets or Resets the TIM1 peripheral Capture Compare Preload Control bit.
01179   * @param   NewState new state of the Capture Compare Preload Control bit.
01180   * This parameter can be ENABLE or DISABLE.
01181   * @retval None
01182   */
01183 void TIM1_CCPreloadControl(FunctionalState NewState)
01184 {
01185   /* Check the parameters */
01186   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01187
01188   /* Set or Reset the CCPC Bit */
01189   if (NewState != DISABLE)
01190   {
01191     TIM1->CR2 |= TIM1_CR2_CCPC;
01192   }
01193   else
01194   {
01195     TIM1->CR2 &= (uint8_t)(~TIM1_CR2_CCPC);
01196   }
01197 }
01198
01199 /**
01200   * @brief  Enables or disables the TIM1 peripheral Preload Register on CCR1.
01201   * @param   NewState new state of the Capture Compare Preload register.
01202   * This parameter can be ENABLE or DISABLE.
01203   * @retval None
01204   */
01205 void TIM1_OC1PreloadConfig(FunctionalState NewState)
01206 {
01207   /* Check the parameters */
01208   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01209
01210   /* Set or Reset the OC1PE Bit */
01211   if (NewState != DISABLE)
01212   {
01213     TIM1->CCMR1 |= TIM1_CCMR_OCxPE;
01214   }
01215   else
01216   {
01217     TIM1->CCMR1 &= (uint8_t)(~TIM1_CCMR_OCxPE);
01218   }
01219 }
01220
01221 /**
01222   * @brief  Enables or disables the TIM1 peripheral Preload Register on CCR2.
01223   * @param   NewState new state of the Capture Compare Preload register.
01224   * This parameter can be ENABLE or DISABLE.
01225   * @retval None
01226   */
01227 void TIM1_OC2PreloadConfig(FunctionalState NewState)
01228 {
01229   /* Check the parameters */
01230   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01231
01232   /* Set or Reset the OC2PE Bit */
01233   if (NewState != DISABLE)
01234   {
01235     TIM1->CCMR2 |= TIM1_CCMR_OCxPE;
01236   }
01237   else
01238   {
01239     TIM1->CCMR2 &= (uint8_t)(~TIM1_CCMR_OCxPE);
01240   }
01241 }
01242
01243 /**
01244   * @brief  Enables or disables the TIM1 peripheral Preload Register on CCR3.
01245   * @param   NewState new state of the Capture Compare Preload register.
01246   * This parameter can be ENABLE or DISABLE.
01247   * @retval None
01248   */
01249 void TIM1_OC3PreloadConfig(FunctionalState NewState)
01250 {
01251   /* Check the parameters */
01252   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01253
01254   /* Set or Reset the OC3PE Bit */
01255   if (NewState != DISABLE)
01256   {
01257     TIM1->CCMR3 |= TIM1_CCMR_OCxPE;
01258   }
01259   else
01260   {
01261     TIM1->CCMR3 &= (uint8_t)(~TIM1_CCMR_OCxPE);
01262   }
01263 }
01264
01265 /**
01266   * @brief  Enables or disables the TIM1 peripheral Preload Register on CCR4.
01267   * @param   NewState new state of the Capture Compare Preload register.
01268   * This parameter can be ENABLE or DISABLE.
01269   * @retval None
01270   */
01271 void TIM1_OC4PreloadConfig(FunctionalState NewState)
01272 {
01273   /* Check the parameters */
01274   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01275
01276   /* Set or Reset the OC4PE Bit */
01277   if (NewState != DISABLE)
01278   {
01279     TIM1->CCMR4 |= TIM1_CCMR_OCxPE;
01280   }
01281   else
01282   {
01283     TIM1->CCMR4 &= (uint8_t)(~TIM1_CCMR_OCxPE);
01284   }
01285 }
01286
01287 /**
01288   * @brief  Configures the TIM1 Capture Compare 1 Fast feature.
01289   * @param   NewState new state of the Output Compare Fast Enable bit.
01290   * This parameter can be ENABLE or DISABLE.
01291   * @retval None
01292   */
01293 void TIM1_OC1FastConfig(FunctionalState NewState)
01294 {
01295   /* Check the parameters */
01296   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01297
01298   /* Set or Reset the OC1FE Bit */
01299   if (NewState != DISABLE)
01300   {
01301     TIM1->CCMR1 |= TIM1_CCMR_OCxFE;
01302   }
01303   else
01304   {
01305     TIM1->CCMR1 &= (uint8_t)(~TIM1_CCMR_OCxFE);
01306   }
01307 }
01308
01309 /**
01310   * @brief  Configures the TIM1 Capture Compare 2 Fast feature.
01311   * @param   NewState new state of the Output Compare Fast Enable bit.
01312   * This parameter can be ENABLE or DISABLE.
01313   * @retval None
01314   */
01315 void TIM1_OC2FastConfig(FunctionalState NewState)
01316 {
01317   /* Check the parameters */
01318   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01319
01320   /* Set or Reset the OC2FE Bit */
01321   if (NewState != DISABLE)
01322   {
01323     TIM1->CCMR2 |= TIM1_CCMR_OCxFE;
01324   }
01325   else
01326   {
01327     TIM1->CCMR2 &= (uint8_t)(~TIM1_CCMR_OCxFE);
01328   }
01329 }
01330
01331 /**
01332   * @brief  Configures the TIM1 Capture Compare 3 Fast feature.
01333   * @param   NewState new state of the Output Compare Fast Enable bit.
01334   * This parameter can be ENABLE or DISABLE.
01335   * @retval None
01336   */
01337 void TIM1_OC3FastConfig(FunctionalState NewState)
01338 {
01339   /* Check the parameters */
01340   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01341
01342   /* Set or Reset the OC3FE Bit */
01343   if (NewState != DISABLE)
01344   {
01345     TIM1->CCMR3 |= TIM1_CCMR_OCxFE;
01346   }
01347   else
01348   {
01349     TIM1->CCMR3 &= (uint8_t)(~TIM1_CCMR_OCxFE);
01350   }
01351 }
01352
01353 /**
01354   * @brief  Configures the TIM1 Capture Compare 4 Fast feature.
01355   * @param   NewState new state of the Output Compare Fast Enable bit.
01356   * This parameter can be ENABLE or DISABLE.
01357   * @retval None
01358   */
01359 void TIM1_OC4FastConfig(FunctionalState NewState)
01360 {
01361   /* Check the parameters */
01362   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01363
01364   /* Set or Reset the OC4FE Bit */
01365   if (NewState != DISABLE)
01366   {
01367     TIM1->CCMR4 |= TIM1_CCMR_OCxFE;
01368   }
01369   else
01370   {
01371     TIM1->CCMR4 &= (uint8_t)(~TIM1_CCMR_OCxFE);
01372   }
01373 }
01374
01375 /**
01376   * @brief  Configures the TIM1 event to be generated by software.
01377   * @param   TIM1_EventSource specifies the event source.
01378   * This parameter can be one of the following values:
01379   *                       - TIM1_EVENTSOURCE_UPDATE: TIM1 update Event source
01380   *                       - TIM1_EVENTSOURCE_CC1: TIM1 Capture Compare 1 Event source
01381   *                       - TIM1_EVENTSOURCE_CC2: TIM1 Capture Compare 2 Event source
01382   *                       - TIM1_EVENTSOURCE_CC3: TIM1 Capture Compare 3 Event source
01383   *                       - TIM1_EVENTSOURCE_CC4: TIM1 Capture Compare 4 Event source
01384   *                       - TIM1_EVENTSOURCE_COM: TIM1 COM Event source
01385   *                       - TIM1_EVENTSOURCE_TRIGGER: TIM1 Trigger Event source
01386   *                       - TIM1_EventSourceBreak: TIM1 Break Event source
01387   * @retval None
01388   */
01389 void TIM1_GenerateEvent(TIM1_EventSource_TypeDef TIM1_EventSource)
01390 {
01391   /* Check the parameters */
01392   assert_param(IS_TIM1_EVENT_SOURCE_OK(TIM1_EventSource));
01393
01394   /* Set the event sources */
01395   TIM1->EGR = (uint8_t)TIM1_EventSource;
01396 }
01397
01398 /**
01399   * @brief  Configures the TIM1 Channel 1 polarity.
01400   * @param   TIM1_OCPolarity specifies the OC1 Polarity.
01401   * This parameter can be one of the following values:
01402   *                       - TIM1_OCPOLARITY_LOW: Output Compare active low
01403   *                       - TIM1_OCPOLARITY_HIGH: Output Compare active high
01404   * @retval None
01405   */
01406 void TIM1_OC1PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
01407 {
01408   /* Check the parameters */
01409   assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
01410
01411   /* Set or Reset the CC1P Bit */
01412   if (TIM1_OCPolarity != TIM1_OCPOLARITY_HIGH)
01413   {
01414     TIM1->CCER1 |= TIM1_CCER1_CC1P;
01415   }
01416   else
01417   {
01418     TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1P);
01419   }
01420 }
01421
01422 /**
01423   * @brief  Configures the TIM1 Channel 1N polarity.
01424   * @param   TIM1_OCNPolarity specifies the OC1N Polarity.
01425   * This parameter can be one of the following values:
01426   *                       - TIM1_OCNPOLARITY_LOW: Output Compare active low
01427   *                       - TIM1_OCNPOLARITY_HIGH: Output Compare active high
01428   * @retval None
01429   */
01430 void TIM1_OC1NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
01431 {
01432   /* Check the parameters */
01433   assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));
01434
01435   /* Set or Reset the CC3P Bit */
01436   if (TIM1_OCNPolarity != TIM1_OCNPOLARITY_HIGH)
01437   {
01438     TIM1->CCER1 |= TIM1_CCER1_CC1NP;
01439   }
01440   else
01441   {
01442     TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1NP);
01443   }
01444 }
01445
01446 /**
01447   * @brief  Configures the TIM1 Channel 2 polarity.
01448   * @param   TIM1_OCPolarity specifies the OC2 Polarity.
01449   * This parameter can be one of the following values:
01450   *                       - TIM1_OCPOLARITY_LOW: Output Compare active low
01451   *                       - TIM1_OCPOLARITY_HIGH: Output Compare active high
01452   * @retval None
01453   */
01454 void TIM1_OC2PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
01455 {
01456   /* Check the parameters */
01457   assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
01458
01459   /* Set or Reset the CC2P Bit */
01460   if (TIM1_OCPolarity != TIM1_OCPOLARITY_HIGH)
01461   {
01462     TIM1->CCER1 |= TIM1_CCER1_CC2P;
01463   }
01464   else
01465   {
01466     TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2P);
01467   }
01468 }
01469
01470 /**
01471   * @brief  Configures the TIM1 Channel 2N polarity.
01472   * @param   TIM1_OCNPolarity specifies the OC2N Polarity.
01473   * This parameter can be one of the following values:
01474   *                       - TIM1_OCNPOLARITY_LOW: Output Compare active low
01475   *                       - TIM1_OCNPOLARITY_HIGH: Output Compare active high
01476   * @retval None
01477   */
01478 void TIM1_OC2NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
01479 {
01480   /* Check the parameters */
01481   assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));
01482
01483   /* Set or Reset the CC3P Bit */
01484   if (TIM1_OCNPolarity != TIM1_OCNPOLARITY_HIGH)
01485   {
01486     TIM1->CCER1 |= TIM1_CCER1_CC2NP;
01487   }
01488   else
01489   {
01490     TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2NP);
01491   }
01492 }
01493
01494 /**
01495   * @brief  Configures the TIM1 Channel 3 polarity.
01496   * @param   TIM1_OCPolarity specifies the OC3 Polarity.
01497   * This parameter can be one of the following values:
01498   *                       - TIM1_OCPOLARITY_LOW: Output Compare active low
01499   *                       - TIM1_OCPOLARITY_HIGH: Output Compare active high
01500   * @retval None
01501   */
01502 void TIM1_OC3PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
01503 {
01504   /* Check the parameters */
01505   assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
01506
01507   /* Set or Reset the CC3P Bit */
01508   if (TIM1_OCPolarity != TIM1_OCPOLARITY_HIGH)
01509   {
01510     TIM1->CCER2 |= TIM1_CCER2_CC3P;
01511   }
01512   else
01513   {
01514     TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3P);
01515   }
01516 }
01517
01518
01519 /**
01520   * @brief  Configures the TIM1 Channel 3N polarity.
01521   * @param   TIM1_OCNPolarity specifies the OC3N Polarity.
01522   * This parameter can be one of the following values:
01523   *                       - TIM1_OCNPOLARITY_LOW: Output Compare active low
01524   *                       - TIM1_OCNPOLARITY_HIGH: Output Compare active high
01525   * @retval None
01526   */
01527 void TIM1_OC3NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
01528 {
01529   /* Check the parameters */
01530   assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));
01531
01532   /* Set or Reset the CC3P Bit */
01533   if (TIM1_OCNPolarity != TIM1_OCNPOLARITY_HIGH)
01534   {
01535     TIM1->CCER2 |= TIM1_CCER2_CC3NP;
01536   }
01537   else
01538   {
01539     TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3NP);
01540   }
01541 }
01542
01543 /**
01544   * @brief  Configures the TIM1 Channel 4 polarity.
01545   * @param   TIM1_OCPolarity specifies the OC4 Polarity.
01546   * This parameter can be one of the following values:
01547   *                       - TIM1_OCPOLARITY_LOW: Output Compare active low
01548   *                       - TIM1_OCPOLARITY_HIGH: Output Compare active high
01549   * @retval None
01550   */
01551 void TIM1_OC4PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
01552 {
01553   /* Check the parameters */
01554   assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
01555
01556   /* Set or Reset the CC4P Bit */
01557   if (TIM1_OCPolarity != TIM1_OCPOLARITY_HIGH)
01558   {
01559     TIM1->CCER2 |= TIM1_CCER2_CC4P;
01560   }
01561   else
01562   {
01563     TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC4P);
01564   }
01565 }
01566
01567 /**
01568   * @brief  Enables or disables the TIM1 Capture Compare Channel x (x=1,..,4).
01569   * @param   TIM1_Channel specifies the TIM1 Channel.
01570   * This parameter can be one of the following values:
01571   *                       - TIM1_CHANNEL_1: TIM1 Channel1
01572   *                       - TIM1_CHANNEL_2: TIM1 Channel2
01573   *                       - TIM1_CHANNEL_3: TIM1 Channel3
01574   *                       - TIM1_CHANNEL_4: TIM1 Channel4
01575   * @param   NewState specifies the TIM1 Channel CCxE bit new state.
01576   * This parameter can be: ENABLE or DISABLE.
01577   * @retval None
01578   */
01579 void TIM1_CCxCmd(TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState)
01580 {
01581   /* Check the parameters */
01582   assert_param(IS_TIM1_CHANNEL_OK(TIM1_Channel));
01583   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01584
01585   if (TIM1_Channel == TIM1_CHANNEL_1)
01586   {
01587     /* Set or Reset the CC1E Bit */
01588     if (NewState != DISABLE)
01589     {
01590       TIM1->CCER1 |= TIM1_CCER1_CC1E;
01591     }
01592     else
01593     {
01594       TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1E);
01595     }
01596
01597   }
01598   else if (TIM1_Channel == TIM1_CHANNEL_2)
01599   {
01600     /* Set or Reset the CC2E Bit */
01601     if (NewState != DISABLE)
01602     {
01603       TIM1->CCER1 |= TIM1_CCER1_CC2E;
01604     }
01605     else
01606     {
01607       TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2E);
01608     }
01609   }
01610   else if (TIM1_Channel == TIM1_CHANNEL_3)
01611   {
01612     /* Set or Reset the CC3E Bit */
01613     if (NewState != DISABLE)
01614     {
01615       TIM1->CCER2 |= TIM1_CCER2_CC3E;
01616     }
01617     else
01618     {
01619       TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3E);
01620     }
01621   }
01622   else
01623   {
01624     /* Set or Reset the CC4E Bit */
01625     if (NewState != DISABLE)
01626     {
01627       TIM1->CCER2 |= TIM1_CCER2_CC4E;
01628     }
01629     else
01630     {
01631       TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC4E);
01632     }
01633   }
01634 }
01635
01636 /**
01637   * @brief  Enables or disables the TIM1 Capture Compare Channel xN (xN=1,..,3).
01638   * @param   TIM1_Channel specifies the TIM1 Channel.
01639   * This parameter can be one of the following values:
01640   *                       - TIM1_CHANNEL_1: TIM1 Channel1
01641   *                       - TIM1_CHANNEL_2: TIM1 Channel2
01642   *                       - TIM1_CHANNEL_3: TIM1 Channel3
01643   * @param   NewState specifies the TIM1 Channel CCxNE bit new state.
01644   * This parameter can be: ENABLE or DISABLE.
01645   * @retval None
01646   */
01647 void TIM1_CCxNCmd(TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState)
01648 {
01649   /* Check the parameters */
01650   assert_param(IS_TIM1_COMPLEMENTARY_CHANNEL_OK(TIM1_Channel));
01651   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01652
01653   if (TIM1_Channel == TIM1_CHANNEL_1)
01654   {
01655     /* Set or Reset the CC1NE Bit */
01656     if (NewState != DISABLE)
01657     {
01658       TIM1->CCER1 |= TIM1_CCER1_CC1NE;
01659     }
01660     else
01661     {
01662       TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1NE);
01663     }
01664   }
01665   else if (TIM1_Channel == TIM1_CHANNEL_2)
01666   {
01667     /* Set or Reset the CC2NE Bit */
01668     if (NewState != DISABLE)
01669     {
01670       TIM1->CCER1 |= TIM1_CCER1_CC2NE;
01671     }
01672     else
01673     {
01674       TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2NE);
01675     }
01676   }
01677   else
01678   {
01679     /* Set or Reset the CC3NE Bit */
01680     if (NewState != DISABLE)
01681     {
01682       TIM1->CCER2 |= TIM1_CCER2_CC3NE;
01683     }
01684     else
01685     {
01686       TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3NE);
01687     }
01688   }
01689 }
01690
01691 /**
01692   * @brief  Selects the TIM1 Output Compare Mode. This function disables the
01693   * selected channel before changing the Output Compare Mode. User has to
01694   * enable this channel using TIM1_CCxCmd and TIM1_CCxNCmd functions.
01695   * @param   TIM1_Channel specifies the TIM1 Channel.
01696   * This parameter can be one of the following values:
01697   *                       - TIM1_CHANNEL_1: TIM1 Channel1
01698   *                       - TIM1_CHANNEL_2: TIM1 Channel2
01699   *                       - TIM1_CHANNEL_3: TIM1 Channel3
01700   *                       - TIM1_CHANNEL_4: TIM1 Channel4
01701   * @param   TIM1_OCMode specifies the TIM1 Output Compare Mode.
01702   * This parameter can be one of the following values:
01703   *                       - TIM1_OCMODE_TIMING
01704   *                       - TIM1_OCMODE_ACTIVE
01705   *                       - TIM1_OCMODE_TOGGLE
01706   *                       - TIM1_OCMODE_PWM1
01707   *                       - TIM1_OCMODE_PWM2
01708   *                       - TIM1_FORCEDACTION_ACTIVE
01709   *                       - TIM1_FORCEDACTION_INACTIVE
01710   * @retval None
01711   */
01712 void TIM1_SelectOCxM(TIM1_Channel_TypeDef TIM1_Channel, TIM1_OCMode_TypeDef TIM1_OCMode)
01713 {
01714   /* Check the parameters */
01715   assert_param(IS_TIM1_CHANNEL_OK(TIM1_Channel));
01716   assert_param(IS_TIM1_OCM_OK(TIM1_OCMode));
01717
01718   if (TIM1_Channel == TIM1_CHANNEL_1)
01719   {
01720     /* Disable the Channel 1: Reset the CCE Bit */
01721     TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1E);
01722
01723     /* Reset the Output Compare Bits & Set the Output Compare Mode */
01724     TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_OCM))
01725                             | (uint8_t)TIM1_OCMode);
01726   }
01727   else if (TIM1_Channel == TIM1_CHANNEL_2)
01728   {
01729     /* Disable the Channel 2: Reset the CCE Bit */
01730     TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2E);
01731
01732     /* Reset the Output Compare Bits & Set the Output Compare Mode */
01733     TIM1->CCMR2 = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~TIM1_CCMR_OCM))
01734                             | (uint8_t)TIM1_OCMode);
01735   }
01736   else if (TIM1_Channel == TIM1_CHANNEL_3)
01737   {
01738     /* Disable the Channel 3: Reset the CCE Bit */
01739     TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3E);
01740
01741     /* Reset the Output Compare Bits & Set the Output Compare Mode */
01742     TIM1->CCMR3 = (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~TIM1_CCMR_OCM))
01743                             | (uint8_t)TIM1_OCMode);
01744   }
01745   else
01746   {
01747     /* Disable the Channel 4: Reset the CCE Bit */
01748     TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC4E);
01749
01750     /* Reset the Output Compare Bits & Set the Output Compare Mode */
01751     TIM1->CCMR4 = (uint8_t)((uint8_t)(TIM1->CCMR4 & (uint8_t)(~TIM1_CCMR_OCM))
01752                             | (uint8_t)TIM1_OCMode);
01753   }
01754 }
01755
01756 /**
01757   * @brief  Sets the TIM1 Counter Register value.
01758   * @param   Counter specifies the Counter register new value.
01759   * This parameter is between 0x0000 and 0xFFFF.
01760   * @retval None
01761   */
01762 void TIM1_SetCounter(uint16_t Counter)
01763 {
01764   /* Set the Counter Register value */
01765   TIM1->CNTRH = (uint8_t)(Counter >> 8);
01766   TIM1->CNTRL = (uint8_t)(Counter);
01767 }
01768
01769 /**
01770   * @brief  Sets the TIM1 Autoreload Register value.
01771   * @param   Autoreload specifies the Autoreload register new value.
01772   * This parameter is between 0x0000 and 0xFFFF.
01773   * @retval None
01774   */
01775 void TIM1_SetAutoreload(uint16_t Autoreload)
01776 {
01777   /* Set the Autoreload Register value */
01778   TIM1->ARRH = (uint8_t)(Autoreload >> 8);
01779   TIM1->ARRL = (uint8_t)(Autoreload);
01780  }
01781
01782 /**
01783   * @brief  Sets the TIM1 Capture Compare1 Register value.
01784   * @param   Compare1 specifies the Capture Compare1 register new value.
01785   * This parameter is between 0x0000 and 0xFFFF.
01786   * @retval None
01787   */
01788 void TIM1_SetCompare1(uint16_t Compare1)
01789 {
01790   /* Set the Capture Compare1 Register value */
01791   TIM1->CCR1H = (uint8_t)(Compare1 >> 8);
01792   TIM1->CCR1L = (uint8_t)(Compare1);
01793 }
01794
01795 /**
01796   * @brief  Sets the TIM1 Capture Compare2 Register value.
01797   * @param   Compare2 specifies the Capture Compare2 register new value.
01798   * This parameter is between 0x0000 and 0xFFFF.
01799   * @retval None
01800   */
01801 void TIM1_SetCompare2(uint16_t Compare2)
01802 {
01803   /* Set the Capture Compare2 Register value */
01804   TIM1->CCR2H = (uint8_t)(Compare2 >> 8);
01805   TIM1->CCR2L = (uint8_t)(Compare2);
01806 }
01807
01808 /**
01809   * @brief  Sets the TIM1 Capture Compare3 Register value.
01810   * @param   Compare3 specifies the Capture Compare3 register new value.
01811   * This parameter is between 0x0000 and 0xFFFF.
01812   * @retval None
01813   */
01814 void TIM1_SetCompare3(uint16_t Compare3)
01815 {
01816   /* Set the Capture Compare3 Register value */
01817   TIM1->CCR3H = (uint8_t)(Compare3 >> 8);
01818   TIM1->CCR3L = (uint8_t)(Compare3);
01819 }
01820
01821 /**
01822   * @brief  Sets the TIM1 Capture Compare4 Register value.
01823   * @param   Compare4 specifies the Capture Compare4 register new value.
01824   * This parameter is between 0x0000 and 0xFFFF.
01825   * @retval None
01826   */
01827 void TIM1_SetCompare4(uint16_t Compare4)
01828 {
01829   /* Set the Capture Compare4 Register value */
01830   TIM1->CCR4H = (uint8_t)(Compare4 >> 8);
01831   TIM1->CCR4L = (uint8_t)(Compare4);
01832 }
01833
01834 /**
01835   * @brief  Sets the TIM1 Input Capture 1 prescaler.
01836   * @param   TIM1_IC1Prescaler specifies the Input Capture prescaler new value
01837   * This parameter can be one of the following values:
01838   *                       - TIM1_ICPSC_DIV1: no prescaler
01839   *                       - TIM1_ICPSC_DIV2: capture is done once every 2 events
01840   *                       - TIM1_ICPSC_DIV4: capture is done once every 4 events
01841   *                       - TIM1_ICPSC_DIV8: capture is done once every 8 events
01842   * @retval None
01843   */
01844 void TIM1_SetIC1Prescaler(TIM1_ICPSC_TypeDef TIM1_IC1Prescaler)
01845 {
01846   /* Check the parameters */
01847   assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_IC1Prescaler));
01848
01849   /* Reset the IC1PSC Bits */ /* Set the IC1PSC value */
01850   TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_ICxPSC))
01851                           | (uint8_t)TIM1_IC1Prescaler);
01852 }
01853
01854 /**
01855   * @brief  Sets the TIM1 Input Capture 2 prescaler.
01856   * @param   TIM1_IC2Prescaler specifies the Input Capture prescaler new value
01857   * This parameter can be one of the following values:
01858   *                       - TIM1_ICPSC_DIV1: no prescaler
01859   *                       - TIM1_ICPSC_DIV2: capture is done once every 2 events
01860   *                       - TIM1_ICPSC_DIV4: capture is done once every 4 events
01861   *                       - TIM1_ICPSC_DIV8: capture is done once every 8 events
01862   * @retval None
01863   */
01864 void TIM1_SetIC2Prescaler(TIM1_ICPSC_TypeDef TIM1_IC2Prescaler)
01865 {
01866
01867   /* Check the parameters */
01868   assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_IC2Prescaler));
01869
01870   /* Reset the IC1PSC Bits */ /* Set the IC1PSC value */
01871   TIM1->CCMR2 = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~TIM1_CCMR_ICxPSC))
01872                           | (uint8_t)TIM1_IC2Prescaler);
01873 }
01874
01875 /**
01876   * @brief  Sets the TIM1 Input Capture 3 prescaler.
01877   * @param   TIM1_IC3Prescaler specifies the Input Capture prescaler new value
01878   * This parameter can be one of the following values:
01879   *                       - TIM1_ICPSC_DIV1: no prescaler
01880   *                       - TIM1_ICPSC_DIV2: capture is done once every 2 events
01881   *                       - TIM1_ICPSC_DIV4: capture is done once every 4 events
01882   *                       - TIM1_ICPSC_DIV8: capture is done once every 8 events
01883   * @retval None
01884   */
01885 void TIM1_SetIC3Prescaler(TIM1_ICPSC_TypeDef TIM1_IC3Prescaler)
01886 {
01887
01888   /* Check the parameters */
01889   assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_IC3Prescaler));
01890
01891   /* Reset the IC1PSC Bits & Set the IC1PSC value */
01892   TIM1->CCMR3 = (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~TIM1_CCMR_ICxPSC)) |
01893                           (uint8_t)TIM1_IC3Prescaler);
01894 }
01895
01896 /**
01897   * @brief  Sets the TIM1 Input Capture 4 prescaler.
01898   * @param  TIM1_IC4Prescaler specifies the Input Capture prescaler new value
01899   *         This parameter can be one of the following values:
01900   *                       - TIM1_ICPSC_DIV1: no prescaler
01901   *                       - TIM1_ICPSC_DIV2: capture is done once every 2 events
01902   *                       - TIM1_ICPSC_DIV4: capture is done once every 4 events
01903   *                       - TIM1_ICPSC_DIV8: capture is done once every 8 events
01904   * @retval None
01905   */
01906 void TIM1_SetIC4Prescaler(TIM1_ICPSC_TypeDef TIM1_IC4Prescaler)
01907 {
01908
01909   /* Check the parameters */
01910   assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_IC4Prescaler));
01911
01912   /* Reset the IC1PSC Bits &  Set the IC1PSC value */
01913   TIM1->CCMR4 = (uint8_t)((uint8_t)(TIM1->CCMR4 & (uint8_t)(~TIM1_CCMR_ICxPSC)) |
01914                           (uint8_t)TIM1_IC4Prescaler);
01915 }
01916
01917 /**
01918   * @brief  Gets the TIM1 Input Capture 1 value.
01919   * @param  None
01920   * @retval Capture Compare 1 Register value.
01921   */
01922 uint16_t TIM1_GetCapture1(void)
01923 {
01924   /* Get the Capture 1 Register value */
01925
01926   uint16_t tmpccr1 = 0;
01927   uint8_t tmpccr1l=0, tmpccr1h=0;
01928
01929   tmpccr1h = TIM1->CCR1H;
01930   tmpccr1l = TIM1->CCR1L;
01931
01932   tmpccr1 = (uint16_t)(tmpccr1l);
01933   tmpccr1 |= (uint16_t)((uint16_t)tmpccr1h << 8);
01934   /* Get the Capture 1 Register value */
01935   return (uint16_t)tmpccr1;
01936 }
01937
01938 /**
01939   * @brief  Gets the TIM1 Input Capture 2 value.
01940   * @param  None
01941   * @retval Capture Compare 2 Register value.
01942   */
01943 uint16_t TIM1_GetCapture2(void)
01944 {
01945   /* Get the Capture 2 Register value */
01946
01947   uint16_t tmpccr2 = 0;
01948   uint8_t tmpccr2l=0, tmpccr2h=0;
01949
01950   tmpccr2h = TIM1->CCR2H;
01951   tmpccr2l = TIM1->CCR2L;
01952
01953   tmpccr2 = (uint16_t)(tmpccr2l);
01954   tmpccr2 |= (uint16_t)((uint16_t)tmpccr2h << 8);
01955   /* Get the Capture 2 Register value */
01956   return (uint16_t)tmpccr2;
01957 }
01958
01959 /**
01960   * @brief  Gets the TIM1 Input Capture 3 value.
01961   * @param  None
01962   * @retval Capture Compare 3 Register value.
01963   */
01964 uint16_t TIM1_GetCapture3(void)
01965 {
01966   /* Get the Capture 3 Register value */
01967   uint16_t tmpccr3 = 0;
01968   uint8_t tmpccr3l=0, tmpccr3h=0;
01969
01970   tmpccr3h = TIM1->CCR3H;
01971   tmpccr3l = TIM1->CCR3L;
01972
01973   tmpccr3 = (uint16_t)(tmpccr3l);
01974   tmpccr3 |= (uint16_t)((uint16_t)tmpccr3h << 8);
01975   /* Get the Capture 3 Register value */
01976   return (uint16_t)tmpccr3;
01977 }
01978
01979 /**
01980   * @brief  Gets the TIM1 Input Capture 4 value.
01981   * @param  None
01982   * @retval Capture Compare 4 Register value.
01983   */
01984 uint16_t TIM1_GetCapture4(void)
01985 {
01986   /* Get the Capture 4 Register value */
01987   uint16_t tmpccr4 = 0;
01988   uint8_t tmpccr4l=0, tmpccr4h=0;
01989
01990   tmpccr4h = TIM1->CCR4H;
01991   tmpccr4l = TIM1->CCR4L;
01992
01993   tmpccr4 = (uint16_t)(tmpccr4l);
01994   tmpccr4 |= (uint16_t)((uint16_t)tmpccr4h << 8);
01995   /* Get the Capture 4 Register value */
01996   return (uint16_t)tmpccr4;
01997 }
01998
01999 /**
02000   * @brief  Gets the TIM1 Counter value.
02001   * @param  None
02002   * @retval Counter Register value.
02003   */
02004 uint16_t TIM1_GetCounter(void)
02005 {
02006   uint16_t tmpcntr = 0;
02007
02008   tmpcntr = ((uint16_t)TIM1->CNTRH << 8);
02009
02010   /* Get the Counter Register value */
02011   return (uint16_t)(tmpcntr | (uint16_t)(TIM1->CNTRL));
02012 }
02013
02014 /**
02015   * @brief  Gets the TIM1 Prescaler value.
02016   * @param  None
02017   * @retval Prescaler Register value.
02018   */
02019 uint16_t TIM1_GetPrescaler(void)
02020 {
02021   uint16_t temp = 0;
02022
02023   temp = ((uint16_t)TIM1->PSCRH << 8);
02024
02025   /* Get the Prescaler Register value */
02026   return (uint16_t)( temp | (uint16_t)(TIM1->PSCRL));
02027 }
02028
02029 /**
02030   * @brief  Checks whether the specified TIM1 flag is set or not.
02031   * @param  TIM1_FLAG specifies the flag to check.
02032   *         This parameter can be one of the following values:
02033   *                   - TIM1_FLAG_UPDATE: TIM1 update Flag
02034   *                   - TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag
02035   *                   - TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag
02036   *                   - TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag
02037   *                   - TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag
02038   *                   - TIM1_FLAG_COM: TIM1 Commutation Flag
02039   *                   - TIM1_FLAG_TRIGGER: TIM1 Trigger Flag
02040   *                   - TIM1_FLAG_BREAK: TIM1 Break Flag
02041   *                   - TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag
02042   *                   - TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag
02043   *                   - TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag
02044   *                   - TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag
02045   * @retval FlagStatus The new state of TIM1_FLAG (SET or RESET).
02046   */
02047 FlagStatus TIM1_GetFlagStatus(TIM1_FLAG_TypeDef TIM1_FLAG)
02048 {
02049   FlagStatus bitstatus = RESET;
02050   uint8_t tim1_flag_l = 0, tim1_flag_h = 0;
02051
02052   /* Check the parameters */
02053   assert_param(IS_TIM1_GET_FLAG_OK(TIM1_FLAG));
02054
02055   tim1_flag_l = (uint8_t)(TIM1->SR1 & (uint8_t)TIM1_FLAG);
02056   tim1_flag_h = (uint8_t)((uint16_t)TIM1_FLAG >> 8);
02057
02058   if ((tim1_flag_l | (uint8_t)(TIM1->SR2 & tim1_flag_h)) != 0)
02059   {
02060     bitstatus = SET;
02061   }
02062   else
02063   {
02064     bitstatus = RESET;
02065   }
02066   return (FlagStatus)(bitstatus);
02067 }
02068
02069 /**
02070   * @brief  Clears the TIM1’s pending flags.
02071   * @param  TIM1_FLAG specifies the flag to clear.
02072   *         This parameter can be one of the following values:
02073   *                       - TIM1_FLAG_UPDATE: TIM1 update Flag
02074   *                       - TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag
02075   *                       - TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag
02076   *                       - TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag
02077   *                       - TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag
02078   *                       - TIM1_FLAG_COM: TIM1 Commutation Flag
02079   *                       - TIM1_FLAG_TRIGGER: TIM1 Trigger Flag
02080   *                       - TIM1_FLAG_BREAK: TIM1 Break Flag
02081   *                       - TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag
02082   *                       - TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag
02083   *                       - TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag
02084   *                       - TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag
02085   * @retval None.
02086   */
02087 void TIM1_ClearFlag(TIM1_FLAG_TypeDef TIM1_FLAG)
02088 {
02089   /* Check the parameters */
02090   assert_param(IS_TIM1_CLEAR_FLAG_OK(TIM1_FLAG));
02091
02092   /* Clear the flags (rc_w0) clear this bit by writing 0. Writing ‘1’ has no effect*/
02093   TIM1->SR1 = (uint8_t)(~(uint8_t)(TIM1_FLAG));
02094   TIM1->SR2 = (uint8_t)((uint8_t)(~((uint8_t)((uint16_t)TIM1_FLAG >> 8))) &
02095                         (uint8_t)0x1E);
02096 }
02097
02098 /**
02099   * @brief  Checks whether the TIM1 interrupt has occurred or not.
02100   * @param  TIM1_IT specifies the TIM1 interrupt source to check.
02101   *         This parameter can be one of the following values:
02102   *                       - TIM1_IT_UPDATE: TIM1 update Interrupt source
02103   *                       - TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source
02104   *                       - TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source
02105   *                       - TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source
02106   *                       - TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source
02107   *                       - TIM1_IT_COM: TIM1 Commutation Interrupt source
02108   *                       - TIM1_IT_TRIGGER: TIM1 Trigger Interrupt source
02109   *                       - TIM1_IT_BREAK: TIM1 Break Interrupt source
02110   * @retval ITStatus The new state of the TIM1_IT(SET or RESET).
02111   */
02112 ITStatus TIM1_GetITStatus(TIM1_IT_TypeDef TIM1_IT)
02113 {
02114   ITStatus bitstatus = RESET;
02115   uint8_t TIM1_itStatus = 0, TIM1_itEnable = 0;
02116
02117   /* Check the parameters */
02118   assert_param(IS_TIM1_GET_IT_OK(TIM1_IT));
02119
02120   TIM1_itStatus = (uint8_t)(TIM1->SR1 & (uint8_t)TIM1_IT);
02121
02122   TIM1_itEnable = (uint8_t)(TIM1->IER & (uint8_t)TIM1_IT);
02123
02124   if ((TIM1_itStatus != (uint8_t)RESET ) && (TIM1_itEnable != (uint8_t)RESET ))
02125   {
02126     bitstatus = SET;
02127   }
02128   else
02129   {
02130     bitstatus = RESET;
02131   }
02132   return (ITStatus)(bitstatus);
02133 }
02134
02135 /**
02136   * @brief  Clears the TIM1's interrupt pending bits.
02137   * @param  TIM1_IT specifies the pending bit to clear.
02138   *         This parameter can be one of the following values:
02139   *                       - TIM1_IT_UPDATE: TIM1 update Interrupt source
02140   *                       - TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source
02141   *                       - TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source
02142   *                       - TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source
02143   *                       - TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source
02144   *                       - TIM1_IT_COM: TIM1 Commutation Interrupt source
02145   *                       - TIM1_IT_TRIGGER: TIM1 Trigger Interrupt source
02146   *                       - TIM1_IT_BREAK: TIM1 Break Interrupt source
02147   * @retval None.
02148   */
02149 void TIM1_ClearITPendingBit(TIM1_IT_TypeDef TIM1_IT)
02150 {
02151   /* Check the parameters */
02152   assert_param(IS_TIM1_IT_OK(TIM1_IT));
02153
02154   /* Clear the IT pending Bit */
02155   TIM1->SR1 = (uint8_t)(~(uint8_t)TIM1_IT);
02156 }
02157
02158 /**
02159   * @brief  Configure the TI1 as Input.
02160   * @param  TIM1_ICPolarity  The Input Polarity.
02161   *         This parameter can be one of the following values:
02162   *                       - TIM1_ICPOLARITY_FALLING
02163   *                       - TIM1_ICPOLARITY_RISING
02164   * @param  TIM1_ICSelection specifies the input to be used.
02165   *         This parameter can be one of the following values:
02166   *                       - TIM1_ICSELECTION_DIRECTTI: TIM1 Input 1 is selected to
02167   *                         be connected to IC1.
02168   *                       - TIM1_ICSELECTION_INDIRECTTI: TIM1 Input 1 is selected to
02169   *                         be connected to IC2.
02170   * @param  TIM1_ICFilter Specifies the Input Capture Filter.
02171   *         This parameter must be a value between 0x00 and 0x0F.
02172   * @retval None
02173   */
02174 static void TI1_Config(uint8_t TIM1_ICPolarity,
02175                        uint8_t TIM1_ICSelection,
02176                        uint8_t TIM1_ICFilter)
02177 {
02178   /* Disable the Channel 1: Reset the CCE Bit */
02179   TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1E);
02180
02181   /* Select the Input and set the filter */
02182   TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~(uint8_t)( TIM1_CCMR_CCxS | TIM1_CCMR_ICxF ))) |
02183                           (uint8_t)(( (TIM1_ICSelection)) | ((uint8_t)( TIM1_ICFilter << 4))));
02184
02185   /* Select the Polarity */
02186   if (TIM1_ICPolarity != TIM1_ICPOLARITY_RISING)
02187   {
02188     TIM1->CCER1 |= TIM1_CCER1_CC1P;
02189   }
02190   else
02191   {
02192     TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1P);
02193   }
02194
02195   /* Set the CCE Bit */
02196   TIM1->CCER1 |=  TIM1_CCER1_CC1E;
02197 }
02198
02199 /**
02200   * @brief  Configure the TI2 as Input.
02201   * @param  TIM1_ICPolarity  The Input Polarity.
02202   *         This parameter can be one of the following values:
02203   *                       - TIM1_ICPOLARITY_FALLING
02204   *                       - TIM1_ICPOLARITY_RISING
02205   * @param  TIM1_ICSelection specifies the input to be used.
02206   *         This parameter can be one of the following values:
02207   *                       - TIM1_ICSELECTION_DIRECTTI: TIM1 Input 2 is selected to
02208   *                         be connected to IC2.
02209   *                       - TIM1_ICSELECTION_INDIRECTTI: TIM1 Input 2 is selected to
02210   *                         be connected to IC1.
02211   * @param  TIM1_ICFilter Specifies the Input Capture Filter.
02212   *         This parameter must be a value between 0x00 and 0x0F.
02213   * @retval None
02214   */
02215 static void TI2_Config(uint8_t TIM1_ICPolarity,
02216                        uint8_t TIM1_ICSelection,
02217                        uint8_t TIM1_ICFilter)
02218 {
02219   /* Disable the Channel 2: Reset the CCE Bit */
02220   TIM1->CCER1 &=  (uint8_t)(~TIM1_CCER1_CC2E);
02221
02222   /* Select the Input and set the filter */
02223   TIM1->CCMR2  = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~(uint8_t)( TIM1_CCMR_CCxS | TIM1_CCMR_ICxF )))
02224                            | (uint8_t)(( (TIM1_ICSelection)) | ((uint8_t)( TIM1_ICFilter << 4))));
02225   /* Select the Polarity */
02226   if (TIM1_ICPolarity != TIM1_ICPOLARITY_RISING)
02227   {
02228     TIM1->CCER1 |= TIM1_CCER1_CC2P;
02229   }
02230   else
02231   {
02232     TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2P);
02233   }
02234   /* Set the CCE Bit */
02235   TIM1->CCER1 |=  TIM1_CCER1_CC2E;
02236 }
02237
02238 /**
02239   * @brief  Configure the TI3 as Input.
02240   * @param  TIM1_ICPolarity  The Input Polarity.
02241   *         This parameter can be one of the following values:
02242   *                       - TIM1_ICPOLARITY_FALLING
02243   *                       - TIM1_ICPOLARITY_RISING
02244   * @param  TIM1_ICSelection specifies the input to be used.
02245   *         This parameter can be one of the following values:
02246   *                       - TIM1_ICSELECTION_DIRECTTI: TIM1 Input 3 is selected to
02247   *                         be connected to IC3.
02248   *                       - TIM1_ICSELECTION_INDIRECTTI: TIM1 Input 3 is selected to
02249   *                         be connected to IC4.
02250   * @param  TIM1_ICFilter Specifies the Input Capture Filter.
02251   *         This parameter must be a value between 0x00 and 0x0F.
02252   * @retval None
02253   */
02254 static void TI3_Config(uint8_t TIM1_ICPolarity,
02255                        uint8_t TIM1_ICSelection,
02256                        uint8_t TIM1_ICFilter)
02257 {
02258   /* Disable the Channel 3: Reset the CCE Bit */
02259   TIM1->CCER2 &=  (uint8_t)(~TIM1_CCER2_CC3E);
02260
02261   /* Select the Input and set the filter */
02262   TIM1->CCMR3 = (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~(uint8_t)( TIM1_CCMR_CCxS | TIM1_CCMR_ICxF)))
02263                           | (uint8_t)(( (TIM1_ICSelection)) | ((uint8_t)( TIM1_ICFilter << 4))));
02264
02265   /* Select the Polarity */
02266   if (TIM1_ICPolarity != TIM1_ICPOLARITY_RISING)
02267   {
02268     TIM1->CCER2 |= TIM1_CCER2_CC3P;
02269   }
02270   else
02271   {
02272     TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3P);
02273   }
02274   /* Set the CCE Bit */
02275   TIM1->CCER2 |=  TIM1_CCER2_CC3E;
02276 }
02277
02278 /**
02279   * @brief  Configure the TI4 as Input.
02280   * @param  TIM1_ICPolarity  The Input Polarity.
02281   *         This parameter can be one of the following values:
02282   *                       - TIM1_ICPOLARITY_FALLING
02283   *                       - TIM1_ICPOLARITY_RISING
02284   * @param  TIM1_ICSelection specifies the input to be used.
02285   *         This parameter can be one of the following values:
02286   *                       - TIM1_ICSELECTION_DIRECTTI: TIM1 Input 4 is selected to
02287   *                         be connected to IC4.
02288   *                       - TIM1_ICSELECTION_INDIRECTTI: TIM1 Input 4 is selected to
02289   *                         be connected to IC3.
02290   * @param  TIM1_ICFilter Specifies the Input Capture Filter.
02291   *         This parameter must be a value between 0x00 and 0x0F.
02292   * @retval None
02293   */
02294 static void TI4_Config(uint8_t TIM1_ICPolarity,
02295                        uint8_t TIM1_ICSelection,
02296                        uint8_t TIM1_ICFilter)
02297 {
02298   /* Disable the Channel 4: Reset the CCE Bit */
02299   TIM1->CCER2 &=  (uint8_t)(~TIM1_CCER2_CC4E);
02300
02301   /* Select the Input and set the filter */
02302   TIM1->CCMR4 = (uint8_t)((uint8_t)(TIM1->CCMR4 & (uint8_t)(~(uint8_t)( TIM1_CCMR_CCxS | TIM1_CCMR_ICxF )))
02303                           | (uint8_t)(( (TIM1_ICSelection)) | ((uint8_t)( TIM1_ICFilter << 4))));
02304
02305   /* Select the Polarity */
02306   if (TIM1_ICPolarity != TIM1_ICPOLARITY_RISING)
02307   {
02308     TIM1->CCER2 |= TIM1_CCER2_CC4P;
02309   }
02310   else
02311   {
02312     TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC4P);
02313   }
02314
02315   /* Set the CCE Bit */
02316   TIM1->CCER2 |=  TIM1_CCER2_CC4E;
02317 }
02318
02319
02320 /**
02321   * @}
02322   */
02323
02324 /**
02325   * @}
02326   */
02327
02328
02329 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_tim1.h Source File

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stm8s_tim1.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_tim1.h
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all functions prototype and macros for the TIM1 peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Define to prevent recursive inclusion -------------------------------------*/
00029 #ifndef __STM8S_TIM1_H
00030 #define __STM8S_TIM1_H
00031
00032 /* Includes ------------------------------------------------------------------*/
00033 #include "stm8s.h"
00034
00035 /** @addtogroup STM8S_StdPeriph_Driver
00036   * @{
00037   */
00038
00039 /** @addtogroup TIM1_Exported_Types
00040  * @{
00041  */
00042
00043 /** TIM1 Output Compare and PWM modes */
00044
00045 typedef enum
00046 {
00047   TIM1_OCMODE_TIMING     = ((uint8_t)0x00),
00048   TIM1_OCMODE_ACTIVE     = ((uint8_t)0x10),
00049   TIM1_OCMODE_INACTIVE   = ((uint8_t)0x20),
00050   TIM1_OCMODE_TOGGLE     = ((uint8_t)0x30),
00051   TIM1_OCMODE_PWM1       = ((uint8_t)0x60),
00052   TIM1_OCMODE_PWM2       = ((uint8_t)0x70)
00053 }TIM1_OCMode_TypeDef;
00054
00055 #define IS_TIM1_OC_MODE_OK(MODE) (((MODE) ==  TIM1_OCMODE_TIMING) || \
00056                                   ((MODE) == TIM1_OCMODE_ACTIVE) || \
00057                                   ((MODE) == TIM1_OCMODE_INACTIVE) || \
00058                                   ((MODE) == TIM1_OCMODE_TOGGLE)|| \
00059                                   ((MODE) == TIM1_OCMODE_PWM1) || \
00060                                   ((MODE) == TIM1_OCMODE_PWM2))
00061
00062 #define IS_TIM1_OCM_OK(MODE)(((MODE) ==  TIM1_OCMODE_TIMING) || \
00063                              ((MODE) == TIM1_OCMODE_ACTIVE) || \
00064                              ((MODE) == TIM1_OCMODE_INACTIVE) || \
00065                              ((MODE) == TIM1_OCMODE_TOGGLE)|| \
00066                              ((MODE) == TIM1_OCMODE_PWM1) || \
00067                              ((MODE) == TIM1_OCMODE_PWM2) || \
00068                              ((MODE) == (uint8_t)TIM1_FORCEDACTION_ACTIVE) || \
00069                              ((MODE) == (uint8_t)TIM1_FORCEDACTION_INACTIVE))
00070
00071 /** TIM1 One Pulse Mode */
00072 typedef enum
00073 {
00074   TIM1_OPMODE_SINGLE                 = ((uint8_t)0x01),
00075   TIM1_OPMODE_REPETITIVE             = ((uint8_t)0x00)
00076 }TIM1_OPMode_TypeDef;
00077
00078 #define IS_TIM1_OPM_MODE_OK(MODE) (((MODE) == TIM1_OPMODE_SINGLE) || \
00079                                    ((MODE) == TIM1_OPMODE_REPETITIVE))
00080
00081 /** TIM1 Channel */
00082
00083 typedef enum
00084 {
00085   TIM1_CHANNEL_1                     = ((uint8_t)0x00),
00086   TIM1_CHANNEL_2                     = ((uint8_t)0x01),
00087   TIM1_CHANNEL_3                     = ((uint8_t)0x02),
00088   TIM1_CHANNEL_4                     = ((uint8_t)0x03)
00089 }TIM1_Channel_TypeDef;
00090
00091
00092 #define IS_TIM1_CHANNEL_OK(CHANNEL) (((CHANNEL) == TIM1_CHANNEL_1) || \
00093                                      ((CHANNEL) == TIM1_CHANNEL_2) || \
00094                                      ((CHANNEL) == TIM1_CHANNEL_3) || \
00095                                      ((CHANNEL) == TIM1_CHANNEL_4))
00096
00097 #define IS_TIM1_PWMI_CHANNEL_OK(CHANNEL) (((CHANNEL) == TIM1_CHANNEL_1) || \
00098     ((CHANNEL) == TIM1_CHANNEL_2))
00099
00100 #define IS_TIM1_COMPLEMENTARY_CHANNEL_OK(CHANNEL) (((CHANNEL) == TIM1_CHANNEL_1) || \
00101     ((CHANNEL) == TIM1_CHANNEL_2) || \
00102     ((CHANNEL) == TIM1_CHANNEL_3))
00103
00104
00105 /** TIM1 Counter Mode */
00106 typedef enum
00107 {
00108   TIM1_COUNTERMODE_UP                = ((uint8_t)0x00),
00109   TIM1_COUNTERMODE_DOWN              = ((uint8_t)0x10),
00110   TIM1_COUNTERMODE_CENTERALIGNED1    = ((uint8_t)0x20),
00111   TIM1_COUNTERMODE_CENTERALIGNED2    = ((uint8_t)0x40),
00112   TIM1_COUNTERMODE_CENTERALIGNED3    = ((uint8_t)0x60)
00113 }TIM1_CounterMode_TypeDef;
00114
00115 #define IS_TIM1_COUNTER_MODE_OK(MODE) (((MODE) == TIM1_COUNTERMODE_UP) || \
00116                                        ((MODE) == TIM1_COUNTERMODE_DOWN) || \
00117                                        ((MODE) == TIM1_COUNTERMODE_CENTERALIGNED1) || \
00118                                        ((MODE) == TIM1_COUNTERMODE_CENTERALIGNED2) || \
00119                                        ((MODE) == TIM1_COUNTERMODE_CENTERALIGNED3))
00120
00121 /** TIM1 Output Compare Polarity */
00122 typedef enum
00123 {
00124   TIM1_OCPOLARITY_HIGH               = ((uint8_t)0x00),
00125   TIM1_OCPOLARITY_LOW                = ((uint8_t)0x22)
00126 }TIM1_OCPolarity_TypeDef;
00127
00128 #define IS_TIM1_OC_POLARITY_OK(POLARITY) (((POLARITY) == TIM1_OCPOLARITY_HIGH) || \
00129     ((POLARITY) == TIM1_OCPOLARITY_LOW))
00130
00131 /** TIM1 Output Compare N Polarity */
00132 typedef enum
00133 {
00134   TIM1_OCNPOLARITY_HIGH              = ((uint8_t)0x00),
00135   TIM1_OCNPOLARITY_LOW               = ((uint8_t)0x88)
00136 }TIM1_OCNPolarity_TypeDef;
00137
00138 #define IS_TIM1_OCN_POLARITY_OK(POLARITY) (((POLARITY) == TIM1_OCNPOLARITY_HIGH) || \
00139     ((POLARITY) == TIM1_OCNPOLARITY_LOW))
00140
00141 /** TIM1 Output Compare states */
00142 typedef enum
00143 {
00144   TIM1_OUTPUTSTATE_DISABLE           = ((uint8_t)0x00),
00145   TIM1_OUTPUTSTATE_ENABLE            = ((uint8_t)0x11)
00146 }TIM1_OutputState_TypeDef;
00147
00148 #define IS_TIM1_OUTPUT_STATE_OK(STATE) (((STATE) == TIM1_OUTPUTSTATE_DISABLE) || \
00149                                         ((STATE) == TIM1_OUTPUTSTATE_ENABLE))
00150
00151 /** TIM1 Output Compare N States */
00152 typedef enum
00153 {
00154   TIM1_OUTPUTNSTATE_DISABLE = ((uint8_t)0x00),
00155   TIM1_OUTPUTNSTATE_ENABLE  = ((uint8_t)0x44)
00156 } TIM1_OutputNState_TypeDef;
00157
00158 #define IS_TIM1_OUTPUTN_STATE_OK(STATE) (((STATE) == TIM1_OUTPUTNSTATE_DISABLE) ||\
00159     ((STATE) == TIM1_OUTPUTNSTATE_ENABLE))
00160
00161 /** TIM1 Break Input enable/disable */
00162 typedef enum
00163 {
00164   TIM1_BREAK_ENABLE                  = ((uint8_t)0x10),
00165   TIM1_BREAK_DISABLE                 = ((uint8_t)0x00)
00166 }TIM1_BreakState_TypeDef;
00167 #define IS_TIM1_BREAK_STATE_OK(STATE) (((STATE) == TIM1_BREAK_ENABLE) || \
00168                                        ((STATE) == TIM1_BREAK_DISABLE))
00169
00170 /** TIM1 Break Polarity */
00171 typedef enum
00172 {
00173   TIM1_BREAKPOLARITY_LOW             = ((uint8_t)0x00),
00174   TIM1_BREAKPOLARITY_HIGH            = ((uint8_t)0x20)
00175 }TIM1_BreakPolarity_TypeDef;
00176 #define IS_TIM1_BREAK_POLARITY_OK(POLARITY) (((POLARITY) == TIM1_BREAKPOLARITY_LOW) || \
00177     ((POLARITY) == TIM1_BREAKPOLARITY_HIGH))
00178
00179 /** TIM1 AOE Bit Set/Reset */
00180 typedef enum
00181 {
00182   TIM1_AUTOMATICOUTPUT_ENABLE        = ((uint8_t)0x40),
00183   TIM1_AUTOMATICOUTPUT_DISABLE       = ((uint8_t)0x00)
00184 }TIM1_AutomaticOutput_TypeDef;
00185
00186 #define IS_TIM1_AUTOMATIC_OUTPUT_STATE_OK(STATE) (((STATE) == TIM1_AUTOMATICOUTPUT_ENABLE) || \
00187     ((STATE) == TIM1_AUTOMATICOUTPUT_DISABLE))
00188
00189 /** TIM1 Lock levels */
00190 typedef enum
00191 {
00192   TIM1_LOCKLEVEL_OFF                 = ((uint8_t)0x00),
00193   TIM1_LOCKLEVEL_1                   = ((uint8_t)0x01),
00194   TIM1_LOCKLEVEL_2                   = ((uint8_t)0x02),
00195   TIM1_LOCKLEVEL_3                   = ((uint8_t)0x03)
00196 }TIM1_LockLevel_TypeDef;
00197
00198 #define IS_TIM1_LOCK_LEVEL_OK(LEVEL) (((LEVEL) == TIM1_LOCKLEVEL_OFF) || \
00199                                       ((LEVEL) == TIM1_LOCKLEVEL_1) || \
00200                                       ((LEVEL) == TIM1_LOCKLEVEL_2) || \
00201                                       ((LEVEL) == TIM1_LOCKLEVEL_3))
00202
00203 /** TIM1 OSSI: Off-State Selection for Idle mode states */
00204 typedef enum
00205 {
00206   TIM1_OSSISTATE_ENABLE              = ((uint8_t)0x04),
00207   TIM1_OSSISTATE_DISABLE             = ((uint8_t)0x00)
00208 }TIM1_OSSIState_TypeDef;
00209
00210 #define IS_TIM1_OSSI_STATE_OK(STATE) (((STATE) == TIM1_OSSISTATE_ENABLE) || \
00211                                       ((STATE) == TIM1_OSSISTATE_DISABLE))
00212
00213 /** TIM1 Output Compare Idle State */
00214 typedef enum
00215 {
00216   TIM1_OCIDLESTATE_SET               = ((uint8_t)0x55),
00217   TIM1_OCIDLESTATE_RESET             = ((uint8_t)0x00)
00218 }TIM1_OCIdleState_TypeDef;
00219
00220 #define IS_TIM1_OCIDLE_STATE_OK(STATE) (((STATE) == TIM1_OCIDLESTATE_SET) || \
00221                                         ((STATE) == TIM1_OCIDLESTATE_RESET))
00222
00223 /** TIM1 Output Compare N Idle State */
00224 typedef enum
00225 {
00226   TIM1_OCNIDLESTATE_SET             = ((uint8_t)0x2A),
00227   TIM1_OCNIDLESTATE_RESET           = ((uint8_t)0x00)
00228 }TIM1_OCNIdleState_TypeDef;
00229
00230 #define IS_TIM1_OCNIDLE_STATE_OK(STATE) (((STATE) == TIM1_OCNIDLESTATE_SET) || \
00231     ((STATE) == TIM1_OCNIDLESTATE_RESET))
00232
00233 /** TIM1 Input Capture Polarity */
00234 typedef enum
00235 {
00236   TIM1_ICPOLARITY_RISING            = ((uint8_t)0x00),
00237   TIM1_ICPOLARITY_FALLING           = ((uint8_t)0x01)
00238 }TIM1_ICPolarity_TypeDef;
00239
00240 #define IS_TIM1_IC_POLARITY_OK(POLARITY) (((POLARITY) == TIM1_ICPOLARITY_RISING) || \
00241     ((POLARITY) == TIM1_ICPOLARITY_FALLING))
00242
00243 /** TIM1 Input Capture Selection */
00244 typedef enum
00245 {
00246   TIM1_ICSELECTION_DIRECTTI          = ((uint8_t)0x01),
00247   TIM1_ICSELECTION_INDIRECTTI        = ((uint8_t)0x02),
00248   TIM1_ICSELECTION_TRGI              = ((uint8_t)0x03)
00249 }TIM1_ICSelection_TypeDef;
00250
00251 #define IS_TIM1_IC_SELECTION_OK(SELECTION) (((SELECTION) == TIM1_ICSELECTION_DIRECTTI) || \
00252     ((SELECTION) == TIM1_ICSELECTION_INDIRECTTI) || \
00253     ((SELECTION) == TIM1_ICSELECTION_TRGI))
00254
00255 /** TIM1 Input Capture Prescaler */
00256 typedef enum
00257 {
00258   TIM1_ICPSC_DIV1                    = ((uint8_t)0x00),
00259   TIM1_ICPSC_DIV2                    = ((uint8_t)0x04),
00260   TIM1_ICPSC_DIV4                    = ((uint8_t)0x08),
00261   TIM1_ICPSC_DIV8                    = ((uint8_t)0x0C)
00262 }TIM1_ICPSC_TypeDef;
00263
00264 #define IS_TIM1_IC_PRESCALER_OK(PRESCALER) (((PRESCALER) == TIM1_ICPSC_DIV1) || \
00265     ((PRESCALER) == TIM1_ICPSC_DIV2) || \
00266     ((PRESCALER) == TIM1_ICPSC_DIV4) || \
00267     ((PRESCALER) == TIM1_ICPSC_DIV8))
00268
00269 /** TIM1 Input Capture Filer Value */
00270
00271 #define IS_TIM1_IC_FILTER_OK(ICFILTER) ((ICFILTER) <= 0x0F)
00272
00273 /** TIM1 External Trigger Filer Value */
00274 #define IS_TIM1_EXT_TRG_FILTER_OK(FILTER) ((FILTER) <= 0x0F)
00275
00276 /** TIM1 interrupt sources */
00277 typedef enum
00278 {
00279   TIM1_IT_UPDATE                     = ((uint8_t)0x01),
00280   TIM1_IT_CC1                        = ((uint8_t)0x02),
00281   TIM1_IT_CC2                        = ((uint8_t)0x04),
00282   TIM1_IT_CC3                        = ((uint8_t)0x08),
00283   TIM1_IT_CC4                        = ((uint8_t)0x10),
00284   TIM1_IT_COM                        = ((uint8_t)0x20),
00285   TIM1_IT_TRIGGER                    = ((uint8_t)0x40),
00286   TIM1_IT_BREAK                      = ((uint8_t)0x80)
00287 }TIM1_IT_TypeDef;
00288
00289 #define IS_TIM1_IT_OK(IT) ((IT) != 0x00)
00290
00291 #define IS_TIM1_GET_IT_OK(IT) (((IT) == TIM1_IT_UPDATE) || \
00292                                ((IT) == TIM1_IT_CC1) || \
00293                                ((IT) == TIM1_IT_CC2) || \
00294                                ((IT) == TIM1_IT_CC3) || \
00295                                ((IT) == TIM1_IT_CC4) || \
00296                                ((IT) == TIM1_IT_COM) || \
00297                                ((IT) == TIM1_IT_TRIGGER) || \
00298                                ((IT) == TIM1_IT_BREAK))
00299
00300
00301 /** TIM1 External Trigger Prescaler */
00302 typedef enum
00303 {
00304   TIM1_EXTTRGPSC_OFF                 = ((uint8_t)0x00),
00305   TIM1_EXTTRGPSC_DIV2                = ((uint8_t)0x10),
00306   TIM1_EXTTRGPSC_DIV4                = ((uint8_t)0x20),
00307   TIM1_EXTTRGPSC_DIV8                = ((uint8_t)0x30)
00308 }TIM1_ExtTRGPSC_TypeDef;
00309
00310 #define IS_TIM1_EXT_PRESCALER_OK(PRESCALER) (((PRESCALER) == TIM1_EXTTRGPSC_OFF) || \
00311     ((PRESCALER) == TIM1_EXTTRGPSC_DIV2) || \
00312     ((PRESCALER) == TIM1_EXTTRGPSC_DIV4) || \
00313     ((PRESCALER) == TIM1_EXTTRGPSC_DIV8))
00314
00315 /** TIM1 Internal Trigger Selection */
00316 typedef enum
00317 {
00318   TIM1_TS_TIM6                       = ((uint8_t)0x00),  /*!< TRIG Input source =  TIM6 TRIG Output  */
00319   TIM1_TS_TIM5                       = ((uint8_t)0x30),  /*!< TRIG Input source =  TIM5 TRIG Output  */
00320   TIM1_TS_TI1F_ED                    = ((uint8_t)0x40),
00321   TIM1_TS_TI1FP1                     = ((uint8_t)0x50),
00322   TIM1_TS_TI2FP2                     = ((uint8_t)0x60),
00323   TIM1_TS_ETRF                       = ((uint8_t)0x70)
00324 }TIM1_TS_TypeDef;
00325
00326 #define IS_TIM1_TRIGGER_SELECTION_OK(SELECTION) (((SELECTION) == TIM1_TS_TI1F_ED) || \
00327     ((SELECTION) == TIM1_TS_TI1FP1) || \
00328     ((SELECTION) == TIM1_TS_TI2FP2) || \
00329     ((SELECTION) == TIM1_TS_ETRF) || \
00330     ((SELECTION) == TIM1_TS_TIM5) || \
00331     ((SELECTION) == TIM1_TS_TIM6))
00332
00333
00334 #define IS_TIM1_TIX_TRIGGER_SELECTION_OK(SELECTION) (((SELECTION) == TIM1_TS_TI1F_ED) || \
00335     ((SELECTION) == TIM1_TS_TI1FP1) || \
00336     ((SELECTION) == TIM1_TS_TI2FP2))
00337
00338 /** TIM1 TIx External Clock Source */
00339 typedef enum
00340 {
00341   TIM1_TIXEXTERNALCLK1SOURCE_TI1ED   = ((uint8_t)0x40),
00342   TIM1_TIXEXTERNALCLK1SOURCE_TI1     = ((uint8_t)0x50),
00343   TIM1_TIXEXTERNALCLK1SOURCE_TI2     = ((uint8_t)0x60)
00344 }TIM1_TIxExternalCLK1Source_TypeDef;
00345
00346 #define IS_TIM1_TIXCLK_SOURCE_OK(SOURCE)  (((SOURCE) == TIM1_TIXEXTERNALCLK1SOURCE_TI1ED) || \
00347     ((SOURCE) == TIM1_TIXEXTERNALCLK1SOURCE_TI2) || \
00348     ((SOURCE) == TIM1_TIXEXTERNALCLK1SOURCE_TI1))
00349
00350 /** TIM1 External Trigger Polarity */
00351 typedef enum
00352 {
00353   TIM1_EXTTRGPOLARITY_INVERTED       = ((uint8_t)0x80),
00354   TIM1_EXTTRGPOLARITY_NONINVERTED    = ((uint8_t)0x00)
00355 }TIM1_ExtTRGPolarity_TypeDef;
00356
00357 #define IS_TIM1_EXT_POLARITY_OK(POLARITY) (((POLARITY) == TIM1_EXTTRGPOLARITY_INVERTED) || \
00358     ((POLARITY) == TIM1_EXTTRGPOLARITY_NONINVERTED))
00359
00360 /** TIM1 Prescaler Reload Mode */
00361 typedef enum
00362 {
00363   TIM1_PSCRELOADMODE_UPDATE          = ((uint8_t)0x00),
00364   TIM1_PSCRELOADMODE_IMMEDIATE       = ((uint8_t)0x01)
00365 }TIM1_PSCReloadMode_TypeDef;
00366
00367 #define IS_TIM1_PRESCALER_RELOAD_OK(RELOAD) (((RELOAD) == TIM1_PSCRELOADMODE_UPDATE) || \
00368     ((RELOAD) == TIM1_PSCRELOADMODE_IMMEDIATE))
00369
00370 /** TIM1 Encoder Mode */
00371 typedef enum
00372 {
00373   TIM1_ENCODERMODE_TI1               = ((uint8_t)0x01),
00374   TIM1_ENCODERMODE_TI2               = ((uint8_t)0x02),
00375   TIM1_ENCODERMODE_TI12              = ((uint8_t)0x03)
00376 }TIM1_EncoderMode_TypeDef;
00377
00378 #define IS_TIM1_ENCODER_MODE_OK(MODE) (((MODE) == TIM1_ENCODERMODE_TI1) || \
00379                                        ((MODE) == TIM1_ENCODERMODE_TI2) || \
00380                                        ((MODE) == TIM1_ENCODERMODE_TI12))
00381
00382 /** TIM1 Event Source */
00383 typedef enum
00384 {
00385   TIM1_EVENTSOURCE_UPDATE            = ((uint8_t)0x01),
00386   TIM1_EVENTSOURCE_CC1               = ((uint8_t)0x02),
00387   TIM1_EVENTSOURCE_CC2               = ((uint8_t)0x04),
00388   TIM1_EVENTSOURCE_CC3               = ((uint8_t)0x08),
00389   TIM1_EVENTSOURCE_CC4               = ((uint8_t)0x10),
00390   TIM1_EVENTSOURCE_COM               = ((uint8_t)0x20),
00391   TIM1_EVENTSOURCE_TRIGGER           = ((uint8_t)0x40),
00392   TIM1_EVENTSOURCE_BREAK             = ((uint8_t)0x80)
00393 }TIM1_EventSource_TypeDef;
00394
00395 #define IS_TIM1_EVENT_SOURCE_OK(SOURCE) ((SOURCE) != 0x00)
00396
00397 /** TIM1 Update Source */
00398 typedef enum
00399 {
00400   TIM1_UPDATESOURCE_GLOBAL           = ((uint8_t)0x00),
00401   TIM1_UPDATESOURCE_REGULAR          = ((uint8_t)0x01)
00402 }TIM1_UpdateSource_TypeDef;
00403
00404 #define IS_TIM1_UPDATE_SOURCE_OK(SOURCE) (((SOURCE) == TIM1_UPDATESOURCE_GLOBAL) || \
00405     ((SOURCE) == TIM1_UPDATESOURCE_REGULAR))
00406
00407 /** TIM1 Trigger Output Source */
00408 typedef enum
00409 {
00410   TIM1_TRGOSOURCE_RESET              = ((uint8_t)0x00),
00411   TIM1_TRGOSOURCE_ENABLE             = ((uint8_t)0x10),
00412   TIM1_TRGOSOURCE_UPDATE             = ((uint8_t)0x20),
00413   TIM1_TRGOSource_OC1                = ((uint8_t)0x30),
00414   TIM1_TRGOSOURCE_OC1REF             = ((uint8_t)0x40),
00415   TIM1_TRGOSOURCE_OC2REF             = ((uint8_t)0x50),
00416   TIM1_TRGOSOURCE_OC3REF             = ((uint8_t)0x60)
00417 }TIM1_TRGOSource_TypeDef;
00418
00419 #define IS_TIM1_TRGO_SOURCE_OK(SOURCE) (((SOURCE) == TIM1_TRGOSOURCE_RESET) || \
00420                                         ((SOURCE) == TIM1_TRGOSOURCE_ENABLE) || \
00421                                         ((SOURCE) == TIM1_TRGOSOURCE_UPDATE) || \
00422                                         ((SOURCE) == TIM1_TRGOSource_OC1)  || \
00423                                         ((SOURCE) == TIM1_TRGOSOURCE_OC1REF) || \
00424                                         ((SOURCE) == TIM1_TRGOSOURCE_OC2REF) || \
00425                                         ((SOURCE) == TIM1_TRGOSOURCE_OC3REF))
00426
00427 /** TIM1 Slave Mode */
00428 typedef enum
00429 {
00430   TIM1_SLAVEMODE_RESET               = ((uint8_t)0x04),
00431   TIM1_SLAVEMODE_GATED               = ((uint8_t)0x05),
00432   TIM1_SLAVEMODE_TRIGGER             = ((uint8_t)0x06),
00433   TIM1_SLAVEMODE_EXTERNAL1           = ((uint8_t)0x07)
00434 }TIM1_SlaveMode_TypeDef;
00435
00436 #define IS_TIM1_SLAVE_MODE_OK(MODE) (((MODE) == TIM1_SLAVEMODE_RESET) || \
00437                                      ((MODE) == TIM1_SLAVEMODE_GATED) || \
00438                                      ((MODE) == TIM1_SLAVEMODE_TRIGGER) || \
00439                                      ((MODE) == TIM1_SLAVEMODE_EXTERNAL1))
00440
00441 /** TIM1 Flags */
00442 typedef enum
00443 {
00444   TIM1_FLAG_UPDATE                   = ((uint16_t)0x0001),
00445   TIM1_FLAG_CC1                      = ((uint16_t)0x0002),
00446   TIM1_FLAG_CC2                      = ((uint16_t)0x0004),
00447   TIM1_FLAG_CC3                      = ((uint16_t)0x0008),
00448   TIM1_FLAG_CC4                      = ((uint16_t)0x0010),
00449   TIM1_FLAG_COM                      = ((uint16_t)0x0020),
00450   TIM1_FLAG_TRIGGER                  = ((uint16_t)0x0040),
00451   TIM1_FLAG_BREAK                    = ((uint16_t)0x0080),
00452   TIM1_FLAG_CC1OF                    = ((uint16_t)0x0200),
00453   TIM1_FLAG_CC2OF                    = ((uint16_t)0x0400),
00454   TIM1_FLAG_CC3OF                    = ((uint16_t)0x0800),
00455   TIM1_FLAG_CC4OF                    = ((uint16_t)0x1000)
00456 }TIM1_FLAG_TypeDef;
00457
00458 #define IS_TIM1_GET_FLAG_OK(FLAG) (((FLAG) == TIM1_FLAG_UPDATE) || \
00459                                    ((FLAG) == TIM1_FLAG_CC1) || \
00460                                    ((FLAG) == TIM1_FLAG_CC2) || \
00461                                    ((FLAG) == TIM1_FLAG_CC3) || \
00462                                    ((FLAG) == TIM1_FLAG_CC4) || \
00463                                    ((FLAG) == TIM1_FLAG_COM) || \
00464                                    ((FLAG) == TIM1_FLAG_TRIGGER) || \
00465                                    ((FLAG) == TIM1_FLAG_BREAK) || \
00466                                    ((FLAG) == TIM1_FLAG_CC1OF) || \
00467                                    ((FLAG) == TIM1_FLAG_CC2OF) || \
00468                                    ((FLAG) == TIM1_FLAG_CC3OF) || \
00469                                    ((FLAG) == TIM1_FLAG_CC4OF))
00470
00471 #define IS_TIM1_CLEAR_FLAG_OK(FLAG) ((((uint16_t)(FLAG) & (uint16_t)0xE100) == 0x0000) && ((FLAG) != 0x0000))
00472
00473 /** TIM1 Forced Action */
00474 typedef enum
00475 {
00476   TIM1_FORCEDACTION_ACTIVE           = ((uint8_t)0x50),
00477   TIM1_FORCEDACTION_INACTIVE         = ((uint8_t)0x40)
00478 }TIM1_ForcedAction_TypeDef;
00479
00480 #define IS_TIM1_FORCED_ACTION_OK(ACTION) (((ACTION) == TIM1_FORCEDACTION_ACTIVE) || \
00481     ((ACTION) == TIM1_FORCEDACTION_INACTIVE))
00482 /**
00483   * @}
00484   */
00485
00486 /* Exported macro ------------------------------------------------------------*/
00487
00488 /* Exported functions --------------------------------------------------------*/
00489
00490 /** @addtogroup TIM1_Exported_Functions
00491   * @{
00492   */
00493
00494 void TIM1_DeInit(void);
00495 void TIM1_TimeBaseInit(uint16_t TIM1_Prescaler,
00496                        TIM1_CounterMode_TypeDef TIM1_CounterMode,
00497                        uint16_t TIM1_Period, uint8_t TIM1_RepetitionCounter);
00498 void TIM1_OC1Init(TIM1_OCMode_TypeDef TIM1_OCMode,
00499                   TIM1_OutputState_TypeDef TIM1_OutputState,
00500                   TIM1_OutputNState_TypeDef TIM1_OutputNState,
00501                   uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
00502                   TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
00503                   TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
00504                   TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState);
00505 void TIM1_OC2Init(TIM1_OCMode_TypeDef TIM1_OCMode,
00506                   TIM1_OutputState_TypeDef TIM1_OutputState,
00507                   TIM1_OutputNState_TypeDef TIM1_OutputNState,
00508                   uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
00509                   TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
00510                   TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
00511                   TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState);
00512 void TIM1_OC3Init(TIM1_OCMode_TypeDef TIM1_OCMode,
00513                   TIM1_OutputState_TypeDef TIM1_OutputState,
00514                   TIM1_OutputNState_TypeDef TIM1_OutputNState,
00515                   uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
00516                   TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
00517                   TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
00518                   TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState);
00519 void TIM1_OC4Init(TIM1_OCMode_TypeDef TIM1_OCMode,
00520                   TIM1_OutputState_TypeDef TIM1_OutputState, uint16_t TIM1_Pulse,
00521                   TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
00522                   TIM1_OCIdleState_TypeDef TIM1_OCIdleState);
00523 void TIM1_BDTRConfig(TIM1_OSSIState_TypeDef TIM1_OSSIState,
00524                      TIM1_LockLevel_TypeDef TIM1_LockLevel, uint8_t TIM1_DeadTime,
00525                      TIM1_BreakState_TypeDef TIM1_Break,
00526                      TIM1_BreakPolarity_TypeDef TIM1_BreakPolarity,
00527                      TIM1_AutomaticOutput_TypeDef TIM1_AutomaticOutput);
00528 void TIM1_ICInit(TIM1_Channel_TypeDef TIM1_Channel,
00529                  TIM1_ICPolarity_TypeDef TIM1_ICPolarity,
00530                  TIM1_ICSelection_TypeDef TIM1_ICSelection,
00531                  TIM1_ICPSC_TypeDef TIM1_ICPrescaler, uint8_t TIM1_ICFilter);
00532 void TIM1_PWMIConfig(TIM1_Channel_TypeDef TIM1_Channel,
00533                      TIM1_ICPolarity_TypeDef TIM1_ICPolarity,
00534                      TIM1_ICSelection_TypeDef TIM1_ICSelection,
00535                      TIM1_ICPSC_TypeDef TIM1_ICPrescaler, uint8_t TIM1_ICFilter);
00536 void TIM1_Cmd(FunctionalState NewState);
00537 void TIM1_CtrlPWMOutputs(FunctionalState NewState);
00538 void TIM1_ITConfig(TIM1_IT_TypeDef TIM1_IT, FunctionalState NewState);
00539 void TIM1_InternalClockConfig(void);
00540 void TIM1_ETRClockMode1Config(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler,
00541                               TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity,
00542                               uint8_t ExtTRGFilter);
00543 void TIM1_ETRClockMode2Config(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler,
00544                               TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity,
00545                               uint8_t ExtTRGFilter);
00546 void TIM1_ETRConfig(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler,
00547                     TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity,
00548                     uint8_t ExtTRGFilter);
00549 void TIM1_TIxExternalClockConfig(TIM1_TIxExternalCLK1Source_TypeDef TIM1_TIxExternalCLKSource,
00550                                  TIM1_ICPolarity_TypeDef TIM1_ICPolarity,
00551                                  uint8_t ICFilter);
00552 void TIM1_SelectInputTrigger(TIM1_TS_TypeDef TIM1_InputTriggerSource);
00553 void TIM1_UpdateDisableConfig(FunctionalState NewState);
00554 void TIM1_UpdateRequestConfig(TIM1_UpdateSource_TypeDef TIM1_UpdateSource);
00555 void TIM1_SelectHallSensor(FunctionalState NewState);
00556 void TIM1_SelectOnePulseMode(TIM1_OPMode_TypeDef TIM1_OPMode);
00557 void TIM1_SelectOutputTrigger(TIM1_TRGOSource_TypeDef TIM1_TRGOSource);
00558 void TIM1_SelectSlaveMode(TIM1_SlaveMode_TypeDef TIM1_SlaveMode);
00559 void TIM1_SelectMasterSlaveMode(FunctionalState NewState);
00560 void TIM1_EncoderInterfaceConfig(TIM1_EncoderMode_TypeDef TIM1_EncoderMode,
00561                                  TIM1_ICPolarity_TypeDef TIM1_IC1Polarity,
00562                                  TIM1_ICPolarity_TypeDef TIM1_IC2Polarity);
00563 void TIM1_PrescalerConfig(uint16_t Prescaler, TIM1_PSCReloadMode_TypeDef TIM1_PSCReloadMode);
00564 void TIM1_CounterModeConfig(TIM1_CounterMode_TypeDef TIM1_CounterMode);
00565 void TIM1_ForcedOC1Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction);
00566 void TIM1_ForcedOC2Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction);
00567 void TIM1_ForcedOC3Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction);
00568 void TIM1_ForcedOC4Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction);
00569 void TIM1_ARRPreloadConfig(FunctionalState NewState);
00570 void TIM1_SelectCOM(FunctionalState NewState);
00571 void TIM1_CCPreloadControl(FunctionalState NewState);
00572 void TIM1_OC1PreloadConfig(FunctionalState NewState);
00573 void TIM1_OC2PreloadConfig(FunctionalState NewState);
00574 void TIM1_OC3PreloadConfig(FunctionalState NewState);
00575 void TIM1_OC4PreloadConfig(FunctionalState NewState);
00576 void TIM1_OC1FastConfig(FunctionalState NewState);
00577 void TIM1_OC2FastConfig(FunctionalState NewState);
00578 void TIM1_OC3FastConfig(FunctionalState NewState);
00579 void TIM1_OC4FastConfig(FunctionalState NewState);
00580 void TIM1_GenerateEvent(TIM1_EventSource_TypeDef TIM1_EventSource);
00581 void TIM1_OC1PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity);
00582 void TIM1_OC1NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity);
00583 void TIM1_OC2PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity);
00584 void TIM1_OC2NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity);
00585 void TIM1_OC3PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity);
00586 void TIM1_OC3NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity);
00587 void TIM1_OC4PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity);
00588 void TIM1_CCxCmd(TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState);
00589 void TIM1_CCxNCmd(TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState);
00590 void TIM1_SelectOCxM(TIM1_Channel_TypeDef TIM1_Channel, TIM1_OCMode_TypeDef TIM1_OCMode);
00591 void TIM1_SetCounter(uint16_t Counter);
00592 void TIM1_SetAutoreload(uint16_t Autoreload);
00593 void TIM1_SetCompare1(uint16_t Compare1);
00594 void TIM1_SetCompare2(uint16_t Compare2);
00595 void TIM1_SetCompare3(uint16_t Compare3);
00596 void TIM1_SetCompare4(uint16_t Compare4);
00597 void TIM1_SetIC1Prescaler(TIM1_ICPSC_TypeDef TIM1_IC1Prescaler);
00598 void TIM1_SetIC2Prescaler(TIM1_ICPSC_TypeDef TIM1_IC2Prescaler);
00599 void TIM1_SetIC3Prescaler(TIM1_ICPSC_TypeDef TIM1_IC3Prescaler);
00600 void TIM1_SetIC4Prescaler(TIM1_ICPSC_TypeDef TIM1_IC4Prescaler);
00601 uint16_t TIM1_GetCapture1(void);
00602 uint16_t TIM1_GetCapture2(void);
00603 uint16_t TIM1_GetCapture3(void);
00604 uint16_t TIM1_GetCapture4(void);
00605 uint16_t TIM1_GetCounter(void);
00606 uint16_t TIM1_GetPrescaler(void);
00607 FlagStatus TIM1_GetFlagStatus(TIM1_FLAG_TypeDef TIM1_FLAG);
00608 void TIM1_ClearFlag(TIM1_FLAG_TypeDef TIM1_FLAG);
00609 ITStatus TIM1_GetITStatus(TIM1_IT_TypeDef TIM1_IT);
00610 void TIM1_ClearITPendingBit(TIM1_IT_TypeDef TIM1_IT);
00611
00612 /**
00613   * @}
00614   */
00615
00616 #endif /* __STM8S_TIM1_H */
00617
00618 /**
00619   * @}
00620   */
00621
00622
00623 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_tim2.c Source File

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stm8s_tim2.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_tim2.c
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all the functions for the TIM2 peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm8s_tim2.h"
00030
00031 /** @addtogroup STM8S_StdPeriph_Driver
00032   * @{
00033   */
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 /* Private macro -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038 /* Private function prototypes -----------------------------------------------*/
00039 static void TI1_Config(uint8_t TIM2_ICPolarity, uint8_t TIM2_ICSelection, uint8_t TIM2_ICFilter);
00040 static void TI2_Config(uint8_t TIM2_ICPolarity, uint8_t TIM2_ICSelection, uint8_t TIM2_ICFilter);
00041 static void TI3_Config(uint8_t TIM2_ICPolarity, uint8_t TIM2_ICSelection, uint8_t TIM2_ICFilter);
00042 /**
00043   * @addtogroup TIM2_Public_Functions
00044   * @{
00045   */
00046
00047 /**
00048   * @brief  Deinitializes the TIM2 peripheral registers to their default reset values.
00049   * @param  None
00050   * @retval None
00051   */
00052 void TIM2_DeInit(void)
00053 {
00054   TIM2->CR1 = (uint8_t)TIM2_CR1_RESET_VALUE;
00055   TIM2->IER = (uint8_t)TIM2_IER_RESET_VALUE;
00056   TIM2->SR2 = (uint8_t)TIM2_SR2_RESET_VALUE;
00057
00058   /* Disable channels */
00059   TIM2->CCER1 = (uint8_t)TIM2_CCER1_RESET_VALUE;
00060   TIM2->CCER2 = (uint8_t)TIM2_CCER2_RESET_VALUE;
00061
00062
00063   /* Then reset channel registers: it also works if lock level is equal to 2 or 3 */
00064   TIM2->CCER1 = (uint8_t)TIM2_CCER1_RESET_VALUE;
00065   TIM2->CCER2 = (uint8_t)TIM2_CCER2_RESET_VALUE;
00066   TIM2->CCMR1 = (uint8_t)TIM2_CCMR1_RESET_VALUE;
00067   TIM2->CCMR2 = (uint8_t)TIM2_CCMR2_RESET_VALUE;
00068   TIM2->CCMR3 = (uint8_t)TIM2_CCMR3_RESET_VALUE;
00069   TIM2->CNTRH = (uint8_t)TIM2_CNTRH_RESET_VALUE;
00070   TIM2->CNTRL = (uint8_t)TIM2_CNTRL_RESET_VALUE;
00071   TIM2->PSCR = (uint8_t)TIM2_PSCR_RESET_VALUE;
00072   TIM2->ARRH  = (uint8_t)TIM2_ARRH_RESET_VALUE;
00073   TIM2->ARRL  = (uint8_t)TIM2_ARRL_RESET_VALUE;
00074   TIM2->CCR1H = (uint8_t)TIM2_CCR1H_RESET_VALUE;
00075   TIM2->CCR1L = (uint8_t)TIM2_CCR1L_RESET_VALUE;
00076   TIM2->CCR2H = (uint8_t)TIM2_CCR2H_RESET_VALUE;
00077   TIM2->CCR2L = (uint8_t)TIM2_CCR2L_RESET_VALUE;
00078   TIM2->CCR3H = (uint8_t)TIM2_CCR3H_RESET_VALUE;
00079   TIM2->CCR3L = (uint8_t)TIM2_CCR3L_RESET_VALUE;
00080   TIM2->SR1 = (uint8_t)TIM2_SR1_RESET_VALUE;
00081 }
00082
00083 /**
00084   * @brief  Initializes the TIM2 Time Base Unit according to the specified parameters.
00085   * @param    TIM2_Prescaler specifies the Prescaler from TIM2_Prescaler_TypeDef.
00086   * @param    TIM2_Period specifies the Period value.
00087   * @retval None
00088   */
00089 void TIM2_TimeBaseInit( TIM2_Prescaler_TypeDef TIM2_Prescaler,
00090                         uint16_t TIM2_Period)
00091 {
00092   /* Set the Prescaler value */
00093   TIM2->PSCR = (uint8_t)(TIM2_Prescaler);
00094   /* Set the Autoreload value */
00095   TIM2->ARRH = (uint8_t)(TIM2_Period >> 8);
00096   TIM2->ARRL = (uint8_t)(TIM2_Period);
00097 }
00098
00099
00100 /**
00101   * @brief  Initializes the TIM2 Channel1 according to the specified parameters.
00102   * @param   TIM2_OCMode specifies the Output Compare mode  from @ref TIM2_OCMode_TypeDef.
00103   * @param   TIM2_OutputState specifies the Output State  from @ref TIM2_OutputState_TypeDef.
00104   * @param   TIM2_Pulse specifies the Pulse width  value.
00105   * @param   TIM2_OCPolarity specifies the Output Compare Polarity  from @ref TIM2_OCPolarity_TypeDef.
00106   * @retval None
00107   */
00108 void TIM2_OC1Init(TIM2_OCMode_TypeDef TIM2_OCMode,
00109                   TIM2_OutputState_TypeDef TIM2_OutputState,
00110                   uint16_t TIM2_Pulse,
00111                   TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
00112 {
00113   /* Check the parameters */
00114   assert_param(IS_TIM2_OC_MODE_OK(TIM2_OCMode));
00115   assert_param(IS_TIM2_OUTPUT_STATE_OK(TIM2_OutputState));
00116   assert_param(IS_TIM2_OC_POLARITY_OK(TIM2_OCPolarity));
00117
00118   /* Disable the Channel 1: Reset the CCE Bit, Set the Output State , the Output Polarity */
00119   TIM2->CCER1 &= (uint8_t)(~( TIM2_CCER1_CC1E | TIM2_CCER1_CC1P));
00120   /* Set the Output State &  Set the Output Polarity  */
00121   TIM2->CCER1 |= (uint8_t)((uint8_t)(TIM2_OutputState & TIM2_CCER1_CC1E ) |
00122                            (uint8_t)(TIM2_OCPolarity & TIM2_CCER1_CC1P));
00123
00124   /* Reset the Output Compare Bits  & Set the Ouput Compare Mode */
00125   TIM2->CCMR1 = (uint8_t)((uint8_t)(TIM2->CCMR1 & (uint8_t)(~TIM2_CCMR_OCM)) |
00126                           (uint8_t)TIM2_OCMode);
00127
00128   /* Set the Pulse value */
00129   TIM2->CCR1H = (uint8_t)(TIM2_Pulse >> 8);
00130   TIM2->CCR1L = (uint8_t)(TIM2_Pulse);
00131 }
00132
00133
00134 /**
00135   * @brief  Initializes the TIM2 Channel2 according to the specified parameters.
00136   * @param   TIM2_OCMode specifies the Output Compare mode  from @ref TIM2_OCMode_TypeDef.
00137   * @param   TIM2_OutputState specifies the Output State  from @ref TIM2_OutputState_TypeDef.
00138   * @param   TIM2_Pulse specifies the Pulse width  value.
00139   * @param   TIM2_OCPolarity specifies the Output Compare Polarity  from @ref TIM2_OCPolarity_TypeDef.
00140   * @retval None
00141   */
00142 void TIM2_OC2Init(TIM2_OCMode_TypeDef TIM2_OCMode,
00143                   TIM2_OutputState_TypeDef TIM2_OutputState,
00144                   uint16_t TIM2_Pulse,
00145                   TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
00146 {
00147   /* Check the parameters */
00148   assert_param(IS_TIM2_OC_MODE_OK(TIM2_OCMode));
00149   assert_param(IS_TIM2_OUTPUT_STATE_OK(TIM2_OutputState));
00150   assert_param(IS_TIM2_OC_POLARITY_OK(TIM2_OCPolarity));
00151
00152
00153   /* Disable the Channel 1: Reset the CCE Bit, Set the Output State, the Output Polarity */
00154   TIM2->CCER1 &= (uint8_t)(~( TIM2_CCER1_CC2E |  TIM2_CCER1_CC2P ));
00155   /* Set the Output State & Set the Output Polarity */
00156   TIM2->CCER1 |= (uint8_t)((uint8_t)(TIM2_OutputState  & TIM2_CCER1_CC2E ) |
00157                            (uint8_t)(TIM2_OCPolarity & TIM2_CCER1_CC2P));
00158
00159
00160   /* Reset the Output Compare Bits & Set the Output Compare Mode */
00161   TIM2->CCMR2 = (uint8_t)((uint8_t)(TIM2->CCMR2 & (uint8_t)(~TIM2_CCMR_OCM)) |
00162                           (uint8_t)TIM2_OCMode);
00163
00164
00165   /* Set the Pulse value */
00166   TIM2->CCR2H = (uint8_t)(TIM2_Pulse >> 8);
00167   TIM2->CCR2L = (uint8_t)(TIM2_Pulse);
00168 }
00169
00170
00171 /**
00172   * @brief  Initializes the TIM2 Channel3 according to the specified parameters.
00173   * @param   TIM2_OCMode specifies the Output Compare mode from @ref TIM2_OCMode_TypeDef.
00174   * @param   TIM2_OutputState specifies the Output State from @ref TIM2_OutputState_TypeDef.
00175   * @param   TIM2_Pulse specifies the Pulse width value.
00176   * @param   TIM2_OCPolarity specifies the Output Compare Polarity  from @ref TIM2_OCPolarity_TypeDef.
00177   * @retval None
00178   */
00179 void TIM2_OC3Init(TIM2_OCMode_TypeDef TIM2_OCMode,
00180                   TIM2_OutputState_TypeDef TIM2_OutputState,
00181                   uint16_t TIM2_Pulse,
00182                   TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
00183 {
00184   /* Check the parameters */
00185   assert_param(IS_TIM2_OC_MODE_OK(TIM2_OCMode));
00186   assert_param(IS_TIM2_OUTPUT_STATE_OK(TIM2_OutputState));
00187   assert_param(IS_TIM2_OC_POLARITY_OK(TIM2_OCPolarity));
00188   /* Disable the Channel 1: Reset the CCE Bit, Set the Output State, the Output Polarity */
00189   TIM2->CCER2 &= (uint8_t)(~( TIM2_CCER2_CC3E  | TIM2_CCER2_CC3P));
00190   /* Set the Output State & Set the Output Polarity */
00191   TIM2->CCER2 |= (uint8_t)((uint8_t)(TIM2_OutputState & TIM2_CCER2_CC3E) |
00192                            (uint8_t)(TIM2_OCPolarity & TIM2_CCER2_CC3P));
00193
00194   /* Reset the Output Compare Bits & Set the Output Compare Mode */
00195   TIM2->CCMR3 = (uint8_t)((uint8_t)(TIM2->CCMR3 & (uint8_t)(~TIM2_CCMR_OCM)) |
00196                           (uint8_t)TIM2_OCMode);
00197
00198   /* Set the Pulse value */
00199   TIM2->CCR3H = (uint8_t)(TIM2_Pulse >> 8);
00200   TIM2->CCR3L = (uint8_t)(TIM2_Pulse);
00201 }
00202
00203 /**
00204   * @brief  Initializes the TIM2 peripheral according to the specified parameters.
00205   * @param    TIM2_Channel specifies the Input Capture Channel from @ref TIM2_Channel_TypeDef.
00206   * @param   TIM2_ICPolarity specifies the Input Capture Polarity from @ref TIM2_ICPolarity_TypeDef.
00207   * @param   TIM2_ICSelection specifies the Input Capture Selection from @ref TIM2_ICSelection_TypeDef.
00208   * @param   TIM2_ICPrescaler specifies the Input Capture Prescaler from @ref TIM2_ICPSC_TypeDef.
00209   * @param   TIM2_ICFilter specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
00210   * @retval None
00211   */
00212 void TIM2_ICInit(TIM2_Channel_TypeDef TIM2_Channel,
00213                  TIM2_ICPolarity_TypeDef TIM2_ICPolarity,
00214                  TIM2_ICSelection_TypeDef TIM2_ICSelection,
00215                  TIM2_ICPSC_TypeDef TIM2_ICPrescaler,
00216                  uint8_t TIM2_ICFilter)
00217 {
00218   /* Check the parameters */
00219   assert_param(IS_TIM2_CHANNEL_OK(TIM2_Channel));
00220   assert_param(IS_TIM2_IC_POLARITY_OK(TIM2_ICPolarity));
00221   assert_param(IS_TIM2_IC_SELECTION_OK(TIM2_ICSelection));
00222   assert_param(IS_TIM2_IC_PRESCALER_OK(TIM2_ICPrescaler));
00223   assert_param(IS_TIM2_IC_FILTER_OK(TIM2_ICFilter));
00224
00225   if (TIM2_Channel == TIM2_CHANNEL_1)
00226   {
00227     /* TI1 Configuration */
00228     TI1_Config((uint8_t)TIM2_ICPolarity,
00229                (uint8_t)TIM2_ICSelection,
00230                (uint8_t)TIM2_ICFilter);
00231
00232     /* Set the Input Capture Prescaler value */
00233     TIM2_SetIC1Prescaler(TIM2_ICPrescaler);
00234   }
00235   else if (TIM2_Channel == TIM2_CHANNEL_2)
00236   {
00237     /* TI2 Configuration */
00238     TI2_Config((uint8_t)TIM2_ICPolarity,
00239                (uint8_t)TIM2_ICSelection,
00240                (uint8_t)TIM2_ICFilter);
00241
00242     /* Set the Input Capture Prescaler value */
00243     TIM2_SetIC2Prescaler(TIM2_ICPrescaler);
00244   }
00245   else
00246   {
00247     /* TI3 Configuration */
00248     TI3_Config((uint8_t)TIM2_ICPolarity,
00249                (uint8_t)TIM2_ICSelection,
00250                (uint8_t)TIM2_ICFilter);
00251
00252     /* Set the Input Capture Prescaler value */
00253     TIM2_SetIC3Prescaler(TIM2_ICPrescaler);
00254   }
00255 }
00256
00257 /**
00258   * @brief  Configures the TIM2 peripheral in PWM Input Mode according to the specified parameters.
00259     * @param    TIM2_Channel specifies the Input Capture Channel from @ref TIM2_Channel_TypeDef.
00260   * @param   TIM2_ICPolarity specifies the Input Capture Polarity from @ref TIM2_ICPolarity_TypeDef.
00261   * @param   TIM2_ICSelection specifies the Input Capture Selection from @ref TIM2_ICSelection_TypeDef.
00262   * @param   TIM2_ICPrescaler specifies the Input Capture Prescaler from @ref TIM2_ICPSC_TypeDef.
00263   * @param   TIM2_ICFilter specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
00264   * @retval None
00265   */
00266 void TIM2_PWMIConfig(TIM2_Channel_TypeDef TIM2_Channel,
00267                      TIM2_ICPolarity_TypeDef TIM2_ICPolarity,
00268                      TIM2_ICSelection_TypeDef TIM2_ICSelection,
00269                      TIM2_ICPSC_TypeDef TIM2_ICPrescaler,
00270                      uint8_t TIM2_ICFilter)
00271 {
00272   uint8_t icpolarity = (uint8_t)TIM2_ICPOLARITY_RISING;
00273   uint8_t icselection = (uint8_t)TIM2_ICSELECTION_DIRECTTI;
00274
00275   /* Check the parameters */
00276   assert_param(IS_TIM2_PWMI_CHANNEL_OK(TIM2_Channel));
00277   assert_param(IS_TIM2_IC_POLARITY_OK(TIM2_ICPolarity));
00278   assert_param(IS_TIM2_IC_SELECTION_OK(TIM2_ICSelection));
00279   assert_param(IS_TIM2_IC_PRESCALER_OK(TIM2_ICPrescaler));
00280
00281   /* Select the Opposite Input Polarity */
00282   if (TIM2_ICPolarity != TIM2_ICPOLARITY_FALLING)
00283   {
00284     icpolarity = (uint8_t)TIM2_ICPOLARITY_FALLING;
00285   }
00286   else
00287   {
00288     icpolarity = (uint8_t)TIM2_ICPOLARITY_RISING;
00289   }
00290
00291   /* Select the Opposite Input */
00292   if (TIM2_ICSelection == TIM2_ICSELECTION_DIRECTTI)
00293   {
00294     icselection = (uint8_t)TIM2_ICSELECTION_INDIRECTTI;
00295   }
00296   else
00297   {
00298     icselection = (uint8_t)TIM2_ICSELECTION_DIRECTTI;
00299   }
00300
00301   if (TIM2_Channel == TIM2_CHANNEL_1)
00302   {
00303     /* TI1 Configuration */
00304     TI1_Config((uint8_t)TIM2_ICPolarity, (uint8_t)TIM2_ICSelection,
00305                (uint8_t)TIM2_ICFilter);
00306
00307     /* Set the Input Capture Prescaler value */
00308     TIM2_SetIC1Prescaler(TIM2_ICPrescaler);
00309
00310     /* TI2 Configuration */
00311     TI2_Config(icpolarity, icselection, TIM2_ICFilter);
00312
00313     /* Set the Input Capture Prescaler value */
00314     TIM2_SetIC2Prescaler(TIM2_ICPrescaler);
00315   }
00316   else
00317   {
00318     /* TI2 Configuration */
00319     TI2_Config((uint8_t)TIM2_ICPolarity, (uint8_t)TIM2_ICSelection,
00320                (uint8_t)TIM2_ICFilter);
00321
00322     /* Set the Input Capture Prescaler value */
00323     TIM2_SetIC2Prescaler(TIM2_ICPrescaler);
00324
00325     /* TI1 Configuration */
00326     TI1_Config((uint8_t)icpolarity, icselection, (uint8_t)TIM2_ICFilter);
00327
00328     /* Set the Input Capture Prescaler value */
00329     TIM2_SetIC1Prescaler(TIM2_ICPrescaler);
00330   }
00331 }
00332
00333 /**
00334   * @brief  Enables or disables the TIM2 peripheral.
00335   * @param   NewState new state of the TIM2 peripheral. This parameter can
00336   * be ENABLE or DISABLE.
00337   * @retval None
00338   */
00339 void TIM2_Cmd(FunctionalState NewState)
00340 {
00341   /* Check the parameters */
00342   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00343
00344   /* set or Reset the CEN Bit */
00345   if (NewState != DISABLE)
00346   {
00347     TIM2->CR1 |= (uint8_t)TIM2_CR1_CEN;
00348   }
00349   else
00350   {
00351     TIM2->CR1 &= (uint8_t)(~TIM2_CR1_CEN);
00352   }
00353 }
00354
00355 /**
00356   * @brief  Enables or disables the specified TIM2 interrupts.
00357   * @param   NewState new state of the TIM2 peripheral.
00358   * This parameter can be: ENABLE or DISABLE.
00359   * @param   TIM2_IT specifies the TIM2 interrupts sources to be enabled or disabled.
00360   * This parameter can be any combination of the following values:
00361   *                       - TIM2_IT_UPDATE: TIM2 update Interrupt source
00362   *                       - TIM2_IT_CC1: TIM2 Capture Compare 1 Interrupt source
00363   *                       - TIM2_IT_CC2: TIM2 Capture Compare 2 Interrupt source
00364   *                       - TIM2_IT_CC3: TIM2 Capture Compare 3 Interrupt source
00365   * @param   NewState new state of the TIM2 peripheral.
00366   * @retval None
00367   */
00368 void TIM2_ITConfig(TIM2_IT_TypeDef TIM2_IT, FunctionalState NewState)
00369 {
00370   /* Check the parameters */
00371   assert_param(IS_TIM2_IT_OK(TIM2_IT));
00372   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00373
00374   if (NewState != DISABLE)
00375   {
00376     /* Enable the Interrupt sources */
00377     TIM2->IER |= (uint8_t)TIM2_IT;
00378   }
00379   else
00380   {
00381     /* Disable the Interrupt sources */
00382     TIM2->IER &= (uint8_t)(~TIM2_IT);
00383   }
00384 }
00385
00386 /**
00387   * @brief  Enables or Disables the TIM2 Update event.
00388   * @param   NewState new state of the TIM2 peripheral Preload register. This parameter can
00389   * be ENABLE or DISABLE.
00390   * @retval None
00391   */
00392 void TIM2_UpdateDisableConfig(FunctionalState NewState)
00393 {
00394   /* Check the parameters */
00395   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00396
00397   /* Set or Reset the UDIS Bit */
00398   if (NewState != DISABLE)
00399   {
00400     TIM2->CR1 |= (uint8_t)TIM2_CR1_UDIS;
00401   }
00402   else
00403   {
00404     TIM2->CR1 &= (uint8_t)(~TIM2_CR1_UDIS);
00405   }
00406 }
00407
00408 /**
00409   * @brief  Selects the TIM2 Update Request Interrupt source.
00410   * @param   TIM2_UpdateSource specifies the Update source.
00411   * This parameter can be one of the following values
00412   *                       - TIM2_UPDATESOURCE_REGULAR
00413   *                       - TIM2_UPDATESOURCE_GLOBAL
00414   * @retval None
00415   */
00416 void TIM2_UpdateRequestConfig(TIM2_UpdateSource_TypeDef TIM2_UpdateSource)
00417 {
00418   /* Check the parameters */
00419   assert_param(IS_TIM2_UPDATE_SOURCE_OK(TIM2_UpdateSource));
00420
00421   /* Set or Reset the URS Bit */
00422   if (TIM2_UpdateSource != TIM2_UPDATESOURCE_GLOBAL)
00423   {
00424     TIM2->CR1 |= (uint8_t)TIM2_CR1_URS;
00425   }
00426   else
00427   {
00428     TIM2->CR1 &= (uint8_t)(~TIM2_CR1_URS);
00429   }
00430 }
00431
00432 /**
00433   * @brief  Selects the TIM2’s One Pulse Mode.
00434   * @param   TIM2_OPMode specifies the OPM Mode to be used.
00435   * This parameter can be one of the following values
00436   *                    - TIM2_OPMODE_SINGLE
00437   *                    - TIM2_OPMODE_REPETITIVE
00438   * @retval None
00439   */
00440 void TIM2_SelectOnePulseMode(TIM2_OPMode_TypeDef TIM2_OPMode)
00441 {
00442   /* Check the parameters */
00443   assert_param(IS_TIM2_OPM_MODE_OK(TIM2_OPMode));
00444
00445   /* Set or Reset the OPM Bit */
00446   if (TIM2_OPMode != TIM2_OPMODE_REPETITIVE)
00447   {
00448     TIM2->CR1 |= (uint8_t)TIM2_CR1_OPM;
00449   }
00450   else
00451   {
00452     TIM2->CR1 &= (uint8_t)(~TIM2_CR1_OPM);
00453   }
00454 }
00455
00456 /**
00457   * @brief  Configures the TIM2 Prescaler.
00458   * @param   Prescaler specifies the Prescaler Register value
00459   * This parameter can be one of the following values
00460   *                       -  TIM2_PRESCALER_1
00461   *                       -  TIM2_PRESCALER_2
00462   *                       -  TIM2_PRESCALER_4
00463   *                       -  TIM2_PRESCALER_8
00464   *                       -  TIM2_PRESCALER_16
00465   *                       -  TIM2_PRESCALER_32
00466   *                       -  TIM2_PRESCALER_64
00467   *                       -  TIM2_PRESCALER_128
00468   *                       -  TIM2_PRESCALER_256
00469   *                       -  TIM2_PRESCALER_512
00470   *                       -  TIM2_PRESCALER_1024
00471   *                       -  TIM2_PRESCALER_2048
00472   *                       -  TIM2_PRESCALER_4096
00473   *                       -  TIM2_PRESCALER_8192
00474   *                       -  TIM2_PRESCALER_16384
00475   *                       -  TIM2_PRESCALER_32768
00476   * @param   TIM2_PSCReloadMode specifies the TIM2 Prescaler Reload mode.
00477   * This parameter can be one of the following values
00478   *                       - TIM2_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded
00479   *                         immediately.
00480   *                       - TIM2_PSCRELOADMODE_UPDATE: The Prescaler is loaded at
00481   *                         the update event.
00482   * @retval None
00483   */
00484 void TIM2_PrescalerConfig(TIM2_Prescaler_TypeDef Prescaler,
00485                           TIM2_PSCReloadMode_TypeDef TIM2_PSCReloadMode)
00486 {
00487   /* Check the parameters */
00488   assert_param(IS_TIM2_PRESCALER_RELOAD_OK(TIM2_PSCReloadMode));
00489   assert_param(IS_TIM2_PRESCALER_OK(Prescaler));
00490
00491   /* Set the Prescaler value */
00492   TIM2->PSCR = (uint8_t)Prescaler;
00493
00494   /* Set or reset the UG Bit */
00495   TIM2->EGR = (uint8_t)TIM2_PSCReloadMode;
00496 }
00497
00498 /**
00499   * @brief  Forces the TIM2 Channel1 output waveform to active or inactive level.
00500   * @param   TIM2_ForcedAction specifies the forced Action to be set to the output waveform.
00501   * This parameter can be one of the following values:
00502   *                       - TIM2_FORCEDACTION_ACTIVE: Force active level on OC1REF
00503   *                       - TIM2_FORCEDACTION_INACTIVE: Force inactive level on
00504   *                         OC1REF.
00505   * @retval None
00506   */
00507 void TIM2_ForcedOC1Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
00508 {
00509   /* Check the parameters */
00510   assert_param(IS_TIM2_FORCED_ACTION_OK(TIM2_ForcedAction));
00511
00512   /* Reset the OCM Bits & Configure the Forced output Mode */
00513   TIM2->CCMR1  =  (uint8_t)((uint8_t)(TIM2->CCMR1 & (uint8_t)(~TIM2_CCMR_OCM))
00514                             | (uint8_t)TIM2_ForcedAction);
00515 }
00516
00517 /**
00518   * @brief  Forces the TIM2 Channel2 output waveform to active or inactive level.
00519   * @param   TIM2_ForcedAction specifies the forced Action to be set to the output waveform.
00520   * This parameter can be one of the following values:
00521   *                       - TIM2_FORCEDACTION_ACTIVE: Force active level on OC2REF
00522   *                       - TIM2_FORCEDACTION_INACTIVE: Force inactive level on
00523   *                         OC2REF.
00524   * @retval None
00525   */
00526 void TIM2_ForcedOC2Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
00527 {
00528   /* Check the parameters */
00529   assert_param(IS_TIM2_FORCED_ACTION_OK(TIM2_ForcedAction));
00530
00531   /* Reset the OCM Bits & Configure the Forced output Mode */
00532   TIM2->CCMR2 = (uint8_t)((uint8_t)(TIM2->CCMR2 & (uint8_t)(~TIM2_CCMR_OCM))
00533                           | (uint8_t)TIM2_ForcedAction);
00534 }
00535
00536 /**
00537   * @brief  Forces the TIM2 Channel3 output waveform to active or inactive level.
00538   * @param   TIM2_ForcedAction specifies the forced Action to be set to the output waveform.
00539   * This parameter can be one of the following values:
00540   *                       - TIM2_FORCEDACTION_ACTIVE: Force active level on OC3REF
00541   *                       - TIM2_FORCEDACTION_INACTIVE: Force inactive level on
00542   *                         OC3REF.
00543   * @retval None
00544   */
00545 void TIM2_ForcedOC3Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
00546 {
00547   /* Check the parameters */
00548   assert_param(IS_TIM2_FORCED_ACTION_OK(TIM2_ForcedAction));
00549
00550   /* Reset the OCM Bits & Configure the Forced output Mode */
00551   TIM2->CCMR3  =  (uint8_t)((uint8_t)(TIM2->CCMR3 & (uint8_t)(~TIM2_CCMR_OCM))
00552                             | (uint8_t)TIM2_ForcedAction);
00553 }
00554
00555 /**
00556   * @brief  Enables or disables TIM2 peripheral Preload register on ARR.
00557   * @param   NewState new state of the TIM2 peripheral Preload register.
00558   * This parameter can be ENABLE or DISABLE.
00559   * @retval None
00560   */
00561 void TIM2_ARRPreloadConfig(FunctionalState NewState)
00562 {
00563   /* Check the parameters */
00564   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00565
00566   /* Set or Reset the ARPE Bit */
00567   if (NewState != DISABLE)
00568   {
00569     TIM2->CR1 |= (uint8_t)TIM2_CR1_ARPE;
00570   }
00571   else
00572   {
00573     TIM2->CR1 &= (uint8_t)(~TIM2_CR1_ARPE);
00574   }
00575 }
00576
00577 /**
00578   * @brief  Enables or disables the TIM2 peripheral Preload Register on CCR1.
00579   * @param   NewState new state of the Capture Compare Preload register.
00580   * This parameter can be ENABLE or DISABLE.
00581   * @retval None
00582   */
00583 void TIM2_OC1PreloadConfig(FunctionalState NewState)
00584 {
00585   /* Check the parameters */
00586   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00587
00588   /* Set or Reset the OC1PE Bit */
00589   if (NewState != DISABLE)
00590   {
00591     TIM2->CCMR1 |= (uint8_t)TIM2_CCMR_OCxPE;
00592   }
00593   else
00594   {
00595     TIM2->CCMR1 &= (uint8_t)(~TIM2_CCMR_OCxPE);
00596   }
00597 }
00598
00599 /**
00600   * @brief  Enables or disables the TIM2 peripheral Preload Register on CCR2.
00601   * @param   NewState new state of the Capture Compare Preload register.
00602   * This parameter can be ENABLE or DISABLE.
00603   * @retval None
00604   */
00605 void TIM2_OC2PreloadConfig(FunctionalState NewState)
00606 {
00607   /* Check the parameters */
00608   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00609
00610   /* Set or Reset the OC2PE Bit */
00611   if (NewState != DISABLE)
00612   {
00613     TIM2->CCMR2 |= (uint8_t)TIM2_CCMR_OCxPE;
00614   }
00615   else
00616   {
00617     TIM2->CCMR2 &= (uint8_t)(~TIM2_CCMR_OCxPE);
00618   }
00619 }
00620
00621 /**
00622   * @brief  Enables or disables the TIM2 peripheral Preload Register on CCR3.
00623   * @param   NewState new state of the Capture Compare Preload register.
00624   * This parameter can be ENABLE or DISABLE.
00625   * @retval None
00626   */
00627 void TIM2_OC3PreloadConfig(FunctionalState NewState)
00628 {
00629   /* Check the parameters */
00630   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00631
00632   /* Set or Reset the OC3PE Bit */
00633   if (NewState != DISABLE)
00634   {
00635     TIM2->CCMR3 |= (uint8_t)TIM2_CCMR_OCxPE;
00636   }
00637   else
00638   {
00639     TIM2->CCMR3 &= (uint8_t)(~TIM2_CCMR_OCxPE);
00640   }
00641 }
00642
00643 /**
00644   * @brief  Configures the TIM2 event to be generated by software.
00645   * @param   TIM2_EventSource specifies the event source.
00646   * This parameter can be one of the following values:
00647   *                       - TIM2_EVENTSOURCE_UPDATE: TIM2 update Event source
00648   *                       - TIM2_EVENTSOURCE_CC1: TIM2 Capture Compare 1 Event source
00649   *                       - TIM2_EVENTSOURCE_CC2: TIM2 Capture Compare 2 Event source
00650   *                       - TIM2_EVENTSOURCE_CC3: TIM2 Capture Compare 3 Event source
00651   * @retval None
00652   */
00653 void TIM2_GenerateEvent(TIM2_EventSource_TypeDef TIM2_EventSource)
00654 {
00655   /* Check the parameters */
00656   assert_param(IS_TIM2_EVENT_SOURCE_OK(TIM2_EventSource));
00657
00658   /* Set the event sources */
00659   TIM2->EGR = (uint8_t)TIM2_EventSource;
00660 }
00661
00662 /**
00663   * @brief  Configures the TIM2 Channel 1 polarity.
00664   * @param   TIM2_OCPolarity specifies the OC1 Polarity.
00665   * This parameter can be one of the following values:
00666   *                       - TIM2_OCPOLARITY_LOW: Output Compare active low
00667   *                       - TIM2_OCPOLARITY_HIGH: Output Compare active high
00668   * @retval None
00669   */
00670 void TIM2_OC1PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
00671 {
00672   /* Check the parameters */
00673   assert_param(IS_TIM2_OC_POLARITY_OK(TIM2_OCPolarity));
00674
00675   /* Set or Reset the CC1P Bit */
00676   if (TIM2_OCPolarity != TIM2_OCPOLARITY_HIGH)
00677   {
00678     TIM2->CCER1 |= (uint8_t)TIM2_CCER1_CC1P;
00679   }
00680   else
00681   {
00682     TIM2->CCER1 &= (uint8_t)(~TIM2_CCER1_CC1P);
00683   }
00684 }
00685
00686 /**
00687   * @brief  Configures the TIM2 Channel 2 polarity.
00688   * @param   TIM2_OCPolarity specifies the OC2 Polarity.
00689   * This parameter can be one of the following values:
00690   *                       - TIM2_OCPOLARITY_LOW: Output Compare active low
00691   *                       - TIM2_OCPOLARITY_HIGH: Output Compare active high
00692   * @retval None
00693   */
00694 void TIM2_OC2PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
00695 {
00696   /* Check the parameters */
00697   assert_param(IS_TIM2_OC_POLARITY_OK(TIM2_OCPolarity));
00698
00699   /* Set or Reset the CC2P Bit */
00700   if (TIM2_OCPolarity != TIM2_OCPOLARITY_HIGH)
00701   {
00702     TIM2->CCER1 |= TIM2_CCER1_CC2P;
00703   }
00704   else
00705   {
00706     TIM2->CCER1 &= (uint8_t)(~TIM2_CCER1_CC2P);
00707   }
00708 }
00709
00710 /**
00711   * @brief  Configures the TIM2 Channel 3 polarity.
00712   * @param   TIM2_OCPolarity specifies the OC3 Polarity.
00713   * This parameter can be one of the following values:
00714   *                       - TIM2_OCPOLARITY_LOW: Output Compare active low
00715   *                       - TIM2_OCPOLARITY_HIGH: Output Compare active high
00716   * @retval None
00717   */
00718 void TIM2_OC3PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
00719 {
00720   /* Check the parameters */
00721   assert_param(IS_TIM2_OC_POLARITY_OK(TIM2_OCPolarity));
00722
00723   /* Set or Reset the CC3P Bit */
00724   if (TIM2_OCPolarity != TIM2_OCPOLARITY_HIGH)
00725   {
00726     TIM2->CCER2 |= (uint8_t)TIM2_CCER2_CC3P;
00727   }
00728   else
00729   {
00730     TIM2->CCER2 &= (uint8_t)(~TIM2_CCER2_CC3P);
00731   }
00732 }
00733
00734 /**
00735   * @brief  Enables or disables the TIM2 Capture Compare Channel x.
00736   * @param   TIM2_Channel specifies the TIM2 Channel.
00737   * This parameter can be one of the following values:
00738   *                       - TIM2_CHANNEL_1: TIM2 Channel1
00739   *                       - TIM2_CHANNEL_2: TIM2 Channel2
00740   *                       - TIM2_CHANNEL_3: TIM2 Channel3
00741   * @param   NewState specifies the TIM2 Channel CCxE bit new state.
00742   * This parameter can be: ENABLE or DISABLE.
00743   * @retval None
00744   */
00745 void TIM2_CCxCmd(TIM2_Channel_TypeDef TIM2_Channel, FunctionalState NewState)
00746 {
00747   /* Check the parameters */
00748   assert_param(IS_TIM2_CHANNEL_OK(TIM2_Channel));
00749   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00750
00751   if (TIM2_Channel == TIM2_CHANNEL_1)
00752   {
00753     /* Set or Reset the CC1E Bit */
00754     if (NewState != DISABLE)
00755     {
00756       TIM2->CCER1 |= (uint8_t)TIM2_CCER1_CC1E;
00757     }
00758     else
00759     {
00760       TIM2->CCER1 &= (uint8_t)(~TIM2_CCER1_CC1E);
00761     }
00762
00763   }
00764   else if (TIM2_Channel == TIM2_CHANNEL_2)
00765   {
00766     /* Set or Reset the CC2E Bit */
00767     if (NewState != DISABLE)
00768     {
00769       TIM2->CCER1 |= (uint8_t)TIM2_CCER1_CC2E;
00770     }
00771     else
00772     {
00773       TIM2->CCER1 &= (uint8_t)(~TIM2_CCER1_CC2E);
00774     }
00775   }
00776   else
00777   {
00778     /* Set or Reset the CC3E Bit */
00779     if (NewState != DISABLE)
00780     {
00781       TIM2->CCER2 |= (uint8_t)TIM2_CCER2_CC3E;
00782     }
00783     else
00784     {
00785       TIM2->CCER2 &= (uint8_t)(~TIM2_CCER2_CC3E);
00786     }
00787   }
00788 }
00789
00790 /**
00791   * @brief  Selects the TIM2 Output Compare Mode. This function disables the
00792   * selected channel before changing the Output Compare Mode. User has to
00793   * enable this channel using TIM2_CCxCmd and TIM2_CCxNCmd functions.
00794   * @param   TIM2_Channel specifies the TIM2 Channel.
00795   * This parameter can be one of the following values:
00796   *                       - TIM2_CHANNEL_1: TIM2 Channel1
00797   *                       - TIM2_CHANNEL_2: TIM2 Channel2
00798   *                       - TIM2_CHANNEL_3: TIM2 Channel3
00799   * @param   TIM2_OCMode specifies the TIM2 Output Compare Mode.
00800   * This parameter can be one of the following values:
00801   *                       - TIM2_OCMODE_TIMING
00802   *                       - TIM2_OCMODE_ACTIVE
00803   *                       - TIM2_OCMODE_TOGGLE
00804   *                       - TIM2_OCMODE_PWM1
00805   *                       - TIM2_OCMODE_PWM2
00806   *                       - TIM2_FORCEDACTION_ACTIVE
00807   *                       - TIM2_FORCEDACTION_INACTIVE
00808   * @retval None
00809   */
00810 void TIM2_SelectOCxM(TIM2_Channel_TypeDef TIM2_Channel, TIM2_OCMode_TypeDef TIM2_OCMode)
00811 {
00812   /* Check the parameters */
00813   assert_param(IS_TIM2_CHANNEL_OK(TIM2_Channel));
00814   assert_param(IS_TIM2_OCM_OK(TIM2_OCMode));
00815
00816   if (TIM2_Channel == TIM2_CHANNEL_1)
00817   {
00818     /* Disable the Channel 1: Reset the CCE Bit */
00819     TIM2->CCER1 &= (uint8_t)(~TIM2_CCER1_CC1E);
00820
00821     /* Reset the Output Compare Bits & Set the Output Compare Mode */
00822     TIM2->CCMR1 = (uint8_t)((uint8_t)(TIM2->CCMR1 & (uint8_t)(~TIM2_CCMR_OCM))
00823                             | (uint8_t)TIM2_OCMode);
00824   }
00825   else if (TIM2_Channel == TIM2_CHANNEL_2)
00826   {
00827     /* Disable the Channel 2: Reset the CCE Bit */
00828     TIM2->CCER1 &= (uint8_t)(~TIM2_CCER1_CC2E);
00829
00830     /* Reset the Output Compare Bits & Set the Output Compare Mode */
00831     TIM2->CCMR2 = (uint8_t)((uint8_t)(TIM2->CCMR2 & (uint8_t)(~TIM2_CCMR_OCM))
00832                             | (uint8_t)TIM2_OCMode);
00833   }
00834   else
00835   {
00836     /* Disable the Channel 3: Reset the CCE Bit */
00837     TIM2->CCER2 &= (uint8_t)(~TIM2_CCER2_CC3E);
00838
00839     /* Reset the Output Compare Bits & Set the Output Compare Mode */
00840     TIM2->CCMR3 = (uint8_t)((uint8_t)(TIM2->CCMR3 & (uint8_t)(~TIM2_CCMR_OCM))
00841                             | (uint8_t)TIM2_OCMode);
00842   }
00843 }
00844
00845 /**
00846   * @brief  Sets the TIM2 Counter Register value.
00847   * @param   Counter specifies the Counter register new value.
00848   * This parameter is between 0x0000 and 0xFFFF.
00849   * @retval None
00850   */
00851 void TIM2_SetCounter(uint16_t Counter)
00852 {
00853   /* Set the Counter Register value */
00854   TIM2->CNTRH = (uint8_t)(Counter >> 8);
00855   TIM2->CNTRL = (uint8_t)(Counter);
00856 }
00857
00858 /**
00859   * @brief  Sets the TIM2 Autoreload Register value.
00860   * @param   Autoreload specifies the Autoreload register new value.
00861   * This parameter is between 0x0000 and 0xFFFF.
00862   * @retval None
00863   */
00864 void TIM2_SetAutoreload(uint16_t Autoreload)
00865 {
00866   /* Set the Autoreload Register value */
00867   TIM2->ARRH = (uint8_t)(Autoreload >> 8);
00868   TIM2->ARRL = (uint8_t)(Autoreload);
00869 }
00870
00871 /**
00872   * @brief  Sets the TIM2 Capture Compare1 Register value.
00873   * @param   Compare1 specifies the Capture Compare1 register new value.
00874   * This parameter is between 0x0000 and 0xFFFF.
00875   * @retval None
00876   */
00877 void TIM2_SetCompare1(uint16_t Compare1)
00878 {
00879   /* Set the Capture Compare1 Register value */
00880   TIM2->CCR1H = (uint8_t)(Compare1 >> 8);
00881   TIM2->CCR1L = (uint8_t)(Compare1);
00882 }
00883
00884 /**
00885   * @brief  Sets the TIM2 Capture Compare2 Register value.
00886   * @param   Compare2 specifies the Capture Compare2 register new value.
00887   * This parameter is between 0x0000 and 0xFFFF.
00888   * @retval None
00889   */
00890 void TIM2_SetCompare2(uint16_t Compare2)
00891 {
00892   /* Set the Capture Compare2 Register value */
00893   TIM2->CCR2H = (uint8_t)(Compare2 >> 8);
00894   TIM2->CCR2L = (uint8_t)(Compare2);
00895 }
00896
00897 /**
00898   * @brief  Sets the TIM2 Capture Compare3 Register value.
00899   * @param   Compare3 specifies the Capture Compare3 register new value.
00900   * This parameter is between 0x0000 and 0xFFFF.
00901   * @retval None
00902   */
00903 void TIM2_SetCompare3(uint16_t Compare3)
00904 {
00905   /* Set the Capture Compare3 Register value */
00906   TIM2->CCR3H = (uint8_t)(Compare3 >> 8);
00907   TIM2->CCR3L = (uint8_t)(Compare3);
00908 }
00909
00910 /**
00911   * @brief  Sets the TIM2 Input Capture 1 Prescaler.
00912   * @param   TIM2_IC1Prescaler specifies the Input Capture prescaler new value
00913   * This parameter can be one of the following values:
00914   *                       - TIM2_ICPSC_DIV1: no prescaler
00915   *                       - TIM2_ICPSC_DIV2: capture is done once every 2 events
00916   *                       - TIM2_ICPSC_DIV4: capture is done once every 4 events
00917   *                       - TIM2_ICPSC_DIV8: capture is done once every 8 events
00918   * @retval None
00919   */
00920 void TIM2_SetIC1Prescaler(TIM2_ICPSC_TypeDef TIM2_IC1Prescaler)
00921 {
00922   /* Check the parameters */
00923   assert_param(IS_TIM2_IC_PRESCALER_OK(TIM2_IC1Prescaler));
00924
00925   /* Reset the IC1PSC Bits &Set the IC1PSC value */
00926   TIM2->CCMR1 = (uint8_t)((uint8_t)(TIM2->CCMR1 & (uint8_t)(~TIM2_CCMR_ICxPSC))
00927                           | (uint8_t)TIM2_IC1Prescaler);
00928 }
00929
00930 /**
00931   * @brief  Sets the TIM2 Input Capture 2 prescaler.
00932   * @param   TIM2_IC2Prescaler specifies the Input Capture prescaler new value
00933   * This parameter can be one of the following values:
00934   *                       - TIM2_ICPSC_DIV1: no prescaler
00935   *                       - TIM2_ICPSC_DIV2: capture is done once every 2 events
00936   *                       - TIM2_ICPSC_DIV4: capture is done once every 4 events
00937   *                       - TIM2_ICPSC_DIV8: capture is done once every 8 events
00938   * @retval None
00939   */
00940 void TIM2_SetIC2Prescaler(TIM2_ICPSC_TypeDef TIM2_IC2Prescaler)
00941 {
00942   /* Check the parameters */
00943   assert_param(IS_TIM2_IC_PRESCALER_OK(TIM2_IC2Prescaler));
00944
00945   /* Reset the IC1PSC Bits &Set the IC1PSC value */
00946   TIM2->CCMR2 = (uint8_t)((uint8_t)(TIM2->CCMR2 & (uint8_t)(~TIM2_CCMR_ICxPSC))
00947                           | (uint8_t)TIM2_IC2Prescaler);
00948 }
00949
00950 /**
00951   * @brief  Sets the TIM2 Input Capture 3 prescaler.
00952   * @param   TIM2_IC3Prescaler specifies the Input Capture prescaler new value
00953   * This parameter can be one of the following values:
00954   *                       - TIM2_ICPSC_DIV1: no prescaler
00955   *                       - TIM2_ICPSC_DIV2: capture is done once every 2 events
00956   *                       - TIM2_ICPSC_DIV4: capture is done once every 4 events
00957   *                       - TIM2_ICPSC_DIV8: capture is done once every 8 events
00958   * @retval None
00959   */
00960 void TIM2_SetIC3Prescaler(TIM2_ICPSC_TypeDef TIM2_IC3Prescaler)
00961 {
00962
00963   /* Check the parameters */
00964   assert_param(IS_TIM2_IC_PRESCALER_OK(TIM2_IC3Prescaler));
00965   /* Reset the IC1PSC Bits &Set the IC1PSC value */
00966   TIM2->CCMR3 = (uint8_t)((uint8_t)(TIM2->CCMR3 & (uint8_t)(~TIM2_CCMR_ICxPSC))
00967                           | (uint8_t)TIM2_IC3Prescaler);
00968 }
00969
00970 /**
00971   * @brief  Gets the TIM2 Input Capture 1 value.
00972   * @param  None
00973   * @retval Capture Compare 1 Register value.
00974   */
00975 uint16_t TIM2_GetCapture1(void)
00976 {
00977   /* Get the Capture 1 Register value */
00978   uint16_t tmpccr1 = 0;
00979   uint8_t tmpccr1l=0, tmpccr1h=0;
00980
00981   tmpccr1h = TIM2->CCR1H;
00982   tmpccr1l = TIM2->CCR1L;
00983
00984   tmpccr1 = (uint16_t)(tmpccr1l);
00985   tmpccr1 |= (uint16_t)((uint16_t)tmpccr1h << 8);
00986   /* Get the Capture 1 Register value */
00987   return (uint16_t)tmpccr1;
00988 }
00989
00990 /**
00991   * @brief  Gets the TIM2 Input Capture 2 value.
00992   * @param  None
00993   * @retval Capture Compare 2 Register value.
00994   */
00995 uint16_t TIM2_GetCapture2(void)
00996 {
00997   /* Get the Capture 2 Register value */
00998   uint16_t tmpccr2 = 0;
00999   uint8_t tmpccr2l=0, tmpccr2h=0;
01000
01001   tmpccr2h = TIM2->CCR2H;
01002   tmpccr2l = TIM2->CCR2L;
01003
01004   tmpccr2 = (uint16_t)(tmpccr2l);
01005   tmpccr2 |= (uint16_t)((uint16_t)tmpccr2h << 8);
01006   /* Get the Capture 2 Register value */
01007   return (uint16_t)tmpccr2;
01008 }
01009
01010 /**
01011   * @brief  Gets the TIM2 Input Capture 3 value.
01012   * @param  None
01013   * @retval Capture Compare 3 Register value.
01014   */
01015 uint16_t TIM2_GetCapture3(void)
01016 {
01017   /* Get the Capture 3 Register value */
01018   uint16_t tmpccr3 = 0;
01019   uint8_t tmpccr3l=0, tmpccr3h=0;
01020
01021   tmpccr3h = TIM2->CCR3H;
01022   tmpccr3l = TIM2->CCR3L;
01023
01024   tmpccr3 = (uint16_t)(tmpccr3l);
01025   tmpccr3 |= (uint16_t)((uint16_t)tmpccr3h << 8);
01026   /* Get the Capture 3 Register value */
01027   return (uint16_t)tmpccr3;
01028 }
01029
01030 /**
01031   * @brief  Gets the TIM2 Counter value.
01032   * @param  None
01033   * @retval Counter Register value.
01034   */
01035 uint16_t TIM2_GetCounter(void)
01036 {
01037   uint16_t tmpcntr = 0;
01038
01039   tmpcntr =  ((uint16_t)TIM2->CNTRH << 8);
01040   /* Get the Counter Register value */
01041   return (uint16_t)( tmpcntr| (uint16_t)(TIM2->CNTRL));
01042 }
01043
01044 /**
01045   * @brief  Gets the TIM2 Prescaler value.
01046   * @param  None
01047   * @retval Prescaler Register configuration value  @ref TIM2_Prescaler_TypeDef.
01048   */
01049 TIM2_Prescaler_TypeDef TIM2_GetPrescaler(void)
01050 {
01051   /* Get the Prescaler Register value */
01052   return (TIM2_Prescaler_TypeDef)(TIM2->PSCR);
01053 }
01054
01055 /**
01056   * @brief  Checks whether the specified TIM2 flag is set or not.
01057   * @param   TIM2_FLAG specifies the flag to check.
01058   * This parameter can be one of the following values:
01059   *                       - TIM2_FLAG_UPDATE: TIM2 update Flag
01060   *                       - TIM2_FLAG_CC1: TIM2 Capture Compare 1 Flag
01061   *                       - TIM2_FLAG_CC2: TIM2 Capture Compare 2 Flag
01062   *                       - TIM2_FLAG_CC3: TIM2 Capture Compare 3 Flag
01063   *                       - TIM2_FLAG_CC1OF: TIM2 Capture Compare 1 over capture Flag
01064   *                       - TIM2_FLAG_CC2OF: TIM2 Capture Compare 2 over capture Flag
01065   *                       - TIM2_FLAG_CC3OF: TIM2 Capture Compare 3 over capture Flag
01066   * @retval FlagStatus The new state of TIM2_FLAG (SET or RESET).
01067   */
01068 FlagStatus TIM2_GetFlagStatus(TIM2_FLAG_TypeDef TIM2_FLAG)
01069 {
01070   FlagStatus bitstatus = RESET;
01071   uint8_t tim2_flag_l = 0, tim2_flag_h = 0;
01072
01073   /* Check the parameters */
01074   assert_param(IS_TIM2_GET_FLAG_OK(TIM2_FLAG));
01075
01076   tim2_flag_l = (uint8_t)(TIM2->SR1 & (uint8_t)TIM2_FLAG);
01077   tim2_flag_h = (uint8_t)((uint16_t)TIM2_FLAG >> 8);
01078
01079   if ((tim2_flag_l | (uint8_t)(TIM2->SR2 & tim2_flag_h)) != (uint8_t)RESET )
01080   {
01081     bitstatus = SET;
01082   }
01083   else
01084   {
01085     bitstatus = RESET;
01086   }
01087   return (FlagStatus)bitstatus;
01088 }
01089
01090 /**
01091   * @brief  Clears the TIM2’s pending flags.
01092   * @param   TIM2_FLAG specifies the flag to clear.
01093   * This parameter can be one of the following values:
01094   *                       - TIM2_FLAG_UPDATE: TIM2 update Flag
01095   *                       - TIM2_FLAG_CC1: TIM2 Capture Compare 1 Flag
01096   *                       - TIM2_FLAG_CC2: TIM2 Capture Compare 2 Flag
01097   *                       - TIM2_FLAG_CC3: TIM2 Capture Compare 3 Flag
01098   *                       - TIM2_FLAG_CC1OF: TIM2 Capture Compare 1 over capture Flag
01099   *                       - TIM2_FLAG_CC2OF: TIM2 Capture Compare 2 over capture Flag
01100   *                       - TIM2_FLAG_CC3OF: TIM2 Capture Compare 3 over capture Flag
01101   * @retval None.
01102   */
01103 void TIM2_ClearFlag(TIM2_FLAG_TypeDef TIM2_FLAG)
01104 {
01105   /* Check the parameters */
01106   assert_param(IS_TIM2_CLEAR_FLAG_OK(TIM2_FLAG));
01107
01108   /* Clear the flags (rc_w0) clear this bit by writing 0. Writing ‘1’ has no effect*/
01109   TIM2->SR1 = (uint8_t)(~((uint8_t)(TIM2_FLAG)));
01110   TIM2->SR2 = (uint8_t)(~((uint8_t)((uint8_t)TIM2_FLAG >> 8)));
01111 }
01112
01113 /**
01114   * @brief  Checks whether the TIM2 interrupt has occurred or not.
01115   * @param   TIM2_IT specifies the TIM2 interrupt source to check.
01116   * This parameter can be one of the following values:
01117   *                       - TIM2_IT_UPDATE: TIM2 update Interrupt source
01118   *                       - TIM2_IT_CC1: TIM2 Capture Compare 1 Interrupt source
01119   *                       - TIM2_IT_CC2: TIM2 Capture Compare 2 Interrupt source
01120   *                       - TIM2_IT_CC3: TIM2 Capture Compare 3 Interrupt source
01121   * @retval ITStatus The new state of the TIM2_IT(SET or RESET).
01122   */
01123 ITStatus TIM2_GetITStatus(TIM2_IT_TypeDef TIM2_IT)
01124 {
01125   ITStatus bitstatus = RESET;
01126   uint8_t TIM2_itStatus = 0, TIM2_itEnable = 0;
01127
01128   /* Check the parameters */
01129   assert_param(IS_TIM2_GET_IT_OK(TIM2_IT));
01130
01131   TIM2_itStatus = (uint8_t)(TIM2->SR1 & TIM2_IT);
01132
01133   TIM2_itEnable = (uint8_t)(TIM2->IER & TIM2_IT);
01134
01135   if ((TIM2_itStatus != (uint8_t)RESET ) && (TIM2_itEnable != (uint8_t)RESET ))
01136   {
01137     bitstatus = SET;
01138   }
01139   else
01140   {
01141     bitstatus = RESET;
01142   }
01143   return (ITStatus)(bitstatus);
01144 }
01145
01146 /**
01147   * @brief  Clears the TIM2's interrupt pending bits.
01148   * @param   TIM2_IT specifies the pending bit to clear.
01149   * This parameter can be one of the following values:
01150   *                       - TIM2_IT_UPDATE: TIM2 update Interrupt source
01151   *                       - TIM2_IT_CC1: TIM2 Capture Compare 1 Interrupt source
01152   *                       - TIM2_IT_CC2: TIM2 Capture Compare 2 Interrupt source
01153   *                       - TIM2_IT_CC3: TIM2 Capture Compare 3 Interrupt source
01154   * @retval None.
01155   */
01156 void TIM2_ClearITPendingBit(TIM2_IT_TypeDef TIM2_IT)
01157 {
01158   /* Check the parameters */
01159   assert_param(IS_TIM2_IT_OK(TIM2_IT));
01160
01161   /* Clear the IT pending Bit */
01162   TIM2->SR1 = (uint8_t)(~TIM2_IT);
01163 }
01164
01165 /**
01166   * @brief  Configure the TI1 as Input.
01167   * @param   TIM2_ICPolarity  The Input Polarity.
01168   * This parameter can be one of the following values:
01169   *                       - TIM2_ICPOLARITY_FALLING
01170   *                       - TIM2_ICPOLARITY_RISING
01171   * @param   TIM2_ICSelection specifies the input to be used.
01172   * This parameter can be one of the following values:
01173   *                       - TIM2_ICSELECTION_DIRECTTI: TIM2 Input 1 is selected to
01174   *                         be connected to IC1.
01175   *                       - TIM2_ICSELECTION_INDIRECTTI: TIM2 Input 1 is selected to
01176   *                         be connected to IC2.
01177   * @param   TIM2_ICFilter Specifies the Input Capture Filter.
01178   * This parameter must be a value between 0x00 and 0x0F.
01179   * @retval None
01180   */
01181 static void TI1_Config(uint8_t TIM2_ICPolarity,
01182                        uint8_t TIM2_ICSelection,
01183                        uint8_t TIM2_ICFilter)
01184 {
01185   /* Disable the Channel 1: Reset the CCE Bit */
01186   TIM2->CCER1 &= (uint8_t)(~TIM2_CCER1_CC1E);
01187
01188   /* Select the Input and set the filter */
01189   TIM2->CCMR1  = (uint8_t)((uint8_t)(TIM2->CCMR1 & (uint8_t)(~(uint8_t)( TIM2_CCMR_CCxS | TIM2_CCMR_ICxF )))
01190                            | (uint8_t)(((TIM2_ICSelection)) | ((uint8_t)( TIM2_ICFilter << 4))));
01191
01192   /* Select the Polarity */
01193   if (TIM2_ICPolarity != TIM2_ICPOLARITY_RISING)
01194   {
01195     TIM2->CCER1 |= TIM2_CCER1_CC1P;
01196   }
01197   else
01198   {
01199     TIM2->CCER1 &= (uint8_t)(~TIM2_CCER1_CC1P);
01200   }
01201   /* Set the CCE Bit */
01202   TIM2->CCER1 |= TIM2_CCER1_CC1E;
01203 }
01204
01205 /**
01206   * @brief  Configure the TI2 as Input.
01207   * @param   TIM2_ICPolarity  The Input Polarity.
01208   * This parameter can be one of the following values:
01209   *                       - TIM2_ICPOLARITY_FALLING
01210   *                       - TIM2_ICPOLARITY_RISING
01211   * @param   TIM2_ICSelection specifies the input to be used.
01212   * This parameter can be one of the following values:
01213   *                       - TIM2_ICSELECTION_DIRECTTI: TIM2 Input 2 is selected to
01214   *                         be connected to IC2.
01215   *                       - TIM2_ICSELECTION_INDIRECTTI: TIM2 Input 2 is selected to
01216   *                         be connected to IC1.
01217   * @param   TIM2_ICFilter Specifies the Input Capture Filter.
01218   * This parameter must be a value between 0x00 and 0x0F.
01219   * @retval None
01220   */
01221 static void TI2_Config(uint8_t TIM2_ICPolarity,
01222                        uint8_t TIM2_ICSelection,
01223                        uint8_t TIM2_ICFilter)
01224 {
01225   /* Disable the Channel 2: Reset the CCE Bit */
01226   TIM2->CCER1 &= (uint8_t)(~TIM2_CCER1_CC2E);
01227
01228   /* Select the Input and set the filter */
01229   TIM2->CCMR2 = (uint8_t)((uint8_t)(TIM2->CCMR2 & (uint8_t)(~(uint8_t)( TIM2_CCMR_CCxS | TIM2_CCMR_ICxF )))
01230                           | (uint8_t)(( (TIM2_ICSelection)) | ((uint8_t)( TIM2_ICFilter << 4))));
01231
01232
01233   /* Select the Polarity */
01234   if (TIM2_ICPolarity != TIM2_ICPOLARITY_RISING)
01235   {
01236     TIM2->CCER1 |= TIM2_CCER1_CC2P;
01237   }
01238   else
01239   {
01240     TIM2->CCER1 &= (uint8_t)(~TIM2_CCER1_CC2P);
01241   }
01242
01243   /* Set the CCE Bit */
01244   TIM2->CCER1 |= TIM2_CCER1_CC2E;
01245 }
01246
01247 /**
01248   * @brief  Configure the TI3 as Input.
01249   * @param   TIM2_ICPolarity  The Input Polarity.
01250   * This parameter can be one of the following values:
01251   *                       - TIM2_ICPOLARITY_FALLING
01252   *                       - TIM2_ICPOLARITY_RISING
01253   * @param   TIM2_ICSelection specifies the input to be used.
01254   * This parameter can be one of the following values:
01255   *                       - TIM2_ICSELECTION_DIRECTTI: TIM2 Input 3 is selected to
01256   *                         be connected to IC3.
01257   * @param   TIM2_ICFilter Specifies the Input Capture Filter.
01258   * This parameter must be a value between 0x00 and 0x0F.
01259   * @retval None
01260   */
01261 static void TI3_Config(uint8_t TIM2_ICPolarity, uint8_t TIM2_ICSelection,
01262                        uint8_t TIM2_ICFilter)
01263 {
01264   /* Disable the Channel 3: Reset the CCE Bit */
01265   TIM2->CCER2 &=  (uint8_t)(~TIM2_CCER2_CC3E);
01266
01267   /* Select the Input and set the filter */
01268   TIM2->CCMR3 = (uint8_t)((uint8_t)(TIM2->CCMR3 & (uint8_t)(~( TIM2_CCMR_CCxS | TIM2_CCMR_ICxF)))
01269                           | (uint8_t)(( (TIM2_ICSelection)) | ((uint8_t)( TIM2_ICFilter << 4))));
01270
01271
01272   /* Select the Polarity */
01273   if (TIM2_ICPolarity != TIM2_ICPOLARITY_RISING)
01274   {
01275     TIM2->CCER2 |= TIM2_CCER2_CC3P;
01276   }
01277   else
01278   {
01279     TIM2->CCER2 &= (uint8_t)(~TIM2_CCER2_CC3P);
01280   }
01281   /* Set the CCE Bit */
01282   TIM2->CCER2 |= TIM2_CCER2_CC3E;
01283 }
01284
01285 /**
01286   * @}
01287   */
01288
01289   /**
01290   * @}
01291   */
01292
01293
01294 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_tim2.h Source File

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  • inc
stm8s_tim2.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_tim2.h
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all functions prototype and macros for the TIM2 peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Define to prevent recursive inclusion -------------------------------------*/
00029 #ifndef __STM8S_TIM2_H
00030 #define __STM8S_TIM2_H
00031
00032 /* Includes ------------------------------------------------------------------*/
00033 #include "stm8s.h"
00034
00035 /** @addtogroup STM8S_StdPeriph_Driver
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040
00041
00042 /** TIM2 Forced Action */
00043 typedef enum
00044 {
00045   TIM2_FORCEDACTION_ACTIVE           = ((uint8_t)0x50),
00046   TIM2_FORCEDACTION_INACTIVE         = ((uint8_t)0x40)
00047 }TIM2_ForcedAction_TypeDef;
00048
00049 #define IS_TIM2_FORCED_ACTION_OK(ACTION) (((ACTION) == TIM2_FORCEDACTION_ACTIVE) || \
00050     ((ACTION) == TIM2_FORCEDACTION_INACTIVE))
00051
00052 /** TIM2 Prescaler */
00053 typedef enum
00054 {
00055   TIM2_PRESCALER_1  = ((uint8_t)0x00),
00056   TIM2_PRESCALER_2    = ((uint8_t)0x01),
00057   TIM2_PRESCALER_4    = ((uint8_t)0x02),
00058   TIM2_PRESCALER_8     = ((uint8_t)0x03),
00059   TIM2_PRESCALER_16   = ((uint8_t)0x04),
00060   TIM2_PRESCALER_32     = ((uint8_t)0x05),
00061   TIM2_PRESCALER_64    = ((uint8_t)0x06),
00062   TIM2_PRESCALER_128   = ((uint8_t)0x07),
00063   TIM2_PRESCALER_256   = ((uint8_t)0x08),
00064   TIM2_PRESCALER_512   = ((uint8_t)0x09),
00065   TIM2_PRESCALER_1024  = ((uint8_t)0x0A),
00066   TIM2_PRESCALER_2048 = ((uint8_t)0x0B),
00067   TIM2_PRESCALER_4096   = ((uint8_t)0x0C),
00068   TIM2_PRESCALER_8192 = ((uint8_t)0x0D),
00069   TIM2_PRESCALER_16384 = ((uint8_t)0x0E),
00070   TIM2_PRESCALER_32768 = ((uint8_t)0x0F)
00071 }TIM2_Prescaler_TypeDef;
00072
00073 #define IS_TIM2_PRESCALER_OK(PRESCALER) (((PRESCALER) == TIM2_PRESCALER_1  ) || \
00074     ((PRESCALER) == TIM2_PRESCALER_2    ) || \
00075     ((PRESCALER) == TIM2_PRESCALER_4    ) || \
00076     ((PRESCALER) == TIM2_PRESCALER_8  ) || \
00077     ((PRESCALER) == TIM2_PRESCALER_16   ) || \
00078     ((PRESCALER) == TIM2_PRESCALER_32     ) || \
00079     ((PRESCALER) == TIM2_PRESCALER_64    ) || \
00080     ((PRESCALER) == TIM2_PRESCALER_128   ) || \
00081     ((PRESCALER) == TIM2_PRESCALER_256   ) || \
00082     ((PRESCALER) == TIM2_PRESCALER_512   ) || \
00083     ((PRESCALER) == TIM2_PRESCALER_1024  ) || \
00084     ((PRESCALER) == TIM2_PRESCALER_2048 ) || \
00085     ((PRESCALER) == TIM2_PRESCALER_4096 ) || \
00086     ((PRESCALER) == TIM2_PRESCALER_8192 ) || \
00087     ((PRESCALER) == TIM2_PRESCALER_16384 ) || \
00088     ((PRESCALER) == TIM2_PRESCALER_32768 ))
00089
00090 /** TIM2 Output Compare and PWM modes */
00091 typedef enum
00092 {
00093   TIM2_OCMODE_TIMING     = ((uint8_t)0x00),
00094   TIM2_OCMODE_ACTIVE     = ((uint8_t)0x10),
00095   TIM2_OCMODE_INACTIVE   = ((uint8_t)0x20),
00096   TIM2_OCMODE_TOGGLE     = ((uint8_t)0x30),
00097   TIM2_OCMODE_PWM1       = ((uint8_t)0x60),
00098   TIM2_OCMODE_PWM2       = ((uint8_t)0x70)
00099 }TIM2_OCMode_TypeDef;
00100
00101 #define IS_TIM2_OC_MODE_OK(MODE) (((MODE) ==  TIM2_OCMODE_TIMING) || \
00102                                   ((MODE) == TIM2_OCMODE_ACTIVE) || \
00103                                   ((MODE) == TIM2_OCMODE_INACTIVE) || \
00104                                   ((MODE) == TIM2_OCMODE_TOGGLE)|| \
00105                                   ((MODE) == TIM2_OCMODE_PWM1) || \
00106                                   ((MODE) == TIM2_OCMODE_PWM2))
00107
00108 #define IS_TIM2_OCM_OK(MODE)(((MODE) ==  TIM2_OCMODE_TIMING) || \
00109                              ((MODE) == TIM2_OCMODE_ACTIVE) || \
00110                              ((MODE) == TIM2_OCMODE_INACTIVE) || \
00111                              ((MODE) == TIM2_OCMODE_TOGGLE)|| \
00112                              ((MODE) == TIM2_OCMODE_PWM1) || \
00113                              ((MODE) == TIM2_OCMODE_PWM2) || \
00114                              ((MODE) == (uint8_t)TIM2_FORCEDACTION_ACTIVE) || \
00115                              ((MODE) == (uint8_t)TIM2_FORCEDACTION_INACTIVE))
00116
00117 /** TIM2 One Pulse Mode */
00118 typedef enum
00119 {
00120   TIM2_OPMODE_SINGLE                 = ((uint8_t)0x01),
00121   TIM2_OPMODE_REPETITIVE             = ((uint8_t)0x00)
00122 }TIM2_OPMode_TypeDef;
00123
00124 #define IS_TIM2_OPM_MODE_OK(MODE) (((MODE) == TIM2_OPMODE_SINGLE) || \
00125                                    ((MODE) == TIM2_OPMODE_REPETITIVE))
00126
00127 /** TIM2 Channel */
00128 typedef enum
00129 {
00130   TIM2_CHANNEL_1                     = ((uint8_t)0x00),
00131   TIM2_CHANNEL_2                     = ((uint8_t)0x01),
00132   TIM2_CHANNEL_3                     = ((uint8_t)0x02)
00133 }TIM2_Channel_TypeDef;
00134
00135 #define IS_TIM2_CHANNEL_OK(CHANNEL) (((CHANNEL) == TIM2_CHANNEL_1) || \
00136                                      ((CHANNEL) == TIM2_CHANNEL_2) || \
00137                                      ((CHANNEL) == TIM2_CHANNEL_3))
00138
00139 #define IS_TIM2_PWMI_CHANNEL_OK(CHANNEL) (((CHANNEL) == TIM2_CHANNEL_1) || \
00140     ((CHANNEL) == TIM2_CHANNEL_2))
00141
00142 /** TIM2 Output Compare Polarity */
00143 typedef enum
00144 {
00145   TIM2_OCPOLARITY_HIGH               = ((uint8_t)0x00),
00146   TIM2_OCPOLARITY_LOW                = ((uint8_t)0x22)
00147 }TIM2_OCPolarity_TypeDef;
00148
00149 #define IS_TIM2_OC_POLARITY_OK(POLARITY) (((POLARITY) == TIM2_OCPOLARITY_HIGH) || \
00150     ((POLARITY) == TIM2_OCPOLARITY_LOW))
00151
00152 /** TIM2 Output Compare states */
00153 typedef enum
00154 {
00155   TIM2_OUTPUTSTATE_DISABLE           = ((uint8_t)0x00),
00156   TIM2_OUTPUTSTATE_ENABLE            = ((uint8_t)0x11)
00157 }TIM2_OutputState_TypeDef;
00158
00159 #define IS_TIM2_OUTPUT_STATE_OK(STATE) (((STATE) == TIM2_OUTPUTSTATE_DISABLE) || \
00160                                         ((STATE) == TIM2_OUTPUTSTATE_ENABLE))
00161
00162 /** TIM2 Input Capture Polarity */
00163 typedef enum
00164 {
00165   TIM2_ICPOLARITY_RISING            = ((uint8_t)0x00),
00166   TIM2_ICPOLARITY_FALLING           = ((uint8_t)0x44)
00167 }TIM2_ICPolarity_TypeDef;
00168
00169 #define IS_TIM2_IC_POLARITY_OK(POLARITY) (((POLARITY) == TIM2_ICPOLARITY_RISING) || \
00170     ((POLARITY) == TIM2_ICPOLARITY_FALLING))
00171
00172 /** TIM2 Input Capture Selection */
00173 typedef enum
00174 {
00175   TIM2_ICSELECTION_DIRECTTI          = ((uint8_t)0x01),
00176   TIM2_ICSELECTION_INDIRECTTI        = ((uint8_t)0x02),
00177   TIM2_ICSELECTION_TRGI              = ((uint8_t)0x03)
00178 }TIM2_ICSelection_TypeDef;
00179
00180 #define IS_TIM2_IC_SELECTION_OK(SELECTION) (((SELECTION) == TIM2_ICSELECTION_DIRECTTI) || \
00181     ((SELECTION) == TIM2_ICSELECTION_INDIRECTTI) || \
00182     ((SELECTION) == TIM2_ICSELECTION_TRGI))
00183
00184 #define IS_TIM2_IC_SELECTION1_OK(SELECTION) (((SELECTION) == TIM2_ICSELECTION_DIRECTTI) || \
00185     ((SELECTION) == TIM2_ICSELECTION_TRGI))
00186
00187 /** TIM2 Input Capture Prescaler */
00188 typedef enum
00189 {
00190   TIM2_ICPSC_DIV1                    = ((uint8_t)0x00),
00191   TIM2_ICPSC_DIV2                    = ((uint8_t)0x04),
00192   TIM2_ICPSC_DIV4                    = ((uint8_t)0x08),
00193   TIM2_ICPSC_DIV8                    = ((uint8_t)0x0C)
00194 }TIM2_ICPSC_TypeDef;
00195
00196 #define IS_TIM2_IC_PRESCALER_OK(PRESCALER) (((PRESCALER) == TIM2_ICPSC_DIV1) || \
00197     ((PRESCALER) == TIM2_ICPSC_DIV2) || \
00198     ((PRESCALER) == TIM2_ICPSC_DIV4) || \
00199     ((PRESCALER) == TIM2_ICPSC_DIV8))
00200
00201 /** TIM2 Input Capture Filer Value */
00202 #define IS_TIM2_IC_FILTER_OK(ICFILTER) ((ICFILTER) <= 0x0F)
00203
00204 /** TIM2 interrupt sources */
00205 typedef enum
00206 {
00207   TIM2_IT_UPDATE                     = ((uint8_t)0x01),
00208   TIM2_IT_CC1                        = ((uint8_t)0x02),
00209   TIM2_IT_CC2                        = ((uint8_t)0x04),
00210   TIM2_IT_CC3                        = ((uint8_t)0x08)
00211 }TIM2_IT_TypeDef;
00212
00213 #define IS_TIM2_IT_OK(IT) (((IT) != 0x00) && ((IT) <= 0x0F))
00214
00215 #define IS_TIM2_GET_IT_OK(IT) (((IT) == TIM2_IT_UPDATE) || \
00216                                ((IT) == TIM2_IT_CC1) || \
00217                                ((IT) == TIM2_IT_CC2) || \
00218                                ((IT) == TIM2_IT_CC3))
00219
00220 /** TIM2 Prescaler Reload Mode */
00221 typedef enum
00222 {
00223   TIM2_PSCRELOADMODE_UPDATE          = ((uint8_t)0x00),
00224   TIM2_PSCRELOADMODE_IMMEDIATE       = ((uint8_t)0x01)
00225 }TIM2_PSCReloadMode_TypeDef;
00226
00227 #define IS_TIM2_PRESCALER_RELOAD_OK(RELOAD) (((RELOAD) == TIM2_PSCRELOADMODE_UPDATE) || \
00228     ((RELOAD) == TIM2_PSCRELOADMODE_IMMEDIATE))
00229
00230 /** TIM2 Event Source */
00231 typedef enum
00232 {
00233   TIM2_EVENTSOURCE_UPDATE            = ((uint8_t)0x01),
00234   TIM2_EVENTSOURCE_CC1               = ((uint8_t)0x02),
00235   TIM2_EVENTSOURCE_CC2               = ((uint8_t)0x04),
00236   TIM2_EVENTSOURCE_CC3               = ((uint8_t)0x08)
00237 }TIM2_EventSource_TypeDef;
00238
00239 #define IS_TIM2_EVENT_SOURCE_OK(SOURCE) (((SOURCE) != 0x00))
00240
00241 /** TIM2 Update Source */
00242 typedef enum
00243 {
00244   TIM2_UPDATESOURCE_GLOBAL           = ((uint8_t)0x00),
00245   TIM2_UPDATESOURCE_REGULAR          = ((uint8_t)0x01)
00246 }TIM2_UpdateSource_TypeDef;
00247
00248 #define IS_TIM2_UPDATE_SOURCE_OK(SOURCE) (((SOURCE) == TIM2_UPDATESOURCE_GLOBAL) || \
00249     ((SOURCE) == TIM2_UPDATESOURCE_REGULAR))
00250
00251 /** TIM2 Flags */
00252 typedef enum
00253 {
00254   TIM2_FLAG_UPDATE                   = ((uint16_t)0x0001),
00255   TIM2_FLAG_CC1                      = ((uint16_t)0x0002),
00256   TIM2_FLAG_CC2                      = ((uint16_t)0x0004),
00257   TIM2_FLAG_CC3                      = ((uint16_t)0x0008),
00258   TIM2_FLAG_CC1OF                    = ((uint16_t)0x0200),
00259   TIM2_FLAG_CC2OF                    = ((uint16_t)0x0400),
00260   TIM2_FLAG_CC3OF                    = ((uint16_t)0x0800)
00261 }TIM2_FLAG_TypeDef;
00262
00263 #define IS_TIM2_GET_FLAG_OK(FLAG) (((FLAG) == TIM2_FLAG_UPDATE) || \
00264                                    ((FLAG) == TIM2_FLAG_CC1) || \
00265                                    ((FLAG) == TIM2_FLAG_CC2) || \
00266                                    ((FLAG) == TIM2_FLAG_CC3) || \
00267                                    ((FLAG) == TIM2_FLAG_CC1OF) || \
00268                                    ((FLAG) == TIM2_FLAG_CC2OF) || \
00269                                    ((FLAG) == TIM2_FLAG_CC3OF))
00270
00271 #define IS_TIM2_CLEAR_FLAG_OK(FLAG) ((((uint16_t)(FLAG) & 0xF1F0) == 0x0000) && ((uint16_t)(FLAG) != 0x0000))
00272
00273 /**
00274   * @}
00275   */
00276
00277 /* Exported macro ------------------------------------------------------------*/
00278
00279 /* Exported functions --------------------------------------------------------*/
00280
00281 /** @addtogroup TIM2_Exported_Functions
00282   * @{
00283   */
00284
00285 void TIM2_DeInit(void);
00286 void TIM2_TimeBaseInit(TIM2_Prescaler_TypeDef TIM2_Prescaler, uint16_t TIM2_Period);
00287 void TIM2_OC1Init(TIM2_OCMode_TypeDef TIM2_OCMode, TIM2_OutputState_TypeDef TIM2_OutputState, uint16_t TIM2_Pulse, TIM2_OCPolarity_TypeDef TIM2_OCPolarity);
00288 void TIM2_OC2Init(TIM2_OCMode_TypeDef TIM2_OCMode, TIM2_OutputState_TypeDef TIM2_OutputState, uint16_t TIM2_Pulse, TIM2_OCPolarity_TypeDef TIM2_OCPolarity);
00289 void TIM2_OC3Init(TIM2_OCMode_TypeDef TIM2_OCMode, TIM2_OutputState_TypeDef TIM2_OutputState, uint16_t TIM2_Pulse, TIM2_OCPolarity_TypeDef TIM2_OCPolarity);
00290 void TIM2_ICInit(TIM2_Channel_TypeDef TIM2_Channel, TIM2_ICPolarity_TypeDef TIM2_ICPolarity, TIM2_ICSelection_TypeDef TIM2_ICSelection,  TIM2_ICPSC_TypeDef TIM2_ICPrescaler, uint8_t TIM2_ICFilter);
00291 void TIM2_PWMIConfig(TIM2_Channel_TypeDef TIM2_Channel, TIM2_ICPolarity_TypeDef TIM2_ICPolarity, TIM2_ICSelection_TypeDef TIM2_ICSelection,  TIM2_ICPSC_TypeDef TIM2_ICPrescaler, uint8_t TIM2_ICFilter);
00292 void TIM2_Cmd(FunctionalState NewState);
00293 void TIM2_ITConfig(TIM2_IT_TypeDef TIM2_IT, FunctionalState NewState);
00294 void TIM2_InternalClockConfig(void);
00295 void TIM2_UpdateDisableConfig(FunctionalState NewState);
00296 void TIM2_UpdateRequestConfig(TIM2_UpdateSource_TypeDef TIM2_UpdateSource);
00297 void TIM2_SelectOnePulseMode(TIM2_OPMode_TypeDef TIM2_OPMode);
00298 void TIM2_PrescalerConfig(TIM2_Prescaler_TypeDef Prescaler, TIM2_PSCReloadMode_TypeDef TIM2_PSCReloadMode);
00299 void TIM2_ForcedOC1Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction);
00300 void TIM2_ForcedOC2Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction);
00301 void TIM2_ForcedOC3Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction);
00302 void TIM2_ARRPreloadConfig(FunctionalState NewState);
00303 void TIM2_CCPreloadControl(FunctionalState NewState);
00304 void TIM2_OC1PreloadConfig(FunctionalState NewState);
00305 void TIM2_OC2PreloadConfig(FunctionalState NewState);
00306 void TIM2_OC3PreloadConfig(FunctionalState NewState);
00307 void TIM2_GenerateEvent(TIM2_EventSource_TypeDef TIM2_EventSource);
00308 void TIM2_OC1PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity);
00309 void TIM2_OC2PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity);
00310 void TIM2_OC3PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity);
00311 void TIM2_CCxCmd(TIM2_Channel_TypeDef TIM2_Channel, FunctionalState NewState);
00312 void TIM2_SelectOCxM(TIM2_Channel_TypeDef TIM2_Channel, TIM2_OCMode_TypeDef TIM2_OCMode);
00313 void TIM2_SetCounter(uint16_t Counter);
00314 void TIM2_SetAutoreload(uint16_t Autoreload);
00315 void TIM2_SetCompare1(uint16_t Compare1);
00316 void TIM2_SetCompare2(uint16_t Compare2);
00317 void TIM2_SetCompare3(uint16_t Compare3);
00318 void TIM2_SetIC1Prescaler(TIM2_ICPSC_TypeDef TIM2_IC1Prescaler);
00319 void TIM2_SetIC2Prescaler(TIM2_ICPSC_TypeDef TIM2_IC2Prescaler);
00320 void TIM2_SetIC3Prescaler(TIM2_ICPSC_TypeDef TIM2_IC3Prescaler);
00321 uint16_t TIM2_GetCapture1(void);
00322 uint16_t TIM2_GetCapture2(void);
00323 uint16_t TIM2_GetCapture3(void);
00324 uint16_t TIM2_GetCounter(void);
00325 TIM2_Prescaler_TypeDef TIM2_GetPrescaler(void);
00326 FlagStatus TIM2_GetFlagStatus(TIM2_FLAG_TypeDef TIM2_FLAG);
00327 void TIM2_ClearFlag(TIM2_FLAG_TypeDef TIM2_FLAG);
00328 ITStatus TIM2_GetITStatus(TIM2_IT_TypeDef TIM2_IT);
00329 void TIM2_ClearITPendingBit(TIM2_IT_TypeDef TIM2_IT);
00330
00331 /**
00332   * @}
00333   */
00334
00335 #endif /* __STM8S_TIM2_H */
00336
00337 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_tim3.c Source File

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  • STM8S_StdPeriph_Driver
  • src
stm8s_tim3.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_tim3.c
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all the functions for the TIM3 peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm8s_tim3.h"
00030
00031 /** @addtogroup STM8S_StdPeriph_Driver
00032   * @{
00033   */
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 /* Private macro -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038 /* Private function prototypes -----------------------------------------------*/
00039 static void TI1_Config(uint8_t TIM3_ICPolarity, uint8_t TIM3_ICSelection, uint8_t TIM3_ICFilter);
00040 static void TI2_Config(uint8_t TIM3_ICPolarity, uint8_t TIM3_ICSelection, uint8_t TIM3_ICFilter);
00041 /**
00042   * @addtogroup TIM3_Public_Functions
00043   * @{
00044   */
00045
00046 /**
00047   * @brief  Deinitializes the TIM3 peripheral registers to their default reset values.
00048   * @param  None
00049   * @retval None
00050   */
00051 void TIM3_DeInit(void)
00052 {
00053   TIM3->CR1 = (uint8_t)TIM3_CR1_RESET_VALUE;
00054   TIM3->IER = (uint8_t)TIM3_IER_RESET_VALUE;
00055   TIM3->SR2 = (uint8_t)TIM3_SR2_RESET_VALUE;
00056
00057   /* Disable channels */
00058   TIM3->CCER1 = (uint8_t)TIM3_CCER1_RESET_VALUE;
00059
00060   /* Then reset channel registers: it also works if lock level is equal to 2 or 3 */
00061   TIM3->CCER1 = (uint8_t)TIM3_CCER1_RESET_VALUE;
00062   TIM3->CCMR1 = (uint8_t)TIM3_CCMR1_RESET_VALUE;
00063   TIM3->CCMR2 = (uint8_t)TIM3_CCMR2_RESET_VALUE;
00064   TIM3->CNTRH = (uint8_t)TIM3_CNTRH_RESET_VALUE;
00065   TIM3->CNTRL = (uint8_t)TIM3_CNTRL_RESET_VALUE;
00066   TIM3->PSCR = (uint8_t)TIM3_PSCR_RESET_VALUE;
00067   TIM3->ARRH  = (uint8_t)TIM3_ARRH_RESET_VALUE;
00068   TIM3->ARRL  = (uint8_t)TIM3_ARRL_RESET_VALUE;
00069   TIM3->CCR1H = (uint8_t)TIM3_CCR1H_RESET_VALUE;
00070   TIM3->CCR1L = (uint8_t)TIM3_CCR1L_RESET_VALUE;
00071   TIM3->CCR2H = (uint8_t)TIM3_CCR2H_RESET_VALUE;
00072   TIM3->CCR2L = (uint8_t)TIM3_CCR2L_RESET_VALUE;
00073   TIM3->SR1 = (uint8_t)TIM3_SR1_RESET_VALUE;
00074 }
00075
00076 /**
00077   * @brief  Initializes the TIM3 Time Base Unit according to the specified parameters.
00078   * @param    TIM3_Prescaler specifies the Prescaler from TIM3_Prescaler_TypeDef.
00079   * @param    TIM3_Period specifies the Period value.
00080   * @retval None
00081   */
00082 void TIM3_TimeBaseInit( TIM3_Prescaler_TypeDef TIM3_Prescaler,
00083                         uint16_t TIM3_Period)
00084 {
00085   /* Set the Prescaler value */
00086   TIM3->PSCR = (uint8_t)(TIM3_Prescaler);
00087   /* Set the Autoreload value */
00088   TIM3->ARRH = (uint8_t)(TIM3_Period >> 8);
00089   TIM3->ARRL = (uint8_t)(TIM3_Period);
00090 }
00091
00092 /**
00093   * @brief  Initializes the TIM3 Channel1 according to the specified parameters.
00094   * @param   TIM3_OCMode specifies the Output Compare mode  from @ref TIM3_OCMode_TypeDef.
00095   * @param   TIM3_OutputState specifies the Output State  from @ref TIM3_OutputState_TypeDef.
00096   * @param   TIM3_Pulse specifies the Pulse width  value.
00097   * @param   TIM3_OCPolarity specifies the Output Compare Polarity  from @ref TIM3_OCPolarity_TypeDef.
00098   * @retval None
00099   */
00100 void TIM3_OC1Init(TIM3_OCMode_TypeDef TIM3_OCMode,
00101                   TIM3_OutputState_TypeDef TIM3_OutputState,
00102                   uint16_t TIM3_Pulse,
00103                   TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
00104 {
00105   /* Check the parameters */
00106   assert_param(IS_TIM3_OC_MODE_OK(TIM3_OCMode));
00107   assert_param(IS_TIM3_OUTPUT_STATE_OK(TIM3_OutputState));
00108   assert_param(IS_TIM3_OC_POLARITY_OK(TIM3_OCPolarity));
00109
00110   /* Disable the Channel 1: Reset the CCE Bit, Set the Output State , the Output Polarity */
00111   TIM3->CCER1 &= (uint8_t)(~( TIM3_CCER1_CC1E | TIM3_CCER1_CC1P));
00112   /* Set the Output State &  Set the Output Polarity  */
00113   TIM3->CCER1 |= (uint8_t)((uint8_t)(TIM3_OutputState  & TIM3_CCER1_CC1E   ) | (uint8_t)(TIM3_OCPolarity   & TIM3_CCER1_CC1P   ));
00114
00115   /* Reset the Output Compare Bits & Set the Output Compare Mode */
00116   TIM3->CCMR1 = (uint8_t)((uint8_t)(TIM3->CCMR1 & (uint8_t)(~TIM3_CCMR_OCM)) | (uint8_t)TIM3_OCMode);
00117
00118   /* Set the Pulse value */
00119   TIM3->CCR1H = (uint8_t)(TIM3_Pulse >> 8);
00120   TIM3->CCR1L = (uint8_t)(TIM3_Pulse);
00121 }
00122
00123 /**
00124   * @brief  Initializes the TIM3 Channel2 according to the specified parameters.
00125   * @param   TIM3_OCMode specifies the Output Compare mode  from @ref TIM3_OCMode_TypeDef.
00126   * @param   TIM3_OutputState specifies the Output State  from @ref TIM3_OutputState_TypeDef.
00127   * @param   TIM3_Pulse specifies the Pulse width  value.
00128   * @param   TIM3_OCPolarity specifies the Output Compare Polarity  from @ref TIM3_OCPolarity_TypeDef.
00129   * @retval None
00130   */
00131 void TIM3_OC2Init(TIM3_OCMode_TypeDef TIM3_OCMode,
00132                   TIM3_OutputState_TypeDef TIM3_OutputState,
00133                   uint16_t TIM3_Pulse,
00134                   TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
00135 {
00136   /* Check the parameters */
00137   assert_param(IS_TIM3_OC_MODE_OK(TIM3_OCMode));
00138   assert_param(IS_TIM3_OUTPUT_STATE_OK(TIM3_OutputState));
00139   assert_param(IS_TIM3_OC_POLARITY_OK(TIM3_OCPolarity));
00140
00141
00142   /* Disable the Channel 1: Reset the CCE Bit, Set the Output State, the Output Polarity */
00143   TIM3->CCER1 &= (uint8_t)(~( TIM3_CCER1_CC2E |  TIM3_CCER1_CC2P ));
00144   /* Set the Output State & Set the Output Polarity */
00145   TIM3->CCER1 |= (uint8_t)((uint8_t)(TIM3_OutputState  & TIM3_CCER1_CC2E   ) | (uint8_t)(TIM3_OCPolarity   & TIM3_CCER1_CC2P ));
00146
00147
00148   /* Reset the Output Compare Bits & Set the Output Compare Mode */
00149   TIM3->CCMR2 = (uint8_t)((uint8_t)(TIM3->CCMR2 & (uint8_t)(~TIM3_CCMR_OCM)) | (uint8_t)TIM3_OCMode);
00150
00151
00152   /* Set the Pulse value */
00153   TIM3->CCR2H = (uint8_t)(TIM3_Pulse >> 8);
00154   TIM3->CCR2L = (uint8_t)(TIM3_Pulse);
00155 }
00156
00157 /**
00158   * @brief  Initializes the TIM3 peripheral according to the specified parameters.
00159   * @param    TIM3_Channel specifies the Input Capture Channel from @ref TIM3_Channel_TypeDef.
00160   * @param   TIM3_ICPolarity specifies the Input Capture Polarity from @ref TIM3_ICPolarity_TypeDef.
00161   * @param   TIM3_ICSelection specifies the Input Capture Selection from @ref TIM3_ICSelection_TypeDef.
00162   * @param   TIM3_ICPrescaler specifies the Input Capture Prescaler from @ref TIM3_ICPSC_TypeDef.
00163   * @param   TIM3_ICFilter specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
00164   * @retval None
00165   */
00166 void TIM3_ICInit(TIM3_Channel_TypeDef TIM3_Channel,
00167                  TIM3_ICPolarity_TypeDef TIM3_ICPolarity,
00168                  TIM3_ICSelection_TypeDef TIM3_ICSelection,
00169                  TIM3_ICPSC_TypeDef TIM3_ICPrescaler,
00170                  uint8_t TIM3_ICFilter)
00171 {
00172   /* Check the parameters */
00173   assert_param(IS_TIM3_CHANNEL_OK(TIM3_Channel));
00174   assert_param(IS_TIM3_IC_POLARITY_OK(TIM3_ICPolarity));
00175   assert_param(IS_TIM3_IC_SELECTION_OK(TIM3_ICSelection));
00176   assert_param(IS_TIM3_IC_PRESCALER_OK(TIM3_ICPrescaler));
00177   assert_param(IS_TIM3_IC_FILTER_OK(TIM3_ICFilter));
00178
00179   if (TIM3_Channel != TIM3_CHANNEL_2)
00180   {
00181     /* TI1 Configuration */
00182     TI1_Config((uint8_t)TIM3_ICPolarity,
00183                (uint8_t)TIM3_ICSelection,
00184                (uint8_t)TIM3_ICFilter);
00185
00186     /* Set the Input Capture Prescaler value */
00187     TIM3_SetIC1Prescaler(TIM3_ICPrescaler);
00188   }
00189   else
00190   {
00191     /* TI2 Configuration */
00192     TI2_Config((uint8_t)TIM3_ICPolarity,
00193                (uint8_t)TIM3_ICSelection,
00194                (uint8_t)TIM3_ICFilter);
00195
00196     /* Set the Input Capture Prescaler value */
00197     TIM3_SetIC2Prescaler(TIM3_ICPrescaler);
00198   }
00199 }
00200
00201 /**
00202   * @brief  Configures the TIM3 peripheral in PWM Input Mode according to the specified parameters.
00203   * @param    TIM3_Channel specifies the Input Capture Channel from @ref TIM3_Channel_TypeDef.
00204   * @param   TIM3_ICPolarity specifies the Input Capture Polarity from @ref TIM3_ICPolarity_TypeDef.
00205   * @param   TIM3_ICSelection specifies the Input Capture Selection from @ref TIM3_ICSelection_TypeDef.
00206   * @param   TIM3_ICPrescaler specifies the Input Capture Prescaler from @ref TIM3_ICPSC_TypeDef.
00207   * @param   TIM3_ICFilter specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
00208   * @retval None
00209   */
00210 void TIM3_PWMIConfig(TIM3_Channel_TypeDef TIM3_Channel,
00211                      TIM3_ICPolarity_TypeDef TIM3_ICPolarity,
00212                      TIM3_ICSelection_TypeDef TIM3_ICSelection,
00213                      TIM3_ICPSC_TypeDef TIM3_ICPrescaler,
00214                      uint8_t TIM3_ICFilter)
00215 {
00216   uint8_t icpolarity = (uint8_t)TIM3_ICPOLARITY_RISING;
00217   uint8_t icselection = (uint8_t)TIM3_ICSELECTION_DIRECTTI;
00218
00219   /* Check the parameters */
00220   assert_param(IS_TIM3_PWMI_CHANNEL_OK(TIM3_Channel));
00221   assert_param(IS_TIM3_IC_POLARITY_OK(TIM3_ICPolarity));
00222   assert_param(IS_TIM3_IC_SELECTION_OK(TIM3_ICSelection));
00223   assert_param(IS_TIM3_IC_PRESCALER_OK(TIM3_ICPrescaler));
00224
00225   /* Select the Opposite Input Polarity */
00226   if (TIM3_ICPolarity != TIM3_ICPOLARITY_FALLING)
00227   {
00228     icpolarity = (uint8_t)TIM3_ICPOLARITY_FALLING;
00229   }
00230   else
00231   {
00232     icpolarity = (uint8_t)TIM3_ICPOLARITY_RISING;
00233   }
00234
00235   /* Select the Opposite Input */
00236   if (TIM3_ICSelection == TIM3_ICSELECTION_DIRECTTI)
00237   {
00238     icselection = (uint8_t)TIM3_ICSELECTION_INDIRECTTI;
00239   }
00240   else
00241   {
00242     icselection = (uint8_t)TIM3_ICSELECTION_DIRECTTI;
00243   }
00244
00245   if (TIM3_Channel != TIM3_CHANNEL_2)
00246   {
00247     /* TI1 Configuration */
00248     TI1_Config((uint8_t)TIM3_ICPolarity, (uint8_t)TIM3_ICSelection,
00249                (uint8_t)TIM3_ICFilter);
00250
00251     /* Set the Input Capture Prescaler value */
00252     TIM3_SetIC1Prescaler(TIM3_ICPrescaler);
00253
00254     /* TI2 Configuration */
00255     TI2_Config(icpolarity, icselection, TIM3_ICFilter);
00256
00257     /* Set the Input Capture Prescaler value */
00258     TIM3_SetIC2Prescaler(TIM3_ICPrescaler);
00259   }
00260   else
00261   {
00262     /* TI2 Configuration */
00263     TI2_Config((uint8_t)TIM3_ICPolarity, (uint8_t)TIM3_ICSelection,
00264                (uint8_t)TIM3_ICFilter);
00265
00266     /* Set the Input Capture Prescaler value */
00267     TIM3_SetIC2Prescaler(TIM3_ICPrescaler);
00268
00269     /* TI1 Configuration */
00270     TI1_Config(icpolarity, icselection, TIM3_ICFilter);
00271
00272     /* Set the Input Capture Prescaler value */
00273     TIM3_SetIC1Prescaler(TIM3_ICPrescaler);
00274   }
00275 }
00276
00277 /**
00278   * @brief  Enables or disables the TIM3 peripheral.
00279   * @param   NewState new state of the TIM3 peripheral. This parameter can
00280   * be ENABLE or DISABLE.
00281   * @retval None
00282   */
00283 void TIM3_Cmd(FunctionalState NewState)
00284 {
00285   /* Check the parameters */
00286   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00287
00288   /* set or Reset the CEN Bit */
00289   if (NewState != DISABLE)
00290   {
00291     TIM3->CR1 |= (uint8_t)TIM3_CR1_CEN;
00292   }
00293   else
00294   {
00295     TIM3->CR1 &= (uint8_t)(~TIM3_CR1_CEN);
00296   }
00297 }
00298
00299 /**
00300   * @brief  Enables or disables the specified TIM3 interrupts.
00301   * @param   NewState new state of the TIM3 peripheral.
00302   * This parameter can be: ENABLE or DISABLE.
00303   * @param   TIM3_IT specifies the TIM3 interrupts sources to be enabled or disabled.
00304   * This parameter can be any combination of the following values:
00305   *                       - TIM3_IT_UPDATE: TIM3 update Interrupt source
00306   *                       - TIM3_IT_CC1: TIM3 Capture Compare 1 Interrupt source
00307   *                       - TIM3_IT_CC2: TIM3 Capture Compare 2 Interrupt source
00308   *                       - TIM3_IT_CC3: TIM3 Capture Compare 3 Interrupt source
00309   * @param   NewState new state of the TIM3 peripheral.  * @retval None
00310   */
00311 void TIM3_ITConfig(TIM3_IT_TypeDef TIM3_IT, FunctionalState NewState)
00312 {
00313   /* Check the parameters */
00314   assert_param(IS_TIM3_IT_OK(TIM3_IT));
00315   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00316
00317   if (NewState != DISABLE)
00318   {
00319     /* Enable the Interrupt sources */
00320     TIM3->IER |= (uint8_t)TIM3_IT;
00321   }
00322   else
00323   {
00324     /* Disable the Interrupt sources */
00325     TIM3->IER &= (uint8_t)(~TIM3_IT);
00326   }
00327 }
00328
00329 /**
00330   * @brief  Enables or Disables the TIM3 Update event.
00331   * @param   NewState new state of the TIM3 peripheral Preload register. This parameter can
00332   * be ENABLE or DISABLE.
00333   * @retval None
00334   */
00335 void TIM3_UpdateDisableConfig(FunctionalState NewState)
00336 {
00337   /* Check the parameters */
00338   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00339
00340   /* Set or Reset the UDIS Bit */
00341   if (NewState != DISABLE)
00342   {
00343     TIM3->CR1 |= TIM3_CR1_UDIS;
00344   }
00345   else
00346   {
00347     TIM3->CR1 &= (uint8_t)(~TIM3_CR1_UDIS);
00348   }
00349 }
00350
00351 /**
00352   * @brief  Selects the TIM3 Update Request Interrupt source.
00353   * @param   TIM3_UpdateSource specifies the Update source.
00354   * This parameter can be one of the following values
00355   *                       - TIM3_UPDATESOURCE_REGULAR
00356   *                       - TIM3_UPDATESOURCE_GLOBAL
00357   * @retval None
00358   */
00359 void TIM3_UpdateRequestConfig(TIM3_UpdateSource_TypeDef TIM3_UpdateSource)
00360 {
00361   /* Check the parameters */
00362   assert_param(IS_TIM3_UPDATE_SOURCE_OK(TIM3_UpdateSource));
00363
00364   /* Set or Reset the URS Bit */
00365   if (TIM3_UpdateSource != TIM3_UPDATESOURCE_GLOBAL)
00366   {
00367     TIM3->CR1 |= TIM3_CR1_URS;
00368   }
00369   else
00370   {
00371     TIM3->CR1 &= (uint8_t)(~TIM3_CR1_URS);
00372   }
00373 }
00374
00375 /**
00376   * @brief  Selects the TIM3’s One Pulse Mode.
00377   * @param   TIM3_OPMode specifies the OPM Mode to be used.
00378   * This parameter can be one of the following values
00379   *                    - TIM3_OPMODE_SINGLE
00380   *                    - TIM3_OPMODE_REPETITIVE
00381   * @retval None
00382   */
00383 void TIM3_SelectOnePulseMode(TIM3_OPMode_TypeDef TIM3_OPMode)
00384 {
00385   /* Check the parameters */
00386   assert_param(IS_TIM3_OPM_MODE_OK(TIM3_OPMode));
00387
00388   /* Set or Reset the OPM Bit */
00389   if (TIM3_OPMode != TIM3_OPMODE_REPETITIVE)
00390   {
00391     TIM3->CR1 |= TIM3_CR1_OPM;
00392   }
00393   else
00394   {
00395     TIM3->CR1 &= (uint8_t)(~TIM3_CR1_OPM);
00396   }
00397 }
00398
00399 /**
00400   * @brief  Configures the TIM3 Prescaler.
00401   * @param   Prescaler specifies the Prescaler Register value
00402   * This parameter can be one of the following values
00403   *                       -  TIM3_PRESCALER_1
00404   *                       -  TIM3_PRESCALER_2
00405   *                       -  TIM3_PRESCALER_4
00406   *                       -  TIM3_PRESCALER_8
00407   *                       -  TIM3_PRESCALER_16
00408   *                       -  TIM3_PRESCALER_32
00409   *                       -  TIM3_PRESCALER_64
00410   *                       -  TIM3_PRESCALER_128
00411   *                       -  TIM3_PRESCALER_256
00412   *                       -  TIM3_PRESCALER_512
00413   *                       -  TIM3_PRESCALER_1024
00414   *                       -  TIM3_PRESCALER_2048
00415   *                       -  TIM3_PRESCALER_4096
00416   *                       -  TIM3_PRESCALER_8192
00417   *                       -  TIM3_PRESCALER_16384
00418   *                       -  TIM3_PRESCALER_32768
00419   * @param   TIM3_PSCReloadMode specifies the TIM3 Prescaler Reload mode.
00420   * This parameter can be one of the following values
00421   *                       - TIM3_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded
00422   *                         immediately.
00423   *                       - TIM3_PSCRELOADMODE_UPDATE: The Prescaler is loaded at
00424   *                         the update event.
00425   * @retval None
00426   */
00427 void TIM3_PrescalerConfig(TIM3_Prescaler_TypeDef Prescaler,
00428                           TIM3_PSCReloadMode_TypeDef TIM3_PSCReloadMode)
00429 {
00430   /* Check the parameters */
00431   assert_param(IS_TIM3_PRESCALER_RELOAD_OK(TIM3_PSCReloadMode));
00432   assert_param(IS_TIM3_PRESCALER_OK(Prescaler));
00433
00434   /* Set the Prescaler value */
00435   TIM3->PSCR = (uint8_t)Prescaler;
00436
00437   /* Set or reset the UG Bit */
00438   TIM3->EGR = (uint8_t)TIM3_PSCReloadMode;
00439 }
00440
00441 /**
00442   * @brief  Forces the TIM3 Channel1 output waveform to active or inactive level.
00443   * @param   TIM3_ForcedAction specifies the forced Action to be set to the output waveform.
00444   * This parameter can be one of the following values:
00445   *                       - TIM3_FORCEDACTION_ACTIVE: Force active level on OC1REF
00446   *                       - TIM3_FORCEDACTION_INACTIVE: Force inactive level on
00447   *                         OC1REF.
00448   * @retval None
00449   */
00450 void TIM3_ForcedOC1Config(TIM3_ForcedAction_TypeDef TIM3_ForcedAction)
00451 {
00452   /* Check the parameters */
00453   assert_param(IS_TIM3_FORCED_ACTION_OK(TIM3_ForcedAction));
00454
00455   /* Reset the OCM Bits & Configure the Forced output Mode */
00456   TIM3->CCMR1 =  (uint8_t)((uint8_t)(TIM3->CCMR1 & (uint8_t)(~TIM3_CCMR_OCM))  | (uint8_t)TIM3_ForcedAction);
00457 }
00458
00459 /**
00460   * @brief  Forces the TIM3 Channel2 output waveform to active or inactive level.
00461   * @param   TIM3_ForcedAction specifies the forced Action to be set to the output waveform.
00462   * This parameter can be one of the following values:
00463   *                       - TIM3_FORCEDACTION_ACTIVE: Force active level on OC2REF
00464   *                       - TIM3_FORCEDACTION_INACTIVE: Force inactive level on
00465   *                         OC2REF.
00466   * @retval None
00467   */
00468 void TIM3_ForcedOC2Config(TIM3_ForcedAction_TypeDef TIM3_ForcedAction)
00469 {
00470   /* Check the parameters */
00471   assert_param(IS_TIM3_FORCED_ACTION_OK(TIM3_ForcedAction));
00472
00473   /* Reset the OCM Bits & Configure the Forced output Mode */
00474   TIM3->CCMR2 =  (uint8_t)((uint8_t)(TIM3->CCMR2 & (uint8_t)(~TIM3_CCMR_OCM)) | (uint8_t)TIM3_ForcedAction);
00475 }
00476
00477 /**
00478   * @brief  Enables or disables TIM3 peripheral Preload register on ARR.
00479   * @param   NewState new state of the TIM3 peripheral Preload register.
00480   * This parameter can be ENABLE or DISABLE.
00481   * @retval None
00482   */
00483 void TIM3_ARRPreloadConfig(FunctionalState NewState)
00484 {
00485   /* Check the parameters */
00486   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00487
00488   /* Set or Reset the ARPE Bit */
00489   if (NewState != DISABLE)
00490   {
00491     TIM3->CR1 |= TIM3_CR1_ARPE;
00492   }
00493   else
00494   {
00495     TIM3->CR1 &= (uint8_t)(~TIM3_CR1_ARPE);
00496   }
00497 }
00498
00499 /**
00500   * @brief  Enables or disables the TIM3 peripheral Preload Register on CCR1.
00501   * @param   NewState new state of the Capture Compare Preload register.
00502   * This parameter can be ENABLE or DISABLE.
00503   * @retval None
00504   */
00505 void TIM3_OC1PreloadConfig(FunctionalState NewState)
00506 {
00507   /* Check the parameters */
00508   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00509
00510   /* Set or Reset the OC1PE Bit */
00511   if (NewState != DISABLE)
00512   {
00513     TIM3->CCMR1 |= TIM3_CCMR_OCxPE;
00514   }
00515   else
00516   {
00517     TIM3->CCMR1 &= (uint8_t)(~TIM3_CCMR_OCxPE);
00518   }
00519 }
00520
00521 /**
00522   * @brief  Enables or disables the TIM3 peripheral Preload Register on CCR2.
00523   * @param   NewState new state of the Capture Compare Preload register.
00524   * This parameter can be ENABLE or DISABLE.
00525   * @retval None
00526   */
00527 void TIM3_OC2PreloadConfig(FunctionalState NewState)
00528 {
00529   /* Check the parameters */
00530   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00531
00532   /* Set or Reset the OC2PE Bit */
00533   if (NewState != DISABLE)
00534   {
00535     TIM3->CCMR2 |= TIM3_CCMR_OCxPE;
00536   }
00537   else
00538   {
00539     TIM3->CCMR2 &= (uint8_t)(~TIM3_CCMR_OCxPE);
00540   }
00541 }
00542
00543 /**
00544   * @brief  Configures the TIM3 event to be generated by software.
00545   * @param   TIM3_EventSource specifies the event source.
00546   * This parameter can be one of the following values:
00547   *                       - TIM3_EVENTSOURCE_UPDATE: TIM3 update Event source
00548   *                       - TIM3_EVENTSOURCE_CC1: TIM3 Capture Compare 1 Event source
00549   *                       - TIM3_EVENTSOURCE_CC2: TIM3 Capture Compare 2 Event source
00550   * @retval None
00551   */
00552 void TIM3_GenerateEvent(TIM3_EventSource_TypeDef TIM3_EventSource)
00553 {
00554   /* Check the parameters */
00555   assert_param(IS_TIM3_EVENT_SOURCE_OK(TIM3_EventSource));
00556
00557   /* Set the event sources */
00558   TIM3->EGR = (uint8_t)TIM3_EventSource;
00559 }
00560
00561 /**
00562   * @brief  Configures the TIM3 Channel 1 polarity.
00563   * @param   TIM3_OCPolarity specifies the OC1 Polarity.
00564   * This parameter can be one of the following values:
00565   *                       - TIM3_OCPOLARITY_LOW: Output Compare active low
00566   *                       - TIM3_OCPOLARITY_HIGH: Output Compare active high
00567   * @retval None
00568   */
00569 void TIM3_OC1PolarityConfig(TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
00570 {
00571   /* Check the parameters */
00572   assert_param(IS_TIM3_OC_POLARITY_OK(TIM3_OCPolarity));
00573
00574   /* Set or Reset the CC1P Bit */
00575   if (TIM3_OCPolarity != TIM3_OCPOLARITY_HIGH)
00576   {
00577     TIM3->CCER1 |= TIM3_CCER1_CC1P;
00578   }
00579   else
00580   {
00581     TIM3->CCER1 &= (uint8_t)(~TIM3_CCER1_CC1P);
00582   }
00583 }
00584
00585 /**
00586   * @brief  Configures the TIM3 Channel 2 polarity.
00587   * @param   TIM3_OCPolarity specifies the OC2 Polarity.
00588   * This parameter can be one of the following values:
00589   *                       - TIM3_OCPOLARITY_LOW: Output Compare active low
00590   *                       - TIM3_OCPOLARITY_HIGH: Output Compare active high
00591   * @retval None
00592   */
00593 void TIM3_OC2PolarityConfig(TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
00594 {
00595   /* Check the parameters */
00596   assert_param(IS_TIM3_OC_POLARITY_OK(TIM3_OCPolarity));
00597
00598   /* Set or Reset the CC2P Bit */
00599   if (TIM3_OCPolarity != TIM3_OCPOLARITY_HIGH)
00600   {
00601     TIM3->CCER1 |= TIM3_CCER1_CC2P;
00602   }
00603   else
00604   {
00605     TIM3->CCER1 &= (uint8_t)(~TIM3_CCER1_CC2P);
00606   }
00607 }
00608
00609 /**
00610   * @brief  Enables or disables the TIM3 Capture Compare Channel x.
00611   * @param   TIM3_Channel specifies the TIM3 Channel.
00612   * This parameter can be one of the following values:
00613   *                       - TIM3_CHANNEL_1: TIM3 Channel1
00614   *                       - TIM3_CHANNEL_2: TIM3 Channel2
00615   * @param   NewState specifies the TIM3 Channel CCxE bit new state.
00616   * This parameter can be: ENABLE or DISABLE.
00617   * @retval None
00618   */
00619 void TIM3_CCxCmd(TIM3_Channel_TypeDef TIM3_Channel, FunctionalState NewState)
00620 {
00621   /* Check the parameters */
00622   assert_param(IS_TIM3_CHANNEL_OK(TIM3_Channel));
00623   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00624
00625   if (TIM3_Channel == TIM3_CHANNEL_1)
00626   {
00627     /* Set or Reset the CC1E Bit */
00628     if (NewState != DISABLE)
00629     {
00630       TIM3->CCER1 |= TIM3_CCER1_CC1E;
00631     }
00632     else
00633     {
00634       TIM3->CCER1 &= (uint8_t)(~TIM3_CCER1_CC1E);
00635     }
00636
00637   }
00638   else
00639   {
00640     /* Set or Reset the CC2E Bit */
00641     if (NewState != DISABLE)
00642     {
00643       TIM3->CCER1 |= TIM3_CCER1_CC2E;
00644     }
00645     else
00646     {
00647       TIM3->CCER1 &= (uint8_t)(~TIM3_CCER1_CC2E);
00648     }
00649   }
00650 }
00651
00652 /**
00653   * @brief  Selects the TIM3 Output Compare Mode. This function disables the
00654   * selected channel before changing the Output Compare Mode. User has to
00655   * enable this channel using TIM3_CCxCmd and TIM3_CCxNCmd functions.
00656   * @param   TIM3_Channel specifies the TIM3 Channel.
00657   * This parameter can be one of the following values:
00658   *                       - TIM3_CHANNEL_1: TIM3 Channel1
00659   *                       - TIM3_CHANNEL_2: TIM3 Channel2
00660   * @param   TIM3_OCMode specifies the TIM3 Output Compare Mode.
00661   * This parameter can be one of the following values:
00662   *                       - TIM3_OCMODE_TIMING
00663   *                       - TIM3_OCMODE_ACTIVE
00664   *                       - TIM3_OCMODE_TOGGLE
00665   *                       - TIM3_OCMODE_PWM1
00666   *                       - TIM3_OCMODE_PWM2
00667   *                       - TIM3_FORCEDACTION_ACTIVE
00668   *                       - TIM3_FORCEDACTION_INACTIVE
00669   * @retval None
00670   */
00671 void TIM3_SelectOCxM(TIM3_Channel_TypeDef TIM3_Channel, TIM3_OCMode_TypeDef TIM3_OCMode)
00672 {
00673   /* Check the parameters */
00674   assert_param(IS_TIM3_CHANNEL_OK(TIM3_Channel));
00675   assert_param(IS_TIM3_OCM_OK(TIM3_OCMode));
00676
00677   if (TIM3_Channel == TIM3_CHANNEL_1)
00678   {
00679     /* Disable the Channel 1: Reset the CCE Bit */
00680     TIM3->CCER1 &= (uint8_t)(~TIM3_CCER1_CC1E);
00681
00682     /* Reset the Output Compare Bits & Set the Output Compare Mode */
00683     TIM3->CCMR1 = (uint8_t)((uint8_t)(TIM3->CCMR1 & (uint8_t)(~TIM3_CCMR_OCM)) | (uint8_t)TIM3_OCMode);
00684   }
00685   else
00686   {
00687     /* Disable the Channel 2: Reset the CCE Bit */
00688     TIM3->CCER1 &= (uint8_t)(~TIM3_CCER1_CC2E);
00689
00690     /* Reset the Output Compare Bits & Set the Output Compare Mode */
00691     TIM3->CCMR2 = (uint8_t)((uint8_t)(TIM3->CCMR2 & (uint8_t)(~TIM3_CCMR_OCM)) | (uint8_t)TIM3_OCMode);
00692   }
00693 }
00694
00695 /**
00696   * @brief  Sets the TIM3 Counter Register value.
00697   * @param   Counter specifies the Counter register new value.
00698   * This parameter is between 0x0000 and 0xFFFF.
00699   * @retval None
00700   */
00701 void TIM3_SetCounter(uint16_t Counter)
00702 {
00703   /* Set the Counter Register value */
00704   TIM3->CNTRH = (uint8_t)(Counter >> 8);
00705   TIM3->CNTRL = (uint8_t)(Counter);
00706 }
00707
00708 /**
00709   * @brief  Sets the TIM3 Autoreload Register value.
00710   * @param   Autoreload specifies the Autoreload register new value.
00711   * This parameter is between 0x0000 and 0xFFFF.
00712   * @retval None
00713   */
00714 void TIM3_SetAutoreload(uint16_t Autoreload)
00715 {
00716   /* Set the Autoreload Register value */
00717   TIM3->ARRH = (uint8_t)(Autoreload >> 8);
00718   TIM3->ARRL = (uint8_t)(Autoreload);
00719 }
00720
00721 /**
00722   * @brief  Sets the TIM3 Capture Compare1 Register value.
00723   * @param   Compare1 specifies the Capture Compare1 register new value.
00724   * This parameter is between 0x0000 and 0xFFFF.
00725   * @retval None
00726   */
00727 void TIM3_SetCompare1(uint16_t Compare1)
00728 {
00729   /* Set the Capture Compare1 Register value */
00730   TIM3->CCR1H = (uint8_t)(Compare1 >> 8);
00731   TIM3->CCR1L = (uint8_t)(Compare1);
00732 }
00733
00734 /**
00735   * @brief  Sets the TIM3 Capture Compare2 Register value.
00736   * @param   Compare2 specifies the Capture Compare2 register new value.
00737   * This parameter is between 0x0000 and 0xFFFF.
00738   * @retval None
00739   */
00740 void TIM3_SetCompare2(uint16_t Compare2)
00741 {
00742   /* Set the Capture Compare2 Register value */
00743   TIM3->CCR2H = (uint8_t)(Compare2 >> 8);
00744   TIM3->CCR2L = (uint8_t)(Compare2);
00745 }
00746
00747 /**
00748   * @brief  Sets the TIM3 Input Capture 1 prescaler.
00749   * @param   TIM3_IC1Prescaler specifies the Input Capture prescaler new value
00750   * This parameter can be one of the following values:
00751   *                       - TIM3_ICPSC_DIV1: no prescaler
00752   *                       - TIM3_ICPSC_DIV2: capture is done once every 2 events
00753   *                       - TIM3_ICPSC_DIV4: capture is done once every 4 events
00754   *                       - TIM3_ICPSC_DIV8: capture is done once every 8 events
00755   * @retval None
00756   */
00757 void TIM3_SetIC1Prescaler(TIM3_ICPSC_TypeDef TIM3_IC1Prescaler)
00758 {
00759   /* Check the parameters */
00760   assert_param(IS_TIM3_IC_PRESCALER_OK(TIM3_IC1Prescaler));
00761
00762   /* Reset the IC1PSC Bits & Set the IC1PSC value */
00763   TIM3->CCMR1 = (uint8_t)((uint8_t)(TIM3->CCMR1 & (uint8_t)(~TIM3_CCMR_ICxPSC)) | (uint8_t)TIM3_IC1Prescaler);
00764 }
00765
00766 /**
00767   * @brief  Sets the TIM3 Input Capture 2 prescaler.
00768   * @param   TIM3_IC2Prescaler specifies the Input Capture prescaler new value
00769   * This parameter can be one of the following values:
00770   *                       - TIM3_ICPSC_DIV1: no prescaler
00771   *                       - TIM3_ICPSC_DIV2: capture is done once every 2 events
00772   *                       - TIM3_ICPSC_DIV4: capture is done once every 4 events
00773   *                       - TIM3_ICPSC_DIV8: capture is done once every 8 events
00774   * @retval None
00775   */
00776 void TIM3_SetIC2Prescaler(TIM3_ICPSC_TypeDef TIM3_IC2Prescaler)
00777 {
00778   /* Check the parameters */
00779   assert_param(IS_TIM3_IC_PRESCALER_OK(TIM3_IC2Prescaler));
00780
00781   /* Reset the IC1PSC Bits & Set the IC1PSC value */
00782   TIM3->CCMR2 = (uint8_t)((uint8_t)(TIM3->CCMR2 & (uint8_t)(~TIM3_CCMR_ICxPSC)) | (uint8_t)TIM3_IC2Prescaler);
00783 }
00784
00785 /**
00786   * @brief  Gets the TIM3 Input Capture 1 value.
00787   * @param  None
00788   * @retval Capture Compare 1 Register value.
00789   */
00790 uint16_t TIM3_GetCapture1(void)
00791 {
00792   /* Get the Capture 1 Register value */
00793   uint16_t tmpccr1 = 0;
00794   uint8_t tmpccr1l=0, tmpccr1h=0;
00795
00796   tmpccr1h = TIM3->CCR1H;
00797   tmpccr1l = TIM3->CCR1L;
00798
00799   tmpccr1 = (uint16_t)(tmpccr1l);
00800   tmpccr1 |= (uint16_t)((uint16_t)tmpccr1h << 8);
00801   /* Get the Capture 1 Register value */
00802   return (uint16_t)tmpccr1;
00803 }
00804
00805 /**
00806   * @brief  Gets the TIM3 Input Capture 2 value.
00807   * @param  None
00808   * @retval Capture Compare 2 Register value.
00809   */
00810 uint16_t TIM3_GetCapture2(void)
00811 {
00812   /* Get the Capture 2 Register value */
00813   uint16_t tmpccr2 = 0;
00814   uint8_t tmpccr2l=0, tmpccr2h=0;
00815
00816   tmpccr2h = TIM3->CCR2H;
00817   tmpccr2l = TIM3->CCR2L;
00818
00819   tmpccr2 = (uint16_t)(tmpccr2l);
00820   tmpccr2 |= (uint16_t)((uint16_t)tmpccr2h << 8);
00821   /* Get the Capture 2 Register value */
00822   return (uint16_t)tmpccr2;
00823 }
00824
00825 /**
00826   * @brief  Gets the TIM3 Counter value.
00827   * @param  None
00828   * @retval Counter Register value.
00829   */
00830 uint16_t TIM3_GetCounter(void)
00831 {
00832   uint16_t tmpcntr = 0;
00833
00834   tmpcntr = ((uint16_t)TIM3->CNTRH << 8);
00835   /* Get the Counter Register value */
00836   return (uint16_t)( tmpcntr| (uint16_t)(TIM3->CNTRL));
00837 }
00838
00839 /**
00840   * @brief  Gets the TIM3 Prescaler value.
00841   * @param  None
00842   * @retval Prescaler Register configuration value @ref TIM3_Prescaler_TypeDef.
00843   */
00844 TIM3_Prescaler_TypeDef TIM3_GetPrescaler(void)
00845 {
00846   /* Get the Prescaler Register value */
00847   return (TIM3_Prescaler_TypeDef)(TIM3->PSCR);
00848 }
00849
00850 /**
00851   * @brief  Checks whether the specified TIM3 flag is set or not.
00852   * @param   TIM3_FLAG specifies the flag to check.
00853   * This parameter can be one of the following values:
00854   *                       - TIM3_FLAG_UPDATE: TIM3 update Flag
00855   *                       - TIM3_FLAG_CC1: TIM3 Capture Compare 1 Flag
00856   *                       - TIM3_FLAG_CC2: TIM3 Capture Compare 2 Flag
00857   *                       - TIM3_FLAG_CC1OF: TIM3 Capture Compare 1 over capture Flag
00858   *                       - TIM3_FLAG_CC2OF: TIM3 Capture Compare 2 over capture Flag
00859   * @retval FlagStatus The new state of TIM3_FLAG (SET or RESET).
00860   */
00861 FlagStatus TIM3_GetFlagStatus(TIM3_FLAG_TypeDef TIM3_FLAG)
00862 {
00863   FlagStatus bitstatus = RESET;
00864   uint8_t tim3_flag_l = 0, tim3_flag_h = 0;
00865
00866   /* Check the parameters */
00867   assert_param(IS_TIM3_GET_FLAG_OK(TIM3_FLAG));
00868
00869   tim3_flag_l = (uint8_t)(TIM3->SR1 & (uint8_t)TIM3_FLAG);
00870   tim3_flag_h = (uint8_t)((uint16_t)TIM3_FLAG >> 8);
00871
00872   if (((tim3_flag_l) | (uint8_t)(TIM3->SR2 & tim3_flag_h)) != (uint8_t)RESET )
00873   {
00874     bitstatus = SET;
00875   }
00876   else
00877   {
00878     bitstatus = RESET;
00879   }
00880   return (FlagStatus)bitstatus;
00881 }
00882
00883 /**
00884   * @brief  Clears the TIM3’s pending flags.
00885   * @param   TIM3_FLAG specifies the flag to clear.
00886   * This parameter can be one of the following values:
00887   *                       - TIM3_FLAG_UPDATE: TIM3 update Flag
00888   *                       - TIM3_FLAG_CC1: TIM3 Capture Compare 1 Flag
00889   *                       - TIM3_FLAG_CC2: TIM3 Capture Compare 2 Flag
00890   *                       - TIM3_FLAG_CC1OF: TIM3 Capture Compare 1 over capture Flag
00891   *                       - TIM3_FLAG_CC2OF: TIM3 Capture Compare 2 over capture Flag
00892   * @retval None.
00893   */
00894 void TIM3_ClearFlag(TIM3_FLAG_TypeDef TIM3_FLAG)
00895 {
00896   /* Check the parameters */
00897   assert_param(IS_TIM3_CLEAR_FLAG_OK(TIM3_FLAG));
00898
00899   /* Clear the flags (rc_w0) clear this bit by writing 0. Writing ‘1’ has no effect*/
00900   TIM3->SR1 = (uint8_t)(~((uint8_t)(TIM3_FLAG)));
00901   TIM3->SR2 = (uint8_t)(~((uint8_t)((uint16_t)TIM3_FLAG >> 8)));
00902 }
00903
00904 /**
00905   * @brief  Checks whether the TIM3 interrupt has occurred or not.
00906   * @param   TIM3_IT specifies the TIM3 interrupt source to check.
00907   * This parameter can be one of the following values:
00908   *                       - TIM3_IT_UPDATE: TIM3 update Interrupt source
00909   *                       - TIM3_IT_CC1: TIM3 Capture Compare 1 Interrupt source
00910   *                       - TIM3_IT_CC2: TIM3 Capture Compare 2 Interrupt source
00911   * @retval ITStatus The new state of the TIM3_IT(SET or RESET).
00912   */
00913 ITStatus TIM3_GetITStatus(TIM3_IT_TypeDef TIM3_IT)
00914 {
00915   ITStatus bitstatus = RESET;
00916   uint8_t TIM3_itStatus = 0, TIM3_itEnable = 0;
00917
00918   /* Check the parameters */
00919   assert_param(IS_TIM3_GET_IT_OK(TIM3_IT));
00920
00921   TIM3_itStatus = (uint8_t)(TIM3->SR1 & TIM3_IT);
00922
00923   TIM3_itEnable = (uint8_t)(TIM3->IER & TIM3_IT);
00924
00925   if ((TIM3_itStatus != (uint8_t)RESET ) && (TIM3_itEnable != (uint8_t)RESET ))
00926   {
00927     bitstatus = SET;
00928   }
00929   else
00930   {
00931     bitstatus = RESET;
00932   }
00933   return (ITStatus)(bitstatus);
00934 }
00935
00936 /**
00937   * @brief  Clears the TIM3's interrupt pending bits.
00938   * @param   TIM3_IT specifies the pending bit to clear.
00939   * This parameter can be one of the following values:
00940   *                       - TIM3_IT_UPDATE: TIM3 update Interrupt source
00941   *                       - TIM3_IT_CC1: TIM3 Capture Compare 1 Interrupt source
00942   *                       - TIM3_IT_CC2: TIM3 Capture Compare 2 Interrupt source
00943   * @retval None.
00944   */
00945 void TIM3_ClearITPendingBit(TIM3_IT_TypeDef TIM3_IT)
00946 {
00947   /* Check the parameters */
00948   assert_param(IS_TIM3_IT_OK(TIM3_IT));
00949
00950   /* Clear the IT pending Bit */
00951   TIM3->SR1 = (uint8_t)(~TIM3_IT);
00952 }
00953
00954 /**
00955   * @brief  Configure the TI1 as Input.
00956   * @param   TIM3_ICPolarity  The Input Polarity.
00957   * This parameter can be one of the following values:
00958   *                       - TIM3_ICPOLARITY_FALLING
00959   *                       - TIM3_ICPOLARITY_RISING
00960   * @param   TIM3_ICSelection specifies the input to be used.
00961   * This parameter can be one of the following values:
00962   *                       - TIM3_ICSELECTION_DIRECTTI: TIM3 Input 1 is selected to
00963   *                         be connected to IC1.
00964   *                       - TIM3_ICSELECTION_INDIRECTTI: TIM3 Input 1 is selected to
00965   *                         be connected to IC2.
00966   * @param   TIM3_ICFilter Specifies the Input Capture Filter.
00967   * This parameter must be a value between 0x00 and 0x0F.
00968   * @retval None
00969   */
00970 static void TI1_Config(uint8_t TIM3_ICPolarity,
00971                        uint8_t TIM3_ICSelection,
00972                        uint8_t TIM3_ICFilter)
00973 {
00974   /* Disable the Channel 1: Reset the CCE Bit */
00975   TIM3->CCER1 &= (uint8_t)(~TIM3_CCER1_CC1E);
00976
00977   /* Select the Input and set the filter */
00978   TIM3->CCMR1 = (uint8_t)((uint8_t)(TIM3->CCMR1 & (uint8_t)(~( TIM3_CCMR_CCxS | TIM3_CCMR_ICxF))) | (uint8_t)(( (TIM3_ICSelection)) | ((uint8_t)( TIM3_ICFilter << 4))));
00979
00980   /* Select the Polarity */
00981   if (TIM3_ICPolarity != TIM3_ICPOLARITY_RISING)
00982   {
00983     TIM3->CCER1 |= TIM3_CCER1_CC1P;
00984   }
00985   else
00986   {
00987     TIM3->CCER1 &= (uint8_t)(~TIM3_CCER1_CC1P);
00988   }
00989   /* Set the CCE Bit */
00990   TIM3->CCER1 |= TIM3_CCER1_CC1E;
00991 }
00992
00993 /**
00994   * @brief  Configure the TI2 as Input.
00995   * @param   TIM3_ICPolarity  The Input Polarity.
00996   * This parameter can be one of the following values:
00997   *                       - TIM3_ICPOLARITY_FALLING
00998   *                       - TIM3_ICPOLARITY_RISING
00999   * @param   TIM3_ICSelection specifies the input to be used.
01000   * This parameter can be one of the following values:
01001   *                       - TIM3_ICSELECTION_DIRECTTI: TIM3 Input 2 is selected to
01002   *                         be connected to IC2.
01003   *                       - TIM3_ICSELECTION_INDIRECTTI: TIM3 Input 2 is selected to
01004   *                         be connected to IC1.
01005   * @param   TIM3_ICFilter Specifies the Input Capture Filter.
01006   * This parameter must be a value between 0x00 and 0x0F.
01007   * @retval None
01008   */
01009 static void TI2_Config(uint8_t TIM3_ICPolarity,
01010                        uint8_t TIM3_ICSelection,
01011                        uint8_t TIM3_ICFilter)
01012 {
01013   /* Disable the Channel 2: Reset the CCE Bit */
01014   TIM3->CCER1 &=  (uint8_t)(~TIM3_CCER1_CC2E);
01015
01016   /* Select the Input and set the filter */
01017   TIM3->CCMR2 = (uint8_t)((uint8_t)(TIM3->CCMR2 & (uint8_t)(~( TIM3_CCMR_CCxS |
01018                                                               TIM3_CCMR_ICxF    ))) | (uint8_t)(( (TIM3_ICSelection)) |
01019                                                                                                 ((uint8_t)( TIM3_ICFilter << 4))));
01020
01021   /* Select the Polarity */
01022   if (TIM3_ICPolarity != TIM3_ICPOLARITY_RISING)
01023   {
01024     TIM3->CCER1 |= TIM3_CCER1_CC2P;
01025   }
01026   else
01027   {
01028     TIM3->CCER1 &= (uint8_t)(~TIM3_CCER1_CC2P);
01029   }
01030
01031   /* Set the CCE Bit */
01032   TIM3->CCER1 |= TIM3_CCER1_CC2E;
01033 }
01034
01035 /**
01036   * @}
01037   */
01038
01039   /**
01040   * @}
01041   */
01042
01043
01044 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_tim3.h Source File

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stm8s_tim3.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_tim3.h
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief  This file contains all functions prototype and macros for the TIM3 peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Define to prevent recursive inclusion -------------------------------------*/
00029 #ifndef __STM8S_TIM3_H
00030 #define __STM8S_TIM3_H
00031
00032 /* Includes ------------------------------------------------------------------*/
00033 #include "stm8s.h"
00034
00035 /** @addtogroup STM8S_StdPeriph_Driver
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040
00041 /** @addtogroup TIM3_Exported_Types
00042   * @{
00043   */
00044
00045 /** TIM3 Forced Action */
00046 typedef enum
00047 {
00048   TIM3_FORCEDACTION_ACTIVE           = ((uint8_t)0x50),
00049   TIM3_FORCEDACTION_INACTIVE         = ((uint8_t)0x40)
00050 } TIM3_ForcedAction_TypeDef;
00051
00052 #define IS_TIM3_FORCED_ACTION_OK(ACTION) (((ACTION) == TIM3_FORCEDACTION_ACTIVE) || \
00053     ((ACTION) == TIM3_FORCEDACTION_INACTIVE))
00054
00055 /** TIM3 Prescaler */
00056 typedef enum
00057 {
00058   TIM3_PRESCALER_1  = ((uint8_t)0x00),
00059   TIM3_PRESCALER_2    = ((uint8_t)0x01),
00060   TIM3_PRESCALER_4    = ((uint8_t)0x02),
00061   TIM3_PRESCALER_8     = ((uint8_t)0x03),
00062   TIM3_PRESCALER_16   = ((uint8_t)0x04),
00063   TIM3_PRESCALER_32     = ((uint8_t)0x05),
00064   TIM3_PRESCALER_64    = ((uint8_t)0x06),
00065   TIM3_PRESCALER_128   = ((uint8_t)0x07),
00066   TIM3_PRESCALER_256   = ((uint8_t)0x08),
00067   TIM3_PRESCALER_512   = ((uint8_t)0x09),
00068   TIM3_PRESCALER_1024  = ((uint8_t)0x0A),
00069   TIM3_PRESCALER_2048 = ((uint8_t)0x0B),
00070   TIM3_PRESCALER_4096   = ((uint8_t)0x0C),
00071   TIM3_PRESCALER_8192 = ((uint8_t)0x0D),
00072   TIM3_PRESCALER_16384 = ((uint8_t)0x0E),
00073   TIM3_PRESCALER_32768 = ((uint8_t)0x0F)
00074 } TIM3_Prescaler_TypeDef;
00075
00076 #define IS_TIM3_PRESCALER_OK(PRESCALER) (((PRESCALER) == TIM3_PRESCALER_1  ) || \
00077     ((PRESCALER) == TIM3_PRESCALER_2    ) || \
00078     ((PRESCALER) == TIM3_PRESCALER_4    ) || \
00079     ((PRESCALER) == TIM3_PRESCALER_8  ) || \
00080     ((PRESCALER) == TIM3_PRESCALER_16   ) || \
00081     ((PRESCALER) == TIM3_PRESCALER_32     ) || \
00082     ((PRESCALER) == TIM3_PRESCALER_64    ) || \
00083     ((PRESCALER) == TIM3_PRESCALER_128   ) || \
00084     ((PRESCALER) == TIM3_PRESCALER_256   ) || \
00085     ((PRESCALER) == TIM3_PRESCALER_512   ) || \
00086     ((PRESCALER) == TIM3_PRESCALER_1024  ) || \
00087     ((PRESCALER) == TIM3_PRESCALER_2048 ) || \
00088     ((PRESCALER) == TIM3_PRESCALER_4096 ) || \
00089     ((PRESCALER) == TIM3_PRESCALER_8192 ) || \
00090     ((PRESCALER) == TIM3_PRESCALER_16384 ) || \
00091     ((PRESCALER) == TIM3_PRESCALER_32768 ))
00092
00093 /** TIM3 Output Compare and PWM modes */
00094 typedef enum
00095 {
00096   TIM3_OCMODE_TIMING     = ((uint8_t)0x00),
00097   TIM3_OCMODE_ACTIVE     = ((uint8_t)0x10),
00098   TIM3_OCMODE_INACTIVE   = ((uint8_t)0x20),
00099   TIM3_OCMODE_TOGGLE     = ((uint8_t)0x30),
00100   TIM3_OCMODE_PWM1       = ((uint8_t)0x60),
00101   TIM3_OCMODE_PWM2       = ((uint8_t)0x70)
00102 } TIM3_OCMode_TypeDef;
00103
00104 #define IS_TIM3_OC_MODE_OK(MODE) (((MODE) ==  TIM3_OCMODE_TIMING) || \
00105                                   ((MODE) == TIM3_OCMODE_ACTIVE) || \
00106                                   ((MODE) == TIM3_OCMODE_INACTIVE) || \
00107                                   ((MODE) == TIM3_OCMODE_TOGGLE)|| \
00108                                   ((MODE) == TIM3_OCMODE_PWM1) || \
00109                                   ((MODE) == TIM3_OCMODE_PWM2))
00110
00111 #define IS_TIM3_OCM_OK(MODE)(((MODE) ==  TIM3_OCMODE_TIMING) || \
00112                              ((MODE) == TIM3_OCMODE_ACTIVE) || \
00113                              ((MODE) == TIM3_OCMODE_INACTIVE) || \
00114                              ((MODE) == TIM3_OCMODE_TOGGLE)|| \
00115                              ((MODE) == TIM3_OCMODE_PWM1) || \
00116                              ((MODE) == TIM3_OCMODE_PWM2) || \
00117                              ((MODE) == (uint8_t)TIM3_FORCEDACTION_ACTIVE) || \
00118                              ((MODE) == (uint8_t)TIM3_FORCEDACTION_INACTIVE))
00119
00120 /** TIM3 One Pulse Mode */
00121 typedef enum
00122 {
00123   TIM3_OPMODE_SINGLE                 = ((uint8_t)0x01),
00124   TIM3_OPMODE_REPETITIVE             = ((uint8_t)0x00)
00125 } TIM3_OPMode_TypeDef;
00126
00127 #define IS_TIM3_OPM_MODE_OK(MODE) (((MODE) == TIM3_OPMODE_SINGLE) || \
00128                                    ((MODE) == TIM3_OPMODE_REPETITIVE))
00129
00130 /** TIM3 Channel */
00131
00132 typedef enum
00133 {
00134   TIM3_CHANNEL_1                     = ((uint8_t)0x00),
00135   TIM3_CHANNEL_2                     = ((uint8_t)0x01)
00136 } TIM3_Channel_TypeDef;
00137
00138 #define IS_TIM3_CHANNEL_OK(CHANNEL) (((CHANNEL) == TIM3_CHANNEL_1) || \
00139                                      ((CHANNEL) == TIM3_CHANNEL_2))
00140
00141 #define IS_TIM3_PWMI_CHANNEL_OK(CHANNEL) (((CHANNEL) == TIM3_CHANNEL_1) || \
00142     ((CHANNEL) == TIM3_CHANNEL_2))
00143
00144 /** TIM3 Output Compare Polarity */
00145 typedef enum
00146 {
00147   TIM3_OCPOLARITY_HIGH               = ((uint8_t)0x00),
00148   TIM3_OCPOLARITY_LOW                = ((uint8_t)0x22)
00149 } TIM3_OCPolarity_TypeDef;
00150
00151 #define IS_TIM3_OC_POLARITY_OK(POLARITY) (((POLARITY) == TIM3_OCPOLARITY_HIGH) || \
00152     ((POLARITY) == TIM3_OCPOLARITY_LOW))
00153
00154 /** TIM3 Output Compare states */
00155 typedef enum
00156 {
00157   TIM3_OUTPUTSTATE_DISABLE           = ((uint8_t)0x00),
00158   TIM3_OUTPUTSTATE_ENABLE            = ((uint8_t)0x11)
00159 } TIM3_OutputState_TypeDef;
00160
00161 #define IS_TIM3_OUTPUT_STATE_OK(STATE) (((STATE) == TIM3_OUTPUTSTATE_DISABLE) || \
00162                                         ((STATE) == TIM3_OUTPUTSTATE_ENABLE))
00163
00164 /** TIM3 Input Capture Polarity */
00165 typedef enum
00166 {
00167   TIM3_ICPOLARITY_RISING            = ((uint8_t)0x00),
00168   TIM3_ICPOLARITY_FALLING           = ((uint8_t)0x44)
00169 } TIM3_ICPolarity_TypeDef;
00170
00171 #define IS_TIM3_IC_POLARITY_OK(POLARITY) (((POLARITY) == TIM3_ICPOLARITY_RISING) || \
00172     ((POLARITY) == TIM3_ICPOLARITY_FALLING))
00173
00174 /** TIM3 Input Capture Selection */
00175 typedef enum
00176 {
00177   TIM3_ICSELECTION_DIRECTTI          = ((uint8_t)0x01),
00178   TIM3_ICSELECTION_INDIRECTTI        = ((uint8_t)0x02),
00179   TIM3_ICSELECTION_TRGI              = ((uint8_t)0x03)
00180 } TIM3_ICSelection_TypeDef;
00181
00182 #define IS_TIM3_IC_SELECTION_OK(SELECTION) (((SELECTION) == TIM3_ICSELECTION_DIRECTTI) || \
00183     ((SELECTION) == TIM3_ICSELECTION_INDIRECTTI) || \
00184     ((SELECTION) == TIM3_ICSELECTION_TRGI))
00185
00186 /** TIM3 Input Capture Prescaler */
00187 typedef enum
00188 {
00189   TIM3_ICPSC_DIV1                    = ((uint8_t)0x00),
00190   TIM3_ICPSC_DIV2                    = ((uint8_t)0x04),
00191   TIM3_ICPSC_DIV4                    = ((uint8_t)0x08),
00192   TIM3_ICPSC_DIV8                    = ((uint8_t)0x0C)
00193 } TIM3_ICPSC_TypeDef;
00194
00195 #define IS_TIM3_IC_PRESCALER_OK(PRESCALER) (((PRESCALER) == TIM3_ICPSC_DIV1) || \
00196     ((PRESCALER) == TIM3_ICPSC_DIV2) || \
00197     ((PRESCALER) == TIM3_ICPSC_DIV4) || \
00198     ((PRESCALER) == TIM3_ICPSC_DIV8))
00199
00200 /** TIM3 Input Capture Filer Value */
00201 #define IS_TIM3_IC_FILTER_OK(ICFILTER) ((ICFILTER) <= 0x0F)
00202
00203 /** TIM3 interrupt sources */
00204 typedef enum
00205 {
00206   TIM3_IT_UPDATE                     = ((uint8_t)0x01),
00207   TIM3_IT_CC1                        = ((uint8_t)0x02),
00208   TIM3_IT_CC2                        = ((uint8_t)0x04)
00209 } TIM3_IT_TypeDef;
00210
00211 #define IS_TIM3_IT_OK(IT) (((IT) != 0x00) && ((IT) <= 0x07))
00212
00213 #define IS_TIM3_GET_IT_OK(IT) (((IT) == TIM3_IT_UPDATE) || \
00214                                ((IT) == TIM3_IT_CC1) || \
00215                                ((IT) == TIM3_IT_CC2))
00216
00217 /** TIM3 Prescaler Reload Mode */
00218 typedef enum
00219 {
00220   TIM3_PSCRELOADMODE_UPDATE          = ((uint8_t)0x00),
00221   TIM3_PSCRELOADMODE_IMMEDIATE       = ((uint8_t)0x01)
00222 } TIM3_PSCReloadMode_TypeDef;
00223
00224 #define IS_TIM3_PRESCALER_RELOAD_OK(RELOAD) (((RELOAD) == TIM3_PSCRELOADMODE_UPDATE) || \
00225     ((RELOAD) == TIM3_PSCRELOADMODE_IMMEDIATE))
00226
00227 /** TIM3 Event Source */
00228 typedef enum
00229 {
00230   TIM3_EVENTSOURCE_UPDATE            = ((uint8_t)0x01),
00231   TIM3_EVENTSOURCE_CC1               = ((uint8_t)0x02),
00232   TIM3_EVENTSOURCE_CC2               = ((uint8_t)0x04)
00233 } TIM3_EventSource_TypeDef;
00234
00235 #define IS_TIM3_EVENT_SOURCE_OK(SOURCE) (((SOURCE) != 0x00))
00236
00237 /** TIM3 Update Source */
00238 typedef enum
00239 {
00240   TIM3_UPDATESOURCE_GLOBAL           = ((uint8_t)0x00),
00241   TIM3_UPDATESOURCE_REGULAR          = ((uint8_t)0x01)
00242 } TIM3_UpdateSource_TypeDef;
00243
00244 #define IS_TIM3_UPDATE_SOURCE_OK(SOURCE) (((SOURCE) == TIM3_UPDATESOURCE_GLOBAL) || \
00245     ((SOURCE) == TIM3_UPDATESOURCE_REGULAR))
00246
00247 /** TIM3 Flags */
00248 typedef enum
00249 {
00250   TIM3_FLAG_UPDATE                   = ((uint16_t)0x0001),
00251   TIM3_FLAG_CC1                      = ((uint16_t)0x0002),
00252   TIM3_FLAG_CC2                      = ((uint16_t)0x0004),
00253   TIM3_FLAG_CC1OF                    = ((uint16_t)0x0200),
00254   TIM3_FLAG_CC2OF                    = ((uint16_t)0x0400)
00255 } TIM3_FLAG_TypeDef;
00256
00257 #define IS_TIM3_GET_FLAG_OK(FLAG) (((FLAG) == TIM3_FLAG_UPDATE) || \
00258                                    ((FLAG) == TIM3_FLAG_CC1) || \
00259                                    ((FLAG) == TIM3_FLAG_CC2) || \
00260                                    ((FLAG) == TIM3_FLAG_CC1OF) || \
00261                                    ((FLAG) == TIM3_FLAG_CC2OF) )
00262
00263 #define IS_TIM3_CLEAR_FLAG_OK(FLAG) ((((uint16_t)(FLAG) & 0xF9F8) == 0x0000) && ((uint16_t)(FLAG)!= 0x0000))
00264
00265 /**
00266   * @}
00267   */
00268
00269 /* Exported macro ------------------------------------------------------------*/
00270
00271 /* Exported functions --------------------------------------------------------*/
00272
00273 /** @addtogroup TIM3_Exported_Functions
00274   * @{
00275   */
00276
00277 void TIM3_DeInit(void);
00278 void TIM3_TimeBaseInit(TIM3_Prescaler_TypeDef TIM3_Prescaler, uint16_t TIM3_Period);
00279 void TIM3_OC1Init(TIM3_OCMode_TypeDef TIM3_OCMode, TIM3_OutputState_TypeDef TIM3_OutputState, uint16_t TIM3_Pulse, TIM3_OCPolarity_TypeDef TIM3_OCPolarity);
00280 void TIM3_OC2Init(TIM3_OCMode_TypeDef TIM3_OCMode, TIM3_OutputState_TypeDef TIM3_OutputState, uint16_t TIM3_Pulse, TIM3_OCPolarity_TypeDef TIM3_OCPolarity);
00281 void TIM3_ICInit(TIM3_Channel_TypeDef TIM3_Channel, TIM3_ICPolarity_TypeDef TIM3_ICPolarity, TIM3_ICSelection_TypeDef TIM3_ICSelection,  TIM3_ICPSC_TypeDef TIM3_ICPrescaler, uint8_t TIM3_ICFilter);
00282 void TIM3_PWMIConfig(TIM3_Channel_TypeDef TIM3_Channel, TIM3_ICPolarity_TypeDef TIM3_ICPolarity, TIM3_ICSelection_TypeDef TIM3_ICSelection,  TIM3_ICPSC_TypeDef TIM3_ICPrescaler, uint8_t TIM3_ICFilter);
00283 void TIM3_Cmd(FunctionalState NewState);
00284 void TIM3_ITConfig(TIM3_IT_TypeDef TIM3_IT, FunctionalState NewState);
00285 void TIM3_InternalClockConfig(void);
00286 void TIM3_UpdateDisableConfig(FunctionalState NewState);
00287 void TIM3_UpdateRequestConfig(TIM3_UpdateSource_TypeDef TIM3_UpdateSource);
00288 void TIM3_SelectOnePulseMode(TIM3_OPMode_TypeDef TIM3_OPMode);
00289 void TIM3_PrescalerConfig(TIM3_Prescaler_TypeDef Prescaler, TIM3_PSCReloadMode_TypeDef TIM3_PSCReloadMode);
00290 void TIM3_ForcedOC1Config(TIM3_ForcedAction_TypeDef TIM3_ForcedAction);
00291 void TIM3_ForcedOC2Config(TIM3_ForcedAction_TypeDef TIM3_ForcedAction);
00292 void TIM3_ARRPreloadConfig(FunctionalState NewState);
00293 void TIM3_CCPreloadControl(FunctionalState NewState);
00294 void TIM3_OC1PreloadConfig(FunctionalState NewState);
00295 void TIM3_OC2PreloadConfig(FunctionalState NewState);
00296 void TIM3_GenerateEvent(TIM3_EventSource_TypeDef TIM3_EventSource);
00297 void TIM3_OC1PolarityConfig(TIM3_OCPolarity_TypeDef TIM3_OCPolarity);
00298 void TIM3_OC2PolarityConfig(TIM3_OCPolarity_TypeDef TIM3_OCPolarity);
00299 void TIM3_CCxCmd(TIM3_Channel_TypeDef TIM3_Channel, FunctionalState NewState);
00300 void TIM3_SelectOCxM(TIM3_Channel_TypeDef TIM3_Channel, TIM3_OCMode_TypeDef TIM3_OCMode);
00301 void TIM3_SetCounter(uint16_t Counter);
00302 void TIM3_SetAutoreload(uint16_t Autoreload);
00303 void TIM3_SetCompare1(uint16_t Compare1);
00304 void TIM3_SetCompare2(uint16_t Compare2);
00305 void TIM3_SetIC1Prescaler(TIM3_ICPSC_TypeDef TIM3_IC1Prescaler);
00306 void TIM3_SetIC2Prescaler(TIM3_ICPSC_TypeDef TIM3_IC2Prescaler);
00307 uint16_t TIM3_GetCapture1(void);
00308 uint16_t TIM3_GetCapture2(void);
00309 uint16_t TIM3_GetCounter(void);
00310 TIM3_Prescaler_TypeDef TIM3_GetPrescaler(void);
00311 FlagStatus TIM3_GetFlagStatus(TIM3_FLAG_TypeDef TIM3_FLAG);
00312 void TIM3_ClearFlag(TIM3_FLAG_TypeDef TIM3_FLAG);
00313 ITStatus TIM3_GetITStatus(TIM3_IT_TypeDef TIM3_IT);
00314 void TIM3_ClearITPendingBit(TIM3_IT_TypeDef TIM3_IT);
00315
00316 /**
00317   * @}
00318   */
00319
00320 #endif /* __STM8S_TIM3_H */
00321
00322 /**
00323   * @}
00324   */
00325
00326
00327 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_tim4.c Source File

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stm8s_tim4.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_tim4.c
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all the functions for the TIM4 peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm8s_tim4.h"
00030
00031 /** @addtogroup STM8S_StdPeriph_Driver
00032   * @{
00033   */
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 /* Private macro -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038 /* Private function prototypes -----------------------------------------------*/
00039 /**
00040   * @addtogroup TIM4_Public_Functions
00041   * @{
00042   */
00043
00044 /**
00045   * @brief  Deinitializes the TIM4 peripheral registers to their default reset values.
00046   * @param  None
00047   * @retval None
00048   */
00049 void TIM4_DeInit(void)
00050 {
00051   TIM4->CR1 = TIM4_CR1_RESET_VALUE;
00052   TIM4->IER = TIM4_IER_RESET_VALUE;
00053   TIM4->CNTR = TIM4_CNTR_RESET_VALUE;
00054   TIM4->PSCR = TIM4_PSCR_RESET_VALUE;
00055   TIM4->ARR = TIM4_ARR_RESET_VALUE;
00056   TIM4->SR1 = TIM4_SR1_RESET_VALUE;
00057 }
00058
00059 /**
00060   * @brief  Initializes the TIM4 Time Base Unit according to the specified parameters.
00061   * @param    TIM4_Prescaler specifies the Prescaler from TIM4_Prescaler_TypeDef.
00062   * @param    TIM4_Period specifies the Period value.
00063   * @retval None
00064   */
00065 void TIM4_TimeBaseInit(TIM4_Prescaler_TypeDef TIM4_Prescaler, uint8_t TIM4_Period)
00066 {
00067   /* Check TIM4 prescaler value */
00068   assert_param(IS_TIM4_PRESCALER_OK(TIM4_Prescaler));
00069   /* Set the Prescaler value */
00070   TIM4->PSCR = (uint8_t)(TIM4_Prescaler);
00071   /* Set the Autoreload value */
00072   TIM4->ARR = (uint8_t)(TIM4_Period);
00073 }
00074
00075 /**
00076   * @brief  Enables or disables the TIM4 peripheral.
00077   * @param   NewState new state of the TIM4 peripheral. This parameter can
00078   * be ENABLE or DISABLE.
00079   * @retval None
00080   */
00081 void TIM4_Cmd(FunctionalState NewState)
00082 {
00083   /* Check the parameters */
00084   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00085
00086   /* set or Reset the CEN Bit */
00087   if (NewState != DISABLE)
00088   {
00089     TIM4->CR1 |= TIM4_CR1_CEN;
00090   }
00091   else
00092   {
00093     TIM4->CR1 &= (uint8_t)(~TIM4_CR1_CEN);
00094   }
00095 }
00096
00097 /**
00098   * @brief  Enables or disables the specified TIM4 interrupts.
00099   * @param   NewState new state of the TIM4 peripheral.
00100   * This parameter can be: ENABLE or DISABLE.
00101   * @param   TIM4_IT specifies the TIM4 interrupts sources to be enabled or disabled.
00102   * This parameter can be any combination of the following values:
00103   * - TIM4_IT_UPDATE: TIM4 update Interrupt source
00104   * @param   NewState new state of the TIM4 peripheral.
00105   * @retval None
00106   */
00107 void TIM4_ITConfig(TIM4_IT_TypeDef TIM4_IT, FunctionalState NewState)
00108 {
00109   /* Check the parameters */
00110   assert_param(IS_TIM4_IT_OK(TIM4_IT));
00111   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00112
00113   if (NewState != DISABLE)
00114   {
00115     /* Enable the Interrupt sources */
00116     TIM4->IER |= (uint8_t)TIM4_IT;
00117   }
00118   else
00119   {
00120     /* Disable the Interrupt sources */
00121     TIM4->IER &= (uint8_t)(~TIM4_IT);
00122   }
00123 }
00124
00125 /**
00126   * @brief  Enables or Disables the TIM4 Update event.
00127   * @param   NewState new state of the TIM4 peripheral Preload register. This parameter can
00128   * be ENABLE or DISABLE.
00129   * @retval None
00130   */
00131 void TIM4_UpdateDisableConfig(FunctionalState NewState)
00132 {
00133   /* Check the parameters */
00134   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00135
00136   /* Set or Reset the UDIS Bit */
00137   if (NewState != DISABLE)
00138   {
00139     TIM4->CR1 |= TIM4_CR1_UDIS;
00140   }
00141   else
00142   {
00143     TIM4->CR1 &= (uint8_t)(~TIM4_CR1_UDIS);
00144   }
00145 }
00146
00147 /**
00148   * @brief  Selects the TIM4 Update Request Interrupt source.
00149   * @param   TIM4_UpdateSource specifies the Update source.
00150   * This parameter can be one of the following values
00151   *                       - TIM4_UPDATESOURCE_REGULAR
00152   *                       - TIM4_UPDATESOURCE_GLOBAL
00153   * @retval None
00154   */
00155 void TIM4_UpdateRequestConfig(TIM4_UpdateSource_TypeDef TIM4_UpdateSource)
00156 {
00157   /* Check the parameters */
00158   assert_param(IS_TIM4_UPDATE_SOURCE_OK(TIM4_UpdateSource));
00159
00160   /* Set or Reset the URS Bit */
00161   if (TIM4_UpdateSource != TIM4_UPDATESOURCE_GLOBAL)
00162   {
00163     TIM4->CR1 |= TIM4_CR1_URS;
00164   }
00165   else
00166   {
00167     TIM4->CR1 &= (uint8_t)(~TIM4_CR1_URS);
00168   }
00169 }
00170
00171 /**
00172   * @brief  Selects the TIM4’s One Pulse Mode.
00173   * @param   TIM4_OPMode specifies the OPM Mode to be used.
00174   * This parameter can be one of the following values
00175   *                    - TIM4_OPMODE_SINGLE
00176   *                    - TIM4_OPMODE_REPETITIVE
00177   * @retval None
00178   */
00179 void TIM4_SelectOnePulseMode(TIM4_OPMode_TypeDef TIM4_OPMode)
00180 {
00181   /* Check the parameters */
00182   assert_param(IS_TIM4_OPM_MODE_OK(TIM4_OPMode));
00183
00184   /* Set or Reset the OPM Bit */
00185   if (TIM4_OPMode != TIM4_OPMODE_REPETITIVE)
00186   {
00187     TIM4->CR1 |= TIM4_CR1_OPM;
00188   }
00189   else
00190   {
00191     TIM4->CR1 &= (uint8_t)(~TIM4_CR1_OPM);
00192   }
00193 }
00194
00195 /**
00196   * @brief  Configures the TIM4 Prescaler.
00197   * @param   Prescaler specifies the Prescaler Register value
00198   * This parameter can be one of the following values
00199   *                       -  TIM4_PRESCALER_1
00200   *                       -  TIM4_PRESCALER_2
00201   *                       -  TIM4_PRESCALER_4
00202   *                       -  TIM4_PRESCALER_8
00203   *                       -  TIM4_PRESCALER_16
00204   *                       -  TIM4_PRESCALER_32
00205   *                       -  TIM4_PRESCALER_64
00206   *                       -  TIM4_PRESCALER_128
00207   * @param   TIM4_PSCReloadMode specifies the TIM4 Prescaler Reload mode.
00208   * This parameter can be one of the following values
00209   *                       - TIM4_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded
00210   *                         immediately.
00211   *                       - TIM4_PSCRELOADMODE_UPDATE: The Prescaler is loaded at
00212   *                         the update event.
00213   * @retval None
00214   */
00215 void TIM4_PrescalerConfig(TIM4_Prescaler_TypeDef Prescaler, TIM4_PSCReloadMode_TypeDef TIM4_PSCReloadMode)
00216 {
00217   /* Check the parameters */
00218   assert_param(IS_TIM4_PRESCALER_RELOAD_OK(TIM4_PSCReloadMode));
00219   assert_param(IS_TIM4_PRESCALER_OK(Prescaler));
00220
00221   /* Set the Prescaler value */
00222   TIM4->PSCR = (uint8_t)Prescaler;
00223
00224   /* Set or reset the UG Bit */
00225   TIM4->EGR = (uint8_t)TIM4_PSCReloadMode;
00226 }
00227
00228 /**
00229   * @brief  Enables or disables TIM4 peripheral Preload register on ARR.
00230   * @param   NewState new state of the TIM4 peripheral Preload register.
00231   * This parameter can be ENABLE or DISABLE.
00232   * @retval None
00233   */
00234 void TIM4_ARRPreloadConfig(FunctionalState NewState)
00235 {
00236   /* Check the parameters */
00237   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00238
00239   /* Set or Reset the ARPE Bit */
00240   if (NewState != DISABLE)
00241   {
00242     TIM4->CR1 |= TIM4_CR1_ARPE;
00243   }
00244   else
00245   {
00246     TIM4->CR1 &= (uint8_t)(~TIM4_CR1_ARPE);
00247   }
00248 }
00249
00250 /**
00251   * @brief  Configures the TIM4 event to be generated by software.
00252   * @param   TIM4_EventSource specifies the event source.
00253   * This parameter can be one of the following values:
00254   *                       - TIM4_EVENTSOURCE_UPDATE: TIM4 update Event source
00255   * @retval None
00256   */
00257 void TIM4_GenerateEvent(TIM4_EventSource_TypeDef TIM4_EventSource)
00258 {
00259   /* Check the parameters */
00260   assert_param(IS_TIM4_EVENT_SOURCE_OK(TIM4_EventSource));
00261
00262   /* Set the event sources */
00263   TIM4->EGR = (uint8_t)(TIM4_EventSource);
00264 }
00265
00266 /**
00267   * @brief  Sets the TIM4 Counter Register value.
00268   * @param   Counter specifies the Counter register new value.
00269   * This parameter is between 0x00 and 0xFF.
00270   * @retval None
00271   */
00272 void TIM4_SetCounter(uint8_t Counter)
00273 {
00274   /* Set the Counter Register value */
00275   TIM4->CNTR = (uint8_t)(Counter);
00276 }
00277
00278 /**
00279   * @brief  Sets the TIM4 Autoreload Register value.
00280   * @param   Autoreload specifies the Autoreload register new value.
00281   * This parameter is between 0x00 and 0xFF.
00282   * @retval None
00283   */
00284 void TIM4_SetAutoreload(uint8_t Autoreload)
00285 {
00286   /* Set the Autoreload Register value */
00287   TIM4->ARR = (uint8_t)(Autoreload);
00288 }
00289
00290 /**
00291   * @brief  Gets the TIM4 Counter value.
00292   * @param  None
00293   * @retval Counter Register value.
00294   */
00295 uint8_t TIM4_GetCounter(void)
00296 {
00297   /* Get the Counter Register value */
00298   return (uint8_t)(TIM4->CNTR);
00299 }
00300
00301 /**
00302   * @brief  Gets the TIM4 Prescaler value.
00303   * @param  None
00304   * @retval Prescaler Register configuration value.
00305   */
00306 TIM4_Prescaler_TypeDef TIM4_GetPrescaler(void)
00307 {
00308   /* Get the Prescaler Register value */
00309   return (TIM4_Prescaler_TypeDef)(TIM4->PSCR);
00310 }
00311
00312 /**
00313   * @brief  Checks whether the specified TIM4 flag is set or not.
00314   * @param   TIM4_FLAG specifies the flag to check.
00315   * This parameter can be one of the following values:
00316   *                       - TIM4_FLAG_UPDATE: TIM4 update Flag
00317   * @retval FlagStatus The new state of TIM4_FLAG (SET or RESET).
00318   */
00319 FlagStatus TIM4_GetFlagStatus(TIM4_FLAG_TypeDef TIM4_FLAG)
00320 {
00321   FlagStatus bitstatus = RESET;
00322
00323   /* Check the parameters */
00324   assert_param(IS_TIM4_GET_FLAG_OK(TIM4_FLAG));
00325
00326   if ((TIM4->SR1 & (uint8_t)TIM4_FLAG)  != 0)
00327   {
00328     bitstatus = SET;
00329   }
00330   else
00331   {
00332     bitstatus = RESET;
00333   }
00334   return ((FlagStatus)bitstatus);
00335 }
00336
00337 /**
00338   * @brief  Clears the TIM4’s pending flags.
00339   * @param   TIM4_FLAG specifies the flag to clear.
00340   * This parameter can be one of the following values:
00341   *                       - TIM4_FLAG_UPDATE: TIM4 update Flag
00342   * @retval None.
00343   */
00344 void TIM4_ClearFlag(TIM4_FLAG_TypeDef TIM4_FLAG)
00345 {
00346   /* Check the parameters */
00347   assert_param(IS_TIM4_GET_FLAG_OK(TIM4_FLAG));
00348
00349   /* Clear the flags (rc_w0) clear this bit by writing 0. Writing ‘1’ has no effect*/
00350   TIM4->SR1 = (uint8_t)(~TIM4_FLAG);
00351 }
00352
00353 /**
00354   * @brief  Checks whether the TIM4 interrupt has occurred or not.
00355   * @param  TIM4_IT specifies the TIM4 interrupt source to check.
00356   * This parameter can be one of the following values:
00357   *                       - TIM4_IT_UPDATE: TIM4 update Interrupt source
00358   * @retval ITStatus The new state of the TIM4_IT (SET or RESET).
00359   */
00360 ITStatus TIM4_GetITStatus(TIM4_IT_TypeDef TIM4_IT)
00361 {
00362   ITStatus bitstatus = RESET;
00363
00364   uint8_t itstatus = 0x0, itenable = 0x0;
00365
00366   /* Check the parameters */
00367   assert_param(IS_TIM4_IT_OK(TIM4_IT));
00368
00369   itstatus = (uint8_t)(TIM4->SR1 & (uint8_t)TIM4_IT);
00370
00371   itenable = (uint8_t)(TIM4->IER & (uint8_t)TIM4_IT);
00372
00373   if ((itstatus != (uint8_t)RESET ) && (itenable != (uint8_t)RESET ))
00374   {
00375     bitstatus = (ITStatus)SET;
00376   }
00377   else
00378   {
00379     bitstatus = (ITStatus)RESET;
00380   }
00381   return ((ITStatus)bitstatus);
00382 }
00383
00384 /**
00385   * @brief Clears the TIM4's interrupt pending bits.
00386   * @param TIM4_IT specifies the pending bit to clear.
00387   * This parameter can be one of the following values:
00388   *                       - TIM4_IT_UPDATE: TIM4 update Interrupt source
00389   * @retval None.
00390   */
00391 void TIM4_ClearITPendingBit(TIM4_IT_TypeDef TIM4_IT)
00392 {
00393   /* Check the parameters */
00394   assert_param(IS_TIM4_IT_OK(TIM4_IT));
00395
00396   /* Clear the IT pending Bit */
00397   TIM4->SR1 = (uint8_t)(~TIM4_IT);
00398 }
00399
00400 /**
00401   * @}
00402   */
00403
00404   /**
00405   * @}
00406   */
00407
00408
00409 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_tim4.h Source File

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  • STM8S_StdPeriph_Driver
  • inc
stm8s_tim4.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_tim4.h
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all functions prototype and macros for the TIM4 peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Define to prevent recursive inclusion -------------------------------------*/
00029 #ifndef __STM8S_TIM4_H
00030 #define __STM8S_TIM4_H
00031
00032 /* Includes ------------------------------------------------------------------*/
00033 #include "stm8s.h"
00034
00035 /** @addtogroup STM8S_StdPeriph_Driver
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040
00041 /** @addtogroup TIM4_Exported_Types
00042   * @{
00043   */
00044
00045
00046
00047 /** TIM4 Prescaler */
00048 typedef enum
00049 {
00050   TIM4_PRESCALER_1  = ((uint8_t)0x00),
00051   TIM4_PRESCALER_2    = ((uint8_t)0x01),
00052   TIM4_PRESCALER_4    = ((uint8_t)0x02),
00053   TIM4_PRESCALER_8     = ((uint8_t)0x03),
00054   TIM4_PRESCALER_16   = ((uint8_t)0x04),
00055   TIM4_PRESCALER_32     = ((uint8_t)0x05),
00056   TIM4_PRESCALER_64    = ((uint8_t)0x06),
00057   TIM4_PRESCALER_128   = ((uint8_t)0x07)
00058 } TIM4_Prescaler_TypeDef;
00059
00060 #define IS_TIM4_PRESCALER_OK(PRESCALER) (((PRESCALER) == TIM4_PRESCALER_1  ) || \
00061     ((PRESCALER) == TIM4_PRESCALER_2    ) || \
00062     ((PRESCALER) == TIM4_PRESCALER_4    ) || \
00063     ((PRESCALER) == TIM4_PRESCALER_8  ) || \
00064     ((PRESCALER) == TIM4_PRESCALER_16   ) || \
00065     ((PRESCALER) == TIM4_PRESCALER_32     ) || \
00066     ((PRESCALER) == TIM4_PRESCALER_64    ) || \
00067     ((PRESCALER) == TIM4_PRESCALER_128   ) )
00068
00069 /** TIM4 One Pulse Mode */
00070 typedef enum
00071 {
00072   TIM4_OPMODE_SINGLE                 = ((uint8_t)0x01),
00073   TIM4_OPMODE_REPETITIVE             = ((uint8_t)0x00)
00074 } TIM4_OPMode_TypeDef;
00075
00076 #define IS_TIM4_OPM_MODE_OK(MODE) (((MODE) == TIM4_OPMODE_SINGLE) || \
00077                                    ((MODE) == TIM4_OPMODE_REPETITIVE))
00078
00079 /** TIM4 Prescaler Reload Mode */
00080 typedef enum
00081 {
00082   TIM4_PSCRELOADMODE_UPDATE          = ((uint8_t)0x00),
00083   TIM4_PSCRELOADMODE_IMMEDIATE       = ((uint8_t)0x01)
00084 } TIM4_PSCReloadMode_TypeDef;
00085
00086 #define IS_TIM4_PRESCALER_RELOAD_OK(RELOAD) (((RELOAD) == TIM4_PSCRELOADMODE_UPDATE) || \
00087     ((RELOAD) == TIM4_PSCRELOADMODE_IMMEDIATE))
00088
00089 /** TIM4 Update Source */
00090 typedef enum
00091 {
00092   TIM4_UPDATESOURCE_GLOBAL           = ((uint8_t)0x00),
00093   TIM4_UPDATESOURCE_REGULAR          = ((uint8_t)0x01)
00094 } TIM4_UpdateSource_TypeDef;
00095
00096 #define IS_TIM4_UPDATE_SOURCE_OK(SOURCE) (((SOURCE) == TIM4_UPDATESOURCE_GLOBAL) || \
00097     ((SOURCE) == TIM4_UPDATESOURCE_REGULAR))
00098
00099 /** TIM4 Event Source */
00100 typedef enum
00101 {
00102   TIM4_EVENTSOURCE_UPDATE            = ((uint8_t)0x01)
00103 }TIM4_EventSource_TypeDef;
00104
00105 #define IS_TIM4_EVENT_SOURCE_OK(SOURCE) (((SOURCE) == 0x01))
00106
00107 /** TIM4 Flags */
00108 typedef enum
00109 {
00110   TIM4_FLAG_UPDATE                   = ((uint8_t)0x01)
00111 }TIM4_FLAG_TypeDef;
00112
00113 #define IS_TIM4_GET_FLAG_OK(FLAG) ((FLAG) == TIM4_FLAG_UPDATE)
00114
00115
00116
00117 /** TIM4 interrupt sources */
00118 typedef enum
00119 {
00120   TIM4_IT_UPDATE                     = ((uint8_t)0x01)
00121 }TIM4_IT_TypeDef;
00122
00123 #define IS_TIM4_IT_OK(IT) ((IT) == TIM4_IT_UPDATE)
00124
00125
00126
00127 /**
00128   * @}
00129   */
00130
00131 /* Exported macro ------------------------------------------------------------*/
00132
00133 /* Exported functions --------------------------------------------------------*/
00134
00135 /** @addtogroup TIM4_Exported_Functions
00136   * @{
00137   */
00138 void TIM4_DeInit(void);
00139 void TIM4_TimeBaseInit(TIM4_Prescaler_TypeDef TIM4_Prescaler, uint8_t TIM4_Period);
00140 void TIM4_Cmd(FunctionalState NewState);
00141 void TIM4_ITConfig(TIM4_IT_TypeDef TIM4_IT, FunctionalState NewState);
00142 void TIM4_UpdateDisableConfig(FunctionalState NewState);
00143 void TIM4_UpdateRequestConfig(TIM4_UpdateSource_TypeDef TIM4_UpdateSource);
00144 void TIM4_SelectOnePulseMode(TIM4_OPMode_TypeDef TIM4_OPMode);
00145 void TIM4_PrescalerConfig(TIM4_Prescaler_TypeDef Prescaler, TIM4_PSCReloadMode_TypeDef TIM4_PSCReloadMode);
00146 void TIM4_ARRPreloadConfig(FunctionalState NewState);
00147 void TIM4_GenerateEvent(TIM4_EventSource_TypeDef TIM4_EventSource);
00148 void TIM4_SetCounter(uint8_t Counter);
00149 void TIM4_SetAutoreload(uint8_t Autoreload);
00150 uint8_t TIM4_GetCounter(void);
00151 TIM4_Prescaler_TypeDef TIM4_GetPrescaler(void);
00152 FlagStatus TIM4_GetFlagStatus(TIM4_FLAG_TypeDef TIM4_FLAG);
00153 void TIM4_ClearFlag(TIM4_FLAG_TypeDef TIM4_FLAG);
00154 ITStatus TIM4_GetITStatus(TIM4_IT_TypeDef TIM4_IT);
00155 void TIM4_ClearITPendingBit(TIM4_IT_TypeDef TIM4_IT);
00156
00157
00158 /**
00159   * @}
00160   */
00161
00162 #endif /* __STM8S_TIM4_H */
00163
00164 /**
00165   * @}
00166   */
00167
00168
00169 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_tim5.c Source File

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  • STM8S_StdPeriph_Driver
  • src
stm8s_tim5.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_tim5.c
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all the functions for the TIM5 peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm8s_tim5.h"
00030
00031 /** @addtogroup STM8S_StdPeriph_Driver
00032   * @{
00033   */
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 /* Private macro -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038 /* Private function prototypes -----------------------------------------------*/
00039 static void TI1_Config(uint8_t TIM5_ICPolarity, uint8_t TIM5_ICSelection, uint8_t TIM5_ICFilter);
00040 static void TI2_Config(uint8_t TIM5_ICPolarity, uint8_t TIM5_ICSelection, uint8_t TIM5_ICFilter);
00041 static void TI3_Config(uint8_t TIM5_ICPolarity, uint8_t TIM5_ICSelection, uint8_t TIM5_ICFilter);
00042 /**
00043   * @addtogroup TIM5_Public_Functions
00044   * @{
00045   */
00046
00047 /**
00048   * @brief  Deinitializes the TIM5 peripheral registers to their default reset values.
00049   * @param  None
00050   * @retval None
00051   */
00052 void TIM5_DeInit(void)
00053 {
00054   TIM5->CR1 = (uint8_t)TIM5_CR1_RESET_VALUE;
00055   TIM5->CR2 = TIM5_CR2_RESET_VALUE;
00056   TIM5->SMCR = TIM5_SMCR_RESET_VALUE;
00057   TIM5->IER = (uint8_t)TIM5_IER_RESET_VALUE;
00058   TIM5->SR2 = (uint8_t)TIM5_SR2_RESET_VALUE;
00059
00060   /* Disable channels */
00061   TIM5->CCER1 = (uint8_t)TIM5_CCER1_RESET_VALUE;
00062   TIM5->CCER2 = (uint8_t)TIM5_CCER2_RESET_VALUE;
00063
00064   /* Then reset channel registers: it also works if lock level is equal to 2 or 3 */
00065   TIM5->CCER1 = (uint8_t)TIM5_CCER1_RESET_VALUE;
00066   TIM5->CCER2 = (uint8_t)TIM5_CCER2_RESET_VALUE;
00067   TIM5->CCMR1 = (uint8_t)TIM5_CCMR1_RESET_VALUE;
00068   TIM5->CCMR2 = (uint8_t)TIM5_CCMR2_RESET_VALUE;
00069   TIM5->CCMR3 = (uint8_t)TIM5_CCMR3_RESET_VALUE;
00070   TIM5->CNTRH = (uint8_t)TIM5_CNTRH_RESET_VALUE;
00071   TIM5->CNTRL = (uint8_t)TIM5_CNTRL_RESET_VALUE;
00072   TIM5->PSCR    = (uint8_t)TIM5_PSCR_RESET_VALUE;
00073   TIM5->ARRH    = (uint8_t)TIM5_ARRH_RESET_VALUE;
00074   TIM5->ARRL    = (uint8_t)TIM5_ARRL_RESET_VALUE;
00075   TIM5->CCR1H = (uint8_t)TIM5_CCR1H_RESET_VALUE;
00076   TIM5->CCR1L = (uint8_t)TIM5_CCR1L_RESET_VALUE;
00077   TIM5->CCR2H = (uint8_t)TIM5_CCR2H_RESET_VALUE;
00078   TIM5->CCR2L = (uint8_t)TIM5_CCR2L_RESET_VALUE;
00079   TIM5->CCR3H = (uint8_t)TIM5_CCR3H_RESET_VALUE;
00080   TIM5->CCR3L = (uint8_t)TIM5_CCR3L_RESET_VALUE;
00081   TIM5->SR1 = (uint8_t)TIM5_SR1_RESET_VALUE;
00082 }
00083
00084 /**
00085   * @brief  Initializes the TIM5 Time Base Unit according to the specified parameters.
00086   * @param    TIM5_Prescaler specifies the Prescaler from TIM5_Prescaler_TypeDef.
00087   * @param    TIM5_Period specifies the Period value.
00088   * @retval None
00089   */
00090 void TIM5_TimeBaseInit( TIM5_Prescaler_TypeDef TIM5_Prescaler,
00091                         uint16_t TIM5_Period)
00092 {
00093   /* Set the Prescaler value */
00094   TIM5->PSCR = (uint8_t)(TIM5_Prescaler);
00095   /* Set the Autoreload value */
00096   TIM5->ARRH = (uint8_t)(TIM5_Period >> 8) ;
00097   TIM5->ARRL = (uint8_t)(TIM5_Period);
00098 }
00099
00100 /**
00101   * @brief  Initializes the TIM5 Channel1 according to the specified parameters.
00102   * @param   TIM5_OCMode specifies the Output Compare mode  from @ref TIM5_OCMode_TypeDef.
00103   * @param   TIM5_OutputState specifies the Output State  from @ref TIM5_OutputState_TypeDef.
00104   * @param   TIM5_Pulse specifies the Pulse width  value.
00105   * @param   TIM5_OCPolarity specifies the Output Compare Polarity  from @ref TIM5_OCPolarity_TypeDef.
00106   * @retval None
00107   */
00108 void TIM5_OC1Init(TIM5_OCMode_TypeDef TIM5_OCMode,
00109                   TIM5_OutputState_TypeDef TIM5_OutputState,
00110                   uint16_t TIM5_Pulse,
00111                   TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
00112 {
00113   /* Check the parameters */
00114   assert_param(IS_TIM5_OC_MODE_OK(TIM5_OCMode));
00115   assert_param(IS_TIM5_OUTPUT_STATE_OK(TIM5_OutputState));
00116   assert_param(IS_TIM5_OC_POLARITY_OK(TIM5_OCPolarity));
00117
00118   /* Disable the Channel 1: Reset the CCE Bit, Set the Output State , the Output Polarity */
00119   TIM5->CCER1 &= (uint8_t)(~( TIM5_CCER1_CC1E | TIM5_CCER1_CC1P));
00120   /* Set the Output State &  Set the Output Polarity  */
00121   TIM5->CCER1 |= (uint8_t)((uint8_t)(TIM5_OutputState & TIM5_CCER1_CC1E )|
00122                            (uint8_t)(TIM5_OCPolarity & TIM5_CCER1_CC1P));
00123
00124   /* Reset the Output Compare Bits  & Set the Output Compare Mode */
00125   TIM5->CCMR1 = (uint8_t)((uint8_t)(TIM5->CCMR1 & (uint8_t)(~TIM5_CCMR_OCM)) |
00126                           (uint8_t)TIM5_OCMode);
00127
00128   /* Set the Pulse value */
00129   TIM5->CCR1H = (uint8_t)(TIM5_Pulse >> 8);
00130   TIM5->CCR1L = (uint8_t)(TIM5_Pulse);
00131 }
00132
00133 /**
00134   * @brief  Initializes the TIM5 Channel2 according to the specified parameters.
00135   * @param   TIM5_OCMode specifies the Output Compare mode  from @ref TIM5_OCMode_TypeDef.
00136   * @param   TIM5_OutputState specifies the Output State  from @ref TIM5_OutputState_TypeDef.
00137   * @param   TIM5_Pulse specifies the Pulse width  value.
00138   * @param   TIM5_OCPolarity specifies the Output Compare Polarity  from @ref TIM5_OCPolarity_TypeDef.
00139   * @retval None
00140   */
00141 void TIM5_OC2Init(TIM5_OCMode_TypeDef TIM5_OCMode,
00142                   TIM5_OutputState_TypeDef TIM5_OutputState,
00143                   uint16_t TIM5_Pulse,
00144                   TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
00145 {
00146   /* Check the parameters */
00147   assert_param(IS_TIM5_OC_MODE_OK(TIM5_OCMode));
00148   assert_param(IS_TIM5_OUTPUT_STATE_OK(TIM5_OutputState));
00149   assert_param(IS_TIM5_OC_POLARITY_OK(TIM5_OCPolarity));
00150
00151   /* Disable the Channel 1: Reset the CCE Bit, Set the Output State , the Output Polarity */
00152   TIM5->CCER1 &= (uint8_t)(~( TIM5_CCER1_CC2E |  TIM5_CCER1_CC2P ));
00153   /* Set the Output State & Set the Output Polarity  */
00154   TIM5->CCER1 |= (uint8_t)((uint8_t)(TIM5_OutputState  & TIM5_CCER1_CC2E )| \
00155     (uint8_t)(TIM5_OCPolarity & TIM5_CCER1_CC2P));
00156
00157
00158   /* Reset the Output Compare Bits  & Set the Output Compare Mode */
00159   TIM5->CCMR2 = (uint8_t)((uint8_t)(TIM5->CCMR2 & (uint8_t)(~TIM5_CCMR_OCM)) |
00160                           (uint8_t)TIM5_OCMode);
00161
00162   /* Set the Pulse value */
00163   TIM5->CCR2H = (uint8_t)(TIM5_Pulse >> 8);
00164   TIM5->CCR2L = (uint8_t)(TIM5_Pulse);
00165 }
00166
00167 /**
00168   * @brief  Initializes the TIM5 Channel3 according to the specified parameters.
00169   * @param   TIM5_OCMode specifies the Output Compare mode from @ref TIM5_OCMode_TypeDef.
00170   * @param   TIM5_OutputState specifies the Output State from @ref TIM5_OutputState_TypeDef.
00171   * @param   TIM5_Pulse specifies the Pulse width value.
00172   * @param   TIM5_OCPolarity specifies the Output Compare Polarity  from @ref TIM5_OCPolarity_TypeDef.
00173   * @retval None
00174   */
00175 void TIM5_OC3Init(TIM5_OCMode_TypeDef TIM5_OCMode,
00176                   TIM5_OutputState_TypeDef TIM5_OutputState,
00177                   uint16_t TIM5_Pulse,
00178                   TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
00179 {
00180   /* Check the parameters */
00181   assert_param(IS_TIM5_OC_MODE_OK(TIM5_OCMode));
00182   assert_param(IS_TIM5_OUTPUT_STATE_OK(TIM5_OutputState));
00183   assert_param(IS_TIM5_OC_POLARITY_OK(TIM5_OCPolarity));
00184   /* Disable the Channel 1: Reset the CCE Bit, Set the Output State, the Output Polarity */
00185   TIM5->CCER2 &= (uint8_t)(~( TIM5_CCER2_CC3E  | TIM5_CCER2_CC3P));
00186   /* Set the Output State & Set the Output Polarity  */
00187   TIM5->CCER2 |= (uint8_t)((uint8_t)(TIM5_OutputState  & TIM5_CCER2_CC3E   )|
00188                            (uint8_t)(TIM5_OCPolarity   & TIM5_CCER2_CC3P   ));
00189
00190   /* Reset the Output Compare Bits  & Set the Output Compare Mode */
00191   TIM5->CCMR3 = (uint8_t)((uint8_t)(TIM5->CCMR3 & (uint8_t)(~TIM5_CCMR_OCM)) | (uint8_t)TIM5_OCMode);
00192
00193   /* Set the Pulse value */
00194   TIM5->CCR3H = (uint8_t)(TIM5_Pulse >> 8);
00195   TIM5->CCR3L = (uint8_t)(TIM5_Pulse);
00196 }
00197
00198 /**
00199   * @brief  Initializes the TIM5 peripheral according to the specified parameters.
00200   * @param    TIM5_Channel specifies the Input Capture Channel from @ref TIM5_Channel_TypeDef.
00201   * @param   TIM5_ICPolarity specifies the Input Capture Polarity from @ref TIM5_ICPolarity_TypeDef.
00202   * @param   TIM5_ICSelection specifies theInput Capture Selection from @ref TIM5_ICSelection_TypeDef.
00203   * @param   TIM5_ICPrescaler specifies the Input Capture Prescaler from @ref TIM5_ICPSC_TypeDef.
00204   * @param   TIM5_ICFilter specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
00205   * @retval None
00206   */
00207 void TIM5_ICInit(TIM5_Channel_TypeDef TIM5_Channel,
00208                  TIM5_ICPolarity_TypeDef TIM5_ICPolarity,
00209                  TIM5_ICSelection_TypeDef TIM5_ICSelection,
00210                  TIM5_ICPSC_TypeDef TIM5_ICPrescaler,
00211                  uint8_t TIM5_ICFilter)
00212 {
00213   /* Check the parameters */
00214   assert_param(IS_TIM5_CHANNEL_OK(TIM5_Channel));
00215   assert_param(IS_TIM5_IC_POLARITY_OK(TIM5_ICPolarity));
00216   assert_param(IS_TIM5_IC_SELECTION_OK(TIM5_ICSelection));
00217   assert_param(IS_TIM5_IC_PRESCALER_OK(TIM5_ICPrescaler));
00218   assert_param(IS_TIM5_IC_FILTER_OK(TIM5_ICFilter));
00219
00220   if (TIM5_Channel == TIM5_CHANNEL_1)
00221   {
00222     /* TI1 Configuration */
00223     TI1_Config((uint8_t)TIM5_ICPolarity,
00224                (uint8_t)TIM5_ICSelection,
00225                (uint8_t)TIM5_ICFilter);
00226
00227     /* Set the Input Capture Prescaler value */
00228     TIM5_SetIC1Prescaler(TIM5_ICPrescaler);
00229   }
00230   else if (TIM5_Channel == TIM5_CHANNEL_2)
00231   {
00232     /* TI2 Configuration */
00233     TI2_Config((uint8_t)TIM5_ICPolarity,
00234                (uint8_t)TIM5_ICSelection,
00235                (uint8_t)TIM5_ICFilter);
00236
00237     /* Set the Input Capture Prescaler value */
00238     TIM5_SetIC2Prescaler(TIM5_ICPrescaler);
00239   }
00240   else
00241   {
00242     /* TI3 Configuration */
00243     TI3_Config((uint8_t)TIM5_ICPolarity,
00244                (uint8_t)TIM5_ICSelection,
00245                (uint8_t)TIM5_ICFilter);
00246
00247     /* Set the Input Capture Prescaler value */
00248     TIM5_SetIC3Prescaler(TIM5_ICPrescaler);
00249   }
00250 }
00251
00252 /**
00253   * @brief  Configures the TIM5 peripheral in PWM Input Mode according to the specified parameters.
00254     * @param    TIM5_Channel specifies the Input Capture Channel from @ref TIM5_Channel_TypeDef.
00255   * @param   TIM5_ICPolarity specifies the Input Capture Polarity from @ref TIM5_ICPolarity_TypeDef.
00256   * @param   TIM5_ICSelection specifies theInput Capture Selection from @ref TIM5_ICSelection_TypeDef.
00257   * @param   TIM5_ICPrescaler specifies the Input Capture Prescaler from @ref TIM5_ICPSC_TypeDef.
00258   * @param   TIM5_ICFilter specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
00259   * @retval None
00260   */
00261 void TIM5_PWMIConfig(TIM5_Channel_TypeDef TIM5_Channel,
00262                      TIM5_ICPolarity_TypeDef TIM5_ICPolarity,
00263                      TIM5_ICSelection_TypeDef TIM5_ICSelection,
00264                      TIM5_ICPSC_TypeDef TIM5_ICPrescaler,
00265                      uint8_t TIM5_ICFilter)
00266 {
00267   uint8_t icpolarity = (uint8_t)TIM5_ICPOLARITY_RISING;
00268   uint8_t icselection = (uint8_t)TIM5_ICSELECTION_DIRECTTI;
00269
00270   /* Check the parameters */
00271   assert_param(IS_TIM5_PWMI_CHANNEL_OK(TIM5_Channel));
00272   assert_param(IS_TIM5_IC_POLARITY_OK(TIM5_ICPolarity));
00273   assert_param(IS_TIM5_IC_SELECTION_OK(TIM5_ICSelection));
00274   assert_param(IS_TIM5_IC_PRESCALER_OK(TIM5_ICPrescaler));
00275
00276   /* Select the Opposite Input Polarity */
00277   if (TIM5_ICPolarity != TIM5_ICPOLARITY_FALLING)
00278   {
00279     icpolarity = (uint8_t)TIM5_ICPOLARITY_FALLING;
00280   }
00281   else
00282   {
00283     icpolarity = (uint8_t)TIM5_ICPOLARITY_RISING;
00284   }
00285
00286   /* Select the Opposite Input */
00287   if (TIM5_ICSelection == TIM5_ICSELECTION_DIRECTTI)
00288   {
00289     icselection = (uint8_t)TIM5_ICSELECTION_INDIRECTTI;
00290   }
00291   else
00292   {
00293     icselection = (uint8_t)TIM5_ICSELECTION_DIRECTTI;
00294   }
00295
00296   if (TIM5_Channel == TIM5_CHANNEL_1)
00297   {
00298     /* TI1 Configuration */
00299     TI1_Config((uint8_t)TIM5_ICPolarity, (uint8_t)TIM5_ICSelection,
00300                (uint8_t)TIM5_ICFilter);
00301
00302     /* Set the Input Capture Prescaler value */
00303     TIM5_SetIC1Prescaler(TIM5_ICPrescaler);
00304
00305     /* TI2 Configuration */
00306     TI2_Config((uint8_t)icpolarity, (uint8_t)icselection, (uint8_t)TIM5_ICFilter);
00307
00308     /* Set the Input Capture Prescaler value */
00309     TIM5_SetIC2Prescaler(TIM5_ICPrescaler);
00310   }
00311   else
00312   {
00313     /* TI2 Configuration */
00314     TI2_Config((uint8_t)TIM5_ICPolarity, (uint8_t)TIM5_ICSelection,
00315                (uint8_t)TIM5_ICFilter);
00316
00317     /* Set the Input Capture Prescaler value */
00318     TIM5_SetIC2Prescaler(TIM5_ICPrescaler);
00319
00320     /* TI1 Configuration */
00321     TI1_Config((uint8_t)icpolarity, (uint8_t)icselection, (uint8_t)TIM5_ICFilter);
00322
00323     /* Set the Input Capture Prescaler value */
00324     TIM5_SetIC1Prescaler(TIM5_ICPrescaler);
00325   }
00326 }
00327
00328 /**
00329   * @brief  Enables or disables the TIM5 peripheral.
00330   * @param   NewState new state of the TIM5 peripheral.This parameter can
00331   * be ENABLE or DISABLE.
00332   * @retval None
00333   */
00334 void TIM5_Cmd(FunctionalState NewState)
00335 {
00336   /* Check the parameters */
00337   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00338
00339   /* set or Reset the CEN Bit */
00340   if (NewState != DISABLE)
00341   {
00342     TIM5->CR1 |= TIM5_CR1_CEN ;
00343   }
00344   else
00345   {
00346     TIM5->CR1 &= (uint8_t)(~TIM5_CR1_CEN) ;
00347   }
00348 }
00349
00350 /**
00351   * @brief  Enables or disables the specified TIM5 interrupts.
00352   * @param   NewState new state of the TIM5 peripheral.
00353   * This parameter can be: ENABLE or DISABLE.
00354   * @param   TIM5_IT specifies the TIM5 interrupts sources to be enabled or disabled.
00355   * This parameter can be any combination of the following values:
00356   *                       - TIM5_IT_UPDATE: TIM5 update Interrupt source
00357   *                       - TIM5_IT_CC1: TIM5 Capture Compare 1 Interrupt source
00358   *                       - TIM5_IT_CC2: TIM5 Capture Compare 2 Interrupt source
00359   *                       - TIM5_IT_CC3: TIM5 Capture Compare 3 Interrupt source
00360   * @param   NewState new state of the TIM5 peripheral.
00361   * @retval None
00362   */
00363 void TIM5_ITConfig(TIM5_IT_TypeDef TIM5_IT, FunctionalState NewState)
00364 {
00365   /* Check the parameters */
00366   assert_param(IS_TIM5_IT_OK(TIM5_IT));
00367   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00368
00369   if (NewState != DISABLE)
00370   {
00371     /* Enable the Interrupt sources */
00372     TIM5->IER |= (uint8_t)TIM5_IT;
00373   }
00374   else
00375   {
00376     /* Disable the Interrupt sources */
00377     TIM5->IER &= (uint8_t)(~TIM5_IT);
00378   }
00379 }
00380
00381 /**
00382   * @brief  Enables or Disables the TIM5 Update event.
00383   * @param   NewState new state of the TIM5 peripheral Preload register.This parameter can
00384   * be ENABLE or DISABLE.
00385   * @retval None
00386   */
00387 void TIM5_UpdateDisableConfig(FunctionalState NewState)
00388 {
00389   /* Check the parameters */
00390   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00391
00392   /* Set or Reset the UDIS Bit */
00393   if (NewState != DISABLE)
00394   {
00395     TIM5->CR1 |= TIM5_CR1_UDIS ;
00396   }
00397   else
00398   {
00399     TIM5->CR1 &= (uint8_t)(~TIM5_CR1_UDIS) ;
00400   }
00401 }
00402
00403 /**
00404   * @brief  Selects the TIM5 Update Request Interrupt source.
00405   * @param   TIM5_UpdateSource specifies the Update source.
00406   * This parameter can be one of the following values
00407   *                       - TIM5_UPDATESOURCE_REGULAR
00408   *                       - TIM5_UPDATESOURCE_GLOBAL
00409   * @retval None
00410   */
00411 void TIM5_UpdateRequestConfig(TIM5_UpdateSource_TypeDef TIM5_UpdateSource)
00412 {
00413   /* Check the parameters */
00414   assert_param(IS_TIM5_UPDATE_SOURCE_OK(TIM5_UpdateSource));
00415
00416   /* Set or Reset the URS Bit */
00417   if (TIM5_UpdateSource != TIM5_UPDATESOURCE_GLOBAL)
00418   {
00419     TIM5->CR1 |= TIM5_CR1_URS ;
00420   }
00421   else
00422   {
00423     TIM5->CR1 &= (uint8_t)(~TIM5_CR1_URS) ;
00424   }
00425 }
00426
00427 /**
00428   * @brief  Selects the TIM5’s One Pulse Mode.
00429   * @param   TIM5_OPMode specifies the OPM Mode to be used.
00430   * This parameter can be one of the following values
00431   *                    - TIM5_OPMODE_SINGLE
00432   *                    - TIM5_OPMODE_REPETITIVE
00433   * @retval None
00434   */
00435 void TIM5_SelectOnePulseMode(TIM5_OPMode_TypeDef TIM5_OPMode)
00436 {
00437   /* Check the parameters */
00438   assert_param(IS_TIM5_OPM_MODE_OK(TIM5_OPMode));
00439
00440   /* Set or Reset the OPM Bit */
00441   if (TIM5_OPMode != TIM5_OPMODE_REPETITIVE)
00442   {
00443     TIM5->CR1 |= TIM5_CR1_OPM ;
00444   }
00445   else
00446   {
00447     TIM5->CR1 &= (uint8_t)(~TIM5_CR1_OPM) ;
00448   }
00449 }
00450
00451 /**
00452   * @brief  Configures the TIM5 Prescaler.
00453   * @param   Prescaler specifies the Prescaler Register value
00454   * This parameter can be one of the following values
00455   *                       -  TIM5_PRESCALER_1
00456   *                       -  TIM5_PRESCALER_2
00457   *                       -  TIM5_PRESCALER_4
00458   *                       -  TIM5_PRESCALER_8
00459   *                       -  TIM5_PRESCALER_16
00460   *                       -  TIM5_PRESCALER_32
00461   *                       -  TIM5_PRESCALER_64
00462   *                       -  TIM5_PRESCALER_128
00463   *                       -  TIM5_PRESCALER_256
00464   *                       -  TIM5_PRESCALER_512
00465   *                       -  TIM5_PRESCALER_1024
00466   *                       -  TIM5_PRESCALER_2048
00467   *                       -  TIM5_PRESCALER_4096
00468   *                       -  TIM5_PRESCALER_8192
00469   *                       -  TIM5_PRESCALER_16384
00470   *                       -  TIM5_PRESCALER_32768
00471   * @param   TIM5_PSCReloadMode specifies the TIM5 Prescaler Reload mode.
00472   * This parameter can be one of the following values
00473   *                       - TIM5_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded
00474   *                         immediately.
00475   *                       - TIM5_PSCRELOADMODE_UPDATE: The Prescaler is loaded at
00476   *                         the update event.
00477   * @retval None
00478   */
00479 void TIM5_PrescalerConfig(TIM5_Prescaler_TypeDef Prescaler,
00480                           TIM5_PSCReloadMode_TypeDef TIM5_PSCReloadMode)
00481 {
00482   /* Check the parameters */
00483   assert_param(IS_TIM5_PRESCALER_RELOAD_OK(TIM5_PSCReloadMode));
00484   assert_param(IS_TIM5_PRESCALER_OK(Prescaler));
00485
00486   /* Set the Prescaler value */
00487   TIM5->PSCR = (uint8_t)Prescaler;
00488
00489   /* Set or reset the UG Bit */
00490   TIM5->EGR = (uint8_t)TIM5_PSCReloadMode ;
00491 }
00492
00493 /**
00494   * @brief  Forces the TIM5 Channel1 output waveform to active or inactive level.
00495   * @param   TIM5_ForcedAction specifies the forced Action to be set to the output waveform.
00496   * This parameter can be one of the following values:
00497   *                       - TIM5_FORCEDACTION_ACTIVE: Force active level on OC1REF
00498   *                       - TIM5_FORCEDACTION_INACTIVE: Force inactive level on
00499   *                         OC1REF.
00500   * @retval None
00501   */
00502 void TIM5_ForcedOC1Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
00503 {
00504   /* Check the parameters */
00505   assert_param(IS_TIM5_FORCED_ACTION_OK(TIM5_ForcedAction));
00506
00507   /* Reset the OCM Bits */ /* Configure The Forced output Mode */
00508   TIM5->CCMR1  =  (uint8_t)((uint8_t)(TIM5->CCMR1 & (uint8_t)(~TIM5_CCMR_OCM))
00509                             | (uint8_t)TIM5_ForcedAction);
00510 }
00511
00512 /**
00513   * @brief  Forces the TIM5 Channel2 output waveform to active or inactive level.
00514   * @param   TIM5_ForcedAction specifies the forced Action to be set to the output waveform.
00515   * This parameter can be one of the following values:
00516   *                       - TIM5_FORCEDACTION_ACTIVE: Force active level on OC2REF
00517   *                       - TIM5_FORCEDACTION_INACTIVE: Force inactive level on
00518   *                         OC2REF.
00519   * @retval None
00520   */
00521 void TIM5_ForcedOC2Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
00522 {
00523   /* Check the parameters */
00524   assert_param(IS_TIM5_FORCED_ACTION_OK(TIM5_ForcedAction));
00525
00526   /* Reset the OCM Bits */ /* Configure The Forced output Mode */
00527   TIM5->CCMR2  =  (uint8_t)((uint8_t)(TIM5->CCMR2 & (uint8_t)(~TIM5_CCMR_OCM))
00528                             | (uint8_t)TIM5_ForcedAction);
00529 }
00530
00531 /**
00532   * @brief  Forces the TIM5 Channel3 output waveform to active or inactive level.
00533   * @param   TIM5_ForcedAction specifies the forced Action to be set to the output waveform.
00534   * This parameter can be one of the following values:
00535   *                       - TIM5_FORCEDACTION_ACTIVE: Force active level on OC3REF
00536   *                       - TIM5_FORCEDACTION_INACTIVE: Force inactive level on
00537   *                         OC3REF.
00538   * @retval None
00539   */
00540 void TIM5_ForcedOC3Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
00541 {
00542   /* Check the parameters */
00543   assert_param(IS_TIM5_FORCED_ACTION_OK(TIM5_ForcedAction));
00544
00545   /* Reset the OCM Bits */ /* Configure The Forced output Mode */
00546   TIM5->CCMR3  =  (uint8_t)((uint8_t)(TIM5->CCMR3 & (uint8_t)(~TIM5_CCMR_OCM))
00547                             | (uint8_t)TIM5_ForcedAction);
00548 }
00549
00550 /**
00551   * @brief  Enables or disables TIM5 peripheral Preload register on ARR.
00552   * @param   NewState new state of the TIM5 peripheral Preload register.
00553   * This parameter can be ENABLE or DISABLE.
00554   * @retval None
00555   */
00556 void TIM5_ARRPreloadConfig(FunctionalState NewState)
00557 {
00558   /* Check the parameters */
00559   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00560
00561   /* Set or Reset the ARPE Bit */
00562   if (NewState != DISABLE)
00563   {
00564     TIM5->CR1 |= TIM5_CR1_ARPE ;
00565   }
00566   else
00567   {
00568     TIM5->CR1 &= (uint8_t)(~TIM5_CR1_ARPE) ;
00569   }
00570 }
00571
00572 /**
00573   * @brief  Enables or disables the TIM5 peripheral Preload Register on CCR1.
00574   * @param   NewState new state of the Capture Compare Preload register.
00575   * This parameter can be ENABLE or DISABLE.
00576   * @retval None
00577   */
00578 void TIM5_OC1PreloadConfig(FunctionalState NewState)
00579 {
00580   /* Check the parameters */
00581   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00582
00583   /* Set or Reset the OC1PE Bit */
00584   if (NewState != DISABLE)
00585   {
00586     TIM5->CCMR1 |= TIM5_CCMR_OCxPE ;
00587   }
00588   else
00589   {
00590     TIM5->CCMR1 &= (uint8_t)(~TIM5_CCMR_OCxPE) ;
00591   }
00592 }
00593
00594 /**
00595   * @brief  Enables or disables the TIM5 peripheral Preload Register on CCR2.
00596   * @param   NewState new state of the Capture Compare Preload register.
00597   * This parameter can be ENABLE or DISABLE.
00598   * @retval None
00599   */
00600 void TIM5_OC2PreloadConfig(FunctionalState NewState)
00601 {
00602   /* Check the parameters */
00603   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00604
00605   /* Set or Reset the OC2PE Bit */
00606   if (NewState != DISABLE)
00607   {
00608     TIM5->CCMR2 |= TIM5_CCMR_OCxPE ;
00609   }
00610   else
00611   {
00612     TIM5->CCMR2 &= (uint8_t)(~TIM5_CCMR_OCxPE) ;
00613   }
00614 }
00615
00616 /**
00617   * @brief  Enables or disables the TIM5 peripheral Preload Register on CCR3.
00618   * @param   NewState new state of the Capture Compare Preload register.
00619   * This parameter can be ENABLE or DISABLE.
00620   * @retval None
00621   */
00622 void TIM5_OC3PreloadConfig(FunctionalState NewState)
00623 {
00624   /* Check the parameters */
00625   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00626
00627   /* Set or Reset the OC3PE Bit */
00628   if (NewState != DISABLE)
00629   {
00630     TIM5->CCMR3 |= TIM5_CCMR_OCxPE ;
00631   }
00632   else
00633   {
00634     TIM5->CCMR3 &= (uint8_t)(~TIM5_CCMR_OCxPE) ;
00635   }
00636 }
00637
00638 /**
00639   * @brief  Configures the TIM5 event to be generated by software.
00640   * @param   TIM5_EventSource specifies the event source.
00641   * This parameter can be one of the following values:
00642   *                       - TIM5_EVENTSOURCE_UPDATE: TIM5 update Event source
00643   *                       - TIM5_EVENTSOURCE_CC1: TIM5 Capture Compare 1 Event source
00644   *                       - TIM5_EVENTSOURCE_CC2: TIM5 Capture Compare 2 Event source
00645   *                       - TIM5_EVENTSOURCE_CC3: TIM5 Capture Compare 3 Event source
00646   * @retval None
00647   */
00648 void TIM5_GenerateEvent(TIM5_EventSource_TypeDef TIM5_EventSource)
00649 {
00650   /* Check the parameters */
00651   assert_param(IS_TIM5_EVENT_SOURCE_OK(TIM5_EventSource));
00652
00653   /* Set the event sources */
00654   TIM5->EGR = (uint8_t)TIM5_EventSource;
00655 }
00656
00657 /**
00658   * @brief  Configures the TIM5 Channel 1 polarity.
00659   * @param   TIM5_OCPolarity specifies the OC1 Polarity.
00660   * This parameter can be one of the following values:
00661   *                       - TIM5_OCPOLARITY_LOW: Output Compare active low
00662   *                       - TIM5_OCPOLARITY_HIGH: Output Compare active high
00663   * @retval None
00664   */
00665 void TIM5_OC1PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
00666 {
00667     /* Check the parameters */
00668     assert_param(IS_TIM5_OC_POLARITY_OK(TIM5_OCPolarity));
00669
00670     /* Set or Reset the CC1P Bit */
00671     if (TIM5_OCPolarity != TIM5_OCPOLARITY_HIGH)
00672     {
00673         TIM5->CCER1 |= TIM5_CCER1_CC1P ;
00674     }
00675     else
00676     {
00677         TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC1P) ;
00678     }
00679 }
00680
00681
00682 /**
00683   * @brief  Configures the TIM5 Channel 2 polarity.
00684   * @param   TIM5_OCPolarity specifies the OC2 Polarity.
00685   * This parameter can be one of the following values:
00686   *                       - TIM5_OCPOLARITY_LOW: Output Compare active low
00687   *                       - TIM5_OCPOLARITY_HIGH: Output Compare active high
00688   * @retval None
00689   */
00690 void TIM5_OC2PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
00691 {
00692   /* Check the parameters */
00693   assert_param(IS_TIM5_OC_POLARITY_OK(TIM5_OCPolarity));
00694
00695   /* Set or Reset the CC2P Bit */
00696   if (TIM5_OCPolarity != TIM5_OCPOLARITY_HIGH)
00697   {
00698     TIM5->CCER1 |= TIM5_CCER1_CC2P ;
00699   }
00700   else
00701   {
00702     TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC2P) ;
00703   }
00704 }
00705
00706 /**
00707   * @brief  Configures the TIM5 Channel 3 polarity.
00708   * @param   TIM5_OCPolarity specifies the OC3 Polarity.
00709   * This parameter can be one of the following values:
00710   *                       - TIM5_OCPOLARITY_LOW: Output Compare active low
00711   *                       - TIM5_OCPOLARITY_HIGH: Output Compare active high
00712   * @retval None
00713   */
00714 void TIM5_OC3PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
00715 {
00716   /* Check the parameters */
00717   assert_param(IS_TIM5_OC_POLARITY_OK(TIM5_OCPolarity));
00718
00719   /* Set or Reset the CC3P Bit */
00720   if (TIM5_OCPolarity != TIM5_OCPOLARITY_HIGH)
00721   {
00722     TIM5->CCER2 |= TIM5_CCER2_CC3P ;
00723   }
00724   else
00725   {
00726     TIM5->CCER2 &= (uint8_t)(~TIM5_CCER2_CC3P) ;
00727   }
00728 }
00729
00730 /**
00731   * @brief  Enables or disables the TIM5 Capture Compare Channel x.
00732   * @param   TIM5_Channel specifies the TIM5 Channel.
00733   * This parameter can be one of the following values:
00734   *                       - TIM5_Channel1: TIM5 Channel1
00735   *                       - TIM5_Channel2: TIM5 Channel2
00736   *                       - TIM5_Channel3: TIM5 Channel3
00737   * @param   NewState specifies the TIM5 Channel CCxE bit new state.
00738   * This parameter can be: ENABLE or DISABLE.
00739   * @retval None
00740   */
00741 void TIM5_CCxCmd(TIM5_Channel_TypeDef TIM5_Channel, FunctionalState NewState)
00742 {
00743   /* Check the parameters */
00744   assert_param(IS_TIM5_CHANNEL_OK(TIM5_Channel));
00745   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00746
00747   if (TIM5_Channel == TIM5_CHANNEL_1)
00748   {
00749     /* Set or Reset the CC1E Bit */
00750     if (NewState != DISABLE)
00751     {
00752       TIM5->CCER1 |= TIM5_CCER1_CC1E ;
00753     }
00754     else
00755     {
00756       TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC1E) ;
00757     }
00758
00759   }
00760   else if (TIM5_Channel == TIM5_CHANNEL_2)
00761   {
00762     /* Set or Reset the CC2E Bit */
00763     if (NewState != DISABLE)
00764     {
00765       TIM5->CCER1 |= TIM5_CCER1_CC2E;
00766     }
00767     else
00768     {
00769       TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC2E) ;
00770     }
00771   }
00772   else
00773   {
00774     /* Set or Reset the CC3E Bit */
00775     if (NewState != DISABLE)
00776     {
00777       TIM5->CCER2 |= TIM5_CCER2_CC3E;
00778     }
00779     else
00780     {
00781       TIM5->CCER2 &= (uint8_t)(~TIM5_CCER2_CC3E) ;
00782     }
00783   }
00784 }
00785
00786 /**
00787   * @brief  Selects the TIM5 Output Compare Mode. This function disables the
00788   * selected channel before changing the Output Compare Mode. User has to
00789   * enable this channel using TIM5_CCxCmd and TIM5_CCxNCmd functions.
00790   * @param   TIM5_Channel specifies the TIM5 Channel.
00791   * This parameter can be one of the following values:
00792   *                       - TIM5_Channel1: TIM5 Channel1
00793   *                       - TIM5_Channel2: TIM5 Channel2
00794   *                       - TIM5_Channel3: TIM5 Channel3
00795   * @param   TIM5_OCMode specifies the TIM5 Output Compare Mode.
00796   * This parameter can be one of the following values:
00797   *                       - TIM5_OCMODE_TIMING
00798   *                       - TIM5_OCMODE_ACTIVE
00799   *                       - TIM5_OCMODE_TOGGLE
00800   *                       - TIM5_OCMODE_PWM1
00801   *                       - TIM5_OCMODE_PWM2
00802   *                       - TIM5_FORCEDACTION_ACTIVE
00803   *                       - TIM5_FORCEDACTION_INACTIVE
00804   * @retval None
00805   */
00806 void TIM5_SelectOCxM(TIM5_Channel_TypeDef TIM5_Channel, TIM5_OCMode_TypeDef TIM5_OCMode)
00807 {
00808   /* Check the parameters */
00809   assert_param(IS_TIM5_CHANNEL_OK(TIM5_Channel));
00810   assert_param(IS_TIM5_OCM_OK(TIM5_OCMode));
00811
00812   if (TIM5_Channel == TIM5_CHANNEL_1)
00813   {
00814     /* Disable the Channel 1: Reset the CCE Bit */
00815     TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC1E);
00816
00817     /* Reset the Output Compare Bits  Set the Output Compare Mode */
00818     TIM5->CCMR1 = (uint8_t)((uint8_t)(TIM5->CCMR1 & (uint8_t)(~TIM5_CCMR_OCM))
00819                             | (uint8_t)TIM5_OCMode);
00820   }
00821   else if (TIM5_Channel == TIM5_CHANNEL_2)
00822   {
00823     /* Disable the Channel 2: Reset the CCE Bit */
00824     TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC2E);
00825
00826     /* Reset the Output Compare Bits ** Set the Output Compare Mode */
00827     TIM5->CCMR2 = (uint8_t)((uint8_t)(TIM5->CCMR2 & (uint8_t)(~TIM5_CCMR_OCM))
00828                             | (uint8_t)TIM5_OCMode);
00829   }
00830   else
00831   {
00832     /* Disable the Channel 3: Reset the CCE Bit */
00833     TIM5->CCER2 &= (uint8_t)(~TIM5_CCER2_CC3E);
00834
00835     /* Reset the Output Compare Bits ** Set the Output Compare Mode */
00836     TIM5->CCMR3 = (uint8_t)((uint8_t)(TIM5->CCMR3 & (uint8_t)(~TIM5_CCMR_OCM))
00837                             | (uint8_t)TIM5_OCMode);
00838   }
00839 }
00840
00841 /**
00842   * @brief  Sets the TIM5 Counter Register value.
00843   * @param   Counter specifies the Counter register new value.
00844   * This parameter is between 0x0000 and 0xFFFF.
00845   * @retval None
00846   */
00847 void TIM5_SetCounter(uint16_t Counter)
00848 {
00849   /* Set the Counter Register value */
00850   TIM5->CNTRH = (uint8_t)(Counter >> 8);
00851   TIM5->CNTRL = (uint8_t)(Counter);
00852 }
00853
00854 /**
00855   * @brief  Sets the TIM5 Autoreload Register value.
00856   * @param   Autoreload specifies the Autoreload register new value.
00857   * This parameter is between 0x0000 and 0xFFFF.
00858   * @retval None
00859   */
00860 void TIM5_SetAutoreload(uint16_t Autoreload)
00861 {
00862   /* Set the Autoreload Register value */
00863   TIM5->ARRH = (uint8_t)(Autoreload >> 8);
00864   TIM5->ARRL = (uint8_t)(Autoreload);
00865 }
00866
00867 /**
00868   * @brief  Sets the TIM5 Capture Compare1 Register value.
00869   * @param   Compare1 specifies the Capture Compare1 register new value.
00870   * This parameter is between 0x0000 and 0xFFFF.
00871   * @retval None
00872   */
00873 void TIM5_SetCompare1(uint16_t Compare1)
00874 {
00875   /* Set the Capture Compare1 Register value */
00876   TIM5->CCR1H = (uint8_t)(Compare1 >> 8);
00877   TIM5->CCR1L = (uint8_t)(Compare1);
00878 }
00879
00880 /**
00881   * @brief  Sets the TIM5 Capture Compare2 Register value.
00882   * @param   Compare2 specifies the Capture Compare2 register new value.
00883   * This parameter is between 0x0000 and 0xFFFF.
00884   * @retval None
00885   */
00886 void TIM5_SetCompare2(uint16_t Compare2)
00887 {
00888   /* Set the Capture Compare2 Register value */
00889   TIM5->CCR2H = (uint8_t)(Compare2 >> 8);
00890   TIM5->CCR2L = (uint8_t)(Compare2);
00891 }
00892
00893 /**
00894   * @brief  Sets the TIM5 Capture Compare3 Register value.
00895   * @param   Compare3 specifies the Capture Compare3 register new value.
00896   * This parameter is between 0x0000 and 0xFFFF.
00897   * @retval None
00898   */
00899 void TIM5_SetCompare3(uint16_t Compare3)
00900 {
00901   /* Set the Capture Compare3 Register value */
00902   TIM5->CCR3H = (uint8_t)(Compare3 >> 8);
00903   TIM5->CCR3L = (uint8_t)(Compare3);
00904 }
00905
00906 /**
00907   * @brief  Sets the TIM5 Input Capture 1 prescaler.
00908   * @param   TIM5_IC1Prescaler specifies the Input Capture prescaler new value
00909   * This parameter can be one of the following values:
00910   *                       - TIM5_ICPSC_DIV1: no prescaler
00911   *                       - TIM5_ICPSC_DIV2: capture is done once every 2 events
00912   *                       - TIM5_ICPSC_DIV4: capture is done once every 4 events
00913   *                       - TIM5_ICPSC_DIV8: capture is done once every 8 events
00914   * @retval None
00915   */
00916 void TIM5_SetIC1Prescaler(TIM5_ICPSC_TypeDef TIM5_IC1Prescaler)
00917 {
00918   /* Check the parameters */
00919   assert_param(IS_TIM5_IC_PRESCALER_OK(TIM5_IC1Prescaler));
00920
00921   /* Reset the IC1PSC Bits */ /* Set the IC1PSC value */
00922   TIM5->CCMR1 = (uint8_t)((uint8_t)(TIM5->CCMR1 & (uint8_t)(~TIM5_CCMR_ICxPSC))|
00923                           (uint8_t)TIM5_IC1Prescaler);
00924 }
00925
00926 /**
00927   * @brief  Sets the TIM5 Input Capture 2 prescaler.
00928   * @param   TIM5_IC2Prescaler specifies the Input Capture prescaler new value
00929   * This parameter can be one of the following values:
00930   *                       - TIM5_ICPSC_DIV1: no prescaler
00931   *                       - TIM5_ICPSC_DIV2: capture is done once every 2 events
00932   *                       - TIM5_ICPSC_DIV4: capture is done once every 4 events
00933   *                       - TIM5_ICPSC_DIV8: capture is done once every 8 events
00934   * @retval None
00935   */
00936 void TIM5_SetIC2Prescaler(TIM5_ICPSC_TypeDef TIM5_IC2Prescaler)
00937 {
00938   /* Check the parameters */
00939   assert_param(IS_TIM5_IC_PRESCALER_OK(TIM5_IC2Prescaler));
00940
00941   /* Reset the IC1PSC Bits */ /* Set the IC1PSC value */
00942   TIM5->CCMR2 = (uint8_t)((uint8_t)(TIM5->CCMR2 & (uint8_t)(~TIM5_CCMR_ICxPSC))
00943                           | (uint8_t)TIM5_IC2Prescaler);
00944 }
00945
00946 /**
00947   * @brief  Sets the TIM5 Input Capture 3 prescaler.
00948   * @param   TIM5_IC3Prescaler specifies the Input Capture prescaler new value
00949   * This parameter can be one of the following values:
00950   *                       - TIM5_ICPSC_DIV1: no prescaler
00951   *                       - TIM5_ICPSC_DIV2: capture is done once every 2 events
00952   *                       - TIM5_ICPSC_DIV4: capture is done once every 4 events
00953   *                       - TIM5_ICPSC_DIV8: capture is done once every 8 events
00954   * @retval None
00955   */
00956 void TIM5_SetIC3Prescaler(TIM5_ICPSC_TypeDef TIM5_IC3Prescaler)
00957 {
00958   /* Check the parameters */
00959   assert_param(IS_TIM5_IC_PRESCALER_OK(TIM5_IC3Prescaler));
00960   /* Reset the IC1PSC Bits */ /* Set the IC1PSC value */
00961   TIM5->CCMR3 = (uint8_t)((uint8_t)(TIM5->CCMR3 & (uint8_t)(~TIM5_CCMR_ICxPSC)) |
00962                           (uint8_t)TIM5_IC3Prescaler);
00963 }
00964
00965 /**
00966   * @brief  Gets the TIM5 Input Capture 1 value.
00967   * @param  None
00968   * @retval Capture Compare 1 Register value.
00969   */
00970 uint16_t TIM5_GetCapture1(void)
00971 {
00972   uint16_t temp = 0;
00973
00974   temp = ((uint16_t)TIM5->CCR1H << 8);
00975
00976   /* Get the Capture 1 Register value */
00977   return (uint16_t)(temp | (uint16_t)(TIM5->CCR1L));
00978 }
00979
00980 /**
00981   * @brief  Gets the TIM5 Input Capture 2 value.
00982   * @param  None
00983   * @retval Capture Compare 2 Register value.
00984   */
00985 uint16_t TIM5_GetCapture2(void)
00986 {
00987   uint16_t temp = 0;
00988
00989   temp = ((uint16_t)TIM5->CCR2H << 8);
00990
00991   /* Get the Capture 2 Register value */
00992   return (uint16_t)(temp | (uint16_t)(TIM5->CCR2L));
00993 }
00994
00995 /**
00996   * @brief  Gets the TIM5 Input Capture 3 value.
00997   * @param  None
00998   * @retval Capture Compare 3 Register value.
00999   */
01000 uint16_t TIM5_GetCapture3(void)
01001 {
01002   uint16_t temp = 0;
01003
01004   temp = ((uint16_t)TIM5->CCR3H << 8);
01005   /* Get the Capture 1 Register value */
01006   return (uint16_t)(temp | (uint16_t)(TIM5->CCR3L));
01007 }
01008
01009 /**
01010   * @brief  Gets the TIM5 Counter value.
01011   * @param  None
01012   * @retval Counter Register value.
01013   */
01014 uint16_t TIM5_GetCounter(void)
01015 {
01016   uint16_t tmpcntr = 0;
01017
01018   tmpcntr = ((uint16_t)TIM5->CNTRH << 8);
01019   /* Get the Counter Register value */
01020   return (uint16_t)(tmpcntr | (uint16_t)(TIM5->CNTRL));
01021 }
01022
01023 /**
01024   * @brief  Gets the TIM5 Prescaler value.
01025   * @param  None
01026   * @retval Prescaler Register configuration value  @ref TIM5_Prescaler_TypeDef .
01027   */
01028 TIM5_Prescaler_TypeDef TIM5_GetPrescaler(void)
01029 {
01030   /* Get the Prescaler Register value */
01031   return (TIM5_Prescaler_TypeDef)(TIM5->PSCR);
01032 }
01033
01034 /**
01035   * @brief  Checks whether the specified TIM5 flag is set or not.
01036   * @param   TIM5_FLAG specifies the flag to check.
01037   * This parameter can be one of the following values:
01038   *                       - TIM5_FLAG_UPDATE: TIM5 update Flag
01039   *                       - TIM5_FLAG_CC1: TIM5 Capture Compare 1 Flag
01040   *                       - TIM5_FLAG_CC2: TIM5 Capture Compare 2 Flag
01041   *                       - TIM5_FLAG_CC3: TIM5 Capture Compare 3 Flag
01042   *                       - TIM5_FLAG_CC1OF: TIM5 Capture Compare 1 overcapture Flag
01043   *                       - TIM5_FLAG_CC2OF: TIM5 Capture Compare 2 overcapture Flag
01044   *                       - TIM5_FLAG_CC3OF: TIM5 Capture Compare 3 overcapture Flag
01045   * @retval FlagStatus The new state of TIM5_FLAG (SET or RESET).
01046   */
01047 FlagStatus TIM5_GetFlagStatus(TIM5_FLAG_TypeDef TIM5_FLAG)
01048 {
01049   FlagStatus bitstatus = RESET;
01050   uint8_t tim5_flag_l, tim5_flag_h;
01051
01052   /* Check the parameters */
01053   assert_param(IS_TIM5_GET_FLAG_OK(TIM5_FLAG));
01054
01055   tim5_flag_l= (uint8_t)(TIM5->SR1 & (uint8_t)TIM5_FLAG);
01056   tim5_flag_h= (uint8_t)((uint16_t)TIM5_FLAG >> 8);
01057
01058   if (((tim5_flag_l)|(uint8_t)(TIM5->SR2 & tim5_flag_h)) != RESET )
01059   {
01060     bitstatus = SET;
01061   }
01062   else
01063   {
01064     bitstatus = RESET;
01065   }
01066   return (FlagStatus)bitstatus;
01067 }
01068
01069 /**
01070   * @brief  Clears the TIM5’s pending flags.
01071   * @param   TIM5_FLAG specifies the flag to clear.
01072   * This parameter can be one of the following values:
01073   *                       - TIM5_FLAG_UPDATE: TIM5 update Flag
01074   *                       - TIM5_FLAG_CC1: TIM5 Capture Compare 1 Flag
01075   *                       - TIM5_FLAG_CC2: TIM5 Capture Compare 2 Flag
01076   *                       - TIM5_FLAG_CC3: TIM5 Capture Compare 3 Flag
01077   *                       - TIM5_FLAG_CC1OF: TIM5 Capture Compare 1 overcapture Flag
01078   *                       - TIM5_FLAG_CC2OF: TIM5 Capture Compare 2 overcapture Flag
01079   *                       - TIM5_FLAG_CC3OF: TIM5 Capture Compare 3 overcapture Flag
01080   * @retval None.
01081   */
01082 void TIM5_ClearFlag(TIM5_FLAG_TypeDef TIM5_FLAG)
01083 {
01084   /* Check the parameters */
01085   assert_param(IS_TIM5_CLEAR_FLAG_OK(TIM5_FLAG));
01086
01087   /* Clear the flags (rc_w0) clear this bit by writing 0. Writing ‘1’ has no effect*/
01088   TIM5->SR1 = (uint8_t)(~((uint8_t)(TIM5_FLAG)));
01089   TIM5->SR2 &= (uint8_t)(~((uint8_t)((uint16_t)TIM5_FLAG >> 8)));
01090 }
01091
01092 /**
01093   * @brief  Checks whether the TIM5 interrupt has occurred or not.
01094   * @param   TIM5_IT specifies the TIM5 interrupt source to check.
01095   * This parameter can be one of the following values:
01096   *                       - TIM5_IT_UPDATE: TIM5 update Interrupt source
01097   *                       - TIM5_IT_CC1: TIM5 Capture Compare 1 Interrupt source
01098   *                       - TIM5_IT_CC2: TIM5 Capture Compare 2 Interrupt source
01099   *                       - TIM5_IT_CC3: TIM5 Capture Compare 3 Interrupt source
01100   * @retval ITStatus The new state of the TIM5_IT(SET or RESET).
01101   */
01102
01103 ITStatus TIM5_GetITStatus(TIM5_IT_TypeDef TIM5_IT)
01104 {
01105   ITStatus bitstatus = RESET;
01106   uint8_t TIM5_itStatus = 0, TIM5_itEnable = 0;
01107
01108   /* Check the parameters */
01109   assert_param(IS_TIM5_GET_IT_OK(TIM5_IT));
01110
01111   TIM5_itStatus = (uint8_t)(TIM5->SR1 & TIM5_IT);
01112
01113   TIM5_itEnable = (uint8_t)(TIM5->IER & TIM5_IT);
01114
01115   if ((TIM5_itStatus != (uint8_t)RESET ) && (TIM5_itEnable != (uint8_t)RESET ))
01116   {
01117     bitstatus = SET;
01118   }
01119   else
01120   {
01121     bitstatus = RESET;
01122   }
01123   return (ITStatus)(bitstatus);
01124 }
01125
01126 /**
01127   * @brief  Clears the TIM5's interrupt pending bits.
01128   * @param   TIM5_IT specifies the pending bit to clear.
01129   * This parameter can be one of the following values:
01130   *                       - TIM5_IT_UPDATE: TIM5 update Interrupt source
01131   *                       - TIM5_IT_CC1: TIM5 Capture Compare 1 Interrupt source
01132   *                       - TIM5_IT_CC2: TIM5 Capture Compare 2 Interrupt source
01133   *                       - TIM5_IT_CC3: TIM5 Capture Compare 3 Interrupt source
01134   * @retval None.
01135   */
01136 void TIM5_ClearITPendingBit(TIM5_IT_TypeDef TIM5_IT)
01137 {
01138   /* Check the parameters */
01139   assert_param(IS_TIM5_IT_OK(TIM5_IT));
01140
01141   /* Clear the IT pending Bit */
01142   TIM5->SR1 = (uint8_t)(~TIM5_IT);
01143 }
01144
01145 /**
01146   * @brief  Configure the TI1 as Input.
01147   * @param   TIM5_ICPolarity  The Input Polarity.
01148   * This parameter can be one of the following values:
01149   *                       - TIM5_ICPOLARITY_FALLING
01150   *                       - TIM5_ICPOLARITY_RISING
01151   * @param   TIM5_ICSelection specifies the input to be used.
01152   * This parameter can be one of the following values:
01153   *                       - TIM5_ICSELECTION_DIRECTTI: TIM5 Input 1 is selected to
01154   *                         be connected to IC1.
01155   *                       - TIM5_ICSELECTION_INDIRECTTI: TIM5 Input 1 is selected to
01156   *                         be connected to IC2.
01157   * @param   TIM5_ICFilter Specifies the Input Capture Filter.
01158   * This parameter must be a value between 0x00 and 0x0F.
01159   * @retval None
01160   */
01161 static void TI1_Config(uint8_t TIM5_ICPolarity,
01162                        uint8_t TIM5_ICSelection,
01163                        uint8_t TIM5_ICFilter)
01164 {
01165   /* Disable the Channel 1: Reset the CCE Bit */
01166   TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC1E);
01167
01168   /* Select the Input and set the filter */
01169   TIM5->CCMR1  = (uint8_t)((uint8_t)(TIM5->CCMR1 & (uint8_t)(~( TIM5_CCMR_CCxS | TIM5_CCMR_ICxF )))
01170                            | (uint8_t)(( (TIM5_ICSelection)) | ((uint8_t)( TIM5_ICFilter << 4))));
01171
01172   /* Select the Polarity */
01173   if (TIM5_ICPolarity != TIM5_ICPOLARITY_RISING)
01174   {
01175     TIM5->CCER1 |= TIM5_CCER1_CC1P ;
01176   }
01177   else
01178   {
01179     TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC1P) ;
01180   }
01181   /* Set the CCE Bit */
01182   TIM5->CCER1 |=  TIM5_CCER1_CC1E;
01183 }
01184
01185 /**
01186   * @brief  Configure the TI2 as Input.
01187   * @param   TIM5_ICPolarity  The Input Polarity.
01188   * This parameter can be one of the following values:
01189   *                       - TIM5_ICPOLARITY_FALLING
01190   *                       - TIM5_ICPOLARITY_RISING
01191   * @param   TIM5_ICSelection specifies the input to be used.
01192   * This parameter can be one of the following values:
01193   *                       - TIM5_ICSELECTION_DIRECTTI: TIM5 Input 2 is selected to
01194   *                         be connected to IC2.
01195   *                       - TIM5_ICSELECTION_INDIRECTTI: TIM5 Input 2 is selected to
01196   *                         be connected to IC1.
01197   * @param   TIM5_ICFilter Specifies the Input Capture Filter.
01198   * This parameter must be a value between 0x00 and 0x0F.
01199   * @retval None
01200   */
01201 static void TI2_Config(uint8_t TIM5_ICPolarity,
01202                        uint8_t TIM5_ICSelection,
01203                        uint8_t TIM5_ICFilter)
01204 {
01205   /* Disable the Channel 2: Reset the CCE Bit */
01206   TIM5->CCER1 &=  (uint8_t)(~TIM5_CCER1_CC2E);
01207
01208   /* Select the Input and set the filter */
01209   TIM5->CCMR2  = (uint8_t)((uint8_t)(TIM5->CCMR2 & (uint8_t)(~( TIM5_CCMR_CCxS | TIM5_CCMR_ICxF)))
01210                            | (uint8_t)(( (TIM5_ICSelection)) | ((uint8_t)( TIM5_ICFilter << 4))));
01211
01212
01213   /* Select the Polarity */
01214   if (TIM5_ICPolarity != TIM5_ICPOLARITY_RISING)
01215   {
01216     TIM5->CCER1 |= TIM5_CCER1_CC2P ;
01217   }
01218   else
01219   {
01220     TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC2P) ;
01221   }
01222
01223   /* Set the CCE Bit */
01224   TIM5->CCER1 |=  TIM5_CCER1_CC2E;
01225 }
01226
01227 /**
01228   * @brief  Configure the TI3 as Input.
01229   * @param   TIM5_ICPolarity  The Input Polarity.
01230   * This parameter can be one of the following values:
01231   *                       - TIM5_ICPOLARITY_FALLING
01232   *                       - TIM5_ICPOLARITY_RISING
01233   * @param   TIM5_ICSelection specifies the input to be used.
01234   * This parameter can be one of the following values:
01235   *                       - TIM5_ICSELECTION_DIRECTTI: TIM5 Input 3 is selected to
01236   *                         be connected to IC3.
01237   * @param   TIM5_ICFilter Specifies the Input Capture Filter.
01238   * This parameter must be a value between 0x00 and 0x0F.
01239   * @retval None
01240   */
01241 static void TI3_Config(uint8_t TIM5_ICPolarity, uint8_t TIM5_ICSelection,
01242                        uint8_t TIM5_ICFilter)
01243 {
01244   /* Disable the Channel 3: Reset the CCE Bit */
01245   TIM5->CCER2 &=  (uint8_t)(~TIM5_CCER2_CC3E);
01246
01247   /* Select the Input and set the filter */
01248   TIM5->CCMR3 = (uint8_t)((uint8_t)(TIM5->CCMR3 & (uint8_t)(~( TIM5_CCMR_CCxS | TIM5_CCMR_ICxF)))
01249                           | (uint8_t)(( (TIM5_ICSelection)) | ((uint8_t)( TIM5_ICFilter << 4))));
01250
01251
01252   /* Select the Polarity */
01253   if (TIM5_ICPolarity != TIM5_ICPOLARITY_RISING)
01254   {
01255     TIM5->CCER2 |= TIM5_CCER2_CC3P ;
01256   }
01257   else
01258   {
01259     TIM5->CCER2 &= (uint8_t)(~TIM5_CCER2_CC3P) ;
01260   }
01261   /* Set the CCE Bit */
01262   TIM5->CCER2 |=  TIM5_CCER2_CC3E;
01263 }
01264
01265 /**
01266   * @brief  Enables the TIM5 internal Clock.
01267   * @par Parameters:
01268         * None
01269   * @retval None
01270   */
01271 void TIM5_InternalClockConfig(void)
01272 {
01273   /* Disable slave mode to clock the prescaler directly with the internal clock */
01274   TIM5->SMCR &=  (uint8_t)(~TIM5_SMCR_SMS);
01275 }
01276
01277 /**
01278   * @brief  Selects the TIM5 Trigger Output Mode.
01279   * @param   TIM5_TRGOSource : Specifies the Trigger Output source.
01280   * This parameter can be one of the @ref TIM5_TRGOSource_TypeDef enumeration.
01281   * @retval None
01282   */
01283 void TIM5_SelectOutputTrigger(TIM5_TRGOSource_TypeDef TIM5_TRGOSource)
01284 {
01285   uint8_t tmpcr2 = 0;
01286
01287   /* Check the parameters */
01288   assert_param(IS_TIM5_TRGO_SOURCE_OK(TIM5_TRGOSource));
01289
01290   tmpcr2 = TIM5->CR2;
01291
01292   /* Reset the MMS Bits */
01293   tmpcr2 &= (uint8_t)(~TIM5_CR2_MMS);
01294
01295   /* Select the TRGO source */
01296   tmpcr2 |=  (uint8_t)TIM5_TRGOSource;
01297
01298   TIM5->CR2 = tmpcr2;
01299 }
01300
01301 /**
01302   * @brief  Selects the TIM5 Slave Mode.
01303   * @param   TIM5_SlaveMode : Specifies the TIM5 Slave Mode.
01304   * This parameter can be one of the @ref TIM5_SlaveMode_TypeDef enumeration.
01305   * @retval None
01306   */
01307 void TIM5_SelectSlaveMode(TIM5_SlaveMode_TypeDef TIM5_SlaveMode)
01308 {
01309   uint8_t tmpsmcr = 0;
01310
01311   /* Check the parameters */
01312   assert_param(IS_TIM5_SLAVE_MODE_OK(TIM5_SlaveMode));
01313
01314   tmpsmcr = TIM5->SMCR;
01315
01316   /* Reset the SMS Bits */
01317   tmpsmcr &= (uint8_t)(~TIM5_SMCR_SMS);
01318
01319   /* Select the Slave Mode */
01320   tmpsmcr |= (uint8_t)TIM5_SlaveMode;
01321
01322   TIM5->SMCR = tmpsmcr;
01323 }
01324
01325 /**
01326   * @brief  Selects the TIM5 Input Trigger source.
01327   * @param   TIM5_InputTriggerSource : Specifies Input Trigger source.
01328   * This parameter can be one of the @ref TIM5_TS_TypeDef enumeration.
01329   * @retval None
01330   */
01331 void TIM5_SelectInputTrigger(TIM5_TS_TypeDef TIM5_InputTriggerSource)
01332 {
01333   uint8_t tmpsmcr = 0;
01334
01335   /* Check the parameters */
01336   assert_param(IS_TIM5_TRIGGER_SELECTION_OK(TIM5_InputTriggerSource));
01337
01338   tmpsmcr = TIM5->SMCR;
01339
01340   /* Select the Trigger Source */
01341   tmpsmcr &= (uint8_t)(~TIM5_SMCR_TS);
01342   tmpsmcr |= (uint8_t)TIM5_InputTriggerSource;
01343
01344   TIM5->SMCR = (uint8_t)tmpsmcr;
01345 }
01346
01347 /**
01348   * @brief  Configures the TIM5 Encoder Interface.
01349   * @param   TIM5_EncoderMode : Specifies the TIM5 Encoder Mode.
01350   * This parameter can be one of the @ref TIM5_EncoderMode_TypeDef enumeration.
01351   * @param   TIM5_IC1Polarity : Specifies the IC1 Polarity.
01352   * This parameter can be one of the @ref TIM5_ICPolarity_TypeDef enumeration.
01353   * @param   TIM5_IC2Polarity : Specifies the IC2 Polarity.
01354   * This parameter can be one of the @ref TIM5_ICPolarity_TypeDef enumeration.
01355   * @retval None
01356   */
01357 void TIM5_EncoderInterfaceConfig(TIM5_EncoderMode_TypeDef TIM5_EncoderMode,
01358                                  TIM5_ICPolarity_TypeDef TIM5_IC1Polarity,
01359                                  TIM5_ICPolarity_TypeDef TIM5_IC2Polarity)
01360 {
01361   uint8_t tmpsmcr = 0;
01362   uint8_t tmpccmr1 = 0;
01363   uint8_t tmpccmr2 = 0;
01364
01365   /* Check the parameters */
01366   assert_param(IS_TIM5_ENCODER_MODE_OK(TIM5_EncoderMode));
01367   assert_param(IS_TIM5_IC_POLARITY_OK(TIM5_IC1Polarity));
01368   assert_param(IS_TIM5_IC_POLARITY_OK(TIM5_IC2Polarity));
01369
01370   tmpsmcr = TIM5->SMCR;
01371   tmpccmr1 = TIM5->CCMR1;
01372   tmpccmr2 = TIM5->CCMR2;
01373
01374   /* Set the encoder Mode */
01375   tmpsmcr &= (uint8_t)(TIM5_SMCR_MSM | TIM5_SMCR_TS)  ;
01376   tmpsmcr |= (uint8_t)TIM5_EncoderMode;
01377
01378   /* Select the Capture Compare 1 and the Capture Compare 2 as input */
01379   tmpccmr1 &= (uint8_t)(~TIM5_CCMR_CCxS);
01380   tmpccmr2 &= (uint8_t)(~TIM5_CCMR_CCxS);
01381   tmpccmr1 |= TIM5_CCMR_TIxDirect_Set;
01382   tmpccmr2 |= TIM5_CCMR_TIxDirect_Set;
01383
01384   /* Set the TI1 and the TI2 Polarities */
01385   if (TIM5_IC1Polarity == TIM5_ICPOLARITY_FALLING)
01386   {
01387     TIM5->CCER1 |= TIM5_CCER1_CC1P ;
01388   }
01389   else
01390   {
01391     TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC1P) ;
01392   }
01393
01394   if (TIM5_IC2Polarity == TIM5_ICPOLARITY_FALLING)
01395   {
01396     TIM5->CCER1 |= TIM5_CCER1_CC2P ;
01397   }
01398   else
01399   {
01400     TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC2P) ;
01401   }
01402
01403   TIM5->SMCR = tmpsmcr;
01404   TIM5->CCMR1 = tmpccmr1;
01405   TIM5->CCMR2 = tmpccmr2;
01406 }
01407
01408 /**
01409   * @}
01410   */
01411
01412 /**
01413   * @}
01414   */
01415
01416
01417 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_tim5.h Source File

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stm8s_tim5.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_tim5.h
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all functions prototype and macros for the TIM5 peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Define to prevent recursive inclusion -------------------------------------*/
00029 #ifndef __STM8S_TIM5_H
00030 #define __STM8S_TIM5_H
00031
00032 /* Includes ------------------------------------------------------------------*/
00033 #include "stm8s.h"
00034
00035 /** @addtogroup STM8S_StdPeriph_Driver
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040
00041
00042 /** TIM5 Forced Action */
00043 typedef enum
00044 {
00045     TIM5_FORCEDACTION_ACTIVE           =((uint8_t)0x50),
00046     TIM5_FORCEDACTION_INACTIVE         =((uint8_t)0x40)
00047 }TIM5_ForcedAction_TypeDef;
00048
00049 #define IS_TIM5_FORCED_ACTION_OK(ACTION) (((ACTION) == TIM5_FORCEDACTION_ACTIVE) || \
00050                                        ((ACTION) == TIM5_FORCEDACTION_INACTIVE))
00051
00052 /** TIM5 Prescaler */
00053 typedef enum
00054 {
00055     TIM5_PRESCALER_1     =((uint8_t)0x00),
00056     TIM5_PRESCALER_2      =((uint8_t)0x01),
00057     TIM5_PRESCALER_4      =((uint8_t)0x02),
00058     TIM5_PRESCALER_8      =((uint8_t)0x03),
00059     TIM5_PRESCALER_16     =((uint8_t)0x04),
00060     TIM5_PRESCALER_32     =((uint8_t)0x05),
00061     TIM5_PRESCALER_64     =((uint8_t)0x06),
00062     TIM5_PRESCALER_128    =((uint8_t)0x07),
00063     TIM5_PRESCALER_256    =((uint8_t)0x08),
00064     TIM5_PRESCALER_512    =((uint8_t)0x09),
00065     TIM5_PRESCALER_1024   =((uint8_t)0x0A),
00066     TIM5_PRESCALER_2048   =((uint8_t)0x0B),
00067     TIM5_PRESCALER_4096   =((uint8_t)0x0C),
00068     TIM5_PRESCALER_8192   =((uint8_t)0x0D),
00069     TIM5_PRESCALER_16384  =((uint8_t)0x0E),
00070     TIM5_PRESCALER_32768  =((uint8_t)0x0F)
00071 }TIM5_Prescaler_TypeDef;
00072
00073 #define IS_TIM5_PRESCALER_OK(PRESCALER) (((PRESCALER) == TIM5_PRESCALER_1) || \
00074                  ((PRESCALER) == TIM5_PRESCALER_2     ) || \
00075                  ((PRESCALER) == TIM5_PRESCALER_4     ) || \
00076                  ((PRESCALER) == TIM5_PRESCALER_8    ) || \
00077                  ((PRESCALER) == TIM5_PRESCALER_16    ) || \
00078                  ((PRESCALER) == TIM5_PRESCALER_32      ) || \
00079                  ((PRESCALER) == TIM5_PRESCALER_64     ) || \
00080                  ((PRESCALER) == TIM5_PRESCALER_128    ) || \
00081                  ((PRESCALER) == TIM5_PRESCALER_256    ) || \
00082                  ((PRESCALER) == TIM5_PRESCALER_512    ) || \
00083                  ((PRESCALER) == TIM5_PRESCALER_1024   ) || \
00084                  ((PRESCALER) == TIM5_PRESCALER_2048  ) || \
00085                  ((PRESCALER) == TIM5_PRESCALER_4096  ) || \
00086                  ((PRESCALER) == TIM5_PRESCALER_8192  ) || \
00087                  ((PRESCALER) == TIM5_PRESCALER_16384  ) || \
00088                  ((PRESCALER) == TIM5_PRESCALER_32768  ))
00089
00090 /** TIM5 Output Compare and PWM modes */
00091 typedef enum
00092 {
00093     TIM5_OCMODE_TIMING     =((uint8_t)0x00),
00094     TIM5_OCMODE_ACTIVE     =((uint8_t)0x10),
00095     TIM5_OCMODE_INACTIVE   =((uint8_t)0x20),
00096     TIM5_OCMODE_TOGGLE     =((uint8_t)0x30),
00097     TIM5_OCMODE_PWM1       =((uint8_t)0x60),
00098     TIM5_OCMODE_PWM2       =((uint8_t)0x70)
00099 }TIM5_OCMode_TypeDef;
00100
00101 #define IS_TIM5_OC_MODE_OK(MODE) (((MODE) ==  TIM5_OCMODE_TIMING) || \
00102                                   ((MODE) == TIM5_OCMODE_ACTIVE) || \
00103                                   ((MODE) == TIM5_OCMODE_INACTIVE) || \
00104                                   ((MODE) == TIM5_OCMODE_TOGGLE)|| \
00105                                   ((MODE) == TIM5_OCMODE_PWM1) || \
00106                                   ((MODE) == TIM5_OCMODE_PWM2))
00107
00108 #define IS_TIM5_OCM_OK(MODE)(((MODE) ==  TIM5_OCMODE_TIMING) || \
00109                              ((MODE) == TIM5_OCMODE_ACTIVE) || \
00110                              ((MODE) == TIM5_OCMODE_INACTIVE) || \
00111                              ((MODE) == TIM5_OCMODE_TOGGLE)|| \
00112                              ((MODE) == TIM5_OCMODE_PWM1) || \
00113                              ((MODE) == TIM5_OCMODE_PWM2) ||  \
00114                              ((MODE) == (uint8_t)TIM5_FORCEDACTION_ACTIVE) || \
00115                              ((MODE) == (uint8_t)TIM5_FORCEDACTION_INACTIVE))
00116
00117 /** TIM5 One Pulse Mode */
00118 typedef enum
00119 {
00120     TIM5_OPMODE_SINGLE                 =((uint8_t)0x01),
00121     TIM5_OPMODE_REPETITIVE             =((uint8_t)0x00)
00122 }TIM5_OPMode_TypeDef;
00123
00124 #define IS_TIM5_OPM_MODE_OK(MODE) (((MODE) == TIM5_OPMODE_SINGLE) || \
00125                                    ((MODE) == TIM5_OPMODE_REPETITIVE))
00126
00127 /** TIM5 Channel */
00128 typedef enum
00129 {
00130     TIM5_CHANNEL_1                     =((uint8_t)0x00),
00131     TIM5_CHANNEL_2                     =((uint8_t)0x01),
00132     TIM5_CHANNEL_3                     =((uint8_t)0x02)
00133 }TIM5_Channel_TypeDef;
00134
00135 #define IS_TIM5_CHANNEL_OK(CHANNEL) (((CHANNEL) == TIM5_CHANNEL_1) || \
00136                                      ((CHANNEL) == TIM5_CHANNEL_2) || \
00137                                      ((CHANNEL) == TIM5_CHANNEL_3))
00138
00139 #define IS_TIM5_PWMI_CHANNEL_OK(CHANNEL) (((CHANNEL) == TIM5_CHANNEL_1) || \
00140                                           ((CHANNEL) == TIM5_CHANNEL_2))
00141
00142 /** TIM5 Output Compare Polarity */
00143 typedef enum
00144 {
00145     TIM5_OCPOLARITY_HIGH               =((uint8_t)0x00),
00146     TIM5_OCPOLARITY_LOW                =((uint8_t)0x22)
00147 }TIM5_OCPolarity_TypeDef;
00148
00149 #define IS_TIM5_OC_POLARITY_OK(POLARITY) (((POLARITY) == TIM5_OCPOLARITY_HIGH) || \
00150                                        ((POLARITY) == TIM5_OCPOLARITY_LOW))
00151
00152 /** TIM5 Output Compare states */
00153 typedef enum
00154 {
00155     TIM5_OUTPUTSTATE_DISABLE           =((uint8_t)0x00),
00156     TIM5_OUTPUTSTATE_ENABLE            =((uint8_t)0x11)
00157 }TIM5_OutputState_TypeDef;
00158
00159 #define IS_TIM5_OUTPUT_STATE_OK(STATE) (((STATE) == TIM5_OUTPUTSTATE_DISABLE) || \
00160                                      ((STATE) == TIM5_OUTPUTSTATE_ENABLE))
00161
00162 /** TIM5 Input Capture Polarity */
00163 typedef enum
00164 {
00165     TIM5_ICPOLARITY_RISING            =((uint8_t)0x00),
00166     TIM5_ICPOLARITY_FALLING           =((uint8_t)0x44)
00167 }TIM5_ICPolarity_TypeDef;
00168
00169 #define IS_TIM5_IC_POLARITY_OK(POLARITY) (((POLARITY) == TIM5_ICPOLARITY_RISING) || \
00170                                        ((POLARITY) == TIM5_ICPOLARITY_FALLING))
00171
00172 /** TIM5 Input Capture Selection */
00173 typedef enum
00174 {
00175     TIM5_ICSELECTION_DIRECTTI          =((uint8_t)0x01),
00176     TIM5_ICSELECTION_INDIRECTTI        =((uint8_t)0x02),
00177     TIM5_ICSELECTION_TRGI              =((uint8_t)0x03)
00178 }TIM5_ICSelection_TypeDef;
00179
00180 #define IS_TIM5_IC_SELECTION_OK(SELECTION) (((SELECTION) == TIM5_ICSELECTION_DIRECTTI) || \
00181                                            ((SELECTION) == TIM5_ICSELECTION_INDIRECTTI) || \
00182                                            ((SELECTION) == TIM5_ICSELECTION_TRGI))
00183
00184 #define IS_TIM5_IC_SELECTION1_OK(SELECTION) (((SELECTION) == TIM5_ICSELECTION_DIRECTTI) || \
00185                                              ((SELECTION) == TIM5_ICSELECTION_TRGI))
00186
00187 /** TIM5 Input Capture Prescaler */
00188 typedef enum
00189 {
00190     TIM5_ICPSC_DIV1                    =((uint8_t)0x00),
00191     TIM5_ICPSC_DIV2                    =((uint8_t)0x04),
00192     TIM5_ICPSC_DIV4                    =((uint8_t)0x08),
00193     TIM5_ICPSC_DIV8                    =((uint8_t)0x0C)
00194 }TIM5_ICPSC_TypeDef;
00195
00196 #define IS_TIM5_IC_PRESCALER_OK(PRESCALER) (((PRESCALER) == TIM5_ICPSC_DIV1) || \
00197                                          ((PRESCALER) == TIM5_ICPSC_DIV2) || \
00198                                          ((PRESCALER) == TIM5_ICPSC_DIV4) || \
00199                                          ((PRESCALER) == TIM5_ICPSC_DIV8))
00200
00201 /** TIM5 Input Capture Filer Value */
00202 #define IS_TIM5_IC_FILTER_OK(ICFILTER) ((ICFILTER) <= 0x0F)
00203
00204 /** TIM5 interrupt sources */
00205 typedef enum
00206 {
00207     TIM5_IT_UPDATE                     =((uint8_t)0x01),
00208     TIM5_IT_CC1                        =((uint8_t)0x02),
00209     TIM5_IT_CC2                        =((uint8_t)0x04),
00210     TIM5_IT_CC3                        =((uint8_t)0x08),
00211     TIM5_IT_TRIGGER                    = ((uint8_t)0x40)
00212 }TIM5_IT_TypeDef;
00213
00214 #define IS_TIM5_IT_OK(IT) (((IT) != 0x00) && ((IT) <= 0x4F))
00215
00216 #define IS_TIM5_GET_IT_OK(IT) (((IT) == TIM5_IT_UPDATE) || \
00217                             ((IT) == TIM5_IT_CC1) || \
00218                             ((IT) == TIM5_IT_CC2) || \
00219                             ((IT) == TIM5_IT_CC3) || \
00220                             ((IT) == TIM5_IT_TRIGGER))
00221
00222 /** TIM5 Prescaler Reload Mode */
00223 typedef enum
00224 {
00225     TIM5_PSCRELOADMODE_UPDATE          =((uint8_t)0x00),
00226     TIM5_PSCRELOADMODE_IMMEDIATE       =((uint8_t)0x01)
00227 }TIM5_PSCReloadMode_TypeDef;
00228
00229 #define IS_TIM5_PRESCALER_RELOAD_OK(RELOAD) (((RELOAD) == TIM5_PSCRELOADMODE_UPDATE) || \
00230                                           ((RELOAD) == TIM5_PSCRELOADMODE_IMMEDIATE))
00231
00232 /** TIM5 Event Source */
00233 typedef enum
00234 {
00235     TIM5_EVENTSOURCE_UPDATE            =((uint8_t)0x01),
00236     TIM5_EVENTSOURCE_CC1               =((uint8_t)0x02),
00237     TIM5_EVENTSOURCE_CC2               =((uint8_t)0x04),
00238     TIM5_EVENTSOURCE_CC3               =((uint8_t)0x08),
00239     TIM5_EVENTSOURCE_TRIGGER           = ((uint8_t)0x40)
00240 }TIM5_EventSource_TypeDef;
00241
00242 #define IS_TIM5_EVENT_SOURCE_OK(SOURCE) (((SOURCE) != 0x00))
00243
00244 /** TIM5 Update Source */
00245 typedef enum
00246 {
00247     TIM5_UPDATESOURCE_GLOBAL           =((uint8_t)0x00),
00248     TIM5_UPDATESOURCE_REGULAR          =((uint8_t)0x01)
00249 }TIM5_UpdateSource_TypeDef;
00250
00251
00252 #define IS_TIM5_UPDATE_SOURCE_OK(SOURCE) (((SOURCE) == TIM5_UPDATESOURCE_GLOBAL) || \
00253                                        ((SOURCE) == TIM5_UPDATESOURCE_REGULAR))
00254
00255 /**
00256   * @brief  TIM5 Trigger Output Source
00257   */
00258 typedef enum
00259 {
00260     TIM5_TRGOSOURCE_RESET   = ((uint8_t)0x00),   /*!< Trigger Output source = Reset*/
00261     TIM5_TRGOSOURCE_ENABLE  = ((uint8_t)0x10),   /*!< Trigger Output source = TIM5 is enabled*/
00262     TIM5_TRGOSOURCE_UPDATE  = ((uint8_t)0x20),   /*!< Trigger Output source = Update event*/
00263     TIM5_TRGOSOURCE_OC1     = ((uint8_t)0x30),   /*!< Trigger Output source = output compare channel1  */
00264     TIM5_TRGOSOURCE_OC1REF  = ((uint8_t)0x40),   /*!< Trigger Output source = output compare channel 1 reference */
00265     TIM5_TRGOSOURCE_OC2REF  = ((uint8_t)0x50)    /*!< Trigger Output source = output compare channel 2 reference */
00266 }TIM5_TRGOSource_TypeDef;
00267
00268 /**
00269   * @brief  Macro TIM5 TRGO source
00270   */
00271 #define IS_TIM5_TRGO_SOURCE_OK(SOURCE) \
00272    (((SOURCE) == TIM5_TRGOSOURCE_RESET)  || \
00273     ((SOURCE) == TIM5_TRGOSOURCE_ENABLE) || \
00274     ((SOURCE) == TIM5_TRGOSOURCE_UPDATE) || \
00275     ((SOURCE) == TIM5_TRGOSOURCE_OC1)    || \
00276     ((SOURCE) == TIM5_TRGOSOURCE_OC1REF) || \
00277     ((SOURCE) == TIM5_TRGOSOURCE_OC2REF))
00278
00279 /** TIM5 Flags */
00280 typedef enum
00281 {
00282     TIM5_FLAG_UPDATE                   =((uint16_t)0x0001),
00283     TIM5_FLAG_CC1                      =((uint16_t)0x0002),
00284     TIM5_FLAG_CC2                      =((uint16_t)0x0004),
00285     TIM5_FLAG_CC3                      =((uint16_t)0x0008),
00286     TIM5_FLAG_TRIGGER                  = ((uint16_t)0x0040),
00287     TIM5_FLAG_CC1OF                    =((uint16_t)0x0200),
00288     TIM5_FLAG_CC2OF                    =((uint16_t)0x0400),
00289     TIM5_FLAG_CC3OF                    =((uint16_t)0x0800)
00290 }TIM5_FLAG_TypeDef;
00291
00292 #define IS_TIM5_GET_FLAG_OK(FLAG) (((FLAG) == TIM5_FLAG_UPDATE) || \
00293                                 ((FLAG) == TIM5_FLAG_CC1) || \
00294                                 ((FLAG) == TIM5_FLAG_CC2) || \
00295                                 ((FLAG) == TIM5_FLAG_CC3) || \
00296                                 ((FLAG) == TIM5_FLAG_TRIGGER) || \
00297                                 ((FLAG) == TIM5_FLAG_CC1OF) || \
00298                                 ((FLAG) == TIM5_FLAG_CC2OF) || \
00299                                 ((FLAG) == TIM5_FLAG_CC3OF))
00300
00301 #define IS_TIM5_CLEAR_FLAG_OK(FLAG) ((((uint16_t)(FLAG) & 0xF1F0) == 0x0000) && ((uint16_t)(FLAG) != 0x0000))
00302
00303
00304 /**
00305   * @brief  TIM5 Slave Mode
00306   */
00307 typedef enum
00308 {
00309     TIM5_SLAVEMODE_RESET      = ((uint8_t)0x04),   /*!< Slave Mode Selection  = Reset*/
00310     TIM5_SLAVEMODE_GATED      = ((uint8_t)0x05),   /*!< Slave Mode Selection  = Gated*/
00311     TIM5_SLAVEMODE_TRIGGER    = ((uint8_t)0x06),   /*!< Slave Mode Selection  = Trigger*/
00312     TIM5_SLAVEMODE_EXTERNAL1  = ((uint8_t)0x07)  /*!< Slave Mode Selection  = External 1*/
00313 }TIM5_SlaveMode_TypeDef;
00314
00315 /**
00316   * @brief  Macro TIM5 Slave mode
00317   */
00318 #define IS_TIM5_SLAVE_MODE_OK(MODE) \
00319    (((MODE) == TIM5_SLAVEMODE_RESET)   || \
00320     ((MODE) == TIM5_SLAVEMODE_GATED)   || \
00321     ((MODE) == TIM5_SLAVEMODE_TRIGGER) || \
00322     ((MODE) == TIM5_SLAVEMODE_EXTERNAL1))
00323
00324 /**
00325   * @brief  TIM5 Internal Trigger Selection
00326   */
00327 typedef enum
00328 {
00329     TIM5_TS_TIM6  = ((uint8_t)0x00), /*!< TRIG Input source =  TIM6 TRIG Output  */
00330     TIM5_TS_TIM1  = ((uint8_t)0x03) /*!< TRIG Input source =  TIM1 TRIG Output  */
00331 }TIM5_TS_TypeDef;
00332
00333 /**
00334   * @brief  Macro TIM5  Trigger Selection
00335   */
00336 #define IS_TIM5_TRIGGER_SELECTION_OK(SELECTION) \
00337    (((SELECTION) == TIM5_TS_TIM6)  || \
00338     ((SELECTION) == TIM5_TS_TIM1)  )
00339
00340
00341 #define IS_TIM5_TIX_TRIGGER_SELECTION_OK(SELECTION) \
00342    (((SELECTION) == TIM5_TS_TI1F_ED) || \
00343     ((SELECTION) == TIM5_TS_TI1FP1)  || \
00344     ((SELECTION) == TIM5_TS_TI2FP2))
00345
00346
00347 /**
00348   * @brief  TIM5 Encoder Mode
00349   */
00350 typedef enum
00351 {
00352     TIM5_ENCODERMODE_TI1    = ((uint8_t)0x01),   /*!< Encoder mode 1*/
00353     TIM5_ENCODERMODE_TI2    = ((uint8_t)0x02),   /*!< Encoder mode 2*/
00354     TIM5_ENCODERMODE_TI12   = ((uint8_t)0x03)    /*!< Encoder mode 3*/
00355 }TIM5_EncoderMode_TypeDef;
00356 /**
00357   * @brief  Macro TIM5 encoder mode
00358   */
00359 #define IS_TIM5_ENCODER_MODE_OK(MODE) \
00360    (((MODE) == TIM5_ENCODERMODE_TI1) || \
00361     ((MODE) == TIM5_ENCODERMODE_TI2) || \
00362     ((MODE) == TIM5_ENCODERMODE_TI12))
00363
00364 /**
00365   * @brief  TIM5 External Trigger Prescaler
00366   */
00367 typedef enum
00368 {
00369     TIM5_EXTTRGPSC_OFF   = ((uint8_t)0x00),   /*!< No External Trigger prescaler  */
00370     TIM5_EXTTRGPSC_DIV2  = ((uint8_t)0x10),   /*!< External Trigger prescaler = 2 (ETRP frequency divided by 2) */
00371     TIM5_EXTTRGPSC_DIV4  = ((uint8_t)0x20),   /*!< External Trigger prescaler = 4 (ETRP frequency divided by 4) */
00372     TIM5_EXTTRGPSC_DIV8  = ((uint8_t)0x30)    /*!< External Trigger prescaler = 8 (ETRP frequency divided by 8) */
00373 }TIM5_ExtTRGPSC_TypeDef;
00374
00375 /**
00376   * @brief  Macro TIM5 external trigger prescaler
00377   */
00378 #define IS_TIM5_EXT_PRESCALER_OK(PRESCALER) \
00379    (((PRESCALER) == TIM5_EXTTRGPSC_OFF)  || \
00380     ((PRESCALER) == TIM5_EXTTRGPSC_DIV2) || \
00381     ((PRESCALER) == TIM5_EXTTRGPSC_DIV4) || \
00382     ((PRESCALER) == TIM5_EXTTRGPSC_DIV8))
00383
00384 /**
00385   * @brief  TIM5 External Trigger Polarity
00386   */
00387 typedef enum
00388 {
00389     TIM5_EXTTRGPOLARITY_INVERTED    = ((uint8_t)0x80),   /*!< External Trigger Polarity = inverted */
00390     TIM5_EXTTRGPOLARITY_NONINVERTED  = ((uint8_t)0x00)    /*!< External Trigger Polarity = non inverted */
00391 }TIM5_ExtTRGPolarity_TypeDef;
00392
00393 /**
00394   * @brief  Macro TIM5  Trigger Polarity
00395   */
00396 #define IS_TIM5_EXT_POLARITY_OK(POLARITY) \
00397    (((POLARITY) == TIM5_EXTTRGPOLARITY_INVERTED) || \
00398     ((POLARITY) == TIM5_EXTTRGPOLARITY_NONINVERTED))
00399
00400 /**
00401   * @brief  Macro TIM5 External Trigger Filter
00402   */
00403 #define IS_TIM5_EXT_FILTER_OK(EXTFILTER) ((EXTFILTER) <= 0x0F)
00404 /**
00405   * @}
00406   */
00407
00408 /* Exported macro ------------------------------------------------------------*/
00409
00410 /* Exported functions --------------------------------------------------------*/
00411
00412 /** @addtogroup TIM5_Exported_Functions
00413   * @{
00414   */
00415
00416 void TIM5_DeInit(void);
00417 void TIM5_TimeBaseInit(TIM5_Prescaler_TypeDef TIM5_Prescaler, uint16_t TIM5_Period);
00418 void TIM5_OC1Init(TIM5_OCMode_TypeDef TIM5_OCMode, TIM5_OutputState_TypeDef TIM5_OutputState,uint16_t TIM5_Pulse, TIM5_OCPolarity_TypeDef TIM5_OCPolarity);
00419 void TIM5_OC2Init(TIM5_OCMode_TypeDef TIM5_OCMode, TIM5_OutputState_TypeDef TIM5_OutputState,uint16_t TIM5_Pulse, TIM5_OCPolarity_TypeDef TIM5_OCPolarity);
00420 void TIM5_OC3Init(TIM5_OCMode_TypeDef TIM5_OCMode, TIM5_OutputState_TypeDef TIM5_OutputState,uint16_t TIM5_Pulse, TIM5_OCPolarity_TypeDef TIM5_OCPolarity);
00421 void TIM5_ICInit(TIM5_Channel_TypeDef TIM5_Channel, TIM5_ICPolarity_TypeDef TIM5_ICPolarity, TIM5_ICSelection_TypeDef TIM5_ICSelection,  TIM5_ICPSC_TypeDef TIM5_ICPrescaler, uint8_t TIM5_ICFilter);
00422 void TIM5_PWMIConfig(TIM5_Channel_TypeDef TIM5_Channel, TIM5_ICPolarity_TypeDef TIM5_ICPolarity, TIM5_ICSelection_TypeDef TIM5_ICSelection,  TIM5_ICPSC_TypeDef TIM5_ICPrescaler, uint8_t TIM5_ICFilter);
00423 void TIM5_Cmd(FunctionalState NewState);
00424 void TIM5_ITConfig(TIM5_IT_TypeDef TIM5_IT, FunctionalState NewState);
00425 void TIM5_InternalClockConfig(void);
00426 void TIM5_UpdateDisableConfig(FunctionalState NewState);
00427 void TIM5_UpdateRequestConfig(TIM5_UpdateSource_TypeDef TIM5_UpdateSource);
00428 void TIM5_SelectOnePulseMode(TIM5_OPMode_TypeDef TIM5_OPMode);
00429 void TIM5_PrescalerConfig(TIM5_Prescaler_TypeDef Prescaler, TIM5_PSCReloadMode_TypeDef TIM5_PSCReloadMode);
00430 void TIM5_SelectOutputTrigger(TIM5_TRGOSource_TypeDef TIM5_TRGOSource);
00431 void TIM5_ForcedOC1Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction);
00432 void TIM5_ForcedOC2Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction);
00433 void TIM5_ForcedOC3Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction);
00434 void TIM5_ARRPreloadConfig(FunctionalState NewState);
00435 void TIM5_CCPreloadControl(FunctionalState NewState);
00436 void TIM5_OC1PreloadConfig(FunctionalState NewState);
00437 void TIM5_OC2PreloadConfig(FunctionalState NewState);
00438 void TIM5_OC3PreloadConfig(FunctionalState NewState);
00439 void TIM5_GenerateEvent(TIM5_EventSource_TypeDef TIM5_EventSource);
00440 void TIM5_OC1PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity);
00441 void TIM5_OC2PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity);
00442 void TIM5_OC3PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity);
00443 void TIM5_CCxCmd(TIM5_Channel_TypeDef TIM5_Channel, FunctionalState NewState);
00444 void TIM5_SelectOCxM(TIM5_Channel_TypeDef TIM5_Channel, TIM5_OCMode_TypeDef TIM5_OCMode);
00445 void TIM5_SetCounter(uint16_t Counter);
00446 void TIM5_SetAutoreload(uint16_t Autoreload);
00447 void TIM5_SetCompare1(uint16_t Compare1);
00448 void TIM5_SetCompare2(uint16_t Compare2);
00449 void TIM5_SetCompare3(uint16_t Compare3);
00450 void TIM5_SetIC1Prescaler(TIM5_ICPSC_TypeDef TIM5_IC1Prescaler);
00451 void TIM5_SetIC2Prescaler(TIM5_ICPSC_TypeDef TIM5_IC2Prescaler);
00452 void TIM5_SetIC3Prescaler(TIM5_ICPSC_TypeDef TIM5_IC3Prescaler);
00453 uint16_t TIM5_GetCapture1(void);
00454 uint16_t TIM5_GetCapture2(void);
00455 uint16_t TIM5_GetCapture3(void);
00456 uint16_t TIM5_GetCounter(void);
00457 TIM5_Prescaler_TypeDef TIM5_GetPrescaler(void);
00458 FlagStatus TIM5_GetFlagStatus(TIM5_FLAG_TypeDef TIM5_FLAG);
00459 void TIM5_ClearFlag(TIM5_FLAG_TypeDef TIM5_FLAG);
00460 ITStatus TIM5_GetITStatus(TIM5_IT_TypeDef TIM5_IT);
00461 void TIM5_ClearITPendingBit(TIM5_IT_TypeDef TIM5_IT);
00462 void TIM5_SelectInputTrigger(TIM5_TS_TypeDef TIM5_InputTriggerSource);
00463 void TIM5_SelectSlaveMode(TIM5_SlaveMode_TypeDef TIM5_SlaveMode);
00464 void TIM5_EncoderInterfaceConfig(TIM5_EncoderMode_TypeDef TIM5_EncoderMode, TIM5_ICPolarity_TypeDef TIM5_IC1Polarity,TIM5_ICPolarity_TypeDef TIM5_IC2Polarity);
00465
00466
00467 /**
00468   * @}
00469   */
00470
00471 #endif /* __STM8S_TIM5_H */
00472
00473 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_tim6.c Source File

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  • STM8S_StdPeriph_Driver
  • src
stm8s_tim6.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_tim6.c
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all the functions for the TIM6 peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028
00029 /* Includes ------------------------------------------------------------------*/
00030 #include "stm8s_tim6.h"
00031
00032 /** @addtogroup STM8S_StdPeriph_Driver
00033   * @{
00034   */
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private typedef -----------------------------------------------------------*/
00038 /* Private define ------------------------------------------------------------*/
00039 /* Private macro -------------------------------------------------------------*/
00040 /* Private variables ---------------------------------------------------------*/
00041 /* Private function prototypes -----------------------------------------------*/
00042 /**
00043   * @addtogroup TIM6_Public_Functions
00044   * @{
00045   */
00046
00047 /**
00048   * @brief  Deinitializes the TIM6 peripheral registers to their default reset values.
00049   * @param  None
00050   * @retval None
00051   */
00052 void TIM6_DeInit(void)
00053 {
00054   TIM6->CR1     = TIM6_CR1_RESET_VALUE;
00055   TIM6->CR2     = TIM6_CR2_RESET_VALUE;
00056   TIM6->SMCR    = TIM6_SMCR_RESET_VALUE;
00057   TIM6->IER     = TIM6_IER_RESET_VALUE;
00058   TIM6->CNTR    = TIM6_CNTR_RESET_VALUE;
00059   TIM6->PSCR    = TIM6_PSCR_RESET_VALUE;
00060   TIM6->ARR     = TIM6_ARR_RESET_VALUE;
00061   TIM6->SR1     = TIM6_SR1_RESET_VALUE;
00062 }
00063
00064 /**
00065   * @brief  Initializes the TIM6 Time Base Unit according to the specified
00066   * parameters.
00067   * @param   TIM6_Prescaler : This parameter can be any of the @ref TIM6_Prescaler_TypeDef enumeration.
00068   * @param   TIM6_Period : This parameter must be a value between 0x00 and 0xFF.
00069   * @retval None
00070   */
00071 void TIM6_TimeBaseInit(TIM6_Prescaler_TypeDef TIM6_Prescaler,
00072                        uint8_t TIM6_Period)
00073 {
00074   /* Check TIM6 prescaler value */
00075   assert_param(IS_TIM6_PRESCALER_OK(TIM6_Prescaler));
00076   /* Set the Autoreload value */
00077   TIM6->ARR = (uint8_t)(TIM6_Period);
00078   /* Set the Prescaler value */
00079   TIM6->PSCR = (uint8_t)(TIM6_Prescaler);
00080 }
00081
00082 /**
00083   * @brief  Enables or disables the TIM6 peripheral.
00084   * @param   NewState : The new state of the TIM6 peripheral.
00085   * This parameter can be any of the @ref FunctionalState enumeration.
00086   * @retval None
00087   */
00088 void TIM6_Cmd(FunctionalState NewState)
00089 {
00090   /* Check the parameters */
00091   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00092
00093   /* set or Reset the CEN Bit */
00094   if (NewState == ENABLE)
00095   {
00096     TIM6->CR1 |= TIM6_CR1_CEN ;
00097   }
00098   else
00099   {
00100     TIM6->CR1 &= (uint8_t)(~TIM6_CR1_CEN) ;
00101   }
00102 }
00103
00104 /**
00105   * @brief  Enables or Disables the TIM6 Update event.
00106   * @param   NewState : The new state of the TIM6 peripheral Preload register.
00107   * This parameter can be any of the @ref FunctionalState enumeration.
00108   * @retval None
00109   */
00110 void TIM6_UpdateDisableConfig(FunctionalState NewState)
00111 {
00112   /* Check the parameters */
00113   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00114
00115   /* Set or Reset the UDIS Bit */
00116   if (NewState == ENABLE)
00117   {
00118     TIM6->CR1 |= TIM6_CR1_UDIS ;
00119   }
00120   else
00121   {
00122     TIM6->CR1 &= (uint8_t)(~TIM6_CR1_UDIS) ;
00123   }
00124 }
00125
00126 /**
00127   * @brief  Selects the TIM6 Update Request Interrupt source.
00128   * @param   TIM6_UpdateSource : Specifies the Update source.
00129   * This parameter can be one of the @ref TIM6_UpdateSource_TypeDef enumeration.
00130   * @retval None
00131   */
00132 void TIM6_UpdateRequestConfig(TIM6_UpdateSource_TypeDef TIM6_UpdateSource)
00133 {
00134   /* Check the parameters */
00135   assert_param(IS_TIM6_UPDATE_SOURCE_OK(TIM6_UpdateSource));
00136
00137   /* Set or Reset the URS Bit */
00138   if (TIM6_UpdateSource == TIM6_UPDATESOURCE_REGULAR)
00139   {
00140     TIM6->CR1 |= TIM6_CR1_URS ;
00141   }
00142   else
00143   {
00144     TIM6->CR1 &= (uint8_t)(~TIM6_CR1_URS) ;
00145   }
00146 }
00147
00148 /**
00149   * @brief  Selects the TIM6’s One Pulse Mode.
00150   * @param   TIM6_OPMode : Specifies the OPM Mode to be used.
00151   * This parameter can be one of the @ref TIM6_OPMode_TypeDef enumeration.
00152   * @retval None
00153   */
00154 void TIM6_SelectOnePulseMode(TIM6_OPMode_TypeDef TIM6_OPMode)
00155 {
00156   /* Check the parameters */
00157   assert_param(IS_TIM6_OPM_MODE_OK(TIM6_OPMode));
00158
00159   /* Set or Reset the OPM Bit */
00160   if (TIM6_OPMode == TIM6_OPMODE_SINGLE)
00161   {
00162     TIM6->CR1 |= TIM6_CR1_OPM ;
00163   }
00164   else
00165   {
00166     TIM6->CR1 &= (uint8_t)(~TIM6_CR1_OPM) ;
00167   }
00168 }
00169
00170 /**
00171   * @brief  Configures the TIM6 Prescaler.
00172   * @param   Prescaler : Specifies the Prescaler Register value
00173   * This parameter can be one of the @ref TIM6_Prescaler_TypeDef enumeration.
00174   * @param   TIM6_PSCReloadMode : Specifies the TIM6 Prescaler Reload mode.
00175   * This parameter can be one of the @ref TIM6_PSCReloadMode_TypeDef enumeration.
00176   * @retval None
00177   */
00178 void TIM6_PrescalerConfig(TIM6_Prescaler_TypeDef Prescaler,
00179                           TIM6_PSCReloadMode_TypeDef TIM6_PSCReloadMode)
00180 {
00181   /* Check the parameters */
00182   assert_param(IS_TIM6_PRESCALER_RELOAD_OK(TIM6_PSCReloadMode));
00183   assert_param(IS_TIM6_PRESCALER_OK(Prescaler));
00184
00185   /* Set the Prescaler value */
00186   TIM6->PSCR = (uint8_t)Prescaler;
00187
00188   /* Set or reset the UG Bit */
00189   if (TIM6_PSCReloadMode == TIM6_PSCRELOADMODE_IMMEDIATE)
00190   {
00191     TIM6->EGR |= TIM6_EGR_UG ;
00192   }
00193   else
00194   {
00195     TIM6->EGR &= (uint8_t)(~TIM6_EGR_UG) ;
00196   }
00197 }
00198
00199 /**
00200   * @brief  Enables or disables TIM6 peripheral Preload register on ARR.
00201   * @param   NewState : The new state of the TIM6 peripheral Preload register.
00202   * This parameter can be any of the @ref FunctionalState enumeration.
00203   * @retval None
00204   */
00205 void TIM6_ARRPreloadConfig(FunctionalState NewState)
00206 {
00207   /* Check the parameters */
00208   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00209
00210   /* Set or Reset the ARPE Bit */
00211   if (NewState == ENABLE)
00212   {
00213     TIM6->CR1 |= TIM6_CR1_ARPE ;
00214   }
00215   else
00216   {
00217     TIM6->CR1 &= (uint8_t)(~TIM6_CR1_ARPE) ;
00218   }
00219 }
00220
00221 /**
00222   * @brief  Sets the TIM6 Counter Register value.
00223   * @param   Counter : Specifies the Counter register new value.
00224   * This parameter is between 0x00 and 0xFF.
00225   * @retval None
00226   */
00227 void TIM6_SetCounter(uint8_t Counter)
00228 {
00229   /* Set the Counter Register value */
00230   TIM6->CNTR = (uint8_t)(Counter);
00231 }
00232
00233 /**
00234   * @brief  Sets the TIM6 Autoreload Register value.
00235   * @param   Autoreload : Specifies the Autoreload register new value.
00236   * This parameter is between 0x00 and 0xFF.
00237   * @retval None
00238   */
00239 void TIM6_SetAutoreload(uint8_t Autoreload)
00240 {
00241   /* Set the Autoreload Register value */
00242   TIM6->ARR = (uint8_t)(Autoreload);
00243 }
00244
00245 /**
00246   * @brief  Gets the TIM6 Counter value.
00247   * @param  None
00248   * @retval uint8_t: Counter Register value.
00249   */
00250 uint8_t TIM6_GetCounter(void)
00251 {
00252   uint8_t tmpcntr=0;
00253   tmpcntr = TIM6->CNTR;
00254   /* Get the Counter Register value */
00255   return ((uint8_t)tmpcntr);
00256 }
00257
00258 /**
00259   * @brief  Gets the TIM6 Prescaler value.
00260   * @param  None
00261   * @retval TIM6_Prescaler_TypeDef : Prescaler Register configuration value.
00262   */
00263 TIM6_Prescaler_TypeDef TIM6_GetPrescaler(void)
00264 {
00265   /* Get the Prescaler Register value */
00266   return ((TIM6_Prescaler_TypeDef)TIM6->PSCR);
00267 }
00268
00269 /**
00270   * @brief  Enables or disables the specified TIM6 interrupts.
00271   * @param   TIM6_IT : Specifies the TIM6 interrupts sources to be enabled or disabled.
00272   * This parameter can be any combination of the @ref TIM6_IT_TypeDef enumeration.
00273   * @param   NewState : The new state of the TIM6 peripheral.
00274   * This parameter can be any of the @ref FunctionalState enumeration.
00275   * @retval None
00276   * @par Required preconditions:
00277   * If QST option bit is enabled, the TIM6 Interrupt vector will be mapped on IRQ number 2 (irq0).
00278   * Otherwise, it will be mapped on IRQ number 27 (irq25).
00279   */
00280 void TIM6_ITConfig(TIM6_IT_TypeDef TIM6_IT, FunctionalState NewState)
00281 {
00282   /* Check the parameters */
00283   assert_param(IS_TIM6_IT_OK(TIM6_IT));
00284   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00285
00286   if (NewState == ENABLE)
00287   {
00288     /* Enable the Interrupt sources */
00289     TIM6->IER |= (uint8_t)TIM6_IT;
00290   }
00291   else
00292   {
00293     /* Disable the Interrupt sources */
00294     TIM6->IER &= (uint8_t)(~(uint8_t)TIM6_IT);
00295   }
00296 }
00297
00298 /**
00299   * @brief  Clears the TIM’s pending flags.
00300   * @param   TIM6_FLAG : Specifies the flag to clear.
00301   * This parameter can be one of the @ref TIM6_FLAG_TypeDef enumeration.
00302   * @retval None
00303   */
00304 void TIM6_ClearFlag(TIM6_FLAG_TypeDef TIM6_FLAG)
00305 {
00306   /* Check the parameters */
00307   assert_param(IS_TIM6_CLEAR_FLAG_OK((uint8_t)TIM6_FLAG));
00308   /* Clear the flags (rc_w0) clear this bit by writing 0. Writing ‘1’ has no effect*/
00309   TIM6->SR1 &= (uint8_t)(~((uint8_t)TIM6_FLAG));
00310 }
00311
00312 /**
00313   * @brief  Checks whether the TIM6 interrupt has occurred or not.
00314   * @param   TIM6_IT : Specifies the TIM6 interrupt source to check.
00315   * This parameter can be one of the @ref TIM6_IT_TypeDef enumeration.
00316   * @retval ITStatus : The new state of the TIM6_IT.
00317   * This parameter can be any of the @ref ITStatus enumeration.
00318   */
00319 ITStatus TIM6_GetITStatus(TIM6_IT_TypeDef TIM6_IT)
00320 {
00321   ITStatus bitstatus = RESET;
00322   uint8_t itStatus = 0, itEnable = 0;
00323
00324   /* Check the parameters */
00325   assert_param(IS_TIM6_GET_IT_OK(TIM6_IT));
00326
00327   itStatus = (uint8_t)(TIM6->SR1 & (uint8_t)TIM6_IT);
00328
00329   itEnable = (uint8_t)(TIM6->IER & (uint8_t)TIM6_IT);
00330
00331   if ((itStatus != (uint8_t)RESET ) && (itEnable != (uint8_t)RESET ))
00332   {
00333     bitstatus = (ITStatus)SET;
00334   }
00335   else
00336   {
00337     bitstatus = (ITStatus)RESET;
00338   }
00339   return ((ITStatus)bitstatus);
00340 }
00341
00342 /**
00343   * @brief  Configures the TIM6 event to be generated by software.
00344   * @param   TIM6_EventSource : Specifies the event source.
00345   * This parameter can be one of the @ref TIM6_EventSource_TypeDef enumeration.
00346   * @retval None
00347   */
00348 void TIM6_GenerateEvent(TIM6_EventSource_TypeDef TIM6_EventSource)
00349 {
00350   /* Check the parameters */
00351   assert_param(IS_TIM6_EVENT_SOURCE_OK((uint8_t)TIM6_EventSource));
00352
00353   /* Set the event sources */
00354   TIM6->EGR |= (uint8_t)TIM6_EventSource;
00355 }
00356
00357 /**
00358   * @brief  Checks whether the specified TIM6 flag is set or not.
00359   * @param   TIM6_FLAG : Specifies the flag to check.
00360   * This parameter can be one of the @ref TIM6_FLAG_TypeDef enumeration.
00361   * @retval FlagStatus : The new state of TIM6_FLAG.
00362   * This parameter can be any of the @ref FlagStatus enumeration.
00363   */
00364 FlagStatus TIM6_GetFlagStatus(TIM6_FLAG_TypeDef TIM6_FLAG)
00365 {
00366   volatile FlagStatus bitstatus = RESET;
00367
00368   /* Check the parameters */
00369   assert_param(IS_TIM6_GET_FLAG_OK(TIM6_FLAG));
00370
00371   if ((TIM6->SR1 & (uint8_t)TIM6_FLAG)  != 0)
00372   {
00373     bitstatus = SET;
00374   }
00375   else
00376   {
00377     bitstatus = RESET;
00378   }
00379   return ((FlagStatus)bitstatus);
00380 }
00381
00382 /**
00383   * @brief  Clears the TIM6's interrupt pending bits.
00384   * @param   TIM6_IT : Specifies the pending bit to clear.
00385   * This parameter can be one of the @ref TIM6_IT_TypeDef enumeration.
00386   * @retval None
00387   */
00388 void TIM6_ClearITPendingBit(TIM6_IT_TypeDef TIM6_IT)
00389 {
00390   /* Check the parameters */
00391   assert_param(IS_TIM6_IT_OK(TIM6_IT));
00392
00393   /* Clear the IT pending Bit */
00394   TIM6->SR1 &= (uint8_t)(~(uint8_t)TIM6_IT);
00395 }
00396
00397 /**
00398   * @brief  Selects the TIM6 Trigger Output Mode.
00399   * @param   TIM6_TRGOSource : Specifies the Trigger Output source.
00400   * This parameter can be one of the @ref TIM6_TRGOSource_TypeDef enumeration.
00401   * @retval None
00402   */
00403 void TIM6_SelectOutputTrigger(TIM6_TRGOSource_TypeDef TIM6_TRGOSource)
00404 {
00405   uint8_t tmpcr2 = 0;
00406
00407   /* Check the parameters */
00408   assert_param(IS_TIM6_TRGO_SOURCE_OK(TIM6_TRGOSource));
00409
00410   tmpcr2 = TIM6->CR2;
00411
00412   /* Reset the MMS Bits */
00413   tmpcr2 &= (uint8_t)(~TIM6_CR2_MMS);
00414
00415   /* Select the TRGO source */
00416   tmpcr2 |=  (uint8_t)TIM6_TRGOSource;
00417
00418   TIM6->CR2 = tmpcr2;
00419 }
00420
00421 /**
00422   * @brief  Sets or Resets the TIM6 Master/Slave Mode.
00423   * @param   NewState : The new state of the synchronization between TIM6 and its slaves (through TRGO).
00424   * This parameter can be any of the @ref FunctionalState enumeration.
00425   * @retval None
00426   */
00427
00428 void TIM6_SelectMasterSlaveMode(FunctionalState NewState)
00429 {
00430   /* Check the parameters */
00431   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00432
00433   /* Set or Reset the MSM Bit */
00434   if (NewState == ENABLE)
00435   {
00436     TIM6->SMCR |= TIM6_SMCR_MSM;
00437   }
00438   else
00439   {
00440     TIM6->SMCR &= (uint8_t)(~TIM6_SMCR_MSM);
00441   }
00442 }
00443
00444 /**
00445   * @brief  Selects the TIM6 Input Trigger source.
00446   * @param   TIM6_InputTriggerSource : Specifies Input Trigger source.
00447   * This parameter can be one of the @ref TIM6_TS_TypeDef enumeration.
00448   * @retval None
00449   */
00450 void TIM6_SelectInputTrigger(TIM6_TS_TypeDef TIM6_InputTriggerSource)
00451 {
00452   uint8_t tmpsmcr = 0;
00453
00454   /* Check the parameters */
00455   assert_param(IS_TIM6_TRIGGER_SELECTION_OK(TIM6_InputTriggerSource));
00456
00457   tmpsmcr = TIM6->SMCR;
00458
00459   /* Select the Trigger Source */
00460   tmpsmcr &= (uint8_t)(~TIM6_SMCR_TS);
00461   tmpsmcr |= (uint8_t)TIM6_InputTriggerSource;
00462
00463   TIM6->SMCR = (uint8_t)tmpsmcr;
00464 }
00465
00466 /**
00467   * @brief  Enables the TIM6 internal Clock.
00468   * @param  None
00469   * @retval None
00470   */
00471 void TIM6_InternalClockConfig(void)
00472 {
00473   /* Disable slave mode to clock the prescaler directly with the internal clock */
00474   TIM6->SMCR &=  (uint8_t)(~TIM6_SMCR_SMS);
00475 }
00476
00477 /**
00478   * @brief  Selects the TIM6 Slave Mode.
00479   * @param   TIM6_SlaveMode : Specifies the TIM6 Slave Mode.
00480   * This parameter can be one of the @ref TIM6_SlaveMode_TypeDef enumeration.
00481   * @retval None
00482   */
00483 void TIM6_SelectSlaveMode(TIM6_SlaveMode_TypeDef TIM6_SlaveMode)
00484 {
00485   uint8_t tmpsmcr = 0;
00486
00487   /* Check the parameters */
00488   assert_param(IS_TIM6_SLAVE_MODE_OK(TIM6_SlaveMode));
00489
00490   tmpsmcr = TIM6->SMCR;
00491
00492   /* Reset the SMS Bits */
00493   tmpsmcr &= (uint8_t)(~TIM6_SMCR_SMS);
00494
00495   /* Select the Slave Mode */
00496   tmpsmcr |= (uint8_t)TIM6_SlaveMode;
00497
00498   TIM6->SMCR = tmpsmcr;
00499 }
00500
00501 /**
00502   * @}
00503   */
00504
00505 /**
00506   * @}
00507   */
00508
00509
00510 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_tim6.h Source File

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
stm8s_tim6.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_tim6.h
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all functions prototype and macros for the TIM6 peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Define to prevent recursive inclusion -------------------------------------*/
00029 #ifndef __STM8S_TIM6_H
00030 #define __STM8S_TIM6_H
00031
00032 /* Includes ------------------------------------------------------------------*/
00033 #include "stm8s.h"
00034
00035 /** @addtogroup STM8S_StdPeriph_Driver
00036   * @{
00037   */
00038
00039 /* Exported variables ------------------------------------------------------- */
00040 /* Exported types ------------------------------------------------------------*/
00041
00042 /** @addtogroup TIM6_Exported_Types
00043   * @{
00044   */
00045
00046
00047 /**
00048   * @brief  TIM6 Prescaler
00049   */
00050 typedef enum
00051 {
00052     TIM6_PRESCALER_1      = ((uint8_t)0x00),  /*!< Time base Prescaler = 1 (No effect)*/
00053     TIM6_PRESCALER_2      = ((uint8_t)0x01),  /*!< Time base Prescaler = 2 */
00054     TIM6_PRESCALER_4      = ((uint8_t)0x02),  /*!< Time base Prescaler = 4 */
00055     TIM6_PRESCALER_8      = ((uint8_t)0x03),  /*!< Time base Prescaler = 8 */
00056     TIM6_PRESCALER_16     = ((uint8_t)0x04),  /*!< Time base Prescaler = 16 */
00057     TIM6_PRESCALER_32     = ((uint8_t)0x05),  /*!< Time base Prescaler = 32 */
00058     TIM6_PRESCALER_64     = ((uint8_t)0x06),  /*!< Time base Prescaler = 64 */
00059     TIM6_PRESCALER_128    = ((uint8_t)0x07)  /*!< Time base Prescaler = 128 */
00060 }TIM6_Prescaler_TypeDef;
00061
00062 /**
00063   * @brief  TIM6 One Pulse Mode
00064   */
00065 typedef enum
00066 {
00067     TIM6_OPMODE_SINGLE      = ((uint8_t)0x01),  /*!< Single one Pulse mode (OPM Active) */
00068     TIM6_OPMODE_REPETITIVE  = ((uint8_t)0x00)   /*!< Repetitive Pulse mode (OPM inactive) */
00069 }TIM6_OPMode_TypeDef;
00070
00071 /**
00072   * @brief  TIM6 Prescaler Reload Mode
00073   */
00074 typedef enum
00075 {
00076     TIM6_PSCRELOADMODE_UPDATE      =((uint8_t)0x00),  /*!< Prescaler value is reloaded at every update*/
00077     TIM6_PSCRELOADMODE_IMMEDIATE   =((uint8_t)0x01)    /*!< Prescaler value is reloaded immediately*/
00078 }TIM6_PSCReloadMode_TypeDef;
00079
00080 /**
00081   * @brief  TIM6 Update Source
00082   */
00083 typedef enum
00084 {
00085     TIM6_UPDATESOURCE_GLOBAL   =((uint8_t)0x00),  /*!< Global Update request source */
00086     TIM6_UPDATESOURCE_REGULAR  =((uint8_t)0x01)    /*!< Regular Update request source */
00087 }TIM6_UpdateSource_TypeDef;
00088
00089 /**
00090   * @brief  TIM6 Event Source
00091   */
00092 typedef enum
00093 {
00094     TIM6_EVENTSOURCE_UPDATE    = ((uint8_t)0x01),    /*!< Update Event*/
00095     TIM6_EVENTSOURCE_TRIGGER   = ((uint8_t)0x40)    /*!< Trigger Event*/
00096 }TIM6_EventSource_TypeDef;
00097
00098 /**
00099   * @brief  TIM6 Trigger Output Source
00100   */
00101 typedef enum
00102 {
00103     TIM6_TRGOSOURCE_RESET    = ((uint8_t)0x00),    /*!< Trigger Output source = Reset*/
00104     TIM6_TRGOSOURCE_ENABLE   = ((uint8_t)0x10),    /*!< Trigger Output source = TIM5 is enabled*/
00105     TIM6_TRGOSOURCE_UPDATE   = ((uint8_t)0x20)    /*!< Trigger Output source = Update event*/
00106 }TIM6_TRGOSource_TypeDef;
00107
00108 /**
00109   * @brief  TIM6 Slave Mode
00110   */
00111 typedef enum
00112 {
00113     TIM6_SLAVEMODE_DISABLE    = ((uint8_t)0x00),   /*!< Disable slave mode to clock the prescaler directly with the internal clock */
00114     TIM6_SLAVEMODE_RESET      = ((uint8_t)0x04),   /*!< Slave Mode Selection  = Reset*/
00115     TIM6_SLAVEMODE_GATED      = ((uint8_t)0x05),   /*!< Slave Mode Selection  = Gated*/
00116     TIM6_SLAVEMODE_TRIGGER    = ((uint8_t)0x06),    /*!< Slave Mode Selection  = Trigger*/
00117     TIM6_SLAVEMODE_EXTERNAL1  = ((uint8_t)0x07)    /*!< Slave Mode Selection  = External 1*/
00118 }TIM6_SlaveMode_TypeDef;
00119
00120 /**
00121   * @brief  TIM6 Flags
00122   */
00123 typedef enum
00124 {
00125     TIM6_FLAG_UPDATE   = ((uint8_t)0x01),    /*!< Update Flag */
00126     TIM6_FLAG_TRIGGER  = ((uint8_t)0x40)    /*!< Trigger Flag */
00127 }TIM6_FLAG_TypeDef;
00128
00129 /**
00130   * @brief  TIM6 interrupt sources
00131   */
00132 typedef enum
00133 {
00134     TIM6_IT_UPDATE   = ((uint8_t)0x01),    /*!< Update Interrupt*/
00135     TIM6_IT_TRIGGER  = ((uint8_t)0x40)    /*!< Trigger  Interrupt*/
00136 }TIM6_IT_TypeDef;
00137
00138 /**
00139   * @brief  TIM6 Internal Trigger Selection
00140   */
00141 typedef enum
00142 {
00143     TIM6_TS_TIM1  = ((uint8_t)0x20),/*!< TRIG Input source =  TIM1 TRIG Output  */
00144     TIM6_TS_TIM5  = ((uint8_t)0x30) /*!< TRIG Input source =  TIM5 TRIG Output  */
00145 }TIM6_TS_TypeDef;
00146
00147 /**
00148   * @}
00149   */
00150
00151 /* Exported constants --------------------------------------------------------*/
00152 /* Exported macros -----------------------------------------------------------*/
00153 /* Private macros ------------------------------------------------------------*/
00154
00155 /** @addtogroup TIM6_Private_Macros
00156   * @{
00157   */
00158
00159 /**
00160   * @brief  Macro used by the assert function to check the different functions parameters.
00161   */
00162
00163 /**
00164   * @brief  Macro TIM6 Prescaler
00165   */
00166 #define IS_TIM6_PRESCALER_OK(PRESCALER)  \
00167    (((PRESCALER) == TIM6_PRESCALER_1)    || \
00168     ((PRESCALER) == TIM6_PRESCALER_2)    || \
00169     ((PRESCALER) == TIM6_PRESCALER_4)    || \
00170     ((PRESCALER) == TIM6_PRESCALER_8)    || \
00171     ((PRESCALER) == TIM6_PRESCALER_16)   || \
00172     ((PRESCALER) == TIM6_PRESCALER_32)   || \
00173     ((PRESCALER) == TIM6_PRESCALER_64)   || \
00174     ((PRESCALER) == TIM6_PRESCALER_128))
00175 /**
00176   * @brief  Macro TIM6 One Pulse Mode
00177   */
00178 #define IS_TIM6_OPM_MODE_OK(MODE)  \
00179    (((MODE) == TIM6_OPMODE_SINGLE) || \
00180     ((MODE) == TIM6_OPMODE_REPETITIVE))
00181
00182 /**
00183   * @brief  Macro TIM6 Prescaler reload
00184   */
00185 #define IS_TIM6_PRESCALER_RELOAD_OK(RELOAD) \
00186    (((RELOAD) == TIM6_PSCRELOADMODE_UPDATE) || \
00187     ((RELOAD) == TIM6_PSCRELOADMODE_IMMEDIATE))
00188 /**
00189   * @brief  Macro TIM6 Update source
00190   */
00191 #define IS_TIM6_UPDATE_SOURCE_OK(SOURCE) \
00192    (((SOURCE) == TIM6_UPDATESOURCE_GLOBAL) || \
00193     ((SOURCE) == TIM6_UPDATESOURCE_REGULAR))
00194 /**
00195   * @brief  Macro TIM6 Event source
00196   */
00197 #define IS_TIM6_EVENT_SOURCE_OK(SOURCE) \
00198    ((((SOURCE) & (uint8_t)0xBE) == 0x00) && \
00199     ((SOURCE) != 0x00))
00200
00201 /**
00202   * @brief  Macro TIM6 TRGO source
00203   */
00204 #define IS_TIM6_TRGO_SOURCE_OK(SOURCE) \
00205    (((SOURCE) == TIM6_TRGOSOURCE_RESET) || \
00206     ((SOURCE) == TIM6_TRGOSOURCE_ENABLE)|| \
00207     ((SOURCE) == TIM6_TRGOSOURCE_UPDATE))
00208 /**
00209   * @brief  Macro TIM6 Slave mode
00210   */
00211 #define IS_TIM6_SLAVE_MODE_OK(MODE) \
00212    (((MODE) == TIM6_SLAVEMODE_DISABLE) || \
00213     ((MODE) == TIM6_SLAVEMODE_RESET)   || \
00214     ((MODE) == TIM6_SLAVEMODE_GATED)   || \
00215     ((MODE) == TIM6_SLAVEMODE_TRIGGER) || \
00216     ((MODE) == TIM6_SLAVEMODE_EXTERNAL1))
00217 /**
00218   * @brief  Macro TIM6 Flags
00219   */
00220 #define IS_TIM6_GET_FLAG_OK(FLAG) \
00221    (((FLAG) == TIM6_FLAG_UPDATE) || \
00222     ((FLAG) == TIM6_FLAG_TRIGGER))
00223
00224 #define IS_TIM6_CLEAR_FLAG_OK(FLAG) \
00225    ((((FLAG) & (uint8_t)0xBE) == 0x00) && ((FLAG) != 0x00))
00226 /**
00227   * @brief  Macro TIM6 interrupts
00228   */
00229 #define IS_TIM6_IT_OK(IT) \
00230    (((IT) != 0x00) && \
00231     (((IT) & (uint8_t)(~(uint8_t)(0x41)))== 0x00))
00232
00233 #define IS_TIM6_GET_IT_OK(IT) \
00234    (((IT) == TIM6_IT_UPDATE) || \
00235     ((IT) == TIM6_IT_TRIGGER))
00236 /**
00237   * @brief  Macro TIM6 Trigger selection
00238   */
00239 #define IS_TIM6_TRIGGER_SELECTION_OK(SELECTION) \
00240    (((SELECTION) == TIM6_TS_TIM5) || \
00241     ((SELECTION) == TIM6_TS_TIM1))
00242 /**
00243  * @}
00244  */
00245
00246 /* Exported functions --------------------------------------------------------*/
00247
00248 /** @addtogroup TIM6_Exported_Functions
00249   * @{
00250   */
00251
00252 void TIM6_DeInit(void);
00253 void TIM6_TimeBaseInit(TIM6_Prescaler_TypeDef TIM6_Prescaler, uint8_t TIM6_Period);
00254 void TIM6_Cmd(FunctionalState NewState);
00255 void TIM6_UpdateDisableConfig(FunctionalState NewState);
00256 void TIM6_UpdateRequestConfig(TIM6_UpdateSource_TypeDef TIM6_UpdateSource);
00257 void TIM6_SelectOnePulseMode(TIM6_OPMode_TypeDef TIM6_OPMode);
00258 void TIM6_PrescalerConfig(TIM6_Prescaler_TypeDef Prescaler, TIM6_PSCReloadMode_TypeDef TIM6_PSCReloadMode);
00259 void TIM6_ARRPreloadConfig(FunctionalState NewState);
00260 void TIM6_SetCounter(uint8_t Counter);
00261 void TIM6_SetAutoreload(uint8_t Autoreload);
00262 uint8_t TIM6_GetCounter(void);
00263 TIM6_Prescaler_TypeDef TIM6_GetPrescaler(void);
00264 void TIM6_ITConfig(TIM6_IT_TypeDef TIM6_IT, FunctionalState NewState);
00265 void TIM6_ClearFlag(TIM6_FLAG_TypeDef TIM6_FLAG);
00266 ITStatus TIM6_GetITStatus(TIM6_IT_TypeDef TIM6_IT);
00267 void TIM6_GenerateEvent(TIM6_EventSource_TypeDef TIM6_EventSource);
00268 FlagStatus TIM6_GetFlagStatus(TIM6_FLAG_TypeDef TIM6_FLAG);
00269 void TIM6_ClearITPendingBit(TIM6_IT_TypeDef TIM6_IT);
00270 void TIM6_SelectOutputTrigger(TIM6_TRGOSource_TypeDef TIM6_TRGOSource);
00271 void TIM6_SelectMasterSlaveMode(FunctionalState NewState);
00272 void TIM6_SelectInputTrigger(TIM6_TS_TypeDef TIM6_InputTriggerSource);
00273 void TIM6_InternalClockConfig(void);
00274 void TIM6_SelectSlaveMode(TIM6_SlaveMode_TypeDef TIM6_SlaveMode);
00275
00276 /**
00277  * @}
00278  */
00279
00280 #endif /* __STM8S_TIM6_H */
00281
00282 /**
00283   * @}
00284   */
00285
00286
00287 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_uart1.c Source File

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stm8s_uart1.c
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00001 /**
00002   ********************************************************************************
00003   * @file    stm8s_uart1.c
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all the functions for the UART1 peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm8s_uart1.h"
00030
00031 /** @addtogroup STM8S_StdPeriph_Driver
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041 /* Public functions ----------------------------------------------------------*/
00042
00043 /**
00044   * @addtogroup UART1_Public_Functions
00045   * @{
00046   */
00047
00048 /**
00049   * @brief  Deinitializes the UART peripheral.
00050   * @param  None
00051   * @retval None
00052         */
00053 void UART1_DeInit(void)
00054 {
00055   /* Clear the Idle Line Detected bit in the status register by a read
00056   to the UART1_SR register followed by a Read to the UART1_DR register */
00057   (void)UART1->SR;
00058   (void)UART1->DR;
00059
00060   UART1->BRR2 = UART1_BRR2_RESET_VALUE;  /* Set UART1_BRR2 to reset value 0x00 */
00061   UART1->BRR1 = UART1_BRR1_RESET_VALUE;  /* Set UART1_BRR1 to reset value 0x00 */
00062
00063   UART1->CR1 = UART1_CR1_RESET_VALUE;  /* Set UART1_CR1 to reset value 0x00 */
00064   UART1->CR2 = UART1_CR2_RESET_VALUE;  /* Set UART1_CR2 to reset value 0x00 */
00065   UART1->CR3 = UART1_CR3_RESET_VALUE;  /* Set UART1_CR3 to reset value 0x00 */
00066   UART1->CR4 = UART1_CR4_RESET_VALUE;  /* Set UART1_CR4 to reset value 0x00 */
00067   UART1->CR5 = UART1_CR5_RESET_VALUE;  /* Set UART1_CR5 to reset value 0x00 */
00068
00069   UART1->GTR = UART1_GTR_RESET_VALUE;
00070   UART1->PSCR = UART1_PSCR_RESET_VALUE;
00071 }
00072
00073 /**
00074   * @brief  Initializes the UART1 according to the specified parameters.
00075   * @note   Configure in Push Pull or Open Drain mode the Tx pin by setting the
00076   *         correct I/O Port register according the product package and line
00077   *         configuration
00078   * @param  BaudRate: The baudrate.
00079   * @param  WordLength : This parameter can be any of the
00080   *         @ref UART1_WordLength_TypeDef enumeration.
00081   * @param  StopBits: This parameter can be any of the
00082   *         @ref UART1_StopBits_TypeDef enumeration.
00083   * @param  Parity: This parameter can be any of the
00084   *         @ref UART1_Parity_TypeDef enumeration.
00085   * @param  SyncMode: This parameter can be any of the
00086   *         @ref UART1_SyncMode_TypeDef values.
00087   * @param  Mode: This parameter can be any of the @ref UART1_Mode_TypeDef values
00088   * @retval None
00089   */
00090 void UART1_Init(uint32_t BaudRate, UART1_WordLength_TypeDef WordLength,
00091                 UART1_StopBits_TypeDef StopBits, UART1_Parity_TypeDef Parity,
00092                 UART1_SyncMode_TypeDef SyncMode, UART1_Mode_TypeDef Mode)
00093 {
00094   uint32_t BaudRate_Mantissa = 0, BaudRate_Mantissa100 = 0;
00095
00096   /* Check the parameters */
00097   assert_param(IS_UART1_BAUDRATE_OK(BaudRate));
00098   assert_param(IS_UART1_WORDLENGTH_OK(WordLength));
00099   assert_param(IS_UART1_STOPBITS_OK(StopBits));
00100   assert_param(IS_UART1_PARITY_OK(Parity));
00101   assert_param(IS_UART1_MODE_OK((uint8_t)Mode));
00102   assert_param(IS_UART1_SYNCMODE_OK((uint8_t)SyncMode));
00103
00104   /* Clear the word length bit */
00105   UART1->CR1 &= (uint8_t)(~UART1_CR1_M);
00106
00107   /* Set the word length bit according to UART1_WordLength value */
00108   UART1->CR1 |= (uint8_t)WordLength;
00109
00110   /* Clear the STOP bits */
00111   UART1->CR3 &= (uint8_t)(~UART1_CR3_STOP);
00112   /* Set the STOP bits number according to UART1_StopBits value  */
00113   UART1->CR3 |= (uint8_t)StopBits;
00114
00115   /* Clear the Parity Control bit */
00116   UART1->CR1 &= (uint8_t)(~(UART1_CR1_PCEN | UART1_CR1_PS  ));
00117   /* Set the Parity Control bit to UART1_Parity value */
00118   UART1->CR1 |= (uint8_t)Parity;
00119
00120   /* Clear the LSB mantissa of UART1DIV  */
00121   UART1->BRR1 &= (uint8_t)(~UART1_BRR1_DIVM);
00122   /* Clear the MSB mantissa of UART1DIV  */
00123   UART1->BRR2 &= (uint8_t)(~UART1_BRR2_DIVM);
00124   /* Clear the Fraction bits of UART1DIV */
00125   UART1->BRR2 &= (uint8_t)(~UART1_BRR2_DIVF);
00126
00127   /* Set the UART1 BaudRates in BRR1 and BRR2 registers according to UART1_BaudRate value */
00128   BaudRate_Mantissa    = ((uint32_t)CLK_GetClockFreq() / (BaudRate << 4));
00129   BaudRate_Mantissa100 = (((uint32_t)CLK_GetClockFreq() * 100) / (BaudRate << 4));
00130   /* Set the fraction of UART1DIV  */
00131   UART1->BRR2 |= (uint8_t)((uint8_t)(((BaudRate_Mantissa100 - (BaudRate_Mantissa * 100)) << 4) / 100) & (uint8_t)0x0F);
00132   /* Set the MSB mantissa of UART1DIV  */
00133   UART1->BRR2 |= (uint8_t)((BaudRate_Mantissa >> 4) & (uint8_t)0xF0);
00134   /* Set the LSB mantissa of UART1DIV  */
00135   UART1->BRR1 |= (uint8_t)BaudRate_Mantissa;
00136
00137   /* Disable the Transmitter and Receiver before setting the LBCL, CPOL and CPHA bits */
00138   UART1->CR2 &= (uint8_t)~(UART1_CR2_TEN | UART1_CR2_REN);
00139   /* Clear the Clock Polarity, lock Phase, Last Bit Clock pulse */
00140   UART1->CR3 &= (uint8_t)~(UART1_CR3_CPOL | UART1_CR3_CPHA | UART1_CR3_LBCL);
00141   /* Set the Clock Polarity, lock Phase, Last Bit Clock pulse */
00142   UART1->CR3 |= (uint8_t)((uint8_t)SyncMode & (uint8_t)(UART1_CR3_CPOL |
00143                                                         UART1_CR3_CPHA | UART1_CR3_LBCL));
00144
00145   if ((uint8_t)(Mode & UART1_MODE_TX_ENABLE))
00146   {
00147     /* Set the Transmitter Enable bit */
00148     UART1->CR2 |= (uint8_t)UART1_CR2_TEN;
00149   }
00150   else
00151   {
00152     /* Clear the Transmitter Disable bit */
00153     UART1->CR2 &= (uint8_t)(~UART1_CR2_TEN);
00154   }
00155   if ((uint8_t)(Mode & UART1_MODE_RX_ENABLE))
00156   {
00157     /* Set the Receiver Enable bit */
00158     UART1->CR2 |= (uint8_t)UART1_CR2_REN;
00159   }
00160   else
00161   {
00162     /* Clear the Receiver Disable bit */
00163     UART1->CR2 &= (uint8_t)(~UART1_CR2_REN);
00164   }
00165   /* Set the Clock Enable bit, lock Polarity, lock Phase and Last Bit Clock
00166   pulse bits according to UART1_Mode value */
00167   if ((uint8_t)(SyncMode & UART1_SYNCMODE_CLOCK_DISABLE))
00168   {
00169     /* Clear the Clock Enable bit */
00170     UART1->CR3 &= (uint8_t)(~UART1_CR3_CKEN);
00171   }
00172   else
00173   {
00174     UART1->CR3 |= (uint8_t)((uint8_t)SyncMode & UART1_CR3_CKEN);
00175   }
00176 }
00177
00178 /**
00179   * @brief  Enable the UART1 peripheral.
00180   * @param  NewState : The new state of the UART Communication.
00181   *         This parameter can be any of the @ref FunctionalState enumeration.
00182   * @retval None
00183   */
00184 void UART1_Cmd(FunctionalState NewState)
00185 {
00186   if (NewState != DISABLE)
00187   {
00188     /* UART1 Enable */
00189     UART1->CR1 &= (uint8_t)(~UART1_CR1_UARTD);
00190   }
00191   else
00192   {
00193     /* UART Disable */
00194     UART1->CR1 |= UART1_CR1_UARTD;
00195   }
00196 }
00197
00198 /**
00199   * @brief  Enables or disables the specified USART interrupts.
00200   * @param  UART1_IT specifies the USART interrupt sources to be enabled or disabled.
00201   *         This parameter can be one of the following values:
00202   *         - UART1_IT_TXE:  Transmit Data Register empty interrupt
00203   *         - UART1_IT_TC:   Transmission complete interrupt
00204   *         - UART1_IT_RXNE_OR: Receive Data register not empty and Overrun interrupt
00205   *         - UART1_IT_IDLE: Idle line detection interrupt
00206   *         - USRT1_IT_ERR:  Error interrupt
00207   * @param  NewState new state of the specified USART interrupts.
00208   *         This parameter can be: ENABLE or DISABLE.
00209   * @retval None
00210   */
00211 void UART1_ITConfig(UART1_IT_TypeDef UART1_IT, FunctionalState NewState)
00212 {
00213   uint8_t uartreg = 0, itpos = 0x00;
00214
00215   /* Check the parameters */
00216   assert_param(IS_UART1_CONFIG_IT_OK(UART1_IT));
00217   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00218
00219   /* Get the UART1 register index */
00220   uartreg = (uint8_t)((uint16_t)UART1_IT >> 0x08);
00221   /* Get the UART1 IT index */
00222   itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)UART1_IT & (uint8_t)0x0F));
00223
00224   if (NewState != DISABLE)
00225   {
00226     /**< Enable the Interrupt bits according to UART1_IT mask */
00227     if (uartreg == 0x01)
00228     {
00229       UART1->CR1 |= itpos;
00230     }
00231     else if (uartreg == 0x02)
00232     {
00233       UART1->CR2 |= itpos;
00234     }
00235     else
00236     {
00237       UART1->CR4 |= itpos;
00238     }
00239   }
00240   else
00241   {
00242     /**< Disable the interrupt bits according to UART1_IT mask */
00243     if (uartreg == 0x01)
00244     {
00245       UART1->CR1 &= (uint8_t)(~itpos);
00246     }
00247     else if (uartreg == 0x02)
00248     {
00249       UART1->CR2 &= (uint8_t)(~itpos);
00250     }
00251     else
00252     {
00253       UART1->CR4 &= (uint8_t)(~itpos);
00254     }
00255   }
00256
00257 }
00258
00259 /**
00260   * @brief  Enables or disables the UART’s Half Duplex communication.
00261   * @param  NewState new state of the UART Communication.
00262   *         This parameter can be: ENABLE or DISABLE.
00263   * @retval None
00264   */
00265 void UART1_HalfDuplexCmd(FunctionalState NewState)
00266 {
00267   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00268
00269   if (NewState != DISABLE)
00270   {
00271     UART1->CR5 |= UART1_CR5_HDSEL;  /**< UART1 Half Duplex Enable  */
00272   }
00273   else
00274   {
00275     UART1->CR5 &= (uint8_t)~UART1_CR5_HDSEL; /**< UART1 Half Duplex Disable */
00276   }
00277 }
00278
00279 /**
00280   * @brief  Configures the UART’s IrDA interface.
00281   * @param  UART1_IrDAMode specifies the IrDA mode.
00282   *         This parameter can be any of the @ref UART1_IrDAMode_TypeDef values.
00283   * @retval None
00284   */
00285 void UART1_IrDAConfig(UART1_IrDAMode_TypeDef UART1_IrDAMode)
00286 {
00287   assert_param(IS_UART1_IRDAMODE_OK(UART1_IrDAMode));
00288
00289   if (UART1_IrDAMode != UART1_IRDAMODE_NORMAL)
00290   {
00291     UART1->CR5 |= UART1_CR5_IRLP;
00292   }
00293   else
00294   {
00295     UART1->CR5 &= ((uint8_t)~UART1_CR5_IRLP);
00296   }
00297 }
00298
00299 /**
00300   * @brief  Enables or disables the UART’s IrDA interface.
00301   * @param  NewState new state of the IrDA mode.
00302   *         This parameter can be: ENABLE or DISABLE.
00303   * @retval None
00304   */
00305 void UART1_IrDACmd(FunctionalState NewState)
00306 {
00307   /* Check parameters */
00308   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00309
00310   if (NewState != DISABLE)
00311   {
00312     /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
00313     UART1->CR5 |= UART1_CR5_IREN;
00314   }
00315   else
00316   {
00317     /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
00318     UART1->CR5 &= ((uint8_t)~UART1_CR5_IREN);
00319   }
00320 }
00321
00322 /**
00323   * @brief  Sets the UART1 LIN Break detection length.
00324   * @param  UART1_LINBreakDetectionLength specifies the LIN break detection length.
00325   *         This parameter can be any of the
00326   *         @ref UART1_LINBreakDetectionLength_TypeDef values.
00327   * @retval None
00328   */
00329 void UART1_LINBreakDetectionConfig(UART1_LINBreakDetectionLength_TypeDef UART1_LINBreakDetectionLength)
00330 {
00331   assert_param(IS_UART1_LINBREAKDETECTIONLENGTH_OK(UART1_LINBreakDetectionLength));
00332
00333   if (UART1_LINBreakDetectionLength != UART1_LINBREAKDETECTIONLENGTH_10BITS)
00334   {
00335     UART1->CR4 |= UART1_CR4_LBDL;
00336   }
00337   else
00338   {
00339     UART1->CR4 &= ((uint8_t)~UART1_CR4_LBDL);
00340   }
00341 }
00342
00343 /**
00344   * @brief  Enables or disables the UART1’s LIN mode.
00345   * @param  NewState is new state of the UART1 LIN mode.
00346   *         This parameter can be: ENABLE or DISABLE.
00347   * @retval None
00348   */
00349 void UART1_LINCmd(FunctionalState NewState)
00350 {
00351   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00352
00353   if (NewState != DISABLE)
00354   {
00355     /* Enable the LIN mode by setting the LINE bit in the CR2 register */
00356     UART1->CR3 |= UART1_CR3_LINEN;
00357   }
00358   else
00359   {
00360     /* Disable the LIN mode by clearing the LINE bit in the CR2 register */
00361     UART1->CR3 &= ((uint8_t)~UART1_CR3_LINEN);
00362   }
00363 }
00364
00365 /**
00366   * @brief  Enables or disables the UART1 Smart Card mode.
00367   * @param  NewState: new state of the Smart Card mode.
00368   * This parameter can be: ENABLE or DISABLE.
00369   * @retval None
00370   */
00371 void UART1_SmartCardCmd(FunctionalState NewState)
00372 {
00373   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00374
00375   if (NewState != DISABLE)
00376   {
00377     /* Enable the SC mode by setting the SCEN bit in the CR5 register */
00378     UART1->CR5 |= UART1_CR5_SCEN;
00379   }
00380   else
00381   {
00382     /* Disable the SC mode by clearing the SCEN bit in the CR5 register */
00383     UART1->CR5 &= ((uint8_t)(~UART1_CR5_SCEN));
00384   }
00385 }
00386
00387 /**
00388   * @brief  Enables or disables NACK transmission.
00389   * @note   This function is valid only for UART1 because is related to SmartCard mode.
00390   * @param  NewState: new state of the Smart Card mode.
00391   *         This parameter can be: ENABLE or DISABLE.
00392   * @retval None
00393   */
00394 void UART1_SmartCardNACKCmd(FunctionalState NewState)
00395 {
00396   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00397
00398   if (NewState != DISABLE)
00399   {
00400     /* Enable the NACK transmission by setting the NACK bit in the CR5 register */
00401     UART1->CR5 |= UART1_CR5_NACK;
00402   }
00403   else
00404   {
00405     /* Disable the NACK transmission by clearing the NACK bit in the CR5 register */
00406     UART1->CR5 &= ((uint8_t)~(UART1_CR5_NACK));
00407   }
00408 }
00409
00410 /**
00411   * @brief  Selects the UART1 WakeUp method.
00412   * @param  UART1_WakeUp: specifies the UART1 wakeup method.
00413   *         This parameter can be any of the @ref UART1_WakeUp_TypeDef values.
00414   * @retval None
00415   */
00416 void UART1_WakeUpConfig(UART1_WakeUp_TypeDef UART1_WakeUp)
00417 {
00418   assert_param(IS_UART1_WAKEUP_OK(UART1_WakeUp));
00419
00420   UART1->CR1 &= ((uint8_t)~UART1_CR1_WAKE);
00421   UART1->CR1 |= (uint8_t)UART1_WakeUp;
00422 }
00423
00424 /**
00425   * @brief  Determines if the UART1 is in mute mode or not.
00426   * @param  NewState: new state of the UART1 mode.
00427   *         This parameter can be: ENABLE or DISABLE.
00428   * @retval None
00429   */
00430 void UART1_ReceiverWakeUpCmd(FunctionalState NewState)
00431 {
00432   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00433
00434   if (NewState != DISABLE)
00435   {
00436     /* Enable the mute mode UART1 by setting the RWU bit in the CR2 register */
00437     UART1->CR2 |= UART1_CR2_RWU;
00438   }
00439   else
00440   {
00441     /* Disable the mute mode UART1 by clearing the RWU bit in the CR1 register */
00442     UART1->CR2 &= ((uint8_t)~UART1_CR2_RWU);
00443   }
00444 }
00445
00446 /**
00447   * @brief  Returns the most recent received data by the UART1 peripheral.
00448   * @param  None
00449   * @retval The received data.
00450   */
00451 uint8_t UART1_ReceiveData8(void)
00452 {
00453   return ((uint8_t)UART1->DR);
00454 }
00455
00456 /**
00457   * @brief  Returns the most recent received data by the UART1 peripheral.
00458   * @param  None
00459   * @retval The received data.
00460   */
00461 uint16_t UART1_ReceiveData9(void)
00462 {
00463   uint16_t temp = 0;
00464
00465   temp = (uint16_t)(((uint16_t)( (uint16_t)UART1->CR1 & (uint16_t)UART1_CR1_R8)) << 1);
00466   return (uint16_t)( (((uint16_t) UART1->DR) | temp ) & ((uint16_t)0x01FF));
00467 }
00468
00469 /**
00470   * @brief  Transmits 8 bit data through the UART1 peripheral.
00471   * @param  Data: The data to transmit.
00472   * @retval None
00473   */
00474 void UART1_SendData8(uint8_t Data)
00475 {
00476   /* Transmit Data */
00477   UART1->DR = Data;
00478 }
00479
00480 /**
00481   * @brief  Transmits 9 bit data through the UART peripheral.
00482   * @param  Data : The data to transmit.
00483   *         This parameter should be lower than 0x1FF.
00484   * @retval None
00485   */
00486 void UART1_SendData9(uint16_t Data)
00487 {
00488   /**< Clear the transmit data bit 8 [8]  */
00489   UART1->CR1 &= ((uint8_t)~UART1_CR1_T8);
00490   /**< Write the transmit data bit [8]  */
00491   UART1->CR1 |= (uint8_t)(((uint8_t)(Data >> 2)) & UART1_CR1_T8);
00492   /**< Write the transmit data bit [0:7] */
00493   UART1->DR   = (uint8_t)(Data);
00494 }
00495
00496 /**
00497   * @brief  Transmits break characters.
00498   * @param  None
00499   * @retval None
00500   */
00501 void UART1_SendBreak(void)
00502 {
00503   UART1->CR2 |= UART1_CR2_SBK;
00504 }
00505
00506 /**
00507   * @brief  Sets the address of the UART1 node.
00508   * @param  UART1_Address: Indicates the address of the UART1 node.
00509   * @retval None
00510   */
00511 void UART1_SetAddress(uint8_t UART1_Address)
00512 {
00513   /*assert_param for UART1_Address*/
00514   assert_param(IS_UART1_ADDRESS_OK(UART1_Address));
00515
00516   /* Clear the UART1 address */
00517   UART1->CR4 &= ((uint8_t)~UART1_CR4_ADD);
00518   /* Set the UART1 address node */
00519   UART1->CR4 |= UART1_Address;
00520 }
00521
00522 /**
00523   * @brief  Sets the specified UART guard time.
00524   * @note   SmartCard Mode should be Enabled
00525   * @param  UART1_GuardTime: specifies the guard time.
00526   * @retval None
00527   */
00528 void UART1_SetGuardTime(uint8_t UART1_GuardTime)
00529 {
00530   /* Set the UART1 guard time */
00531   UART1->GTR = UART1_GuardTime;
00532 }
00533
00534 /**
00535   * @brief  Sets the system clock prescaler.
00536   * @note   IrDA Low Power mode or smartcard mode should be enabled
00537   * @note   This function is related to SmartCard and IrDa mode.
00538   * @param  UART1_Prescaler: specifies the prescaler clock.
00539   *         This parameter can be one of the following values:
00540   *         @par IrDA Low Power Mode
00541   *         The clock source is divided by the value given in the register (8 bits)
00542   *         - 0000 0000 Reserved
00543   *         - 0000 0001 divides the clock source by 1
00544   *         - 0000 0010 divides the clock source by 2
00545   *         - ...
00546   *        @par Smart Card Mode
00547   *        The clock source is divided by the value given in the register
00548   *        (5 significant bits) multiplied by 2
00549   *         - 0 0000 Reserved
00550   *         - 0 0001 divides the clock source by 2
00551   *         - 0 0010 divides the clock source by 4
00552   *         - 0 0011 divides the clock source by 6
00553   *         - ...
00554   * @retval None
00555   */
00556 void UART1_SetPrescaler(uint8_t UART1_Prescaler)
00557 {
00558   /* Load the UART1 prescaler value*/
00559   UART1->PSCR = UART1_Prescaler;
00560 }
00561
00562 /**
00563   * @brief  Checks whether the specified UART1 flag is set or not.
00564   * @param  UART1_FLAG specifies the flag to check.
00565   *         This parameter can be any of the @ref UART1_Flag_TypeDef enumeration.
00566   * @retval FlagStatus (SET or RESET)
00567   */
00568 FlagStatus UART1_GetFlagStatus(UART1_Flag_TypeDef UART1_FLAG)
00569 {
00570   FlagStatus status = RESET;
00571
00572   /* Check parameters */
00573   assert_param(IS_UART1_FLAG_OK(UART1_FLAG));
00574
00575
00576   /* Check the status of the specified UART1 flag*/
00577   if (UART1_FLAG == UART1_FLAG_LBDF)
00578   {
00579     if ((UART1->CR4 & (uint8_t)UART1_FLAG) != (uint8_t)0x00)
00580     {
00581       /* UART1_FLAG is set*/
00582       status = SET;
00583     }
00584     else
00585     {
00586       /* UART1_FLAG is reset*/
00587       status = RESET;
00588     }
00589   }
00590   else if (UART1_FLAG == UART1_FLAG_SBK)
00591   {
00592     if ((UART1->CR2 & (uint8_t)UART1_FLAG) != (uint8_t)0x00)
00593     {
00594       /* UART1_FLAG is set*/
00595       status = SET;
00596     }
00597     else
00598     {
00599       /* UART1_FLAG is reset*/
00600       status = RESET;
00601     }
00602   }
00603   else
00604   {
00605     if ((UART1->SR & (uint8_t)UART1_FLAG) != (uint8_t)0x00)
00606     {
00607       /* UART1_FLAG is set*/
00608       status = SET;
00609     }
00610     else
00611     {
00612       /* UART1_FLAG is reset*/
00613       status = RESET;
00614     }
00615   }
00616   /* Return the UART1_FLAG status*/
00617   return status;
00618 }
00619
00620 /**
00621   * @brief  Clears the UART1 flags.
00622   * @param  UART1_FLAG specifies the flag to clear
00623   *         This parameter can be any combination of the following values:
00624   *         - UART1_FLAG_LBDF: LIN Break detection flag.
00625   *         - UART1_FLAG_RXNE: Receive data register not empty flag.
00626   * @note
00627   *         - PE (Parity error), FE (Framing error), NE (Noise error),
00628   *         OR (OverRun error) and IDLE (Idle line detected) flags are
00629   *         cleared by software sequence: a read operation to UART1_SR register
00630   *         (UART1_GetFlagStatus())followed by a read operation to UART1_DR
00631   *         register(UART1_ReceiveData8() or UART1_ReceiveData9()).
00632   *
00633   *         - RXNE flag can be also cleared by a read to the UART1_DR register
00634   *         (UART1_ReceiveData8()or UART1_ReceiveData9()).
00635   *
00636   *         - TC flag can be also cleared by software sequence: a read operation
00637   *         to UART1_SR register (UART1_GetFlagStatus()) followed by a write
00638   *         operation to UART1_DR register (UART1_SendData8() or UART1_SendData9()).
00639   *
00640   *         - TXE flag is cleared only by a write to the UART1_DR register
00641   *         (UART1_SendData8() or UART1_SendData9()).
00642   *
00643   *         - SBK flag is cleared during the stop bit of break.
00644   * @retval None
00645   */
00646 void UART1_ClearFlag(UART1_Flag_TypeDef UART1_FLAG)
00647 {
00648   assert_param(IS_UART1_CLEAR_FLAG_OK(UART1_FLAG));
00649
00650   /* Clear the Receive Register Not Empty flag */
00651   if (UART1_FLAG == UART1_FLAG_RXNE)
00652   {
00653     UART1->SR = (uint8_t)~(UART1_SR_RXNE);
00654   }
00655   /* Clear the LIN Break Detection flag */
00656   else
00657   {
00658     UART1->CR4 &= (uint8_t)~(UART1_CR4_LBDF);
00659   }
00660 }
00661
00662 /**
00663   * @brief  Checks whether the specified UART1 interrupt has occurred or not.
00664   * @param  UART1_IT: Specifies the UART1 interrupt pending bit to check.
00665   *         This parameter can be one of the following values:
00666   *         - UART1_IT_LBDF:  LIN Break detection interrupt
00667   *         - UART1_IT_TXE:  Transmit Data Register empty interrupt
00668   *         - UART1_IT_TC:   Transmission complete interrupt
00669   *         - UART1_IT_RXNE: Receive Data register not empty interrupt
00670   *         - UART1_IT_IDLE: Idle line detection interrupt
00671   *         - UART1_IT_OR:  OverRun Error interrupt
00672   *         - UART1_IT_PE:   Parity Error interrupt
00673   * @retval The new state of UART1_IT (SET or RESET).
00674   */
00675 ITStatus UART1_GetITStatus(UART1_IT_TypeDef UART1_IT)
00676 {
00677   ITStatus pendingbitstatus = RESET;
00678   uint8_t itpos = 0;
00679   uint8_t itmask1 = 0;
00680   uint8_t itmask2 = 0;
00681   uint8_t enablestatus = 0;
00682
00683   /* Check parameters */
00684   assert_param(IS_UART1_GET_IT_OK(UART1_IT));
00685
00686   /* Get the UART1 IT index */
00687   itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)UART1_IT & (uint8_t)0x0F));
00688   /* Get the UART1 IT index */
00689   itmask1 = (uint8_t)((uint8_t)UART1_IT >> (uint8_t)4);
00690   /* Set the IT mask*/
00691   itmask2 = (uint8_t)((uint8_t)1 << itmask1);
00692
00693
00694   /* Check the status of the specified UART1 pending bit*/
00695   if (UART1_IT == UART1_IT_PE)
00696   {
00697     /* Get the UART1_IT enable bit status*/
00698     enablestatus = (uint8_t)((uint8_t)UART1->CR1 & itmask2);
00699     /* Check the status of the specified UART1 interrupt*/
00700
00701     if (((UART1->SR & itpos) != (uint8_t)0x00) && enablestatus)
00702     {
00703       /* Interrupt occurred*/
00704       pendingbitstatus = SET;
00705     }
00706     else
00707     {
00708       /* Interrupt not occurred*/
00709       pendingbitstatus = RESET;
00710     }
00711   }
00712
00713   else if (UART1_IT == UART1_IT_LBDF)
00714   {
00715     /* Get the UART1_IT enable bit status*/
00716     enablestatus = (uint8_t)((uint8_t)UART1->CR4 & itmask2);
00717     /* Check the status of the specified UART1 interrupt*/
00718     if (((UART1->CR4 & itpos) != (uint8_t)0x00) && enablestatus)
00719     {
00720       /* Interrupt occurred*/
00721       pendingbitstatus = SET;
00722     }
00723     else
00724     {
00725       /* Interrupt not occurred*/
00726       pendingbitstatus = RESET;
00727     }
00728   }
00729   else
00730   {
00731     /* Get the UART1_IT enable bit status*/
00732     enablestatus = (uint8_t)((uint8_t)UART1->CR2 & itmask2);
00733     /* Check the status of the specified UART1 interrupt*/
00734     if (((UART1->SR & itpos) != (uint8_t)0x00) && enablestatus)
00735     {
00736       /* Interrupt occurred*/
00737       pendingbitstatus = SET;
00738     }
00739     else
00740     {
00741       /* Interrupt not occurred*/
00742       pendingbitstatus = RESET;
00743     }
00744   }
00745
00746   /* Return the UART1_IT status*/
00747   return  pendingbitstatus;
00748 }
00749
00750 /**
00751   * @brief  Clears the UART1 pending flags.
00752   * @param  UART1_IT specifies the pending bit to clear
00753   *         This parameter can be one of the following values:
00754   *         - UART1_IT_LBDF:  LIN Break detection interrupt
00755   *         - UART1_IT_RXNE: Receive Data register not empty interrupt.
00756   * @note
00757   *         - PE (Parity error), FE (Framing error), NE (Noise error),
00758   *           OR (OverRun error) and IDLE (Idle line detected) pending bits are
00759   *           cleared by software sequence: a read operation to UART1_SR register
00760   *           (UART1_GetITStatus()) followed by a read operation to UART1_DR register
00761   *           (UART1_ReceiveData8() or UART1_ReceiveData9()).
00762   *
00763   *         - RXNE pending bit can be also cleared by a read to the UART1_DR register
00764   *           (UART1_ReceiveData8() or UART1_ReceiveData9()).
00765   *
00766   *         - TC (Transmit complete) pending bit can be cleared by software
00767   *           sequence: a read operation to UART1_SR register (UART1_GetITStatus())
00768   *           followed by a write operation to UART1_DR register (UART1_SendData8()
00769   *           or UART1_SendData9()).
00770   *
00771   *         - TXE pending bit is cleared only by a write to the UART1_DR register
00772   *           (UART1_SendData8() or UART1_SendData9()).
00773   * @retval None
00774   */
00775 void UART1_ClearITPendingBit(UART1_IT_TypeDef UART1_IT)
00776 {
00777   assert_param(IS_UART1_CLEAR_IT_OK(UART1_IT));
00778
00779   /* Clear the Receive Register Not Empty pending bit */
00780   if (UART1_IT == UART1_IT_RXNE)
00781   {
00782     UART1->SR = (uint8_t)~(UART1_SR_RXNE);
00783   }
00784   /* Clear the LIN Break Detection pending bit */
00785   else
00786   {
00787     UART1->CR4 &= (uint8_t)~(UART1_CR4_LBDF);
00788   }
00789 }
00790
00791 /**
00792   * @}
00793   */
00794
00795 /**
00796   * @}
00797   */
00798
00799
00800 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_uart1.h Source File

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stm8s_uart1.h
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00001 /**
00002   ********************************************************************************
00003   * @file    stm8s_uart1.h
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all functions prototypes and macros for the UART1 peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Define to prevent recursive inclusion -------------------------------------*/
00029 #ifndef __STM8S_UART1_H
00030 #define __STM8S_UART1_H
00031
00032 /* Includes ------------------------------------------------------------------*/
00033 #include "stm8s.h"
00034
00035 /** @addtogroup STM8S_StdPeriph_Driver
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040
00041 /** @addtogroup UART1_Exported_Types
00042   * @{
00043   */
00044
00045
00046 /**
00047   * @brief  UART1 Irda Modes
00048   */
00049
00050 typedef enum { UART1_IRDAMODE_NORMAL    = (uint8_t)0x00, /**< 0x00 Irda Normal Mode   */
00051                UART1_IRDAMODE_LOWPOWER  = (uint8_t)0x01  /**< 0x01 Irda Low Power Mode */
00052              } UART1_IrDAMode_TypeDef;
00053
00054 /**
00055   * @brief  UART1 WakeUP Modes
00056   */
00057 typedef enum { UART1_WAKEUP_IDLELINE       = (uint8_t)0x00, /**< 0x01 Idle Line wake up                */
00058                UART1_WAKEUP_ADDRESSMARK    = (uint8_t)0x08  /**< 0x02 Address Mark wake up          */
00059              } UART1_WakeUp_TypeDef;
00060
00061 /**
00062   * @brief  UART1 LIN Break detection length possible values
00063   */
00064 typedef enum { UART1_LINBREAKDETECTIONLENGTH_10BITS = (uint8_t)0x00, /**< 0x01 10 bits Lin Break detection            */
00065                UART1_LINBREAKDETECTIONLENGTH_11BITS = (uint8_t)0x01  /**< 0x02 11 bits Lin Break detection          */
00066              } UART1_LINBreakDetectionLength_TypeDef;
00067
00068 /**
00069   * @brief  UART1 stop bits possible values
00070   */
00071
00072 typedef enum { UART1_STOPBITS_1   = (uint8_t)0x00,    /**< One stop bit is  transmitted at the end of frame*/
00073                UART1_STOPBITS_0_5 = (uint8_t)0x10,    /**< Half stop bits is transmitted at the end of frame*/
00074                UART1_STOPBITS_2   = (uint8_t)0x20,    /**< Two stop bits are  transmitted at the end of frame*/
00075                UART1_STOPBITS_1_5 = (uint8_t)0x30     /**< One and half stop bits*/
00076              } UART1_StopBits_TypeDef;
00077
00078 /**
00079   * @brief  UART1 parity possible values
00080   */
00081 typedef enum { UART1_PARITY_NO     = (uint8_t)0x00,      /**< No Parity*/
00082                UART1_PARITY_EVEN   = (uint8_t)0x04,      /**< Even Parity*/
00083                UART1_PARITY_ODD    = (uint8_t)0x06       /**< Odd Parity*/
00084              } UART1_Parity_TypeDef;
00085
00086 /**
00087   * @brief  UART1 Synchrone modes
00088   */
00089 typedef enum { UART1_SYNCMODE_CLOCK_DISABLE    = (uint8_t)0x80, /**< 0x80 Sync mode Disable, SLK pin Disable */
00090                UART1_SYNCMODE_CLOCK_ENABLE     = (uint8_t)0x08, /**< 0x08 Sync mode Enable, SLK pin Enable     */
00091                UART1_SYNCMODE_CPOL_LOW         = (uint8_t)0x40, /**< 0x40 Steady low value on SCLK pin outside transmission window */
00092                UART1_SYNCMODE_CPOL_HIGH        = (uint8_t)0x04, /**< 0x04 Steady high value on SCLK pin outside transmission window */
00093                UART1_SYNCMODE_CPHA_MIDDLE      = (uint8_t)0x20, /**< 0x20 SCLK clock line activated in middle of data bit     */
00094                UART1_SYNCMODE_CPHA_BEGINING    = (uint8_t)0x02, /**< 0x02 SCLK clock line activated at beginning of data bit  */
00095                UART1_SYNCMODE_LASTBIT_DISABLE  = (uint8_t)0x10, /**< 0x10 The clock pulse of the last data bit is not output to the SCLK pin */
00096                UART1_SYNCMODE_LASTBIT_ENABLE   = (uint8_t)0x01  /**< 0x01 The clock pulse of the last data bit is output to the SCLK pin */
00097              } UART1_SyncMode_TypeDef;
00098
00099 /**
00100   * @brief  UART1 Word length possible values
00101   */
00102 typedef enum { UART1_WORDLENGTH_8D = (uint8_t)0x00,/**< 0x00 8 bits Data  */
00103                UART1_WORDLENGTH_9D = (uint8_t)0x10 /**< 0x10 9 bits Data  */
00104              } UART1_WordLength_TypeDef;
00105
00106 /**
00107   * @brief  UART1 Mode possible values
00108   */
00109 typedef enum { UART1_MODE_RX_ENABLE     = (uint8_t)0x08,  /**< 0x08 Receive Enable */
00110                UART1_MODE_TX_ENABLE     = (uint8_t)0x04,  /**< 0x04 Transmit Enable */
00111                UART1_MODE_TX_DISABLE    = (uint8_t)0x80,  /**< 0x80 Transmit Disable */
00112                UART1_MODE_RX_DISABLE    = (uint8_t)0x40,  /**< 0x40 Single-wire Half-duplex mode */
00113                UART1_MODE_TXRX_ENABLE   = (uint8_t)0x0C  /**< 0x0C Transmit Enable and Receive Enable */
00114              } UART1_Mode_TypeDef;
00115
00116 /**
00117   * @brief  UART1 Flag possible values
00118   */
00119 typedef enum { UART1_FLAG_TXE   = (uint16_t)0x0080, /*!< Transmit Data Register Empty flag */
00120                UART1_FLAG_TC    = (uint16_t)0x0040, /*!< Transmission Complete flag */
00121                UART1_FLAG_RXNE  = (uint16_t)0x0020, /*!< Read Data Register Not Empty flag */
00122                UART1_FLAG_IDLE  = (uint16_t)0x0010, /*!< Idle line detected flag */
00123                UART1_FLAG_OR    = (uint16_t)0x0008, /*!< OverRun error flag */
00124                UART1_FLAG_NF    = (uint16_t)0x0004, /*!< Noise error flag */
00125                UART1_FLAG_FE    = (uint16_t)0x0002, /*!< Framing Error flag */
00126                UART1_FLAG_PE    = (uint16_t)0x0001, /*!< Parity Error flag */
00127                UART1_FLAG_LBDF  = (uint16_t)0x0210, /*!< Line Break Detection Flag */
00128                UART1_FLAG_SBK   = (uint16_t)0x0101  /*!< Send Break characters Flag */
00129              } UART1_Flag_TypeDef;
00130
00131 /**
00132   * @brief  UART1 Interrupt definition
00133   * UART1_IT possible values
00134   * Elements values convention: 0xZYX
00135   * X: Position of the corresponding Interrupt
00136   *   - For the following values, X means the interrupt position in the CR2 register.
00137   *     UART1_IT_TXE
00138   *     UART1_IT_TC
00139   *     UART1_IT_RXNE
00140   *     UART1_IT_IDLE
00141   *     UART1_IT_OR
00142   *   - For the UART1_IT_PE value, X means the flag position in the CR1 register.
00143   *   - For the UART1_IT_LBDF value, X means the flag position in the CR4 register.
00144   * Y: Flag position
00145   *  - For the following values, Y means the flag (pending bit) position in the SR register.
00146   *     UART1_IT_TXE
00147   *     UART1_IT_TC
00148   *     UART1_IT_RXNE
00149   *     UART1_IT_IDLE
00150   *     UART1_IT_OR
00151   *     UART1_IT_PE
00152   *  - For the UART1_IT_LBDF value, Y means the flag position in the CR4 register.
00153   * Z: Register index: indicate in which register the dedicated interrupt source is:
00154   *  - 1==> CR1 register
00155   *  - 2==> CR2 register
00156   *  - 3==> CR4 register
00157   */
00158 typedef enum { UART1_IT_TXE        = (uint16_t)0x0277, /*!< Transmit interrupt */
00159                UART1_IT_TC         = (uint16_t)0x0266, /*!< Transmission Complete interrupt */
00160                UART1_IT_RXNE       = (uint16_t)0x0255, /*!< Receive interrupt */
00161                UART1_IT_IDLE       = (uint16_t)0x0244, /*!< IDLE line interrupt */
00162                UART1_IT_OR         = (uint16_t)0x0235, /*!< Overrun Error interrupt */
00163                UART1_IT_PE         = (uint16_t)0x0100, /*!< Parity Error interrupt */
00164                UART1_IT_LBDF       = (uint16_t)0x0346, /**< LIN break detection interrupt */
00165                UART1_IT_RXNE_OR    = (uint16_t)0x0205  /*!< Receive/Overrun interrupt */
00166              } UART1_IT_TypeDef;
00167
00168 /**
00169   * @}
00170   */
00171
00172 /* Exported constants --------------------------------------------------------*/
00173 /* Exported macros ------------------------------------------------------------*/
00174
00175 /* Private macros ------------------------------------------------------------*/
00176
00177 /** @addtogroup UART1_Private_Macros
00178   * @{
00179   */
00180
00181 /**
00182   * @brief  Macro used by the assert function to check the different functions parameters.
00183   */
00184
00185 /**
00186  * @brief Macro used by the assert_param function in order to check the different
00187  *        sensitivity values for the MODEs possible combination should be one of
00188  *        the following
00189  */
00190 #define IS_UART1_MODE_OK(Mode) \
00191   (((Mode) == (uint8_t)UART1_MODE_RX_ENABLE) || \
00192    ((Mode) == (uint8_t)UART1_MODE_RX_DISABLE) || \
00193    ((Mode) == (uint8_t)UART1_MODE_TX_ENABLE) || \
00194    ((Mode) == (uint8_t)UART1_MODE_TX_DISABLE) || \
00195    ((Mode) == (uint8_t)UART1_MODE_TXRX_ENABLE) || \
00196    ((Mode) == (uint8_t)((uint8_t)UART1_MODE_TX_ENABLE|(uint8_t)UART1_MODE_RX_ENABLE)) || \
00197    ((Mode) == (uint8_t)((uint8_t)UART1_MODE_TX_ENABLE|(uint8_t)UART1_MODE_RX_DISABLE)) || \
00198    ((Mode) == (uint8_t)((uint8_t)UART1_MODE_TX_DISABLE|(uint8_t)UART1_MODE_RX_DISABLE)) || \
00199    ((Mode) == (uint8_t)((uint8_t)UART1_MODE_TX_DISABLE|(uint8_t)UART1_MODE_RX_ENABLE)))
00200
00201 /**
00202  * @brief Macro used by the assert_param function in order to check the different
00203  *        sensitivity values for the WordLengths
00204  */
00205 #define IS_UART1_WORDLENGTH_OK(WordLength) \
00206   (((WordLength) == UART1_WORDLENGTH_8D) || \
00207    ((WordLength) == UART1_WORDLENGTH_9D))
00208
00209 /**
00210   * @brief  Macro used by the assert_param function in order to check the different
00211   *         sensitivity values for the SyncModes; it should exclude values such
00212   *         as  UART1_CLOCK_ENABLE|UART1_CLOCK_DISABLE
00213   */
00214 #define IS_UART1_SYNCMODE_OK(SyncMode) \
00215   (!((((SyncMode)&(((uint8_t)UART1_SYNCMODE_CLOCK_ENABLE)|((uint8_t)UART1_SYNCMODE_CLOCK_DISABLE))) == (((uint8_t)UART1_SYNCMODE_CLOCK_ENABLE)|((uint8_t)UART1_SYNCMODE_CLOCK_DISABLE))) \
00216     || (((SyncMode)&(((uint8_t)UART1_SYNCMODE_CPOL_LOW )|((uint8_t)UART1_SYNCMODE_CPOL_HIGH))) == (((uint8_t)UART1_SYNCMODE_CPOL_LOW )|((uint8_t)UART1_SYNCMODE_CPOL_HIGH))) \
00217     ||(((SyncMode)&(((uint8_t)UART1_SYNCMODE_CPHA_MIDDLE)|((uint8_t)UART1_SYNCMODE_CPHA_BEGINING))) ==  (((uint8_t)UART1_SYNCMODE_CPHA_MIDDLE)|((uint8_t)UART1_SYNCMODE_CPHA_BEGINING))) \
00218     || (((SyncMode)&(((uint8_t)UART1_SYNCMODE_LASTBIT_DISABLE)|((uint8_t)UART1_SYNCMODE_LASTBIT_ENABLE))) == (((uint8_t)UART1_SYNCMODE_LASTBIT_DISABLE)|((uint8_t)UART1_SYNCMODE_LASTBIT_ENABLE)))))
00219
00220 /**
00221   * @brief  Macro used by the assert_param function in order to check the different
00222   *         sensitivity values for the FLAGs
00223   */
00224 #define IS_UART1_FLAG_OK(Flag) \
00225   (((Flag) == UART1_FLAG_TXE) || \
00226    ((Flag) == UART1_FLAG_TC)  || \
00227    ((Flag) == UART1_FLAG_RXNE) || \
00228    ((Flag) == UART1_FLAG_IDLE) || \
00229    ((Flag) == UART1_FLAG_OR) || \
00230    ((Flag) == UART1_FLAG_NF) || \
00231    ((Flag) == UART1_FLAG_FE) || \
00232    ((Flag) == UART1_FLAG_PE) || \
00233    ((Flag) == UART1_FLAG_SBK) || \
00234    ((Flag) == UART1_FLAG_LBDF))
00235 /**
00236   * @brief  Macro used by the assert_param function in order to check the different
00237   *         sensitivity values for the FLAGs that can be cleared by writing 0
00238   */
00239 #define IS_UART1_CLEAR_FLAG_OK(Flag) \
00240   (((Flag) == UART1_FLAG_RXNE) || \
00241    ((Flag) == UART1_FLAG_LBDF))
00242
00243
00244
00245 /**
00246   * @brief  Macro used by the assert_param function in order to check the different
00247   *         sensitivity values for the Interrupts
00248   */
00249
00250 #define IS_UART1_CONFIG_IT_OK(Interrupt) \
00251   (((Interrupt) == UART1_IT_PE) || \
00252    ((Interrupt) == UART1_IT_TXE) || \
00253    ((Interrupt) == UART1_IT_TC) || \
00254    ((Interrupt) == UART1_IT_RXNE_OR ) || \
00255    ((Interrupt) == UART1_IT_IDLE) || \
00256    ((Interrupt) == UART1_IT_LBDF))
00257
00258 /**
00259   * @brief  Macro used by the assert function in order to check the different
00260   *         sensitivity values for the pending bit
00261   */
00262 #define IS_UART1_GET_IT_OK(ITPendingBit) \
00263   (((ITPendingBit) == UART1_IT_TXE)  || \
00264    ((ITPendingBit) == UART1_IT_TC)   || \
00265    ((ITPendingBit) == UART1_IT_RXNE) || \
00266    ((ITPendingBit) == UART1_IT_IDLE) || \
00267    ((ITPendingBit) == UART1_IT_OR)  || \
00268    ((ITPendingBit) == UART1_IT_LBDF)  || \
00269    ((ITPendingBit) == UART1_IT_PE))
00270
00271 /**
00272   * @brief  Macro used by the assert function in order to check the different
00273   *         sensitivity values for the pending bit that can be cleared by writing 0
00274   */
00275 #define IS_UART1_CLEAR_IT_OK(ITPendingBit) \
00276   (((ITPendingBit) == UART1_IT_RXNE) || \
00277    ((ITPendingBit) == UART1_IT_LBDF))
00278
00279
00280 /**
00281  * @brief Macro used by the assert_param function in order to check the different
00282  *        sensitivity values for the IrDAModes
00283  */
00284 #define IS_UART1_IRDAMODE_OK(IrDAMode) \
00285   (((IrDAMode) == UART1_IRDAMODE_LOWPOWER) || \
00286    ((IrDAMode) == UART1_IRDAMODE_NORMAL))
00287
00288 /**
00289   * @brief  Macro used by the assert_param function in order to check the different
00290   *         sensitivity values for the WakeUps
00291   */
00292 #define IS_UART1_WAKEUP_OK(WakeUp) \
00293   (((WakeUp) == UART1_WAKEUP_IDLELINE) || \
00294    ((WakeUp) == UART1_WAKEUP_ADDRESSMARK))
00295
00296 /**
00297   * @brief  Macro used by the assert_param function in order to check the different
00298   *        sensitivity values for the LINBreakDetectionLengths
00299   */
00300 #define IS_UART1_LINBREAKDETECTIONLENGTH_OK(LINBreakDetectionLength) \
00301   (((LINBreakDetectionLength) == UART1_LINBREAKDETECTIONLENGTH_10BITS) || \
00302    ((LINBreakDetectionLength) == UART1_LINBREAKDETECTIONLENGTH_11BITS))
00303
00304 /**
00305   * @brief  Macro used by the assert_param function in order to check the different
00306   *         sensitivity values for the UART1_StopBits
00307   */
00308 #define IS_UART1_STOPBITS_OK(StopBit) (((StopBit) == UART1_STOPBITS_1) || \
00309                                        ((StopBit) == UART1_STOPBITS_0_5) || \
00310                                        ((StopBit) == UART1_STOPBITS_2) || \
00311                                        ((StopBit) == UART1_STOPBITS_1_5 ))
00312
00313 /**
00314  * @brief Macro used by the assert_param function in order to check the different
00315  *        sensitivity values for the Parity
00316  */
00317 #define IS_UART1_PARITY_OK(Parity) (((Parity) == UART1_PARITY_NO) || \
00318                                     ((Parity) == UART1_PARITY_EVEN) || \
00319                                     ((Parity) == UART1_PARITY_ODD ))
00320
00321 /**
00322  * @brief Macro used by the assert_param function in order to check the maximum
00323  *        baudrate value
00324  */
00325 #define IS_UART1_BAUDRATE_OK(NUM) ((NUM) <= (uint32_t)625000)
00326
00327
00328 /**
00329  * @brief Macro used by the assert_param function in order to check the address
00330  *        of the UART1 or UART node
00331  */
00332 #define UART1_ADDRESS_MAX ((uint8_t)16)
00333 #define IS_UART1_ADDRESS_OK(node) ((node) < UART1_ADDRESS_MAX )
00334
00335 /**
00336   * @}
00337   */
00338
00339 /* Exported functions ------------------------------------------------------- */
00340
00341 /** @addtogroup UART1_Exported_Functions
00342   * @{
00343   */
00344
00345 void UART1_DeInit(void);
00346 void UART1_Init(uint32_t BaudRate, UART1_WordLength_TypeDef WordLength,
00347                 UART1_StopBits_TypeDef StopBits, UART1_Parity_TypeDef Parity,
00348                 UART1_SyncMode_TypeDef SyncMode, UART1_Mode_TypeDef Mode);
00349 void UART1_Cmd(FunctionalState NewState);
00350 void UART1_ITConfig(UART1_IT_TypeDef UART1_IT, FunctionalState NewState);
00351 void UART1_HalfDuplexCmd(FunctionalState NewState);
00352 void UART1_IrDAConfig(UART1_IrDAMode_TypeDef UART1_IrDAMode);
00353 void UART1_IrDACmd(FunctionalState NewState);
00354 void UART1_LINBreakDetectionConfig(UART1_LINBreakDetectionLength_TypeDef UART1_LINBreakDetectionLength);
00355 void UART1_LINCmd(FunctionalState NewState);
00356 void UART1_SmartCardCmd(FunctionalState NewState);
00357 void UART1_SmartCardNACKCmd(FunctionalState NewState);
00358 void UART1_WakeUpConfig(UART1_WakeUp_TypeDef UART1_WakeUp);
00359 void UART1_ReceiverWakeUpCmd(FunctionalState NewState);
00360 uint8_t UART1_ReceiveData8(void);
00361 uint16_t UART1_ReceiveData9(void);
00362 void UART1_SendData8(uint8_t Data);
00363 void UART1_SendData9(uint16_t Data);
00364 void UART1_SendBreak(void);
00365 void UART1_SetAddress(uint8_t UART1_Address);
00366 void UART1_SetGuardTime(uint8_t UART1_GuardTime);
00367 void UART1_SetPrescaler(uint8_t UART1_Prescaler);
00368 FlagStatus UART1_GetFlagStatus(UART1_Flag_TypeDef UART1_FLAG);
00369 void UART1_ClearFlag(UART1_Flag_TypeDef UART1_FLAG);
00370 ITStatus UART1_GetITStatus(UART1_IT_TypeDef UART1_IT);
00371 void UART1_ClearITPendingBit(UART1_IT_TypeDef UART1_IT);
00372
00373 /**
00374   * @}
00375   */
00376
00377 #endif /* __STM8S_UART1_H */
00378
00379 /**
00380   * @}
00381   */
00382
00383 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_uart2.c Source File

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stm8s_uart2.c
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00001 /**
00002   ********************************************************************************
00003   * @file    stm8s_uart2.c
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all the functions for the UART2 peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm8s_uart2.h"
00030
00031 /** @addtogroup STM8S_StdPeriph_Driver
00032   * @{
00033   */
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 /* Private macro -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038 /* Private function prototypes -----------------------------------------------*/
00039 /* Private functions ---------------------------------------------------------*/
00040 /* Public functions ----------------------------------------------------------*/
00041
00042 /**
00043   * @addtogroup UART2_Public_Functions
00044   * @{
00045   */
00046
00047 /**
00048   * @brief  Deinitializes the UART peripheral.
00049   * @param  None
00050   * @retval None
00051   */
00052
00053 void UART2_DeInit(void)
00054 {
00055   /*  Clear the Idle Line Detected bit in the status register by a read
00056   to the UART2_SR register followed by a Read to the UART2_DR register */
00057   (void) UART2->SR;
00058   (void)UART2->DR;
00059
00060   UART2->BRR2 = UART2_BRR2_RESET_VALUE;  /*  Set UART2_BRR2 to reset value 0x00 */
00061   UART2->BRR1 = UART2_BRR1_RESET_VALUE;  /*  Set UART2_BRR1 to reset value 0x00 */
00062
00063   UART2->CR1 = UART2_CR1_RESET_VALUE; /*  Set UART2_CR1 to reset value 0x00  */
00064   UART2->CR2 = UART2_CR2_RESET_VALUE; /*  Set UART2_CR2 to reset value 0x00  */
00065   UART2->CR3 = UART2_CR3_RESET_VALUE; /*  Set UART2_CR3 to reset value 0x00  */
00066   UART2->CR4 = UART2_CR4_RESET_VALUE; /*  Set UART2_CR4 to reset value 0x00  */
00067   UART2->CR5 = UART2_CR5_RESET_VALUE; /*  Set UART2_CR5 to reset value 0x00  */
00068   UART2->CR6 = UART2_CR6_RESET_VALUE; /*  Set UART2_CR6 to reset value 0x00  */
00069 }
00070
00071 /**
00072   * @brief  Initializes the UART2 according to the specified parameters.
00073   * @param  BaudRate: The baudrate.
00074   * @param  WordLength : This parameter can be any of the
00075   *         @ref UART2_WordLength_TypeDef enumeration.
00076   * @param  StopBits: This parameter can be any of the
00077   *         @ref UART2_StopBits_TypeDef enumeration.
00078   * @param  Parity: This parameter can be any of the
00079   *         @ref UART2_Parity_TypeDef enumeration.
00080   * @param  SyncMode: This parameter can be any of the
00081   *         @ref UART2_SyncMode_TypeDef values.
00082   * @param  Mode: This parameter can be any of the @ref UART2_Mode_TypeDef values
00083   * @retval None
00084   */
00085 void UART2_Init(uint32_t BaudRate, UART2_WordLength_TypeDef WordLength, UART2_StopBits_TypeDef StopBits, UART2_Parity_TypeDef Parity, UART2_SyncMode_TypeDef SyncMode, UART2_Mode_TypeDef Mode)
00086 {
00087   uint8_t BRR2_1 = 0, BRR2_2 = 0;
00088   uint32_t BaudRate_Mantissa = 0, BaudRate_Mantissa100 = 0;
00089
00090   /* Check the parameters */
00091   assert_param(IS_UART2_BAUDRATE_OK(BaudRate));
00092   assert_param(IS_UART2_WORDLENGTH_OK(WordLength));
00093   assert_param(IS_UART2_STOPBITS_OK(StopBits));
00094   assert_param(IS_UART2_PARITY_OK(Parity));
00095   assert_param(IS_UART2_MODE_OK((uint8_t)Mode));
00096   assert_param(IS_UART2_SYNCMODE_OK((uint8_t)SyncMode));
00097
00098   /* Clear the word length bit */
00099   UART2->CR1 &= (uint8_t)(~UART2_CR1_M);
00100   /* Set the word length bit according to UART2_WordLength value */
00101   UART2->CR1 |= (uint8_t)WordLength;
00102
00103   /* Clear the STOP bits */
00104   UART2->CR3 &= (uint8_t)(~UART2_CR3_STOP);
00105   /* Set the STOP bits number according to UART2_StopBits value  */
00106   UART2->CR3 |= (uint8_t)StopBits;
00107
00108   /* Clear the Parity Control bit */
00109   UART2->CR1 &= (uint8_t)(~(UART2_CR1_PCEN | UART2_CR1_PS  ));
00110   /* Set the Parity Control bit to UART2_Parity value */
00111   UART2->CR1 |= (uint8_t)Parity;
00112
00113   /* Clear the LSB mantissa of UART2DIV  */
00114   UART2->BRR1 &= (uint8_t)(~UART2_BRR1_DIVM);
00115   /* Clear the MSB mantissa of UART2DIV  */
00116   UART2->BRR2 &= (uint8_t)(~UART2_BRR2_DIVM);
00117   /* Clear the Fraction bits of UART2DIV */
00118   UART2->BRR2 &= (uint8_t)(~UART2_BRR2_DIVF);
00119
00120   /* Set the UART2 BaudRates in BRR1 and BRR2 registers according to UART2_BaudRate value */
00121   BaudRate_Mantissa    = ((uint32_t)CLK_GetClockFreq() / (BaudRate << 4));
00122   BaudRate_Mantissa100 = (((uint32_t)CLK_GetClockFreq() * 100) / (BaudRate << 4));
00123
00124   /* The fraction and MSB mantissa should be loaded in one step in the BRR2 register*/
00125   /* Set the fraction of UARTDIV  */
00126   BRR2_1 = (uint8_t)((uint8_t)(((BaudRate_Mantissa100 - (BaudRate_Mantissa * 100))
00127                                 << 4) / 100) & (uint8_t)0x0F);
00128   BRR2_2 = (uint8_t)((BaudRate_Mantissa >> 4) & (uint8_t)0xF0);
00129
00130   UART2->BRR2 = (uint8_t)(BRR2_1 | BRR2_2);
00131   /* Set the LSB mantissa of UARTDIV  */
00132   UART2->BRR1 = (uint8_t)BaudRate_Mantissa;
00133
00134   /* Disable the Transmitter and Receiver before setting the LBCL, CPOL and CPHA bits */
00135   UART2->CR2 &= (uint8_t)~(UART2_CR2_TEN | UART2_CR2_REN);
00136   /* Clear the Clock Polarity, lock Phase, Last Bit Clock pulse */
00137   UART2->CR3 &= (uint8_t)~(UART2_CR3_CPOL | UART2_CR3_CPHA | UART2_CR3_LBCL);
00138   /* Set the Clock Polarity, lock Phase, Last Bit Clock pulse */
00139   UART2->CR3 |= (uint8_t)((uint8_t)SyncMode & (uint8_t)(UART2_CR3_CPOL | \
00140     UART2_CR3_CPHA | UART2_CR3_LBCL));
00141
00142   if ((uint8_t)(Mode & UART2_MODE_TX_ENABLE))
00143   {
00144     /* Set the Transmitter Enable bit */
00145     UART2->CR2 |= (uint8_t)UART2_CR2_TEN;
00146   }
00147   else
00148   {
00149     /* Clear the Transmitter Disable bit */
00150     UART2->CR2 &= (uint8_t)(~UART2_CR2_TEN);
00151   }
00152   if ((uint8_t)(Mode & UART2_MODE_RX_ENABLE))
00153   {
00154     /* Set the Receiver Enable bit */
00155     UART2->CR2 |= (uint8_t)UART2_CR2_REN;
00156   }
00157   else
00158   {
00159     /* Clear the Receiver Disable bit */
00160     UART2->CR2 &= (uint8_t)(~UART2_CR2_REN);
00161   }
00162   /* Set the Clock Enable bit, lock Polarity, lock Phase and Last Bit Clock
00163   pulse bits according to UART2_Mode value */
00164   if ((uint8_t)(SyncMode & UART2_SYNCMODE_CLOCK_DISABLE))
00165   {
00166     /* Clear the Clock Enable bit */
00167     UART2->CR3 &= (uint8_t)(~UART2_CR3_CKEN);
00168   }
00169   else
00170   {
00171     UART2->CR3 |= (uint8_t)((uint8_t)SyncMode & UART2_CR3_CKEN);
00172   }
00173 }
00174
00175 /**
00176   * @brief  Enable the UART2 peripheral.
00177   * @param  NewState : The new state of the UART Communication.
00178   *         This parameter can be any of the @ref FunctionalState enumeration.
00179   * @retval None
00180   */
00181 void UART2_Cmd(FunctionalState NewState)
00182 {
00183   if (NewState != DISABLE)
00184   {
00185     /* UART2 Enable */
00186     UART2->CR1 &= (uint8_t)(~UART2_CR1_UARTD);
00187   }
00188   else
00189   {
00190     /* UART2 Disable */
00191     UART2->CR1 |= UART2_CR1_UARTD;
00192   }
00193 }
00194
00195 /**
00196   * @brief  Enables or disables the specified UART2 interrupts.
00197   * @param  UART2_IT specifies the UART2 interrupt sources to be enabled or disabled.
00198   *         This parameter can be one of the following values:
00199   *         - UART2_IT_LBDF:  LIN Break detection interrupt
00200   *         - UART2_IT_LHDF:  LIN Break detection interrupt
00201   *         - UART2_IT_TXE:  Transmit Data Register empty interrupt
00202   *         - UART2_IT_TC:   Transmission complete interrupt
00203   *         - UART2_IT_RXNE_OR: Receive Data register not empty/Over run error interrupt
00204   *         - UART2_IT_IDLE: Idle line detection interrupt
00205   *         - UART2_IT_PE:   Parity Error interrupt
00206   * @param  NewState new state of the specified UART2 interrupts.
00207   *         This parameter can be: ENABLE or DISABLE.
00208   * @retval None
00209   */
00210 void UART2_ITConfig(UART2_IT_TypeDef UART2_IT, FunctionalState NewState)
00211 {
00212   uint8_t uartreg = 0, itpos = 0x00;
00213
00214   /* Check the parameters */
00215   assert_param(IS_UART2_CONFIG_IT_OK(UART2_IT));
00216   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00217
00218   /* Get the UART2 register index */
00219   uartreg = (uint8_t)((uint16_t)UART2_IT >> 0x08);
00220
00221   /* Get the UART2 IT index */
00222   itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)UART2_IT & (uint8_t)0x0F));
00223
00224   if (NewState != DISABLE)
00225   {
00226     /* Enable the Interrupt bits according to UART2_IT mask */
00227     if (uartreg == 0x01)
00228     {
00229       UART2->CR1 |= itpos;
00230     }
00231     else if (uartreg == 0x02)
00232     {
00233       UART2->CR2 |= itpos;
00234     }
00235     else if (uartreg == 0x03)
00236     {
00237       UART2->CR4 |= itpos;
00238     }
00239     else
00240     {
00241       UART2->CR6 |= itpos;
00242     }
00243   }
00244   else
00245   {
00246     /* Disable the interrupt bits according to UART2_IT mask */
00247     if (uartreg == 0x01)
00248     {
00249       UART2->CR1 &= (uint8_t)(~itpos);
00250     }
00251     else if (uartreg == 0x02)
00252     {
00253       UART2->CR2 &= (uint8_t)(~itpos);
00254     }
00255     else if (uartreg == 0x03)
00256     {
00257       UART2->CR4 &= (uint8_t)(~itpos);
00258     }
00259     else
00260     {
00261       UART2->CR6 &= (uint8_t)(~itpos);
00262     }
00263   }
00264 }
00265
00266 /**
00267   * @brief  Configures the UART2’s IrDA interface.
00268   * @param  UART2_IrDAMode specifies the IrDA mode.
00269   *         This parameter can be any of the @ref UART2_IrDAMode_TypeDef values.
00270   * @retval None
00271   */
00272 void UART2_IrDAConfig(UART2_IrDAMode_TypeDef UART2_IrDAMode)
00273 {
00274   assert_param(IS_UART2_IRDAMODE_OK(UART2_IrDAMode));
00275
00276   if (UART2_IrDAMode != UART2_IRDAMODE_NORMAL)
00277   {
00278     UART2->CR5 |= UART2_CR5_IRLP;
00279   }
00280   else
00281   {
00282     UART2->CR5 &= ((uint8_t)~UART2_CR5_IRLP);
00283   }
00284 }
00285
00286 /**
00287   * @brief  Enables or disables the UART2’s IrDA interface.
00288   * @param  NewState new state of the IrDA mode.
00289   *         This parameter can be: ENABLE or DISABLE.
00290   * @retval None
00291   */
00292 void UART2_IrDACmd(FunctionalState NewState)
00293 {
00294   /* Check parameters */
00295   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00296
00297   if (NewState != DISABLE)
00298   {
00299     /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
00300     UART2->CR5 |= UART2_CR5_IREN;
00301   }
00302   else
00303   {
00304     /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
00305     UART2->CR5 &= ((uint8_t)~UART2_CR5_IREN);
00306   }
00307 }
00308
00309 /**
00310   * @brief  Sets the UART2 LIN Break detection length.
00311   * @param  UART2_LINBreakDetectionLength specifies the LIN break detection length.
00312   *         This parameter can be any of the
00313   *         @ref UART2_LINBreakDetectionLength_TypeDef values.
00314   * @retval None
00315   */
00316 void UART2_LINBreakDetectionConfig(UART2_LINBreakDetectionLength_TypeDef UART2_LINBreakDetectionLength)
00317 {
00318   /* Check parameters */
00319   assert_param(IS_UART2_LINBREAKDETECTIONLENGTH_OK(UART2_LINBreakDetectionLength));
00320
00321   if (UART2_LINBreakDetectionLength != UART2_LINBREAKDETECTIONLENGTH_10BITS)
00322   {
00323     UART2->CR4 |= UART2_CR4_LBDL;
00324   }
00325   else
00326   {
00327     UART2->CR4 &= ((uint8_t)~UART2_CR4_LBDL);
00328   }
00329 }
00330
00331 /**
00332   * @brief  Configure the UART2 peripheral.
00333   * @param  UART2_Mode specifies the LIN mode.
00334   *         This parameter can be any of the @ref UART2_LinMode_TypeDef values.
00335   * @param  UART2_Autosync specifies the LIN automatic resynchronization mode.
00336   *         This parameter can be any of the @ref UART2_LinAutosync_TypeDef values.
00337   * @param  UART2_DivUp specifies the LIN divider update method.
00338   *         This parameter can be any of the @ref UART2_LinDivUp_TypeDef values.
00339   * @retval None
00340   */
00341 void UART2_LINConfig(UART2_LinMode_TypeDef UART2_Mode,
00342                      UART2_LinAutosync_TypeDef UART2_Autosync,
00343                      UART2_LinDivUp_TypeDef UART2_DivUp)
00344 {
00345   /* Check parameters */
00346   assert_param(IS_UART2_SLAVE_OK(UART2_Mode));
00347   assert_param(IS_UART2_AUTOSYNC_OK(UART2_Autosync));
00348   assert_param(IS_UART2_DIVUP_OK(UART2_DivUp));
00349
00350   if (UART2_Mode != UART2_LIN_MODE_MASTER)
00351   {
00352     UART2->CR6 |=  UART2_CR6_LSLV;
00353   }
00354   else
00355   {
00356     UART2->CR6 &= ((uint8_t)~UART2_CR6_LSLV);
00357   }
00358
00359   if (UART2_Autosync != UART2_LIN_AUTOSYNC_DISABLE)
00360   {
00361     UART2->CR6 |=  UART2_CR6_LASE ;
00362   }
00363   else
00364   {
00365     UART2->CR6 &= ((uint8_t)~ UART2_CR6_LASE );
00366   }
00367
00368   if (UART2_DivUp != UART2_LIN_DIVUP_LBRR1)
00369   {
00370     UART2->CR6 |=  UART2_CR6_LDUM;
00371   }
00372   else
00373   {
00374     UART2->CR6 &= ((uint8_t)~ UART2_CR6_LDUM);
00375   }
00376 }
00377
00378 /**
00379   * @brief  Enables or disables the UART2 LIN mode.
00380   * @param  NewState is new state of the UART2 LIN mode.
00381   *         This parameter can be ENABLE or DISABLE
00382   * @retval None
00383   */
00384 void UART2_LINCmd(FunctionalState NewState)
00385 {
00386   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00387
00388   if (NewState != DISABLE)
00389   {
00390     /* Enable the LIN mode by setting the LINE bit in the CR2 register */
00391     UART2->CR3 |= UART2_CR3_LINEN;
00392   }
00393   else
00394   {
00395     /* Disable the LIN mode by clearing the LINE bit in the CR2 register */
00396     UART2->CR3 &= ((uint8_t)~UART2_CR3_LINEN);
00397   }
00398 }
00399
00400 /**
00401   * @brief  Enables or disables the UART2 Smart Card mode.
00402   * @param  NewState: new state of the Smart Card mode.
00403   *         This parameter can be: ENABLE or DISABLE.
00404   * @retval None
00405   */
00406 void UART2_SmartCardCmd(FunctionalState NewState)
00407 {
00408   /* Check parameters */
00409   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00410
00411   if (NewState != DISABLE)
00412   {
00413     /* Enable the SC mode by setting the SCEN bit in the CR5 register */
00414     UART2->CR5 |= UART2_CR5_SCEN;
00415   }
00416   else
00417   {
00418     /* Disable the SC mode by clearing the SCEN bit in the CR5 register */
00419     UART2->CR5 &= ((uint8_t)(~UART2_CR5_SCEN));
00420   }
00421 }
00422
00423 /**
00424   * @brief  Enables or disables NACK transmission.
00425   * @param  NewState: new state of the Smart Card mode.
00426   *         This parameter can be: ENABLE or DISABLE.
00427   * @retval None
00428   */
00429 void UART2_SmartCardNACKCmd(FunctionalState NewState)
00430 {
00431   /* Check parameters */
00432   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00433
00434   if (NewState != DISABLE)
00435   {
00436     /* Enable the NACK transmission by setting the NACK bit in the CR5 register */
00437     UART2->CR5 |= UART2_CR5_NACK;
00438   }
00439   else
00440   {
00441     /* Disable the NACK transmission by clearing the NACK bit in the CR5 register */
00442     UART2->CR5 &= ((uint8_t)~(UART2_CR5_NACK));
00443   }
00444 }
00445
00446 /**
00447   * @brief  Selects the UART2 WakeUp method.
00448   * @param  UART2_WakeUp: specifies the UART2 wakeup method.
00449   *         This parameter can be any of the @ref UART2_WakeUp_TypeDef values.
00450   * @retval None
00451   */
00452 void UART2_WakeUpConfig(UART2_WakeUp_TypeDef UART2_WakeUp)
00453 {
00454   assert_param(IS_UART2_WAKEUP_OK(UART2_WakeUp));
00455
00456   UART2->CR1 &= ((uint8_t)~UART2_CR1_WAKE);
00457   UART2->CR1 |= (uint8_t)UART2_WakeUp;
00458 }
00459
00460 /**
00461   * @brief  Determines if the UART2 is in mute mode or not.
00462   * @param  NewState: new state of the UART2 mode.
00463   *         This parameter can be ENABLE or DISABLE
00464   * @retval None
00465   */
00466 void UART2_ReceiverWakeUpCmd(FunctionalState NewState)
00467 {
00468   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00469
00470   if (NewState != DISABLE)
00471   {
00472     /* Enable the mute mode UART2 by setting the RWU bit in the CR2 register */
00473     UART2->CR2 |= UART2_CR2_RWU;
00474   }
00475   else
00476   {
00477     /* Disable the mute mode UART2 by clearing the RWU bit in the CR1 register */
00478     UART2->CR2 &= ((uint8_t)~UART2_CR2_RWU);
00479   }
00480 }
00481
00482 /**
00483   * @brief  Returns the most recent received data by the UART2 peripheral.
00484   * @param  None
00485   * @retval Received Data
00486   */
00487 uint8_t UART2_ReceiveData8(void)
00488 {
00489   return ((uint8_t)UART2->DR);
00490 }
00491
00492 /**
00493   * @brief  Returns the most recent received data by the UART2 peripheral.
00494   * @param  None
00495   * @retval Received Data
00496   */
00497 uint16_t UART2_ReceiveData9(void)
00498 {
00499   uint16_t temp = 0;
00500
00501   temp = ((uint16_t)(((uint16_t)((uint16_t)UART2->CR1 & (uint16_t)UART2_CR1_R8)) << 1));
00502
00503   return (uint16_t)((((uint16_t)UART2->DR) | temp) & ((uint16_t)0x01FF));
00504 }
00505
00506 /**
00507   * @brief  Transmits 8 bit data through the UART2 peripheral.
00508   * @param  Data: the data to transmit.
00509   * @retval None
00510   */
00511 void UART2_SendData8(uint8_t Data)
00512 {
00513   /* Transmit Data */
00514   UART2->DR = Data;
00515 }
00516
00517 /**
00518   * @brief  Transmits 9 bit data through the UART2 peripheral.
00519   * @param  Data: the data to transmit.
00520   * @retval None
00521   */
00522 void UART2_SendData9(uint16_t Data)
00523 {
00524   /* Clear the transmit data bit 8 */
00525   UART2->CR1 &= ((uint8_t)~UART2_CR1_T8);
00526
00527   /* Write the transmit data bit [8] */
00528   UART2->CR1 |= (uint8_t)(((uint8_t)(Data >> 2)) & UART2_CR1_T8);
00529
00530   /* Write the transmit data bit [0:7] */
00531   UART2->DR   = (uint8_t)(Data);
00532 }
00533
00534 /**
00535   * @brief  Transmits break characters.
00536   * @param  None
00537   * @retval None
00538   */
00539 void UART2_SendBreak(void)
00540 {
00541   UART2->CR2 |= UART2_CR2_SBK;
00542 }
00543
00544 /**
00545   * @brief  Sets the address of the UART2 node.
00546   * @param  UART2_Address: Indicates the address of the UART2 node.
00547   * @retval None
00548   */
00549 void UART2_SetAddress(uint8_t UART2_Address)
00550 {
00551   /*assert_param for x UART2_Address*/
00552   assert_param(IS_UART2_ADDRESS_OK(UART2_Address));
00553
00554   /* Clear the UART2 address */
00555   UART2->CR4 &= ((uint8_t)~UART2_CR4_ADD);
00556   /* Set the UART2 address node */
00557   UART2->CR4 |= UART2_Address;
00558 }
00559
00560 /**
00561   * @brief  Sets the specified UART2 guard time.
00562   * @note   SmartCard Mode should be Enabled
00563   * @param  UART2_GuardTime: specifies the guard time.
00564   * @retval None
00565   */
00566 void UART2_SetGuardTime(uint8_t UART2_GuardTime)
00567 {
00568   /* Set the UART2 guard time */
00569   UART2->GTR = UART2_GuardTime;
00570 }
00571
00572 /**
00573   * @brief  Sets the system clock prescaler.
00574   * @note   IrDA Low Power mode or smartcard mode should be enabled
00575   * @note   This function is related to SmartCard and IrDa mode.
00576   * @param  UART2_Prescaler: specifies the prescaler clock.
00577   *         This parameter can be one of the following values:
00578   *         @par IrDA Low Power Mode
00579   *         The clock source is divided by the value given in the register (8 bits)
00580   *         - 0000 0000 Reserved
00581   *         - 0000 0001 divides the clock source by 1
00582   *         - 0000 0010 divides the clock source by 2
00583   *         - ...
00584   *        @par Smart Card Mode
00585   *        The clock source is divided by the value given in the register
00586   *        (5 significant bits) multiped by 2
00587   *         - 0 0000 Reserved
00588   *         - 0 0001 divides the clock source by 2
00589   *         - 0 0010 divides the clock source by 4
00590   *         - 0 0011 divides the clock source by 6
00591   *         - ...
00592   * @retval None
00593   */
00594 void UART2_SetPrescaler(uint8_t UART2_Prescaler)
00595 {
00596   /* Load the UART2 prescaler value*/
00597   UART2->PSCR = UART2_Prescaler;
00598 }
00599
00600 /**
00601   * @brief  Checks whether the specified UART2 flag is set or not.
00602   * @param  UART2_FLAG specifies the flag to check.
00603   *         This parameter can be any of the @ref UART2_Flag_TypeDef enumeration.
00604   * @retval FlagStatus (SET or RESET)
00605   */
00606 FlagStatus UART2_GetFlagStatus(UART2_Flag_TypeDef UART2_FLAG)
00607 {
00608   FlagStatus status = RESET;
00609
00610   /* Check parameters */
00611   assert_param(IS_UART2_FLAG_OK(UART2_FLAG));
00612
00613   /* Check the status of the specified UART2 flag*/
00614   if (UART2_FLAG == UART2_FLAG_LBDF)
00615   {
00616     if ((UART2->CR4 & (uint8_t)UART2_FLAG) != (uint8_t)0x00)
00617     {
00618       /* UART2_FLAG is set*/
00619       status = SET;
00620     }
00621     else
00622     {
00623       /* UART2_FLAG is reset*/
00624       status = RESET;
00625     }
00626   }
00627   else if (UART2_FLAG == UART2_FLAG_SBK)
00628   {
00629     if ((UART2->CR2 & (uint8_t)UART2_FLAG) != (uint8_t)0x00)
00630     {
00631       /* UART2_FLAG is set*/
00632       status = SET;
00633     }
00634     else
00635     {
00636       /* UART2_FLAG is reset*/
00637       status = RESET;
00638     }
00639   }
00640   else if ((UART2_FLAG == UART2_FLAG_LHDF) || (UART2_FLAG == UART2_FLAG_LSF))
00641   {
00642     if ((UART2->CR6 & (uint8_t)UART2_FLAG) != (uint8_t)0x00)
00643     {
00644       /* UART2_FLAG is set*/
00645       status = SET;
00646     }
00647     else
00648     {
00649       /* UART2_FLAG is reset*/
00650       status = RESET;
00651     }
00652   }
00653   else
00654   {
00655     if ((UART2->SR & (uint8_t)UART2_FLAG) != (uint8_t)0x00)
00656     {
00657       /* UART2_FLAG is set*/
00658       status = SET;
00659     }
00660     else
00661     {
00662       /* UART2_FLAG is reset*/
00663       status = RESET;
00664     }
00665   }
00666
00667   /* Return the UART2_FLAG status*/
00668   return  status;
00669 }
00670
00671 /**
00672   * @brief  Clears the UART2 flags.
00673   * @param  UART2_FLAG specifies the flag to clear
00674   *         This parameter can be any combination of the following values:
00675   *         - UART2_FLAG_LBDF: LIN Break detection flag.
00676   *         - UART2_FLAG_LHDF: LIN Header detection flag.
00677   *         - UART2_FLAG_LSF: LIN synchrone field flag.
00678   *         - UART2_FLAG_RXNE: Receive data register not empty flag.
00679   * @note:
00680   *         - PE (Parity error), FE (Framing error), NE (Noise error),
00681   *           OR (OverRun error) and IDLE (Idle line detected) flags are cleared
00682   *           by software sequence: a read operation to UART2_SR register
00683   *           (UART2_GetFlagStatus())followed by a read operation to UART2_DR
00684   *           register(UART2_ReceiveData8() or UART2_ReceiveData9()).
00685   *
00686   *         - RXNE flag can be also cleared by a read to the UART2_DR register
00687   *           (UART2_ReceiveData8()or UART2_ReceiveData9()).
00688   *
00689   *         - TC flag can be also cleared by software sequence: a read operation
00690   *           to UART2_SR register (UART2_GetFlagStatus()) followed by a write
00691   *           operation to UART2_DR register (UART2_SendData8() or UART2_SendData9()).
00692   *
00693   *         - TXE flag is cleared only by a write to the UART2_DR register
00694   *           (UART2_SendData8() or UART2_SendData9()).
00695   *
00696   *         - SBK flag is cleared during the stop bit of break.
00697   * @retval None
00698   */
00699 void UART2_ClearFlag(UART2_Flag_TypeDef UART2_FLAG)
00700 {
00701   assert_param(IS_UART2_CLEAR_FLAG_OK(UART2_FLAG));
00702
00703   /*  Clear the Receive Register Not Empty flag */
00704   if (UART2_FLAG == UART2_FLAG_RXNE)
00705   {
00706     UART2->SR = (uint8_t)~(UART2_SR_RXNE);
00707   }
00708   /*  Clear the LIN Break Detection flag */
00709   else if (UART2_FLAG == UART2_FLAG_LBDF)
00710   {
00711     UART2->CR4 &= (uint8_t)(~UART2_CR4_LBDF);
00712   }
00713   /*  Clear the LIN Header Detection Flag */
00714   else if (UART2_FLAG == UART2_FLAG_LHDF)
00715   {
00716     UART2->CR6 &= (uint8_t)(~UART2_CR6_LHDF);
00717   }
00718   /*  Clear the LIN Synch Field flag */
00719   else
00720   {
00721     UART2->CR6 &= (uint8_t)(~UART2_CR6_LSF);
00722   }
00723 }
00724
00725 /**
00726   * @brief  Checks whether the specified UART2 interrupt has occurred or not.
00727   * @param  UART2_IT: Specifies the UART2 interrupt pending bit to check.
00728   *         This parameter can be one of the following values:
00729   *         - UART2_IT_LBDF:  LIN Break detection interrupt
00730   *         - UART2_IT_TXE:  Transmit Data Register empty interrupt
00731   *         - UART2_IT_TC:   Transmission complete interrupt
00732   *         - UART2_IT_RXNE: Receive Data register not empty interrupt
00733   *         - UART2_IT_IDLE: Idle line detection interrupt
00734   *         - UART2_IT_OR:  OverRun Error interrupt
00735   *         - UART2_IT_PE:   Parity Error interrupt
00736   * @retval The state of UART2_IT (SET or RESET).
00737   */
00738 ITStatus UART2_GetITStatus(UART2_IT_TypeDef UART2_IT)
00739 {
00740   ITStatus pendingbitstatus = RESET;
00741   uint8_t itpos = 0;
00742   uint8_t itmask1 = 0;
00743   uint8_t itmask2 = 0;
00744   uint8_t enablestatus = 0;
00745
00746   /* Check parameters */
00747   assert_param(IS_UART2_GET_IT_OK(UART2_IT));
00748
00749   /* Get the UART2 IT index*/
00750   itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)UART2_IT & (uint8_t)0x0F));
00751   /* Get the UART2 IT index*/
00752   itmask1 = (uint8_t)((uint8_t)UART2_IT >> (uint8_t)4);
00753   /* Set the IT mask*/
00754   itmask2 = (uint8_t)((uint8_t)1 << itmask1);
00755
00756   /* Check the status of the specified UART2 pending bit*/
00757   if (UART2_IT == UART2_IT_PE)
00758   {
00759     /* Get the UART2_ITPENDINGBIT enable bit status*/
00760     enablestatus = (uint8_t)((uint8_t)UART2->CR1 & itmask2);
00761     /* Check the status of the specified UART2 interrupt*/
00762
00763     if (((UART2->SR & itpos) != (uint8_t)0x00) && enablestatus)
00764     {
00765       /* Interrupt occurred*/
00766       pendingbitstatus = SET;
00767     }
00768     else
00769     {
00770       /* Interrupt not occurred*/
00771       pendingbitstatus = RESET;
00772     }
00773   }
00774   else if (UART2_IT == UART2_IT_LBDF)
00775   {
00776     /* Get the UART2_IT enable bit status*/
00777     enablestatus = (uint8_t)((uint8_t)UART2->CR4 & itmask2);
00778     /* Check the status of the specified UART2 interrupt*/
00779     if (((UART2->CR4 & itpos) != (uint8_t)0x00) && enablestatus)
00780     {
00781       /* Interrupt occurred*/
00782       pendingbitstatus = SET;
00783     }
00784     else
00785     {
00786       /* Interrupt not occurred*/
00787       pendingbitstatus = RESET;
00788     }
00789   }
00790   else if (UART2_IT == UART2_IT_LHDF)
00791   {
00792     /* Get the UART2_IT enable bit status*/
00793     enablestatus = (uint8_t)((uint8_t)UART2->CR6 & itmask2);
00794     /* Check the status of the specified UART2 interrupt*/
00795     if (((UART2->CR6 & itpos) != (uint8_t)0x00) && enablestatus)
00796     {
00797       /* Interrupt occurred*/
00798       pendingbitstatus = SET;
00799     }
00800     else
00801     {
00802       /* Interrupt not occurred*/
00803       pendingbitstatus = RESET;
00804     }
00805   }
00806   else
00807   {
00808     /* Get the UART2_IT enable bit status*/
00809     enablestatus = (uint8_t)((uint8_t)UART2->CR2 & itmask2);
00810     /* Check the status of the specified UART2 interrupt*/
00811     if (((UART2->SR & itpos) != (uint8_t)0x00) && enablestatus)
00812     {
00813       /* Interrupt occurred*/
00814       pendingbitstatus = SET;
00815     }
00816     else
00817     {
00818       /* Interrupt not occurred*/
00819       pendingbitstatus = RESET;
00820     }
00821   }
00822   /* Return the UART2_IT status*/
00823   return  pendingbitstatus;
00824 }
00825
00826 /**
00827   * @brief  Clears the UART2 pending flags.
00828   * @param  UART2_IT specifies the pending bit to clear
00829   *         This parameter can be one of the following values:
00830   *         - UART2_IT_LBDF:  LIN Break detection interrupt
00831   *         - UART2_IT_LHDF:  LIN Header detection interrupt
00832   *         - UART2_IT_RXNE: Receive Data register not empty interrupt.
00833   * @note
00834   *         - PE (Parity error), FE (Framing error), NE (Noise error),
00835   *           OR (OverRun error) and IDLE (Idle line detected) pending bits are
00836   *           cleared by software sequence: a read operation to UART2_SR register
00837   *           (UART2_GetITStatus()) followed by a read operation to UART2_DR register
00838   *           (UART2_ReceiveData8() or UART2_ReceiveData9()).
00839   *
00840   *         - RXNE pending bit can be also cleared by a read to the UART2_DR
00841   *           register (UART2_ReceiveData8() or UART2_ReceiveData9()).
00842   *
00843   *         - TC (Transmit complete) pending bit can be cleared by software
00844   *           sequence: a read operation to UART2_SR register
00845   *           (UART2_GetITStatus()) followed by a write operation to UART2_DR
00846   *           register (UART2_SendData8()or UART2_SendData9()).
00847   *
00848   *         - TXE pending bit is cleared only by a write to the UART2_DR register
00849   *           (UART2_SendData8() or UART2_SendData9()).
00850   * @retval None
00851   */
00852 void UART2_ClearITPendingBit(UART2_IT_TypeDef UART2_IT)
00853 {
00854   assert_param(IS_UART2_CLEAR_IT_OK(UART2_IT));
00855
00856   /*  Clear the Receive Register Not Empty pending bit */
00857   if (UART2_IT == UART2_IT_RXNE)
00858   {
00859     UART2->SR = (uint8_t)~(UART2_SR_RXNE);
00860   }
00861   /*  Clear the LIN Break Detection pending bit */
00862   else if (UART2_IT == UART2_IT_LBDF)
00863   {
00864     UART2->CR4 &= (uint8_t)~(UART2_CR4_LBDF);
00865   }
00866   /*  Clear the LIN Header Detection pending bit */
00867   else
00868   {
00869     UART2->CR6 &= (uint8_t)(~UART2_CR6_LHDF);
00870   }
00871 }
00872
00873 /**
00874   * @}
00875   */
00876
00877 /**
00878   * @}
00879   */
00880
00881
00882 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_uart2.h Source File

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stm8s_uart2.h
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00001 /**
00002   ********************************************************************************
00003   * @file    stm8s_uart2.h
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all functions prototypes and macros for the UART2 peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Define to prevent recursive inclusion -------------------------------------*/
00029 #ifndef __STM8S_UART2_H
00030 #define __STM8S_UART2_H
00031
00032 /* Includes ------------------------------------------------------------------*/
00033 #include "stm8s.h"
00034
00035 /** @addtogroup STM8S_StdPeriph_Driver
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040
00041 /** @addtogroup UART2_Exported_Types
00042   * @{
00043   */
00044
00045 /**
00046   * @brief  UART2 Irda Modes
00047   */
00048
00049 typedef enum { UART2_IRDAMODE_NORMAL     = (uint8_t)0x00, /**< 0x00 Irda Normal Mode   */
00050                UART2_IRDAMODE_LOWPOWER   = (uint8_t)0x01  /**< 0x01 Irda Low Power Mode */
00051
00052              } UART2_IrDAMode_TypeDef;
00053
00054 /**
00055   * @brief  UART2 WakeUP Modes
00056   */
00057
00058 typedef enum { UART2_WAKEUP_IDLELINE       = (uint8_t)0x00, /**< 0x01 Idle Line wake up */
00059                UART2_WAKEUP_ADDRESSMARK    = (uint8_t)0x08  /**< 0x02 Address Mark wake up */
00060              } UART2_WakeUp_TypeDef;
00061
00062
00063 /**
00064   * @brief  UART2 LIN Break detection length possible values
00065   */
00066 typedef enum { UART2_LINBREAKDETECTIONLENGTH_10BITS = (uint8_t)0x00, /**< 0x01 10 bits Lin Break detection */
00067                UART2_LINBREAKDETECTIONLENGTH_11BITS = (uint8_t)0x01  /**< 0x02 11 bits Lin Break detection */
00068              } UART2_LINBreakDetectionLength_TypeDef;
00069
00070 /**
00071   * @brief  UART2 stop bits possible values
00072   */
00073
00074 typedef enum { UART2_STOPBITS_1   = (uint8_t)0x00,    /**< One stop bit is  transmitted at the end of frame*/
00075                UART2_STOPBITS_0_5 = (uint8_t)0x10,    /**< Half stop bits is transmitted at the end of frame*/
00076                UART2_STOPBITS_2   = (uint8_t)0x20,    /**< Two stop bits are  transmitted at the end of frame*/
00077                UART2_STOPBITS_1_5 = (uint8_t)0x30     /**< One and half stop bits*/
00078              } UART2_StopBits_TypeDef;
00079
00080
00081 /**
00082   * @brief  UART2 parity possible values
00083   */
00084 typedef enum { UART2_PARITY_NO     = (uint8_t)0x00,      /**< No Parity*/
00085                UART2_PARITY_EVEN   = (uint8_t)0x04,      /**< Even Parity*/
00086                UART2_PARITY_ODD    = (uint8_t)0x06       /**< Odd Parity*/
00087              } UART2_Parity_TypeDef;
00088 /**
00089   * @brief  UART2 Mode possible values
00090   */
00091 typedef enum { UART2_LIN_MODE_MASTER  = (uint8_t)0x00, /**<  LIN Master Mode*/
00092                UART2_LIN_MODE_SLAVE   = (uint8_t)0x01  /**<  LIN Slave Mode*/
00093              } UART2_LinMode_TypeDef;
00094 /**
00095   * @brief  UART2 automatic resynchronisation possible values
00096   */
00097 typedef enum { UART2_LIN_AUTOSYNC_DISABLE   = (uint8_t)0x00,  /**< LIN Autosynchronization Disable*/
00098                UART2_LIN_AUTOSYNC_ENABLE    = (uint8_t)0x01   /**< LIN Autosynchronization Enable*/
00099              } UART2_LinAutosync_TypeDef;
00100 /**
00101   * @brief  UART2 Divider Update Method possible values
00102   */
00103 typedef enum { UART2_LIN_DIVUP_LBRR1    = (uint8_t)0x00, /**<  LIN LDIV is updated as soon as LBRR1 is written*/
00104                UART2_LIN_DIVUP_NEXTRXNE = (uint8_t)0x01  /**<  LIN LDIV is updated at the next received character*/
00105              } UART2_LinDivUp_TypeDef;
00106
00107 /**
00108   * @brief  UART2 Synchrone modes
00109   */
00110 typedef enum { UART2_SYNCMODE_CLOCK_DISABLE    = (uint8_t)0x80, /**< 0x80 Sync mode Disable, SLK pin Disable */
00111                UART2_SYNCMODE_CLOCK_ENABLE     = (uint8_t)0x08, /**< 0x08 Sync mode Enable, SLK pin Enable     */
00112                UART2_SYNCMODE_CPOL_LOW         = (uint8_t)0x40, /**< 0x40 Steady low value on SCLK pin outside transmission window */
00113                UART2_SYNCMODE_CPOL_HIGH        = (uint8_t)0x04, /**< 0x04 Steady high value on SCLK pin outside transmission window */
00114                UART2_SYNCMODE_CPHA_MIDDLE      = (uint8_t)0x20, /**< 0x20 SCLK clock line activated in middle of data bit     */
00115                UART2_SYNCMODE_CPHA_BEGINING    = (uint8_t)0x02, /**< 0x02 SCLK clock line activated at beginning of data bit  */
00116                UART2_SYNCMODE_LASTBIT_DISABLE  = (uint8_t)0x10, /**< 0x10 The clock pulse of the last data bit is not output to the SCLK pin */
00117                UART2_SYNCMODE_LASTBIT_ENABLE   = (uint8_t)0x01  /**< 0x01 The clock pulse of the last data bit is output to the SCLK pin */
00118              } UART2_SyncMode_TypeDef;
00119
00120 /**
00121   * @brief  UART2 Word length possible values
00122   */
00123 typedef enum { UART2_WORDLENGTH_8D = (uint8_t)0x00,/**< 0x00 8 bits Data  */
00124                UART2_WORDLENGTH_9D = (uint8_t)0x10 /**< 0x10 9 bits Data  */
00125              } UART2_WordLength_TypeDef;
00126
00127 /**
00128   * @brief  UART2 Mode possible values
00129   */
00130 typedef enum { UART2_MODE_RX_ENABLE     = (uint8_t)0x08,  /**< 0x08 Receive Enable */
00131                UART2_MODE_TX_ENABLE     = (uint8_t)0x04,  /**< 0x04 Transmit Enable */
00132                UART2_MODE_TX_DISABLE    = (uint8_t)0x80,  /**< 0x80 Transmit Disable */
00133                UART2_MODE_RX_DISABLE    = (uint8_t)0x40,  /**< 0x40 Single-wire Half-duplex mode */
00134                UART2_MODE_TXRX_ENABLE   = (uint8_t)0x0C  /**< 0x0C Transmit Enable and Receive Enable */
00135              } UART2_Mode_TypeDef;
00136 /**
00137   * @brief  UART2 Flag possible values
00138   */
00139 typedef enum
00140 {
00141   UART2_FLAG_TXE          = (uint16_t)0x0080, /*!< Transmit Data Register Empty flag */
00142   UART2_FLAG_TC           = (uint16_t)0x0040, /*!< Transmission Complete flag */
00143   UART2_FLAG_RXNE         = (uint16_t)0x0020, /*!< Read Data Register Not Empty flag */
00144   UART2_FLAG_IDLE         = (uint16_t)0x0010, /*!< Idle line detected flag */
00145   UART2_FLAG_OR_LHE       = (uint16_t)0x0008, /*!< OverRun error flag */
00146   UART2_FLAG_NF           = (uint16_t)0x0004, /*!< Noise error flag */
00147   UART2_FLAG_FE           = (uint16_t)0x0002, /*!< Framing Error flag */
00148   UART2_FLAG_PE           = (uint16_t)0x0001, /*!< Parity Error flag */
00149   UART2_FLAG_SBK          = (uint16_t)0x0101,  /**< Send Break Complete interrupt flag */
00150   UART2_FLAG_LBDF         = (uint16_t)0x0210, /**< LIN Break Detection Flag           */
00151   UART2_FLAG_LHDF         = (uint16_t)0x0302, /**< LIN Header Detection Flag*/
00152   UART2_FLAG_LSF          = (uint16_t)0x0301  /**< LIN Sync Field Flag*/
00153 } UART2_Flag_TypeDef;
00154
00155 /**
00156   * @brief  UART2 Interrupt definition
00157   * UART2_IT possible values
00158   * Elements values convention: 0xZYX
00159   * X: Position of the corresponding Interrupt
00160   *   - For the following values, X means the interrupt position in the CR2 register.
00161   *     UART2_IT_TXE
00162   *     UART2_IT_TC
00163   *     UART2_IT_RXNE
00164   *     UART2_IT_IDLE
00165   *     UART2_IT_OR
00166   *   - For the UART2_IT_PE value, X means the flag position in the CR1 register.
00167   *   - For the UART2_IT_LBDF value, X means the flag position in the CR4 register.
00168   *   - For the UART2_IT_LHDF value, X means the flag position in the CR6 register.
00169   * Y: Flag position
00170   *  - For the following values, Y means the flag (pending bit) position in the SR register.
00171   *     UART2_IT_TXE
00172   *     UART2_IT_TC
00173   *     UART2_IT_RXNE
00174   *     UART2_IT_IDLE
00175   *     UART2_IT_OR
00176   *     UART2_IT_PE
00177   *  - For the UART2_IT_LBDF value, Y means the flag position in the CR4 register.
00178   *  - For the UART2_IT_LHDF value, Y means the flag position in the CR6 register.
00179   * Z: Register index: indicate in which register the dedicated interrupt source is:
00180   *  - 1==> CR1 register
00181   *  - 2==> CR2 register
00182   *  - 3==> CR4 register
00183   *  - 4==> CR6 register
00184   */
00185 typedef enum { UART2_IT_TXE        = (uint16_t)0x0277, /**< Transmit interrupt */
00186                UART2_IT_TC         = (uint16_t)0x0266, /**< Transmission Complete interrupt */
00187                UART2_IT_RXNE       = (uint16_t)0x0255, /**< Data Register Not Empty interrupt */
00188                UART2_IT_IDLE       = (uint16_t)0x0244, /**< Idle line detected interrupt */
00189                UART2_IT_OR         = (uint16_t)0x0235, /**< OverRun error interrupt */
00190                UART2_IT_PE         = (uint16_t)0x0100, /**< Parity Error interrupt */
00191                UART2_IT_LBDF       = (uint16_t)0x0346, /**< LIN Break Detection interrupt */
00192                UART2_IT_LHDF       = (uint16_t)0x0412, /**< LIN Header Detection interrupt*/
00193                UART2_IT_RXNE_OR    = (uint16_t)0x0205  /*!< Receive/Overrun interrupt */
00194              } UART2_IT_TypeDef;
00195
00196 /**
00197   * @}
00198   */
00199
00200 /* Exported constants --------------------------------------------------------*/
00201 /* Exported macros ------------------------------------------------------------*/
00202
00203 /* Private macros ------------------------------------------------------------*/
00204
00205 /** @addtogroup UART2_Private_Macros
00206   * @{
00207   */
00208
00209 /**
00210   * @brief  Macro used by the assert function to check the different functions parameters.
00211   */
00212
00213 /**
00214  * @brief Macro used by the assert_param function in order to check the different
00215  *        sensitivity values for the MODEs possible combination should be one of
00216  *        the following.
00217  */
00218
00219 #define IS_UART2_MODE_OK(Mode) \
00220   (((Mode) == (uint8_t)UART2_MODE_RX_ENABLE) || \
00221    ((Mode) == (uint8_t)UART2_MODE_RX_DISABLE) || \
00222    ((Mode) == (uint8_t)UART2_MODE_TX_ENABLE) || \
00223    ((Mode) == (uint8_t)UART2_MODE_TX_DISABLE) || \
00224    ((Mode) == (uint8_t)UART2_MODE_TXRX_ENABLE) || \
00225    ((Mode) == (uint8_t)((uint8_t)UART2_MODE_TX_ENABLE|(uint8_t)UART2_MODE_RX_ENABLE)) || \
00226    ((Mode) == (uint8_t)((uint8_t)UART2_MODE_TX_ENABLE|(uint8_t)UART2_MODE_RX_DISABLE)) || \
00227    ((Mode) == (uint8_t)((uint8_t)UART2_MODE_TX_DISABLE|(uint8_t)UART2_MODE_RX_DISABLE)) || \
00228    ((Mode) == (uint8_t)((uint8_t)UART2_MODE_TX_DISABLE|(uint8_t)UART2_MODE_RX_ENABLE)))
00229
00230 /**
00231  * @brief Macro used by the assert_param function in order to check the different
00232  *        sensitivity values for the WordLengths
00233  */
00234 #define IS_UART2_WORDLENGTH_OK(WordLength) \
00235   (((WordLength) == UART2_WORDLENGTH_8D) || \
00236    ((WordLength) == UART2_WORDLENGTH_9D))
00237
00238 /**
00239   * @brief  Macro used by the assert_param function in order to check the different
00240   *         sensitivity values for the SyncModes; it should exclude values such
00241   *         as  UART2_CLOCK_ENABLE|UART2_CLOCK_DISABLE
00242   */
00243 #define IS_UART2_SYNCMODE_OK(SyncMode) \
00244   (!((((SyncMode)&(((uint8_t)UART2_SYNCMODE_CLOCK_ENABLE)|((uint8_t)UART2_SYNCMODE_CLOCK_DISABLE))) == (((uint8_t)UART2_SYNCMODE_CLOCK_ENABLE)|((uint8_t)UART2_SYNCMODE_CLOCK_DISABLE))) || \
00245      (((SyncMode)&(((uint8_t)UART2_SYNCMODE_CPOL_LOW )|((uint8_t)UART2_SYNCMODE_CPOL_HIGH))) == (((uint8_t)UART2_SYNCMODE_CPOL_LOW )|((uint8_t)UART2_SYNCMODE_CPOL_HIGH))) || \
00246      (((SyncMode)&(((uint8_t)UART2_SYNCMODE_CPHA_MIDDLE)|((uint8_t)UART2_SYNCMODE_CPHA_BEGINING))) == (((uint8_t)UART2_SYNCMODE_CPHA_MIDDLE)|((uint8_t)UART2_SYNCMODE_CPHA_BEGINING))) || \
00247      (((SyncMode)&(((uint8_t)UART2_SYNCMODE_LASTBIT_DISABLE)|((uint8_t)UART2_SYNCMODE_LASTBIT_ENABLE))) == (((uint8_t)UART2_SYNCMODE_LASTBIT_DISABLE)|((uint8_t)UART2_SYNCMODE_LASTBIT_ENABLE)))))
00248
00249 /**
00250   * @brief  Macro used by the assert_param function in order to check the
00251   *         different sensitivity values for the FLAGs
00252   */
00253 #define IS_UART2_FLAG_OK(Flag) \
00254   (((Flag) == UART2_FLAG_TXE) || \
00255    ((Flag) == UART2_FLAG_TC)  || \
00256    ((Flag) == UART2_FLAG_RXNE) || \
00257    ((Flag) == UART2_FLAG_IDLE) || \
00258    ((Flag) == UART2_FLAG_OR_LHE) || \
00259    ((Flag) == UART2_FLAG_NF) || \
00260    ((Flag) == UART2_FLAG_FE) || \
00261    ((Flag) == UART2_FLAG_PE) || \
00262    ((Flag) == UART2_FLAG_SBK) || \
00263    ((Flag) == UART2_FLAG_LSF) || \
00264    ((Flag) == UART2_FLAG_LHDF) || \
00265    ((Flag) == UART2_FLAG_LBDF))
00266
00267
00268 /**
00269   * @brief  Macro used by the assert_param function in order to check the
00270   *         different sensitivity values for the FLAGs that can be cleared by writing 0
00271   */
00272 #define IS_UART2_CLEAR_FLAG_OK(Flag) \
00273   (((Flag) == UART2_FLAG_RXNE) || \
00274    ((Flag) == UART2_FLAG_LHDF) || \
00275    ((Flag) == UART2_FLAG_LSF) || \
00276    ((Flag) == UART2_FLAG_LBDF))
00277
00278 /**
00279   * @brief  Macro used by the assert_param function in order to check
00280   *         the different sensitivity values for the Interrupts
00281   */
00282
00283 #define IS_UART2_CONFIG_IT_OK(Interrupt) \
00284   (((Interrupt) == UART2_IT_PE) || \
00285    ((Interrupt) == UART2_IT_TXE) || \
00286    ((Interrupt) == UART2_IT_TC) || \
00287    ((Interrupt) == UART2_IT_RXNE_OR ) || \
00288    ((Interrupt) == UART2_IT_IDLE) || \
00289    ((Interrupt) == UART2_IT_LHDF) || \
00290    ((Interrupt) == UART2_IT_LBDF))
00291
00292 /**
00293   * @brief  Macro used by the assert function in order to check the different
00294   *         sensitivity values for the pending bit
00295   */
00296 #define IS_UART2_GET_IT_OK(ITPendingBit) \
00297   (((ITPendingBit) == UART2_IT_TXE)  || \
00298    ((ITPendingBit) == UART2_IT_TC)   || \
00299    ((ITPendingBit) == UART2_IT_RXNE) || \
00300    ((ITPendingBit) == UART2_IT_IDLE) || \
00301    ((ITPendingBit) == UART2_IT_OR)  || \
00302    ((ITPendingBit) == UART2_IT_LBDF)  || \
00303    ((ITPendingBit) == UART2_IT_LHDF)  || \
00304    ((ITPendingBit) == UART2_IT_PE))
00305
00306 /**
00307   * @brief  Macro used by the assert function in order to check the different
00308   *         sensitivity values for the pending bit that can be cleared by writing 0
00309   */
00310 #define IS_UART2_CLEAR_IT_OK(ITPendingBit) \
00311   (((ITPendingBit) == UART2_IT_RXNE) || \
00312    ((ITPendingBit) == UART2_IT_LHDF) || \
00313    ((ITPendingBit) == UART2_IT_LBDF))
00314
00315
00316 /**
00317  * @brief Macro used by the assert_param function in order to check the different
00318  *        sensitivity values for the IrDAModes
00319  */
00320 #define IS_UART2_IRDAMODE_OK(IrDAMode) \
00321   (((IrDAMode) == UART2_IRDAMODE_LOWPOWER) || \
00322    ((IrDAMode) == UART2_IRDAMODE_NORMAL))
00323
00324 /**
00325   * @brief  Macro used by the assert_param function in order to check the different
00326   *         sensitivity values for the WakeUps
00327   */
00328 #define IS_UART2_WAKEUP_OK(WakeUp) \
00329   (((WakeUp) == UART2_WAKEUP_IDLELINE) || \
00330    ((WakeUp) == UART2_WAKEUP_ADDRESSMARK))
00331
00332 /**
00333   * @brief  Macro used by the assert_param function in order to check the different
00334   *         sensitivity values for the LINBreakDetectionLengths
00335   */
00336 #define IS_UART2_LINBREAKDETECTIONLENGTH_OK(LINBreakDetectionLength) \
00337   (((LINBreakDetectionLength) == UART2_LINBREAKDETECTIONLENGTH_10BITS) || \
00338    ((LINBreakDetectionLength) == UART2_LINBREAKDETECTIONLENGTH_11BITS))
00339
00340 /**
00341   * @brief  Macro used by the assert_param function in order to check the different
00342   *         sensitivity values for the UART2_StopBits
00343   */
00344 #define IS_UART2_STOPBITS_OK(StopBit) (((StopBit) == UART2_STOPBITS_1) || \
00345                                        ((StopBit) == UART2_STOPBITS_0_5) || \
00346                                        ((StopBit) == UART2_STOPBITS_2) || \
00347                                        ((StopBit) == UART2_STOPBITS_1_5 ))
00348
00349 /**
00350  * @brief Macro used by the assert_param function in order to check the different
00351  *        sensitivity values for the Paritys
00352  */
00353 #define IS_UART2_PARITY_OK(Parity) (((Parity) == UART2_PARITY_NO) || \
00354                                     ((Parity) == UART2_PARITY_EVEN) || \
00355                                     ((Parity) == UART2_PARITY_ODD ))
00356
00357 /**
00358  * @brief Macro used by the assert_param function in order to check the maximum
00359  *        baudrate value
00360  */
00361 #define IS_UART2_BAUDRATE_OK(NUM) ((NUM) <= (uint32_t)625000)
00362
00363
00364 /**
00365  * @brief Macro used by the assert_param function in order to check the address
00366  *        of the UART2 or UART node
00367  */
00368 #define UART2_ADDRESS_MAX ((uint8_t)16)
00369 #define IS_UART2_ADDRESS_OK(node) ((node) < UART2_ADDRESS_MAX )
00370
00371 /**
00372  * @brief Macro used by the assert_param function in order to check the LIN mode
00373  */
00374 #define IS_UART2_SLAVE_OK(Mode) \
00375   (((Mode) == UART2_LIN_MODE_MASTER) || \
00376    ((Mode) == UART2_LIN_MODE_SLAVE))
00377
00378 /**
00379  * @brief Macro used by the assert_param function in order to check the LIN
00380  *        automatic resynchronization mode
00381  */
00382 #define IS_UART2_AUTOSYNC_OK(AutosyncMode) \
00383   (((AutosyncMode) ==  UART2_LIN_AUTOSYNC_ENABLE) || \
00384    ((AutosyncMode) == UART2_LIN_AUTOSYNC_DISABLE))
00385
00386 /**
00387  * @brief Macro used by the assert_param function in order to check the LIN divider update method
00388  */
00389 #define IS_UART2_DIVUP_OK(DivupMethod) \
00390   (((DivupMethod) == UART2_LIN_DIVUP_LBRR1) || \
00391    ((DivupMethod) == UART2_LIN_DIVUP_NEXTRXNE))
00392
00393
00394 /**
00395   * @}
00396   */
00397
00398 /* Exported functions ------------------------------------------------------- */
00399
00400 /** @addtogroup UART2_Exported_Functions
00401   * @{
00402   */
00403
00404 void UART2_DeInit(void);
00405 void UART2_Init(uint32_t BaudRate, UART2_WordLength_TypeDef WordLength,
00406                 UART2_StopBits_TypeDef StopBits, UART2_Parity_TypeDef Parity,
00407                 UART2_SyncMode_TypeDef SyncMode, UART2_Mode_TypeDef Mode);
00408 void UART2_Cmd(FunctionalState NewState);
00409 void UART2_ITConfig(UART2_IT_TypeDef UART2_IT, FunctionalState NewState);
00410 void UART2_HalfDuplexCmd(FunctionalState NewState);
00411 void UART2_IrDAConfig(UART2_IrDAMode_TypeDef UART2_IrDAMode);
00412 void UART2_IrDACmd(FunctionalState NewState);
00413 void UART2_LINBreakDetectionConfig(UART2_LINBreakDetectionLength_TypeDef UART2_LINBreakDetectionLength);
00414 void UART2_LINConfig(UART2_LinMode_TypeDef UART2_Mode,
00415                      UART2_LinAutosync_TypeDef UART2_Autosync,
00416                      UART2_LinDivUp_TypeDef UART2_DivUp);
00417 void UART2_LINCmd(FunctionalState NewState);
00418 void UART2_SmartCardCmd(FunctionalState NewState);
00419 void UART2_SmartCardNACKCmd(FunctionalState NewState);
00420 void UART2_WakeUpConfig(UART2_WakeUp_TypeDef UART2_WakeUp);
00421 void UART2_ReceiverWakeUpCmd(FunctionalState NewState);
00422 uint8_t UART2_ReceiveData8(void);
00423 uint16_t UART2_ReceiveData9(void);
00424 void UART2_SendData8(uint8_t Data);
00425 void UART2_SendData9(uint16_t Data);
00426 void UART2_SendBreak(void);
00427 void UART2_SetAddress(uint8_t UART2_Address);
00428 void UART2_SetGuardTime(uint8_t UART2_GuardTime);
00429 void UART2_SetPrescaler(uint8_t UART2_Prescaler);
00430 FlagStatus UART2_GetFlagStatus(UART2_Flag_TypeDef UART2_FLAG);
00431 void UART2_ClearFlag(UART2_Flag_TypeDef UART2_FLAG);
00432 ITStatus UART2_GetITStatus(UART2_IT_TypeDef UART2_IT);
00433 void UART2_ClearITPendingBit(UART2_IT_TypeDef UART2_IT);
00434
00435
00436 /**
00437   * @}
00438   */
00439
00440 #endif /* __STM8S_UART2_H */
00441
00442 /**
00443   * @}
00444   */
00445
00446
00447 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_uart3.c Source File

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stm8s_uart3.c
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00001 /**
00002   ********************************************************************************
00003   * @file    stm8s_uart3.c
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all the functions for the uart3 peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm8s_uart3.h"
00030
00031 /** @addtogroup STM8S_StdPeriph_Driver
00032   * @{
00033   */
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 /* Private macro -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038 /* Private function prototypes -----------------------------------------------*/
00039
00040 /* Private functions ---------------------------------------------------------*/
00041 /* Public functions ----------------------------------------------------------*/
00042
00043 /**
00044   * @addtogroup UART3_Public_Functions
00045   * @{
00046   */
00047
00048 /**
00049   * @brief  Deinitializes the UART peripheral.
00050   * @param  None
00051   * @retval None
00052   */
00053
00054 void UART3_DeInit(void)
00055 {
00056   /* Clear the Idle Line Detected bit in the status rerister by a read
00057   to the UART3_SR register followed by a Read to the UART3_DR register */
00058   (void) UART3->SR;
00059   (void) UART3->DR;
00060
00061   UART3->BRR2 = UART3_BRR2_RESET_VALUE; /*Set UART3_BRR2 to reset value 0x00 */
00062   UART3->BRR1 = UART3_BRR1_RESET_VALUE; /*Set UART3_BRR1 to reset value 0x00 */
00063
00064   UART3->CR1 = UART3_CR1_RESET_VALUE;  /*Set UART3_CR1 to reset value 0x00  */
00065   UART3->CR2 = UART3_CR2_RESET_VALUE;  /*Set UART3_CR2 to reset value 0x00  */
00066   UART3->CR3 = UART3_CR3_RESET_VALUE;  /*Set UART3_CR3 to reset value 0x00  */
00067   UART3->CR4 = UART3_CR4_RESET_VALUE;  /*Set UART3_CR4 to reset value 0x00  */
00068   UART3->CR6 = UART3_CR6_RESET_VALUE;  /*Set UART3_CR6 to reset value 0x00  */
00069 }
00070
00071 /**
00072   * @brief  Initializes the UART3 according to the specified parameters.
00073   * @param  BaudRate: The baudrate.
00074   * @param  WordLength : This parameter can be any of
00075   *         the @ref UART3_WordLength_TypeDef enumeration.
00076   * @param  StopBits: This parameter can be any of the
00077   *         @ref UART3_StopBits_TypeDef enumeration.
00078   * @param  Parity: This parameter can be any of the
00079   *         @ref UART3_Parity_TypeDef enumeration.
00080   * @param  Mode: This parameter can be any of the @ref UART3_Mode_TypeDef values
00081   * @retval None
00082   */
00083 void UART3_Init(uint32_t BaudRate, UART3_WordLength_TypeDef WordLength,
00084                 UART3_StopBits_TypeDef StopBits, UART3_Parity_TypeDef Parity,
00085                 UART3_Mode_TypeDef Mode)
00086 {
00087   uint8_t BRR2_1 = 0, BRR2_2 = 0;
00088   uint32_t BaudRate_Mantissa = 0, BaudRate_Mantissa100 = 0;
00089
00090   /* Check the parameters */
00091   assert_param(IS_UART3_WORDLENGTH_OK(WordLength));
00092   assert_param(IS_UART3_STOPBITS_OK(StopBits));
00093   assert_param(IS_UART3_PARITY_OK(Parity));
00094   assert_param(IS_UART3_BAUDRATE_OK(BaudRate));
00095   assert_param(IS_UART3_MODE_OK((uint8_t)Mode));
00096
00097   /* Clear the word length bit */
00098   UART3->CR1 &= (uint8_t)(~UART3_CR1_M);
00099   /* Set the word length bit according to UART3_WordLength value */
00100   UART3->CR1 |= (uint8_t)WordLength;
00101
00102   /* Clear the STOP bits */
00103   UART3->CR3 &= (uint8_t)(~UART3_CR3_STOP);
00104   /* Set the STOP bits number according to UART3_StopBits value  */
00105   UART3->CR3 |= (uint8_t)StopBits;
00106
00107   /* Clear the Parity Control bit */
00108   UART3->CR1 &= (uint8_t)(~(UART3_CR1_PCEN | UART3_CR1_PS));
00109   /* Set the Parity Control bit to UART3_Parity value */
00110   UART3->CR1 |= (uint8_t)Parity;
00111
00112   /* Clear the LSB mantissa of UART3DIV  */
00113   UART3->BRR1 &= (uint8_t)(~UART3_BRR1_DIVM);
00114   /* Clear the MSB mantissa of UART3DIV  */
00115   UART3->BRR2 &= (uint8_t)(~UART3_BRR2_DIVM);
00116   /* Clear the Fraction bits of UART3DIV */
00117   UART3->BRR2 &= (uint8_t)(~UART3_BRR2_DIVF);
00118
00119   /* Set the UART3 BaudRates in BRR1 and BRR2 registers according to UART3_BaudRate value */
00120   BaudRate_Mantissa    = ((uint32_t)CLK_GetClockFreq() / (BaudRate << 4));
00121   BaudRate_Mantissa100 = (((uint32_t)CLK_GetClockFreq() * 100) / (BaudRate << 4));
00122   /* The fraction and MSB mantissa should be loaded in one step in the BRR2 register */
00123   /* Set the fraction of UART3DIV  */
00124   BRR2_1 = (uint8_t)((uint8_t)(((BaudRate_Mantissa100 - (BaudRate_Mantissa * 100))
00125                                 << 4) / 100) & (uint8_t)0x0F);
00126   BRR2_2 = (uint8_t)((BaudRate_Mantissa >> 4) & (uint8_t)0xF0);
00127
00128   UART3->BRR2 = (uint8_t)(BRR2_1 | BRR2_2);
00129   /* Set the LSB mantissa of UART3DIV  */
00130   UART3->BRR1 = (uint8_t)BaudRate_Mantissa;
00131
00132   if ((uint8_t)(Mode & UART3_MODE_TX_ENABLE))
00133   {
00134     /* Set the Transmitter Enable bit */
00135     UART3->CR2 |= UART3_CR2_TEN;
00136   }
00137   else
00138   {
00139     /* Clear the Transmitter Disable bit */
00140     UART3->CR2 &= (uint8_t)(~UART3_CR2_TEN);
00141   }
00142   if ((uint8_t)(Mode & UART3_MODE_RX_ENABLE))
00143   {
00144     /* Set the Receiver Enable bit */
00145     UART3->CR2 |= UART3_CR2_REN;
00146   }
00147   else
00148   {
00149     /* Clear the Receiver Disable bit */
00150     UART3->CR2 &= (uint8_t)(~UART3_CR2_REN);
00151   }
00152 }
00153
00154 /**
00155   * @brief  Enable the UART1 peripheral.
00156   * @param  NewState : The new state of the UART Communication.
00157   *         This parameter can be any of the @ref FunctionalState enumeration.
00158   * @retval None
00159   */
00160 void UART3_Cmd(FunctionalState NewState)
00161 {
00162   if (NewState != DISABLE)
00163   {
00164     /* UART3 Enable */
00165     UART3->CR1 &= (uint8_t)(~UART3_CR1_UARTD);
00166   }
00167   else
00168   {
00169     /* UART3 Disable */
00170     UART3->CR1 |= UART3_CR1_UARTD;
00171   }
00172 }
00173
00174 /**
00175   * @brief  Enables or disables the specified UART3 interrupts.
00176   * @param  UART3_IT specifies the UART3 interrupt sources to be enabled or disabled.
00177   *         This parameter can be one of the following values:
00178   *         - UART3_IT_LBDF:  LIN Break detection interrupt
00179   *         - UART3_IT_LHDF:  LIN Break detection interrupt
00180   *         - UART3_IT_TXE:  Transmit Data Register empty interrupt
00181   *         - UART3_IT_TC:   Transmission complete interrupt
00182   *         - UART3_IT_RXNE_OR: Receive Data register not empty/Over run error interrupt
00183   *         - UART3_IT_IDLE: Idle line detection interrupt
00184   *         - UART3_IT_PE:   Parity Error interrupt
00185   * @param  NewState new state of the specified UART3 interrupts.
00186   *         This parameter can be: ENABLE or DISABLE.
00187   * @retval None
00188   */
00189 void UART3_ITConfig(UART3_IT_TypeDef UART3_IT, FunctionalState NewState)
00190 {
00191   uint8_t uartreg = 0, itpos = 0x00;
00192
00193   /* Check the parameters */
00194   assert_param(IS_UART3_CONFIG_IT_OK(UART3_IT));
00195   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00196
00197   /* Get the UART3 register index */
00198   uartreg = (uint8_t)((uint16_t)UART3_IT >> 0x08);
00199
00200   /* Get the UART3 IT index */
00201   itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)UART3_IT & (uint8_t)0x0F));
00202
00203   if (NewState != DISABLE)
00204   {
00205     /* Enable the Interrupt bits according to UART3_IT mask */
00206     if (uartreg == 0x01)
00207     {
00208       UART3->CR1 |= itpos;
00209     }
00210     else if (uartreg == 0x02)
00211     {
00212       UART3->CR2 |= itpos;
00213     }
00214     else if (uartreg == 0x03)
00215     {
00216       UART3->CR4 |= itpos;
00217     }
00218     else
00219     {
00220       UART3->CR6 |= itpos;
00221     }
00222   }
00223   else
00224   {
00225     /* Disable the interrupt bits according to UART3_IT mask */
00226     if (uartreg == 0x01)
00227     {
00228       UART3->CR1 &= (uint8_t)(~itpos);
00229     }
00230     else if (uartreg == 0x02)
00231     {
00232       UART3->CR2 &= (uint8_t)(~itpos);
00233     }
00234     else if (uartreg == 0x03)
00235     {
00236       UART3->CR4 &= (uint8_t)(~itpos);
00237     }
00238     else
00239     {
00240       UART3->CR6 &= (uint8_t)(~itpos);
00241     }
00242   }
00243 }
00244
00245 /**
00246   * @brief  Sets the UART3 LIN Break detection length.
00247   * @param  UART3_LINBreakDetectionLength specifies the LIN break detection length.
00248   *         This parameter can be any of the
00249   *         @ref UART3_LINBreakDetectionLength_TypeDef values.
00250   * @retval None
00251   */
00252 void UART3_LINBreakDetectionConfig(UART3_LINBreakDetectionLength_TypeDef UART3_LINBreakDetectionLength)
00253 {
00254   /* Check the parameters */
00255   assert_param(IS_UART3_LINBREAKDETECTIONLENGTH_OK(UART3_LINBreakDetectionLength));
00256
00257   if (UART3_LINBreakDetectionLength != UART3_LINBREAKDETECTIONLENGTH_10BITS)
00258   {
00259     UART3->CR4 |= UART3_CR4_LBDL;
00260   }
00261   else
00262   {
00263     UART3->CR4 &= ((uint8_t)~UART3_CR4_LBDL);
00264   }
00265 }
00266
00267 /**
00268   * @brief  Configure the UART3 peripheral.
00269   * @param  UART3_Mode specifies the LIN mode.
00270   *         This parameter can be any of the @ref UART3_LinMode_TypeDef values.
00271   * @param  UART3_Autosync specifies the LIN automatic resynchronization mode.
00272   *         This parameter can be any of the @ref UART3_LinAutosync_TypeDef values.
00273   * @param  UART3_DivUp specifies the LIN divider update method.
00274   *         This parameter can be any of the @ref UART3_LinDivUp_TypeDef values.
00275   * @retval None
00276   */
00277 void UART3_LINConfig(UART3_LinMode_TypeDef UART3_Mode,
00278                      UART3_LinAutosync_TypeDef UART3_Autosync,
00279                      UART3_LinDivUp_TypeDef UART3_DivUp)
00280 {
00281   /* Check the parameters */
00282   assert_param(IS_UART3_SLAVE_OK(UART3_Mode));
00283   assert_param(IS_UART3_AUTOSYNC_OK(UART3_Autosync));
00284   assert_param(IS_UART3_DIVUP_OK(UART3_DivUp));
00285
00286   if (UART3_Mode != UART3_LIN_MODE_MASTER)
00287   {
00288     UART3->CR6 |=  UART3_CR6_LSLV;
00289   }
00290   else
00291   {
00292     UART3->CR6 &= ((uint8_t)~UART3_CR6_LSLV);
00293   }
00294
00295   if (UART3_Autosync != UART3_LIN_AUTOSYNC_DISABLE)
00296   {
00297     UART3->CR6 |=  UART3_CR6_LASE ;
00298   }
00299   else
00300   {
00301     UART3->CR6 &= ((uint8_t)~ UART3_CR6_LASE );
00302   }
00303
00304   if (UART3_DivUp != UART3_LIN_DIVUP_LBRR1)
00305   {
00306     UART3->CR6 |=  UART3_CR6_LDUM;
00307   }
00308   else
00309   {
00310     UART3->CR6 &= ((uint8_t)~ UART3_CR6_LDUM);
00311   }
00312 }
00313
00314 /**
00315   * @brief  Enables or disables the UART3 LIN mode.
00316   * @param  NewState is new state of the UART3 LIN mode.
00317   *         This parameter can be ENABLE or DISABLE
00318   * @retval None
00319   */
00320 void UART3_LINCmd(FunctionalState NewState)
00321 {
00322   /* Check the parameters */
00323   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00324
00325   if (NewState != DISABLE)
00326   {
00327     /* Enable the LIN mode by setting the LINE bit in the CR2 register */
00328     UART3->CR3 |= UART3_CR3_LINEN;
00329   }
00330   else
00331   {
00332     /* Disable the LIN mode by clearing the LINE bit in the CR2 register */
00333     UART3->CR3 &= ((uint8_t)~UART3_CR3_LINEN);
00334   }
00335 }
00336
00337 /**
00338   * @brief  Selects the UART3 WakeUp method.
00339   * @param  UART3_WakeUp: specifies the UART3 wakeup method.
00340   *         This parameter can be any of the @ref UART3_WakeUp_TypeDef values.
00341   * @retval None
00342   */
00343 void UART3_WakeUpConfig(UART3_WakeUp_TypeDef UART3_WakeUp)
00344 {
00345   /* Check the parameters */
00346   assert_param(IS_UART3_WAKEUP_OK(UART3_WakeUp));
00347
00348   UART3->CR1 &= ((uint8_t)~UART3_CR1_WAKE);
00349   UART3->CR1 |= (uint8_t)UART3_WakeUp;
00350 }
00351
00352 /**
00353   * @brief  Determines if the UART3 is in mute mode or not.
00354   * @param  NewState: new state of the UART3 mode.
00355   *         This parameter can be ENABLE or DISABLE
00356   * @retval None
00357   */
00358 void UART3_ReceiverWakeUpCmd(FunctionalState NewState)
00359 {
00360   /* Check the parameters */
00361   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00362
00363   if (NewState != DISABLE)
00364   {
00365     /* Enable the mute mode UART3 by setting the RWU bit in the CR2 register */
00366     UART3->CR2 |= UART3_CR2_RWU;
00367   }
00368   else
00369   {
00370     /* Disable the mute mode UART3 by clearing the RWU bit in the CR1 register */
00371     UART3->CR2 &= ((uint8_t)~UART3_CR2_RWU);
00372   }
00373 }
00374
00375 /**
00376   * @brief  Returns the most recent received data by the UART3 peripheral.
00377   * @param  None
00378   * @retval Received Data
00379   */
00380 uint8_t UART3_ReceiveData8(void)
00381 {
00382   return ((uint8_t)UART3->DR);
00383 }
00384
00385 /**
00386   * @brief  Returns the most recent received data by the UART3 peripheral.
00387   * @param  None
00388   * @retval Received Data
00389   */
00390 uint16_t UART3_ReceiveData9(void)
00391 {
00392   uint16_t temp = 0;
00393
00394   temp = (uint16_t)(((uint16_t)((uint16_t)UART3->CR1 & (uint16_t)UART3_CR1_R8)) << 1);
00395   return (uint16_t)((((uint16_t)UART3->DR) | temp) & ((uint16_t)0x01FF));
00396 }
00397
00398 /**
00399   * @brief  Transmits 8 bit data through the UART3 peripheral.
00400   * @param  Data the data to transmit.
00401   * @retval None
00402   */
00403 void UART3_SendData8(uint8_t Data)
00404 {
00405   /* Transmit Data */
00406   UART3->DR = Data;
00407 }
00408
00409 /**
00410   * @brief  Transmits 9 bit data through the UART3 peripheral.
00411   * @param   Data: the data to transmit.
00412   * @retval None
00413   */
00414 void UART3_SendData9(uint16_t Data)
00415 {
00416   /* Clear the transmit data bit 8 */
00417   UART3->CR1 &= ((uint8_t)~UART3_CR1_T8);
00418
00419   /* Write the transmit data bit [8] */
00420   UART3->CR1 |= (uint8_t)(((uint8_t)(Data >> 2)) & UART3_CR1_T8);
00421
00422   /* Write the transmit data bit [0:7] */
00423   UART3->DR   = (uint8_t)(Data);
00424 }
00425
00426 /**
00427   * @brief  Transmits break characters.
00428   * @param  None
00429   * @retval None
00430   */
00431 void UART3_SendBreak(void)
00432 {
00433   UART3->CR2 |= UART3_CR2_SBK;
00434 }
00435
00436 /**
00437   * @brief  Sets the address of the UART3 node.
00438   * @param  UART3_Address: Indicates the address of the UART3 node.
00439   * @retval None
00440   */
00441 void UART3_SetAddress(uint8_t UART3_Address)
00442 {
00443   /* Check the parameters */
00444   assert_param(IS_UART3_ADDRESS_OK(UART3_Address));
00445
00446   /* Clear the UART3 address */
00447   UART3->CR4 &= ((uint8_t)~UART3_CR4_ADD);
00448   /* Set the UART3 address node */
00449   UART3->CR4 |= UART3_Address;
00450 }
00451
00452 /**
00453   * @brief  Checks whether the specified UART3 flag is set or not.
00454   * @param  UART3_FLAG specifies the flag to check.
00455   *         This parameter can be any of the @ref UART3_Flag_TypeDef enumeration.
00456   * @retval FlagStatus (SET or RESET)
00457   */
00458 FlagStatus UART3_GetFlagStatus(UART3_Flag_TypeDef UART3_FLAG)
00459 {
00460   FlagStatus status = RESET;
00461
00462   /* Check parameters */
00463   assert_param(IS_UART3_FLAG_OK(UART3_FLAG));
00464
00465   /* Check the status of the specified UART3 flag*/
00466   if (UART3_FLAG == UART3_FLAG_LBDF)
00467   {
00468     if ((UART3->CR4 & (uint8_t)UART3_FLAG) != (uint8_t)0x00)
00469     {
00470       /* UART3_FLAG is set*/
00471       status = SET;
00472     }
00473     else
00474     {
00475       /* UART3_FLAG is reset*/
00476       status = RESET;
00477     }
00478   }
00479   else if (UART3_FLAG == UART3_FLAG_SBK)
00480   {
00481     if ((UART3->CR2 & (uint8_t)UART3_FLAG) != (uint8_t)0x00)
00482     {
00483       /* UART3_FLAG is set*/
00484       status = SET;
00485     }
00486     else
00487     {
00488       /* UART3_FLAG is reset*/
00489       status = RESET;
00490     }
00491   }
00492   else if ((UART3_FLAG == UART3_FLAG_LHDF) || (UART3_FLAG == UART3_FLAG_LSF))
00493   {
00494     if ((UART3->CR6 & (uint8_t)UART3_FLAG) != (uint8_t)0x00)
00495     {
00496       /* UART3_FLAG is set*/
00497       status = SET;
00498     }
00499     else
00500     {
00501       /* UART3_FLAG is reset*/
00502       status = RESET;
00503     }
00504   }
00505   else
00506   {
00507     if ((UART3->SR & (uint8_t)UART3_FLAG) != (uint8_t)0x00)
00508     {
00509       /* UART3_FLAG is set*/
00510       status = SET;
00511     }
00512     else
00513     {
00514       /* UART3_FLAG is reset*/
00515       status = RESET;
00516     }
00517   }
00518
00519   /* Return the UART3_FLAG status*/
00520   return  status;
00521 }
00522
00523 /**
00524   * @brief  Clears the UART3 flags.
00525   * @param  UART3_FLAG specifies the flag to clear
00526   *         This parameter can be any combination of the following values:
00527   *         - UART3_FLAG_LBDF: LIN Break detection flag.
00528   *         - UART3_FLAG_LHDF: LIN Header detection flag.
00529   *         - UART3_FLAG_LSF: LIN synchrone field flag.
00530   *         - UART3_FLAG_RXNE: Receive data register not empty flag.
00531   * @note
00532   *         - PE (Parity error), FE (Framing error), NF (Noise error),
00533   *           OR (OverRun error) and IDLE (Idle line detected) flags are cleared
00534   *           by software sequence: a read operation to UART3_SR register
00535   *           (UART3_GetFlagStatus())followed by a read operation to UART3_DR
00536   *           register(UART3_ReceiveData8() or UART3_ReceiveData9()).
00537   *
00538   *         - RXNE flag can be also cleared by a read to the UART3_DR register
00539   *           (UART3_ReceiveData8()or UART3_ReceiveData9()).
00540   *
00541   *         - TC flag can be also cleared by software sequence: a read operation
00542   *           to UART3_SR register (UART3_GetFlagStatus()) followed by a write
00543   *           operation to UART3_DR register (UART3_SendData8() or UART3_SendData9()).
00544   *
00545   *         - TXE flag is cleared only by a write to the UART3_DR register
00546   *           (UART3_SendData8() or UART3_SendData9()).
00547   *
00548   *         - SBK flag is cleared during the stop bit of break.
00549   * @retval None
00550   */
00551 void UART3_ClearFlag(UART3_Flag_TypeDef UART3_FLAG)
00552 {
00553   /* Check the parameters */
00554   assert_param(IS_UART3_CLEAR_FLAG_OK(UART3_FLAG));
00555
00556   /*Clear the Receive Register Not Empty flag */
00557   if (UART3_FLAG == UART3_FLAG_RXNE)
00558   {
00559     UART3->SR = (uint8_t)~(UART3_SR_RXNE);
00560   }
00561   /*Clear the LIN Break Detection flag */
00562   else if (UART3_FLAG == UART3_FLAG_LBDF)
00563   {
00564     UART3->CR4 &= (uint8_t)(~UART3_CR4_LBDF);
00565   }
00566   /*Clear the LIN Header Detection Flag */
00567   else if (UART3_FLAG == UART3_FLAG_LHDF)
00568   {
00569     UART3->CR6 &= (uint8_t)(~UART3_CR6_LHDF);
00570   }
00571   /*Clear the LIN Synch Field flag */
00572   else
00573   {
00574     UART3->CR6 &= (uint8_t)(~UART3_CR6_LSF);
00575   }
00576 }
00577
00578 /**
00579   * @brief  Checks whether the specified UART3 interrupt has occurred or not.
00580   * @param  UART3_IT: Specifies the UART3 interrupt pending bit to check.
00581   *         This parameter can be one of the following values:
00582   *         - UART3_IT_LBDF:  LIN Break detection interrupt
00583   *         - UART3_IT_TXE:  Transmit Data Register empty interrupt
00584   *         - UART3_IT_TC:   Transmission complete interrupt
00585   *         - UART3_IT_RXNE: Receive Data register not empty interrupt
00586   *         - UART3_IT_IDLE: Idle line detection interrupt
00587   *         - UART3_IT_OR:  OverRun Error interrupt
00588   *         - UART3_IT_PE:   Parity Error interrupt
00589   * @retval The state of UART3_IT (SET or RESET).
00590   */
00591 ITStatus UART3_GetITStatus(UART3_IT_TypeDef UART3_IT)
00592 {
00593   ITStatus pendingbitstatus = RESET;
00594   uint8_t itpos = 0;
00595   uint8_t itmask1 = 0;
00596   uint8_t itmask2 = 0;
00597   uint8_t enablestatus = 0;
00598
00599   /* Check parameters */
00600   assert_param(IS_UART3_GET_IT_OK(UART3_IT));
00601
00602   /* Get the UART3 IT index*/
00603   itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)UART3_IT & (uint8_t)0x0F));
00604   /* Get the UART3 IT index*/
00605   itmask1 = (uint8_t)((uint8_t)UART3_IT >> (uint8_t)4);
00606   /* Set the IT mask*/
00607   itmask2 = (uint8_t)((uint8_t)1 << itmask1);
00608
00609   /* Check the status of the specified UART3 pending bit*/
00610   if (UART3_IT == UART3_IT_PE)
00611   {
00612     /* Get the UART3_ITPENDINGBIT enable bit status*/
00613     enablestatus = (uint8_t)((uint8_t)UART3->CR1 & itmask2);
00614     /* Check the status of the specified UART3 interrupt*/
00615
00616     if (((UART3->SR & itpos) != (uint8_t)0x00) && enablestatus)
00617     {
00618       /* Interrupt occurred*/
00619       pendingbitstatus = SET;
00620     }
00621     else
00622     {
00623       /* Interrupt not occurred*/
00624       pendingbitstatus = RESET;
00625     }
00626   }
00627   else if (UART3_IT == UART3_IT_LBDF)
00628   {
00629     /* Get the UART3_IT enable bit status*/
00630     enablestatus = (uint8_t)((uint8_t)UART3->CR4 & itmask2);
00631     /* Check the status of the specified UART3 interrupt*/
00632     if (((UART3->CR4 & itpos) != (uint8_t)0x00) && enablestatus)
00633     {
00634       /* Interrupt occurred*/
00635       pendingbitstatus = SET;
00636     }
00637     else
00638     {
00639       /* Interrupt not occurred*/
00640       pendingbitstatus = RESET;
00641     }
00642   }
00643   else if (UART3_IT == UART3_IT_LHDF)
00644   {
00645     /* Get the UART3_IT enable bit status*/
00646     enablestatus = (uint8_t)((uint8_t)UART3->CR6 & itmask2);
00647     /* Check the status of the specified UART3 interrupt*/
00648     if (((UART3->CR6 & itpos) != (uint8_t)0x00) && enablestatus)
00649     {
00650       /* Interrupt occurred*/
00651       pendingbitstatus = SET;
00652     }
00653     else
00654     {
00655       /* Interrupt not occurred*/
00656       pendingbitstatus = RESET;
00657     }
00658   }
00659   else
00660   {
00661     /* Get the UART3_IT enable bit status*/
00662     enablestatus = (uint8_t)((uint8_t)UART3->CR2 & itmask2);
00663     /* Check the status of the specified UART3 interrupt*/
00664     if (((UART3->SR & itpos) != (uint8_t)0x00) && enablestatus)
00665     {
00666       /* Interrupt occurred*/
00667       pendingbitstatus = SET;
00668     }
00669     else
00670     {
00671       /* Interrupt not occurred*/
00672       pendingbitstatus = RESET;
00673     }
00674   }
00675   /* Return the UART3_IT status*/
00676   return  pendingbitstatus;
00677 }
00678
00679 /**
00680   * @brief  Clears the UART3 pending flags.
00681   * @param  UART3_IT specifies the pending bit to clear
00682   *         This parameter can be one of the following values:
00683   *         - UART3_IT_LBDF:  LIN Break detection interrupt
00684   *         - UART3_IT_LHDF:  LIN Header detection interrupt
00685   *         - UART3_IT_RXNE: Receive Data register not empty interrupt.
00686   *
00687   * @note
00688   *         - PE (Parity error), FE (Framing error), NF (Noise error),
00689   *           OR (OverRun error) and IDLE (Idle line detected) pending bits are
00690   *           cleared by software sequence: a read operation to UART3_SR register
00691   *           (UART3_GetITStatus()) followed by a read operation to UART3_DR register
00692   *           (UART3_ReceiveData8() or UART3_ReceiveData9()).
00693   *
00694   *         - RXNE pending bit can be also cleared by a read to the UART3_DR register
00695   *           (UART3_ReceiveData8() or UART3_ReceiveData9() ).
00696   *
00697   *         - TC (Transmit complete) pending bit can be cleared by software
00698   *           sequence: a read operation to UART3_SR register (UART3_GetITStatus())
00699   *           followed by a write operation to UART3_DR register
00700   *           (UART3_SendData8()or UART3_SendData9()).
00701   *
00702   *         - TXE pending bit is cleared only by a write to the UART3_DR register
00703   *           (UART3_SendData8() or UART3_SendData9()).
00704   * @retval None
00705   */
00706 void UART3_ClearITPendingBit(UART3_IT_TypeDef UART3_IT)
00707 {
00708   /* Check the parameters */
00709   assert_param(IS_UART3_CLEAR_IT_OK(UART3_IT));
00710
00711   /*Clear the Receive Register Not Empty pending bit */
00712   if (UART3_IT == UART3_IT_RXNE)
00713   {
00714     UART3->SR = (uint8_t)~(UART3_SR_RXNE);
00715   }
00716   /*Clear the LIN Break Detection pending bit */
00717   else if (UART3_IT == UART3_IT_LBDF)
00718   {
00719     UART3->CR4 &= (uint8_t)~(UART3_CR4_LBDF);
00720   }
00721   /*Clear the LIN Header Detection pending bit */
00722   else
00723   {
00724     UART3->CR6 &= (uint8_t)(~UART3_CR6_LHDF);
00725   }
00726 }
00727
00728 /**
00729   * @}
00730   */
00731
00732 /**
00733   * @}
00734   */
00735
00736
00737 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_uart3.h Source File

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stm8s_uart3.h
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00001 /**
00002   ********************************************************************************
00003   * @file    stm8s_uart3.h
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all functions prototypes and macros for the UART3 peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Define to prevent recursive inclusion -------------------------------------*/
00029 #ifndef __STM8S_UART3_H
00030 #define __STM8S_UART3_H
00031
00032 /* Includes ------------------------------------------------------------------*/
00033 #include "stm8s.h"
00034
00035 /** @addtogroup STM8S_StdPeriph_Driver
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040
00041 /** @addtogroup UART3_Exported_Types
00042   * @{
00043   */
00044
00045 /**
00046   * @brief  UART3 WakeUP Modes
00047   */
00048 typedef enum { UART3_WAKEUP_IDLELINE      = (uint8_t)0x00,  /**< 0x01 Idle Line wake up*/
00049                UART3_WAKEUP_ADDRESSMARK   = (uint8_t)0x08   /**< 0x02 Address Mark wake up*/
00050              } UART3_WakeUp_TypeDef;
00051
00052 /**
00053   * @brief  UART3 LIN Break detection length possible values
00054   */
00055 typedef enum { UART3_LINBREAKDETECTIONLENGTH_10BITS = (uint8_t)0x00, /**< 10 bits Lin Break detection */
00056                UART3_LINBREAKDETECTIONLENGTH_11BITS = (uint8_t)0x01  /**< 11 bits Lin Break detection */
00057              } UART3_LINBreakDetectionLength_TypeDef;
00058
00059
00060 /**
00061   * @brief  UART3 stop bits possible values
00062   */
00063 typedef enum { UART3_STOPBITS_1  = (uint8_t)0x00,  /**< One stop bit is  transmitted at the end of frame*/
00064                UART3_STOPBITS_2  = (uint8_t)0x20   /**< Two stop bits are  transmitted at the end of frame*/
00065              } UART3_StopBits_TypeDef;
00066
00067 /**
00068   * @brief  UART3 parity possible values
00069   */
00070 typedef enum { UART3_PARITY_NO    = (uint8_t)0x00,    /**< No Parity*/
00071                UART3_PARITY_EVEN  = (uint8_t)0x04,    /**< Even Parity*/
00072                UART3_PARITY_ODD   = (uint8_t)0x06     /**< Odd Parity*/
00073              } UART3_Parity_TypeDef;
00074
00075 /**
00076   * @brief  UART3 Word length possible values
00077   */
00078 typedef enum { UART3_WORDLENGTH_8D = (uint8_t)0x00,    /**< 0x00 8 bits Data*/
00079                UART3_WORDLENGTH_9D = (uint8_t)0x10     /**< 0x10 9 bits Data*/
00080              } UART3_WordLength_TypeDef;
00081
00082 /**
00083   * @brief  UART3 Mode Transmit/Receive possible values
00084   */
00085 typedef enum { UART3_MODE_RX_ENABLE    = (uint8_t)0x08,  /**< 0x08 Receive Enable*/
00086                UART3_MODE_TX_ENABLE    = (uint8_t)0x04,  /**< 0x04 Transmit Enable*/
00087                UART3_MODE_TX_DISABLE   = (uint8_t)0x80,  /**< 0x80 Receive Enable*/
00088                UART3_MODE_RX_DISABLE   = (uint8_t)0x40,  /**< 0x40 Single-wire Half-duplex mode*/
00089                UART3_MODE_TXRX_ENABLE  = (uint8_t)0x0C   /**< 0x0C Receive Enable and Transmit enable*/
00090              } UART3_Mode_TypeDef;
00091
00092 /**
00093   * @brief  UART3 Mode possible values
00094   */
00095 typedef enum { UART3_LIN_MODE_MASTER  = (uint8_t)0x00, /**<  LIN Master Mode*/
00096                UART3_LIN_MODE_SLAVE   = (uint8_t)0x01  /**<  LIN Slave Mode*/
00097              } UART3_LinMode_TypeDef;
00098 /**
00099   * @brief  UART3 automatic resynchronisation possible values
00100   */
00101 typedef enum { UART3_LIN_AUTOSYNC_DISABLE   = (uint8_t)0x00,  /**< LIN Autosynchronization Disable*/
00102                UART3_LIN_AUTOSYNC_ENABLE    = (uint8_t)0x01   /**< LIN Autosynchronization Enable*/
00103              } UART3_LinAutosync_TypeDef;
00104 /**
00105   * @brief  UART3 Divider Update Method possible values
00106   */
00107 typedef enum { UART3_LIN_DIVUP_LBRR1    = (uint8_t)0x00, /**<  LIN LDIV is updated as soon as LBRR1 is written*/
00108                UART3_LIN_DIVUP_NEXTRXNE = (uint8_t)0x01  /**<  LIN LDIV is updated at the next received character*/
00109              } UART3_LinDivUp_TypeDef;
00110
00111
00112 /**
00113   * @brief  UART3 Flag possible values
00114   */
00115 typedef enum
00116 {
00117   UART3_FLAG_TXE         = (uint16_t)0x0080, /*!< Transmit Data Register Empty flag */
00118   UART3_FLAG_TC          = (uint16_t)0x0040, /*!< Transmission Complete flag */
00119   UART3_FLAG_RXNE        = (uint16_t)0x0020, /*!< Read Data Register Not Empty flag */
00120   UART3_FLAG_IDLE        = (uint16_t)0x0010, /*!< Idle line detected flag */
00121   UART3_FLAG_OR_LHE      = (uint16_t)0x0008, /*!< OverRun error flag */
00122   UART3_FLAG_NF          = (uint16_t)0x0004, /*!< Noise error flag */
00123   UART3_FLAG_FE          = (uint16_t)0x0002, /*!< Framing Error flag */
00124   UART3_FLAG_PE          = (uint16_t)0x0001, /*!< Parity Error flag */
00125   UART3_FLAG_SBK         = (uint16_t)0x0101,  /**< Send Break Complete interrupt flag */
00126   UART3_FLAG_LBDF        = (uint16_t)0x0210, /**< LIN Break Detection Flag           */
00127   UART3_FLAG_LHDF        = (uint16_t)0x0302, /**< LIN Header Detection Flag*/
00128   UART3_FLAG_LSF         = (uint16_t)0x0301  /**< LIN Sync Field Flag*/
00129 } UART3_Flag_TypeDef;
00130
00131 /**
00132   * @brief  UART3 Interrupt definition
00133   * UART3_IT possible values
00134   * Elements values convention: 0xZYX
00135   * X: Position of the corresponding Interrupt
00136   *   - For the following values, X means the interrupt position in the CR2 register.
00137   *     UART3_IT_TXE
00138   *     UART3_IT_TC
00139   *     UART3_IT_RXNE
00140   *     UART3_IT_IDLE
00141   *     UART3_IT_OR
00142   *   - For the UART3_IT_PE value, X means the flag position in the CR1 register.
00143   *   - For the UART3_IT_LBDF value, X means the flag position in the CR4 register.
00144   *   - For the UART3_IT_LHDF value, X means the flag position in the CR6 register.
00145   * Y: Flag position
00146   *  - For the following values, Y means the flag (pending bit) position in the SR register.
00147   *     UART3_IT_TXE
00148   *     UART3_IT_TC
00149   *     UART3_IT_RXNE
00150   *     UART3_IT_IDLE
00151   *     UART3_IT_OR
00152   *     UART3_IT_PE
00153   *  - For the UART3_IT_LBDF value, Y means the flag position in the CR4 register.
00154   *  - For the UART3_IT_LHDF value, Y means the flag position in the CR6 register.
00155   * Z: Register index: indicate in which register the dedicated interrupt source is:
00156   *  - 1==> CR1 register
00157   *  - 2==> CR2 register
00158   *  - 3==> CR4 register
00159   *  - 4==> CR6 register
00160   */
00161 typedef enum { UART3_IT_TXE        = (uint16_t)0x0277, /**< Transmit interrupt */
00162                UART3_IT_TC         = (uint16_t)0x0266, /**< Transmission Complete interrupt */
00163                UART3_IT_RXNE       = (uint16_t)0x0255, /**< Data Register Not Empty interrupt */
00164                UART3_IT_IDLE       = (uint16_t)0x0244, /**< Idle line detected interrupt */
00165                UART3_IT_OR         = (uint16_t)0x0235, /**< OverRun error interrupt */
00166                UART3_IT_PE         = (uint16_t)0x0100, /**< Parity Error interrupt */
00167                UART3_IT_LBDF       = (uint16_t)0x0346, /**< LIN Break Detection interrupt */
00168                UART3_IT_LHDF       = (uint16_t)0x0412, /**< LIN Header Detection interrupt*/
00169                UART3_IT_RXNE_OR    = (uint16_t)0x0205  /*!< Receive/Overrun interrupt */
00170              } UART3_IT_TypeDef;
00171
00172
00173 /**
00174   * @}
00175   */
00176
00177 /* Exported constants --------------------------------------------------------*/
00178 /* Exported macros ------------------------------------------------------------*/
00179
00180 /* Private macros ------------------------------------------------------------*/
00181
00182 /** @addtogroup UART3_Private_Macros
00183   * @{
00184   */
00185
00186 /**
00187   * @brief  Macro used by the assert_param function in order to check the
00188   *         different sensitivity values for the FLAGs
00189   */
00190 #define IS_UART3_FLAG_OK(Flag) \
00191   (((Flag) == UART3_FLAG_TXE) || \
00192    ((Flag) == UART3_FLAG_TC)  || \
00193    ((Flag) == UART3_FLAG_RXNE) || \
00194    ((Flag) == UART3_FLAG_IDLE) || \
00195    ((Flag) == UART3_FLAG_OR_LHE) || \
00196    ((Flag) == UART3_FLAG_NF) || \
00197    ((Flag) == UART3_FLAG_FE) || \
00198    ((Flag) == UART3_FLAG_PE) || \
00199    ((Flag) == UART3_FLAG_SBK) || \
00200    ((Flag) == UART3_FLAG_LSF) || \
00201    ((Flag) == UART3_FLAG_LHDF) || \
00202    ((Flag) == UART3_FLAG_LBDF))
00203
00204
00205 /**
00206   * @brief  Macro used by the assert_param function in order to check the
00207   *         different sensitivity values for the FLAGs that can be cleared by writing 0
00208   */
00209 #define IS_UART3_CLEAR_FLAG_OK(Flag) \
00210   (((Flag) == UART3_FLAG_RXNE) || \
00211    ((Flag) == UART3_FLAG_LHDF) || \
00212    ((Flag) == UART3_FLAG_LSF) || \
00213    ((Flag) == UART3_FLAG_LBDF))
00214
00215 /**
00216   * @brief  Macro used by the assert_param function in order to check the
00217   *         different sensitivity values for the Interrupts
00218   */
00219
00220 #define IS_UART3_CONFIG_IT_OK(Interrupt) \
00221   (((Interrupt) == UART3_IT_PE) || \
00222    ((Interrupt) == UART3_IT_TXE) || \
00223    ((Interrupt) == UART3_IT_TC) || \
00224    ((Interrupt) == UART3_IT_RXNE_OR ) || \
00225    ((Interrupt) == UART3_IT_IDLE) || \
00226    ((Interrupt) == UART3_IT_LHDF) || \
00227    ((Interrupt) == UART3_IT_LBDF))
00228
00229 /**
00230   * @brief  Macro used by the assert function in order to check the different
00231   *         sensitivity values for the pending bit
00232   */
00233 #define IS_UART3_GET_IT_OK(ITPendingBit) \
00234   (((ITPendingBit) == UART3_IT_TXE)  || \
00235    ((ITPendingBit) == UART3_IT_TC)   || \
00236    ((ITPendingBit) == UART3_IT_RXNE) || \
00237    ((ITPendingBit) == UART3_IT_IDLE) || \
00238    ((ITPendingBit) == UART3_IT_OR)  || \
00239    ((ITPendingBit) == UART3_IT_LBDF)  || \
00240    ((ITPendingBit) == UART3_IT_LHDF)  || \
00241    ((ITPendingBit) == UART3_IT_PE))
00242
00243 /**
00244   * @brief  Macro used by the assert function in order to check the different
00245   *         sensitivity values for the pending bit that can be cleared by writing 0
00246   */
00247 #define IS_UART3_CLEAR_IT_OK(ITPendingBit) \
00248   (((ITPendingBit) == UART3_IT_RXNE) || \
00249    ((ITPendingBit) == UART3_IT_LHDF) || \
00250    ((ITPendingBit) == UART3_IT_LBDF))
00251
00252 /**
00253  * @brief Macro used by the assert_param function in order to check the different
00254  *        sensitivity values for the MODEs
00255  */
00256 #define IS_UART3_MODE_OK(Mode) \
00257   (((Mode) == (uint8_t)UART3_MODE_RX_ENABLE) || \
00258    ((Mode) == (uint8_t)UART3_MODE_RX_DISABLE) || \
00259    ((Mode) == (uint8_t)UART3_MODE_TX_ENABLE) || \
00260    ((Mode) == (uint8_t)UART3_MODE_TX_DISABLE) || \
00261    ((Mode) == (uint8_t)UART3_MODE_TXRX_ENABLE) || \
00262    ((Mode) == (uint8_t)((uint8_t)UART3_MODE_TX_ENABLE|(uint8_t)UART3_MODE_RX_ENABLE)) || \
00263    ((Mode) == (uint8_t)((uint8_t)UART3_MODE_TX_ENABLE|(uint8_t)UART3_MODE_RX_DISABLE)) || \
00264    ((Mode) == (uint8_t)((uint8_t)UART3_MODE_TX_DISABLE|(uint8_t)UART3_MODE_RX_DISABLE)) || \
00265    ((Mode) == (uint8_t)((uint8_t)UART3_MODE_TX_DISABLE|(uint8_t)UART3_MODE_RX_ENABLE)))
00266
00267 /**
00268  * @brief Macro used by the assert_param function in order to check the different
00269  *        sensitivity values for the WordLengths
00270  */
00271 #define IS_UART3_WORDLENGTH_OK(WordLength) \
00272   (((WordLength) == UART3_WORDLENGTH_8D) || \
00273    ((WordLength) == UART3_WORDLENGTH_9D))
00274
00275
00276 /**
00277   * @brief  Macro used by the assert_param function in order to check the different
00278   *         sensitivity values for the WakeUps
00279   */
00280 #define IS_UART3_WAKEUP_OK(WakeUpMode) \
00281   (((WakeUpMode) == UART3_WAKEUP_IDLELINE) || \
00282    ((WakeUpMode) == UART3_WAKEUP_ADDRESSMARK))
00283
00284 /**
00285   * @brief  Macro used by the assert_param function in order to check the different
00286   *         sensitivity values for the LINBreakDetectionLengths
00287   */
00288 #define IS_UART3_LINBREAKDETECTIONLENGTH_OK(LINBreakDetectionLengths) \
00289   (((LINBreakDetectionLengths) == UART3_LINBREAKDETECTIONLENGTH_10BITS) || \
00290    ((LINBreakDetectionLengths) == UART3_LINBREAKDETECTIONLENGTH_11BITS))
00291
00292 /**
00293   * @brief  Macro used by the assert_param function in order to check the different
00294   *         sensitivity values for the UART3_StopBits
00295   */
00296 #define IS_UART3_STOPBITS_OK(StopBit) \
00297   (((StopBit) == UART3_STOPBITS_1) || \
00298    ((StopBit) == UART3_STOPBITS_2))
00299
00300 /**
00301  * @brief Macro used by the assert_param function in order to check the different
00302  *        sensitivity values for the Parity
00303  */
00304 #define IS_UART3_PARITY_OK(Parity) \
00305   (((Parity) == UART3_PARITY_NO) || \
00306    ((Parity) == UART3_PARITY_EVEN) || \
00307    ((Parity) == UART3_PARITY_ODD ))
00308
00309 /**
00310  * @brief Macro used by the assert_param function in order to check the maximum
00311  *        baudrate value
00312  */
00313 #define IS_UART3_BAUDRATE_OK(NUM) ((NUM) <= (uint32_t)625000)
00314
00315 /**
00316  * @brief Macro used by the assert_param function in order to check the address
00317  *        of the UART3 or UART node
00318  */
00319 #define UART3_ADDRESS_MAX ((uint8_t)16)
00320 #define IS_UART3_ADDRESS_OK(Node) ((Node) < UART3_ADDRESS_MAX)
00321
00322 /**
00323  * @brief Macro used by the assert_param function in order to check the LIN mode
00324  */
00325 #define IS_UART3_SLAVE_OK(Mode) \
00326   (((Mode) == UART3_LIN_MODE_MASTER) || \
00327    ((Mode) == UART3_LIN_MODE_SLAVE))
00328
00329 /**
00330  * @brief Macro used by the assert_param function in order to check the LIN
00331  *        automatic resynchronization mode
00332  */
00333 #define IS_UART3_AUTOSYNC_OK(AutosyncMode) \
00334   (((AutosyncMode) ==  UART3_LIN_AUTOSYNC_ENABLE) || \
00335    ((AutosyncMode) == UART3_LIN_AUTOSYNC_DISABLE))
00336
00337 /**
00338  * @brief Macro used by the assert_param function in order to check the LIN
00339  *        divider update method
00340  */
00341 #define IS_UART3_DIVUP_OK(DivupMethod) \
00342   (((DivupMethod) == UART3_LIN_DIVUP_LBRR1) || \
00343    ((DivupMethod) == UART3_LIN_DIVUP_NEXTRXNE))
00344
00345 /**
00346   * @}
00347   */
00348
00349 /* Exported functions ------------------------------------------------------- */
00350
00351 /** @addtogroup UART3_Exported_Functions
00352   * @{
00353   */
00354
00355 void UART3_DeInit(void);
00356 void UART3_Init(uint32_t BaudRate, UART3_WordLength_TypeDef WordLength,
00357                 UART3_StopBits_TypeDef StopBits, UART3_Parity_TypeDef Parity,
00358                 UART3_Mode_TypeDef Mode);
00359 void UART3_Cmd(FunctionalState NewState);
00360 void UART3_ITConfig(UART3_IT_TypeDef UART3_IT, FunctionalState NewState);
00361 void UART3_LINBreakDetectionConfig(UART3_LINBreakDetectionLength_TypeDef UART3_LINBreakDetectionLength);
00362 void UART3_LINConfig(UART3_LinMode_TypeDef UART3_Mode,
00363                      UART3_LinAutosync_TypeDef UART3_Autosync,
00364                      UART3_LinDivUp_TypeDef UART3_DivUp);
00365 void UART3_LINCmd(FunctionalState NewState);
00366 void UART3_ReceiverWakeUpCmd(FunctionalState NewState);
00367 void UART3_WakeUpConfig( UART3_WakeUp_TypeDef UART3_WakeUp);
00368 uint8_t UART3_ReceiveData8(void);
00369 uint16_t UART3_ReceiveData9(void);
00370 void UART3_SendData8(uint8_t Data);
00371 void UART3_SendData9(uint16_t Data);
00372 void UART3_SendBreak(void);
00373 void UART3_SetAddress(uint8_t UART3_Address);
00374 FlagStatus UART3_GetFlagStatus(UART3_Flag_TypeDef UART3_FLAG);
00375 void UART3_ClearFlag(UART3_Flag_TypeDef UART3_FLAG);
00376 ITStatus UART3_GetITStatus(UART3_IT_TypeDef UART3_IT);
00377 void UART3_ClearITPendingBit(UART3_IT_TypeDef UART3_IT);
00378 /**
00379   * @}
00380   */
00381
00382 #endif /* __STM8S_UART3_H */
00383
00384 /**
00385   * @}
00386   */
00387
00388
00389 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_uart4.c Source File

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stm8s_uart4.c
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00001 /**
00002   ********************************************************************************
00003   * @file    stm8s_uart4.c
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all the functions for the UART4 peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm8s_uart4.h"
00030
00031 /** @addtogroup STM8S_StdPeriph_Driver
00032   * @{
00033   */
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 /* Private macro -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038 /* Private function prototypes -----------------------------------------------*/
00039 /* Private functions ---------------------------------------------------------*/
00040 /* Public functions ----------------------------------------------------------*/
00041
00042 /**
00043   * @addtogroup UART4_Public_Functions
00044   * @{
00045   */
00046
00047 /**
00048   * @brief  Deinitializes the UART peripheral.
00049   * @param  None
00050   * @retval None
00051   */
00052
00053 void UART4_DeInit(void)
00054 {
00055   /*  Clear the Idle Line Detected bit in the status register by a read
00056   to the UART4_SR register followed by a Read to the UART4_DR register */
00057   (void)UART4->SR;
00058   (void)UART4->DR;
00059
00060   UART4->BRR2 = UART4_BRR2_RESET_VALUE;  /*  Set UART4_BRR2 to reset value 0x00 */
00061   UART4->BRR1 = UART4_BRR1_RESET_VALUE;  /*  Set UART4_BRR1 to reset value 0x00 */
00062
00063   UART4->CR1 = UART4_CR1_RESET_VALUE; /*  Set UART4_CR1 to reset value 0x00  */
00064   UART4->CR2 = UART4_CR2_RESET_VALUE; /*  Set UART4_CR2 to reset value 0x00  */
00065   UART4->CR3 = UART4_CR3_RESET_VALUE; /*  Set UART4_CR3 to reset value 0x00  */
00066   UART4->CR4 = UART4_CR4_RESET_VALUE; /*  Set UART4_CR4 to reset value 0x00  */
00067   UART4->CR5 = UART4_CR5_RESET_VALUE; /*  Set UART4_CR5 to reset value 0x00  */
00068   UART4->CR6 = UART4_CR6_RESET_VALUE; /*  Set UART4_CR6 to reset value 0x00  */
00069 }
00070
00071 /**
00072   * @brief  Initializes the UART4 according to the specified parameters.
00073   * @param  BaudRate: The baudrate.
00074   * @param  WordLength : This parameter can be any of the
00075   *         @ref UART4_WordLength_TypeDef enumeration.
00076   * @param  StopBits: This parameter can be any of the
00077   *         @ref UART4_StopBits_TypeDef enumeration.
00078   * @param  Parity: This parameter can be any of the
00079   *         @ref UART4_Parity_TypeDef enumeration.
00080   * @param  SyncMode: This parameter can be any of the
00081   *         @ref UART4_SyncMode_TypeDef values.
00082   * @param  Mode: This parameter can be any of the @ref UART4_Mode_TypeDef values
00083   * @retval None
00084   */
00085 void UART4_Init(uint32_t BaudRate, UART4_WordLength_TypeDef WordLength, UART4_StopBits_TypeDef StopBits, UART4_Parity_TypeDef Parity, UART4_SyncMode_TypeDef SyncMode, UART4_Mode_TypeDef Mode)
00086 {
00087   uint8_t BRR2_1 = 0, BRR2_2 = 0;
00088   uint32_t BaudRate_Mantissa = 0, BaudRate_Mantissa100 = 0;
00089
00090   /* Check the parameters */
00091   assert_param(IS_UART4_BAUDRATE_OK(BaudRate));
00092   assert_param(IS_UART4_WORDLENGTH_OK(WordLength));
00093   assert_param(IS_UART4_STOPBITS_OK(StopBits));
00094   assert_param(IS_UART4_PARITY_OK(Parity));
00095   assert_param(IS_UART4_MODE_OK((uint8_t)Mode));
00096   assert_param(IS_UART4_SYNCMODE_OK((uint8_t)SyncMode));
00097
00098   /* Clear the word length bit */
00099   UART4->CR1 &= (uint8_t)(~UART4_CR1_M);
00100   /* Set the word length bit according to UART4_WordLength value */
00101   UART4->CR1 |= (uint8_t)WordLength;
00102
00103   /* Clear the STOP bits */
00104   UART4->CR3 &= (uint8_t)(~UART4_CR3_STOP);
00105   /* Set the STOP bits number according to UART4_StopBits value  */
00106   UART4->CR3 |= (uint8_t)StopBits;
00107
00108   /* Clear the Parity Control bit */
00109   UART4->CR1 &= (uint8_t)(~(UART4_CR1_PCEN | UART4_CR1_PS  ));
00110   /* Set the Parity Control bit to UART4_Parity value */
00111   UART4->CR1 |= (uint8_t)Parity;
00112
00113   /* Clear the LSB mantissa of UART4DIV  */
00114   UART4->BRR1 &= (uint8_t)(~UART4_BRR1_DIVM);
00115   /* Clear the MSB mantissa of UART4DIV  */
00116   UART4->BRR2 &= (uint8_t)(~UART4_BRR2_DIVM);
00117   /* Clear the Fraction bits of UART4DIV */
00118   UART4->BRR2 &= (uint8_t)(~UART4_BRR2_DIVF);
00119
00120   /* Set the UART4 BaudRates in BRR1 and BRR2 registers according to UART4_BaudRate value */
00121   BaudRate_Mantissa    = ((uint32_t)CLK_GetClockFreq() / (BaudRate << 4));
00122   BaudRate_Mantissa100 = (((uint32_t)CLK_GetClockFreq() * 100) / (BaudRate << 4));
00123
00124   /* The fraction and MSB mantissa should be loaded in one step in the BRR2 register*/
00125   /* Set the fraction of UARTDIV  */
00126   BRR2_1 = (uint8_t)((uint8_t)(((BaudRate_Mantissa100 - (BaudRate_Mantissa * 100))
00127                                 << 4) / 100) & (uint8_t)0x0F);
00128   BRR2_2 = (uint8_t)((BaudRate_Mantissa >> 4) & (uint8_t)0xF0);
00129
00130   UART4->BRR2 = (uint8_t)(BRR2_1 | BRR2_2);
00131   /* Set the LSB mantissa of UARTDIV  */
00132   UART4->BRR1 = (uint8_t)BaudRate_Mantissa;
00133
00134   /* Disable the Transmitter and Receiver before setting the LBCL, CPOL and CPHA bits */
00135   UART4->CR2 &= (uint8_t)~(UART4_CR2_TEN | UART4_CR2_REN);
00136   /* Clear the Clock Polarity, lock Phase, Last Bit Clock pulse */
00137   UART4->CR3 &= (uint8_t)~(UART4_CR3_CPOL | UART4_CR3_CPHA | UART4_CR3_LBCL);
00138   /* Set the Clock Polarity, lock Phase, Last Bit Clock pulse */
00139   UART4->CR3 |= (uint8_t)((uint8_t)SyncMode & (uint8_t)(UART4_CR3_CPOL | \
00140     UART4_CR3_CPHA | UART4_CR3_LBCL));
00141
00142   if((uint8_t)(Mode & UART4_MODE_TX_ENABLE))
00143   {
00144     /* Set the Transmitter Enable bit */
00145     UART4->CR2 |= (uint8_t)UART4_CR2_TEN;
00146   }
00147   else
00148   {
00149     /* Clear the Transmitter Disable bit */
00150     UART4->CR2 &= (uint8_t)(~UART4_CR2_TEN);
00151   }
00152   if((uint8_t)(Mode & UART4_MODE_RX_ENABLE))
00153   {
00154     /* Set the Receiver Enable bit */
00155     UART4->CR2 |= (uint8_t)UART4_CR2_REN;
00156   }
00157   else
00158   {
00159     /* Clear the Receiver Disable bit */
00160     UART4->CR2 &= (uint8_t)(~UART4_CR2_REN);
00161   }
00162   /* Set the Clock Enable bit, lock Polarity, lock Phase and Last Bit Clock
00163   pulse bits according to UART4_Mode value */
00164   if((uint8_t)(SyncMode & UART4_SYNCMODE_CLOCK_DISABLE))
00165   {
00166     /* Clear the Clock Enable bit */
00167     UART4->CR3 &= (uint8_t)(~UART4_CR3_CKEN);
00168   }
00169   else
00170   {
00171     UART4->CR3 |= (uint8_t)((uint8_t)SyncMode & UART4_CR3_CKEN);
00172   }
00173 }
00174
00175 /**
00176   * @brief  Enable the UART4 peripheral.
00177   * @param  NewState : The new state of the UART Communication.
00178   *         This parameter can be any of the @ref FunctionalState enumeration.
00179   * @retval None
00180   */
00181 void UART4_Cmd(FunctionalState NewState)
00182 {
00183   if(NewState != DISABLE)
00184   {
00185     /* UART4 Enable */
00186     UART4->CR1 &= (uint8_t)(~UART4_CR1_UARTD);
00187   }
00188   else
00189   {
00190     /* UART4 Disable */
00191     UART4->CR1 |= UART4_CR1_UARTD;
00192   }
00193 }
00194
00195 /**
00196   * @brief  Enables or disables the specified UART4 interrupts.
00197   * @param  UART4_IT specifies the UART4 interrupt sources to be enabled or disabled.
00198   *         This parameter can be one of the following values:
00199   *         - UART4_IT_LBDF:  LIN Break detection interrupt
00200   *         - UART4_IT_LHDF:  LIN Break detection interrupt
00201   *         - UART4_IT_TXE:  Transmit Data Register empty interrupt
00202   *         - UART4_IT_TC:   Transmission complete interrupt
00203   *         - UART4_IT_RXNE_OR: Receive Data register not empty/Over run error interrupt
00204   *         - UART4_IT_IDLE: Idle line detection interrupt
00205   *         - UART4_IT_PE:   Parity Error interrupt
00206   * @param  NewState new state of the specified UART4 interrupts.
00207   *         This parameter can be: ENABLE or DISABLE.
00208   * @retval None
00209   */
00210 void UART4_ITConfig(UART4_IT_TypeDef UART4_IT, FunctionalState NewState)
00211 {
00212   uint8_t uartreg = 0, itpos = 0x00;
00213
00214   /* Check the parameters */
00215   assert_param(IS_UART4_CONFIG_IT_OK(UART4_IT));
00216   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00217
00218   /* Get the UART4 register index */
00219   uartreg = (uint8_t)((uint16_t)UART4_IT >> 0x08);
00220
00221   /* Get the UART4 IT index */
00222   itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)UART4_IT & (uint8_t)0x0F));
00223
00224   if(NewState != DISABLE)
00225   {
00226     /* Enable the Interrupt bits according to UART4_IT mask */
00227     if(uartreg == 0x01)
00228     {
00229       UART4->CR1 |= itpos;
00230     }
00231     else if(uartreg == 0x02)
00232     {
00233       UART4->CR2 |= itpos;
00234     }
00235     else if(uartreg == 0x03)
00236     {
00237       UART4->CR4 |= itpos;
00238     }
00239     else
00240     {
00241       UART4->CR6 |= itpos;
00242     }
00243   }
00244   else
00245   {
00246     /* Disable the interrupt bits according to UART4_IT mask */
00247     if(uartreg == 0x01)
00248     {
00249       UART4->CR1 &= (uint8_t)(~itpos);
00250     }
00251     else if(uartreg == 0x02)
00252     {
00253       UART4->CR2 &= (uint8_t)(~itpos);
00254     }
00255     else if(uartreg == 0x03)
00256     {
00257       UART4->CR4 &= (uint8_t)(~itpos);
00258     }
00259     else
00260     {
00261       UART4->CR6 &= (uint8_t)(~itpos);
00262     }
00263   }
00264 }
00265
00266 /**
00267   * @brief  Enables or disables the UART’s Half Duplex communication.
00268   * @param  NewState new state of the UART Communication.
00269   *         This parameter can be: ENABLE or DISABLE.
00270   * @retval None
00271   */
00272 void UART4_HalfDuplexCmd(FunctionalState NewState)
00273 {
00274   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00275
00276   if (NewState != DISABLE)
00277   {
00278     UART4->CR5 |= UART4_CR5_HDSEL;  /**< UART4 Half Duplex Enable  */
00279   }
00280   else
00281   {
00282     UART4->CR5 &= (uint8_t)~UART4_CR5_HDSEL; /**< UART4 Half Duplex Disable */
00283   }
00284 }
00285
00286 /**
00287   * @brief  Configures the UART4’s IrDA interface.
00288   * @param  UART4_IrDAMode specifies the IrDA mode.
00289   *         This parameter can be any of the @ref UART4_IrDAMode_TypeDef values.
00290   * @retval None
00291   */
00292 void UART4_IrDAConfig(UART4_IrDAMode_TypeDef UART4_IrDAMode)
00293 {
00294   assert_param(IS_UART4_IRDAMODE_OK(UART4_IrDAMode));
00295
00296   if(UART4_IrDAMode != UART4_IRDAMODE_NORMAL)
00297   {
00298     UART4->CR5 |= UART4_CR5_IRLP;
00299   }
00300   else
00301   {
00302     UART4->CR5 &= ((uint8_t)~UART4_CR5_IRLP);
00303   }
00304 }
00305
00306 /**
00307   * @brief  Enables or disables the UART4’s IrDA interface.
00308   * @param  NewState new state of the IrDA mode.
00309   *         This parameter can be: ENABLE or DISABLE.
00310   * @retval None
00311   */
00312 void UART4_IrDACmd(FunctionalState NewState)
00313 {
00314   /* Check parameters */
00315   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00316
00317   if(NewState != DISABLE)
00318   {
00319     /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
00320     UART4->CR5 |= UART4_CR5_IREN;
00321   }
00322   else
00323   {
00324     /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
00325     UART4->CR5 &= ((uint8_t)~UART4_CR5_IREN);
00326   }
00327 }
00328
00329 /**
00330   * @brief  Sets the UART4 LIN Break detection length.
00331   * @param  UART4_LINBreakDetectionLength specifies the LIN break detection length.
00332   *         This parameter can be any of the
00333   *         @ref UART4_LINBreakDetectionLength_TypeDef values.
00334   * @retval None
00335   */
00336 void UART4_LINBreakDetectionConfig(UART4_LINBreakDetectionLength_TypeDef UART4_LINBreakDetectionLength)
00337 {
00338   /* Check parameters */
00339   assert_param(IS_UART4_LINBREAKDETECTIONLENGTH_OK(UART4_LINBreakDetectionLength));
00340
00341   if(UART4_LINBreakDetectionLength != UART4_LINBREAKDETECTIONLENGTH_10BITS)
00342   {
00343     UART4->CR4 |= UART4_CR4_LBDL;
00344   }
00345   else
00346   {
00347     UART4->CR4 &= ((uint8_t)~UART4_CR4_LBDL);
00348   }
00349 }
00350
00351 /**
00352   * @brief  Configure the UART4 peripheral.
00353   * @param  UART4_Mode specifies the LIN mode.
00354   *         This parameter can be any of the @ref UART4_LinMode_TypeDef values.
00355   * @param  UART4_Autosync specifies the LIN automatic resynchronization mode.
00356   *         This parameter can be any of the @ref UART4_LinAutosync_TypeDef values.
00357   * @param  UART4_DivUp specifies the LIN divider update method.
00358   *         This parameter can be any of the @ref UART4_LinDivUp_TypeDef values.
00359   * @retval None
00360   */
00361 void UART4_LINConfig(UART4_LinMode_TypeDef UART4_Mode,
00362                      UART4_LinAutosync_TypeDef UART4_Autosync,
00363                      UART4_LinDivUp_TypeDef UART4_DivUp)
00364 {
00365   /* Check parameters */
00366   assert_param(IS_UART4_SLAVE_OK(UART4_Mode));
00367   assert_param(IS_UART4_AUTOSYNC_OK(UART4_Autosync));
00368   assert_param(IS_UART4_DIVUP_OK(UART4_DivUp));
00369
00370   if(UART4_Mode != UART4_LIN_MODE_MASTER)
00371   {
00372     UART4->CR6 |=  UART4_CR6_LSLV;
00373   }
00374   else
00375   {
00376     UART4->CR6 &= ((uint8_t)~UART4_CR6_LSLV);
00377   }
00378
00379   if(UART4_Autosync != UART4_LIN_AUTOSYNC_DISABLE)
00380   {
00381     UART4->CR6 |=  UART4_CR6_LASE ;
00382   }
00383   else
00384   {
00385     UART4->CR6 &= ((uint8_t)~ UART4_CR6_LASE );
00386   }
00387
00388   if(UART4_DivUp != UART4_LIN_DIVUP_LBRR1)
00389   {
00390     UART4->CR6 |=  UART4_CR6_LDUM;
00391   }
00392   else
00393   {
00394     UART4->CR6 &= ((uint8_t)~ UART4_CR6_LDUM);
00395   }
00396 }
00397
00398 /**
00399   * @brief  Enables or disables the UART4 LIN mode.
00400   * @param  NewState is new state of the UART4 LIN mode.
00401   *         This parameter can be ENABLE or DISABLE
00402   * @retval None
00403   */
00404 void UART4_LINCmd(FunctionalState NewState)
00405 {
00406   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00407
00408   if(NewState != DISABLE)
00409   {
00410     /* Enable the LIN mode by setting the LINE bit in the CR2 register */
00411     UART4->CR3 |= UART4_CR3_LINEN;
00412   }
00413   else
00414   {
00415     /* Disable the LIN mode by clearing the LINE bit in the CR2 register */
00416     UART4->CR3 &= ((uint8_t)~UART4_CR3_LINEN);
00417   }
00418 }
00419
00420 /**
00421   * @brief  Enables or disables the UART4 Smart Card mode.
00422   * @param  NewState: new state of the Smart Card mode.
00423   *         This parameter can be: ENABLE or DISABLE.
00424   * @retval None
00425   */
00426 void UART4_SmartCardCmd(FunctionalState NewState)
00427 {
00428   /* Check parameters */
00429   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00430
00431   if(NewState != DISABLE)
00432   {
00433     /* Enable the SC mode by setting the SCEN bit in the CR5 register */
00434     UART4->CR5 |= UART4_CR5_SCEN;
00435   }
00436   else
00437   {
00438     /* Disable the SC mode by clearing the SCEN bit in the CR5 register */
00439     UART4->CR5 &= ((uint8_t)(~UART4_CR5_SCEN));
00440   }
00441 }
00442
00443 /**
00444   * @brief  Enables or disables NACK transmission.
00445   * @param  NewState: new state of the Smart Card mode.
00446   *         This parameter can be: ENABLE or DISABLE.
00447   * @retval None
00448   */
00449 void UART4_SmartCardNACKCmd(FunctionalState NewState)
00450 {
00451   /* Check parameters */
00452   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00453
00454   if(NewState != DISABLE)
00455   {
00456     /* Enable the NACK transmission by setting the NACK bit in the CR5 register */
00457     UART4->CR5 |= UART4_CR5_NACK;
00458   }
00459   else
00460   {
00461     /* Disable the NACK transmission by clearing the NACK bit in the CR5 register */
00462     UART4->CR5 &= ((uint8_t)~(UART4_CR5_NACK));
00463   }
00464 }
00465
00466 /**
00467   * @brief  Selects the UART4 WakeUp method.
00468   * @param  UART4_WakeUp: specifies the UART4 wakeup method.
00469   *         This parameter can be any of the @ref UART4_WakeUp_TypeDef values.
00470   * @retval None
00471   */
00472 void UART4_WakeUpConfig(UART4_WakeUp_TypeDef UART4_WakeUp)
00473 {
00474   assert_param(IS_UART4_WAKEUP_OK(UART4_WakeUp));
00475
00476   UART4->CR1 &= ((uint8_t)~UART4_CR1_WAKE);
00477   UART4->CR1 |= (uint8_t)UART4_WakeUp;
00478 }
00479
00480 /**
00481   * @brief  Determines if the UART4 is in mute mode or not.
00482   * @param  NewState: new state of the UART4 mode.
00483   *         This parameter can be ENABLE or DISABLE
00484   * @retval None
00485   */
00486 void UART4_ReceiverWakeUpCmd(FunctionalState NewState)
00487 {
00488   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00489
00490   if(NewState != DISABLE)
00491   {
00492     /* Enable the mute mode UART4 by setting the RWU bit in the CR2 register */
00493     UART4->CR2 |= UART4_CR2_RWU;
00494   }
00495   else
00496   {
00497     /* Disable the mute mode UART4 by clearing the RWU bit in the CR1 register */
00498     UART4->CR2 &= ((uint8_t)~UART4_CR2_RWU);
00499   }
00500 }
00501
00502 /**
00503   * @brief  Returns the most recent received data by the UART4 peripheral.
00504   * @param  None
00505   * @retval Received Data
00506   */
00507 uint8_t UART4_ReceiveData8(void)
00508 {
00509   return ((uint8_t)UART4->DR);
00510 }
00511
00512 /**
00513   * @brief  Returns the most recent received data by the UART4 peripheral.
00514   * @param  None
00515   * @retval Received Data
00516   */
00517 uint16_t UART4_ReceiveData9(void)
00518 {
00519   uint16_t temp = 0;
00520
00521   temp = ((uint16_t)(((uint16_t)((uint16_t)UART4->CR1 & (uint16_t)UART4_CR1_R8)) << 1));
00522
00523   return (uint16_t)((((uint16_t)UART4->DR) | temp) & ((uint16_t)0x01FF));
00524 }
00525
00526 /**
00527   * @brief  Transmits 8 bit data through the UART4 peripheral.
00528   * @param  Data: the data to transmit.
00529   * @retval None
00530   */
00531 void UART4_SendData8(uint8_t Data)
00532 {
00533   /* Transmit Data */
00534   UART4->DR = Data;
00535 }
00536
00537 /**
00538   * @brief  Transmits 9 bit data through the UART4 peripheral.
00539   * @param  Data: the data to transmit.
00540   * @retval None
00541   */
00542 void UART4_SendData9(uint16_t Data)
00543 {
00544   /* Clear the transmit data bit 8 */
00545   UART4->CR1 &= ((uint8_t)~UART4_CR1_T8);
00546
00547   /* Write the transmit data bit [8] */
00548   UART4->CR1 |= (uint8_t)(((uint8_t)(Data >> 2)) & UART4_CR1_T8);
00549
00550   /* Write the transmit data bit [0:7] */
00551   UART4->DR   = (uint8_t)(Data);
00552 }
00553
00554 /**
00555   * @brief  Transmits break characters.
00556   * @param  None
00557   * @retval None
00558   */
00559 void UART4_SendBreak(void)
00560 {
00561   UART4->CR2 |= UART4_CR2_SBK;
00562 }
00563
00564 /**
00565   * @brief  Sets the address of the UART4 node.
00566   * @param  UART4_Address: Indicates the address of the UART4 node.
00567   * @retval None
00568   */
00569 void UART4_SetAddress(uint8_t UART4_Address)
00570 {
00571   /*assert_param for x UART4_Address*/
00572   assert_param(IS_UART4_ADDRESS_OK(UART4_Address));
00573
00574   /* Clear the UART4 address */
00575   UART4->CR4 &= ((uint8_t)~UART4_CR4_ADD);
00576   /* Set the UART4 address node */
00577   UART4->CR4 |= UART4_Address;
00578 }
00579
00580 /**
00581   * @brief  Sets the specified UART4 guard time.
00582   * @note   SmartCard Mode should be Enabled
00583   * @param  UART4_GuardTime: specifies the guard time.
00584   * @retval None
00585   */
00586 void UART4_SetGuardTime(uint8_t UART4_GuardTime)
00587 {
00588   /* Set the UART4 guard time */
00589   UART4->GTR = UART4_GuardTime;
00590 }
00591
00592 /**
00593   * @brief  Sets the system clock prescaler.
00594   * @note   IrDA Low Power mode or smartcard mode should be enabled
00595   * @note   This function is related to SmartCard and IrDa mode.
00596   * @param  UART4_Prescaler: specifies the prescaler clock.
00597   *         This parameter can be one of the following values:
00598   *         @par IrDA Low Power Mode
00599   *         The clock source is divided by the value given in the register (8 bits)
00600   *         - 0000 0000 Reserved
00601   *         - 0000 0001 divides the clock source by 1
00602   *         - 0000 0010 divides the clock source by 2
00603   *         - ...
00604   *        @par Smart Card Mode
00605   *        The clock source is divided by the value given in the register
00606   *        (5 significant bits) multiplied by 2
00607   *         - 0 0000 Reserved
00608   *         - 0 0001 divides the clock source by 2
00609   *         - 0 0010 divides the clock source by 4
00610   *         - 0 0011 divides the clock source by 6
00611   *         - ...
00612   * @retval None
00613   */
00614 void UART4_SetPrescaler(uint8_t UART4_Prescaler)
00615 {
00616   /* Load the UART4 prescaler value*/
00617   UART4->PSCR = UART4_Prescaler;
00618 }
00619
00620 /**
00621   * @brief  Checks whether the specified UART4 flag is set or not.
00622   * @param  UART4_FLAG specifies the flag to check.
00623   *         This parameter can be any of the @ref UART4_Flag_TypeDef enumeration.
00624   * @retval FlagStatus (SET or RESET)
00625   */
00626 FlagStatus UART4_GetFlagStatus(UART4_Flag_TypeDef UART4_FLAG)
00627 {
00628   FlagStatus status = RESET;
00629
00630   /* Check parameters */
00631   assert_param(IS_UART4_FLAG_OK(UART4_FLAG));
00632
00633   /* Check the status of the specified UART4 flag*/
00634   if(UART4_FLAG == UART4_FLAG_LBDF)
00635   {
00636     if((UART4->CR4 & (uint8_t)UART4_FLAG) != (uint8_t)0x00)
00637     {
00638       /* UART4_FLAG is set*/
00639       status = SET;
00640     }
00641     else
00642     {
00643       /* UART4_FLAG is reset*/
00644       status = RESET;
00645     }
00646   }
00647   else if(UART4_FLAG == UART4_FLAG_SBK)
00648   {
00649     if((UART4->CR2 & (uint8_t)UART4_FLAG) != (uint8_t)0x00)
00650     {
00651       /* UART4_FLAG is set*/
00652       status = SET;
00653     }
00654     else
00655     {
00656       /* UART4_FLAG is reset*/
00657       status = RESET;
00658     }
00659   }
00660   else if((UART4_FLAG == UART4_FLAG_LHDF) || (UART4_FLAG == UART4_FLAG_LSF))
00661   {
00662     if((UART4->CR6 & (uint8_t)UART4_FLAG) != (uint8_t)0x00)
00663     {
00664       /* UART4_FLAG is set*/
00665       status = SET;
00666     }
00667     else
00668     {
00669       /* UART4_FLAG is reset*/
00670       status = RESET;
00671     }
00672   }
00673   else
00674   {
00675     if((UART4->SR & (uint8_t)UART4_FLAG) != (uint8_t)0x00)
00676     {
00677       /* UART4_FLAG is set*/
00678       status = SET;
00679     }
00680     else
00681     {
00682       /* UART4_FLAG is reset*/
00683       status = RESET;
00684     }
00685   }
00686
00687   /* Return the UART4_FLAG status*/
00688   return  status;
00689 }
00690
00691 /**
00692   * @brief  Clears the UART4 flags.
00693   * @param  UART4_FLAG specifies the flag to clear
00694   *         This parameter can be any combination of the following values:
00695   *         - UART4_FLAG_LBDF: LIN Break detection flag.
00696   *         - UART4_FLAG_LHDF: LIN Header detection flag.
00697   *         - UART4_FLAG_LSF: LIN synchrone field flag.
00698   *         - UART4_FLAG_RXNE: Receive data register not empty flag.
00699   * @note:
00700   *         - PE (Parity error), FE (Framing error), NE (Noise error),
00701   *           OR (OverRun error) and IDLE (Idle line detected) flags are cleared
00702   *           by software sequence: a read operation to UART4_SR register
00703   *           (UART4_GetFlagStatus())followed by a read operation to UART4_DR
00704   *           register(UART4_ReceiveData8() or UART4_ReceiveData9()).
00705   *
00706   *         - RXNE flag can be also cleared by a read to the UART4_DR register
00707   *           (UART4_ReceiveData8()or UART4_ReceiveData9()).
00708   *
00709   *         - TC flag can be also cleared by software sequence: a read operation
00710   *           to UART4_SR register (UART4_GetFlagStatus()) followed by a write
00711   *           operation to UART4_DR register (UART4_SendData8() or UART4_SendData9()).
00712   *
00713   *         - TXE flag is cleared only by a write to the UART4_DR register
00714   *           (UART4_SendData8() or UART4_SendData9()).
00715   *
00716   *         - SBK flag is cleared during the stop bit of break.
00717   * @retval None
00718   */
00719 void UART4_ClearFlag(UART4_Flag_TypeDef UART4_FLAG)
00720 {
00721   assert_param(IS_UART4_CLEAR_FLAG_OK(UART4_FLAG));
00722
00723   /*  Clear the Receive Register Not Empty flag */
00724   if(UART4_FLAG == UART4_FLAG_RXNE)
00725   {
00726     UART4->SR = (uint8_t)~(UART4_SR_RXNE);
00727   }
00728   /*  Clear the LIN Break Detection flag */
00729   else if(UART4_FLAG == UART4_FLAG_LBDF)
00730   {
00731     UART4->CR4 &= (uint8_t)(~UART4_CR4_LBDF);
00732   }
00733   /*  Clear the LIN Header Detection Flag */
00734   else if(UART4_FLAG == UART4_FLAG_LHDF)
00735   {
00736     UART4->CR6 &= (uint8_t)(~UART4_CR6_LHDF);
00737   }
00738   /*  Clear the LIN Synch Field flag */
00739   else
00740   {
00741     UART4->CR6 &= (uint8_t)(~UART4_CR6_LSF);
00742   }
00743 }
00744
00745 /**
00746   * @brief  Checks whether the specified UART4 interrupt has occurred or not.
00747   * @param  UART4_IT: Specifies the UART4 interrupt pending bit to check.
00748   *         This parameter can be one of the following values:
00749   *         - UART4_IT_LBDF:  LIN Break detection interrupt
00750   *         - UART4_IT_TXE:  Transmit Data Register empty interrupt
00751   *         - UART4_IT_TC:   Transmission complete interrupt
00752   *         - UART4_IT_RXNE: Receive Data register not empty interrupt
00753   *         - UART4_IT_IDLE: Idle line detection interrupt
00754   *         - UART4_IT_OR:  OverRun Error interrupt
00755   *         - UART4_IT_PE:   Parity Error interrupt
00756   * @retval The state of UART4_IT (SET or RESET).
00757   */
00758 ITStatus UART4_GetITStatus(UART4_IT_TypeDef UART4_IT)
00759 {
00760   ITStatus pendingbitstatus = RESET;
00761   uint8_t itpos = 0;
00762   uint8_t itmask1 = 0;
00763   uint8_t itmask2 = 0;
00764   uint8_t enablestatus = 0;
00765
00766   /* Check parameters */
00767   assert_param(IS_UART4_GET_IT_OK(UART4_IT));
00768
00769   /* Get the UART4 IT index*/
00770   itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)UART4_IT & (uint8_t)0x0F));
00771   /* Get the UART4 IT index*/
00772   itmask1 = (uint8_t)((uint8_t)UART4_IT >> (uint8_t)4);
00773   /* Set the IT mask*/
00774   itmask2 = (uint8_t)((uint8_t)1 << itmask1);
00775
00776   /* Check the status of the specified UART4 pending bit*/
00777   if(UART4_IT == UART4_IT_PE)
00778   {
00779     /* Get the UART4_ITPENDINGBIT enable bit status*/
00780     enablestatus = (uint8_t)((uint8_t)UART4->CR1 & itmask2);
00781     /* Check the status of the specified UART4 interrupt*/
00782
00783     if(((UART4->SR & itpos) != (uint8_t)0x00) && enablestatus)
00784     {
00785       /* Interrupt occurred*/
00786       pendingbitstatus = SET;
00787     }
00788     else
00789     {
00790       /* Interrupt not occurred*/
00791       pendingbitstatus = RESET;
00792     }
00793   }
00794   else if(UART4_IT == UART4_IT_LBDF)
00795   {
00796     /* Get the UART4_IT enable bit status*/
00797     enablestatus = (uint8_t)((uint8_t)UART4->CR4 & itmask2);
00798     /* Check the status of the specified UART4 interrupt*/
00799     if(((UART4->CR4 & itpos) != (uint8_t)0x00) && enablestatus)
00800     {
00801       /* Interrupt occurred*/
00802       pendingbitstatus = SET;
00803     }
00804     else
00805     {
00806       /* Interrupt not occurred*/
00807       pendingbitstatus = RESET;
00808     }
00809   }
00810   else if(UART4_IT == UART4_IT_LHDF)
00811   {
00812     /* Get the UART4_IT enable bit status*/
00813     enablestatus = (uint8_t)((uint8_t)UART4->CR6 & itmask2);
00814     /* Check the status of the specified UART4 interrupt*/
00815     if(((UART4->CR6 & itpos) != (uint8_t)0x00) && enablestatus)
00816     {
00817       /* Interrupt occurred*/
00818       pendingbitstatus = SET;
00819     }
00820     else
00821     {
00822       /* Interrupt not occurred*/
00823       pendingbitstatus = RESET;
00824     }
00825   }
00826   else
00827   {
00828     /* Get the UART4_IT enable bit status*/
00829     enablestatus = (uint8_t)((uint8_t)UART4->CR2 & itmask2);
00830     /* Check the status of the specified UART4 interrupt*/
00831     if(((UART4->SR & itpos) != (uint8_t)0x00) && enablestatus)
00832     {
00833       /* Interrupt occurred*/
00834       pendingbitstatus = SET;
00835     }
00836     else
00837     {
00838       /* Interrupt not occurred*/
00839       pendingbitstatus = RESET;
00840     }
00841   }
00842   /* Return the UART4_IT status*/
00843   return  pendingbitstatus;
00844 }
00845
00846 /**
00847   * @brief  Clears the UART4 pending flags.
00848   * @param  UART4_IT specifies the pending bit to clear
00849   *         This parameter can be one of the following values:
00850   *         - UART4_IT_LBDF:  LIN Break detection interrupt
00851   *         - UART4_IT_LHDF:  LIN Header detection interrupt
00852   *         - UART4_IT_RXNE: Receive Data register not empty interrupt.
00853   * @note
00854   *         - PE (Parity error), FE (Framing error), NE (Noise error),
00855   *           OR (OverRun error) and IDLE (Idle line detected) pending bits are
00856   *           cleared by software sequence: a read operation to UART4_SR register
00857   *           (UART4_GetITStatus()) followed by a read operation to UART4_DR register
00858   *           (UART4_ReceiveData8() or UART4_ReceiveData9()).
00859   *
00860   *         - RXNE pending bit can be also cleared by a read to the UART4_DR
00861   *           register (UART4_ReceiveData8() or UART4_ReceiveData9()).
00862   *
00863   *         - TC (Transmit complete) pending bit can be cleared by software
00864   *           sequence: a read operation to UART4_SR register
00865   *           (UART4_GetITStatus()) followed by a write operation to UART4_DR
00866   *           register (UART4_SendData8()or UART4_SendData9()).
00867   *
00868   *         - TXE pending bit is cleared only by a write to the UART4_DR register
00869   *           (UART4_SendData8() or UART4_SendData9()).
00870   * @retval None
00871   */
00872 void UART4_ClearITPendingBit(UART4_IT_TypeDef UART4_IT)
00873 {
00874   assert_param(IS_UART4_CLEAR_IT_OK(UART4_IT));
00875
00876   /*  Clear the Receive Register Not Empty pending bit */
00877   if(UART4_IT == UART4_IT_RXNE)
00878   {
00879     UART4->SR = (uint8_t)~(UART4_SR_RXNE);
00880   }
00881   /*  Clear the LIN Break Detection pending bit */
00882   else if(UART4_IT == UART4_IT_LBDF)
00883   {
00884     UART4->CR4 &= (uint8_t)~(UART4_CR4_LBDF);
00885   }
00886   /*  Clear the LIN Header Detection pending bit */
00887   else
00888   {
00889     UART4->CR6 &= (uint8_t)(~UART4_CR6_LHDF);
00890   }
00891 }
00892
00893 /**
00894   * @}
00895   */
00896
00897 /**
00898   * @}
00899   */
00900
00901
00902 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_uart4.h Source File

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stm8s_uart4.h
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00001 /**
00002   ********************************************************************************
00003   * @file    stm8s_uart4.h
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all functions prototypes and macros for the UART4 peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Define to prevent recursive inclusion -------------------------------------*/
00029 #ifndef __STM8S_UART4_H
00030 #define __STM8S_UART4_H
00031
00032 /* Includes ------------------------------------------------------------------*/
00033 #include "stm8s.h"
00034
00035 /** @addtogroup STM8S_StdPeriph_Driver
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040
00041 /** @addtogroup UART4_Exported_Types
00042   * @{
00043   */
00044
00045 /**
00046   * @brief  UART4 Irda Modes
00047   */
00048
00049 typedef enum { UART4_IRDAMODE_NORMAL     = (uint8_t)0x00, /**< 0x00 Irda Normal Mode   */
00050                UART4_IRDAMODE_LOWPOWER   = (uint8_t)0x01  /**< 0x01 Irda Low Power Mode */
00051
00052              } UART4_IrDAMode_TypeDef;
00053
00054 /**
00055   * @brief  UART4 WakeUP Modes
00056   */
00057
00058 typedef enum { UART4_WAKEUP_IDLELINE       = (uint8_t)0x00, /**< 0x01 Idle Line wake up */
00059                UART4_WAKEUP_ADDRESSMARK    = (uint8_t)0x08  /**< 0x02 Address Mark wake up */
00060              } UART4_WakeUp_TypeDef;
00061
00062
00063 /**
00064   * @brief  UART4 LIN Break detection length possible values
00065   */
00066 typedef enum { UART4_LINBREAKDETECTIONLENGTH_10BITS = (uint8_t)0x00, /**< 0x01 10 bits Lin Break detection */
00067                UART4_LINBREAKDETECTIONLENGTH_11BITS = (uint8_t)0x01  /**< 0x02 11 bits Lin Break detection */
00068              } UART4_LINBreakDetectionLength_TypeDef;
00069
00070 /**
00071   * @brief  UART4 stop bits possible values
00072   */
00073
00074 typedef enum { UART4_STOPBITS_1   = (uint8_t)0x00,    /**< One stop bit is  transmitted at the end of frame*/
00075                UART4_STOPBITS_0_5 = (uint8_t)0x10,    /**< Half stop bits is transmitted at the end of frame*/
00076                UART4_STOPBITS_2   = (uint8_t)0x20,    /**< Two stop bits are  transmitted at the end of frame*/
00077                UART4_STOPBITS_1_5 = (uint8_t)0x30     /**< One and half stop bits*/
00078              } UART4_StopBits_TypeDef;
00079
00080
00081 /**
00082   * @brief  UART4 parity possible values
00083   */
00084 typedef enum { UART4_PARITY_NO     = (uint8_t)0x00,      /**< No Parity*/
00085                UART4_PARITY_EVEN   = (uint8_t)0x04,      /**< Even Parity*/
00086                UART4_PARITY_ODD    = (uint8_t)0x06       /**< Odd Parity*/
00087              } UART4_Parity_TypeDef;
00088 /**
00089   * @brief  UART4 Mode possible values
00090   */
00091 typedef enum { UART4_LIN_MODE_MASTER  = (uint8_t)0x00, /**<  LIN Master Mode*/
00092                UART4_LIN_MODE_SLAVE   = (uint8_t)0x01  /**<  LIN Slave Mode*/
00093              } UART4_LinMode_TypeDef;
00094 /**
00095   * @brief  UART4 automatic resynchronisation possible values
00096   */
00097 typedef enum { UART4_LIN_AUTOSYNC_DISABLE   = (uint8_t)0x00,  /**< LIN Autosynchronization Disable*/
00098                UART4_LIN_AUTOSYNC_ENABLE    = (uint8_t)0x01   /**< LIN Autosynchronization Enable*/
00099              } UART4_LinAutosync_TypeDef;
00100 /**
00101   * @brief  UART4 Divider Update Method possible values
00102   */
00103 typedef enum { UART4_LIN_DIVUP_LBRR1    = (uint8_t)0x00, /**<  LIN LDIV is updated as soon as LBRR1 is written*/
00104                UART4_LIN_DIVUP_NEXTRXNE = (uint8_t)0x01  /**<  LIN LDIV is updated at the next received character*/
00105              } UART4_LinDivUp_TypeDef;
00106
00107 /**
00108   * @brief  UART4 Synchrone modes
00109   */
00110 typedef enum { UART4_SYNCMODE_CLOCK_DISABLE    = (uint8_t)0x80, /**< 0x80 Sync mode Disable, SLK pin Disable */
00111                UART4_SYNCMODE_CLOCK_ENABLE     = (uint8_t)0x08, /**< 0x08 Sync mode Enable, SLK pin Enable     */
00112                UART4_SYNCMODE_CPOL_LOW         = (uint8_t)0x40, /**< 0x40 Steady low value on SCLK pin outside transmission window */
00113                UART4_SYNCMODE_CPOL_HIGH        = (uint8_t)0x04, /**< 0x04 Steady high value on SCLK pin outside transmission window */
00114                UART4_SYNCMODE_CPHA_MIDDLE      = (uint8_t)0x20, /**< 0x20 SCLK clock line activated in middle of data bit     */
00115                UART4_SYNCMODE_CPHA_BEGINING    = (uint8_t)0x02, /**< 0x02 SCLK clock line activated at beginning of data bit  */
00116                UART4_SYNCMODE_LASTBIT_DISABLE  = (uint8_t)0x10, /**< 0x10 The clock pulse of the last data bit is not output to the SCLK pin */
00117                UART4_SYNCMODE_LASTBIT_ENABLE   = (uint8_t)0x01  /**< 0x01 The clock pulse of the last data bit is output to the SCLK pin */
00118              } UART4_SyncMode_TypeDef;
00119
00120 /**
00121   * @brief  UART4 Word length possible values
00122   */
00123 typedef enum { UART4_WORDLENGTH_8D = (uint8_t)0x00,/**< 0x00 8 bits Data  */
00124                UART4_WORDLENGTH_9D = (uint8_t)0x10 /**< 0x10 9 bits Data  */
00125              } UART4_WordLength_TypeDef;
00126
00127 /**
00128   * @brief  UART4 Mode possible values
00129   */
00130 typedef enum { UART4_MODE_RX_ENABLE     = (uint8_t)0x08,  /**< 0x08 Receive Enable */
00131                UART4_MODE_TX_ENABLE     = (uint8_t)0x04,  /**< 0x04 Transmit Enable */
00132                UART4_MODE_TX_DISABLE    = (uint8_t)0x80,  /**< 0x80 Transmit Disable */
00133                UART4_MODE_RX_DISABLE    = (uint8_t)0x40,  /**< 0x40 Single-wire Half-duplex mode */
00134                UART4_MODE_TXRX_ENABLE   = (uint8_t)0x0C  /**< 0x0C Transmit Enable and Receive Enable */
00135              } UART4_Mode_TypeDef;
00136 /**
00137   * @brief  UART4 Flag possible values
00138   */
00139 typedef enum
00140 {
00141   UART4_FLAG_TXE          = (uint16_t)0x0080, /*!< Transmit Data Register Empty flag */
00142   UART4_FLAG_TC           = (uint16_t)0x0040, /*!< Transmission Complete flag */
00143   UART4_FLAG_RXNE         = (uint16_t)0x0020, /*!< Read Data Register Not Empty flag */
00144   UART4_FLAG_IDLE         = (uint16_t)0x0010, /*!< Idle line detected flag */
00145   UART4_FLAG_OR_LHE       = (uint16_t)0x0008, /*!< OverRun error flag */
00146   UART4_FLAG_NF           = (uint16_t)0x0004, /*!< Noise error flag */
00147   UART4_FLAG_FE           = (uint16_t)0x0002, /*!< Framing Error flag */
00148   UART4_FLAG_PE           = (uint16_t)0x0001, /*!< Parity Error flag */
00149   UART4_FLAG_SBK          = (uint16_t)0x0101,  /**< Send Break Complete interrupt flag */
00150   UART4_FLAG_LBDF         = (uint16_t)0x0210, /**< LIN Break Detection Flag           */
00151   UART4_FLAG_LHDF         = (uint16_t)0x0302, /**< LIN Header Detection Flag*/
00152   UART4_FLAG_LSF          = (uint16_t)0x0301  /**< LIN Sync Field Flag*/
00153 } UART4_Flag_TypeDef;
00154
00155 /**
00156   * @brief  UART4 Interrupt definition
00157   * UART4_IT possible values
00158   * Elements values convention: 0xZYX
00159   * X: Position of the corresponding Interrupt
00160   *   - For the following values, X means the interrupt position in the CR2 register.
00161   *     UART4_IT_TXE
00162   *     UART4_IT_TC
00163   *     UART4_IT_RXNE
00164   *     UART4_IT_IDLE
00165   *     UART4_IT_OR
00166   *   - For the UART4_IT_PE value, X means the flag position in the CR1 register.
00167   *   - For the UART4_IT_LBDF value, X means the flag position in the CR4 register.
00168   *   - For the UART4_IT_LHDF value, X means the flag position in the CR6 register.
00169   * Y: Flag position
00170   *  - For the following values, Y means the flag (pending bit) position in the SR register.
00171   *     UART4_IT_TXE
00172   *     UART4_IT_TC
00173   *     UART4_IT_RXNE
00174   *     UART4_IT_IDLE
00175   *     UART4_IT_OR
00176   *     UART4_IT_PE
00177   *  - For the UART4_IT_LBDF value, Y means the flag position in the CR4 register.
00178   *  - For the UART4_IT_LHDF value, Y means the flag position in the CR6 register.
00179   * Z: Register index: indicate in which register the dedicated interrupt source is:
00180   *  - 1==> CR1 register
00181   *  - 2==> CR2 register
00182   *  - 3==> CR4 register
00183   *  - 4==> CR6 register
00184   */
00185 typedef enum { UART4_IT_TXE        = (uint16_t)0x0277, /**< Transmit interrupt */
00186                UART4_IT_TC         = (uint16_t)0x0266, /**< Transmission Complete interrupt */
00187                UART4_IT_RXNE       = (uint16_t)0x0255, /**< Data Register Not Empty interrupt */
00188                UART4_IT_IDLE       = (uint16_t)0x0244, /**< Idle line detected interrupt */
00189                UART4_IT_OR         = (uint16_t)0x0235, /**< OverRun error interrupt */
00190                UART4_IT_PE         = (uint16_t)0x0100, /**< Parity Error interrupt */
00191                UART4_IT_LBDF       = (uint16_t)0x0346, /**< LIN Break Detection interrupt */
00192                UART4_IT_LHDF       = (uint16_t)0x0412, /**< LIN Header Detection interrupt*/
00193                UART4_IT_RXNE_OR    = (uint16_t)0x0205  /*!< Receive/Overrun interrupt */
00194              } UART4_IT_TypeDef;
00195
00196 /**
00197   * @}
00198   */
00199
00200 /* Exported constants --------------------------------------------------------*/
00201 /* Exported macros -----------------------------------------------------------*/
00202 /* Private macros ------------------------------------------------------------*/
00203
00204 /** @addtogroup UART4_Private_Macros
00205   * @{
00206   */
00207
00208 /**
00209   * @brief  Macro used by the assert function to check the different functions parameters.
00210   */
00211
00212 /**
00213  * @brief Macro used by the assert_param function in order to check the different
00214  *        sensitivity values for the MODEs possible combination should be one of
00215  *        the following.
00216  */
00217
00218 #define IS_UART4_MODE_OK(Mode) \
00219   (((Mode) == (uint8_t)UART4_MODE_RX_ENABLE) || \
00220    ((Mode) == (uint8_t)UART4_MODE_RX_DISABLE) || \
00221    ((Mode) == (uint8_t)UART4_MODE_TX_ENABLE) || \
00222    ((Mode) == (uint8_t)UART4_MODE_TX_DISABLE) || \
00223    ((Mode) == (uint8_t)UART4_MODE_TXRX_ENABLE) || \
00224    ((Mode) == (uint8_t)((uint8_t)UART4_MODE_TX_ENABLE|(uint8_t)UART4_MODE_RX_ENABLE)) || \
00225    ((Mode) == (uint8_t)((uint8_t)UART4_MODE_TX_ENABLE|(uint8_t)UART4_MODE_RX_DISABLE)) || \
00226    ((Mode) == (uint8_t)((uint8_t)UART4_MODE_TX_DISABLE|(uint8_t)UART4_MODE_RX_DISABLE)) || \
00227    ((Mode) == (uint8_t)((uint8_t)UART4_MODE_TX_DISABLE|(uint8_t)UART4_MODE_RX_ENABLE)))
00228
00229 /**
00230  * @brief Macro used by the assert_param function in order to check the different
00231  *        sensitivity values for the WordLengths
00232  */
00233 #define IS_UART4_WORDLENGTH_OK(WordLength) \
00234   (((WordLength) == UART4_WORDLENGTH_8D) || \
00235    ((WordLength) == UART4_WORDLENGTH_9D))
00236
00237 /**
00238   * @brief  Macro used by the assert_param function in order to check the different
00239   *         sensitivity values for the SyncModes; it should exclude values such
00240   *         as  UART4_CLOCK_ENABLE|UART4_CLOCK_DISABLE
00241   */
00242 #define IS_UART4_SYNCMODE_OK(SyncMode) \
00243   (!((((SyncMode)&(((uint8_t)UART4_SYNCMODE_CLOCK_ENABLE)|((uint8_t)UART4_SYNCMODE_CLOCK_DISABLE))) == (((uint8_t)UART4_SYNCMODE_CLOCK_ENABLE)|((uint8_t)UART4_SYNCMODE_CLOCK_DISABLE))) || \
00244      (((SyncMode)&(((uint8_t)UART4_SYNCMODE_CPOL_LOW )|((uint8_t)UART4_SYNCMODE_CPOL_HIGH))) == (((uint8_t)UART4_SYNCMODE_CPOL_LOW )|((uint8_t)UART4_SYNCMODE_CPOL_HIGH))) || \
00245      (((SyncMode)&(((uint8_t)UART4_SYNCMODE_CPHA_MIDDLE)|((uint8_t)UART4_SYNCMODE_CPHA_BEGINING))) == (((uint8_t)UART4_SYNCMODE_CPHA_MIDDLE)|((uint8_t)UART4_SYNCMODE_CPHA_BEGINING))) || \
00246      (((SyncMode)&(((uint8_t)UART4_SYNCMODE_LASTBIT_DISABLE)|((uint8_t)UART4_SYNCMODE_LASTBIT_ENABLE))) == (((uint8_t)UART4_SYNCMODE_LASTBIT_DISABLE)|((uint8_t)UART4_SYNCMODE_LASTBIT_ENABLE)))))
00247
00248 /**
00249   * @brief  Macro used by the assert_param function in order to check the
00250   *         different sensitivity values for the FLAGs
00251   */
00252 #define IS_UART4_FLAG_OK(Flag) \
00253   (((Flag) == UART4_FLAG_TXE) || \
00254    ((Flag) == UART4_FLAG_TC)  || \
00255    ((Flag) == UART4_FLAG_RXNE) || \
00256    ((Flag) == UART4_FLAG_IDLE) || \
00257    ((Flag) == UART4_FLAG_OR_LHE) || \
00258    ((Flag) == UART4_FLAG_NF) || \
00259    ((Flag) == UART4_FLAG_FE) || \
00260    ((Flag) == UART4_FLAG_PE) || \
00261    ((Flag) == UART4_FLAG_SBK) || \
00262    ((Flag) == UART4_FLAG_LSF) || \
00263    ((Flag) == UART4_FLAG_LHDF) || \
00264    ((Flag) == UART4_FLAG_LBDF))
00265
00266
00267 /**
00268   * @brief  Macro used by the assert_param function in order to check the
00269   *         different sensitivity values for the FLAGs that can be cleared by writing 0
00270   */
00271 #define IS_UART4_CLEAR_FLAG_OK(Flag) \
00272   (((Flag) == UART4_FLAG_RXNE) || \
00273    ((Flag) == UART4_FLAG_LHDF) || \
00274    ((Flag) == UART4_FLAG_LSF) || \
00275    ((Flag) == UART4_FLAG_LBDF))
00276
00277 /**
00278   * @brief  Macro used by the assert_param function in order to check
00279   *         the different sensitivity values for the Interrupts
00280   */
00281
00282 #define IS_UART4_CONFIG_IT_OK(Interrupt) \
00283   (((Interrupt) == UART4_IT_PE) || \
00284    ((Interrupt) == UART4_IT_TXE) || \
00285    ((Interrupt) == UART4_IT_TC) || \
00286    ((Interrupt) == UART4_IT_RXNE_OR ) || \
00287    ((Interrupt) == UART4_IT_IDLE) || \
00288    ((Interrupt) == UART4_IT_LHDF) || \
00289    ((Interrupt) == UART4_IT_LBDF))
00290
00291 /**
00292   * @brief  Macro used by the assert function in order to check the different
00293   *         sensitivity values for the pending bit
00294   */
00295 #define IS_UART4_GET_IT_OK(ITPendingBit) \
00296   (((ITPendingBit) == UART4_IT_TXE)  || \
00297    ((ITPendingBit) == UART4_IT_TC)   || \
00298    ((ITPendingBit) == UART4_IT_RXNE) || \
00299    ((ITPendingBit) == UART4_IT_IDLE) || \
00300    ((ITPendingBit) == UART4_IT_OR)  || \
00301    ((ITPendingBit) == UART4_IT_LBDF)  || \
00302    ((ITPendingBit) == UART4_IT_LHDF)  || \
00303    ((ITPendingBit) == UART4_IT_PE))
00304
00305 /**
00306   * @brief  Macro used by the assert function in order to check the different
00307   *         sensitivity values for the pending bit that can be cleared by writing 0
00308   */
00309 #define IS_UART4_CLEAR_IT_OK(ITPendingBit) \
00310   (((ITPendingBit) == UART4_IT_RXNE) || \
00311    ((ITPendingBit) == UART4_IT_LHDF) || \
00312    ((ITPendingBit) == UART4_IT_LBDF))
00313
00314
00315 /**
00316  * @brief Macro used by the assert_param function in order to check the different
00317  *        sensitivity values for the IrDAModes
00318  */
00319 #define IS_UART4_IRDAMODE_OK(IrDAMode) \
00320   (((IrDAMode) == UART4_IRDAMODE_LOWPOWER) || \
00321    ((IrDAMode) == UART4_IRDAMODE_NORMAL))
00322
00323 /**
00324   * @brief  Macro used by the assert_param function in order to check the different
00325   *         sensitivity values for the WakeUps
00326   */
00327 #define IS_UART4_WAKEUP_OK(WakeUp) \
00328   (((WakeUp) == UART4_WAKEUP_IDLELINE) || \
00329    ((WakeUp) == UART4_WAKEUP_ADDRESSMARK))
00330
00331 /**
00332   * @brief  Macro used by the assert_param function in order to check the different
00333   *         sensitivity values for the LINBreakDetectionLengths
00334   */
00335 #define IS_UART4_LINBREAKDETECTIONLENGTH_OK(LINBreakDetectionLength) \
00336   (((LINBreakDetectionLength) == UART4_LINBREAKDETECTIONLENGTH_10BITS) || \
00337    ((LINBreakDetectionLength) == UART4_LINBREAKDETECTIONLENGTH_11BITS))
00338
00339 /**
00340   * @brief  Macro used by the assert_param function in order to check the different
00341   *         sensitivity values for the UART4_StopBits
00342   */
00343 #define IS_UART4_STOPBITS_OK(StopBit) (((StopBit) == UART4_STOPBITS_1) || \
00344                                        ((StopBit) == UART4_STOPBITS_0_5) || \
00345                                        ((StopBit) == UART4_STOPBITS_2) || \
00346                                        ((StopBit) == UART4_STOPBITS_1_5 ))
00347
00348 /**
00349  * @brief Macro used by the assert_param function in order to check the different
00350  *        sensitivity values for the Paritys
00351  */
00352 #define IS_UART4_PARITY_OK(Parity) (((Parity) == UART4_PARITY_NO) || \
00353                                     ((Parity) == UART4_PARITY_EVEN) || \
00354                                     ((Parity) == UART4_PARITY_ODD ))
00355
00356 /**
00357  * @brief Macro used by the assert_param function in order to check the maximum
00358  *        baudrate value
00359  */
00360 #define IS_UART4_BAUDRATE_OK(NUM) ((NUM) <= (uint32_t)625000)
00361
00362 /**
00363  * @brief Macro used by the assert_param function in order to check the address
00364  *        of the UART4 or UART node
00365  */
00366 #define UART4_ADDRESS_MAX ((uint8_t)16)
00367 #define IS_UART4_ADDRESS_OK(node) ((node) < UART4_ADDRESS_MAX )
00368
00369 /**
00370  * @brief Macro used by the assert_param function in order to check the LIN mode
00371  */
00372 #define IS_UART4_SLAVE_OK(Mode) \
00373   (((Mode) == UART4_LIN_MODE_MASTER) || \
00374    ((Mode) == UART4_LIN_MODE_SLAVE))
00375
00376 /**
00377  * @brief Macro used by the assert_param function in order to check the LIN
00378  *        automatic resynchronization mode
00379  */
00380 #define IS_UART4_AUTOSYNC_OK(AutosyncMode) \
00381   (((AutosyncMode) ==  UART4_LIN_AUTOSYNC_ENABLE) || \
00382    ((AutosyncMode) == UART4_LIN_AUTOSYNC_DISABLE))
00383
00384 /**
00385  * @brief Macro used by the assert_param function in order to check the LIN divider update method
00386  */
00387 #define IS_UART4_DIVUP_OK(DivupMethod) \
00388   (((DivupMethod) == UART4_LIN_DIVUP_LBRR1) || \
00389    ((DivupMethod) == UART4_LIN_DIVUP_NEXTRXNE))
00390
00391
00392 /**
00393   * @}
00394   */
00395
00396 /* Exported functions ------------------------------------------------------- */
00397
00398 /** @addtogroup UART4_Exported_Functions
00399   * @{
00400   */
00401 void UART4_DeInit(void);
00402 void UART4_Init(uint32_t BaudRate, UART4_WordLength_TypeDef WordLength,
00403                 UART4_StopBits_TypeDef StopBits, UART4_Parity_TypeDef Parity,
00404                 UART4_SyncMode_TypeDef SyncMode, UART4_Mode_TypeDef Mode);
00405 void UART4_Cmd(FunctionalState NewState);
00406 void UART4_ITConfig(UART4_IT_TypeDef UART4_IT, FunctionalState NewState);
00407 void UART4_HalfDuplexCmd(FunctionalState NewState);
00408 void UART4_IrDAConfig(UART4_IrDAMode_TypeDef UART4_IrDAMode);
00409 void UART4_IrDACmd(FunctionalState NewState);
00410 void UART4_LINBreakDetectionConfig(UART4_LINBreakDetectionLength_TypeDef UART4_LINBreakDetectionLength);
00411 void UART4_LINConfig(UART4_LinMode_TypeDef UART4_Mode,
00412                      UART4_LinAutosync_TypeDef UART4_Autosync,
00413                      UART4_LinDivUp_TypeDef UART4_DivUp);
00414 void UART4_LINCmd(FunctionalState NewState);
00415 void UART4_SmartCardCmd(FunctionalState NewState);
00416 void UART4_SmartCardNACKCmd(FunctionalState NewState);
00417 void UART4_WakeUpConfig(UART4_WakeUp_TypeDef UART4_WakeUp);
00418 void UART4_ReceiverWakeUpCmd(FunctionalState NewState);
00419 uint8_t UART4_ReceiveData8(void);
00420 uint16_t UART4_ReceiveData9(void);
00421 void UART4_SendData8(uint8_t Data);
00422 void UART4_SendData9(uint16_t Data);
00423 void UART4_SendBreak(void);
00424 void UART4_SetAddress(uint8_t UART4_Address);
00425 void UART4_SetGuardTime(uint8_t UART4_GuardTime);
00426 void UART4_SetPrescaler(uint8_t UART4_Prescaler);
00427 FlagStatus UART4_GetFlagStatus(UART4_Flag_TypeDef UART4_FLAG);
00428 void UART4_ClearFlag(UART4_Flag_TypeDef UART4_FLAG);
00429 ITStatus UART4_GetITStatus(UART4_IT_TypeDef UART4_IT);
00430 void UART4_ClearITPendingBit(UART4_IT_TypeDef UART4_IT);
00431
00432
00433 /**
00434   * @}
00435   */
00436
00437 #endif /* __STM8S_UART4_H */
00438
00439 /**
00440   * @}
00441   */
00442
00443
00444 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_wwdg.c Source File

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stm8s_wwdg.c
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00001 /**
00002   ********************************************************************************
00003   * @file    stm8s_wwdg.c
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all the functions for the WWDG peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm8s_wwdg.h"
00030
00031 /** @addtogroup STM8S_StdPeriph_Driver
00032   * @{
00033   */
00034 /* Private define ------------------------------------------------------------*/
00035 #define BIT_MASK          ((uint8_t)0x7F)
00036 /* Private macro -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038 /* Private function prototypes -----------------------------------------------*/
00039 /* Private functions ---------------------------------------------------------*/
00040
00041 /** @addtogroup WWDG_Public_Functions
00042   * @{
00043   */
00044
00045 /**
00046   * @brief  Initializes the WWDG peripheral.
00047   *         This function set Window Register = WindowValue, Counter Register
00048   *         according to Counter and \b ENABLE \b WWDG
00049   * @param  Counter : WWDG counter value
00050   * @param  WindowValue : specifies the WWDG Window Register, range is 0x00 to 0x7F.
00051   * @retval None
00052   */
00053 void WWDG_Init(uint8_t Counter, uint8_t WindowValue)
00054 {
00055   /* Check the parameters */
00056   assert_param(IS_WWDG_WINDOWLIMITVALUE_OK(WindowValue));
00057
00058   WWDG->WR = WWDG_WR_RESET_VALUE;
00059   WWDG->CR = (uint8_t)((uint8_t)(WWDG_CR_WDGA | WWDG_CR_T6) | (uint8_t)Counter);
00060   WWDG->WR = (uint8_t)((uint8_t)(~WWDG_CR_WDGA) & (uint8_t)(WWDG_CR_T6 | WindowValue));
00061 }
00062
00063 /**
00064   * @brief  Refreshes the WWDG peripheral.
00065   * @param  Counter :  WWDG Counter Value
00066   *         This parameter must be a number between 0x40 and 0x7F.
00067   * @retval None
00068   */
00069 void WWDG_SetCounter(uint8_t Counter)
00070 {
00071   /* Check the parameters */
00072   assert_param(IS_WWDG_COUNTERVALUE_OK(Counter));
00073
00074   /* Write to T[6:0] bits to configure the counter value, no need to do
00075   a read-modify-write; writing a 0 to WDGA bit does nothing */
00076   WWDG->CR = (uint8_t)(Counter & (uint8_t)BIT_MASK);
00077 }
00078
00079 /**
00080   * @brief Gets the WWDG Counter Value.
00081   *        This value could be used to check if WWDG is in the window, where
00082   *        refresh is allowed.
00083   * @param  None
00084   * @retval WWDG Counter Value
00085   */
00086 uint8_t WWDG_GetCounter(void)
00087 {
00088   return(WWDG->CR);
00089 }
00090
00091 /**
00092   * @brief  Generates immediate WWDG RESET.
00093   * @param  None
00094   * @retval None
00095   */
00096 void WWDG_SWReset(void)
00097 {
00098   WWDG->CR = WWDG_CR_WDGA; /* Activate WWDG, with clearing T6 */
00099 }
00100
00101 /**
00102   * @brief  Sets the WWDG window value.
00103   * @param  WindowValue: specifies the window value to be compared to the
00104   *         downcounter.
00105   *         This parameter value must be lower than 0x80.
00106   * @retval None
00107   */
00108 void WWDG_SetWindowValue(uint8_t WindowValue)
00109 {
00110   /* Check the parameters */
00111   assert_param(IS_WWDG_WINDOWLIMITVALUE_OK(WindowValue));
00112
00113   WWDG->WR = (uint8_t)((uint8_t)(~WWDG_CR_WDGA) & (uint8_t)(WWDG_CR_T6 | WindowValue));
00114 }
00115
00116 /**
00117   * @}
00118   */
00119
00120 /**
00121   * @}
00122   */
00123
00124
00125 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_wwdg.h Source File

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stm8s_wwdg.h
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00001 /**
00002   ********************************************************************************
00003   * @file    stm8s_wwdg.h
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all functions prototype and macros for the WWDG peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software
00020   * distributed under the License is distributed on an "AS IS" BASIS,
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027
00028 /* Define to prevent recursive inclusion -------------------------------------*/
00029 #ifndef __STM8S_WWDG_H
00030 #define __STM8S_WWDG_H
00031
00032 /* Includes ------------------------------------------------------------------*/
00033 #include "stm8s.h"
00034
00035 /** @addtogroup STM8S_StdPeriph_Driver
00036   * @{
00037   */
00038
00039 /* Private macros ------------------------------------------------------------*/
00040
00041 /** @addtogroup WWDG_Private_Macros
00042   * @{
00043   */
00044
00045 /**
00046   * @brief  Macro used by the assert function in order to check the
00047   * values of the window register.
00048   */
00049 #define IS_WWDG_WINDOWLIMITVALUE_OK(WindowLimitValue) ((WindowLimitValue) <= 0x7F)
00050
00051 /**
00052   * @brief  Macro used by the assert function in order to check the different
00053   * values of the counter register.
00054   */
00055 #define IS_WWDG_COUNTERVALUE_OK(CounterValue) ((CounterValue) <= 0x7F)
00056
00057 /**
00058   * @}
00059   */
00060
00061 /* Exported types ------------------------------------------------------------*/
00062
00063 /* Exported functions ------------------------------------------------------- */
00064
00065 /** @addtogroup WWDG_Exported_Functions
00066   * @{
00067   */
00068
00069 void WWDG_Init(uint8_t Counter, uint8_t WindowValue);
00070 void WWDG_SetCounter(uint8_t Counter);
00071 uint8_t WWDG_GetCounter(void);
00072 void WWDG_SWReset(void);
00073 void WWDG_SetWindowValue(uint8_t WindowValue);
00074
00075
00076 /**
00077   * @}
00078   */
00079
00080 #endif /* __STM8S_WWDG_H */
00081
00082 /**
00083   * @}
00084   */
00085
00086
00087 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/