diff -Nuar u-boot-2010.09/arch/arm/cpu/arm920t/s3c24x0/speed.c u-boot-2010.09-fl2440/arch/arm/cpu/arm920t/s3c24x0/speed.c --- u-boot-2010.09/arch/arm/cpu/arm920t/s3c24x0/speed.c 2010-09-29 05:20:55.000000000 +0800 +++ u-boot-2010.09-fl2440/arch/arm/cpu/arm920t/s3c24x0/speed.c 2020-08-21 12:06:35.008546938 +0800 @@ -64,6 +64,11 @@ p = ((r & 0x003F0) >> 4) + 2; s = r & 0x3; +#if defined(CONFIG_S3C2440) /* Add by guowenxue*/ + if (pllreg == MPLL) + return ((CONFIG_SYS_CLK_FREQ * m * 2) /(p << s)); + else if (pllreg == UPLL) +#endif /* Add end*/ return (CONFIG_SYS_CLK_FREQ * m) / (p << s); } @@ -78,7 +83,22 @@ { struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); +#if defined(CONFIG_S3C2440) + if (readl(&clk_power->CLKDIVN) & 0x6) + { + if ((readl(&clk_power->CLKDIVN) & 0x6)==2) + return(get_FCLK()/2); + if ((readl(&clk_power->CLKDIVN) & 0x6)==6) + return((readl(&clk_power->CAMDIVN) & 0x100) ? get_FCLK()/6 : get_FCLK()/3); + if ((readl(&clk_power->CLKDIVN) & 0x6)==4) + return((readl(&clk_power->CAMDIVN) & 0x200) ? get_FCLK()/8 : get_FCLK()/4); + return(get_FCLK()); + } + else + return(get_FCLK()); +#else return (readl(&clk_power->CLKDIVN) & 2) ? get_FCLK() / 2 : get_FCLK(); +#endif } /* return PCLK frequency */ @@ -95,4 +115,17 @@ return get_PLLCLK(UPLL); } + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + printf("S3C2440A CPU clock : %lu MHz\n", get_FCLK()); + printf("S3C2440A HSB clock : %lu MHz\n", get_HCLK()); + printf("S3C2440A PSB clock : %lu MHz\n", get_PCLK()); + printf("S3C2440A USB clock : %lu MHz\n", get_FCLK()); + + return 0; +} +#endif + #endif /* CONFIG_S3C24X0 */ diff -Nuar u-boot-2010.09/arch/arm/cpu/arm920t/s3c24x0/timer.c u-boot-2010.09-fl2440/arch/arm/cpu/arm920t/s3c24x0/timer.c --- u-boot-2010.09/arch/arm/cpu/arm920t/s3c24x0/timer.c 2010-09-29 05:20:55.000000000 +0800 +++ u-boot-2010.09-fl2440/arch/arm/cpu/arm920t/s3c24x0/timer.c 2020-08-21 12:06:35.008546938 +0800 @@ -181,6 +181,7 @@ tbclk = timer_load_val * 100; #elif defined(CONFIG_SBC2410X) || \ defined(CONFIG_SMDK2410) || \ + defined(CONFIG_FL2440) || \ defined(CONFIG_VCMA9) tbclk = CONFIG_SYS_HZ; #else diff -Nuar u-boot-2010.09/arch/arm/cpu/arm920t/start.S u-boot-2010.09-fl2440/arch/arm/cpu/arm920t/start.S --- u-boot-2010.09/arch/arm/cpu/arm920t/start.S 2010-09-29 05:20:55.000000000 +0800 +++ u-boot-2010.09-fl2440/arch/arm/cpu/arm920t/start.S 2020-08-21 12:06:35.012546938 +0800 @@ -114,8 +114,8 @@ orr r0, r0, #0xd3 msr cpsr, r0 - bl coloured_LED_init - bl red_LED_on + @bl coloured_LED_init + @bl red_LED_on #if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) /* @@ -159,13 +159,63 @@ ldr r1, =0x3ff ldr r0, =INTSUBMSK str r1, [r0] +#elif defined CONFIG_S3C2440 + ldr r1, =0x7fff + ldr r0, =INTSUBMSK + str r1, [r0] # endif +# if defined(CONFIG_S3C2440) +#define GPBCON 0x56000010 +#define GPBDAT 0x56000014 +#define GPBUP 0x56000018 + /*Set GPIO5, GPIO6, GPIO8, GPIO10 as GPIO OUTPUT mode*/ + ldr r0, =GPBCON + ldr r1, [r0] + bic r1, r1, #0x3c00 /*Set GPBCON for GPIO5,GPIO6 as 0x00 */ + orr r1, r1, #0x1400 /*Set GPBCON for GPIO5,GPIO6 as GPIOOUT, 0x01*/ + bic r1, r1, #0x00330000 /*Set GPBCON for GPIO8,GPIO10 as 0x00*/ + orr r1, r1, #0x00110000 /*Set GPBCON for GPIO8,GPIO10 as GPIOOUT, 0x01*/ + str r1, [r0] + + /*Set internal pullup resister*/ + ldr r0, =GPBUP + ldr r1, [r0] + orr r1, r1, #0x0560 /*Set bit 5,6,8,10, disable pullup resister*/ + str r1, [r0] + + ldr r2, =GPBDAT + ldr r3, [r2] + orr r3, r3, #0x0560 /*Set bit 5,6,8,10 as high level, Turn Off LED*/ + str r3, [r2] + +# define MPLLCON 0x4C000004 +# define MDIV_405 0x7f << 12 +# define PSDIV_405 0x21 + + + /* FCLK:HCLK:PCLK = 1:4:8 */ + ldr r0, =CLKDIVN + mov r1, #0x05 + str r1, [r0] + + mrc p15, 0, r1, c1, c0, 0 + orr r1, r1, #0xc0000000 + mcr p15, 0, r1, c1, c0, 0 + + Ldr r0,=MPLLCON + mov r1, #MDIV_405 + add r1, r1, #PSDIV_405 + str r1, [r0] + + +#else /*S3C2410, S3C2440 */ /* FCLK:HCLK:PCLK = 1:2:4 */ /* default FCLK is 120 MHz ! */ ldr r0, =CLKDIVN mov r1, #3 str r1, [r0] +#endif /* end of if defined(CONFIG_S3C2440) */ #endif /* CONFIG_S3C24X0 */ /* @@ -183,6 +233,92 @@ cmp r0, r1 /* don't reloc during debug */ beq stack_setup +judgment_norflash_nandflash_boot: + ldr r1, =( (4<<28)|(3<<4)|(3<<2) ) + mov r0, #0 + str r0, [r1] + + mov r1, #0x3c + ldr r0, [r1] + cmp r0, #0 + bne norflash_boot + + /*Nandflash boot going here, recovery address 0x0000003C date*/ + ldr r0, =(0xdeadbeef) + ldr r1, =( (4<<28)|(3<<4)|(3<<2) ) + str r0, [r1] + +nandflash_boot: +#define LENGTH_UBOOT 0x60000 +#define NAND_CTL_BASE 0x4E000000 +/* Offset */ +#define oNFCONF 0x00 +#define oNFCONT 0x04 +#define oNFCMD 0x08 +#define oNFSTAT 0x20 + + mov r1, #NAND_CTL_BASE + ldr r2, =( (7<<12)|(7<<8)|(7<<4)|(0<<0) ) + str r2, [r1, #oNFCONF] + ldr r2, [r1, #oNFCONF] + + ldr r2, =( (1<<4)|(0<<1)|(1<<0) ) @ Active low CE Control + str r2, [r1, #oNFCONT] + ldr r2, [r1, #oNFCONT] + + ldr r2, =(0x6) @ RnB Clear + str r2, [r1, #oNFSTAT] + ldr r2, [r1, #oNFSTAT] + + mov r2, #0xff @ RESET command + strb r2, [r1, #oNFCMD] + + mov r3, #0 @ wait +nand_delay: + add r3, r3, #0x1 + cmp r3, #0xa + blt nand_delay + +nand_wait: + ldr r2, [r1, #oNFSTAT] @ wait ready + tst r2, #0x4 + beq nand_wait + + ldr r2, [r1, #oNFCONT] + orr r2, r2, #0x2 @ Flash Memory Chip Disable + str r2, [r1, #oNFCONT] + + ldr sp, DW_STACK_START @ setup stack pointer + mov fp, #0 @ no previous frame, so fp=0 + + ldr r0, =TEXT_BASE + mov r1, #0x0 + mov r2, #LENGTH_UBOOT + bl nand_read_ll + tst r0, #0x0 + bne infinite_loop /*nand_read_ll() not return 0, then goto dead loop*/ + +nand_read_ok: + /*Then verify the read data validation*/ + mov r0, #0 + ldr r1, =TEXT_BASE + mov r2, #0x400 @ 4 bytes * 1024 = 4K-bytes + +compare_next_byte: + ldr r3, [r0], #4 + ldr r4, [r1], #4 + teq r3, r4 + bne infinite_loop + + subs r2, r2, #4 + beq stack_setup + bne compare_next_byte + +infinite_loop: + b infinite_loop @ infinite loop + +norflash_boot: + ldr r2, _armboot_start ldr r3, _bss_start sub r2, r3, r2 /* r2 <- size of armboot */ @@ -216,10 +352,22 @@ cmp r0, r1 ble clbss_l + ldr r1, =GPBDAT + ldr r2, [r1] + bic r2, r2, #(1<<5) + str r2, [r1] + ldr pc, _start_armboot _start_armboot: .word start_armboot +#ifdef CONFIG_S3C24X0 +#define STACK_BASE 0x33f00000 +#define STACK_SIZE 0x10000 + .align 2 + DW_STACK_START: .word STACK_BASE+STACK_SIZE-4 +#endif + /* ************************************************************************* diff -Nuar u-boot-2010.09/arch/arm/cpu/arm920t/u-boot.lds u-boot-2010.09-fl2440/arch/arm/cpu/arm920t/u-boot.lds --- u-boot-2010.09/arch/arm/cpu/arm920t/u-boot.lds 2010-09-29 05:20:55.000000000 +0800 +++ u-boot-2010.09-fl2440/arch/arm/cpu/arm920t/u-boot.lds 2020-08-21 12:06:35.012546938 +0800 @@ -40,6 +40,8 @@ .text : { arch/arm/cpu/arm920t/start.o (.text) + board/lingyun/fl2440/lowlevel_init.o (.text) + board/lingyun/fl2440/nand_read.o (.text) *(.text) } diff -Nuar u-boot-2010.09/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h u-boot-2010.09-fl2440/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h --- u-boot-2010.09/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h 2010-09-29 05:20:55.000000000 +0800 +++ u-boot-2010.09-fl2440/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h 2020-08-21 12:06:35.012546938 +0800 @@ -20,7 +20,7 @@ #ifdef CONFIG_S3C2400 #include -#elif defined CONFIG_S3C2410 +#elif defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) #include #else #error Please define the s3c24x0 cpu type diff -Nuar u-boot-2010.09/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h u-boot-2010.09-fl2440/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h --- u-boot-2010.09/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h 2010-09-29 05:20:55.000000000 +0800 +++ u-boot-2010.09-fl2440/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h 2020-08-21 12:06:35.012546938 +0800 @@ -78,7 +78,7 @@ u32 PRIORITY; u32 INTPND; u32 INTOFFSET; -#ifdef CONFIG_S3C2410 +#if defined(CONFIG_S3C2410) || defined (CONFIG_S3C2440) u32 SUBSRCPND; u32 INTSUBMSK; #endif @@ -88,11 +88,11 @@ /* DMAS (see manual chapter 8) */ struct s3c24x0_dma { u32 DISRC; -#ifdef CONFIG_S3C2410 +#if defined(CONFIG_S3C2410) || defined (CONFIG_S3C2440) u32 DISRCC; #endif u32 DIDST; -#ifdef CONFIG_S3C2410 +#if defined(CONFIG_S3C2410) || defined (CONFIG_S3C2440) u32 DIDSTC; #endif u32 DCON; @@ -103,7 +103,7 @@ #ifdef CONFIG_S3C2400 u32 res[1]; #endif -#ifdef CONFIG_S3C2410 +#if defined(CONFIG_S3C2410) || defined (CONFIG_S3C2440) u32 res[7]; #endif }; @@ -122,6 +122,9 @@ u32 CLKCON; u32 CLKSLOW; u32 CLKDIVN; +#if defined (CONFIG_S3C2440) + u32 CAMDIVN; +#endif }; @@ -141,7 +144,7 @@ u32 res[8]; u32 DITHMODE; u32 TPAL; -#ifdef CONFIG_S3C2410 +#if defined(CONFIG_S3C2410) || defined (CONFIG_S3C2440) u32 LCDINTPND; u32 LCDSRCPND; u32 LCDINTMSK; @@ -151,6 +154,7 @@ /* NAND FLASH (see S3C2410 manual chapter 6) */ +#if defined(CONFIG_S3C2410) struct s3c2410_nand { u32 NFCONF; u32 NFCMD; @@ -159,6 +163,26 @@ u32 NFSTAT; u32 NFECC; }; +#elif defined (CONFIG_S3C2440) +struct s3c2410_nand { + u32 NFCONF; + u32 NFCONT; + u32 NFCMD; + u32 NFADDR; + u32 NFDATA; + u32 NFMECCD0; + u32 NFMECCD1; + u32 NFSECCD; + u32 NFSTAT; + u32 NFESTAT0; + u32 NFESTAT1; + u32 NFMECC0; + u32 NFMECC1; + u32 NFSECC; + u32 NFSBLK; + u32 NFEBLK; +}; +#endif /* UART (see manual chapter 11) */ @@ -397,7 +421,7 @@ u32 MISCCR; u32 EXTINT; #endif -#ifdef CONFIG_S3C2410 +#if defined(CONFIG_S3C2410) || defined (CONFIG_S3C2440) u32 GPACON; u32 GPADAT; u32 res1[2]; @@ -446,6 +470,13 @@ u32 GSTATUS2; u32 GSTATUS3; u32 GSTATUS4; +#if defined (CONFIG_S3C2440) + u32 res9[3]; + u32 MSLCON; + u32 GPJCON; + u32 GPJDAT; + u32 GPJUP; +#endif #endif }; diff -Nuar u-boot-2010.09/board/lingyun/fl2440/config.mk u-boot-2010.09-fl2440/board/lingyun/fl2440/config.mk --- u-boot-2010.09/board/lingyun/fl2440/config.mk 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-2010.09-fl2440/board/lingyun/fl2440/config.mk 2020-08-21 12:06:35.012546938 +0800 @@ -0,0 +1,25 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# David Mueller, ELSOFT AG, +# +# SAMSUNG SMDK2410 board with S3C2410X (ARM920T) cpu +# +# see http://www.samsung.com/ for more information on SAMSUNG +# + +# +# SMDK2410 has 1 bank of 64 MB DRAM +# +# 3000'0000 to 3400'0000 +# +# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 +# optionally with a ramdisk at 3080'0000 +# +# we load ourself to 33F8'0000 +# +# download area is 3300'0000 +# + + +TEXT_BASE = 0x33F80000 diff -Nuar u-boot-2010.09/board/lingyun/fl2440/fl2440.c u-boot-2010.09-fl2440/board/lingyun/fl2440/fl2440.c --- u-boot-2010.09/board/lingyun/fl2440/fl2440.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-2010.09-fl2440/board/lingyun/fl2440/fl2440.c 2020-08-21 12:06:35.012546938 +0800 @@ -0,0 +1,174 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define FCLK_SPEED 1 + +#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ +#define M_MDIV 0xC3 +#define M_PDIV 0x4 +#define M_SDIV 0x1 +#elif FCLK_SPEED==1 /* Fout = 405MHz, modify by guowenxue */ +#define M_MDIV 0x7f +#define M_PDIV 0x2 +#define M_SDIV 0x1 +#endif + +#define USB_CLOCK 1 + +#if USB_CLOCK==0 +#define U_M_MDIV 0xA1 +#define U_M_PDIV 0x3 +#define U_M_SDIV 0x1 +#elif USB_CLOCK==1 +#define U_M_MDIV 0x38 /* Modify by guowenxue */ +#define U_M_PDIV 0x3 +#define U_M_SDIV 0x2 +#endif + +static inline void delay (unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} + +#ifdef CONFIG_FL2440_BEEP /* Add by guowenxue, 2012.10.04 */ +#define BEEP 0 /* Buzzer use GPB0 */ +#define DELAY_TIME 10000000 + +void turn_beep(void) +{ + int count = 2; + struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); + + gpio->GPBCON = (gpio->GPBCON|0x3)&0x1; /* Set GPB0 as GPIO output mode(0x01) */ + + while(count--) + { + gpio->GPBCON = (gpio->GPBCON|0x3)&0x1; /* Set GPB0 as GPIO output mode(0x01) */ + + gpio->GPBDAT &= ~(1<GPBDAT |= 1<GPBCON &= ~0x3; /* Set GPB0 as GPIO input mode(0x00) */ + } + + return ; +} +#endif + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init (void) +{ + struct s3c24x0_clock_power * const clk_power = + s3c24x0_get_base_clock_power(); + struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); + + /* to reduce PLL lock time, adjust the LOCKTIME register */ + clk_power->LOCKTIME = 0xFFFFFF; + + /* configure MPLL */ + clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); + + /* some delay between MPLL and UPLL */ + delay (4000); + + /* configure UPLL */ + clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); + + /* some delay between MPLL and UPLL */ + delay (8000); + + /* set up the I/O ports */ + gpio->GPACON = 0x007FFFFF; + gpio->GPBCON = 0x00044555; + gpio->GPBUP = 0x000007FF; + gpio->GPCCON = 0xAAAAAAAA; + gpio->GPCUP = 0x0000FFFF; + gpio->GPDCON = 0xAAAAAAAA; + gpio->GPDUP = 0x0000FFFF; + gpio->GPECON = 0xAAAAAAAA; + gpio->GPEUP = 0x0000FFFF; + gpio->GPFCON = 0x000055AA; + gpio->GPFUP = 0x000000FF; + gpio->GPGCON = 0xFF95FFBA; + gpio->GPGUP = 0x0000FFFF; + gpio->GPHCON = 0x002AFAAA; + gpio->GPHUP = 0x000007FF; + + /* arch number of MINI2440-Board */ + gd->bd->bi_arch_number = MACH_TYPE_MINI2440; /* Modify by guowenxue */ + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x30000100; + + icache_enable(); + dcache_enable(); + +#if defined(CONFIG_FL2440_LED) /* Add by guowenxue, 2012.10.04 */ + gpio->GPBDAT = 0x00000181; +#endif +#ifdef CONFIG_FL2440_BEEP /* Add by guowenxue, 2012.10.04 */ + turn_beep(); +#endif + + return 0; +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_CS8900 + rc = cs8900_initialize(0, CONFIG_CS8900_BASE); +#endif +#ifdef CONFIG_DRIVER_DM9000 + rc = dm9000_initialize(bis); +#endif + return rc; +} +#endif diff -Nuar u-boot-2010.09/board/lingyun/fl2440/flash.c u-boot-2010.09-fl2440/board/lingyun/fl2440/flash.c --- u-boot-2010.09/board/lingyun/fl2440/flash.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-2010.09-fl2440/board/lingyun/fl2440/flash.c 2020-08-21 12:06:35.012546938 +0800 @@ -0,0 +1,433 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +ulong myflush (void); + + +#define FLASH_BANK_SIZE PHYS_FLASH_SIZE +#define MAIN_SECT_SIZE 0x10000 /* 64 KB */ + +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; + + +#define CMD_READ_ARRAY 0x000000F0 +#define CMD_UNLOCK1 0x000000AA +#define CMD_UNLOCK2 0x00000055 +#define CMD_ERASE_SETUP 0x00000080 +#define CMD_ERASE_CONFIRM 0x00000030 +#define CMD_PROGRAM 0x000000A0 +#define CMD_UNLOCK_BYPASS 0x00000020 + +#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 1))) +#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA << 1))) + +#define BIT_ERASE_DONE 0x00000080 +#define BIT_RDY_MASK 0x00000080 +#define BIT_PROGRAM_ERROR 0x00000020 +#define BIT_TIMEOUT 0x80000000 /* our flag */ + +#define READY 1 +#define ERR 2 +#define TMO 4 + +/*----------------------------------------------------------------------- + */ + +ulong flash_init (void) +{ + int i, j; + ulong size = 0; + + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { + ulong flashbase = 0; + + flash_info[i].flash_id = +#if defined(CONFIG_AMD_LV400) + (AMD_MANUFACT & FLASH_VENDMASK) | + (AMD_ID_LV400B & FLASH_TYPEMASK); +#elif defined(CONFIG_AMD_LV800) + (AMD_MANUFACT & FLASH_VENDMASK) | + (AMD_ID_LV800B & FLASH_TYPEMASK); +#else +#error "Unknown flash configured" +#endif + flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); + if (i == 0) + flashbase = PHYS_FLASH_1; + else + panic ("configured too many flash banks!\n"); + for (j = 0; j < flash_info[i].sector_count; j++) { + if (j <= 3) { + /* 1st one is 16 KB */ + if (j == 0) { + flash_info[i].start[j] = + flashbase + 0; + } + + /* 2nd and 3rd are both 8 KB */ + if ((j == 1) || (j == 2)) { + flash_info[i].start[j] = + flashbase + 0x4000 + (j - + 1) * + 0x2000; + } + + /* 4th 32 KB */ + if (j == 3) { + flash_info[i].start[j] = + flashbase + 0x8000; + } + } else { + flash_info[i].start[j] = + flashbase + (j - 3) * MAIN_SECT_SIZE; + } + } + size += flash_info[i].size; + } + + flash_protect (FLAG_PROTECT_SET, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0]); + + flash_protect (FLAG_PROTECT_SET, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); + + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case (AMD_MANUFACT & FLASH_VENDMASK): + printf ("AMD: "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (AMD_ID_LV400B & FLASH_TYPEMASK): + printf ("1x Amd29LV400BB (4Mbit)\n"); + break; + case (AMD_ID_LV800B & FLASH_TYPEMASK): + printf ("1x Amd29LV800BB (8Mbit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + goto Done; + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + + Done:; +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + ushort result; + int iflag, cflag, prot, sect; + int rc = ERR_OK; + int chip; + + /* first look for protection bits */ + + if (info->flash_id == FLASH_UNKNOWN) + return ERR_UNKNOWN_FLASH_TYPE; + + if ((s_first < 0) || (s_first > s_last)) { + return ERR_INVAL; + } + + if ((info->flash_id & FLASH_VENDMASK) != + (AMD_MANUFACT & FLASH_VENDMASK)) { + return ERR_UNKNOWN_FLASH_VENDOR; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) + return ERR_PROTECTED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + cflag = icache_status (); + icache_disable (); + iflag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { + printf ("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + if (info->protect[sect] == 0) { /* not protected */ + vu_short *addr = (vu_short *) (info->start[sect]); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + *addr = CMD_ERASE_CONFIRM; + + /* wait until flash is ready */ + chip = 0; + + do { + result = *addr; + + /* check timeout */ + if (get_timer_masked () > + CONFIG_SYS_FLASH_ERASE_TOUT) { + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + chip = TMO; + break; + } + + if (!chip + && (result & 0xFFFF) & BIT_ERASE_DONE) + chip = READY; + + if (!chip + && (result & 0xFFFF) & BIT_PROGRAM_ERROR) + chip = ERR; + + } while (!chip); + + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + + if (chip == ERR) { + rc = ERR_PROG_ERROR; + goto outahere; + } + if (chip == TMO) { + rc = ERR_TIMOUT; + goto outahere; + } + + printf ("ok.\n"); + } else { /* it was protected */ + + printf ("protected!\n"); + } + } + + if (ctrlc ()) + printf ("User Interrupt!\n"); + + outahere: + /* allow flash to settle - wait 10 ms */ + udelay_masked (10000); + + if (iflag) + enable_interrupts (); + + if (cflag) + icache_enable (); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash + */ + +static int write_hword (flash_info_t * info, ulong dest, ushort data) +{ + vu_short *addr = (vu_short *) dest; + ushort result; + int rc = ERR_OK; + int cflag, iflag; + int chip; + + /* + * Check if Flash is (sufficiently) erased + */ + result = *addr; + if ((result & data) != data) + return ERR_NOT_ERASED; + + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + cflag = icache_status (); + icache_disable (); + iflag = disable_interrupts (); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS; + *addr = CMD_PROGRAM; + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait until flash is ready */ + chip = 0; + do { + result = *addr; + + /* check timeout */ + if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { + chip = ERR | TMO; + break; + } + if (!chip && ((result & 0x80) == (data & 0x80))) + chip = READY; + + if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) { + result = *addr; + + if ((result & 0x80) == (data & 0x80)) + chip = READY; + else + chip = ERR; + } + + } while (!chip); + + *addr = CMD_READ_ARRAY; + + if (chip == ERR || *addr != data) + rc = ERR_PROG_ERROR; + + if (iflag) + enable_interrupts (); + + if (cflag) + icache_enable (); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp; + int l; + int i, rc; + ushort data; + + wp = (addr & ~1); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 8); + } + for (; i < 2 && cnt > 0; ++i) { + data = (data >> 8) | (*src++ << 8); + --cnt; + ++cp; + } + for (; cnt == 0 && i < 2; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 8); + } + + if ((rc = write_hword (info, wp, data)) != 0) { + return (rc); + } + wp += 2; + } + + /* + * handle word aligned part + */ + while (cnt >= 2) { + data = *((vu_short *) src); + if ((rc = write_hword (info, wp, data)) != 0) { + return (rc); + } + src += 2; + wp += 2; + cnt -= 2; + } + + if (cnt == 0) { + return ERR_OK; + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { + data = (data >> 8) | (*src++ << 8); + --cnt; + } + for (; i < 2; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 8); + } + + return write_hword (info, wp, data); +} diff -Nuar u-boot-2010.09/board/lingyun/fl2440/lowlevel_init.S u-boot-2010.09-fl2440/board/lingyun/fl2440/lowlevel_init.S --- u-boot-2010.09/board/lingyun/fl2440/lowlevel_init.S 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-2010.09-fl2440/board/lingyun/fl2440/lowlevel_init.S 2020-08-21 12:06:35.012546938 +0800 @@ -0,0 +1,198 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and + * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) + * + * Modified for the Samsung SMDK2410 by + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + + +/* some parameters for the board */ + +/* + * + * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S + * + * Copyright (C) 2002 Samsung Electronics SW.LEE + * + */ + +#define BWSCON 0x48000000 +#define GPBCON 0x56000010 +#define GPBDAT 0x56000014 +#define GPBUP 0x56000018 + +/* BWSCON */ +#define DW8 (0x0) +#define DW16 (0x1) +#define DW32 (0x2) +#define WAIT (0x1<<2) +#define UBLB (0x1<<3) + +#define B1_BWSCON (DW32) +#define B2_BWSCON (DW16) +#define B3_BWSCON (DW16 + WAIT + UBLB) +#define B4_BWSCON (DW16) +#define B5_BWSCON (DW16) +#define B6_BWSCON (DW32) +#define B7_BWSCON (DW32) + +/* BANK0CON */ +#define B0_Tacs 0x0 /* 0clk */ +#define B0_Tcos 0x0 /* 0clk */ +#define B0_Tacc 0x7 /* 14clk */ +#define B0_Tcoh 0x0 /* 0clk */ +#define B0_Tah 0x0 /* 0clk */ +#define B0_Tacp 0x0 +#define B0_PMC 0x0 /* normal */ + +/* BANK1CON */ +#define B1_Tacs 0x0 /* 0clk */ +#define B1_Tcos 0x0 /* 0clk */ +#define B1_Tacc 0x7 /* 14clk */ +#define B1_Tcoh 0x0 /* 0clk */ +#define B1_Tah 0x0 /* 0clk */ +#define B1_Tacp 0x0 +#define B1_PMC 0x0 + +#define B2_Tacs 0x0 +#define B2_Tcos 0x0 +#define B2_Tacc 0x7 +#define B2_Tcoh 0x0 +#define B2_Tah 0x0 +#define B2_Tacp 0x0 +#define B2_PMC 0x0 + +#define B3_Tacs 0x0 /* 0clk */ +#define B3_Tcos 0x3 /* 4clk */ +#define B3_Tacc 0x7 /* 14clk */ +#define B3_Tcoh 0x1 /* 1clk */ +#define B3_Tah 0x0 /* 0clk */ +#define B3_Tacp 0x3 /* 6clk */ +#define B3_PMC 0x0 /* normal */ + +#define B4_Tacs 0x0 /* 0clk */ +#define B4_Tcos 0x0 /* 0clk */ +#define B4_Tacc 0x7 /* 14clk */ +#define B4_Tcoh 0x0 /* 0clk */ +#define B4_Tah 0x0 /* 0clk */ +#define B4_Tacp 0x0 +#define B4_PMC 0x0 /* normal */ + +#define B5_Tacs 0x0 /* 0clk */ +#define B5_Tcos 0x0 /* 0clk */ +#define B5_Tacc 0x7 /* 14clk */ +#define B5_Tcoh 0x0 /* 0clk */ +#define B5_Tah 0x0 /* 0clk */ +#define B5_Tacp 0x0 +#define B5_PMC 0x0 /* normal */ + +/* SDRAM is on HSB bus, so its clock is from HCLK, FCLK=400, HCLK=100; so SDRAM 1clk=10ns */ + +#define B6_MT 0x3 /* SDRAM */ +// K4S561632 datasheet: RAS to CAS delay(Trcd) Min value should be 18/20ns, HCLK is 100MHz, so 1clk=10ns +// EM63A165 datasheet: RAS# to CAS# delay(Trcd) Min value should be 15/20ns, HCLK is 100MHz, so 1clk=10ns +#define B6_Trcd 0x2 /* 4clk */ +#define B6_SCAN 0x1 /* 9bit */ + +#define B7_MT 0x3 /* SDRAM */ +#define B7_Trcd 0x1 /* 3clk */ +#define B7_SCAN 0x1 /* 9bit */ + +/* REFRESH register<0x48000024> parameter */ +#define REFEN 0x1 /* Refresh enable */ +#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ + +// Trp: Row precharge time +// K4S561632 datasheet: Min(Trp) value should be 18/20ns; +// EM63A165 datasheet: Min value should be 15/20ns; +#define Trp 0x2 /* 4clk */ + +// Trc: Row cycle time +// K4S561632 datasheet: Min value should be 60/65ns; +// EM63A165 datasheet: Min value should be 60/63ns; +// S3C2440 datasheet: REFRESH register describe: SDRAM Row cycle time: Trc=Tsrc+Trp +#define Tsrc 0x2 /* 6clk, so Trc=Tsrc+Trp=6+3=9clk */ + +// K4S561632 datasheet: 64ms refresh period (8K Cycle): 64000/8192=7.81us +// EM63A165 datasheet: 8192 refresh cycles/64ms: 64000/8192=7.81us +// S3C2440 datasheet: REFRESH Register Refresh period = (2^11-refresh_count+1)/HCLK +// So Refresh count = 2^11 + 1 - 100x7.81 = 1268 +#define REFCNT 1268 +//#define REFCNT 489 /* HCLK=100Mhz, (2048+1-15.6*100) */ + + +/**************************************/ + +_TEXT_BASE: + .word TEXT_BASE + +.globl lowlevel_init +lowlevel_init: + ldr r5, =GPBDAT + ldr r6, [r5] + bic r6, r6, #(1<<8) + str r6, [r5] + + /* memory control configuration */ + /* make r0 relative the current location so that it */ + /* reads SMRDATA out of FLASH rather than memory ! */ + ldr r0, =SMRDATA + ldr r1, =lowlevel_init + sub r0, r0, r1 + adr r3, lowlevel_init /* r3 <- current position of code */ + add r0, r0, r3 + ldr r1, =BWSCON /* Bus Width Status Controller */ + add r2, r0, #13*4 + +0: + ldr r3, [r0], #4 + str r3, [r1], #4 + cmp r2, r0 + bne 0b + + /* everything is fine now */ + mov pc, lr + + .ltorg +/* the literal pools origin */ + +SMRDATA: + .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) + .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) + .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) + .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) + .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) + .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) + .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) + .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) + .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) + .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Tsrc<<18)+REFCNT) + .word 0xb2 + .word 0x30 + .word 0x30 diff -Nuar u-boot-2010.09/board/lingyun/fl2440/Makefile u-boot-2010.09-fl2440/board/lingyun/fl2440/Makefile --- u-boot-2010.09/board/lingyun/fl2440/Makefile 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-2010.09-fl2440/board/lingyun/fl2440/Makefile 2020-08-21 12:06:35.012546938 +0800 @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := fl2440.o nand_read.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff -Nuar u-boot-2010.09/board/lingyun/fl2440/nand_read.c u-boot-2010.09-fl2440/board/lingyun/fl2440/nand_read.c --- u-boot-2010.09/board/lingyun/fl2440/nand_read.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-2010.09-fl2440/board/lingyun/fl2440/nand_read.c 2020-08-21 12:06:35.012546938 +0800 @@ -0,0 +1,212 @@ +/* + * nand_read.c: Simple NAND read functions for booting from NAND + * + * This is used by cpu/arm920/start.S assembler code, + * and the board-specific linker script must make sure this + * file is linked within the first 4kB of NAND flash. + * + * Taken from GPLv2 licensed vivi bootloader, + * Copyright (C) 2002 MIZI Research, Inc. + * + * Author: Hwang, Chideok + * Date : $Date: 2004/02/04 10:37:37 $ + * + * u-boot integration and bad-block skipping (C) 2006 by OpenMoko, Inc. + * Author: Harald Welte + */ + +#include +#include + + +#define __REGb(x) (*(volatile unsigned char *)(x)) +#define __REGw(x) (*(volatile unsigned short *)(x)) +#define __REGi(x) (*(volatile unsigned int *)(x)) +#define NF_BASE 0x4e000000 +#if defined(CONFIG_S3C2410) +#define NFCONF __REGi(NF_BASE + 0x0) +#define NFCMD __REGb(NF_BASE + 0x4) +#define NFADDR __REGb(NF_BASE + 0x8) +#define NFDATA __REGb(NF_BASE + 0xc) +#define NFSTAT __REGb(NF_BASE + 0x10) +#define NFSTAT_BUSY 1 +#define nand_select() (NFCONF &= ~0x800) +#define nand_deselect() (NFCONF |= 0x800) +#define nand_clear_RnB() do {} while (0) +#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442) +#define NFCONF __REGi(NF_BASE + 0x0) +#define NFCONT __REGi(NF_BASE + 0x4) +#define NFCMD __REGb(NF_BASE + 0x8) +#define NFADDR __REGb(NF_BASE + 0xc) +#define NFDATA __REGb(NF_BASE + 0x10) +#define NFDATA16 __REGw(NF_BASE + 0x10) +#define NFSTAT __REGb(NF_BASE + 0x20) +#define NFSTAT_BUSY 1 +#define nand_select() (NFCONT &= ~(1 << 1)) +#define nand_deselect() (NFCONT |= (1 << 1)) +#define nand_clear_RnB() (NFSTAT |= (1 << 2)) +#endif + +static inline void nand_wait(void) +{ + int i; + + while (!(NFSTAT & NFSTAT_BUSY)) + for (i=0; i<10; i++); +} + +struct boot_nand_t { + int page_size; + int block_size; + int bad_block_offset; +}; + +static int is_bad_block(struct boot_nand_t * nand, unsigned long i) +{ + unsigned char data; + unsigned long page_num; + + nand_clear_RnB(); + if (nand->page_size == 512) { + NFCMD = NAND_CMD_READOOB; /* 0x50 */ + NFADDR = nand->bad_block_offset & 0xf; + NFADDR = (i >> 9) & 0xff; + NFADDR = (i >> 17) & 0xff; + NFADDR = (i >> 25) & 0xff; + } else if (nand->page_size == 2048) { + page_num = i >> 11; /* addr / 2048 */ + NFCMD = NAND_CMD_READ0; + NFADDR = nand->bad_block_offset & 0xff; + NFADDR = (nand->bad_block_offset >> 8) & 0xff; + NFADDR = page_num & 0xff; + NFADDR = (page_num >> 8) & 0xff; + NFADDR = (page_num >> 16) & 0xff; + NFCMD = NAND_CMD_READSTART; + } else { + return -1; + } + nand_wait(); + data = (NFDATA & 0xff); + if (data != 0xff) + return 1; + + return 0; +} + +static int nand_read_page_ll(struct boot_nand_t * nand, unsigned char *buf, unsigned long addr) +{ + unsigned short *ptr16 = (unsigned short *)buf; + unsigned int i, page_num; + + nand_clear_RnB(); + + NFCMD = NAND_CMD_READ0; + + if (nand->page_size == 512) { + /* Write Address */ + NFADDR = addr & 0xff; + NFADDR = (addr >> 9) & 0xff; + NFADDR = (addr >> 17) & 0xff; + NFADDR = (addr >> 25) & 0xff; + } else if (nand->page_size == 2048) { + page_num = addr >> 11; /* addr / 2048 */ + /* Write Address */ + NFADDR = 0; + NFADDR = 0; + NFADDR = page_num & 0xff; + NFADDR = (page_num >> 8) & 0xff; + NFADDR = (page_num >> 16) & 0xff; + NFCMD = NAND_CMD_READSTART; + } else { + return -1; + } + nand_wait(); + +#if defined(CONFIG_S3C2410) + for (i = 0; i < nand->page_size; i++) { + *buf = (NFDATA & 0xff); + buf++; + } +#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442) + for (i = 0; i < (nand->page_size>>1); i++) { + *ptr16 = NFDATA16; + ptr16++; + } +#endif + + return nand->page_size; +} + +static unsigned short nand_read_id() +{ + unsigned short res = 0; + NFCMD = NAND_CMD_READID; + NFADDR = 0; + res = NFDATA; + res = (res << 8) | NFDATA; + return res; +} + +extern unsigned int dynpart_size[]; + +/* low level nand read function */ +int nand_read_ll(unsigned char *buf, unsigned long start_addr, int size) +{ + int i, j; + unsigned short nand_id; + struct boot_nand_t nand; + + /* chip Enable */ + nand_select(); + nand_clear_RnB(); + + for (i = 0; i < 10; i++) + ; + nand_id = nand_read_id(); + if (0) { /* dirty little hack to detect if nand id is misread */ + unsigned short * nid = (unsigned short *)0x31fffff0; + *nid = nand_id; + } + + if (nand_id == 0xec76 || /* Samsung K91208 on SD2410 board */ + nand_id == 0xad76 ) { /*Hynix HY27US08121A*/ + nand.page_size = 512; + nand.block_size = 16 * 1024; + nand.bad_block_offset = 5; + // nand.size = 0x4000000; + } else if (nand_id == 0xecf1 || /* Samsung K9F1G08U0B */ + nand_id == 0xadda || /* Hynix HY27UF082G2B on FL2440 board */ + nand_id == 0xecda || /* Samsung K9F2G08U0B on FL2440 board */ + nand_id == 0xecd3 ) { /* Samsung K9K8G08 */ + nand.page_size = 2048; + nand.block_size = 128 * 1024; + nand.bad_block_offset = nand.page_size; + // nand.size = 0x8000000; + } else { + return -1; // hang + } + if ((start_addr & (nand.block_size-1)) || (size & ((nand.block_size-1)))) + return -1; /* invalid alignment */ + + for (i=start_addr; i < (start_addr + size);) { +#ifdef CONFIG_S3C2410_NAND_SKIP_BAD + if (i & (nand.block_size-1)== 0) { + if (is_bad_block(&nand, i) || + is_bad_block(&nand, i + nand.page_size)) { + /* Bad block */ + i += nand.block_size; + size += nand.block_size; + continue; + } + } +#endif + j = nand_read_page_ll(&nand, buf, i); + i += j; + buf += j; + } + + /* chip Disable */ + nand_deselect(); + + return 0; +} diff -Nuar u-boot-2010.09/boards.cfg u-boot-2010.09-fl2440/boards.cfg --- u-boot-2010.09/boards.cfg 2010-09-29 05:20:55.000000000 +0800 +++ u-boot-2010.09-fl2440/boards.cfg 2020-08-21 12:06:35.012546938 +0800 @@ -238,6 +238,7 @@ sbc2410x arm arm920t - - s3c24x0 smdk2400 arm arm920t - samsung s3c24x0 smdk2410 arm arm920t - samsung s3c24x0 +fl2440 arm arm920t fl2440 lingyun s3c24x0 voiceblue arm arm925t omap1510inn arm arm925t - ti afeb9260 arm arm926ejs - - at91 diff -Nuar u-boot-2010.09/build.sh u-boot-2010.09-fl2440/build.sh --- u-boot-2010.09/build.sh 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-2010.09-fl2440/build.sh 2020-08-21 12:06:35.012546938 +0800 @@ -0,0 +1,72 @@ +#!/bin/bash + +BOARD=fl2440 +TFTP_PATH=/tftp +IMGS_PATH=../images +IMG_NAME=u-boot-${BOARD}.bin + +CROSSTOOL=/opt/buildroot/cortex-a5/bin/arm-linux- +JOBS=`cat /proc/cpuinfo |grep "processor"|wc -l` + + +function do_clean() +{ + make CROSS_COMPILE=${CROSSTOOL} distclean + rm -f tools/logos/logo.bmp + rm -f cscope* tags + rm -f ${IMG_NAME} +} + +function do_modify() +{ + grep "arm-linux-gnueabi" Makefile > /dev/null + + if [ $? == 0 ] ; then + return ; + fi + + echo "Modify Makefile for ARCH and cross compiler" + sed -i -e "s|^CROSS_COMPILE=.*|CROSS_COMPILE=${CROSSTOOL}|g" Makefile +} + +function do_build() +{ + make fl2440_config + + make -j${JOBS} + + if [ ! -f ${IMG_NAME} ] ; then + mv u-boot-*.bin ${IMG_NAME} + fi + + chmod a+x ${IMG_NAME} +} + +function do_install() +{ + if [ -w $TFTP_PATH ] ;then + echo "cp ${IMG_NAME} $TFTP_PATH" + cp ${IMG_NAME} $TFTP_PATH + fi + + if [ -w ${IMGS_PATH} ] ; then + echo "cp ${IMG_NAME} $IMGS_PATH" + cp ${IMG_NAME} $IMGS_PATH + fi +} + +if [ "$1" == "clean" ] ; then + + do_clean + exit 0; +fi + +do_modify + +set -e + +do_build + +do_install + + diff -Nuar u-boot-2010.09/common/cmd_nand.c u-boot-2010.09-fl2440/common/cmd_nand.c --- u-boot-2010.09/common/cmd_nand.c 2010-09-29 05:20:55.000000000 +0800 +++ u-boot-2010.09-fl2440/common/cmd_nand.c 2020-08-21 12:06:35.012546938 +0800 @@ -148,6 +148,11 @@ #if defined(CONFIG_CMD_MTDPARTS) out: #endif + /* If the size is not aligment, then let it's page alignment */ + if(0 != (*size%nand->writesize)) + { + *size = (*size / nand->writesize + 1) * nand->writesize; + } printf("device %d ", idx); if (*size == nand->size) puts("whole chip\n"); diff -Nuar u-boot-2010.09/common/env_common.c u-boot-2010.09-fl2440/common/env_common.c --- u-boot-2010.09/common/env_common.c 2010-09-29 05:20:55.000000000 +0800 +++ u-boot-2010.09-fl2440/common/env_common.c 2020-08-21 12:06:35.016546939 +0800 @@ -53,11 +53,35 @@ #define MK_STR(x) XMK_STR(x) uchar default_environment[] = { +#ifdef CONFIG_DEVNAME /* Add by guowenxue, boardname */ + "devname=" CONFIG_DEVNAME "\0" +#endif #ifdef CONFIG_BOOTARGS "bootargs=" CONFIG_BOOTARGS "\0" #endif #ifdef CONFIG_BOOTCOMMAND - "bootcmd=" CONFIG_BOOTCOMMAND "\0" + "bootcmd=" CONFIG_BOOTCOMMAND "\0" +#endif +#ifdef CONFIG_BBL_COMMAND /* Add by guowenxue, burn u-boot image */ + "bbl=" CONFIG_BBL_COMMAND "\0" +#endif +#ifdef CONFIG_BKR_COMMAND /* Add by guowenxue, burn linux kernel image */ + "bkr=" CONFIG_BKR_COMMAND "\0" +#endif +#ifdef CONFIG_BURN_UBIFS /* Add by guowenxue, burn UBIFS root filesystem image */ + "bfs=" CONFIG_BURN_UBIFS "\0" +#endif +#ifdef CONFIG_BSYS_COMMAND /* Add by guowenxue, burn linux kernel and rootfs */ + "bsys=" CONFIG_BSYS_COMMAND "\0" +#endif +#ifdef CONFIG_BARGS_INITRAMFS /* Add by guowenxue, bootargs for initramfs rootfs */ + "args_initramfs=" CONFIG_BARGS_INITRAMFS "\0" +#endif +#ifdef CONFIG_BARGS_UBIFS /* Add by guowenxue, bootargs for ubifs rootfs */ + "args_ubifs=" CONFIG_BARGS_UBIFS "\0" +#endif +#ifdef CONFIG_TFTPBOOT_COMMAND /* Add by guowenxue, tftp boot linux system */ + "tb=" CONFIG_TFTPBOOT_COMMAND "\0" #endif #ifdef CONFIG_RAMBOOTCOMMAND "ramboot=" CONFIG_RAMBOOTCOMMAND "\0" diff -Nuar u-boot-2010.09/common/serial.c u-boot-2010.09-fl2440/common/serial.c --- u-boot-2010.09/common/serial.c 2010-09-29 05:20:55.000000000 +0800 +++ u-boot-2010.09-fl2440/common/serial.c 2020-08-21 12:06:35.016546939 +0800 @@ -68,7 +68,7 @@ #else #error "Bad CONFIG_PSC_CONSOLE." #endif -#elif defined(CONFIG_S3C2410) +#elif defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) #if defined(CONFIG_SERIAL1) return &s3c24xx_serial0_device; #elif defined(CONFIG_SERIAL2) @@ -157,7 +157,7 @@ #if defined (CONFIG_STUART) serial_register(&serial_stuart_device); #endif -#if defined(CONFIG_S3C2410) +#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) serial_register(&s3c24xx_serial0_device); serial_register(&s3c24xx_serial1_device); serial_register(&s3c24xx_serial2_device); diff -Nuar u-boot-2010.09/drivers/mtd/nand/s3c2410_nand.c u-boot-2010.09-fl2440/drivers/mtd/nand/s3c2410_nand.c --- u-boot-2010.09/drivers/mtd/nand/s3c2410_nand.c 2010-09-29 05:20:55.000000000 +0800 +++ u-boot-2010.09-fl2440/drivers/mtd/nand/s3c2410_nand.c 2020-08-21 12:06:35.016546939 +0800 @@ -24,6 +24,7 @@ #include #include +#if defined(CONFIG_S3C2410) #define S3C2410_NFCONF_EN (1<<15) #define S3C2410_NFCONF_512BYTE (1<<14) #define S3C2410_NFCONF_4STEP (1<<13) @@ -36,6 +37,20 @@ #define S3C2410_ADDR_NALE 4 #define S3C2410_ADDR_NCLE 8 +#elif defined(CONFIG_S3C2440) +#define S3C2410_NFCONT_EN (1<<0) +#define S3C2410_NFCONT_INITECC (1<<4) +#define S3C2410_NFCONT_nFCE (1<<1) +#define S3C2410_NFCONT_MAINECCLOCK (1<<5) +#define S3C2410_NFCONF_TACLS(x) ((x)<<12) +#define S3C2410_NFCONF_TWRPH0(x) ((x)<<8) +#define S3C2410_NFCONF_TWRPH1(x) ((x)<<4) + +#define S3C2410_ADDR_NALE 0x08 +#define S3C2410_ADDR_NCLE 0x0c +#endif +ulong IO_ADDR_W = CONFIG_SYS_NAND_BASE; + #ifdef CONFIG_NAND_SPL /* in the early stage of NAND flash booting, printf() is not available */ @@ -59,25 +74,31 @@ debugX(1, "hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl); if (ctrl & NAND_CTRL_CHANGE) { - ulong IO_ADDR_W = (ulong)nand; + IO_ADDR_W = (ulong)nand; if (!(ctrl & NAND_CLE)) IO_ADDR_W |= S3C2410_ADDR_NCLE; if (!(ctrl & NAND_ALE)) IO_ADDR_W |= S3C2410_ADDR_NALE; - chip->IO_ADDR_W = (void *)IO_ADDR_W; + //chip->IO_ADDR_W = (void *)IO_ADDR_W; if (ctrl & NAND_NCE) - writel(readl(&nand->NFCONF) & ~S3C2410_NFCONF_nFCE, - &nand->NFCONF); +#if defined(CONFIG_S3C2410) + writel(readl(&nand->NFCONF) & ~S3C2410_NFCONF_nFCE, &nand->NFCONF); +#elif defined(CONFIG_S3C2440) + writel(readl(&nand->NFCONT) & ~S3C2410_NFCONT_nFCE, &nand->NFCONT); +#endif else - writel(readl(&nand->NFCONF) | S3C2410_NFCONF_nFCE, - &nand->NFCONF); +#if defined(CONFIG_S3C2410) + writel(readl(&nand->NFCONF) | S3C2410_NFCONF_nFCE, &nand->NFCONF); +#elif defined(CONFIG_S3C2440) + writel(readl(&nand->NFCONT) | S3C2410_NFCONT_nFCE, &nand->NFCONT); +#endif } if (cmd != NAND_CMD_NONE) - writeb(cmd, chip->IO_ADDR_W); + writeb(cmd, (void *)IO_ADDR_W); } static int s3c2410_dev_ready(struct mtd_info *mtd) @@ -92,7 +113,11 @@ { struct s3c2410_nand *nand = s3c2410_get_base_nand(); debugX(1, "s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode); +#if defined(CONFIG_S3C2410) writel(readl(&nand->NFCONF) | S3C2410_NFCONF_INITECC, &nand->NFCONF); +#elif defined(CONFIG_S3C2440) + writel(readl(&nand->NFCONT) | S3C2410_NFCONT_INITECC, &nand->NFCONT); +#endif } static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, @@ -132,6 +157,7 @@ writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON); +#if defined(CONFIG_S3C2410) /* initialize hardware */ twrph0 = 3; twrph1 = 0; @@ -145,6 +171,20 @@ /* initialize nand_chip data structure */ nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)&nand_reg->NFDATA; +#elif defined(CONFIG_S3C2440) + twrph0 = 4; + twrph1 = 2; + tacls = 0; + cfg = 0; + cfg |= S3C2410_NFCONF_TACLS(tacls - 1); + cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1); + cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1); + writel(cfg, &nand_reg->NFCONF); + cfg = (0<<13)|(0<<12)|(0<<10)|(0<<9)|(0<<8)|(0<<6)|(0<<5)|(1<<4)|(0<<1)|(1<<0); + writel(cfg, &nand_reg->NFCONT); + /* initialize nand_chip data structure */ + nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)&nand_reg->NFDATA; +#endif nand->select_chip = NULL; diff -Nuar u-boot-2010.09/drivers/net/dm9000x.c u-boot-2010.09-fl2440/drivers/net/dm9000x.c --- u-boot-2010.09/drivers/net/dm9000x.c 2010-09-29 05:20:55.000000000 +0800 +++ u-boot-2010.09-fl2440/drivers/net/dm9000x.c 2020-08-21 12:06:35.016546939 +0800 @@ -364,7 +364,7 @@ while (!(phy_read(1) & 0x20)) { /* autonegation complete bit */ udelay(1000); i++; - if (i == 10000) { + if (i == 2000) { /* Modify by guowenxue */ printf("could not establish link\n"); return 0; } diff -Nuar u-boot-2010.09/include/configs/fl2440.h u-boot-2010.09-fl2440/include/configs/fl2440.h --- u-boot-2010.09/include/configs/fl2440.h 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-2010.09-fl2440/include/configs/fl2440.h 2020-08-21 12:06:35.016546939 +0800 @@ -0,0 +1,237 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * Gary Jennejohn + * David Mueller + * + * Configuation settings for the SAMSUNG SMDK2410 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ +#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */ +#define CONFIG_S3C2440 1 /* specifically a SAMSUNG S3C2440 SoC */ +#define CONFIG_FL2440 1 /* FL2440 board */ + +#define CONFIG_FL2440_LED 1 +#define CONFIG_FL2440_BEEP 1 +#define CONFIG_S3C2410_NAND_SKIP_BAD 1 + +/* input clock of PLL */ +#define CONFIG_SYS_CLK_FREQ 12000000/* the SMDK2410 has 12MHz input clock */ + + +#define USE_920T_MMU 1 +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_BASE 0x20000300 /* nGCS4 */ +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE+4) +#define CONFIG_DM9000_USE_16BIT 1 +#define CONFIG_DM9000_NO_SROM 1 +#undef CONFIG_DM9000_DEBUG + +/* + * select serial console configuration + */ +#define CONFIG_S3C24X0_SERIAL +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK2410 */ + +/************************************************************ + * RTC + ************************************************************/ +#define CONFIG_RTC_S3C24X0 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ELF +#define CONFIG_CMD_PING +#define CONFIG_CMD_NAND + + +#define CONFIG_BOOTDELAY 2 +#define CONFIG_ETHADDR 08:00:3e:26:0a:5b +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.2.128 +#define CONFIG_SERVERIP 192.168.2.2 + + +#define CONFIG_DEVNAME "fl2440" +#define CONFIG_BBL_COMMAND "tftp 30008000 u-boot-${devname}.bin && nand erase 0 100000 && nand write 30008000 0 60000" +#define CONFIG_BKR_COMMAND "tftp 30008000 linuxrom-${devname}.bin && nand erase 100000 F00000;nand write 30008000 100000 $filesize" +#define CONFIG_BSYS_COMMAND "run bkr;run bfs" +#define CONFIG_TFTPBOOT_COMMAND "tftp 30008000 linuxrom-${devname}.bin; bootm 30008000" +#define CONFIG_BURN_UBIFS "tftp 30008000 rootfs-${devname}.ubi;nand erase 1000000 5000000;nand write 30008000 1000000 $filesize" + +#define CONFIG_BARGS_INITRAMFS "console=tty0 console=ttyS0,115200 mem=64M rw loglevel=7" +#define CONFIG_BARGS_UBIFS "console=tty0 console=ttyS0,115200 ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs mem=64M noinitrd rw loglevel=7" +#define CONFIG_BOOTARGS CONFIG_BARGS_UBIFS +#define CONFIG_BOOTCOMMAND "nand read 30008000 100000 300000; bootm 30008000" + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +/* what's this ? it's not used anywhere */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "[fl2440@lingyun]# " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */ + +#define CONFIG_SYS_LOAD_ADDR 0x33000000 /* default load address */ + +#define CONFIG_SYS_HZ 1000 + +/* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ + +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 + +#define CONFIG_SYS_NO_FLASH 1 +#undef CONFIG_CMD_IMLS + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */ +#endif +#if 0 +#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */ +#endif + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#ifdef CONFIG_AMD_LV800 +#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */ +#define CONFIG_SYS_MAX_FLASH_SECT (19) /* max number of sectors on one chip */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */ +#endif +#ifdef CONFIG_AMD_LV400 +#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */ +#define CONFIG_SYS_MAX_FLASH_SECT (11) /* max number of sectors on one chip */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */ +#endif + +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Write */ + +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ +#endif + +#if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_S3C2410 +#define CONFIG_S3C2410_NAND_SKIP_BAD 1 +#define CONFIG_SYS_NAND_BASE 0x4E000000 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE + +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_OFFSET 0X60000 +#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ +#endif /* CONFIG_CMD_NAND */ + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_TAG + +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_CMDLINE_EDITING +#ifdef CONFIG_CMDLINE_EDITING +#undef CONFIG_AUTO_COMPLETE +#else +#define CONFIG_AUTO_COMPLETE +#endif + +#endif /* __CONFIG_H */ diff -Nuar u-boot-2010.09/include/serial.h u-boot-2010.09-fl2440/include/serial.h --- u-boot-2010.09/include/serial.h 2010-09-29 05:20:55.000000000 +0800 +++ u-boot-2010.09-fl2440/include/serial.h 2020-08-21 12:06:35.016546939 +0800 @@ -46,7 +46,7 @@ extern struct serial_device serial6_device; #endif -#if defined(CONFIG_S3C2410) +#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) extern struct serial_device s3c24xx_serial0_device; extern struct serial_device s3c24xx_serial1_device; extern struct serial_device s3c24xx_serial2_device; diff -Nuar u-boot-2010.09/Makefile u-boot-2010.09-fl2440/Makefile --- u-boot-2010.09/Makefile 2010-09-29 05:20:55.000000000 +0800 +++ u-boot-2010.09-fl2440/Makefile 2020-08-21 12:06:39.420547023 +0800 @@ -154,6 +154,8 @@ # load ARCH, BOARD, and CPU configuration include $(obj)include/config.mk export ARCH CPU BOARD VENDOR SOC +export ARCH=arm +export CROSS_COMPILE=/opt/xtools/arm920t/bin/arm-linux- # set default to nothing for native builds ifeq ($(HOSTARCH),$(ARCH)) @@ -317,6 +319,7 @@ $(obj)u-boot.bin: $(obj)u-boot $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + mv u-boot.bin u-boot-fl2440.bin $(obj)u-boot.ldr: $(obj)u-boot $(CREATE_LDR_ENV)