/*********************************************************************** * File: led.S * Version: 1.0.0 * Copyright: 2013 (c) Guo Wenxue * Description: This ASM used to disable watch dog and interrupt, then call C code to * turn the four LEDs on/off on OK6410 board. * ChangeLog: 1, Release initial version on "Sun Feb 24 15:06:12 CST 2013" * ***********************************************************************/ #define SROM_BW 0x70000000 #define WTCON 0x7E004000 /* Interrupt definition */ #define ELFIN_VIC0_BASE_ADDR (0x71200000) #define ELFIN_VIC1_BASE_ADDR (0x71300000) #define oIRQSTATUS 0x000 #define oFIQSTATUS 0x004 #define oRAWINTR 0x008 #define oINTSELECT 0x00c #define oINTENABLE 0x010 #define oINTENCLEAR 0x014 #define oSOFTINT 0x018 #define oSOFTINTCLEAR 0x01c #define oPROTECTION 0x020 #define oSWPRIORITYMASK 0x024 #define oPRIORITYDAISY 0x028 #define oVECTADDR(X) (0x100+(X)*4) #define oVECPRIORITY(X) (0x200+(X)*4) #define oVECTADDRESS 0xF00 #define VIC0IRQSTATUS (ELFIN_VIC0_BASE_ADDR + oIRQSTATUS) #define VIC0FIQSTATUS (ELFIN_VIC0_BASE_ADDR + oFIQSTATUS) #define VIC0RAWINTR (ELFIN_VIC0_BASE_ADDR + oRAWINTR) #define VIC0INTSELECT (ELFIN_VIC0_BASE_ADDR + oINTSELECT) #define VIC0INTENABLE (ELFIN_VIC0_BASE_ADDR + oINTENABLE) #define VIC0INTENCLEAR (ELFIN_VIC0_BASE_ADDR + oINTENCLEAR) #define VIC0SOFTINT (ELFIN_VIC0_BASE_ADDR + oSOFTINT) #define VIC0SOFTINTCLEAR (ELFIN_VIC0_BASE_ADDR + oSOFTINTCLEAR) #define VIC0PROTECTION (ELFIN_VIC0_BASE_ADDR + oPROTECTION) #define VIC0SWPRIORITYMASK (ELFIN_VIC0_BASE_ADDR + oSWPRIORITYMASK) #define VIC0PRIORITYDAISY (ELFIN_VIC0_BASE_ADDR + oPRIORITYDAISY) #define VIC0VECTADDR(X) (ELFIN_VIC0_BASE_ADDR + oVECTADDR(X)) #define VIC0VECPRIORITY(X) (ELFIN_VIC0_BASE_ADDR + oVECPRIORITY(X)) #define VIC0VECTADDRESS (ELFIN_VIC0_BASE_ADDR + oVECTADDRESS) #define VIC1IRQSTATUS (ELFIN_VIC1_BASE_ADDR + oIRQSTATUS) #define VIC1FIQSTATUS (ELFIN_VIC1_BASE_ADDR + oFIQSTATUS) #define VIC1RAWINTR (ELFIN_VIC1_BASE_ADDR + oRAWINTR) #define VIC1INTSELECT (ELFIN_VIC1_BASE_ADDR + oINTSELECT) #define VIC1INTENABLE (ELFIN_VIC1_BASE_ADDR + oINTENABLE) #define VIC1INTENCLEAR (ELFIN_VIC1_BASE_ADDR + oINTENCLEAR) #define VIC1SOFTINT (ELFIN_VIC1_BASE_ADDR + oSOFTINT) #define VIC1SOFTINTCLEAR (ELFIN_VIC1_BASE_ADDR + oSOFTINTCLEAR) #define VIC1PROTECTION (ELFIN_VIC1_BASE_ADDR + oPROTECTION) #define VIC1SWPRIORITYMASK (ELFIN_VIC1_BASE_ADDR + oSWPRIORITYMASK) #define VIC1PRIORITYDAISY (ELFIN_VIC1_BASE_ADDR + oPRIORITYDAISY) #define VIC1VECTADDR(X) (ELFIN_VIC1_BASE_ADDR + oVECTADDR(X)) #define VIC1VECPRIORITY(X) (ELFIN_VIC1_BASE_ADDR + oVECPRIORITY(X)) #define VIC1VECTADDRESS (ELFIN_VIC1_BASE_ADDR + oVECTADDRESS) /*****************************/ /* CP15 Mode Bit Definition */ /*****************************/ #define R1_iA (1<<31) #define R1_nF (1<<30) #define R1_VE (1<<24) #define R1_I (1<<12) #define R1_BP (1<<11) /* Z bit */ #define R1_C (1<<2) #define R1_A (1<<1) #define R1_M (1<<0) .global _start _start: /* Enable Instruction Cache */ mov r0, #0 mcr p15, 0, r0, c7, c7, 0 /* Invalidate Entire I&D Cache */ mrc p15, 0, r0, c1, c0, 0 /* Enable I Cache */ orr r0, r0, #R1_I mcr p15, 0, r0, c1, c0, 0 /* disable vector interrupt */ mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #(1<<24) mcr p15, 0, r0, c1, c0, 0 /* Peri port setup */ ldr r0, =SROM_BW orr r0, r0, #0x13 mcr p15,0,r0,c15,c2,4 @ 256M(0x70000000-0x7fffffff) /* Disable watchdog */ ldr r0, =WTCON mov r1, #0 str r1, [r0] /* disable all interrupt */ ldr r4, =VIC0INTENCLEAR ldr r5, =0xFFFFFFFF; str r5, [r4] ldr r4, =VIC1INTENCLEAR str r5, [r4] /* Setup Stack */ ldr sp, =8*1024 bl main halt: b halt